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authorAndrew Turner <andrew@FreeBSD.org>2020-06-15 11:30:04 +0000
committerAndrew Turner <andrew@FreeBSD.org>2020-06-15 11:30:04 +0000
commitd7aa8d0a1f110421252d79f5acfb72d89187ad1f (patch)
tree8b0efac880d3949a9d25ab9bb34792eac605eee6
parentcf98ba14dc260458f757fa46419575cf69f45a44 (diff)
downloadsrc-vendor/opencsd.tar.gz
src-vendor/opencsd.zip
Sponsored by: Innovate UK
Notes
Notes: svn path=/vendor/opencsd/dist/; revision=362193 svn path=/vendor/opencsd/v0.14.2/; revision=362194; tag=vendor/opencsd/v0.14.2
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-rw-r--r--decoder/tests/snapshots/trace_cov_a15/device1.ini357
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/device2.ini129
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/device3.ini129
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/device4.ini129
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/device5.ini89
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/device6.ini89
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/mem_Cortex-A15_0_0_VECTORS.binbin0 -> 632 bytes
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/mem_Cortex-A15_0_1_RO_CODE.binbin0 -> 6576 bytes
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/mem_Cortex-A15_0_2_RO_DATA.binbin0 -> 304 bytes
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/mem_Cortex-A15_0_3_RW_DATA.binbin0 -> 16 bytes
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/mem_Cortex-A15_0_4_ZI_DATA.binbin0 -> 576 bytes
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/mem_Cortex-A15_0_5_ARM_LIB_HEAP.binbin0 -> 262144 bytes
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/mem_Cortex-A15_0_6_ARM_LIB_STACK.binbin0 -> 65536 bytes
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/mem_Cortex-A15_0_7_IRQ_STACK.binbin0 -> 65536 bytes
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/mem_Cortex-A15_0_8_TTB.binbin0 -> 16384 bytes
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/snapshot.ini16
-rw-r--r--decoder/tests/snapshots/trace_cov_a15/trace.ini24
262 files changed, 205139 insertions, 1486 deletions
diff --git a/HOWTO.md b/HOWTO.md
index b16294a317ef..c1196ce3c716 100644
--- a/HOWTO.md
+++ b/HOWTO.md
@@ -4,37 +4,39 @@ HOWTO - using the library with perf {#howto_perf}
@brief Using command line perf and OpenCSD to collect and decode trace.
This HOWTO explains how to use the perf cmd line tools and the openCSD
-library to collect and extract program flow traces generated by the
+library to collect and extract program flow traces generated by the
CoreSight IP blocks on a Linux system. The examples have been generated using
-an aarch64 Juno-r0 platform. All information is considered accurate and tested
-using the latest version of the library and the `master` branch on the
-[perf-opencsd github repository][1].
+an aarch64 Juno-r0 platform.
On Target Trace Acquisition - Perf Record
-----------------------------------------
-All the enhancement to the Perf tools that support the new `cs_etm` pmu have
-not been upstreamed yet. To get the required functionality branch
-`perf-opencsd-master` needs to be downloaded to the target system where
-traces are to be collected. This branch is a vanilla upstream kernel
-supplemented with modifications to the CoreSight framework and drivers to be
-usable by the Perf core. The remaining out of tree patches are being
-upstreamed incrementally.
-
-From there compiling the perf tools with `make -C tools/perf CORESIGHT=1` will
-yield a `perf` executable that will support CoreSight trace collection. Note
-that if traces are to be decompressed *off* target, there is no need to download
+
+Compile the perf tool from the same kernel source code version you are using with:
+
+ make -C tools/perf
+
+This will yield a `perf` executable that will support CoreSight trace collection.
+
+*Note:* If traces are to be decompressed **off** target, there is no need to download
and compile the openCSD library (on the target).
+If you are instead planning to use perf to record and decode the trace on the target,
+compile the perf tool linking against the openCSD library, in the following way:
+
+ make -C tools/perf VF=1 CORESIGHT=1
+
+Further information on the needed build environments and options are detailed later
+in the section **Off Target Perf Tools Compilation**.
+
Before launching a trace run a sink that will collect trace data needs to be
identified. All CoreSight blocks identified by the framework are registed in
sysFS:
linaro@linaro-nano:~$ ls /sys/bus/coresight/devices/
- 20010000.etf 20040000.main_funnel 22040000.etm 22140000.etm
- 230c0000.A53_funnel 23240000.etm replicator@20020000 20030000.tpiu
- 20070000.etr 220c0000.A57_funnel 23040000.etm 23140000.etm 23340000.etm
+ etm0 etm2 etm4 etm6 funnel0 funnel2 funnel4 stm0 tmc_etr0
+ etm1 etm3 etm5 etm7 funnel1 funnel3 replicator0 tmc_etf0
CoreSight blocks are listed in the device tree for a specific system and
@@ -43,7 +45,7 @@ the sink that will recieve trace data needs to be identified and given as an
option on the perf command line. Once a sink has been identify trace collection
can start. An easy and yet interesting example is the `uname` command:
- linaro@linaro-nano:~/kernel$ ./tools/perf/perf record -e cs_etm/@20070000.etr/ --per-thread uname
+ linaro@linaro-nano:~/kernel$ ./tools/perf/perf record -e cs_etm/@tmc_etr0/ --per-thread uname
This will generate a `perf.data` file where execution has been traced for both
user and kernel space. To narrow the field to either user or kernel space the
@@ -51,7 +53,7 @@ user and kernel space. To narrow the field to either user or kernel space the
traces to user space:
- linaro@linaro-nano:~/kernel$ ./tools/perf/perf record -vvv -e cs_etm/@20070000.etr/u --per-thread uname
+ linaro@linaro-nano:~/kernel$ ./tools/perf/perf record -vvv -e cs_etm/@tmc_etr0/u --per-thread uname
Problems setting modules path maps, continuing anyway...
-----------------------------------------------------------
perf_event_attr:
@@ -131,9 +133,9 @@ falls within the specified range. Any work done by the CPU outside of that
range will not be traced. Address range filters can be specified for both
user and kernel space session:
- perf record -e cs_etm/@20070000.etr/k --filter 'filter 0xffffff8008562d0c/0x48' --per-thread uname
+ perf record -e cs_etm/@tmc_etr0/k --filter 'filter 0xffffff8008562d0c/0x48' --per-thread uname
- perf record -e cs_etm/@20070000.etr/u --filter 'filter 0x72c/0x40@/opt/lib/libcstest.so.1.0' --per-thread ./main
+ perf record -e cs_etm/@tmc_etr0/u --filter 'filter 0x72c/0x40@/opt/lib/libcstest.so.1.0' --per-thread ./main
When dealing with kernel space trace addresses are typically taken in the
'System.map' file. In user space addresses are relocatable and can be
@@ -171,20 +173,20 @@ equal to the start address. Incidentally traces stop being generated when the
insruction pointer is equal to the stop address. Anything that happens between
there to events is traced:
- perf record -e cs_etm/@20070000.etr/k --filter 'start 0xffffff800856bc50,stop 0xffffff800856bcb0' --per-thread uname
+ perf record -e cs_etm/@tmc_etr0/k --filter 'start 0xffffff800856bc50,stop 0xffffff800856bcb0' --per-thread uname
- perf record -vvv -e cs_etm/@20070000.etr/u --filter 'start 0x72c@/opt/lib/libcstest.so.1.0, \
+ perf record -vvv -e cs_etm/@tmc_etr0/u --filter 'start 0x72c@/opt/lib/libcstest.so.1.0, \
stop 0x40082c@/home/linaro/main' \
- --per-thread ./main
+ --per-thread ./main
**Limitation on address filters:**
The only limitation on address filters is the amount of address comparator
found on an implementation and the mutual exclusion between range and
start stop filters. As such the following example would _not_ work:
- perf record -e cs_etm/@20070000.etr/k --filter 'start 0xffffff800856bc50,stop 0xffffff800856bcb0, \ // start/stop
+ perf record -e cs_etm/@tmc_etr0/k --filter 'start 0xffffff800856bc50,stop 0xffffff800856bcb0, \ // start/stop
filter 0x72c/0x40@/opt/lib/libcstest.so.1.0' \ // address range
- --per-thread uname
+ --per-thread uname
Additional Trace Options
------------------------
@@ -198,10 +200,32 @@ Presently this threshold is fixed at 256 cycles for `perf record`.
Command line options in `perf record` to use these features are part of the options for the `cs_etm` event:
- perf record -e cs_etm/timestamp,cycacc,@20070000.etr/ --per-thread uname
+ perf record -e cs_etm/timestamp,cycacc,@tmc_etr0/ --per-thread uname
At current version, `perf record` and `perf script` do not use this additional information.
+The cs_etm perf event
+---------------------
+
+System information for this perf pmu event can be found at:
+
+ /sys/devices/cs_etm
+
+This contains internal format of the parameters described above:
+
+ root@linaro-developer:~# ls /sys/devices/cs_etm/format
+ contextid cycacc retstack sinkid timestamp
+
+and names of registered sinks:
+
+ root@linaro-developer:~# ls /sys/devices/cs_etm/sinks
+ tmc_etf0 tmc_etr0 tpiu0
+
+Note: The `sinkid` parameter is there to document the usage of a 32-bit internal parameter to
+pass the sink name used in the cs_etm/@sink/ command to the kernel drivers. It can be used
+directly as cs_etm/sinkid=<hash_value>/ but this is not recommended as the values used are
+considered opaque and subject to changes.
+
On Target Trace Collection
--------------------------
The entire program flow will have been recorded in the `perf.data` file.
@@ -248,7 +272,7 @@ The openCSD library is not part of the perf tools. It is available on
[github][1] and needs to be compiled before the perf tools. Checkout the
required branch/tag version into a local directory.
- linaro@t430:~/linaro/coresight$ git clone -b v0.8 https://github.com/Linaro/OpenCSD.git my-opencsd
+ linaro@t430:~/linaro/coresight$ git clone https://github.com/Linaro/OpenCSD.git my-opencsd
Cloning into 'OpenCSD'...
remote: Counting objects: 2063, done.
remote: Total 2063 (delta 0), reused 0 (delta 0), pack-reused 2063
@@ -301,7 +325,8 @@ distribution without having to be compiled.
Off Target Perf Tools Compilation
---------------------------------
-As mentionned above the openCSD library is not part of the perf tools' code base
+
+As mentioned above the openCSD library is not part of the perf tools' code base
and needs to be installed on a system prior to compilation. Information about
the status of the openCSD library on a system is given at compile time by the
perf tools build script:
@@ -366,8 +391,8 @@ output as follows:-
Set to any other value will remove the RAW_PACKED lines.
-Working with a debug version of the openCSD library
----------------------------------------------------
+Working with an alternate version of the openCSD library
+--------------------------------------------------------
When compiling the perf tools it is possible to reference another version of
the openCSD library than the one installed on the system. This is useful when
working with multiple development trees or having the desire to keep system
@@ -407,9 +432,13 @@ where the perf tools and openCSD library have been compiled.
-rw------- 1 linaro linaro 78016 Feb 24 12:21 perf.data
-rw-rw-r-- 1 linaro linaro 1245881 Feb 24 12:25 uname.v4.user.sept20.tgz
-Perf is expecting files related to the trace capture (`perf.data`) to be located
-under `~/.debug` [3]. This example will remove the current `~/.debug` directory
-to be sure everything is clean.
+Perf is expecting files related to the trace capture (`perf.data`) to be located in the `buildid` directory.
+By default this is under `~/.debug`. Alternatively the default `buildid` directory can be changed
+using the command:
+
+ perf config --system buildid.dir=/my/own/buildid/dir
+
+This example will remove the current `~/.debug` directory to be sure everything is clean.
linaro@t430:~/linaro/coresight/sept20$ rm -rf ~/.debug
linaro@t430:~/linaro/coresight/sept20$ cp -dpR .debug ~/
@@ -586,12 +615,18 @@ Use as follows:-
1. Prior to building perf, edit `perf-setup-env.bash` to conform to your environment. There are four lines at the top of the file that will require editing.
-2. Execute the script using the command
+2. Execute the script using the command:
source perf-setup-env.bash
- This will set up all the environment variables mentioned in the sections on building and running
- perf above, and these are used by the `perf-test...` scripts to run the tests.
+ This will set up a perf execute environment for using the perf report and script commands.
+
+ Alternatively use the command:
+
+ source perf-setup-env.base buildenv
+
+ This will add in the build environment variables mentioned in the sections on building above alongside the
+ environment for using the used by the `perf-test...` scripts to run the tests.
3. Build perf as described above.
4. Follow the instructions for downloading the test capture, or create a capture from your target.
@@ -629,8 +664,6 @@ Best regards,
*The Linaro CoreSight Team*
--------------------------------------
-[1]: https://github.com/Linaro/perf-opencsd "perf-opencsd Github"
+[1]: https://github.com/Linaro/OpenCSD
[2]: http://people.linaro.org/~mathieu.poirier/openCSD/uname.v4.user.sept20.tgz
-
-[3]: Get in touch with us if you know a way to change this.
diff --git a/README.md b/README.md
index c3f238ff1946..b8b13d57830e 100644
--- a/README.md
+++ b/README.md
@@ -27,11 +27,11 @@ Releases will appear on the master branch in the git repository with an appropri
CoreSight Trace Component Support.
----------------------------------
-_Current Version 0.12.0_
+_Current Version 0.14.2_
### Current support:
-- ETMv4 (v4.4) instruction trace - packet processing and packet decode.
+- ETMv4 (v4.5 [A/R profile] v4.4 [M profile]) instruction trace - packet processing and packet decode.
- PTM (v1.1) instruction trace - packet processing and packet decode.
- ETMv3 (v3.5) instruction trace - packet processing and packet decode.
- ETMv3 (v3.5) data trace - packet processing.
@@ -55,12 +55,11 @@ Note on the Git Repository.
This git repository for OpenCSD contains only source for the OpenCSD decoder library.
From version 0.4, releases appear as versioned tags on the master branch.
-From version 0.7.4, the required updates to CoreSight drivers and perf, that are not
-currently upstream in the linux kernel tree, are now contained in a separate
-repository to be found at:
-
-https://github.com/Linaro/perf-opencsd
+CoreSight kernel drivers and perf suport for CoreSight trace is maintained in the latest
+upstream kernel versions.
+One exception is a minor patch required for autoFDO support.
+See [autofdo.md](@ref AutoFDO).
Documentation
-------------
@@ -142,29 +141,75 @@ Version and Modification Information
AutoFDO: update documentation for AutoFDO usage and add in "record.sh" script
- _Version 0.9.3_: Bugfix: Test snapshot library not handling 'offset' parameters in dump file sections.
Install: ocsd_if_version.h moved to opencsd/include to allow installation on OS & use in compiling client apps.
-- _Version 0.10.0_: __Updates__: Add additional information about the last instruction to the generic output packet.
- __Docs__: update docs for updated output packet.
- __Bugfix__: typecast removed from OCSD_VER_NUM in ocsd_if_version.h to allow use in C pre-processor.
- __Bugfix__: ETMV4: Interworking ISA change between A32-T32 occasionally missed during instruction decode.
-- _Version 0.10.1_: __Updates__: Build update - allow multi-thread make (make -j<N>).
- __Docs__: Minor update to AutoFDO documentation.
-- _Version 0.11.0_: __Update__: ETM v4 decoder updated to support ETM version up to v4.4
- __Update__: Memory access callback function - added new callback signature to provide TraceID to client when requesting memory.
- __Update__: Created new example program to demonstrate using memory buffer in APIs.
- __Bugfix__: Typos in docs and source.
- __Bugfix__: Memory accessor - validate callback return values.
-- _Version 0.11.1_: __Update__: build:- change -fpic to -fPIC to allow Debian build on sparc.
- __Bugfix__: build:- remove unused variable
-- _Version 0.11.2_: __Update__: docs:- HOWTO.md update to match new perf build requirements.
- __Bugfix__: Minor spelling typos fixed.
-- _Version 0.12.0_: __Update__: Frame deformatter - TPIU FSYNC and HSYNC support added.
- __Update__: ETM v4: Bugfix & clarification on Exception trace handling. Where exception occurs at a branch target before any instructions
- have been executed, the preferred return address is also the target address of the branch instruction. This case now includes as specific flag in
- the packet. Additionally any context change associated with this target address was being applied incorrectly.
- __Update__: Core / Architecture mapping to core names as used by test programs / snapshots updated to include additional recent ARM cores.
- __Update__: Docs: Update to reflect new exception flag. Update test program example to reflect latest output.
- __Bugfix__: ETM v4: Valid trace info packet was not handled correctly (0x01, 0x00).
- __Bugfix__: ETM v4: Error messaging on commit stack overflow.
+- _Version 0.10.0_:
+ - __Updates__: Add additional information about the last instruction to the generic output packet.
+ - __Docs__: update docs for updated output packet.
+ - __Bugfix__: typecast removed from OCSD_VER_NUM in ocsd_if_version.h to allow use in C pre-processor.
+ - __Bugfix__: ETMV4: Interworking ISA change between A32-T32 occasionally missed during instruction decode.
+
+- _Version 0.10.1_:
+ - __Updates__: Build update - allow multi-thread make (make -j<N>).
+ - __Docs__: Minor update to AutoFDO documentation.
+
+- _Version 0.11.0_:
+ - __Update__: ETM v4 decoder updated to support ETM version up to v4.4
+ - __Update__: Memory access callback function - added new callback signature to provide TraceID to client when requesting memory.
+ - __Update__: Created new example program to demonstrate using memory buffer in APIs.
+ - __Bugfix__: Typos in docs and source.
+ - __Bugfix__: Memory accessor - validate callback return values.
+
+- _Version 0.11.1_:
+ - __Update__: build:- change -fpic to -fPIC to allow Debian build on sparc.
+ - __Bugfix__: build:- remove unused variable
+
+- _Version 0.11.2_:
+ - __Update__: docs:- HOWTO.md update to match new perf build requirements.
+ - __Bugfix__: Minor spelling typos fixed.
+
+- _Version 0.12.0_:
+ - __Update__: Frame deformatter - TPIU FSYNC and HSYNC support added.
+ - __Update__: ETM v4: Bugfix & clarification on Exception trace handling. Where exception occurs at a branch target before any instructions
+ have been executed, the preferred return address is also the target address of the branch instruction. This case now includes as specific flag in
+ the packet. Additionally any context change associated with this target address was being applied incorrectly.
+ - _Update__: Core / Architecture mapping to core names as used by test programs / snapshots updated to include additional recent ARM cores.
+ - __Update__: Docs: Update to reflect new exception flag. Update test program example to reflect latest output.
+ - __Bugfix__: ETM v4: Valid trace info packet was not handled correctly (0x01, 0x00).
+ - __Bugfix__: ETM v4: Error messaging on commit stack overflow.
+
+- _Version 0.12.1_:
+ - __Update__: build: remove -g option from release build.
+ - __Update__: tests: Snapshots can now use generic arch+profile names rather than core names, e.g. ARMv8-A
+ - __Bugfix__: Instruction decode - v8.3 B[L]A{A|B}[Z] instructions mis-identified.
+ -__Bugfix__: Transition from A64 to A32 can be mis-decoded if the trace implementation represents the transition
+ as an individual address packet followed by a context packet.
+
+- _Version 0.12.2_:
+ - __Bugfix__: Clean up memory leaks.
+ - __Bugfix__: ETMv4: Ensure addressing history zeroed after TINFO.
+ - __Update__: Allow GCC version to be included in build output path.
+ - __Bugfix__: Packet printing update when WFI/WFE is P0 element.
+
+- _Version 0.13.x_ : Intermediate development version.
+
+- _Version 0.14.0_:
+ - __Update__: ETMv4 - decoder update & simplification to handle advanced trace features.
+ - __Update__: ETMv4 - decoder support for speculative trace.
+ - __Update__: Generic Elements: Additional information in EOT, UNSYNC, ON packets to give reason.
+ - __Update__: Memaccess: Add EL2 secure memory space flag.
+ - __Update__: Documentation: Updated for release changes and to reflect latest kernel version support for CoreSight.
+ - __Update__: Perf helper scripts updated to reflect latest build flow.
+ - __Bugfix__: Fix for component operational flag inputs.
+
+- _Version 0.14.1_:
+ - __Update__: ETMv4 - Add support for Q elements.
+ - __Bugfix__: build: fix logic issue for && operator. (github issue #23, sumitted by yabinc)
+
+- _Version 0.14.2_:
+ - __Update__: Architecture versioning. Set enum tag values to make conversion to numeric version easier.
+ - __Update__: I-decode: remove global temporary decode state data and replace with local instance data
+ to make library more easily usable in multi-threaded programs.
+ - __Bugfix__: I-decode: Some Thumb instructions not correctly reported as implied returns.
+ (github issue #24, submitted by kongy).
Licence Information
diff --git a/decoder/build/linux/makefile b/decoder/build/linux/makefile
index 6032c2cf7283..659cf68c6376 100644
--- a/decoder/build/linux/makefile
+++ b/decoder/build/linux/makefile
@@ -70,8 +70,8 @@ INSTALL_BIN_DIR=$(PREFIX)/bin
export INSTALL_INCLUDE_DIR=$(PREFIX)/include/
# compile flags
-CFLAGS += $(CPPFLAGS) -c -Wall -DLINUX -Wno-switch -fPIC
-CXXFLAGS += $(CPPFLAGS) -c -Wall -DLINUX -Wno-switch -fPIC -std=c++11
+CFLAGS += $(CPPFLAGS) -c -Wall -DLINUX -Wno-switch -Wlogical-op -fPIC
+CXXFLAGS += $(CPPFLAGS) -c -Wall -DLINUX -Wno-switch -Wlogical-op -fPIC -std=c++11
LDFLAGS += -Wl,-z,defs
ARFLAGS ?= rcs
@@ -81,8 +81,8 @@ CFLAGS += -g -O0 -DDEBUG
CXXFLAGS += -g -O0 -DDEBUG
BUILD_VARIANT=dbg
else
-CFLAGS += -g -O2 -DNDEBUG
-CXXFLAGS += -g -O2 -DNDEBUG
+CFLAGS += -O2 -DNDEBUG
+CXXFLAGS += -O2 -DNDEBUG
BUILD_VARIANT=rel
endif
diff --git a/decoder/build/linux/makefile.dev b/decoder/build/linux/makefile.dev
index 7c02328db2a8..5eb1ec9557fa 100644
--- a/decoder/build/linux/makefile.dev
+++ b/decoder/build/linux/makefile.dev
@@ -56,7 +56,12 @@ CXXFLAGS += $(MFLAG)
CFLAGS += $(MFLAG)
LDFLAGS += $(MFLAG)
+ifdef GCCDIR
+GCCVER:= $(shell $(CROSS_COMPILE)gcc -dumpversion | cut -c 1-3)
+PLAT_DIR=builddir/linux$(BIT_VARIANT)/GCC_$(GCCVER)
+else
PLAT_DIR=linux$(BIT_VARIANT)/$(BUILD_VARIANT)
+endif
# include the main makefile
include makefile
diff --git a/decoder/build/linux/ref_trace_decode_lib/makefile b/decoder/build/linux/ref_trace_decode_lib/makefile
index 373e8248bd6a..7087036cc62e 100644
--- a/decoder/build/linux/ref_trace_decode_lib/makefile
+++ b/decoder/build/linux/ref_trace_decode_lib/makefile
@@ -59,11 +59,9 @@ ETMV3OBJ= $(BUILD_DIR)/trc_cmp_cfg_etmv3.o \
$(BUILD_DIR)/trc_pkt_proc_etmv3_impl.o
ETMV4OBJ= $(BUILD_DIR)/trc_cmp_cfg_etmv4.o \
- $(BUILD_DIR)/trc_pkt_proc_etmv4.o \
- $(BUILD_DIR)/trc_pkt_proc_etmv4i_impl.o \
+ $(BUILD_DIR)/trc_pkt_proc_etmv4i.o \
$(BUILD_DIR)/trc_pkt_decode_etmv4i.o \
$(BUILD_DIR)/trc_pkt_elem_etmv4i.o \
- $(BUILD_DIR)/trc_pkt_elem_etmv4d.o \
$(BUILD_DIR)/trc_etmv4_stack_elem.o
PTMOBJ= $(BUILD_DIR)/trc_cmp_cfg_ptm.o \
@@ -94,6 +92,7 @@ OBJECTS=$(BUILD_DIR)/ocsd_code_follower.o \
$(BUILD_DIR)/ocsd_error.o \
$(BUILD_DIR)/ocsd_error_logger.o \
$(BUILD_DIR)/ocsd_gen_elem_list.o \
+ $(BUILD_DIR)/ocsd_gen_elem_stack.o \
$(BUILD_DIR)/ocsd_lib_dcd_register.o \
$(BUILD_DIR)/ocsd_msg_logger.o \
$(BUILD_DIR)/ocsd_version.o \
diff --git a/decoder/build/win-vs2015/ref_trace_decode_lib/ref_trace_decode_lib.vcxproj b/decoder/build/win-vs2015/ref_trace_decode_lib/ref_trace_decode_lib.vcxproj
index 095f27b56acc..f1aaece9b3ba 100644
--- a/decoder/build/win-vs2015/ref_trace_decode_lib/ref_trace_decode_lib.vcxproj
+++ b/decoder/build/win-vs2015/ref_trace_decode_lib/ref_trace_decode_lib.vcxproj
@@ -323,6 +323,7 @@
<ClInclude Include="..\..\..\include\common\ocsd_error.h" />
<ClInclude Include="..\..\..\include\common\ocsd_error_logger.h" />
<ClInclude Include="..\..\..\include\common\ocsd_gen_elem_list.h" />
+ <ClInclude Include="..\..\..\include\common\ocsd_gen_elem_stack.h" />
<ClInclude Include="..\..\..\include\common\ocsd_lib_dcd_register.h" />
<ClInclude Include="..\..\..\include\common\ocsd_msg_logger.h" />
<ClInclude Include="..\..\..\include\common\ocsd_pe_context.h" />
@@ -400,8 +401,6 @@
<ClInclude Include="..\..\..\include\opencsd\trc_gen_elem_types.h" />
<ClInclude Include="..\..\..\include\opencsd\trc_pkt_types.h" />
<ClInclude Include="..\..\..\source\etmv3\trc_pkt_proc_etmv3_impl.h" />
- <ClInclude Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4d_impl.h" />
- <ClInclude Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4i_impl.h" />
<ClInclude Include="..\..\..\source\trc_frame_deformatter_impl.h" />
</ItemGroup>
<ItemGroup>
@@ -413,10 +412,8 @@
<ClCompile Include="..\..\..\source\etmv4\trc_cmp_cfg_etmv4.cpp" />
<ClCompile Include="..\..\..\source\etmv4\trc_etmv4_stack_elem.cpp" />
<ClCompile Include="..\..\..\source\etmv4\trc_pkt_decode_etmv4i.cpp" />
- <ClCompile Include="..\..\..\source\etmv4\trc_pkt_elem_etmv4d.cpp" />
<ClCompile Include="..\..\..\source\etmv4\trc_pkt_elem_etmv4i.cpp" />
- <ClCompile Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4.cpp" />
- <ClCompile Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4i_impl.cpp" />
+ <ClCompile Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4i.cpp" />
<ClCompile Include="..\..\..\source\i_dec\trc_idec_arminst.cpp" />
<ClCompile Include="..\..\..\source\i_dec\trc_i_decode.cpp" />
<ClCompile Include="..\..\..\source\mem_acc\trc_mem_acc_base.cpp" />
@@ -430,6 +427,7 @@
<ClCompile Include="..\..\..\source\ocsd_error.cpp" />
<ClCompile Include="..\..\..\source\ocsd_error_logger.cpp" />
<ClCompile Include="..\..\..\source\ocsd_gen_elem_list.cpp" />
+ <ClCompile Include="..\..\..\source\ocsd_gen_elem_stack.cpp" />
<ClCompile Include="..\..\..\source\ocsd_lib_dcd_register.cpp" />
<ClCompile Include="..\..\..\source\ocsd_msg_logger.cpp" />
<ClCompile Include="..\..\..\source\ocsd_version.cpp" />
diff --git a/decoder/build/win-vs2015/ref_trace_decode_lib/ref_trace_decode_lib.vcxproj.filters b/decoder/build/win-vs2015/ref_trace_decode_lib/ref_trace_decode_lib.vcxproj.filters
index 1ef87207089f..cdb6f84f736d 100644
--- a/decoder/build/win-vs2015/ref_trace_decode_lib/ref_trace_decode_lib.vcxproj.filters
+++ b/decoder/build/win-vs2015/ref_trace_decode_lib/ref_trace_decode_lib.vcxproj.filters
@@ -221,12 +221,6 @@
<ClInclude Include="..\..\..\include\opencsd\ptm\trc_pkt_decode_ptm.h">
<Filter>Header Files\ptm</Filter>
</ClInclude>
- <ClInclude Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4d_impl.h">
- <Filter>Source Files\etmv4</Filter>
- </ClInclude>
- <ClInclude Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4i_impl.h">
- <Filter>Source Files\etmv4</Filter>
- </ClInclude>
<ClInclude Include="..\..\..\source\etmv3\trc_pkt_proc_etmv3_impl.h">
<Filter>Source Files\etmv3</Filter>
</ClInclude>
@@ -359,6 +353,9 @@
<ClInclude Include="..\..\..\include\opencsd\ocsd_if_version.h">
<Filter>Header Files</Filter>
</ClInclude>
+ <ClInclude Include="..\..\..\include\common\ocsd_gen_elem_stack.h">
+ <Filter>Header Files\common</Filter>
+ </ClInclude>
</ItemGroup>
<ItemGroup>
<ClCompile Include="..\..\..\source\trc_component.cpp">
@@ -385,18 +382,9 @@
<ClCompile Include="..\..\..\source\ptm\trc_pkt_proc_ptm.cpp">
<Filter>Source Files\ptm</Filter>
</ClCompile>
- <ClCompile Include="..\..\..\source\etmv4\trc_pkt_elem_etmv4d.cpp">
- <Filter>Source Files\etmv4</Filter>
- </ClCompile>
<ClCompile Include="..\..\..\source\etmv4\trc_pkt_elem_etmv4i.cpp">
<Filter>Source Files\etmv4</Filter>
</ClCompile>
- <ClCompile Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4.cpp">
- <Filter>Source Files\etmv4</Filter>
- </ClCompile>
- <ClCompile Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4i_impl.cpp">
- <Filter>Source Files\etmv4</Filter>
- </ClCompile>
<ClCompile Include="..\..\..\source\etmv4\trc_pkt_decode_etmv4i.cpp">
<Filter>Source Files\etmv4</Filter>
</ClCompile>
@@ -490,5 +478,11 @@
<ClCompile Include="..\..\..\source\mem_acc\trc_mem_acc_cache.cpp">
<Filter>Source Files\mem_acc</Filter>
</ClCompile>
+ <ClCompile Include="..\..\..\source\etmv4\trc_pkt_proc_etmv4i.cpp">
+ <Filter>Source Files\etmv4</Filter>
+ </ClCompile>
+ <ClCompile Include="..\..\..\source\ocsd_gen_elem_stack.cpp">
+ <Filter>Source Files</Filter>
+ </ClCompile>
</ItemGroup>
</Project> \ No newline at end of file
diff --git a/decoder/docs/doxygen_config.dox b/decoder/docs/doxygen_config.dox
index 0ca0cf7349b0..3913d3ac5ea5 100644
--- a/decoder/docs/doxygen_config.dox
+++ b/decoder/docs/doxygen_config.dox
@@ -38,7 +38,7 @@ PROJECT_NAME = "OpenCSD - CoreSight Trace Decode Library"
# could be handy for archiving the generated documentation or if some version
# control system is used.
-PROJECT_NUMBER = 0.10.0
+PROJECT_NUMBER = 0.14.2
# Using the PROJECT_BRIEF tag one can provide an optional one line description
# for a project that appears at the top of each page and should give viewer a
diff --git a/decoder/docs/prog_guide/prog_guide_generic_pkts.md b/decoder/docs/prog_guide/prog_guide_generic_pkts.md
index 9f69aacad44e..e4d50b79fc80 100644
--- a/decoder/docs/prog_guide/prog_guide_generic_pkts.md
+++ b/decoder/docs/prog_guide/prog_guide_generic_pkts.md
@@ -83,7 +83,7 @@ typedef struct _ocsd_generic_trace_elem {
trace_on_reason_t trace_on_reason; /* reason for the trace on packet */
ocsd_swt_info_t sw_trace_info; /* software trace packet info */
uint32_t num_instr_range; /* number of instructions covered by range packet (for T32 this cannot be calculated from en-st/i_size) */
-
+ unsync_info_t unsync_eot_info; /* additional information for unsync / end-of-trace packets. */
};
const void *ptr_extended_data; /* pointer to extended data buffer (data trace, sw trace payload) / custom structure */
@@ -142,6 +142,19 @@ __ETMv3, PTM__ : These protocols can output a cycle count directly as part of th
the trace range. In this case `has_cc` will be 1 and `cycle_count` will be valid.
+### OCSD_GEN_TRC_ELEM_I_RANGE_NOPATH ###
+__packet fields valid__: `isa, st_addr, en_addr, num_instr_range`
+
+`num_instr_range` represents the number of instructions executed in this range, but there is incomplete information
+as to program execution path from start to end of range.
+If `num_instr` is 0, then an unknown number of instructions were executed between the start and end of the range.
+`st_addr` represents the start of execution represented by this packet.
+`en_addr` represents the address where execution will continue from after the instructions represented by this packet.
+`isa` represents the ISA for the instruction at `en_addr`.
+
+Used when ETMv4 Q elements are being traced.
+
+
### OCSD_GEN_TRC_ELEM_ADDR_NACC ###
__packet fields valid__: `st_addr`
diff --git a/decoder/docs/test_progs.md b/decoder/docs/test_progs.md
index 27194553f230..c02d02e96271 100644
--- a/decoder/docs/test_progs.md
+++ b/decoder/docs/test_progs.md
@@ -20,6 +20,9 @@ See [external_custom.md](@ref custom_decoders) for details.
These programs are both built at the same time as the library for the same set of platforms.
See [build_libs.md](@ref build_lib) for build details.
+_Note:_ The programs above use the library's [core name mapper helper class] (@ref CoreArchProfileMap) to map
+the name of the core into a profile / architecture pair that the library can use.
+The snapshot definition must use one of the names recognised by this class or an error will occur.
Trace "Snapshot" directory.
----------------------------
diff --git a/decoder/include/common/ocsd_dcd_mngr.h b/decoder/include/common/ocsd_dcd_mngr.h
index ba7d8a89c46f..3342eacb24ca 100644
--- a/decoder/include/common/ocsd_dcd_mngr.h
+++ b/decoder/include/common/ocsd_dcd_mngr.h
@@ -115,6 +115,9 @@ ocsd_err_t DecoderMngrBase<P,Pt,Pc>::createDecoder(const int create_flags, cons
if(!pkt_proc)
return OCSD_ERR_MEM;
+ // set the op mode flags
+ pkt_proc->setComponentOpMode(create_flags & (OCSD_OPFLG_COMP_MODE_MASK | OCSD_OPFLG_PKTPROC_COMMON));
+
// set the configuration
TrcPktProcBase<P,Pt,Pc> *pProcBase = dynamic_cast< TrcPktProcBase<P,Pt,Pc> *>(pkt_proc);
if(pProcBase == 0)
@@ -133,6 +136,9 @@ ocsd_err_t DecoderMngrBase<P,Pt,Pc>::createDecoder(const int create_flags, cons
if(!pkt_dcd)
return OCSD_ERR_MEM;
+ // set the op mode flags
+ pkt_dcd->setComponentOpMode(create_flags & (OCSD_OPFLG_COMP_MODE_MASK | OCSD_OPFLG_PKTDEC_COMMON));
+
// get the decoder base
TrcPktDecodeBase<P,Pc> *pBase = dynamic_cast< TrcPktDecodeBase<P,Pc> *>(pkt_dcd);
if(pBase == 0)
diff --git a/decoder/include/common/ocsd_gen_elem_list.h b/decoder/include/common/ocsd_gen_elem_list.h
index 0ff1bd59cbbe..2dab240140bf 100644
--- a/decoder/include/common/ocsd_gen_elem_list.h
+++ b/decoder/include/common/ocsd_gen_elem_list.h
@@ -1,6 +1,6 @@
/*
- * \file ocsd_gen_elem_stack.h
- * \brief OpenCSD : Generic element output stack.
+ * \file ocsd_gen_elem_list.h
+ * \brief OpenCSD : Generic element output list.
*
* \copyright Copyright (c) 2016, ARM Limited. All Rights Reserved.
*/
@@ -47,7 +47,7 @@
* This should remove some of the requirement on the packet processing to be re-enterant,
* simplifying this code.
*
- * Last element(s) on this stack can be marked pending to allow for later cancellation.
+ * Last element(s) on this list can be marked pending to allow for later cancellation.
* (This required for cancel element in ETMv3 exeception branch).
*
* The "list" is actually a ring buffer - maintaining pointers to indicate current valid elements.
@@ -150,4 +150,4 @@ inline void OcsdGenElemList::initSendIf(componentAttachPt<ITrcGenElemIn> *pGenEl
m_sendIf = pGenElemIf;
}
-/* End of File ocsd_gen_elem_stack.h */
+/* End of File ocsd_gen_elem_list.h */
diff --git a/decoder/include/common/ocsd_gen_elem_stack.h b/decoder/include/common/ocsd_gen_elem_stack.h
new file mode 100644
index 000000000000..64c525df4270
--- /dev/null
+++ b/decoder/include/common/ocsd_gen_elem_stack.h
@@ -0,0 +1,109 @@
+/*
+* \file ocsd_gen_elem_stack.h
+* \brief OpenCSD : Generic element output stack.
+*
+* \copyright Copyright (c) 2020, ARM Limited. All Rights Reserved.
+*/
+
+/*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "trc_gen_elem.h"
+#include "comp_attach_pt_t.h"
+#include "interfaces/trc_gen_elem_in_i.h"
+
+/* element stack to handle cases where a trace element can generate multiple output packets
+
+ maintains the "current" element, which might be sent independently of this stack, and also
+ ensures that persistent data in the output elements is maintained between elements.
+*/
+class OcsdGenElemStack
+{
+public:
+ OcsdGenElemStack();
+ ~OcsdGenElemStack();
+
+ void initSendIf(componentAttachPt<ITrcGenElemIn> *pGenElemIf);
+ void initCSID(const uint8_t CSID) { m_CSID = CSID; };
+
+ OcsdTraceElement &getCurrElem(); //!< get the current element.
+ ocsd_err_t resetElemStack(); //!< set pointers to base of stack
+ ocsd_err_t addElem(const ocsd_trc_index_t trc_pkt_idx); //!< add elem to stack and set current.
+ void setCurrElemIdx(const ocsd_trc_index_t trc_pkt_idx); //!< packet index for this element
+ ocsd_err_t addElemType(const ocsd_trc_index_t trc_pkt_idx, ocsd_gen_trc_elem_t elem_type);
+
+ ocsd_datapath_resp_t sendElements(); //!< send elements on the stack
+ const int numElemToSend() const;
+
+private:
+ typedef struct _elemPtr {
+ OcsdTraceElement *pElem; //!< pointer to the listed trace element
+ ocsd_trc_index_t trc_pkt_idx; //!< packet index in the trace stream
+ } elemPtr_t;
+
+ const bool isInit(); //!< check correctly initialised.
+
+ ocsd_err_t growArray();
+ void copyPersistentData(int src, int dst); //!< copy across persistent state data between elements
+ void resetIndexes(); //!< clear down all indexes - reset or send complete.
+
+ elemPtr_t *m_pElemArray; //!< an array of pointers to elements.
+ int m_elemArraySize; //!< number of element pointers in the array
+
+ int m_elem_to_send; //!< number of live elements in the stack - init to 1.
+ int m_curr_elem_idx; //!< index into the element array.
+ int m_send_elem_idx; //!< next element to send.
+
+ //!< send packet info
+ uint8_t m_CSID;
+ componentAttachPt<ITrcGenElemIn> *m_sendIf; //!< element send interface.
+
+ bool m_is_init;
+};
+
+inline const int OcsdGenElemStack::numElemToSend() const
+{
+ return m_elem_to_send;
+}
+
+inline void OcsdGenElemStack::initSendIf(componentAttachPt<ITrcGenElemIn> *pGenElemIf)
+{
+ m_sendIf = pGenElemIf;
+}
+
+inline void OcsdGenElemStack::setCurrElemIdx(const ocsd_trc_index_t trc_pkt_idx)
+{
+ m_pElemArray[m_curr_elem_idx].trc_pkt_idx = trc_pkt_idx;
+}
+
+inline OcsdTraceElement &OcsdGenElemStack::getCurrElem()
+{
+ return *(m_pElemArray[m_curr_elem_idx].pElem);
+}
+
+
+/* End of File ocsd_gen_elem_stack.h */
diff --git a/decoder/include/common/trc_core_arch_map.h b/decoder/include/common/trc_core_arch_map.h
index 5a24149180fc..b72b4b411fa4 100644
--- a/decoder/include/common/trc_core_arch_map.h
+++ b/decoder/include/common/trc_core_arch_map.h
@@ -39,6 +39,23 @@
#include <string>
#include "opencsd/ocsd_if_types.h"
+/** @class CoreArchProfileMap
+ *
+ * @brief Map core / arch name to profile for decoder.
+ *
+ * Helper class for library clients to map core or architecture version names onto
+ * a profile / arch version pair suitable for use with the decode library.
+ *
+ * Valid core names are:-
+ * - Cortex-Axx : where xx = 5,7,12,15,17,32,35,53,55,57,65,72,73,75,76,77;
+ * - Cortex-Rxx : where xx = 5,7,8,52;
+ * - Cortex-Mxx : where xx = 0,0+,3,4,23,33;
+ *
+ * Valid architecture profile names are:-
+ * - ARMv7-A, ARMv7-R, ARMv7-M;
+ * - ARMv8-A, ARMv8.3A, ARMv8-R, ARMv8-M;
+ *
+ */
class CoreArchProfileMap
{
public:
@@ -50,16 +67,31 @@ public:
private:
std::map<std::string, ocsd_arch_profile_t> core_profiles;
+ std::map<std::string, ocsd_arch_profile_t> arch_profiles;
};
inline ocsd_arch_profile_t CoreArchProfileMap::getArchProfile(const std::string &coreName)
{
ocsd_arch_profile_t ap = { ARCH_UNKNOWN, profile_Unknown };
+ bool bFound = false;
std::map<std::string, ocsd_arch_profile_t>::const_iterator it;
+
+ /* match against the core name map. */
it = core_profiles.find(coreName);
- if(it != core_profiles.end())
+ if (it != core_profiles.end())
+ {
ap = it->second;
+ bFound = true;
+ }
+
+ /* scan architecture profiles on no core name match */
+ if (!bFound)
+ {
+ it = arch_profiles.find(coreName);
+ if (it != arch_profiles.end())
+ ap = it->second;
+ }
return ap;
}
diff --git a/decoder/include/common/trc_gen_elem.h b/decoder/include/common/trc_gen_elem.h
index 1c4a47b3aa0a..5d8983a8c274 100644
--- a/decoder/include/common/trc_gen_elem.h
+++ b/decoder/include/common/trc_gen_elem.h
@@ -72,6 +72,7 @@ public:
void setTraceOnReason(const trace_on_reason_t reason);
+ void setUnSyncEOTReason(const unsync_info_t reason);
void setAddrRange(const ocsd_vaddr_t st_addr, const ocsd_vaddr_t en_addr, const int num_instr = 1);
void setLastInstrInfo(const bool exec, const ocsd_instr_type last_i_type, const ocsd_instr_subtype last_i_subtype, const uint8_t size);
@@ -94,7 +95,8 @@ public:
// return current context
const ocsd_pe_context &getContext() const { return context; };
-
+ void copyPersistentData(const OcsdTraceElement &src);
+
private:
void printSWInfoPkt(std::ostringstream &oss) const;
void clearPerPktData(); //!< clear flags that indicate validity / have values on a per packet basis
@@ -171,8 +173,8 @@ inline void OcsdTraceElement::init()
inline void OcsdTraceElement::clearPerPktData()
{
- flag_bits = 0; // union with trace_on_reason / trace_event
-
+ flag_bits = 0; // bit-field with various flags.
+ exception_number = 0; // union with trace_on_reason / trace_event
ptr_extended_data = 0; // extended data pointer
}
@@ -181,6 +183,11 @@ inline void OcsdTraceElement::setTraceOnReason(const trace_on_reason_t reason)
trace_on_reason = reason;
}
+inline void OcsdTraceElement::setUnSyncEOTReason(const unsync_info_t reason)
+{
+ unsync_eot_info = reason;
+}
+
inline void OcsdTraceElement::setISA(const ocsd_isa isa_update)
{
isa = isa_update;
@@ -201,6 +208,12 @@ inline void OcsdTraceElement::setExtendedDataPtr(const void *data_ptr)
ptr_extended_data = data_ptr;
}
+// set persistent data between output packets.
+inline void OcsdTraceElement::copyPersistentData(const OcsdTraceElement &src)
+{
+ isa = src.isa;
+ context = src.context;
+}
/** @}*/
diff --git a/decoder/include/common/trc_pkt_decode_base.h b/decoder/include/common/trc_pkt_decode_base.h
index 2bbf5e51d878..da702068f372 100644
--- a/decoder/include/common/trc_pkt_decode_base.h
+++ b/decoder/include/common/trc_pkt_decode_base.h
@@ -85,7 +85,10 @@ protected:
virtual ocsd_err_t onProtocolConfig() = 0;
virtual const uint8_t getCoreSightTraceID() = 0;
+ /* init handling */
const bool checkInit();
+ /* Called on first init confirmation */
+ virtual void onFirstInitOK() {};
/* data output */
ocsd_datapath_resp_t outputTraceElement(const OcsdTraceElement &elem); // use current index
@@ -147,6 +150,8 @@ inline const bool TrcPktDecodeI::checkInit()
init_err_msg = "No instruction decoder interface attached and enabled";
else
m_decode_init_ok = true;
+ if (m_decode_init_ok)
+ onFirstInitOK();
}
return m_decode_init_ok;
}
diff --git a/decoder/include/common/trc_raw_buffer.h b/decoder/include/common/trc_raw_buffer.h
new file mode 100644
index 000000000000..67b8d2403457
--- /dev/null
+++ b/decoder/include/common/trc_raw_buffer.h
@@ -0,0 +1,96 @@
+/*
+* \file trc_raw_buffer.h
+* \brief OpenCSD : Trace raw data byte buffer
+*
+* \copyright Copyright (c) 2019, ARM Limited. All Rights Reserved.
+*/
+
+/*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef ARM_TRC_RAW_BUFFER_H_INCLUDED
+#define ARM_TRC_RAW_BUFFER_H_INCLUDED
+
+#include <vector>
+
+class TraceRawBuffer
+{
+public:
+ TraceRawBuffer() :
+ m_bufSize(0),
+ m_bufProcessed(0),
+ m_pBuffer(0),
+ pkt(0)
+ {};
+ ~TraceRawBuffer() {};
+
+ // init the buffer
+ void init(const uint32_t size, const uint8_t *rawtrace, std::vector<uint8_t> *out_packet);
+ void copyByteToPkt(); // move a byte to the packet buffer
+ uint8_t peekNextByte(); // value of next byte in buffer.
+
+ bool empty() { return m_bufProcessed == m_bufSize; };
+ // bytes processed.
+ uint32_t processed() { return m_bufProcessed; };
+ // buffer size;
+ uint32_t size() { return m_bufSize; }
+
+private:
+ uint32_t m_bufSize;
+ uint32_t m_bufProcessed;
+ const uint8_t *m_pBuffer;
+ std::vector<uint8_t> *pkt;
+
+};
+
+// init the buffer
+inline void TraceRawBuffer::init(const uint32_t size, const uint8_t *rawtrace, std::vector<uint8_t> *out_packet)
+{
+ m_bufSize = size;
+ m_bufProcessed = 0;
+ m_pBuffer = rawtrace;
+ pkt = out_packet;
+}
+
+inline void TraceRawBuffer::copyByteToPkt()
+{
+ if (!empty()) {
+ pkt->push_back(m_pBuffer[m_bufProcessed]);
+ m_bufProcessed++;
+ }
+}
+
+inline uint8_t TraceRawBuffer::peekNextByte()
+{
+ uint8_t val = 0;
+ if (!empty())
+ val = m_pBuffer[m_bufProcessed];
+ return val;
+}
+
+#endif // ARM_TRC_RAW_BUFFER_H_INCLUDED
+
diff --git a/decoder/include/i_dec/trc_i_decode.h b/decoder/include/i_dec/trc_i_decode.h
index 0285f4182523..d519a3aca7be 100644
--- a/decoder/include/i_dec/trc_i_decode.h
+++ b/decoder/include/i_dec/trc_i_decode.h
@@ -46,10 +46,9 @@ public:
virtual ocsd_err_t DecodeInstruction(ocsd_instr_info *instr_info);
private:
- ocsd_err_t DecodeA32(ocsd_instr_info *instr_info);
- ocsd_err_t DecodeA64(ocsd_instr_info *instr_info);
- ocsd_err_t DecodeT32(ocsd_instr_info *instr_info);
- void SetArchVersion(ocsd_instr_info *instr_info);
+ ocsd_err_t DecodeA32(ocsd_instr_info *instr_info, struct decode_info *info);
+ ocsd_err_t DecodeA64(ocsd_instr_info *instr_info, struct decode_info *info);
+ ocsd_err_t DecodeT32(ocsd_instr_info *instr_info, struct decode_info *info);
};
#endif // ARM_TRC_I_DECODE_H_INCLUDED
diff --git a/decoder/include/i_dec/trc_idec_arminst.h b/decoder/include/i_dec/trc_idec_arminst.h
index 8697f68d676c..911b0cf7db95 100644
--- a/decoder/include/i_dec/trc_idec_arminst.h
+++ b/decoder/include/i_dec/trc_idec_arminst.h
@@ -42,6 +42,12 @@
#include "opencsd/ocsd_if_types.h"
#include <cstdint>
+/* supplementary decode information */
+struct decode_info {
+ uint16_t arch_version;
+ ocsd_instr_subtype instr_sub_type;
+};
+
/*
For Thumb2, test if a halfword is the first half of a 32-bit instruction,
as opposed to a complete 16-bit instruction.
@@ -63,19 +69,19 @@ instructions that write to the PC. It does not include exception
instructions such as SVC, HVC and SMC.
(Performance event 0x0C includes these.)
*/
-int inst_ARM_is_branch(uint32_t inst);
-int inst_Thumb_is_branch(uint32_t inst);
-int inst_A64_is_branch(uint32_t inst);
+int inst_ARM_is_branch(uint32_t inst, struct decode_info *info);
+int inst_Thumb_is_branch(uint32_t inst, struct decode_info *info);
+int inst_A64_is_branch(uint32_t inst, struct decode_info *info);
/*
Test whether an instruction is a direct (aka immediate) branch.
Performance event 0x0D counts these.
*/
int inst_ARM_is_direct_branch(uint32_t inst);
-int inst_Thumb_is_direct_branch(uint32_t inst);
-int inst_Thumb_is_direct_branch_link(uint32_t inst, uint8_t *is_link, uint8_t *is_cond);
-int inst_A64_is_direct_branch(uint32_t inst);
-int inst_A64_is_direct_branch_link(uint32_t inst, uint8_t *is_link);
+int inst_Thumb_is_direct_branch(uint32_t inst, struct decode_info *info);
+int inst_Thumb_is_direct_branch_link(uint32_t inst, uint8_t *is_link, uint8_t *is_cond, struct decode_info *info);
+int inst_A64_is_direct_branch(uint32_t inst, struct decode_info *info);
+int inst_A64_is_direct_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info);
/*
Get branch destination for a direct branch.
@@ -84,15 +90,15 @@ int inst_ARM_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc);
int inst_Thumb_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc);
int inst_A64_branch_destination(uint64_t addr, uint32_t inst, uint64_t *pnpc);
-int inst_ARM_is_indirect_branch(uint32_t inst);
-int inst_Thumb_is_indirect_branch_link(uint32_t inst, uint8_t *is_link);
-int inst_Thumb_is_indirect_branch(uint32_t inst);
-int inst_A64_is_indirect_branch_link(uint32_t inst, uint8_t *is_link);
-int inst_A64_is_indirect_branch(uint32_t inst);
+int inst_ARM_is_indirect_branch(uint32_t inst, struct decode_info *info);
+int inst_Thumb_is_indirect_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info);
+int inst_Thumb_is_indirect_branch(uint32_t inst, struct decode_info *info);
+int inst_A64_is_indirect_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info);
+int inst_A64_is_indirect_branch(uint32_t inst, struct decode_info *info);
-int inst_ARM_is_branch_and_link(uint32_t inst);
-int inst_Thumb_is_branch_and_link(uint32_t inst);
-int inst_A64_is_branch_and_link(uint32_t inst);
+int inst_ARM_is_branch_and_link(uint32_t inst, struct decode_info *info);
+int inst_Thumb_is_branch_and_link(uint32_t inst, struct decode_info *info);
+int inst_A64_is_branch_and_link(uint32_t inst, struct decode_info *info);
int inst_ARM_is_conditional(uint32_t inst);
int inst_Thumb_is_conditional(uint32_t inst);
@@ -128,14 +134,6 @@ int inst_ARM_is_UDF(uint32_t inst);
int inst_Thumb_is_UDF(uint32_t inst);
int inst_A64_is_UDF(uint32_t inst);
-
-/* access sub-type information */
-ocsd_instr_subtype get_instr_subtype();
-void clear_instr_subtype();
-
-/* set arch version info. */
-void set_arch_version(uint16_t version);
-
#endif // ARM_TRC_IDEC_ARMINST_H_INCLUDED
/* End of File trc_idec_arminst.h */
diff --git a/decoder/include/mem_acc/trc_mem_acc_bufptr.h b/decoder/include/mem_acc/trc_mem_acc_bufptr.h
index bd9ea8ee1e5d..b6208a7d8a13 100644
--- a/decoder/include/mem_acc/trc_mem_acc_bufptr.h
+++ b/decoder/include/mem_acc/trc_mem_acc_bufptr.h
@@ -68,7 +68,6 @@ public:
private:
const uint8_t *m_p_buffer; /**< pointer to the memory buffer */
- const uint32_t m_size; /**< size of the memory buffer. */
};
#endif // ARM_TRC_MEM_ACC_BUFPTR_H_INCLUDED
diff --git a/decoder/include/opencsd/etmv3/trc_pkt_decode_etmv3.h b/decoder/include/opencsd/etmv3/trc_pkt_decode_etmv3.h
index b2139c0d9e68..902770655a53 100644
--- a/decoder/include/opencsd/etmv3/trc_pkt_decode_etmv3.h
+++ b/decoder/include/opencsd/etmv3/trc_pkt_decode_etmv3.h
@@ -264,6 +264,7 @@ private:
} processor_state_t;
processor_state_t m_curr_state;
+ unsync_info_t m_unsync_info; //!< additional state for unsync
uint8_t m_CSID; //!< Coresight trace ID for this decoder.
};
diff --git a/decoder/include/opencsd/etmv4/etmv4_decoder.h b/decoder/include/opencsd/etmv4/etmv4_decoder.h
index 05bdd44d683e..5d183631a721 100644
--- a/decoder/include/opencsd/etmv4/etmv4_decoder.h
+++ b/decoder/include/opencsd/etmv4/etmv4_decoder.h
@@ -38,7 +38,6 @@
#include "trc_cmp_cfg_etmv4.h"
#include "trc_pkt_elem_etmv4i.h"
-#include "trc_pkt_elem_etmv4d.h"
#include "trc_pkt_proc_etmv4.h"
#include "trc_pkt_types_etmv4.h"
#include "trc_pkt_decode_etmv4i.h"
diff --git a/decoder/include/opencsd/etmv4/trc_etmv4_stack_elem.h b/decoder/include/opencsd/etmv4/trc_etmv4_stack_elem.h
index 15996547163c..5a283c541f3e 100644
--- a/decoder/include/opencsd/etmv4/trc_etmv4_stack_elem.h
+++ b/decoder/include/opencsd/etmv4/trc_etmv4_stack_elem.h
@@ -56,6 +56,7 @@ typedef enum _p0_elem_t
P0_TS,
P0_CC,
P0_TS_CC,
+ P0_Q,
P0_OVERFLOW,
P0_FUNC_RET,
} p0_elem_t;
@@ -120,6 +121,44 @@ inline TrcStackElemAddr::TrcStackElemAddr(const ocsd_etmv4_i_pkt_type root_pkt,
}
/************************************************************/
+/** Q element */
+class TrcStackQElem : public TrcStackElem
+{
+protected:
+ TrcStackQElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index);
+ virtual ~TrcStackQElem() {};
+
+ friend class EtmV4P0Stack;
+
+public:
+ void setInstrCount(const int instr_count) { m_instr_count = instr_count; };
+ const int getInstrCount() const { return m_instr_count; }
+
+ void setAddr(const etmv4_addr_val_t &addr_val)
+ {
+ m_addr_val = addr_val;
+ m_has_addr = true;
+ };
+ const etmv4_addr_val_t &getAddr() const { return m_addr_val; };
+ const bool hasAddr() const { return m_has_addr; };
+
+private:
+ bool m_has_addr;
+ etmv4_addr_val_t m_addr_val;
+ int m_instr_count;
+
+};
+
+inline TrcStackQElem::TrcStackQElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index) :
+ TrcStackElem(P0_Q , true, root_pkt, root_index)
+{
+ m_addr_val.val = 0;
+ m_addr_val.isa = 0;
+ m_has_addr = false;
+ m_instr_count = 0;
+}
+
+/************************************************************/
/** Context element */
class TrcStackElemCtxt : public TrcStackElem
@@ -133,9 +172,12 @@ protected:
public:
void setContext(const etmv4_context_t &ctxt) { m_context = ctxt; };
const etmv4_context_t &getContext() const { return m_context; };
+ void setIS(const uint8_t IS) { m_IS = IS; };
+ const uint8_t getIS() const { return m_IS; };
private:
etmv4_context_t m_context;
+ uint8_t m_IS; //!< IS value at time of generation of packet.
};
inline TrcStackElemCtxt::TrcStackElemCtxt(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index) :
@@ -188,6 +230,7 @@ public:
const ocsd_atm_val commitOldest();
int cancelNewest(const int nCancel);
+ void mispredictNewest();
const bool isEmpty() const { return (m_atom.num == 0); };
private:
@@ -217,6 +260,16 @@ inline int TrcStackElemAtom::cancelNewest(const int nCancel)
return nRemove;
}
+// mispredict newest - flip the bit of the newest atom
+inline void TrcStackElemAtom::mispredictNewest()
+{
+ uint32_t mask = 0x1 << (m_atom.num - 1);
+ if (m_atom.En_bits & mask)
+ m_atom.En_bits &= ~mask;
+ else
+ m_atom.En_bits |= mask;
+}
+
/************************************************************/
/** Generic param element */
@@ -252,12 +305,20 @@ public:
void push_front(TrcStackElem *pElem);
void push_back(TrcStackElem *pElem); // insert element when processing
- void pop_back();
+ void pop_back(bool pend_delete = true);
+ void pop_front(bool pend_delete = true);
TrcStackElem *back();
+ TrcStackElem *front();
size_t size();
+ // iterate through stack from front
+ void from_front_init();
+ TrcStackElem *from_front_next();
+ void erase_curr_from_front(); // erase the element last returned
+
void delete_all();
void delete_back();
+ void delete_front();
void delete_popped();
// creation functions - create and push if successful.
@@ -265,13 +326,13 @@ public:
TrcStackElem *createParamElemNoParam(const p0_elem_t p0_type, const bool isP0, const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, bool back = false);
TrcStackElemAtom *createAtomElem (const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, const ocsd_pkt_atom &atom);
TrcStackElemExcept *createExceptElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, const bool bSame, const uint16_t excepNum);
- TrcStackElemCtxt *createContextElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, const etmv4_context_t &context);
+ TrcStackElemCtxt *createContextElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, const etmv4_context_t &context, const uint8_t IS, const bool back = false);
TrcStackElemAddr *createAddrElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, const etmv4_addr_val_t &addr_val);
-
+ TrcStackQElem *createQElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, const int count);
private:
std::deque<TrcStackElem *> m_P0_stack; //!< P0 decode element stack
std::vector<TrcStackElem *> m_popped_elem; //!< save list of popped but not deleted elements.
-
+ std::deque<TrcStackElem *>::iterator m_iter; //!< iterate across the list w/o removing stuff
};
inline EtmV4P0Stack::~EtmV4P0Stack()
@@ -293,12 +354,20 @@ inline void EtmV4P0Stack::push_back(TrcStackElem *pElem)
}
// pop last element pointer off the stack and stash it for later deletion
-inline void EtmV4P0Stack::pop_back()
+inline void EtmV4P0Stack::pop_back(bool pend_delete /* = true */)
{
- m_popped_elem.push_back(m_P0_stack.back());
+ if (pend_delete)
+ m_popped_elem.push_back(m_P0_stack.back());
m_P0_stack.pop_back();
}
+inline void EtmV4P0Stack::pop_front(bool pend_delete /* = true */)
+{
+ if (pend_delete)
+ m_popped_elem.push_back(m_P0_stack.front());
+ m_P0_stack.pop_front();
+}
+
// pop last element pointer off the stack and delete immediately
inline void EtmV4P0Stack::delete_back()
{
@@ -310,12 +379,30 @@ inline void EtmV4P0Stack::delete_back()
}
}
+// pop first element pointer off the stack and delete immediately
+inline void EtmV4P0Stack::delete_front()
+{
+ if (m_P0_stack.size() > 0)
+ {
+ TrcStackElem* pElem = m_P0_stack.front();
+ delete pElem;
+ m_P0_stack.pop_front();
+ }
+}
+
+
+
// get a pointer to the last element on the stack
inline TrcStackElem *EtmV4P0Stack::back()
{
return m_P0_stack.back();
}
+inline TrcStackElem *EtmV4P0Stack::front()
+{
+ return m_P0_stack.front();
+}
+
// remove and delete all the elements left on the stack
inline void EtmV4P0Stack::delete_all()
{
diff --git a/decoder/include/opencsd/etmv4/trc_pkt_decode_etmv4i.h b/decoder/include/opencsd/etmv4/trc_pkt_decode_etmv4i.h
index 1c06e5ddf03a..419cd828928c 100644
--- a/decoder/include/opencsd/etmv4/trc_pkt_decode_etmv4i.h
+++ b/decoder/include/opencsd/etmv4/trc_pkt_decode_etmv4i.h
@@ -40,6 +40,7 @@
#include "opencsd/etmv4/trc_cmp_cfg_etmv4.h"
#include "common/trc_gen_elem.h"
#include "common/trc_ret_stack.h"
+#include "common/ocsd_gen_elem_stack.h"
#include "opencsd/etmv4/trc_etmv4_stack_elem.h"
class TrcStackElem;
@@ -65,35 +66,69 @@ protected:
/* local decode methods */
void initDecoder(); // initial state on creation (zeros all config)
void resetDecoder(); // reset state to start of decode. (moves state, retains config)
+ virtual void onFirstInitOK(); // override to set init related info.
- ocsd_datapath_resp_t decodePacket(bool &Complete); // return true to indicate decode complete - can change FSM to commit state - return is false.
- ocsd_datapath_resp_t commitElements(bool &Complete); // commit elements - may get wait response, or flag completion.
- ocsd_datapath_resp_t flushEOT();
+ ocsd_err_t decodePacket(); // decode packet into trace elements. return true to indicate decode complete - can change FSM to commit state - return is false.
+ ocsd_datapath_resp_t resolveElements(); // commit/cancel trace elements generated from latest / prior packets & send to output - may get wait response, or flag completion.
+ ocsd_err_t commitElements(); // commit elements - process element stack to generate output packets.
+ ocsd_err_t commitElemOnEOT();
+ ocsd_err_t cancelElements(); // cancel elements. These not output
+ ocsd_err_t mispredictAtom(); // mispredict an atom
+ ocsd_err_t discardElements(); // discard elements and flush
void doTraceInfoPacket();
- void updateContext(TrcStackElemCtxt *pCtxtElem);
+ void updateContext(TrcStackElemCtxt *pCtxtElem, OcsdTraceElement &elem);
- // process atom will output instruction trace, or no memory access trace elements.
- ocsd_datapath_resp_t processAtom(const ocsd_atm_val, bool &bCont);
+ // process atom will create instruction trace, or no memory access trace output elements.
+ ocsd_err_t processAtom(const ocsd_atm_val atom);
// process an exception element - output instruction trace + exception generic type.
- ocsd_datapath_resp_t processException();
+ ocsd_err_t processException();
+
+ // process Q element
+ ocsd_err_t processQElement();
+
+ // process an element that cannot be cancelled / discarded
+ ocsd_err_t processTS_CC_EventElem(TrcStackElem *pElem);
// process a bad packet
- ocsd_datapath_resp_t handleBadPacket(const char *reason);
+ ocsd_err_t handleBadPacket(const char *reason);
- ocsd_datapath_resp_t outputCC(TrcStackElemParam *pParamElem);
- ocsd_datapath_resp_t outputTS(TrcStackElemParam *pParamElem, bool withCC);
- ocsd_datapath_resp_t outputEvent(TrcStackElemParam *pParamElem);
+ ocsd_err_t addElemCC(TrcStackElemParam *pParamElem);
+ ocsd_err_t addElemTS(TrcStackElemParam *pParamElem, bool withCC);
+ ocsd_err_t addElemEvent(TrcStackElemParam *pParamElem);
private:
void SetInstrInfoInAddrISA(const ocsd_vaddr_t addr_val, const uint8_t isa);
+ const ocsd_isa calcISA(const bool SF, const uint8_t IS) const
+ {
+ if (SF)
+ return ocsd_isa_aarch64;
+ return (IS == 0) ? ocsd_isa_arm : ocsd_isa_thumb2;
+ }
+ typedef enum {
+ WP_NOT_FOUND,
+ WP_FOUND,
+ WP_NACC
+ } WP_res_t;
+
+ typedef struct {
+ ocsd_vaddr_t st_addr;
+ ocsd_vaddr_t en_addr;
+ uint32_t num_instr;
+ } instr_range_t;
- ocsd_err_t traceInstrToWP(bool &bWPFound, const bool traceToAddrNext = false, const ocsd_vaddr_t nextAddrMatch = 0); //!< follow instructions from the current address to a WP. true if good, false if memory cannot be accessed.
+ //!< follow instructions from the current address to a WP. true if good, false if memory cannot be accessed.
+ ocsd_err_t traceInstrToWP(instr_range_t &instr_range, WP_res_t &WPRes, const bool traceToAddrNext = false, const ocsd_vaddr_t nextAddrMatch = 0);
- ocsd_datapath_resp_t returnStackPop(); // pop return stack and update instruction address.
+ inline const bool WPFound(WP_res_t res) const { return (res == WP_FOUND); };
+ inline const bool WPNacc(WP_res_t res) const { return (res == WP_NACC); };
+
+ ocsd_err_t returnStackPop(); // pop return stack and update instruction address.
- ocsd_datapath_resp_t outputTraceRange(const bool executed, ocsd_trc_index_t index);
+ void setElemTraceRange(OcsdTraceElement &elemIn, const instr_range_t &addr_range, const bool executed, ocsd_trc_index_t index);
+
+ ocsd_mem_space_acc_t getCurrMemSpace();
//** intra packet state (see ETMv4 spec 6.2.1);
@@ -105,14 +140,18 @@ private:
uint32_t m_vmid_id; // most recent VMID
bool m_is_secure; // true if Secure
bool m_is_64bit; // true if 64 bit
+ uint8_t m_last_IS; // last instruction set value from address packet.
// cycle counts
int m_cc_threshold;
- // speculative trace (unsupported at present in the decoder).
+ // speculative trace
int m_curr_spec_depth;
- int m_max_spec_depth;
-
+ int m_max_spec_depth; // nax depth - from ID reg, beyond which auto-commit occurs
+ int m_unseen_spec_elem; // speculative elements at decode start
+
+/** Remove elements that are associated with data trace */
+#ifdef DATA_TRACE_SUPPORTED
// data trace associative elements (unsupported at present in the decoder).
int m_p0_key;
int m_p0_key_max;
@@ -121,6 +160,7 @@ private:
int m_cond_c_key;
int m_cond_r_key;
int m_cond_key_max_incr;
+#endif
uint8_t m_CSID; //!< Coresight trace ID for this decoder.
@@ -134,55 +174,52 @@ private:
WAIT_SYNC, //!< waiting for sync packet.
WAIT_TINFO, //!< waiting for trace info packet.
DECODE_PKTS, //!< processing packets - creating decode elements on stack
- COMMIT_ELEM, //!< commit elements for execution - create generic trace elements and pass on.
+ RESOLVE_ELEM, //!< analyze / resolve decode elements - create generic trace elements and pass on.
} processor_state_t;
processor_state_t m_curr_state;
+ unsync_info_t m_unsync_eot_info; //!< addition info when / why unsync / eot
//** P0 element stack
EtmV4P0Stack m_P0_stack; //!< P0 decode element stack
- int m_P0_commit; //!< number of elements to commit
+ // element resolution
+ struct {
+ int P0_commit; //!< number of elements to commit
+ int P0_cancel; //!< elements to cancel
+ bool mispredict; //!< mispredict latest atom
+ bool discard; //!< discard elements
+ } m_elem_res;
+
+ //! true if any of the element resolution fields are non-zero
+ const bool isElemForRes() const {
+ return (m_elem_res.P0_commit || m_elem_res.P0_cancel ||
+ m_elem_res.mispredict || m_elem_res.discard);
+ }
+
+ void clearElemRes() {
+ m_elem_res.P0_commit = 0;
+ m_elem_res.P0_cancel = 0;
+ m_elem_res.mispredict = false;
+ m_elem_res.discard = false;
+ }
// packet decode state
bool m_need_ctxt; //!< need context to continue
bool m_need_addr; //!< need an address to continue
- bool m_except_pending_addr; //!< next address packet is part of exception.
-
- // exception packet processing state (may need excep elem only, range+excep, range+
- typedef enum {
- EXCEP_POP, // start of processing read exception packets off the stack and analyze
- EXCEP_RANGE, // output a range element
- EXCEP_NACC, // output a nacc element
- EXCEP_CTXT, // output a ctxt element
- EXCEP_EXCEP, // output an ecxeption element.
- } excep_proc_state_t;
-
- struct {
- excep_proc_state_t proc; //!< state of exception processing
- etmv4_addr_val_t addr; //!< excetion return address.
- uint32_t number; //!< exception number.
- ocsd_trc_index_t index; //!< trace index for exception element
- bool addr_b_tgt; //!< return address is also branch tgt address.
- } m_excep_info; //!< exception info when processing exception packets
+ bool m_elem_pending_addr; //!< next address packet is needed for prev element.
ocsd_instr_info m_instr_info; //!< instruction info for code follower - in address is the next to be decoded.
- bool m_mem_nacc_pending; //!< need to output a memory access failure packet
- ocsd_vaddr_t m_nacc_addr; //!< record unaccessible address
-
- ocsd_pe_context m_pe_context; //!< current context information
etmv4_trace_info_t m_trace_info; //!< trace info for this trace run.
bool m_prev_overflow;
- bool m_flush_EOT; //!< true if doing an end of trace flush - cleans up lingering events / TS / CC
-
- TrcAddrReturnStack m_return_stack;
-
-//** output element
- OcsdTraceElement m_output_elem;
+ TrcAddrReturnStack m_return_stack; //!< the address return stack.
+//** output element handling
+ OcsdGenElemStack m_out_elem; //!< output element stack.
+ OcsdTraceElement &outElem() { return m_out_elem.getCurrElem(); }; //!< current out element
};
#endif // ARM_TRC_PKT_DECODE_ETMV4I_H_INCLUDED
diff --git a/decoder/include/opencsd/etmv4/trc_pkt_elem_etmv4d.h b/decoder/include/opencsd/etmv4/trc_pkt_elem_etmv4d.h
deleted file mode 100644
index bb6a0029c0c0..000000000000
--- a/decoder/include/opencsd/etmv4/trc_pkt_elem_etmv4d.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * \file trc_pkt_elem_etmv4d.h
- * \brief OpenCSD :
- *
- * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- * may be used to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef ARM_TRC_PKT_ELEM_ETMV4D_H_INCLUDED
-#define ARM_TRC_PKT_ELEM_ETMV4D_H_INCLUDED
-
-#include "trc_pkt_types_etmv4.h"
-#include "common/trc_printable_elem.h"
-#include "common/trc_pkt_elem_base.h"
-
-/** @addtogroup trc_pkts
-@{*/
-/*!
- * @class EtmV4DTrcPacket
- * @brief ETMv4 Data Trace Protocol Packet .
- *
- * This class represents a single ETMv4 instruction trace packet, along with intra packet state.
- *
- */
-class EtmV4DTrcPacket : public TrcPacketBase, public ocsd_etmv4_d_pkt, trcPrintableElem
-{
-public:
- EtmV4DTrcPacket();
- ~EtmV4DTrcPacket();
-
- // update interface - set packet values
-
-
-
- // packet status interface - get packet info.
-
-
- // printing
- virtual void toString(std::string &str) const;
- virtual void toStringFmt(const uint32_t fmtFlags, std::string &str) const;
-};
-
-/** @}*/
-
-#endif // ARM_TRC_PKT_ELEM_ETMV4D_H_INCLUDED
-
-/* End of File trc_pkt_elem_etmv4d.h */
diff --git a/decoder/include/opencsd/etmv4/trc_pkt_elem_etmv4i.h b/decoder/include/opencsd/etmv4/trc_pkt_elem_etmv4i.h
index 02adfc51aa75..8ccf36b373db 100644
--- a/decoder/include/opencsd/etmv4/trc_pkt_elem_etmv4i.h
+++ b/decoder/include/opencsd/etmv4/trc_pkt_elem_etmv4i.h
@@ -57,14 +57,7 @@ class Etmv4PktAddrStack
public:
Etmv4PktAddrStack()
{
- for (int i = 0; i < 3; i++)
- {
- m_v_addr[i].pkt_bits = 0;
- m_v_addr[i].size = VA_64BIT;
- m_v_addr[i].val = 0;
- m_v_addr[i].valid_bits = 0;
- m_v_addr_ISA[i] = 0;
- }
+ reset_stack();
}
~Etmv4PktAddrStack() {};
@@ -87,6 +80,20 @@ public:
}
}
+ // explicit reset for TInfo.
+ void reset_stack()
+ {
+ for (int i = 0; i < 3; i++)
+ {
+ m_v_addr[i].pkt_bits = 0;
+ m_v_addr[i].size = OCSD_MAX_VA_BITSIZE == 64 ? VA_64BIT : VA_32BIT;
+ m_v_addr[i].val = 0;
+ m_v_addr[i].valid_bits = OCSD_MAX_VA_BITSIZE;
+ m_v_addr_ISA[i] = 0;
+ }
+
+ }
+
private:
ocsd_pkt_vaddr m_v_addr[3]; //!< most recently broadcast address packet
uint8_t m_v_addr_ISA[3];
@@ -172,6 +179,7 @@ public:
// atom
const ocsd_pkt_atom &getAtom() const { return atom; };
+ const int getNumAtoms() const { return atom.num; };
// context
const etmv4_context_t &getContext() const { return context; };
@@ -188,6 +196,10 @@ public:
// cc
const uint32_t getCC() const { return pkt_valid.bits.cc_valid ? cycle_count : 0; };
+ // speculation
+ const int getCommitElem() const { return commit_elements; };
+ const int getCancelElem() const { return cancel_elements; };
+
// packet type
const bool isBadPacket() const;
@@ -227,6 +239,10 @@ inline void EtmV4ITrcPacket::clearTraceInfo()
// set these as defaults - if they don't appear in TINFO this is the state.
setTraceInfo(0);
setTraceInfoSpec(0);
+
+ // explicitly reset the stack & zero the current address.
+ m_addr_stack.reset_stack();
+ m_addr_stack.get_idx(0, v_addr, v_addr_ISA);
}
inline void EtmV4ITrcPacket::setTraceInfo(const uint32_t infoVal)
@@ -450,17 +466,17 @@ inline void EtmV4ITrcPacket::set32BitAddress(const uint32_t addr, const uint8_t
if (pkt_valid.bits.context_valid && context.SF)
{
v_addr.size = VA_64BIT;
- if (v_addr.valid_bits < 32) // may be updating a 64 bit address so only set 32 if currently less.
- v_addr.valid_bits = 32;
v_addr.val = (v_addr.val & ~mask) | (addr & mask);
}
else
{
v_addr.val = addr;
v_addr.size = VA_32BIT;
- v_addr.valid_bits = 32;
}
-
+
+ if (v_addr.valid_bits < 32) // may be updating a 64 bit address so only set 32 if currently less.
+ v_addr.valid_bits = 32;
+
v_addr_ISA = IS;
push_vaddr();
}
diff --git a/decoder/include/opencsd/etmv4/trc_pkt_proc_etmv4.h b/decoder/include/opencsd/etmv4/trc_pkt_proc_etmv4.h
index 0d9ccea2be54..25bdf5109558 100644
--- a/decoder/include/opencsd/etmv4/trc_pkt_proc_etmv4.h
+++ b/decoder/include/opencsd/etmv4/trc_pkt_proc_etmv4.h
@@ -35,70 +35,13 @@
#ifndef ARM_TRC_PKT_PROC_ETMV4_H_INCLUDED
#define ARM_TRC_PKT_PROC_ETMV4_H_INCLUDED
+// split I & D into separate files, retain this header for backward compatibility
+// for now just include the I packet processor as that is the only one implemented.
#include "trc_pkt_types_etmv4.h"
+#include "trc_pkt_proc_etmv4i.h"
#include "common/trc_pkt_proc_base.h"
-class EtmV4IPktProcImpl; /**< ETMv4 I channel packet processor */
-class EtmV4DPktProcImpl; /**< ETMv4 D channel packet processor */
-class EtmV4ITrcPacket;
-class EtmV4DTrcPacket;
-class EtmV4Config;
-
-/** @addtogroup ocsd_pkt_proc
-@{*/
-
-class TrcPktProcEtmV4I : public TrcPktProcBase< EtmV4ITrcPacket, ocsd_etmv4_i_pkt_type, EtmV4Config>
-{
-public:
- TrcPktProcEtmV4I();
- TrcPktProcEtmV4I(int instIDNum);
- virtual ~TrcPktProcEtmV4I();
-
-protected:
- /* implementation packet processing interface */
- virtual ocsd_datapath_resp_t processData( const ocsd_trc_index_t index,
- const uint32_t dataBlockSize,
- const uint8_t *pDataBlock,
- uint32_t *numBytesProcessed);
- virtual ocsd_datapath_resp_t onEOT();
- virtual ocsd_datapath_resp_t onReset();
- virtual ocsd_datapath_resp_t onFlush();
- virtual ocsd_err_t onProtocolConfig();
- virtual const bool isBadPacket() const;
-
- friend class EtmV4IPktProcImpl;
-
- EtmV4IPktProcImpl *m_pProcessor;
-};
-
-
-class TrcPktProcEtmV4D : public TrcPktProcBase< EtmV4DTrcPacket, ocsd_etmv4_d_pkt_type, EtmV4Config>
-{
-public:
- TrcPktProcEtmV4D();
- TrcPktProcEtmV4D(int instIDNum);
- virtual ~TrcPktProcEtmV4D();
-
-protected:
- /* implementation packet processing interface */
- virtual ocsd_datapath_resp_t processData( const ocsd_trc_index_t index,
- const uint32_t dataBlockSize,
- const uint8_t *pDataBlock,
- uint32_t *numBytesProcessed);
- virtual ocsd_datapath_resp_t onEOT();
- virtual ocsd_datapath_resp_t onReset();
- virtual ocsd_datapath_resp_t onFlush();
- virtual ocsd_err_t onProtocolConfig();
- virtual const bool isBadPacket() const;
-
- friend class EtmV4DPktProcImpl;
-
- EtmV4DPktProcImpl *m_pProcessor;
-};
-
-/** @}*/
-
#endif // ARM_TRC_PKT_PROC_ETMV4_H_INCLUDED
/* End of File trc_pkt_proc_etmv4.h */
diff --git a/decoder/source/etmv4/trc_pkt_proc_etmv4i_impl.h b/decoder/include/opencsd/etmv4/trc_pkt_proc_etmv4i.h
index 429f32711f3e..abc322654b8d 100644
--- a/decoder/source/etmv4/trc_pkt_proc_etmv4i_impl.h
+++ b/decoder/include/opencsd/etmv4/trc_pkt_proc_etmv4i.h
@@ -1,8 +1,8 @@
/*
- * \file trc_pkt_proc_etmv4i_impl.h
+ * \file trc_pkt_proc_etmv4i.h
* \brief OpenCSD : Implementation of ETMv4 packet processing
*
- * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
+ * \copyright Copyright (c) 2015, 2019 ARM Limited. All Rights Reserved.
*/
/*
@@ -35,54 +35,37 @@
#ifndef ARM_TRC_PKT_PROC_ETMV4I_IMPL_H_INCLUDED
#define ARM_TRC_PKT_PROC_ETMV4I_IMPL_H_INCLUDED
+#include "trc_pkt_types_etmv4.h"
#include "opencsd/etmv4/trc_pkt_proc_etmv4.h"
#include "opencsd/etmv4/trc_cmp_cfg_etmv4.h"
#include "opencsd/etmv4/trc_pkt_elem_etmv4i.h"
+#include "common/trc_raw_buffer.h"
+#include "common/trc_pkt_proc_base.h"
-class TraceRawBuffer
-{
-public:
- TraceRawBuffer();
- ~TraceRawBuffer() {};
-
- // init the buffer
- void init(const uint32_t size, const uint8_t *rawtrace, std::vector<uint8_t> *out_packet);
- void copyByteToPkt(); // move a byte to the packet buffer
- uint8_t peekNextByte(); // value of next byte in buffer.
-
- bool empty() { return m_bufProcessed == m_bufSize; };
- // bytes processed.
- uint32_t processed() { return m_bufProcessed; };
- // buffer size;
- uint32_t size() { return m_bufSize; }
-
-private:
- uint32_t m_bufSize;
- uint32_t m_bufProcessed;
- const uint8_t *m_pBuffer;
- std::vector<uint8_t> *pkt;
+class EtmV4ITrcPacket;
+class EtmV4Config;
-};
+/** @addtogroup ocsd_pkt_proc
+@{*/
-class EtmV4IPktProcImpl
+class TrcPktProcEtmV4I : public TrcPktProcBase< EtmV4ITrcPacket, ocsd_etmv4_i_pkt_type, EtmV4Config>
{
public:
- EtmV4IPktProcImpl();
- ~EtmV4IPktProcImpl();
-
- void Initialise(TrcPktProcEtmV4I *p_interface);
-
- ocsd_err_t Configure(const EtmV4Config *p_config);
+ TrcPktProcEtmV4I();
+ TrcPktProcEtmV4I(int instIDNum);
+ virtual ~TrcPktProcEtmV4I();
-
- ocsd_datapath_resp_t processData( const ocsd_trc_index_t index,
+protected:
+ /* implementation packet processing interface */
+ virtual ocsd_datapath_resp_t processData( const ocsd_trc_index_t index,
const uint32_t dataBlockSize,
const uint8_t *pDataBlock,
uint32_t *numBytesProcessed);
- ocsd_datapath_resp_t onEOT();
- ocsd_datapath_resp_t onReset();
- ocsd_datapath_resp_t onFlush();
- const bool isBadPacket() const;
+ virtual ocsd_datapath_resp_t onEOT();
+ virtual ocsd_datapath_resp_t onReset();
+ virtual ocsd_datapath_resp_t onFlush();
+ virtual ocsd_err_t onProtocolConfig();
+ virtual const bool isBadPacket() const;
protected:
typedef enum _process_state {
@@ -100,7 +83,6 @@ protected:
/** packet processor configuration **/
bool m_isInit;
- TrcPktProcEtmV4I *m_interface; /**< The interface to the other decode components */
// etmv4 hardware configuration
EtmV4Config m_config;
@@ -111,7 +93,6 @@ protected:
int m_currPktIdx; // index into raw packet when expanding
EtmV4ITrcPacket m_curr_packet; // expanded packet
ocsd_trc_index_t m_packet_index; // index of the start of the current packet
-// uint32_t m_blockBytesProcessed; // number of bytes processed in the current data block
ocsd_trc_index_t m_blockIndex; // index at the start of the current data block being processed
// searching for sync
@@ -207,7 +188,7 @@ private:
int extractShortAddr(const std::vector<uint8_t> &buffer, const int st_idx, const uint8_t IS, uint32_t &value, int &bits);
// packet processing is table driven.
- typedef void (EtmV4IPktProcImpl::*PPKTFN)(uint8_t);
+ typedef void (TrcPktProcEtmV4I::*PPKTFN)(uint8_t);
PPKTFN m_pIPktFn;
struct _pkt_i_table_t {
@@ -221,11 +202,13 @@ private:
};
-inline const bool EtmV4IPktProcImpl::isBadPacket() const
+inline const bool TrcPktProcEtmV4I::isBadPacket() const
{
return m_curr_packet.isBadPacket();
}
+/** @}*/
+
#endif // ARM_TRC_PKT_PROC_ETMV4I_IMPL_H_INCLUDED
/* End of File trc_pkt_proc_etmv4i_impl.h */
diff --git a/decoder/include/opencsd/etmv4/trc_pkt_types_etmv4.h b/decoder/include/opencsd/etmv4/trc_pkt_types_etmv4.h
index dd69a4bf6778..7e98050c77c4 100644
--- a/decoder/include/opencsd/etmv4/trc_pkt_types_etmv4.h
+++ b/decoder/include/opencsd/etmv4/trc_pkt_types_etmv4.h
@@ -85,7 +85,8 @@ typedef enum _ocsd_etmv4_i_pkt_type
// speculation
ETM4_PKT_I_COMMIT = 0x2D, /*!< b00101101 */
- ETM4_PKT_I_CANCEL_F1 = 0x2E, /*!< b0010111x */
+ ETM4_PKT_I_CANCEL_F1 = 0x2E, /*!< b00101110 */
+ ETM4_PKT_I_CANCEL_F1_MISPRED = 0x2F, /*!< b00101111 */
ETM4_PKT_I_MISPREDICT = 0x30, /*!< b001100xx */
ETM4_PKT_I_CANCEL_F2 = 0x34, /*!< b001101xx */
ETM4_PKT_I_CANCEL_F3 = 0x38, /*!< b00111xxx */
diff --git a/decoder/include/opencsd/ocsd_if_types.h b/decoder/include/opencsd/ocsd_if_types.h
index 7d74d77c240b..23087ee694b1 100644
--- a/decoder/include/opencsd/ocsd_if_types.h
+++ b/decoder/include/opencsd/ocsd_if_types.h
@@ -273,11 +273,11 @@ typedef enum _ocsd_dcd_tree_src_t {
/** Core Architecture Version */
typedef enum _ocsd_arch_version {
- ARCH_UNKNOWN, /**< unknown architecture */
- ARCH_CUSTOM, /**< None ARM, custom architecture */
- ARCH_V7, /**< V7 architecture */
- ARCH_V8, /**< V8 architecture */
- ARCH_V8r3, /**< V8.3 architecture */
+ ARCH_UNKNOWN = 0x0000, /**< unknown architecture */
+ ARCH_CUSTOM = 0x0001, /**< None ARM, custom architecture */
+ ARCH_V7 = 0x0700, /**< V7 architecture */
+ ARCH_V8 = 0x0800, /**< V8 architecture */
+ ARCH_V8r3 = 0x0803, /**< V8.3 architecture */
} ocsd_arch_version_t;
// macros for arch version comparisons.
@@ -430,9 +430,10 @@ typedef enum _ocsd_mem_space_acc_t {
OCSD_MEM_SPACE_EL1N = 0x2, /**< NS EL1/0 */
OCSD_MEM_SPACE_EL2 = 0x4, /**< NS EL2 */
OCSD_MEM_SPACE_EL3 = 0x8, /**< S EL3 */
- OCSD_MEM_SPACE_S = 0x9, /**< Any S */
+ OCSD_MEM_SPACE_EL2S = 0x10, /**< S EL2 */
+ OCSD_MEM_SPACE_S = 0x19, /**< Any S */
OCSD_MEM_SPACE_N = 0x6, /**< Any NS */
- OCSD_MEM_SPACE_ANY = 0xF, /**< Any sec level / EL - live system use current EL + sec state */
+ OCSD_MEM_SPACE_ANY = 0x1F, /**< Any sec level / EL - live system use current EL + sec state */
} ocsd_mem_space_acc_t;
/**
@@ -494,13 +495,14 @@ typedef struct _ocsd_file_mem_region {
/** @name Packet Processor Operation Control Flags
common operational flags - bottom 16 bits,
- component specific - top 16 bits.
+ protocol component specific - top 16 bits.
+ (common flags share bitfield with pkt decoder common flags and create flags)
@{*/
-#define OCSD_OPFLG_PKTPROC_NOFWD_BAD_PKTS 0x00000001 /**< don't forward bad packets up data path */
-#define OCSD_OPFLG_PKTPROC_NOMON_BAD_PKTS 0x00000002 /**< don't forward bad packets to monitor interface */
-#define OCSD_OPFLG_PKTPROC_ERR_BAD_PKTS 0x00000004 /**< throw error for bad packets - halt decoding. */
-#define OCSD_OPFLG_PKTPROC_UNSYNC_ON_BAD_PKTS 0x00000008 /**< switch to unsynced state on bad packets - wait for next sync point */
+#define OCSD_OPFLG_PKTPROC_NOFWD_BAD_PKTS 0x00000010 /**< don't forward bad packets up data path */
+#define OCSD_OPFLG_PKTPROC_NOMON_BAD_PKTS 0x00000020 /**< don't forward bad packets to monitor interface */
+#define OCSD_OPFLG_PKTPROC_ERR_BAD_PKTS 0x00000040 /**< throw error for bad packets - halt decoding. */
+#define OCSD_OPFLG_PKTPROC_UNSYNC_ON_BAD_PKTS 0x00000080 /**< switch to unsynced state on bad packets - wait for next sync point */
/** mask to combine all common packet processor operational control flags */
#define OCSD_OPFLG_PKTPROC_COMMON (OCSD_OPFLG_PKTPROC_NOFWD_BAD_PKTS | \
@@ -508,14 +510,18 @@ typedef struct _ocsd_file_mem_region {
OCSD_OPFLG_PKTPROC_ERR_BAD_PKTS | \
OCSD_OPFLG_PKTPROC_UNSYNC_ON_BAD_PKTS )
+/** mask for the component spcific flags */
+#define OCSD_OPFLG_COMP_MODE_MASK 0xFFFF0000
+
/** @}*/
/** @name Packet Decoder Operation Control Flags
common operational flags - bottom 16 bits,
- component specific - top 16 bits.
-@{*/
+ protcol component specific - top 16 bits.
+ (common flags share bitfield with pkt processor common flags and create flags)
+ @{*/
-#define OCSD_OPFLG_PKTDEC_ERROR_BAD_PKTS 0x00000001 /**< throw error on bad packets input (default is to unsync and wait) */
+#define OCSD_OPFLG_PKTDEC_ERROR_BAD_PKTS 0x00000100 /**< throw error on bad packets input (default is to unsync and wait) */
/** mask to combine all common packet processor operational control flags */
#define OCSD_OPFLG_PKTDEC_COMMON (OCSD_OPFLG_PKTDEC_ERROR_BAD_PKTS)
@@ -524,7 +530,8 @@ typedef struct _ocsd_file_mem_region {
/** @name Decoder creation information
- Flags to use when creating decoders by name
+ Flags to use when creating decoders by name.
+ - share bitfield with pkt processor flags and packet decoder common flags.
Builtin decoder names.
diff --git a/decoder/include/opencsd/ocsd_if_version.h b/decoder/include/opencsd/ocsd_if_version.h
index 70c8df41f52b..38baa02e8b48 100644
--- a/decoder/include/opencsd/ocsd_if_version.h
+++ b/decoder/include/opencsd/ocsd_if_version.h
@@ -43,8 +43,8 @@
/** @name Library Versioning
@{*/
#define OCSD_VER_MAJOR 0x0 /**< Library Major Version */
-#define OCSD_VER_MINOR 0xC /**< Library Minor Version */
-#define OCSD_VER_PATCH 0x0 /**< Library Patch Version */
+#define OCSD_VER_MINOR 0xE /**< Library Minor Version */
+#define OCSD_VER_PATCH 0x2 /**< Library Patch Version */
/** Library version number - MMMMnnpp format.
MMMM = major version,
@@ -53,7 +53,7 @@
*/
#define OCSD_VER_NUM ((OCSD_VER_MAJOR << 16) | (OCSD_VER_MINOR << 8) | OCSD_VER_PATCH)
-#define OCSD_VER_STRING "0.12.0" /**< Library Version string */
+#define OCSD_VER_STRING "0.14.2" /**< Library Version string */
#define OCSD_LIB_NAME "OpenCSD Library" /**< Library name string */
#define OCSD_LIB_SHORT_NAME "OCSD" /**< Library Short name string */
/** @}*/
diff --git a/decoder/include/opencsd/ptm/trc_pkt_decode_ptm.h b/decoder/include/opencsd/ptm/trc_pkt_decode_ptm.h
index 395b316cda06..f9e1abe4ebc3 100644
--- a/decoder/include/opencsd/ptm/trc_pkt_decode_ptm.h
+++ b/decoder/include/opencsd/ptm/trc_pkt_decode_ptm.h
@@ -154,6 +154,7 @@ private:
} processor_state_t;
processor_state_t m_curr_state;
+ unsync_info_t m_unsync_info;
const bool processStateIsCont() const;
diff --git a/decoder/include/opencsd/stm/trc_pkt_decode_stm.h b/decoder/include/opencsd/stm/trc_pkt_decode_stm.h
index a4807207eb1e..bd29cafa799f 100644
--- a/decoder/include/opencsd/stm/trc_pkt_decode_stm.h
+++ b/decoder/include/opencsd/stm/trc_pkt_decode_stm.h
@@ -79,6 +79,7 @@ private:
} processor_state_t;
processor_state_t m_curr_state;
+ unsync_info_t m_unsync_info;
ocsd_swt_info_t m_swt_packet_info;
diff --git a/decoder/include/opencsd/trc_gen_elem_types.h b/decoder/include/opencsd/trc_gen_elem_types.h
index 1d77b53cf8f9..1a285a064b63 100644
--- a/decoder/include/opencsd/trc_gen_elem_types.h
+++ b/decoder/include/opencsd/trc_gen_elem_types.h
@@ -52,6 +52,7 @@ typedef enum _ocsd_gen_trc_elem_t
OCSD_GEN_TRC_ELEM_EO_TRACE, /*!< end of the available trace in the buffer. */
OCSD_GEN_TRC_ELEM_PE_CONTEXT, /*!< PE status update / change (arch, ctxtid, vmid etc). */
OCSD_GEN_TRC_ELEM_INSTR_RANGE, /*!< traced N consecutive instructions from addr (no intervening events or data elements), may have data assoc key */
+ OCSD_GEN_TRC_ELEM_I_RANGE_NOPATH, /*!< traced N instructions in a range, but incomplete information as to program execution path from start to end of range */
OCSD_GEN_TRC_ELEM_ADDR_NACC, /*!< tracing in inaccessible memory area */
OCSD_GEN_TRC_ELEM_ADDR_UNKNOWN, /*!< address currently unknown - need address packet update */
OCSD_GEN_TRC_ELEM_EXCEPTION, /*!< exception - start address may be exception target, end address may be preferred ret addr. */
@@ -75,6 +76,16 @@ typedef struct _trace_event_t {
uint16_t ev_number; /**< event number if numbered event type */
} trace_event_t;
+typedef enum _unsync_info_t {
+ UNSYNC_UNKNOWN, /**< unknown /undefined */
+ UNSYNC_INIT_DECODER, /**< decoder intialisation - start of trace. */
+ UNSYNC_RESET_DECODER, /**< decoder reset. */
+ UNSYNC_OVERFLOW, /**< overflow packet - need to re-sync / end of trace after overflow. */
+ UNSYNC_DISCARD, /**< specl trace discard - need to re-sync. */
+ UNSYNC_BAD_PACKET, /**< bad packet at input - resync to restart. */
+ UNSYNC_EOT, /**< end of trace - no additional info */
+} unsync_info_t;
+
typedef struct _ocsd_generic_trace_elem {
ocsd_gen_trc_elem_t elem_type; /**< Element type - remaining data interpreted according to this value */
ocsd_isa isa; /**< instruction set for executed instructions */
@@ -110,6 +121,7 @@ typedef struct _ocsd_generic_trace_elem {
trace_on_reason_t trace_on_reason; /**< reason for the trace on packet */
ocsd_swt_info_t sw_trace_info; /**< software trace packet info */
uint32_t num_instr_range; /**< number of instructions covered by range packet (for T32 this cannot be calculated from en-st/i_size) */
+ unsync_info_t unsync_eot_info; /**< additional information for unsync / end-of-trace packets. */
};
const void *ptr_extended_data; /**< pointer to extended data buffer (data trace, sw trace payload) / custom structure */
diff --git a/decoder/include/pkt_printers/pkt_printer_t.h b/decoder/include/pkt_printers/pkt_printer_t.h
index 9eb37f4e2833..c00daa1f64d3 100644
--- a/decoder/include/pkt_printers/pkt_printer_t.h
+++ b/decoder/include/pkt_printers/pkt_printer_t.h
@@ -102,7 +102,7 @@ template<class P> ocsd_datapath_resp_t PacketPrinter<P>::PacketDataIn( const ocs
if(!m_bRawPrint && (m_last_resp == OCSD_RESP_WAIT))
{
// expect a flush or a complete reset after a wait.
- if((op != OCSD_OP_FLUSH) || (op != OCSD_OP_RESET))
+ if((op != OCSD_OP_FLUSH) && (op != OCSD_OP_RESET))
{
m_oss <<"ID:"<< std::hex << (uint32_t)m_trcID << "\tERROR: FLUSH operation expected after wait on trace decode path\n";
itemPrintLine(m_oss.str());
diff --git a/decoder/source/etmv3/trc_pkt_decode_etmv3.cpp b/decoder/source/etmv3/trc_pkt_decode_etmv3.cpp
index 0a15a33c42fb..e68a73fd9e0d 100644
--- a/decoder/source/etmv3/trc_pkt_decode_etmv3.cpp
+++ b/decoder/source/etmv3/trc_pkt_decode_etmv3.cpp
@@ -130,6 +130,7 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV3::onEOT()
try {
pElem = GetNextOpElem(resp);
pElem->setType(OCSD_GEN_TRC_ELEM_EO_TRACE);
+ pElem->setUnSyncEOTReason(UNSYNC_EOT);
m_outputElemList.commitAllPendElem();
m_curr_state = SEND_PKTS;
resp = m_outputElemList.sendElements();
@@ -147,6 +148,7 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV3::onEOT()
ocsd_datapath_resp_t TrcPktDecodeEtmV3::onReset()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ m_unsync_info = UNSYNC_RESET_DECODER;
resetDecoder();
return resp;
}
@@ -199,6 +201,7 @@ void TrcPktDecodeEtmV3::initDecoder()
{
m_CSID = 0;
resetDecoder();
+ m_unsync_info = UNSYNC_INIT_DECODER;
m_code_follower.initInterfaces(getMemoryAccessAttachPt(),getInstrDecodeAttachPt());
m_outputElemList.initSendIf(getTraceElemOutAttachPt());
}
@@ -355,6 +358,7 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV3::decodePacket(bool &pktDone)
catch(ocsdError &err)
{
LogError(err);
+ m_unsync_info = UNSYNC_BAD_PACKET;
resetDecoder(); // mark decoder as unsynced - dump any current state.
pktDone = true;
}
@@ -362,6 +366,7 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV3::decodePacket(bool &pktDone)
{
LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_FAIL,m_index_curr_pkt,m_CSID,"Bad Packet sequence."));
resp = OCSD_RESP_FATAL_SYS_ERR;
+ m_unsync_info = UNSYNC_BAD_PACKET;
resetDecoder(); // mark decoder as unsynced - dump any current state.
pktDone = true;
}
@@ -375,11 +380,13 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV3::sendUnsyncPacket()
try {
pElem = GetNextOpElem(resp);
pElem->setType(OCSD_GEN_TRC_ELEM_NO_SYNC);
+ pElem->setUnSyncEOTReason(m_unsync_info);
resp = m_outputElemList.sendElements();
}
catch(ocsdError &err)
{
LogError(err);
+ m_unsync_info = UNSYNC_BAD_PACKET;
resetDecoder(); // mark decoder as unsynced - dump any current state.
}
return resp;
@@ -464,6 +471,7 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV3::processISync(const bool withCC, const bo
catch(ocsdError &err)
{
LogError(err);
+ m_unsync_info = UNSYNC_BAD_PACKET;
resetDecoder(); // mark decoder as unsynced - dump any current state.
}
return resp;
@@ -531,6 +539,7 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV3::processBranchAddr()
catch(ocsdError &err)
{
LogError(err);
+ m_unsync_info = UNSYNC_BAD_PACKET;
resetDecoder(); // mark decoder as unsynced - dump any current state.
}
}
@@ -647,6 +656,7 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV3::processPHdr()
catch(ocsdError &err)
{
LogError(err);
+ m_unsync_info = UNSYNC_BAD_PACKET;
resetDecoder(); // mark decoder as unsynced - dump any current state.
}
return resp;
diff --git a/decoder/source/etmv4/trc_etmv4_stack_elem.cpp b/decoder/source/etmv4/trc_etmv4_stack_elem.cpp
index 8916c7dc350d..8e9ba9ac43ca 100644
--- a/decoder/source/etmv4/trc_etmv4_stack_elem.cpp
+++ b/decoder/source/etmv4/trc_etmv4_stack_elem.cpp
@@ -90,13 +90,17 @@ TrcStackElemExcept *EtmV4P0Stack::createExceptElem(const ocsd_etmv4_i_pkt_type r
return pElem;
}
-TrcStackElemCtxt *EtmV4P0Stack::createContextElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, const etmv4_context_t &context)
+TrcStackElemCtxt *EtmV4P0Stack::createContextElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, const etmv4_context_t &context, const uint8_t IS, const bool back /*= false*/)
{
TrcStackElemCtxt *pElem = new (std::nothrow) TrcStackElemCtxt(root_pkt, root_index);
if (pElem)
{
pElem->setContext(context);
- push_front(pElem);
+ pElem->setIS(IS);
+ if (back)
+ push_back(pElem);
+ else
+ push_front(pElem);
}
return pElem;
@@ -113,4 +117,40 @@ TrcStackElemAddr *EtmV4P0Stack::createAddrElem(const ocsd_etmv4_i_pkt_type root_
return pElem;
}
+TrcStackQElem *EtmV4P0Stack::createQElem(const ocsd_etmv4_i_pkt_type root_pkt, const ocsd_trc_index_t root_index, const int count)
+{
+ TrcStackQElem *pElem = new (std::nothrow) TrcStackQElem(root_pkt, root_index);
+ if (pElem)
+ {
+ pElem->setInstrCount(count);
+ push_front(pElem);
+ }
+ return pElem;
+}
+
+// iteration functions
+void EtmV4P0Stack::from_front_init()
+{
+ m_iter = m_P0_stack.begin();
+}
+
+TrcStackElem *EtmV4P0Stack::from_front_next()
+{
+ TrcStackElem *pElem = 0;
+ if (m_iter != m_P0_stack.end())
+ {
+ pElem = *m_iter++;
+ }
+ return pElem;
+}
+
+void EtmV4P0Stack::erase_curr_from_front()
+{
+ std::deque<TrcStackElem *>::iterator erase_iter;
+ erase_iter = m_iter;
+ erase_iter--;
+ m_P0_stack.erase(erase_iter);
+}
+
+
/* End of file trc_etmv4_stack_elem.cpp */
diff --git a/decoder/source/etmv4/trc_pkt_decode_etmv4i.cpp b/decoder/source/etmv4/trc_pkt_decode_etmv4i.cpp
index 2eb6cbc3f5bf..393046ba23d1 100644
--- a/decoder/source/etmv4/trc_pkt_decode_etmv4i.cpp
+++ b/decoder/source/etmv4/trc_pkt_decode_etmv4i.cpp
@@ -5,7 +5,6 @@
* \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
*/
-
/*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,6 +62,7 @@ TrcPktDecodeEtmV4I::~TrcPktDecodeEtmV4I()
ocsd_datapath_resp_t TrcPktDecodeEtmV4I::processPacket()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ ocsd_err_t err = OCSD_OK;
bool bPktDone = false;
while(!bPktDone)
@@ -71,9 +71,18 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::processPacket()
{
case NO_SYNC:
// output the initial not synced packet to the sink
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_NO_SYNC);
- resp = outputTraceElement(m_output_elem);
- m_curr_state = WAIT_SYNC;
+ err = m_out_elem.resetElemStack();
+ if (!err)
+ err = m_out_elem.addElemType(m_index_curr_pkt, OCSD_GEN_TRC_ELEM_NO_SYNC);
+ if (!err)
+ {
+ outElem().setUnSyncEOTReason(m_unsync_eot_info);
+ resp = m_out_elem.sendElements();
+ m_curr_state = WAIT_SYNC;
+ }
+ else
+ resp = OCSD_RESP_FATAL_SYS_ERR;
+
// fall through to check if the current packet is the async we are waiting for.
break;
@@ -96,13 +105,31 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::processPacket()
break;
case DECODE_PKTS:
- resp = decodePacket(bPktDone); // this may change the state to commit elem;
- break;
+ // this may change the state to RESOLVE_ELEM if required;
+ err = decodePacket();
+ if (err)
+ {
+#ifdef OCSD_WARN_UNSUPPORTED
+ if (err == OCSD_ERR_UNSUPP_DECODE_PKT)
+ resp = OCSD_RESP_WARN_CONT;
+ else
+#else
+ resp = OCSD_RESP_FATAL_INVALID_DATA;
+#endif
- case COMMIT_ELEM:
- resp = commitElements(bPktDone); // this will change the state to DECODE_PKTS once all elem committed.
+ bPktDone = true;
+ }
+ else if (m_curr_state != RESOLVE_ELEM)
+ bPktDone = true;
break;
+ case RESOLVE_ELEM:
+ // this will change the state to DECODE_PKTS once required elem resolved &
+ // needed generic packets output
+ resp = resolveElements();
+ if ((m_curr_state == DECODE_PKTS) || (!OCSD_DATA_RESP_IS_CONT(resp)))
+ bPktDone = true;
+ break;
}
}
return resp;
@@ -111,14 +138,21 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::processPacket()
ocsd_datapath_resp_t TrcPktDecodeEtmV4I::onEOT()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
- m_flush_EOT = true;
- resp = flushEOT();
+ ocsd_err_t err;
+ if ((err = commitElemOnEOT()) != OCSD_OK)
+ {
+ resp = OCSD_RESP_FATAL_INVALID_DATA;
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR, err, "Error flushing element stack at end of trace data."));
+ }
+ else
+ resp = m_out_elem.sendElements();
return resp;
}
ocsd_datapath_resp_t TrcPktDecodeEtmV4I::onReset()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ m_unsync_eot_info = UNSYNC_RESET_DECODER;
resetDecoder();
return resp;
}
@@ -127,15 +161,10 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::onFlush()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
- // continue exception processing (can't go through processPacket as elements no longer on stack)
- if(m_excep_info.proc != EXCEP_POP)
- resp = processException();
- // continue ongoing output operations on comitted elements.
- else if(m_curr_state == COMMIT_ELEM)
- resp = processPacket();
- // continue flushing at end of trace
- else if(m_flush_EOT)
- resp = flushEOT();
+ if (m_curr_state == RESOLVE_ELEM)
+ resp = resolveElements();
+ else
+ resp = m_out_elem.sendElements();
return resp;
}
@@ -146,8 +175,14 @@ ocsd_err_t TrcPktDecodeEtmV4I::onProtocolConfig()
// set some static config elements
m_CSID = m_config->getTraceID();
m_max_spec_depth = m_config->MaxSpecDepth();
+
+ // elements associated with data trace
+#ifdef DATA_TRACE_SUPPORTED
m_p0_key_max = m_config->P0_Key_Max();
m_cond_key_max_incr = m_config->CondKeyMaxIncr();
+#endif
+
+ m_out_elem.initCSID(m_CSID);
// set up static trace instruction decode elements
m_instr_info.dsb_dmb_waypoints = 0;
@@ -168,12 +203,7 @@ ocsd_err_t TrcPktDecodeEtmV4I::onProtocolConfig()
// check config compatible with current decoder support level.
// at present no data trace, no spec depth, no return stack, no QE
// Remove these checks as support is added.
- if(m_max_spec_depth != 0)
- {
- err = OCSD_ERR_HW_CFG_UNSUPP;
- LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_HW_CFG_UNSUPP,"ETMv4 instruction decode : None-zero speculation depth not supported"));
- }
- else if(m_config->enabledDataTrace())
+ if(m_config->enabledDataTrace())
{
err = OCSD_ERR_HW_CFG_UNSUPP;
LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_HW_CFG_UNSUPP,"ETMv4 instruction decode : Data trace elements not supported"));
@@ -188,15 +218,9 @@ ocsd_err_t TrcPktDecodeEtmV4I::onProtocolConfig()
err = OCSD_ERR_HW_CFG_UNSUPP;
LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_HW_CFG_UNSUPP,"ETMv4 instruction decode : Trace on conditional non-branch elements not supported."));
}
- else if(m_config->enabledQE())
- {
- err = OCSD_ERR_HW_CFG_UNSUPP;
- LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_HW_CFG_UNSUPP,"ETMv4 instruction decode : Trace using Q elements not supported."));
- }
return err;
}
-
/************* local decode methods */
void TrcPktDecodeEtmV4I::initDecoder()
{
@@ -205,12 +229,17 @@ void TrcPktDecodeEtmV4I::initDecoder()
/* init elements that get set by config */
m_max_spec_depth = 0;
- m_p0_key_max = 0;
m_CSID = 0;
- m_cond_key_max_incr = 0;
m_IASize64 = false;
+ // elements associated with data trace
+#ifdef DATA_TRACE_SUPPORTED
+ m_p0_key_max = 0;
+ m_cond_key_max_incr = 0;
+#endif
+
// reset decoder state to unsynced
+ m_unsync_eot_info = UNSYNC_INIT_DECODER;
resetDecoder();
}
@@ -224,30 +253,36 @@ void TrcPktDecodeEtmV4I::resetDecoder()
m_is_64bit = false;
m_cc_threshold = 0;
m_curr_spec_depth = 0;
- m_p0_key = 0;
- m_cond_c_key = 0;
- m_cond_r_key = 0;
m_need_ctxt = true;
m_need_addr = true;
- m_except_pending_addr = false;
- m_mem_nacc_pending = false;
+ m_elem_pending_addr = false;
m_prev_overflow = false;
m_P0_stack.delete_all();
- m_output_elem.init();
- m_excep_info.proc = EXCEP_POP;
- m_flush_EOT = false;
+ m_out_elem.resetElemStack();
+ m_last_IS = 0;
+ clearElemRes();
+
+ // elements associated with data trace
+#ifdef DATA_TRACE_SUPPORTED
+ m_p0_key = 0;
+ m_cond_c_key = 0;
+ m_cond_r_key = 0;
+#endif
+}
+
+void TrcPktDecodeEtmV4I::onFirstInitOK()
+{
+ // once init, set the output element interface to the out elem list.
+ m_out_elem.initSendIf(this->getTraceElemOutAttachPt());
}
-// this function can output an immediate generic element if this covers the complete packet decode,
-// or stack P0 and other elements for later processing on commit or cancel.
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::decodePacket(bool &Complete)
+// Changes a packet into stack of trace elements - these will be resolved and output later
+ocsd_err_t TrcPktDecodeEtmV4I::decodePacket()
{
+ ocsd_err_t err = OCSD_OK;
bool bAllocErr = false;
- ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
- Complete = true;
bool is_addr = false;
- bool is_except = false;
-
+
switch(m_curr_packet_in->getType())
{
case ETM4_PKT_I_ASYNC: // nothing to do with this packet.
@@ -266,13 +301,6 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::decodePacket(bool &Complete)
}
break;
- case ETM4_PKT_I_OVERFLOW:
- {
- if (m_P0_stack.createParamElemNoParam(P0_OVERFLOW, false, m_curr_packet_in->getType(), m_index_curr_pkt) == 0)
- bAllocErr = true;
- }
- break;
-
case ETM4_PKT_I_ATOM_F1:
case ETM4_PKT_I_ATOM_F2:
case ETM4_PKT_I_ATOM_F3:
@@ -289,7 +317,7 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::decodePacket(bool &Complete)
case ETM4_PKT_I_CTXT:
{
- if (m_P0_stack.createContextElem(m_curr_packet_in->getType(), m_index_curr_pkt, m_curr_packet_in->getContext()) == 0)
+ if (m_P0_stack.createContextElem(m_curr_packet_in->getType(), m_index_curr_pkt, m_curr_packet_in->getContext(), m_last_IS) == 0)
bAllocErr = true;
}
break;
@@ -299,7 +327,8 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::decodePacket(bool &Complete)
etmv4_addr_val_t addr;
addr.val = m_curr_packet_in->getAddrVal();
- addr.isa = m_curr_packet_in->getAddrIS();
+ addr.isa = m_last_IS = m_curr_packet_in->getAddrIS();
+
if (m_P0_stack.createAddrElem(m_curr_packet_in->getType(), m_index_curr_pkt, addr) == 0)
bAllocErr = true;
is_addr = true;
@@ -311,7 +340,8 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::decodePacket(bool &Complete)
case ETM4_PKT_I_ADDR_CTXT_L_32IS0:
case ETM4_PKT_I_ADDR_CTXT_L_32IS1:
{
- if (m_P0_stack.createContextElem(m_curr_packet_in->getType(), m_index_curr_pkt, m_curr_packet_in->getContext()) == 0)
+ m_last_IS = m_curr_packet_in->getAddrIS();
+ if (m_P0_stack.createContextElem(m_curr_packet_in->getType(), m_index_curr_pkt, m_curr_packet_in->getContext(), m_last_IS) == 0)
bAllocErr = true;
}
case ETM4_PKT_I_ADDR_L_32IS0:
@@ -324,7 +354,8 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::decodePacket(bool &Complete)
etmv4_addr_val_t addr;
addr.val = m_curr_packet_in->getAddrVal();
- addr.isa = m_curr_packet_in->getAddrIS();
+ addr.isa = m_last_IS = m_curr_packet_in->getAddrIS();
+
if (m_P0_stack.createAddrElem(m_curr_packet_in->getType(), m_index_curr_pkt, addr) == 0)
bAllocErr = true;
is_addr = true;
@@ -339,10 +370,7 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::decodePacket(bool &Complete)
m_curr_packet_in->exception_info.exceptionType) == 0)
bAllocErr = true;
else
- {
- m_except_pending_addr = true; // wait for following packets before marking for commit.
- is_except = true;
- }
+ m_elem_pending_addr = true; // wait for following packets before marking for commit.
}
break;
@@ -411,15 +439,67 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::decodePacket(bool &Complete)
break;
case ETM4_PKT_I_BAD_SEQUENCE:
- resp = handleBadPacket("Bad byte sequence in packet.");
+ err = handleBadPacket("Bad byte sequence in packet.");
break;
case ETM4_PKT_I_BAD_TRACEMODE:
- resp = handleBadPacket("Invalid packet type for trace mode.");
+ err = handleBadPacket("Invalid packet type for trace mode.");
break;
case ETM4_PKT_I_RESERVED:
- resp = handleBadPacket("Reserved packet header");
+ err = handleBadPacket("Reserved packet header");
+ break;
+
+ // speculation
+ case ETM4_PKT_I_MISPREDICT:
+ case ETM4_PKT_I_CANCEL_F1_MISPRED:
+ case ETM4_PKT_I_CANCEL_F2:
+ case ETM4_PKT_I_CANCEL_F3:
+ m_elem_res.mispredict = true;
+ if (m_curr_packet_in->getNumAtoms())
+ {
+ if (m_P0_stack.createAtomElem(m_curr_packet_in->getType(), m_index_curr_pkt, m_curr_packet_in->getAtom()) == 0)
+ bAllocErr = true;
+ else
+ m_curr_spec_depth += m_curr_packet_in->getNumAtoms();
+ }
+
+ case ETM4_PKT_I_CANCEL_F1:
+ m_elem_res.P0_cancel = m_curr_packet_in->getCancelElem();
+ break;
+
+ case ETM4_PKT_I_COMMIT:
+ m_elem_res.P0_commit = m_curr_packet_in->getCommitElem();
+ break;
+
+ case ETM4_PKT_I_OVERFLOW:
+ m_prev_overflow = true;
+ case ETM4_PKT_I_DISCARD:
+ m_curr_spec_depth = 0;
+ m_elem_res.discard = true;
+ break;
+
+ /* Q packets */
+ case ETM4_PKT_I_Q:
+ {
+ TrcStackQElem *pQElem = m_P0_stack.createQElem(m_curr_packet_in->getType(), m_index_curr_pkt, m_curr_packet_in->Q_pkt.q_count);
+ if (pQElem)
+ {
+ if (m_curr_packet_in->Q_pkt.addr_present)
+ {
+ etmv4_addr_val_t addr;
+
+ addr.val = m_curr_packet_in->getAddrVal();
+ addr.isa = m_curr_packet_in->getAddrIS();
+ pQElem->setAddr(addr);
+ m_curr_spec_depth++;
+ }
+ else
+ m_elem_pending_addr = true;
+ }
+ else
+ bAllocErr = true;
+ }
break;
/*** presently unsupported packets ***/
@@ -432,90 +512,134 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::decodePacket(bool &Complete)
case ETM4_PKT_I_COND_RES_F2:
case ETM4_PKT_I_COND_RES_F3:
case ETM4_PKT_I_COND_RES_F4:
- // speculation
- case ETM4_PKT_I_CANCEL_F1:
- case ETM4_PKT_I_CANCEL_F2:
- case ETM4_PKT_I_CANCEL_F3:
- case ETM4_PKT_I_COMMIT:
- case ETM4_PKT_I_MISPREDICT:
- case ETM4_PKT_I_DISCARD:
// data synchronisation markers
case ETM4_PKT_I_NUM_DS_MKR:
case ETM4_PKT_I_UNNUM_DS_MKR:
- /* Q packets */
- case ETM4_PKT_I_Q:
- resp = OCSD_RESP_FATAL_INVALID_DATA;
- LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_BAD_DECODE_PKT,"Unsupported packet type."));
+ // all currently unsupported
+ {
+ ocsd_err_severity_t sev = OCSD_ERR_SEV_ERROR;
+#ifdef OCSD_WARN_UNSUPPORTED
+ sev = OCSD_ERR_SEV_WARN;
+ //resp = OCSD_RESP_WARN_CONT;
+#else
+ //resp = OCSD_RESP_FATAL_INVALID_DATA;
+#endif
+ err = OCSD_ERR_UNSUPP_DECODE_PKT;
+ LogError(ocsdError(sev, err, "Data trace releated, unsupported packet type."));
+ }
break;
default:
// any other packet - bad packet error
- resp = OCSD_RESP_FATAL_INVALID_DATA;
- LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_BAD_DECODE_PKT,"Unknown packet type."));
+ err = OCSD_ERR_BAD_DECODE_PKT;
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR,err,"Unknown packet type."));
break;
-
}
- // we need to wait for following address after exception
+ // we need to wait for following address after certain packets
// - work out if we have seen enough here...
- if(m_except_pending_addr && !is_except)
+ if (is_addr && m_elem_pending_addr)
{
- m_except_pending_addr = false; //next packet has to be an address
- // exception packet sequence complete
- if(is_addr)
- {
- m_curr_spec_depth++; // exceptions are P0 elements so up the spec depth to commit if needed.
- }
- else
- {
- resp = OCSD_RESP_FATAL_INVALID_DATA;
- LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_BAD_DECODE_PKT,"Expected Address packet to follow exception packet."));
- }
+ m_curr_spec_depth++; // increase spec depth for element waiting on address.
+ m_elem_pending_addr = false; // can't be waiting on both
}
if(bAllocErr)
{
- resp = OCSD_RESP_FATAL_SYS_ERR;
+ err = OCSD_ERR_MEM;
LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_MEM,"Memory allocation error."));
}
else if(m_curr_spec_depth > m_max_spec_depth)
{
// auto commit anything above max spec depth
// (this will auto commit anything if spec depth not supported!)
- m_P0_commit = m_curr_spec_depth - m_max_spec_depth;
- m_curr_state = COMMIT_ELEM;
- Complete = false; // force the processing of the commit elements.
+ m_elem_res.P0_commit = m_curr_spec_depth - m_max_spec_depth;
}
- return resp;
+
+ if (!err && isElemForRes())
+ m_curr_state = RESOLVE_ELEM;
+ return err;
}
void TrcPktDecodeEtmV4I::doTraceInfoPacket()
{
m_trace_info = m_curr_packet_in->getTraceInfo();
m_cc_threshold = m_curr_packet_in->getCCThreshold();
- m_p0_key = m_curr_packet_in->getP0Key();
m_curr_spec_depth = m_curr_packet_in->getCurrSpecDepth();
+
+ // elements associated with data trace
+#ifdef DATA_TRACE_SUPPORTED
+ m_p0_key = m_curr_packet_in->getP0Key();
+#endif
+}
+
+/* Element resolution
+ * Commit or cancel elements as required
+ * Send any buffered output packets.
+ */
+ocsd_datapath_resp_t TrcPktDecodeEtmV4I::resolveElements()
+{
+ ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ bool Complete = false;
+
+ while (!Complete)
+ {
+ if (m_out_elem.numElemToSend())
+ resp = m_out_elem.sendElements();
+ else if (isElemForRes())
+ {
+ ocsd_err_t err = OCSD_OK;
+ if (m_elem_res.P0_commit)
+ err = commitElements();
+
+ if (!err && m_elem_res.P0_cancel)
+ err = cancelElements();
+
+ if (!err && m_elem_res.mispredict)
+ err = mispredictAtom();
+
+ if (!err && m_elem_res.discard)
+ err = discardElements();
+
+ if (err != OCSD_OK)
+ resp = OCSD_RESP_FATAL_INVALID_DATA;
+ }
+
+ // break out on error or wait request.
+ if (!OCSD_DATA_RESP_IS_CONT(resp))
+ break;
+
+ // completion is nothing to send and nothing to commit
+ Complete = !m_out_elem.numElemToSend() && !isElemForRes();
+
+ // done all elements - need more packets.
+ if (Complete) {
+ // if we are still in resolve, the goto decode.
+ if (m_curr_state == RESOLVE_ELEM)
+ m_curr_state = DECODE_PKTS;
+ }
+ }
+ return resp;
}
/*
* Walks through the element stack, processing from oldest element to the newest,
according to the number of P0 elements that need committing.
+ Build a stack of output elements in the process.
*/
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::commitElements(bool &Complete)
+ocsd_err_t TrcPktDecodeEtmV4I::commitElements()
{
- ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
- bool bPause = false; // pause commit operation
+ ocsd_err_t err = OCSD_OK;
bool bPopElem = true; // do we remove the element from the stack (multi atom elements may need to stay!)
- int num_commit_req = m_P0_commit;
+ int num_commit_req = m_elem_res.P0_commit;
ocsd_trc_index_t err_idx = 0;
-
- Complete = true; // assume we exit due to completion of commit operation
-
TrcStackElem *pElem = 0; // stacked element pointer
- while(m_P0_commit && !bPause)
+ err = m_out_elem.resetElemStack();
+
+ while(m_elem_res.P0_commit && !err)
{
- if(m_P0_stack.size() > 0)
+ if (m_P0_stack.size() > 0)
{
pElem = m_P0_stack.back(); // get oldest element
err_idx = pElem->getRootIndex(); // save index in case of error.
@@ -524,11 +648,13 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::commitElements(bool &Complete)
{
// indicates a trace restart - beginning of trace or discontinuiuty
case P0_TRC_ON:
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_TRACE_ON);
- m_output_elem.trace_on_reason = m_prev_overflow ? TRACE_ON_OVERFLOW : TRACE_ON_NORMAL;
- m_prev_overflow = false;
- resp = outputTraceElementIdx(pElem->getRootIndex(),m_output_elem);
- m_return_stack.flush();
+ err = m_out_elem.addElemType(pElem->getRootIndex(), OCSD_GEN_TRC_ELEM_TRACE_ON);
+ if (!err)
+ {
+ m_out_elem.getCurrElem().trace_on_reason = m_prev_overflow ? TRACE_ON_OVERFLOW : TRACE_ON_NORMAL;
+ m_prev_overflow = false;
+ m_return_stack.flush();
+ }
break;
case P0_ADDR:
@@ -551,50 +677,20 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::commitElements(bool &Complete)
etmv4_context_t ctxt = pCtxtElem->getContext();
// check this is an updated context
if(ctxt.updated)
- {
- updateContext(pCtxtElem);
-
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_PE_CONTEXT);
- resp = outputTraceElementIdx(pElem->getRootIndex(),m_output_elem);
+ {
+ err = m_out_elem.addElem(pElem->getRootIndex());
+ if (!err)
+ updateContext(pCtxtElem, outElem());
}
}
}
break;
case P0_EVENT:
- {
- TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
- if(pParamElem)
- resp = this->outputEvent(pParamElem);
- }
- break;
-
case P0_TS:
- {
- TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
- if(pParamElem)
- resp = outputTS(pParamElem,false);
- }
- break;
-
case P0_CC:
- {
- TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
- if(pParamElem)
- resp = outputCC(pParamElem);
- }
- break;
-
case P0_TS_CC:
- {
- TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
- if(pParamElem)
- resp = outputTS(pParamElem,true);
- }
- break;
-
- case P0_OVERFLOW:
- m_prev_overflow = true;
+ err = processTS_CC_EventElem(pElem);
break;
case P0_ATOM:
@@ -603,22 +699,21 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::commitElements(bool &Complete)
if(pAtomElem)
{
- bool bContProcess = true;
- while(!pAtomElem->isEmpty() && m_P0_commit && bContProcess)
+ while(!pAtomElem->isEmpty() && m_elem_res.P0_commit && !err)
{
ocsd_atm_val atom = pAtomElem->commitOldest();
// check if prev atom left us an indirect address target on the return stack
- if ((resp = returnStackPop()) != OCSD_RESP_CONT)
+ if ((err = returnStackPop()) != OCSD_OK)
break;
// if address and context do instruction trace follower.
// otherwise skip atom and reduce committed elements
if(!m_need_ctxt && !m_need_addr)
{
- resp = processAtom(atom,bContProcess);
+ err = processAtom(atom);
}
- m_P0_commit--; // mark committed
+ m_elem_res.P0_commit--; // mark committed
}
if(!pAtomElem->isEmpty())
bPopElem = false; // don't remove if still atoms to process.
@@ -628,68 +723,63 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::commitElements(bool &Complete)
case P0_EXCEP:
// check if prev atom left us an indirect address target on the return stack
- if ((resp = returnStackPop()) != OCSD_RESP_CONT)
+ if ((err = returnStackPop()) != OCSD_OK)
break;
- m_excep_info.proc = EXCEP_POP; // set state in case we need to stop part way through
- resp = processException(); // output trace + exception elements.
- m_P0_commit--;
+ err = processException(); // output trace + exception elements.
+ m_elem_res.P0_commit--;
break;
case P0_EXCEP_RET:
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_EXCEPTION_RET);
- resp = outputTraceElementIdx(pElem->getRootIndex(),m_output_elem);
- if(pElem->isP0()) // are we on a core that counts ERET as P0?
- m_P0_commit--;
+ err = m_out_elem.addElemType(pElem->getRootIndex(), OCSD_GEN_TRC_ELEM_EXCEPTION_RET);
+ if (!err)
+ {
+ if (pElem->isP0()) // are we on a core that counts ERET as P0?
+ m_elem_res.P0_commit--;
+ }
break;
case P0_FUNC_RET:
// func ret is V8M - data trace only - hint that data has been popped off the stack.
// at this point nothing to do till the decoder starts handling data trace.
if (pElem->isP0())
- m_P0_commit--;
+ m_elem_res.P0_commit--;
+ break;
+
+ case P0_Q:
+ err = processQElement();
+ m_elem_res.P0_commit--;
break;
}
if(bPopElem)
m_P0_stack.delete_back(); // remove element from stack;
-
- // if response not continue, then break out of the loop.
- if(!OCSD_DATA_RESP_IS_CONT(resp))
- {
- bPause = true;
- }
}
else
{
// too few elements for commit operation - decode error.
- resp = OCSD_RESP_FATAL_INVALID_DATA;
+ err = OCSD_ERR_COMMIT_PKT_OVERRUN;
LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_COMMIT_PKT_OVERRUN,err_idx,m_CSID,"Not enough elements to commit"));
- bPause = true;
}
}
- // done all elements - need more packets.
- if(m_P0_commit == 0)
- m_curr_state = DECODE_PKTS;
-
// reduce the spec depth by number of comitted elements
- m_curr_spec_depth -= (num_commit_req-m_P0_commit);
- return resp;
+ m_curr_spec_depth -= (num_commit_req-m_elem_res.P0_commit);
+ return err;
}
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::returnStackPop()
+ocsd_err_t TrcPktDecodeEtmV4I::returnStackPop()
{
- ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ ocsd_err_t err = OCSD_OK;
ocsd_isa nextISA;
-
+
if (m_return_stack.pop_pending())
{
ocsd_vaddr_t popAddr = m_return_stack.pop(nextISA);
if (m_return_stack.overflow())
{
- resp = OCSD_RESP_FATAL_INVALID_DATA;
- LogError(ocsdError(OCSD_ERR_SEV_ERROR, OCSD_ERR_RET_STACK_OVERFLOW, "Trace Return Stack Overflow."));
+ err = OCSD_ERR_RET_STACK_OVERFLOW;
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR, err, "Trace Return Stack Overflow."));
}
else
{
@@ -698,20 +788,23 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::returnStackPop()
m_need_addr = false;
}
}
- return resp;
+ return err;
}
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::flushEOT()
+ocsd_err_t TrcPktDecodeEtmV4I::commitElemOnEOT()
{
- ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
- if(m_flush_EOT)
+ ocsd_err_t err = OCSD_OK;
+ TrcStackElem *pElem = 0;
+
+ // nothing outstanding - reset the stack before we add more
+ if (!m_out_elem.numElemToSend())
+ m_out_elem.resetElemStack();
+
+ while((m_P0_stack.size() > 0) && !err)
{
- TrcStackElem *pElem = 0;
- while(OCSD_DATA_RESP_IS_CONT(resp) && (m_P0_stack.size() > 0))
- {
- // scan for outstanding events, TS and CC, before any outstanding
- // P0 commit elements.
- pElem = m_P0_stack.back();
+ // scan for outstanding events, TS and CC, that appear before any outstanding
+ // uncommited P0 element.
+ pElem = m_P0_stack.back();
switch(pElem->getP0Type())
{
@@ -722,104 +815,293 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::flushEOT()
case P0_EXCEP:
case P0_EXCEP_RET:
case P0_OVERFLOW:
+ case P0_Q:
m_P0_stack.delete_all();
break;
- //skip
- case P0_ADDR:
- case P0_CTXT:
- break;
+ //skip
+ case P0_ADDR:
+ case P0_CTXT:
+ break;
- // output
- case P0_EVENT:
- {
- TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
- if(pParamElem)
- resp = this->outputEvent(pParamElem);
- }
- break;
+ // output
+ case P0_EVENT:
+ case P0_TS:
+ case P0_CC:
+ case P0_TS_CC:
+ err = processTS_CC_EventElem(pElem);
+ break;
+ }
+ m_P0_stack.delete_back();
+ }
- case P0_TS:
- {
- TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
- if(pParamElem)
- resp = outputTS(pParamElem,false);
- }
- break;
+ if(!err)
+ {
+ err = m_out_elem.addElemType(m_index_curr_pkt, OCSD_GEN_TRC_ELEM_EO_TRACE);
+ outElem().setUnSyncEOTReason(m_prev_overflow ? UNSYNC_OVERFLOW : UNSYNC_EOT);
+ }
+ return err;
+}
- case P0_CC:
- {
- TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
- if(pParamElem)
- resp = outputCC(pParamElem);
+// cancel elements. These not output
+ocsd_err_t TrcPktDecodeEtmV4I::cancelElements()
+{
+ ocsd_err_t err = OCSD_OK;
+ bool P0StackDone = false; // checked all P0 elements on the stack
+ TrcStackElem *pElem = 0; // stacked element pointer
+ EtmV4P0Stack temp;
+ int num_cancel_req = m_elem_res.P0_cancel;
+
+ while (m_elem_res.P0_cancel)
+ {
+ //search the stack for the newest elements
+ if (!P0StackDone)
+ {
+ if (m_P0_stack.size() == 0)
+ P0StackDone = true;
+ else
+ {
+ // get the newest element
+ pElem = m_P0_stack.front();
+ if (pElem->isP0()) {
+ if (pElem->getP0Type() == P0_ATOM)
+ {
+ TrcStackElemAtom *pAtomElem = (TrcStackElemAtom *)pElem;
+ // atom - cancel N atoms
+ m_elem_res.P0_cancel -= pAtomElem->cancelNewest(m_elem_res.P0_cancel);
+ if (pAtomElem->isEmpty())
+ m_P0_stack.delete_front(); // remove the element
+ }
+ else
+ {
+ m_elem_res.P0_cancel--;
+ m_P0_stack.delete_front(); // remove the element
+ }
+ } else {
+ // not P0, make a keep / remove decision
+ switch (pElem->getP0Type())
+ {
+ // keep these
+ case P0_EVENT:
+ case P0_TS:
+ case P0_CC:
+ case P0_TS_CC:
+ m_P0_stack.pop_front(false);
+ temp.push_back(pElem);
+ break;
+
+ default:
+ m_P0_stack.delete_front();
+ break;
+ }
}
- break;
+ }
+ }
+ // may have some unseen elements
+ else if (m_unseen_spec_elem)
+ {
+ m_unseen_spec_elem--;
+ m_elem_res.P0_cancel--;
+ }
+ // otherwise we have some sort of overrun
+ else
+ {
+ // too few elements for commit operation - decode error.
+ err = OCSD_ERR_COMMIT_PKT_OVERRUN;
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR, err, m_index_curr_pkt, m_CSID, "Not enough elements to cancel"));
+ m_elem_res.P0_cancel = 0;
+ break;
+ }
+
+ if (temp.size())
+ {
+ while (temp.size())
+ {
+ pElem = temp.back();
+ m_P0_stack.push_front(pElem);
+ temp.pop_back(false);
+ }
+ }
+ }
+ m_curr_spec_depth -= num_cancel_req - m_elem_res.P0_cancel;
+ return err;
+}
- case P0_TS_CC:
+// mispredict an atom
+ocsd_err_t TrcPktDecodeEtmV4I::mispredictAtom()
+{
+ ocsd_err_t err = OCSD_OK;
+ bool bFoundAtom = false, bDone = false;
+ TrcStackElem *pElem = 0;
+
+ m_P0_stack.from_front_init(); // init iterator at front.
+ while (!bDone)
+ {
+ pElem = m_P0_stack.from_front_next();
+ if (pElem)
+ {
+ if (pElem->getP0Type() == P0_ATOM)
+ {
+ TrcStackElemAtom *pAtomElem = dynamic_cast<TrcStackElemAtom *>(pElem);
+ if (pAtomElem)
{
- TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
- if(pParamElem)
- resp = outputTS(pParamElem,true);
+ pAtomElem->mispredictNewest();
+ bFoundAtom = true;
}
- break;
+ bDone = true;
+ }
+ else if (pElem->getP0Type() == P0_ADDR)
+ {
+ // need to disregard any addresses that appear between mispredict and the atom in question
+ m_P0_stack.erase_curr_from_front();
}
- m_P0_stack.delete_back();
}
+ else
+ bDone = true;
+ }
+
+ // if missed atom then either overrun error or mispredict on unseen element
+ if (!bFoundAtom && !m_unseen_spec_elem)
+ {
+ err = OCSD_ERR_COMMIT_PKT_OVERRUN;
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR, err, m_index_curr_pkt, m_CSID, "Not found mispredict atom"));
+ }
+ m_elem_res.mispredict = false;
+ return err;
+}
+
+// discard elements and flush
+ocsd_err_t TrcPktDecodeEtmV4I::discardElements()
+{
+ ocsd_err_t err = OCSD_OK;
+ TrcStackElem *pElem = 0; // stacked element pointer
+
+ // dump P0, elemnts - output remaining CC / TS
+ while ((m_P0_stack.size() > 0) && !err)
+ {
+ pElem = m_P0_stack.back();
+ err = processTS_CC_EventElem(pElem);
+ m_P0_stack.delete_back();
+ }
+
+ // clear all speculation info
+ clearElemRes();
+ m_curr_spec_depth = 0;
+
+ // set decode state
+ m_curr_state = NO_SYNC;
+ m_unsync_eot_info = m_prev_overflow ? UNSYNC_OVERFLOW : UNSYNC_DISCARD;
+
+ // unsync so need context & address.
+ m_need_ctxt = true;
+ m_need_addr = true;
+ m_elem_pending_addr = false;
+ return err;
+}
+
+ocsd_err_t TrcPktDecodeEtmV4I::processTS_CC_EventElem(TrcStackElem *pElem)
+{
+ ocsd_err_t err = OCSD_OK;
- if(OCSD_DATA_RESP_IS_CONT(resp) && (m_P0_stack.size() == 0))
+ switch (pElem->getP0Type())
+ {
+ case P0_EVENT:
+ {
+ TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
+ if (pParamElem)
+ err = addElemEvent(pParamElem);
+ }
+ break;
+
+ case P0_TS:
+ {
+ TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
+ if (pParamElem)
+ err = addElemTS(pParamElem, false);
+ }
+ break;
+
+ case P0_CC:
{
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_EO_TRACE);
- resp = outputTraceElement(m_output_elem);
- m_flush_EOT = false;
+ TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
+ if (pParamElem)
+ err = addElemCC(pParamElem);
}
+ break;
+
+ case P0_TS_CC:
+ {
+ TrcStackElemParam *pParamElem = dynamic_cast<TrcStackElemParam *>(pElem);
+ if (pParamElem)
+ err = addElemTS(pParamElem, true);
+ }
+ break;
}
- return resp;
+ return err;
+
}
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::outputCC(TrcStackElemParam *pParamElem)
+ocsd_err_t TrcPktDecodeEtmV4I::addElemCC(TrcStackElemParam *pParamElem)
{
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_CYCLE_COUNT);
- m_output_elem.setCycleCount(pParamElem->getParam(0));
- return outputTraceElementIdx(pParamElem->getRootIndex(),m_output_elem);
+ ocsd_err_t err = OCSD_OK;
+
+ err = m_out_elem.addElemType(pParamElem->getRootIndex(), OCSD_GEN_TRC_ELEM_CYCLE_COUNT);
+ if (!err)
+ outElem().setCycleCount(pParamElem->getParam(0));
+ return err;
}
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::outputTS(TrcStackElemParam *pParamElem, bool withCC)
+ocsd_err_t TrcPktDecodeEtmV4I::addElemTS(TrcStackElemParam *pParamElem, bool withCC)
{
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_TIMESTAMP);
- m_output_elem.timestamp = (uint64_t)(pParamElem->getParam(0)) | (((uint64_t)pParamElem->getParam(1)) << 32);
- if(withCC)
- m_output_elem.setCycleCount(pParamElem->getParam(2));
- return outputTraceElementIdx(pParamElem->getRootIndex(),m_output_elem);
+ ocsd_err_t err = OCSD_OK;
+
+ err = m_out_elem.addElemType(pParamElem->getRootIndex(), OCSD_GEN_TRC_ELEM_TIMESTAMP);
+ if (!err)
+ {
+ outElem().timestamp = (uint64_t)(pParamElem->getParam(0)) | (((uint64_t)pParamElem->getParam(1)) << 32);
+ if (withCC)
+ outElem().setCycleCount(pParamElem->getParam(2));
+ }
+ return err;
}
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::outputEvent(TrcStackElemParam *pParamElem)
+ocsd_err_t TrcPktDecodeEtmV4I::addElemEvent(TrcStackElemParam *pParamElem)
{
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_EVENT);
- m_output_elem.trace_event.ev_type = EVENT_NUMBERED;
- m_output_elem.trace_event.ev_number = pParamElem->getParam(0);
- return outputTraceElementIdx(pParamElem->getRootIndex(),m_output_elem);
+ ocsd_err_t err = OCSD_OK;
+
+ err = m_out_elem.addElemType(pParamElem->getRootIndex(), OCSD_GEN_TRC_ELEM_EVENT);
+ if (!err)
+ {
+ outElem().trace_event.ev_type = EVENT_NUMBERED;
+ outElem().trace_event.ev_number = pParamElem->getParam(0);
+ }
+ return err;
}
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::outputTraceRange(const bool executed, ocsd_trc_index_t index)
+void TrcPktDecodeEtmV4I::setElemTraceRange(OcsdTraceElement &elemIn, const instr_range_t &addr_range,
+ const bool executed, ocsd_trc_index_t index)
{
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_INSTR_RANGE);
- m_output_elem.setLastInstrInfo(executed, m_instr_info.type, m_instr_info.sub_type, m_instr_info.instr_size);
- m_output_elem.setISA(m_instr_info.isa);
- m_output_elem.setLastInstrCond(m_instr_info.is_conditional);
+ elemIn.setType(OCSD_GEN_TRC_ELEM_INSTR_RANGE);
+ elemIn.setLastInstrInfo(executed, m_instr_info.type, m_instr_info.sub_type, m_instr_info.instr_size);
+ elemIn.setISA(m_instr_info.isa);
+ elemIn.setLastInstrCond(m_instr_info.is_conditional);
+ elemIn.setAddrRange(addr_range.st_addr, addr_range.en_addr, addr_range.num_instr);
if (executed)
m_instr_info.isa = m_instr_info.next_isa;
- return outputTraceElementIdx(index, m_output_elem);
}
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::processAtom(const ocsd_atm_val atom, bool &bCont)
+ocsd_err_t TrcPktDecodeEtmV4I::processAtom(const ocsd_atm_val atom)
{
- ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
- TrcStackElem *pElem = m_P0_stack.back(); // get the atom element
- bool bWPFound = false;
ocsd_err_t err;
- bCont = true;
+ TrcStackElem *pElem = m_P0_stack.back(); // get the atom element
+ WP_res_t WPRes;
+ instr_range_t addr_range;
+
+ // new element for this processed atom
+ if ((err = m_out_elem.addElem(pElem->getRootIndex())) != OCSD_OK)
+ return err;
- err = traceInstrToWP(bWPFound);
+ err = traceInstrToWP(addr_range, WPRes);
if(err != OCSD_OK)
{
if(err == OCSD_ERR_UNSUPPORTED_ISA)
@@ -828,18 +1110,16 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::processAtom(const ocsd_atm_val atom, bo
m_need_ctxt = true;
LogError(ocsdError(OCSD_ERR_SEV_WARN,err,pElem->getRootIndex(),m_CSID,"Warning: unsupported instruction set processing atom packet."));
// wait for next context
- return resp;
+ return OCSD_OK;
}
else
{
- bCont = false;
- resp = OCSD_RESP_FATAL_INVALID_DATA;
LogError(ocsdError(OCSD_ERR_SEV_ERROR,err,pElem->getRootIndex(),m_CSID,"Error processing atom packet."));
- return resp;
+ return err;
}
}
- if(bWPFound)
+ if(WPFound(WPRes))
{
// save recorded next instuction address
ocsd_vaddr_t nextAddr = m_instr_info.instr_addr;
@@ -867,125 +1147,113 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::processAtom(const ocsd_atm_val atom, bo
}
break;
}
- resp = outputTraceRange((atom == ATOM_E), pElem->getRootIndex());
-
+ setElemTraceRange(outElem(), addr_range, (atom == ATOM_E), pElem->getRootIndex());
}
else
{
// no waypoint - likely inaccessible memory range.
m_need_addr = true; // need an address update
- if(m_output_elem.st_addr != m_output_elem.en_addr)
+ if(addr_range.st_addr != addr_range.en_addr)
{
// some trace before we were out of memory access range
- resp = outputTraceRange(true, pElem->getRootIndex());
+ setElemTraceRange(outElem(), addr_range, true, pElem->getRootIndex());
+
+ // another element for the nacc...
+ if (WPNacc(WPRes))
+ err = m_out_elem.addElem(pElem->getRootIndex());
}
- if(m_mem_nacc_pending && OCSD_DATA_RESP_IS_CONT(resp))
+ if(WPNacc(WPRes) && !err)
{
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_ADDR_NACC);
- m_output_elem.st_addr = m_nacc_addr;
- resp = outputTraceElementIdx(pElem->getRootIndex(),m_output_elem);
- m_mem_nacc_pending = false;
+ outElem().setType(OCSD_GEN_TRC_ELEM_ADDR_NACC);
+ outElem().st_addr = m_instr_info.instr_addr;
}
}
-
- if(!OCSD_DATA_RESP_IS_CONT(resp))
- bCont = false;
-
- return resp;
+ return err;
}
// Exception processor
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::processException()
+ocsd_err_t TrcPktDecodeEtmV4I::processException()
{
- ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
- TrcStackElemExcept *pExceptElem;
-
- m_excep_info.addr_b_tgt = false;
-
- if(m_excep_info.proc == EXCEP_POP)
+ ocsd_err_t err;
+ TrcStackElem *pElem = 0;
+ TrcStackElemExcept *pExceptElem = 0;
+ TrcStackElemAddr *pAddressElem = 0;
+ TrcStackElemCtxt *pCtxtElem = 0;
+ bool branch_target = false; // exception address implies prior branch target address
+ ocsd_vaddr_t excep_ret_addr;
+ ocsd_trc_index_t excep_pkt_index;
+ WP_res_t WPRes = WP_NOT_FOUND;
+
+ // grab the exception element off the stack
+ pExceptElem = dynamic_cast<TrcStackElemExcept *>(m_P0_stack.back()); // get the exception element
+ excep_pkt_index = pExceptElem->getRootIndex();
+ branch_target = pExceptElem->getPrevSame();
+ m_P0_stack.pop_back(); // remove the exception element
+
+ pElem = m_P0_stack.back(); // look at next element.
+ if(pElem->getP0Type() == P0_CTXT)
{
- pExceptElem = dynamic_cast<TrcStackElemExcept *>(m_P0_stack.back()); // get the exception element
- TrcStackElemAddr *pAddressElem = 0;
- TrcStackElemCtxt *pCtxtElem = 0;
- TrcStackElem *pElem = 0;
-
- m_P0_stack.pop_back(); // remove the exception element
- pElem = m_P0_stack.back(); // look at next element.
- if(pElem->getP0Type() == P0_CTXT)
- {
- pCtxtElem = dynamic_cast<TrcStackElemCtxt *>(pElem);
- m_P0_stack.pop_back(); // remove the context element
- pElem = m_P0_stack.back(); // next one should be an address element
- }
+ pCtxtElem = dynamic_cast<TrcStackElemCtxt *>(pElem);
+ m_P0_stack.pop_back(); // remove the context element
+ pElem = m_P0_stack.back(); // next one should be an address element
+ }
- if(pElem->getP0Type() != P0_ADDR)
+ if(pElem->getP0Type() != P0_ADDR)
+ {
+ // no following address element - indicate processing error.
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_BAD_PACKET_SEQ, excep_pkt_index,m_CSID,"Address missing in exception packet."));
+ return OCSD_ERR_BAD_PACKET_SEQ;
+ }
+ else
+ {
+ // extract address
+ pAddressElem = static_cast<TrcStackElemAddr *>(pElem);
+ excep_ret_addr = pAddressElem->getAddr().val;
+
+ // see if there is an address + optional context element implied
+ // prior to the exception.
+ if (branch_target)
{
- // no following address element - indicate processing error.
- resp = OCSD_RESP_FATAL_INVALID_DATA;
- LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_BAD_PACKET_SEQ,pExceptElem->getRootIndex(),m_CSID,"Address missing in exception packet."));
- }
- else
- {
- // extract address
- pAddressElem = static_cast<TrcStackElemAddr *>(pElem);
-
- // fill in exception info for use later
- m_excep_info.addr = pAddressElem->getAddr();
- m_excep_info.number = pExceptElem->getExcepNum();
- m_excep_info.index = pExceptElem->getRootIndex();
- m_excep_info.addr_b_tgt = pExceptElem->getPrevSame();
-
- // see if there is an address + optional context element implied
- // prior to the exception.
- if (m_excep_info.addr_b_tgt)
- {
- // this was a branch target address - update current setting
- bool b64bit = m_instr_info.isa == ocsd_isa_aarch64;
- if (pCtxtElem) {
- b64bit = pCtxtElem->getContext().SF;
- }
- m_instr_info.instr_addr = m_excep_info.addr.val;
- m_instr_info.isa = (m_excep_info.addr.isa == 0) ?
- (b64bit ? ocsd_isa_aarch64 : ocsd_isa_arm) : ocsd_isa_thumb2;
- m_need_addr = false;
- }
-
- // figure out next move
+ // this was a branch target address - update current setting
+ bool b64bit = m_instr_info.isa == ocsd_isa_aarch64;
if (pCtxtElem) {
- m_excep_info.proc = EXCEP_CTXT;
- updateContext(pCtxtElem);
+ b64bit = pCtxtElem->getContext().SF;
}
- else if(m_excep_info.addr.val == m_instr_info.instr_addr)
- m_excep_info.proc = EXCEP_EXCEP;
- else
- m_excep_info.proc = EXCEP_RANGE;
+
+ // as the exception address was also a branch target address then update the
+ // current maintained address value. This also means that there is no range to
+ // output before the exception packet.
+ m_instr_info.instr_addr = excep_ret_addr;
+ m_instr_info.isa = (pAddressElem->getAddr().isa == 0) ?
+ (b64bit ? ocsd_isa_aarch64 : ocsd_isa_arm) : ocsd_isa_thumb2;
+ m_need_addr = false;
}
- m_P0_stack.delete_popped();
- }
+ }
- // output a context element
- if (m_excep_info.proc == EXCEP_CTXT)
- {
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_PE_CONTEXT);
- resp = outputTraceElementIdx(m_excep_info.index, m_output_elem);
- m_excep_info.proc = EXCEP_EXCEP;
- if (!OCSD_DATA_RESP_IS_CONT(resp))
- return resp;
- }
+ // need to output something - set up an element
+ if ((err = m_out_elem.addElem(excep_pkt_index)))
+ return err;
- // output a range element
- if(m_excep_info.proc == EXCEP_RANGE)
+ // output a context element if present
+ if (pCtxtElem)
{
- bool bWPFound = false;
- ocsd_err_t err;
+ updateContext(pCtxtElem, outElem());
- // last instr_info address is the start address
- m_output_elem.st_addr = m_instr_info.instr_addr;
+ // used the element - need another for later stages
+ if ((err = m_out_elem.addElem(excep_pkt_index)))
+ return err;
+ }
+
+ // if the preferred return address is not the end of the last output range...
+ if (m_instr_info.instr_addr != excep_ret_addr)
+ {
+ bool range_out = false;
+ instr_range_t addr_range;
// look for match to return address.
- err = traceInstrToWP(bWPFound,true,m_excep_info.addr.val);
+ err = traceInstrToWP(addr_range, WPRes, true, excep_ret_addr);
if(err != OCSD_OK)
{
@@ -993,90 +1261,221 @@ ocsd_datapath_resp_t TrcPktDecodeEtmV4I::processException()
{
m_need_addr = true;
m_need_ctxt = true;
- LogError(ocsdError(OCSD_ERR_SEV_WARN,err,m_excep_info.index,m_CSID,"Warning: unsupported instruction set processing exception packet."));
+ LogError(ocsdError(OCSD_ERR_SEV_WARN,err, excep_pkt_index,m_CSID,"Warning: unsupported instruction set processing exception packet."));
}
else
{
- resp = OCSD_RESP_FATAL_INVALID_DATA;
- LogError(ocsdError(OCSD_ERR_SEV_ERROR,err,m_excep_info.index,m_CSID,"Error processing exception packet."));
- m_excep_info.proc = EXCEP_POP; // nothing more to do, reset to start of exception handling
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR,err, excep_pkt_index,m_CSID,"Error processing exception packet."));
}
+ return err;
}
- if(bWPFound)
+ if(WPFound(WPRes))
{
// waypoint address found - output range
- resp = outputTraceRange(true, m_excep_info.index);
- m_excep_info.proc = EXCEP_EXCEP;
+ setElemTraceRange(outElem(), addr_range, true, excep_pkt_index);
+ range_out = true;
}
else
{
// no waypoint - likely inaccessible memory range.
m_need_addr = true; // need an address update
- if(m_output_elem.st_addr != m_output_elem.en_addr)
+ if(addr_range.st_addr != addr_range.en_addr)
{
// some trace before we were out of memory access range
- resp = outputTraceRange(true, m_excep_info.index);
+ setElemTraceRange(outElem(), addr_range, true, excep_pkt_index);
+ range_out = true;
}
+ }
- m_excep_info.proc = m_mem_nacc_pending ? EXCEP_NACC : EXCEP_EXCEP;
+ // used the element need another for NACC or EXCEP.
+ if (range_out)
+ {
+ if ((err = m_out_elem.addElem(excep_pkt_index)))
+ return err;
}
- }
-
- if((m_excep_info.proc == EXCEP_NACC) && OCSD_DATA_RESP_IS_CONT(resp))
+ }
+
+ // watchpoint walk resulted in inaccessible memory call...
+ if (WPNacc(WPRes))
{
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_ADDR_NACC);
- m_output_elem.st_addr = m_nacc_addr;
- resp = outputTraceElementIdx(m_excep_info.index,m_output_elem);
- m_excep_info.proc = EXCEP_EXCEP;
- m_mem_nacc_pending = false;
+
+ outElem().setType(OCSD_GEN_TRC_ELEM_ADDR_NACC);
+ outElem().st_addr = m_instr_info.instr_addr;
+
+ // used the element - need another for the final exception packet.
+ if ((err = m_out_elem.addElem(excep_pkt_index)))
+ return err;
}
- if((m_excep_info.proc == EXCEP_EXCEP) && OCSD_DATA_RESP_IS_CONT(resp))
+ // output exception element.
+ outElem().setType(OCSD_GEN_TRC_ELEM_EXCEPTION);
+
+ // add end address as preferred return address to end addr in element
+ outElem().en_addr = excep_ret_addr;
+ outElem().excep_ret_addr = 1;
+ outElem().excep_ret_addr_br_tgt = branch_target;
+ outElem().exception_number = pExceptElem->getExcepNum();
+
+ m_P0_stack.delete_popped(); // clear the used elements from the stack
+ return err;
+}
+
+ocsd_err_t TrcPktDecodeEtmV4I::processQElement()
+{
+ ocsd_err_t err = OCSD_OK;
+ TrcStackQElem *pQElem;
+ etmv4_addr_val_t QAddr; // address where trace restarts
+ int iCount = 0;
+
+ pQElem = dynamic_cast<TrcStackQElem *>(m_P0_stack.back()); // get the exception element
+ m_P0_stack.pop_back(); // remove the Q element.
+
+ if (!pQElem->hasAddr()) // no address - it must be next on the stack....
{
- // output element.
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_EXCEPTION);
- // add end address as preferred return address to end addr in element
- m_output_elem.en_addr = m_excep_info.addr.val;
- m_output_elem.excep_ret_addr = 1;
- m_output_elem.excep_ret_addr_br_tgt = m_excep_info.addr_b_tgt;
- m_output_elem.exception_number = m_excep_info.number;
- resp = outputTraceElementIdx(m_excep_info.index,m_output_elem);
- m_excep_info.proc = EXCEP_POP;
- }
- return resp;
+ TrcStackElemAddr *pAddressElem = 0;
+ TrcStackElemCtxt *pCtxtElem = 0;
+ TrcStackElem *pElem = 0;
+
+ pElem = m_P0_stack.back(); // look at next element.
+ if (pElem->getP0Type() == P0_CTXT)
+ {
+ pCtxtElem = dynamic_cast<TrcStackElemCtxt *>(pElem);
+ m_P0_stack.pop_back(); // remove the context element
+ pElem = m_P0_stack.back(); // next one should be an address element
+ }
+
+ if (pElem->getP0Type() != P0_ADDR)
+ {
+ // no following address element - indicate processing error.
+ err = OCSD_ERR_BAD_PACKET_SEQ;
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR, err, pQElem->getRootIndex(), m_CSID, "Address missing in Q packet."));
+ m_P0_stack.delete_popped();
+ return err;
+ }
+ pAddressElem = dynamic_cast<TrcStackElemAddr *>(pElem);
+ QAddr = pAddressElem->getAddr();
+ m_P0_stack.pop_back(); // remove the address element
+ m_P0_stack.delete_popped(); // clear used elements
+
+ // return the context element for processing next time.
+ if (pCtxtElem)
+ {
+ // need a new copy at the back - old one will be deleted as popped.
+ m_P0_stack.createContextElem(pCtxtElem->getRootPkt(), pCtxtElem->getRootIndex(), pCtxtElem->getContext(),true);
+ }
+ }
+ else
+ QAddr = pQElem->getAddr();
+
+ // process the Q element with address.
+ iCount = pQElem->getInstrCount();
+
+ bool isBranch = false;
+
+ // need to output something - set up an element
+ if ((err = m_out_elem.addElem(pQElem->getRootIndex())))
+ return err;
+
+ instr_range_t addr_range;
+ addr_range.st_addr = addr_range.en_addr = m_instr_info.instr_addr;
+ addr_range.num_instr = 0;
+
+ // walk iCount instructions
+ for (int i = 0; i < iCount; i++)
+ {
+ uint32_t opcode;
+ uint32_t bytesReq = 4;
+
+ err = accessMemory(m_instr_info.instr_addr, getCurrMemSpace(), &bytesReq, (uint8_t *)&opcode);
+ if (err != OCSD_OK) break;
+
+ if (bytesReq == 4) // got data back
+ {
+ m_instr_info.opcode = opcode;
+ err = instrDecode(&m_instr_info);
+ if (err != OCSD_OK) break;
+
+ // increment address - may be adjusted by direct branch value later
+ m_instr_info.instr_addr += m_instr_info.instr_size;
+ addr_range.num_instr++;
+
+ isBranch = (m_instr_info.type == OCSD_INSTR_BR) ||
+ (m_instr_info.type == OCSD_INSTR_BR_INDIRECT);
+
+ // on a branch no way of knowing if taken - bail out
+ if (isBranch)
+ break;
+ }
+ else
+ break; // missing memory
+
+ }
+
+ if (err == OCSD_OK)
+ {
+ bool inCompleteRange = true;
+ if (iCount && (addr_range.num_instr == (unsigned)iCount))
+ {
+ if ((m_instr_info.instr_addr == QAddr.val) || // complete range
+ (isBranch)) // or ends on branch - only way we know if branch taken.
+ {
+ // output a range and continue
+ inCompleteRange = false;
+ // update the range decoded address in the output packet.
+ addr_range.en_addr = m_instr_info.instr_addr;
+ setElemTraceRange(outElem(), addr_range, true, pQElem->getRootIndex());
+ }
+ }
+
+ if (inCompleteRange)
+ {
+ // unknown instructions executed.
+ addr_range.en_addr = QAddr.val;
+ addr_range.num_instr = iCount;
+
+ outElem().setType(OCSD_GEN_TRC_ELEM_I_RANGE_NOPATH);
+ outElem().setAddrRange(addr_range.st_addr, addr_range.en_addr, addr_range.num_instr);
+ outElem().setISA(calcISA(m_is_64bit, QAddr.isa));
+ }
+
+ // after the Q element, tracing resumes at the address supplied
+ SetInstrInfoInAddrISA(QAddr.val, QAddr.isa);
+ m_need_addr = false;
+ }
+ else
+ {
+ // output error and halt decode.
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR, err, pQElem->getRootIndex(), m_CSID, "Error processing Q packet"));
+ }
+ m_P0_stack.delete_popped();
+ return err;
}
void TrcPktDecodeEtmV4I::SetInstrInfoInAddrISA(const ocsd_vaddr_t addr_val, const uint8_t isa)
{
m_instr_info.instr_addr = addr_val;
- if(m_is_64bit)
- m_instr_info.isa = ocsd_isa_aarch64;
- else
- m_instr_info.isa = (isa == 0) ? ocsd_isa_arm : ocsd_isa_thumb2;
+ m_instr_info.isa = calcISA(m_is_64bit, isa);
}
// trace an instruction range to a waypoint - and set next address to restart from.
-ocsd_err_t TrcPktDecodeEtmV4I::traceInstrToWP(bool &bWPFound, const bool traceToAddrNext /*= false*/, const ocsd_vaddr_t nextAddrMatch /*= 0*/)
+ocsd_err_t TrcPktDecodeEtmV4I::traceInstrToWP(instr_range_t &range, WP_res_t &WPRes, const bool traceToAddrNext /*= false*/, const ocsd_vaddr_t nextAddrMatch /*= 0*/)
{
uint32_t opcode;
uint32_t bytesReq;
ocsd_err_t err = OCSD_OK;
- // TBD?: update mem space to allow for EL as well.
- ocsd_mem_space_acc_t mem_space = m_is_secure ? OCSD_MEM_SPACE_S : OCSD_MEM_SPACE_N;
-
- m_output_elem.st_addr = m_output_elem.en_addr = m_instr_info.instr_addr;
- m_output_elem.num_instr_range = 0;
+ range.st_addr = range.en_addr = m_instr_info.instr_addr;
+ range.num_instr = 0;
- bWPFound = false;
+ WPRes = WP_NOT_FOUND;
- while(!bWPFound && !m_mem_nacc_pending)
+ while(WPRes == WP_NOT_FOUND)
{
// start off by reading next opcode;
bytesReq = 4;
- err = accessMemory(m_instr_info.instr_addr,mem_space,&bytesReq,(uint8_t *)&opcode);
+ err = accessMemory(m_instr_info.instr_addr, getCurrMemSpace(),&bytesReq,(uint8_t *)&opcode);
if(err != OCSD_OK) break;
if(bytesReq == 4) // got data back
@@ -1087,69 +1486,100 @@ ocsd_err_t TrcPktDecodeEtmV4I::traceInstrToWP(bool &bWPFound, const bool traceTo
// increment address - may be adjusted by direct branch value later
m_instr_info.instr_addr += m_instr_info.instr_size;
-
- // update the range decoded address in the output packet.
- m_output_elem.en_addr = m_instr_info.instr_addr;
- m_output_elem.num_instr_range++;
+ range.num_instr++;
// either walking to match the next instruction address or a real watchpoint
- if(traceToAddrNext)
- bWPFound = (m_output_elem.en_addr == nextAddrMatch);
- else
- bWPFound = (m_instr_info.type != OCSD_INSTR_OTHER);
+ if (traceToAddrNext)
+ {
+ if (m_instr_info.instr_addr == nextAddrMatch)
+ WPRes = WP_FOUND;
+ }
+ else if (m_instr_info.type != OCSD_INSTR_OTHER)
+ WPRes = WP_FOUND;
}
else
{
// not enough memory accessible.
- m_mem_nacc_pending = true;
- m_nacc_addr = m_instr_info.instr_addr;
+ WPRes = WP_NACC;
}
}
+ // update the range decoded address in the output packet.
+ range.en_addr = m_instr_info.instr_addr;
return err;
}
-void TrcPktDecodeEtmV4I::updateContext(TrcStackElemCtxt *pCtxtElem)
+void TrcPktDecodeEtmV4I::updateContext(TrcStackElemCtxt *pCtxtElem, OcsdTraceElement &elem)
{
etmv4_context_t ctxt = pCtxtElem->getContext();
- // map to output element and local saved state.
+
+ elem.setType(OCSD_GEN_TRC_ELEM_PE_CONTEXT);
+
+ // map to output element and local saved state.
m_is_64bit = (ctxt.SF != 0);
- m_output_elem.context.bits64 = ctxt.SF;
+ elem.context.bits64 = ctxt.SF;
m_is_secure = (ctxt.NS == 0);
- m_output_elem.context.security_level = ctxt.NS ? ocsd_sec_nonsecure : ocsd_sec_secure;
- m_output_elem.context.exception_level = (ocsd_ex_level)ctxt.EL;
- m_output_elem.context.el_valid = 1;
+ elem.context.security_level = ctxt.NS ? ocsd_sec_nonsecure : ocsd_sec_secure;
+ elem.context.exception_level = (ocsd_ex_level)ctxt.EL;
+ elem.context.el_valid = 1;
if(ctxt.updated_c)
{
- m_output_elem.context.ctxt_id_valid = 1;
- m_context_id = m_output_elem.context.context_id = ctxt.ctxtID;
+ elem.context.ctxt_id_valid = 1;
+ m_context_id = elem.context.context_id = ctxt.ctxtID;
}
if(ctxt.updated_v)
{
- m_output_elem.context.vmid_valid = 1;
- m_vmid_id = m_output_elem.context.vmid = ctxt.VMID;
+ elem.context.vmid_valid = 1;
+ m_vmid_id = elem.context.vmid = ctxt.VMID;
}
+
+ // need to update ISA in case context follows address.
+ elem.isa = m_instr_info.isa = calcISA(m_is_64bit, pCtxtElem->getIS());
m_need_ctxt = false;
}
-ocsd_datapath_resp_t TrcPktDecodeEtmV4I::handleBadPacket(const char *reason)
+ocsd_err_t TrcPktDecodeEtmV4I::handleBadPacket(const char *reason)
{
- ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ ocsd_err_t err = OCSD_OK;
- if(getComponentOpMode() && OCSD_OPFLG_PKTDEC_ERROR_BAD_PKTS)
+ if(getComponentOpMode() & OCSD_OPFLG_PKTDEC_ERROR_BAD_PKTS)
{
// error out - stop decoding
- resp = OCSD_RESP_FATAL_INVALID_DATA;
- LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_BAD_DECODE_PKT,reason));
+ err = OCSD_ERR_BAD_DECODE_PKT;
+ LogError(ocsdError(OCSD_ERR_SEV_ERROR,err,reason));
}
else
{
+ LogError(ocsdError(OCSD_ERR_SEV_WARN, OCSD_ERR_BAD_DECODE_PKT, reason));
// switch to unsync - clear decode state
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_NO_SYNC);
- resp = outputTraceElement(m_output_elem);
resetDecoder();
- m_curr_state = WAIT_SYNC;
+ m_curr_state = NO_SYNC;
+ m_unsync_eot_info = UNSYNC_BAD_PACKET;
}
- return resp;
+ return err;
}
+inline ocsd_mem_space_acc_t TrcPktDecodeEtmV4I::getCurrMemSpace()
+{
+ static ocsd_mem_space_acc_t SMemSpace[] = {
+ OCSD_MEM_SPACE_EL1S,
+ OCSD_MEM_SPACE_EL1S,
+ OCSD_MEM_SPACE_EL2S,
+ OCSD_MEM_SPACE_EL3
+ };
+
+ static ocsd_mem_space_acc_t NSMemSpace[] = {
+ OCSD_MEM_SPACE_EL1N,
+ OCSD_MEM_SPACE_EL1N,
+ OCSD_MEM_SPACE_EL2,
+ OCSD_MEM_SPACE_EL3
+ };
+
+ /* if no valid EL value - just use S/NS */
+ if (!outElem().context.el_valid)
+ return m_is_secure ? OCSD_MEM_SPACE_S : OCSD_MEM_SPACE_N;
+
+ /* mem space according to EL + S/NS */
+ int el = (int)(outElem().context.exception_level) & 0x3;
+ return m_is_secure ? SMemSpace[el] : NSMemSpace[el];
+}
/* End of File trc_pkt_decode_etmv4i.cpp */
diff --git a/decoder/source/etmv4/trc_pkt_elem_etmv4d.cpp b/decoder/source/etmv4/trc_pkt_elem_etmv4d.cpp
deleted file mode 100644
index 58343b4117bf..000000000000
--- a/decoder/source/etmv4/trc_pkt_elem_etmv4d.cpp
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * \file trc_pkt_elem_etmv4d.cpp
- * \brief OpenCSD :
- *
- * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
- */
-
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- * may be used to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "opencsd/etmv4/trc_pkt_elem_etmv4d.h"
-
-EtmV4DTrcPacket::EtmV4DTrcPacket()
-{
-}
-
-EtmV4DTrcPacket::~EtmV4DTrcPacket()
-{
-}
-
- // printing
-void EtmV4DTrcPacket::toString(std::string &str) const
-{
-}
-
-void EtmV4DTrcPacket::toStringFmt(const uint32_t fmtFlags, std::string &str) const
-{
-}
-
-
-
-/* End of File trc_pkt_elem_etmv4d.cpp */
diff --git a/decoder/source/etmv4/trc_pkt_elem_etmv4i.cpp b/decoder/source/etmv4/trc_pkt_elem_etmv4i.cpp
index 3f9d534db82c..853fde499a1b 100644
--- a/decoder/source/etmv4/trc_pkt_elem_etmv4i.cpp
+++ b/decoder/source/etmv4/trc_pkt_elem_etmv4i.cpp
@@ -161,6 +161,7 @@ void EtmV4ITrcPacket::toString(std::string &str) const
{
std::ostringstream oss;
oss << "; INFO=" << std::hex << "0x" << trace_info.val;
+ oss << " { CC." << std::dec << trace_info.bits.cc_enabled << " }";
if (trace_info.bits.cc_enabled)
oss << "; CC_THRESHOLD=" << std::hex << "0x" << cc_threshold;
str += oss.str();
@@ -176,8 +177,96 @@ void EtmV4ITrcPacket::toString(std::string &str) const
str += oss.str();
}
break;
+
+ case ETM4_PKT_I_CANCEL_F1:
+ {
+ std::ostringstream oss;
+ oss << "; Cancel(" << std::dec << cancel_elements << ")";
+ str += oss.str();
+ }
+ break;
+
+ case ETM4_PKT_I_CANCEL_F1_MISPRED:
+ {
+ std::ostringstream oss;
+ oss << "; Cancel(" << std::dec << cancel_elements << "), Mispredict";
+ str += oss.str();
+ }
+ break;
+
+ case ETM4_PKT_I_MISPREDICT:
+ {
+ std::ostringstream oss;
+ oss << "; ";
+ if (atom.num) {
+ atomSeq(valStr);
+ oss << "Atom: " << valStr << ", ";
+ }
+ oss << "Mispredict";
+ str += oss.str();
+ }
+ break;
+
+ case ETM4_PKT_I_CANCEL_F2:
+ {
+ std::ostringstream oss;
+ oss << "; ";
+ if (atom.num) {
+ atomSeq(valStr);
+ oss << "Atom: " << valStr << ", ";
+ }
+ oss << "Cancel(1), Mispredict";
+ str += oss.str();
+ }
+ break;
+
+ case ETM4_PKT_I_CANCEL_F3:
+ {
+ std::ostringstream oss;
+ oss << "; ";
+ if (atom.num) {
+ oss << "Atom: E, ";
+ }
+ oss << "Cancel(" << std::dec << cancel_elements << "), Mispredict";
+ str += oss.str();
+ }
+ break;
+
+ case ETM4_PKT_I_COMMIT:
+ {
+ std::ostringstream oss;
+ oss << "; Commit(" << std::dec << commit_elements << ")";
+ str += oss.str();
+ }
+ break;
+
+ case ETM4_PKT_I_Q:
+ {
+ std::ostringstream oss;
+ if (Q_pkt.count_present)
+ {
+ oss << "; Count(" << std::dec << Q_pkt.q_count << ")";
+ str += oss.str();
+ }
+ else
+ str += "; Count(Unknown)";
+
+ if (Q_pkt.addr_match)
+ {
+ addrMatchIdx(valStr);
+ str += "; " + valStr;
+ }
+
+ if (Q_pkt.addr_present || Q_pkt.addr_match)
+ {
+ trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 64) ? v_addr.pkt_bits : 0);
+ str += "; Addr=" + valStr;
+ }
+ }
+ break;
}
-}
+
+}
void EtmV4ITrcPacket::toStringFmt(const uint32_t fmtFlags, std::string &str) const
{
@@ -296,6 +385,12 @@ const char *EtmV4ITrcPacket::packetTypeName(const ocsd_etmv4_i_pkt_type type, co
pDesc = "Cancel Format 1.";
break;
+ case ETM4_PKT_I_CANCEL_F1_MISPRED:
+ pName = "I_CANCEL_F1_MISPRED";
+ pDesc = "Cancel Format 1 + Mispredict.";
+ break;
+
+
case ETM4_PKT_I_MISPREDICT:
pName = "I_MISPREDICT";
pDesc = "Mispredict.";
diff --git a/decoder/source/etmv4/trc_pkt_proc_etmv4.cpp b/decoder/source/etmv4/trc_pkt_proc_etmv4.cpp
deleted file mode 100644
index b8c4f819c2d3..000000000000
--- a/decoder/source/etmv4/trc_pkt_proc_etmv4.cpp
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * \file trc_pkt_proc_etmv4.cpp
- * \brief OpenCSD :
- *
- * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
- */
-
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- * may be used to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "opencsd/etmv4/trc_pkt_proc_etmv4.h"
-#include "trc_pkt_proc_etmv4i_impl.h"
-#include "common/ocsd_error.h"
-
-#ifdef __GNUC__
-// G++ doesn't like the ## pasting
-#define ETMV4I_PKTS_NAME "PKTP_ETMV4I"
-#else
-// VC++ is fine
-#define ETMV4I_PKTS_NAME OCSD_CMPNAME_PREFIX_PKTPROC##"_ETMV4I"
-#endif
-
-static const uint32_t ETMV4_SUPPORTED_OP_FLAGS = OCSD_OPFLG_PKTPROC_COMMON;
-
-/***************************************************************************/
-/*******************ETM V4 INSTRUCTION *************************************/
-/***************************************************************************/
-
-TrcPktProcEtmV4I::TrcPktProcEtmV4I() : TrcPktProcBase(ETMV4I_PKTS_NAME),
- m_pProcessor(0)
-{
- m_supported_op_flags = ETMV4_SUPPORTED_OP_FLAGS;
-}
-
-TrcPktProcEtmV4I::TrcPktProcEtmV4I(int instIDNum) : TrcPktProcBase(ETMV4I_PKTS_NAME, instIDNum),
- m_pProcessor(0)
-{
- m_supported_op_flags = ETMV4_SUPPORTED_OP_FLAGS;
-}
-
-TrcPktProcEtmV4I::~TrcPktProcEtmV4I()
-{
- if(m_pProcessor)
- delete m_pProcessor;
- m_pProcessor = 0;
-}
-
-ocsd_err_t TrcPktProcEtmV4I::onProtocolConfig()
-{
- if(m_pProcessor == 0)
- {
- m_pProcessor = new (std::nothrow) EtmV4IPktProcImpl();
- if(m_pProcessor == 0)
- {
- LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_MEM));
- return OCSD_ERR_MEM;
- }
- m_pProcessor->Initialise(this);
- }
- return m_pProcessor->Configure(m_config);
-}
-
-ocsd_datapath_resp_t TrcPktProcEtmV4I::processData( const ocsd_trc_index_t index,
- const uint32_t dataBlockSize,
- const uint8_t *pDataBlock,
- uint32_t *numBytesProcessed)
-{
- if(m_pProcessor)
- return m_pProcessor->processData(index,dataBlockSize,pDataBlock,numBytesProcessed);
- return OCSD_RESP_FATAL_NOT_INIT;
-}
-
-ocsd_datapath_resp_t TrcPktProcEtmV4I::onEOT()
-{
- if(m_pProcessor)
- return m_pProcessor->onEOT();
- return OCSD_RESP_FATAL_NOT_INIT;
-}
-
-ocsd_datapath_resp_t TrcPktProcEtmV4I::onReset()
-{
- if(m_pProcessor)
- return m_pProcessor->onReset();
- return OCSD_RESP_FATAL_NOT_INIT;
-}
-
-ocsd_datapath_resp_t TrcPktProcEtmV4I::onFlush()
-{
- if(m_pProcessor)
- return m_pProcessor->onFlush();
- return OCSD_RESP_FATAL_NOT_INIT;
-}
-
-const bool TrcPktProcEtmV4I::isBadPacket() const
-{
- if(m_pProcessor)
- return m_pProcessor->isBadPacket();
- return false;
-}
-
-/* End of File trc_pkt_proc_etmv4.cpp */
diff --git a/decoder/source/etmv4/trc_pkt_proc_etmv4d_impl.h b/decoder/source/etmv4/trc_pkt_proc_etmv4d_impl.h
deleted file mode 100644
index 3be35bd12b55..000000000000
--- a/decoder/source/etmv4/trc_pkt_proc_etmv4d_impl.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * \file trc_pkt_proc_etmv4d_impl.h
- * \brief OpenCSD :
- *
- * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- * may be used to endorse or promote products derived from this software without
- * specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef ARM_TRC_PKT_PROC_ETMV4D_IMPL_H_INCLUDED
-#define ARM_TRC_PKT_PROC_ETMV4D_IMPL_H_INCLUDED
-
-#include "etmv4/trc_pkt_proc_etmv4.h"
-#include "etmv4/trc_cmp_cfg_etmv4.h"
-
-class EtmV4DPktProcImpl
-{
-public:
- EtmV4DPktProcImpl();
- ~EtmV4DPktProcImpl();
-
- void Initialise(TrcPktProcEtmV4D *p_interface);
-
- ocsd_err_t Configure(const EtmV4Config *p_config);
-
-
- ocsd_datapath_resp_t processData( const ocsd_trc_index_t index,
- const uint32_t dataBlockSize,
- const uint8_t *pDataBlock,
- uint32_t *numBytesProcessed);
- ocsd_datapath_resp_t onEOT();
- ocsd_datapath_resp_t onReset();
- ocsd_datapath_resp_t onFlush();
-
-protected:
-
- bool m_isInit;
- TrcPktProcEtmV4D *m_interface; /**< The interface to the other decode components */
-
- EtmV4Config m_config;
-};
-
-
-#endif // ARM_TRC_PKT_PROC_ETMV4D_IMPL_H_INCLUDED
-
-/* End of File trc_pkt_proc_etmv4d_impl.h */
diff --git a/decoder/source/etmv4/trc_pkt_proc_etmv4i_impl.cpp b/decoder/source/etmv4/trc_pkt_proc_etmv4i.cpp
index 0607c192f879..d8c7d84667d1 100644
--- a/decoder/source/etmv4/trc_pkt_proc_etmv4i_impl.cpp
+++ b/decoder/source/etmv4/trc_pkt_proc_etmv4i.cpp
@@ -1,8 +1,8 @@
/*
- * \file trc_pkt_proc_etmv4i_impl.cpp
- * \brief OpenCSD :
+ * \file trc_pkt_proc_etmv4i.cpp
+ * \brief OpenCSD : Packet processor for ETMv4
*
- * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
+ * \copyright Copyright (c) 2015, 2019, ARM Limited. All Rights Reserved.
*/
/*
@@ -32,87 +32,58 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "trc_pkt_proc_etmv4i_impl.h"
+#include "opencsd/etmv4/trc_pkt_proc_etmv4.h"
+#include "common/ocsd_error.h"
-/* Trace raw input buffer class */
-TraceRawBuffer::TraceRawBuffer()
-{
- m_bufSize = 0;
- m_bufProcessed = 0;
- m_pBuffer = 0;
- pkt = 0;
-}
+#ifdef __GNUC__
+ // G++ doesn't like the ## pasting
+#define ETMV4I_PKTS_NAME "PKTP_ETMV4I"
+#else
+ // VC++ is fine
+#define ETMV4I_PKTS_NAME OCSD_CMPNAME_PREFIX_PKTPROC##"_ETMV4I"
+#endif
-// init the buffer
-void TraceRawBuffer::init(const uint32_t size, const uint8_t *rawtrace, std::vector<uint8_t> *out_packet)
-{
- m_bufSize = size;
- m_bufProcessed = 0;
- m_pBuffer = rawtrace;
- pkt = out_packet;
-}
-
-void TraceRawBuffer::copyByteToPkt()
-{
- if (!empty()) {
- pkt->push_back(m_pBuffer[m_bufProcessed]);
- m_bufProcessed++;
- }
-}
-uint8_t TraceRawBuffer::peekNextByte()
-{
- uint8_t val = 0;
- if (!empty())
- val = m_pBuffer[m_bufProcessed];
- return val;
-}
+static const uint32_t ETMV4_SUPPORTED_OP_FLAGS = OCSD_OPFLG_PKTPROC_COMMON;
/* trace etmv4 packet processing class */
-EtmV4IPktProcImpl::EtmV4IPktProcImpl() :
+TrcPktProcEtmV4I::TrcPktProcEtmV4I() : TrcPktProcBase(ETMV4I_PKTS_NAME),
m_isInit(false),
- m_interface(0),
m_first_trace_info(false)
{
-
+ m_supported_op_flags = ETMV4_SUPPORTED_OP_FLAGS;
}
-EtmV4IPktProcImpl::~EtmV4IPktProcImpl()
+TrcPktProcEtmV4I::TrcPktProcEtmV4I(int instIDNum) : TrcPktProcBase(ETMV4I_PKTS_NAME, instIDNum),
+ m_isInit(false),
+ m_first_trace_info(false)
{
+ m_supported_op_flags = ETMV4_SUPPORTED_OP_FLAGS;
}
-void EtmV4IPktProcImpl::Initialise(TrcPktProcEtmV4I *p_interface)
+
+TrcPktProcEtmV4I::~TrcPktProcEtmV4I()
{
- if(p_interface)
- {
- m_interface = p_interface;
- m_isInit = true;
- }
- InitProcessorState();
}
-ocsd_err_t EtmV4IPktProcImpl::Configure(const EtmV4Config *p_config)
+ocsd_err_t TrcPktProcEtmV4I::onProtocolConfig()
{
- ocsd_err_t err = OCSD_OK;
- if(p_config != 0)
- {
- m_config = *p_config;
- BuildIPacketTable(); // packet table based on config
- }
- else
- {
- err = OCSD_ERR_INVALID_PARAM_VAL;
- if(m_isInit)
- m_interface->LogError(ocsdError(OCSD_ERR_SEV_ERROR,err));
- }
- return err;
+ InitProcessorState();
+ m_config = *TrcPktProcBase::getProtocolConfig();
+ BuildIPacketTable(); // packet table based on config
+ m_isInit = true;
+ return OCSD_OK;
}
-ocsd_datapath_resp_t EtmV4IPktProcImpl::processData( const ocsd_trc_index_t index,
+ocsd_datapath_resp_t TrcPktProcEtmV4I::processData( const ocsd_trc_index_t index,
const uint32_t dataBlockSize,
const uint8_t *pDataBlock,
uint32_t *numBytesProcessed)
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+
+ if (!m_isInit)
+ return OCSD_RESP_FATAL_NOT_INIT;
+
m_trcIn.init(dataBlockSize, pDataBlock, &m_currPacketData);
m_blockIndex = index;
bool done = false;
@@ -122,9 +93,6 @@ ocsd_datapath_resp_t EtmV4IPktProcImpl::processData( const ocsd_trc_index_t ind
{
try
{
- /* while (((m_blockBytesProcessed < dataBlockSize) ||
- ((m_blockBytesProcessed == dataBlockSize) && (m_process_state == SEND_PKT))) &&
- OCSD_DATA_RESP_IS_CONT(resp))*/
while ( (!m_trcIn.empty() || (m_process_state == SEND_PKT)) &&
OCSD_DATA_RESP_IS_CONT(resp)
)
@@ -142,7 +110,7 @@ ocsd_datapath_resp_t EtmV4IPktProcImpl::processData( const ocsd_trc_index_t ind
else
{
// unsynced - process data until we see a sync point
- m_pIPktFn = &EtmV4IPktProcImpl::iNotSync;
+ m_pIPktFn = &TrcPktProcEtmV4I::iNotSync;
m_curr_packet.type = ETM4_PKT_I_NOTSYNC;
}
m_process_state = PROC_DATA;
@@ -153,8 +121,6 @@ ocsd_datapath_resp_t EtmV4IPktProcImpl::processData( const ocsd_trc_index_t ind
{
nextByte = m_trcIn.peekNextByte();
m_trcIn.copyByteToPkt(); // move next byte into the packet
- // m_currPacketData.push_back(pDataBlock[m_blockBytesProcessed]);
- // m_blockBytesProcessed++;
(this->*m_pIPktFn)(nextByte);
}
break;
@@ -181,7 +147,7 @@ ocsd_datapath_resp_t EtmV4IPktProcImpl::processData( const ocsd_trc_index_t ind
catch(ocsdError &err)
{
done = true;
- m_interface->LogError(err);
+ LogError(err);
if( (err.getErrorCode() == OCSD_ERR_BAD_PACKET_SEQ) ||
(err.getErrorCode() == OCSD_ERR_INVALID_PCKT_HDR))
{
@@ -201,7 +167,7 @@ ocsd_datapath_resp_t EtmV4IPktProcImpl::processData( const ocsd_trc_index_t ind
/// vv bad at this point.
resp = OCSD_RESP_FATAL_SYS_ERR;
const ocsdError &fatal = ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_FAIL,m_packet_index,m_config.getTraceID(),"Unknown System Error decoding trace.");
- m_interface->LogError(fatal);
+ LogError(fatal);
}
} while (!done);
@@ -209,9 +175,12 @@ ocsd_datapath_resp_t EtmV4IPktProcImpl::processData( const ocsd_trc_index_t ind
return resp;
}
-ocsd_datapath_resp_t EtmV4IPktProcImpl::onEOT()
+ocsd_datapath_resp_t TrcPktProcEtmV4I::onEOT()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ if (!m_isInit)
+ return OCSD_RESP_FATAL_NOT_INIT;
+
// if we have a partial packet then send to attached sinks
if(m_currPacketData.size() != 0)
{
@@ -222,31 +191,37 @@ ocsd_datapath_resp_t EtmV4IPktProcImpl::onEOT()
return resp;
}
-ocsd_datapath_resp_t EtmV4IPktProcImpl::onReset()
+ocsd_datapath_resp_t TrcPktProcEtmV4I::onReset()
{
+ if (!m_isInit)
+ return OCSD_RESP_FATAL_NOT_INIT;
+
// prepare for new decoding session
InitProcessorState();
return OCSD_RESP_CONT;
}
-ocsd_datapath_resp_t EtmV4IPktProcImpl::onFlush()
+ocsd_datapath_resp_t TrcPktProcEtmV4I::onFlush()
{
+ if (!m_isInit)
+ return OCSD_RESP_FATAL_NOT_INIT;
+
// packet processor never holds on to flushable data (may have partial packet,
// but any full packets are immediately sent)
return OCSD_RESP_CONT;
}
-void EtmV4IPktProcImpl::InitPacketState()
+void TrcPktProcEtmV4I::InitPacketState()
{
m_currPacketData.clear();
m_curr_packet.initNextPacket(); // clear for next packet.
m_update_on_unsync_packet_index = 0;
}
-void EtmV4IPktProcImpl::InitProcessorState()
+void TrcPktProcEtmV4I::InitProcessorState()
{
InitPacketState();
- m_pIPktFn = &EtmV4IPktProcImpl::iNotSync;
+ m_pIPktFn = &TrcPktProcEtmV4I::iNotSync;
m_packet_index = 0;
m_is_sync = false;
m_first_trace_info = false;
@@ -255,23 +230,23 @@ void EtmV4IPktProcImpl::InitProcessorState()
m_curr_packet.initStartState();
}
-ocsd_datapath_resp_t EtmV4IPktProcImpl::outputPacket()
+ocsd_datapath_resp_t TrcPktProcEtmV4I::outputPacket()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
- resp = m_interface->outputOnAllInterfaces(m_packet_index,&m_curr_packet,&m_curr_packet.type,m_currPacketData);
+ resp = outputOnAllInterfaces(m_packet_index,&m_curr_packet,&m_curr_packet.type,m_currPacketData);
return resp;
}
-ocsd_datapath_resp_t EtmV4IPktProcImpl::outputUnsyncedRawPacket()
+ocsd_datapath_resp_t TrcPktProcEtmV4I::outputUnsyncedRawPacket()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
- m_interface->outputRawPacketToMonitor(m_packet_index,&m_curr_packet,m_dump_unsynced_bytes,&m_currPacketData[0]);
+ outputRawPacketToMonitor(m_packet_index,&m_curr_packet,m_dump_unsynced_bytes,&m_currPacketData[0]);
if(!m_sent_notsync_packet)
{
- resp = m_interface->outputDecodedPacket(m_packet_index,&m_curr_packet);
+ resp = outputDecodedPacket(m_packet_index,&m_curr_packet);
m_sent_notsync_packet = true;
}
@@ -283,7 +258,7 @@ ocsd_datapath_resp_t EtmV4IPktProcImpl::outputUnsyncedRawPacket()
return resp;
}
-void EtmV4IPktProcImpl::iNotSync(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iNotSync(const uint8_t lastByte)
{
// is it an extension byte?
if (lastByte == 0x00) // TBD : add check for forced sync in here?
@@ -309,7 +284,7 @@ void EtmV4IPktProcImpl::iNotSync(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktNoPayload(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktNoPayload(const uint8_t lastByte)
{
// some expansion may be required...
switch(m_curr_packet.type)
@@ -338,26 +313,26 @@ void EtmV4IPktProcImpl::iPktNoPayload(const uint8_t lastByte)
m_process_state = SEND_PKT; // now just send it....
}
-void EtmV4IPktProcImpl::iPktReserved(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktReserved(const uint8_t lastByte)
{
m_curr_packet.updateErrType(ETM4_PKT_I_RESERVED, lastByte); // swap type for err type
throw ocsdError(OCSD_ERR_SEV_ERROR, OCSD_ERR_INVALID_PCKT_HDR,m_packet_index,m_config.getTraceID());
}
-void EtmV4IPktProcImpl::iPktInvalidCfg(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktInvalidCfg(const uint8_t lastByte)
{
m_curr_packet.updateErrType(ETM4_PKT_I_RESERVED_CFG, lastByte); // swap type for err type
throw ocsdError(OCSD_ERR_SEV_ERROR, OCSD_ERR_INVALID_PCKT_HDR, m_packet_index, m_config.getTraceID());
}
-void EtmV4IPktProcImpl::iPktExtension(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktExtension(const uint8_t lastByte)
{
if(m_currPacketData.size() == 2)
{
// not sync and not next by 0x00 - not sync sequence
if(!m_is_sync && (lastByte != 0x00))
{
- m_pIPktFn = &EtmV4IPktProcImpl::iNotSync;
+ m_pIPktFn = &TrcPktProcEtmV4I::iNotSync;
m_curr_packet.type = ETM4_PKT_I_NOTSYNC;
return;
}
@@ -376,7 +351,7 @@ void EtmV4IPktProcImpl::iPktExtension(const uint8_t lastByte)
case 0x00:
m_curr_packet.type = ETM4_PKT_I_ASYNC;
- m_pIPktFn = &EtmV4IPktProcImpl::iPktASync; // handle subsequent bytes as async
+ m_pIPktFn = &TrcPktProcEtmV4I::iPktASync; // handle subsequent bytes as async
break;
default:
@@ -388,14 +363,14 @@ void EtmV4IPktProcImpl::iPktExtension(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktASync(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktASync(const uint8_t lastByte)
{
if(lastByte != 0x00)
{
// not sync and not next by 0x00 - not sync sequence if < 12
if(!m_is_sync && m_currPacketData.size() != 12)
{
- m_pIPktFn = &EtmV4IPktProcImpl::iNotSync;
+ m_pIPktFn = &TrcPktProcEtmV4I::iNotSync;
m_curr_packet.type = ETM4_PKT_I_NOTSYNC;
return;
}
@@ -428,7 +403,7 @@ void EtmV4IPktProcImpl::iPktASync(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktTraceInfo(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktTraceInfo(const uint8_t lastByte)
{
if(m_currPacketData.size() == 1) // header
{
@@ -500,7 +475,7 @@ void EtmV4IPktProcImpl::iPktTraceInfo(const uint8_t lastByte)
}
-void EtmV4IPktProcImpl::iPktTimestamp(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktTimestamp(const uint8_t lastByte)
{
// process the header byte
if(m_currPacketData.size() == 1)
@@ -550,7 +525,7 @@ void EtmV4IPktProcImpl::iPktTimestamp(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktException(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktException(const uint8_t lastByte)
{
uint16_t excep_type = 0;
@@ -582,7 +557,7 @@ void EtmV4IPktProcImpl::iPktException(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktCycleCntF123(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktCycleCntF123(const uint8_t lastByte)
{
ocsd_etmv4_i_pkt_type format = m_curr_packet.type;
@@ -657,7 +632,7 @@ void EtmV4IPktProcImpl::iPktCycleCntF123(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktSpeclRes(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktSpeclRes(const uint8_t lastByte)
{
if(m_currPacketData.size() == 1)
{
@@ -671,8 +646,10 @@ void EtmV4IPktProcImpl::iPktSpeclRes(const uint8_t lastByte)
case 0x2: m_curr_packet.setAtomPacket(ATOM_PATTERN, 0x3, 2); break; // EE
case 0x3: m_curr_packet.setAtomPacket(ATOM_PATTERN, 0x0, 1); break; // N
}
- if(m_curr_packet.getType() == ETM4_PKT_I_CANCEL_F2)
+ if (m_curr_packet.getType() == ETM4_PKT_I_CANCEL_F2)
m_curr_packet.setCancelElements(1);
+ else
+ m_curr_packet.setCancelElements(0);
m_process_state = SEND_PKT;
break;
@@ -694,13 +671,12 @@ void EtmV4IPktProcImpl::iPktSpeclRes(const uint8_t lastByte)
m_curr_packet.setCommitElements(field_val);
else
m_curr_packet.setCancelElements(field_val);
- // TBD: sanity check with max spec depth here?
m_process_state = SEND_PKT;
}
}
}
-void EtmV4IPktProcImpl::iPktCondInstr(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktCondInstr(const uint8_t lastByte)
{
bool bF1Done = false;
@@ -740,7 +716,7 @@ void EtmV4IPktProcImpl::iPktCondInstr(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktCondResult(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktCondResult(const uint8_t lastByte)
{
if(m_currPacketData.size() == 1)
{
@@ -810,7 +786,7 @@ void EtmV4IPktProcImpl::iPktCondResult(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktContext(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktContext(const uint8_t lastByte)
{
bool bSendPacket = false;
@@ -852,7 +828,7 @@ void EtmV4IPktProcImpl::iPktContext(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::extractAndSetContextInfo(const std::vector<uint8_t> &buffer, const int st_idx)
+void TrcPktProcEtmV4I::extractAndSetContextInfo(const std::vector<uint8_t> &buffer, const int st_idx)
{
// on input, buffer index points at the info byte - always present
uint8_t infoByte = m_currPacketData[st_idx];
@@ -887,7 +863,7 @@ void EtmV4IPktProcImpl::extractAndSetContextInfo(const std::vector<uint8_t> &buf
}
}
-void EtmV4IPktProcImpl::iPktAddrCtxt(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktAddrCtxt(const uint8_t lastByte)
{
if( m_currPacketData.size() == 1)
{
@@ -955,7 +931,7 @@ void EtmV4IPktProcImpl::iPktAddrCtxt(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktShortAddr(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktShortAddr(const uint8_t lastByte)
{
if (m_currPacketData.size() == 1)
{
@@ -980,7 +956,7 @@ void EtmV4IPktProcImpl::iPktShortAddr(const uint8_t lastByte)
}
}
-int EtmV4IPktProcImpl::extractShortAddr(const std::vector<uint8_t> &buffer, const int st_idx, const uint8_t IS, uint32_t &value, int &bits)
+int TrcPktProcEtmV4I::extractShortAddr(const std::vector<uint8_t> &buffer, const int st_idx, const uint8_t IS, uint32_t &value, int &bits)
{
int IS_shift = (IS == 0) ? 2 : 1;
int idx = 0;
@@ -1000,7 +976,7 @@ int EtmV4IPktProcImpl::extractShortAddr(const std::vector<uint8_t> &buffer, cons
return idx;
}
-void EtmV4IPktProcImpl::iPktLongAddr(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktLongAddr(const uint8_t lastByte)
{
if(m_currPacketData.size() == 1)
{
@@ -1044,7 +1020,7 @@ void EtmV4IPktProcImpl::iPktLongAddr(const uint8_t lastByte)
}
}
-void EtmV4IPktProcImpl::iPktQ(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iPktQ(const uint8_t lastByte)
{
if(m_currPacketData.size() == 1)
{
@@ -1096,7 +1072,7 @@ void EtmV4IPktProcImpl::iPktQ(const uint8_t lastByte)
default:
m_curr_packet.err_type = m_curr_packet.type;
m_curr_packet.type = ETM4_PKT_I_BAD_SEQUENCE;
- //SendBadIPacket( PKT_BAD_SEQUENCE, "ERROR: Bad Q packet type", PKT_Q );
+ m_process_state = SEND_PKT;
break;
}
}
@@ -1156,7 +1132,7 @@ void EtmV4IPktProcImpl::iPktQ(const uint8_t lastByte)
}
-void EtmV4IPktProcImpl::iAtom(const uint8_t lastByte)
+void TrcPktProcEtmV4I::iAtom(const uint8_t lastByte)
{
// patterns lsbit = oldest atom, ms bit = newest.
static const uint32_t f4_patterns[] = {
@@ -1228,32 +1204,32 @@ void EtmV4IPktProcImpl::iAtom(const uint8_t lastByte)
}
// header byte processing is table driven.
-void EtmV4IPktProcImpl::BuildIPacketTable()
+void TrcPktProcEtmV4I::BuildIPacketTable()
{
// initialise everything as reserved.
for(int i = 0; i < 256; i++)
{
m_i_table[i].pkt_type = ETM4_PKT_I_RESERVED;
- m_i_table[i].pptkFn = &EtmV4IPktProcImpl::iPktReserved;
+ m_i_table[i].pptkFn = &TrcPktProcEtmV4I::iPktReserved;
}
// 0x00 - extension
m_i_table[0x00].pkt_type = ETM4_PKT_I_EXTENSION;
- m_i_table[0x00].pptkFn = &EtmV4IPktProcImpl::iPktExtension;
+ m_i_table[0x00].pptkFn = &TrcPktProcEtmV4I::iPktExtension;
// 0x01 - Trace info
m_i_table[0x01].pkt_type = ETM4_PKT_I_TRACE_INFO;
- m_i_table[0x01].pptkFn = &EtmV4IPktProcImpl::iPktTraceInfo;
+ m_i_table[0x01].pptkFn = &TrcPktProcEtmV4I::iPktTraceInfo;
// b0000001x - timestamp
m_i_table[0x02].pkt_type = ETM4_PKT_I_TIMESTAMP;
- m_i_table[0x02].pptkFn = &EtmV4IPktProcImpl::iPktTimestamp;
+ m_i_table[0x02].pptkFn = &TrcPktProcEtmV4I::iPktTimestamp;
m_i_table[0x03].pkt_type = ETM4_PKT_I_TIMESTAMP;
- m_i_table[0x03].pptkFn = &EtmV4IPktProcImpl::iPktTimestamp;
+ m_i_table[0x03].pptkFn = &TrcPktProcEtmV4I::iPktTimestamp;
// b0000 0100 - trace on
m_i_table[0x04].pkt_type = ETM4_PKT_I_TRACE_ON;
- m_i_table[0x04].pptkFn = &EtmV4IPktProcImpl::iPktNoPayload;
+ m_i_table[0x04].pptkFn = &TrcPktProcEtmV4I::iPktNoPayload;
// b0000 0101 - Funct ret V8M
@@ -1262,30 +1238,30 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
(OCSD_IS_V8_ARCH(m_config.archVersion())) &&
(m_config.FullVersion() >= 0x42))
{
- m_i_table[0x05].pptkFn = &EtmV4IPktProcImpl::iPktNoPayload;
+ m_i_table[0x05].pptkFn = &TrcPktProcEtmV4I::iPktNoPayload;
}
// b0000 0110 - exception
m_i_table[0x06].pkt_type = ETM4_PKT_I_EXCEPT;
- m_i_table[0x06].pptkFn = &EtmV4IPktProcImpl::iPktException;
+ m_i_table[0x06].pptkFn = &TrcPktProcEtmV4I::iPktException;
// b0000 0111 - exception return
m_i_table[0x07].pkt_type = ETM4_PKT_I_EXCEPT_RTN;
- m_i_table[0x07].pptkFn = &EtmV4IPktProcImpl::iPktNoPayload;
+ m_i_table[0x07].pptkFn = &TrcPktProcEtmV4I::iPktNoPayload;
// b0000 110x - cycle count f2
// b0000 111x - cycle count f1
for(int i = 0; i < 4; i++)
{
m_i_table[0x0C+i].pkt_type = (i >= 2) ? ETM4_PKT_I_CCNT_F1 : ETM4_PKT_I_CCNT_F2;
- m_i_table[0x0C+i].pptkFn = &EtmV4IPktProcImpl::iPktCycleCntF123;
+ m_i_table[0x0C+i].pptkFn = &TrcPktProcEtmV4I::iPktCycleCntF123;
}
// b0001 xxxx - cycle count f3
for(int i = 0; i < 16; i++)
{
m_i_table[0x10+i].pkt_type = ETM4_PKT_I_CCNT_F3;
- m_i_table[0x10+i].pptkFn = &EtmV4IPktProcImpl::iPktCycleCntF123;
+ m_i_table[0x10+i].pptkFn = &TrcPktProcEtmV4I::iPktCycleCntF123;
}
// b0010 0xxx - NDSM
@@ -1293,9 +1269,9 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
{
m_i_table[0x20 + i].pkt_type = ETM4_PKT_I_NUM_DS_MKR;
if (m_config.enabledDataTrace())
- m_i_table[0x20+i].pptkFn = &EtmV4IPktProcImpl::iPktNoPayload;
+ m_i_table[0x20+i].pptkFn = &TrcPktProcEtmV4I::iPktNoPayload;
else
- m_i_table[0x20+i].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x20+i].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
}
// b0010 10xx, b0010 1100 - UDSM
@@ -1303,43 +1279,40 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
{
m_i_table[0x28+i].pkt_type = ETM4_PKT_I_UNNUM_DS_MKR;
if (m_config.enabledDataTrace())
- m_i_table[0x28+i].pptkFn = &EtmV4IPktProcImpl::iPktNoPayload;
+ m_i_table[0x28+i].pptkFn = &TrcPktProcEtmV4I::iPktNoPayload;
else
- m_i_table[0x28+i].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x28+i].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
}
// b0010 1101 - commit
m_i_table[0x2D].pkt_type = ETM4_PKT_I_COMMIT;
- m_i_table[0x2D].pptkFn = &EtmV4IPktProcImpl::iPktSpeclRes;
+ m_i_table[0x2D].pptkFn = &TrcPktProcEtmV4I::iPktSpeclRes;
- // b0010 111x - cancel f1
- for(int i = 0; i < 2; i++)
- {
- // G++ doesn't understand [0x2E+i] so...
- int idx = i + 0x2E;
- m_i_table[idx].pkt_type = ETM4_PKT_I_CANCEL_F1;
- m_i_table[idx].pptkFn = &EtmV4IPktProcImpl::iPktSpeclRes;
- }
+ // b0010 111x - cancel f1 (mis pred)
+ m_i_table[0x2E].pkt_type = ETM4_PKT_I_CANCEL_F1;
+ m_i_table[0x2E].pptkFn = &TrcPktProcEtmV4I::iPktSpeclRes;
+ m_i_table[0x2F].pkt_type = ETM4_PKT_I_CANCEL_F1_MISPRED;
+ m_i_table[0x2F].pptkFn = &TrcPktProcEtmV4I::iPktSpeclRes;
// b0011 00xx - mis predict
for(int i = 0; i < 4; i++)
{
m_i_table[0x30+i].pkt_type = ETM4_PKT_I_MISPREDICT;
- m_i_table[0x30+i].pptkFn = &EtmV4IPktProcImpl::iPktSpeclRes;
+ m_i_table[0x30+i].pptkFn = &TrcPktProcEtmV4I::iPktSpeclRes;
}
// b0011 01xx - cancel f2
for(int i = 0; i < 4; i++)
{
m_i_table[0x34+i].pkt_type = ETM4_PKT_I_CANCEL_F2;
- m_i_table[0x34+i].pptkFn = &EtmV4IPktProcImpl::iPktSpeclRes;
+ m_i_table[0x34+i].pptkFn = &TrcPktProcEtmV4I::iPktSpeclRes;
}
// b0011 1xxx - cancel f3
for(int i = 0; i < 8; i++)
{
m_i_table[0x38+i].pkt_type = ETM4_PKT_I_CANCEL_F3;
- m_i_table[0x38+i].pptkFn = &EtmV4IPktProcImpl::iPktSpeclRes;
+ m_i_table[0x38+i].pptkFn = &TrcPktProcEtmV4I::iPktSpeclRes;
}
bool bCondValid = m_config.hasCondTrace() && m_config.enabledCondITrace();
@@ -1349,26 +1322,26 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
{
m_i_table[0x40 + i].pkt_type = ETM4_PKT_I_COND_I_F2;
if (bCondValid)
- m_i_table[0x40 + i].pptkFn = &EtmV4IPktProcImpl::iPktCondInstr;
+ m_i_table[0x40 + i].pptkFn = &TrcPktProcEtmV4I::iPktCondInstr;
else
- m_i_table[0x40 + i].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x40 + i].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
}
// b0100 0011 - cond flush
m_i_table[0x43].pkt_type = ETM4_PKT_I_COND_FLUSH;
if (bCondValid)
- m_i_table[0x43].pptkFn = &EtmV4IPktProcImpl::iPktNoPayload;
+ m_i_table[0x43].pptkFn = &TrcPktProcEtmV4I::iPktNoPayload;
else
- m_i_table[0x43].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x43].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
// b0100 010x, b0100 0110 - cond res f4
for (int i = 0; i < 3; i++)
{
m_i_table[0x44 + i].pkt_type = ETM4_PKT_I_COND_RES_F4;
if (bCondValid)
- m_i_table[0x44 + i].pptkFn = &EtmV4IPktProcImpl::iPktCondResult;
+ m_i_table[0x44 + i].pptkFn = &TrcPktProcEtmV4I::iPktCondResult;
else
- m_i_table[0x44 + i].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x44 + i].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
}
// b0100 100x, b0100 0110 - cond res f2
@@ -1377,17 +1350,17 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
{
m_i_table[0x48 + i].pkt_type = ETM4_PKT_I_COND_RES_F2;
if (bCondValid)
- m_i_table[0x48 + i].pptkFn = &EtmV4IPktProcImpl::iPktCondResult;
+ m_i_table[0x48 + i].pptkFn = &TrcPktProcEtmV4I::iPktCondResult;
else
- m_i_table[0x48 + i].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x48 + i].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
}
for (int i = 0; i < 3; i++)
{
m_i_table[0x4C + i].pkt_type = ETM4_PKT_I_COND_RES_F2;
if (bCondValid)
- m_i_table[0x4C + i].pptkFn = &EtmV4IPktProcImpl::iPktCondResult;
+ m_i_table[0x4C + i].pptkFn = &TrcPktProcEtmV4I::iPktCondResult;
else
- m_i_table[0x4C + i].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x4C + i].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
}
// b0101xxxx - cond res f3
@@ -1395,9 +1368,9 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
{
m_i_table[0x50 + i].pkt_type = ETM4_PKT_I_COND_RES_F3;
if (bCondValid)
- m_i_table[0x50 + i].pptkFn = &EtmV4IPktProcImpl::iPktCondResult;
+ m_i_table[0x50 + i].pptkFn = &TrcPktProcEtmV4I::iPktCondResult;
else
- m_i_table[0x50 + i].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x50 + i].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
}
// b011010xx - cond res f1
@@ -1405,24 +1378,24 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
{
m_i_table[0x68 + i].pkt_type = ETM4_PKT_I_COND_RES_F1;
if (bCondValid)
- m_i_table[0x68 + i].pptkFn = &EtmV4IPktProcImpl::iPktCondResult;
+ m_i_table[0x68 + i].pptkFn = &TrcPktProcEtmV4I::iPktCondResult;
else
- m_i_table[0x68 + i].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x68 + i].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
}
// b0110 1100 - cond instr f1
m_i_table[0x6C].pkt_type = ETM4_PKT_I_COND_I_F1;
if (bCondValid)
- m_i_table[0x6C].pptkFn = &EtmV4IPktProcImpl::iPktCondInstr;
+ m_i_table[0x6C].pptkFn = &TrcPktProcEtmV4I::iPktCondInstr;
else
- m_i_table[0x6C].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x6C].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
// b0110 1101 - cond instr f3
m_i_table[0x6D].pkt_type = ETM4_PKT_I_COND_I_F3;
if (bCondValid)
- m_i_table[0x6D].pptkFn = &EtmV4IPktProcImpl::iPktCondInstr;
+ m_i_table[0x6D].pptkFn = &TrcPktProcEtmV4I::iPktCondInstr;
else
- m_i_table[0x6D].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[0x6D].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
// b0110111x - cond res f1
for (int i = 0; i < 2; i++)
@@ -1430,30 +1403,30 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
// G++ cannot understand [0x6E+i] so change these round
m_i_table[i + 0x6E].pkt_type = ETM4_PKT_I_COND_RES_F1;
if (bCondValid)
- m_i_table[i + 0x6E].pptkFn = &EtmV4IPktProcImpl::iPktCondResult;
+ m_i_table[i + 0x6E].pptkFn = &TrcPktProcEtmV4I::iPktCondResult;
else
- m_i_table[i + 0x6E].pptkFn = &EtmV4IPktProcImpl::iPktInvalidCfg;
+ m_i_table[i + 0x6E].pptkFn = &TrcPktProcEtmV4I::iPktInvalidCfg;
}
// ETM 4.3 introduces ignore packets
if (m_config.FullVersion() >= 0x43)
{
m_i_table[0x70].pkt_type = ETM4_PKT_I_IGNORE;
- m_i_table[0x70].pptkFn = &EtmV4IPktProcImpl::iPktNoPayload;
+ m_i_table[0x70].pptkFn = &TrcPktProcEtmV4I::iPktNoPayload;
}
// b01110001 - b01111111 - event trace
for(int i = 0; i < 15; i++)
{
m_i_table[0x71+i].pkt_type = ETM4_PKT_I_EVENT;
- m_i_table[0x71+i].pptkFn = &EtmV4IPktProcImpl::iPktNoPayload;
+ m_i_table[0x71+i].pptkFn = &TrcPktProcEtmV4I::iPktNoPayload;
}
// 0b1000 000x - context
for(int i = 0; i < 2; i++)
{
m_i_table[0x80+i].pkt_type = ETM4_PKT_I_CTXT;
- m_i_table[0x80+i].pptkFn = &EtmV4IPktProcImpl::iPktContext;
+ m_i_table[0x80+i].pptkFn = &TrcPktProcEtmV4I::iPktContext;
}
// 0b1000 0010 to b1000 0011 - addr with ctxt
@@ -1461,27 +1434,27 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
for(int i = 0; i < 2; i++)
{
m_i_table[0x82+i].pkt_type = (i == 0) ? ETM4_PKT_I_ADDR_CTXT_L_32IS0 : ETM4_PKT_I_ADDR_CTXT_L_32IS1;
- m_i_table[0x82+i].pptkFn = &EtmV4IPktProcImpl::iPktAddrCtxt;
+ m_i_table[0x82+i].pptkFn = &TrcPktProcEtmV4I::iPktAddrCtxt;
}
for(int i = 0; i < 2; i++)
{
m_i_table[0x85+i].pkt_type = (i == 0) ? ETM4_PKT_I_ADDR_CTXT_L_64IS0 : ETM4_PKT_I_ADDR_CTXT_L_64IS1;
- m_i_table[0x85+i].pptkFn = &EtmV4IPktProcImpl::iPktAddrCtxt;
+ m_i_table[0x85+i].pptkFn = &TrcPktProcEtmV4I::iPktAddrCtxt;
}
// 0b1001 0000 to b1001 0010 - exact match addr
for(int i = 0; i < 3; i++)
{
m_i_table[0x90+i].pkt_type = ETM4_PKT_I_ADDR_MATCH;
- m_i_table[0x90+i].pptkFn = &EtmV4IPktProcImpl::iPktNoPayload;
+ m_i_table[0x90+i].pptkFn = &TrcPktProcEtmV4I::iPktNoPayload;
}
// b1001 0101 - b1001 0110 - addr short address
for(int i = 0; i < 2; i++)
{
m_i_table[0x95+i].pkt_type = (i == 0) ? ETM4_PKT_I_ADDR_S_IS0 : ETM4_PKT_I_ADDR_S_IS1;
- m_i_table[0x95+i].pptkFn = &EtmV4IPktProcImpl::iPktShortAddr;
+ m_i_table[0x95+i].pptkFn = &TrcPktProcEtmV4I::iPktShortAddr;
}
// b10011010 - b10011011 - addr long address
@@ -1489,12 +1462,12 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
for(int i = 0; i < 2; i++)
{
m_i_table[0x9A+i].pkt_type = (i == 0) ? ETM4_PKT_I_ADDR_L_32IS0 : ETM4_PKT_I_ADDR_L_32IS1;
- m_i_table[0x9A+i].pptkFn = &EtmV4IPktProcImpl::iPktLongAddr;
+ m_i_table[0x9A+i].pptkFn = &TrcPktProcEtmV4I::iPktLongAddr;
}
for(int i = 0; i < 2; i++)
{
m_i_table[0x9D+i].pkt_type = (i == 0) ? ETM4_PKT_I_ADDR_L_64IS0 : ETM4_PKT_I_ADDR_L_64IS1;
- m_i_table[0x9D+i].pptkFn = &EtmV4IPktProcImpl::iPktLongAddr;
+ m_i_table[0x9D+i].pptkFn = &TrcPktProcEtmV4I::iPktLongAddr;
}
// b1010xxxx - Q packet
@@ -1515,7 +1488,7 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
default:
// if this config supports Q elem - otherwise reserved again.
if (m_config.hasQElem())
- m_i_table[0xA0 + i].pptkFn = &EtmV4IPktProcImpl::iPktQ;
+ m_i_table[0xA0 + i].pptkFn = &TrcPktProcEtmV4I::iPktQ;
}
}
@@ -1523,46 +1496,46 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
for(int i = 0xC0; i <= 0xD4; i++) // atom f6
{
m_i_table[i].pkt_type = ETM4_PKT_I_ATOM_F6;
- m_i_table[i].pptkFn = &EtmV4IPktProcImpl::iAtom;
+ m_i_table[i].pptkFn = &TrcPktProcEtmV4I::iAtom;
}
for(int i = 0xD5; i <= 0xD7; i++) // atom f5
{
m_i_table[i].pkt_type = ETM4_PKT_I_ATOM_F5;
- m_i_table[i].pptkFn = &EtmV4IPktProcImpl::iAtom;
+ m_i_table[i].pptkFn = &TrcPktProcEtmV4I::iAtom;
}
for(int i = 0xD8; i <= 0xDB; i++) // atom f2
{
m_i_table[i].pkt_type = ETM4_PKT_I_ATOM_F2;
- m_i_table[i].pptkFn = &EtmV4IPktProcImpl::iAtom;
+ m_i_table[i].pptkFn = &TrcPktProcEtmV4I::iAtom;
}
for(int i = 0xDC; i <= 0xDF; i++) // atom f4
{
m_i_table[i].pkt_type = ETM4_PKT_I_ATOM_F4;
- m_i_table[i].pptkFn = &EtmV4IPktProcImpl::iAtom;
+ m_i_table[i].pptkFn = &TrcPktProcEtmV4I::iAtom;
}
for(int i = 0xE0; i <= 0xF4; i++) // atom f6
{
m_i_table[i].pkt_type = ETM4_PKT_I_ATOM_F6;
- m_i_table[i].pptkFn = &EtmV4IPktProcImpl::iAtom;
+ m_i_table[i].pptkFn = &TrcPktProcEtmV4I::iAtom;
}
// atom f5
m_i_table[0xF5].pkt_type = ETM4_PKT_I_ATOM_F5;
- m_i_table[0xF5].pptkFn = &EtmV4IPktProcImpl::iAtom;
+ m_i_table[0xF5].pptkFn = &TrcPktProcEtmV4I::iAtom;
for(int i = 0xF6; i <= 0xF7; i++) // atom f1
{
m_i_table[i].pkt_type = ETM4_PKT_I_ATOM_F1;
- m_i_table[i].pptkFn = &EtmV4IPktProcImpl::iAtom;
+ m_i_table[i].pptkFn = &TrcPktProcEtmV4I::iAtom;
}
for(int i = 0xF8; i <= 0xFF; i++) // atom f3
{
m_i_table[i].pkt_type = ETM4_PKT_I_ATOM_F3;
- m_i_table[i].pptkFn = &EtmV4IPktProcImpl::iAtom;
+ m_i_table[i].pptkFn = &TrcPktProcEtmV4I::iAtom;
}
}
- unsigned EtmV4IPktProcImpl::extractContField(const std::vector<uint8_t> &buffer, const unsigned st_idx, uint32_t &value, const unsigned byte_limit /*= 5*/)
+ unsigned TrcPktProcEtmV4I::extractContField(const std::vector<uint8_t> &buffer, const unsigned st_idx, uint32_t &value, const unsigned byte_limit /*= 5*/)
{
unsigned idx = 0;
bool lastByte = false;
@@ -1586,7 +1559,7 @@ void EtmV4IPktProcImpl::BuildIPacketTable()
return idx;
}
-unsigned EtmV4IPktProcImpl::extractContField64(const std::vector<uint8_t> &buffer, const unsigned st_idx, uint64_t &value, const unsigned byte_limit /*= 9*/)
+unsigned TrcPktProcEtmV4I::extractContField64(const std::vector<uint8_t> &buffer, const unsigned st_idx, uint64_t &value, const unsigned byte_limit /*= 9*/)
{
unsigned idx = 0;
bool lastByte = false;
@@ -1610,7 +1583,7 @@ unsigned EtmV4IPktProcImpl::extractContField64(const std::vector<uint8_t> &buffe
return idx;
}
- unsigned EtmV4IPktProcImpl::extractCondResult(const std::vector<uint8_t> &buffer, const unsigned st_idx, uint32_t& key, uint8_t &result)
+ unsigned TrcPktProcEtmV4I::extractCondResult(const std::vector<uint8_t> &buffer, const unsigned st_idx, uint32_t& key, uint8_t &result)
{
unsigned idx = 0;
bool lastByte = false;
@@ -1644,7 +1617,7 @@ unsigned EtmV4IPktProcImpl::extractContField64(const std::vector<uint8_t> &buffe
return idx;
}
-int EtmV4IPktProcImpl::extract64BitLongAddr(const std::vector<uint8_t> &buffer, const int st_idx, const uint8_t IS, uint64_t &value)
+int TrcPktProcEtmV4I::extract64BitLongAddr(const std::vector<uint8_t> &buffer, const int st_idx, const uint8_t IS, uint64_t &value)
{
value = 0;
if(IS == 0)
@@ -1666,7 +1639,7 @@ int EtmV4IPktProcImpl::extract64BitLongAddr(const std::vector<uint8_t> &buffer,
return 8;
}
-int EtmV4IPktProcImpl::extract32BitLongAddr(const std::vector<uint8_t> &buffer, const int st_idx, const uint8_t IS, uint32_t &value)
+int TrcPktProcEtmV4I::extract32BitLongAddr(const std::vector<uint8_t> &buffer, const int st_idx, const uint8_t IS, uint32_t &value)
{
value = 0;
if(IS == 0)
@@ -1684,11 +1657,11 @@ int EtmV4IPktProcImpl::extract32BitLongAddr(const std::vector<uint8_t> &buffer,
return 4;
}
-void EtmV4IPktProcImpl::throwBadSequenceError(const char *pszExtMsg)
+void TrcPktProcEtmV4I::throwBadSequenceError(const char *pszExtMsg)
{
m_curr_packet.updateErrType(ETM4_PKT_I_BAD_SEQUENCE); // swap type for err type
throw ocsdError(OCSD_ERR_SEV_ERROR, OCSD_ERR_BAD_PACKET_SEQ,m_packet_index,m_config.getTraceID(),pszExtMsg);
}
-/* End of File trc_pkt_proc_etmv4i_impl.cpp */
+/* End of File trc_pkt_proc_etmv4i.cpp */
diff --git a/decoder/source/i_dec/trc_i_decode.cpp b/decoder/source/i_dec/trc_i_decode.cpp
index ab93284848bb..614fc1d8b45c 100644
--- a/decoder/source/i_dec/trc_i_decode.cpp
+++ b/decoder/source/i_dec/trc_i_decode.cpp
@@ -39,21 +39,23 @@
ocsd_err_t TrcIDecode::DecodeInstruction(ocsd_instr_info *instr_info)
{
ocsd_err_t err = OCSD_OK;
- clear_instr_subtype();
- SetArchVersion(instr_info);
+ struct decode_info info;
+
+ info.instr_sub_type = OCSD_S_INSTR_NONE;
+ info.arch_version = (uint16_t)(instr_info->pe_type.arch);
switch(instr_info->isa)
{
case ocsd_isa_arm:
- err = DecodeA32(instr_info);
+ err = DecodeA32(instr_info, &info);
break;
case ocsd_isa_thumb2:
- err = DecodeT32(instr_info);
+ err = DecodeT32(instr_info, &info);
break;
case ocsd_isa_aarch64:
- err = DecodeA64(instr_info);
+ err = DecodeA64(instr_info, &info);
break;
case ocsd_isa_tee:
@@ -63,27 +65,11 @@ ocsd_err_t TrcIDecode::DecodeInstruction(ocsd_instr_info *instr_info)
err = OCSD_ERR_UNSUPPORTED_ISA;
break;
}
- instr_info->sub_type = get_instr_subtype();
+ instr_info->sub_type = info.instr_sub_type;
return err;
}
-void TrcIDecode::SetArchVersion(ocsd_instr_info *instr_info)
-{
- uint16_t arch = 0x0700;
-
- switch (instr_info->pe_type.arch)
- {
- case ARCH_V8: arch = 0x0800; break;
- case ARCH_V8r3: arch = 0x0803; break;
- case ARCH_V7:
- default:
- break;
- }
- set_arch_version(arch);
-}
-
-
-ocsd_err_t TrcIDecode::DecodeA32(ocsd_instr_info *instr_info)
+ocsd_err_t TrcIDecode::DecodeA32(ocsd_instr_info *instr_info, struct decode_info *info)
{
uint32_t branchAddr = 0;
arm_barrier_t barrier;
@@ -93,10 +79,10 @@ ocsd_err_t TrcIDecode::DecodeA32(ocsd_instr_info *instr_info)
instr_info->next_isa = instr_info->isa; // assume same ISA
instr_info->is_link = 0;
- if(inst_ARM_is_indirect_branch(instr_info->opcode))
+ if(inst_ARM_is_indirect_branch(instr_info->opcode, info))
{
instr_info->type = OCSD_INSTR_BR_INDIRECT;
- instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode);
+ instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode, info);
}
else if(inst_ARM_is_direct_branch(instr_info->opcode))
{
@@ -108,7 +94,7 @@ ocsd_err_t TrcIDecode::DecodeA32(ocsd_instr_info *instr_info)
branchAddr &= ~0x1;
}
instr_info->branch_addr = (ocsd_vaddr_t)branchAddr;
- instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode);
+ instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode, info);
}
else if((barrier = inst_ARM_barrier(instr_info->opcode)) != ARM_BARRIER_NONE)
{
@@ -137,7 +123,7 @@ ocsd_err_t TrcIDecode::DecodeA32(ocsd_instr_info *instr_info)
return OCSD_OK;
}
-ocsd_err_t TrcIDecode::DecodeA64(ocsd_instr_info *instr_info)
+ocsd_err_t TrcIDecode::DecodeA64(ocsd_instr_info *instr_info, struct decode_info *info)
{
uint64_t branchAddr = 0;
arm_barrier_t barrier;
@@ -147,12 +133,12 @@ ocsd_err_t TrcIDecode::DecodeA64(ocsd_instr_info *instr_info)
instr_info->next_isa = instr_info->isa; // assume same ISA
instr_info->is_link = 0;
- if(inst_A64_is_indirect_branch_link(instr_info->opcode, &instr_info->is_link))
+ if(inst_A64_is_indirect_branch_link(instr_info->opcode, &instr_info->is_link, info))
{
instr_info->type = OCSD_INSTR_BR_INDIRECT;
// instr_info->is_link = inst_A64_is_branch_and_link(instr_info->opcode);
}
- else if(inst_A64_is_direct_branch_link(instr_info->opcode, &instr_info->is_link))
+ else if(inst_A64_is_direct_branch_link(instr_info->opcode, &instr_info->is_link, info))
{
inst_A64_branch_destination(instr_info->instr_addr,instr_info->opcode,&branchAddr);
instr_info->type = OCSD_INSTR_BR;
@@ -187,7 +173,7 @@ ocsd_err_t TrcIDecode::DecodeA64(ocsd_instr_info *instr_info)
return OCSD_OK;
}
-ocsd_err_t TrcIDecode::DecodeT32(ocsd_instr_info *instr_info)
+ocsd_err_t TrcIDecode::DecodeT32(ocsd_instr_info *instr_info, struct decode_info *info)
{
uint32_t branchAddr = 0;
arm_barrier_t barrier;
@@ -206,7 +192,7 @@ ocsd_err_t TrcIDecode::DecodeT32(ocsd_instr_info *instr_info)
instr_info->is_conditional = 0;
- if(inst_Thumb_is_direct_branch_link(instr_info->opcode,&instr_info->is_link, &instr_info->is_conditional))
+ if(inst_Thumb_is_direct_branch_link(instr_info->opcode,&instr_info->is_link, &instr_info->is_conditional, info))
{
inst_Thumb_branch_destination((uint32_t)instr_info->instr_addr,instr_info->opcode,&branchAddr);
instr_info->type = OCSD_INSTR_BR;
@@ -214,7 +200,7 @@ ocsd_err_t TrcIDecode::DecodeT32(ocsd_instr_info *instr_info)
if((branchAddr & 0x1) == 0)
instr_info->next_isa = ocsd_isa_arm;
}
- else if (inst_Thumb_is_indirect_branch_link(instr_info->opcode, &instr_info->is_link))
+ else if (inst_Thumb_is_indirect_branch_link(instr_info->opcode, &instr_info->is_link, info))
{
instr_info->type = OCSD_INSTR_BR_INDIRECT;
}
@@ -246,5 +232,4 @@ ocsd_err_t TrcIDecode::DecodeT32(ocsd_instr_info *instr_info)
return OCSD_OK;
}
-
/* End of File trc_i_decode.cpp */
diff --git a/decoder/source/i_dec/trc_idec_arminst.cpp b/decoder/source/i_dec/trc_idec_arminst.cpp
index 09964a15e7b3..3652e84921f3 100644
--- a/decoder/source/i_dec/trc_idec_arminst.cpp
+++ b/decoder/source/i_dec/trc_idec_arminst.cpp
@@ -42,27 +42,6 @@ block identification and trace decode.
#include <stddef.h> /* for NULL */
#include <assert.h>
-
-static ocsd_instr_subtype instr_sub_type = OCSD_S_INSTR_NONE;
-
-/* need to spot the architecture version for certain instructions */
-static uint16_t arch_version = 0x70;
-
-ocsd_instr_subtype get_instr_subtype()
-{
- return instr_sub_type;
-}
-
-void clear_instr_subtype()
-{
- instr_sub_type = OCSD_S_INSTR_NONE;
-}
-
-void set_arch_version(uint16_t version)
-{
- arch_version = version;
-}
-
int inst_ARM_is_direct_branch(uint32_t inst)
{
int is_direct_branch = 1;
@@ -91,7 +70,7 @@ int inst_ARM_wfiwfe(uint32_t inst)
return 0;
}
-int inst_ARM_is_indirect_branch(uint32_t inst)
+int inst_ARM_is_indirect_branch(uint32_t inst, struct decode_info *info)
{
int is_indirect_branch = 1;
if ((inst & 0xf0000000) == 0xf0000000) {
@@ -104,23 +83,23 @@ int inst_ARM_is_indirect_branch(uint32_t inst)
} else if ((inst & 0x0ff000d0) == 0x01200010) {
/* BLX (register), BX */
if ((inst & 0xFF) == 0x1E)
- instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* BX LR */
+ info->instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* BX LR */
} else if ((inst & 0x0ff000f0) == 0x01200020) {
/* BXJ: in v8 this behaves like BX */
} else if ((inst & 0x0e108000) == 0x08108000) {
/* POP {...,pc} or LDMxx {...,pc} */
if ((inst & 0x0FFFA000) == 0x08BD8000) /* LDMIA SP!,{...,pc} */
- instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET;
+ info->instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET;
} else if ((inst & 0x0e50f000) == 0x0410f000) {
/* LDR PC,imm... inc. POP {PC} */
if ( (inst & 0x01ff0000) == 0x009D0000)
- instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* LDR PC, [SP], #imm */
+ info->instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* LDR PC, [SP], #imm */
} else if ((inst & 0x0e50f010) == 0x0610f000) {
/* LDR PC,reg */
} else if ((inst & 0x0fe0f000) == 0x01a0f000) {
/* MOV PC,rx */
if ((inst & 0x00100FFF) == 0x00E) /* ensure the S=0, LSL #0 variant - i.e plain MOV */
- instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* MOV PC, R14 */
+ info->instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* MOV PC, R14 */
} else if ((inst & 0x0f900080) == 0x01000000) {
/* "Miscellaneous instructions" - in DP space */
is_indirect_branch = 0;
@@ -144,13 +123,13 @@ int inst_ARM_is_indirect_branch(uint32_t inst)
return is_indirect_branch;
}
-int inst_Thumb_is_direct_branch(uint32_t inst)
+int inst_Thumb_is_direct_branch(uint32_t inst, struct decode_info *info)
{
uint8_t link, cond;
- return inst_Thumb_is_direct_branch_link(inst, &link, &cond);
+ return inst_Thumb_is_direct_branch_link(inst, &link, &cond, info);
}
-int inst_Thumb_is_direct_branch_link(uint32_t inst, uint8_t *is_link, uint8_t *is_cond)
+int inst_Thumb_is_direct_branch_link(uint32_t inst, uint8_t *is_link, uint8_t *is_cond, struct decode_info *info)
{
int is_direct_branch = 1;
@@ -166,12 +145,12 @@ int inst_Thumb_is_direct_branch_link(uint32_t inst, uint8_t *is_link, uint8_t *i
/* B (encoding T4); BL (encoding T1) */
if (inst & 0x00004000) {
*is_link = 1;
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
}
} else if ((inst & 0xf800d001) == 0xf000c000) {
/* BLX (imm) (encoding T2) */
*is_link = 1;
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
} else if ((inst & 0xf5000000) == 0xb1000000) {
/* CB(NZ) */
*is_cond = 1;
@@ -197,13 +176,13 @@ int inst_Thumb_wfiwfe(uint32_t inst)
return is_wfiwfe;
}
-int inst_Thumb_is_indirect_branch(uint32_t inst)
+int inst_Thumb_is_indirect_branch(uint32_t inst, struct decode_info *info)
{
uint8_t link;
- return inst_Thumb_is_indirect_branch_link(inst, &link);
+ return inst_Thumb_is_indirect_branch_link(inst, &link, info);
}
-int inst_Thumb_is_indirect_branch_link(uint32_t inst, uint8_t *is_link)
+int inst_Thumb_is_indirect_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info)
{
/* See e.g. PFT Table 2-3 and Table 2-5 */
int is_branch = 1;
@@ -212,20 +191,20 @@ int inst_Thumb_is_indirect_branch_link(uint32_t inst, uint8_t *is_link)
/* BX, BLX (reg) [v8M includes BXNS, BLXNS] */
if (inst & 0x00800000) {
*is_link = 1;
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
}
else if ((inst & 0x00780000) == 0x00700000) {
- instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* BX LR */
+ info->instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* BX LR */
}
} else if ((inst & 0xfff0d000) == 0xf3c08000) {
/* BXJ: in v8 this behaves like BX */
} else if ((inst & 0xff000000) == 0xbd000000) {
/* POP {pc} */
- instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET;
+ info->instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET;
} else if ((inst & 0xfd870000) == 0x44870000) {
/* MOV PC,reg or ADD PC,reg */
- if ((inst & 0xffff0000) == 0x46f700000)
- instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* MOV PC,LR */
+ if ((inst & 0xffff0000) == 0x46f70000)
+ info->instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* MOV PC,LR */
} else if ((inst & 0xfff0ffe0) == 0xe8d0f000) {
/* TBB/TBH */
} else if ((inst & 0xffd00000) == 0xe8100000) {
@@ -241,26 +220,26 @@ int inst_Thumb_is_indirect_branch_link(uint32_t inst, uint8_t *is_link)
} else if ((inst & 0xfff0f800) == 0xf850f800) {
/* LDR PC,imm (T4) */
if((inst & 0x000f0f00) == 0x000d0b00)
- instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* LDR PC, [SP], #imm*/
+ info->instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* LDR PC, [SP], #imm*/
} else if ((inst & 0xfff0ffc0) == 0xf850f000) {
/* LDR PC,reg (T2) */
} else if ((inst & 0xfe508000) == 0xe8108000) {
/* LDM PC */
if ((inst & 0x0FFF0000) == 0x08BD0000) /* LDMIA [SP]!, */
- instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* POP {...,pc} */
+ info->instr_sub_type = OCSD_S_INSTR_V7_IMPLIED_RET; /* POP {...,pc} */
} else {
is_branch = 0;
}
return is_branch;
}
-int inst_A64_is_direct_branch(uint32_t inst)
+int inst_A64_is_direct_branch(uint32_t inst, struct decode_info *info)
{
uint8_t link = 0;
- return inst_A64_is_direct_branch_link(inst, &link);
+ return inst_A64_is_direct_branch_link(inst, &link, info);
}
-int inst_A64_is_direct_branch_link(uint32_t inst, uint8_t *is_link)
+int inst_A64_is_direct_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info)
{
int is_direct_branch = 1;
if ((inst & 0x7c000000) == 0x34000000) {
@@ -271,7 +250,7 @@ int inst_A64_is_direct_branch_link(uint32_t inst, uint8_t *is_link)
/* B, BL imm */
if (inst & 0x80000000) {
*is_link = 1;
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
}
} else {
is_direct_branch = 0;
@@ -287,13 +266,13 @@ int inst_A64_wfiwfe(uint32_t inst)
return 0;
}
-int inst_A64_is_indirect_branch(uint32_t inst)
+int inst_A64_is_indirect_branch(uint32_t inst, struct decode_info *info)
{
uint8_t link = 0;
- return inst_A64_is_indirect_branch_link(inst, &link);
+ return inst_A64_is_indirect_branch_link(inst, &link, info);
}
-int inst_A64_is_indirect_branch_link(uint32_t inst, uint8_t *is_link)
+int inst_A64_is_indirect_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info)
{
int is_indirect_branch = 1;
@@ -301,34 +280,34 @@ int inst_A64_is_indirect_branch_link(uint32_t inst, uint8_t *is_link)
/* BR, BLR */
if (inst & 0x00200000) {
*is_link = 1;
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
}
} else if ((inst & 0xfffffc1f) == 0xd65f0000) {
- instr_sub_type = OCSD_S_INSTR_V8_RET;
+ info->instr_sub_type = OCSD_S_INSTR_V8_RET;
/* RET */
} else if ((inst & 0xffffffff) == 0xd69f03e0) {
/* ERET */
- instr_sub_type = OCSD_S_INSTR_V8_ERET;
- } else if (arch_version >= 0x0803) {
+ info->instr_sub_type = OCSD_S_INSTR_V8_ERET;
+ } else if (info->arch_version >= 0x0803) {
/* new pointer auth instr for v8.3 arch */
- if ((inst & 0xffdff800) == 0xd61f0800) {
+ if ((inst & 0xffdff800) == 0xd71f0800) {
/* BRAA, BRAB, BLRAA, BLRBB */
if (inst & 0x00200000) {
*is_link = 1;
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
}
- } else if ((inst & 0xffdff81F) == 0xd71f081F) {
+ } else if ((inst & 0xffdff81F) == 0xd61f081F) {
/* BRAAZ, BRABZ, BLRAAZ, BLRBBZ */
if (inst & 0x00200000) {
*is_link = 1;
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
}
} else if ((inst & 0xfffffbff) == 0xd69f0bff) {
/* ERETAA, ERETAB */
- instr_sub_type = OCSD_S_INSTR_V8_ERET;
+ info->instr_sub_type = OCSD_S_INSTR_V8_ERET;
} else if ((inst & 0xfffffbff) == 0xd65f0bff) {
/* RETAA, RETAB */
- instr_sub_type = OCSD_S_INSTR_V8_RET;
+ info->instr_sub_type = OCSD_S_INSTR_V8_RET;
} else {
is_indirect_branch = 0;
}
@@ -441,39 +420,39 @@ int inst_A64_branch_destination(uint64_t addr, uint32_t inst, uint64_t *pnpc)
return is_direct_branch;
}
-int inst_ARM_is_branch(uint32_t inst)
+int inst_ARM_is_branch(uint32_t inst, struct decode_info *info)
{
- return inst_ARM_is_indirect_branch(inst) ||
+ return inst_ARM_is_indirect_branch(inst, info) ||
inst_ARM_is_direct_branch(inst);
}
-int inst_Thumb_is_branch(uint32_t inst)
+int inst_Thumb_is_branch(uint32_t inst, struct decode_info *info)
{
- return inst_Thumb_is_indirect_branch(inst) ||
- inst_Thumb_is_direct_branch(inst);
+ return inst_Thumb_is_indirect_branch(inst, info) ||
+ inst_Thumb_is_direct_branch(inst, info);
}
-int inst_A64_is_branch(uint32_t inst)
+int inst_A64_is_branch(uint32_t inst, struct decode_info *info)
{
- return inst_A64_is_indirect_branch(inst) ||
- inst_A64_is_direct_branch(inst);
+ return inst_A64_is_indirect_branch(inst, info) ||
+ inst_A64_is_direct_branch(inst, info);
}
-int inst_ARM_is_branch_and_link(uint32_t inst)
+int inst_ARM_is_branch_and_link(uint32_t inst, struct decode_info *info)
{
int is_branch = 1;
if ((inst & 0xf0000000) == 0xf0000000) {
if ((inst & 0xfe000000) == 0xfa000000){
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
/* BLX (imm) */
} else {
is_branch = 0;
}
} else if ((inst & 0x0f000000) == 0x0b000000) {
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
/* BL */
} else if ((inst & 0x0ff000f0) == 0x01200030) {
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
/* BLX (reg) */
} else {
is_branch = 0;
@@ -481,14 +460,14 @@ int inst_ARM_is_branch_and_link(uint32_t inst)
return is_branch;
}
-int inst_Thumb_is_branch_and_link(uint32_t inst)
+int inst_Thumb_is_branch_and_link(uint32_t inst, struct decode_info *info)
{
int is_branch = 1;
if ((inst & 0xff800000) == 0x47800000) {
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
/* BLX (reg) */
} else if ((inst & 0xf800c000) == 0xf000c000) {
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
/* BL, BLX (imm) */
} else {
is_branch = 0;
@@ -496,23 +475,23 @@ int inst_Thumb_is_branch_and_link(uint32_t inst)
return is_branch;
}
-int inst_A64_is_branch_and_link(uint32_t inst)
+int inst_A64_is_branch_and_link(uint32_t inst, struct decode_info *info)
{
int is_branch = 1;
if ((inst & 0xfffffc1f) == 0xd63f0000) {
/* BLR */
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
} else if ((inst & 0xfc000000) == 0x94000000) {
/* BL */
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
- } else if (arch_version >= 0x0803) {
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ } else if (info->arch_version >= 0x0803) {
/* new pointer auth instr for v8.3 arch */
if ((inst & 0xfffff800) == 0xd73f0800) {
/* BLRAA, BLRBB */
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
} else if ((inst & 0xfffff81F) == 0xd63f081F) {
/* BLRAAZ, BLRBBZ */
- instr_sub_type = OCSD_S_INSTR_BR_LINK;
+ info->instr_sub_type = OCSD_S_INSTR_BR_LINK;
} else {
is_branch = 0;
}
diff --git a/decoder/source/mem_acc/trc_mem_acc_bufptr.cpp b/decoder/source/mem_acc/trc_mem_acc_bufptr.cpp
index 25c736387c0b..7ecd3b018dab 100644
--- a/decoder/source/mem_acc/trc_mem_acc_bufptr.cpp
+++ b/decoder/source/mem_acc/trc_mem_acc_bufptr.cpp
@@ -37,8 +37,7 @@
TrcMemAccBufPtr::TrcMemAccBufPtr(const ocsd_vaddr_t s_address, const uint8_t *p_buffer, const uint32_t size) :
TrcMemAccessorBase(MEMACC_BUFPTR, s_address, s_address+size-1),
- m_p_buffer(p_buffer),
- m_size(size)
+ m_p_buffer(p_buffer)
{
}
diff --git a/decoder/source/ocsd_dcd_tree.cpp b/decoder/source/ocsd_dcd_tree.cpp
index cf75e569d72a..be15e36e9cb3 100644
--- a/decoder/source/ocsd_dcd_tree.cpp
+++ b/decoder/source/ocsd_dcd_tree.cpp
@@ -111,6 +111,7 @@ DecodeTree::~DecodeTree()
destroyDecodeElement(i);
}
PktPrinterFact::destroyAllPrinters(m_printer_list);
+ delete m_frame_deformatter_root;
}
diff --git a/decoder/source/ocsd_error.cpp b/decoder/source/ocsd_error.cpp
index 251964b7a4b0..74e9e4977f60 100644
--- a/decoder/source/ocsd_error.cpp
+++ b/decoder/source/ocsd_error.cpp
@@ -207,7 +207,7 @@ const std::string ocsdError::getErrorString(const ocsdError &error)
void ocsdError::appendErrorDetails(std::string &errStr, const ocsdError &error)
{
- int numerrstr = ((sizeof(s_errorCodeDescs) / sizeof(const char *)) / 2);
+ int numerrstr = sizeof(s_errorCodeDescs) / sizeof(s_errorCodeDescs[0]);
int code = (int)error.getErrorCode();
ocsd_trc_index_t idx = error.getErrorIndex();
uint8_t chan_ID = error.getErrorChanID();
diff --git a/decoder/source/ocsd_gen_elem_stack.cpp b/decoder/source/ocsd_gen_elem_stack.cpp
new file mode 100644
index 000000000000..bb758427a9b8
--- /dev/null
+++ b/decoder/source/ocsd_gen_elem_stack.cpp
@@ -0,0 +1,196 @@
+/*
+* \file ocsd_gen_elem_stack.cpp
+* \brief OpenCSD : List of Generic trace elements for output.
+*
+* \copyright Copyright (c) 2020, ARM Limited. All Rights Reserved.
+*/
+
+
+/*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "common/ocsd_gen_elem_stack.h"
+
+OcsdGenElemStack::OcsdGenElemStack() :
+ m_pElemArray(0),
+ m_elemArraySize(0),
+ m_elem_to_send(0),
+ m_curr_elem_idx(0),
+ m_send_elem_idx(0),
+ m_CSID(0),
+ m_is_init(false)
+{
+
+}
+
+OcsdGenElemStack::~OcsdGenElemStack()
+{
+ for (int i = 0; i<m_elemArraySize; i++)
+ {
+ delete m_pElemArray[i].pElem;
+ }
+ delete [] m_pElemArray;
+ m_pElemArray = 0;
+}
+
+ocsd_err_t OcsdGenElemStack::addElem(const ocsd_trc_index_t trc_pkt_idx)
+{
+ ocsd_err_t err = OCSD_OK;
+
+ if (((m_curr_elem_idx + 1) == m_elemArraySize) || !m_pElemArray)
+ {
+ err = growArray();
+ if (err)
+ return err;
+ }
+
+ // if there is a least one element then copy and increment
+ // otherwise we are at base of stack.
+ if (m_elem_to_send)
+ {
+ copyPersistentData(m_curr_elem_idx, m_curr_elem_idx + 1);
+ m_curr_elem_idx++;
+ }
+ m_pElemArray[m_curr_elem_idx].trc_pkt_idx = trc_pkt_idx;
+ m_elem_to_send++;
+ return err;
+}
+
+ocsd_err_t OcsdGenElemStack::addElemType(const ocsd_trc_index_t trc_pkt_idx, ocsd_gen_trc_elem_t elem_type)
+{
+ ocsd_err_t err = addElem(trc_pkt_idx);
+ if (!err)
+ getCurrElem().setType(elem_type);
+ return err;
+}
+
+ocsd_err_t OcsdGenElemStack::resetElemStack()
+{
+ ocsd_err_t err = OCSD_OK;
+ if (!m_pElemArray)
+ {
+ err = growArray();
+ if (err)
+ return err;
+ }
+
+ if (!isInit())
+ return OCSD_ERR_NOT_INIT;
+
+ resetIndexes();
+ return err;
+}
+
+void OcsdGenElemStack::resetIndexes()
+{
+ // last time there was more than one element on stack
+ if (m_curr_elem_idx > 0)
+ copyPersistentData(m_curr_elem_idx, 0);
+
+ // indexes to bottom of stack, nothing in use at present
+ m_curr_elem_idx = 0;
+ m_send_elem_idx = 0;
+ m_elem_to_send = 0;
+}
+
+ocsd_datapath_resp_t OcsdGenElemStack::sendElements()
+{
+ ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ if (!isInit())
+ return OCSD_RESP_FATAL_NOT_INIT;
+
+ while (m_elem_to_send && OCSD_DATA_RESP_IS_CONT(resp))
+ {
+ resp = m_sendIf->first()->TraceElemIn(m_pElemArray[m_send_elem_idx].trc_pkt_idx, m_CSID, *(m_pElemArray[m_send_elem_idx].pElem));
+ m_send_elem_idx++;
+ m_elem_to_send--;
+ }
+
+ // clear the indexes if we are done.
+ if (!m_elem_to_send)
+ resetIndexes();
+ return resp;
+}
+
+ocsd_err_t OcsdGenElemStack::growArray()
+{
+ elemPtr_t *p_new_array = 0;
+ const int increment = 4;
+
+ p_new_array = new (std::nothrow) elemPtr_t[m_elemArraySize + increment];
+
+ if (p_new_array != 0)
+ {
+ OcsdTraceElement *pElem = 0;
+
+ // fill the last increment elements with new objects
+ for (int i = 0; i < increment; i++)
+ {
+ pElem = new (std::nothrow) OcsdTraceElement();
+ if (!pElem)
+ return OCSD_ERR_MEM;
+ pElem->init();
+ p_new_array[m_elemArraySize + i].pElem = pElem;
+ }
+
+ // copy the existing objects from the old array to the start of the new one
+ if (m_elemArraySize > 0)
+ {
+ for (int i = 0; i < m_elemArraySize; i++)
+ {
+ p_new_array[i].pElem = m_pElemArray[i].pElem;
+ p_new_array[i].trc_pkt_idx = m_pElemArray[i].trc_pkt_idx;
+ }
+ }
+
+ // delete the old pointer array.
+ delete[] m_pElemArray;
+ m_elemArraySize += increment;
+ m_pElemArray = p_new_array;
+ }
+ else
+ return OCSD_ERR_MEM;
+
+ return OCSD_OK;
+}
+
+void OcsdGenElemStack::copyPersistentData(int src, int dst)
+{
+ m_pElemArray[dst].pElem->copyPersistentData(*(m_pElemArray[src].pElem));
+}
+
+const bool OcsdGenElemStack::isInit()
+{
+ if (!m_is_init) {
+ if (m_elemArraySize && m_pElemArray && m_sendIf)
+ m_is_init = true;
+ }
+ return m_is_init;
+}
+
+
+/* End of File ocsd_gen_elem_stack.cpp */
diff --git a/decoder/source/ptm/trc_pkt_decode_ptm.cpp b/decoder/source/ptm/trc_pkt_decode_ptm.cpp
index 94ed5acc243a..7abee8499f46 100644
--- a/decoder/source/ptm/trc_pkt_decode_ptm.cpp
+++ b/decoder/source/ptm/trc_pkt_decode_ptm.cpp
@@ -67,6 +67,7 @@ ocsd_datapath_resp_t TrcPktDecodePtm::processPacket()
case NO_SYNC:
// no sync - output a no sync packet then transition to wait sync.
m_output_elem.elem_type = OCSD_GEN_TRC_ELEM_NO_SYNC;
+ m_output_elem.unsync_eot_info = m_unsync_info;
resp = outputTraceElement(m_output_elem);
m_curr_state = (m_curr_packet_in->getType() == PTM_PKT_A_SYNC) ? WAIT_ISYNC : WAIT_SYNC;
bPktDone = true;
@@ -108,6 +109,7 @@ ocsd_datapath_resp_t TrcPktDecodePtm::onEOT()
// shouldn't be any packets left to be processed - flush shoudl have done this.
// just output the end of trace marker
m_output_elem.setType(OCSD_GEN_TRC_ELEM_EO_TRACE);
+ m_output_elem.setUnSyncEOTReason(UNSYNC_EOT);
resp = outputTraceElement(m_output_elem);
return resp;
}
@@ -115,6 +117,7 @@ ocsd_datapath_resp_t TrcPktDecodePtm::onEOT()
ocsd_datapath_resp_t TrcPktDecodePtm::onReset()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ m_unsync_info = UNSYNC_RESET_DECODER;
resetDecoder();
return resp;
}
@@ -191,6 +194,7 @@ void TrcPktDecodePtm::initDecoder()
m_instr_info.pe_type.profile = profile_Unknown;
m_instr_info.pe_type.arch = ARCH_UNKNOWN;
m_instr_info.dsb_dmb_waypoints = 0;
+ m_unsync_info = UNSYNC_INIT_DECODER;
resetDecoder();
}
@@ -504,11 +508,15 @@ ocsd_datapath_resp_t TrcPktDecodePtm::processAtomRange(const ocsd_atm_val A, con
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
bool bWPFound = false;
std::ostringstream oss;
+ ocsd_err_t err = OCSD_OK;
m_instr_info.instr_addr = m_curr_pe_state.instr_addr;
m_instr_info.isa = m_curr_pe_state.isa;
- ocsd_err_t err = traceInstrToWP(bWPFound,traceWPOp,nextAddrMatch);
+ // set type (which resets out-elem) before traceInstrToWP modifies out-elem values
+ m_output_elem.setType(OCSD_GEN_TRC_ELEM_INSTR_RANGE);
+
+ err = traceInstrToWP(bWPFound,traceWPOp,nextAddrMatch);
if(err != OCSD_OK)
{
if(err == OCSD_ERR_UNSUPPORTED_ISA)
@@ -576,7 +584,6 @@ ocsd_datapath_resp_t TrcPktDecodePtm::processAtomRange(const ocsd_atm_val A, con
break;
}
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_INSTR_RANGE);
m_output_elem.setLastInstrInfo((A == ATOM_E),m_instr_info.type, m_instr_info.sub_type,m_instr_info.instr_size);
m_output_elem.setISA(m_curr_pe_state.isa);
if(m_curr_packet_in->hasCC())
@@ -595,7 +602,6 @@ ocsd_datapath_resp_t TrcPktDecodePtm::processAtomRange(const ocsd_atm_val A, con
if(m_output_elem.st_addr != m_output_elem.en_addr)
{
// some trace before we were out of memory access range
- m_output_elem.setType(OCSD_GEN_TRC_ELEM_INSTR_RANGE);
m_output_elem.setLastInstrInfo(true,m_instr_info.type, m_instr_info.sub_type,m_instr_info.instr_size);
m_output_elem.setISA(m_curr_pe_state.isa);
m_output_elem.setLastInstrCond(m_instr_info.is_conditional);
diff --git a/decoder/source/stm/trc_pkt_decode_stm.cpp b/decoder/source/stm/trc_pkt_decode_stm.cpp
index a47e96312546..1bb8d7346be0 100644
--- a/decoder/source/stm/trc_pkt_decode_stm.cpp
+++ b/decoder/source/stm/trc_pkt_decode_stm.cpp
@@ -68,6 +68,7 @@ ocsd_datapath_resp_t TrcPktDecodeStm::processPacket()
{
case NO_SYNC:
m_output_elem.setType(OCSD_GEN_TRC_ELEM_NO_SYNC);
+ m_output_elem.setUnSyncEOTReason(m_unsync_info);
resp = outputTraceElement(m_output_elem);
m_curr_state = WAIT_SYNC;
break;
@@ -90,6 +91,7 @@ ocsd_datapath_resp_t TrcPktDecodeStm::onEOT()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
m_output_elem.setType(OCSD_GEN_TRC_ELEM_EO_TRACE);
+ m_output_elem.setUnSyncEOTReason(UNSYNC_EOT);
resp = outputTraceElement(m_output_elem);
return resp;
}
@@ -97,6 +99,7 @@ ocsd_datapath_resp_t TrcPktDecodeStm::onEOT()
ocsd_datapath_resp_t TrcPktDecodeStm::onReset()
{
ocsd_datapath_resp_t resp = OCSD_RESP_CONT;
+ m_unsync_info = UNSYNC_RESET_DECODER;
resetDecoder();
return resp;
}
@@ -127,7 +130,7 @@ void TrcPktDecodeStm::initDecoder()
// base decoder state - STM requires no memory and instruction decode.
setUsesMemAccess(false);
setUsesIDecode(false);
-
+ m_unsync_info = UNSYNC_INIT_DECODER;
resetDecoder();
}
@@ -166,6 +169,7 @@ ocsd_datapath_resp_t TrcPktDecodeStm::decodePacket(bool &bPktDone)
case STM_PKT_BAD_SEQUENCE: /**< Incorrect protocol sequence */
case STM_PKT_RESERVED:
resp = OCSD_RESP_FATAL_INVALID_DATA;
+ m_unsync_info = UNSYNC_BAD_PACKET;
case STM_PKT_NOTSYNC:
resetDecoder();
break;
diff --git a/decoder/source/trc_component.cpp b/decoder/source/trc_component.cpp
index 47200a1ead67..dae92d4213de 100644
--- a/decoder/source/trc_component.cpp
+++ b/decoder/source/trc_component.cpp
@@ -41,7 +41,13 @@ public:
{
m_pComp = 0;
};
- virtual ~ errLogAttachMonitor() {};
+ virtual ~ errLogAttachMonitor()
+ {
+ if (m_pComp)
+ m_pComp->getErrorLogAttachPt()->set_notifier(0);
+ m_pComp = 0;
+
+ };
virtual void attachNotify(const int num_attached)
{
if(m_pComp)
@@ -73,6 +79,8 @@ TraceComponent::TraceComponent(const std::string &name, int instIDNum)
TraceComponent::~TraceComponent()
{
+ if (m_pErrAttachMon)
+ delete m_pErrAttachMon;
}
void TraceComponent::Init(const std::string &name)
@@ -140,9 +148,7 @@ void TraceComponent::updateErrorLogLevel()
ocsd_err_t TraceComponent::setComponentOpMode(uint32_t op_flags)
{
- if( (~m_supported_op_flags & op_flags) != 0)
- return OCSD_ERR_INVALID_PARAM_VAL;
- m_op_flags = op_flags;
+ m_op_flags = op_flags & m_supported_op_flags;
return OCSD_OK;
}
diff --git a/decoder/source/trc_core_arch_map.cpp b/decoder/source/trc_core_arch_map.cpp
index 70a25eef0359..a26f79db996e 100644
--- a/decoder/source/trc_core_arch_map.cpp
+++ b/decoder/source/trc_core_arch_map.cpp
@@ -34,10 +34,12 @@
#include "common/trc_core_arch_map.h"
-static struct _ap_map_elements {
+typedef struct _ap_map_elements {
const char *name;
ocsd_arch_profile_t ap;
-} ap_map_array[] =
+} ap_map_elem_t;
+
+static ap_map_elem_t ap_map_array[] =
{
{ "Cortex-A77", { ARCH_V8r3, profile_CortexA } },
{ "Cortex-A76", { ARCH_V8r3, profile_CortexA } },
@@ -70,12 +72,28 @@ static struct _ap_map_elements {
{ "Cortex-M4", { ARCH_V7, profile_CortexM } }
};
+static ap_map_elem_t arch_map_array[] =
+{
+ { "ARMv7-A", { ARCH_V7, profile_CortexA } },
+ { "ARMv7-R", { ARCH_V7, profile_CortexR } },
+ { "ARMv7-M", { ARCH_V7, profile_CortexM } },
+ { "ARMv8-A", { ARCH_V8, profile_CortexA } },
+ { "ARMv8.3-A", { ARCH_V8r3, profile_CortexA } },
+ { "ARMv8-R", { ARCH_V8, profile_CortexR } },
+ { "ARMv8-M", { ARCH_V8, profile_CortexM } },
+};
+
CoreArchProfileMap::CoreArchProfileMap()
{
- for(unsigned i = 0; i < sizeof(ap_map_array)/sizeof(_ap_map_elements); i++)
+ unsigned i;
+ for (i = 0; i < sizeof(ap_map_array) / sizeof(_ap_map_elements); i++)
{
core_profiles[ap_map_array[i].name] = ap_map_array[i].ap;
}
+ for (i = 0; i < sizeof(arch_map_array) / sizeof(_ap_map_elements); i++)
+ {
+ arch_profiles[arch_map_array[i].name] = arch_map_array[i].ap;
+ }
}
/* End of File trc_core_arch_map.cpp */
diff --git a/decoder/source/trc_gen_elem.cpp b/decoder/source/trc_gen_elem.cpp
index b3ec75f059d4..e1774203ebc5 100644
--- a/decoder/source/trc_gen_elem.cpp
+++ b/decoder/source/trc_gen_elem.cpp
@@ -46,6 +46,7 @@ static const char *s_elem_descs[][2] =
{"OCSD_GEN_TRC_ELEM_EO_TRACE","End of the available trace in the buffer."},
{"OCSD_GEN_TRC_ELEM_PE_CONTEXT","PE status update / change (arch, ctxtid, vmid etc)."},
{"OCSD_GEN_TRC_ELEM_INSTR_RANGE","Traced N consecutive instructions from addr (no intervening events or data elements), may have data assoc key"},
+ {"OCSD_GEN_TRC_ELEM_I_RANGE_NOPATH","Traced N instructions in a range, but incomplete information as to program execution path from start to end of range"},
{"OCSD_GEN_TRC_ELEM_ADDR_NACC","Tracing in inaccessible memory area."},
{"OCSD_GEN_TRC_ELEM_ADDR_UNKNOWN","Tracing unknown address area."},
{"OCSD_GEN_TRC_ELEM_EXCEPTION","Exception"},
@@ -62,7 +63,8 @@ static const char *instr_type[] = {
"BR ",
"iBR ",
"ISB ",
- "DSB.DMB"
+ "DSB.DMB",
+ "WFI.WFE"
};
#define T_SIZE (sizeof(instr_type) / sizeof(const char *))
@@ -94,10 +96,20 @@ static const char *s_isa_str[] = {
"Unk" /**< ISA not yet known */
};
+static const char *s_unsync_reason[] = {
+ "undefined", // UNSYNC_UNKNOWN - unknown /undefined
+ "init-decoder", // UNSYNC_INIT_DECODER - decoder intialisation - start of trace.
+ "reset-decoder", // UNSYNC_RESET_DECODER - decoder reset.
+ "overflow", // UNSYNC_OVERFLOW - overflow packet - need to re-sync
+ "discard", // UNSYNC_DISCARD - specl trace discard - need to re-sync
+ "bad-packet", // UNSYNC_BAD_PACKET - bad packet at input - resync to restart.
+ "end-of-trace", // UNSYNC_EOT - end of trace info.
+};
+
void OcsdTraceElement::toString(std::string &str) const
{
std::ostringstream oss;
- int num_str = ((sizeof(s_elem_descs) / sizeof(const char *)) / 2);
+ int num_str = sizeof(s_elem_descs) / sizeof(s_elem_descs[0]);
int typeIdx = (int)this->elem_type;
if(typeIdx < num_str)
{
@@ -122,6 +134,11 @@ void OcsdTraceElement::toString(std::string &str) const
oss << " 0x" << std::hex << st_addr << " ";
break;
+ case OCSD_GEN_TRC_ELEM_I_RANGE_NOPATH:
+ oss << "first 0x" << std::hex << st_addr << ":[next 0x" << en_addr << "] ";
+ oss << "num_i(" << std::dec << num_instr_range << ") ";
+ break;
+
case OCSD_GEN_TRC_ELEM_EXCEPTION:
if (excep_ret_addr == 1)
{
@@ -167,6 +184,12 @@ void OcsdTraceElement::toString(std::string &str) const
oss << " Numbered:" << std::dec << trace_event.ev_number << "; ";
break;
+ case OCSD_GEN_TRC_ELEM_EO_TRACE:
+ case OCSD_GEN_TRC_ELEM_NO_SYNC:
+ if (unsync_eot_info <= UNSYNC_EOT)
+ oss << " [" << s_unsync_reason[unsync_eot_info] << "]";
+ break;
+
default: break;
}
if(has_cc)
diff --git a/decoder/tests/auto-fdo/autofdo.md b/decoder/tests/auto-fdo/autofdo.md
index b1f22417b50e..69ed1520eda8 100644
--- a/decoder/tests/auto-fdo/autofdo.md
+++ b/decoder/tests/auto-fdo/autofdo.md
@@ -99,6 +99,8 @@ You can include these backports in your kernel by either merging the
appropriate branch using git or generating patches (using `git
format-patch`).
+For 5.x based kernel onwards, the only patch which needs to be applied is the one enabling strobing - etm4x: `Enable strobing of ETM`.
+
For 4.9 based kernels, use the `coresight-4.9-etr-etm_strobe` branch:
```
@@ -129,7 +131,7 @@ git am /output/dir/*.patch # or patch -p1 /output/dir/*.patch if not using git
The CoreSight trace drivers must also be enabled in the kernel
configuration. This can be done using the configuration menu (`make
-menuconfig`), selecting `Kernel hacking` / `CoreSight Tracing Support` and
+menuconfig`), selecting `Kernel hacking` / `arm64 Debugging` /`CoreSight Tracing Support` and
enabling all options, or by setting the following in the configuration
file:
@@ -165,11 +167,15 @@ CoreSight devices, you should find the devices in sysfs:
```
# ls /sys/bus/coresight/devices/
-28440000.etm 28540000.etm 28640000.etm 28740000.etm
-28c03000.funnel 28c04000.etf 28c05000.replicator 28c06000.etr
-28c07000.tpiu
+etm0 etm2 etm4 etm6 funnel0 funnel2 funnel4 stm0 tmc_etr0
+etm1 etm3 etm5 etm7 funnel1 funnel3 replicator0 tmc_etf0
```
+The naming convention for etm devices can be different according to the kernel version you're using.
+For more information about the naming scheme, please check out the [Linux Kernel Documentation](https://www.kernel.org/doc/html/latest/trace/coresight/coresight.html#device-naming-scheme)
+
+If `/sys/bus/coresight/devices/` is empty, you may want to check out your Kernel configuration to make sure your .config file is including CoreSight dependencies, such as the clock.
+
### Perf tools
The perf tool is used to capture execution trace, configuring the trace
@@ -180,9 +186,12 @@ Arm recommends to use the perf version corresponding to the kernel running
on the target. This can be built from the same kernel sources with
```
-make -C tools/perf ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu-
+make -C tools/perf CORESIGHT=1 VF=1 ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu-
```
+When specifying CORESIGHT=1, perf will be built using the installed OpenCSD library.
+If you are cross compiling, then additional setup is required to ensure the build process links against the correct version of the library.
+
If the post-processing (`perf inject`) of the captured data is not being
done on the target, then the OpenCSD library is not required for this build
of perf.
@@ -193,13 +202,22 @@ also be restricted to user space or kernel space with 'u' or 'k'
parameters. For example:
```
-perf record -e cs_etm/@28c06000.etr/u --per-thread -- /bin/ls
+perf record -e cs_etm/@tmc_etr0/u --per-thread -- /bin/ls
```
-
-Will record the userspace execution of '/bin/ls' into the ETR located at
-0x28c06000. Note the `--per-thread` option is required - perf currently
-only supports trace of a single thread of execution. CPU wide trace is a
-work in progresss.
+
+Will record the userspace execution of '/bin/ls' using tmc_etr0 as sink.
+
+## Capturing modes
+
+You can trace a single-threaded program in two different ways:
+
+1. By specifying `--per-thread`, and in this case the CoreSight subsystem will
+record only a trace relative to the given program.
+
+2. By NOT specifying `--per-thread`, and in this case CPU-wide tracing will
+be enabled. In this scenario the trace will contain both the target program trace
+and other workloads that were executing on the same CPU
+
## Processing trace and profiles
@@ -241,26 +259,42 @@ For example, a typical configuration is to use a window size of 5000 cycles
and a period of 10000 - this will collect 5000 cycles of trace every 50M
cycles. With these proof-of-concept patches, the strobe parameters are
configured via sysfs - each ETM will have `strobe_window` and
-`strobe_period` parameters in `/sys/bus/coresight/devices/NNNNNNNN.etm` and
+`strobe_period` parameters in `/sys/bus/coresight/devices/<sink>` and
these values will have to be written to each (In a future version, this
-will be integrated into the drivers and perf tool). The `record.sh`
-script in this directory [`<opencsd>/decoder/tests/auto-fdo`] automates this process.
+will be integrated into the drivers and perf tool).
+The `set_strobing.sh` script in this directory [`<opencsd>/decoder/tests/auto-fdo`] automates this process.
To collect trace from an application using ETM strobing, run:
```
-taskset -c 0 ./record.sh --strobe 5000 10000 28c06000.etr ./my_application arg1 arg2
+sudo ./set_strobing.sh 5000 10000
+perf record -e cs_etm/@tmc_etr0/u --per-thread -- <your app>"
```
-The taskset command is used to ensure the process stays on the same CPU
-during execution.
-
The raw trace can be examined using the `perf report` command:
```
perf report -D -i perf.data --stdio
```
+Perf needs to be built from your linux kernel version souce code repository against the OpenCSD library in order to be able to properly read ETM-gathered samples and post-process them.
+If running `perf report` produces an error like:
+
+```
+0x1f8 [0x268]: failed to process type: 70 [Operation not permitted]
+Error:
+failed to process sample
+```
+or
+
+```
+"file uses a more recent and unsupported ABI (8 bytes extra). incompatible file format".
+```
+
+You are probably using a perf version which is not using this library: please make sure to install this project in your system by either compiling it from [Source Code]( <https://github.com/Linaro/OpenCSD>) from v0.9.1 or later and compile perf using this library.
+Otherwise, this project is packaged for debian (install the libopencsd0, libopencsd-dev packages).
+
+
For example:
```
@@ -295,6 +329,8 @@ an embedded target). The `perf inject` command
decodes the execution trace and generates periodic instruction samples,
with branch histories:
+!! Careful: if you are using a device different than the one used to collect the profiling data,
+you'll need to run `perf buildid-cache` as described below.
```
perf inject -i perf.data -o inj.data --itrace=i100000il
```
@@ -393,7 +429,8 @@ clang -O2 -fprofile-sample-use=program.llvmprof -o program program.c
The basic commands to run an application and create a compiler profile are:
```
-taskset -c 0 ./record.sh --strobe 5000 10000 28c06000.etr ./my_application arg1 arg2
+sudo ./set_strobing.sh 5000 10000
+perf record -e cs_etm/@tmc_etr0/u --per-thread -- <your app>"
perf inject -i perf.data -o inj.data --itrace=i100000il
create_llvm_prof -binary=/path/to/binary -profile=inj.data -out=program.llvmprof
```
diff --git a/decoder/tests/auto-fdo/record.sh b/decoder/tests/auto-fdo/record.sh
deleted file mode 100755
index 16d4ba22db3c..000000000000
--- a/decoder/tests/auto-fdo/record.sh
+++ /dev/null
@@ -1,68 +0,0 @@
-#!/bin/sh
-
-BUFFER_ETF_A53=ec802000.etf
-BUFFER_ETF_A73=ed002000.etf
-BUFFER_ETF_SYS=ec036000.etf
-BUFFER_ETR=ec033000.etr
-
-OUT_FILE=perf.data
-
-STROBE=
-
-while :; do
- case $1 in
- --strobe)
- STROBE=y
- WINDOW=$2
- PERIOD=$3
- shift 3
- ;;
-
- *)
- break ;;
- esac
-done
-
-case $1 in
- etr)
- BUFFER=$BUFFER_ETR
- ;;
-
- etf-sys)
- BUFFER=$BUFFER_ETF_SYS
- ;;
-
- "")
- BUFFER=$BUFFER_ETR
- ;;
-
- *)
- BUFFER=$1
- ;;
-esac
-
-shift 1
-
-case $0 in
- /*) F=$0 ;;
- *) F=$(pwd)/$0 ;;
-esac
-
-SCRIPT_DIR=$(dirname $F)
-
-if [ "$STROBE" ]; then
- for e in /sys/bus/coresight/devices/*.etm/; do
- printf "%x" $WINDOW | sudo tee $e/strobe_window > /dev/null
- printf "%x" $PERIOD | sudo tee $e/strobe_period > /dev/null
- done
-fi
-
-PERF=$SCRIPT_DIR/perf
-
-export LD_LIBRARY_PATH=$SCRIPT_DIR:$LD_LIBRARY_PATH
-
-sudo LD_LIBRARY_PATH=$SCRIPT_DIR:$LD_LIBRARY_PATH $PERF record $PERF_ARGS -e cs_etm/@$BUFFER/u --per-thread "$@"
-
-sudo chown $(id -u):$(id -g) $OUT_FILE
-
-
diff --git a/decoder/tests/auto-fdo/set_strobing.sh b/decoder/tests/auto-fdo/set_strobing.sh
new file mode 100755
index 000000000000..081f371dcc9b
--- /dev/null
+++ b/decoder/tests/auto-fdo/set_strobing.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+
+WINDOW=$1
+PERIOD=$2
+
+if [[ -z $WINDOW ]] || [[ -z $PERIOD ]]; then
+ echo "Window or Period not specified!"
+ echo "Example usage: ./set_strobing.sh <WINDOW VALUE> <PERIOD VALUE>"
+ echo "Example usage: ./set_strobing.sh 5000 10000"
+ exit -1
+fi
+
+
+if [[ $EUID != 0 ]]; then
+ echo "Please run as root"
+ exit -1
+fi
+
+for e in /sys/bus/coresight/devices/etm*/; do
+ printf "%x" $WINDOW | tee $e/strobe_window > /dev/null
+ printf "%x" $PERIOD | tee $e/strobe_period > /dev/null
+ echo "Strobing period for $e set to $((`cat $e/strobe_period`))"
+ echo "Strobing window for $e set to $((`cat $e/strobe_window`))"
+done
+
+## Shows the user a simple usage example
+echo ">> Done! <<"
+echo "You can now run perf to trace your application, for example:"
+echo "perf record -e cs_etm/@tmc_etr0/u -- <your app>"
diff --git a/decoder/tests/auto-fdo/show_strobing.sh b/decoder/tests/auto-fdo/show_strobing.sh
new file mode 100755
index 000000000000..44302ae11c4a
--- /dev/null
+++ b/decoder/tests/auto-fdo/show_strobing.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+
+for e in /sys/bus/coresight/devices/etm*/; do
+ echo "Strobing period for $e is $((`cat $e/strobe_period`))"
+ echo "Strobing window for $e is $((`cat $e/strobe_window`))"
+done
diff --git a/decoder/tests/perf-test-scripts/perf-setup-env.bash b/decoder/tests/perf-test-scripts/perf-setup-env.bash
index 09431a7fd410..95bfdc8aaacd 100755
--- a/decoder/tests/perf-test-scripts/perf-setup-env.bash
+++ b/decoder/tests/perf-test-scripts/perf-setup-env.bash
@@ -5,35 +5,44 @@
#
# to use this script:-
#
+# 1) for perf exec env only
# source perf-setup-env.bash
#
+# 2) for perf build and exec env
+# source perf-setup-env.bash buildenv
+#
#------ User Edits Start -------
# Edit as required for user system.
# Root of the opencsd library project as cloned from github
-export OPENCSD_ROOT=~/OpenCSD/opencsd-github/opencsd
+export OPENCSD_ROOT=~/work/opencsd-master
# the opencsd build library directory to use.
-export OCSD_LIB_DIR=lib/linux64/rel
+export OCSD_LIB_DIR=lib/builddir
# the root of the perf branch / perf dev-tree as checked out
-export PERF_ROOT=~/work2/perf-opencsd/mp-4.7-rc4/coresight
+export PERF_ROOT=~/work/kernel-dev
# the arm x-compiler toolchain path
-export XTOOLS_PATH=~/work2/toolchain-aarch64/gcc-linaro-4.9-2015.05-1-rc1-x86_64_aarch64-linux-gnu/bin/
+export XTOOLS_PATH=~/work/gcc-x-aarch64-6.2/bin
#------ User Edits End -------
# path to source/include root dir - used by perf build to
# include Opencsd decoder.
-export CSTRACE_PATH=${OPENCSD_ROOT}/decoder
-# add library to lib path
-if [ "${LD_LIBRARY_PATH}" == "" ]; then
- export LD_LIBRARY_PATH=${CSTRACE_PATH}/${OCSD_LIB_DIR}
-else
- export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${CSTRACE_PATH}/${OCSD_LIB_DIR}
+if [ "$1" == "buildenv" ]; then
+ export CSTRACE_PATH=${OPENCSD_ROOT}/decoder
+ export CSLIBS=${CSTRACE_PATH}/${OCSD_LIB_DIR}
+ export CSINCLUDES=${CSTRACE_PATH}/include
+
+ # add library to lib path
+ if [ "${LD_LIBRARY_PATH}" == "" ]; then
+ export LD_LIBRARY_PATH=${CSLIBS}
+ else
+ export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${CSLIBS}
+ fi
fi
# perf script defines
diff --git a/decoder/tests/run_capi_test.bash b/decoder/tests/run_capi_test.bash
new file mode 100755
index 000000000000..bac5da4342d3
--- /dev/null
+++ b/decoder/tests/run_capi_test.bash
@@ -0,0 +1,54 @@
+#!/bin/bash
+#################################################################################
+# Copyright 2018 ARM. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors
+# may be used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#################################################################################
+# OpenCSD library: Test script.
+#
+# Test script to run packet lister on each of the snapshots retained with the repository.
+# No attempt is made to compare output results to previous versions, (output formatting
+# may change due to bugfix / enhancements) or assess the validity of the trace output.
+#
+#################################################################################
+
+OUT_DIR=./results
+SNAPSHOT_DIR=./snapshots
+BIN_DIR=./bin/linux64/rel
+
+echo "Running trc_pkt_lister on snapshot directories."
+
+mkdir -p ${OUT_DIR}
+
+# === test the decode set ===
+export LD_LIBRARY_PATH=${BIN_DIR}/.
+
+
+# === test the C-API lib ===
+echo "Testing C-API"
+${BIN_DIR}/c_api_pkt_print_test -ss_path ${SNAPSHOT_DIR} -decode
+mv ./c_api_test.log ./${OUT_DIR}/c_api_test.ppl
diff --git a/decoder/tests/run_pkt_decode_tests.bash b/decoder/tests/run_pkt_decode_tests.bash
index 56b1cbfd38be..09f642b097c8 100755
--- a/decoder/tests/run_pkt_decode_tests.bash
+++ b/decoder/tests/run_pkt_decode_tests.bash
@@ -35,10 +35,20 @@
# may change due to bugfix / enhancements) or assess the validity of the trace output.
#
#################################################################################
+# Usage options:-
+# * default: run tests on binary + libs in ./bin/linux64/rel
+# run_pkt_decode_tests.bash
+#
+# * use installed opencsd libraries & program
+# run_pkt_decode_tests.bash use-installed
+#
+# * use supplied path for binary + libs (must have trailing /)
+# run_pkt_decode_tests.bash <custom>/<path>/
+#
OUT_DIR=./results
SNAPSHOT_DIR=./snapshots
-BIN_DIR=./bin/linux64/rel
+BIN_DIR=./bin/linux64/rel/
# directories for tests using full decode
declare -a test_dirs_decode=( "juno-ret-stck"
@@ -62,17 +72,41 @@ echo "Running trc_pkt_lister on snapshot directories."
mkdir -p ${OUT_DIR}
-# === test the decode set ===
-export LD_LIBRARY_PATH=${BIN_DIR}/.
+if [ "$1" == "use-installed" ]; then
+ BIN_DIR=""
+elif [ "$1" != "" ]; then
+ BIN_DIR=$1
+fi
+
+echo "Tests using BIN_DIR = ${BIN_DIR}"
+if [ "${BIN_DIR}" != "" ]; then
+ export LD_LIBRARY_PATH=${BIN_DIR}.
+ echo "LD_LIBRARY_PATH set to ${BIN_DIR}"
+fi
+
+# === test the decode set ===
for test_dir in "${test_dirs_decode[@]}"
do
echo "Testing $test_dir..."
- ${BIN_DIR}/trc_pkt_lister -ss_dir "${SNAPSHOT_DIR}/$test_dir" -decode -logfilename "${OUT_DIR}/$test_dir.ppl"
+ ${BIN_DIR}trc_pkt_lister -ss_dir "${SNAPSHOT_DIR}/$test_dir" -decode -logfilename "${OUT_DIR}/$test_dir.ppl"
echo "Done : Return $?"
done
+# === test a packet only example ===
+echo "Testing init-short-addr..."
+${BIN_DIR}trc_pkt_lister -ss_dir "${SNAPSHOT_DIR}/init-short-addr" -pkt_mon -logfilename "${OUT_DIR}/init-short-addr.ppl"
+
# === test the TPIU deformatter ===
echo "Testing a55-test-tpiu..."
-${BIN_DIR}/trc_pkt_lister -ss_dir "${SNAPSHOT_DIR}/a55-test-tpiu" -dstream_format -o_raw_packed -o_raw_unpacked -logfilename "${OUT_DIR}/a55-test-tpiu.ppl"
+${BIN_DIR}trc_pkt_lister -ss_dir "${SNAPSHOT_DIR}/a55-test-tpiu" -dstream_format -o_raw_packed -o_raw_unpacked -logfilename "${OUT_DIR}/a55-test-tpiu.ppl"
echo "Done : Return $?"
+
+# === test the C-API lib - this test prog is not installed ===
+if [ "$1" != "use-installed" ]; then
+ echo "Testing C-API library"
+ ${BIN_DIR}c_api_pkt_print_test -ss_path ${SNAPSHOT_DIR} -decode > /dev/null
+ echo "Done : Return $?"
+ echo "moving result file."
+ mv ./c_api_test.log ./${OUT_DIR}/c_api_test.ppl
+fi
diff --git a/decoder/tests/snapshots/Snowball/cpu_0.ini b/decoder/tests/snapshots/Snowball/cpu_0.ini
new file mode 100644
index 000000000000..04e8cf7bde2d
--- /dev/null
+++ b/decoder/tests/snapshots/Snowball/cpu_0.ini
@@ -0,0 +1,15 @@
+[device]
+name=cpu_0
+class=core
+type=Cortex-A9
+
+[regs]
+R15=0xC0008000
+R13=0
+CPSR=0x1D3
+
+[dump]
+file=kernel_dump.bin
+address=0xC0008000
+length=0x00050000
+
diff --git a/decoder/tests/snapshots/Snowball/cpu_1.ini b/decoder/tests/snapshots/Snowball/cpu_1.ini
new file mode 100644
index 000000000000..9bdd21966449
--- /dev/null
+++ b/decoder/tests/snapshots/Snowball/cpu_1.ini
@@ -0,0 +1,15 @@
+[device]
+name=cpu_1
+class=core
+type=Cortex-A9
+
+[regs]
+R15=0xC0008000
+R13=0
+CPSR=0x1D3
+
+[dump]
+file=kernel_dump.bin
+address=0xC0008000
+length=0x00050000
+
diff --git a/decoder/tests/snapshots/Snowball/cstrace.bin b/decoder/tests/snapshots/Snowball/cstrace.bin
new file mode 100644
index 000000000000..f828a687be08
--- /dev/null
+++ b/decoder/tests/snapshots/Snowball/cstrace.bin
Binary files differ
diff --git a/decoder/tests/snapshots/Snowball/device_2.ini b/decoder/tests/snapshots/Snowball/device_2.ini
new file mode 100644
index 000000000000..289d9290eaf1
--- /dev/null
+++ b/decoder/tests/snapshots/Snowball/device_2.ini
@@ -0,0 +1,10 @@
+[device]
+name=PTM_0
+class=trace_source
+type=PTM1.0
+
+[regs]
+ETMCR(0x000)=0x10001000
+ETMIDR(0x079)=0x411CF301
+ETMCCER(0x07A)=0x000008EA
+ETMTRACEIDR(0x080)=0x00000010
diff --git a/decoder/tests/snapshots/Snowball/device_3.ini b/decoder/tests/snapshots/Snowball/device_3.ini
new file mode 100644
index 000000000000..dfa0e92334ea
--- /dev/null
+++ b/decoder/tests/snapshots/Snowball/device_3.ini
@@ -0,0 +1,10 @@
+[device]
+name=PTM_1
+class=trace_source
+type=PTM1.0
+
+[regs]
+ETMCR(0x000)=0x10001000
+ETMIDR(0x079)=0x411CF301
+ETMCCER(0x07A)=0x000008EA
+ETMTRACEIDR(0x080)=0x00000011
diff --git a/decoder/tests/snapshots/Snowball/kernel_dump.bin b/decoder/tests/snapshots/Snowball/kernel_dump.bin
new file mode 100644
index 000000000000..3f0e26eedb7c
--- /dev/null
+++ b/decoder/tests/snapshots/Snowball/kernel_dump.bin
Binary files differ
diff --git a/decoder/tests/snapshots/Snowball/snapshot.ini b/decoder/tests/snapshots/Snowball/snapshot.ini
new file mode 100644
index 000000000000..370c950cfc92
--- /dev/null
+++ b/decoder/tests/snapshots/Snowball/snapshot.ini
@@ -0,0 +1,11 @@
+[snapshot]
+version=1.0
+
+[device_list]
+device0=cpu_0.ini
+device1=cpu_1.ini
+device2=device_2.ini
+device3=device_3.ini
+
+[trace]
+metadata=trace.ini
diff --git a/decoder/tests/snapshots/Snowball/trace.ini b/decoder/tests/snapshots/Snowball/trace.ini
new file mode 100644
index 000000000000..c00356a46c9e
--- /dev/null
+++ b/decoder/tests/snapshots/Snowball/trace.ini
@@ -0,0 +1,16 @@
+[trace_buffers]
+buffers=buffer0
+
+[buffer0]
+name=ETB_0
+file=cstrace.bin
+format=coresight
+
+[source_buffers]
+PTM_0=ETB_0
+PTM_1=ETB_0
+
+[core_trace_sources]
+cpu_0=PTM_0
+cpu_1=PTM_1
+
diff --git a/decoder/tests/snapshots/TC2/cpu_0.ini b/decoder/tests/snapshots/TC2/cpu_0.ini
new file mode 100644
index 000000000000..e7ce6790ccae
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/cpu_0.ini
@@ -0,0 +1,15 @@
+[device]
+name=cpu_0
+class=core
+type=Cortex-A7
+
+[regs]
+R15=0xC0008000
+R13=0
+CPSR=0x1D3
+
+[dump]
+file=kernel_dump.bin
+address=0xC0008000
+length=0x00050000
+
diff --git a/decoder/tests/snapshots/TC2/cpu_1.ini b/decoder/tests/snapshots/TC2/cpu_1.ini
new file mode 100644
index 000000000000..ba422c0cff88
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/cpu_1.ini
@@ -0,0 +1,15 @@
+[device]
+name=cpu_1
+class=core
+type=Cortex-A7
+
+[regs]
+R15=0xC0008000
+R13=0
+CPSR=0x1D3
+
+[dump]
+file=kernel_dump.bin
+address=0xC0008000
+length=0x00050000
+
diff --git a/decoder/tests/snapshots/TC2/cpu_2.ini b/decoder/tests/snapshots/TC2/cpu_2.ini
new file mode 100644
index 000000000000..a1bc632cb6ab
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/cpu_2.ini
@@ -0,0 +1,15 @@
+[device]
+name=cpu_2
+class=core
+type=Cortex-A7
+
+[regs]
+R15=0xC0008000
+R13=0
+CPSR=0x1D3
+
+[dump]
+file=kernel_dump.bin
+address=0xC0008000
+length=0x00050000
+
diff --git a/decoder/tests/snapshots/TC2/cpu_3.ini b/decoder/tests/snapshots/TC2/cpu_3.ini
new file mode 100644
index 000000000000..d6ccbc77d95c
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/cpu_3.ini
@@ -0,0 +1,15 @@
+[device]
+name=cpu_3
+class=core
+type=Cortex-A15
+
+[regs]
+R15=0xC0008000
+R13=0
+CPSR=0x1D3
+
+[dump]
+file=kernel_dump.bin
+address=0xC0008000
+length=0x00050000
+
diff --git a/decoder/tests/snapshots/TC2/cpu_4.ini b/decoder/tests/snapshots/TC2/cpu_4.ini
new file mode 100644
index 000000000000..29528af22c11
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/cpu_4.ini
@@ -0,0 +1,15 @@
+[device]
+name=cpu_4
+class=core
+type=Cortex-A15
+
+[regs]
+R15=0xC0008000
+R13=0
+CPSR=0x1D3
+
+[dump]
+file=kernel_dump.bin
+address=0xC0008000
+length=0x00050000
+
diff --git a/decoder/tests/snapshots/TC2/cstrace.bin b/decoder/tests/snapshots/TC2/cstrace.bin
new file mode 100644
index 000000000000..5c6e8b9589a3
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/cstrace.bin
Binary files differ
diff --git a/decoder/tests/snapshots/TC2/device_10.ini b/decoder/tests/snapshots/TC2/device_10.ini
new file mode 100644
index 000000000000..b2c0d2a31350
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/device_10.ini
@@ -0,0 +1,7 @@
+[device]
+name=ITM_0
+class=trace_source
+type=ITM
+
+[regs]
+ITM_CTRL(0x3A0)=0x00200006
diff --git a/decoder/tests/snapshots/TC2/device_5.ini b/decoder/tests/snapshots/TC2/device_5.ini
new file mode 100644
index 000000000000..caaf40c51da2
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/device_5.ini
@@ -0,0 +1,10 @@
+[device]
+name=ETM_0
+class=trace_source
+type=ETM3.5
+
+[regs]
+ETMCR(0x000)=0x10001860
+ETMIDR(0x079)=0x410CF250
+ETMCCER(0x07A)=0x344008F2
+ETMTRACEIDR(0x080)=0x00000010
diff --git a/decoder/tests/snapshots/TC2/device_6.ini b/decoder/tests/snapshots/TC2/device_6.ini
new file mode 100644
index 000000000000..e67dd3aca56f
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/device_6.ini
@@ -0,0 +1,10 @@
+[device]
+name=ETM_1
+class=trace_source
+type=ETM3.5
+
+[regs]
+ETMCR(0x000)=0x10001860
+ETMIDR(0x079)=0x410CF250
+ETMCCER(0x07A)=0x344008F2
+ETMTRACEIDR(0x080)=0x00000011
diff --git a/decoder/tests/snapshots/TC2/device_7.ini b/decoder/tests/snapshots/TC2/device_7.ini
new file mode 100644
index 000000000000..d2b3a513d030
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/device_7.ini
@@ -0,0 +1,10 @@
+[device]
+name=ETM_2
+class=trace_source
+type=ETM3.5
+
+[regs]
+ETMCR(0x000)=0x10001860
+ETMIDR(0x079)=0x410CF250
+ETMCCER(0x07A)=0x344008F2
+ETMTRACEIDR(0x080)=0x00000012
diff --git a/decoder/tests/snapshots/TC2/device_8.ini b/decoder/tests/snapshots/TC2/device_8.ini
new file mode 100644
index 000000000000..ccb3acdb3987
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/device_8.ini
@@ -0,0 +1,10 @@
+[device]
+name=PTM_0
+class=trace_source
+type=PTM1.1
+
+[regs]
+ETMCR(0x000)=0x10001000
+ETMIDR(0x079)=0x411CF312
+ETMCCER(0x07A)=0x34C01AC2
+ETMTRACEIDR(0x080)=0x00000013
diff --git a/decoder/tests/snapshots/TC2/device_9.ini b/decoder/tests/snapshots/TC2/device_9.ini
new file mode 100644
index 000000000000..1b5bcbfac2cd
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/device_9.ini
@@ -0,0 +1,10 @@
+[device]
+name=PTM_1
+class=trace_source
+type=PTM1.1
+
+[regs]
+ETMCR(0x000)=0x10001000
+ETMIDR(0x079)=0x411CF312
+ETMCCER(0x07A)=0x34C01AC2
+ETMTRACEIDR(0x080)=0x00000014
diff --git a/decoder/tests/snapshots/TC2/ds5-dumps/etmv3_0x10.txt b/decoder/tests/snapshots/TC2/ds5-dumps/etmv3_0x10.txt
new file mode 100644
index 000000000000..551a80534826
--- /dev/null
+++ b/decoder/tests/snapshots/TC2/ds5-dumps/etmv3_0x10.txt
@@ -0,0 +1,7518 @@
+Record Type Index Address 0x + Opcode Cycles Detail Branch Condition Failure
+Debug stop Debug stop
+Function 0 S:0xC002115C <Unknown>
+Instruction 0 S:0xC002115C 0x6963 1 LDR r3,[r4,#0x14] false
+Instruction 1 S:0xC002115E 0x4A06 23 LDR r2,[pc,#24] ; [0xC0021178] = 0xC06498C0 false
+Instruction 2 S:0xC0021160 0x019B 4 LSLS r3,r3,#6 false
+Instruction 3 S:0xC0021162 0x58D3 15 LDR r3,[r2,r3] false
+Instruction 4 S:0xC0021164 0x2B00 2 CMP r3,#0 false
+Instruction 5 S:0xC0021166 0xD0EA 0 BEQ {pc}-0x28 ; 0xc002113e true
+Instruction 6 S:0xC002113E 0x6863 44 LDR r3,[r4,#4] false
+Instruction 7 S:0xC0021140 0x3B01 2 SUBS r3,#1 false
+Instruction 8 S:0xC0021142 0x6063 1 STR r3,[r4,#4] false
+Instruction 9 S:0xC0021144 0xBD38 3 POP {r3-r5,pc} true
+Cycle Count 7695 Tracing disabled
+Info Tracing enabled
+Instruction 10 S:0xC004F698 0xB530 1 PUSH {r4,r5,lr} false
+Instruction 11 S:0xC004F69A 0xB083 2 SUB sp,sp,#0xc false
+Instruction 12 S:0xC004F69C 0xB500 3 PUSH {lr} false
+Instruction 13 S:0xC004F69E 0xF85DEB04 15 POP {lr} false
+Instruction 14 S:0xC004F6A2 0x4604 0 MOV r4,r0 false
+Instruction 15 S:0xC004F6A4 0x4668 1 MOV r0,sp false
+Instruction 16 S:0xC004F6A6 0xF7FFFFE5 1 BL {pc}-0x32 ; 0xc004f674 true
+Instruction 17 S:0xC004F674 0xB508 2 PUSH {r3,lr} false
+Instruction 18 S:0xC004F676 0xB500 1 PUSH {lr} false
+Instruction 19 S:0xC004F678 0xF85DEB04 2 POP {lr} false
+Instruction 20 S:0xC004F67C 0xF7FFFC84 1 BL {pc}-0x6f4 ; 0xc004ef88 true
+Instruction 21 S:0xC004EF88 0xE92D47F0 2 PUSH {r4-r10,lr} false
+Instruction 22 S:0xC004EF8C 0xB084 4 SUB sp,sp,#0x10 false
+Instruction 23 S:0xC004EF8E 0xB500 3 PUSH {lr} false
+Instruction 24 S:0xC004EF90 0xF85DEB04 2 POP {lr} false
+Instruction 25 S:0xC004EF94 0x4D3E 2 LDR r5,[pc,#248] ; [0xC004F090] = 0xC064D1C0 false
+Instruction 26 S:0xC004EF96 0x4682 0 MOV r10,r0 false
+Instruction 27 S:0xC004EF98 0x462C 2 MOV r4,r5 false
+Instruction 28 S:0xC004EF9A 0xF8D57090 3 LDR r7,[r5,#0x90] false
+Instruction 29 S:0xC004EF9E 0x07FE 3 LSLS r6,r7,#31 false
+Instruction 30 S:0xC004EFA0 0xD46A 0 BMI {pc}+0xd8 ; 0xc004f078 true fail
+Instruction 31 S:0xC004EFA2 0xF3BF8F5F 1 DMB false
+Instruction 32 S:0xC004EFA6 0x6BA3 28 LDR r3,[r4,#0x38] false
+Instruction 33 S:0xC004EFA8 0xF8CA3000 3 STR r3,[r10,#0] false
+Instruction 34 S:0xC004EFAC 0x6826 1 LDR r6,[r4,#0] false
+Instruction 35 S:0xC004EFAE 0x4630 2 MOV r0,r6 false
+Instruction 36 S:0xC004EFB0 0x6833 3 LDR r3,[r6,#0] false
+Instruction 37 S:0xC004EFB2 0x4798 1 BLX r3 true
+Timestamp Timestamp: 562536959839
+Cycle Count 42 Tracing disabled
+Info Tracing enabled
+Instruction 38 S:0xC004EFB4 0xE9D62302 1 LDRD r2,r3,[r6,#8] false
+Instruction 39 S:0xC004EFB8 0xE9CD2300 2 STRD r2,r3,[sp,#0] false
+Instruction 40 S:0xC004EFBC 0xE9D62304 1 LDRD r2,r3,[r6,#0x10] false
+Instruction 41 S:0xC004EFC0 0xE9CD2302 1 STRD r2,r3,[sp,#8] false
+Instruction 42 S:0xC004EFC4 0x6862 1 LDR r2,[r4,#4] false
+Instruction 43 S:0xC004EFC6 0x6C63 1 LDR r3,[r4,#0x44] false
+Instruction 44 S:0xC004EFC8 0x4680 0 MOV r8,r0 false
+Instruction 45 S:0xC004EFCA 0x4689 1 MOV r9,r1 false
+Instruction 46 S:0xC004EFCC 0x6C20 1 LDR r0,[r4,#0x40] false
+Instruction 47 S:0xC004EFCE 0x68A1 1 LDR r1,[r4,#8] false
+Instruction 48 S:0xC004EFD0 0xF3BF8F5F 1 DMB false
+Instruction 49 S:0xC004EFD4 0xF8D46090 27 LDR r6,[r4,#0x90] false
+Instruction 50 S:0xC004EFD8 0x42B7 2 CMP r7,r6 false
+Instruction 51 S:0xC004EFDA 0xD1DE 0 BNE {pc}-0x40 ; 0xc004ef9a true fail
+Instruction 52 S:0xC004EFDC 0xE9DD4500 1 LDRD r4,r5,[sp,#0] false
+Instruction 53 S:0xC004EFE0 0xE9DD6702 1 LDRD r6,r7,[sp,#8] false
+Instruction 54 S:0xC004EFE4 0xEBB80804 1 SUBS r8,r8,r4 false
+Instruction 55 S:0xC004EFE8 0xEB690905 1 SBC r9,r9,r5 false
+Instruction 56 S:0xC004EFEC 0x4604 0 MOV r4,r0 false
+Instruction 57 S:0xC004EFEE 0xEA080806 1 AND r8,r8,r6 false
+Instruction 58 S:0xC004EFF2 0xEA090907 1 AND r9,r9,r7 false
+Instruction 59 S:0xC004EFF6 0xF1C10020 1 RSB r0,r1,#0x20 false
+Instruction 60 S:0xC004EFFA 0xF8DAC000 1 LDR r12,[r10,#0] false
+Instruction 61 S:0xC004EFFE 0xFBA86702 1 UMULL r6,r7,r8,r2 false
+Instruction 62 S:0xC004F002 0x19A4 2 ADDS r4,r4,r6 false
+Instruction 63 S:0xC004F004 0xFB027709 1 MLA r7,r2,r9,r7 false
+Instruction 64 S:0xC004F008 0xFA24F201 1 LSR r2,r4,r1 false
+Instruction 65 S:0xC004F00C 0xEB430507 1 ADC r5,r3,r7 false
+Instruction 66 S:0xC004F010 0xF1B10620 0 SUBS r6,r1,#0x20 false
+Instruction 67 S:0xC004F014 0xFA05F000 2 LSL r0,r5,r0 false
+Instruction 68 S:0xC004F018 0xBF58 0 IT PL false
+Instruction 69 S:0xC004F01A 0xFA45F606 1 ASR r6,r5,r6 false fail
+Instruction 70 S:0xC004F01E 0xEA420200 1 ORR r2,r2,r0 false
+Instruction 71 S:0xC004F022 0xFA45F301 1 ASR r3,r5,r1 false
+Instruction 72 S:0xC004F026 0xBF58 0 IT PL false
+Instruction 73 S:0xC004F028 0x4332 1 ORRS r2,r2,r6 false fail
+Instruction 74 S:0xC004F02A 0xA715 0 ADR r7,{pc}+0x56 ; 0xc004f080 false
+Instruction 75 S:0xC004F02C 0xE9D76700 3 LDRD r6,r7,[r7,#0] false
+Instruction 76 S:0xC004F030 0x429F 2 CMP r7,r3 false
+Instruction 77 S:0xC004F032 0xBF08 0 IT EQ false
+Instruction 78 S:0xC004F034 0x4296 1 CMP r6,r2 false
+Instruction 79 S:0xC004F036 0xD21D 0 BCS {pc}+0x3e ; 0xc004f074 true
+Instruction 80 S:0xC004F074 0x2600 8 MOVS r6,#0 false
+Instruction 81 S:0xC004F076 0xE7EE 0 B {pc}-0x20 ; 0xc004f056 true
+Instruction 82 S:0xC004F056 0x4B0F 3 LDR r3,[pc,#60] ; [0xC004F094] = 0xC05FC59C false
+Instruction 83 S:0xC004F058 0x4466 1 ADD r6,r6,r12 false
+Instruction 84 S:0xC004F05A 0xF8CA6000 1 STR r6,[r10,#0] false
+Instruction 85 S:0xC004F05E 0xF8CA2004 1 STR r2,[r10,#4] false
+Instruction 86 S:0xC004F062 0x681B 3 LDR r3,[r3,#0] false
+Instruction 87 S:0xC004F064 0x2B00 2 CMP r3,#0 false
+Instruction 88 S:0xC004F066 0xBF14 0 ITE NE false
+Instruction 89 S:0xC004F068 0xF06F000A 1 MVN r0,#0xa false fail
+Instruction 90 S:0xC004F06C 0x2000 0 MOVS r0,#0 false
+Instruction 91 S:0xC004F06E 0xB004 1 ADD sp,sp,#0x10 false
+Instruction 92 S:0xC004F070 0xE8BD87F0 3 POP {r4-r10,pc} true
+Instruction 93 S:0xC004F680 0xB900 4 CBNZ r0,{pc}+4 ; 0xc004f684 true fail
+Instruction 94 S:0xC004F682 0xBD08 2 POP {r3,pc} true
+Instruction 95 S:0xC004F6AA 0x9801 3 LDR r0,[sp,#4] false
+Instruction 96 S:0xC004F6AC 0x9D00 1 LDR r5,[sp,#0] false
+Instruction 97 S:0xC004F6AE 0xF44F414A 0 MOV r1,#0xca00 false
+Instruction 98 S:0xC004F6B2 0x4602 1 MOV r2,r0 false
+Instruction 99 S:0xC004F6B4 0xF6C3319A 0 MOVT r1,#0x3b9a false
+Instruction 100 S:0xC004F6B8 0x2300 1 MOVS r3,#0 false
+Instruction 101 S:0xC004F6BA 0x4620 0 MOV r0,r4 false
+Instruction 102 S:0xC004F6BC 0xFBC12305 2 SMLAL r2,r3,r1,r5 false
+Instruction 103 S:0xC004F6C0 0xE9C42300 1 STRD r2,r3,[r4,#0] false
+Instruction 104 S:0xC004F6C4 0xB003 1 ADD sp,sp,#0xc false
+Instruction 105 S:0xC004F6C6 0xBD30 3 POP {r4,r5,pc} true
+Cycle Count 6046 Tracing disabled
+Info Tracing enabled
+Instruction 106 S:0xC0020A14 0xB500 1 PUSH {lr} false
+Instruction 107 S:0xC0020A16 0xF85DEB04 2 POP {lr} false
+Instruction 108 S:0xC0020A1A 0x466A 1 MOV r2,sp false
+Instruction 109 S:0xC0020A1C 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 110 S:0xC0020A20 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 111 S:0xC0020A24 0x685A 5 LDR r2,[r3,#4] false
+Instruction 112 S:0xC0020A26 0xF5027200 2 ADD r2,r2,#0x200 false
+Instruction 113 S:0xC0020A2A 0x605A 1 STR r2,[r3,#4] false
+Instruction 114 S:0xC0020A2C 0x4770 1 BX lr true
+Cycle Count 188 Tracing disabled
+Info Tracing enabled
+Instruction 115 S:0xC0021104 0xB538 1 PUSH {r3-r5,lr} false
+Instruction 116 S:0xC0021106 0xB500 4 PUSH {lr} false
+Instruction 117 S:0xC0021108 0xF85DEB04 2 POP {lr} false
+Instruction 118 S:0xC002110C 0x466B 1 MOV r3,sp false
+Instruction 119 S:0xC002110E 0xF42354FF 1 BIC r4,r3,#0x1fe0 false
+Instruction 120 S:0xC0021112 0x2300 0 MOVS r3,#0 false
+Instruction 121 S:0xC0021114 0xF024041F 1 BIC r4,r4,#0x1f false
+Instruction 122 S:0xC0021118 0xF2C033FF 0 MOVT r3,#0x3ff false
+Instruction 123 S:0xC002111C 0x6862 3 LDR r2,[r4,#4] false
+Instruction 124 S:0xC002111E 0x4013 2 ANDS r3,r3,r2 false
+Instruction 125 S:0xC0021120 0xB98B 1 CBNZ r3,{pc}+0x26 ; 0xc0021146 true fail
+Instruction 126 S:0xC0021122 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 127 S:0xC0021126 0x061B 3 LSLS r3,r3,#24 false
+Instruction 128 S:0xC0021128 0xD40D 0 BMI {pc}+0x1e ; 0xc0021146 true fail
+Instruction 129 S:0xC002112A 0x6863 1 LDR r3,[r4,#4] false
+Instruction 130 S:0xC002112C 0xF46F70FF 0 MVN r0,#0x1fe false
+Instruction 131 S:0xC0021130 0x181B 2 ADDS r3,r3,r0 false
+Instruction 132 S:0xC0021132 0x6063 1 STR r3,[r4,#4] false
+Instruction 133 S:0xC0021134 0xF0234378 0 BIC r3,r3,#0xf8000000 false
+Instruction 134 S:0xC0021138 0xF02303FF 1 BIC r3,r3,#0xff false
+Instruction 135 S:0xC002113C 0xB173 1 CBZ r3,{pc}+0x20 ; 0xc002115c true
+Instruction 136 S:0xC002115C 0x6963 1 LDR r3,[r4,#0x14] false
+Instruction 137 S:0xC002115E 0x4A06 3 LDR r2,[pc,#24] ; [0xC0021178] = 0xC06498C0 false
+Instruction 138 S:0xC0021160 0x019B 5 LSLS r3,r3,#6 false
+Instruction 139 S:0xC0021162 0x58D3 15 LDR r3,[r2,r3] false
+Instruction 140 S:0xC0021164 0x2B00 2 CMP r3,#0 false
+Instruction 141 S:0xC0021166 0xD0EA 0 BEQ {pc}-0x28 ; 0xc002113e true
+Instruction 142 S:0xC002113E 0x6863 11 LDR r3,[r4,#4] false
+Instruction 143 S:0xC0021140 0x3B01 2 SUBS r3,#1 false
+Instruction 144 S:0xC0021142 0x6063 1 STR r3,[r4,#4] false
+Instruction 145 S:0xC0021144 0xBD38 1 POP {r3-r5,pc} true
+Cycle Count 491 Tracing disabled
+Info Tracing enabled
+Instruction 146 S:0xC0020A14 0xB500 1 PUSH {lr} false
+Instruction 147 S:0xC0020A16 0xF85DEB04 2 POP {lr} false
+Instruction 148 S:0xC0020A1A 0x466A 1 MOV r2,sp false
+Instruction 149 S:0xC0020A1C 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 150 S:0xC0020A20 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 151 S:0xC0020A24 0x685A 5 LDR r2,[r3,#4] false
+Instruction 152 S:0xC0020A26 0xF5027200 2 ADD r2,r2,#0x200 false
+Instruction 153 S:0xC0020A2A 0x605A 1 STR r2,[r3,#4] false
+Instruction 154 S:0xC0020A2C 0x4770 1 BX lr true
+Cycle Count 768 Tracing disabled
+Info Tracing enabled
+Instruction 155 S:0xC0020A14 0xB500 1 PUSH {lr} false
+Instruction 156 S:0xC0020A16 0xF85DEB04 2 POP {lr} false
+Instruction 157 S:0xC0020A1A 0x466A 1 MOV r2,sp false
+Instruction 158 S:0xC0020A1C 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 159 S:0xC0020A20 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 160 S:0xC0020A24 0x685A 3 LDR r2,[r3,#4] false
+Instruction 161 S:0xC0020A26 0xF5027200 2 ADD r2,r2,#0x200 false
+Instruction 162 S:0xC0020A2A 0x605A 1 STR r2,[r3,#4] false
+Instruction 163 S:0xC0020A2C 0x4770 1 BX lr true
+Cycle Count 3715 Tracing disabled
+Info Tracing enabled
+Instruction 164 S:0xC004F698 0xB530 1 PUSH {r4,r5,lr} false
+Instruction 165 S:0xC004F69A 0xB083 2 SUB sp,sp,#0xc false
+Instruction 166 S:0xC004F69C 0xB500 3 PUSH {lr} false
+Instruction 167 S:0xC004F69E 0xF85DEB04 2 POP {lr} false
+Instruction 168 S:0xC004F6A2 0x4604 0 MOV r4,r0 false
+Instruction 169 S:0xC004F6A4 0x4668 1 MOV r0,sp false
+Instruction 170 S:0xC004F6A6 0xF7FFFFE5 1 BL {pc}-0x32 ; 0xc004f674 true
+Instruction 171 S:0xC004F674 0xB508 1 PUSH {r3,lr} false
+Instruction 172 S:0xC004F676 0xB500 1 PUSH {lr} false
+Instruction 173 S:0xC004F678 0xF85DEB04 2 POP {lr} false
+Instruction 174 S:0xC004F67C 0xF7FFFC84 1 BL {pc}-0x6f4 ; 0xc004ef88 true
+Instruction 175 S:0xC004EF88 0xE92D47F0 2 PUSH {r4-r10,lr} false
+Instruction 176 S:0xC004EF8C 0xB084 4 SUB sp,sp,#0x10 false
+Instruction 177 S:0xC004EF8E 0xB500 3 PUSH {lr} false
+Instruction 178 S:0xC004EF90 0xF85DEB04 2 POP {lr} false
+Instruction 179 S:0xC004EF94 0x4D3E 12 LDR r5,[pc,#248] ; [0xC004F090] = 0xC064D1C0 false
+Instruction 180 S:0xC004EF96 0x4682 0 MOV r10,r0 false
+Instruction 181 S:0xC004EF98 0x462C 2 MOV r4,r5 false
+Instruction 182 S:0xC004EF9A 0xF8D57090 3 LDR r7,[r5,#0x90] false
+Instruction 183 S:0xC004EF9E 0x07FE 3 LSLS r6,r7,#31 false
+Instruction 184 S:0xC004EFA0 0xD46A 0 BMI {pc}+0xd8 ; 0xc004f078 true fail
+Instruction 185 S:0xC004EFA2 0xF3BF8F5F 8 DMB false
+Instruction 186 S:0xC004EFA6 0x6BA3 28 LDR r3,[r4,#0x38] false
+Instruction 187 S:0xC004EFA8 0xF8CA3000 3 STR r3,[r10,#0] false
+Instruction 188 S:0xC004EFAC 0x6826 1 LDR r6,[r4,#0] false
+Instruction 189 S:0xC004EFAE 0x4630 2 MOV r0,r6 false
+Instruction 190 S:0xC004EFB0 0x6833 3 LDR r3,[r6,#0] false
+Instruction 191 S:0xC004EFB2 0x4798 1 BLX r3 true
+Timestamp Timestamp: 562536960633
+Cycle Count 52 Tracing disabled
+Info Tracing enabled
+Instruction 192 S:0xC004EFB4 0xE9D62302 1 LDRD r2,r3,[r6,#8] false
+Instruction 193 S:0xC004EFB8 0xE9CD2300 2 STRD r2,r3,[sp,#0] false
+Instruction 194 S:0xC004EFBC 0xE9D62304 1 LDRD r2,r3,[r6,#0x10] false
+Instruction 195 S:0xC004EFC0 0xE9CD2302 1 STRD r2,r3,[sp,#8] false
+Instruction 196 S:0xC004EFC4 0x6862 1 LDR r2,[r4,#4] false
+Instruction 197 S:0xC004EFC6 0x6C63 1 LDR r3,[r4,#0x44] false
+Instruction 198 S:0xC004EFC8 0x4680 0 MOV r8,r0 false
+Instruction 199 S:0xC004EFCA 0x4689 1 MOV r9,r1 false
+Instruction 200 S:0xC004EFCC 0x6C20 1 LDR r0,[r4,#0x40] false
+Instruction 201 S:0xC004EFCE 0x68A1 1 LDR r1,[r4,#8] false
+Instruction 202 S:0xC004EFD0 0xF3BF8F5F 1 DMB false
+Instruction 203 S:0xC004EFD4 0xF8D46090 27 LDR r6,[r4,#0x90] false
+Instruction 204 S:0xC004EFD8 0x42B7 2 CMP r7,r6 false
+Instruction 205 S:0xC004EFDA 0xD1DE 0 BNE {pc}-0x40 ; 0xc004ef9a true fail
+Instruction 206 S:0xC004EFDC 0xE9DD4500 1 LDRD r4,r5,[sp,#0] false
+Instruction 207 S:0xC004EFE0 0xE9DD6702 1 LDRD r6,r7,[sp,#8] false
+Instruction 208 S:0xC004EFE4 0xEBB80804 1 SUBS r8,r8,r4 false
+Instruction 209 S:0xC004EFE8 0xEB690905 1 SBC r9,r9,r5 false
+Instruction 210 S:0xC004EFEC 0x4604 0 MOV r4,r0 false
+Instruction 211 S:0xC004EFEE 0xEA080806 1 AND r8,r8,r6 false
+Instruction 212 S:0xC004EFF2 0xEA090907 1 AND r9,r9,r7 false
+Instruction 213 S:0xC004EFF6 0xF1C10020 1 RSB r0,r1,#0x20 false
+Instruction 214 S:0xC004EFFA 0xF8DAC000 1 LDR r12,[r10,#0] false
+Instruction 215 S:0xC004EFFE 0xFBA86702 1 UMULL r6,r7,r8,r2 false
+Instruction 216 S:0xC004F002 0x19A4 2 ADDS r4,r4,r6 false
+Instruction 217 S:0xC004F004 0xFB027709 1 MLA r7,r2,r9,r7 false
+Instruction 218 S:0xC004F008 0xFA24F201 1 LSR r2,r4,r1 false
+Instruction 219 S:0xC004F00C 0xEB430507 1 ADC r5,r3,r7 false
+Instruction 220 S:0xC004F010 0xF1B10620 0 SUBS r6,r1,#0x20 false
+Instruction 221 S:0xC004F014 0xFA05F000 2 LSL r0,r5,r0 false
+Instruction 222 S:0xC004F018 0xBF58 0 IT PL false
+Instruction 223 S:0xC004F01A 0xFA45F606 1 ASR r6,r5,r6 false fail
+Instruction 224 S:0xC004F01E 0xEA420200 1 ORR r2,r2,r0 false
+Instruction 225 S:0xC004F022 0xFA45F301 1 ASR r3,r5,r1 false
+Instruction 226 S:0xC004F026 0xBF58 0 IT PL false
+Instruction 227 S:0xC004F028 0x4332 1 ORRS r2,r2,r6 false fail
+Instruction 228 S:0xC004F02A 0xA715 0 ADR r7,{pc}+0x56 ; 0xc004f080 false
+Instruction 229 S:0xC004F02C 0xE9D76700 3 LDRD r6,r7,[r7,#0] false
+Instruction 230 S:0xC004F030 0x429F 2 CMP r7,r3 false
+Instruction 231 S:0xC004F032 0xBF08 0 IT EQ false
+Instruction 232 S:0xC004F034 0x4296 1 CMP r6,r2 false
+Instruction 233 S:0xC004F036 0xD21D 0 BCS {pc}+0x3e ; 0xc004f074 true
+Instruction 234 S:0xC004F074 0x2600 1 MOVS r6,#0 false
+Instruction 235 S:0xC004F076 0xE7EE 0 B {pc}-0x20 ; 0xc004f056 true
+Instruction 236 S:0xC004F056 0x4B0F 1 LDR r3,[pc,#60] ; [0xC004F094] = 0xC05FC59C false
+Instruction 237 S:0xC004F058 0x4466 1 ADD r6,r6,r12 false
+Instruction 238 S:0xC004F05A 0xF8CA6000 1 STR r6,[r10,#0] false
+Instruction 239 S:0xC004F05E 0xF8CA2004 1 STR r2,[r10,#4] false
+Instruction 240 S:0xC004F062 0x681B 13 LDR r3,[r3,#0] false
+Instruction 241 S:0xC004F064 0x2B00 2 CMP r3,#0 false
+Instruction 242 S:0xC004F066 0xBF14 0 ITE NE false
+Instruction 243 S:0xC004F068 0xF06F000A 1 MVN r0,#0xa false fail
+Instruction 244 S:0xC004F06C 0x2000 0 MOVS r0,#0 false
+Instruction 245 S:0xC004F06E 0xB004 1 ADD sp,sp,#0x10 false
+Instruction 246 S:0xC004F070 0xE8BD87F0 3 POP {r4-r10,pc} true
+Instruction 247 S:0xC004F680 0xB900 4 CBNZ r0,{pc}+4 ; 0xc004f684 true fail
+Instruction 248 S:0xC004F682 0xBD08 2 POP {r3,pc} true
+Instruction 249 S:0xC004F6AA 0x9801 3 LDR r0,[sp,#4] false
+Instruction 250 S:0xC004F6AC 0x9D00 1 LDR r5,[sp,#0] false
+Instruction 251 S:0xC004F6AE 0xF44F414A 0 MOV r1,#0xca00 false
+Instruction 252 S:0xC004F6B2 0x4602 1 MOV r2,r0 false
+Instruction 253 S:0xC004F6B4 0xF6C3319A 0 MOVT r1,#0x3b9a false
+Instruction 254 S:0xC004F6B8 0x2300 1 MOVS r3,#0 false
+Instruction 255 S:0xC004F6BA 0x4620 0 MOV r0,r4 false
+Instruction 256 S:0xC004F6BC 0xFBC12305 2 SMLAL r2,r3,r1,r5 false
+Instruction 257 S:0xC004F6C0 0xE9C42300 1 STRD r2,r3,[r4,#0] false
+Instruction 258 S:0xC004F6C4 0xB003 1 ADD sp,sp,#0xc false
+Instruction 259 S:0xC004F6C6 0xBD30 3 POP {r4,r5,pc} true
+Cycle Count 6649 Tracing disabled
+Info Tracing enabled
+Instruction 260 S:0xC0021104 0xB538 1 PUSH {r3-r5,lr} false
+Instruction 261 S:0xC0021106 0xB500 4 PUSH {lr} false
+Instruction 262 S:0xC0021108 0xF85DEB04 2 POP {lr} false
+Instruction 263 S:0xC002110C 0x466B 1 MOV r3,sp false
+Instruction 264 S:0xC002110E 0xF42354FF 1 BIC r4,r3,#0x1fe0 false
+Instruction 265 S:0xC0021112 0x2300 0 MOVS r3,#0 false
+Instruction 266 S:0xC0021114 0xF024041F 1 BIC r4,r4,#0x1f false
+Instruction 267 S:0xC0021118 0xF2C033FF 0 MOVT r3,#0x3ff false
+Instruction 268 S:0xC002111C 0x6862 5 LDR r2,[r4,#4] false
+Instruction 269 S:0xC002111E 0x4013 2 ANDS r3,r3,r2 false
+Instruction 270 S:0xC0021120 0xB98B 1 CBNZ r3,{pc}+0x26 ; 0xc0021146 true fail
+Instruction 271 S:0xC0021122 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 272 S:0xC0021126 0x061B 3 LSLS r3,r3,#24 false
+Instruction 273 S:0xC0021128 0xD40D 0 BMI {pc}+0x1e ; 0xc0021146 true fail
+Instruction 274 S:0xC002112A 0x6863 1 LDR r3,[r4,#4] false
+Instruction 275 S:0xC002112C 0xF46F70FF 0 MVN r0,#0x1fe false
+Instruction 276 S:0xC0021130 0x181B 2 ADDS r3,r3,r0 false
+Instruction 277 S:0xC0021132 0x6063 1 STR r3,[r4,#4] false
+Instruction 278 S:0xC0021134 0xF0234378 0 BIC r3,r3,#0xf8000000 false
+Instruction 279 S:0xC0021138 0xF02303FF 1 BIC r3,r3,#0xff false
+Instruction 280 S:0xC002113C 0xB173 1 CBZ r3,{pc}+0x20 ; 0xc002115c true fail
+Instruction 281 S:0xC002113E 0x6863 8 LDR r3,[r4,#4] false
+Instruction 282 S:0xC0021140 0x3B01 2 SUBS r3,#1 false
+Instruction 283 S:0xC0021142 0x6063 1 STR r3,[r4,#4] false
+Instruction 284 S:0xC0021144 0xBD38 1 POP {r3-r5,pc} true
+Cycle Count 25 Tracing disabled
+Info Tracing enabled
+Instruction 285 S:0xC0021104 0xB538 1 PUSH {r3-r5,lr} false
+Instruction 286 S:0xC0021106 0xB500 4 PUSH {lr} false
+Instruction 287 S:0xC0021108 0xF85DEB04 2 POP {lr} false
+Instruction 288 S:0xC002110C 0x466B 1 MOV r3,sp false
+Instruction 289 S:0xC002110E 0xF42354FF 1 BIC r4,r3,#0x1fe0 false
+Instruction 290 S:0xC0021112 0x2300 0 MOVS r3,#0 false
+Instruction 291 S:0xC0021114 0xF024041F 1 BIC r4,r4,#0x1f false
+Instruction 292 S:0xC0021118 0xF2C033FF 0 MOVT r3,#0x3ff false
+Instruction 293 S:0xC002111C 0x6862 3 LDR r2,[r4,#4] false
+Instruction 294 S:0xC002111E 0x4013 2 ANDS r3,r3,r2 false
+Instruction 295 S:0xC0021120 0xB98B 1 CBNZ r3,{pc}+0x26 ; 0xc0021146 true fail
+Instruction 296 S:0xC0021122 0xF3EF8300 15 MRS r3,APSR ; formerly CPSR false
+Instruction 297 S:0xC0021126 0x061B 3 LSLS r3,r3,#24 false
+Instruction 298 S:0xC0021128 0xD40D 1 BMI {pc}+0x1e ; 0xc0021146 true fail
+Instruction 299 S:0xC002112A 0x6863 1 LDR r3,[r4,#4] false
+Instruction 300 S:0xC002112C 0xF46F70FF 0 MVN r0,#0x1fe false
+Instruction 301 S:0xC0021130 0x181B 2 ADDS r3,r3,r0 false
+Instruction 302 S:0xC0021132 0x6063 1 STR r3,[r4,#4] false
+Instruction 303 S:0xC0021134 0xF0234378 0 BIC r3,r3,#0xf8000000 false
+Instruction 304 S:0xC0021138 0xF02303FF 1 BIC r3,r3,#0xff false
+Instruction 305 S:0xC002113C 0xB173 1 CBZ r3,{pc}+0x20 ; 0xc002115c true
+Instruction 306 S:0xC002115C 0x6963 8 LDR r3,[r4,#0x14] false
+Instruction 307 S:0xC002115E 0x4A06 1 LDR r2,[pc,#24] ; [0xC0021178] = 0xC06498C0 false
+Instruction 308 S:0xC0021160 0x019B 2 LSLS r3,r3,#6 false
+Instruction 309 S:0xC0021162 0x58D3 5 LDR r3,[r2,r3] false
+Instruction 310 S:0xC0021164 0x2B00 2 CMP r3,#0 false
+Instruction 311 S:0xC0021166 0xD0EA 0 BEQ {pc}-0x28 ; 0xc002113e true
+Instruction 312 S:0xC002113E 0x6863 8 LDR r3,[r4,#4] false
+Instruction 313 S:0xC0021140 0x3B01 2 SUBS r3,#1 false
+Instruction 314 S:0xC0021142 0x6063 1 STR r3,[r4,#4] false
+Instruction 315 S:0xC0021144 0xBD38 1 POP {r3-r5,pc} true
+Cycle Count 558 Tracing disabled
+Info Tracing enabled
+Instruction 316 S:0xC0025DC4 0xE92D41F0 1 PUSH {r4-r8,lr} false
+Instruction 317 S:0xC0025DC8 0xB082 3 SUB sp,sp,#8 false
+Instruction 318 S:0xC0025DCA 0xB500 3 PUSH {lr} false
+Instruction 319 S:0xC0025DCC 0xF85DEB04 2 POP {lr} false
+Instruction 320 S:0xC0025DD0 0x6983 1 LDR r3,[r0,#0x18] false
+Instruction 321 S:0xC0025DD2 0x4604 0 MOV r4,r0 false
+Instruction 322 S:0xC0025DD4 0x460E 1 MOV r6,r1 false
+Instruction 323 S:0xC0025DD6 0x2B00 1 CMP r3,#0 false
+Instruction 324 S:0xC0025DD8 0x4677 0 MOV r7,lr false
+Instruction 325 S:0xC0025DDA 0xBFA8 1 IT GE false
+Instruction 326 S:0xC0025DDC 0x18CD 1 ADDS r5,r1,r3 false fail
+Instruction 327 S:0xC0025DDE 0xDB55 0 BLT {pc}+0xae ; 0xc0025e8c true
+Instruction 328 S:0xC0025E8C 0x4B21 39 LDR r3,[pc,#132] ; [0xC0025F14] = 0xC05F60C0 false
+Instruction 329 S:0xC0025E8E 0x681D 5 LDR r5,[r3,#0] false
+Instruction 330 S:0xC0025E90 0x1B4D 2 SUBS r5,r1,r5 false
+Instruction 331 S:0xC0025E92 0x2DFF 1 CMP r5,#0xff false
+Instruction 332 S:0xC0025E94 0xDDA9 0 BLE {pc}-0xaa ; 0xc0025dea true
+Instruction 333 S:0xC0025DEA 0x6823 5 LDR r3,[r4,#0] false
+Instruction 334 S:0xC0025DEC 0xB113 2 CBZ r3,{pc}+8 ; 0xc0025df4 true
+Instruction 335 S:0xC0025DF4 0x4B42 1 LDR r3,[pc,#264] ; [0xC0025F00] false
+Instruction 336 S:0xC0025DF6 0x681B 5 LDR r3,[r3,#0] false
+Instruction 337 S:0xC0025DF8 0x2B00 2 CMP r3,#0 false
+Instruction 338 S:0xC0025DFA 0xD16A 0 BNE {pc}+0xd8 ; 0xc0025ed2 true fail
+Instruction 339 S:0xC0025DFC 0x6923 1 LDR r3,[r4,#0x10] false
+Instruction 340 S:0xC0025DFE 0x2B00 2 CMP r3,#0 false
+Instruction 341 S:0xC0025E00 0xD07C 9 BEQ {pc}+0xfc ; 0xc0025efc true fail
+Instruction 342 S:0xC0025E02 0xA901 21 ADD r1,sp,#4 false
+Instruction 343 S:0xC0025E04 0x4620 0 MOV r0,r4 false
+Instruction 344 S:0xC0025E06 0xF7FFFD61 1 BL {pc}-0x53a ; 0xc00258cc true
+Instruction 345 S:0xC00258CC 0xB5F8 18 PUSH {r3-r7,lr} false
+Instruction 346 S:0xC00258CE 0xB500 5 PUSH {lr} false
+Instruction 347 S:0xC00258D0 0xF85DEB04 2 POP {lr} false
+Instruction 348 S:0xC00258D4 0x4606 0 MOV r6,r0 false
+Instruction 349 S:0xC00258D6 0x460F 1 MOV r7,r1 false
+Instruction 350 S:0xC00258D8 0x68F5 2 LDR r5,[r6,#0xc] false
+Instruction 351 S:0xC00258DA 0xF0350403 2 BICS r4,r5,#3 false
+Instruction 352 S:0xC00258DE 0x4620 1 MOV r0,r4 false
+Instruction 353 S:0xC00258E0 0xD00A 5 BEQ {pc}+0x18 ; 0xc00258f8 true fail
+Instruction 354 S:0xC00258E2 0xF3BEFE81 1 BL {pc}+0x3bed06 ; 0xc03e45e8 true
+Cycle Count 123 Tracing disabled
+Info Tracing enabled
+Instruction 355 S:0xC00258E6 0x6038 1 STR r0,[r7,#0] false
+Instruction 356 S:0xC00258E8 0x4601 1 MOV r1,r0 false
+Instruction 357 S:0xC00258EA 0x68F2 1 LDR r2,[r6,#0xc] false
+Instruction 358 S:0xC00258EC 0x4620 0 MOV r0,r4 false
+Instruction 359 S:0xC00258EE 0x4295 2 CMP r5,r2 false
+Instruction 360 S:0xC00258F0 0xD100 0 BNE {pc}+4 ; 0xc00258f4 true fail
+Instruction 361 S:0xC00258F2 0xBDF8 1 POP {r3-r7,pc} true
+Instruction 362 S:0xC0025E0A 0x2200 3 MOVS r2,#0 false
+Instruction 363 S:0xC0025E0C 0x4607 0 MOV r7,r0 false
+Instruction 364 S:0xC0025E0E 0x4620 1 MOV r0,r4 false
+Instruction 365 S:0xC0025E10 0x4639 0 MOV r1,r7 false
+Instruction 366 S:0xC0025E12 0xF7FFF849 1 BL {pc}-0xf6a ; 0xc0024ea8 true
+Instruction 367 S:0xC0024EA8 0xB5F8 9 PUSH {r3-r7,lr} false
+Instruction 368 S:0xC0024EAA 0xB500 5 PUSH {lr} false
+Instruction 369 S:0xC0024EAC 0xF85DEB04 2 POP {lr} false
+Instruction 370 S:0xC0024EB0 0x4604 0 MOV r4,r0 false
+Instruction 371 S:0xC0024EB2 0x6800 1 LDR r0,[r0,#0] false
+Instruction 372 S:0xC0024EB4 0x460E 0 MOV r6,r1 false
+Instruction 373 S:0xC0024EB6 0x4617 1 MOV r7,r2 false
+Instruction 374 S:0xC0024EB8 0xB1B8 1 CBZ r0,{pc}+0x32 ; 0xc0024eea true
+Instruction 375 S:0xC0024EEA 0xBDF8 25 POP {r3-r7,pc} true
+Instruction 376 S:0xC0025E16 0x4B3B 3 LDR r3,[pc,#236] ; [0xC0025F04] = 0xC0635D88 false
+Instruction 377 S:0xC0025E18 0x6D5A 16 LDR r2,[r3,#0x54] false
+Instruction 378 S:0xC0025E1A 0x4680 0 MOV r8,r0 false
+Instruction 379 S:0xC0025E1C 0x2A00 2 CMP r2,#0 false
+Instruction 380 S:0xC0025E1E 0xD15D 0 BNE {pc}+0xbe ; 0xc0025edc true fail
+Instruction 381 S:0xC0025E20 0x4B39 20 LDR r3,[pc,#228] ; [0xC0025F08] = 0xC05FC574 false
+Instruction 382 S:0xC0025E22 0x4669 0 MOV r1,sp false
+Instruction 383 S:0xC0025E24 0xF42152FF 1 BIC r2,r1,#0x1fe0 false
+Instruction 384 S:0xC0025E28 0xF022021F 1 BIC r2,r2,#0x1f false
+Instruction 385 S:0xC0025E2C 0x681B 12 LDR r3,[r3,#0] false
+Instruction 386 S:0xC0025E2E 0x6955 2 LDR r5,[r2,#0x14] false
+Instruction 387 S:0xC0025E30 0x2B00 1 CMP r3,#0 false
+Instruction 388 S:0xC0025E32 0xD142 0 BNE {pc}+0x88 ; 0xc0025eba true
+Instruction 389 S:0xC0025EBA 0x4628 8 MOV r0,r5 false
+Instruction 390 S:0xC0025EBC 0xF017F826 0 BL {pc}+0x17050 ; 0xc003cf0c true
+Instruction 391 S:0xC003CF0C 0xB488 5 PUSH {r3,r7} false
+Instruction 392 S:0xC003CF0E 0xAF00 1 ADD r7,sp,#0 false
+Instruction 393 S:0xC003CF10 0xB500 2 PUSH {lr} false
+Instruction 394 S:0xC003CF12 0xF85DEB04 2 POP {lr} false
+Instruction 395 S:0xC003CF16 0x4A0C 12 LDR r2,[pc,#48] ; [0xC003CF48] = 0xC05FD5C0 false
+Instruction 396 S:0xC003CF18 0x4B0C 2 LDR r3,[pc,#48] ; [0xC003CF4C] = 0xC05F3080 false
+Instruction 397 S:0xC003CF1A 0xF8522020 14 LDR r2,[r2,r0,LSL #2] false
+Instruction 398 S:0xC003CF1E 0x189B 2 ADDS r3,r3,r2 false
+Instruction 399 S:0xC003CF20 0xF8D31460 15 LDR r1,[r3,#0x460] false
+Instruction 400 S:0xC003CF24 0xF8D32464 3 LDR r2,[r3,#0x464] false
+Instruction 401 S:0xC003CF28 0x4291 2 CMP r1,r2 false
+Instruction 402 S:0xC003CF2A 0xD003 0 BEQ {pc}+0xa ; 0xc003cf34 true fail
+Instruction 403 S:0xC003CF2C 0x2000 1 MOVS r0,#0 false
+Instruction 404 S:0xC003CF2E 0x46BD 0 MOV sp,r7 false
+Instruction 405 S:0xC003CF30 0xBC88 3 POP {r3,r7} false
+Instruction 406 S:0xC003CF32 0x4770 1 BX lr true
+Instruction 407 S:0xC0025EC0 0x2800 1 CMP r0,#0 false
+Instruction 408 S:0xC0025EC2 0xD0B7 0 BEQ {pc}-0x8e ; 0xc0025e34 true
+Instruction 409 S:0xC0025E34 0x4A35 3 LDR r2,[pc,#212] ; [0xC0025F0C] = 0xC05FD5C0 false
+Instruction 410 S:0xC0025E36 0x4B36 3 LDR r3,[pc,#216] ; [0xC0025F10] = 0xC05F0638 false
+Instruction 411 S:0xC0025E38 0xF8522025 1 LDR r2,[r2,r5,LSL #2] false
+Instruction 412 S:0xC0025E3C 0x58D5 15 LDR r5,[r2,r3] false
+Instruction 413 S:0xC0025E3E 0x42AF 2 CMP r7,r5 false
+Instruction 414 S:0xC0025E40 0xD017 0 BEQ {pc}+0x32 ; 0xc0025e72 true fail
+Instruction 415 S:0xC0025E42 0x687B 11 LDR r3,[r7,#4] false
+Instruction 416 S:0xC0025E44 0x429C 2 CMP r4,r3 false
+Instruction 417 S:0xC0025E46 0xD057 1 BEQ {pc}+0xb2 ; 0xc0025ef8 true fail
+Instruction 418 S:0xC0025E48 0x68E3 21 LDR r3,[r4,#0xc] false
+Instruction 419 S:0xC0025E4A 0xF0030303 2 AND r3,r3,#3 false
+Instruction 420 S:0xC0025E4E 0x60E3 1 STR r3,[r4,#0xc] false
+Instruction 421 S:0xC0025E50 0xF3BF8F5F 1 DMB false
+Instruction 422 S:0xC0025E54 0x883B 31 LDRH r3,[r7,#0] false
+Instruction 423 S:0xC0025E56 0x3301 2 ADDS r3,#1 false
+Instruction 424 S:0xC0025E58 0x803B 1 STRH r3,[r7,#0] false
+Instruction 425 S:0xC0025E5A 0xF3BF8F4F 31 DSB false
+Instruction 426 S:0xC0025E5E 0xF3AF8004 1 SEV.W false
+Instruction 427 S:0xC0025E62 0x4628 1 MOV r0,r5 false
+Instruction 428 S:0xC0025E64 0xF3BEFBA8 0 BL {pc}+0x3be754 ; 0xc03e45b8 true
+Cycle Count 106 Tracing disabled
+Info Tracing enabled
+Instruction 429 S:0xC0025E68 0x68E3 1 LDR r3,[r4,#0xc] false
+Instruction 430 S:0xC0025E6A 0xF0030303 2 AND r3,r3,#3 false
+Instruction 431 S:0xC0025E6E 0x432B 1 ORRS r3,r3,r5 false
+Instruction 432 S:0xC0025E70 0x60E3 1 STR r3,[r4,#0xc] false
+Instruction 433 S:0xC0025E72 0x4621 0 MOV r1,r4 false
+Instruction 434 S:0xC0025E74 0x4628 1 MOV r0,r5 false
+Instruction 435 S:0xC0025E76 0x60A6 1 STR r6,[r4,#8] false
+Instruction 436 S:0xC0025E78 0xF7FFFDAA 0 BL {pc}-0x4a8 ; 0xc00259d0 true
+Instruction 437 S:0xC00259D0 0xB538 1 PUSH {r3-r5,lr} false
+Instruction 438 S:0xC00259D2 0xB500 4 PUSH {lr} false
+Instruction 439 S:0xC00259D4 0xF85DEB04 2 POP {lr} false
+Instruction 440 S:0xC00259D8 0x460D 0 MOV r5,r1 false
+Instruction 441 S:0xC00259DA 0x4604 1 MOV r4,r0 false
+Instruction 442 S:0xC00259DC 0xF7FFF8F6 1 BL {pc}-0xe10 ; 0xc0024bcc true
+Instruction 443 S:0xC0024BCC 0xB418 6 PUSH {r3,r4} false
+Instruction 444 S:0xC0024BCE 0xB500 1 PUSH {lr} false
+Instruction 445 S:0xC0024BD0 0xF85DEB04 2 POP {lr} false
+Instruction 446 S:0xC0024BD4 0x6884 1 LDR r4,[r0,#8] false
+Instruction 447 S:0xC0024BD6 0x688A 2 LDR r2,[r1,#8] false
+Instruction 448 S:0xC0024BD8 0x1B13 2 SUBS r3,r2,r4 false
+Instruction 449 S:0xC0024BDA 0x2BFF 1 CMP r3,#0xff false
+Instruction 450 S:0xC0024BDC 0xD922 0 BLS {pc}+0x48 ; 0xc0024c24 true
+Instruction 451 S:0xC0024C24 0xB2D2 28 UXTB r2,r2 false
+Instruction 452 S:0xC0024C26 0xEB0000C2 2 ADD r0,r0,r2,LSL #3 false
+Instruction 453 S:0xC0024C2A 0x3014 1 ADDS r0,r0,#0x14 false
+Instruction 454 S:0xC0024C2C 0xE7F3 1 B {pc}-0x16 ; 0xc0024c16 true
+Instruction 455 S:0xC0024C16 0x6843 76 LDR r3,[r0,#4] false
+Instruction 456 S:0xC0024C18 0x6041 3 STR r1,[r0,#4] false
+Instruction 457 S:0xC0024C1A 0xE8810009 1 STM r1,{r0,r3} false
+Instruction 458 S:0xC0024C1E 0x6019 1 STR r1,[r3,#0] false
+Instruction 459 S:0xC0024C20 0xBC18 1 POP {r3,r4} false
+Instruction 460 S:0xC0024C22 0x4770 1 BX lr true
+Instruction 461 S:0xC00259E0 0x68EB 1 LDR r3,[r5,#0xc] false
+Instruction 462 S:0xC00259E2 0x07D8 3 LSLS r0,r3,#31 false
+Instruction 463 S:0xC00259E4 0xD408 0 BMI {pc}+0x14 ; 0xc00259f8 true fail
+Instruction 464 S:0xC00259E6 0x68AB 1 LDR r3,[r5,#8] false
+Instruction 465 S:0xC00259E8 0x68E2 1 LDR r2,[r4,#0xc] false
+Instruction 466 S:0xC00259EA 0x1A9A 2 SUBS r2,r3,r2 false
+Instruction 467 S:0xC00259EC 0x2A00 1 CMP r2,#0 false
+Instruction 468 S:0xC00259EE 0xBFB8 0 IT LT false
+Instruction 469 S:0xC00259F0 0x60E3 1 STR r3,[r4,#0xc] false fail
+Instruction 470 S:0xC00259F2 0x6923 1 LDR r3,[r4,#0x10] false
+Instruction 471 S:0xC00259F4 0x3301 2 ADDS r3,#1 false
+Instruction 472 S:0xC00259F6 0x6123 1 STR r3,[r4,#0x10] false
+Instruction 473 S:0xC00259F8 0xBD38 1 POP {r3-r5,pc} true
+Instruction 474 S:0xC0025E7C 0x4628 3 MOV r0,r5 false
+Instruction 475 S:0xC0025E7E 0x9901 1 LDR r1,[sp,#4] false
+Instruction 476 S:0xC0025E80 0xF3BEFBEA 0 BL {pc}+0x3be7d8 ; 0xc03e4658 true
+Cycle Count 78 Tracing disabled
+Info Tracing enabled
+Instruction 477 S:0xC0025E84 0x4640 1 MOV r0,r8 false
+Instruction 478 S:0xC0025E86 0xB002 0 ADD sp,sp,#8 false
+Instruction 479 S:0xC0025E88 0xE8BD81F0 3 POP {r4-r8,pc} true
+Cycle Count 683 Tracing disabled
+Info Tracing enabled
+Instruction 480 S:0xC00202C8 0xB500 1 PUSH {lr} false
+Instruction 481 S:0xC00202CA 0xF85DEB04 2 POP {lr} false
+Instruction 482 S:0xC00202CE 0x2800 1 CMP r0,#0 false
+Instruction 483 S:0xC00202D0 0xBFA1 0 ITTTT GE false
+Instruction 484 S:0xC00202D2 0xF64C43CD 1 MOV r3,#0xcccd false
+Instruction 485 S:0xC00202D6 0x3009 0 ADDS r0,r0,#9 false
+Instruction 486 S:0xC00202D8 0xF6CC43CC 1 MOVT r3,#0xcccc false
+Instruction 487 S:0xC00202DC 0xFBA32000 2 UMULL r2,r0,r3,r0 false
+Instruction 488 S:0xC00202E0 0xBFAE 12 ITEE GE false
+Instruction 489 S:0xC00202E2 0x08C0 1 LSRS r0,r0,#3 false
+Instruction 490 S:0xC00202E4 0xF64F70FE 0 MOV r0,#0xfffe false fail
+Instruction 491 S:0xC00202E8 0xF6C370FF 1 MOVT r0,#0x3fff false fail
+Instruction 492 S:0xC00202EC 0x4770 1 BX lr true
+Cycle Count 41 Tracing disabled
+Info Tracing enabled
+Instruction 493 S:0xC0025DC4 0xE92D41F0 1 PUSH {r4-r8,lr} false
+Instruction 494 S:0xC0025DC8 0xB082 3 SUB sp,sp,#8 false
+Instruction 495 S:0xC0025DCA 0xB500 3 PUSH {lr} false
+Instruction 496 S:0xC0025DCC 0xF85DEB04 2 POP {lr} false
+Instruction 497 S:0xC0025DD0 0x6983 1 LDR r3,[r0,#0x18] false
+Instruction 498 S:0xC0025DD2 0x4604 0 MOV r4,r0 false
+Instruction 499 S:0xC0025DD4 0x460E 1 MOV r6,r1 false
+Instruction 500 S:0xC0025DD6 0x2B00 1 CMP r3,#0 false
+Instruction 501 S:0xC0025DD8 0x4677 0 MOV r7,lr false
+Instruction 502 S:0xC0025DDA 0xBFA8 1 IT GE false
+Instruction 503 S:0xC0025DDC 0x18CD 1 ADDS r5,r1,r3 false fail
+Instruction 504 S:0xC0025DDE 0xDB55 0 BLT {pc}+0xae ; 0xc0025e8c true
+Instruction 505 S:0xC0025E8C 0x4B21 10 LDR r3,[pc,#132] ; [0xC0025F14] = 0xC05F60C0 false
+Instruction 506 S:0xC0025E8E 0x681D 3 LDR r5,[r3,#0] false
+Instruction 507 S:0xC0025E90 0x1B4D 2 SUBS r5,r1,r5 false
+Instruction 508 S:0xC0025E92 0x2DFF 1 CMP r5,#0xff false
+Instruction 509 S:0xC0025E94 0xDDA9 0 BLE {pc}-0xaa ; 0xc0025dea true
+Instruction 510 S:0xC0025DEA 0x6823 22 LDR r3,[r4,#0] false
+Instruction 511 S:0xC0025DEC 0xB113 2 CBZ r3,{pc}+8 ; 0xc0025df4 true fail
+Instruction 512 S:0xC0025DEE 0x68A3 1 LDR r3,[r4,#8] false
+Instruction 513 S:0xC0025DF0 0x42B3 2 CMP r3,r6 false
+Instruction 514 S:0xC0025DF2 0xD06B 0 BEQ {pc}+0xda ; 0xc0025ecc true fail
+Instruction 515 S:0xC0025DF4 0x4B42 8 LDR r3,[pc,#264] ; [0xC0025F00] false
+Instruction 516 S:0xC0025DF6 0x681B 5 LDR r3,[r3,#0] false
+Instruction 517 S:0xC0025DF8 0x2B00 2 CMP r3,#0 false
+Instruction 518 S:0xC0025DFA 0xD16A 0 BNE {pc}+0xd8 ; 0xc0025ed2 true fail
+Instruction 519 S:0xC0025DFC 0x6923 1 LDR r3,[r4,#0x10] false
+Instruction 520 S:0xC0025DFE 0x2B00 2 CMP r3,#0 false
+Instruction 521 S:0xC0025E00 0xD07C 0 BEQ {pc}+0xfc ; 0xc0025efc true fail
+Instruction 522 S:0xC0025E02 0xA901 1 ADD r1,sp,#4 false
+Instruction 523 S:0xC0025E04 0x4620 0 MOV r0,r4 false
+Instruction 524 S:0xC0025E06 0xF7FFFD61 1 BL {pc}-0x53a ; 0xc00258cc true
+Instruction 525 S:0xC00258CC 0xB5F8 1 PUSH {r3-r7,lr} false
+Instruction 526 S:0xC00258CE 0xB500 5 PUSH {lr} false
+Instruction 527 S:0xC00258D0 0xF85DEB04 2 POP {lr} false
+Instruction 528 S:0xC00258D4 0x4606 0 MOV r6,r0 false
+Instruction 529 S:0xC00258D6 0x460F 1 MOV r7,r1 false
+Instruction 530 S:0xC00258D8 0x68F5 2 LDR r5,[r6,#0xc] false
+Instruction 531 S:0xC00258DA 0xF0350403 2 BICS r4,r5,#3 false
+Instruction 532 S:0xC00258DE 0x4620 1 MOV r0,r4 false
+Instruction 533 S:0xC00258E0 0xD00A 0 BEQ {pc}+0x18 ; 0xc00258f8 true fail
+Instruction 534 S:0xC00258E2 0xF3BEFE81 1 BL {pc}+0x3bed06 ; 0xc03e45e8 true
+Cycle Count 63 Tracing disabled
+Info Tracing enabled
+Instruction 535 S:0xC00258E6 0x6038 1 STR r0,[r7,#0] false
+Instruction 536 S:0xC00258E8 0x4601 1 MOV r1,r0 false
+Instruction 537 S:0xC00258EA 0x68F2 1 LDR r2,[r6,#0xc] false
+Instruction 538 S:0xC00258EC 0x4620 0 MOV r0,r4 false
+Instruction 539 S:0xC00258EE 0x4295 2 CMP r5,r2 false
+Instruction 540 S:0xC00258F0 0xD100 0 BNE {pc}+4 ; 0xc00258f4 true fail
+Instruction 541 S:0xC00258F2 0xBDF8 1 POP {r3-r7,pc} true
+Instruction 542 S:0xC0025E0A 0x2200 3 MOVS r2,#0 false
+Instruction 543 S:0xC0025E0C 0x4607 0 MOV r7,r0 false
+Instruction 544 S:0xC0025E0E 0x4620 1 MOV r0,r4 false
+Instruction 545 S:0xC0025E10 0x4639 0 MOV r1,r7 false
+Instruction 546 S:0xC0025E12 0xF7FFF849 1 BL {pc}-0xf6a ; 0xc0024ea8 true
+Instruction 547 S:0xC0024EA8 0xB5F8 1 PUSH {r3-r7,lr} false
+Instruction 548 S:0xC0024EAA 0xB500 5 PUSH {lr} false
+Instruction 549 S:0xC0024EAC 0xF85DEB04 2 POP {lr} false
+Instruction 550 S:0xC0024EB0 0x4604 0 MOV r4,r0 false
+Instruction 551 S:0xC0024EB2 0x6800 1 LDR r0,[r0,#0] false
+Instruction 552 S:0xC0024EB4 0x460E 0 MOV r6,r1 false
+Instruction 553 S:0xC0024EB6 0x4617 1 MOV r7,r2 false
+Instruction 554 S:0xC0024EB8 0xB1B8 1 CBZ r0,{pc}+0x32 ; 0xc0024eea true fail
+Instruction 555 S:0xC0024EBA 0x4B17 55 LDR r3,[pc,#92] ; [0xC0024F18] = 0xC0635D88 false
+Instruction 556 S:0xC0024EBC 0x685A 15 LDR r2,[r3,#4] false
+Instruction 557 S:0xC0024EBE 0xB9E2 2 CBNZ r2,{pc}+0x3c ; 0xc0024efa true fail
+Instruction 558 S:0xC0024EC0 0x6863 1 LDR r3,[r4,#4] false
+Instruction 559 S:0xC0024EC2 0x6043 3 STR r3,[r0,#4] false
+Instruction 560 S:0xC0024EC4 0x6018 3 STR r0,[r3,#0] false
+Instruction 561 S:0xC0024EC6 0xB98F 1 CBNZ r7,{pc}+0x26 ; 0xc0024eec true fail
+Instruction 562 S:0xC0024EC8 0x68E2 1 LDR r2,[r4,#0xc] false
+Instruction 563 S:0xC0024ECA 0xF44F7300 0 MOV r3,#0x200 false
+Instruction 564 S:0xC0024ECE 0xF2C00320 1 MOVT r3,#0x20 false
+Instruction 565 S:0xC0024ED2 0x6063 1 STR r3,[r4,#4] false
+Instruction 566 S:0xC0024ED4 0x07D3 1 LSLS r3,r2,#31 false
+Instruction 567 S:0xC0024ED6 0xD406 0 BMI {pc}+0x10 ; 0xc0024ee6 true fail
+Instruction 568 S:0xC0024ED8 0x6932 1 LDR r2,[r6,#0x10] false
+Instruction 569 S:0xC0024EDA 0x68F3 1 LDR r3,[r6,#0xc] false
+Instruction 570 S:0xC0024EDC 0x3A01 1 SUBS r2,#1 false
+Instruction 571 S:0xC0024EDE 0x6132 1 STR r2,[r6,#0x10] false
+Instruction 572 S:0xC0024EE0 0x68A2 1 LDR r2,[r4,#8] false
+Instruction 573 S:0xC0024EE2 0x429A 2 CMP r2,r3 false
+Instruction 574 S:0xC0024EE4 0xD005 0 BEQ {pc}+0xe ; 0xc0024ef2 true fail
+Instruction 575 S:0xC0024EE6 0x2001 1 MOVS r0,#1 false
+Instruction 576 S:0xC0024EE8 0xBDF8 3 POP {r3-r7,pc} true
+Instruction 577 S:0xC0025E16 0x4B3B 5 LDR r3,[pc,#236] ; [0xC0025F04] = 0xC0635D88 false
+Instruction 578 S:0xC0025E18 0x6D5A 3 LDR r2,[r3,#0x54] false
+Instruction 579 S:0xC0025E1A 0x4680 0 MOV r8,r0 false
+Instruction 580 S:0xC0025E1C 0x2A00 2 CMP r2,#0 false
+Instruction 581 S:0xC0025E1E 0xD15D 0 BNE {pc}+0xbe ; 0xc0025edc true fail
+Instruction 582 S:0xC0025E20 0x4B39 1 LDR r3,[pc,#228] ; [0xC0025F08] = 0xC05FC574 false
+Instruction 583 S:0xC0025E22 0x4669 0 MOV r1,sp false
+Instruction 584 S:0xC0025E24 0xF42152FF 1 BIC r2,r1,#0x1fe0 false
+Instruction 585 S:0xC0025E28 0xF022021F 1 BIC r2,r2,#0x1f false
+Instruction 586 S:0xC0025E2C 0x681B 1 LDR r3,[r3,#0] false
+Instruction 587 S:0xC0025E2E 0x6955 4 LDR r5,[r2,#0x14] false
+Instruction 588 S:0xC0025E30 0x2B00 1 CMP r3,#0 false
+Instruction 589 S:0xC0025E32 0xD142 0 BNE {pc}+0x88 ; 0xc0025eba true
+Instruction 590 S:0xC0025EBA 0x4628 8 MOV r0,r5 false
+Instruction 591 S:0xC0025EBC 0xF017F826 0 BL {pc}+0x17050 ; 0xc003cf0c true
+Instruction 592 S:0xC003CF0C 0xB488 3 PUSH {r3,r7} false
+Instruction 593 S:0xC003CF0E 0xAF00 1 ADD r7,sp,#0 false
+Instruction 594 S:0xC003CF10 0xB500 2 PUSH {lr} false
+Instruction 595 S:0xC003CF12 0xF85DEB04 2 POP {lr} false
+Instruction 596 S:0xC003CF16 0x4A0C 2 LDR r2,[pc,#48] ; [0xC003CF48] = 0xC05FD5C0 false
+Instruction 597 S:0xC003CF18 0x4B0C 2 LDR r3,[pc,#48] ; [0xC003CF4C] = 0xC05F3080 false
+Instruction 598 S:0xC003CF1A 0xF8522020 3 LDR r2,[r2,r0,LSL #2] false
+Instruction 599 S:0xC003CF1E 0x189B 2 ADDS r3,r3,r2 false
+Instruction 600 S:0xC003CF20 0xF8D31460 5 LDR r1,[r3,#0x460] false
+Instruction 601 S:0xC003CF24 0xF8D32464 3 LDR r2,[r3,#0x464] false
+Instruction 602 S:0xC003CF28 0x4291 2 CMP r1,r2 false
+Instruction 603 S:0xC003CF2A 0xD003 0 BEQ {pc}+0xa ; 0xc003cf34 true fail
+Instruction 604 S:0xC003CF2C 0x2000 8 MOVS r0,#0 false
+Instruction 605 S:0xC003CF2E 0x46BD 0 MOV sp,r7 false
+Instruction 606 S:0xC003CF30 0xBC88 3 POP {r3,r7} false
+Instruction 607 S:0xC003CF32 0x4770 1 BX lr true
+Instruction 608 S:0xC0025EC0 0x2800 1 CMP r0,#0 false
+Instruction 609 S:0xC0025EC2 0xD0B7 0 BEQ {pc}-0x8e ; 0xc0025e34 true
+Instruction 610 S:0xC0025E34 0x4A35 66 LDR r2,[pc,#212] ; [0xC0025F0C] = 0xC05FD5C0 false
+Instruction 611 S:0xC0025E36 0x4B36 3 LDR r3,[pc,#216] ; [0xC0025F10] = 0xC05F0638 false
+Instruction 612 S:0xC0025E38 0xF8522025 1 LDR r2,[r2,r5,LSL #2] false
+Instruction 613 S:0xC0025E3C 0x58D5 5 LDR r5,[r2,r3] false
+Instruction 614 S:0xC0025E3E 0x42AF 2 CMP r7,r5 false
+Instruction 615 S:0xC0025E40 0xD017 0 BEQ {pc}+0x32 ; 0xc0025e72 true
+Instruction 616 S:0xC0025E72 0x4621 8 MOV r1,r4 false
+Instruction 617 S:0xC0025E74 0x4628 0 MOV r0,r5 false
+Instruction 618 S:0xC0025E76 0x60A6 3 STR r6,[r4,#8] false
+Instruction 619 S:0xC0025E78 0xF7FFFDAA 0 BL {pc}-0x4a8 ; 0xc00259d0 true
+Instruction 620 S:0xC00259D0 0xB538 3 PUSH {r3-r5,lr} false
+Instruction 621 S:0xC00259D2 0xB500 4 PUSH {lr} false
+Instruction 622 S:0xC00259D4 0xF85DEB04 2 POP {lr} false
+Instruction 623 S:0xC00259D8 0x460D 0 MOV r5,r1 false
+Instruction 624 S:0xC00259DA 0x4604 1 MOV r4,r0 false
+Instruction 625 S:0xC00259DC 0xF7FFF8F6 1 BL {pc}-0xe10 ; 0xc0024bcc true
+Instruction 626 S:0xC0024BCC 0xB418 1 PUSH {r3,r4} false
+Instruction 627 S:0xC0024BCE 0xB500 1 PUSH {lr} false
+Instruction 628 S:0xC0024BD0 0xF85DEB04 2 POP {lr} false
+Instruction 629 S:0xC0024BD4 0x6884 1 LDR r4,[r0,#8] false
+Instruction 630 S:0xC0024BD6 0x688A 2 LDR r2,[r1,#8] false
+Instruction 631 S:0xC0024BD8 0x1B13 2 SUBS r3,r2,r4 false
+Instruction 632 S:0xC0024BDA 0x2BFF 1 CMP r3,#0xff false
+Instruction 633 S:0xC0024BDC 0xD922 0 BLS {pc}+0x48 ; 0xc0024c24 true
+Instruction 634 S:0xC0024C24 0xB2D2 8 UXTB r2,r2 false
+Instruction 635 S:0xC0024C26 0xEB0000C2 2 ADD r0,r0,r2,LSL #3 false
+Instruction 636 S:0xC0024C2A 0x3014 1 ADDS r0,r0,#0x14 false
+Instruction 637 S:0xC0024C2C 0xE7F3 1 B {pc}-0x16 ; 0xc0024c16 true
+Instruction 638 S:0xC0024C16 0x6843 2 LDR r3,[r0,#4] false
+Instruction 639 S:0xC0024C18 0x6041 1 STR r1,[r0,#4] false
+Instruction 640 S:0xC0024C1A 0xE8810009 1 STM r1,{r0,r3} false
+Instruction 641 S:0xC0024C1E 0x6019 1 STR r1,[r3,#0] false
+Instruction 642 S:0xC0024C20 0xBC18 1 POP {r3,r4} false
+Instruction 643 S:0xC0024C22 0x4770 1 BX lr true
+Instruction 644 S:0xC00259E0 0x68EB 1 LDR r3,[r5,#0xc] false
+Instruction 645 S:0xC00259E2 0x07D8 3 LSLS r0,r3,#31 false
+Instruction 646 S:0xC00259E4 0xD408 0 BMI {pc}+0x14 ; 0xc00259f8 true fail
+Instruction 647 S:0xC00259E6 0x68AB 1 LDR r3,[r5,#8] false
+Instruction 648 S:0xC00259E8 0x68E2 1 LDR r2,[r4,#0xc] false
+Instruction 649 S:0xC00259EA 0x1A9A 2 SUBS r2,r3,r2 false
+Instruction 650 S:0xC00259EC 0x2A00 1 CMP r2,#0 false
+Instruction 651 S:0xC00259EE 0xBFB8 0 IT LT false
+Instruction 652 S:0xC00259F0 0x60E3 1 STR r3,[r4,#0xc] false fail
+Instruction 653 S:0xC00259F2 0x6923 1 LDR r3,[r4,#0x10] false
+Instruction 654 S:0xC00259F4 0x3301 2 ADDS r3,#1 false
+Instruction 655 S:0xC00259F6 0x6123 1 STR r3,[r4,#0x10] false
+Instruction 656 S:0xC00259F8 0xBD38 1 POP {r3-r5,pc} true
+Instruction 657 S:0xC0025E7C 0x4628 3 MOV r0,r5 false
+Instruction 658 S:0xC0025E7E 0x9901 1 LDR r1,[sp,#4] false
+Instruction 659 S:0xC0025E80 0xF3BEFBEA 0 BL {pc}+0x3be7d8 ; 0xc03e4658 true
+Cycle Count 74 Tracing disabled
+Info Tracing enabled
+Instruction 660 S:0xC0025E84 0x4640 1 MOV r0,r8 false
+Instruction 661 S:0xC0025E86 0xB002 0 ADD sp,sp,#8 false
+Instruction 662 S:0xC0025E88 0xE8BD81F0 3 POP {r4-r8,pc} true
+Cycle Count 291 Tracing disabled
+Info Tracing enabled
+Instruction 663 S:0xC0020A14 0xB500 1 PUSH {lr} false
+Instruction 664 S:0xC0020A16 0xF85DEB04 2 POP {lr} false
+Instruction 665 S:0xC0020A1A 0x466A 1 MOV r2,sp false
+Instruction 666 S:0xC0020A1C 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 667 S:0xC0020A20 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 668 S:0xC0020A24 0x685A 5 LDR r2,[r3,#4] false
+Instruction 669 S:0xC0020A26 0xF5027200 2 ADD r2,r2,#0x200 false
+Instruction 670 S:0xC0020A2A 0x605A 1 STR r2,[r3,#4] false
+Instruction 671 S:0xC0020A2C 0x4770 1 BX lr true
+Cycle Count 331 Tracing disabled
+Info Tracing enabled
+Instruction 672 S:0xC002108C 0xB538 1 PUSH {r3-r5,lr} false
+Timestamp Timestamp: 562536961348
+Instruction 673 S:0xC002108E 0xB500 4 PUSH {lr} false
+Instruction 674 S:0xC0021090 0xF85DEB04 2 POP {lr} false
+Instruction 675 S:0xC0021094 0x466B 1 MOV r3,sp false
+Instruction 676 S:0xC0021096 0xF42354FF 1 BIC r4,r3,#0x1fe0 false
+Instruction 677 S:0xC002109A 0x2300 0 MOVS r3,#0 false
+Instruction 678 S:0xC002109C 0xF024041F 1 BIC r4,r4,#0x1f false
+Instruction 679 S:0xC00210A0 0xF2C033FF 0 MOVT r3,#0x3ff false
+Instruction 680 S:0xC00210A4 0x6862 3 LDR r2,[r4,#4] false
+Instruction 681 S:0xC00210A6 0x4013 2 ANDS r3,r3,r2 false
+Instruction 682 S:0xC00210A8 0xB98B 1 CBNZ r3,{pc}+0x26 ; 0xc00210ce true fail
+Instruction 683 S:0xC00210AA 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 684 S:0xC00210AE 0x0619 3 LSLS r1,r3,#24 false
+Instruction 685 S:0xC00210B0 0xD40D 0 BMI {pc}+0x1e ; 0xc00210ce true fail
+Instruction 686 S:0xC00210B2 0x6863 1 LDR r3,[r4,#4] false
+Instruction 687 S:0xC00210B4 0xF46F72FF 0 MVN r2,#0x1fe false
+Instruction 688 S:0xC00210B8 0x189B 2 ADDS r3,r3,r2 false
+Instruction 689 S:0xC00210BA 0x6063 1 STR r3,[r4,#4] false
+Instruction 690 S:0xC00210BC 0xF0234378 0 BIC r3,r3,#0xf8000000 false
+Instruction 691 S:0xC00210C0 0xF02303FF 1 BIC r3,r3,#0xff false
+Instruction 692 S:0xC00210C4 0xB173 1 CBZ r3,{pc}+0x20 ; 0xc00210e4 true
+Instruction 693 S:0xC00210E4 0x6963 15 LDR r3,[r4,#0x14] false
+Instruction 694 S:0xC00210E6 0x4A06 13 LDR r2,[pc,#24] ; [0xC0021100] = 0xC06498C0 false
+Instruction 695 S:0xC00210E8 0x019B 2 LSLS r3,r3,#6 false
+Instruction 696 S:0xC00210EA 0x58D3 3 LDR r3,[r2,r3] false
+Instruction 697 S:0xC00210EC 0x2B00 2 CMP r3,#0 false
+Instruction 698 S:0xC00210EE 0xD0EA 0 BEQ {pc}-0x28 ; 0xc00210c6 true
+Instruction 699 S:0xC00210C6 0x6863 8 LDR r3,[r4,#4] false
+Instruction 700 S:0xC00210C8 0x3B01 2 SUBS r3,#1 false
+Instruction 701 S:0xC00210CA 0x6063 1 STR r3,[r4,#4] false
+Instruction 702 S:0xC00210CC 0xBD38 1 POP {r3-r5,pc} true
+Cycle Count 395 Tracing disabled
+Info Tracing enabled
+Instruction 703 S:0xC00361D8 0xB500 1 PUSH {lr} false
+Instruction 704 S:0xC00361DA 0xF85DEB04 2 POP {lr} false
+Instruction 705 S:0xC00361DE 0x4603 1 MOV r3,r0 false
+Instruction 706 S:0xC00361E0 0x6800 70 LDR r0,[r0,#0] false
+Instruction 707 S:0xC00361E2 0xF0000001 2 AND r0,r0,#1 false
+Instruction 708 S:0xC00361E6 0xEE1D1F90 1 MRC p15,#0x0,r1,c13,c0,#4 false
+Instruction 709 S:0xC00361EA 0x685A 1 LDR r2,[r3,#4] false
+Instruction 710 S:0xC00361EC 0x188A 3 ADDS r2,r1,r2 false
+Instruction 711 S:0xC00361EE 0xF8521020 15 LDR r1,[r2,r0,LSL #2] false
+Instruction 712 S:0xC00361F2 0x3101 2 ADDS r1,#1 false
+Instruction 713 S:0xC00361F4 0xF8421020 1 STR r1,[r2,r0,LSL #2] false
+Instruction 714 S:0xC00361F8 0xF3BF8F5F 1 DMB false
+Instruction 715 S:0xC00361FC 0xEE1D1F90 1 MRC p15,#0x0,r1,c13,c0,#4 false
+Instruction 716 S:0xC0036200 0x685B 48 LDR r3,[r3,#4] false
+Instruction 717 S:0xC0036202 0x1C82 0 ADDS r2,r0,#2 false
+Instruction 718 S:0xC0036204 0x18CB 3 ADDS r3,r1,r3 false
+Instruction 719 S:0xC0036206 0xF8531022 3 LDR r1,[r3,r2,LSL #2] false
+Instruction 720 S:0xC003620A 0x3101 2 ADDS r1,#1 false
+Instruction 721 S:0xC003620C 0xF8431022 1 STR r1,[r3,r2,LSL #2] false
+Instruction 722 S:0xC0036210 0x4770 1 BX lr true
+Cycle Count 115 Tracing disabled
+Info Tracing enabled
+Instruction 723 S:0xC0036214 0xB418 1 PUSH {r3,r4} false
+Instruction 724 S:0xC0036216 0xB500 1 PUSH {lr} false
+Instruction 725 S:0xC0036218 0xF85DEB04 2 POP {lr} false
+Instruction 726 S:0xC003621C 0xF3BF8F5F 1 DMB false
+Instruction 727 S:0xC0036220 0xF3EF8400 1 MRS r4,APSR ; formerly CPSR false
+Instruction 728 S:0xC0036224 0xB672 1 CPSID i false
+Instruction 729 S:0xC0036226 0x6842 30 LDR r2,[r0,#4] false
+Instruction 730 S:0xC0036228 0xEE1D3F90 1 MRC p15,#0x0,r3,c13,c0,#4 false
+Instruction 731 S:0xC003622C 0xEB020181 1 ADD r1,r2,r1,LSL #2 false
+Instruction 732 S:0xC0036230 0x585A 3 LDR r2,[r3,r1] false
+Instruction 733 S:0xC0036232 0x3A01 2 SUBS r2,#1 false
+Instruction 734 S:0xC0036234 0x505A 1 STR r2,[r3,r1] false
+Instruction 735 S:0xC0036236 0xF3848100 1 MSR CPSR_c,r4 false
+Instruction 736 S:0xC003623A 0xBC18 5 POP {r3,r4} false
+Instruction 737 S:0xC003623C 0x4770 1 BX lr true
+Cycle Count 120 Tracing disabled
+Info Tracing enabled
+Instruction 738 S:0xC000CD40 0xB672 1 CPSID i false
+Instruction 739 S:0xC000CD42 0xF8D91000 4 LDR r1,[r9,#0] false
+Instruction 740 S:0xC000CD46 0xF0110F07 2 TST r1,#7 false
+Instruction 741 S:0xC000CD4A 0xF040801C 0 BNE.W {pc}+0x3c ; 0xc000cd86 true fail
+Instruction 742 S:0xC000CD4E 0xF3BF8F2F 1 CLREX false
+Instruction 743 S:0xC000CD52 0x466A 1 MOV r2,sp false
+Instruction 744 S:0xC000CD54 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 745 S:0xC000CD58 0xF083030C 2 EOR r3,r3,#0xc false
+Instruction 746 S:0xC000CD5C 0xF3838100 3 MSR CPSR_c,r3 false
+Instruction 747 S:0xC000CD60 0xF8D2D03C 5 LDR sp,[r2,#0x3c] false
+Instruction 748 S:0xC000CD64 0xF8D2E040 1 LDR lr,[r2,#0x40] false
+Instruction 749 S:0xC000CD68 0xF083030C 0 EOR r3,r3,#0xc false
+Instruction 750 S:0xC000CD6C 0xF3838100 3 MSR CPSR_c,r3 false
+Instruction 751 S:0xC000CD70 0x9912 5 LDR r1,[sp,#0x48] false
+Instruction 752 S:0xC000CD72 0xF8DDE044 1 LDR lr,[sp,#0x44] false
+Instruction 753 S:0xC000CD76 0xB00F 0 ADD sp,sp,#0x3c false
+Instruction 754 S:0xC000CD78 0xF3918F00 2 MSR SPSR_cxsf,r1 false
+Instruction 755 S:0xC000CD7C 0xE91D1FFE 5 LDMDB sp,{r1-r12} false
+Instruction 756 S:0xC000CD80 0xB005 7 ADD sp,sp,#0x14 false
+Instruction 757 S:0xC000CD82 0xF3DE8F00 1 SUBS pc,lr,#0 true
+Info Return from exception
+Timestamp Timestamp: 562536961413
+Cycle Count 2136 Tracing disabled
+Info Tracing enabled
+Instruction 758 S:0xC000CE40 0xB092 1 SUB sp,sp,#0x48 false
+Timestamp Timestamp: 562536961560
+Instruction 759 S:0xC000CE42 0xE88D1FFF 6 STM sp,{r0-r12} false
+Instruction 760 S:0xC000CE46 0x46E8 11 MOV r8,sp false
+Instruction 761 S:0xC000CE48 0xF3EF8A00 1 MRS r10,APSR ; formerly CPSR false
+Instruction 762 S:0xC000CE4C 0xF08A0A0C 2 EOR r10,r10,#0xc false
+Instruction 763 S:0xC000CE50 0xF38A8100 3 MSR CPSR_c,r10 false
+Instruction 764 S:0xC000CE54 0xF8C8D034 5 STR sp,[r8,#0x34] false
+Instruction 765 S:0xC000CE58 0xF8C8E038 1 STR lr,[r8,#0x38] false
+Instruction 766 S:0xC000CE5C 0xF08A0A0C 0 EOR r10,r10,#0xc false
+Instruction 767 S:0xC000CE60 0xF38A8100 3 MSR CPSR_c,r10 false
+Instruction 768 S:0xC000CE64 0xF3FF8800 5 MRS r8,SPSR false
+Instruction 769 S:0xC000CE68 0xF8CDE03C 1 STR lr,[sp,#0x3c] false
+Instruction 770 S:0xC000CE6C 0xF8CD8040 1 STR r8,[sp,#0x40] false
+Instruction 771 S:0xC000CE70 0x9011 1 STR r0,[sp,#0x44] false
+Instruction 772 S:0xC000CE72 0xF8DFC08C 14 LDR r12,[pc,#140] ; [0xC000CF00] = 0xC06013D4 false
+Instruction 773 S:0xC000CE76 0xF8DCC000 5 LDR r12,[r12,#0] false
+Instruction 774 S:0xC000CE7A 0xEE01CF10 1 MCR p15,#0x0,r12,c1,c0,#0 false
+Instruction 775 S:0xC000CE7E 0xB662 6 CPSIE i false
+Instruction 776 S:0xC000CE80 0x46E9 1 MOV r9,sp false
+Instruction 777 S:0xC000CE82 0xEA4F3959 2 LSR r9,r9,#13 false
+Instruction 778 S:0xC000CE86 0xEA4F3949 2 LSL r9,r9,#13 false
+Instruction 779 S:0xC000CE8A 0xF20F0878 0 ADR.W r8,{pc}+0x7a ; 0xc000cf04 false
+Instruction 780 S:0xC000CE8E 0xF8D9A000 5 LDR r10,[r9,#0] false
+Instruction 781 S:0xC000CE92 0xE92D0030 3 PUSH.W {r4,r5} false
+Instruction 782 S:0xC000CE96 0xF41A6F70 1 TST r10,#0xf00 false
+Instruction 783 S:0xC000CE9A 0xF0408012 0 BNE.W {pc}+0x28 ; 0xc000cec2 true fail
+Instruction 784 S:0xC000CE9E 0xF5B77FC0 1 CMP r7,#0x180 false
+Instruction 785 S:0xC000CEA2 0xF2AF1E63 1 ADR lr,{pc}-0x161 ; 0xc000cd41 false
+Instruction 786 S:0xC000CEA6 0xBF38 0 IT CC false
+Instruction 787 S:0xC000CEA8 0xF858F027 3 LDR pc,[r8,r7,LSL #2] true
+Instruction 788 S:0xC0020598 0xB530 9 PUSH {r4,r5,lr} false
+Instruction 789 S:0xC002059A 0xB083 2 SUB sp,sp,#0xc false
+Instruction 790 S:0xC002059C 0xB500 3 PUSH {lr} false
+Instruction 791 S:0xC002059E 0xF85DEB04 2 POP {lr} false
+Instruction 792 S:0xC00205A2 0x4604 0 MOV r4,r0 false
+Instruction 793 S:0xC00205A4 0x460D 1 MOV r5,r1 false
+Instruction 794 S:0xC00205A6 0xB1D0 1 CBZ r0,{pc}+0x38 ; 0xc00205de true fail
+Instruction 795 S:0xC00205A8 0x4668 1 MOV r0,sp false
+Instruction 796 S:0xC00205AA 0xF02FF88D 0 BL {pc}+0x2f11e ; 0xc004f6c8 true
+Instruction 797 S:0xC004F6C8 0xB510 12 PUSH {r4,lr} false
+Instruction 798 S:0xC004F6CA 0xB082 1 SUB sp,sp,#8 false
+Instruction 799 S:0xC004F6CC 0xB500 3 PUSH {lr} false
+Instruction 800 S:0xC004F6CE 0xF85DEB04 2 POP {lr} false
+Instruction 801 S:0xC004F6D2 0x4604 0 MOV r4,r0 false
+Instruction 802 S:0xC004F6D4 0x4668 1 MOV r0,sp false
+Instruction 803 S:0xC004F6D6 0xF7FFFFCD 1 BL {pc}-0x62 ; 0xc004f674 true
+Instruction 804 S:0xC004F674 0xB508 1 PUSH {r3,lr} false
+Instruction 805 S:0xC004F676 0xB500 1 PUSH {lr} false
+Instruction 806 S:0xC004F678 0xF85DEB04 2 POP {lr} false
+Instruction 807 S:0xC004F67C 0xF7FFFC84 1 BL {pc}-0x6f4 ; 0xc004ef88 true
+Instruction 808 S:0xC004EF88 0xE92D47F0 2 PUSH {r4-r10,lr} false
+Instruction 809 S:0xC004EF8C 0xB084 4 SUB sp,sp,#0x10 false
+Instruction 810 S:0xC004EF8E 0xB500 3 PUSH {lr} false
+Instruction 811 S:0xC004EF90 0xF85DEB04 2 POP {lr} false
+Instruction 812 S:0xC004EF94 0x4D3E 2 LDR r5,[pc,#248] ; [0xC004F090] = 0xC064D1C0 false
+Instruction 813 S:0xC004EF96 0x4682 0 MOV r10,r0 false
+Instruction 814 S:0xC004EF98 0x462C 2 MOV r4,r5 false
+Instruction 815 S:0xC004EF9A 0xF8D57090 3 LDR r7,[r5,#0x90] false
+Instruction 816 S:0xC004EF9E 0x07FE 3 LSLS r6,r7,#31 false
+Instruction 817 S:0xC004EFA0 0xD46A 0 BMI {pc}+0xd8 ; 0xc004f078 true fail
+Instruction 818 S:0xC004EFA2 0xF3BF8F5F 1 DMB false
+Instruction 819 S:0xC004EFA6 0x6BA3 27 LDR r3,[r4,#0x38] false
+Instruction 820 S:0xC004EFA8 0xF8CA3000 3 STR r3,[r10,#0] false
+Instruction 821 S:0xC004EFAC 0x6826 1 LDR r6,[r4,#0] false
+Instruction 822 S:0xC004EFAE 0x4630 2 MOV r0,r6 false
+Instruction 823 S:0xC004EFB0 0x6833 3 LDR r3,[r6,#0] false
+Instruction 824 S:0xC004EFB2 0x4798 1 BLX r3 true
+Timestamp Timestamp: 562536961573
+Cycle Count 62 Tracing disabled
+Info Tracing enabled
+Instruction 825 S:0xC004EFB4 0xE9D62302 1 LDRD r2,r3,[r6,#8] false
+Instruction 826 S:0xC004EFB8 0xE9CD2300 2 STRD r2,r3,[sp,#0] false
+Instruction 827 S:0xC004EFBC 0xE9D62304 1 LDRD r2,r3,[r6,#0x10] false
+Instruction 828 S:0xC004EFC0 0xE9CD2302 1 STRD r2,r3,[sp,#8] false
+Instruction 829 S:0xC004EFC4 0x6862 1 LDR r2,[r4,#4] false
+Instruction 830 S:0xC004EFC6 0x6C63 1 LDR r3,[r4,#0x44] false
+Instruction 831 S:0xC004EFC8 0x4680 0 MOV r8,r0 false
+Instruction 832 S:0xC004EFCA 0x4689 1 MOV r9,r1 false
+Instruction 833 S:0xC004EFCC 0x6C20 1 LDR r0,[r4,#0x40] false
+Instruction 834 S:0xC004EFCE 0x68A1 1 LDR r1,[r4,#8] false
+Instruction 835 S:0xC004EFD0 0xF3BF8F5F 1 DMB false
+Instruction 836 S:0xC004EFD4 0xF8D46090 28 LDR r6,[r4,#0x90] false
+Instruction 837 S:0xC004EFD8 0x42B7 2 CMP r7,r6 false
+Instruction 838 S:0xC004EFDA 0xD1DE 0 BNE {pc}-0x40 ; 0xc004ef9a true fail
+Instruction 839 S:0xC004EFDC 0xE9DD4500 1 LDRD r4,r5,[sp,#0] false
+Instruction 840 S:0xC004EFE0 0xE9DD6702 1 LDRD r6,r7,[sp,#8] false
+Instruction 841 S:0xC004EFE4 0xEBB80804 1 SUBS r8,r8,r4 false
+Instruction 842 S:0xC004EFE8 0xEB690905 1 SBC r9,r9,r5 false
+Instruction 843 S:0xC004EFEC 0x4604 0 MOV r4,r0 false
+Instruction 844 S:0xC004EFEE 0xEA080806 1 AND r8,r8,r6 false
+Instruction 845 S:0xC004EFF2 0xEA090907 1 AND r9,r9,r7 false
+Instruction 846 S:0xC004EFF6 0xF1C10020 1 RSB r0,r1,#0x20 false
+Instruction 847 S:0xC004EFFA 0xF8DAC000 1 LDR r12,[r10,#0] false
+Instruction 848 S:0xC004EFFE 0xFBA86702 1 UMULL r6,r7,r8,r2 false
+Instruction 849 S:0xC004F002 0x19A4 2 ADDS r4,r4,r6 false
+Instruction 850 S:0xC004F004 0xFB027709 1 MLA r7,r2,r9,r7 false
+Instruction 851 S:0xC004F008 0xFA24F201 1 LSR r2,r4,r1 false
+Instruction 852 S:0xC004F00C 0xEB430507 1 ADC r5,r3,r7 false
+Instruction 853 S:0xC004F010 0xF1B10620 0 SUBS r6,r1,#0x20 false
+Instruction 854 S:0xC004F014 0xFA05F000 2 LSL r0,r5,r0 false
+Instruction 855 S:0xC004F018 0xBF58 0 IT PL false
+Instruction 856 S:0xC004F01A 0xFA45F606 1 ASR r6,r5,r6 false fail
+Instruction 857 S:0xC004F01E 0xEA420200 1 ORR r2,r2,r0 false
+Instruction 858 S:0xC004F022 0xFA45F301 1 ASR r3,r5,r1 false
+Instruction 859 S:0xC004F026 0xBF58 0 IT PL false
+Instruction 860 S:0xC004F028 0x4332 1 ORRS r2,r2,r6 false fail
+Instruction 861 S:0xC004F02A 0xA715 0 ADR r7,{pc}+0x56 ; 0xc004f080 false
+Instruction 862 S:0xC004F02C 0xE9D76700 3 LDRD r6,r7,[r7,#0] false
+Instruction 863 S:0xC004F030 0x429F 2 CMP r7,r3 false
+Instruction 864 S:0xC004F032 0xBF08 0 IT EQ false
+Instruction 865 S:0xC004F034 0x4296 1 CMP r6,r2 false
+Instruction 866 S:0xC004F036 0xD21D 0 BCS {pc}+0x3e ; 0xc004f074 true
+Instruction 867 S:0xC004F074 0x2600 8 MOVS r6,#0 false
+Instruction 868 S:0xC004F076 0xE7EE 0 B {pc}-0x20 ; 0xc004f056 true
+Instruction 869 S:0xC004F056 0x4B0F 3 LDR r3,[pc,#60] ; [0xC004F094] = 0xC05FC59C false
+Instruction 870 S:0xC004F058 0x4466 1 ADD r6,r6,r12 false
+Instruction 871 S:0xC004F05A 0xF8CA6000 1 STR r6,[r10,#0] false
+Instruction 872 S:0xC004F05E 0xF8CA2004 1 STR r2,[r10,#4] false
+Instruction 873 S:0xC004F062 0x681B 3 LDR r3,[r3,#0] false
+Instruction 874 S:0xC004F064 0x2B00 2 CMP r3,#0 false
+Instruction 875 S:0xC004F066 0xBF14 0 ITE NE false
+Instruction 876 S:0xC004F068 0xF06F000A 1 MVN r0,#0xa false fail
+Instruction 877 S:0xC004F06C 0x2000 0 MOVS r0,#0 false
+Instruction 878 S:0xC004F06E 0xB004 1 ADD sp,sp,#0x10 false
+Instruction 879 S:0xC004F070 0xE8BD87F0 3 POP {r4-r10,pc} true
+Instruction 880 S:0xC004F680 0xB900 4 CBNZ r0,{pc}+4 ; 0xc004f684 true fail
+Instruction 881 S:0xC004F682 0xBD08 2 POP {r3,pc} true
+Instruction 882 S:0xC004F6DA 0x9B01 3 LDR r3,[sp,#4] false
+Instruction 883 S:0xC004F6DC 0xF64452D3 0 MOV r2,#0x4dd3 false
+Instruction 884 S:0xC004F6E0 0x9900 1 LDR r1,[sp,#0] false
+Instruction 885 S:0xC004F6E2 0xF2C10262 0 MOVT r2,#0x1062 false
+Instruction 886 S:0xC004F6E6 0xFB820203 2 SMULL r0,r2,r2,r3 false
+Instruction 887 S:0xC004F6EA 0x17DB 1 ASRS r3,r3,#31 false
+Instruction 888 S:0xC004F6EC 0x6021 1 STR r1,[r4,#0] false
+Instruction 889 S:0xC004F6EE 0xEBC313A2 1 RSB r3,r3,r2,ASR #6 false
+Instruction 890 S:0xC004F6F2 0x6063 1 STR r3,[r4,#4] false
+Instruction 891 S:0xC004F6F4 0xB002 0 ADD sp,sp,#8 false
+Instruction 892 S:0xC004F6F6 0xBD10 3 POP {r4,pc} true
+Instruction 893 S:0xC00205AE 0x466A 1 MOV r2,sp false
+Instruction 894 S:0xC00205B0 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 895 S:0xC00205B4 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 896 S:0xC00205B8 0x689B 3 LDR r3,[r3,#8] false
+Instruction 897 S:0xC00205BA 0xF1140208 0 ADDS r2,r4,#8 false
+Instruction 898 S:0xC00205BE 0xBF3C 1 ITT CC false
+Instruction 899 S:0xC00205C0 0xEB720203 1 SBCS.W r2,r2,r3 false
+Instruction 900 S:0xC00205C4 0x2300 0 MOVS r3,#0 false
+Instruction 901 S:0xC00205C6 0xB11B 2 CBZ r3,{pc}+0xa ; 0xc00205d0 true
+Instruction 902 S:0xC00205D0 0x4620 1 MOV r0,r4 false
+Instruction 903 S:0xC00205D2 0x4669 0 MOV r1,sp false
+Instruction 904 S:0xC00205D4 0x2208 1 MOVS r2,#8 false
+Instruction 905 S:0xC00205D6 0xF22FFD13 0 BL {pc}+0x22fa2a ; 0xc0250000 true
+Cycle Count 152 Tracing disabled
+Info Tracing enabled
+Instruction 906 S:0xC00205DA 0x2800 1 CMP r0,#0 false
+Instruction 907 S:0xC00205DC 0xD1F4 0 BNE {pc}-0x14 ; 0xc00205c8 true fail
+Instruction 908 S:0xC00205DE 0x4628 1 MOV r0,r5 false
+Instruction 909 S:0xC00205E0 0x2D00 0 CMP r5,#0 false
+Instruction 910 S:0xC00205E2 0xD0F3 1 BEQ {pc}-0x16 ; 0xc00205cc true
+Instruction 911 S:0xC00205CC 0xB003 8 ADD sp,sp,#0xc false
+Instruction 912 S:0xC00205CE 0xBD30 3 POP {r4,r5,pc} true
+Instruction 913 S:0xC000CD40 0xB672 10 CPSID i false
+Instruction 914 S:0xC000CD42 0xF8D91000 1 LDR r1,[r9,#0] false
+Instruction 915 S:0xC000CD46 0xF0110F07 2 TST r1,#7 false
+Instruction 916 S:0xC000CD4A 0xF040801C 0 BNE.W {pc}+0x3c ; 0xc000cd86 true fail
+Instruction 917 S:0xC000CD4E 0xF3BF8F2F 1 CLREX false
+Instruction 918 S:0xC000CD52 0x466A 1 MOV r2,sp false
+Instruction 919 S:0xC000CD54 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 920 S:0xC000CD58 0xF083030C 2 EOR r3,r3,#0xc false
+Instruction 921 S:0xC000CD5C 0xF3838100 3 MSR CPSR_c,r3 false
+Instruction 922 S:0xC000CD60 0xF8D2D03C 5 LDR sp,[r2,#0x3c] false
+Instruction 923 S:0xC000CD64 0xF8D2E040 1 LDR lr,[r2,#0x40] false
+Instruction 924 S:0xC000CD68 0xF083030C 0 EOR r3,r3,#0xc false
+Instruction 925 S:0xC000CD6C 0xF3838100 3 MSR CPSR_c,r3 false
+Instruction 926 S:0xC000CD70 0x9912 5 LDR r1,[sp,#0x48] false
+Instruction 927 S:0xC000CD72 0xF8DDE044 1 LDR lr,[sp,#0x44] false
+Instruction 928 S:0xC000CD76 0xB00F 0 ADD sp,sp,#0x3c false
+Instruction 929 S:0xC000CD78 0xF3918F00 2 MSR SPSR_cxsf,r1 false
+Instruction 930 S:0xC000CD7C 0xE91D1FFE 5 LDMDB sp,{r1-r12} false
+Instruction 931 S:0xC000CD80 0xB005 7 ADD sp,sp,#0x14 false
+Instruction 932 S:0xC000CD82 0xF3DE8F00 1 SUBS pc,lr,#0 true
+Info Return from exception
+Timestamp Timestamp: 562536961601
+Cycle Count 1922 Tracing disabled
+Info Tracing enabled
+Instruction 933 S:0xC000CE40 0xB092 1 SUB sp,sp,#0x48 false
+Timestamp Timestamp: 562536961733
+Instruction 934 S:0xC000CE42 0xE88D1FFF 6 STM sp,{r0-r12} false
+Instruction 935 S:0xC000CE46 0x46E8 11 MOV r8,sp false
+Instruction 936 S:0xC000CE48 0xF3EF8A00 1 MRS r10,APSR ; formerly CPSR false
+Instruction 937 S:0xC000CE4C 0xF08A0A0C 2 EOR r10,r10,#0xc false
+Instruction 938 S:0xC000CE50 0xF38A8100 3 MSR CPSR_c,r10 false
+Instruction 939 S:0xC000CE54 0xF8C8D034 5 STR sp,[r8,#0x34] false
+Instruction 940 S:0xC000CE58 0xF8C8E038 1 STR lr,[r8,#0x38] false
+Instruction 941 S:0xC000CE5C 0xF08A0A0C 0 EOR r10,r10,#0xc false
+Instruction 942 S:0xC000CE60 0xF38A8100 3 MSR CPSR_c,r10 false
+Instruction 943 S:0xC000CE64 0xF3FF8800 5 MRS r8,SPSR false
+Instruction 944 S:0xC000CE68 0xF8CDE03C 1 STR lr,[sp,#0x3c] false
+Instruction 945 S:0xC000CE6C 0xF8CD8040 1 STR r8,[sp,#0x40] false
+Instruction 946 S:0xC000CE70 0x9011 1 STR r0,[sp,#0x44] false
+Instruction 947 S:0xC000CE72 0xF8DFC08C 3 LDR r12,[pc,#140] ; [0xC000CF00] = 0xC06013D4 false
+Instruction 948 S:0xC000CE76 0xF8DCC000 5 LDR r12,[r12,#0] false
+Instruction 949 S:0xC000CE7A 0xEE01CF10 1 MCR p15,#0x0,r12,c1,c0,#0 false
+Instruction 950 S:0xC000CE7E 0xB662 6 CPSIE i false
+Instruction 951 S:0xC000CE80 0x46E9 1 MOV r9,sp false
+Instruction 952 S:0xC000CE82 0xEA4F3959 2 LSR r9,r9,#13 false
+Instruction 953 S:0xC000CE86 0xEA4F3949 2 LSL r9,r9,#13 false
+Instruction 954 S:0xC000CE8A 0xF20F0878 0 ADR.W r8,{pc}+0x7a ; 0xc000cf04 false
+Instruction 955 S:0xC000CE8E 0xF8D9A000 5 LDR r10,[r9,#0] false
+Instruction 956 S:0xC000CE92 0xE92D0030 3 PUSH.W {r4,r5} false
+Instruction 957 S:0xC000CE96 0xF41A6F70 1 TST r10,#0xf00 false
+Instruction 958 S:0xC000CE9A 0xF0408012 0 BNE.W {pc}+0x28 ; 0xc000cec2 true fail
+Instruction 959 S:0xC000CE9E 0xF5B77FC0 1 CMP r7,#0x180 false
+Instruction 960 S:0xC000CEA2 0xF2AF1E63 1 ADR lr,{pc}-0x161 ; 0xc000cd41 false
+Instruction 961 S:0xC000CEA6 0xBF38 0 IT CC false
+Instruction 962 S:0xC000CEA8 0xF858F027 3 LDR pc,[r8,r7,LSL #2] true
+Cycle Count 1622 Tracing disabled
+Info Tracing enabled
+Instruction 963 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 964 S:0xC00331C2 0xB500 4 PUSH {lr} false
+Instruction 965 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 966 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 967 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 968 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 969 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 970 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 971 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 972 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 89 Tracing disabled
+Info Tracing enabled
+Instruction 973 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 974 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 975 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 976 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 977 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 978 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 979 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 980 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 981 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 982 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 544 Tracing disabled
+Info Tracing enabled
+Instruction 983 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 984 S:0xC00331C2 0xB500 4 PUSH {lr} false
+Instruction 985 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 986 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 987 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 988 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 989 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 990 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 991 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 992 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 65 Tracing disabled
+Info Tracing enabled
+Instruction 993 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 994 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 995 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 996 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 997 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 998 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 999 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 1000 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 1001 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 1002 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 318 Tracing disabled
+Info Tracing enabled
+Instruction 1003 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 1004 S:0xC00331C2 0xB500 6 PUSH {lr} false
+Instruction 1005 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 1006 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 1007 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 1008 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 1009 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 1010 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 1011 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 1012 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 56 Tracing disabled
+Info Tracing enabled
+Instruction 1013 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 1014 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 1015 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 1016 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 1017 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 1018 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 1019 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 1020 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 1021 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 1022 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 285 Tracing disabled
+Info Tracing enabled
+Instruction 1023 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 1024 S:0xC00331C2 0xB500 4 PUSH {lr} false
+Instruction 1025 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 1026 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 1027 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 1028 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 1029 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 1030 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 1031 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 1032 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 69 Tracing disabled
+Info Tracing enabled
+Instruction 1033 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 1034 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 1035 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 1036 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 1037 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 1038 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 1039 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 1040 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 1041 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 1042 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 699 Tracing disabled
+Info Tracing enabled
+Instruction 1043 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 1044 S:0xC00331C2 0xB500 6 PUSH {lr} false
+Instruction 1045 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 1046 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 1047 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 1048 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 1049 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 1050 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 1051 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 1052 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 68 Tracing disabled
+Info Tracing enabled
+Instruction 1053 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 1054 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 1055 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 1056 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 1057 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 1058 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 1059 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 1060 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 1061 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 1062 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 153 Tracing disabled
+Info Tracing enabled
+Instruction 1063 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 1064 S:0xC00331C2 0xB500 4 PUSH {lr} false
+Instruction 1065 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 1066 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 1067 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 1068 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 1069 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 1070 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 1071 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 1072 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 63 Tracing disabled
+Info Tracing enabled
+Instruction 1073 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 1074 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 1075 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 1076 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 1077 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 1078 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 1079 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 1080 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 1081 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 1082 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 149 Tracing disabled
+Info Tracing enabled
+Instruction 1083 S:0xC002D904 0xB5F0 1 PUSH {r4-r7,lr} false
+Instruction 1084 S:0xC002D906 0xB089 3 SUB sp,sp,#0x24 false
+Instruction 1085 S:0xC002D908 0xB500 3 PUSH {lr} false
+Instruction 1086 S:0xC002D90A 0xF85DEB04 2 POP {lr} false
+Instruction 1087 S:0xC002D90E 0x4604 0 MOV r4,r0 false
+Instruction 1088 S:0xC002D910 0xB672 1 CPSID i false
+Instruction 1089 S:0xC002D912 0xF7FFFE59 1 BL {pc}-0x34a ; 0xc002d5c8 true
+Instruction 1090 S:0xC002D5C8 0xB500 1 PUSH {lr} false
+Instruction 1091 S:0xC002D5CA 0xF85DEB04 2 POP {lr} false
+Instruction 1092 S:0xC002D5CE 0x6801 11 LDR r1,[r0,#0] false
+Instruction 1093 S:0xC002D5D0 0xF0110004 2 ANDS r0,r1,#4 false
+Instruction 1094 S:0xC002D5D4 0xD110 0 BNE {pc}+0x24 ; 0xc002d5f8 true fail
+Instruction 1095 S:0xC002D5D6 0x0949 1 LSRS r1,r1,#5 false
+Instruction 1096 S:0xC002D5D8 0xF06F4378 0 MVN r3,#0xf8000000 false
+Instruction 1097 S:0xC002D5DC 0x4299 1 CMP r1,r3 false
+Instruction 1098 S:0xC002D5DE 0xD00A 0 BEQ {pc}+0x18 ; 0xc002d5f6 true fail
+Instruction 1099 S:0xC002D5E0 0x4B0A 14 LDR r3,[pc,#40] ; [0xC002D60C] = 0xC064AEB0 false
+Instruction 1100 S:0xC002D5E2 0x689B 5 LDR r3,[r3,#8] false
+Instruction 1101 S:0xC002D5E4 0xB123 2 CBZ r3,{pc}+0xc ; 0xc002d5f0 true fail
+Instruction 1102 S:0xC002D5E6 0x681A 14 LDR r2,[r3,#0] false
+Instruction 1103 S:0xC002D5E8 0xF02100FF 0 BIC r0,r1,#0xff false
+Instruction 1104 S:0xC002D5EC 0x4290 2 CMP r0,r2 false
+Instruction 1105 S:0xC002D5EE 0xD007 0 BEQ {pc}+0x12 ; 0xc002d600 true
+Instruction 1106 S:0xC002D600 0xB2C9 19 UXTB r1,r1 false
+Instruction 1107 S:0xC002D602 0x3108 1 ADDS r1,r1,#8 false
+Instruction 1108 S:0xC002D604 0xEB030381 2 ADD r3,r3,r1,LSL #2 false
+Instruction 1109 S:0xC002D608 0x6858 3 LDR r0,[r3,#4] false
+Instruction 1110 S:0xC002D60A 0x4770 1 BX lr true
+Instruction 1111 S:0xC002D916 0x4605 1 MOV r5,r0 false
+Instruction 1112 S:0xC002D918 0x2800 0 CMP r0,#0 false
+Instruction 1113 S:0xC002D91A 0xD037 1 BEQ {pc}+0x72 ; 0xc002d98c true fail
+Instruction 1114 S:0xC002D91C 0xF3B6FE4C 1 BL {pc}+0x3b6c9c ; 0xc03e45b8 true
+Cycle Count 81 Tracing disabled
+Info Tracing enabled
+Instruction 1115 S:0xC002D920 0x6820 1 LDR r0,[r4,#0] false
+Instruction 1116 S:0xC002D922 0x0742 3 LSLS r2,r0,#29 false
+Instruction 1117 S:0xC002D924 0xD535 1 BPL {pc}+0x6e ; 0xc002d992 true
+Instruction 1118 S:0xC002D992 0x4621 12 MOV r1,r4 false
+Instruction 1119 S:0xC002D994 0x4628 0 MOV r0,r5 false
+Instruction 1120 S:0xC002D996 0xF7FEFDA9 1 BL {pc}-0x14aa ; 0xc002c4ec true
+Instruction 1121 S:0xC002C4EC 0xB500 3 PUSH {lr} false
+Instruction 1122 S:0xC002C4EE 0xF85DEB04 2 POP {lr} false
+Instruction 1123 S:0xC002C4F2 0x2301 0 MOVS r3,#1 false
+Instruction 1124 S:0xC002C4F4 0xF6C96337 1 MOVT r3,#0x9e37 false
+Instruction 1125 S:0xC002C4F8 0xFB03F301 2 MUL r3,r3,r1 false
+Instruction 1126 S:0xC002C4FC 0x0E9B 3 LSRS r3,r3,#26 false
+Instruction 1127 S:0xC002C4FE 0xEB000083 11 ADD r0,r0,r3,LSL #2 false
+Instruction 1128 S:0xC002C502 0xF8D00094 13 LDR r0,[r0,#0x94] false
+Instruction 1129 S:0xC002C506 0xB938 2 CBNZ r0,{pc}+0x12 ; 0xc002c518 true fail
+Instruction 1130 S:0xC002C508 0x4770 1 BX lr true
+Instruction 1131 S:0xC002D99A 0x4604 1 MOV r4,r0 false
+Instruction 1132 S:0xC002D99C 0xB198 1 CBZ r0,{pc}+0x2a ; 0xc002d9c6 true
+Instruction 1133 S:0xC002D9C6 0xF3BF8F5F 20 DMB false
+Instruction 1134 S:0xC002D9CA 0x882B 35 LDRH r3,[r5,#0] false
+Instruction 1135 S:0xC002D9CC 0x3301 2 ADDS r3,#1 false
+Instruction 1136 S:0xC002D9CE 0x802B 1 STRH r3,[r5,#0] false
+Instruction 1137 S:0xC002D9D0 0xF3BF8F4F 31 DSB false
+Instruction 1138 S:0xC002D9D4 0xF3AF8004 1 SEV.W false
+Instruction 1139 S:0xC002D9D8 0xB662 1 CPSIE i false
+Instruction 1140 S:0xC002D9DA 0xE7D8 1 B {pc}-0x4c ; 0xc002d98e true
+Instruction 1141 S:0xC002D98E 0x2000 1 MOVS r0,#0 false
+Instruction 1142 S:0xC002D990 0xE7FA 0 B {pc}-8 ; 0xc002d988 true
+Instruction 1143 S:0xC002D988 0xB009 1 ADD sp,sp,#0x24 false
+Instruction 1144 S:0xC002D98A 0xBDF0 3 POP {r4-r7,pc} true
+Cycle Count 785 Tracing disabled
+Info Tracing enabled
+Instruction 1145 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 1146 S:0xC00331C2 0xB500 4 PUSH {lr} false
+Instruction 1147 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 1148 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 1149 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 1150 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 1151 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 1152 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 1153 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 1154 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 78 Tracing disabled
+Info Tracing enabled
+Instruction 1155 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 1156 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 1157 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 1158 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 1159 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 1160 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 1161 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 1162 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 1163 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 1164 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 284 Tracing disabled
+Info Tracing enabled
+Instruction 1165 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 1166 S:0xC00331C2 0xB500 4 PUSH {lr} false
+Instruction 1167 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 1168 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 1169 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 1170 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 1171 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 1172 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 1173 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 1174 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 55 Tracing disabled
+Info Tracing enabled
+Instruction 1175 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 1176 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 1177 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 1178 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 1179 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 1180 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 1181 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 1182 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 1183 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 1184 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 582 Tracing disabled
+Info Tracing enabled
+Instruction 1185 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 1186 S:0xC00331C2 0xB500 4 PUSH {lr} false
+Instruction 1187 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 1188 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 1189 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 1190 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 1191 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 1192 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 1193 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 1194 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 53 Tracing disabled
+Info Tracing enabled
+Instruction 1195 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 1196 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 1197 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 1198 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 1199 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 1200 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 1201 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 1202 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 1203 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 1204 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 182 Tracing disabled
+Info Tracing enabled
+Instruction 1205 S:0xC00331C0 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 1206 S:0xC00331C2 0xB500 4 PUSH {lr} false
+Instruction 1207 S:0xC00331C4 0xF85DEB04 2 POP {lr} false
+Instruction 1208 S:0xC00331C8 0x460C 0 MOV r4,r1 false
+Instruction 1209 S:0xC00331CA 0x680B 1 LDR r3,[r1,#0] false
+Instruction 1210 S:0xC00331CC 0x460D 0 MOV r5,r1 false
+Instruction 1211 S:0xC00331CE 0x4606 1 MOV r6,r0 false
+Instruction 1212 S:0xC00331D0 0xF0230301 1 BIC r3,r3,#1 false
+Instruction 1213 S:0xC00331D4 0xF8443B0C 1 STR r3,[r4],#0xc false
+Instruction 1214 S:0xC00331D8 0xF3B1FA06 0 BL {pc}+0x3b1410 ; 0xc03e45e8 true
+Cycle Count 63 Tracing disabled
+Info Tracing enabled
+Instruction 1215 S:0xC00331DC 0x4633 1 MOV r3,r6 false
+Instruction 1216 S:0xC00331DE 0xF8532F04 3 LDR r2,[r3,#4]! false
+Instruction 1217 S:0xC00331E2 0x6054 3 STR r4,[r2,#4] false
+Instruction 1218 S:0xC00331E4 0x60EA 1 STR r2,[r5,#0xc] false
+Instruction 1219 S:0xC00331E6 0x612B 1 STR r3,[r5,#0x10] false
+Instruction 1220 S:0xC00331E8 0x6074 1 STR r4,[r6,#4] false
+Instruction 1221 S:0xC00331EA 0x4601 0 MOV r1,r0 false
+Instruction 1222 S:0xC00331EC 0x4630 1 MOV r0,r6 false
+Instruction 1223 S:0xC00331EE 0xE8BD4070 1 POP {r4-r6,lr} false
+Instruction 1224 S:0xC00331F2 0xF3B1BA31 2 B.W {pc}+0x3b1466 ; 0xc03e4658 true
+Cycle Count 113 Tracing disabled
+Info Tracing enabled
+Instruction 1225 S:0xC002D904 0xB5F0 1 PUSH {r4-r7,lr} false
+Instruction 1226 S:0xC002D906 0xB089 3 SUB sp,sp,#0x24 false
+Instruction 1227 S:0xC002D908 0xB500 3 PUSH {lr} false
+Instruction 1228 S:0xC002D90A 0xF85DEB04 2 POP {lr} false
+Instruction 1229 S:0xC002D90E 0x4604 0 MOV r4,r0 false
+Instruction 1230 S:0xC002D910 0xB672 1 CPSID i false
+Instruction 1231 S:0xC002D912 0xF7FFFE59 1 BL {pc}-0x34a ; 0xc002d5c8 true
+Instruction 1232 S:0xC002D5C8 0xB500 1 PUSH {lr} false
+Instruction 1233 S:0xC002D5CA 0xF85DEB04 2 POP {lr} false
+Instruction 1234 S:0xC002D5CE 0x6801 11 LDR r1,[r0,#0] false
+Instruction 1235 S:0xC002D5D0 0xF0110004 2 ANDS r0,r1,#4 false
+Instruction 1236 S:0xC002D5D4 0xD110 0 BNE {pc}+0x24 ; 0xc002d5f8 true fail
+Instruction 1237 S:0xC002D5D6 0x0949 1 LSRS r1,r1,#5 false
+Instruction 1238 S:0xC002D5D8 0xF06F4378 0 MVN r3,#0xf8000000 false
+Instruction 1239 S:0xC002D5DC 0x4299 1 CMP r1,r3 false
+Instruction 1240 S:0xC002D5DE 0xD00A 0 BEQ {pc}+0x18 ; 0xc002d5f6 true fail
+Instruction 1241 S:0xC002D5E0 0x4B0A 3 LDR r3,[pc,#40] ; [0xC002D60C] = 0xC064AEB0 false
+Instruction 1242 S:0xC002D5E2 0x689B 5 LDR r3,[r3,#8] false
+Instruction 1243 S:0xC002D5E4 0xB123 2 CBZ r3,{pc}+0xc ; 0xc002d5f0 true fail
+Instruction 1244 S:0xC002D5E6 0x681A 3 LDR r2,[r3,#0] false
+Instruction 1245 S:0xC002D5E8 0xF02100FF 0 BIC r0,r1,#0xff false
+Instruction 1246 S:0xC002D5EC 0x4290 2 CMP r0,r2 false
+Instruction 1247 S:0xC002D5EE 0xD007 0 BEQ {pc}+0x12 ; 0xc002d600 true
+Instruction 1248 S:0xC002D600 0xB2C9 8 UXTB r1,r1 false
+Instruction 1249 S:0xC002D602 0x3108 1 ADDS r1,r1,#8 false
+Instruction 1250 S:0xC002D604 0xEB030381 2 ADD r3,r3,r1,LSL #2 false
+Instruction 1251 S:0xC002D608 0x6858 3 LDR r0,[r3,#4] false
+Instruction 1252 S:0xC002D60A 0x4770 1 BX lr true
+Instruction 1253 S:0xC002D916 0x4605 1 MOV r5,r0 false
+Instruction 1254 S:0xC002D918 0x2800 0 CMP r0,#0 false
+Instruction 1255 S:0xC002D91A 0xD037 1 BEQ {pc}+0x72 ; 0xc002d98c true fail
+Instruction 1256 S:0xC002D91C 0xF3B6FE4C 1 BL {pc}+0x3b6c9c ; 0xc03e45b8 true
+Cycle Count 72 Tracing disabled
+Info Tracing enabled
+Instruction 1257 S:0xC002D920 0x6820 1 LDR r0,[r4,#0] false
+Instruction 1258 S:0xC002D922 0x0742 3 LSLS r2,r0,#29 false
+Instruction 1259 S:0xC002D924 0xD535 0 BPL {pc}+0x6e ; 0xc002d992 true
+Instruction 1260 S:0xC002D992 0x4621 8 MOV r1,r4 false
+Instruction 1261 S:0xC002D994 0x4628 0 MOV r0,r5 false
+Instruction 1262 S:0xC002D996 0xF7FEFDA9 1 BL {pc}-0x14aa ; 0xc002c4ec true
+Instruction 1263 S:0xC002C4EC 0xB500 1 PUSH {lr} false
+Instruction 1264 S:0xC002C4EE 0xF85DEB04 2 POP {lr} false
+Instruction 1265 S:0xC002C4F2 0x2301 1 MOVS r3,#1 false
+Instruction 1266 S:0xC002C4F4 0xF6C96337 1 MOVT r3,#0x9e37 false
+Instruction 1267 S:0xC002C4F8 0xFB03F301 2 MUL r3,r3,r1 false
+Instruction 1268 S:0xC002C4FC 0x0E9B 3 LSRS r3,r3,#26 false
+Instruction 1269 S:0xC002C4FE 0xEB000083 2 ADD r0,r0,r3,LSL #2 false
+Instruction 1270 S:0xC002C502 0xF8D00094 13 LDR r0,[r0,#0x94] false
+Instruction 1271 S:0xC002C506 0xB938 2 CBNZ r0,{pc}+0x12 ; 0xc002c518 true fail
+Instruction 1272 S:0xC002C508 0x4770 1 BX lr true
+Instruction 1273 S:0xC002D99A 0x4604 1 MOV r4,r0 false
+Instruction 1274 S:0xC002D99C 0xB198 1 CBZ r0,{pc}+0x2a ; 0xc002d9c6 true
+Instruction 1275 S:0xC002D9C6 0xF3BF8F5F 9 DMB false
+Instruction 1276 S:0xC002D9CA 0x882B 28 LDRH r3,[r5,#0] false
+Instruction 1277 S:0xC002D9CC 0x3301 2 ADDS r3,#1 false
+Instruction 1278 S:0xC002D9CE 0x802B 1 STRH r3,[r5,#0] false
+Instruction 1279 S:0xC002D9D0 0xF3BF8F4F 31 DSB false
+Instruction 1280 S:0xC002D9D4 0xF3AF8004 1 SEV.W false
+Instruction 1281 S:0xC002D9D8 0xB662 1 CPSIE i false
+Instruction 1282 S:0xC002D9DA 0xE7D8 1 B {pc}-0x4c ; 0xc002d98e true
+Instruction 1283 S:0xC002D98E 0x2000 1 MOVS r0,#0 false
+Instruction 1284 S:0xC002D990 0xE7FA 0 B {pc}-8 ; 0xc002d988 true
+Instruction 1285 S:0xC002D988 0xB009 1 ADD sp,sp,#0x24 false
+Instruction 1286 S:0xC002D98A 0xBDF0 3 POP {r4-r7,pc} true
+Cycle Count 1175 Tracing disabled
+Info Tracing enabled
+Instruction 1287 S:0xC003BE34 0xB488 1 PUSH {r3,r7} false
+Instruction 1288 S:0xC003BE36 0xAF00 1 ADD r7,sp,#0 false
+Instruction 1289 S:0xC003BE38 0xB500 2 PUSH {lr} false
+Instruction 1290 S:0xC003BE3A 0xF85DEB04 2 POP {lr} false
+Instruction 1291 S:0xC003BE3E 0x680B 1 LDR r3,[r1,#0] false
+Instruction 1292 S:0xC003BE40 0x079B 12 LSLS r3,r3,#30 false
+Instruction 1293 S:0xC003BE42 0xD507 0 BPL {pc}+0x12 ; 0xc003be54 true
+Instruction 1294 S:0xC003BE54 0x46BD 21 MOV sp,r7 false
+Instruction 1295 S:0xC003BE56 0xBC88 3 POP {r3,r7} false
+Instruction 1296 S:0xC003BE58 0xF7FFBCBC 1 B.W {pc}-0x684 ; 0xc003b7d4 true
+Instruction 1297 S:0xC003B7D4 0xE92D47F0 16 PUSH {r4-r10,lr} false
+Instruction 1298 S:0xC003B7D8 0xAF00 4 ADD r7,sp,#0 false
+Instruction 1299 S:0xC003B7DA 0xB500 2 PUSH {lr} false
+Instruction 1300 S:0xC003B7DC 0xF85DEB04 2 POP {lr} false
+Instruction 1301 S:0xC003B7E0 0x460E 11 MOV r6,r1 false
+Instruction 1302 S:0xC003B7E2 0x4692 0 MOV r10,r2 false
+Instruction 1303 S:0xC003B7E4 0x4680 1 MOV r8,r0 false
+Instruction 1304 S:0xC003B7E6 0xF7FFFFCF 0 BL {pc}-0x5e ; 0xc003b788 true
+Instruction 1305 S:0xC003B788 0xE92D43C8 3 PUSH {r3,r6-r9,lr} false
+Instruction 1306 S:0xC003B78C 0xAF00 3 ADD r7,sp,#0 false
+Instruction 1307 S:0xC003B78E 0xB500 2 PUSH {lr} false
+Instruction 1308 S:0xC003B790 0xF85DEB04 2 POP {lr} false
+Timestamp Timestamp: 562536962321
+Instruction 1309 S:0xC003B794 0x6AC3 1 LDR r3,[r0,#0x2c] false
+Instruction 1310 S:0xC003B796 0x4606 0 MOV r6,r0 false
+Instruction 1311 S:0xC003B798 0x2B00 2 CMP r3,#0 false
+Instruction 1312 S:0xC003B79A 0xDD01 0 BLE {pc}+6 ; 0xc003b7a0 true
+Instruction 1313 S:0xC003B7A0 0xF8D004C0 10 LDR r0,[r0,#0x4c0] false
+Instruction 1314 S:0xC003B7A4 0xF003FD86 0 BL {pc}+0x3b10 ; 0xc003f2b4 true
+Instruction 1315 S:0xC003F2B4 0x4B03 5 LDR r3,[pc,#12] ; [0xC003F2C4] = 0xC05FC57C false
+Instruction 1316 S:0xC003F2B6 0x6818 3 LDR r0,[r3,#0] false
+Instruction 1317 S:0xC003F2B8 0xB108 2 CBZ r0,{pc}+6 ; 0xc003f2be true fail
+Instruction 1318 S:0xC003F2BA 0xF7CFBD35 1 B {pc}-0x30592 ; 0xc000ed28 true
+Instruction 1319 S:0xC000ED28 0xB508 12 PUSH {r3,lr} false
+Instruction 1320 S:0xC000ED2A 0xF24C43CC 1 MOV r3,#0xc4cc false
+Instruction 1321 S:0xC000ED2E 0xF2CC035F 1 MOVT r3,#0xc05f false
+Instruction 1322 S:0xC000ED32 0x689B 3 LDR r3,[r3,#8] false
+Instruction 1323 S:0xC000ED34 0x4798 1 BLX r3 true
+Instruction 1324 S:0xC00113EC 0xF24A2340 21 MOV r3,#0xa240 false
+Instruction 1325 S:0xC00113F0 0xF2CC0362 1 MOVT r3,#0xc062 false
+Instruction 1326 S:0xC00113F4 0xB510 1 PUSH {r4,lr} false
+Instruction 1327 S:0xC00113F6 0x681B 4 LDR r3,[r3,#0] false
+Instruction 1328 S:0xC00113F8 0x4798 1 BLX r3 true
+Timestamp Timestamp: 562536962326
+Cycle Count 28 Tracing disabled
+Info Tracing enabled
+Instruction 1329 S:0xC00113FA 0xF24C5320 1 MOV r3,#0xc520 false
+Instruction 1330 S:0xC00113FE 0xF2CC035F 1 MOVT r3,#0xc05f false
+Instruction 1331 S:0xC0011402 0x681C 3 LDR r4,[r3,#0] false
+Instruction 1332 S:0xC0011404 0xFBA02304 3 UMULL r2,r3,r0,r4 false
+Instruction 1333 S:0xC0011408 0x4610 2 MOV r0,r2 false
+Instruction 1334 S:0xC001140A 0xFB043101 1 MLA r1,r4,r1,r3 false
+Instruction 1335 S:0xC001140E 0xBD10 1 POP {r4,pc} true
+Instruction 1336 S:0xC000ED36 0xBD08 3 POP {r3,pc} true
+Instruction 1337 S:0xC003B7A8 0xF506638F 1 ADD r3,r6,#0x478 false
+Instruction 1338 S:0xC003B7AC 0xF5066690 0 ADD r6,r6,#0x480 false
+Instruction 1339 S:0xC003B7B0 0xE9D38900 3 LDRD r8,r9,[r3,#0] false
+Instruction 1340 S:0xC003B7B4 0xE9C30100 1 STRD r0,r1,[r3,#0] false
+Instruction 1341 S:0xC003B7B8 0xE9D62300 54 LDRD r2,r3,[r6,#0] false
+Instruction 1342 S:0xC003B7BC 0xEBB20208 2 SUBS r2,r2,r8 false
+Instruction 1343 S:0xC003B7C0 0xEB630309 1 SBC r3,r3,r9 false
+Instruction 1344 S:0xC003B7C4 0x1812 1 ADDS r2,r2,r0 false
+Instruction 1345 S:0xC003B7C6 0xEB430301 1 ADC r3,r3,r1 false
+Instruction 1346 S:0xC003B7CA 0xE9C62300 1 STRD r2,r3,[r6,#0] false
+Instruction 1347 S:0xC003B7CE 0xE8BD83C8 1 POP {r3,r6-r9,pc} true
+Instruction 1348 S:0xC003B7EA 0x6870 6 LDR r0,[r6,#4] false
+Instruction 1349 S:0xC003B7EC 0xF8DFE070 3 LDR lr,[pc,#112] ; [0xC003B860] = 0xC05FD5C0 false
+Instruction 1350 S:0xC003B7F0 0x4631 0 MOV r1,r6 false
+Instruction 1351 S:0xC003B7F2 0xF8DFC070 2 LDR r12,[pc,#112] ; [0xC003B864] = 0xC05F3080 false
+Instruction 1352 S:0xC003B7F6 0x6944 2 LDR r4,[r0,#0x14] false
+Instruction 1353 S:0xC003B7F8 0xE9F1237A 2 LDRD r2,r3,[r1,#0x1e8]! false
+Instruction 1354 S:0xC003B7FC 0x4665 1 MOV r5,r12 false
+Instruction 1355 S:0xC003B7FE 0xF85E4024 3 LDR r4,[lr,r4,LSL #2] false
+Instruction 1356 S:0xC003B802 0xEA520903 1 ORRS r9,r2,r3 false
+Instruction 1357 S:0xC003B806 0x4425 1 ADD r5,r5,r4 false
+Instruction 1358 S:0xC003B808 0xF505658F 1 ADD r5,r5,#0x478 false
+Instruction 1359 S:0xC003B80C 0xE9D54500 3 LDRD r4,r5,[r5,#0] false
+Instruction 1360 S:0xC003B810 0xD002 1 BEQ {pc}+8 ; 0xc003b818 true
+Instruction 1361 S:0xC003B818 0x46B1 1 MOV r9,r6 false
+Instruction 1362 S:0xC003B81A 0x2400 0 MOVS r4,#0 false
+Instruction 1363 S:0xC003B81C 0x2500 1 MOVS r5,#0 false
+Instruction 1364 S:0xC003B81E 0xE9C14500 1 STRD r4,r5,[r1,#0] false
+Instruction 1365 S:0xC003B822 0xE9F94576 1 LDRD r4,r5,[r9,#0x1d8]! false
+Instruction 1366 S:0xC003B826 0x18A4 2 ADDS r4,r4,r2 false
+Instruction 1367 S:0xC003B828 0xEB450503 1 ADC r5,r5,r3 false
+Instruction 1368 S:0xC003B82C 0xE9C94500 1 STRD r4,r5,[r9,#0] false
+Instruction 1369 S:0xC003B830 0x6941 1 LDR r1,[r0,#0x14] false
+Instruction 1370 S:0xC003B832 0xF85E1021 3 LDR r1,[lr,r1,LSL #2] false
+Instruction 1371 S:0xC003B836 0xEB1C0C01 2 ADDS r12,r12,r1 false
+Instruction 1372 S:0xC003B83A 0xD008 0 BEQ {pc}+0x14 ; 0xc003b84e true fail
+Instruction 1373 S:0xC003B83C 0xF50C6CAC 10 ADD r12,r12,#0x560 false
+Instruction 1374 S:0xC003B840 0xE9DC0100 3 LDRD r0,r1,[r12,#0] false
+Instruction 1375 S:0xC003B844 0x1880 2 ADDS r0,r0,r2 false
+Instruction 1376 S:0xC003B846 0xEB410103 1 ADC r1,r1,r3 false
+Instruction 1377 S:0xC003B84A 0xE9CC0100 1 STRD r0,r1,[r12,#0] false
+Instruction 1378 S:0xC003B84E 0x6B33 1 LDR r3,[r6,#0x30] false
+Instruction 1379 S:0xC003B850 0x4640 0 MOV r0,r8 false
+Instruction 1380 S:0xC003B852 0x4652 1 MOV r2,r10 false
+Instruction 1381 S:0xC003B854 0x4631 0 MOV r1,r6 false
+Instruction 1382 S:0xC003B856 0x689B 14 LDR r3,[r3,#8] false
+Instruction 1383 S:0xC003B858 0x4798 1 BLX r3 true
+Instruction 1384 S:0xC004268C 0xE92D4FF0 21 PUSH {r4-r11,lr} false
+Instruction 1385 S:0xC0042690 0xB09B 7 SUB sp,sp,#0x6c false
+Instruction 1386 S:0xC0042692 0xB500 3 PUSH {lr} false
+Instruction 1387 S:0xC0042694 0xF85DEB04 2 POP {lr} false
+Instruction 1388 S:0xC0042698 0xF1110738 0 ADDS r7,r1,#0x38 false
+Instruction 1389 S:0xC004269C 0x9014 3 STR r0,[sp,#0x50] false
+Instruction 1390 S:0xC004269E 0x9215 1 STR r2,[sp,#0x54] false
+Instruction 1391 S:0xC00426A0 0xF0008172 3 BEQ.W {pc}+0x2e8 ; 0xc0042988 true fail
+Instruction 1392 S:0xC00426A4 0x4691 1 MOV r9,r2 false
+Instruction 1393 S:0xC00426A6 0xF8D76124 1 LDR r6,[r7,#0x124] false
+Instruction 1394 S:0xC00426AA 0xF0090801 0 AND r8,r9,#1 false
+Instruction 1395 S:0xC00426AE 0x4630 2 MOV r0,r6 false
+Instruction 1396 S:0xC00426B0 0xF7FDFD2A 0 BL {pc}-0x25a8 ; 0xc0040108 true
+Instruction 1397 S:0xC0040108 0xE92D4FF0 20 PUSH {r4-r11,lr} false
+Instruction 1398 S:0xC004010C 0xB085 7 SUB sp,sp,#0x14 false
+Instruction 1399 S:0xC004010E 0xB500 3 PUSH {lr} false
+Instruction 1400 S:0xC0040110 0xF85DEB04 2 POP {lr} false
+Instruction 1401 S:0xC0040114 0xF8D02084 11 LDR r2,[r0,#0x84] false
+Instruction 1402 S:0xC0040118 0xF8D0A030 9 LDR r10,[r0,#0x30] false
+Instruction 1403 S:0xC004011C 0x4683 0 MOV r11,r0 false
+Instruction 1404 S:0xC004011E 0xF8D23480 2 LDR r3,[r2,#0x480] false
+Instruction 1405 S:0xC0040122 0xF8D2C484 1 LDR r12,[r2,#0x484] false
+Instruction 1406 S:0xC0040126 0xF1BA0F00 0 CMP r10,#0 false
+Instruction 1407 S:0xC004012A 0xD041 1 BEQ {pc}+0x86 ; 0xc00401b0 true fail
+Instruction 1408 S:0xC004012C 0xF8DA2020 23 LDR r2,[r10,#0x20] false
+Instruction 1409 S:0xC0040130 0x1A9A 2 SUBS r2,r3,r2 false
+Instruction 1410 S:0xC0040132 0xD03D 0 BEQ {pc}+0x7e ; 0xc00401b0 true fail
+Instruction 1411 S:0xC0040134 0xE9DA6728 13 LDRD r6,r7,[r10,#0xa0] false
+Instruction 1412 S:0xC0040138 0x2500 1 MOVS r5,#0 false
+Instruction 1413 S:0xC004013A 0x4614 0 MOV r4,r2 false
+Instruction 1414 S:0xC004013C 0x4629 1 MOV r1,r5 false
+Instruction 1415 S:0xC004013E 0x42BD 1 CMP r5,r7 false
+Instruction 1416 S:0xC0040140 0xBF08 15 IT EQ false
+Instruction 1417 S:0xC0040142 0x42B4 1 CMP r4,r6 false
+Instruction 1418 S:0xC0040144 0x4610 0 MOV r0,r2 false
+Instruction 1419 S:0xC0040146 0xBF3C 1 ITT CC false
+Instruction 1420 S:0xC0040148 0x4639 1 MOV r1,r7 false
+Instruction 1421 S:0xC004014A 0x4630 0 MOV r0,r6 false
+Instruction 1422 S:0xC004014C 0xE9DA670A 1 LDRD r6,r7,[r10,#0x28] false
+Instruction 1423 S:0xC0040150 0xF8CA10A4 1 STR r1,[r10,#0xa4] false
+Instruction 1424 S:0xC0040154 0x18B6 1 ADDS r6,r6,r2 false
+Instruction 1425 S:0xC0040156 0xF8CA00A0 1 STR r0,[r10,#0xa0] false
+Instruction 1426 S:0xC004015A 0xEB470705 1 ADC r7,r7,r5 false
+Instruction 1427 S:0xC004015E 0xE9CA670A 14 STRD r6,r7,[r10,#0x28] false
+Instruction 1428 S:0xC0040162 0xE9DB6704 1 LDRD r6,r7,[r11,#0x10] false
+Instruction 1429 S:0xC0040166 0x18B6 2 ADDS r6,r6,r2 false
+Instruction 1430 S:0xC0040168 0xEB470705 1 ADC r7,r7,r5 false
+Instruction 1431 S:0xC004016C 0xE9CB6704 1 STRD r6,r7,[r11,#0x10] false
+Instruction 1432 S:0xC0040170 0xF8DA1000 1 LDR r1,[r10,#0] false
+Instruction 1433 S:0xC0040174 0xF5B16F80 2 CMP r1,#0x400 false
+Instruction 1434 S:0xC0040178 0xBF04 0 ITT EQ false
+Instruction 1435 S:0xC004017A 0x4690 1 MOV r8,r2 false
+Instruction 1436 S:0xC004017C 0x46A9 0 MOV r9,r5 false
+Instruction 1437 S:0xC004017E 0xD13D 1 BNE {pc}+0x7e ; 0xc00401fc true fail
+Instruction 1438 S:0xC0040180 0xE9DA670C 11 LDRD r6,r7,[r10,#0x30] false
+Instruction 1439 S:0xC0040184 0x4658 1 MOV r0,r11 false
+Instruction 1440 S:0xC0040186 0xEB160608 1 ADDS r6,r6,r8 false
+Instruction 1441 S:0xC004018A 0xEB470709 1 ADC r7,r7,r9 false
+Instruction 1442 S:0xC004018E 0xE9CA670C 1 STRD r6,r7,[r10,#0x30] false
+Instruction 1443 S:0xC0040192 0x9303 1 STR r3,[sp,#0xc] false
+Instruction 1444 S:0xC0040194 0xF8CDC008 1 STR r12,[sp,#8] false
+Instruction 1445 S:0xC0040198 0xF7FFFB06 0 BL {pc}-0x9f0 ; 0xc003f7a8 true
+Instruction 1446 S:0xC003F7A8 0xE92D03F0 17 PUSH {r4-r9} false
+Instruction 1447 S:0xC003F7AC 0xB500 5 PUSH {lr} false
+Instruction 1448 S:0xC003F7AE 0xF85DEB04 2 POP {lr} false
+Instruction 1449 S:0xC003F7B2 0x6B03 1 LDR r3,[r0,#0x30] false
+Instruction 1450 S:0xC003F7B4 0xE9D04506 2 LDRD r4,r5,[r0,#0x18] false
+Instruction 1451 S:0xC003F7B8 0x2B00 1 CMP r3,#0 false
+Instruction 1452 S:0xC003F7BA 0xD029 0 BEQ {pc}+0x56 ; 0xc003f810 true fail
+Instruction 1453 S:0xC003F7BC 0x6AC1 10 LDR r1,[r0,#0x2c] false
+Instruction 1454 S:0xC003F7BE 0xE9D3230C 1 LDRD r2,r3,[r3,#0x30] false
+Instruction 1455 S:0xC003F7C2 0xB171 1 CBZ r1,{pc}+0x20 ; 0xc003f7e2 true fail
+Instruction 1456 S:0xC003F7C4 0xE9D1670A 3 LDRD r6,r7,[r1,#0x28] false
+Instruction 1457 S:0xC003F7C8 0x46B0 2 MOV r8,r6 false
+Instruction 1458 S:0xC003F7CA 0x46B9 1 MOV r9,r7 false
+Instruction 1459 S:0xC003F7CC 0xEBB80802 1 SUBS r8,r8,r2 false
+Instruction 1460 S:0xC003F7D0 0xEB690903 1 SBC r9,r9,r3 false
+Instruction 1461 S:0xC003F7D4 0xF1B80F00 0 CMP r8,#0 false
+Instruction 1462 S:0xC003F7D8 0xF1790100 1 SBCS r1,r9,#0 false
+Instruction 1463 S:0xC003F7DC 0xBFBC 0 ITT LT false
+Instruction 1464 S:0xC003F7DE 0x4632 1 MOV r2,r6 false fail
+Instruction 1465 S:0xC003F7E0 0x463B 9 MOV r3,r7 false fail
+Instruction 1466 S:0xC003F7E2 0x4616 0 MOV r6,r2 false
+Instruction 1467 S:0xC003F7E4 0x461F 1 MOV r7,r3 false
+Instruction 1468 S:0xC003F7E6 0x1B36 1 SUBS r6,r6,r4 false
+Instruction 1469 S:0xC003F7E8 0xEB670705 1 SBC r7,r7,r5 false
+Instruction 1470 S:0xC003F7EC 0x2E01 0 CMP r6,#1 false
+Instruction 1471 S:0xC003F7EE 0xF1770100 1 SBCS r1,r7,#0 false
+Instruction 1472 S:0xC003F7F2 0xDB0A 0 BLT {pc}+0x18 ; 0xc003f80a true
+Instruction 1473 S:0xC003F80A 0x4622 18 MOV r2,r4 false
+Instruction 1474 S:0xC003F80C 0x462B 0 MOV r3,r5 false
+Instruction 1475 S:0xC003F80E 0xE7F1 1 B {pc}-0x1a ; 0xc003f7f4 true
+Instruction 1476 S:0xC003F7F4 0xE9C02306 3 STRD r2,r3,[r0,#0x18] false
+Instruction 1477 S:0xC003F7F8 0xF3BF8F5F 1 DMB false
+Instruction 1478 S:0xC003F7FC 0xE9D02306 31 LDRD r2,r3,[r0,#0x18] false
+Instruction 1479 S:0xC003F800 0xE9C02308 3 STRD r2,r3,[r0,#0x20] false
+Instruction 1480 S:0xC003F804 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 1481 S:0xC003F808 0x4770 3 BX lr true
+Instruction 1482 S:0xC004019C 0x9B03 2 LDR r3,[sp,#0xc] false
+Instruction 1483 S:0xC004019E 0xF8DA2128 1 LDR r2,[r10,#0x128] false
+Instruction 1484 S:0xC00401A2 0xF8CA3020 1 STR r3,[r10,#0x20] false
+Instruction 1485 S:0xC00401A6 0xF8DDC008 1 LDR r12,[sp,#8] false
+Instruction 1486 S:0xC00401AA 0xF8CAC024 1 STR r12,[r10,#0x24] false
+Instruction 1487 S:0xC00401AE 0xB112 1 CBZ r2,{pc}+8 ; 0xc00401b6 true
+Instruction 1488 S:0xC00401B6 0x4B24 26 LDR r3,[pc,#144] ; [0xC0040248] = 0xC0636008 false
+Instruction 1489 S:0xC00401B8 0xE9DA670C 3 LDRD r6,r7,[r10,#0x30] false
+Instruction 1490 S:0xC00401BC 0x685A 13 LDR r2,[r3,#4] false
+Instruction 1491 S:0xC00401BE 0x2A00 2 CMP r2,#0 false
+Instruction 1492 S:0xC00401C0 0xD12C 0 BNE {pc}+0x5c ; 0xc004021c true fail
+Instruction 1493 S:0xC00401C2 0xF8DA639C 1 LDR r6,[r10,#0x39c] false
+Instruction 1494 S:0xC00401C6 0xF8D630D8 15 LDR r3,[r6,#0xd8] false
+Instruction 1495 S:0xC00401CA 0x2B00 2 CMP r3,#0 false
+Instruction 1496 S:0xC00401CC 0xD0F0 0 BEQ {pc}-0x1c ; 0xc00401b0 true
+Instruction 1497 S:0xC00401B0 0xB005 8 ADD sp,sp,#0x14 false
+Instruction 1498 S:0xC00401B2 0xE8BD8FF0 5 POP {r4-r11,pc} true
+Instruction 1499 S:0xC00426B4 0xF8D7C124 7 LDR r12,[r7,#0x124] false
+Instruction 1500 S:0xC00426B8 0xF8D73128 1 LDR r3,[r7,#0x128] false
+Instruction 1501 S:0xC00426BC 0xF8DC2084 4 LDR r2,[r12,#0x84] false
+Instruction 1502 S:0xC00426C0 0xF8D244C0 3 LDR r4,[r2,#0x4c0] false
+Instruction 1503 S:0xC00426C4 0x940A 1 STR r4,[sp,#0x28] false
+Instruction 1504 S:0xC00426C6 0x2B00 0 CMP r3,#0 false
+Instruction 1505 S:0xC00426C8 0xF00081F6 1 BEQ.W {pc}+0x3f0 ; 0xc0042ab8 true
+Instruction 1506 S:0xC0042AB8 0xF5026290 24 ADD r2,r2,#0x480 false
+Instruction 1507 S:0xC0042ABC 0xE9D24500 3 LDRD r4,r5,[r2,#0] false
+Instruction 1508 S:0xC0042AC0 0xE60A 14 B {pc}-0x3e8 ; 0xc00426d8 true
+Instruction 1509 S:0xC00426D8 0x69FA 5 LDR r2,[r7,#0x1c] false
+Instruction 1510 S:0xC00426DA 0x463B 0 MOV r3,r7 false
+Instruction 1511 S:0xC00426DC 0xE9F3014E 3 LDRD r0,r1,[r3,#0x138]! false
+Instruction 1512 S:0xC00426E0 0x9212 1 STR r2,[sp,#0x48] false
+Instruction 1513 S:0xC00426E2 0xF8DC2030 1 LDR r2,[r12,#0x30] false
+Instruction 1514 S:0xC00426E6 0x1A20 1 SUBS r0,r4,r0 false
+Instruction 1515 S:0xC00426E8 0xEB650101 1 SBC r1,r5,r1 false
+Instruction 1516 S:0xC00426EC 0x9305 1 STR r3,[sp,#0x14] false
+Instruction 1517 S:0xC00426EE 0xF8CDC010 1 STR r12,[sp,#0x10] false
+Instruction 1518 S:0xC00426F2 0x920C 1 STR r2,[sp,#0x30] false
+Instruction 1519 S:0xC00426F4 0xF7FDF932 0 BL {pc}-0x2d98 ; 0xc003f95c true
+Instruction 1520 S:0xC003F95C 0xE92D03F0 1 PUSH {r4-r9} false
+Instruction 1521 S:0xC003F960 0xB500 11 PUSH {lr} false
+Instruction 1522 S:0xC003F962 0xF85DEB04 2 POP {lr} false
+Instruction 1523 S:0xC003F966 0xF64B7640 1 MOV r6,#0xbf40 false
+Instruction 1524 S:0xC003F96A 0xF2CC0664 1 MOVT r6,#0xc064 false
+Instruction 1525 S:0xC003F96E 0x6876 16 LDR r6,[r6,#4] false
+Instruction 1526 S:0xC003F970 0xFBA18906 3 UMULL r8,r9,r1,r6 false
+Instruction 1527 S:0xC003F974 0xEA4F7CE6 1 ASR r12,r6,#31 false
+Instruction 1528 S:0xC003F978 0xFBA06706 1 UMULL r6,r7,r0,r6 false
+Instruction 1529 S:0xC003F97C 0xFB01990C 1 MLA r9,r1,r12,r9 false
+Instruction 1530 S:0xC003F980 0xEA4F4408 1 LSL r4,r8,#16 false
+Instruction 1531 S:0xC003F984 0xFB00770C 1 MLA r7,r0,r12,r7 false
+Instruction 1532 S:0xC003F988 0x0C32 1 LSRS r2,r6,#16 false
+Instruction 1533 S:0xC003F98A 0xEA4F4509 1 LSL r5,r9,#16 false
+Instruction 1534 S:0xC003F98E 0xEA454518 1 ORR r5,r5,r8,LSR #16 false
+Instruction 1535 S:0xC003F992 0xEA424207 1 ORR r2,r2,r7,LSL #16 false
+Instruction 1536 S:0xC003F996 0x0C3B 1 LSRS r3,r7,#16 false
+Instruction 1537 S:0xC003F998 0x1912 1 ADDS r2,r2,r4 false
+Instruction 1538 S:0xC003F99A 0xEB430305 1 ADC r3,r3,r5 false
+Instruction 1539 S:0xC003F99E 0x4610 0 MOV r0,r2 false
+Instruction 1540 S:0xC003F9A0 0x4619 1 MOV r1,r3 false
+Instruction 1541 S:0xC003F9A2 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 1542 S:0xC003F9A6 0x4770 3 BX lr true
+Instruction 1543 S:0xC00426F8 0x9B05 2 LDR r3,[sp,#0x14] false
+Instruction 1544 S:0xC00426FA 0xF8DDC010 1 LDR r12,[sp,#0x10] false
+Instruction 1545 S:0xC00426FE 0x2800 0 CMP r0,#0 false
+Instruction 1546 S:0xC0042700 0xF1710E00 6 SBCS lr,r1,#0 false
+Instruction 1547 S:0xC0042704 0xF2C081CC 0 BLT.W {pc}+0x39c ; 0xc0042aa0 true fail
+Instruction 1548 S:0xC0042708 0xEA4F2A90 1 LSR r10,r0,#10 false
+Instruction 1549 S:0xC004270C 0xEA4F2B91 1 LSR r11,r1,#10 false
+Instruction 1550 S:0xC0042710 0xEA4A5A81 1 ORR r10,r10,r1,LSL #22 false
+Instruction 1551 S:0xC0042714 0xEA5A000B 1 ORRS r0,r10,r11 false
+Instruction 1552 S:0xC0042718 0xF00080D4 0 BEQ.W {pc}+0x1ac ; 0xc00428c4 true fail
+Instruction 1553 S:0xC004271C 0xF64B7140 1 MOV r1,#0xbf40 false
+Instruction 1554 S:0xC0042720 0xE9C34500 14 STRD r4,r5,[r3,#0] false
+Instruction 1555 S:0xC0042724 0xF2CC0164 1 MOVT r1,#0xc064 false
+Instruction 1556 S:0xC0042728 0x680A 3 LDR r2,[r1,#0] false
+Instruction 1557 S:0xC004272A 0x2A00 2 CMP r2,#0 false
+Instruction 1558 S:0xC004272C 0xF00081BB 0 BEQ.W {pc}+0x37a ; 0xc0042aa6 true fail
+Instruction 1559 S:0xC0042730 0x9A0A 22 LDR r2,[sp,#0x28] false
+Instruction 1560 S:0xC0042732 0x2400 0 MOVS r4,#0 false
+Instruction 1561 S:0xC0042734 0x940B 1 STR r4,[sp,#0x2c] false
+Instruction 1562 S:0xC0042736 0xEB011302 2 ADD r3,r1,r2,LSL #4 false
+Instruction 1563 S:0xC004273A 0xF8D33098 14 LDR r3,[r3,#0x98] false
+Instruction 1564 S:0xC004273E 0x9313 1 STR r3,[sp,#0x4c] false
+Instruction 1565 S:0xC0042740 0x930A 1 STR r3,[sp,#0x28] false
+Instruction 1566 S:0xC0042742 0xF8D7E134 1 LDR lr,[r7,#0x134] false
+Instruction 1567 S:0xC0042746 0xF24032FF 0 MOV r2,#0x3ff false
+Instruction 1568 S:0xC004274A 0x9C0C 2 LDR r4,[sp,#0x30] false
+Instruction 1569 S:0xC004274C 0x2300 0 MOVS r3,#0 false
+Instruction 1570 S:0xC004274E 0x1B39 2 SUBS r1,r7,r4 false
+Instruction 1571 S:0xC0042750 0xEA4F548E 1 LSL r4,lr,#22 false
+Instruction 1572 S:0xC0042754 0x424D 1 RSBS r5,r1,#0 false
+Instruction 1573 S:0xC0042756 0xEA4F5494 1 LSR r4,r4,#22 false
+Instruction 1574 S:0xC004275A 0x414D 1 ADCS r5,r5,r1 false
+Instruction 1575 S:0xC004275C 0xEB1A0004 1 ADDS r0,r10,r4 false
+Instruction 1576 S:0xC0042760 0xF14B0100 1 ADC r1,r11,#0 false
+Instruction 1577 S:0xC0042764 0x428B 1 CMP r3,r1 false
+Instruction 1578 S:0xC0042766 0xBF08 0 IT EQ false
+Instruction 1579 S:0xC0042768 0x4282 1 CMP r2,r0 false
+Instruction 1580 S:0xC004276A 0xBF28 0 IT CS false
+Instruction 1581 S:0xC004276C 0x2400 1 MOVS r4,#0 false fail
+Instruction 1582 S:0xC004276E 0xD279 0 BCS {pc}+0xf6 ; 0xc0042864 true fail
+Instruction 1583 S:0xC0042770 0x9B13 1 LDR r3,[sp,#0x4c] false
+Instruction 1584 S:0xC0042772 0xF5C46480 1 RSB r4,r4,#0x400 false
+Instruction 1585 S:0xC0042776 0xF8D70130 1 LDR r0,[r7,#0x130] false
+Instruction 1586 S:0xC004277A 0xFB04F203 1 MUL r2,r4,r3 false
+Instruction 1587 S:0xC004277E 0x9B12 1 LDR r3,[sp,#0x48] false
+Instruction 1588 S:0xC0042780 0x0A92 6 LSRS r2,r2,#10 false
+Instruction 1589 S:0xC0042782 0x2B00 0 CMP r3,#0 false
+Instruction 1590 S:0xC0042784 0xF04081AD 1 BNE.W {pc}+0x35e ; 0xc0042ae2 true
+Instruction 1591 S:0xC0042AE2 0x1810 19 ADDS r0,r2,r0 false
+Instruction 1592 S:0xC0042AE4 0x900C 1 STR r0,[sp,#0x30] false
+Instruction 1593 S:0xC0042AE6 0xF8C70130 1 STR r0,[r7,#0x130] false
+Instruction 1594 S:0xC0042AEA 0xE64E 0 B {pc}-0x360 ; 0xc004278a true
+Instruction 1595 S:0xC004278A 0xB125 2 CBZ r5,{pc}+0xc ; 0xc0042796 true fail
+Instruction 1596 S:0xC004278C 0xF8D73160 1 LDR r3,[r7,#0x160] false
+Instruction 1597 S:0xC0042790 0x189B 2 ADDS r3,r3,r2 false
+Instruction 1598 S:0xC0042792 0xF8C73160 1 STR r3,[r7,#0x160] false
+Instruction 1599 S:0xC0042796 0xEBBA0204 1 SUBS r2,r10,r4 false
+Instruction 1600 S:0xC004279A 0xEB6B73E4 1 SBC r3,r11,r4,ASR #31 false
+Instruction 1601 S:0xC004279E 0x2100 0 MOVS r1,#0 false
+Instruction 1602 S:0xC00427A0 0xEA030B01 11 AND r11,r3,r1 false
+Instruction 1603 S:0xC00427A4 0x4474 1 ADD r4,r4,lr false
+Instruction 1604 S:0xC00427A6 0x0A91 1 LSRS r1,r2,#10 false
+Instruction 1605 S:0xC00427A8 0xF24030FF 0 MOV r0,#0x3ff false
+Instruction 1606 S:0xC00427AC 0xEA4F2E93 1 LSR lr,r3,#10 false
+Instruction 1607 S:0xC00427B0 0x9418 1 STR r4,[sp,#0x60] false
+Instruction 1608 S:0xC00427B2 0xF8C74134 1 STR r4,[r7,#0x134] false
+Instruction 1609 S:0xC00427B6 0xEA415483 1 ORR r4,r1,r3,LSL #22 false
+Instruction 1610 S:0xC00427BA 0xF8CDE03C 1 STR lr,[sp,#0x3c] false
+Instruction 1611 S:0xC00427BE 0xEA020A00 15 AND r10,r2,r0 false
+Instruction 1612 S:0xC00427C2 0x940E 1 STR r4,[sp,#0x38] false
+Instruction 1613 S:0xC00427C4 0x2001 1 MOVS r0,#1 false
+Instruction 1614 S:0xC00427C6 0xE9DD230E 1 LDRD r2,r3,[sp,#0x38] false
+Instruction 1615 S:0xC00427CA 0x2100 1 MOVS r1,#0 false
+Instruction 1616 S:0xC00427CC 0x1812 1 ADDS r2,r2,r0 false
+Instruction 1617 S:0xC00427CE 0xF44F60FC 0 MOV r0,#0x7e0 false
+Instruction 1618 S:0xC00427D2 0xEB430301 1 ADC r3,r3,r1 false
+Instruction 1619 S:0xC00427D6 0x2100 0 MOVS r1,#0 false
+Instruction 1620 S:0xC00427D8 0x4299 1 CMP r1,r3 false
+Instruction 1621 S:0xC00427DA 0xBF08 0 IT EQ false
+Instruction 1622 S:0xC00427DC 0x4290 1 CMP r0,r2 false
+Instruction 1623 S:0xC00427DE 0xF0C08390 15 BCC.W {pc}+0x724 ; 0xc0042f02 true fail
+Instruction 1624 S:0xC00427E2 0x2A1F 1 CMP r2,#0x1f false
+Instruction 1625 S:0xC00427E4 0x4614 1 MOV r4,r2 false
+Instruction 1626 S:0xC00427E6 0xF20083D8 0 BHI.W {pc}+0x7b4 ; 0xc0042f9a true fail
+Instruction 1627 S:0xC00427EA 0xF24830C8 66 MOV r0,#0x83c8 false
+Instruction 1628 S:0xC00427EE 0x990C 1 LDR r1,[sp,#0x30] false
+Instruction 1629 S:0xC00427F0 0xF2CC003E 1 MOVT r0,#0xc03e false
+Instruction 1630 S:0xC00427F4 0xF8DFE564 14 LDR lr,[pc,#1380] ; [0xC0042D5C] false
+Instruction 1631 S:0xC00427F8 0xF8500022 3 LDR r0,[r0,r2,LSL #2] false
+Instruction 1632 S:0xC00427FC 0xFBA02301 3 UMULL r2,r3,r0,r1 false
+Instruction 1633 S:0xC0042800 0x9009 1 STR r0,[sp,#0x24] false
+Instruction 1634 S:0xC0042802 0x4601 0 MOV r1,r0 false
+Instruction 1635 S:0xC0042804 0x9818 1 LDR r0,[sp,#0x60] false
+Instruction 1636 S:0xC0042806 0xFBA10100 3 UMULL r0,r1,r1,r0 false
+Instruction 1637 S:0xC004280A 0x930C 1 STR r3,[sp,#0x30] false
+Instruction 1638 S:0xC004280C 0xF8C73130 1 STR r3,[r7,#0x130] false
+Instruction 1639 S:0xC0042810 0xF8D73160 1 LDR r3,[r7,#0x160] false
+Instruction 1640 S:0xC0042814 0xE9CD0118 1 STRD r0,r1,[sp,#0x60] false
+Instruction 1641 S:0xC0042818 0xF8C71134 1 STR r1,[r7,#0x134] false
+Instruction 1642 S:0xC004281C 0xF85E2024 1 LDR r2,[lr,r4,LSL #2] false
+Instruction 1643 S:0xC0042820 0xFBA22303 10 UMULL r2,r3,r2,r3 false
+Instruction 1644 S:0xC0042824 0xF8C73160 1 STR r3,[r7,#0x160] false
+Instruction 1645 S:0xC0042828 0xE9DD010E 1 LDRD r0,r1,[sp,#0x38] false
+Instruction 1646 S:0xC004282C 0xF8CDC010 1 STR r12,[sp,#0x10] false
+Instruction 1647 S:0xC0042830 0xF7FEFF4E 1 BL {pc}-0x1160 ; 0xc00416d0 true
+Instruction 1648 S:0xC00416D0 0xE92D03F0 2 PUSH {r4-r9} false
+Instruction 1649 S:0xC00416D4 0xB500 5 PUSH {lr} false
+Instruction 1650 S:0xC00416D6 0xF85DEB04 2 POP {lr} false
+Instruction 1651 S:0xC00416DA 0x2620 0 MOVS r6,#0x20 false
+Instruction 1652 S:0xC00416DC 0x2700 1 MOVS r7,#0 false
+Instruction 1653 S:0xC00416DE 0x428F 1 CMP r7,r1 false
+Instruction 1654 S:0xC00416E0 0xBF08 7 IT EQ false
+Instruction 1655 S:0xC00416E2 0x4286 1 CMP r6,r0 false
+Instruction 1656 S:0xC00416E4 0xD307 0 BCC {pc}+0x12 ; 0xc00416f6 true fail
+Instruction 1657 S:0xC00416E6 0x4B31 3 LDR r3,[pc,#196] ; [0xC00417AC] false
+Instruction 1658 S:0xC00416E8 0xEB030080 2 ADD r0,r3,r0,LSL #2 false
+Instruction 1659 S:0xC00416EC 0xF8D000FC 16 LDR r0,[r0,#0xfc] false
+Instruction 1660 S:0xC00416F0 0xE8BD03F0 3 POP {r4-r9} false
+Instruction 1661 S:0xC00416F4 0x4770 3 BX lr true
+Instruction 1662 S:0xC0042834 0x9A13 2 LDR r2,[sp,#0x4c] false
+Instruction 1663 S:0xC0042836 0xF8DDC010 1 LDR r12,[sp,#0x10] false
+Instruction 1664 S:0xC004283A 0xFB02F300 2 MUL r3,r2,r0 false
+Instruction 1665 S:0xC004283E 0x0A9A 3 LSRS r2,r3,#10 false
+Instruction 1666 S:0xC0042840 0x9B12 1 LDR r3,[sp,#0x48] false
+Instruction 1667 S:0xC0042842 0xB11B 2 CBZ r3,{pc}+0xa ; 0xc004284c true fail
+Instruction 1668 S:0xC0042844 0x9C0C 8 LDR r4,[sp,#0x30] false
+Instruction 1669 S:0xC0042846 0x1913 2 ADDS r3,r2,r4 false
+Instruction 1670 S:0xC0042848 0xF8C73130 1 STR r3,[r7,#0x130] false
+Instruction 1671 S:0xC004284C 0xB125 1 CBZ r5,{pc}+0xc ; 0xc0042858 true fail
+Instruction 1672 S:0xC004284E 0xF8D73160 9 LDR r3,[r7,#0x160] false
+Instruction 1673 S:0xC0042852 0x189B 2 ADDS r3,r3,r2 false
+Instruction 1674 S:0xC0042854 0xF8C73160 1 STR r3,[r7,#0x160] false
+Instruction 1675 S:0xC0042858 0xF8D7E134 1 LDR lr,[r7,#0x134] false
+Instruction 1676 S:0xC004285C 0x2401 0 MOVS r4,#1 false
+Instruction 1677 S:0xC004285E 0x4486 2 ADD lr,lr,r0 false
+Instruction 1678 S:0xC0042860 0xF8C7E134 1 STR lr,[r7,#0x134] false
+Instruction 1679 S:0xC0042864 0x990B 1 LDR r1,[sp,#0x2c] false
+Instruction 1680 S:0xC0042866 0x9A0A 1 LDR r2,[sp,#0x28] false
+Instruction 1681 S:0xC0042868 0xFB0AF001 2 MUL r0,r10,r1 false
+Instruction 1682 S:0xC004286C 0xFB02000B 1 MLA r0,r2,r11,r0 false
+Instruction 1683 S:0xC0042870 0xFBAA2302 1 UMULL r2,r3,r10,r2 false
+Instruction 1684 S:0xC0042874 0x18C3 2 ADDS r3,r0,r3 false
+Instruction 1685 S:0xC0042876 0x0A92 1 LSRS r2,r2,#10 false
+Instruction 1686 S:0xC0042878 0xEA425283 1 ORR r2,r2,r3,LSL #22 false
+Instruction 1687 S:0xC004287C 0x9B12 1 LDR r3,[sp,#0x48] false
+Instruction 1688 S:0xC004287E 0xB123 2 CBZ r3,{pc}+0xc ; 0xc004288a true fail
+Instruction 1689 S:0xC0042880 0xF8D73130 1 LDR r3,[r7,#0x130] false
+Instruction 1690 S:0xC0042884 0x189B 2 ADDS r3,r3,r2 false
+Instruction 1691 S:0xC0042886 0xF8C73130 1 STR r3,[r7,#0x130] false
+Instruction 1692 S:0xC004288A 0xB125 1 CBZ r5,{pc}+0xc ; 0xc0042896 true fail
+Instruction 1693 S:0xC004288C 0xF8D73160 1 LDR r3,[r7,#0x160] false
+Instruction 1694 S:0xC0042890 0x189A 2 ADDS r2,r3,r2 false
+Instruction 1695 S:0xC0042892 0xF8C72160 1 STR r2,[r7,#0x160] false
+Instruction 1696 S:0xC0042896 0xEB0E010A 1 ADD r1,lr,r10 false
+Instruction 1697 S:0xC004289A 0xF8C71134 1 STR r1,[r7,#0x134] false
+Instruction 1698 S:0xC004289E 0xB18C 1 CBZ r4,{pc}+0x26 ; 0xc00428c4 true fail
+Instruction 1699 S:0xC00428A0 0x4638 24 MOV r0,r7 false
+Instruction 1700 S:0xC00428A2 0xF8CDC010 1 STR r12,[sp,#0x10] false
+Instruction 1701 S:0xC00428A6 0xF7FDFD11 1 BL {pc}-0x25da ; 0xc00402cc true
+Instruction 1702 S:0xC00402CC 0xE92D4FF8 17 PUSH {r3-r11,lr} false
+Instruction 1703 S:0xC00402D0 0xB500 7 PUSH {lr} false
+Instruction 1704 S:0xC00402D2 0xF85DEB04 2 POP {lr} false
+Instruction 1705 S:0xC00402D6 0x4606 0 MOV r6,r0 false
+Instruction 1706 S:0xC00402D8 0xF8D05128 1 LDR r5,[r0,#0x128] false
+Instruction 1707 S:0xC00402DC 0xF8D0A148 2 LDR r10,[r0,#0x148] false
+Instruction 1708 S:0xC00402E0 0x2D00 6 CMP r5,#0 false
+Instruction 1709 S:0xC00402E2 0xD067 0 BEQ {pc}+0xd2 ; 0xc00403b4 true
+Instruction 1710 S:0xC00403B4 0xF8D04134 22 LDR r4,[r0,#0x134] false
+Instruction 1711 S:0xC00403B8 0xF1A00538 1 SUB r5,r0,#0x38 false
+Instruction 1712 S:0xC00403BC 0xF8D08130 1 LDR r8,[r0,#0x130] false
+Instruction 1713 S:0xC00403C0 0x6800 17 LDR r0,[r0,#0] false
+Instruction 1714 S:0xC00403C2 0x3401 0 ADDS r4,#1 false
+Instruction 1715 S:0xC00403C4 0x4621 1 MOV r1,r4 false
+Instruction 1716 S:0xC00403C6 0xFB00F008 2 MUL r0,r0,r8 false
+Instruction 1717 S:0xC00403CA 0xF211F883 1 BL {pc}+0x21110a ; 0xc02514d4 true
+Cycle Count 143 Tracing disabled
+Info Tracing enabled
+Instruction 1718 S:0xC00403CE 0x4B27 1 LDR r3,[pc,#156] ; [0xC004046C] = 0xC0635FF4 false
+Instruction 1719 S:0xC00403D0 0x685A 15 LDR r2,[r3,#4] false
+Instruction 1720 S:0xC00403D2 0x4607 0 MOV r7,r0 false
+Instruction 1721 S:0xC00403D4 0xF8C60148 3 STR r0,[r6,#0x148] false
+Instruction 1722 S:0xC00403D8 0xB98A 1 CBNZ r2,{pc}+0x26 ; 0xc00403fe true fail
+Instruction 1723 S:0xC00403DA 0xEA4F2088 1 LSL r0,r8,#10 false
+Instruction 1724 S:0xC00403DE 0x4621 0 MOV r1,r4 false
+Instruction 1725 S:0xC00403E0 0xF211F878 1 BL {pc}+0x2110f4 ; 0xc02514d4 true
+Cycle Count 51 Tracing disabled
+Info Tracing enabled
+Instruction 1726 S:0xC00403E4 0x4607 1 MOV r7,r0 false
+Instruction 1727 S:0xC00403E6 0xF8C6014C 1 STR r0,[r6,#0x14c] false
+Instruction 1728 S:0xC00403EA 0x4B21 3 LDR r3,[pc,#132] ; [0xC0040470] = 0xC0635FE0 false
+Instruction 1729 S:0xC00403EC 0x685A 3 LDR r2,[r3,#4] false
+Instruction 1730 S:0xC00403EE 0x2A00 2 CMP r2,#0 false
+Instruction 1731 S:0xC00403F0 0xD12E 0 BNE {pc}+0x60 ; 0xc0040450 true fail
+Instruction 1732 S:0xC00403F2 0xF8D60148 1 LDR r0,[r6,#0x148] false
+Instruction 1733 S:0xC00403F6 0xEBCA0000 2 RSB r0,r10,r0 false
+Instruction 1734 S:0xC00403FA 0xE8BD8FF8 1 POP {r3-r11,pc} true
+Instruction 1735 S:0xC00428AA 0x69FB 13 LDR r3,[r7,#0x1c] false
+Instruction 1736 S:0xC00428AC 0xF8DDC010 1 LDR r12,[sp,#0x10] false
+Instruction 1737 S:0xC00428B0 0x2B00 1 CMP r3,#0 false
+Instruction 1738 S:0xC00428B2 0xF0008106 0 BEQ.W {pc}+0x210 ; 0xc0042ac2 true fail
+Instruction 1739 S:0xC00428B6 0xE9DC2312 12 LDRD r2,r3,[r12,#0x48] false
+Instruction 1740 S:0xC00428BA 0x1812 2 ADDS r2,r2,r0 false
+Instruction 1741 S:0xC00428BC 0xEB4373E0 1 ADC r3,r3,r0,ASR #31 false
+Instruction 1742 S:0xC00428C0 0xE9CC2312 1 STRD r2,r3,[r12,#0x48] false
+Instruction 1743 S:0xC00428C4 0xF0880101 1 EOR r1,r8,#1 false
+Instruction 1744 S:0xC00428C8 0x4630 0 MOV r0,r6 false
+Instruction 1745 S:0xC00428CA 0xF7FDF967 1 BL {pc}-0x2d2e ; 0xc003fb9c true
+Instruction 1746 S:0xC003FB9C 0xE92D0FF0 1 PUSH {r4-r11} false
+Instruction 1747 S:0xC003FBA0 0xB500 9 PUSH {lr} false
+Instruction 1748 S:0xC003FBA2 0xF85DEB04 2 POP {lr} false
+Instruction 1749 S:0xC003FBA6 0xF8D06084 1 LDR r6,[r0,#0x84] false
+Instruction 1750 S:0xC003FBAA 0xE9D0451A 2 LDRD r4,r5,[r0,#0x68] false
+Instruction 1751 S:0xC003FBAE 0xF8D67480 1 LDR r7,[r6,#0x480] false
+Instruction 1752 S:0xC003FBB2 0xF8D66484 1 LDR r6,[r6,#0x484] false
+Instruction 1753 S:0xC003FBB6 0x0D3A 2 LSRS r2,r7,#20 false
+Instruction 1754 S:0xC003FBB8 0xEA423206 1 ORR r2,r2,r6,LSL #12 false
+Instruction 1755 S:0xC003FBBC 0x0D33 1 LSRS r3,r6,#20 false
+Instruction 1756 S:0xC003FBBE 0x1B14 1 SUBS r4,r2,r4 false
+Instruction 1757 S:0xC003FBC0 0xEB630505 5 SBC r5,r3,r5 false
+Instruction 1758 S:0xC003FBC4 0xEA540605 1 ORRS r6,r4,r5 false
+Instruction 1759 S:0xC003FBC8 0xBF14 1 ITE NE false
+Instruction 1760 S:0xC003FBCA 0x2600 1 MOVS r6,#0 false
+Instruction 1761 S:0xC003FBCC 0x2601 0 MOVS r6,#1 false fail
+Instruction 1762 S:0xC003FBCE 0x2900 1 CMP r1,#0 false
+Instruction 1763 S:0xC003FBD0 0xBF14 0 ITE NE false
+Instruction 1764 S:0xC003FBD2 0x2600 1 MOVS r6,#0 false fail
+Instruction 1765 S:0xC003FBD4 0xF0060601 1 AND r6,r6,#1 false
+Instruction 1766 S:0xC003FBD8 0x2E00 1 CMP r6,#0 false
+Instruction 1767 S:0xC003FBDA 0xD167 0 BNE {pc}+0xd2 ; 0xc003fcac true fail
+Instruction 1768 S:0xC003FBDC 0xF1000C60 1 ADD r12,r0,#0x60 false
+Instruction 1769 S:0xC003FBE0 0xE8DC677F 15 LDREXD r6,r7,[r12] false
+Instruction 1770 S:0xC003FBE4 0xEA560807 2 ORRS r8,r6,r7 false
+Instruction 1771 S:0xC003FBE8 0xD163 1 BNE {pc}+0xca ; 0xc003fcb2 true fail
+Instruction 1772 S:0xC003FBEA 0xE9D06714 1 LDRD r6,r7,[r0,#0x50] false
+Instruction 1773 S:0xC003FBEE 0xEA540C05 1 ORRS r12,r4,r5 false
+Instruction 1774 S:0xC003FBF2 0xD027 0 BEQ {pc}+0x52 ; 0xc003fc44 true fail
+Instruction 1775 S:0xC003FBF4 0xF44F68FC 1 MOV r8,#0x7e0 false
+Instruction 1776 S:0xC003FBF8 0xF04F0900 0 MOV r9,#0 false
+Instruction 1777 S:0xC003FBFC 0x45A9 1 CMP r9,r5 false
+Instruction 1778 S:0xC003FBFE 0xBF08 0 IT EQ false
+Instruction 1779 S:0xC003FC00 0x45A0 9 CMP r8,r4 false
+Instruction 1780 S:0xC003FC02 0xF0C0808F 0 BCC.W {pc}+0x122 ; 0xc003fd24 true fail
+Instruction 1781 S:0xC003FC06 0x2C1F 1 CMP r4,#0x1f false
+Instruction 1782 S:0xC003FC08 0x46A4 0 MOV r12,r4 false
+Instruction 1783 S:0xC003FC0A 0xD871 1 BHI {pc}+0xe6 ; 0xc003fcf0 true fail
+Instruction 1784 S:0xC003FC0C 0xF8DF8120 14 LDR r8,[pc,#288] ; [0xC003FD30] = 0xC03E83C8 false
+Instruction 1785 S:0xC003FC10 0xF04F0B00 1 MOV r11,#0 false
+Instruction 1786 S:0xC003FC14 0xF858C02C 2 LDR r12,[r8,r12,LSL #2] false
+Instruction 1787 S:0xC003FC18 0xFBAC8906 3 UMULL r8,r9,r12,r6 false
+Instruction 1788 S:0xC003FC1C 0xFB0C9A07 2 MLA r10,r12,r7,r9 false
+Instruction 1789 S:0xC003FC20 0xE9C0AB14 1 STRD r10,r11,[r0,#0x50] false
+Instruction 1790 S:0xC003FC24 0xF1000C58 1 ADD r12,r0,#0x58 false
+Instruction 1791 S:0xC003FC28 0xE8DC677F 8 LDREXD r6,r7,[r12] false
+Instruction 1792 S:0xC003FC2C 0x1936 2 ADDS r6,r6,r4 false
+Instruction 1793 S:0xC003FC2E 0xEB470705 1 ADC r7,r7,r5 false
+Instruction 1794 S:0xC003FC32 0xE8CC6778 7 STREXD r8,r6,r7,[r12] false
+Instruction 1795 S:0xC003FC36 0xF0980F00 2 TEQ r8,#0 false
+Instruction 1796 S:0xC003FC3A 0xD1F5 0 BNE {pc}-0x12 ; 0xc003fc28 true fail
+Instruction 1797 S:0xC003FC3C 0x4656 1 MOV r6,r10 false
+Instruction 1798 S:0xC003FC3E 0x465F 0 MOV r7,r11 false
+Instruction 1799 S:0xC003FC40 0xE9C0231A 1 STRD r2,r3,[r0,#0x68] false
+Instruction 1800 S:0xC003FC44 0xE9D0451E 1 LDRD r4,r5,[r0,#0x78] false
+Instruction 1801 S:0xC003FC48 0xE9D02312 1 LDRD r2,r3,[r0,#0x48] false
+Instruction 1802 S:0xC003FC4C 0xF8D0C094 1 LDR r12,[r0,#0x94] false
+Instruction 1803 S:0xC003FC50 0x1B12 1 SUBS r2,r2,r4 false
+Instruction 1804 S:0xC003FC52 0xEB630305 1 SBC r3,r3,r5 false
+Instruction 1805 S:0xC003FC56 0x1992 1 ADDS r2,r2,r6 false
+Instruction 1806 S:0xC003FC58 0xEB430307 1 ADC r3,r3,r7 false
+Instruction 1807 S:0xC003FC5C 0xB999 1 CBNZ r1,{pc}+0x2a ; 0xc003fc86 true fail
+Instruction 1808 S:0xC003FC5E 0x17DE 1 ASRS r6,r3,#31 false
+Instruction 1809 S:0xC003FC60 0xEA4F0AD4 2 LSR r10,r4,#3 false
+Instruction 1810 S:0xC003FC64 0x4637 0 MOV r7,r6 false
+Instruction 1811 S:0xC003FC66 0xEA860802 1 EOR r8,r6,r2 false
+Instruction 1812 S:0xC003FC6A 0xEA860903 1 EOR r9,r6,r3 false
+Instruction 1813 S:0xC003FC6E 0xEA4A7A45 1 ORR r10,r10,r5,LSL #29 false
+Instruction 1814 S:0xC003FC72 0xEA4F0BD5 1 LSR r11,r5,#3 false
+Instruction 1815 S:0xC003FC76 0xEBB80806 1 SUBS r8,r8,r6 false
+Instruction 1816 S:0xC003FC7A 0xEB690907 1 SBC r9,r9,r7 false
+Instruction 1817 S:0xC003FC7E 0x45CB 1 CMP r11,r9 false
+Instruction 1818 S:0xC003FC80 0xBF08 13 IT EQ false
+Instruction 1819 S:0xC003FC82 0x45C2 1 CMP r10,r8 false
+Instruction 1820 S:0xC003FC84 0xD212 0 BCS {pc}+0x28 ; 0xc003fcac true fail
+Instruction 1821 S:0xC003FC86 0xF10C0130 1 ADD r1,r12,#0x30 false
+Instruction 1822 S:0xC003FC8A 0xE8D1457F 16 LDREXD r4,r5,[r1] false
+Instruction 1823 S:0xC003FC8E 0x18A4 2 ADDS r4,r4,r2 false
+Instruction 1824 S:0xC003FC90 0xEB450503 1 ADC r5,r5,r3 false
+Instruction 1825 S:0xC003FC94 0xE8C14576 20 STREXD r6,r4,r5,[r1] false
+Instruction 1826 S:0xC003FC98 0xF0960F00 2 TEQ r6,#0 false
+Instruction 1827 S:0xC003FC9C 0xD1F5 0 BNE {pc}-0x12 ; 0xc003fc8a true fail
+Instruction 1828 S:0xC003FC9E 0xE9D0451E 1 LDRD r4,r5,[r0,#0x78] false
+Instruction 1829 S:0xC003FCA2 0x18A4 2 ADDS r4,r4,r2 false
+Instruction 1830 S:0xC003FCA4 0xEB450503 1 ADC r5,r5,r3 false
+Instruction 1831 S:0xC003FCA8 0xE9C0451E 1 STRD r4,r5,[r0,#0x78] false
+Instruction 1832 S:0xC003FCAC 0xE8BD0FF0 1 POP {r4-r11} false
+Instruction 1833 S:0xC003FCB0 0x4770 4 BX lr true
+Instruction 1834 S:0xC00428CE 0xF8D71148 1 LDR r1,[r7,#0x148] false
+Instruction 1835 S:0xC00428D2 0xE9D62312 1 LDRD r2,r3,[r6,#0x48] false
+Instruction 1836 S:0xC00428D6 0x1A52 2 SUBS r2,r2,r1 false
+Instruction 1837 S:0xC00428D8 0xF1630300 1 SBC r3,r3,#0 false
+Instruction 1838 S:0xC00428DC 0xE9C62312 1 STRD r2,r3,[r6,#0x48] false
+Instruction 1839 S:0xC00428E0 0xF1B80F00 1 CMP r8,#0 false
+Instruction 1840 S:0xC00428E4 0xD010 0 BEQ {pc}+0x24 ; 0xc0042908 true fail
+Instruction 1841 S:0xC00428E6 0xE9D62314 1 LDRD r2,r3,[r6,#0x50] false
+Instruction 1842 S:0xC00428EA 0xF1060058 1 ADD r0,r6,#0x58 false
+Instruction 1843 S:0xC00428EE 0xF8D71148 1 LDR r1,[r7,#0x148] false
+Instruction 1844 S:0xC00428F2 0x1852 2 ADDS r2,r2,r1 false
+Instruction 1845 S:0xC00428F4 0xF1430300 1 ADC r3,r3,#0 false
+Instruction 1846 S:0xC00428F8 0xE9C62314 1 STRD r2,r3,[r6,#0x50] false
+Instruction 1847 S:0xC00428FC 0xE8D0237F 9 LDREXD r2,r3,[r0] false
+Instruction 1848 S:0xC0042900 0xF8C72140 4 STR r2,[r7,#0x140] false
+Instruction 1849 S:0xC0042904 0xF8C73144 1 STR r3,[r7,#0x144] false
+Instruction 1850 S:0xC0042908 0x6B33 1 LDR r3,[r6,#0x30] false
+Instruction 1851 S:0xC004290A 0x429F 2 CMP r7,r3 false
+Instruction 1852 S:0xC004290C 0xD003 0 BEQ {pc}+0xa ; 0xc0042916 true
+Instruction 1853 S:0xC0042916 0xF1B80F00 13 CMP r8,#0 false
+Instruction 1854 S:0xC004291A 0xD004 0 BEQ {pc}+0xc ; 0xc0042926 true fail
+Instruction 1855 S:0xC004291C 0xF8D73128 1 LDR r3,[r7,#0x128] false
+Instruction 1856 S:0xC0042920 0x2B00 15 CMP r3,#0 false
+Instruction 1857 S:0xC0042922 0xF00080E3 0 BEQ.W {pc}+0x1ca ; 0xc0042aec true
+Instruction 1858 S:0xC0042AEC 0xF8573C38 22 LDR r3,[r7,#-0x38] false
+Instruction 1859 S:0xC0042AF0 0x07DA 3 LSLS r2,r3,#31 false
+Instruction 1860 S:0xC0042AF2 0xD507 0 BPL {pc}+0x12 ; 0xc0042b04 true fail
+Instruction 1861 S:0xC0042AF4 0xF8D63084 1 LDR r3,[r6,#0x84] false
+Instruction 1862 S:0xC0042AF8 0xF503638F 2 ADD r3,r3,#0x478 false
+Instruction 1863 S:0xC0042AFC 0xE9D32300 3 LDRD r2,r3,[r3,#0] false
+Instruction 1864 S:0xC0042B00 0xE9C7231E 9 STRD r2,r3,[r7,#0x78] false
+Instruction 1865 S:0xC0042B04 0xF8573C38 1 LDR r3,[r7,#-0x38] false
+Instruction 1866 S:0xC0042B08 0x079B 3 LSLS r3,r3,#30 false
+Instruction 1867 S:0xC0042B0A 0xF57FAF0C 0 BPL {pc}-0x1e4 ; 0xc0042926 true
+Instruction 1868 S:0xC0042926 0x4630 18 MOV r0,r6 false
+Instruction 1869 S:0xC0042928 0x4639 1 MOV r1,r7 false
+Instruction 1870 S:0xC004292A 0xF7FEFD03 0 BL {pc}-0x15f6 ; 0xc0041334 true
+Instruction 1871 S:0xC0041334 0xB430 3 PUSH {r4,r5} false
+Instruction 1872 S:0xC0041336 0xB500 1 PUSH {lr} false
+Instruction 1873 S:0xC0041338 0xF85DEB04 2 POP {lr} false
+Instruction 1874 S:0xC004133C 0x6B83 1 LDR r3,[r0,#0x38] false
+Instruction 1875 S:0xC004133E 0x428B 2 CMP r3,r1 false
+Instruction 1876 S:0xC0041340 0xD038 0 BEQ {pc}+0x74 ; 0xc00413b4 true fail
+Instruction 1877 S:0xC0041342 0x6B43 16 LDR r3,[r0,#0x34] false
+Instruction 1878 S:0xC0041344 0x428B 2 CMP r3,r1 false
+Instruction 1879 S:0xC0041346 0xD01D 1 BEQ {pc}+0x3e ; 0xc0041384 true fail
+Instruction 1880 S:0xC0041348 0x6BC3 1 LDR r3,[r0,#0x3c] false
+Instruction 1881 S:0xC004134A 0x428B 2 CMP r3,r1 false
+Instruction 1882 S:0xC004134C 0xD001 0 BEQ {pc}+6 ; 0xc0041352 true fail
+Instruction 1883 S:0xC004134E 0xBC30 1 POP {r4,r5} false
+Instruction 1884 S:0xC0041350 0x4770 1 BX lr true
+Instruction 1885 S:0xC004292E 0x6B33 1 LDR r3,[r6,#0x30] false
+Instruction 1886 S:0xC0042930 0x429F 2 CMP r7,r3 false
+Instruction 1887 S:0xC0042932 0xD003 0 BEQ {pc}+0xa ; 0xc004293c true
+Instruction 1888 S:0xC004293C 0x2500 1 MOVS r5,#0 false
+Instruction 1889 S:0xC004293E 0x4630 0 MOV r0,r6 false
+Instruction 1890 S:0xC0042940 0x61FD 14 STR r5,[r7,#0x1c] false
+Instruction 1891 S:0xC0042942 0x4639 0 MOV r1,r7 false
+Instruction 1892 S:0xC0042944 0xF7FCFF96 1 BL {pc}-0x30d0 ; 0xc003f874 true
+Instruction 1893 S:0xC003F874 0xB430 18 PUSH {r4,r5} false
+Instruction 1894 S:0xC003F876 0xB500 1 PUSH {lr} false
+Instruction 1895 S:0xC003F878 0xF85DEB04 2 POP {lr} false
+Instruction 1896 S:0xC003F87C 0x2400 0 MOVS r4,#0 false
+Instruction 1897 S:0xC003F87E 0x680A 1 LDR r2,[r1,#0] false
+Instruction 1898 S:0xC003F880 0x6803 14 LDR r3,[r0,#0] false
+Instruction 1899 S:0xC003F882 0x6044 1 STR r4,[r0,#4] false
+Instruction 1900 S:0xC003F884 0x1A9B 1 SUBS r3,r3,r2 false
+Instruction 1901 S:0xC003F886 0x6003 1 STR r3,[r0,#0] false
+Instruction 1902 S:0xC003F888 0xF8D13120 1 LDR r3,[r1,#0x120] false
+Instruction 1903 S:0xC003F88C 0xB183 2 CBZ r3,{pc}+0x24 ; 0xc003f8b0 true
+Instruction 1904 S:0xC003F8B0 0xF8D02084 17 LDR r2,[r0,#0x84] false
+Instruction 1905 S:0xC003F8B4 0x680D 1 LDR r5,[r1,#0] false
+Instruction 1906 S:0xC003F8B6 0x6B14 2 LDR r4,[r2,#0x30] false
+Instruction 1907 S:0xC003F8B8 0x6353 1 STR r3,[r2,#0x34] false
+Instruction 1908 S:0xC003F8BA 0x1B64 1 SUBS r4,r4,r5 false
+Instruction 1909 S:0xC003F8BC 0x6314 1 STR r4,[r2,#0x30] false
+Instruction 1910 S:0xC003F8BE 0xE7E6 0 B {pc}-0x30 ; 0xc003f88e true
+Instruction 1911 S:0xC003F88E 0xF8D13128 1 LDR r3,[r1,#0x128] false
+Instruction 1912 S:0xC003F892 0xB123 2 CBZ r3,{pc}+0xc ; 0xc003f89e true
+Instruction 1913 S:0xC003F89E 0x698A 8 LDR r2,[r1,#0x18] false
+Instruction 1914 S:0xC003F8A0 0xF1010314 1 ADD r3,r1,#0x14 false
+Instruction 1915 S:0xC003F8A4 0x694C 1 LDR r4,[r1,#0x14] false
+Instruction 1916 S:0xC003F8A6 0x6062 5 STR r2,[r4,#4] false
+Instruction 1917 S:0xC003F8A8 0x6014 3 STR r4,[r2,#0] false
+Instruction 1918 S:0xC003F8AA 0x614B 1 STR r3,[r1,#0x14] false
+Instruction 1919 S:0xC003F8AC 0x618B 2 STR r3,[r1,#0x18] false
+Instruction 1920 S:0xC003F8AE 0xE7F1 0 B {pc}-0x1a ; 0xc003f894 true
+Instruction 1921 S:0xC003F894 0x6883 1 LDR r3,[r0,#8] false
+Instruction 1922 S:0xC003F896 0x3B01 2 SUBS r3,#1 false
+Instruction 1923 S:0xC003F898 0x6083 1 STR r3,[r0,#8] false
+Instruction 1924 S:0xC003F89A 0xBC30 3 POP {r4,r5} false
+Instruction 1925 S:0xC003F89C 0x4770 1 BX lr true
+Instruction 1926 S:0xC0042948 0xF1B80F00 1 CMP r8,#0 false
+Instruction 1927 S:0xC004294C 0xD108 0 BNE {pc}+0x14 ; 0xc0042960 true
+Instruction 1928 S:0xC0042960 0x4630 9 MOV r0,r6 false
+Instruction 1929 S:0xC0042962 0xF7FCFF21 0 BL {pc}-0x31ba ; 0xc003f7a8 true
+Instruction 1930 S:0xC003F7A8 0xE92D03F0 3 PUSH {r4-r9} false
+Instruction 1931 S:0xC003F7AC 0xB500 5 PUSH {lr} false
+Instruction 1932 S:0xC003F7AE 0xF85DEB04 2 POP {lr} false
+Instruction 1933 S:0xC003F7B2 0x6B03 2 LDR r3,[r0,#0x30] false
+Instruction 1934 S:0xC003F7B4 0xE9D04506 2 LDRD r4,r5,[r0,#0x18] false
+Instruction 1935 S:0xC003F7B8 0x2B00 1 CMP r3,#0 false
+Instruction 1936 S:0xC003F7BA 0xD029 0 BEQ {pc}+0x56 ; 0xc003f810 true fail
+Instruction 1937 S:0xC003F7BC 0x6AC1 1 LDR r1,[r0,#0x2c] false
+Instruction 1938 S:0xC003F7BE 0xE9D3230C 3 LDRD r2,r3,[r3,#0x30] false
+Instruction 1939 S:0xC003F7C2 0xB171 1 CBZ r1,{pc}+0x20 ; 0xc003f7e2 true fail
+Instruction 1940 S:0xC003F7C4 0xE9D1670A 2 LDRD r6,r7,[r1,#0x28] false
+Instruction 1941 S:0xC003F7C8 0x46B0 2 MOV r8,r6 false
+Instruction 1942 S:0xC003F7CA 0x46B9 1 MOV r9,r7 false
+Instruction 1943 S:0xC003F7CC 0xEBB80802 1 SUBS r8,r8,r2 false
+Instruction 1944 S:0xC003F7D0 0xEB690903 1 SBC r9,r9,r3 false
+Instruction 1945 S:0xC003F7D4 0xF1B80F00 0 CMP r8,#0 false
+Instruction 1946 S:0xC003F7D8 0xF1790100 1 SBCS r1,r9,#0 false
+Instruction 1947 S:0xC003F7DC 0xBFBC 0 ITT LT false
+Instruction 1948 S:0xC003F7DE 0x4632 1 MOV r2,r6 false fail
+Instruction 1949 S:0xC003F7E0 0x463B 0 MOV r3,r7 false fail
+Instruction 1950 S:0xC003F7E2 0x4616 1 MOV r6,r2 false
+Instruction 1951 S:0xC003F7E4 0x461F 0 MOV r7,r3 false
+Instruction 1952 S:0xC003F7E6 0x1B36 1 SUBS r6,r6,r4 false
+Instruction 1953 S:0xC003F7E8 0xEB670705 1 SBC r7,r7,r5 false
+Instruction 1954 S:0xC003F7EC 0x2E01 0 CMP r6,#1 false
+Instruction 1955 S:0xC003F7EE 0xF1770100 1 SBCS r1,r7,#0 false
+Instruction 1956 S:0xC003F7F2 0xDB0A 0 BLT {pc}+0x18 ; 0xc003f80a true
+Instruction 1957 S:0xC003F80A 0x4622 8 MOV r2,r4 false
+Instruction 1958 S:0xC003F80C 0x462B 0 MOV r3,r5 false
+Instruction 1959 S:0xC003F80E 0xE7F1 1 B {pc}-0x1a ; 0xc003f7f4 true
+Instruction 1960 S:0xC003F7F4 0xE9C02306 3 STRD r2,r3,[r0,#0x18] false
+Instruction 1961 S:0xC003F7F8 0xF3BF8F5F 1 DMB false
+Instruction 1962 S:0xC003F7FC 0xE9D02306 38 LDRD r2,r3,[r0,#0x18] false
+Instruction 1963 S:0xC003F800 0xE9C02308 3 STRD r2,r3,[r0,#0x20] false
+Instruction 1964 S:0xC003F804 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 1965 S:0xC003F808 0x4770 3 BX lr true
+Instruction 1966 S:0xC0042966 0x4630 1 MOV r0,r6 false
+Instruction 1967 S:0xC0042968 0xF7FDFC70 0 BL {pc}-0x271c ; 0xc004024c true
+Instruction 1968 S:0xC004024C 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 1969 S:0xC004024E 0xB500 4 PUSH {lr} false
+Instruction 1970 S:0xC0040250 0xF85DEB04 2 POP {lr} false
+Instruction 1971 S:0xC0040254 0xF8D01094 1 LDR r1,[r0,#0x94] false
+Instruction 1972 S:0xC0040258 0xF8D02084 2 LDR r2,[r0,#0x84] false
+Instruction 1973 S:0xC004025C 0x6A0B 3 LDR r3,[r1,#0x20] false
+Instruction 1974 S:0xC004025E 0xF8D224C0 3 LDR r2,[r2,#0x4c0] false
+Instruction 1975 S:0xC0040262 0xF8534022 15 LDR r4,[r3,r2,LSL #2] false
+Instruction 1976 S:0xC0040266 0x2C00 2 CMP r4,#0 false
+Instruction 1977 S:0xC0040268 0xD02B 0 BEQ {pc}+0x5a ; 0xc00402c2 true
+Instruction 1978 S:0xC00402C2 0xBD70 1 POP {r4-r6,pc} true
+Instruction 1979 S:0xC004296C 0x68F3 4 LDR r3,[r6,#0xc] false
+Instruction 1980 S:0xC004296E 0x6832 1 LDR r2,[r6,#0] false
+Instruction 1981 S:0xC0042970 0x3B01 1 SUBS r3,#1 false
+Instruction 1982 S:0xC0042972 0x60F3 1 STR r3,[r6,#0xc] false
+Instruction 1983 S:0xC0042974 0x2A00 0 CMP r2,#0 false
+Instruction 1984 S:0xC0042976 0xF04080D3 1 BNE.W {pc}+0x1aa ; 0xc0042b20 true
+Instruction 1985 S:0xC0042B20 0xF8DD8054 8 LDR r8,[sp,#0x54] false
+Instruction 1986 S:0xC0042B24 0xF0180F01 2 TST r8,#1 false
+Instruction 1987 S:0xC0042B28 0xD006 1 BEQ {pc}+0x10 ; 0xc0042b38 true fail
+Instruction 1988 S:0xC0042B2A 0xF8D70120 1 LDR r0,[r7,#0x120] false
+Instruction 1989 S:0xC0042B2E 0x2800 2 CMP r0,#0 false
+Instruction 1990 S:0xC0042B30 0xF43FAF2A 0 BEQ {pc}-0x1a8 ; 0xc0042988 true
+Instruction 1991 S:0xC0042988 0x9D14 1 LDR r5,[sp,#0x50] false
+Instruction 1992 S:0xC004298A 0xF5056290 2 ADD r2,r5,#0x480 false
+Instruction 1993 S:0xC004298E 0xF50569B4 1 ADD r9,r5,#0x5a0 false
+Instruction 1994 S:0xC0042992 0x686B 1 LDR r3,[r5,#4] false
+Instruction 1995 S:0xC0042994 0xF8D584C0 1 LDR r8,[r5,#0x4c0] false
+Instruction 1996 S:0xC0042998 0x3B01 1 SUBS r3,#1 false
+Instruction 1997 S:0xC004299A 0x606B 1 STR r3,[r5,#4] false
+Instruction 1998 S:0xC004299C 0xE9D24500 1 LDRD r4,r5,[r2,#0] false
+Instruction 1999 S:0xC00429A0 0xE9D90100 7 LDRD r0,r1,[r9,#0] false
+Instruction 2000 S:0xC00429A4 0x1A20 2 SUBS r0,r4,r0 false
+Instruction 2001 S:0xC00429A6 0xEB650101 1 SBC r1,r5,r1 false
+Instruction 2002 S:0xC00429AA 0xF7FCFFD7 0 BL {pc}-0x304e ; 0xc003f95c true
+Instruction 2003 S:0xC003F95C 0xE92D03F0 1 PUSH {r4-r9} false
+Instruction 2004 S:0xC003F960 0xB500 5 PUSH {lr} false
+Instruction 2005 S:0xC003F962 0xF85DEB04 2 POP {lr} false
+Instruction 2006 S:0xC003F966 0xF64B7640 0 MOV r6,#0xbf40 false
+Instruction 2007 S:0xC003F96A 0xF2CC0664 1 MOVT r6,#0xc064 false
+Instruction 2008 S:0xC003F96E 0x6876 3 LDR r6,[r6,#4] false
+Instruction 2009 S:0xC003F970 0xFBA18906 3 UMULL r8,r9,r1,r6 false
+Instruction 2010 S:0xC003F974 0xEA4F7CE6 1 ASR r12,r6,#31 false
+Instruction 2011 S:0xC003F978 0xFBA06706 1 UMULL r6,r7,r0,r6 false
+Instruction 2012 S:0xC003F97C 0xFB01990C 1 MLA r9,r1,r12,r9 false
+Instruction 2013 S:0xC003F980 0xEA4F4408 1 LSL r4,r8,#16 false
+Instruction 2014 S:0xC003F984 0xFB00770C 1 MLA r7,r0,r12,r7 false
+Instruction 2015 S:0xC003F988 0x0C32 1 LSRS r2,r6,#16 false
+Instruction 2016 S:0xC003F98A 0xEA4F4509 1 LSL r5,r9,#16 false
+Instruction 2017 S:0xC003F98E 0xEA454518 1 ORR r5,r5,r8,LSR #16 false
+Instruction 2018 S:0xC003F992 0xEA424207 1 ORR r2,r2,r7,LSL #16 false
+Instruction 2019 S:0xC003F996 0x0C3B 1 LSRS r3,r7,#16 false
+Instruction 2020 S:0xC003F998 0x1912 1 ADDS r2,r2,r4 false
+Instruction 2021 S:0xC003F99A 0xEB430305 1 ADC r3,r3,r5 false
+Instruction 2022 S:0xC003F99E 0x4610 0 MOV r0,r2 false
+Instruction 2023 S:0xC003F9A0 0x4619 1 MOV r1,r3 false
+Instruction 2024 S:0xC003F9A2 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 2025 S:0xC003F9A6 0x4770 3 BX lr true
+Instruction 2026 S:0xC00429AE 0x2800 1 CMP r0,#0 false
+Instruction 2027 S:0xC00429B0 0xF1710E00 1 SBCS lr,r1,#0 false
+Instruction 2028 S:0xC00429B4 0xF2C0822B 0 BLT.W {pc}+0x45a ; 0xc0042e0e true fail
+Instruction 2029 S:0xC00429B8 0x0A86 1 LSRS r6,r0,#10 false
+Instruction 2030 S:0xC00429BA 0x0A8F 1 LSRS r7,r1,#10 false
+Instruction 2031 S:0xC00429BC 0xEA465681 1 ORR r6,r6,r1,LSL #22 false
+Instruction 2032 S:0xC00429C0 0xEA560E07 6 ORRS lr,r6,r7 false
+Instruction 2033 S:0xC00429C4 0xF04081E9 0 BNE.W {pc}+0x3d6 ; 0xc0042d9a true
+Instruction 2034 S:0xC0042D9A 0x4B9F 39 LDR r3,[pc,#636] ; [0xC0043018] = 0xC064BF40 false
+Instruction 2035 S:0xC0042D9C 0xE9C94500 3 STRD r4,r5,[r9,#0] false
+Instruction 2036 S:0xC0042DA0 0x681A 13 LDR r2,[r3,#0] false
+Instruction 2037 S:0xC0042DA2 0x2A00 2 CMP r2,#0 false
+Instruction 2038 S:0xC0042DA4 0xD03D 1 BEQ {pc}+0x7e ; 0xc0042e22 true fail
+Instruction 2039 S:0xC0042DA6 0xEB031308 9 ADD r3,r3,r8,LSL #4 false
+Instruction 2040 S:0xC0042DAA 0xF04F0B00 0 MOV r11,#0 false
+Instruction 2041 S:0xC0042DAE 0xF8D33098 14 LDR r3,[r3,#0x98] false
+Instruction 2042 S:0xC0042DB2 0x469A 2 MOV r10,r3 false
+Instruction 2043 S:0xC0042DB4 0x9312 1 STR r3,[sp,#0x48] false
+Instruction 2044 S:0xC0042DB6 0x9D14 1 LDR r5,[sp,#0x50] false
+Instruction 2045 S:0xC0042DB8 0xF24032FF 0 MOV r2,#0x3ff false
+Instruction 2046 S:0xC0042DBC 0x2300 1 MOVS r3,#0 false
+Instruction 2047 S:0xC0042DBE 0xF8D5459C 2 LDR r4,[r5,#0x59c] false
+Instruction 2048 S:0xC0042DC2 0x05A5 3 LSLS r5,r4,#22 false
+Instruction 2049 S:0xC0042DC4 0x0DAD 2 LSRS r5,r5,#22 false
+Instruction 2050 S:0xC0042DC6 0x1970 1 ADDS r0,r6,r5 false
+Instruction 2051 S:0xC0042DC8 0xF1470100 1 ADC r1,r7,#0 false
+Instruction 2052 S:0xC0042DCC 0x428B 1 CMP r3,r1 false
+Instruction 2053 S:0xC0042DCE 0xBF08 0 IT EQ false
+Instruction 2054 S:0xC0042DD0 0x4282 1 CMP r2,r0 false
+Instruction 2055 S:0xC0042DD2 0xD32E 0 BCC {pc}+0x60 ; 0xc0042e32 true fail
+Instruction 2056 S:0xC0042DD4 0xF8DD8050 1 LDR r8,[sp,#0x50] false
+Instruction 2057 S:0xC0042DD8 0xF8D83598 3 LDR r3,[r8,#0x598] false
+Instruction 2058 S:0xC0042DDC 0xF8D815C8 1 LDR r1,[r8,#0x5c8] false
+Instruction 2059 S:0xC0042DE0 0xFB06F20B 1 MUL r2,r6,r11 false
+Instruction 2060 S:0xC0042DE4 0x19A4 1 ADDS r4,r4,r6 false
+Instruction 2061 S:0xC0042DE6 0xFB0A2207 1 MLA r2,r10,r7,r2 false
+Instruction 2062 S:0xC0042DEA 0xF8DD8050 1 LDR r8,[sp,#0x50] false
+Instruction 2063 S:0xC0042DEE 0xFBA6670A 1 UMULL r6,r7,r6,r10 false
+Instruction 2064 S:0xC0042DF2 0x4625 1 MOV r5,r4 false
+Instruction 2065 S:0xC0042DF4 0xF8C8459C 1 STR r4,[r8,#0x59c] false
+Instruction 2066 S:0xC0042DF8 0x19D7 1 ADDS r7,r2,r7 false
+Instruction 2067 S:0xC0042DFA 0x0AB2 1 LSRS r2,r6,#10 false
+Instruction 2068 S:0xC0042DFC 0xEA425287 1 ORR r2,r2,r7,LSL #22 false
+Instruction 2069 S:0xC0042E00 0x18D3 1 ADDS r3,r2,r3 false
+Instruction 2070 S:0xC0042E02 0x1852 1 ADDS r2,r2,r1 false
+Instruction 2071 S:0xC0042E04 0xF8C83598 1 STR r3,[r8,#0x598] false
+Instruction 2072 S:0xC0042E08 0xF8C825C8 1 STR r2,[r8,#0x5c8] false
+Instruction 2073 S:0xC0042E0C 0xE5E3 0 B {pc}-0x436 ; 0xc00429d6 true
+Instruction 2074 S:0xC00429D6 0xF8DD9050 1 LDR r9,[sp,#0x50] false
+Instruction 2075 S:0xC00429DA 0x029B 1 LSLS r3,r3,#10 false
+Instruction 2076 S:0xC00429DC 0x3401 0 ADDS r4,#1 false
+Instruction 2077 S:0xC00429DE 0x2100 1 MOVS r1,#0 false
+Instruction 2078 S:0xC00429E0 0xF8D905C8 1 LDR r0,[r9,#0x5c8] false
+Instruction 2079 S:0xC00429E4 0xF8D980B8 1 LDR r8,[r9,#0xb8] false
+Instruction 2080 S:0xC00429E8 0xF8D960BC 1 LDR r6,[r9,#0xbc] false
+Instruction 2081 S:0xC00429EC 0x9006 1 STR r0,[sp,#0x18] false
+Instruction 2082 S:0xC00429EE 0x4618 0 MOV r0,r3 false
+Instruction 2083 S:0xC00429F0 0xF20EF9CE 1 BL {pc}+0x20e3a0 ; 0xc0250d90 true
+Cycle Count 323 Tracing disabled
+Info Tracing enabled
+Instruction 2084 S:0xC00429F4 0x1C6C 1 ADDS r4,r5,#1 false
+Instruction 2085 S:0xC00429F6 0x9D06 1 LDR r5,[sp,#0x18] false
+Instruction 2086 S:0xC00429F8 0xEBC80702 1 RSB r7,r8,r2 false
+Instruction 2087 S:0xC00429FC 0x2100 0 MOVS r1,#0 false
+Instruction 2088 S:0xC00429FE 0xEA877AE7 14 EOR r10,r7,r7,ASR #31 false
+Instruction 2089 S:0xC0042A02 0xEBAA7AE7 1 SUB r10,r10,r7,ASR #31 false
+Instruction 2090 S:0xC0042A06 0x02A8 1 LSLS r0,r5,#10 false
+Instruction 2091 S:0xC0042A08 0xF8D950DC 1 LDR r5,[r9,#0xdc] false
+Instruction 2092 S:0xC0042A0C 0xF20EF9C0 0 BL {pc}+0x20e384 ; 0xc0250d90 true
+Cycle Count 241 Tracing disabled
+Info Tracing enabled
+Instruction 2093 S:0xC0042A10 0xEBBA1F98 1 CMP r10,r8,LSR #6 false
+Instruction 2094 S:0xC0042A14 0xEBC60202 1 RSB r2,r6,r2 false
+Instruction 2095 S:0xC0042A18 0xD806 1 BHI {pc}+0x10 ; 0xc0042a28 true
+Instruction 2096 S:0xC0042A28 0xF1050338 14 ADD r3,r5,#0x38 false
+Instruction 2097 S:0xC0042A2C 0xE8531F00 8 LDREX r1,[r3] false
+Instruction 2098 S:0xC0042A30 0x4439 2 ADD r1,r1,r7 false
+Instruction 2099 S:0xC0042A32 0xE8431000 7 STREX r0,r1,[r3] false
+Instruction 2100 S:0xC0042A36 0xF0900F00 2 TEQ r0,#0 false
+Instruction 2101 S:0xC0042A3A 0xD1F7 0 BNE {pc}-0xe ; 0xc0042a2c true fail
+Instruction 2102 S:0xC0042A3C 0xF8DD8050 1 LDR r8,[sp,#0x50] false
+Instruction 2103 S:0xC0042A40 0xF105033C 1 ADD r3,r5,#0x3c false
+Instruction 2104 S:0xC0042A44 0xF8D810B8 2 LDR r1,[r8,#0xb8] false
+Instruction 2105 S:0xC0042A48 0x19C9 2 ADDS r1,r1,r7 false
+Instruction 2106 S:0xC0042A4A 0xF8C810B8 1 STR r1,[r8,#0xb8] false
+Instruction 2107 S:0xC0042A4E 0xE8531F00 10 LDREX r1,[r3] false
+Instruction 2108 S:0xC0042A52 0x4411 2 ADD r1,r1,r2 false
+Instruction 2109 S:0xC0042A54 0xE8431000 7 STREX r0,r1,[r3] false
+Instruction 2110 S:0xC0042A58 0xF0900F00 2 TEQ r0,#0 false
+Instruction 2111 S:0xC0042A5C 0xD1F7 0 BNE {pc}-0xe ; 0xc0042a4e true fail
+Instruction 2112 S:0xC0042A5E 0xF8D830BC 1 LDR r3,[r8,#0xbc] false
+Instruction 2113 S:0xC0042A62 0x189B 2 ADDS r3,r3,r2 false
+Instruction 2114 S:0xC0042A64 0xF8C830BC 1 STR r3,[r8,#0xbc] false
+Instruction 2115 S:0xC0042A68 0x4BBA 3 LDR r3,[pc,#744] ; [0xC0042D54] false
+Instruction 2116 S:0xC0042A6A 0xF8DD9050 3 LDR r9,[sp,#0x50] false
+Instruction 2117 S:0xC0042A6E 0x685A 3 LDR r2,[r3,#4] false
+Instruction 2118 S:0xC0042A70 0xF8D90598 3 LDR r0,[r9,#0x598] false
+Instruction 2119 S:0xC0042A74 0xF8D9159C 1 LDR r1,[r9,#0x59c] false
+Instruction 2120 S:0xC0042A78 0xF8D984C0 1 LDR r8,[r9,#0x4c0] false
+Instruction 2121 S:0xC0042A7C 0x2A00 0 CMP r2,#0 false
+Instruction 2122 S:0xC0042A7E 0xF0408256 1 BNE.W {pc}+0x4b0 ; 0xc0042f2e true fail
+Instruction 2123 S:0xC0042A82 0x4BB5 1 LDR r3,[pc,#724] ; [0xC0042D58] false
+Instruction 2124 S:0xC0042A84 0xF8DD9050 1 LDR r9,[sp,#0x50] false
+Instruction 2125 S:0xC0042A88 0x685A 13 LDR r2,[r3,#4] false
+Instruction 2126 S:0xC0042A8A 0xE9D94524 1 LDRD r4,r5,[r9,#0x90] false
+Instruction 2127 S:0xC0042A8E 0x2A00 1 CMP r2,#0 false
+Instruction 2128 S:0xC0042A90 0xF040823E 0 BNE.W {pc}+0x480 ; 0xc0042f10 true fail
+Instruction 2129 S:0xC0042A94 0x9814 1 LDR r0,[sp,#0x50] false
+Instruction 2130 S:0xC0042A96 0xB01B 0 ADD sp,sp,#0x6c false
+Instruction 2131 S:0xC0042A98 0xE8BD4FF0 3 POP {r4-r11,lr} false
+Instruction 2132 S:0xC0042A9C 0xF7FEBB58 5 B {pc}-0x194c ; 0xc0041150 true
+Instruction 2133 S:0xC0041150 0xB478 2 PUSH {r3-r6} false
+Instruction 2134 S:0xC0041152 0xB500 4 PUSH {lr} false
+Instruction 2135 S:0xC0041154 0xF85DEB04 2 POP {lr} false
+Instruction 2136 S:0xC0041158 0x4A16 12 LDR r2,[pc,#88] ; [0xC00411B4] = 0xC05FC568 false
+Instruction 2137 S:0xC004115A 0xF8D01460 2 LDR r1,[r0,#0x460] false
+Instruction 2138 S:0xC004115E 0x6812 3 LDR r2,[r2,#0] false
+Instruction 2139 S:0xC0041160 0x0612 3 LSLS r2,r2,#24 false
+Instruction 2140 S:0xC0041162 0xD51A 0 BPL {pc}+0x38 ; 0xc004119a true
+Instruction 2141 S:0xC004119A 0xBC78 18 POP {r3-r6} false
+Instruction 2142 S:0xC004119C 0x4770 2 BX lr true
+Instruction 2143 S:0xC003B85A 0xE8BD87F0 9 POP {r4-r10,pc} true
+Cycle Count 128 Tracing disabled
+Info Tracing enabled
+Instruction 2144 S:0xC0042274 0xE92D4FF0 1 PUSH {r4-r11,lr} false
+Instruction 2145 S:0xC0042278 0xB097 7 SUB sp,sp,#0x5c false
+Instruction 2146 S:0xC004227A 0xB500 3 PUSH {lr} false
+Instruction 2147 S:0xC004227C 0xF85DEB04 2 POP {lr} false
+Instruction 2148 S:0xC0042280 0xF1110A38 4 ADDS r10,r1,#0x38 false
+Instruction 2149 S:0xC0042284 0xF00081A1 0 BEQ.W {pc}+0x346 ; 0xc00425ca true fail
+Instruction 2150 S:0xC0042288 0xF8DFB3FC 1 LDR r11,[pc,#1020] ; [0xC0042688] false
+Instruction 2151 S:0xC004228C 0xE008 0 B {pc}+0x14 ; 0xc00422a0 true
+Instruction 2152 S:0xC00422A0 0xF8DA301C 18 LDR r3,[r10,#0x1c] false
+Instruction 2153 S:0xC00422A4 0xF8DA8124 1 LDR r8,[r10,#0x124] false
+Instruction 2154 S:0xC00422A8 0x2B00 1 CMP r3,#0 false
+Instruction 2155 S:0xC00422AA 0xF0408191 0 BNE.W {pc}+0x326 ; 0xc00425d0 true fail
+Instruction 2156 S:0xC00422AE 0xE9D82306 4 LDRD r2,r3,[r8,#0x18] false
+Instruction 2157 S:0xC00422B2 0xE9DA010C 3 LDRD r0,r1,[r10,#0x30] false
+Instruction 2158 S:0xC00422B6 0xF8DB4000 3 LDR r4,[r11,#0] false
+Instruction 2159 S:0xC00422BA 0x1A80 1 SUBS r0,r0,r2 false
+Instruction 2160 S:0xC00422BC 0xEB610103 1 SBC r1,r1,r3 false
+Instruction 2161 S:0xC00422C0 0x2300 6 MOVS r3,#0 false
+Instruction 2162 S:0xC00422C2 0x17CE 1 ASRS r6,r1,#31 false
+Instruction 2163 S:0xC00422C4 0xEB040444 1 ADD r4,r4,r4,LSL #1 false
+Instruction 2164 S:0xC00422C8 0x4637 0 MOV r7,r6 false
+Instruction 2165 S:0xC00422CA 0x4070 1 EORS r0,r0,r6 false
+Instruction 2166 S:0xC00422CC 0x4071 1 EORS r1,r1,r6 false
+Instruction 2167 S:0xC00422CE 0x4622 0 MOV r2,r4 false
+Instruction 2168 S:0xC00422D0 0x1B80 1 SUBS r0,r0,r6 false
+Instruction 2169 S:0xC00422D2 0xEB610107 1 SBC r1,r1,r7 false
+Instruction 2170 S:0xC00422D6 0x4282 1 CMP r2,r0 false
+Instruction 2171 S:0xC00422D8 0xEB730401 1 SBCS r4,r3,r1 false
+Instruction 2172 S:0xC00422DC 0xBFBE 0 ITTT LT false
+Instruction 2173 S:0xC00422DE 0xF8D83040 14 LDR r3,[r8,#0x40] false fail
+Instruction 2174 S:0xC00422E2 0x3301 2 ADDS r3,#1 false fail
+Instruction 2175 S:0xC00422E4 0xF8C83040 1 STR r3,[r8,#0x40] false fail
+Instruction 2176 S:0xC00422E8 0xF8DA301C 1 LDR r3,[r10,#0x1c] false
+Instruction 2177 S:0xC00422EC 0x2B00 2 CMP r3,#0 false
+Instruction 2178 S:0xC00422EE 0xD0CE 0 BEQ {pc}-0x60 ; 0xc004228e true
+Instruction 2179 S:0xC004228E 0x2500 67 MOVS r5,#0 false
+Instruction 2180 S:0xC0042290 0xF8C85030 1 STR r5,[r8,#0x30] false
+Instruction 2181 S:0xC0042294 0xF8DAA120 1 LDR r10,[r10,#0x120] false
+Instruction 2182 S:0xC0042298 0xF1BA0F00 2 CMP r10,#0 false
+Instruction 2183 S:0xC004229C 0xF0008195 0 BEQ.W {pc}+0x32e ; 0xc00425ca true
+Instruction 2184 S:0xC00425CA 0xB017 22 ADD sp,sp,#0x5c false
+Instruction 2185 S:0xC00425CC 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Cycle Count 25 Tracing disabled
+Info Tracing enabled
+Instruction 2186 S:0xC00421AC 0xB5F8 1 PUSH {r3-r7,lr} false
+Instruction 2187 S:0xC00421AE 0xB500 5 PUSH {lr} false
+Instruction 2188 S:0xC00421B0 0xF85DEB04 2 POP {lr} false
+Instruction 2189 S:0xC00421B4 0x4607 0 MOV r7,r0 false
+Instruction 2190 S:0xC00421B6 0x6D05 1 LDR r5,[r0,#0x50] false
+Instruction 2191 S:0xC00421B8 0xF1000448 0 ADD r4,r0,#0x48 false
+Instruction 2192 S:0xC00421BC 0x2D00 2 CMP r5,#0 false
+Instruction 2193 S:0xC00421BE 0xD043 0 BEQ {pc}+0x8a ; 0xc0042248 true fail
+Timestamp Timestamp: 562536962560
+Instruction 2194 S:0xC00421C0 0x6AE6 5 LDR r6,[r4,#0x2c] false
+Instruction 2195 S:0xC00421C2 0xB106 2 CBZ r6,{pc}+4 ; 0xc00421c6 true fail
+Instruction 2196 S:0xC00421C4 0x3E08 1 SUBS r6,r6,#8 false
+Instruction 2197 S:0xC00421C6 0x6BE5 1 LDR r5,[r4,#0x3c] false
+Instruction 2198 S:0xC00421C8 0x42B5 2 CMP r5,r6 false
+Instruction 2199 S:0xC00421CA 0xBF18 0 IT NE false
+Instruction 2200 S:0xC00421CC 0x4635 1 MOV r5,r6 false
+Instruction 2201 S:0xC00421CE 0xD03D 0 BEQ {pc}+0x7e ; 0xc004224c true fail
+Instruction 2202 S:0xC00421D0 0x6BA0 1 LDR r0,[r4,#0x38] false
+Instruction 2203 S:0xC00421D2 0xB128 2 CBZ r0,{pc}+0xe ; 0xc00421e0 true
+Instruction 2204 S:0xC00421E0 0x6B60 11 LDR r0,[r4,#0x34] false
+Instruction 2205 S:0xC00421E2 0xB128 2 CBZ r0,{pc}+0xe ; 0xc00421f0 true
+Instruction 2206 S:0xC00421F0 0x4620 58 MOV r0,r4 false
+Instruction 2207 S:0xC00421F2 0x4629 0 MOV r1,r5 false
+Instruction 2208 S:0xC00421F4 0xF7FFF89E 1 BL {pc}-0xec0 ; 0xc0041334 true
+Instruction 2209 S:0xC0041334 0xB430 21 PUSH {r4,r5} false
+Instruction 2210 S:0xC0041336 0xB500 1 PUSH {lr} false
+Instruction 2211 S:0xC0041338 0xF85DEB04 2 POP {lr} false
+Instruction 2212 S:0xC004133C 0x6B83 1 LDR r3,[r0,#0x38] false
+Instruction 2213 S:0xC004133E 0x428B 2 CMP r3,r1 false
+Instruction 2214 S:0xC0041340 0xD038 0 BEQ {pc}+0x74 ; 0xc00413b4 true fail
+Instruction 2215 S:0xC0041342 0x6B43 1 LDR r3,[r0,#0x34] false
+Instruction 2216 S:0xC0041344 0x428B 2 CMP r3,r1 false
+Instruction 2217 S:0xC0041346 0xD01D 0 BEQ {pc}+0x3e ; 0xc0041384 true fail
+Instruction 2218 S:0xC0041348 0x6BC3 14 LDR r3,[r0,#0x3c] false
+Instruction 2219 S:0xC004134A 0x428B 2 CMP r3,r1 false
+Instruction 2220 S:0xC004134C 0xD001 1 BEQ {pc}+6 ; 0xc0041352 true fail
+Instruction 2221 S:0xC004134E 0xBC30 1 POP {r4,r5} false
+Instruction 2222 S:0xC0041350 0x4770 1 BX lr true
+Instruction 2223 S:0xC00421F8 0x4620 1 MOV r0,r4 false
+Instruction 2224 S:0xC00421FA 0x4629 0 MOV r1,r5 false
+Instruction 2225 S:0xC00421FC 0xF7FFFE3E 1 BL {pc}-0x380 ; 0xc0041e7c true
+Instruction 2226 S:0xC0041E7C 0xE92D4FF0 62 PUSH {r4-r11,lr} false
+Instruction 2227 S:0xC0041E80 0xB091 63 SUB sp,sp,#0x44 false
+Instruction 2228 S:0xC0041E82 0xB500 3 PUSH {lr} false
+Instruction 2229 S:0xC0041E84 0xF85DEB04 2 POP {lr} false
+Instruction 2230 S:0xC0041E88 0x69CB 2 LDR r3,[r1,#0x1c] false
+Instruction 2231 S:0xC0041E8A 0x4688 0 MOV r8,r1 false
+Instruction 2232 S:0xC0041E8C 0x4681 1 MOV r9,r0 false
+Instruction 2233 S:0xC0041E8E 0x2B00 1 CMP r3,#0 false
+Instruction 2234 S:0xC0041E90 0xD127 0 BNE {pc}+0x52 ; 0xc0041ee2 true
+Instruction 2235 S:0xC0041EE2 0xF7FEF89B 11 BL {pc}-0x1ec6 ; 0xc004001c true
+Instruction 2236 S:0xC004001C 0xE92D4FF8 4 PUSH {r3-r11,lr} false
+Instruction 2237 S:0xC0040020 0xB500 17 PUSH {lr} false
+Instruction 2238 S:0xC0040022 0xF85DEB04 2 POP {lr} false
+Instruction 2239 S:0xC0040026 0xF04F0A01 1 MOV r10,#1 false
+Instruction 2240 S:0xC004002A 0xF8D03084 1 LDR r3,[r0,#0x84] false
+Instruction 2241 S:0xC004002E 0xF04F0B00 0 MOV r11,#0 false
+Instruction 2242 S:0xC0040032 0xE9D16712 11 LDRD r6,r7,[r1,#0x48] false
+Instruction 2243 S:0xC0040036 0x4688 1 MOV r8,r1 false
+Instruction 2244 S:0xC0040038 0xF503638F 0 ADD r3,r3,#0x478 false
+Instruction 2245 S:0xC004003C 0xE9D14514 1 LDRD r4,r5,[r1,#0x50] false
+Instruction 2246 S:0xC0040040 0xE9D32300 44 LDRD r2,r3,[r3,#0] false
+Instruction 2247 S:0xC0040044 0x1B92 2 SUBS r2,r2,r6 false
+Instruction 2248 S:0xC0040046 0xEB630307 1 SBC r3,r3,r7 false
+Instruction 2249 S:0xC004004A 0x42AB 1 CMP r3,r5 false
+Instruction 2250 S:0xC004004C 0xBF08 0 IT EQ false
+Instruction 2251 S:0xC004004E 0x42A2 1 CMP r2,r4 false
+Instruction 2252 S:0xC0040050 0xBF3C 0 ITT CC false
+Instruction 2253 S:0xC0040052 0x4622 1 MOV r2,r4 false
+Instruction 2254 S:0xC0040054 0x462B 0 MOV r3,r5 false
+Instruction 2255 S:0xC0040056 0xE9D14516 1 LDRD r4,r5,[r1,#0x58] false
+Instruction 2256 S:0xC004005A 0xE9C12314 1 STRD r2,r3,[r1,#0x50] false
+Instruction 2257 S:0xC004005E 0xEB14040A 17 ADDS r4,r4,r10 false
+Instruction 2258 S:0xC0040062 0xEB45050B 1 ADC r5,r5,r11 false
+Instruction 2259 S:0xC0040066 0xE9C14516 1 STRD r4,r5,[r1,#0x58] false
+Instruction 2260 S:0xC004006A 0xF8D03084 1 LDR r3,[r0,#0x84] false
+Instruction 2261 S:0xC004006E 0xE9D14518 1 LDRD r4,r5,[r1,#0x60] false
+Instruction 2262 S:0xC0040072 0xF503638F 1 ADD r3,r3,#0x478 false
+Instruction 2263 S:0xC0040076 0xF8D11128 12 LDR r1,[r1,#0x128] false
+Instruction 2264 S:0xC004007A 0xE9D32300 2 LDRD r2,r3,[r3,#0] false
+Instruction 2265 S:0xC004007E 0x1912 2 ADDS r2,r2,r4 false
+Instruction 2266 S:0xC0040080 0xEB430305 1 ADC r3,r3,r5 false
+Instruction 2267 S:0xC0040084 0x1B92 1 SUBS r2,r2,r6 false
+Instruction 2268 S:0xC0040086 0xEB630307 1 SBC r3,r3,r7 false
+Instruction 2269 S:0xC004008A 0xE9C82318 1 STRD r2,r3,[r8,#0x60] false
+Instruction 2270 S:0xC004008E 0xB129 1 CBZ r1,{pc}+0xe ; 0xc004009c true
+Instruction 2271 S:0xC004009C 0x490E 29 LDR r1,[pc,#56] ; [0xC00400D8] = 0xC0636058 false
+Instruction 2272 S:0xC004009E 0xF8D03084 3 LDR r3,[r0,#0x84] false
+Instruction 2273 S:0xC00400A2 0x6848 13 LDR r0,[r1,#4] false
+Instruction 2274 S:0xC00400A4 0xF503638F 1 ADD r3,r3,#0x478 false
+Instruction 2275 S:0xC00400A8 0xE9D32300 3 LDRD r2,r3,[r3,#0] false
+Instruction 2276 S:0xC00400AC 0x2800 1 CMP r0,#0 false
+Instruction 2277 S:0xC00400AE 0xD0EF 0 BEQ {pc}-0x1e ; 0xc0040090 true
+Instruction 2278 S:0xC0040090 0x2200 1 MOVS r2,#0 false
+Instruction 2279 S:0xC0040092 0x2300 0 MOVS r3,#0 false
+Instruction 2280 S:0xC0040094 0xE9C82312 1 STRD r2,r3,[r8,#0x48] false
+Instruction 2281 S:0xC0040098 0xE8BD8FF8 1 POP {r3-r11,pc} true
+Instruction 2282 S:0xC0041EE6 0x4648 5 MOV r0,r9 false
+Instruction 2283 S:0xC0041EE8 0x4641 0 MOV r1,r8 false
+Instruction 2284 S:0xC0041EEA 0xF7FEFAC7 1 BL {pc}-0x1a6e ; 0xc004047c true
+Instruction 2285 S:0xC004047C 0xB538 1 PUSH {r3-r5,lr} false
+Instruction 2286 S:0xC004047E 0xB500 4 PUSH {lr} false
+Instruction 2287 S:0xC0040480 0xF85DEB04 50 POP {lr} false
+Instruction 2288 S:0xC0040484 0xF1010508 0 ADD r5,r1,#8 false
+Instruction 2289 S:0xC0040488 0x6AC3 1 LDR r3,[r0,#0x2c] false
+Instruction 2290 S:0xC004048A 0x4604 0 MOV r4,r0 false
+Instruction 2291 S:0xC004048C 0x42AB 2 CMP r3,r5 false
+Instruction 2292 S:0xC004048E 0xD006 0 BEQ {pc}+0x10 ; 0xc004049e true
+Instruction 2293 S:0xC004049E 0x4628 22 MOV r0,r5 false
+Instruction 2294 S:0xC00404A0 0xF216F87E 1 BL {pc}+0x216100 ; 0xc02565a0 true
+Cycle Count 55 Tracing disabled
+Info Tracing enabled
+Instruction 2295 S:0xC00404A4 0x62E0 1 STR r0,[r4,#0x2c] false
+Instruction 2296 S:0xC00404A6 0xE7F3 0 B {pc}-0x16 ; 0xc0040490 true
+Instruction 2297 S:0xC0040490 0x4628 3 MOV r0,r5 false
+Instruction 2298 S:0xC0040492 0xF1040128 0 ADD r1,r4,#0x28 false
+Instruction 2299 S:0xC0040496 0xE8BD4038 1 POP {r3-r5,lr} false
+Instruction 2300 S:0xC004049A 0xF215BECF 2 B.W {pc}+0x215da2 ; 0xc025623c true
+Cycle Count 205 Tracing disabled
+Info Tracing enabled
+Instruction 2301 S:0xC0041EEE 0xF8D8A124 1 LDR r10,[r8,#0x124] false
+Instruction 2302 S:0xC0041EF2 0xF8D83128 1 LDR r3,[r8,#0x128] false
+Instruction 2303 S:0xC0041EF6 0xF8DA2084 2 LDR r2,[r10,#0x84] false
+Instruction 2304 S:0xC0041EFA 0xF8D274C0 3 LDR r7,[r2,#0x4c0] false
+Instruction 2305 S:0xC0041EFE 0x9704 1 STR r7,[sp,#0x10] false
+Instruction 2306 S:0xC0041F00 0x2B00 12 CMP r3,#0 false
+Instruction 2307 S:0xC0041F02 0xF0008108 0 BEQ.W {pc}+0x214 ; 0xc0042116 true
+Instruction 2308 S:0xC0042116 0xF5026290 40 ADD r2,r2,#0x480 false
+Instruction 2309 S:0xC004211A 0xE9D26700 3 LDRD r6,r7,[r2,#0] false
+Instruction 2310 S:0xC004211E 0xE6F8 1 B {pc}-0x20c ; 0xc0041f12 true
+Instruction 2311 S:0xC0041F12 0x46C3 14 MOV r11,r8 false
+Instruction 2312 S:0xC0041F14 0xF8D8201C 1 LDR r2,[r8,#0x1c] false
+Instruction 2313 S:0xC0041F18 0xF8DA3030 1 LDR r3,[r10,#0x30] false
+Instruction 2314 S:0xC0041F1C 0xE9FB014E 1 LDRD r0,r1,[r11,#0x138]! false
+Instruction 2315 S:0xC0041F20 0x9209 1 STR r2,[sp,#0x24] false
+Instruction 2316 S:0xC0041F22 0x1A30 1 SUBS r0,r6,r0 false
+Instruction 2317 S:0xC0041F24 0xEB670101 1 SBC r1,r7,r1 false
+Instruction 2318 S:0xC0041F28 0x9306 1 STR r3,[sp,#0x18] false
+Instruction 2319 S:0xC0041F2A 0xF7FDFD17 0 BL {pc}-0x25ce ; 0xc003f95c true
+Instruction 2320 S:0xC003F95C 0xE92D03F0 1 PUSH {r4-r9} false
+Instruction 2321 S:0xC003F960 0xB500 5 PUSH {lr} false
+Instruction 2322 S:0xC003F962 0xF85DEB04 2 POP {lr} false
+Instruction 2323 S:0xC003F966 0xF64B7640 0 MOV r6,#0xbf40 false
+Instruction 2324 S:0xC003F96A 0xF2CC0664 1 MOVT r6,#0xc064 false
+Instruction 2325 S:0xC003F96E 0x6876 5 LDR r6,[r6,#4] false
+Instruction 2326 S:0xC003F970 0xFBA18906 3 UMULL r8,r9,r1,r6 false
+Instruction 2327 S:0xC003F974 0xEA4F7CE6 1 ASR r12,r6,#31 false
+Instruction 2328 S:0xC003F978 0xFBA06706 1 UMULL r6,r7,r0,r6 false
+Instruction 2329 S:0xC003F97C 0xFB01990C 1 MLA r9,r1,r12,r9 false
+Instruction 2330 S:0xC003F980 0xEA4F4408 1 LSL r4,r8,#16 false
+Instruction 2331 S:0xC003F984 0xFB00770C 1 MLA r7,r0,r12,r7 false
+Instruction 2332 S:0xC003F988 0x0C32 1 LSRS r2,r6,#16 false
+Instruction 2333 S:0xC003F98A 0xEA4F4509 1 LSL r5,r9,#16 false
+Instruction 2334 S:0xC003F98E 0xEA454518 1 ORR r5,r5,r8,LSR #16 false
+Instruction 2335 S:0xC003F992 0xEA424207 1 ORR r2,r2,r7,LSL #16 false
+Instruction 2336 S:0xC003F996 0x0C3B 1 LSRS r3,r7,#16 false
+Instruction 2337 S:0xC003F998 0x1912 1 ADDS r2,r2,r4 false
+Instruction 2338 S:0xC003F99A 0xEB430305 1 ADC r3,r3,r5 false
+Instruction 2339 S:0xC003F99E 0x4610 0 MOV r0,r2 false
+Instruction 2340 S:0xC003F9A0 0x4619 1 MOV r1,r3 false
+Instruction 2341 S:0xC003F9A2 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 2342 S:0xC003F9A6 0x4770 3 BX lr true
+Instruction 2343 S:0xC0041F2E 0x2800 1 CMP r0,#0 false
+Instruction 2344 S:0xC0041F30 0xF1710C00 1 SBCS r12,r1,#0 false
+Instruction 2345 S:0xC0041F34 0xF2C080D9 0 BLT.W {pc}+0x1b6 ; 0xc00420ea true fail
+Instruction 2346 S:0xC0041F38 0x0A84 1 LSRS r4,r0,#10 false
+Instruction 2347 S:0xC0041F3A 0x0A8D 1 LSRS r5,r1,#10 false
+Instruction 2348 S:0xC0041F3C 0xEA445481 1 ORR r4,r4,r1,LSL #22 false
+Instruction 2349 S:0xC0041F40 0xEA540005 6 ORRS r0,r4,r5 false
+Instruction 2350 S:0xC0041F44 0xD0A5 0 BEQ {pc}-0xb2 ; 0xc0041e92 true fail
+Instruction 2351 S:0xC0041F46 0x4A8E 13 LDR r2,[pc,#568] ; [0xC0042180] = 0xC064BF40 false
+Instruction 2352 S:0xC0041F48 0xE9CB6700 3 STRD r6,r7,[r11,#0] false
+Instruction 2353 S:0xC0041F4C 0x6813 1 LDR r3,[r2,#0] false
+Instruction 2354 S:0xC0041F4E 0x2B00 2 CMP r3,#0 false
+Instruction 2355 S:0xC0041F50 0xF00080CE 0 BEQ.W {pc}+0x1a0 ; 0xc00420f0 true fail
+Instruction 2356 S:0xC0041F54 0x9B04 8 LDR r3,[sp,#0x10] false
+Instruction 2357 S:0xC0041F56 0xF04F0C00 1 MOV r12,#0 false
+Instruction 2358 S:0xC0041F5A 0xF8CDC014 1 STR r12,[sp,#0x14] false
+Instruction 2359 S:0xC0041F5E 0xEB021203 19 ADD r2,r2,r3,LSL #4 false
+Instruction 2360 S:0xC0041F62 0xF8D2B098 3 LDR r11,[r2,#0x98] false
+Instruction 2361 S:0xC0041F66 0xF8CDB010 1 STR r11,[sp,#0x10] false
+Instruction 2362 S:0xC0041F6A 0x9B06 1 LDR r3,[sp,#0x18] false
+Instruction 2363 S:0xC0041F6C 0xF8D82134 1 LDR r2,[r8,#0x134] false
+Instruction 2364 S:0xC0041F70 0xEBB80703 1 SUBS r7,r8,r3 false
+Instruction 2365 S:0xC0041F74 0x427E 1 RSBS r6,r7,#0 false
+Instruction 2366 S:0xC0041F76 0x417E 1 ADCS r6,r6,r7 false
+Instruction 2367 S:0xC0041F78 0x0597 1 LSLS r7,r2,#22 false
+Instruction 2368 S:0xC0041F7A 0x0DBF 2 LSRS r7,r7,#22 false
+Instruction 2369 S:0xC0041F7C 0x19E0 1 ADDS r0,r4,r7 false
+Instruction 2370 S:0xC0041F7E 0xF1450100 9 ADC r1,r5,#0 false
+Instruction 2371 S:0xC0041F82 0x2900 1 CMP r1,#0 false
+Instruction 2372 S:0xC0041F84 0xBF08 1 IT EQ false
+Instruction 2373 S:0xC0041F86 0xF5B06F80 1 CMP r0,#0x400 false
+Instruction 2374 S:0xC0041F8A 0xBF38 0 IT CC false
+Instruction 2375 S:0xC0041F8C 0x2700 1 MOVS r7,#0 false fail
+Instruction 2376 S:0xC0041F8E 0xD377 0 BCC {pc}+0xf2 ; 0xc0042080 true fail
+Instruction 2377 S:0xC0041F90 0xF5C76780 18 RSB r7,r7,#0x400 false
+Instruction 2378 S:0xC0041F94 0x9B09 1 LDR r3,[sp,#0x24] false
+Instruction 2379 S:0xC0041F96 0xFB07F10B 1 MUL r1,r7,r11 false
+Instruction 2380 S:0xC0041F9A 0x0A89 3 LSRS r1,r1,#10 false
+Instruction 2381 S:0xC0041F9C 0x2B00 0 CMP r3,#0 false
+Instruction 2382 S:0xC0041F9E 0xF00080B7 15 BEQ.W {pc}+0x172 ; 0xc0042110 true fail
+Instruction 2383 S:0xC0041FA2 0xF8D80130 1 LDR r0,[r8,#0x130] false
+Instruction 2384 S:0xC0041FA6 0xEB010C00 2 ADD r12,r1,r0 false
+Instruction 2385 S:0xC0041FAA 0xF8C8C130 1 STR r12,[r8,#0x130] false
+Instruction 2386 S:0xC0041FAE 0xB126 1 CBZ r6,{pc}+0xc ; 0xc0041fba true
+Instruction 2387 S:0xC0041FBA 0x1BE4 1 SUBS r4,r4,r7 false
+Instruction 2388 S:0xC0041FBC 0xEB6575E7 1 SBC r5,r5,r7,ASR #31 false
+Instruction 2389 S:0xC0041FC0 0x18BF 60 ADDS r7,r7,r2 false
+Instruction 2390 S:0xC0041FC2 0xF24032FF 0 MOV r2,#0x3ff false
+Instruction 2391 S:0xC0041FC6 0x2300 1 MOVS r3,#0 false
+Instruction 2392 S:0xC0041FC8 0x0AA1 1 LSRS r1,r4,#10 false
+Instruction 2393 S:0xC0041FCA 0x4014 1 ANDS r4,r4,r2 false
+Instruction 2394 S:0xC0041FCC 0xEA415085 1 ORR r0,r1,r5,LSL #22 false
+Instruction 2395 S:0xC0041FD0 0x0AA9 1 LSRS r1,r5,#10 false
+Instruction 2396 S:0xC0041FD2 0x9000 1 STR r0,[sp,#0] false
+Instruction 2397 S:0xC0041FD4 0x2201 0 MOVS r2,#1 false
+Instruction 2398 S:0xC0041FD6 0x9101 1 STR r1,[sp,#4] false
+Instruction 2399 S:0xC0041FD8 0x401D 1 ANDS r5,r5,r3 false
+Instruction 2400 S:0xC0041FDA 0xE9DD0100 1 LDRD r0,r1,[sp,#0] false
+Instruction 2401 S:0xC0041FDE 0x2300 1 MOVS r3,#0 false
+Instruction 2402 S:0xC0041FE0 0xF8C87134 15 STR r7,[r8,#0x134] false
+Instruction 2403 S:0xC0041FE4 0x1812 1 ADDS r2,r2,r0 false
+Instruction 2404 S:0xC0041FE6 0xF44F60FC 1 MOV r0,#0x7e0 false
+Instruction 2405 S:0xC0041FEA 0xEB430301 1 ADC r3,r3,r1 false
+Instruction 2406 S:0xC0041FEE 0x2100 0 MOVS r1,#0 false
+Instruction 2407 S:0xC0041FF0 0x4299 1 CMP r1,r3 false
+Instruction 2408 S:0xC0041FF2 0xBF08 0 IT EQ false
+Instruction 2409 S:0xC0041FF4 0x4290 1 CMP r0,r2 false
+Instruction 2410 S:0xC0041FF6 0xE9CD2306 1 STRD r2,r3,[sp,#0x18] false
+Instruction 2411 S:0xC0041FFA 0xF0C08091 1 BCC.W {pc}+0x126 ; 0xc0042120 true fail
+Instruction 2412 S:0xC0041FFE 0x9906 1 LDR r1,[sp,#0x18] false
+Instruction 2413 S:0xC0042000 0x4610 92 MOV r0,r2 false
+Instruction 2414 S:0xC0042002 0xF8DFE180 1 LDR lr,[pc,#384] ; [0xC0042184] = 0xC03E83C8 false
+Instruction 2415 S:0xC0042006 0x291F 1 CMP r1,#0x1f false
+Instruction 2416 S:0xC0042008 0xF2008096 0 BHI.W {pc}+0x130 ; 0xc0042138 true fail
+Instruction 2417 S:0xC004200C 0xF85E1022 83 LDR r1,[lr,r2,LSL #2] false
+Instruction 2418 S:0xC0042010 0xF8D83160 12 LDR r3,[r8,#0x160] false
+Instruction 2419 S:0xC0042014 0x9108 1 STR r1,[sp,#0x20] false
+Instruction 2420 S:0xC0042016 0x930D 2 STR r3,[sp,#0x34] false
+Instruction 2421 S:0xC0042018 0xFBAC2301 1 UMULL r2,r3,r12,r1 false
+Instruction 2422 S:0xC004201C 0xE9CD2306 1 STRD r2,r3,[sp,#0x18] false
+Instruction 2423 S:0xC0042020 0xFBA72301 1 UMULL r2,r3,r7,r1 false
+Instruction 2424 S:0xC0042024 0x9F07 1 LDR r7,[sp,#0x1c] false
+Instruction 2425 S:0xC0042026 0x970C 1 STR r7,[sp,#0x30] false
+Instruction 2426 S:0xC0042028 0xF8C87130 1 STR r7,[r8,#0x130] false
+Instruction 2427 S:0xC004202C 0x9306 1 STR r3,[sp,#0x18] false
+Instruction 2428 S:0xC004202E 0xF8C83134 1 STR r3,[r8,#0x134] false
+Instruction 2429 S:0xC0042032 0x2300 0 MOVS r3,#0 false
+Instruction 2430 S:0xC0042034 0xF85E7020 1 LDR r7,[lr,r0,LSL #2] false
+Instruction 2431 S:0xC0042038 0x2200 0 MOVS r2,#0 false
+Instruction 2432 S:0xC004203A 0xE9CD230E 1 STRD r2,r3,[sp,#0x38] false
+Instruction 2433 S:0xC004203E 0x9B0D 1 LDR r3,[sp,#0x34] false
+Instruction 2434 S:0xC0042040 0xFBA70103 51 UMULL r0,r1,r7,r3 false
+Instruction 2435 S:0xC0042044 0x910E 1 STR r1,[sp,#0x38] false
+Instruction 2436 S:0xC0042046 0x980E 2 LDR r0,[sp,#0x38] false
+Instruction 2437 S:0xC0042048 0x9F0E 1 LDR r7,[sp,#0x38] false
+Instruction 2438 S:0xC004204A 0xF8C80160 2 STR r0,[r8,#0x160] false
+Instruction 2439 S:0xC004204E 0xE9DD0100 1 LDRD r0,r1,[sp,#0] false
+Instruction 2440 S:0xC0042052 0xF7FFFB3D 1 BL {pc}-0x982 ; 0xc00416d0 true
+Instruction 2441 S:0xC00416D0 0xE92D03F0 1 PUSH {r4-r9} false
+Instruction 2442 S:0xC00416D4 0xB500 5 PUSH {lr} false
+Instruction 2443 S:0xC00416D6 0xF85DEB04 2 POP {lr} false
+Instruction 2444 S:0xC00416DA 0x2620 0 MOVS r6,#0x20 false
+Instruction 2445 S:0xC00416DC 0x2700 1 MOVS r7,#0 false
+Instruction 2446 S:0xC00416DE 0x428F 1 CMP r7,r1 false
+Instruction 2447 S:0xC00416E0 0xBF08 0 IT EQ false
+Instruction 2448 S:0xC00416E2 0x4286 1 CMP r6,r0 false
+Instruction 2449 S:0xC00416E4 0xD307 0 BCC {pc}+0x12 ; 0xc00416f6 true fail
+Instruction 2450 S:0xC00416E6 0x4B31 3 LDR r3,[pc,#196] ; [0xC00417AC] false
+Instruction 2451 S:0xC00416E8 0xEB030080 2 ADD r0,r3,r0,LSL #2 false
+Instruction 2452 S:0xC00416EC 0xF8D000FC 3 LDR r0,[r0,#0xfc] false
+Instruction 2453 S:0xC00416F0 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 2454 S:0xC00416F4 0x4770 3 BX lr true
+Instruction 2455 S:0xC0042056 0x9A09 2 LDR r2,[sp,#0x24] false
+Instruction 2456 S:0xC0042058 0xFB0BFB00 1 MUL r11,r11,r0 false
+Instruction 2457 S:0xC004205C 0xEA4F2B9B 3 LSR r11,r11,#10 false
+Instruction 2458 S:0xC0042060 0xB12A 1 CBZ r2,{pc}+0xe ; 0xc004206e true fail
+Instruction 2459 S:0xC0042062 0xF8DDC030 1 LDR r12,[sp,#0x30] false
+Instruction 2460 S:0xC0042066 0xEB0B030C 2 ADD r3,r11,r12 false
+Instruction 2461 S:0xC004206A 0xF8C83130 1 STR r3,[r8,#0x130] false
+Instruction 2462 S:0xC004206E 0xB116 1 CBZ r6,{pc}+8 ; 0xc0042076 true
+Instruction 2463 S:0xC0042076 0x9B06 8 LDR r3,[sp,#0x18] false
+Instruction 2464 S:0xC0042078 0x2701 1 MOVS r7,#1 false
+Instruction 2465 S:0xC004207A 0x18C2 1 ADDS r2,r0,r3 false
+Instruction 2466 S:0xC004207C 0xF8C82134 1 STR r2,[r8,#0x134] false
+Instruction 2467 S:0xC0042080 0xF8DDC014 1 LDR r12,[sp,#0x14] false
+Instruction 2468 S:0xC0042084 0x9804 1 LDR r0,[sp,#0x10] false
+Instruction 2469 S:0xC0042086 0xFB04F30C 2 MUL r3,r4,r12 false
+Instruction 2470 S:0xC004208A 0xFB003305 1 MLA r3,r0,r5,r3 false
+Instruction 2471 S:0xC004208E 0xFBA40100 1 UMULL r0,r1,r4,r0 false
+Instruction 2472 S:0xC0042092 0x1859 2 ADDS r1,r3,r1 false
+Instruction 2473 S:0xC0042094 0x9B09 1 LDR r3,[sp,#0x24] false
+Instruction 2474 S:0xC0042096 0x0A80 1 LSRS r0,r0,#10 false
+Instruction 2475 S:0xC0042098 0xEA405081 1 ORR r0,r0,r1,LSL #22 false
+Instruction 2476 S:0xC004209C 0xB123 1 CBZ r3,{pc}+0xc ; 0xc00420a8 true fail
+Instruction 2477 S:0xC004209E 0xF8D83130 7 LDR r3,[r8,#0x130] false
+Instruction 2478 S:0xC00420A2 0x181B 2 ADDS r3,r3,r0 false
+Instruction 2479 S:0xC00420A4 0xF8C83130 1 STR r3,[r8,#0x130] false
+Instruction 2480 S:0xC00420A8 0xB126 1 CBZ r6,{pc}+0xc ; 0xc00420b4 true
+Instruction 2481 S:0xC00420B4 0x1912 8 ADDS r2,r2,r4 false
+Instruction 2482 S:0xC00420B6 0xF8C82134 1 STR r2,[r8,#0x134] false
+Instruction 2483 S:0xC00420BA 0x2F00 0 CMP r7,#0 false
+Instruction 2484 S:0xC00420BC 0xF43FAEE9 1 BEQ {pc}-0x22a ; 0xc0041e92 true fail
+Instruction 2485 S:0xC00420C0 0x4640 1 MOV r0,r8 false
+Instruction 2486 S:0xC00420C2 0xF7FEF903 1 BL {pc}-0x1df6 ; 0xc00402cc true
+Instruction 2487 S:0xC00402CC 0xE92D4FF8 2 PUSH {r3-r11,lr} false
+Instruction 2488 S:0xC00402D0 0xB500 7 PUSH {lr} false
+Instruction 2489 S:0xC00402D2 0xF85DEB04 2 POP {lr} false
+Instruction 2490 S:0xC00402D6 0x4606 0 MOV r6,r0 false
+Instruction 2491 S:0xC00402D8 0xF8D05128 1 LDR r5,[r0,#0x128] false
+Instruction 2492 S:0xC00402DC 0xF8D0A148 2 LDR r10,[r0,#0x148] false
+Instruction 2493 S:0xC00402E0 0x2D00 1 CMP r5,#0 false
+Instruction 2494 S:0xC00402E2 0xD067 0 BEQ {pc}+0xd2 ; 0xc00403b4 true
+Instruction 2495 S:0xC00403B4 0xF8D04134 1 LDR r4,[r0,#0x134] false
+Instruction 2496 S:0xC00403B8 0xF1A00538 0 SUB r5,r0,#0x38 false
+Instruction 2497 S:0xC00403BC 0xF8D08130 1 LDR r8,[r0,#0x130] false
+Instruction 2498 S:0xC00403C0 0x6800 11 LDR r0,[r0,#0] false
+Instruction 2499 S:0xC00403C2 0x3401 0 ADDS r4,#1 false
+Instruction 2500 S:0xC00403C4 0x4621 1 MOV r1,r4 false
+Instruction 2501 S:0xC00403C6 0xFB00F008 2 MUL r0,r0,r8 false
+Instruction 2502 S:0xC00403CA 0xF211F883 1 BL {pc}+0x21110a ; 0xc02514d4 true
+Cycle Count 51 Tracing disabled
+Info Tracing enabled
+Instruction 2503 S:0xC00403CE 0x4B27 1 LDR r3,[pc,#156] ; [0xC004046C] = 0xC0635FF4 false
+Instruction 2504 S:0xC00403D0 0x685A 5 LDR r2,[r3,#4] false
+Instruction 2505 S:0xC00403D2 0x4607 0 MOV r7,r0 false
+Instruction 2506 S:0xC00403D4 0xF8C60148 3 STR r0,[r6,#0x148] false
+Instruction 2507 S:0xC00403D8 0xB98A 1 CBNZ r2,{pc}+0x26 ; 0xc00403fe true fail
+Instruction 2508 S:0xC00403DA 0xEA4F2088 8 LSL r0,r8,#10 false
+Instruction 2509 S:0xC00403DE 0x4621 0 MOV r1,r4 false
+Instruction 2510 S:0xC00403E0 0xF211F878 1 BL {pc}+0x2110f4 ; 0xc02514d4 true
+Cycle Count 125 Tracing disabled
+Info Tracing enabled
+Instruction 2511 S:0xC00403E4 0x4607 1 MOV r7,r0 false
+Instruction 2512 S:0xC00403E6 0xF8C6014C 1 STR r0,[r6,#0x14c] false
+Instruction 2513 S:0xC00403EA 0x4B21 1 LDR r3,[pc,#132] ; [0xC0040470] = 0xC0635FE0 false
+Instruction 2514 S:0xC00403EC 0x685A 3 LDR r2,[r3,#4] false
+Instruction 2515 S:0xC00403EE 0x2A00 2 CMP r2,#0 false
+Instruction 2516 S:0xC00403F0 0xD12E 0 BNE {pc}+0x60 ; 0xc0040450 true fail
+Instruction 2517 S:0xC00403F2 0xF8D60148 1 LDR r0,[r6,#0x148] false
+Instruction 2518 S:0xC00403F6 0xEBCA0000 2 RSB r0,r10,r0 false
+Instruction 2519 S:0xC00403FA 0xE8BD8FF8 1 POP {r3-r11,pc} true
+Instruction 2520 S:0xC00420C6 0xF8D8301C 14 LDR r3,[r8,#0x1c] false
+Instruction 2521 S:0xC00420CA 0xB9CB 2 CBNZ r3,{pc}+0x36 ; 0xc0042100 true
+Instruction 2522 S:0xC0042100 0xE9DA2312 10 LDRD r2,r3,[r10,#0x48] false
+Instruction 2523 S:0xC0042104 0x1812 2 ADDS r2,r2,r0 false
+Instruction 2524 S:0xC0042106 0xEB4373E0 1 ADC r3,r3,r0,ASR #31 false
+Instruction 2525 S:0xC004210A 0xE9CA2312 1 STRD r2,r3,[r10,#0x48] false
+Instruction 2526 S:0xC004210E 0xE6C0 1 B {pc}-0x27c ; 0xc0041e92 true
+Instruction 2527 S:0xC0041E92 0xF8D93084 1 LDR r3,[r9,#0x84] false
+Instruction 2528 S:0xC0041E96 0xF5036390 2 ADD r3,r3,#0x480 false
+Instruction 2529 S:0xC0041E9A 0xE9D32300 3 LDRD r2,r3,[r3,#0] false
+Instruction 2530 S:0xC0041E9E 0xE9C82308 9 STRD r2,r3,[r8,#0x20] false
+Instruction 2531 S:0xC0041EA2 0xF8D92084 1 LDR r2,[r9,#0x84] false
+Instruction 2532 S:0xC0041EA6 0xF8C98030 1 STR r8,[r9,#0x30] false
+Instruction 2533 S:0xC0041EAA 0xF8D83000 1 LDR r3,[r8,#0] false
+Instruction 2534 S:0xC0041EAE 0x6B12 1 LDR r2,[r2,#0x30] false
+Instruction 2535 S:0xC0041EB0 0xEBB20F43 2 CMP r2,r3,LSL #1 false
+Instruction 2536 S:0xC0041EB4 0xE9D8230A 1 LDRD r2,r3,[r8,#0x28] false
+Instruction 2537 S:0xC0041EB8 0xD30E 1 BCC {pc}+0x20 ; 0xc0041ed8 true
+Instruction 2538 S:0xC0041ED8 0xE9C8230E 15 STRD r2,r3,[r8,#0x38] false
+Instruction 2539 S:0xC0041EDC 0xB011 1 ADD sp,sp,#0x44 false
+Instruction 2540 S:0xC0041EDE 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Instruction 2541 S:0xC0042200 0xF8D54128 13 LDR r4,[r5,#0x128] false
+Instruction 2542 S:0xC0042204 0x2C00 2 CMP r4,#0 false
+Instruction 2543 S:0xC0042206 0xD1DB 1 BNE {pc}-0x46 ; 0xc00421c0 true fail
+Instruction 2544 S:0xC0042208 0x4B18 12 LDR r3,[pc,#96] ; [0xC004226C] = 0xC05FC568 false
+Instruction 2545 S:0xC004220A 0x3D38 0 SUBS r5,r5,#0x38 false
+Instruction 2546 S:0xC004220C 0x681B 5 LDR r3,[r3,#0] false
+Instruction 2547 S:0xC004220E 0x061A 3 LSLS r2,r3,#24 false
+Instruction 2548 S:0xC0042210 0xD51A 0 BPL {pc}+0x38 ; 0xc0042248 true
+Instruction 2549 S:0xC0042248 0x4628 8 MOV r0,r5 false
+Instruction 2550 S:0xC004224A 0xBDF8 1 POP {r3-r7,pc} true
+Cycle Count 559 Tracing disabled
+Info Tracing enabled
+Instruction 2551 S:0xC001769C 0xE92D4FF0 1 PUSH {r4-r11,lr} false
+Instruction 2552 S:0xC00176A0 0xB08B 16 SUB sp,sp,#0x2c false
+Instruction 2553 S:0xC00176A2 0xB500 3 PUSH {lr} false
+Instruction 2554 S:0xC00176A4 0xF85DEB04 2 POP {lr} false
+Instruction 2555 S:0xC00176A8 0x4AA2 13 LDR r2,[pc,#648] ; [0xC0017934] = 0xC060B128 false
+Instruction 2556 S:0xC00176AA 0x466B 0 MOV r3,sp false
+Instruction 2557 S:0xC00176AC 0x4606 1 MOV r6,r0 false
+Instruction 2558 S:0xC00176AE 0xF42351FF 0 BIC r1,r3,#0x1fe0 false
+Instruction 2559 S:0xC00176B2 0xF8D03168 1 LDR r3,[r0,#0x168] false
+Instruction 2560 S:0xC00176B6 0xF8D22168 14 LDR r2,[r2,#0x168] false
+Instruction 2561 S:0xC00176BA 0xF021011F 0 BIC r1,r1,#0x1f false
+Instruction 2562 S:0xC00176BE 0x4293 2 CMP r3,r2 false
+Instruction 2563 S:0xC00176C0 0xF8D1A014 1 LDR r10,[r1,#0x14] false
+Instruction 2564 S:0xC00176C4 0xF04081BF 0 BNE.W {pc}+0x382 ; 0xc0017a46 true fail
+Instruction 2565 S:0xC00176C8 0xEE123F30 1 MRC p15,#0x0,r3,c2,c0,#1 false
+Instruction 2566 S:0xC00176CC 0xEE023F10 4 MCR p15,#0x0,r3,c2,c0,#0 false
+Instruction 2567 S:0xC00176D0 0xF3BF8F6F 1 ISB false
+Timestamp Timestamp: 562536962731
+Instruction 2568 S:0xC00176D4 0xF50679B0 12 ADD r9,r6,#0x160 false
+Instruction 2569 S:0xC00176D8 0xE8D9457F 6 LDREXD r4,r5,[r9] false
+Instruction 2570 S:0xC00176DC 0x4F96 3 LDR r7,[pc,#600] ; [0xC0017938] = 0xC06024F8 false
+Instruction 2571 S:0xC00176DE 0xE8D7017F 16 LDREXD r0,r1,[r7] false
+Instruction 2572 S:0xC00176E2 0x4060 2 EORS r0,r0,r4 false
+Instruction 2573 S:0xC00176E4 0x4069 1 EORS r1,r1,r5 false
+Instruction 2574 S:0xC00176E6 0x0A02 1 LSRS r2,r0,#8 false
+Instruction 2575 S:0xC00176E8 0x0A0B 1 LSRS r3,r1,#8 false
+Instruction 2576 S:0xC00176EA 0xEA426201 1 ORR r2,r2,r1,LSL #24 false
+Instruction 2577 S:0xC00176EE 0xEA520003 1 ORRS r0,r2,r3 false
+Instruction 2578 S:0xC00176F2 0xD16A 0 BNE {pc}+0xd8 ; 0xc00177ca true fail
+Instruction 2579 S:0xC00176F4 0xF8DF825C 23 LDR r8,[pc,#604] ; [0xC0017954] = 0xC05FD5C0 false
+Instruction 2580 S:0xC00176F8 0x4B90 1 LDR r3,[pc,#576] ; [0xC001793C] = 0xC05F03B0 false
+Instruction 2581 S:0xC00176FA 0x9302 1 STR r3,[sp,#8] false
+Instruction 2582 S:0xC00176FC 0xF858302A 3 LDR r3,[r8,r10,LSL #2] false
+Instruction 2583 S:0xC0017700 0x9902 6 LDR r1,[sp,#8] false
+Instruction 2584 S:0xC0017702 0x18C9 2 ADDS r1,r1,r3 false
+Instruction 2585 S:0xC0017704 0xF3BF8F5F 1 DMB false
+Instruction 2586 S:0xC0017708 0xE8D1237F 39 LDREXD r2,r3,[r1] false
+Instruction 2587 S:0xC001770C 0xE8C14570 22 STREXD r0,r4,r5,[r1] false
+Instruction 2588 S:0xC0017710 0xF0900F00 2 TEQ r0,#0 false
+Instruction 2589 S:0xC0017714 0xD1F8 0 BNE {pc}-0xc ; 0xc0017708 true fail
+Instruction 2590 S:0xC0017716 0xF3BF8F5F 9 DMB false
+Instruction 2591 S:0xC001771A 0xEA520403 1 ORRS r4,r2,r3 false
+Instruction 2592 S:0xC001771E 0xD12C 1 BNE {pc}+0x5c ; 0xc001777a true
+Instruction 2593 S:0xC001777A 0x6AB0 35 LDR r0,[r6,#0x28] false
+Instruction 2594 S:0xC001777C 0x4631 0 MOV r1,r6 false
+Instruction 2595 S:0xC001777E 0xF1004040 4 ADD r0,r0,#0xc0000000 false
+Instruction 2596 S:0xC0017782 0xB00B 0 ADD sp,sp,#0x2c false
+Instruction 2597 S:0xC0017784 0xE8BD4FF0 3 POP {r4-r11,lr} false
+Instruction 2598 S:0xC0017788 0xF000B99A 5 B.W {pc}+0x338 ; 0xc0017ac0 true
+Instruction 2599 S:0xC0017AC0 0xF04F0200 43 MOV r2,#0 false
+Instruction 2600 S:0xC0017AC4 0xF8D11160 1 LDR r1,[r1,#0x160] false
+Instruction 2601 S:0xC0017AC8 0xF040006A 1 ORR r0,r0,#0x6a false
+Instruction 2602 S:0xC0017ACC 0xEE0D1F30 1 MCR p15,#0x0,r1,c13,c0,#1 false
+Instruction 2603 S:0xC0017AD0 0xF3BF8F6F 1 ISB false
+Timestamp Timestamp: 562536962748
+Instruction 2604 S:0xC0017AD4 0xEE020F10 26 MCR p15,#0x0,r0,c2,c0,#0 false
+Instruction 2605 S:0xC0017AD8 0xF3BF8F6F 1 ISB false
+Timestamp Timestamp: 562536962750
+Instruction 2606 S:0xC0017ADC 0x46F7 12 MOV pc,lr true
+Cycle Count 79 Tracing disabled
+Info Tracing enabled
+Instruction 2607 S:0xC000CCF8 0xF1010C1C 1 ADD r12,r1,#0x1c false
+Instruction 2608 S:0xC000CCFC 0x6E13 14 LDR r3,[r2,#0x60] false
+Instruction 2609 S:0xC000CCFE 0xE8AC0FF0 6 STM r12!,{r4-r11} false
+Instruction 2610 S:0xC000CD02 0xF84CDB04 10 STR sp,[r12],#4 false
+Instruction 2611 S:0xC000CD06 0xF84CEB04 3 STR lr,[r12],#4 false
+Instruction 2612 S:0xC000CD0A 0xEE0D3F70 1 MCR p15,#0x0,r3,c13,c0,#3 false
+Instruction 2613 S:0xC000CD0E 0xF04F0400 1 MOV r4,#0 false
+Instruction 2614 S:0xC000CD12 0xEE0D4F50 1 MCR p15,#0x0,r4,c13,c0,#2 false
+Instruction 2615 S:0xC000CD16 0x4605 1 MOV r5,r0 false
+Instruction 2616 S:0xC000CD18 0xF102041C 0 ADD r4,r2,#0x1c false
+Instruction 2617 S:0xC000CD1C 0x4806 18 LDR r0,[pc,#24] ; [0xC000CD38] = 0xC0637C50 false
+Instruction 2618 S:0xC000CD1E 0xF04F0102 0 MOV r1,#2 false
+Instruction 2619 S:0xC000CD22 0xF029FDF7 1 BL {pc}+0x29bf2 ; 0xc0036914 true
+Instruction 2620 S:0xC0036914 0xB510 5 PUSH {r4,lr} false
+Instruction 2621 S:0xC0036916 0xB082 1 SUB sp,sp,#8 false
+Instruction 2622 S:0xC0036918 0xB500 3 PUSH {lr} false
+Instruction 2623 S:0xC003691A 0xF85DEB04 2 POP {lr} false
+Instruction 2624 S:0xC003691E 0x2400 0 MOVS r4,#0 false
+Instruction 2625 S:0xC0036920 0xF04F33FF 6 MOV r3,#0xffffffff false
+Instruction 2626 S:0xC0036924 0x9400 1 STR r4,[sp,#0] false
+Instruction 2627 S:0xC0036926 0xF7FFFFE9 1 BL {pc}-0x2a ; 0xc00368fc true
+Instruction 2628 S:0xC00368FC 0xB510 17 PUSH {r4,lr} false
+Instruction 2629 S:0xC00368FE 0xB082 1 SUB sp,sp,#8 false
+Instruction 2630 S:0xC0036900 0xB500 3 PUSH {lr} false
+Instruction 2631 S:0xC0036902 0xF85DEB04 2 POP {lr} false
+Instruction 2632 S:0xC0036906 0x9C04 3 LDR r4,[sp,#0x10] false
+Instruction 2633 S:0xC0036908 0x9400 1 STR r4,[sp,#0] false
+Instruction 2634 S:0xC003690A 0x3004 0 ADDS r0,#4 false
+Instruction 2635 S:0xC003690C 0xF7FFFFCC 1 BL {pc}-0x64 ; 0xc00368a8 true
+Instruction 2636 S:0xC00368A8 0xE92D41F0 11 PUSH {r4-r8,lr} false
+Instruction 2637 S:0xC00368AC 0xB500 5 PUSH {lr} false
+Instruction 2638 S:0xC00368AE 0xF85DEB04 2 POP {lr} false
+Instruction 2639 S:0xC00368B2 0x461D 0 MOV r5,r3 false
+Instruction 2640 S:0xC00368B4 0x6804 2 LDR r4,[r0,#0] false
+Instruction 2641 S:0xC00368B6 0x460F 0 MOV r7,r1 false
+Instruction 2642 S:0xC00368B8 0x4690 1 MOV r8,r2 false
+Instruction 2643 S:0xC00368BA 0x9E06 1 LDR r6,[sp,#0x18] false
+Instruction 2644 S:0xC00368BC 0x2B00 0 CMP r3,#0 false
+Instruction 2645 S:0xC00368BE 0xBF18 1 IT NE false
+Instruction 2646 S:0xC00368C0 0x2C00 7 CMP r4,#0 false
+Instruction 2647 S:0xC00368C2 0xBF0C 0 ITE EQ false
+Instruction 2648 S:0xC00368C4 0x2000 1 MOVS r0,#0 false fail
+Instruction 2649 S:0xC00368C6 0x2001 0 MOVS r0,#1 false
+Instruction 2650 S:0xC00368C8 0xD10A 1 BNE {pc}+0x18 ; 0xc00368e0 true
+Instruction 2651 S:0xC00368E0 0x6823 15 LDR r3,[r4,#0] false
+Instruction 2652 S:0xC00368E2 0x4620 0 MOV r0,r4 false
+Instruction 2653 S:0xC00368E4 0x4639 1 MOV r1,r7 false
+Instruction 2654 S:0xC00368E6 0x4642 0 MOV r2,r8 false
+Instruction 2655 S:0xC00368E8 0x6864 2 LDR r4,[r4,#4] false
+Instruction 2656 S:0xC00368EA 0x4798 1 BLX r3 true
+Instruction 2657 S:0xC0008C20 0xB538 23 PUSH {r3-r5,lr} false
+Instruction 2658 S:0xC0008C22 0xB500 4 PUSH {lr} false
+Instruction 2659 S:0xC0008C24 0xF85DEB04 2 POP {lr} false
+Instruction 2660 S:0xC0008C28 0x4614 0 MOV r4,r2 false
+Instruction 2661 S:0xC0008C2A 0x2903 1 CMP r1,#3 false
+Instruction 2662 S:0xC0008C2C 0xD816 0 BHI {pc}+0x30 ; 0xc0008c5c true fail
+Instruction 2663 S:0xC0008C2E 0xE8DFF001 21 TBB [pc,r1] true
+Instruction 2664 S:0xC0008C60 0xEEF84A10 23 VMRS r4,FPEXC false
+Instruction 2665 S:0xC0008C64 0x0060 3 LSLS r0,r4,#1 false
+Instruction 2666 S:0xC0008C66 0x6953 12 LDR r3,[r2,#0x14] false
+Instruction 2667 S:0xC0008C68 0xD507 0 BPL {pc}+0x12 ; 0xc0008c7a true
+Instruction 2668 S:0xC0008C7A 0xF0244480 1 BIC r4,r4,#0x40000000 false
+Instruction 2669 S:0xC0008C7E 0xEEE84A10 6 VMSR FPEXC,r4 false
+Instruction 2670 S:0xC0008C82 0x2000 7 MOVS r0,#0 false
+Instruction 2671 S:0xC0008C84 0xBD38 1 POP {r3-r5,pc} true
+Instruction 2672 S:0xC00368EC 0xB116 2 CBZ r6,{pc}+8 ; 0xc00368f4 true
+Instruction 2673 S:0xC00368F4 0x0403 8 LSLS r3,r0,#16 false
+Instruction 2674 S:0xC00368F6 0xD5E9 0 BPL {pc}-0x2a ; 0xc00368cc true
+Instruction 2675 S:0xC00368CC 0x3D01 8 SUBS r5,#1 false
+Instruction 2676 S:0xC00368CE 0xBF0C 0 ITE EQ false
+Instruction 2677 S:0xC00368D0 0x2300 1 MOVS r3,#0 false fail
+Instruction 2678 S:0xC00368D2 0x2301 0 MOVS r3,#1 false
+Instruction 2679 S:0xC00368D4 0x2C00 1 CMP r4,#0 false
+Instruction 2680 S:0xC00368D6 0xBF0C 0 ITE EQ false
+Instruction 2681 S:0xC00368D8 0x2300 1 MOVS r3,#0 false
+Instruction 2682 S:0xC00368DA 0xF0030301 1 AND r3,r3,#1 false fail
+Instruction 2683 S:0xC00368DE 0xB15B 1 CBZ r3,{pc}+0x1a ; 0xc00368f8 true
+Instruction 2684 S:0xC00368F8 0xE8BD81F0 2 POP {r4-r8,pc} true
+Instruction 2685 S:0xC0036910 0xB002 3 ADD sp,sp,#8 false
+Instruction 2686 S:0xC0036912 0xBD10 3 POP {r4,pc} true
+Instruction 2687 S:0xC003692A 0xB002 1 ADD sp,sp,#8 false
+Instruction 2688 S:0xC003692C 0xBD10 3 POP {r4,pc} true
+Instruction 2689 S:0xC000CD26 0x46A4 2 MOV r12,r4 false
+Instruction 2690 S:0xC000CD28 0x4628 1 MOV r0,r5 false
+Instruction 2691 S:0xC000CD2A 0xE8BC0FF0 2 LDM r12!,{r4-r11} false
+Instruction 2692 S:0xC000CD2E 0xF85CDB04 7 LDR sp,[r12],#4 false
+Instruction 2693 S:0xC000CD32 0xF8DCF000 3 LDR pc,[r12,#0] true
+Cycle Count 28 Tracing disabled
+Info Tracing enabled
+Instruction 2694 S:0xC003AC6C 0xB5F0 1 PUSH {r4-r7,lr} false
+Instruction 2695 S:0xC003AC6E 0xB083 3 SUB sp,sp,#0xc false
+Instruction 2696 S:0xC003AC70 0xAF00 1 ADD r7,sp,#0 false
+Instruction 2697 S:0xC003AC72 0xB500 2 PUSH {lr} false
+Instruction 2698 S:0xC003AC74 0xF85DEB04 2 POP {lr} false
+Instruction 2699 S:0xC003AC78 0x4B2E 14 LDR r3,[pc,#184] ; [0xC003AD34] = 0xC05FD380 false
+Instruction 2700 S:0xC003AC7A 0x460E 0 MOV r6,r1 false
+Instruction 2701 S:0xC003AC7C 0x466A 1 MOV r2,sp false
+Instruction 2702 S:0xC003AC7E 0xF8D04470 5 LDR r4,[r0,#0x470] false
+Instruction 2703 S:0xC003AC82 0xF42251FF 0 BIC r1,r2,#0x1fe0 false
+Instruction 2704 S:0xC003AC86 0x2200 1 MOVS r2,#0 false
+Instruction 2705 S:0xC003AC88 0xF021011F 0 BIC r1,r1,#0x1f false
+Instruction 2706 S:0xC003AC8C 0xF8C02470 2 STR r2,[r0,#0x470] false
+Instruction 2707 S:0xC003AC90 0x6832 3 LDR r2,[r6,#0] false
+Instruction 2708 S:0xC003AC92 0x4605 0 MOV r5,r0 false
+Instruction 2709 S:0xC003AC94 0x681B 3 LDR r3,[r3,#0] false
+Instruction 2710 S:0xC003AC96 0x68C9 3 LDR r1,[r1,#0xc] false
+Instruction 2711 S:0xC003AC98 0x2B00 1 CMP r3,#0 false
+Instruction 2712 S:0xC003AC9A 0xD125 0 BNE {pc}+0x4e ; 0xc003ace8 true fail
+Instruction 2713 S:0xC003AC9C 0xF3BF8F5F 63 DMB false
+Instruction 2714 S:0xC003ACA0 0x2300 1 MOVS r3,#0 false
+Instruction 2715 S:0xC003ACA2 0x61B3 1 STR r3,[r6,#0x18] false
+Instruction 2716 S:0xC003ACA4 0xF3BF8F5F 1 DMB false
+Instruction 2717 S:0xC003ACA8 0x882B 57 LDRH r3,[r5,#0] false
+Instruction 2718 S:0xC003ACAA 0x3301 2 ADDS r3,#1 false
+Instruction 2719 S:0xC003ACAC 0x802B 1 STRH r3,[r5,#0] false
+Instruction 2720 S:0xC003ACAE 0xF3BF8F4F 31 DSB false
+Instruction 2721 S:0xC003ACB2 0xF3AF8004 1 SEV.W false
+Instruction 2722 S:0xC003ACB6 0xB662 1 CPSIE i false
+Instruction 2723 S:0xC003ACB8 0xB184 1 CBZ r4,{pc}+0x24 ; 0xc003acdc true
+Instruction 2724 S:0xC003ACDC 0x2A40 1 CMP r2,#0x40 false
+Instruction 2725 S:0xC003ACDE 0xD009 0 BEQ {pc}+0x16 ; 0xc003acf4 true fail
+Instruction 2726 S:0xC003ACE0 0xF107070C 8 ADD r7,r7,#0xc false
+Instruction 2727 S:0xC003ACE4 0x46BD 1 MOV sp,r7 false
+Instruction 2728 S:0xC003ACE6 0xBDF0 3 POP {r4-r7,pc} true
+Cycle Count 75 Tracing disabled
+Info Tracing enabled
+Instruction 2729 S:0xC000F72E 0xB672 1 CPSID i false
+Instruction 2730 S:0xC000F730 0x6821 1 LDR r1,[r4,#0] false
+Instruction 2731 S:0xC000F732 0x0748 3 LSLS r0,r1,#29 false
+Instruction 2732 S:0xC000F734 0xD1F5 1 BNE {pc}-0x12 ; 0xc000f722 true fail
+Instruction 2733 S:0xC000F736 0x2000 15 MOVS r0,#0 false
+Instruction 2734 S:0xC000F738 0xE8BD81F0 1 POP {r4-r8,pc} true
+Instruction 2735 S:0xC000CD92 0x2800 11 CMP r0,#0 false
+Instruction 2736 S:0xC000CD94 0xF000800E 0 BEQ.W {pc}+0x20 ; 0xc000cdb4 true
+Instruction 2737 S:0xC000CDB4 0xF3BF8F2F 19 CLREX false
+Instruction 2738 S:0xC000CDB8 0x466A 1 MOV r2,sp false
+Instruction 2739 S:0xC000CDBA 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 2740 S:0xC000CDBE 0xF083030C 66 EOR r3,r3,#0xc false
+Instruction 2741 S:0xC000CDC2 0xF3838100 3 MSR CPSR_c,r3 false
+Instruction 2742 S:0xC000CDC6 0xF8D2D034 16 LDR sp,[r2,#0x34] false
+Instruction 2743 S:0xC000CDCA 0xF8D2E038 1 LDR lr,[r2,#0x38] false
+Instruction 2744 S:0xC000CDCE 0xF083030C 0 EOR r3,r3,#0xc false
+Instruction 2745 S:0xC000CDD2 0xF3838100 3 MSR CPSR_c,r3 false
+Instruction 2746 S:0xC000CDD6 0x9910 5 LDR r1,[sp,#0x40] false
+Instruction 2747 S:0xC000CDD8 0xF8DDE03C 1 LDR lr,[sp,#0x3c] false
+Instruction 2748 S:0xC000CDDC 0xB00D 0 ADD sp,sp,#0x34 false
+Instruction 2749 S:0xC000CDDE 0xF3918F00 2 MSR SPSR_cxsf,r1 false
+Instruction 2750 S:0xC000CDE2 0xE91D1FFF 5 LDMDB sp,{r0-r12} false
+Instruction 2751 S:0xC000CDE6 0xB005 7 ADD sp,sp,#0x14 false
+Instruction 2752 S:0xC000CDE8 0xF3DE8F00 1 SUBS pc,lr,#0 true
+Info Return from exception
+Timestamp Timestamp: 562536962810
+Cycle Count 193 Tracing disabled
+Info Tracing enabled
+Instruction 2753 S:0xC000CB00 0xB092 1 SUB sp,sp,#0x48 false
+Timestamp Timestamp: 562536962823
+Instruction 2754 S:0xC000CB02 0xE88D1FFF 3 STM sp,{r0-r12} false
+Instruction 2755 S:0xC000CB06 0xE8900038 26 LDM r0,{r3-r5} false
+Instruction 2756 S:0xC000CB0A 0xA80F 3 ADD r0,sp,#0x3c false
+Instruction 2757 S:0xC000CB0C 0xF04F36FF 0 MOV r6,#0xffffffff false
+Instruction 2758 S:0xC000CB10 0x9300 1 STR r3,[sp,#0] false
+Instruction 2759 S:0xC000CB12 0xE8800070 2 STM r0,{r4-r6} false
+Instruction 2760 S:0xC000CB16 0xF3EF8100 2 MRS r1,APSR ; formerly CPSR false
+Instruction 2761 S:0xC000CB1A 0xF081010C 2 EOR r1,r1,#0xc false
+Instruction 2762 S:0xC000CB1E 0xF3818100 3 MSR CPSR_c,r1 false
+Instruction 2763 S:0xC000CB22 0xF840DC08 5 STR sp,[r0,#-8] false
+Instruction 2764 S:0xC000CB26 0xF840EC04 1 STR lr,[r0,#-4] false
+Instruction 2765 S:0xC000CB2A 0xF081010C 0 EOR r1,r1,#0xc false
+Instruction 2766 S:0xC000CB2E 0xF3818100 3 MSR CPSR_c,r1 false
+Instruction 2767 S:0xC000CB32 0xF85F0114 18 LDR r0,[pc,#-276] ; [0xC000CA20] = 0xC06013D4 false
+Instruction 2768 S:0xC000CB36 0x6800 5 LDR r0,[r0,#0] false
+Instruction 2769 S:0xC000CB38 0xEE010F10 1 MCR p15,#0x0,r0,c1,c0,#0 false
+Instruction 2770 S:0xC000CB3C 0x4622 6 MOV r2,r4 false
+Instruction 2771 S:0xC000CB3E 0x462B 0 MOV r3,r5 false
+Instruction 2772 S:0xC000CB40 0xF20F19A1 1 ADR.W r9,{pc}+0x1a5 ; 0xc000cce5 false
+Instruction 2773 S:0xC000CB44 0xF0130F20 0 TST r3,#0x20 false
+Instruction 2774 S:0xC000CB48 0xF0408008 1 BNE.W {pc}+0x14 ; 0xc000cb5c true fail
+Instruction 2775 S:0xC000CB4C 0xF1A20404 16 SUB r4,r2,#4 false
+Instruction 2776 S:0xC000CB50 0xF8540E00 112 LDRT r0,[r4,#0] false
+Instruction 2777 S:0xC000CB54 0xF20F1E2B 0 ADR.W lr,{pc}+0x12f ; 0xc000cc83 false
+Instruction 2778 S:0xC000CB58 0xF000B818 1 B.W {pc}+0x34 ; 0xc000cb8c true
+Instruction 2779 S:0xC000CB8C 0x46EA 3 MOV r10,sp false
+Instruction 2780 S:0xC000CB8E 0xEA4F3A5A 2 LSR r10,r10,#13 false
+Instruction 2781 S:0xC000CB92 0xEA4F3A4A 2 LSL r10,r10,#13 false
+Instruction 2782 S:0xC000CB96 0xA62A 0 ADR r6,{pc}+0xaa ; 0xc000cc40 false
+Instruction 2783 S:0xC000CB98 0xF8565B04 58 LDR r5,[r6],#4 false
+Instruction 2784 S:0xC000CB9C 0xF8567B04 3 LDR r7,[r6],#4 false
+Instruction 2785 S:0xC000CBA0 0x2D00 1 CMP r5,#0 false
+Instruction 2786 S:0xC000CBA2 0xD00B 0 BEQ {pc}+0x1a ; 0xc000cbbc true fail
+Instruction 2787 S:0xC000CBA4 0xEA000805 1 AND r8,r0,r5 false
+Instruction 2788 S:0xC000CBA8 0x45B8 1 CMP r8,r7 false
+Instruction 2789 S:0xC000CBAA 0xD1F5 0 BNE {pc}-0x12 ; 0xc000cb98 true
+Instruction 2790 S:0xC000CB98 0xF8565B04 11 LDR r5,[r6],#4 false
+Instruction 2791 S:0xC000CB9C 0xF8567B04 3 LDR r7,[r6],#4 false
+Instruction 2792 S:0xC000CBA0 0x2D00 1 CMP r5,#0 false
+Instruction 2793 S:0xC000CBA2 0xD00B 0 BEQ {pc}+0x1a ; 0xc000cbbc true fail
+Instruction 2794 S:0xC000CBA4 0xEA000805 1 AND r8,r0,r5 false
+Instruction 2795 S:0xC000CBA8 0x45B8 1 CMP r8,r7 false
+Instruction 2796 S:0xC000CBAA 0xD1F5 0 BNE {pc}-0x12 ; 0xc000cb98 true
+Instruction 2797 S:0xC000CB98 0xF8565B04 21 LDR r5,[r6],#4 false
+Instruction 2798 S:0xC000CB9C 0xF8567B04 3 LDR r7,[r6],#4 false
+Instruction 2799 S:0xC000CBA0 0x2D00 1 CMP r5,#0 false
+Instruction 2800 S:0xC000CBA2 0xD00B 0 BEQ {pc}+0x1a ; 0xc000cbbc true
+Instruction 2801 S:0xC000CBBC 0xF0106F00 8 TST r0,#0x8000000 false
+Instruction 2802 S:0xC000CBC0 0xBF14 1 ITE NE false
+Instruction 2803 S:0xC000CBC2 0xF0106F80 1 TST r0,#0x4000000 false
+Instruction 2804 S:0xC000CBC6 0x46F7 1 MOV pc,lr true fail
+Instruction 2805 S:0xC000CBC8 0xF4006870 1 AND r8,r0,#0xf00 false
+Instruction 2806 S:0xC000CBCC 0xEA4F2818 2 LSR r8,r8,#8 false
+Instruction 2807 S:0xC000CBD0 0xF04F0701 0 MOV r7,#1 false
+Instruction 2808 S:0xC000CBD4 0xF10A0650 1 ADD r6,r10,#0x50 false
+Instruction 2809 S:0xC000CBD8 0xF8067008 3 STRB r7,[r6,r8] false
+Instruction 2810 S:0xC000CBDC 0xEA4F0888 1 LSL r8,r8,#2 false
+Instruction 2811 S:0xC000CBE0 0x44C7 9 ADD pc,pc,r8 true
+Instruction 2812 S:0xC000CC0C 0xF7FCB906 42 B {pc}-0x3df0 ; 0xc0008e1c true
+Instruction 2813 S:0xC0008E1C 0xB662 3 CPSIE i false
+Instruction 2814 S:0xC0008E1E 0x4C04 19 LDR r4,[pc,#16] ; [0xC0008E30] = 0xC0601098 false
+Instruction 2815 S:0xC0008E20 0xF8DAB014 4 LDR r11,[r10,#0x14] false
+Instruction 2816 S:0xC0008E24 0xF10A0AF8 0 ADD r10,r10,#0xf8 false
+Instruction 2817 S:0xC0008E28 0xF8D4F000 1 LDR pc,[r4,#0] true
+Instruction 2818 S:0xC0008E34 0xEEF81A10 9 VMRS r1,FPEXC false
+Instruction 2819 S:0xC0008E38 0xF0114F80 2 TST r1,#0x40000000 false
+Instruction 2820 S:0xC0008E3C 0xF040803A 0 BNE.W {pc}+0x78 ; 0xc0008eb4 true fail
+Instruction 2821 S:0xC0008E40 0x4B31 25 LDR r3,[pc,#196] ; [0xC0008F08] = 0xC0637B9C false
+Instruction 2822 S:0xC0008E42 0xF0414180 0 ORR r1,r1,#0x40000000 false
+Instruction 2823 S:0xC0008E46 0xF853402B 61 LDR r4,[r3,r11,LSL #2] false
+Instruction 2824 S:0xC0008E4A 0xF0214500 0 BIC r5,r1,#0x80000000 false
+Instruction 2825 S:0xC0008E4E 0x4554 2 CMP r4,r10 false
+Instruction 2826 S:0xC0008E50 0xF0408006 0 BNE.W {pc}+0x10 ; 0xc0008e60 true fail
+Instruction 2827 S:0xC0008E54 0xF8DAC110 68 LDR r12,[r10,#0x110] false
+Instruction 2828 S:0xC0008E58 0xEA9C0F0B 2 TEQ r12,r11 false
+Instruction 2829 S:0xC0008E5C 0xF0008020 0 BEQ.W {pc}+0x44 ; 0xc0008ea0 true
+Instruction 2830 S:0xC0008EA0 0xF0114F00 2 TST r1,#0x80000000 false
+Instruction 2831 S:0xC0008EA4 0xF0408011 0 BNE.W {pc}+0x26 ; 0xc0008eca true fail
+Instruction 2832 S:0xC0008EA8 0xEEE81A10 1 VMSR FPEXC,r1 false
+Instruction 2833 S:0xC0008EAC 0xF1A20204 7 SUB r2,r2,#4 false
+Instruction 2834 S:0xC0008EB0 0x920F 3 STR r2,[sp,#0x3c] false
+Instruction 2835 S:0xC0008EB2 0x46CF 1 MOV pc,r9 true
+Instruction 2836 S:0xC000CCE4 0x46E9 16 MOV r9,sp false
+Instruction 2837 S:0xC000CCE6 0xEA4F3959 2 LSR r9,r9,#13 false
+Instruction 2838 S:0xC000CCEA 0xEA4F3949 2 LSL r9,r9,#13 false
+Timestamp Timestamp: 562536962867
+Instruction 2839 S:0xC000CCEE 0xF04F0800 1 MOV r8,#0 false
+Instruction 2840 S:0xC000CCF2 0xF000B857 0 B.W {pc}+0xb2 ; 0xc000cda4 true
+Instruction 2841 S:0xC000CDA4 0xB672 1 CPSID i false
+Instruction 2842 S:0xC000CDA6 0xBF00 1 NOP false
+Instruction 2843 S:0xC000CDA8 0xF8D91000 1 LDR r1,[r9,#0] false
+Instruction 2844 S:0xC000CDAC 0xF0110F07 2 TST r1,#7 false
+Instruction 2845 S:0xC000CDB0 0xF47FAFEB 0 BNE.W {pc}-0x26 ; 0xc000cd8a true fail
+Instruction 2846 S:0xC000CDB4 0xF3BF8F2F 1 CLREX false
+Instruction 2847 S:0xC000CDB8 0x466A 1 MOV r2,sp false
+Instruction 2848 S:0xC000CDBA 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 2849 S:0xC000CDBE 0xF083030C 2 EOR r3,r3,#0xc false
+Instruction 2850 S:0xC000CDC2 0xF3838100 3 MSR CPSR_c,r3 false
+Instruction 2851 S:0xC000CDC6 0xF8D2D034 5 LDR sp,[r2,#0x34] false
+Instruction 2852 S:0xC000CDCA 0xF8D2E038 1 LDR lr,[r2,#0x38] false
+Instruction 2853 S:0xC000CDCE 0xF083030C 0 EOR r3,r3,#0xc false
+Instruction 2854 S:0xC000CDD2 0xF3838100 3 MSR CPSR_c,r3 false
+Instruction 2855 S:0xC000CDD6 0x9910 5 LDR r1,[sp,#0x40] false
+Instruction 2856 S:0xC000CDD8 0xF8DDE03C 1 LDR lr,[sp,#0x3c] false
+Instruction 2857 S:0xC000CDDC 0xB00D 0 ADD sp,sp,#0x34 false
+Instruction 2858 S:0xC000CDDE 0xF3918F00 2 MSR SPSR_cxsf,r1 false
+Instruction 2859 S:0xC000CDE2 0xE91D1FFF 5 LDMDB sp,{r0-r12} false
+Instruction 2860 S:0xC000CDE6 0xB005 7 ADD sp,sp,#0x14 false
+Instruction 2861 S:0xC000CDE8 0xF3DE8F00 1 SUBS pc,lr,#0 true
+Info Return from exception
+Timestamp Timestamp: 562536962870
+Cycle Count 301997 Tracing disabled
+Info Tracing enabled
+Instruction 2862 S:0xC000CAA0 0xB092 1 SUB sp,sp,#0x48 false
+Timestamp Timestamp: 562536983623
+Instruction 2863 S:0xC000CAA2 0xE88D1FFF 6 STM sp,{r0-r12} false
+Instruction 2864 S:0xC000CAA6 0xE8900038 11 LDM r0,{r3-r5} false
+Instruction 2865 S:0xC000CAAA 0xA80F 2 ADD r0,sp,#0x3c false
+Instruction 2866 S:0xC000CAAC 0xF04F36FF 0 MOV r6,#0xffffffff false
+Instruction 2867 S:0xC000CAB0 0x9300 1 STR r3,[sp,#0] false
+Instruction 2868 S:0xC000CAB2 0xE8800070 2 STM r0,{r4-r6} false
+Instruction 2869 S:0xC000CAB6 0xF3EF8100 2 MRS r1,APSR ; formerly CPSR false
+Instruction 2870 S:0xC000CABA 0xF081010C 2 EOR r1,r1,#0xc false
+Instruction 2871 S:0xC000CABE 0xF3818100 3 MSR CPSR_c,r1 false
+Instruction 2872 S:0xC000CAC2 0xF840DC08 5 STR sp,[r0,#-8] false
+Instruction 2873 S:0xC000CAC6 0xF840EC04 1 STR lr,[r0,#-4] false
+Instruction 2874 S:0xC000CACA 0xF081010C 0 EOR r1,r1,#0xc false
+Instruction 2875 S:0xC000CACE 0xF3818100 3 MSR CPSR_c,r1 false
+Instruction 2876 S:0xC000CAD2 0xF85F00B4 7 LDR r0,[pc,#-180] ; [0xC000CA20] = 0xC06013D4 false
+Instruction 2877 S:0xC000CAD6 0x6800 17 LDR r0,[r0,#0] false
+Instruction 2878 S:0xC000CAD8 0xEE010F10 1 MCR p15,#0x0,r0,c1,c0,#0 false
+Instruction 2879 S:0xC000CADC 0x4907 16 LDR r1,[pc,#28] ; [0xC000CAFC] = 0xC06013DC false
+Instruction 2880 S:0xC000CADE 0x4668 0 MOV r0,sp false
+Instruction 2881 S:0xC000CAE0 0xF20F0E05 1 ADR.W lr,{pc}+9 ; 0xc000cae9 false
+Instruction 2882 S:0xC000CAE4 0xF8D1F000 2 LDR pc,[r1,#0] true
+Instruction 2883 S:0xC00083D0 0xE92D41F0 22 PUSH {r4-r8,lr} false
+Instruction 2884 S:0xC00083D4 0xB500 5 PUSH {lr} false
+Instruction 2885 S:0xC00083D6 0xF004FD19 1 BL {pc}+0x4a36 ; 0xc000ce0c true
+Instruction 2886 S:0xC000CE0C 0x46F4 36 MOV r12,lr false
+Instruction 2887 S:0xC000CE0E 0xF85DEB04 1 POP {lr} false
+Instruction 2888 S:0xC000CE12 0x46E7 1 MOV pc,r12 true
+Instruction 2889 S:0xC00083DA 0x4607 28 MOV r7,r0 false
+Instruction 2890 S:0xC00083DC 0x4E0F 13 LDR r6,[pc,#60] ; [0xC000841C] = 0xC05FD730 false
+Instruction 2891 S:0xC00083DE 0xF8D6800C 17 LDR r8,[r6,#0xc] false
+Instruction 2892 S:0xC00083E2 0xF108040C 2 ADD r4,r8,#0xc false
+Instruction 2893 S:0xC00083E6 0xE006 1 B {pc}+0x10 ; 0xc00083f6 true
+Instruction 2894 S:0xC00083F6 0x6822 26 LDR r2,[r4,#0] false
+Instruction 2895 S:0xC00083F8 0xF42250E0 2 BIC r0,r2,#0x1c00 false
+Instruction 2896 S:0xC00083FC 0xF1A00510 1 SUB r5,r0,#0x10 false
+Instruction 2897 S:0xC0008400 0x4601 0 MOV r1,r0 false
+Instruction 2898 S:0xC0008402 0xF5B57F7B 1 CMP r5,#0x3ec false
+Instruction 2899 S:0xC0008406 0xD9EF 0 BLS {pc}-0x1e ; 0xc00083e8 true
+Instruction 2900 S:0xC00083E8 0xF8D60594 19 LDR r0,[r6,#0x594] false
+Instruction 2901 S:0xC00083EC 0xF065FB40 0 BL {pc}+0x65684 ; 0xc006da70 true
+Cycle Count 218 Tracing disabled
+Info Tracing enabled
+Instruction 2902 S:0xC00083F0 0x4639 1 MOV r1,r7 false
+Instruction 2903 S:0xC00083F2 0xF005F8F7 0 BL {pc}+0x51f2 ; 0xc000d5e4 true
+Instruction 2904 S:0xC000D5E4 0xB570 21 PUSH {r4-r6,lr} false
+Instruction 2905 S:0xC000D5E6 0xB500 4 PUSH {lr} false
+Instruction 2906 S:0xC000D5E8 0xF85DEB04 2 POP {lr} false
+Instruction 2907 S:0xC000D5EC 0x4605 0 MOV r5,r0 false
+Instruction 2908 S:0xC000D5EE 0x4C12 22 LDR r4,[pc,#72] ; [0xC000D638] = 0xC05F1F34 false
+Instruction 2909 S:0xC000D5F0 0xEE1D2F90 1 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 2910 S:0xC000D5F4 0x4623 1 MOV r3,r4 false
+Instruction 2911 S:0xC000D5F6 0x58D6 15 LDR r6,[r2,r3] false
+Instruction 2912 S:0xC000D5F8 0x50D1 3 STR r1,[r2,r3] false
+Instruction 2913 S:0xC000D5FA 0xF013FDBF 0 BL {pc}+0x13b82 ; 0xc002117c true
+Instruction 2914 S:0xC002117C 0xB538 1 PUSH {r3-r5,lr} false
+Instruction 2915 S:0xC002117E 0xB500 4 PUSH {lr} false
+Instruction 2916 S:0xC0021180 0xF85DEB04 16 POP {lr} false
+Instruction 2917 S:0xC0021184 0x466B 1 MOV r3,sp false
+Instruction 2918 S:0xC0021186 0xF42354FF 1 BIC r4,r3,#0x1fe0 false
+Instruction 2919 S:0xC002118A 0xF024041F 1 BIC r4,r4,#0x1f false
+Instruction 2920 S:0xC002118E 0x6965 5 LDR r5,[r4,#0x14] false
+Instruction 2921 S:0xC0021190 0xF04EFFCE 0 BL {pc}+0x4efa0 ; 0xc0070130 true
+Cycle Count 132 Tracing disabled
+Info Tracing enabled
+Instruction 2922 S:0xC0021194 0x68E3 1 LDR r3,[r4,#0xc] false
+Instruction 2923 S:0xC0021196 0xF8D33240 32 LDR r3,[r3,#0x240] false
+Instruction 2924 S:0xC002119A 0xB92B 2 CBNZ r3,{pc}+0xe ; 0xc00211a8 true
+Instruction 2925 S:0xC00211A8 0x6863 8 LDR r3,[r4,#4] false
+Instruction 2926 S:0xC00211AA 0xF5033380 2 ADD r3,r3,#0x10000 false
+Instruction 2927 S:0xC00211AE 0x6063 1 STR r3,[r4,#4] false
+Instruction 2928 S:0xC00211B0 0xBD38 1 POP {r3-r5,pc} true
+Instruction 2929 S:0xC000D5FE 0x4B0F 2 LDR r3,[pc,#60] ; [0xC000D63C] = 0xC0608914 false
+Instruction 2930 S:0xC000D600 0x681B 17 LDR r3,[r3,#0] false
+Instruction 2931 S:0xC000D602 0x42AB 2 CMP r3,r5 false
+Instruction 2932 S:0xC000D604 0xD909 0 BLS {pc}+0x16 ; 0xc000d61a true fail
+Instruction 2933 S:0xC000D606 0x4628 1 MOV r0,r5 false
+Instruction 2934 S:0xC000D608 0xF05DF91A 0 BL {pc}+0x5d238 ; 0xc006a840 true
+Timestamp Timestamp: 562536983677
+Cycle Count 725 Tracing disabled
+Info Tracing enabled
+Instruction 2935 S:0xC0035900 0xE92D4FF0 1 PUSH {r4-r11,lr} false
+Instruction 2936 S:0xC0035904 0xB091 7 SUB sp,sp,#0x44 false
+Instruction 2937 S:0xC0035906 0xB500 3 PUSH {lr} false
+Instruction 2938 S:0xC0035908 0xF85DEB04 2 POP {lr} false
+Instruction 2939 S:0xC003590C 0x4986 13 LDR r1,[pc,#536] ; [0xC0035B28] false
+Instruction 2940 S:0xC003590E 0xEE1D3F90 1 MRC p15,#0x0,r3,c13,c0,#4 false
+Instruction 2941 S:0xC0035912 0xEB030A01 4 ADD r10,r3,r1 false
+Instruction 2942 S:0xC0035916 0x930B 1 STR r3,[sp,#0x2c] false
+Instruction 2943 S:0xC0035918 0x4602 0 MOV r2,r0 false
+Instruction 2944 S:0xC003591A 0x9105 1 STR r1,[sp,#0x14] false
+Instruction 2945 S:0xC003591C 0xF8DA3018 57 LDR r3,[r10,#0x18] false
+Instruction 2946 S:0xC0035920 0x2B00 2 CMP r3,#0 false
+Instruction 2947 S:0xC0035922 0xF00080F9 0 BEQ.W {pc}+0x1f6 ; 0xc0035b18 true fail
+Instruction 2948 S:0xC0035926 0xF8DA3020 1 LDR r3,[r10,#0x20] false
+Instruction 2949 S:0xC003592A 0x4650 0 MOV r0,r10 false
+Instruction 2950 S:0xC003592C 0xF04F34FF 1 MOV r4,#0xffffffff false
+Instruction 2951 S:0xC0035930 0xF06F4500 0 MVN r5,#0x80000000 false
+Instruction 2952 S:0xC0035934 0x3301 1 ADDS r3,#1 false
+Instruction 2953 S:0xC0035936 0xF8CA3020 1 STR r3,[r10,#0x20] false
+Instruction 2954 S:0xC003593A 0xE9C24504 1 STRD r4,r5,[r2,#0x10] false
+Instruction 2955 S:0xC003593E 0xF50A7388 1 ADD r3,r10,#0x110 false
+Instruction 2956 S:0xC0035942 0xF10A01A0 0 ADD r1,r10,#0xa0 false
+Instruction 2957 S:0xC0035946 0x930A 1 STR r3,[sp,#0x28] false
+Instruction 2958 S:0xC0035948 0x9108 1 STR r1,[sp,#0x20] false
+Instruction 2959 S:0xC003594A 0xF10A01D8 0 ADD r1,r10,#0xd8 false
+Instruction 2960 S:0xC003594E 0x9109 1 STR r1,[sp,#0x24] false
+Instruction 2961 S:0xC0035950 0xF3AEFE32 0 BL {pc}+0x3aec68 ; 0xc03e45b8 true
+Cycle Count 49 Tracing disabled
+Info Tracing enabled
+Instruction 2962 S:0xC0035954 0xA908 1 ADD r1,sp,#0x20 false
+Instruction 2963 S:0xC0035956 0xA80C 0 ADD r0,sp,#0x30 false
+Instruction 2964 S:0xC0035958 0xF04F0B01 1 MOV r11,#1 false
+Instruction 2965 S:0xC003595C 0xC90E 23 LDM r1,{r1-r3} false
+Instruction 2966 S:0xC003595E 0xF01BFAA9 4 BL {pc}+0x1b556 ; 0xc0050eb4 true
+Instruction 2967 S:0xC0050EB4 0xE92D4FF0 1 PUSH {r4-r11,lr} false
+Instruction 2968 S:0xC0050EB8 0xB089 7 SUB sp,sp,#0x24 false
+Instruction 2969 S:0xC0050EBA 0xB500 3 PUSH {lr} false
+Instruction 2970 S:0xC0050EBC 0xF85DEB04 2 POP {lr} false
+Instruction 2971 S:0xC0050EC0 0x4D36 22 LDR r5,[pc,#216] ; [0xC0050F9C] false
+Instruction 2972 S:0xC0050EC2 0x4682 0 MOV r10,r0 false
+Instruction 2973 S:0xC0050EC4 0x468B 1 MOV r11,r1 false
+Instruction 2974 S:0xC0050EC6 0x4690 0 MOV r8,r2 false
+Instruction 2975 S:0xC0050EC8 0x462C 1 MOV r4,r5 false
+Instruction 2976 S:0xC0050ECA 0x4699 0 MOV r9,r3 false
+Instruction 2977 S:0xC0050ECC 0xF8D56090 28 LDR r6,[r5,#0x90] false
+Instruction 2978 S:0xC0050ED0 0x07F0 3 LSLS r0,r6,#31 false
+Instruction 2979 S:0xC0050ED2 0xD462 0 BMI {pc}+0xc8 ; 0xc0050f9a true fail
+Instruction 2980 S:0xC0050ED4 0xF3BF8F5F 1 DMB false
+Instruction 2981 S:0xC0050ED8 0x6827 37 LDR r7,[r4,#0] false
+Instruction 2982 S:0xC0050EDA 0x6BA2 3 LDR r2,[r4,#0x38] false
+Instruction 2983 S:0xC0050EDC 0x4638 1 MOV r0,r7 false
+Instruction 2984 S:0xC0050EDE 0x683B 3 LDR r3,[r7,#0] false
+Instruction 2985 S:0xC0050EE0 0x9205 3 STR r2,[sp,#0x14] false
+Instruction 2986 S:0xC0050EE2 0x4798 1 BLX r3 true
+Timestamp Timestamp: 562536983747
+Cycle Count 52 Tracing disabled
+Info Tracing enabled
+Instruction 2987 S:0xC0050EE4 0xE9D72302 1 LDRD r2,r3,[r7,#8] false
+Instruction 2988 S:0xC0050EE8 0xF8D4C044 1 LDR r12,[r4,#0x44] false
+Instruction 2989 S:0xC0050EEC 0xE9CD2306 1 STRD r2,r3,[sp,#0x18] false
+Instruction 2990 S:0xC0050EF0 0xE9D72304 1 LDRD r2,r3,[r7,#0x10] false
+Instruction 2991 S:0xC0050EF4 0x6C27 1 LDR r7,[r4,#0x40] false
+Instruction 2992 S:0xC0050EF6 0xE9CD2300 1 STRD r2,r3,[sp,#0] false
+Instruction 2993 S:0xC0050EFA 0xE9D42318 1 LDRD r2,r3,[r4,#0x60] false
+Instruction 2994 S:0xC0050EFE 0xE9CD0102 22 STRD r0,r1,[sp,#8] false
+Instruction 2995 S:0xC0050F02 0x6860 1 LDR r0,[r4,#4] false
+Instruction 2996 S:0xC0050F04 0x68A1 1 LDR r1,[r4,#8] false
+Instruction 2997 S:0xC0050F06 0xE9CB2300 1 STRD r2,r3,[r11,#0] false
+Instruction 2998 S:0xC0050F0A 0xE9D4231C 1 LDRD r2,r3,[r4,#0x70] false
+Instruction 2999 S:0xC0050F0E 0xE9C82300 1 STRD r2,r3,[r8,#0] false
+Instruction 3000 S:0xC0050F12 0xE9D42322 1 LDRD r2,r3,[r4,#0x88] false
+Instruction 3001 S:0xC0050F16 0xE9C92300 1 STRD r2,r3,[r9,#0] false
+Instruction 3002 S:0xC0050F1A 0xF3BF8F5F 1 DMB false
+Instruction 3003 S:0xC0050F1E 0xF8D43090 65 LDR r3,[r4,#0x90] false
+Instruction 3004 S:0xC0050F22 0x429E 2 CMP r6,r3 false
+Instruction 3005 S:0xC0050F24 0xD1D2 1 BNE {pc}-0x58 ; 0xc0050ecc true fail
+Instruction 3006 S:0xC0050F26 0xE9DD2306 9 LDRD r2,r3,[sp,#0x18] false
+Instruction 3007 S:0xC0050F2A 0xE9DD8902 1 LDRD r8,r9,[sp,#8] false
+Instruction 3008 S:0xC0050F2E 0xE9DD4500 1 LDRD r4,r5,[sp,#0] false
+Instruction 3009 S:0xC0050F32 0xEBB80802 1 SUBS r8,r8,r2 false
+Instruction 3010 S:0xC0050F36 0xEB690903 1 SBC r9,r9,r3 false
+Instruction 3011 S:0xC0050F3A 0x463A 0 MOV r2,r7 false
+Instruction 3012 S:0xC0050F3C 0xEA080804 1 AND r8,r8,r4 false
+Instruction 3013 S:0xC0050F40 0xEA090905 14 AND r9,r9,r5 false
+Instruction 3014 S:0xC0050F44 0x4663 0 MOV r3,r12 false
+Instruction 3015 S:0xC0050F46 0xF1C10C20 1 RSB r12,r1,#0x20 false
+Instruction 3016 S:0xC0050F4A 0xFBA86700 1 UMULL r6,r7,r8,r0 false
+Instruction 3017 S:0xC0050F4E 0x1992 2 ADDS r2,r2,r6 false
+Instruction 3018 S:0xC0050F50 0xF44F464A 0 MOV r6,#0xca00 false
+Instruction 3019 S:0xC0050F54 0xFA22F401 2 LSR r4,r2,r1 false
+Instruction 3020 S:0xC0050F58 0xF6C3369A 1 MOVT r6,#0x3b9a false
+Instruction 3021 S:0xC0050F5C 0xFB007709 1 MLA r7,r0,r9,r7 false
+Instruction 3022 S:0xC0050F60 0xEB430307 15 ADC r3,r3,r7 false
+Instruction 3023 S:0xC0050F64 0xF1B10020 0 SUBS r0,r1,#0x20 false
+Instruction 3024 S:0xC0050F68 0xFA03FC0C 2 LSL r12,r3,r12 false
+Instruction 3025 S:0xC0050F6C 0xBF58 0 IT PL false
+Instruction 3026 S:0xC0050F6E 0xFA43F000 1 ASR r0,r3,r0 false fail
+Instruction 3027 S:0xC0050F72 0xEA44040C 1 ORR r4,r4,r12 false
+Instruction 3028 S:0xC0050F76 0xFA43F501 1 ASR r5,r3,r1 false
+Instruction 3029 S:0xC0050F7A 0x9905 1 LDR r1,[sp,#0x14] false
+Instruction 3030 S:0xC0050F7C 0xBF58 0 IT PL false
+Instruction 3031 S:0xC0050F7E 0x4304 1 ORRS r4,r4,r0 false fail
+Instruction 3032 S:0xC0050F80 0xE9DB2300 1 LDRD r2,r3,[r11,#0] false
+Instruction 3033 S:0xC0050F84 0x4650 1 MOV r0,r10 false
+Instruction 3034 S:0xC0050F86 0xFBC64501 1 SMLAL r4,r5,r6,r1 false
+Instruction 3035 S:0xC0050F8A 0x1AA4 2 SUBS r4,r4,r2 false
+Instruction 3036 S:0xC0050F8C 0xEB650503 1 SBC r5,r5,r3 false
+Instruction 3037 S:0xC0050F90 0xE9CA4500 1 STRD r4,r5,[r10,#0] false
+Instruction 3038 S:0xC0050F94 0xB009 1 ADD sp,sp,#0x24 false
+Instruction 3039 S:0xC0050F96 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Instruction 3040 S:0xC0035962 0x2103 5 MOVS r1,#3 false
+Instruction 3041 S:0xC0035964 0x980C 2 LDR r0,[sp,#0x30] false
+Instruction 3042 S:0xC0035966 0x9A0D 1 LDR r2,[sp,#0x34] false
+Instruction 3043 S:0xC0035968 0x9104 1 STR r1,[sp,#0x10] false
+Instruction 3044 S:0xC003596A 0x9006 1 STR r0,[sp,#0x18] false
+Instruction 3045 S:0xC003596C 0x9207 1 STR r2,[sp,#0x1c] false
+Instruction 3046 S:0xC003596E 0xE9DD0106 2 LDRD r0,r1,[sp,#0x18] false
+Instruction 3047 S:0xC0035972 0xE9CD0100 1 STRD r0,r1,[sp,#0] false
+Instruction 3048 S:0xC0035976 0x2700 1 MOVS r7,#0 false
+Instruction 3049 S:0xC0035978 0xF04F32FF 0 MOV r2,#0xffffffff false
+Instruction 3050 S:0xC003597C 0xF06F4300 1 MVN r3,#0x80000000 false
+Instruction 3051 S:0xC0035980 0xE9CD2302 50 STRD r2,r3,[sp,#8] false
+Instruction 3052 S:0xC0035984 0xE9CA2304 1 STRD r2,r3,[r10,#0x10] false
+Instruction 3053 S:0xC0035988 0xF8DA3004 1 LDR r3,[r10,#4] false
+Instruction 3054 S:0xC003598C 0xFA0BF207 1 LSL r2,r11,r7 false
+Instruction 3055 S:0xC0035990 0x3701 1 ADDS r7,#1 false
+Instruction 3056 S:0xC0035992 0x421A 1 TST r2,r3 false
+Instruction 3057 S:0xC0035994 0xD024 0 BEQ {pc}+0x4c ; 0xc00359e0 true fail
+Instruction 3058 S:0xC0035996 0xEBC706C7 1 RSB r6,r7,r7,LSL #3 false
+Instruction 3059 S:0xC003599A 0xE9DD4500 1 LDRD r4,r5,[sp,#0] false
+Instruction 3060 S:0xC003599E 0xEB0A06C6 27 ADD r6,r10,r6,LSL #3 false
+Instruction 3061 S:0xC00359A2 0xE9D6890C 26 LDRD r8,r9,[r6,#0x30] false
+Instruction 3062 S:0xC00359A6 0x6930 2 LDR r0,[r6,#0x10] false
+Instruction 3063 S:0xC00359A8 0xEB140408 1 ADDS r4,r4,r8 false
+Instruction 3064 S:0xC00359AC 0xEB450509 1 ADC r5,r5,r9 false
+Instruction 3065 S:0xC00359B0 0xE9CD450E 1 STRD r4,r5,[sp,#0x38] false
+Instruction 3066 S:0xC00359B4 0xB1A0 1 CBZ r0,{pc}+0x2c ; 0xc00359e0 true fail
+Instruction 3067 S:0xC00359B6 0xE9D02306 20 LDRD r2,r3,[r0,#0x18] false
+Instruction 3068 S:0xC00359BA 0x4294 2 CMP r4,r2 false
+Instruction 3069 S:0xC00359BC 0xEB750103 1 SBCS r1,r5,r3 false
+Instruction 3070 S:0xC00359C0 0xDA08 1 BGE {pc}+0x14 ; 0xc00359d4 true
+Instruction 3071 S:0xC00359D4 0xA90E 4 ADD r1,sp,#0x38 false
+Instruction 3072 S:0xC00359D6 0xF7FFFB6B 1 BL {pc}-0x926 ; 0xc00350b0 true
+Instruction 3073 S:0xC00350B0 0xE92D43F0 17 PUSH {r4-r9,lr} false
+Instruction 3074 S:0xC00350B4 0xB083 4 SUB sp,sp,#0xc false
+Instruction 3075 S:0xC00350B6 0xB500 3 PUSH {lr} false
+Instruction 3076 S:0xC00350B8 0xF85DEB04 2 POP {lr} false
+Instruction 3077 S:0xC00350BC 0x6A47 1 LDR r7,[r0,#0x24] false
+Instruction 3078 S:0xC00350BE 0x4604 0 MOV r4,r0 false
+Instruction 3079 S:0xC00350C0 0x4688 59 MOV r8,r1 false
+Instruction 3080 S:0xC00350C2 0x683E 1 LDR r6,[r7,#0] false
+Instruction 3081 S:0xC00350C4 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 3082 S:0xC00350C8 0x0618 3 LSLS r0,r3,#24 false
+Instruction 3083 S:0xC00350CA 0xD56E 0 BPL {pc}+0xe0 ; 0xc00351aa true fail
+Instruction 3084 S:0xC00350CC 0x4B40 14 LDR r3,[pc,#256] ; [0xC00351D0] = 0xC0635E28 false
+Instruction 3085 S:0xC00350CE 0x685A 13 LDR r2,[r3,#4] false
+Instruction 3086 S:0xC00350D0 0x2A00 2 CMP r2,#0 false
+Instruction 3087 S:0xC00350D2 0xD15D 0 BNE {pc}+0xbe ; 0xc0035190 true fail
+Instruction 3088 S:0xC00350D4 0x2300 1 MOVS r3,#0 false
+Instruction 3089 S:0xC00350D6 0x4620 0 MOV r0,r4 false
+Instruction 3090 S:0xC00350D8 0x4639 1 MOV r1,r7 false
+Instruction 3091 S:0xC00350DA 0x2202 0 MOVS r2,#2 false
+Instruction 3092 S:0xC00350DC 0xF7FFFFA0 1 BL {pc}-0xbc ; 0xc0035020 true
+Instruction 3093 S:0xC0035020 0xE92D4F70 46 PUSH {r4-r6,r8-r11,lr} false
+Instruction 3094 S:0xC0035024 0xB500 7 PUSH {lr} false
+Instruction 3095 S:0xC0035026 0xF85DEB04 2 POP {lr} false
+Instruction 3096 S:0xC003502A 0x468B 0 MOV r11,r1 false
+Instruction 3097 S:0xC003502C 0x6A81 1 LDR r1,[r0,#0x28] false
+Instruction 3098 S:0xC003502E 0x4616 0 MOV r6,r2 false
+Instruction 3099 S:0xC0035030 0x4682 1 MOV r10,r0 false
+Instruction 3100 S:0xC0035032 0x461C 0 MOV r4,r3 false
+Instruction 3101 S:0xC0035034 0x07CA 2 LSLS r2,r1,#31 false
+Instruction 3102 S:0xC0035036 0xD403 0 BMI {pc}+0xa ; 0xc0035040 true
+Instruction 3103 S:0xC0035040 0xF8DB5010 50 LDR r5,[r11,#0x10] false
+Instruction 3104 S:0xC0035044 0xF10B000C 0 ADD r0,r11,#0xc false
+Instruction 3105 S:0xC0035048 0x4651 1 MOV r1,r10 false
+Instruction 3106 S:0xC003504A 0xF221FF6B 0 BL {pc}+0x221eda ; 0xc0256f24 true
+Cycle Count 185 Tracing disabled
+Info Tracing enabled
+Instruction 3107 S:0xC003504E 0x45AA 1 CMP r10,r5 false
+Instruction 3108 S:0xC0035050 0xD00F 1 BEQ {pc}+0x22 ; 0xc0035072 true
+Instruction 3109 S:0xC0035072 0x2C00 23 CMP r4,#0 false
+Instruction 3110 S:0xC0035074 0xD0ED 0 BEQ {pc}-0x22 ; 0xc0035052 true
+Instruction 3111 S:0xC0035052 0xF8DB3010 26 LDR r3,[r11,#0x10] false
+Instruction 3112 S:0xC0035056 0x2B00 2 CMP r3,#0 false
+Instruction 3113 S:0xC0035058 0xD1EE 1 BNE {pc}-0x20 ; 0xc0035038 true
+Instruction 3114 S:0xC0035038 0xF8CA6028 8 STR r6,[r10,#0x28] false
+Instruction 3115 S:0xC003503C 0xE8BD8F70 1 POP {r4-r6,r8-r11,pc} true
+Instruction 3116 S:0xC00350E0 0x4B3C 4 LDR r3,[pc,#240] ; [0xC00351D4] = 0xC05FC5AC false
+Instruction 3117 S:0xC00350E2 0x681B 16 LDR r3,[r3,#0] false
+Instruction 3118 S:0xC00350E4 0x2B00 2 CMP r3,#0 false
+Instruction 3119 S:0xC00350E6 0xD147 0 BNE {pc}+0x92 ; 0xc0035178 true fail
+Instruction 3120 S:0xC00350E8 0xF8D49020 1 LDR r9,[r4,#0x20] false
+Instruction 3121 S:0xC00350EC 0xF3BF8F5F 1 DMB false
+Instruction 3122 S:0xC00350F0 0x8833 29 LDRH r3,[r6,#0] false
+Instruction 3123 S:0xC00350F2 0x3301 2 ADDS r3,#1 false
+Instruction 3124 S:0xC00350F4 0x8033 1 STRH r3,[r6,#0] false
+Instruction 3125 S:0xC00350F6 0xF3BF8F4F 74 DSB false
+Instruction 3126 S:0xC00350FA 0xF3AF8004 1 SEV.W false
+Instruction 3127 S:0xC00350FE 0x4B36 3 LDR r3,[pc,#216] ; [0xC00351D8] = 0xC0635E50 false
+Instruction 3128 S:0xC0035100 0x685A 13 LDR r2,[r3,#4] false
+Instruction 3129 S:0xC0035102 0x2A00 2 CMP r2,#0 false
+Instruction 3130 S:0xC0035104 0xD12A 0 BNE {pc}+0x58 ; 0xc003515c true fail
+Instruction 3131 S:0xC0035106 0x4620 1 MOV r0,r4 false
+Instruction 3132 S:0xC0035108 0x47C8 1 BLX r9 true
+Instruction 3133 S:0xC0055728 0xB5F0 22 PUSH {r4-r7,lr} false
+Instruction 3134 S:0xC005572A 0xB085 3 SUB sp,sp,#0x14 false
+Instruction 3135 S:0xC005572C 0xB500 3 PUSH {lr} false
+Instruction 3136 S:0xC005572E 0xF85DEB04 2 POP {lr} false
+Instruction 3137 S:0xC0055732 0x4606 0 MOV r6,r0 false
+Instruction 3138 S:0xC0055734 0xA802 1 ADD r0,sp,#8 false
+Instruction 3139 S:0xC0055736 0x4B0F 14 LDR r3,[pc,#60] ; [0xC0055774] = 0xC05F1F34 false
+Instruction 3140 S:0xC0055738 0xEE1D2F90 1 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 3141 S:0xC005573C 0x58D7 6 LDR r7,[r2,r3] false
+Instruction 3142 S:0xC005573E 0xF7F9FEF5 1 BL {pc}-0x6212 ; 0xc004f52c true
+Instruction 3143 S:0xC004F52C 0xE92D4FF0 2 PUSH {r4-r11,lr} false
+Instruction 3144 S:0xC004F530 0xB08B 6 SUB sp,sp,#0x2c false
+Instruction 3145 S:0xC004F532 0xB500 3 PUSH {lr} false
+Instruction 3146 S:0xC004F534 0xF85DEB04 2 POP {lr} false
+Instruction 3147 S:0xC004F538 0x4B3D 19 LDR r3,[pc,#244] ; [0xC004F630] = 0xC05FC59C false
+Instruction 3148 S:0xC004F53A 0x4682 0 MOV r10,r0 false
+Instruction 3149 S:0xC004F53C 0x681B 3 LDR r3,[r3,#0] false
+Instruction 3150 S:0xC004F53E 0x2B00 2 CMP r3,#0 false
+Instruction 3151 S:0xC004F540 0xD16F 0 BNE {pc}+0xe2 ; 0xc004f622 true fail
+Instruction 3152 S:0xC004F542 0xF8DF90F4 1 LDR r9,[pc,#244] ; [0xC004F638] = 0xC064D1C0 false
+Instruction 3153 S:0xC004F546 0xF8DFB0F0 2 LDR r11,[pc,#240] ; [0xC004F638] = 0xC064D1C0 false
+Instruction 3154 S:0xC004F54A 0x464F 1 MOV r7,r9 false
+Instruction 3155 S:0xC004F54C 0xF8D75090 3 LDR r5,[r7,#0x90] false
+Instruction 3156 S:0xC004F550 0x07EA 3 LSLS r2,r5,#31 false
+Instruction 3157 S:0xC004F552 0xD46C 0 BMI {pc}+0xdc ; 0xc004f62e true fail
+Instruction 3158 S:0xC004F554 0xF3BF8F5F 1 DMB false
+Instruction 3159 S:0xC004F558 0xF8DB6000 59 LDR r6,[r11,#0] false
+Instruction 3160 S:0xC004F55C 0xF8DB4054 3 LDR r4,[r11,#0x54] false
+Instruction 3161 S:0xC004F560 0xE9DB230E 1 LDRD r2,r3,[r11,#0x38] false
+Instruction 3162 S:0xC004F564 0x4630 1 MOV r0,r6 false
+Instruction 3163 S:0xC004F566 0x6831 1 LDR r1,[r6,#0] false
+Instruction 3164 S:0xC004F568 0x1912 1 ADDS r2,r2,r4 false
+Instruction 3165 S:0xC004F56A 0xEB4373E4 1 ADC r3,r3,r4,ASR #31 false
+Instruction 3166 S:0xC004F56E 0xE9CD2306 3 STRD r2,r3,[sp,#0x18] false
+Instruction 3167 S:0xC004F572 0x4788 1 BLX r1 true
+Timestamp Timestamp: 562536983829
+Cycle Count 34 Tracing disabled
+Info Tracing enabled
+Instruction 3168 S:0xC004F574 0xE9D62302 1 LDRD r2,r3,[r6,#8] false
+Instruction 3169 S:0xC004F578 0xF8DBC004 1 LDR r12,[r11,#4] false
+Instruction 3170 S:0xC004F57C 0xF8DB4008 1 LDR r4,[r11,#8] false
+Instruction 3171 S:0xC004F580 0xE9CD2300 1 STRD r2,r3,[sp,#0] false
+Instruction 3172 S:0xC004F584 0xE9D62304 1 LDRD r2,r3,[r6,#0x10] false
+Instruction 3173 S:0xC004F588 0xF8DB6058 1 LDR r6,[r11,#0x58] false
+Instruction 3174 S:0xC004F58C 0xE9CD2308 1 STRD r2,r3,[sp,#0x20] false
+Instruction 3175 S:0xC004F590 0xE9DB2310 1 LDRD r2,r3,[r11,#0x40] false
+Instruction 3176 S:0xC004F594 0x9604 1 STR r6,[sp,#0x10] false
+Instruction 3177 S:0xC004F596 0xE9CD2302 1 STRD r2,r3,[sp,#8] false
+Instruction 3178 S:0xC004F59A 0x17F3 1 ASRS r3,r6,#31 false
+Instruction 3179 S:0xC004F59C 0x9305 1 STR r3,[sp,#0x14] false
+Instruction 3180 S:0xC004F59E 0xF1C40620 9 RSB r6,r4,#0x20 false
+Instruction 3181 S:0xC004F5A2 0xE9DD2300 1 LDRD r2,r3,[sp,#0] false
+Instruction 3182 S:0xC004F5A6 0x1A80 2 SUBS r0,r0,r2 false
+Instruction 3183 S:0xC004F5A8 0xEB610103 1 SBC r1,r1,r3 false
+Instruction 3184 S:0xC004F5AC 0xE9DD2308 1 LDRD r2,r3,[sp,#0x20] false
+Instruction 3185 S:0xC004F5B0 0x4010 2 ANDS r0,r0,r2 false
+Instruction 3186 S:0xC004F5B2 0x4019 1 ANDS r1,r1,r3 false
+Instruction 3187 S:0xC004F5B4 0xFBA0230C 1 UMULL r2,r3,r0,r12 false
+Instruction 3188 S:0xC004F5B8 0xFB0C3301 2 MLA r3,r12,r1,r3 false
+Instruction 3189 S:0xC004F5BC 0xE9DD0102 1 LDRD r0,r1,[sp,#8] false
+Instruction 3190 S:0xC004F5C0 0x1880 10 ADDS r0,r0,r2 false
+Instruction 3191 S:0xC004F5C2 0xEB410103 1 ADC r1,r1,r3 false
+Instruction 3192 S:0xC004F5C6 0xF1B40320 1 SUBS r3,r4,#0x20 false
+Instruction 3193 S:0xC004F5CA 0xE9CD0102 1 STRD r0,r1,[sp,#8] false
+Instruction 3194 S:0xC004F5CE 0xFA20F804 1 LSR r8,r0,r4 false
+Instruction 3195 S:0xC004F5D2 0xFA41F303 1 ASR r3,r1,r3 false
+Instruction 3196 S:0xC004F5D6 0x9903 1 LDR r1,[sp,#0xc] false
+Instruction 3197 S:0xC004F5D8 0x9A03 1 LDR r2,[sp,#0xc] false
+Instruction 3198 S:0xC004F5DA 0xFA01F606 2 LSL r6,r1,r6 false
+Instruction 3199 S:0xC004F5DE 0xEA480806 14 ORR r8,r8,r6 false
+Instruction 3200 S:0xC004F5E2 0xFA42F904 1 ASR r9,r2,r4 false
+Instruction 3201 S:0xC004F5E6 0xBF58 1 IT PL false
+Instruction 3202 S:0xC004F5E8 0xEA480803 1 ORR r8,r8,r3 false fail
+Instruction 3203 S:0xC004F5EC 0xE9DD2304 1 LDRD r2,r3,[sp,#0x10] false
+Instruction 3204 S:0xC004F5F0 0xEB120208 2 ADDS r2,r2,r8 false
+Instruction 3205 S:0xC004F5F4 0xEB430309 1 ADC r3,r3,r9 false
+Instruction 3206 S:0xC004F5F8 0xF3BF8F5F 1 DMB false
+Instruction 3207 S:0xC004F5FC 0xF8D71090 28 LDR r1,[r7,#0x90] false
+Instruction 3208 S:0xC004F600 0x428D 2 CMP r5,r1 false
+Instruction 3209 S:0xC004F602 0xD1A3 0 BNE {pc}-0xb6 ; 0xc004f54c true fail
+Instruction 3210 S:0xC004F604 0x461D 1 MOV r5,r3 false
+Instruction 3211 S:0xC004F606 0x9906 1 LDR r1,[sp,#0x18] false
+Instruction 3212 S:0xC004F608 0xF44F434A 0 MOV r3,#0xca00 false
+Instruction 3213 S:0xC004F60C 0x4614 1 MOV r4,r2 false
+Instruction 3214 S:0xC004F60E 0xF6C3339A 0 MOVT r3,#0x3b9a false
+Instruction 3215 S:0xC004F612 0x4650 1 MOV r0,r10 false
+Instruction 3216 S:0xC004F614 0xFBC34501 1 SMLAL r4,r5,r3,r1 false
+Instruction 3217 S:0xC004F618 0xE9CA4500 1 STRD r4,r5,[r10,#0] false
+Instruction 3218 S:0xC004F61C 0xB00B 1 ADD sp,sp,#0x2c false
+Instruction 3219 S:0xC004F61E 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Instruction 3220 S:0xC0055742 0xE9DD4502 7 LDRD r4,r5,[sp,#8] false
+Instruction 3221 S:0xC0055746 0x4620 2 MOV r0,r4 false
+Instruction 3222 S:0xC0055748 0x4629 1 MOV r1,r5 false
+Instruction 3223 S:0xC005574A 0xF7FFFF8D 0 BL {pc}-0xe2 ; 0xc0055668 true
+Instruction 3224 S:0xC0055668 0xB418 1 PUSH {r3,r4} false
+Instruction 3225 S:0xC005566A 0xB500 1 PUSH {lr} false
+Instruction 3226 S:0xC005566C 0xF85DEB04 2 POP {lr} false
+Instruction 3227 S:0xC0055670 0x466B 1 MOV r3,sp false
+Instruction 3228 S:0xC0055672 0x4A09 26 LDR r2,[pc,#36] ; [0xC0055698] = 0xC05FC5A4 false
+Instruction 3229 S:0xC0055674 0xF42354FF 0 BIC r4,r3,#0x1fe0 false
+Instruction 3230 S:0xC0055678 0xF024041F 1 BIC r4,r4,#0x1f false
+Instruction 3231 S:0xC005567C 0x6813 2 LDR r3,[r2,#0] false
+Instruction 3232 S:0xC005567E 0x6964 3 LDR r4,[r4,#0x14] false
+Instruction 3233 S:0xC0055680 0xF1B33FFF 1 CMP r3,#0xffffffff false
+Instruction 3234 S:0xC0055684 0xBF08 0 IT EQ false
+Instruction 3235 S:0xC0055686 0x6014 2 STR r4,[r2,#0] false fail
+Instruction 3236 S:0xC0055688 0xD003 0 BEQ {pc}+0xa ; 0xc0055692 true fail
+Instruction 3237 S:0xC005568A 0x429C 1 CMP r4,r3 false
+Instruction 3238 S:0xC005568C 0xD001 0 BEQ {pc}+6 ; 0xc0055692 true fail
+Instruction 3239 S:0xC005568E 0xBC18 1 POP {r3,r4} false
+Instruction 3240 S:0xC0055690 0x4770 1 BX lr true
+Instruction 3241 S:0xC005574E 0xB11F 11 CBZ r7,{pc}+0xa ; 0xc0055758 true fail
+Instruction 3242 S:0xC0055750 0x4639 1 MOV r1,r7 false
+Instruction 3243 S:0xC0055752 0x4630 0 MOV r0,r6 false
+Instruction 3244 S:0xC0055754 0xF7FFFEEE 1 BL {pc}-0x220 ; 0xc0055534 true
+Instruction 3245 S:0xC0055534 0xB508 34 PUSH {r3,lr} false
+Instruction 3246 S:0xC0055536 0xB500 1 PUSH {lr} false
+Instruction 3247 S:0xC0055538 0xF85DEB04 2 POP {lr} false
+Instruction 3248 S:0xC005553C 0x6DC3 14 LDR r3,[r0,#0x5c] false
+Instruction 3249 S:0xC005553E 0xB15B 2 CBZ r3,{pc}+0x1a ; 0xc0055558 true
+Instruction 3250 S:0xC0055558 0x6C0B 26 LDR r3,[r1,#0x40] false
+Instruction 3251 S:0xC005555A 0xF0130F0F 2 TST r3,#0xf false
+Instruction 3252 S:0xC005555E 0xBF14 1 ITE NE false
+Instruction 3253 S:0xC0055560 0x2000 1 MOVS r0,#0 false fail
+Instruction 3254 S:0xC0055562 0x2001 0 MOVS r0,#1 false
+Instruction 3255 S:0xC0055564 0xF7D0FEDE 1 BL {pc}-0x2f240 ; 0xc0026324 true
+Instruction 3256 S:0xC0026324 0xB5F8 18 PUSH {r3-r7,lr} false
+Instruction 3257 S:0xC0026326 0xB500 5 PUSH {lr} false
+Instruction 3258 S:0xC0026328 0xF85DEB04 2 POP {lr} false
+Instruction 3259 S:0xC002632C 0x466B 1 MOV r3,sp false
+Instruction 3260 S:0xC002632E 0xF42354FF 1 BIC r4,r3,#0x1fe0 false
+Instruction 3261 S:0xC0026332 0x4601 0 MOV r1,r0 false
+Instruction 3262 S:0xC0026334 0xF024041F 1 BIC r4,r4,#0x1f false
+Instruction 3263 S:0xC0026338 0x4606 0 MOV r6,r0 false
+Instruction 3264 S:0xC002633A 0x68E5 3 LDR r5,[r4,#0xc] false
+Instruction 3265 S:0xC002633C 0x6967 1 LDR r7,[r4,#0x14] false
+Instruction 3266 S:0xC002633E 0x4628 1 MOV r0,r5 false
+Instruction 3267 S:0xC0026340 0xF019F95A 5 BL {pc}+0x192b8 ; 0xc003f5f8 true
+Instruction 3268 S:0xC003F5F8 0xB430 19 PUSH {r4,r5} false
+Instruction 3269 S:0xC003F5FA 0xB500 1 PUSH {lr} false
+Instruction 3270 S:0xC003F5FC 0xF85DEB04 2 POP {lr} false
+Instruction 3271 S:0xC003F600 0x4604 16 MOV r4,r0 false
+Instruction 3272 S:0xC003F602 0x4B14 28 LDR r3,[pc,#80] ; [0xC003F654] = 0xC05F3080 false
+Instruction 3273 S:0xC003F604 0xEE1D2F90 1 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 3274 S:0xC003F608 0x18D3 4 ADDS r3,r2,r3 false
+Instruction 3275 S:0xC003F60A 0x2900 0 CMP r1,#0 false
+Instruction 3276 S:0xC003F60C 0xD11C 1 BNE {pc}+0x3c ; 0xc003f648 true
+Instruction 3277 S:0xC003F648 0x2101 40 MOVS r1,#1 false
+Instruction 3278 S:0xC003F64A 0x460A 1 MOV r2,r1 false
+Instruction 3279 S:0xC003F64C 0xBC30 1 POP {r4,r5} false
+Instruction 3280 S:0xC003F64E 0xF7FFBE73 1 B.W {pc}-0x316 ; 0xc003f338 true
+Instruction 3281 S:0xC003F338 0xB570 16 PUSH {r4-r6,lr} false
+Instruction 3282 S:0xC003F33A 0xB500 4 PUSH {lr} false
+Instruction 3283 S:0xC003F33C 0xF85DEB04 2 POP {lr} false
+Instruction 3284 S:0xC003F340 0x460E 11 MOV r6,r1 false
+Instruction 3285 S:0xC003F342 0xF8D053D4 13 LDR r5,[r0,#0x3d4] false
+Instruction 3286 S:0xC003F346 0x4604 1 MOV r4,r0 false
+Instruction 3287 S:0xC003F348 0xF8D032B8 54 LDR r3,[r0,#0x2b8] false
+Instruction 3288 S:0xC003F34C 0xF8D012B0 1 LDR r1,[r0,#0x2b0] false
+Instruction 3289 S:0xC003F350 0x189A 1 ADDS r2,r3,r2 false
+Instruction 3290 S:0xC003F352 0xF8C022B8 1 STR r2,[r0,#0x2b8] false
+Instruction 3291 S:0xC003F356 0x1989 1 ADDS r1,r1,r6 false
+Instruction 3292 S:0xC003F358 0xF8C012B0 1 STR r1,[r0,#0x2b0] false
+Instruction 3293 S:0xC003F35C 0xF8D530D8 15 LDR r3,[r5,#0xd8] false
+Instruction 3294 S:0xC003F360 0xB19B 2 CBZ r3,{pc}+0x2a ; 0xc003f38a true
+Instruction 3295 S:0xC003F38A 0x6A61 2 LDR r1,[r4,#0x24] false
+Instruction 3296 S:0xC003F38C 0xEE1D2F90 1 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 3297 S:0xC003F390 0x3978 1 SUBS r1,r1,#0x78 false
+Instruction 3298 S:0xC003F392 0x4B08 11 LDR r3,[pc,#32] ; [0xC003F3B4] = 0xC05F0768 false
+Instruction 3299 S:0xC003F394 0x2900 0 CMP r1,#0 false
+Instruction 3300 S:0xC003F396 0xBFD4 1 ITE LE false
+Instruction 3301 S:0xC003F398 0x2100 1 MOVS r1,#0 false
+Instruction 3302 S:0xC003F39A 0x2101 0 MOVS r1,#1 false fail
+Instruction 3303 S:0xC003F39C 0x18D3 1 ADDS r3,r2,r3 false
+Instruction 3304 S:0xC003F39E 0xEB0301C1 1 ADD r1,r3,r1,LSL #3 false
+Instruction 3305 S:0xC003F3A2 0xE9D12300 3 LDRD r2,r3,[r1,#0] false
+Instruction 3306 S:0xC003F3A6 0x1992 2 ADDS r2,r2,r6 false
+Instruction 3307 S:0xC003F3A8 0xF1430300 1 ADC r3,r3,#0 false
+Instruction 3308 S:0xC003F3AC 0xE9C12300 1 STRD r2,r3,[r1,#0] false
+Instruction 3309 S:0xC003F3B0 0xBD70 1 POP {r4-r6,pc} true
+Instruction 3310 S:0xC0026344 0xF7FFFFE2 5 BL {pc}-0x38 ; 0xc002630c true
+Instruction 3311 S:0xC002630C 0xB508 19 PUSH {r3,lr} false
+Instruction 3312 S:0xC002630E 0xB500 1 PUSH {lr} false
+Instruction 3313 S:0xC0026310 0xF85DEB04 2 POP {lr} false
+Instruction 3314 S:0xC0026314 0xF00FFC92 1 BL {pc}+0xf928 ; 0xc0035c3c true
+Instruction 3315 S:0xC0035C3C 0xE92D47F0 58 PUSH {r4-r10,lr} false
+Instruction 3316 S:0xC0035C40 0xB08A 23 SUB sp,sp,#0x28 false
+Instruction 3317 S:0xC0035C42 0xB500 3 PUSH {lr} false
+Instruction 3318 S:0xC0035C44 0xF85DEB04 2 POP {lr} false
+Instruction 3319 S:0xC0035C48 0x4E44 15 LDR r6,[pc,#272] ; [0xC0035D5C] = 0xC05F0640 false
+Instruction 3320 S:0xC0035C4A 0xEE1D2F90 1 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 3321 S:0xC0035C4E 0xF1060318 1 ADD r3,r6,#0x18 false
+Instruction 3322 S:0xC0035C52 0x58D3 14 LDR r3,[r2,r3] false
+Instruction 3323 S:0xC0035C54 0x2B00 2 CMP r3,#0 false
+Instruction 3324 S:0xC0035C56 0xD13C 0 BNE {pc}+0x7c ; 0xc0035cd2 true
+Instruction 3325 S:0xC0035CD2 0xB00A 1 ADD sp,sp,#0x28 false
+Instruction 3326 S:0xC0035CD4 0xE8BD87F0 3 POP {r4-r10,pc} true
+Instruction 3327 S:0xC0026318 0x2001 4 MOVS r0,#1 false
+Instruction 3328 S:0xC002631A 0xE8BD4008 2 POP {r3,lr} false
+Instruction 3329 S:0xC002631E 0xF7FBB8AF 1 B {pc}-0x4e9e ; 0xc0021480 true
+Instruction 3330 S:0xC0021480 0xB510 15 PUSH {r4,lr} false
+Instruction 3331 S:0xC0021482 0xB500 1 PUSH {lr} false
+Instruction 3332 S:0xC0021484 0xF85DEB04 2 POP {lr} false
+Instruction 3333 S:0xC0021488 0xF3EF8400 1 MRS r4,APSR ; formerly CPSR false
+Instruction 3334 S:0xC002148C 0xB672 1 CPSID i false
+Instruction 3335 S:0xC002148E 0xF7FFFEF1 1 BL {pc}-0x21a ; 0xc0021274 true
+Instruction 3336 S:0xC0021274 0xB538 14 PUSH {r3-r5,lr} false
+Instruction 3337 S:0xC0021276 0xB500 4 PUSH {lr} false
+Instruction 3338 S:0xC0021278 0xF85DEB04 2 POP {lr} false
+Instruction 3339 S:0xC002127C 0x4605 0 MOV r5,r0 false
+Instruction 3340 S:0xC002127E 0x4B0F 17 LDR r3,[pc,#60] ; [0xC00212BC] = 0xC0635D24 false
+Instruction 3341 S:0xC0021280 0x6ADA 6 LDR r2,[r3,#0x2c] false
+Instruction 3342 S:0xC0021282 0xB972 2 CBNZ r2,{pc}+0x20 ; 0xc00212a2 true fail
+Instruction 3343 S:0xC0021284 0x466A 1 MOV r2,sp false
+Instruction 3344 S:0xC0021286 0x2101 0 MOVS r1,#1 false
+Instruction 3345 S:0xC0021288 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 3346 S:0xC002128C 0x4A0C 12 LDR r2,[pc,#48] ; [0xC00212C0] = 0xC06498C0 false
+Instruction 3347 S:0xC002128E 0xF023031F 0 BIC r3,r3,#0x1f false
+Instruction 3348 S:0xC0021292 0xFA01F505 1 LSL r5,r1,r5 false
+Instruction 3349 S:0xC0021296 0x695B 2 LDR r3,[r3,#0x14] false
+Instruction 3350 S:0xC0021298 0x019B 3 LSLS r3,r3,#6 false
+Instruction 3351 S:0xC002129A 0x58D1 18 LDR r1,[r2,r3] false
+Instruction 3352 S:0xC002129C 0x4329 2 ORRS r1,r1,r5 false
+Instruction 3353 S:0xC002129E 0x50D1 1 STR r1,[r2,r3] false
+Instruction 3354 S:0xC00212A0 0xBD38 1 POP {r3-r5,pc} true
+Instruction 3355 S:0xC0021492 0x466A 2 MOV r2,sp false
+Instruction 3356 S:0xC0021494 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 3357 S:0xC0021498 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 3358 S:0xC002149C 0x685B 3 LDR r3,[r3,#4] false
+Instruction 3359 S:0xC002149E 0xF0234378 2 BIC r3,r3,#0xf8000000 false
+Instruction 3360 S:0xC00214A2 0xF02303FF 1 BIC r3,r3,#0xff false
+Instruction 3361 S:0xC00214A6 0xB113 1 CBZ r3,{pc}+8 ; 0xc00214ae true fail
+Instruction 3362 S:0xC00214A8 0xF3848100 10 MSR CPSR_c,r4 false
+Instruction 3363 S:0xC00214AC 0xBD10 5 POP {r4,pc} true
+Instruction 3364 S:0xC0026348 0x4638 1 MOV r0,r7 false
+Instruction 3365 S:0xC002634A 0x4631 0 MOV r1,r6 false
+Instruction 3366 S:0xC002634C 0xF04AFA1A 1 BL {pc}+0x4a438 ; 0xc0070784 true
+Cycle Count 1081 Tracing disabled
+Info Tracing enabled
+Instruction 3367 S:0xC0021480 0xB510 1 PUSH {r4,lr} false
+Instruction 3368 S:0xC0021482 0xB500 1 PUSH {lr} false
+Instruction 3369 S:0xC0021484 0xF85DEB04 2 POP {lr} false
+Instruction 3370 S:0xC0021488 0xF3EF8400 1 MRS r4,APSR ; formerly CPSR false
+Instruction 3371 S:0xC002148C 0xB672 1 CPSID i false
+Instruction 3372 S:0xC002148E 0xF7FFFEF1 1 BL {pc}-0x21a ; 0xc0021274 true
+Instruction 3373 S:0xC0021274 0xB538 1 PUSH {r3-r5,lr} false
+Instruction 3374 S:0xC0021276 0xB500 4 PUSH {lr} false
+Instruction 3375 S:0xC0021278 0xF85DEB04 2 POP {lr} false
+Instruction 3376 S:0xC002127C 0x4605 0 MOV r5,r0 false
+Instruction 3377 S:0xC002127E 0x4B0F 2 LDR r3,[pc,#60] ; [0xC00212BC] = 0xC0635D24 false
+Instruction 3378 S:0xC0021280 0x6ADA 6 LDR r2,[r3,#0x2c] false
+Instruction 3379 S:0xC0021282 0xB972 2 CBNZ r2,{pc}+0x20 ; 0xc00212a2 true fail
+Instruction 3380 S:0xC0021284 0x466A 8 MOV r2,sp false
+Instruction 3381 S:0xC0021286 0x2101 0 MOVS r1,#1 false
+Instruction 3382 S:0xC0021288 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 3383 S:0xC002128C 0x4A0C 1 LDR r2,[pc,#48] ; [0xC00212C0] = 0xC06498C0 false
+Instruction 3384 S:0xC002128E 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 3385 S:0xC0021292 0xFA01F505 1 LSL r5,r1,r5 false
+Instruction 3386 S:0xC0021296 0x695B 2 LDR r3,[r3,#0x14] false
+Instruction 3387 S:0xC0021298 0x019B 3 LSLS r3,r3,#6 false
+Instruction 3388 S:0xC002129A 0x58D1 5 LDR r1,[r2,r3] false
+Instruction 3389 S:0xC002129C 0x4329 2 ORRS r1,r1,r5 false
+Instruction 3390 S:0xC002129E 0x50D1 1 STR r1,[r2,r3] false
+Instruction 3391 S:0xC00212A0 0xBD38 3 POP {r3-r5,pc} true
+Instruction 3392 S:0xC0021492 0x466A 4 MOV r2,sp false
+Instruction 3393 S:0xC0021494 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 3394 S:0xC0021498 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 3395 S:0xC002149C 0x685B 3 LDR r3,[r3,#4] false
+Instruction 3396 S:0xC002149E 0xF0234378 2 BIC r3,r3,#0xf8000000 false
+Instruction 3397 S:0xC00214A2 0xF02303FF 1 BIC r3,r3,#0xff false
+Instruction 3398 S:0xC00214A6 0xB113 1 CBZ r3,{pc}+8 ; 0xc00214ae true fail
+Instruction 3399 S:0xC00214A8 0xF3848100 1 MSR CPSR_c,r4 false
+Instruction 3400 S:0xC00214AC 0xBD10 5 POP {r4,pc} true
+Cycle Count 17 Tracing disabled
+Info Tracing enabled
+Instruction 3401 S:0xC0026350 0x6862 1 LDR r2,[r4,#4] false
+Instruction 3402 S:0xC0026352 0x2300 0 MOVS r3,#0 false
+Instruction 3403 S:0xC0026354 0xF2C033FF 1 MOVT r3,#0x3ff false
+Instruction 3404 S:0xC0026358 0x4013 1 ANDS r3,r3,r2 false
+Instruction 3405 S:0xC002635A 0xB10B 1 CBZ r3,{pc}+6 ; 0xc0026360 true fail
+Instruction 3406 S:0xC002635C 0xF05CFA84 1 BL {pc}+0x5c50c ; 0xc0082868 true
+Cycle Count 173 Tracing disabled
+Info Tracing enabled
+Instruction 3407 S:0xC0026360 0xF016FC22 1 BL {pc}+0x16848 ; 0xc003cba8 true
+Instruction 3408 S:0xC003CBA8 0xE92D4FF0 20 PUSH {r4-r11,lr} false
+Instruction 3409 S:0xC003CBAC 0xB083 7 SUB sp,sp,#0xc false
+Instruction 3410 S:0xC003CBAE 0xAF00 1 ADD r7,sp,#0 false
+Instruction 3411 S:0xC003CBB0 0xB500 2 PUSH {lr} false
+Instruction 3412 S:0xC003CBB2 0xF85DEB04 2 POP {lr} false
+Instruction 3413 S:0xC003CBB6 0x466A 1 MOV r2,sp false
+Instruction 3414 S:0xC003CBB8 0xF8DFA0F4 13 LDR r10,[pc,#244] ; [0xC003CCB0] = 0xC05FD5C0 false
+Instruction 3415 S:0xC003CBBC 0xF42253FF 0 BIC r3,r2,#0x1fe0 false
+Instruction 3416 S:0xC003CBC0 0xF8DF90F0 4 LDR r9,[pc,#240] ; [0xC003CCB4] = 0xC05F3080 false
+Instruction 3417 S:0xC003CBC4 0xF023031F 0 BIC r3,r3,#0x1f false
+Instruction 3418 S:0xC003CBC8 0xF8DFB0EC 1 LDR r11,[pc,#236] ; [0xC003CCB8] = 0xC05F60C0 false
+Instruction 3419 S:0xC003CBCC 0x464D 1 MOV r5,r9 false
+Instruction 3420 S:0xC003CBCE 0x695E 1 LDR r6,[r3,#0x14] false
+Instruction 3421 S:0xC003CBD0 0xF85A8026 5 LDR r8,[r10,r6,LSL #2] false
+Instruction 3422 S:0xC003CBD4 0xEB050408 2 ADD r4,r5,r8 false
+Instruction 3423 S:0xC003CBD8 0x4620 1 MOV r0,r4 false
+Instruction 3424 S:0xC003CBDA 0xF8D4C460 27 LDR r12,[r4,#0x460] false
+Instruction 3425 S:0xC003CBDE 0xF8C7C004 3 STR r12,[r7,#4] false
+Instruction 3426 S:0xC003CBE2 0xF3A7FCE9 0 BL {pc}+0x3a79d6 ; 0xc03e45b8 true
+Cycle Count 55 Tracing disabled
+Info Tracing enabled
+Instruction 3427 S:0xC003CBE6 0x4620 1 MOV r0,r4 false
+Instruction 3428 S:0xC003CBE8 0xF7FEFDCE 0 BL {pc}-0x1460 ; 0xc003b788 true
+Instruction 3429 S:0xC003B788 0xE92D43C8 1 PUSH {r3,r6-r9,lr} false
+Instruction 3430 S:0xC003B78C 0xAF00 3 ADD r7,sp,#0 false
+Instruction 3431 S:0xC003B78E 0xB500 25 PUSH {lr} false
+Instruction 3432 S:0xC003B790 0xF85DEB04 2 POP {lr} false
+Instruction 3433 S:0xC003B794 0x6AC3 2 LDR r3,[r0,#0x2c] false
+Instruction 3434 S:0xC003B796 0x4606 0 MOV r6,r0 false
+Instruction 3435 S:0xC003B798 0x2B00 2 CMP r3,#0 false
+Instruction 3436 S:0xC003B79A 0xDD01 0 BLE {pc}+6 ; 0xc003b7a0 true
+Instruction 3437 S:0xC003B7A0 0xF8D004C0 112 LDR r0,[r0,#0x4c0] false
+Instruction 3438 S:0xC003B7A4 0xF003FD86 0 BL {pc}+0x3b10 ; 0xc003f2b4 true
+Instruction 3439 S:0xC003F2B4 0x4B03 15 LDR r3,[pc,#12] ; [0xC003F2C4] = 0xC05FC57C false
+Instruction 3440 S:0xC003F2B6 0x6818 5 LDR r0,[r3,#0] false
+Instruction 3441 S:0xC003F2B8 0xB108 2 CBZ r0,{pc}+6 ; 0xc003f2be true fail
+Instruction 3442 S:0xC003F2BA 0xF7CFBD35 1 B {pc}-0x30592 ; 0xc000ed28 true
+Instruction 3443 S:0xC000ED28 0xB508 1 PUSH {r3,lr} false
+Instruction 3444 S:0xC000ED2A 0xF24C43CC 1 MOV r3,#0xc4cc false
+Instruction 3445 S:0xC000ED2E 0xF2CC035F 1 MOVT r3,#0xc05f false
+Instruction 3446 S:0xC000ED32 0x689B 15 LDR r3,[r3,#8] false
+Instruction 3447 S:0xC000ED34 0x4798 1 BLX r3 true
+Instruction 3448 S:0xC00113EC 0xF24A2340 23 MOV r3,#0xa240 false
+Instruction 3449 S:0xC00113F0 0xF2CC0362 1 MOVT r3,#0xc062 false
+Instruction 3450 S:0xC00113F4 0xB510 1 PUSH {r4,lr} false
+Instruction 3451 S:0xC00113F6 0x681B 6 LDR r3,[r3,#0] false
+Instruction 3452 S:0xC00113F8 0x4798 1 BLX r3 true
+Timestamp Timestamp: 562536984008
+Cycle Count 24 Tracing disabled
+Info Tracing enabled
+Instruction 3453 S:0xC00113FA 0xF24C5320 1 MOV r3,#0xc520 false
+Instruction 3454 S:0xC00113FE 0xF2CC035F 1 MOVT r3,#0xc05f false
+Instruction 3455 S:0xC0011402 0x681C 3 LDR r4,[r3,#0] false
+Instruction 3456 S:0xC0011404 0xFBA02304 3 UMULL r2,r3,r0,r4 false
+Instruction 3457 S:0xC0011408 0x4610 2 MOV r0,r2 false
+Instruction 3458 S:0xC001140A 0xFB043101 1 MLA r1,r4,r1,r3 false
+Instruction 3459 S:0xC001140E 0xBD10 1 POP {r4,pc} true
+Instruction 3460 S:0xC000ED36 0xBD08 3 POP {r3,pc} true
+Instruction 3461 S:0xC003B7A8 0xF506638F 1 ADD r3,r6,#0x478 false
+Instruction 3462 S:0xC003B7AC 0xF5066690 0 ADD r6,r6,#0x480 false
+Instruction 3463 S:0xC003B7B0 0xE9D38900 3 LDRD r8,r9,[r3,#0] false
+Timestamp Timestamp: 562536984011
+Instruction 3464 S:0xC003B7B4 0xE9C30100 1 STRD r0,r1,[r3,#0] false
+Instruction 3465 S:0xC003B7B8 0xE9D62300 1 LDRD r2,r3,[r6,#0] false
+Instruction 3466 S:0xC003B7BC 0xEBB20208 2 SUBS r2,r2,r8 false
+Instruction 3467 S:0xC003B7C0 0xEB630309 4 SBC r3,r3,r9 false
+Instruction 3468 S:0xC003B7C4 0x1812 1 ADDS r2,r2,r0 false
+Instruction 3469 S:0xC003B7C6 0xEB430301 1 ADC r3,r3,r1 false
+Instruction 3470 S:0xC003B7CA 0xE9C62300 1 STRD r2,r3,[r6,#0] false
+Instruction 3471 S:0xC003B7CE 0xE8BD83C8 1 POP {r3,r6-r9,pc} true
+Instruction 3472 S:0xC003CBEC 0xF8DB3000 22 LDR r3,[r11,#0] false
+Instruction 3473 S:0xC003CBF0 0x2201 1 MOVS r2,#1 false
+Instruction 3474 S:0xC003CBF2 0x4620 0 MOV r0,r4 false
+Instruction 3475 S:0xC003CBF4 0x6B21 1 LDR r1,[r4,#0x30] false
+Instruction 3476 S:0xC003CBF6 0x61E3 1 STR r3,[r4,#0x1c] false
+Instruction 3477 S:0xC003CBF8 0xF7FFF86A 1 BL {pc}-0xf28 ; 0xc003bcd0 true
+Instruction 3478 S:0xC003BCD0 0xE92D0FF0 4 PUSH {r4-r11} false
+Instruction 3479 S:0xC003BCD4 0xB082 6 SUB sp,sp,#8 false
+Instruction 3480 S:0xC003BCD6 0xAF00 1 ADD r7,sp,#0 false
+Instruction 3481 S:0xC003BCD8 0xB500 2 PUSH {lr} false
+Instruction 3482 S:0xC003BCDA 0xF85DEB04 2 POP {lr} false
+Instruction 3483 S:0xC003BCDE 0xF8DF8094 18 LDR r8,[pc,#148] ; [0xC003BD74] = 0xC03E7C64 false
+Instruction 3484 S:0xC003BCE2 0x3A01 0 SUBS r2,#1 false
+Instruction 3485 S:0xC003BCE4 0x6B83 3 LDR r3,[r0,#0x38] false
+Instruction 3486 S:0xC003BCE6 0x4684 0 MOV r12,r0 false
+Instruction 3487 S:0xC003BCE8 0xF1080A20 1 ADD r10,r8,#0x20 false
+Instruction 3488 S:0xC003BCEC 0xF04F0902 0 MOV r9,#2 false
+Instruction 3489 S:0xC003BCF0 0x2601 1 MOVS r6,#1 false
+Instruction 3490 S:0xC003BCF2 0x1E4C 0 SUBS r4,r1,#1 false
+Instruction 3491 S:0xC003BCF4 0x199B 1 ADDS r3,r3,r6 false
+Instruction 3492 S:0xC003BCF6 0x607C 1 STR r4,[r7,#4] false
+Instruction 3493 S:0xC003BCF8 0x6081 1 STR r1,[r0,#8] false
+Instruction 3494 S:0xC003BCFA 0x6383 1 STR r3,[r0,#0x38] false
+Instruction 3495 S:0xC003BCFC 0xF8DC500C 1 LDR r5,[r12,#0xc] false
+Instruction 3496 S:0xC003BD00 0xB1C2 1 CBZ r2,{pc}+0x34 ; 0xc003bd34 true
+Instruction 3497 S:0xC003BD34 0xF10933FF 23 ADD r3,r9,#0xffffffff false
+Instruction 3498 S:0xC003BD38 0xFB03F305 2 MUL r3,r3,r5 false
+Instruction 3499 S:0xC003BD3C 0x42A9 1 CMP r1,r5 false
+Instruction 3500 S:0xC003BD3E 0xF1080808 16 ADD r8,r8,#8 false
+Instruction 3501 S:0xC003BD42 0xBF92 0 ITEE LS false
+Instruction 3502 S:0xC003BD44 0x460C 1 MOV r4,r1 false fail
+Instruction 3503 S:0xC003BD46 0x687D 1 LDR r5,[r7,#4] false
+Instruction 3504 S:0xC003BD48 0xEB050409 2 ADD r4,r5,r9 false
+Instruction 3505 S:0xC003BD4C 0xEA4F0949 1 LSL r9,r9,#1 false
+Instruction 3506 S:0xC003BD50 0x18E3 1 ADDS r3,r4,r3 false
+Instruction 3507 S:0xC003BD52 0x40F3 2 LSRS r3,r3,r6 false
+Instruction 3508 S:0xC003BD54 0x3601 0 ADDS r6,#1 false
+Instruction 3509 S:0xC003BD56 0x2E05 1 CMP r6,#5 false
+Instruction 3510 S:0xC003BD58 0xF8CC300C 1 STR r3,[r12,#0xc] false
+Instruction 3511 S:0xC003BD5C 0xF10C0C04 0 ADD r12,r12,#4 false
+Instruction 3512 S:0xC003BD60 0xD1CC 9 BNE {pc}-0x64 ; 0xc003bcfc true
+Instruction 3513 S:0xC003BCFC 0xF8DC500C 22 LDR r5,[r12,#0xc] false
+Instruction 3514 S:0xC003BD00 0xB1C2 1 CBZ r2,{pc}+0x34 ; 0xc003bd34 true
+Instruction 3515 S:0xC003BD34 0xF10933FF 3 ADD r3,r9,#0xffffffff false
+Instruction 3516 S:0xC003BD38 0xFB03F305 2 MUL r3,r3,r5 false
+Instruction 3517 S:0xC003BD3C 0x42A9 1 CMP r1,r5 false
+Instruction 3518 S:0xC003BD3E 0xF1080808 1 ADD r8,r8,#8 false
+Instruction 3519 S:0xC003BD42 0xBF92 0 ITEE LS false
+Instruction 3520 S:0xC003BD44 0x460C 1 MOV r4,r1 false fail
+Instruction 3521 S:0xC003BD46 0x687D 1 LDR r5,[r7,#4] false
+Instruction 3522 S:0xC003BD48 0xEB050409 2 ADD r4,r5,r9 false
+Instruction 3523 S:0xC003BD4C 0xEA4F0949 1 LSL r9,r9,#1 false
+Instruction 3524 S:0xC003BD50 0x18E3 1 ADDS r3,r4,r3 false
+Instruction 3525 S:0xC003BD52 0x40F3 2 LSRS r3,r3,r6 false
+Instruction 3526 S:0xC003BD54 0x3601 0 ADDS r6,#1 false
+Instruction 3527 S:0xC003BD56 0x2E05 1 CMP r6,#5 false
+Instruction 3528 S:0xC003BD58 0xF8CC300C 1 STR r3,[r12,#0xc] false
+Instruction 3529 S:0xC003BD5C 0xF10C0C04 0 ADD r12,r12,#4 false
+Instruction 3530 S:0xC003BD60 0xD1CC 1 BNE {pc}-0x64 ; 0xc003bcfc true
+Instruction 3531 S:0xC003BCFC 0xF8DC500C 19 LDR r5,[r12,#0xc] false
+Instruction 3532 S:0xC003BD00 0xB1C2 1 CBZ r2,{pc}+0x34 ; 0xc003bd34 true
+Instruction 3533 S:0xC003BD34 0xF10933FF 1 ADD r3,r9,#0xffffffff false
+Instruction 3534 S:0xC003BD38 0xFB03F305 2 MUL r3,r3,r5 false
+Instruction 3535 S:0xC003BD3C 0x42A9 1 CMP r1,r5 false
+Instruction 3536 S:0xC003BD3E 0xF1080808 1 ADD r8,r8,#8 false
+Instruction 3537 S:0xC003BD42 0xBF92 0 ITEE LS false
+Instruction 3538 S:0xC003BD44 0x460C 1 MOV r4,r1 false fail
+Instruction 3539 S:0xC003BD46 0x687D 1 LDR r5,[r7,#4] false
+Instruction 3540 S:0xC003BD48 0xEB050409 2 ADD r4,r5,r9 false
+Instruction 3541 S:0xC003BD4C 0xEA4F0949 1 LSL r9,r9,#1 false
+Instruction 3542 S:0xC003BD50 0x18E3 1 ADDS r3,r4,r3 false
+Instruction 3543 S:0xC003BD52 0x40F3 2 LSRS r3,r3,r6 false
+Instruction 3544 S:0xC003BD54 0x3601 0 ADDS r6,#1 false
+Instruction 3545 S:0xC003BD56 0x2E05 1 CMP r6,#5 false
+Instruction 3546 S:0xC003BD58 0xF8CC300C 1 STR r3,[r12,#0xc] false
+Instruction 3547 S:0xC003BD5C 0xF10C0C04 0 ADD r12,r12,#4 false
+Instruction 3548 S:0xC003BD60 0xD1CC 1 BNE {pc}-0x64 ; 0xc003bcfc true
+Instruction 3549 S:0xC003BCFC 0xF8DC500C 2 LDR r5,[r12,#0xc] false
+Instruction 3550 S:0xC003BD00 0xB1C2 1 CBZ r2,{pc}+0x34 ; 0xc003bd34 true
+Instruction 3551 S:0xC003BD34 0xF10933FF 1 ADD r3,r9,#0xffffffff false
+Instruction 3552 S:0xC003BD38 0xFB03F305 2 MUL r3,r3,r5 false
+Instruction 3553 S:0xC003BD3C 0x42A9 1 CMP r1,r5 false
+Instruction 3554 S:0xC003BD3E 0xF1080808 0 ADD r8,r8,#8 false
+Instruction 3555 S:0xC003BD42 0xBF92 1 ITEE LS false
+Instruction 3556 S:0xC003BD44 0x460C 1 MOV r4,r1 false fail
+Instruction 3557 S:0xC003BD46 0x687D 1 LDR r5,[r7,#4] false
+Instruction 3558 S:0xC003BD48 0xEB050409 2 ADD r4,r5,r9 false
+Instruction 3559 S:0xC003BD4C 0xEA4F0949 1 LSL r9,r9,#1 false
+Instruction 3560 S:0xC003BD50 0x18E3 1 ADDS r3,r4,r3 false
+Instruction 3561 S:0xC003BD52 0x40F3 2 LSRS r3,r3,r6 false
+Instruction 3562 S:0xC003BD54 0x3601 0 ADDS r6,#1 false
+Instruction 3563 S:0xC003BD56 0x2E05 1 CMP r6,#5 false
+Instruction 3564 S:0xC003BD58 0xF8CC300C 1 STR r3,[r12,#0xc] false
+Instruction 3565 S:0xC003BD5C 0xF10C0C04 0 ADD r12,r12,#4 false
+Instruction 3566 S:0xC003BD60 0xD1CC 1 BNE {pc}-0x64 ; 0xc003bcfc true fail
+Instruction 3567 S:0xC003BD62 0xF1070708 8 ADD r7,r7,#8 false
+Instruction 3568 S:0xC003BD66 0x46BD 1 MOV sp,r7 false
+Instruction 3569 S:0xC003BD68 0xE8BD0FF0 3 POP {r4-r11} false
+Instruction 3570 S:0xC003BD6C 0xF7FFBF70 4 B.W {pc}-0x11c ; 0xc003bc50 true
+Instruction 3571 S:0xC003BC50 0xE92D03F0 2 PUSH {r4-r9} false
+Instruction 3572 S:0xC003BC54 0xAF00 3 ADD r7,sp,#0 false
+Instruction 3573 S:0xC003BC56 0xB500 2 PUSH {lr} false
+Instruction 3574 S:0xC003BC58 0xF85DEB04 2 POP {lr} false
+Instruction 3575 S:0xC003BC5C 0x4B1B 15 LDR r3,[pc,#108] ; [0xC003BCCC] = 0xC05FC564 false
+Instruction 3576 S:0xC003BC5E 0xF2442C40 0 MOV r12,#0x4240 false
+Instruction 3577 S:0xC003BC62 0xF500619B 1 ADD r1,r0,#0x4d8 false
+Instruction 3578 S:0xC003BC66 0xF2C00C0F 0 MOVT r12,#0xf false
+Instruction 3579 S:0xC003BC6A 0xF500668F 1 ADD r6,r0,#0x478 false
+Instruction 3580 S:0xC003BC6E 0xF8D38008 1 LDR r8,[r3,#8] false
+Instruction 3581 S:0xC003BC72 0xE9D64500 2 LDRD r4,r5,[r6,#0] false
+Instruction 3582 S:0xC003BC76 0xE9D12300 1 LDRD r2,r3,[r1,#0] false
+Instruction 3583 S:0xC003BC7A 0xFBA8890C 1 UMULL r8,r9,r8,r12 false
+Instruction 3584 S:0xC003BC7E 0x1AA4 1 SUBS r4,r4,r2 false
+Instruction 3585 S:0xC003BC80 0xEB650503 1 SBC r5,r5,r3 false
+Instruction 3586 S:0xC003BC84 0xEA5F0959 1 LSRS r9,r9,#1 false
+Instruction 3587 S:0xC003BC88 0xEA4F0838 1 RRX r8,r8 false
+Instruction 3588 S:0xC003BC8C 0x45A0 1 CMP r8,r4 false
+Instruction 3589 S:0xC003BC8E 0xEB790C05 1 SBCS r12,r9,r5 false
+Instruction 3590 S:0xC003BC92 0xDA17 0 BGE {pc}+0x32 ; 0xc003bcc4 true
+Instruction 3591 S:0xC003BCC4 0x46BD 1 MOV sp,r7 false
+Instruction 3592 S:0xC003BCC6 0xE8BD03F0 3 POP {r4-r9} false
+Instruction 3593 S:0xC003BCCA 0x4770 3 BX lr true
+Instruction 3594 S:0xC003CBFC 0xF8DB3000 1 LDR r3,[r11,#0] false
+Instruction 3595 S:0xC003CC00 0xF8D424F0 1 LDR r2,[r4,#0x4f0] false
+Instruction 3596 S:0xC003CC04 0xF8D7C004 1 LDR r12,[r7,#4] false
+Instruction 3597 S:0xC003CC08 0x1A9B 1 SUBS r3,r3,r2 false
+Instruction 3598 S:0xC003CC0A 0x2B00 1 CMP r3,#0 false
+Instruction 3599 S:0xC003CC0C 0xDB1A 0 BLT {pc}+0x38 ; 0xc003cc44 true
+Instruction 3600 S:0xC003CC44 0xF8DC3030 21 LDR r3,[r12,#0x30] false
+Instruction 3601 S:0xC003CC48 0x4661 1 MOV r1,r12 false
+Instruction 3602 S:0xC003CC4A 0x4620 0 MOV r0,r4 false
+Instruction 3603 S:0xC003CC4C 0x2200 1 MOVS r2,#0 false
+Instruction 3604 S:0xC003CC4E 0x6C9B 14 LDR r3,[r3,#0x48] false
+Instruction 3605 S:0xC003CC50 0x4798 1 BLX r3 true
+Instruction 3606 S:0xC0043020 0xE92D4FF0 21 PUSH {r4-r11,lr} false
+Instruction 3607 S:0xC0043024 0xB091 5 SUB sp,sp,#0x44 false
+Instruction 3608 S:0xC0043026 0xB500 3 PUSH {lr} false
+Instruction 3609 S:0xC0043028 0xF85DEB04 2 POP {lr} false
+Instruction 3610 S:0xC004302C 0xF1110938 0 ADDS r9,r1,#0x38 false
+Instruction 3611 S:0xC0043030 0x900B 3 STR r0,[sp,#0x2c] false
+Instruction 3612 S:0xC0043032 0xBF18 0 IT NE false
+Instruction 3613 S:0xC0043034 0x464E 1 MOV r6,r9 false
+Instruction 3614 S:0xC0043036 0x920D 1 STR r2,[sp,#0x34] false
+Instruction 3615 S:0xC0043038 0xF0008148 0 BEQ.W {pc}+0x294 ; 0xc00432cc true fail
+Instruction 3616 S:0xC004303C 0xF8D67124 29 LDR r7,[r6,#0x124] false
+Instruction 3617 S:0xC0043040 0x4638 2 MOV r0,r7 false
+Instruction 3618 S:0xC0043042 0xF7FDF861 0 BL {pc}-0x2f3a ; 0xc0040108 true
+Instruction 3619 S:0xC0040108 0xE92D4FF0 2 PUSH {r4-r11,lr} false
+Instruction 3620 S:0xC004010C 0xB085 7 SUB sp,sp,#0x14 false
+Instruction 3621 S:0xC004010E 0xB500 3 PUSH {lr} false
+Instruction 3622 S:0xC0040110 0xF85DEB04 2 POP {lr} false
+Instruction 3623 S:0xC0040114 0xF8D02084 1 LDR r2,[r0,#0x84] false
+Instruction 3624 S:0xC0040118 0xF8D0A030 2 LDR r10,[r0,#0x30] false
+Instruction 3625 S:0xC004011C 0x4683 0 MOV r11,r0 false
+Instruction 3626 S:0xC004011E 0xF8D23480 7 LDR r3,[r2,#0x480] false
+Instruction 3627 S:0xC0040122 0xF8D2C484 1 LDR r12,[r2,#0x484] false
+Instruction 3628 S:0xC0040126 0xF1BA0F00 1 CMP r10,#0 false
+Instruction 3629 S:0xC004012A 0xD041 0 BEQ {pc}+0x86 ; 0xc00401b0 true fail
+Instruction 3630 S:0xC004012C 0xF8DA2020 8 LDR r2,[r10,#0x20] false
+Instruction 3631 S:0xC0040130 0x1A9A 2 SUBS r2,r3,r2 false
+Instruction 3632 S:0xC0040132 0xD03D 0 BEQ {pc}+0x7e ; 0xc00401b0 true fail
+Instruction 3633 S:0xC0040134 0xE9DA6728 17 LDRD r6,r7,[r10,#0xa0] false
+Instruction 3634 S:0xC0040138 0x2500 1 MOVS r5,#0 false
+Instruction 3635 S:0xC004013A 0x4614 0 MOV r4,r2 false
+Instruction 3636 S:0xC004013C 0x4629 1 MOV r1,r5 false
+Instruction 3637 S:0xC004013E 0x42BD 1 CMP r5,r7 false
+Instruction 3638 S:0xC0040140 0xBF08 0 IT EQ false
+Instruction 3639 S:0xC0040142 0x42B4 1 CMP r4,r6 false
+Instruction 3640 S:0xC0040144 0x4610 0 MOV r0,r2 false
+Instruction 3641 S:0xC0040146 0xBF3C 1 ITT CC false
+Instruction 3642 S:0xC0040148 0x4639 1 MOV r1,r7 false
+Instruction 3643 S:0xC004014A 0x4630 0 MOV r0,r6 false
+Instruction 3644 S:0xC004014C 0xE9DA670A 1 LDRD r6,r7,[r10,#0x28] false
+Instruction 3645 S:0xC0040150 0xF8CA10A4 1 STR r1,[r10,#0xa4] false
+Instruction 3646 S:0xC0040154 0x18B6 1 ADDS r6,r6,r2 false
+Instruction 3647 S:0xC0040156 0xF8CA00A0 1 STR r0,[r10,#0xa0] false
+Instruction 3648 S:0xC004015A 0xEB470705 1 ADC r7,r7,r5 false
+Instruction 3649 S:0xC004015E 0xE9CA670A 1 STRD r6,r7,[r10,#0x28] false
+Instruction 3650 S:0xC0040162 0xE9DB6704 1 LDRD r6,r7,[r11,#0x10] false
+Instruction 3651 S:0xC0040166 0x18B6 2 ADDS r6,r6,r2 false
+Instruction 3652 S:0xC0040168 0xEB470705 1 ADC r7,r7,r5 false
+Instruction 3653 S:0xC004016C 0xE9CB6704 1 STRD r6,r7,[r11,#0x10] false
+Instruction 3654 S:0xC0040170 0xF8DA1000 1 LDR r1,[r10,#0] false
+Instruction 3655 S:0xC0040174 0xF5B16F80 2 CMP r1,#0x400 false
+Instruction 3656 S:0xC0040178 0xBF04 0 ITT EQ false
+Instruction 3657 S:0xC004017A 0x4690 1 MOV r8,r2 false
+Instruction 3658 S:0xC004017C 0x46A9 0 MOV r9,r5 false
+Instruction 3659 S:0xC004017E 0xD13D 1 BNE {pc}+0x7e ; 0xc00401fc true fail
+Instruction 3660 S:0xC0040180 0xE9DA670C 20 LDRD r6,r7,[r10,#0x30] false
+Instruction 3661 S:0xC0040184 0x4658 1 MOV r0,r11 false
+Instruction 3662 S:0xC0040186 0xEB160608 1 ADDS r6,r6,r8 false
+Instruction 3663 S:0xC004018A 0xEB470709 1 ADC r7,r7,r9 false
+Instruction 3664 S:0xC004018E 0xE9CA670C 1 STRD r6,r7,[r10,#0x30] false
+Instruction 3665 S:0xC0040192 0x9303 1 STR r3,[sp,#0xc] false
+Instruction 3666 S:0xC0040194 0xF8CDC008 1 STR r12,[sp,#8] false
+Instruction 3667 S:0xC0040198 0xF7FFFB06 0 BL {pc}-0x9f0 ; 0xc003f7a8 true
+Instruction 3668 S:0xC003F7A8 0xE92D03F0 1 PUSH {r4-r9} false
+Instruction 3669 S:0xC003F7AC 0xB500 6 PUSH {lr} false
+Instruction 3670 S:0xC003F7AE 0xF85DEB04 2 POP {lr} false
+Instruction 3671 S:0xC003F7B2 0x6B03 1 LDR r3,[r0,#0x30] false
+Instruction 3672 S:0xC003F7B4 0xE9D04506 2 LDRD r4,r5,[r0,#0x18] false
+Instruction 3673 S:0xC003F7B8 0x2B00 1 CMP r3,#0 false
+Instruction 3674 S:0xC003F7BA 0xD029 0 BEQ {pc}+0x56 ; 0xc003f810 true fail
+Instruction 3675 S:0xC003F7BC 0x6AC1 1 LDR r1,[r0,#0x2c] false
+Instruction 3676 S:0xC003F7BE 0xE9D3230C 7 LDRD r2,r3,[r3,#0x30] false
+Instruction 3677 S:0xC003F7C2 0xB171 1 CBZ r1,{pc}+0x20 ; 0xc003f7e2 true
+Instruction 3678 S:0xC003F7E2 0x4616 8 MOV r6,r2 false
+Instruction 3679 S:0xC003F7E4 0x461F 0 MOV r7,r3 false
+Instruction 3680 S:0xC003F7E6 0x1B36 1 SUBS r6,r6,r4 false
+Instruction 3681 S:0xC003F7E8 0xEB670705 1 SBC r7,r7,r5 false
+Instruction 3682 S:0xC003F7EC 0x2E01 1 CMP r6,#1 false
+Instruction 3683 S:0xC003F7EE 0xF1770100 1 SBCS r1,r7,#0 false
+Instruction 3684 S:0xC003F7F2 0xDB0A 0 BLT {pc}+0x18 ; 0xc003f80a true fail
+Instruction 3685 S:0xC003F7F4 0xE9C02306 3 STRD r2,r3,[r0,#0x18] false
+Instruction 3686 S:0xC003F7F8 0xF3BF8F5F 3 DMB false
+Instruction 3687 S:0xC003F7FC 0xE9D02306 32 LDRD r2,r3,[r0,#0x18] false
+Instruction 3688 S:0xC003F800 0xE9C02308 3 STRD r2,r3,[r0,#0x20] false
+Instruction 3689 S:0xC003F804 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 3690 S:0xC003F808 0x4770 3 BX lr true
+Instruction 3691 S:0xC004019C 0x9B03 2 LDR r3,[sp,#0xc] false
+Instruction 3692 S:0xC004019E 0xF8DA2128 1 LDR r2,[r10,#0x128] false
+Instruction 3693 S:0xC00401A2 0xF8CA3020 1 STR r3,[r10,#0x20] false
+Instruction 3694 S:0xC00401A6 0xF8DDC008 1 LDR r12,[sp,#8] false
+Instruction 3695 S:0xC00401AA 0xF8CAC024 1 STR r12,[r10,#0x24] false
+Instruction 3696 S:0xC00401AE 0xB112 1 CBZ r2,{pc}+8 ; 0xc00401b6 true
+Instruction 3697 S:0xC00401B6 0x4B24 20 LDR r3,[pc,#144] ; [0xC0040248] = 0xC0636008 false
+Instruction 3698 S:0xC00401B8 0xE9DA670C 3 LDRD r6,r7,[r10,#0x30] false
+Instruction 3699 S:0xC00401BC 0x685A 3 LDR r2,[r3,#4] false
+Instruction 3700 S:0xC00401BE 0x2A00 2 CMP r2,#0 false
+Instruction 3701 S:0xC00401C0 0xD12C 0 BNE {pc}+0x5c ; 0xc004021c true fail
+Instruction 3702 S:0xC00401C2 0xF8DA639C 1 LDR r6,[r10,#0x39c] false
+Instruction 3703 S:0xC00401C6 0xF8D630D8 5 LDR r3,[r6,#0xd8] false
+Instruction 3704 S:0xC00401CA 0x2B00 2 CMP r3,#0 false
+Instruction 3705 S:0xC00401CC 0xD0F0 0 BEQ {pc}-0x1c ; 0xc00401b0 true
+Instruction 3706 S:0xC00401B0 0xB005 1 ADD sp,sp,#0x14 false
+Instruction 3707 S:0xC00401B2 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Instruction 3708 S:0xC0043046 0xF8D6A124 5 LDR r10,[r6,#0x124] false
+Instruction 3709 S:0xC004304A 0xF8D63128 1 LDR r3,[r6,#0x128] false
+Instruction 3710 S:0xC004304E 0xF8DA2084 2 LDR r2,[r10,#0x84] false
+Instruction 3711 S:0xC0043052 0xF8D244C0 3 LDR r4,[r2,#0x4c0] false
+Instruction 3712 S:0xC0043056 0x9406 1 STR r4,[sp,#0x18] false
+Instruction 3713 S:0xC0043058 0x2B00 0 CMP r3,#0 false
+Instruction 3714 S:0xC004305A 0xF00081D3 1 BEQ.W {pc}+0x3aa ; 0xc0043404 true
+Instruction 3715 S:0xC0043404 0xF5026290 39 ADD r2,r2,#0x480 false
+Instruction 3716 S:0xC0043408 0xE9D24500 3 LDRD r4,r5,[r2,#0] false
+Instruction 3717 S:0xC004340C 0xE62D 1 B {pc}-0x3a2 ; 0xc004306a true
+Instruction 3718 S:0xC004306A 0x46B3 1 MOV r11,r6 false
+Instruction 3719 S:0xC004306C 0x69F2 1 LDR r2,[r6,#0x1c] false
+Instruction 3720 S:0xC004306E 0xF8DA3030 1 LDR r3,[r10,#0x30] false
+Instruction 3721 S:0xC0043072 0xE9FB014E 1 LDRD r0,r1,[r11,#0x138]! false
+Instruction 3722 S:0xC0043076 0x920C 1 STR r2,[sp,#0x30] false
+Instruction 3723 S:0xC0043078 0x1A20 1 SUBS r0,r4,r0 false
+Instruction 3724 S:0xC004307A 0xEB650101 1 SBC r1,r5,r1 false
+Instruction 3725 S:0xC004307E 0x9308 1 STR r3,[sp,#0x20] false
+Instruction 3726 S:0xC0043080 0xF7FCFC6C 0 BL {pc}-0x3724 ; 0xc003f95c true
+Instruction 3727 S:0xC003F95C 0xE92D03F0 1 PUSH {r4-r9} false
+Instruction 3728 S:0xC003F960 0xB500 18 PUSH {lr} false
+Instruction 3729 S:0xC003F962 0xF85DEB04 2 POP {lr} false
+Instruction 3730 S:0xC003F966 0xF64B7640 1 MOV r6,#0xbf40 false
+Instruction 3731 S:0xC003F96A 0xF2CC0664 1 MOVT r6,#0xc064 false
+Instruction 3732 S:0xC003F96E 0x6876 5 LDR r6,[r6,#4] false
+Instruction 3733 S:0xC003F970 0xFBA18906 3 UMULL r8,r9,r1,r6 false
+Instruction 3734 S:0xC003F974 0xEA4F7CE6 1 ASR r12,r6,#31 false
+Instruction 3735 S:0xC003F978 0xFBA06706 1 UMULL r6,r7,r0,r6 false
+Instruction 3736 S:0xC003F97C 0xFB01990C 1 MLA r9,r1,r12,r9 false
+Instruction 3737 S:0xC003F980 0xEA4F4408 1 LSL r4,r8,#16 false
+Instruction 3738 S:0xC003F984 0xFB00770C 1 MLA r7,r0,r12,r7 false
+Instruction 3739 S:0xC003F988 0x0C32 1 LSRS r2,r6,#16 false
+Instruction 3740 S:0xC003F98A 0xEA4F4509 1 LSL r5,r9,#16 false
+Instruction 3741 S:0xC003F98E 0xEA454518 1 ORR r5,r5,r8,LSR #16 false
+Instruction 3742 S:0xC003F992 0xEA424207 1 ORR r2,r2,r7,LSL #16 false
+Instruction 3743 S:0xC003F996 0x0C3B 1 LSRS r3,r7,#16 false
+Instruction 3744 S:0xC003F998 0x1912 1 ADDS r2,r2,r4 false
+Instruction 3745 S:0xC003F99A 0xEB430305 1 ADC r3,r3,r5 false
+Instruction 3746 S:0xC003F99E 0x4610 0 MOV r0,r2 false
+Instruction 3747 S:0xC003F9A0 0x4619 1 MOV r1,r3 false
+Instruction 3748 S:0xC003F9A2 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 3749 S:0xC003F9A6 0x4770 3 BX lr true
+Instruction 3750 S:0xC0043084 0x2800 1 CMP r0,#0 false
+Instruction 3751 S:0xC0043086 0xF1710E00 1 SBCS lr,r1,#0 false
+Instruction 3752 S:0xC004308A 0xF2C081A9 0 BLT.W {pc}+0x356 ; 0xc00433e0 true fail
+Instruction 3753 S:0xC004308E 0xEA4F2890 14 LSR r8,r0,#10 false
+Instruction 3754 S:0xC0043092 0xEA4F2991 1 LSR r9,r1,#10 false
+Instruction 3755 S:0xC0043096 0xEA485881 1 ORR r8,r8,r1,LSL #22 false
+Instruction 3756 S:0xC004309A 0xEA580009 1 ORRS r0,r8,r9 false
+Instruction 3757 S:0xC004309E 0xF00080CF 18 BEQ.W {pc}+0x1a2 ; 0xc0043240 true fail
+Instruction 3758 S:0xC00430A2 0xF64B7140 72 MOV r1,#0xbf40 false
+Instruction 3759 S:0xC00430A6 0xE9CB4500 1 STRD r4,r5,[r11,#0] false
+Instruction 3760 S:0xC00430AA 0xF2CC0164 1 MOVT r1,#0xc064 false
+Instruction 3761 S:0xC00430AE 0x680A 3 LDR r2,[r1,#0] false
+Instruction 3762 S:0xC00430B0 0x2A00 2 CMP r2,#0 false
+Instruction 3763 S:0xC00430B2 0xF000819F 0 BEQ.W {pc}+0x342 ; 0xc00433f4 true fail
+Instruction 3764 S:0xC00430B6 0x9A06 73 LDR r2,[sp,#0x18] false
+Instruction 3765 S:0xC00430B8 0x2400 1 MOVS r4,#0 false
+Instruction 3766 S:0xC00430BA 0x9407 1 STR r4,[sp,#0x1c] false
+Instruction 3767 S:0xC00430BC 0xEB011B02 1 ADD r11,r1,r2,LSL #4 false
+Instruction 3768 S:0xC00430C0 0xF8DBB098 14 LDR r11,[r11,#0x98] false
+Instruction 3769 S:0xC00430C4 0xF8CDB018 1 STR r11,[sp,#0x18] false
+Instruction 3770 S:0xC00430C8 0x9B08 1 LDR r3,[sp,#0x20] false
+Instruction 3771 S:0xC00430CA 0xF24032FF 0 MOV r2,#0x3ff false
+Instruction 3772 S:0xC00430CE 0xF8D64134 1 LDR r4,[r6,#0x134] false
+Instruction 3773 S:0xC00430D2 0x1AF5 1 SUBS r5,r6,r3 false
+Instruction 3774 S:0xC00430D4 0x2300 0 MOVS r3,#0 false
+Instruction 3775 S:0xC00430D6 0xF1D50C00 1 RSBS r12,r5,#0 false
+Instruction 3776 S:0xC00430DA 0xEB5C0C05 1 ADCS r12,r12,r5 false
+Instruction 3777 S:0xC00430DE 0x05A5 1 LSLS r5,r4,#22 false
+Instruction 3778 S:0xC00430E0 0x0DAD 2 LSRS r5,r5,#22 false
+Instruction 3779 S:0xC00430E2 0xEB180005 1 ADDS r0,r8,r5 false
+Instruction 3780 S:0xC00430E6 0xF1490100 1 ADC r1,r9,#0 false
+Instruction 3781 S:0xC00430EA 0x428B 1 CMP r3,r1 false
+Instruction 3782 S:0xC00430EC 0xBF08 0 IT EQ false
+Instruction 3783 S:0xC00430EE 0x4282 1 CMP r2,r0 false
+Instruction 3784 S:0xC00430F0 0xBF28 0 IT CS false
+Instruction 3785 S:0xC00430F2 0x2100 1 MOVS r1,#0 false fail
+Instruction 3786 S:0xC00430F4 0xD276 0 BCS {pc}+0xf0 ; 0xc00431e4 true fail
+Instruction 3787 S:0xC00430F6 0xF5C56280 1 RSB r2,r5,#0x400 false
+Instruction 3788 S:0xC00430FA 0x9B0C 1 LDR r3,[sp,#0x30] false
+Instruction 3789 S:0xC00430FC 0xF8D65130 1 LDR r5,[r6,#0x130] false
+Instruction 3790 S:0xC0043100 0xFB02F10B 61 MUL r1,r2,r11 false
+Instruction 3791 S:0xC0043104 0x0A89 3 LSRS r1,r1,#10 false
+Instruction 3792 S:0xC0043106 0xB113 1 CBZ r3,{pc}+8 ; 0xc004310e true fail
+Instruction 3793 S:0xC0043108 0x194D 1 ADDS r5,r1,r5 false
+Instruction 3794 S:0xC004310A 0xF8C65130 1 STR r5,[r6,#0x130] false
+Instruction 3795 S:0xC004310E 0xF1BC0F00 0 CMP r12,#0 false
+Instruction 3796 S:0xC0043112 0xD004 1 BEQ {pc}+0xc ; 0xc004311e true fail
+Instruction 3797 S:0xC0043114 0xF8D63160 1 LDR r3,[r6,#0x160] false
+Instruction 3798 S:0xC0043118 0x185B 2 ADDS r3,r3,r1 false
+Instruction 3799 S:0xC004311A 0xF8C63160 1 STR r3,[r6,#0x160] false
+Instruction 3800 S:0xC004311E 0xEBB80002 11 SUBS r0,r8,r2 false
+Instruction 3801 S:0xC0043122 0xEB6971E2 1 SBC r1,r9,r2,ASR #31 false
+Instruction 3802 S:0xC0043126 0x1914 1 ADDS r4,r2,r4 false
+Instruction 3803 S:0xC0043128 0x2300 0 MOVS r3,#0 false
+Instruction 3804 S:0xC004312A 0xF8C64134 1 STR r4,[r6,#0x134] false
+Instruction 3805 S:0xC004312E 0xEA4F2990 1 LSR r9,r0,#10 false
+Instruction 3806 S:0xC0043132 0x0A8A 1 LSRS r2,r1,#10 false
+Instruction 3807 S:0xC0043134 0xEA495E81 1 ORR lr,r9,r1,LSL #22 false
+Instruction 3808 S:0xC0043138 0x920F 1 STR r2,[sp,#0x3c] false
+Instruction 3809 S:0xC004313A 0xF8CDE038 1 STR lr,[sp,#0x38] false
+Instruction 3810 S:0xC004313E 0xF24032FF 16 MOV r2,#0x3ff false
+Instruction 3811 S:0xC0043142 0xEA000802 1 AND r8,r0,r2 false
+Instruction 3812 S:0xC0043146 0xEA010903 1 AND r9,r1,r3 false
+Instruction 3813 S:0xC004314A 0xE9DD010E 1 LDRD r0,r1,[sp,#0x38] false
+Instruction 3814 S:0xC004314E 0x2201 1 MOVS r2,#1 false
+Instruction 3815 S:0xC0043150 0x2300 0 MOVS r3,#0 false
+Instruction 3816 S:0xC0043152 0x1880 1 ADDS r0,r0,r2 false
+Instruction 3817 S:0xC0043154 0xF44F62FC 0 MOV r2,#0x7e0 false
+Instruction 3818 S:0xC0043158 0xEB410103 1 ADC r1,r1,r3 false
+Instruction 3819 S:0xC004315C 0x2300 0 MOVS r3,#0 false
+Instruction 3820 S:0xC004315E 0x428B 1 CMP r3,r1 false
+Instruction 3821 S:0xC0043160 0xBF08 14 IT EQ false
+Instruction 3822 S:0xC0043162 0x4282 1 CMP r2,r0 false
+Instruction 3823 S:0xC0043164 0xE9CD0108 1 STRD r0,r1,[sp,#0x20] false
+Instruction 3824 S:0xC0043168 0xF0C08215 1 BCC.W {pc}+0x42e ; 0xc0043596 true fail
+Instruction 3825 S:0xC004316C 0x9B08 1 LDR r3,[sp,#0x20] false
+Instruction 3826 S:0xC004316E 0x4601 0 MOV r1,r0 false
+Instruction 3827 S:0xC0043170 0x2B1F 2 CMP r3,#0x1f false
+Instruction 3828 S:0xC0043172 0xF2008243 0 BHI.W {pc}+0x48a ; 0xc00435fc true fail
+Instruction 3829 S:0xC0043176 0xF24830C8 1 MOV r0,#0x83c8 false
+Instruction 3830 S:0xC004317A 0xF2CC003E 1 MOVT r0,#0xc03e false
+Instruction 3831 S:0xC004317E 0xF850E021 26 LDR lr,[r0,r1,LSL #2] false
+Instruction 3832 S:0xC0043182 0x48A3 13 LDR r0,[pc,#652] ; [0xC0043410] = 0xC03E83C8 false
+Instruction 3833 S:0xC0043184 0xFBAE2305 2 UMULL r2,r3,lr,r5 false
+Instruction 3834 S:0xC0043188 0xFBAE4504 1 UMULL r4,r5,lr,r4 false
+Instruction 3835 S:0xC004318C 0x461C 1 MOV r4,r3 false
+Instruction 3836 S:0xC004318E 0xF8C63130 1 STR r3,[r6,#0x130] false
+Instruction 3837 S:0xC0043192 0xF8D63160 1 LDR r3,[r6,#0x160] false
+Instruction 3838 S:0xC0043196 0xF8C65134 1 STR r5,[r6,#0x134] false
+Instruction 3839 S:0xC004319A 0xF8502021 1 LDR r2,[r0,r1,LSL #2] false
+Instruction 3840 S:0xC004319E 0xFBA22303 3 UMULL r2,r3,r2,r3 false
+Instruction 3841 S:0xC00431A2 0xF8C63160 1 STR r3,[r6,#0x160] false
+Instruction 3842 S:0xC00431A6 0xE9DD010E 3 LDRD r0,r1,[sp,#0x38] false
+Instruction 3843 S:0xC00431AA 0xF8CDC008 3 STR r12,[sp,#8] false
+Instruction 3844 S:0xC00431AE 0xF7FEFA8F 0 BL {pc}-0x1ade ; 0xc00416d0 true
+Instruction 3845 S:0xC00416D0 0xE92D03F0 11 PUSH {r4-r9} false
+Instruction 3846 S:0xC00416D4 0xB500 5 PUSH {lr} false
+Instruction 3847 S:0xC00416D6 0xF85DEB04 2 POP {lr} false
+Instruction 3848 S:0xC00416DA 0x2620 0 MOVS r6,#0x20 false
+Instruction 3849 S:0xC00416DC 0x2700 1 MOVS r7,#0 false
+Instruction 3850 S:0xC00416DE 0x428F 1 CMP r7,r1 false
+Instruction 3851 S:0xC00416E0 0xBF08 8 IT EQ false
+Instruction 3852 S:0xC00416E2 0x4286 1 CMP r6,r0 false
+Instruction 3853 S:0xC00416E4 0xD307 0 BCC {pc}+0x12 ; 0xc00416f6 true fail
+Instruction 3854 S:0xC00416E6 0x4B31 13 LDR r3,[pc,#196] ; [0xC00417AC] false
+Instruction 3855 S:0xC00416E8 0xEB030080 2 ADD r0,r3,r0,LSL #2 false
+Instruction 3856 S:0xC00416EC 0xF8D000FC 13 LDR r0,[r0,#0xfc] false
+Instruction 3857 S:0xC00416F0 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 3858 S:0xC00416F4 0x4770 4 BX lr true
+Instruction 3859 S:0xC00431B2 0x9B0C 2 LDR r3,[sp,#0x30] false
+Instruction 3860 S:0xC00431B4 0xF8DDC008 1 LDR r12,[sp,#8] false
+Instruction 3861 S:0xC00431B8 0xFB0BFB00 1 MUL r11,r11,r0 false
+Instruction 3862 S:0xC00431BC 0xEA4F2B9B 3 LSR r11,r11,#10 false
+Instruction 3863 S:0xC00431C0 0xB113 36 CBZ r3,{pc}+8 ; 0xc00431c8 true fail
+Instruction 3864 S:0xC00431C2 0x445C 1 ADD r4,r4,r11 false
+Instruction 3865 S:0xC00431C4 0xF8C64130 1 STR r4,[r6,#0x130] false
+Instruction 3866 S:0xC00431C8 0xF1BC0F00 1 CMP r12,#0 false
+Instruction 3867 S:0xC00431CC 0xD004 0 BEQ {pc}+0xc ; 0xc00431d8 true fail
+Instruction 3868 S:0xC00431CE 0xF8D63160 27 LDR r3,[r6,#0x160] false
+Instruction 3869 S:0xC00431D2 0x445B 2 ADD r3,r3,r11 false
+Instruction 3870 S:0xC00431D4 0xF8C63160 1 STR r3,[r6,#0x160] false
+Instruction 3871 S:0xC00431D8 0xF8D64134 1 LDR r4,[r6,#0x134] false
+Instruction 3872 S:0xC00431DC 0x2101 0 MOVS r1,#1 false
+Instruction 3873 S:0xC00431DE 0x1824 2 ADDS r4,r4,r0 false
+Instruction 3874 S:0xC00431E0 0xF8C64134 1 STR r4,[r6,#0x134] false
+Instruction 3875 S:0xC00431E4 0xF8DDE018 1 LDR lr,[sp,#0x18] false
+Instruction 3876 S:0xC00431E8 0x9D07 1 LDR r5,[sp,#0x1c] false
+Instruction 3877 S:0xC00431EA 0xFBA8230E 2 UMULL r2,r3,r8,lr false
+Instruction 3878 S:0xC00431EE 0xFB08F005 1 MUL r0,r8,r5 false
+Instruction 3879 S:0xC00431F2 0xFB0E0009 1 MLA r0,lr,r9,r0 false
+Instruction 3880 S:0xC00431F6 0x0A92 1 LSRS r2,r2,#10 false
+Instruction 3881 S:0xC00431F8 0x18C3 1 ADDS r3,r0,r3 false
+Instruction 3882 S:0xC00431FA 0xEA425283 2 ORR r2,r2,r3,LSL #22 false
+Instruction 3883 S:0xC00431FE 0x9B0C 1 LDR r3,[sp,#0x30] false
+Instruction 3884 S:0xC0043200 0xB123 2 CBZ r3,{pc}+0xc ; 0xc004320c true fail
+Instruction 3885 S:0xC0043202 0xF8D63130 8 LDR r3,[r6,#0x130] false
+Instruction 3886 S:0xC0043206 0x189B 2 ADDS r3,r3,r2 false
+Instruction 3887 S:0xC0043208 0xF8C63130 1 STR r3,[r6,#0x130] false
+Instruction 3888 S:0xC004320C 0xF1BC0F00 0 CMP r12,#0 false
+Instruction 3889 S:0xC0043210 0xD004 1 BEQ {pc}+0xc ; 0xc004321c true fail
+Instruction 3890 S:0xC0043212 0xF8D63160 1 LDR r3,[r6,#0x160] false
+Instruction 3891 S:0xC0043216 0x189B 2 ADDS r3,r3,r2 false
+Instruction 3892 S:0xC0043218 0xF8C63160 1 STR r3,[r6,#0x160] false
+Instruction 3893 S:0xC004321C 0x4444 1 ADD r4,r4,r8 false
+Instruction 3894 S:0xC004321E 0xF8C64134 10 STR r4,[r6,#0x134] false
+Instruction 3895 S:0xC0043222 0xB169 1 CBZ r1,{pc}+0x1e ; 0xc0043240 true fail
+Instruction 3896 S:0xC0043224 0x4630 1 MOV r0,r6 false
+Instruction 3897 S:0xC0043226 0xF7FDF851 0 BL {pc}-0x2f5a ; 0xc00402cc true
+Instruction 3898 S:0xC00402CC 0xE92D4FF8 2 PUSH {r3-r11,lr} false
+Instruction 3899 S:0xC00402D0 0xB500 7 PUSH {lr} false
+Instruction 3900 S:0xC00402D2 0xF85DEB04 2 POP {lr} false
+Instruction 3901 S:0xC00402D6 0x4606 0 MOV r6,r0 false
+Instruction 3902 S:0xC00402D8 0xF8D05128 1 LDR r5,[r0,#0x128] false
+Instruction 3903 S:0xC00402DC 0xF8D0A148 2 LDR r10,[r0,#0x148] false
+Instruction 3904 S:0xC00402E0 0x2D00 1 CMP r5,#0 false
+Instruction 3905 S:0xC00402E2 0xD067 0 BEQ {pc}+0xd2 ; 0xc00403b4 true
+Instruction 3906 S:0xC00403B4 0xF8D04134 33 LDR r4,[r0,#0x134] false
+Instruction 3907 S:0xC00403B8 0xF1A00538 1 SUB r5,r0,#0x38 false
+Instruction 3908 S:0xC00403BC 0xF8D08130 1 LDR r8,[r0,#0x130] false
+Instruction 3909 S:0xC00403C0 0x6800 17 LDR r0,[r0,#0] false
+Instruction 3910 S:0xC00403C2 0x3401 0 ADDS r4,#1 false
+Instruction 3911 S:0xC00403C4 0x4621 1 MOV r1,r4 false
+Instruction 3912 S:0xC00403C6 0xFB00F008 2 MUL r0,r0,r8 false
+Instruction 3913 S:0xC00403CA 0xF211F883 1 BL {pc}+0x21110a ; 0xc02514d4 true
+Cycle Count 146 Tracing disabled
+Info Tracing enabled
+Instruction 3914 S:0xC00403CE 0x4B27 1 LDR r3,[pc,#156] ; [0xC004046C] = 0xC0635FF4 false
+Instruction 3915 S:0xC00403D0 0x685A 5 LDR r2,[r3,#4] false
+Instruction 3916 S:0xC00403D2 0x4607 0 MOV r7,r0 false
+Instruction 3917 S:0xC00403D4 0xF8C60148 3 STR r0,[r6,#0x148] false
+Instruction 3918 S:0xC00403D8 0xB98A 1 CBNZ r2,{pc}+0x26 ; 0xc00403fe true fail
+Instruction 3919 S:0xC00403DA 0xEA4F2088 1 LSL r0,r8,#10 false
+Instruction 3920 S:0xC00403DE 0x4621 0 MOV r1,r4 false
+Instruction 3921 S:0xC00403E0 0xF211F878 1 BL {pc}+0x2110f4 ; 0xc02514d4 true
+Cycle Count 58 Tracing disabled
+Info Tracing enabled
+Instruction 3922 S:0xC00403E4 0x4607 1 MOV r7,r0 false
+Instruction 3923 S:0xC00403E6 0xF8C6014C 1 STR r0,[r6,#0x14c] false
+Instruction 3924 S:0xC00403EA 0x4B21 1 LDR r3,[pc,#132] ; [0xC0040470] = 0xC0635FE0 false
+Instruction 3925 S:0xC00403EC 0x685A 3 LDR r2,[r3,#4] false
+Instruction 3926 S:0xC00403EE 0x2A00 2 CMP r2,#0 false
+Instruction 3927 S:0xC00403F0 0xD12E 0 BNE {pc}+0x60 ; 0xc0040450 true fail
+Instruction 3928 S:0xC00403F2 0xF8D60148 1 LDR r0,[r6,#0x148] false
+Instruction 3929 S:0xC00403F6 0xEBCA0000 2 RSB r0,r10,r0 false
+Instruction 3930 S:0xC00403FA 0xE8BD8FF8 1 POP {r3-r11,pc} true
+Instruction 3931 S:0xC004322A 0x69F3 17 LDR r3,[r6,#0x1c] false
+Instruction 3932 S:0xC004322C 0x2B00 2 CMP r3,#0 false
+Instruction 3933 S:0xC004322E 0xF00080F5 1 BEQ.W {pc}+0x1ee ; 0xc004341c true fail
+Instruction 3934 S:0xC0043232 0xE9DA2312 23 LDRD r2,r3,[r10,#0x48] false
+Instruction 3935 S:0xC0043236 0x1812 2 ADDS r2,r2,r0 false
+Instruction 3936 S:0xC0043238 0xEB4373E0 1 ADC r3,r3,r0,ASR #31 false
+Instruction 3937 S:0xC004323C 0xE9CA2312 1 STRD r2,r3,[r10,#0x48] false
+Instruction 3938 S:0xC0043240 0x4638 1 MOV r0,r7 false
+Instruction 3939 S:0xC0043242 0x2101 0 MOVS r1,#1 false
+Instruction 3940 S:0xC0043244 0xF7FCFCAA 1 BL {pc}-0x36a8 ; 0xc003fb9c true
+Instruction 3941 S:0xC003FB9C 0xE92D0FF0 1 PUSH {r4-r11} false
+Instruction 3942 S:0xC003FBA0 0xB500 7 PUSH {lr} false
+Instruction 3943 S:0xC003FBA2 0xF85DEB04 2 POP {lr} false
+Instruction 3944 S:0xC003FBA6 0xF8D06084 1 LDR r6,[r0,#0x84] false
+Instruction 3945 S:0xC003FBAA 0xE9D0451A 2 LDRD r4,r5,[r0,#0x68] false
+Instruction 3946 S:0xC003FBAE 0xF8D67480 1 LDR r7,[r6,#0x480] false
+Instruction 3947 S:0xC003FBB2 0xF8D66484 1 LDR r6,[r6,#0x484] false
+Instruction 3948 S:0xC003FBB6 0x0D3A 2 LSRS r2,r7,#20 false
+Instruction 3949 S:0xC003FBB8 0xEA423206 1 ORR r2,r2,r6,LSL #12 false
+Instruction 3950 S:0xC003FBBC 0x0D33 1 LSRS r3,r6,#20 false
+Instruction 3951 S:0xC003FBBE 0x1B14 1 SUBS r4,r2,r4 false
+Instruction 3952 S:0xC003FBC0 0xEB630505 1 SBC r5,r3,r5 false
+Instruction 3953 S:0xC003FBC4 0xEA540605 1 ORRS r6,r4,r5 false
+Instruction 3954 S:0xC003FBC8 0xBF14 0 ITE NE false
+Instruction 3955 S:0xC003FBCA 0x2600 1 MOVS r6,#0 false
+Instruction 3956 S:0xC003FBCC 0x2601 0 MOVS r6,#1 false fail
+Instruction 3957 S:0xC003FBCE 0x2900 1 CMP r1,#0 false
+Instruction 3958 S:0xC003FBD0 0xBF14 0 ITE NE false
+Instruction 3959 S:0xC003FBD2 0x2600 1 MOVS r6,#0 false
+Instruction 3960 S:0xC003FBD4 0xF0060601 1 AND r6,r6,#1 false fail
+Instruction 3961 S:0xC003FBD8 0x2E00 1 CMP r6,#0 false
+Instruction 3962 S:0xC003FBDA 0xD167 0 BNE {pc}+0xd2 ; 0xc003fcac true fail
+Instruction 3963 S:0xC003FBDC 0xF1000C60 1 ADD r12,r0,#0x60 false
+Instruction 3964 S:0xC003FBE0 0xE8DC677F 7 LDREXD r6,r7,[r12] false
+Instruction 3965 S:0xC003FBE4 0xEA560807 2 ORRS r8,r6,r7 false
+Instruction 3966 S:0xC003FBE8 0xD163 0 BNE {pc}+0xca ; 0xc003fcb2 true fail
+Instruction 3967 S:0xC003FBEA 0xE9D06714 1 LDRD r6,r7,[r0,#0x50] false
+Instruction 3968 S:0xC003FBEE 0xEA540C05 1 ORRS r12,r4,r5 false
+Instruction 3969 S:0xC003FBF2 0xD027 0 BEQ {pc}+0x52 ; 0xc003fc44 true fail
+Instruction 3970 S:0xC003FBF4 0xF44F68FC 1 MOV r8,#0x7e0 false
+Instruction 3971 S:0xC003FBF8 0xF04F0900 0 MOV r9,#0 false
+Instruction 3972 S:0xC003FBFC 0x45A9 1 CMP r9,r5 false
+Instruction 3973 S:0xC003FBFE 0xBF08 0 IT EQ false
+Instruction 3974 S:0xC003FC00 0x45A0 1 CMP r8,r4 false
+Instruction 3975 S:0xC003FC02 0xF0C0808F 0 BCC.W {pc}+0x122 ; 0xc003fd24 true fail
+Instruction 3976 S:0xC003FC06 0x2C1F 9 CMP r4,#0x1f false
+Instruction 3977 S:0xC003FC08 0x46A4 1 MOV r12,r4 false
+Instruction 3978 S:0xC003FC0A 0xD871 0 BHI {pc}+0xe6 ; 0xc003fcf0 true fail
+Instruction 3979 S:0xC003FC0C 0xF8DF8120 3 LDR r8,[pc,#288] ; [0xC003FD30] = 0xC03E83C8 false
+Instruction 3980 S:0xC003FC10 0xF04F0B00 0 MOV r11,#0 false
+Instruction 3981 S:0xC003FC14 0xF858C02C 5 LDR r12,[r8,r12,LSL #2] false
+Instruction 3982 S:0xC003FC18 0xFBAC8906 3 UMULL r8,r9,r12,r6 false
+Instruction 3983 S:0xC003FC1C 0xFB0C9A07 2 MLA r10,r12,r7,r9 false
+Instruction 3984 S:0xC003FC20 0xE9C0AB14 3 STRD r10,r11,[r0,#0x50] false
+Instruction 3985 S:0xC003FC24 0xF1000C58 1 ADD r12,r0,#0x58 false
+Instruction 3986 S:0xC003FC28 0xE8DC677F 8 LDREXD r6,r7,[r12] false
+Instruction 3987 S:0xC003FC2C 0x1936 2 ADDS r6,r6,r4 false
+Instruction 3988 S:0xC003FC2E 0xEB470705 1 ADC r7,r7,r5 false
+Instruction 3989 S:0xC003FC32 0xE8CC6778 7 STREXD r8,r6,r7,[r12] false
+Instruction 3990 S:0xC003FC36 0xF0980F00 2 TEQ r8,#0 false
+Instruction 3991 S:0xC003FC3A 0xD1F5 0 BNE {pc}-0x12 ; 0xc003fc28 true fail
+Instruction 3992 S:0xC003FC3C 0x4656 1 MOV r6,r10 false
+Instruction 3993 S:0xC003FC3E 0x465F 0 MOV r7,r11 false
+Instruction 3994 S:0xC003FC40 0xE9C0231A 1 STRD r2,r3,[r0,#0x68] false
+Instruction 3995 S:0xC003FC44 0xE9D0451E 1 LDRD r4,r5,[r0,#0x78] false
+Instruction 3996 S:0xC003FC48 0xE9D02312 1 LDRD r2,r3,[r0,#0x48] false
+Instruction 3997 S:0xC003FC4C 0xF8D0C094 1 LDR r12,[r0,#0x94] false
+Instruction 3998 S:0xC003FC50 0x1B12 1 SUBS r2,r2,r4 false
+Instruction 3999 S:0xC003FC52 0xEB630305 1 SBC r3,r3,r5 false
+Instruction 4000 S:0xC003FC56 0x1992 1 ADDS r2,r2,r6 false
+Instruction 4001 S:0xC003FC58 0xEB430307 1 ADC r3,r3,r7 false
+Instruction 4002 S:0xC003FC5C 0xB999 1 CBNZ r1,{pc}+0x2a ; 0xc003fc86 true
+Instruction 4003 S:0xC003FC86 0xF10C0130 9 ADD r1,r12,#0x30 false
+Instruction 4004 S:0xC003FC8A 0xE8D1457F 17 LDREXD r4,r5,[r1] false
+Instruction 4005 S:0xC003FC8E 0x18A4 2 ADDS r4,r4,r2 false
+Instruction 4006 S:0xC003FC90 0xEB450503 1 ADC r5,r5,r3 false
+Instruction 4007 S:0xC003FC94 0xE8C14576 22 STREXD r6,r4,r5,[r1] false
+Instruction 4008 S:0xC003FC98 0xF0960F00 2 TEQ r6,#0 false
+Instruction 4009 S:0xC003FC9C 0xD1F5 0 BNE {pc}-0x12 ; 0xc003fc8a true fail
+Instruction 4010 S:0xC003FC9E 0xE9D0451E 9 LDRD r4,r5,[r0,#0x78] false
+Instruction 4011 S:0xC003FCA2 0x18A4 2 ADDS r4,r4,r2 false
+Instruction 4012 S:0xC003FCA4 0xEB450503 1 ADC r5,r5,r3 false
+Instruction 4013 S:0xC003FCA8 0xE9C0451E 1 STRD r4,r5,[r0,#0x78] false
+Instruction 4014 S:0xC003FCAC 0xE8BD0FF0 1 POP {r4-r11} false
+Instruction 4015 S:0xC003FCB0 0x4770 4 BX lr true
+Instruction 4016 S:0xC0043248 0x9D0D 2 LDR r5,[sp,#0x34] false
+Instruction 4017 S:0xC004324A 0x2D00 2 CMP r5,#0 false
+Instruction 4018 S:0xC004324C 0xF04080CB 0 BNE.W {pc}+0x19a ; 0xc00433e6 true fail
+Instruction 4019 S:0xC0043250 0xF24C5E68 1 MOV lr,#0xc568 false
+Instruction 4020 S:0xC0043254 0xF2CC0E5F 1 MOVT lr,#0xc05f false
+Instruction 4021 S:0xC0043258 0xF8DE3000 5 LDR r3,[lr,#0] false
+Instruction 4022 S:0xC004325C 0x05D8 3 LSLS r0,r3,#23 false
+Instruction 4023 S:0xC004325E 0xD404 0 BMI {pc}+0xc ; 0xc004326a true fail
+Instruction 4024 S:0xC0043260 0xF8D73084 1 LDR r3,[r7,#0x84] false
+Instruction 4025 S:0xC0043264 0xF8D33538 66 LDR r3,[r3,#0x538] false
+Instruction 4026 S:0xC0043268 0xBB5B 2 CBNZ r3,{pc}+0x5a ; 0xc00432c2 true fail
+Instruction 4027 S:0xC004326A 0x68BB 8 LDR r3,[r7,#8] false
+Instruction 4028 S:0xC004326C 0x2B01 2 CMP r3,#1 false
+Instruction 4029 S:0xC004326E 0xD928 1 BLS {pc}+0x54 ; 0xc00432c2 true
+Instruction 4030 S:0xC00432C2 0xF8D66120 17 LDR r6,[r6,#0x120] false
+Instruction 4031 S:0xC00432C6 0x2E00 2 CMP r6,#0 false
+Instruction 4032 S:0xC00432C8 0xF47FAEB8 1 BNE {pc}-0x28c ; 0xc004303c true fail
+Instruction 4033 S:0xC00432CC 0x9D0B 1 LDR r5,[sp,#0x2c] false
+Instruction 4034 S:0xC00432CE 0xF5056390 2 ADD r3,r5,#0x480 false
+Instruction 4035 S:0xC00432D2 0xF50569B4 1 ADD r9,r5,#0x5a0 false
+Instruction 4036 S:0xC00432D6 0xF8D584C0 1 LDR r8,[r5,#0x4c0] false
+Instruction 4037 S:0xC00432DA 0xE9D90100 12 LDRD r0,r1,[r9,#0] false
+Instruction 4038 S:0xC00432DE 0xE9D34500 1 LDRD r4,r5,[r3,#0] false
+Instruction 4039 S:0xC00432E2 0x1A20 2 SUBS r0,r4,r0 false
+Instruction 4040 S:0xC00432E4 0xEB650101 1 SBC r1,r5,r1 false
+Instruction 4041 S:0xC00432E8 0xF7FCFB38 0 BL {pc}-0x398c ; 0xc003f95c true
+Instruction 4042 S:0xC003F95C 0xE92D03F0 1 PUSH {r4-r9} false
+Instruction 4043 S:0xC003F960 0xB500 5 PUSH {lr} false
+Instruction 4044 S:0xC003F962 0xF85DEB04 2 POP {lr} false
+Instruction 4045 S:0xC003F966 0xF64B7640 0 MOV r6,#0xbf40 false
+Instruction 4046 S:0xC003F96A 0xF2CC0664 1 MOVT r6,#0xc064 false
+Instruction 4047 S:0xC003F96E 0x6876 3 LDR r6,[r6,#4] false
+Instruction 4048 S:0xC003F970 0xFBA18906 3 UMULL r8,r9,r1,r6 false
+Instruction 4049 S:0xC003F974 0xEA4F7CE6 1 ASR r12,r6,#31 false
+Instruction 4050 S:0xC003F978 0xFBA06706 1 UMULL r6,r7,r0,r6 false
+Instruction 4051 S:0xC003F97C 0xFB01990C 1 MLA r9,r1,r12,r9 false
+Instruction 4052 S:0xC003F980 0xEA4F4408 1 LSL r4,r8,#16 false
+Instruction 4053 S:0xC003F984 0xFB00770C 1 MLA r7,r0,r12,r7 false
+Instruction 4054 S:0xC003F988 0x0C32 1 LSRS r2,r6,#16 false
+Instruction 4055 S:0xC003F98A 0xEA4F4509 1 LSL r5,r9,#16 false
+Instruction 4056 S:0xC003F98E 0xEA454518 1 ORR r5,r5,r8,LSR #16 false
+Instruction 4057 S:0xC003F992 0xEA424207 1 ORR r2,r2,r7,LSL #16 false
+Instruction 4058 S:0xC003F996 0x0C3B 1 LSRS r3,r7,#16 false
+Instruction 4059 S:0xC003F998 0x1912 1 ADDS r2,r2,r4 false
+Instruction 4060 S:0xC003F99A 0xEB430305 1 ADC r3,r3,r5 false
+Instruction 4061 S:0xC003F99E 0x4610 0 MOV r0,r2 false
+Instruction 4062 S:0xC003F9A0 0x4619 1 MOV r1,r3 false
+Instruction 4063 S:0xC003F9A2 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 4064 S:0xC003F9A6 0x4770 3 BX lr true
+Instruction 4065 S:0xC00432EC 0x2800 1 CMP r0,#0 false
+Instruction 4066 S:0xC00432EE 0xF1710E00 1 SBCS lr,r1,#0 false
+Instruction 4067 S:0xC00432F2 0xF2C080EB 0 BLT.W {pc}+0x1da ; 0xc00434cc true fail
+Instruction 4068 S:0xC00432F6 0x0A86 1 LSRS r6,r0,#10 false
+Instruction 4069 S:0xC00432F8 0x0A8F 1 LSRS r7,r1,#10 false
+Instruction 4070 S:0xC00432FA 0xEA465681 1 ORR r6,r6,r1,LSL #22 false
+Instruction 4071 S:0xC00432FE 0xEA560E07 11 ORRS lr,r6,r7 false
+Instruction 4072 S:0xC0043302 0xF04080A6 0 BNE.W {pc}+0x150 ; 0xc0043452 true
+Instruction 4073 S:0xC0043452 0x4B86 30 LDR r3,[pc,#536] ; [0xC004366C] false
+Instruction 4074 S:0xC0043454 0xE9C94500 1 STRD r4,r5,[r9,#0] false
+Instruction 4075 S:0xC0043458 0x681A 2 LDR r2,[r3,#0] false
+Instruction 4076 S:0xC004345A 0x2A00 2 CMP r2,#0 false
+Instruction 4077 S:0xC004345C 0xD140 0 BNE {pc}+0x84 ; 0xc00434e0 true
+Instruction 4078 S:0xC00434E0 0xEB031308 26 ADD r3,r3,r8,LSL #4 false
+Instruction 4079 S:0xC00434E4 0xF04F0B00 0 MOV r11,#0 false
+Instruction 4080 S:0xC00434E8 0xF8D33098 3 LDR r3,[r3,#0x98] false
+Instruction 4081 S:0xC00434EC 0x469A 2 MOV r10,r3 false
+Instruction 4082 S:0xC00434EE 0x9308 1 STR r3,[sp,#0x20] false
+Instruction 4083 S:0xC00434F0 0xE7BC 0 B {pc}-0x84 ; 0xc004346c true
+Instruction 4084 S:0xC004346C 0xF8DD802C 1 LDR r8,[sp,#0x2c] false
+Instruction 4085 S:0xC0043470 0xF24030FF 0 MOV r0,#0x3ff false
+Instruction 4086 S:0xC0043474 0x2100 1 MOVS r1,#0 false
+Instruction 4087 S:0xC0043476 0xF8D8559C 2 LDR r5,[r8,#0x59c] false
+Instruction 4088 S:0xC004347A 0x05AA 3 LSLS r2,r5,#22 false
+Instruction 4089 S:0xC004347C 0x0D92 2 LSRS r2,r2,#22 false
+Instruction 4090 S:0xC004347E 0xEB160802 8 ADDS r8,r6,r2 false
+Instruction 4091 S:0xC0043482 0xF1470900 1 ADC r9,r7,#0 false
+Instruction 4092 S:0xC0043486 0x4549 1 CMP r1,r9 false
+Instruction 4093 S:0xC0043488 0xBF08 0 IT EQ false
+Instruction 4094 S:0xC004348A 0x4540 1 CMP r0,r8 false
+Instruction 4095 S:0xC004348C 0xD331 0 BCC {pc}+0x66 ; 0xc00434f2 true
+Instruction 4096 S:0xC00434F2 0xF5C26C80 2 RSB r12,r2,#0x400 false
+Instruction 4097 S:0xC00434F6 0x9C08 1 LDR r4,[sp,#0x20] false
+Instruction 4098 S:0xC00434F8 0xEBB6060C 1 SUBS r6,r6,r12 false
+Instruction 4099 S:0xC00434FC 0xEB6777EC 1 SBC r7,r7,r12,ASR #31 false
+Instruction 4100 S:0xC0043500 0x2201 16 MOVS r2,#1 false
+Instruction 4101 S:0xC0043502 0x2300 0 MOVS r3,#0 false
+Instruction 4102 S:0xC0043504 0x4465 1 ADD r5,r5,r12 false
+Instruction 4103 S:0xC0043506 0xEA4F2896 1 LSR r8,r6,#10 false
+Instruction 4104 S:0xC004350A 0x4006 1 ANDS r6,r6,r0 false
+Instruction 4105 S:0xC004350C 0xFB0CFE04 1 MUL lr,r12,r4 false
+Instruction 4106 S:0xC0043510 0x980B 1 LDR r0,[sp,#0x2c] false
+Instruction 4107 S:0xC0043512 0xEA485987 1 ORR r9,r8,r7,LSL #22 false
+Instruction 4108 S:0xC0043516 0x9C0B 1 LDR r4,[sp,#0x2c] false
+Instruction 4109 S:0xC0043518 0xEA4F2897 1 LSR r8,r7,#10 false
+Instruction 4110 S:0xC004351C 0xF8CD9018 1 STR r9,[sp,#0x18] false
+Instruction 4111 S:0xC0043520 0xF8CD801C 11 STR r8,[sp,#0x1c] false
+Instruction 4112 S:0xC0043524 0x400F 1 ANDS r7,r7,r1 false
+Instruction 4113 S:0xC0043526 0xE9DD8906 1 LDRD r8,r9,[sp,#0x18] false
+Instruction 4114 S:0xC004352A 0x2100 1 MOVS r1,#0 false
+Instruction 4115 S:0xC004352C 0xF8D005C8 12 LDR r0,[r0,#0x5c8] false
+Instruction 4116 S:0xC0043530 0xEA4F2E9E 1 LSR lr,lr,#10 false
+Instruction 4117 S:0xC0043534 0xEB120208 1 ADDS r2,r2,r8 false
+Instruction 4118 S:0xC0043538 0xF8D44598 1 LDR r4,[r4,#0x598] false
+Instruction 4119 S:0xC004353C 0xEB430309 1 ADC r3,r3,r9 false
+Instruction 4120 S:0xC0043540 0x9004 2 STR r0,[sp,#0x10] false
+Instruction 4121 S:0xC0043542 0xF44F60FC 0 MOV r0,#0x7e0 false
+Instruction 4122 S:0xC0043546 0xEB0E0904 1 ADD r9,lr,r4 false
+Instruction 4123 S:0xC004354A 0x4299 1 CMP r1,r3 false
+Instruction 4124 S:0xC004354C 0xBF08 1 IT EQ false
+Instruction 4125 S:0xC004354E 0x4290 1 CMP r0,r2 false
+Instruction 4126 S:0xC0043550 0x9C04 1 LDR r4,[sp,#0x10] false
+Instruction 4127 S:0xC0043552 0xEB0E0804 2 ADD r8,lr,r4 false
+Instruction 4128 S:0xC0043556 0xD34C 0 BCC {pc}+0x9c ; 0xc00435f2 true fail
+Instruction 4129 S:0xC0043558 0x2A1F 16 CMP r2,#0x1f false
+Instruction 4130 S:0xC004355A 0x4694 0 MOV r12,r2 false
+Instruction 4131 S:0xC004355C 0xF8DFE110 1 LDR lr,[pc,#272] ; [0xC0043670] = 0xC03E83C8 false
+Instruction 4132 S:0xC0043560 0xD835 17 BHI {pc}+0x6e ; 0xc00435ce true fail
+Instruction 4133 S:0xC0043562 0xF85E2022 22 LDR r2,[lr,r2,LSL #2] false
+Instruction 4134 S:0xC0043566 0xFBA90102 3 UMULL r0,r1,r9,r2 false
+Instruction 4135 S:0xC004356A 0xFBA22305 1 UMULL r2,r3,r2,r5 false
+Instruction 4136 S:0xC004356E 0x4689 1 MOV r9,r1 false
+Instruction 4137 S:0xC0043570 0x461D 1 MOV r5,r3 false
+Instruction 4138 S:0xC0043572 0xF85E202C 1 LDR r2,[lr,r12,LSL #2] false
+Instruction 4139 S:0xC0043576 0xFBA22308 3 UMULL r2,r3,r2,r8 false
+Instruction 4140 S:0xC004357A 0x4698 2 MOV r8,r3 false
+Instruction 4141 S:0xC004357C 0xE9DD0106 1 LDRD r0,r1,[sp,#0x18] false
+Instruction 4142 S:0xC0043580 0xF7FEF8A6 7 BL {pc}-0x1eb0 ; 0xc00416d0 true
+Instruction 4143 S:0xC00416D0 0xE92D03F0 3 PUSH {r4-r9} false
+Instruction 4144 S:0xC00416D4 0xB500 5 PUSH {lr} false
+Instruction 4145 S:0xC00416D6 0xF85DEB04 2 POP {lr} false
+Instruction 4146 S:0xC00416DA 0x2620 0 MOVS r6,#0x20 false
+Instruction 4147 S:0xC00416DC 0x2700 1 MOVS r7,#0 false
+Instruction 4148 S:0xC00416DE 0x428F 1 CMP r7,r1 false
+Instruction 4149 S:0xC00416E0 0xBF08 0 IT EQ false
+Instruction 4150 S:0xC00416E2 0x4286 1 CMP r6,r0 false
+Instruction 4151 S:0xC00416E4 0xD307 0 BCC {pc}+0x12 ; 0xc00416f6 true fail
+Instruction 4152 S:0xC00416E6 0x4B31 1 LDR r3,[pc,#196] ; [0xC00417AC] false
+Instruction 4153 S:0xC00416E8 0xEB030080 2 ADD r0,r3,r0,LSL #2 false
+Instruction 4154 S:0xC00416EC 0xF8D000FC 3 LDR r0,[r0,#0xfc] false
+Instruction 4155 S:0xC00416F0 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 4156 S:0xC00416F4 0x4770 3 BX lr true
+Instruction 4157 S:0xC0043584 0x9B08 2 LDR r3,[sp,#0x20] false
+Instruction 4158 S:0xC0043586 0xFB03F200 3 MUL r2,r3,r0 false
+Instruction 4159 S:0xC004358A 0x182D 1 ADDS r5,r5,r0 false
+Instruction 4160 S:0xC004358C 0x0A92 2 LSRS r2,r2,#10 false
+Instruction 4161 S:0xC004358E 0xEB020009 1 ADD r0,r2,r9 false
+Instruction 4162 S:0xC0043592 0x4442 1 ADD r2,r2,r8 false
+Instruction 4163 S:0xC0043594 0xE781 0 B {pc}-0xfa ; 0xc004349a true
+Instruction 4164 S:0xC004349A 0xFB06F30B 1 MUL r3,r6,r11 false
+Instruction 4165 S:0xC004349E 0x19AC 1 ADDS r4,r5,r6 false
+Instruction 4166 S:0xC00434A0 0xFB0A3307 21 MLA r3,r10,r7,r3 false
+Instruction 4167 S:0xC00434A4 0xF8DD802C 1 LDR r8,[sp,#0x2c] false
+Instruction 4168 S:0xC00434A8 0xFBA6670A 1 UMULL r6,r7,r6,r10 false
+Instruction 4169 S:0xC00434AC 0x4625 1 MOV r5,r4 false
+Instruction 4170 S:0xC00434AE 0xF8C8459C 1 STR r4,[r8,#0x59c] false
+Instruction 4171 S:0xC00434B2 0x19DF 1 ADDS r7,r3,r7 false
+Instruction 4172 S:0xC00434B4 0x0AB3 1 LSRS r3,r6,#10 false
+Instruction 4173 S:0xC00434B6 0xEA435387 1 ORR r3,r3,r7,LSL #22 false
+Instruction 4174 S:0xC00434BA 0x1818 1 ADDS r0,r3,r0 false
+Instruction 4175 S:0xC00434BC 0x189B 1 ADDS r3,r3,r2 false
+Instruction 4176 S:0xC00434BE 0xF8C80598 13 STR r0,[r8,#0x598] false
+Instruction 4177 S:0xC00434C2 0xF8C835C8 1 STR r3,[r8,#0x5c8] false
+Instruction 4178 S:0xC00434C6 0xE725 1 B {pc}-0x1b2 ; 0xc0043314 true
+Instruction 4179 S:0xC0043314 0xF8DD802C 2 LDR r8,[sp,#0x2c] false
+Instruction 4180 S:0xC0043318 0x3401 1 ADDS r4,#1 false
+Instruction 4181 S:0xC004331A 0x2100 0 MOVS r1,#0 false
+Instruction 4182 S:0xC004331C 0xF8D890B8 2 LDR r9,[r8,#0xb8] false
+Instruction 4183 S:0xC0043320 0xEA4F2880 15 LSL r8,r0,#10 false
+Instruction 4184 S:0xC0043324 0x980B 1 LDR r0,[sp,#0x2c] false
+Instruction 4185 S:0xC0043326 0xF8D005C8 3 LDR r0,[r0,#0x5c8] false
+Instruction 4186 S:0xC004332A 0x9003 1 STR r0,[sp,#0xc] false
+Instruction 4187 S:0xC004332C 0x4640 0 MOV r0,r8 false
+Instruction 4188 S:0xC004332E 0xF8DD802C 1 LDR r8,[sp,#0x2c] false
+Instruction 4189 S:0xC0043332 0xF20DFD2D 0 BL {pc}+0x20da5e ; 0xc0250d90 true
+Cycle Count 250 Tracing disabled
+Info Tracing enabled
+Instruction 4190 S:0xC0043336 0x1C6C 1 ADDS r4,r5,#1 false
+Instruction 4191 S:0xC0043338 0x9D03 1 LDR r5,[sp,#0xc] false
+Instruction 4192 S:0xC004333A 0xEBC90702 1 RSB r7,r9,r2 false
+Instruction 4193 S:0xC004333E 0xF8D860BC 15 LDR r6,[r8,#0xbc] false
+Instruction 4194 S:0xC0043342 0xEA877AE7 1 EOR r10,r7,r7,ASR #31 false
+Instruction 4195 S:0xC0043346 0xEBAA7AE7 1 SUB r10,r10,r7,ASR #31 false
+Instruction 4196 S:0xC004334A 0x2100 0 MOVS r1,#0 false
+Instruction 4197 S:0xC004334C 0x02A8 1 LSLS r0,r5,#10 false
+Instruction 4198 S:0xC004334E 0xF8D850DC 1 LDR r5,[r8,#0xdc] false
+Instruction 4199 S:0xC0043352 0xF20DFD1D 0 BL {pc}+0x20da3e ; 0xc0250d90 true
+Cycle Count 220 Tracing disabled
+Info Tracing enabled
+Instruction 4200 S:0xC0043356 0xEBBA1F99 1 CMP r10,r9,LSR #6 false
+Instruction 4201 S:0xC004335A 0xEBC60202 1 RSB r2,r6,r2 false
+Instruction 4202 S:0xC004335E 0xD806 1 BHI {pc}+0x10 ; 0xc004336e true
+Instruction 4203 S:0xC004336E 0xF1050338 14 ADD r3,r5,#0x38 false
+Instruction 4204 S:0xC0043372 0xE8531F00 20 LDREX r1,[r3] false
+Instruction 4205 S:0xC0043376 0x4439 2 ADD r1,r1,r7 false
+Instruction 4206 S:0xC0043378 0xE8431000 23 STREX r0,r1,[r3] false
+Instruction 4207 S:0xC004337C 0xF0900F00 2 TEQ r0,#0 false
+Instruction 4208 S:0xC0043380 0xD1F7 1 BNE {pc}-0xe ; 0xc0043372 true fail
+Instruction 4209 S:0xC0043382 0xF8DD802C 1 LDR r8,[sp,#0x2c] false
+Instruction 4210 S:0xC0043386 0xF105033C 0 ADD r3,r5,#0x3c false
+Instruction 4211 S:0xC004338A 0xF8D810B8 3 LDR r1,[r8,#0xb8] false
+Instruction 4212 S:0xC004338E 0x19CF 2 ADDS r7,r1,r7 false
+Instruction 4213 S:0xC0043390 0xF8C870B8 1 STR r7,[r8,#0xb8] false
+Instruction 4214 S:0xC0043394 0xE8531F00 10 LDREX r1,[r3] false
+Instruction 4215 S:0xC0043398 0x4411 2 ADD r1,r1,r2 false
+Instruction 4216 S:0xC004339A 0xE8431000 7 STREX r0,r1,[r3] false
+Instruction 4217 S:0xC004339E 0xF0900F00 2 TEQ r0,#0 false
+Instruction 4218 S:0xC00433A2 0xD1F7 0 BNE {pc}-0xe ; 0xc0043394 true fail
+Instruction 4219 S:0xC00433A4 0xF8D830BC 14 LDR r3,[r8,#0xbc] false
+Instruction 4220 S:0xC00433A8 0x189A 2 ADDS r2,r3,r2 false
+Instruction 4221 S:0xC00433AA 0xF8C820BC 1 STR r2,[r8,#0xbc] false
+Instruction 4222 S:0xC00433AE 0x4B19 1 LDR r3,[pc,#100] ; [0xC0043414] = 0xC0635FCC false
+Instruction 4223 S:0xC00433B0 0xF8DD902C 1 LDR r9,[sp,#0x2c] false
+Instruction 4224 S:0xC00433B4 0x685A 2 LDR r2,[r3,#4] false
+Instruction 4225 S:0xC00433B6 0xF8D90598 1 LDR r0,[r9,#0x598] false
+Instruction 4226 S:0xC00433BA 0xF8D9159C 1 LDR r1,[r9,#0x59c] false
+Instruction 4227 S:0xC00433BE 0xF8D984C0 1 LDR r8,[r9,#0x4c0] false
+Instruction 4228 S:0xC00433C2 0x2A00 0 CMP r2,#0 false
+Instruction 4229 S:0xC00433C4 0xF040813C 1 BNE.W {pc}+0x27c ; 0xc0043640 true fail
+Instruction 4230 S:0xC00433C8 0x4B13 1 LDR r3,[pc,#76] ; [0xC0043418] = 0xC0635FB8 false
+Instruction 4231 S:0xC00433CA 0xF8DD902C 1 LDR r9,[sp,#0x2c] false
+Instruction 4232 S:0xC00433CE 0x685A 12 LDR r2,[r3,#4] false
+Instruction 4233 S:0xC00433D0 0xE9D94524 1 LDRD r4,r5,[r9,#0x90] false
+Instruction 4234 S:0xC00433D4 0x2A00 1 CMP r2,#0 false
+Instruction 4235 S:0xC00433D6 0xF04080EB 0 BNE.W {pc}+0x1da ; 0xc00435b0 true fail
+Instruction 4236 S:0xC00433DA 0xB011 1 ADD sp,sp,#0x44 false
+Instruction 4237 S:0xC00433DC 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Instruction 4238 S:0xC003CC52 0xF3BF8F5F 13 DMB false
+Instruction 4239 S:0xC003CC56 0xF8353008 31 LDRH r3,[r5,r8] false
+Instruction 4240 S:0xC003CC5A 0x3301 2 ADDS r3,#1 false
+Instruction 4241 S:0xC003CC5C 0xF8253008 1 STRH r3,[r5,r8] false
+Instruction 4242 S:0xC003CC60 0xF3BF8F4F 37 DSB false
+Instruction 4243 S:0xC003CC64 0xF3AF8004 1 SEV.W false
+Instruction 4244 S:0xC003CC68 0xF049FF64 1 BL {pc}+0x49ecc ; 0xc0086b34 true
+Cycle Count 149 Tracing disabled
+Info Tracing enabled
+Instruction 4245 S:0xC003CC6C 0xF85A2026 1 LDR r2,[r10,r6,LSL #2] false
+Instruction 4246 S:0xC003CC70 0x464B 0 MOV r3,r9 false
+Instruction 4247 S:0xC003CC72 0x189B 2 ADDS r3,r3,r2 false
+Instruction 4248 S:0xC003CC74 0xF8D31460 3 LDR r1,[r3,#0x460] false
+Instruction 4249 S:0xC003CC78 0xF8D32464 1 LDR r2,[r3,#0x464] false
+Instruction 4250 S:0xC003CC7C 0x4291 2 CMP r1,r2 false
+Instruction 4251 S:0xC003CC7E 0xD00B 0 BEQ {pc}+0x1a ; 0xc003cc98 true fail
+Instruction 4252 S:0xC003CC80 0x2300 5 MOVS r3,#0 false
+Instruction 4253 S:0xC003CC82 0xF8843498 1 STRB r3,[r4,#0x498] false
+Instruction 4254 S:0xC003CC86 0x4620 1 MOV r0,r4 false
+Instruction 4255 S:0xC003CC88 0x4631 0 MOV r1,r6 false
+Instruction 4256 S:0xC003CC8A 0xF107070C 1 ADD r7,r7,#0xc false
+Instruction 4257 S:0xC003CC8E 0x46BD 1 MOV sp,r7 false
+Instruction 4258 S:0xC003CC90 0xE8BD4FF0 5 POP {r4-r11,lr} false
+Instruction 4259 S:0xC003CC94 0xF009BE84 7 B.W {pc}+0x9d0c ; 0xc00469a0 true
+Instruction 4260 S:0xC00469A0 0xE92D4FF0 50 PUSH {r4-r11,lr} false
+Instruction 4261 S:0xC00469A4 0xB083 7 SUB sp,sp,#0xc false
+Instruction 4262 S:0xC00469A6 0xB500 3 PUSH {lr} false
+Instruction 4263 S:0xC00469A8 0xF85DEB04 2 POP {lr} false
+Instruction 4264 S:0xC00469AC 0x4C77 12 LDR r4,[pc,#476] ; [0xC0046B8C] false
+Instruction 4265 S:0xC00469AE 0xF8D0346C 2 LDR r3,[r0,#0x46c] false
+Instruction 4266 S:0xC00469B2 0x4606 0 MOV r6,r0 false
+Instruction 4267 S:0xC00469B4 0x460D 1 MOV r5,r1 false
+Instruction 4268 S:0xC00469B6 0x6822 3 LDR r2,[r4,#0] false
+Instruction 4269 S:0xC00469B8 0x1AD3 2 SUBS r3,r2,r3 false
+Instruction 4270 S:0xC00469BA 0x2B00 1 CMP r3,#0 false
+Instruction 4271 S:0xC00469BC 0xDB0A 0 BLT {pc}+0x18 ; 0xc00469d4 true fail
+Instruction 4272 S:0xC00469BE 0x4A74 1 LDR r2,[pc,#464] ; [0xC0046B90] false
+Instruction 4273 S:0xC00469C0 0x4B74 1 LDR r3,[pc,#464] ; [0xC0046B94] false
+Instruction 4274 S:0xC00469C2 0xF8522021 2 LDR r2,[r2,r1,LSL #2] false
+Instruction 4275 S:0xC00469C6 0x189B 2 ADDS r3,r3,r2 false
+Instruction 4276 S:0xC00469C8 0xF8D33490 3 LDR r3,[r3,#0x490] false
+Instruction 4277 S:0xC00469CC 0xB113 2 CBZ r3,{pc}+8 ; 0xc00469d4 true fail
+Instruction 4278 S:0xC00469CE 0x2007 1 MOVS r0,#7 false
+Instruction 4279 S:0xC00469D0 0xF7DAFD56 0 BL {pc}-0x25550 ; 0xc0021480 true
+Instruction 4280 S:0xC0021480 0xB510 2 PUSH {r4,lr} false
+Instruction 4281 S:0xC0021482 0xB500 1 PUSH {lr} false
+Instruction 4282 S:0xC0021484 0xF85DEB04 2 POP {lr} false
+Instruction 4283 S:0xC0021488 0xF3EF8400 1 MRS r4,APSR ; formerly CPSR false
+Instruction 4284 S:0xC002148C 0xB672 1 CPSID i false
+Instruction 4285 S:0xC002148E 0xF7FFFEF1 1 BL {pc}-0x21a ; 0xc0021274 true
+Instruction 4286 S:0xC0021274 0xB538 1 PUSH {r3-r5,lr} false
+Instruction 4287 S:0xC0021276 0xB500 4 PUSH {lr} false
+Instruction 4288 S:0xC0021278 0xF85DEB04 2 POP {lr} false
+Instruction 4289 S:0xC002127C 0x4605 0 MOV r5,r0 false
+Instruction 4290 S:0xC002127E 0x4B0F 2 LDR r3,[pc,#60] ; [0xC00212BC] = 0xC0635D24 false
+Instruction 4291 S:0xC0021280 0x6ADA 5 LDR r2,[r3,#0x2c] false
+Instruction 4292 S:0xC0021282 0xB972 2 CBNZ r2,{pc}+0x20 ; 0xc00212a2 true fail
+Instruction 4293 S:0xC0021284 0x466A 1 MOV r2,sp false
+Instruction 4294 S:0xC0021286 0x2101 0 MOVS r1,#1 false
+Instruction 4295 S:0xC0021288 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 4296 S:0xC002128C 0x4A0C 1 LDR r2,[pc,#48] ; [0xC00212C0] = 0xC06498C0 false
+Instruction 4297 S:0xC002128E 0xF023031F 0 BIC r3,r3,#0x1f false
+Instruction 4298 S:0xC0021292 0xFA01F505 1 LSL r5,r1,r5 false
+Instruction 4299 S:0xC0021296 0x695B 4 LDR r3,[r3,#0x14] false
+Instruction 4300 S:0xC0021298 0x019B 3 LSLS r3,r3,#6 false
+Instruction 4301 S:0xC002129A 0x58D1 5 LDR r1,[r2,r3] false
+Instruction 4302 S:0xC002129C 0x4329 2 ORRS r1,r1,r5 false
+Instruction 4303 S:0xC002129E 0x50D1 1 STR r1,[r2,r3] false
+Instruction 4304 S:0xC00212A0 0xBD38 1 POP {r3-r5,pc} true
+Instruction 4305 S:0xC0021492 0x466A 2 MOV r2,sp false
+Instruction 4306 S:0xC0021494 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 4307 S:0xC0021498 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 4308 S:0xC002149C 0x685B 3 LDR r3,[r3,#4] false
+Instruction 4309 S:0xC002149E 0xF0234378 2 BIC r3,r3,#0xf8000000 false
+Instruction 4310 S:0xC00214A2 0xF02303FF 1 BIC r3,r3,#0xff false
+Instruction 4311 S:0xC00214A6 0xB113 1 CBZ r3,{pc}+8 ; 0xc00214ae true fail
+Instruction 4312 S:0xC00214A8 0xF3848100 12 MSR CPSR_c,r4 false
+Instruction 4313 S:0xC00214AC 0xBD10 5 POP {r4,pc} true
+Instruction 4314 S:0xC00469D4 0x4628 1 MOV r0,r5 false
+Instruction 4315 S:0xC00469D6 0x6827 2 LDR r7,[r4,#0] false
+Instruction 4316 S:0xC00469D8 0xF7F6FA98 0 BL {pc}-0x9acc ; 0xc003cf0c true
+Instruction 4317 S:0xC003CF0C 0xB488 15 PUSH {r3,r7} false
+Instruction 4318 S:0xC003CF0E 0xAF00 1 ADD r7,sp,#0 false
+Instruction 4319 S:0xC003CF10 0xB500 2 PUSH {lr} false
+Instruction 4320 S:0xC003CF12 0xF85DEB04 2 POP {lr} false
+Instruction 4321 S:0xC003CF16 0x4A0C 23 LDR r2,[pc,#48] ; [0xC003CF48] = 0xC05FD5C0 false
+Instruction 4322 S:0xC003CF18 0x4B0C 2 LDR r3,[pc,#48] ; [0xC003CF4C] = 0xC05F3080 false
+Instruction 4323 S:0xC003CF1A 0xF8522020 1 LDR r2,[r2,r0,LSL #2] false
+Instruction 4324 S:0xC003CF1E 0x189B 2 ADDS r3,r3,r2 false
+Instruction 4325 S:0xC003CF20 0xF8D31460 5 LDR r1,[r3,#0x460] false
+Instruction 4326 S:0xC003CF24 0xF8D32464 3 LDR r2,[r3,#0x464] false
+Instruction 4327 S:0xC003CF28 0x4291 2 CMP r1,r2 false
+Instruction 4328 S:0xC003CF2A 0xD003 0 BEQ {pc}+0xa ; 0xc003cf34 true fail
+Instruction 4329 S:0xC003CF2C 0x2000 1 MOVS r0,#0 false
+Instruction 4330 S:0xC003CF2E 0x46BD 0 MOV sp,r7 false
+Instruction 4331 S:0xC003CF30 0xBC88 3 POP {r3,r7} false
+Instruction 4332 S:0xC003CF32 0x4770 1 BX lr true
+Instruction 4333 S:0xC00469DC 0xBB00 1 CBNZ r0,{pc}+0x44 ; 0xc0046a20 true fail
+Instruction 4334 S:0xC00469DE 0x466A 1 MOV r2,sp false
+Instruction 4335 S:0xC00469E0 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
+Instruction 4336 S:0xC00469E4 0xF023031F 1 BIC r3,r3,#0x1f false
+Instruction 4337 S:0xC00469E8 0x695B 3 LDR r3,[r3,#0x14] false
+Instruction 4338 S:0xC00469EA 0xF8DF91A4 1 LDR r9,[pc,#420] ; [0xC0046B90] false
+Instruction 4339 S:0xC00469EE 0xF8DF81A4 1 LDR r8,[pc,#420] ; [0xC0046B94] false
+Instruction 4340 S:0xC00469F2 0xF8592023 2 LDR r2,[r9,r3,LSL #2] false
+Instruction 4341 S:0xC00469F6 0x4643 1 MOV r3,r8 false
+Instruction 4342 S:0xC00469F8 0x189B 1 ADDS r3,r3,r2 false
+Instruction 4343 S:0xC00469FA 0xF8D32490 3 LDR r2,[r3,#0x490] false
+Instruction 4344 S:0xC00469FE 0xB10A 2 CBZ r2,{pc}+6 ; 0xc0046a04 true fail
+Instruction 4345 S:0xC0046A00 0x6B93 15 LDR r3,[r2,#0x38] false
+Instruction 4346 S:0xC0046A02 0xB983 2 CBNZ r3,{pc}+0x24 ; 0xc0046a26 true
+Timestamp Timestamp: 562536984255
+Instruction 4347 S:0xC0046A26 0x6390 23 STR r0,[r2,#0x38] false
+Instruction 4348 S:0xC0046A28 0x6893 1 LDR r3,[r2,#8] false
+Instruction 4349 S:0xC0046A2A 0x68DB 64 LDR r3,[r3,#0xc] false
+Instruction 4350 S:0xC0046A2C 0xF1030410 2 ADD r4,r3,#0x10 false
+Instruction 4351 S:0xC0046A30 0xE8541F00 19 LDREX r1,[r4] false
+Instruction 4352 S:0xC0046A34 0xF1010101 2 ADD r1,r1,#1 false
+Instruction 4353 S:0xC0046A38 0xE8441000 21 STREX r0,r1,[r4] false
+Instruction 4354 S:0xC0046A3C 0xF0900F00 2 TEQ r0,#0 false
+Instruction 4355 S:0xC0046A40 0xD1F6 0 BNE {pc}-0x10 ; 0xc0046a30 true fail
+Instruction 4356 S:0xC0046A42 0x6812 1 LDR r2,[r2,#0] false
+Instruction 4357 S:0xC0046A44 0x2A00 2 CMP r2,#0 false
+Instruction 4358 S:0xC0046A46 0xD1EF 0 BNE {pc}-0x1e ; 0xc0046a28 true
+Instruction 4359 S:0xC0046A28 0x6893 18 LDR r3,[r2,#8] false
+Instruction 4360 S:0xC0046A2A 0x68DB 19 LDR r3,[r3,#0xc] false
+Instruction 4361 S:0xC0046A2C 0xF1030410 2 ADD r4,r3,#0x10 false
+Instruction 4362 S:0xC0046A30 0xE8541F00 18 LDREX r1,[r4] false
+Instruction 4363 S:0xC0046A34 0xF1010101 2 ADD r1,r1,#1 false
+Instruction 4364 S:0xC0046A38 0xE8441000 27 STREX r0,r1,[r4] false
+Instruction 4365 S:0xC0046A3C 0xF0900F00 2 TEQ r0,#0 false
+Instruction 4366 S:0xC0046A40 0xD1F6 0 BNE {pc}-0x10 ; 0xc0046a30 true fail
+Instruction 4367 S:0xC0046A42 0x6812 8 LDR r2,[r2,#0] false
+Instruction 4368 S:0xC0046A44 0x2A00 2 CMP r2,#0 false
+Instruction 4369 S:0xC0046A46 0xD1EF 1 BNE {pc}-0x1e ; 0xc0046a28 true fail
+Instruction 4370 S:0xC0046A48 0xE7DC 8 B {pc}-0x44 ; 0xc0046a04 true
+Instruction 4371 S:0xC0046A04 0xF8593025 3 LDR r3,[r9,r5,LSL #2] false
+Instruction 4372 S:0xC0046A08 0x4644 1 MOV r4,r8 false
+Instruction 4373 S:0xC0046A0A 0x18E3 1 ADDS r3,r4,r3 false
+Instruction 4374 S:0xC0046A0C 0x4A60 3 LDR r2,[pc,#384] ; [0xC0046B90] false
+Instruction 4375 S:0xC0046A0E 0x6A9B 3 LDR r3,[r3,#0x28] false
+Instruction 4376 S:0xC0046A10 0xF0130F01 2 TST r3,#1 false
+Instruction 4377 S:0xC0046A14 0x4B60 1 LDR r3,[pc,#384] ; [0xC0046B98] false
+Instruction 4378 S:0xC0046A16 0xD16A 0 BNE {pc}+0xd8 ; 0xc0046aee true
+Instruction 4379 S:0xC0046AEE 0xF50371A0 2 ADD r1,r3,#0x140 false
+Instruction 4380 S:0xC0046AF2 0x4628 0 MOV r0,r5 false
+Instruction 4381 S:0xC0046AF4 0x9300 3 STR r3,[sp,#0] false
+Instruction 4382 S:0xC0046AF6 0x9201 3 STR r2,[sp,#4] false
+Instruction 4383 S:0xC0046AF8 0xF209F81E 0 BL {pc}+0x209040 ; 0xc024fb38 true
+Cycle Count 66 Tracing disabled
+Info Tracing enabled
+Instruction 4384 S:0xC0046AFC 0x9B00 1 LDR r3,[sp,#0] false
+Instruction 4385 S:0xC0046AFE 0xF50371A2 2 ADD r1,r3,#0x144 false
+Instruction 4386 S:0xC0046B02 0xE8510F00 5 LDREX r0,[r1] false
+Instruction 4387 S:0xC0046B06 0xF1A00001 2 SUB r0,r0,#1 false
+Instruction 4388 S:0xC0046B0A 0xE8410E00 7 STREX lr,r0,[r1] false
+Instruction 4389 S:0xC0046B0E 0xF09E0F00 2 TEQ lr,#0 false
+Instruction 4390 S:0xC0046B12 0xD1F6 0 BNE {pc}-0x10 ; 0xc0046b02 true fail
+Instruction 4391 S:0xC0046B14 0x9A01 8 LDR r2,[sp,#4] false
+Instruction 4392 S:0xC0046B16 0x2000 0 MOVS r0,#0 false
+Instruction 4393 S:0xC0046B18 0xF8521025 3 LDR r1,[r2,r5,LSL #2] false
+Instruction 4394 S:0xC0046B1C 0x9300 1 STR r3,[sp,#0] false
+Instruction 4395 S:0xC0046B1E 0x1861 1 ADDS r1,r4,r1 false
+Instruction 4396 S:0xC0046B20 0x3128 1 ADDS r1,r1,#0x28 false
+Instruction 4397 S:0xC0046B22 0xF209F809 0 BL {pc}+0x209016 ; 0xc024fb38 true
+Cycle Count 36 Tracing disabled
+Info Tracing enabled
+Instruction 4398 S:0xC0046B26 0x9B00 1 LDR r3,[sp,#0] false
+Instruction 4399 S:0xC0046B28 0xE776 1 B {pc}-0x110 ; 0xc0046a18 true
+Instruction 4400 S:0xC0046A18 0xF8D32144 3 LDR r2,[r3,#0x144] false
+Instruction 4401 S:0xC0046A1C 0x495E 1 LDR r1,[pc,#376] ; [0xC0046B98] false
+Instruction 4402 S:0xC0046A1E 0xB9A2 1 CBNZ r2,{pc}+0x2c ; 0xc0046a4a true
+Instruction 4403 S:0xC0046A4A 0xF8D12148 8 LDR r2,[r1,#0x148] false
+Instruction 4404 S:0xC0046A4E 0x1ABA 2 SUBS r2,r7,r2 false
+Instruction 4405 S:0xC0046A50 0x2A00 1 CMP r2,#0 false
+Instruction 4406 S:0xC0046A52 0xDBE5 0 BLT {pc}-0x32 ; 0xc0046a20 true fail
+Instruction 4407 S:0xC0046A54 0xF8592025 1 LDR r2,[r9,r5,LSL #2] false
+Instruction 4408 S:0xC0046A58 0xF50171A0 0 ADD r1,r1,#0x140 false
+Instruction 4409 S:0xC0046A5C 0x4C4F 1 LDR r4,[pc,#316] ; [0xC0046B9C] false
+Instruction 4410 S:0xC0046A5E 0xF04F30FF 13 MOV r0,#0xffffffff false
+Instruction 4411 S:0xC0046A62 0x4F4F 1 LDR r7,[pc,#316] ; [0xC0046BA0] false
+Instruction 4412 S:0xC0046A64 0x46A6 1 MOV lr,r4 false
+Instruction 4413 S:0xC0046A66 0xF8DFA128 1 LDR r10,[pc,#296] ; [0xC0046B90] false
+Instruction 4414 S:0xC0046A6A 0xF85E2002 4 LDR r2,[lr,r2] false
+Instruction 4415 S:0xC0046A6E 0x9300 3 STR r3,[sp,#0] false
+Instruction 4416 S:0xC0046A70 0xF20BFD48 0 BL {pc}+0x20ba94 ; 0xc0252504 true
+Cycle Count 335 Tracing disabled
+Info Tracing enabled
+Instruction 4417 S:0xC0046A74 0x683A 1 LDR r2,[r7,#0] false
+Instruction 4418 S:0xC0046A76 0x9B00 1 LDR r3,[sp,#0] false
+Instruction 4419 S:0xC0046A78 0x4290 1 CMP r0,r2 false
+Instruction 4420 S:0xC0046A7A 0xDAD1 0 BGE {pc}-0x5a ; 0xc0046a20 true
+Instruction 4421 S:0xC0046A20 0xB003 20 ADD sp,sp,#0xc false
+Instruction 4422 S:0xC0046A22 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Instruction 4423 S:0xC0026364 0x4628 13 MOV r0,r5 false
+Instruction 4424 S:0xC0026366 0xE8BD40F8 1 POP {r3-r7,lr} false
+Instruction 4425 S:0xC002636A 0xF00EB931 3 B.W {pc}+0xe266 ; 0xc00345d0 true
+Instruction 4426 S:0xC00345D0 0xE92D4FF0 12 PUSH {r4-r11,lr} false
+Instruction 4427 S:0xC00345D4 0xB08D 5 SUB sp,sp,#0x34 false
+Instruction 4428 S:0xC00345D6 0xB500 3 PUSH {lr} false
+Instruction 4429 S:0xC00345D8 0xF85DEB04 2 POP {lr} false
+Instruction 4430 S:0xC00345DC 0xF10D0918 1 ADD r9,sp,#0x18 false
+Instruction 4431 S:0xC00345E0 0x4680 7 MOV r8,r0 false
+Instruction 4432 S:0xC00345E2 0xF8CD9018 1 STR r9,[sp,#0x18] false
+Instruction 4433 S:0xC00345E6 0xF8CD901C 1 STR r9,[sp,#0x1c] false
+Instruction 4434 S:0xC00345EA 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 4435 S:0xC00345EE 0x061B 3 LSLS r3,r3,#24 false
+Instruction 4436 S:0xC00345F0 0xF1408250 0 BPL.W {pc}+0x4a4 ; 0xc0034a94 true fail
+Instruction 4437 S:0xC00345F4 0xF8D012F0 14 LDR r1,[r0,#0x2f0] false
+Instruction 4438 S:0xC00345F8 0xF8D842B4 3 LDR r4,[r8,#0x2b4] false
+Instruction 4439 S:0xC00345FC 0xF8D002B0 1 LDR r0,[r0,#0x2b0] false
+Instruction 4440 S:0xC0034600 0xB9B1 1 CBNZ r1,{pc}+0x30 ; 0xc0034630 true fail
+Instruction 4441 S:0xC0034602 0xF8D812F4 16 LDR r1,[r8,#0x2f4] false
+Instruction 4442 S:0xC0034606 0x2900 2 CMP r1,#0 false
+Instruction 4443 S:0xC0034608 0xF040811F 1 BNE.W {pc}+0x242 ; 0xc003484a true fail
+Instruction 4444 S:0xC003460C 0xF508733E 20 ADD r3,r8,#0x2f8 false
+Instruction 4445 S:0xC0034610 0xE9D32300 3 LDRD r2,r3,[r3,#0] false
+Instruction 4446 S:0xC0034614 0xEA520503 2 ORRS r5,r2,r3 false
+Instruction 4447 S:0xC0034618 0xF0408117 1 BNE.W {pc}+0x232 ; 0xc003484a true fail
+Instruction 4448 S:0xC003461C 0xF8D843D4 18 LDR r4,[r8,#0x3d4] false
+Instruction 4449 S:0xC0034620 0xF8D430D8 5 LDR r3,[r4,#0xd8] false
+Instruction 4450 S:0xC0034624 0x2B00 2 CMP r3,#0 false
+Instruction 4451 S:0xC0034626 0xF0408115 1 BNE.W {pc}+0x22e ; 0xc0034854 true fail
+Instruction 4452 S:0xC003462A 0xB00D 1 ADD sp,sp,#0x34 false
+Instruction 4453 S:0xC003462C 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Instruction 4454 S:0xC0055568 0x2001 13 MOVS r0,#1 false
+Instruction 4455 S:0xC005556A 0xE8BD4008 1 POP {r3,lr} false
+Instruction 4456 S:0xC005556E 0xF7F9BB5D 1 B {pc}-0x6942 ; 0xc004ec2c true
+Instruction 4457 S:0xC004EC2C 0xB538 71 PUSH {r3-r5,lr} false
+Instruction 4458 S:0xC004EC2E 0xB500 4 PUSH {lr} false
+Instruction 4459 S:0xC004EC30 0xF85DEB04 2 POP {lr} false
+Instruction 4460 S:0xC004EC34 0x4604 0 MOV r4,r0 false
+Instruction 4461 S:0xC004EC36 0x4B15 13 LDR r3,[pc,#84] ; [0xC004EC8C] = 0xC05F1F34 false
+Instruction 4462 S:0xC004EC38 0xEE1D2F90 1 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 4463 S:0xC004EC3C 0x58D2 6 LDR r2,[r2,r3] false
+Instruction 4464 S:0xC004EC3E 0x6C13 5 LDR r3,[r2,#0x40] false
+Instruction 4465 S:0xC004EC40 0x0718 32 LSLS r0,r3,#28 false
+Instruction 4466 S:0xC004EC42 0xD014 0 BEQ {pc}+0x2c ; 0xc004ec6e true
+Instruction 4467 S:0xC004EC6E 0xBD38 48 POP {r3-r5,pc} true
+Instruction 4468 S:0xC0055758 0x4907 12 LDR r1,[pc,#28] ; [0xC0055778] = 0xC064D488 false
+Instruction 4469 S:0xC005575A 0x4622 0 MOV r2,r4 false
+Instruction 4470 S:0xC005575C 0x462B 1 MOV r3,r5 false
+Instruction 4471 S:0xC005575E 0x4630 0 MOV r0,r6 false
+Instruction 4472 S:0xC0055760 0xE9D14500 17 LDRD r4,r5,[r1,#0] false
+Instruction 4473 S:0xC0055764 0xE9CD4500 3 STRD r4,r5,[sp,#0] false
+Instruction 4474 S:0xC0055768 0xF7DFFDE8 1 BL {pc}-0x2042c ; 0xc003533c true
+Instruction 4475 S:0xC003533C 0xE92D47F0 1 PUSH {r4-r10,lr} false
+Instruction 4476 S:0xC0035340 0xB08A 11 SUB sp,sp,#0x28 false
+Instruction 4477 S:0xC0035342 0xB500 3 PUSH {lr} false
+Instruction 4478 S:0xC0035344 0xF85DEB04 2 POP {lr} false
+Instruction 4479 S:0xC0035348 0x4682 1 MOV r10,r0 false
+Instruction 4480 S:0xC003534A 0x4616 0 MOV r6,r2 false
+Instruction 4481 S:0xC003534C 0x461F 1 MOV r7,r3 false
+Instruction 4482 S:0xC003534E 0xE9DA2304 4 LDRD r2,r3,[r10,#0x10] false
+Instruction 4483 S:0xC0035352 0x9812 3 LDR r0,[sp,#0x48] false
+Instruction 4484 S:0xC0035354 0x1AB2 1 SUBS r2,r6,r2 false
+Instruction 4485 S:0xC0035356 0xEB670303 1 SBC r3,r7,r3 false
+Instruction 4486 S:0xC003535A 0x9913 1 LDR r1,[sp,#0x4c] false
+Instruction 4487 S:0xC003535C 0x2A00 0 CMP r2,#0 false
+Instruction 4488 S:0xC003535E 0xF1730400 1 SBCS r4,r3,#0 false
+Instruction 4489 S:0xC0035362 0xDB2F 0 BLT {pc}+0x62 ; 0xc00353c4 true fail
+Instruction 4490 S:0xC0035364 0xF8DAE024 1 LDR lr,[r10,#0x24] false
+Instruction 4491 S:0xC0035368 0x4604 0 MOV r4,r0 false
+Instruction 4492 S:0xC003536A 0x460D 1 MOV r5,r1 false
+Instruction 4493 S:0xC003536C 0xE9DE0106 12 LDRD r0,r1,[lr,#0x18] false
+Instruction 4494 S:0xC0035370 0x4284 2 CMP r4,r0 false
+Instruction 4495 S:0xC0035372 0xEB750E01 1 SBCS lr,r5,r1 false
+Instruction 4496 S:0xC0035376 0xBFBC 0 ITT LT false
+Instruction 4497 S:0xC0035378 0x4604 1 MOV r4,r0 false fail
+Instruction 4498 S:0xC003537A 0x460D 0 MOV r5,r1 false fail
+Instruction 4499 S:0xC003537C 0x42A2 1 CMP r2,r4 false
+Instruction 4500 S:0xC003537E 0xEB730005 1 SBCS r0,r3,r5 false
+Instruction 4501 S:0xC0035382 0xBFBC 0 ITT LT false
+Instruction 4502 S:0xC0035384 0xF04F0801 1 MOV r8,#1 false
+Instruction 4503 S:0xC0035388 0xF04F0900 0 MOV r9,#0 false
+Instruction 4504 S:0xC003538C 0xDA1F 1 BGE {pc}+0x42 ; 0xc00353ce true fail
+Instruction 4505 S:0xC003538E 0xE9DA2304 1 LDRD r2,r3,[r10,#0x10] false
+Instruction 4506 S:0xC0035392 0xA808 1 ADD r0,sp,#0x20 false
+Instruction 4507 S:0xC0035394 0x9400 1 STR r4,[sp,#0] false
+Instruction 4508 S:0xC0035396 0x9501 1 STR r5,[sp,#4] false
+Instruction 4509 S:0xC0035398 0xF7FFFCAA 0 BL {pc}-0x6a8 ; 0xc0034cf0 true
+Instruction 4510 S:0xC0034CF0 0xE92D03F0 30 PUSH {r4-r9} false
+Instruction 4511 S:0xC0034CF4 0xB500 5 PUSH {lr} false
+Instruction 4512 S:0xC0034CF6 0xF85DEB04 2 POP {lr} false
+Instruction 4513 S:0xC0034CFA 0x461F 0 MOV r7,r3 false
+Instruction 4514 S:0xC0034CFC 0xF8DD8018 3 LDR r8,[sp,#0x18] false
+Instruction 4515 S:0xC0034D00 0x4616 8 MOV r6,r2 false
+Instruction 4516 S:0xC0034D02 0xF8DD901C 1 LDR r9,[sp,#0x1c] false
+Instruction 4517 S:0xC0034D06 0xEB120408 1 ADDS r4,r2,r8 false
+Instruction 4518 S:0xC0034D0A 0xEB430509 1 ADC r5,r3,r9 false
+Instruction 4519 S:0xC0034D0E 0x2C00 0 CMP r4,#0 false
+Instruction 4520 S:0xC0034D10 0xF1750300 1 SBCS r3,r5,#0 false
+Instruction 4521 S:0xC0034D14 0xDB03 0 BLT {pc}+0xa ; 0xc0034d1e true fail
+Instruction 4522 S:0xC0034D16 0x42B4 20 CMP r4,r6 false
+Instruction 4523 S:0xC0034D18 0xEB750307 1 SBCS r3,r5,r7 false
+Instruction 4524 S:0xC0034D1C 0xDA07 0 BGE {pc}+0x12 ; 0xc0034d2e true
+Instruction 4525 S:0xC0034D2E 0x4544 8 CMP r4,r8 false
+Instruction 4526 S:0xC0034D30 0xEB750309 1 SBCS r3,r5,r9 false
+Instruction 4527 S:0xC0034D34 0xDBF3 0 BLT {pc}-0x16 ; 0xc0034d1e true fail
+Instruction 4528 S:0xC0034D36 0xE7F5 1 B {pc}-0x12 ; 0xc0034d24 true
+Instruction 4529 S:0xC0034D24 0xE9C04500 17 STRD r4,r5,[r0,#0] false
+Instruction 4530 S:0xC0034D28 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 4531 S:0xC0034D2C 0x4770 3 BX lr true
+Instruction 4532 S:0xC003539C 0xE9DD6708 2 LDRD r6,r7,[sp,#0x20] false
+Instruction 4533 S:0xC00353A0 0xE9DA2306 1 LDRD r2,r3,[r10,#0x18] false
+Instruction 4534 S:0xC00353A4 0xA808 1 ADD r0,sp,#0x20 false
+Instruction 4535 S:0xC00353A6 0xE88D0030 1 STM sp,{r4,r5} false
+Instruction 4536 S:0xC00353AA 0xE9CA6704 1 STRD r6,r7,[r10,#0x10] false
+Instruction 4537 S:0xC00353AE 0xF7FFFC9F 1 BL {pc}-0x6be ; 0xc0034cf0 true
+Instruction 4538 S:0xC0034CF0 0xE92D03F0 1 PUSH {r4-r9} false
+Instruction 4539 S:0xC0034CF4 0xB500 6 PUSH {lr} false
+Instruction 4540 S:0xC0034CF6 0xF85DEB04 2 POP {lr} false
+Instruction 4541 S:0xC0034CFA 0x461F 0 MOV r7,r3 false
+Instruction 4542 S:0xC0034CFC 0xF8DD8018 3 LDR r8,[sp,#0x18] false
+Instruction 4543 S:0xC0034D00 0x4616 0 MOV r6,r2 false
+Instruction 4544 S:0xC0034D02 0xF8DD901C 1 LDR r9,[sp,#0x1c] false
+Instruction 4545 S:0xC0034D06 0xEB120408 1 ADDS r4,r2,r8 false
+Instruction 4546 S:0xC0034D0A 0xEB430509 1 ADC r5,r3,r9 false
+Instruction 4547 S:0xC0034D0E 0x2C00 0 CMP r4,#0 false
+Instruction 4548 S:0xC0034D10 0xF1750300 1 SBCS r3,r5,#0 false
+Instruction 4549 S:0xC0034D14 0xDB03 0 BLT {pc}+0xa ; 0xc0034d1e true fail
+Instruction 4550 S:0xC0034D16 0x42B4 1 CMP r4,r6 false
+Instruction 4551 S:0xC0034D18 0xEB750307 1 SBCS r3,r5,r7 false
+Instruction 4552 S:0xC0034D1C 0xDA07 0 BGE {pc}+0x12 ; 0xc0034d2e true
+Instruction 4553 S:0xC0034D2E 0x4544 19 CMP r4,r8 false
+Instruction 4554 S:0xC0034D30 0xEB750309 1 SBCS r3,r5,r9 false
+Instruction 4555 S:0xC0034D34 0xDBF3 0 BLT {pc}-0x16 ; 0xc0034d1e true fail
+Instruction 4556 S:0xC0034D36 0xE7F5 1 B {pc}-0x12 ; 0xc0034d24 true
+Instruction 4557 S:0xC0034D24 0xE9C04500 1 STRD r4,r5,[r0,#0] false
+Instruction 4558 S:0xC0034D28 0xE8BD03F0 1 POP {r4-r9} false
+Instruction 4559 S:0xC0034D2C 0x4770 3 BX lr true
+Instruction 4560 S:0xC00353B2 0xE9DD2308 2 LDRD r2,r3,[sp,#0x20] false
+Instruction 4561 S:0xC00353B6 0xE9CA2306 1 STRD r2,r3,[r10,#0x18] false
+Instruction 4562 S:0xC00353BA 0x4640 1 MOV r0,r8 false
+Instruction 4563 S:0xC00353BC 0x4649 0 MOV r1,r9 false
+Instruction 4564 S:0xC00353BE 0xB00A 1 ADD sp,sp,#0x28 false
+Instruction 4565 S:0xC00353C0 0xE8BD87F0 3 POP {r4-r10,pc} true
+Instruction 4566 S:0xC005576C 0x2001 4 MOVS r0,#1 false
+Instruction 4567 S:0xC005576E 0xB005 0 ADD sp,sp,#0x14 false
+Instruction 4568 S:0xC0055770 0xBDF0 3 POP {r4-r7,pc} true
+Instruction 4569 S:0xC003510A 0x4B34 13 LDR r3,[pc,#208] ; [0xC00351DC] = 0xC0635E3C false
+Instruction 4570 S:0xC003510C 0x685A 15 LDR r2,[r3,#4] false
+Instruction 4571 S:0xC003510E 0x4680 1 MOV r8,r0 false
+Instruction 4572 S:0xC0035110 0x2A00 1 CMP r2,#0 false
+Instruction 4573 S:0xC0035112 0xD116 0 BNE {pc}+0x30 ; 0xc0035142 true fail
+Instruction 4574 S:0xC0035114 0x4630 1 MOV r0,r6 false
+Instruction 4575 S:0xC0035116 0xF3AFFA4F 0 BL {pc}+0x3af4a2 ; 0xc03e45b8 true
+Cycle Count 66 Tracing disabled
+Info Tracing enabled
+Instruction 4576 S:0xC003511A 0xF1B80F00 1 CMP r8,#0 false
+Instruction 4577 S:0xC003511E 0xD006 0 BEQ {pc}+0x10 ; 0xc003512e true fail
+Instruction 4578 S:0xC0035120 0x6AA3 23 LDR r3,[r4,#0x28] false
+Instruction 4579 S:0xC0035122 0x2B02 2 CMP r3,#2 false
+Instruction 4580 S:0xC0035124 0xD10C 1 BNE {pc}+0x1c ; 0xc0035140 true fail
+Instruction 4581 S:0xC0035126 0x4639 1 MOV r1,r7 false
+Instruction 4582 S:0xC0035128 0x4620 0 MOV r0,r4 false
+Instruction 4583 S:0xC003512A 0xF7FFFE13 1 BL {pc}-0x3d6 ; 0xc0034d54 true
+Instruction 4584 S:0xC0034D54 0xB570 1 PUSH {r4-r6,lr} false
+Instruction 4585 S:0xC0034D56 0xB500 4 PUSH {lr} false
+Instruction 4586 S:0xC0034D58 0xF85DEB04 2 POP {lr} false
+Instruction 4587 S:0xC0034D5C 0x4605 0 MOV r5,r0 false
+Instruction 4588 S:0xC0034D5E 0x4B13 12 LDR r3,[pc,#76] ; [0xC0034DAC] = 0xC0635E64 false
+Instruction 4589 S:0xC0034D60 0x460E 0 MOV r6,r1 false
+Instruction 4590 S:0xC0034D62 0x685A 3 LDR r2,[r3,#4] false
+Instruction 4591 S:0xC0034D64 0xB9A2 2 CBNZ r2,{pc}+0x2c ; 0xc0034d90 true fail
+Instruction 4592 S:0xC0034D66 0xF106000C 19 ADD r0,r6,#0xc false
+Instruction 4593 S:0xC0034D6A 0x4629 0 MOV r1,r5 false
+Instruction 4594 S:0xC0034D6C 0xF222F8FE 1 BL {pc}+0x222200 ; 0xc0256f6c true
+Cycle Count 207 Tracing disabled
+Info Tracing enabled
+Instruction 4595 S:0xC0034D70 0x6833 1 LDR r3,[r6,#0] false
+Instruction 4596 S:0xC0034D72 0x6871 1 LDR r1,[r6,#4] false
+Instruction 4597 S:0xC0034D74 0x2001 0 MOVS r0,#1 false
+Instruction 4598 S:0xC0034D76 0x685A 2 LDR r2,[r3,#4] false
+Instruction 4599 S:0xC0034D78 0xFA00F101 1 LSL r1,r0,r1 false
+Instruction 4600 S:0xC0034D7C 0x430A 1 ORRS r2,r2,r1 false
+Instruction 4601 S:0xC0034D7E 0x605A 1 STR r2,[r3,#4] false
+Instruction 4602 S:0xC0034D80 0x6AAB 1 LDR r3,[r5,#0x28] false
+Instruction 4603 S:0xC0034D82 0x4303 2 ORRS r3,r3,r0 false
+Instruction 4604 S:0xC0034D84 0x62AB 1 STR r3,[r5,#0x28] false
+Instruction 4605 S:0xC0034D86 0x6930 1 LDR r0,[r6,#0x10] false
+Instruction 4606 S:0xC0034D88 0x1A2B 2 SUBS r3,r5,r0 false
+Instruction 4607 S:0xC0034D8A 0x4258 1 RSBS r0,r3,#0 false
+Instruction 4608 S:0xC0034D8C 0x4158 1 ADCS r0,r0,r3 false
+Instruction 4609 S:0xC0034D8E 0xBD70 1 POP {r4-r6,pc} true
+Instruction 4610 S:0xC003512E 0x6AA3 3 LDR r3,[r4,#0x28] false
+Instruction 4611 S:0xC0035130 0x0799 3 LSLS r1,r3,#30 false
+Instruction 4612 S:0xC0035132 0xD540 0 BPL {pc}+0x84 ; 0xc00351b6 true fail
+Instruction 4613 S:0xC0035134 0xF0230302 1 BIC r3,r3,#2 false
+Instruction 4614 S:0xC0035138 0x62A3 1 STR r3,[r4,#0x28] false
+Instruction 4615 S:0xC003513A 0xB003 0 ADD sp,sp,#0xc false
+Instruction 4616 S:0xC003513C 0xE8BD83F0 3 POP {r4-r9,pc} true
+Instruction 4617 S:0xC00359DA 0x6930 12 LDR r0,[r6,#0x10] false
+Instruction 4618 S:0xC00359DC 0x2800 2 CMP r0,#0 false
+Instruction 4619 S:0xC00359DE 0xD1F1 1 BNE {pc}-0x1a ; 0xc00359c4 true
+Instruction 4620 S:0xC00359C4 0xE9DD450E 11 LDRD r4,r5,[sp,#0x38] false
+Instruction 4621 S:0xC00359C8 0xE9D02306 1 LDRD r2,r3,[r0,#0x18] false
+Instruction 4622 S:0xC00359CC 0x4294 2 CMP r4,r2 false
+Instruction 4623 S:0xC00359CE 0xEB750103 1 SBCS r1,r5,r3 false
+Instruction 4624 S:0xC00359D2 0xDB76 0 BLT {pc}+0xf0 ; 0xc0035ac2 true
+Instruction 4625 S:0xC0035AC2 0xE9D6890C 21 LDRD r8,r9,[r6,#0x30] false
+Instruction 4626 S:0xC0035AC6 0xE9D02304 1 LDRD r2,r3,[r0,#0x10] false
+Instruction 4627 S:0xC0035ACA 0xEBB20208 2 SUBS r2,r2,r8 false
+Instruction 4628 S:0xC0035ACE 0xEB630309 1 SBC r3,r3,r9 false
+Instruction 4629 S:0xC0035AD2 0x2A00 0 CMP r2,#0 false
+Instruction 4630 S:0xC0035AD4 0xF1730000 1 SBCS r0,r3,#0 false
+Instruction 4631 S:0xC0035AD8 0xDB82 0 BLT {pc}-0xf8 ; 0xc00359e0 true fail
+Instruction 4632 S:0xC0035ADA 0xE9DD0102 16 LDRD r0,r1,[sp,#8] false
+Instruction 4633 S:0xC0035ADE 0x4282 2 CMP r2,r0 false
+Instruction 4634 S:0xC0035AE0 0xEB730101 1 SBCS r1,r3,r1 false
+Instruction 4635 S:0xC0035AE4 0xF6BFAF7C 0 BGE {pc}-0x104 ; 0xc00359e0 true fail
+Instruction 4636 S:0xC0035AE8 0x2F04 22 CMP r7,#4 false
+Instruction 4637 S:0xC0035AEA 0xE9CD2302 1 STRD r2,r3,[sp,#8] false
+Instruction 4638 S:0xC0035AEE 0xF47FAF4B 1 BNE {pc}-0x166 ; 0xc0035988 true
+Instruction 4639 S:0xC0035988 0xF8DA3004 8 LDR r3,[r10,#4] false
+Instruction 4640 S:0xC003598C 0xFA0BF207 1 LSL r2,r11,r7 false
+Instruction 4641 S:0xC0035990 0x3701 1 ADDS r7,#1 false
+Instruction 4642 S:0xC0035992 0x421A 1 TST r2,r3 false
+Instruction 4643 S:0xC0035994 0xD024 0 BEQ {pc}+0x4c ; 0xc00359e0 true
+Instruction 4644 S:0xC00359E0 0x2F04 2 CMP r7,#4 false
+Instruction 4645 S:0xC00359E2 0xD1D1 0 BNE {pc}-0x5a ; 0xc0035988 true
+Instruction 4646 S:0xC0035988 0xF8DA3004 3 LDR r3,[r10,#4] false
+Instruction 4647 S:0xC003598C 0xFA0BF207 1 LSL r2,r11,r7 false
+Instruction 4648 S:0xC0035990 0x3701 1 ADDS r7,#1 false
+Instruction 4649 S:0xC0035992 0x421A 1 TST r2,r3 false
+Instruction 4650 S:0xC0035994 0xD024 0 BEQ {pc}+0x4c ; 0xc00359e0 true
+Instruction 4651 S:0xC00359E0 0x2F04 8 CMP r7,#4 false
+Instruction 4652 S:0xC00359E2 0xD1D1 0 BNE {pc}-0x5a ; 0xc0035988 true
+Instruction 4653 S:0xC0035988 0xF8DA3004 3 LDR r3,[r10,#4] false
+Instruction 4654 S:0xC003598C 0xFA0BF207 1 LSL r2,r11,r7 false
+Instruction 4655 S:0xC0035990 0x3701 1 ADDS r7,#1 false
+Instruction 4656 S:0xC0035992 0x421A 1 TST r2,r3 false
+Instruction 4657 S:0xC0035994 0xD024 0 BEQ {pc}+0x4c ; 0xc00359e0 true
+Instruction 4658 S:0xC00359E0 0x2F04 8 CMP r7,#4 false
+Instruction 4659 S:0xC00359E2 0xD1D1 0 BNE {pc}-0x5a ; 0xc0035988 true fail
+Instruction 4660 S:0xC00359E4 0xE9DD2302 8 LDRD r2,r3,[sp,#8] false
+Instruction 4661 S:0xC00359E8 0xE9CA2304 1 STRD r2,r3,[r10,#0x10] false
+Instruction 4662 S:0xC00359EC 0xF3BF8F5F 1 DMB false
+Instruction 4663 S:0xC00359F0 0xF8BA3000 40 LDRH r3,[r10,#0] false
+Instruction 4664 S:0xC00359F4 0x3301 2 ADDS r3,#1 false
+Instruction 4665 S:0xC00359F6 0xF8AA3000 1 STRH r3,[r10,#0] false
+Instruction 4666 S:0xC00359FA 0xF3BF8F4F 36 DSB false
+Instruction 4667 S:0xC00359FE 0xF3AF8004 1 SEV.W false
+Instruction 4668 S:0xC0035A02 0xE9DD2302 3 LDRD r2,r3,[sp,#8] false
+Instruction 4669 S:0xC0035A06 0xF04F30FF 1 MOV r0,#0xffffffff false
+Instruction 4670 S:0xC0035A0A 0xF06F4100 0 MVN r1,#0x80000000 false
+Instruction 4671 S:0xC0035A0E 0x428B 1 CMP r3,r1 false
+Instruction 4672 S:0xC0035A10 0xBF08 0 IT EQ false
+Instruction 4673 S:0xC0035A12 0x4282 1 CMP r2,r0 false fail
+Instruction 4674 S:0xC0035A14 0xD074 0 BEQ {pc}+0xec ; 0xc0035b00 true fail
+Instruction 4675 S:0xC0035A16 0xE9DD0102 9 LDRD r0,r1,[sp,#8] false
+Instruction 4676 S:0xC0035A1A 0x2200 1 MOVS r2,#0 false
+Instruction 4677 S:0xC0035A1C 0xF01FFCA6 1 BL {pc}+0x1f950 ; 0xc005536c true
+Instruction 4678 S:0xC005536C 0xB530 14 PUSH {r4,r5,lr} false
+Instruction 4679 S:0xC005536E 0xB083 2 SUB sp,sp,#0xc false
+Instruction 4680 S:0xC0055370 0xB500 3 PUSH {lr} false
+Instruction 4681 S:0xC0055372 0xF85DEB04 2 POP {lr} false
+Instruction 4682 S:0xC0055376 0xF6400300 0 MOVW r3,#0x800 false
+Instruction 4683 S:0xC005537A 0x1C15 1 ADDS r5,r2,#0 false
+Instruction 4684 S:0xC005537C 0xF2CC035F 0 MOVT r3,#0xc05f false
+Instruction 4685 S:0xC0055380 0xEE1D2F90 12 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 4686 S:0xC0055384 0x58D4 4 LDR r4,[r2,r3] false
+Instruction 4687 S:0xC0055386 0xBF18 1 IT NE false
+Instruction 4688 S:0xC0055388 0x2501 1 MOVS r5,#1 false fail
+Instruction 4689 S:0xC005538A 0x4602 0 MOV r2,r0 false
+Instruction 4690 S:0xC005538C 0x460B 1 MOV r3,r1 false
+Instruction 4691 S:0xC005538E 0x9500 1 STR r5,[sp,#0] false
+Instruction 4692 S:0xC0055390 0x4620 0 MOV r0,r4 false
+Instruction 4693 S:0xC0055392 0xF7FEFF63 1 BL {pc}-0x1136 ; 0xc005425c true
+Instruction 4694 S:0xC005425C 0xE92D43F0 12 PUSH {r4-r9,lr} false
+Instruction 4695 S:0xC0054260 0xB083 17 SUB sp,sp,#0xc false
+Instruction 4696 S:0xC0054262 0xB500 3 PUSH {lr} false
+Instruction 4697 S:0xC0054264 0xF85DEB04 2 POP {lr} false
+Instruction 4698 S:0xC0054268 0x4614 0 MOV r4,r2 false
+Instruction 4699 S:0xC005426A 0x461D 1 MOV r5,r3 false
+Instruction 4700 S:0xC005426C 0x4680 0 MOV r8,r0 false
+Instruction 4701 S:0xC005426E 0x2C00 1 CMP r4,#0 false
+Instruction 4702 S:0xC0054270 0xF1750100 1 SBCS r1,r5,#0 false
+Instruction 4703 S:0xC0054274 0xF89D9028 1 LDRB r9,[sp,#0x28] false
+Instruction 4704 S:0xC0054278 0xDB59 0 BLT {pc}+0xb6 ; 0xc005432e true fail
+Instruction 4705 S:0xC005427A 0x6B01 3 LDR r1,[r0,#0x30] false
+Instruction 4706 S:0xC005427C 0x6102 3 STR r2,[r0,#0x10] false
+Instruction 4707 S:0xC005427E 0x2901 1 CMP r1,#1 false
+Instruction 4708 S:0xC0054280 0x6143 4 STR r3,[r0,#0x14] false
+Instruction 4709 S:0xC0054282 0xD052 0 BEQ {pc}+0xa8 ; 0xc005432a true fail
+Instruction 4710 S:0xC0054284 0x6B41 1 LDR r1,[r0,#0x34] false
+Instruction 4711 S:0xC0054286 0x0749 3 LSLS r1,r1,#29 false
+Instruction 4712 S:0xC0054288 0xD440 1 BMI {pc}+0x84 ; 0xc005430c true fail
+Instruction 4713 S:0xC005428A 0x4668 1 MOV r0,sp false
+Instruction 4714 S:0xC005428C 0xF7FBF94E 0 BL {pc}-0x4d60 ; 0xc004f52c true
+Instruction 4715 S:0xC004F52C 0xE92D4FF0 63 PUSH {r4-r11,lr} false
+Instruction 4716 S:0xC004F530 0xB08B 7 SUB sp,sp,#0x2c false
+Instruction 4717 S:0xC004F532 0xB500 3 PUSH {lr} false
+Instruction 4718 S:0xC004F534 0xF85DEB04 2 POP {lr} false
+Instruction 4719 S:0xC004F538 0x4B3D 2 LDR r3,[pc,#244] ; [0xC004F630] = 0xC05FC59C false
+Instruction 4720 S:0xC004F53A 0x4682 0 MOV r10,r0 false
+Instruction 4721 S:0xC004F53C 0x681B 5 LDR r3,[r3,#0] false
+Instruction 4722 S:0xC004F53E 0x2B00 2 CMP r3,#0 false
+Instruction 4723 S:0xC004F540 0xD16F 1 BNE {pc}+0xe2 ; 0xc004f622 true fail
+Instruction 4724 S:0xC004F542 0xF8DF90F4 1 LDR r9,[pc,#244] ; [0xC004F638] = 0xC064D1C0 false
+Instruction 4725 S:0xC004F546 0xF8DFB0F0 1 LDR r11,[pc,#240] ; [0xC004F638] = 0xC064D1C0 false
+Instruction 4726 S:0xC004F54A 0x464F 1 MOV r7,r9 false
+Instruction 4727 S:0xC004F54C 0xF8D75090 17 LDR r5,[r7,#0x90] false
+Instruction 4728 S:0xC004F550 0x07EA 3 LSLS r2,r5,#31 false
+Instruction 4729 S:0xC004F552 0xD46C 0 BMI {pc}+0xdc ; 0xc004f62e true fail
+Instruction 4730 S:0xC004F554 0xF3BF8F5F 1 DMB false
+Instruction 4731 S:0xC004F558 0xF8DB6000 40 LDR r6,[r11,#0] false
+Instruction 4732 S:0xC004F55C 0xF8DB4054 8 LDR r4,[r11,#0x54] false
+Instruction 4733 S:0xC004F560 0xE9DB230E 1 LDRD r2,r3,[r11,#0x38] false
+Instruction 4734 S:0xC004F564 0x4630 1 MOV r0,r6 false
+Instruction 4735 S:0xC004F566 0x6831 12 LDR r1,[r6,#0] false
+Instruction 4736 S:0xC004F568 0x1912 1 ADDS r2,r2,r4 false
+Instruction 4737 S:0xC004F56A 0xEB4373E4 1 ADC r3,r3,r4,ASR #31 false
+Instruction 4738 S:0xC004F56E 0xE9CD2306 1 STRD r2,r3,[sp,#0x18] false
+Instruction 4739 S:0xC004F572 0x4788 1 BLX r1 true
+Timestamp Timestamp: 562536984416
+Cycle Count 26 Tracing disabled
+Info Tracing enabled
+Instruction 4740 S:0xC004F574 0xE9D62302 1 LDRD r2,r3,[r6,#8] false
+Instruction 4741 S:0xC004F578 0xF8DBC004 1 LDR r12,[r11,#4] false
+Instruction 4742 S:0xC004F57C 0xF8DB4008 1 LDR r4,[r11,#8] false
+Instruction 4743 S:0xC004F580 0xE9CD2300 15 STRD r2,r3,[sp,#0] false
+Instruction 4744 S:0xC004F584 0xE9D62304 1 LDRD r2,r3,[r6,#0x10] false
+Instruction 4745 S:0xC004F588 0xF8DB6058 1 LDR r6,[r11,#0x58] false
+Instruction 4746 S:0xC004F58C 0xE9CD2308 1 STRD r2,r3,[sp,#0x20] false
+Instruction 4747 S:0xC004F590 0xE9DB2310 1 LDRD r2,r3,[r11,#0x40] false
+Instruction 4748 S:0xC004F594 0x9604 1 STR r6,[sp,#0x10] false
+Instruction 4749 S:0xC004F596 0xE9CD2302 1 STRD r2,r3,[sp,#8] false
+Instruction 4750 S:0xC004F59A 0x17F3 1 ASRS r3,r6,#31 false
+Instruction 4751 S:0xC004F59C 0x9305 1 STR r3,[sp,#0x14] false
+Instruction 4752 S:0xC004F59E 0xF1C40620 14 RSB r6,r4,#0x20 false
+Instruction 4753 S:0xC004F5A2 0xE9DD2300 1 LDRD r2,r3,[sp,#0] false
+Instruction 4754 S:0xC004F5A6 0x1A80 2 SUBS r0,r0,r2 false
+Instruction 4755 S:0xC004F5A8 0xEB610103 1 SBC r1,r1,r3 false
+Instruction 4756 S:0xC004F5AC 0xE9DD2308 1 LDRD r2,r3,[sp,#0x20] false
+Instruction 4757 S:0xC004F5B0 0x4010 2 ANDS r0,r0,r2 false
+Instruction 4758 S:0xC004F5B2 0x4019 1 ANDS r1,r1,r3 false
+Instruction 4759 S:0xC004F5B4 0xFBA0230C 1 UMULL r2,r3,r0,r12 false
+Instruction 4760 S:0xC004F5B8 0xFB0C3301 2 MLA r3,r12,r1,r3 false
+Instruction 4761 S:0xC004F5BC 0xE9DD0102 1 LDRD r0,r1,[sp,#8] false
+Instruction 4762 S:0xC004F5C0 0x1880 2 ADDS r0,r0,r2 false
+Instruction 4763 S:0xC004F5C2 0xEB410103 1 ADC r1,r1,r3 false
+Instruction 4764 S:0xC004F5C6 0xF1B40320 0 SUBS r3,r4,#0x20 false
+Instruction 4765 S:0xC004F5CA 0xE9CD0102 1 STRD r0,r1,[sp,#8] false
+Instruction 4766 S:0xC004F5CE 0xFA20F804 1 LSR r8,r0,r4 false
+Instruction 4767 S:0xC004F5D2 0xFA41F303 1 ASR r3,r1,r3 false
+Instruction 4768 S:0xC004F5D6 0x9903 1 LDR r1,[sp,#0xc] false
+Instruction 4769 S:0xC004F5D8 0x9A03 1 LDR r2,[sp,#0xc] false
+Instruction 4770 S:0xC004F5DA 0xFA01F606 2 LSL r6,r1,r6 false
+Instruction 4771 S:0xC004F5DE 0xEA480806 7 ORR r8,r8,r6 false
+Instruction 4772 S:0xC004F5E2 0xFA42F904 1 ASR r9,r2,r4 false
+Instruction 4773 S:0xC004F5E6 0xBF58 1 IT PL false
+Instruction 4774 S:0xC004F5E8 0xEA480803 1 ORR r8,r8,r3 false fail
+Instruction 4775 S:0xC004F5EC 0xE9DD2304 1 LDRD r2,r3,[sp,#0x10] false
+Instruction 4776 S:0xC004F5F0 0xEB120208 2 ADDS r2,r2,r8 false
+Instruction 4777 S:0xC004F5F4 0xEB430309 1 ADC r3,r3,r9 false
+Instruction 4778 S:0xC004F5F8 0xF3BF8F5F 1 DMB false
+Instruction 4779 S:0xC004F5FC 0xF8D71090 27 LDR r1,[r7,#0x90] false
+Instruction 4780 S:0xC004F600 0x428D 2 CMP r5,r1 false
+Instruction 4781 S:0xC004F602 0xD1A3 0 BNE {pc}-0xb6 ; 0xc004f54c true fail
+Instruction 4782 S:0xC004F604 0x461D 1 MOV r5,r3 false
+Instruction 4783 S:0xC004F606 0x9906 1 LDR r1,[sp,#0x18] false
+Instruction 4784 S:0xC004F608 0xF44F434A 0 MOV r3,#0xca00 false
+Instruction 4785 S:0xC004F60C 0x4614 1 MOV r4,r2 false
+Instruction 4786 S:0xC004F60E 0xF6C3339A 0 MOVT r3,#0x3b9a false
+Instruction 4787 S:0xC004F612 0x4650 1 MOV r0,r10 false
+Instruction 4788 S:0xC004F614 0xFBC34501 1 SMLAL r4,r5,r3,r1 false
+Instruction 4789 S:0xC004F618 0xE9CA4500 1 STRD r4,r5,[r10,#0] false
+Instruction 4790 S:0xC004F61C 0xB00B 1 ADD sp,sp,#0x2c false
+Instruction 4791 S:0xC004F61E 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Instruction 4792 S:0xC0054290 0xE9DD6700 7 LDRD r6,r7,[sp,#0] false
+Instruction 4793 S:0xC0054294 0x1BA4 2 SUBS r4,r4,r6 false
+Instruction 4794 S:0xC0054296 0xEB650507 1 SBC r5,r5,r7 false
+Instruction 4795 S:0xC005429A 0x2C01 0 CMP r4,#1 false
+Instruction 4796 S:0xC005429C 0xF1750200 1 SBCS r2,r5,#0 false
+Instruction 4797 S:0xC00542A0 0xDB3D 0 BLT {pc}+0x7e ; 0xc005431e true fail
+Instruction 4798 S:0xC00542A2 0xE9D86706 22 LDRD r6,r7,[r8,#0x18] false
+Instruction 4799 S:0xC00542A6 0xF8D8002C 1 LDR r0,[r8,#0x2c] false
+Instruction 4800 S:0xC00542AA 0x42B4 1 CMP r4,r6 false
+Instruction 4801 S:0xC00542AC 0xEB750307 1 SBCS r3,r5,r7 false
+Instruction 4802 S:0xC00542B0 0xE9D82308 1 LDRD r2,r3,[r8,#0x20] false
+Instruction 4803 S:0xC00542B4 0xBFBC 1 ITT LT false
+Instruction 4804 S:0xC00542B6 0x4626 1 MOV r6,r4 false
+Instruction 4805 S:0xC00542B8 0x462F 0 MOV r7,r5 false
+Instruction 4806 S:0xC00542BA 0x4296 1 CMP r6,r2 false
+Instruction 4807 S:0xC00542BC 0xEB770103 1 SBCS r1,r7,r3 false
+Instruction 4808 S:0xC00542C0 0x4641 12 MOV r1,r8 false
+Instruction 4809 S:0xC00542C2 0xBFB8 0 IT LT false
+Instruction 4810 S:0xC00542C4 0x461F 1 MOV r7,r3 false fail
+Instruction 4811 S:0xC00542C6 0xF8D83028 1 LDR r3,[r8,#0x28] false
+Instruction 4812 S:0xC00542CA 0xBFB8 1 IT LT false
+Instruction 4813 S:0xC00542CC 0x4616 1 MOV r6,r2 false fail
+Instruction 4814 S:0xC00542CE 0xF1A00220 0 SUB r2,r0,#0x20 false
+Instruction 4815 S:0xC00542D2 0xFBA64503 2 UMULL r4,r5,r6,r3 false
+Instruction 4816 S:0xC00542D6 0xF1C00620 1 RSB r6,r0,#0x20 false
+Instruction 4817 S:0xC00542DA 0xFB035507 1 MLA r5,r3,r7,r5 false
+Instruction 4818 S:0xC00542DE 0xFA24F000 14 LSR r0,r4,r0 false
+Instruction 4819 S:0xC00542E2 0xFA05F606 3 LSL r6,r5,r6 false
+Instruction 4820 S:0xC00542E6 0xFA25F202 3 LSR r2,r5,r2 false
+Instruction 4821 S:0xC00542EA 0x4330 1 ORRS r0,r0,r6 false
+Instruction 4822 S:0xC00542EC 0x4310 1 ORRS r0,r0,r2 false
+Instruction 4823 S:0xC00542EE 0xF8D82004 1 LDR r2,[r8,#4] false
+Instruction 4824 S:0xC00542F2 0x4790 1 BLX r2 true
+Timestamp Timestamp: 562536984431
+Cycle Count 83 Tracing disabled
+Info Tracing enabled
+Instruction 4825 S:0xC00542F4 0x2800 1 CMP r0,#0 false
+Instruction 4826 S:0xC00542F6 0xBF0C 0 ITE EQ false
+Timestamp Timestamp: 562536984437
+Instruction 4827 S:0xC00542F8 0x2300 1 MOVS r3,#0 false
+Instruction 4828 S:0xC00542FA 0xF0090301 0 AND r3,r9,#1 false fail
+Instruction 4829 S:0xC00542FE 0xB15B 1 CBZ r3,{pc}+0x1a ; 0xc0054318 true
+Instruction 4830 S:0xC0054318 0xB003 3 ADD sp,sp,#0xc false
+Instruction 4831 S:0xC005431A 0xE8BD83F0 3 POP {r4-r9,pc} true
+Instruction 4832 S:0xC0055396 0xB003 4 ADD sp,sp,#0xc false
+Instruction 4833 S:0xC0055398 0xBD30 3 POP {r4,r5,pc} true
+Instruction 4834 S:0xC0035A20 0x2800 11 CMP r0,#0 false
+Instruction 4835 S:0xC0035A22 0xD06D 0 BEQ {pc}+0xde ; 0xc0035b00 true
+Instruction 4836 S:0xC0035B00 0x2300 8 MOVS r3,#0 false
+Instruction 4837 S:0xC0035B02 0xF8CA301C 3 STR r3,[r10,#0x1c] false
+Instruction 4838 S:0xC0035B06 0xE7D9 1 B {pc}-0x4a ; 0xc0035abc true
+Instruction 4839 S:0xC0035ABC 0xB011 2 ADD sp,sp,#0x44 false
+Instruction 4840 S:0xC0035ABE 0xE8BD8FF0 3 POP {r4-r11,pc} true
+Cycle Count 214 Tracing disabled
+Info Tracing enabled
+Instruction 4841 S:0xC000D60C 0xF013FDDA 1 BL {pc}+0x13bb8 ; 0xc00211c4 true
+Instruction 4842 S:0xC00211C4 0xB510 3 PUSH {r4,lr} false
+Instruction 4843 S:0xC00211C6 0xB500 1 PUSH {lr} false
+Instruction 4844 S:0xC00211C8 0xF85DEB04 2 POP {lr} false
+Instruction 4845 S:0xC00211CC 0xF3EF8300 1 MRS r3,APSR ; formerly CPSR false
+Instruction 4846 S:0xC00211D0 0x0619 3 LSLS r1,r3,#24 false
+Instruction 4847 S:0xC00211D2 0xD529 0 BPL {pc}+0x56 ; 0xc0021228 true fail
+Instruction 4848 S:0xC00211D4 0x466B 16 MOV r3,sp false
+Instruction 4849 S:0xC00211D6 0xF42354FF 1 BIC r4,r3,#0x1fe0 false
+Instruction 4850 S:0xC00211DA 0xF024041F 1 BIC r4,r4,#0x1f false
+Instruction 4851 S:0xC00211DE 0x6863 5 LDR r3,[r4,#4] false
+Instruction 4852 S:0xC00211E0 0xF5A33380 13 SUB r3,r3,#0x10000 false
+Instruction 4853 S:0xC00211E4 0x6063 1 STR r3,[r4,#4] false
+Instruction 4854 S:0xC00211E6 0xF0234378 1 BIC r3,r3,#0xf8000000 false
+Instruction 4855 S:0xC00211EA 0xF02303FF 1 BIC r3,r3,#0xff false
+Instruction 4856 S:0xC00211EE 0xB923 1 CBNZ r3,{pc}+0xc ; 0xc00211fa true fail
+Instruction 4857 S:0xC00211F0 0x6963 1 LDR r3,[r4,#0x14] false
+Instruction 4858 S:0xC00211F2 0x4A13 14 LDR r2,[pc,#76] ; [0xC0021240] = 0xC06498C0 false
+Instruction 4859 S:0xC00211F4 0x019B 2 LSLS r3,r3,#6 false
+Instruction 4860 S:0xC00211F6 0x58D3 5 LDR r3,[r2,r3] false
+Instruction 4861 S:0xC00211F8 0xB99B 2 CBNZ r3,{pc}+0x2a ; 0xc0021222 true
+Instruction 4862 S:0xC0021222 0xF7FFFE0B 8 BL {pc}-0x3e6 ; 0xc0020e3c true
+Instruction 4863 S:0xC0020E3C 0xE92D4FF0 15 PUSH {r4-r11,lr} false
+Instruction 4864 S:0xC0020E40 0xB089 18 SUB sp,sp,#0x24 false
+Instruction 4865 S:0xC0020E42 0xB500 3 PUSH {lr} false
+Instruction 4866 S:0xC0020E44 0xF85DEB04 2 POP {lr} false
+Instruction 4867 S:0xC0020E48 0x2002 0 MOVS r0,#2 false
+Instruction 4868 S:0xC0020E4A 0xF7FFFA3D 1 BL {pc}-0xb82 ; 0xc00202c8 true
+Instruction 4869 S:0xC00202C8 0xB500 14 PUSH {lr} false
+Instruction 4870 S:0xC00202CA 0xF85DEB04 2 POP {lr} false
+Instruction 4871 S:0xC00202CE 0x2800 1 CMP r0,#0 false
+Instruction 4872 S:0xC00202D0 0xBFA1 0 ITTTT GE false
+Instruction 4873 S:0xC00202D2 0xF64C43CD 1 MOV r3,#0xcccd false
+Instruction 4874 S:0xC00202D6 0x3009 0 ADDS r0,r0,#9 false
+Instruction 4875 S:0xC00202D8 0xF6CC43CC 1 MOVT r3,#0xcccc false
+Instruction 4876 S:0xC00202DC 0xFBA32000 2 UMULL r2,r0,r3,r0 false
+Instruction 4877 S:0xC00202E0 0xBFAE 1 ITEE GE false
+Instruction 4878 S:0xC00202E2 0x08C0 2 LSRS r0,r0,#3 false
+Instruction 4879 S:0xC00202E4 0xF64F70FE 0 MOV r0,#0xfffe false fail
+Instruction 4880 S:0xC00202E8 0xF6C370FF 1 MOVT r0,#0x3fff false fail
+Instruction 4881 S:0xC00202EC 0x4770 1 BX lr true
+Instruction 4882 S:0xC0020E4E 0x4669 1 MOV r1,sp false
+Instruction 4883 S:0xC0020E50 0xF42158FF 1 BIC r8,r1,#0x1fe0 false
+Instruction 4884 S:0xC0020E54 0xF24602C0 0 MOV r2,#0x60c0 false
+Instruction 4885 S:0xC0020E58 0xF028081F 1 BIC r8,r8,#0x1f false
+Instruction 4886 S:0xC0020E5C 0xF2CC025F 0 MOVT r2,#0xc05f false
+Instruction 4887 S:0xC0020E60 0xF6490EC0 11 MOV lr,#0x98c0 false
+Instruction 4888 S:0xC0020E64 0xF8D8300C 1 LDR r3,[r8,#0xc] false
+Instruction 4889 S:0xC0020E68 0xF2CC0E64 1 MOVT lr,#0xc064 false
+Instruction 4890 S:0xC0020E6C 0x6811 3 LDR r1,[r2,#0] false
+Instruction 4891 S:0xC0020E6E 0x68DC 3 LDR r4,[r3,#0xc] false
+Instruction 4892 S:0xC0020E70 0xF4246200 2 BIC r2,r4,#0x800 false
+Instruction 4893 S:0xC0020E74 0x60DA 1 STR r2,[r3,#0xc] false
+Instruction 4894 S:0xC0020E76 0xF8D82014 1 LDR r2,[r8,#0x14] false
+Instruction 4895 S:0xC0020E7A 0xF8D83004 1 LDR r3,[r8,#4] false
+Instruction 4896 S:0xC0020E7E 0x9407 1 STR r4,[sp,#0x1c] false
+Instruction 4897 S:0xC0020E80 0x0192 6 LSLS r2,r2,#6 false
+Instruction 4898 S:0xC0020E82 0xF5037380 0 ADD r3,r3,#0x100 false
+Instruction 4899 S:0xC0020E86 0xF8C83004 1 STR r3,[r8,#4] false
+Instruction 4900 S:0xC0020E8A 0xF85E4002 2 LDR r4,[lr,r2] false
+Instruction 4901 S:0xC0020E8E 0x1841 1 ADDS r1,r0,r1 false
+Instruction 4902 S:0xC0020E90 0x9106 1 STR r1,[sp,#0x18] false
+Instruction 4903 S:0xC0020E92 0xF8DFA160 14 LDR r10,[pc,#352] ; [0xC0020FF4] false
+Instruction 4904 S:0xC0020E96 0x46C1 0 MOV r9,r8 false
+Instruction 4905 S:0xC0020E98 0xF8D82014 3 LDR r2,[r8,#0x14] false
+Instruction 4906 S:0xC0020E9C 0x210A 0 MOVS r1,#0xa false
+Instruction 4907 S:0xC0020E9E 0x9105 1 STR r1,[sp,#0x14] false
+Instruction 4908 S:0xC0020EA0 0x9204 1 STR r2,[sp,#0x10] false
+Instruction 4909 S:0xC0020EA2 0xF8D93014 1 LDR r3,[r9,#0x14] false
+Instruction 4910 S:0xC0020EA6 0xF64902C0 0 MOV r2,#0x98c0 false
+Instruction 4911 S:0xC0020EAA 0xF2CC0264 1 MOVT r2,#0xc064 false
+Instruction 4912 S:0xC0020EAE 0x2100 0 MOVS r1,#0 false
+Instruction 4913 S:0xC0020EB0 0x019B 2 LSLS r3,r3,#6 false
+Instruction 4914 S:0xC0020EB2 0x50D1 3 STR r1,[r2,r3] false
+Instruction 4915 S:0xC0020EB4 0xB662 1 CPSIE i false
+Instruction 4916 S:0xC0020EB6 0x4F4E 1 LDR r7,[pc,#312] ; [0xC0020FF0] false
+Instruction 4917 S:0xC0020EB8 0x460E 0 MOV r6,r1 false
+Instruction 4918 S:0xC0020EBA 0xF2460380 1 MOVW r3,#0x6080 false
+Instruction 4919 S:0xC0020EBE 0x07E0 1 LSLS r0,r4,#31 false
+Instruction 4920 S:0xC0020EC0 0xF2CC035F 7 MOVT r3,#0xc05f false
+Instruction 4921 S:0xC0020EC4 0xEB030806 1 ADD r8,r3,r6 false
+Instruction 4922 S:0xC0020EC8 0xD525 1 BPL {pc}+0x4e ; 0xc0020f16 true
+Instruction 4923 S:0xC0020F16 0x0864 39 LSRS r4,r4,#1 false
+Instruction 4924 S:0xC0020F18 0xF1060604 1 ADD r6,r6,#4 false
+Instruction 4925 S:0xC0020F1C 0xF1070704 0 ADD r7,r7,#4 false
+Instruction 4926 S:0xC0020F20 0xD1CB 17 BNE {pc}-0x66 ; 0xc0020eba true
+Instruction 4927 S:0xC0020EBA 0xF2460380 21 MOVW r3,#0x6080 false
+Instruction 4928 S:0xC0020EBE 0x07E0 1 LSLS r0,r4,#31 false
+Instruction 4929 S:0xC0020EC0 0xF2CC035F 1 MOVT r3,#0xc05f false
+Instruction 4930 S:0xC0020EC4 0xEB030806 1 ADD r8,r3,r6 false
+Instruction 4931 S:0xC0020EC8 0xD525 0 BPL {pc}+0x4e ; 0xc0020f16 true fail
+Instruction 4932 S:0xC0020ECA 0x10B5 8 ASRS r5,r6,#2 false
+Instruction 4933 S:0xC0020ECC 0xF8D91004 1 LDR r1,[r9,#4] false
+Instruction 4934 S:0xC0020ED0 0xF2407EB8 1 MOVW lr,#0x7b8 false
+Instruction 4935 S:0xC0020ED4 0x4847 1 LDR r0,[pc,#284] ; [0xC0020FF4] false
+Instruction 4936 S:0xC0020ED6 0x00AB 1 LSLS r3,r5,#2 false
+Instruction 4937 S:0xC0020ED8 0xF2CC0E5F 0 MOVT lr,#0xc05f false
+Instruction 4938 S:0xC0020EDC 0x9303 1 STR r3,[sp,#0xc] false
+Instruction 4939 S:0xC0020EDE 0x4473 1 ADD r3,r3,lr false
+Instruction 4940 S:0xC0020EE0 0xEE1D2F90 1 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 4941 S:0xC0020EE4 0x9102 1 STR r1,[sp,#8] false
+Instruction 4942 S:0xC0020EE6 0x3304 0 ADDS r3,#4 false
+Instruction 4943 S:0xC0020EE8 0x58D1 5 LDR r1,[r2,r3] false
+Instruction 4944 S:0xC0020EEA 0x3101 2 ADDS r1,#1 false
+Instruction 4945 S:0xC0020EEC 0x50D1 1 STR r1,[r2,r3] false
+Instruction 4946 S:0xC0020EEE 0xF8DA3004 13 LDR r3,[r10,#4] false
+Instruction 4947 S:0xC0020EF2 0x2B00 2 CMP r3,#0 false
+Instruction 4948 S:0xC0020EF4 0xD148 0 BNE {pc}+0x94 ; 0xc0020f88 true fail
+Instruction 4949 S:0xC0020EF6 0xF8573C04 28 LDR r3,[r7,#-4] false
+Instruction 4950 S:0xC0020EFA 0x4640 0 MOV r0,r8 false
+Instruction 4951 S:0xC0020EFC 0x4798 1 BLX r3 true
+Instruction 4952 S:0xC0025AC0 0xE92D4FF0 22 PUSH {r4-r11,lr} false
+Instruction 4953 S:0xC0025AC4 0xB08B 7 SUB sp,sp,#0x2c false
+Instruction 4954 S:0xC0025AC6 0xB500 3 PUSH {lr} false
+Instruction 4955 S:0xC0025AC8 0xF85DEB04 2 POP {lr} false
+Instruction 4956 S:0xC0025ACC 0x4B6C 12 LDR r3,[pc,#432] ; [0xC0025C80] = 0xC05F0638 false
+Instruction 4957 S:0xC0025ACE 0xEE1D2F90 1 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 4958 S:0xC0025AD2 0x58D4 4 LDR r4,[r2,r3] false
+Instruction 4959 S:0xC0025AD4 0xF010F862 0 BL {pc}+0x100c8 ; 0xc0035b9c true
+Instruction 4960 S:0xC0035B9C 0xB5F8 1 PUSH {r3-r7,lr} false
+Instruction 4961 S:0xC0035B9E 0xB500 5 PUSH {lr} false
+Instruction 4962 S:0xC0035BA0 0xF85DEB04 6 POP {lr} false
+Instruction 4963 S:0xC0035BA4 0x4C21 16 LDR r4,[pc,#132] ; [0xC0035C2C] = 0xC05F0640 false
+Instruction 4964 S:0xC0035BA6 0xEE1D2F90 1 MRC p15,#0x0,r2,c13,c0,#4 false
+Instruction 4965 S:0xC0035BAA 0xF1040318 1 ADD r3,r4,#0x18 false
+Instruction 4966 S:0xC0035BAE 0x58D3 3 LDR r3,[r2,r3] false
+Instruction 4967 S:0xC0035BB0 0xB103 2 CBZ r3,{pc}+4 ; 0xc0035bb4 true fail
+Instruction 4968 S:0xC0035BB2 0xBDF8 3 POP {r3-r7,pc} true
+Instruction 4969 S:0xC0025AD8 0xF24603C0 5 MOV r3,#0x60c0 false
+Instruction 4970 S:0xC0025ADC 0xF2CC035F 1 MOVT r3,#0xc05f false
+Instruction 4971 S:0xC0025AE0 0x681A 3 LDR r2,[r3,#0] false
+Instruction 4972 S:0xC0025AE2 0x68A3 12 LDR r3,[r4,#8] false
+Instruction 4973 S:0xC0025AE4 0x1AD3 2 SUBS r3,r2,r3 false
+Instruction 4974 S:0xC0025AE6 0x2B00 1 CMP r3,#0 false
+Instruction 4975 S:0xC0025AE8 0xDB7F 0 BLT {pc}+0x102 ; 0xc0025bea true fail
+Instruction 4976 S:0xC0025AEA 0x4620 1 MOV r0,r4 false
+Instruction 4977 S:0xC0025AEC 0xF3BEFD9A 0 BL {pc}+0x3beb38 ; 0xc03e4624 true
+Cycle Count 46 Tracing disabled
+Info Tracing enabled
+Instruction 4978 S:0xC0025AF0 0xF24602C0 1 MOV r2,#0x60c0 false
+Instruction 4979 S:0xC0025AF4 0xF2CC025F 1 MOVT r2,#0xc05f false
+Instruction 4980 S:0xC0025AF8 0x6813 22 LDR r3,[r2,#0] false
+Instruction 4981 S:0xC0025AFA 0x68A2 3 LDR r2,[r4,#8] false
+Instruction 4982 S:0xC0025AFC 0x1A9B 2 SUBS r3,r3,r2 false
+Instruction 4983 S:0xC0025AFE 0x2B00 1 CMP r3,#0 false
+Instruction 4984 S:0xC0025B00 0xDB67 0 BLT {pc}+0xd2 ; 0xc0025bd2 true fail