diff options
| author | Michael Adler <madler@tapil.com> | 2026-07-09 17:00:32 +0000 |
|---|---|---|
| committer | Kevin Bowling <kbowling@FreeBSD.org> | 2026-08-08 00:33:28 +0000 |
| commit | 56cdca658ce721c4651c91bd5dbe5fd6243769a1 (patch) | |
| tree | df8cafda68a5e8507eb52373c506ecd9d555d91d | |
| parent | ebb6b8e7e27367437be0248058920023803d9aac (diff) | |
pci: Add L1 PM definitions
Add register/bit definitions for the L1 PM substates capability
(PCIZ_L1PM) to pcireg.h.
Signed-off-by: Michael Adler <madler@tapil.com>
Pull-Request: https://github.com/freebsd/freebsd-src/pull/2318
(cherry picked from commit 04f8a6aeeba5cbaa48be7134765ee49d5b1b9857)
| -rw-r--r-- | sys/dev/pci/pcireg.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h index f6aaf30611e4..9a48e9183201 100644 --- a/sys/dev/pci/pcireg.h +++ b/sys/dev/pci/pcireg.h @@ -1128,6 +1128,20 @@ #define PCIM_ACS_UNCLAIMED_REQ_REDIRECT_CTL 0x1000 #define PCIR_ACS_EGRESS_CONTROL_VECTOR 0x8 +/* L1 PM Substates definitions */ +#define PCIR_L1PM_CAP 0x04 +#define PCIM_L1PM_CAP_PCIPM_L1_2 0x00000001 +#define PCIM_L1PM_CAP_PCIPM_L1_1 0x00000002 +#define PCIM_L1PM_CAP_ASPM_L1_2 0x00000004 +#define PCIM_L1PM_CAP_ASPM_L1_1 0x00000008 +#define PCIM_L1PM_CAP_L1PM_SUBSTATES 0x00000010 +#define PCIR_L1PM_CTL1 0x08 +#define PCIM_L1PM_CTL1_PCIPM_L1_2 0x00000001 +#define PCIM_L1PM_CTL1_PCIPM_L1_1 0x00000002 +#define PCIM_L1PM_CTL1_ASPM_L1_2 0x00000004 +#define PCIM_L1PM_CTL1_ASPM_L1_1 0x00000008 +#define PCIR_L1PM_CTL2 0x0c + /* * AMD IOMMU Base Capability * From AMD I/O Virtualization Technology (IOMMU) Specification |