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| author | Mitchell Horne <mhorne@FreeBSD.org> | 2021-04-01 13:19:43 +0000 |
|---|---|---|
| committer | Mitchell Horne <mhorne@FreeBSD.org> | 2021-06-30 19:26:07 +0000 |
| commit | 5867cccdc49df3e7eb3147d6516b488dd8384afe (patch) | |
| tree | f0d1dec67bb275541678e7d232a9d78e872a37a9 | |
| parent | 2129c8f6771a9a33253a1fe2d4e9d3494bc77f10 (diff) | |
| download | src-5867cccdc49df3e7eb3147d6516b488dd8384afe.tar.gz src-5867cccdc49df3e7eb3147d6516b488dd8384afe.zip | |
hwpmc_arm64: fill kern.hwpmc.cpuid
This will be used to detect supported pmu events. The expected format is
the MIDR register with the revision and variant fields masked. See also:
lib/libpmc/pmu-events/arch/arm64/mapfile.csv.
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D30601
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_arm64.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c index ba98eaefcc9a..be26605bad51 100644 --- a/sys/dev/hwpmc/hwpmc_arm64.c +++ b/sys/dev/hwpmc/hwpmc_arm64.c @@ -505,6 +505,7 @@ pmc_arm64_initialize() struct pmc_classdep *pcd; int idcode, impcode; int reg; + uint64_t midr; reg = arm64_pmcr_read(); arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; @@ -514,6 +515,18 @@ pmc_arm64_initialize() PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); /* + * Write the CPU model to kern.hwpmc.cpuid. + * + * We zero the variant and revision fields. + * + * TODO: how to handle differences between cores due to big.LITTLE? + * For now, just use MIDR from CPU 0. + */ + midr = (uint64_t)(pcpu_find(0)->pc_midr); + midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); + snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); + + /* * Allocate space for pointers to PMC HW descriptors and for * the MDEP structure used by MI code. */ |