Merge ^/head r305892 through r306302.

1770 files changed, 75248 insertions, 69668 deletions

diff --git a/UPDATING b/UPDATING
index 9b2adeddb52e..ad49262b69bb 100644
--- a/UPDATING
+++ b/UPDATING
@@ -31,6 +31,16 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 12.x IS SLOW:
 	disable the most expensive debugging functionality run
 	"ln -s 'abort:false,junk:false' /etc/malloc.conf".)
 
+20160918:
+	GNU rcs has been turned off by default.  It can (temporarily) be built
+	again by adding WITH_RCS knob in src.conf.
+	Otherwise, GNU rcs is available from packages:
+	- rcs: Latest GPLv3 GNU rcs version.
+	- rcs57: Copy of the latest version of GNU rcs (GPLv2) from base.
+
+20160918:
+	The backup_uses_rcs functionality has been removed from rc.subr.
+
 20160908:
 	The queue(3) debugging macro, QUEUE_MACRO_DEBUG, has been split into
 	two separate components, QUEUE_MACRO_DEBUG_TRACE and
diff --git a/contrib/cortex-strings/.gitignore b/contrib/cortex-strings/.gitignore
new file mode 100644
index 000000000000..558ca155c736
--- /dev/null
+++ b/contrib/cortex-strings/.gitignore
@@ -0,0 +1,11 @@
+*.a
+*.o
+*.la
+*.lo
+*.png
+*.pyc
+.deps
+.dirstamp
+.libs
+try-*
+cache.txt
diff --git a/contrib/cortex-strings/Makefile.am b/contrib/cortex-strings/Makefile.am
new file mode 100644
index 000000000000..db6bb93254a4
--- /dev/null
+++ b/contrib/cortex-strings/Makefile.am
@@ -0,0 +1,327 @@
+# Copyright (c) 2011, Linaro Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of the Linaro nor the
+#       names of its contributors may be used to endorse or promote products
+#       derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+# Top level Makefile for cortex-strings
+
+# Used to record the compiler version in the executables
+COMPILER = $(shell $(CC) --version 2>&1 | head -n1)
+
+# The main library
+lib_LTLIBRARIES = \
+	libcortex-strings.la
+
+## Test suite
+check_PROGRAMS = \
+	tests/test-memchr \
+	tests/test-memcmp \
+	tests/test-memcpy \
+	tests/test-memmove \
+	tests/test-memset \
+	tests/test-strchr \
+	tests/test-strcmp \
+	tests/test-strcpy \
+	tests/test-strlen \
+	tests/test-strncmp \
+	tests/test-strnlen
+
+# Options for the tests
+tests_cflags = -I$(srcdir)/tests $(AM_CFLAGS)
+tests_ldadd = libcortex-strings.la
+tests_test_memchr_LDADD = $(tests_ldadd)
+tests_test_memchr_CFLAGS = $(tests_cflags)
+tests_test_memcmp_LDADD = $(tests_ldadd)
+tests_test_memcmp_CFLAGS = $(tests_cflags)
+tests_test_memcpy_LDADD = $(tests_ldadd)
+tests_test_memcpy_CFLAGS = $(tests_cflags)
+tests_test_memmove_LDADD = $(tests_ldadd)
+tests_test_memmove_CFLAGS = $(tests_cflags)
+tests_test_memset_LDADD = $(tests_ldadd)
+tests_test_memset_CFLAGS = $(tests_cflags)
+tests_test_strchr_LDADD = $(tests_ldadd)
+tests_test_strchr_CFLAGS = $(tests_cflags)
+tests_test_strcmp_LDADD = $(tests_ldadd)
+tests_test_strcmp_CFLAGS = $(tests_cflags)
+tests_test_strcpy_LDADD = $(tests_ldadd)
+tests_test_strcpy_CFLAGS = $(tests_cflags)
+tests_test_strlen_LDADD = $(tests_ldadd)
+tests_test_strlen_CFLAGS = $(tests_cflags)
+tests_test_strncmp_LDADD = $(tests_ldadd)
+tests_test_strncmp_CFLAGS = $(tests_cflags)
+
+TESTS = $(check_PROGRAMS)
+
+## Benchmarks
+noinst_PROGRAMS = \
+	dhry \
+	dhry-native \
+	try-none \
+	try-this \
+	try-plain \
+	try-newlib-c \
+	try-bionic-c \
+	try-glibc-c
+
+# Good 'ol Dhrystone
+dhry_SOURCES = \
+	benchmarks/dhry/dhry_1.c \
+	benchmarks/dhry/dhry_2.c \
+	benchmarks/dhry/dhry.h
+
+dhry_CFLAGS = -Dcompiler="\"$(COMPILER)\"" -Doptions="\"$(CFLAGS)\""
+dhry_LDADD = libcortex-strings.la
+
+dhry_native_SOURCES = $(dhry_SOURCES)
+dhry_native_CFLAGS = $(dhry_CFLAGS)
+
+# Benchmark harness
+noinst_LIBRARIES = \
+	libmulti.a \
+	libbionic-c.a \
+	libglibc-c.a \
+	libnewlib-c.a \
+	libplain.a
+
+libmulti_a_SOURCES = \
+	benchmarks/multi/harness.c
+
+libmulti_a_CFLAGS = -DVERSION=\"$(VERSION)\" $(AM_CFLAGS)
+
+## Other architecture independant implementaions
+libbionic_c_a_SOURCES = \
+	reference/bionic-c/bcopy.c \
+	reference/bionic-c/memchr.c \
+	reference/bionic-c/memcmp.c \
+	reference/bionic-c/memcpy.c \
+	reference/bionic-c/memset.c \
+	reference/bionic-c/strchr.c \
+	reference/bionic-c/strcmp.c \
+	reference/bionic-c/strcpy.c \
+	reference/bionic-c/strlen.c
+
+libglibc_c_a_SOURCES = \
+	reference/glibc-c/memchr.c \
+	reference/glibc-c/memcmp.c \
+	reference/glibc-c/memcpy.c \
+	reference/glibc-c/memset.c \
+	reference/glibc-c/strchr.c \
+	reference/glibc-c/strcmp.c \
+	reference/glibc-c/strcpy.c \
+	reference/glibc-c/strlen.c \
+	reference/glibc-c/wordcopy.c \
+	reference/glibc-c/memcopy.h \
+	reference/glibc-c/pagecopy.h
+
+libnewlib_c_a_SOURCES = \
+	reference/newlib-c/memchr.c \
+	reference/newlib-c/memcmp.c \
+	reference/newlib-c/memcpy.c \
+	reference/newlib-c/memset.c \
+	reference/newlib-c/strchr.c \
+	reference/newlib-c/strcmp.c \
+	reference/newlib-c/strcpy.c \
+	reference/newlib-c/strlen.c \
+	reference/newlib-c/shim.h
+
+libplain_a_SOURCES = \
+	reference/plain/memset.c \
+	reference/plain/memcpy.c \
+	reference/plain/strcmp.c \
+	reference/plain/strcpy.c
+
+try_none_SOURCES =
+try_none_LDADD = libmulti.a -lrt
+try_this_SOURCES =
+try_this_LDADD = libmulti.a libcortex-strings.la -lrt
+try_bionic_c_SOURCES =
+try_bionic_c_LDADD = libmulti.a libbionic-c.a -lrt
+try_glibc_c_SOURCES =
+try_glibc_c_LDADD = libmulti.a libglibc-c.a -lrt
+try_newlib_c_SOURCES =
+try_newlib_c_LDADD = libmulti.a libnewlib-c.a -lrt
+try_plain_SOURCES =
+try_plain_LDADD = libmulti.a libplain.a -lrt
+
+# Architecture specific
+
+if HOST_AARCH32
+
+if WITH_NEON
+# Pull in the NEON specific files
+neon_bionic_a9_sources = \
+	reference/bionic-a9/memcpy.S \
+	reference/bionic-a9/memset.S
+neon_bionic_a15_sources = \
+	reference/bionic-a15/memcpy.S \
+	reference/bionic-a15/memset.S
+fpu_flags = -mfpu=neon
+else
+if WITH_VFP
+fpu_flags = -mfpu=vfp
+else
+fpu_flags = -msoft-float
+endif
+endif
+
+# Benchmarks and example programs
+noinst_PROGRAMS += \
+	try-bionic-a9 \
+	try-bionic-a15 \
+	try-csl \
+	try-glibc \
+	try-newlib \
+	try-newlib-xscale
+
+# Libraries used in the benchmarks and examples
+noinst_LIBRARIES += \
+	libbionic-a9.a \
+	libbionic-a15.a \
+	libcsl.a \
+	libglibc.a \
+	libnewlib.a \
+	libnewlib-xscale.a
+
+# Main library
+libcortex_strings_la_SOURCES = \
+	src/thumb-2/strcpy.c \
+	src/arm/memchr.S \
+	src/arm/strchr.S \
+	src/thumb-2/strlen.S \
+	src/arm/memset.S \
+	src/arm/memcpy.S \
+	src/arm/strcmp.S
+
+# Libraries containing the difference reference versions
+libbionic_a9_a_SOURCES = \
+	$(neon_bionic_a9_sources) \
+	reference/bionic-a9/memcmp.S \
+	reference/bionic-a9/strcmp.S \
+	reference/bionic-a9/strcpy.S \
+	reference/bionic-a9/strlen.c
+
+libbionic_a9_a_CFLAGS = -Wa,-mimplicit-it=thumb
+
+libbionic_a15_a_SOURCES = \
+	$(neon_bionic_a15_sources) \
+	reference/bionic-a15/memcmp.S \
+	reference/bionic-a15/strcmp.S \
+	reference/bionic-a15/strcpy.S \
+	reference/bionic-a15/strlen.c
+
+libbionic_a15_a_CFLAGS = -Wa,-mimplicit-it=thumb
+
+libcsl_a_SOURCES = \
+	reference/csl/memcpy.c \
+	reference/csl/memset.c \
+	reference/csl/arm_asm.h
+
+libglibc_a_SOURCES = \
+	reference/glibc/memcpy.S \
+	reference/glibc/memset.S \
+	reference/glibc/strchr.S \
+	reference/glibc/strlen.S
+
+libnewlib_a_SOURCES = \
+	reference/newlib/memcpy.S \
+	reference/newlib/strcmp.S \
+	reference/newlib/strcpy.c \
+	reference/newlib/strlen.c \
+	reference/newlib/arm_asm.h \
+	reference/newlib/shim.h
+
+libnewlib_xscale_a_SOURCES = \
+	reference/newlib-xscale/memchr.c \
+	reference/newlib-xscale/memcpy.c \
+	reference/newlib-xscale/memset.c \
+	reference/newlib-xscale/strchr.c \
+	reference/newlib-xscale/strcmp.c \
+	reference/newlib-xscale/strcpy.c \
+	reference/newlib-xscale/strlen.c \
+	reference/newlib-xscale/xscale.h
+
+# Flags for the benchmark helpers
+try_bionic_a9_SOURCES =
+try_bionic_a9_LDADD = libmulti.a libbionic-a9.a -lrt
+try_bionic_a15_SOURCES =
+try_bionic_a15_LDADD = libmulti.a libbionic-a15.a -lrt
+try_csl_SOURCES =
+try_csl_LDADD = libmulti.a libcsl.a -lrt
+try_glibc_SOURCES =
+try_glibc_LDADD = libmulti.a libglibc.a -lrt
+try_newlib_SOURCES =
+try_newlib_LDADD = libmulti.a libnewlib.a -lrt
+try_newlib_xscale_SOURCES =
+try_newlib_xscale_LDADD = libmulti.a libnewlib-xscale.a -lrt
+
+AM_CPPFLAGS = $(fpu_flags)
+AM_LDFLAGS = $(fpu_flags)
+
+endif
+
+# aarch64 specific
+if HOST_AARCH64
+
+libcortex_strings_la_SOURCES = \
+	src/aarch64/memchr.S \
+	src/aarch64/memcmp.S \
+	src/aarch64/memcpy.S \
+	src/aarch64/memmove.S \
+	src/aarch64/memset.S \
+	src/aarch64/strchr.S \
+	src/aarch64/strchrnul.S \
+	src/aarch64/strcmp.S \
+	src/aarch64/strcpy.S \
+	src/aarch64/strlen.S \
+	src/aarch64/strncmp.S \
+	src/aarch64/strnlen.S
+
+endif
+
+libcortex_strings_la_LDFLAGS = -version-info 1:0:0
+
+AM_CFLAGS = \
+	-std=gnu99 -Wall \
+	-fno-builtin -fno-stack-protector -U_FORTIFY_SOURCE \
+	$(AM_CPPFLAGS)
+
+if WITH_SUBMACHINE
+AM_CFLAGS += \
+	-mtune=$(submachine)
+endif
+
+EXTRA_DIST = \
+	tests/hp-timing.h \
+	tests/test-string.h \
+	tests/test-skeleton.c \
+	scripts/add-license.sh \
+	scripts/bench.py \
+	scripts/fixup.py \
+	scripts/libplot.py \
+	scripts/plot-align.py \
+	scripts/plot.py \
+	scripts/plot-sizes.py \
+	scripts/plot-top.py \
+	scripts/trim.sh \
+	autogen.sh
diff --git a/contrib/cortex-strings/README b/contrib/cortex-strings/README
new file mode 100644
index 000000000000..5e9e9d3f1d6f
--- /dev/null
+++ b/contrib/cortex-strings/README
@@ -0,0 +1,111 @@
+= Cortex-A String Routines =
+
+This package contains optimised string routines including memcpy(), memset(),
+strcpy(), strlen() for the ARM Cortex-A series of cores.
+
+Various implementations of these routines are provided, including generic
+implementations for ARMv7-A cores with/without Neon, Thumb2 implementations
+and generic implementations for cores supporting AArch64.
+
+== Getting started ==
+First configure and then install libcortex-strings.so.  To make other
+applications use this library, either add -lcortex-strings to the link
+command or use LD_PRELOAD to load the library into existing applications.
+
+Our intent is to get these routines into the common C libraries such
+as GLIBC, Bionic, and Newlib.  Your system may already include them!
+
+== Contents ==
+ * src/  contains the routines themselves
+ * tests/  contains the unit tests
+ * reference/  contains reference copies of other ARM-focused
+   implementations gathered from around the Internet
+ * benchmarks/  contains various benchmarks, tools, and scripts used to
+   check and report on the different implementations.
+
+The src directory contains different variants organised by the
+implementation they run on and optional features used.  For example:
+  * src/thumb-2  contains generic non-NEON routines for AArch32 (with Thumb-2).
+  * src/arm  contains tuned routines for Cortex-A class processors.
+  * src/aarch64  contains generic routines for AArch64.
+  * src/thumb  contains generic routines for armv6-M (with Thumb).
+
+== Reference versions ==
+reference/ contains versions collected from various popular Open
+Source libraries.  These have been modified for use in benchmarking.
+Please refer to the individual files for any licensing terms.
+
+The routines were collected from the following releases:
+ * EGLIBC 2.13
+ * Newlib 1.19.0
+ * Bionic android-2.3.5_r1
+
+== Licensing ==
+All Linaro-authored routines are under the modified BSD license:
+
+Copyright (c) 2011, Linaro Limited
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the Linaro nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+
+All ARM-authored routines are under the modified BSD license:
+
+Copyright (c) 2014 ARM Ltd
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the Linaro nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+All third party routines are under a GPL compatible license.
+
+== Notes and Limitations ==
+Some of the implementations have been collected from other
+projects and have a variety of licenses and copyright holders.
+
+== Style ==
+Assembly code attempts to follow the GLIBC coding convetions.  They
+are:
+ * Copyright headers in C style comment blocks
+ * Instructions indented with one tab
+ * Operands indented with one tab
+ * Text is wrapped at 70 characters
+ * End of line comments are fine
diff --git a/contrib/cortex-strings/autogen.sh b/contrib/cortex-strings/autogen.sh
new file mode 100755
index 000000000000..8e0591cc315a
--- /dev/null
+++ b/contrib/cortex-strings/autogen.sh
@@ -0,0 +1,69 @@
+#!/bin/sh
+#
+# autogen.sh glue for hplip
+#
+# HPLIP used to have five or so different autotools trees.  Upstream
+# has reduced it to two.  Still, this script is capable of cleaning
+# just about any possible mess of autoconf files.
+#
+# BE CAREFUL with trees that are not completely automake-generated,
+# this script deletes all Makefile.in files it can find.
+#
+# Requires: automake 1.9, autoconf 2.57+
+# Conflicts: autoconf 2.13
+set -e
+
+# Refresh GNU autotools toolchain.
+echo Cleaning autotools files...
+find -type d -name autom4te.cache -print0 | xargs -0 rm -rf \;
+find -type f \( -name missing -o -name install-sh -o -name mkinstalldirs \
+	-o -name depcomp -o -name ltmain.sh -o -name configure \
+	-o -name config.sub -o -name config.guess \
+	-o -name Makefile.in \) -print0 | xargs -0 rm -f
+
+echo Running autoreconf...
+autoreconf --force --install
+
+# For the Debian package build
+test -d debian && {
+	# link these in Debian builds
+	rm -f config.sub config.guess
+	ln -s /usr/share/misc/config.sub .
+	ln -s /usr/share/misc/config.guess .
+
+	# refresh list of executable scripts, to avoid possible breakage if
+	# upstream tarball does not include the file or if it is mispackaged
+	# for whatever reason.
+	[ "$1" = "updateexec" ] && {
+		echo Generating list of executable files...
+		rm -f debian/executable.files
+		find -type f -perm +111 ! -name '.*' -fprint debian/executable.files
+	}
+
+	# Remove any files in upstream tarball that we don't have in the Debian
+	# package (because diff cannot remove files)
+	version=`dpkg-parsechangelog | awk '/Version:/ { print $2 }' | sed -e 's/-[^-]\+$//'`
+	source=`dpkg-parsechangelog | awk '/Source:/ { print $2 }' | tr -d ' '`
+	if test -r ../${source}_${version}.orig.tar.gz ; then
+		echo Generating list of files that should be removed...
+		rm -f debian/deletable.files
+		touch debian/deletable.files
+		[ -e debian/tmp ] && rm -rf debian/tmp
+		mkdir debian/tmp
+		( cd debian/tmp ; tar -zxf ../../../${source}_${version}.orig.tar.gz )
+		find debian/tmp/ -type f ! -name '.*' -print0 | xargs -0 -ri echo '{}' | \
+		  while read -r i ; do
+			if test -e "${i}" ; then
+				filename=$(echo "${i}" | sed -e 's#.*debian/tmp/[^/]\+/##')
+				test -e "${filename}" || echo "${filename}" >>debian/deletable.files
+			fi
+		  done
+		rm -fr debian/tmp
+	else
+		echo Emptying list of files that should be deleted...
+		rm -f debian/deletable.files
+		touch debian/deletable.files
+	fi
+}
+
+exit 0
diff --git a/contrib/cortex-strings/benchmarks/dhry/dhry.h b/contrib/cortex-strings/benchmarks/dhry/dhry.h
new file mode 100644
index 000000000000..3010aecdd31f
--- /dev/null
+++ b/contrib/cortex-strings/benchmarks/dhry/dhry.h
@@ -0,0 +1,311 @@
+/*
+ **************************************************************************
+ *                       DHRYSTONE 2.1 BENCHMARK PC VERSION
+ **************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *                                                                            
+ *  Version:    C, Version 2.1
+ *                                                                            
+ *  File:       dhry.h (part 1 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *                      Siemens AG, AUT E 51
+ *                      Postfach 3220
+ *                      8520 Erlangen
+ *                      Germany (West)
+ *                              Phone:  [+49]-9131-7-20330
+ *                                      (8-17 Central European Time)
+ *                              Usenet: ..!mcsun!unido!estevax!weicker
+ *
+ *            Original Version (in Ada) published in
+ *            "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ *            pp. 1013 - 1030, together with the statistics
+ *            on which the distribution of statements etc. is based.
+ *
+ *            In this C version, the following C library functions are used:
+ *            - strcpy, strcmp (inside the measurement loop)
+ *            - printf, scanf (outside the measurement loop)
+ *            In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ *            are used for execution time measurement. For measurements
+ *            on other systems, these calls have to be changed.
+ *
+ *  Collection of Results:
+ *              Reinhold Weicker (address see above) and
+ *              
+ *              Rick Richardson
+ *              PC Research. Inc.
+ *              94 Apple Orchard Drive
+ *              Tinton Falls, NJ 07724
+ *                      Phone:  (201) 389-8963 (9-17 EST)               
+ *                      Usenet: ...!uunet!pcrat!rick
+ *
+ *      Please send results to Rick Richardson and/or Reinhold Weicker.
+ *      Complete information should be given on hardware and software used.
+ *      Hardware information includes: Machine type, CPU, type and size
+ *      of caches; for microprocessors: clock frequency, memory speed
+ *      (number of wait states).
+ *      Software information includes: Compiler (and runtime library)
+ *      manufacturer and version, compilation switches, OS version.
+ *      The Operating System version may give an indication about the
+ *      compiler; Dhrystone itself performs no OS calls in the measurement
+ *      loop.
+ *
+ *      The complete output generated by the program should be mailed
+ *      such that at least some checks for correctness can be made.
+ *
+ **************************************************************************
+ *
+ *  This version has changes made by Roy Longbottom to conform to a common
+ *  format for a series of standard benchmarks for PCs:
+ *
+ *  Running time greater than 5 seconds due to inaccuracy of the PC clock.
+ *
+ *  Automatic adjustment of run time, no manually inserted parameters.
+ *
+ *  Initial display of calibration times to confirm linearity.
+ *
+ *  Display of results within one screen (or at a slow speed as the test
+ *  progresses) so that it can be seen to have run successfully. 
+ *
+ *  Facilities to type in details of system used etc.
+ *
+ *  All results and details appended to a results file.
+ *
+ *
+ *  Roy Longbottom
+ *  101323.2241@compuserve.com
+ *
+ **************************************************************************
+ *
+ *  For details of history, changes, other defines, benchmark construction
+ *  statistics see official versions from ftp.nosc.mil/pub/aburto where
+ *  the latest table of results (dhry.tbl) are available. See also
+ *  netlib@ornl.gov
+ *
+ **************************************************************************
+ *
+ * Defines:     The following "Defines" are possible:
+ *              -DREG=register          (default: Not defined)
+ *                      As an approximation to what an average C programmer
+ *                      might do, the "register" storage class is applied
+ *                      (if enabled by -DREG=register)
+ *                      - for local variables, if they are used (dynamically)
+ *                        five or more times
+ *                      - for parameters if they are used (dynamically)
+ *                        six or more times
+ *                      Note that an optimal "register" strategy is
+ *                      compiler-dependent, and that "register" declarations
+ *                      do not necessarily lead to faster execution.
+ *              -DNOSTRUCTASSIGN        (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      assignment of structures.
+ *              -DNOENUMS               (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      enumeration types.
+ ***************************************************************************
+ *
+ *  Compilation model and measurement (IMPORTANT):
+ *
+ *  This C version of Dhrystone consists of three files:
+ *  - dhry.h (this file, containing global definitions and comments)
+ *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ *  The following "ground rules" apply for measurements:
+ *  - Separate compilation
+ *  - No procedure merging
+ *  - Otherwise, compiler optimizations are allowed but should be indicated
+ *  - Default results are those without register declarations
+ *  See the companion paper "Rationale for Dhrystone Version 2" for a more
+ *  detailed discussion of these ground rules.
+ *
+ *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ *  models ("small", "medium", "large" etc.) should be given if possible,
+ *  together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *                Examples of Pentium Results
+ *
+ * Dhrystone Benchmark  Version 2.1 (Language: C)
+ *
+ * Month run            4/1996
+ * PC model             Escom
+ * CPU                  Pentium
+ * Clock MHz            100
+ * Cache                256K
+ * Options              Neptune chipset
+ * OS/DOS               Windows 95
+ * Compiler             Watcom C/ C++ 10.5 Win386 
+ * OptLevel             -otexan -zp8 -fp5 -5r
+ * Run by               Roy Longbottom
+ * From                 UK
+ * Mail                 101323.2241@compuserve.com
+ * 
+ * Final values         (* implementation-dependent):
+ *
+ * Int_Glob:      O.K.  5
+ * Bool_Glob:     O.K.  1
+ * Ch_1_Glob:     O.K.  A
+ * Ch_2_Glob:     O.K.  B
+ * Arr_1_Glob[8]: O.K.  7
+ * Arr_2_Glob8/7: O.K.     1600010
+ * Ptr_Glob->  
+ *   Ptr_Comp:       *  98008
+ *   Discr:       O.K.  0
+ *   Enum_Comp:   O.K.  2
+ *   Int_Comp:    O.K.  17
+ *   Str_Comp:    O.K.  DHRYSTONE PROGRAM, SOME STRING
+ * Next_Ptr_Glob-> 
+ *   Ptr_Comp:       *  98008 same as above
+ *   Discr:       O.K.  0
+ *   Enum_Comp:   O.K.  1
+ *   Int_Comp:    O.K.  18
+ *   Str_Comp:    O.K.  DHRYSTONE PROGRAM, SOME STRING
+ * Int_1_Loc:     O.K.  5
+ * Int_2_Loc:     O.K.  13
+ * Int_3_Loc:     O.K.  7
+ * Enum_Loc:      O.K.  1
+ * Str_1_Loc:     O.K.  DHRYSTONE PROGRAM, 1'ST STRING
+ * Str_2_Loc:     O.K.  DHRYSTONE PROGRAM, 2'ND STRING
+ *
+ * Register option      Selected.
+ * 
+ * Microseconds 1 loop:          4.53
+ * Dhrystones / second:      220690
+ * VAX MIPS rating:            125.61
+ *
+ *
+ * Dhrystone Benchmark  Version 2.1 (Language: C)
+ *
+ * Month run            4/1996
+ * PC model             Escom
+ * CPU                  Pentium
+ * Clock MHz            100
+ * Cache                256K
+ * Options              Neptune chipset
+ * OS/DOS               Windows 95
+ * Compiler             Watcom C/ C++ 10.5 Win386 
+ * OptLevel                 No optimisation
+ * Run by               Roy Longbottom
+ * From                 UK
+ * Mail                 101323.2241@compuserve.com
+ * 
+ * Final values         (* implementation-dependent):
+ *
+ * Int_Glob:      O.K.  5
+ * Bool_Glob:     O.K.  1
+ * Ch_1_Glob:     O.K.  A
+ * Ch_2_Glob:     O.K.  B
+ * Arr_1_Glob[8]: O.K.  7
+ * Arr_2_Glob8/7: O.K.      320010
+ * Ptr_Glob->  
+ *   Ptr_Comp:       *  98004
+ *   Discr:       O.K.  0
+ *   Enum_Comp:   O.K.  2
+ *   Int_Comp:    O.K.  17
+ *   Str_Comp:    O.K.  DHRYSTONE PROGRAM, SOME STRING
+ * Next_Ptr_Glob-> 
+ *   Ptr_Comp:       *  98004 same as above
+ *   Discr:       O.K.  0
+ *   Enum_Comp:   O.K.  1
+ *   Int_Comp:    O.K.  18
+ *   Str_Comp:    O.K.  DHRYSTONE PROGRAM, SOME STRING
+ * Int_1_Loc:     O.K.  5
+ * Int_2_Loc:     O.K.  13
+ * Int_3_Loc:     O.K.  7
+ * Enum_Loc:      O.K.  1
+ * Str_1_Loc:     O.K.  DHRYSTONE PROGRAM, 1'ST STRING
+ * Str_2_Loc:     O.K.  DHRYSTONE PROGRAM, 2'ND STRING
+ *
+ * Register option      Not selected.
+ *
+ * Microseconds 1 loop:         20.06
+ * Dhrystones / second:       49844
+ * VAX MIPS rating:             28.37
+ *
+ **************************************************************************
+ */
+
+/* Compiler and system dependent definitions: */
+
+#ifndef TIME
+#define TIMES
+#endif
+                /* Use times(2) time function unless    */
+                /* explicitly defined otherwise         */
+
+#ifdef TIMES
+/* #include <sys/types.h> 
+   #include <sys/times.h> */
+                /* for "times" */
+#endif
+
+#define Mic_secs_Per_Second     1000000.0
+                /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef  NOSTRUCTASSIGN
+#define structassign(d, s)      memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s)      d = s
+#endif
+
+#ifdef  NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+  typedef int   Enumeration;
+#else
+  typedef       enum    {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+                Enumeration;
+#endif
+        /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+#include <string.h>
+
+                /* for strcpy, strcmp */
+
+#define Null 0 
+                /* Value of a Null pointer */
+#define true  1
+#define false 0
+
+typedef int     One_Thirty;
+typedef int     One_Fifty;
+typedef char    Capital_Letter;
+typedef int     Boolean;
+typedef char    Str_30 [31];
+typedef int     Arr_1_Dim [50];
+typedef int     Arr_2_Dim [50] [50];
+
+typedef struct record 
+    {
+    struct record *Ptr_Comp;
+    Enumeration    Discr;
+    union {
+          struct {
+                  Enumeration Enum_Comp;
+                  int         Int_Comp;
+                  char        Str_Comp [31];
+                  } var_1;
+          struct {
+                  Enumeration E_Comp_2;
+                  char        Str_2_Comp [31];
+                  } var_2;
+          struct {
+                  char        Ch_1_Comp;
+                  char        Ch_2_Comp;
+                  } var_3;
+          } variant;
+      } Rec_Type, *Rec_Pointer;
+
+
+
diff --git a/contrib/cortex-strings/benchmarks/dhry/dhry_1.c b/contrib/cortex-strings/benchmarks/dhry/dhry_1.c
new file mode 100644
index 000000000000..da272e4c4234
--- /dev/null
+++ b/contrib/cortex-strings/benchmarks/dhry/dhry_1.c
@@ -0,0 +1,778 @@
+/*
+ *************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry_1.c (part 2 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ *************************************************************************
+ */
+
+ #include <time.h>
+ #include <stdlib.h>
+ #include <stdio.h>
+ #include "dhry.h"
+ /*COMPILER COMPILER COMPILER COMPILER COMPILER COMPILER COMPILER*/
+               
+ #ifdef COW
+    #define compiler  "Watcom C/C++ 10.5 Win386"
+    #define options   "  -otexan -zp8 -5r -ms"
+ #endif
+ #ifdef CNW
+    #define compiler  "Watcom C/C++ 10.5 Win386"
+    #define options   "   No optimisation"
+ #endif
+ #ifdef COD
+    #define compiler  "Watcom C/C++ 10.5 Dos4GW"
+    #define options   "  -otexan -zp8 -5r -ms"
+ #endif
+ #ifdef CND
+    #define compiler  "Watcom C/C++ 10.5 Dos4GW"
+    #define options   "   No optimisation"
+ #endif
+ #ifdef CONT
+    #define compiler  "Watcom C/C++ 10.5 Win32NT"
+    #define options   "  -otexan -zp8 -5r -ms"
+ #endif
+ #ifdef CNNT
+    #define compiler  "Watcom C/C++ 10.5 Win32NT"
+    #define options   "   No optimisation"
+ #endif
+ #ifdef COO2
+    #define compiler  "Watcom C/C++ 10.5 OS/2-32"
+    #define options   "  -otexan -zp8 -5r -ms"
+ #endif
+ #ifdef CNO2
+    #define compiler  "Watcom C/C++ 10.5 OS/2-32"
+    #define options   "   No optimisation"
+ #endif
+ 
+
+/* Global Variables: */
+ 
+Rec_Pointer     Ptr_Glob,
+                 Next_Ptr_Glob;
+int             Int_Glob;
+ Boolean         Bool_Glob;
+ char            Ch_1_Glob,
+                 Ch_2_Glob;
+ int             Arr_1_Glob [50];
+ int             Arr_2_Glob [50] [50];
+ int             getinput = 1;
+
+ 
+ char Reg_Define[100] = "Register option      Selected.";
+ 
+ Enumeration Func_1 (Capital_Letter Ch_1_Par_Val,
+                                           Capital_Letter Ch_2_Par_Val);
+   /* 
+   forward declaration necessary since Enumeration may not simply be int
+   */
+ 
+ #ifndef ROPT
+ #define REG
+         /* REG becomes defined as empty */
+         /* i.e. no register variables   */
+ #else
+ #define REG register
+ #endif
+
+ void Proc_1 (REG Rec_Pointer Ptr_Val_Par);
+ void Proc_2 (One_Fifty *Int_Par_Ref);
+ void Proc_3 (Rec_Pointer *Ptr_Ref_Par);
+ void Proc_4 (); 
+ void Proc_5 ();
+ void Proc_6 (Enumeration Enum_Val_Par, Enumeration *Enum_Ref_Par);
+ void Proc_7 (One_Fifty Int_1_Par_Val, One_Fifty Int_2_Par_Val,
+                                              One_Fifty *Int_Par_Ref);
+ void Proc_8 (Arr_1_Dim Arr_1_Par_Ref, Arr_2_Dim Arr_2_Par_Ref,
+                               int Int_1_Par_Val, int Int_2_Par_Val);
+                               
+ Boolean Func_2 (Str_30 Str_1_Par_Ref, Str_30 Str_2_Par_Ref);
+
+ 
+ /* variables for time measurement: */
+ 
+ #define Too_Small_Time 2
+                 /* Measurements should last at least 2 seconds */
+ 
+ double          Begin_Time,
+                 End_Time,
+                 User_Time;
+ 
+ double          Microseconds,
+                 Dhrystones_Per_Second,
+                 Vax_Mips;
+ 
+ /* end of variables for time measurement */
+ 
+ 
+ void main (int argc, char *argv[])
+ /*****/
+ 
+   /* main program, corresponds to procedures        */
+   /* Main and Proc_0 in the Ada version             */
+ {
+   double   dtime();
+ 
+         One_Fifty   Int_1_Loc;
+   REG   One_Fifty   Int_2_Loc;
+         One_Fifty   Int_3_Loc;
+   REG   char        Ch_Index;
+         Enumeration Enum_Loc;
+         Str_30      Str_1_Loc;
+         Str_30      Str_2_Loc;
+   REG   int         Run_Index;
+   REG   int         Number_Of_Runs; 
+         int         endit, count = 10;
+         FILE        *Ap;
+         char        general[9][80] = {" "};
+ 
+   /* Initializations */
+    if (argc > 1)
+     {
+        switch (argv[1][0])
+         {
+             case 'N':
+                getinput = 0;
+                break;
+             case 'n':
+                getinput = 0;
+                break;
+         }
+      }
+ 
+   if ((Ap = fopen("Dhry.txt","a+")) == NULL)
+     {
+        printf("Can not open Dhry.txt\n\n");
+        printf("Press any key\n");
+        exit(1);
+     }
+
+/***********************************************************************
+ *         Change for compiler and optimisation used                   *
+ ***********************************************************************/
+ 
+   Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+   Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+ 
+   Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;
+   Ptr_Glob->Discr                       = Ident_1;
+   Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;
+   Ptr_Glob->variant.var_1.Int_Comp      = 40;
+   strcpy (Ptr_Glob->variant.var_1.Str_Comp, 
+           "DHRYSTONE PROGRAM, SOME STRING");       
+   strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+ 
+   Arr_2_Glob [8][7] = 10;
+         /* Was missing in published program. Without this statement,   */
+         /* Arr_2_Glob [8][7] would have an undefined value.            */
+         /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */
+         /* overflow may occur for this array element.                  */
+ 
+   printf ("\n");
+   printf ("Dhrystone Benchmark, Version 2.1 (Language: C or C++)\n");
+   printf ("\n");
+   
+   if (getinput == 0)
+    {
+        printf ("No run time input data\n\n");
+    }
+   else
+    {
+         printf ("With run time input data\n\n");
+    }
+   
+   printf ("Compiler        %s\n", compiler);
+   printf ("Optimisation    %s\n", options);
+   #ifdef ROPT
+       printf ("Register option selected\n\n");
+   #else
+       printf ("Register option not selected\n\n");
+       strcpy(Reg_Define, "Register option      Not selected.");
+   #endif
+
+ /*  
+   if (Reg)
+   {
+     printf ("Program compiled with 'register' attribute\n");
+     printf ("\n");
+   }
+   else
+   {
+     printf ("Program compiled without 'register' attribute\n");
+     printf ("\n");
+   }
+
+   printf ("Please give the number of runs through the benchmark: ");
+   {
+     int n;
+     scanf ("%d", &n);
+     Number_Of_Runs = n;
+   }   
+   printf ("\n"); 
+   printf ("Execution starts, %d runs through Dhrystone\n",
+                                                 Number_Of_Runs);
+ */
+
+   Number_Of_Runs = 5000;
+
+   do
+     {
+
+       Number_Of_Runs = Number_Of_Runs * 2;
+       count = count - 1;
+       Arr_2_Glob [8][7] = 10;
+        
+       /***************/
+       /* Start timer */
+       /***************/
+  
+       Begin_Time = dtime();
+   
+       for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+       {
+ 
+         Proc_5();
+         Proc_4();
+           /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+         Int_1_Loc = 2;
+         Int_2_Loc = 3;
+         strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+         Enum_Loc = Ident_2;
+         Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+           /* Bool_Glob == 1 */
+         while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */
+         {
+           Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+             /* Int_3_Loc == 7 */
+           Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+             /* Int_3_Loc == 7 */
+           Int_1_Loc += 1;
+         }   /* while */
+            /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+         Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+           /* Int_Glob == 5 */
+         Proc_1 (Ptr_Glob);
+         for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+                              /* loop body executed twice */
+         {
+           if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+               /* then, not executed */
+             {
+               Proc_6 (Ident_1, &Enum_Loc);
+               strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+               Int_2_Loc = Run_Index;
+               Int_Glob = Run_Index;
+             }
+         }
+           /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+         Int_2_Loc = Int_2_Loc * Int_1_Loc;
+         Int_1_Loc = Int_2_Loc / Int_3_Loc;
+         Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+           /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+         Proc_2 (&Int_1_Loc);
+           /* Int_1_Loc == 5 */
+ 
+       }   /* loop "for Run_Index" */
+ 
+       /**************/
+       /* Stop timer */
+       /**************/
+ 
+       End_Time = dtime();
+       User_Time = End_Time - Begin_Time;
+             
+       printf ("%12.0f runs %6.2f seconds \n",(double) Number_Of_Runs, User_Time);
+       if (User_Time > 5)
+         {
+             count = 0;
+         }
+       else
+         {
+             if (User_Time < 0.1)
+               {
+                  Number_Of_Runs = Number_Of_Runs * 5;
+               }
+         }
+     }   /* calibrate/run do while */
+   while (count >0);
+ 
+   printf ("\n");
+   printf ("Final values (* implementation-dependent):\n");
+   printf ("\n");
+   printf ("Int_Glob:      ");
+   if (Int_Glob == 5)  printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d  ", Int_Glob);
+      
+   printf ("Bool_Glob:     ");
+   if (Bool_Glob == 1) printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d\n", Bool_Glob);
+      
+   printf ("Ch_1_Glob:     ");
+   if (Ch_1_Glob == 'A')  printf ("O.K.  ");               
+   else                   printf ("WRONG ");
+   printf ("%c  ", Ch_1_Glob);
+         
+   printf ("Ch_2_Glob:     ");
+   if (Ch_2_Glob == 'B')  printf ("O.K.  ");
+   else                   printf ("WRONG ");
+   printf ("%c\n",  Ch_2_Glob);
+   
+   printf ("Arr_1_Glob[8]: ");
+   if (Arr_1_Glob[8] == 7)  printf ("O.K.  ");
+   else                     printf ("WRONG ");
+   printf ("%d  ", Arr_1_Glob[8]);
+            
+   printf ("Arr_2_Glob8/7: ");
+   if (Arr_2_Glob[8][7] == Number_Of_Runs + 10)
+                          printf ("O.K.  ");
+   else                   printf ("WRONG ");
+   printf ("%10d\n", Arr_2_Glob[8][7]);
+   
+   printf ("Ptr_Glob->            ");
+   printf ("  Ptr_Comp:       *    %d\n", (int) Ptr_Glob->Ptr_Comp);
+   
+   printf ("  Discr:       ");
+   if (Ptr_Glob->Discr == 0)  printf ("O.K.  ");
+   else                       printf ("WRONG ");
+   printf ("%d  ", Ptr_Glob->Discr);
+            
+   printf ("Enum_Comp:     ");
+   if (Ptr_Glob->variant.var_1.Enum_Comp == 2)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+      
+   printf ("  Int_Comp:    ");
+   if (Ptr_Glob->variant.var_1.Int_Comp == 17)  printf ("O.K.  ");
+   else                                         printf ("WRONG ");
+   printf ("%d ", Ptr_Glob->variant.var_1.Int_Comp);
+      
+   printf ("Str_Comp:      ");
+   if (strcmp(Ptr_Glob->variant.var_1.Str_Comp,
+                        "DHRYSTONE PROGRAM, SOME STRING") == 0)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");   
+   printf ("%s\n", Ptr_Glob->variant.var_1.Str_Comp);
+   
+   printf ("Next_Ptr_Glob->       "); 
+   printf ("  Ptr_Comp:       *    %d", (int) Next_Ptr_Glob->Ptr_Comp);
+   printf (" same as above\n");
+   
+   printf ("  Discr:       ");
+   if (Next_Ptr_Glob->Discr == 0)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d  ", Next_Ptr_Glob->Discr);
+   
+   printf ("Enum_Comp:     ");
+   if (Next_Ptr_Glob->variant.var_1.Enum_Comp == 1)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+   
+   printf ("  Int_Comp:    ");
+   if (Next_Ptr_Glob->variant.var_1.Int_Comp == 18)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d ", Next_Ptr_Glob->variant.var_1.Int_Comp);
+   
+   printf ("Str_Comp:      ");
+   if (strcmp(Next_Ptr_Glob->variant.var_1.Str_Comp,
+                        "DHRYSTONE PROGRAM, SOME STRING") == 0)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");   
+   printf ("%s\n", Next_Ptr_Glob->variant.var_1.Str_Comp);
+   
+   printf ("Int_1_Loc:     ");
+   if (Int_1_Loc == 5)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d  ", Int_1_Loc);
+      
+   printf ("Int_2_Loc:     ");
+   if (Int_2_Loc == 13)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d\n", Int_2_Loc);
+   
+   printf ("Int_3_Loc:     ");
+   if (Int_3_Loc == 7)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d  ", Int_3_Loc);
+   
+   printf ("Enum_Loc:      ");
+   if (Enum_Loc == 1)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");
+   printf ("%d\n", Enum_Loc);
+   
+   printf ("Str_1_Loc:                             ");
+   if (strcmp(Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING") == 0)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");   
+   printf ("%s\n", Str_1_Loc);
+   
+   printf ("Str_2_Loc:                             ");
+   if (strcmp(Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING") == 0)
+                        printf ("O.K.  ");
+   else                printf ("WRONG ");   
+   printf ("%s\n", Str_2_Loc);
+         
+   printf ("\n");
+    
+ 
+   if (User_Time < Too_Small_Time)
+   {
+     printf ("Measured time too small to obtain meaningful results\n");
+     printf ("Please increase number of runs\n");
+     printf ("\n");
+   }
+   else
+   {
+     Microseconds = User_Time * Mic_secs_Per_Second 
+                         / (double) Number_Of_Runs;
+     Dhrystones_Per_Second = (double) Number_Of_Runs / User_Time;
+     Vax_Mips = Dhrystones_Per_Second / 1757.0;
+ 
+     printf ("Microseconds for one run through Dhrystone: ");
+     printf ("%12.2lf \n", Microseconds);
+     printf ("Dhrystones per Second:                      ");
+     printf ("%10.0lf \n", Dhrystones_Per_Second);
+     printf ("VAX  MIPS rating =                          ");
+     printf ("%12.2lf \n",Vax_Mips);
+     printf ("\n");
+
+/************************************************************************
+ *             Type details of hardware, software etc.                  *
+ ************************************************************************/
+
+   if (getinput == 1)
+     {
+        printf ("Enter the following which will be added with results to file DHRY.TXT\n");
+        printf ("When submitting a number of results you need only provide details once\n");
+        printf ("but a cross reference such as an abbreviated CPU type would be useful.\n");    
+        printf ("You can kill (exit or close) the program now and no data will be added.\n\n");
+                
+        printf ("PC Supplier/model     ? ");
+        gets(general[1]);
+    
+        printf ("CPU chip              ? ");
+        gets(general[2]);
+    
+        printf ("Clock MHz             ? ");
+        gets(general[3]);
+     
+        printf ("Cache size            ? ");
+        gets(general[4]);
+     
+        printf ("Chipset & H/W options ? ");
+        gets(general[5]);
+      
+        printf ("OS/DOS version        ? ");
+        gets(general[6]);
+        
+        printf ("Your name             ? ");
+        gets(general[7]);
+     
+        printf ("Company/Location      ? ");
+        gets(general[8]);
+     
+        printf ("E-mail address        ? ");
+        gets(general[0]);
+     } 
+/************************************************************************
+ *                Add results to output file Dhry.txt                   *
+ ************************************************************************/
+   fprintf (Ap, "-------------------- -----------------------------------"        
+                         "\n");
+   fprintf (Ap, "Dhrystone Benchmark  Version 2.1 (Language: C++)\n\n");
+   fprintf (Ap, "PC model             %s\n", general[1]);
+   fprintf (Ap, "CPU                  %s\n", general[2]);
+   fprintf (Ap, "Clock MHz            %s\n", general[3]);
+   fprintf (Ap, "Cache                %s\n", general[4]);
+   fprintf (Ap, "Options              %s\n", general[5]);
+   fprintf (Ap, "OS/DOS               %s\n", general[6]);
+   fprintf (Ap, "Compiler             %s\n", compiler);
+   fprintf (Ap, "OptLevel             %s\n", options);
+   fprintf (Ap, "Run by               %s\n", general[7]);
+   fprintf (Ap, "From                 %s\n", general[8]);
+   fprintf (Ap, "Mail                 %s\n\n", general[0]);
+
+   fprintf (Ap, "Final values         (* implementation-dependent):\n");
+   fprintf (Ap, "\n");
+   fprintf (Ap, "Int_Glob:      ");
+   if (Int_Glob == 5)  fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Int_Glob);
+      
+   fprintf (Ap, "Bool_Glob:     ");
+   if (Bool_Glob == 1) fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Bool_Glob);
+      
+   fprintf (Ap, "Ch_1_Glob:     ");
+   if (Ch_1_Glob == 'A')  fprintf (Ap, "O.K.  ");               
+   else                   fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%c\n", Ch_1_Glob);
+         
+   fprintf (Ap, "Ch_2_Glob:     ");
+   if (Ch_2_Glob == 'B')  fprintf (Ap, "O.K.  ");
+   else                   fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%c\n",  Ch_2_Glob);
+   
+   fprintf (Ap, "Arr_1_Glob[8]: ");
+   if (Arr_1_Glob[8] == 7)  fprintf (Ap, "O.K.  ");
+   else                     fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Arr_1_Glob[8]);
+            
+   fprintf (Ap, "Arr_2_Glob8/7: ");
+   if (Arr_2_Glob[8][7] == Number_Of_Runs + 10)
+                          fprintf (Ap, "O.K.  ");
+   else                   fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%10d\n", Arr_2_Glob[8][7]);
+   
+   fprintf (Ap, "Ptr_Glob->  \n");
+   fprintf (Ap, "  Ptr_Comp:       *  %d\n", (int) Ptr_Glob->Ptr_Comp);
+   
+   fprintf (Ap, "  Discr:       ");
+   if (Ptr_Glob->Discr == 0)  fprintf (Ap, "O.K.  ");
+   else                       fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Ptr_Glob->Discr);
+            
+   fprintf (Ap, "  Enum_Comp:   ");
+   if (Ptr_Glob->variant.var_1.Enum_Comp == 2)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+      
+   fprintf (Ap, "  Int_Comp:    ");
+   if (Ptr_Glob->variant.var_1.Int_Comp == 17)  fprintf (Ap, "O.K.  ");
+   else                                         fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Ptr_Glob->variant.var_1.Int_Comp);
+      
+   fprintf (Ap, "  Str_Comp:    ");
+   if (strcmp(Ptr_Glob->variant.var_1.Str_Comp,
+                        "DHRYSTONE PROGRAM, SOME STRING") == 0)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");   
+   fprintf (Ap, "%s\n", Ptr_Glob->variant.var_1.Str_Comp);
+   
+   fprintf (Ap, "Next_Ptr_Glob-> \n"); 
+   fprintf (Ap, "  Ptr_Comp:       *  %d", (int) Next_Ptr_Glob->Ptr_Comp);
+   fprintf (Ap, " same as above\n");
+   
+   fprintf (Ap, "  Discr:       ");
+   if (Next_Ptr_Glob->Discr == 0)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Next_Ptr_Glob->Discr);
+   
+   fprintf (Ap, "  Enum_Comp:   ");
+   if (Next_Ptr_Glob->variant.var_1.Enum_Comp == 1)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+   
+   fprintf (Ap, "  Int_Comp:    ");
+   if (Next_Ptr_Glob->variant.var_1.Int_Comp == 18)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+   
+   fprintf (Ap, "  Str_Comp:    ");
+   if (strcmp(Next_Ptr_Glob->variant.var_1.Str_Comp,
+                        "DHRYSTONE PROGRAM, SOME STRING") == 0)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");   
+   fprintf (Ap, "%s\n", Next_Ptr_Glob->variant.var_1.Str_Comp);
+   
+   fprintf (Ap, "Int_1_Loc:     ");
+   if (Int_1_Loc == 5)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Int_1_Loc);
+      
+   fprintf (Ap, "Int_2_Loc:     ");
+   if (Int_2_Loc == 13)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Int_2_Loc);
+   
+   fprintf (Ap, "Int_3_Loc:     ");
+   if (Int_3_Loc == 7)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Int_3_Loc);
+   
+   fprintf (Ap, "Enum_Loc:      ");
+   if (Enum_Loc == 1)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");
+   fprintf (Ap, "%d\n", Enum_Loc);
+   
+   fprintf (Ap, "Str_1_Loc:     ");
+   if (strcmp(Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING") == 0)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");   
+   fprintf (Ap, "%s\n", Str_1_Loc);
+   
+   fprintf (Ap, "Str_2_Loc:     ");
+   if (strcmp(Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING") == 0)
+                        fprintf (Ap, "O.K.  ");
+   else                fprintf (Ap, "WRONG ");   
+   fprintf (Ap, "%s\n", Str_2_Loc);
+         
+   
+   fprintf (Ap, "\n");
+   fprintf(Ap,"%s\n",Reg_Define);
+   fprintf (Ap, "\n");
+   fprintf(Ap,"Microseconds 1 loop:  %12.2lf\n",Microseconds);
+   fprintf(Ap,"Dhrystones / second:  %10.0lf\n",Dhrystones_Per_Second);
+   fprintf(Ap,"VAX MIPS rating:      %12.2lf\n\n",Vax_Mips);
+   fclose(Ap);
+   }
+   
+    printf ("\n");
+    printf ("A new results file will have been created in the same directory as the\n");
+    printf (".EXE files if one did not already exist. If you made a mistake on input, \n");
+    printf ("you can use a text editor to correct it, delete the results or copy \n");
+    printf ("them to a different file name. If you intend to run multiple tests you\n");
+    printf ("you may wish to rename DHRY.TXT with a more informative title.\n\n");
+    printf ("Please submit feedback and results files as a posting in Section 12\n");
+    printf ("or to Roy_Longbottom@compuserve.com\n\n");
+
+    if (getinput == 1)
+     {
+        printf("Press any key to exit\n");
+        printf ("\nIf this is displayed you must close the window in the normal way\n");    
+     }
+ }
+ 
+ 
+ void Proc_1 (REG Rec_Pointer Ptr_Val_Par)
+ /******************/
+ 
+     /* executed once */
+ {
+   REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;  
+                                         /* == Ptr_Glob_Next */
+   /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */
+   /* corresponds to "rename" in Ada, "with" in Pascal           */
+   
+   structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+   Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+   Next_Record->variant.var_1.Int_Comp 
+         = Ptr_Val_Par->variant.var_1.Int_Comp;
+   Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+   Proc_3 (&Next_Record->Ptr_Comp);
+     /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp 
+                         == Ptr_Glob->Ptr_Comp */
+   if (Next_Record->Discr == Ident_1)
+     /* then, executed */
+   {
+     Next_Record->variant.var_1.Int_Comp = 6;
+     Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, 
+            &Next_Record->variant.var_1.Enum_Comp);
+     Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+     Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, 
+            &Next_Record->variant.var_1.Int_Comp);
+   }
+   else /* not executed */
+     structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+ } /* Proc_1 */
+ 
+ 
+ void Proc_2 (One_Fifty *Int_Par_Ref)
+ /******************/
+     /* executed once */
+     /* *Int_Par_Ref == 1, becomes 4 */
+ 
+ {
+   One_Fifty  Int_Loc;
+   Enumeration   Enum_Loc;
+ 
+   Int_Loc = *Int_Par_Ref + 10;
+   do /* executed once */
+     if (Ch_1_Glob == 'A')
+       /* then, executed */
+     {
+       Int_Loc -= 1;
+       *Int_Par_Ref = Int_Loc - Int_Glob;
+       Enum_Loc = Ident_1;
+     } /* if */
+   while (Enum_Loc != Ident_1); /* true */
+ } /* Proc_2 */
+ 
+ 
+ void Proc_3 (Rec_Pointer *Ptr_Ref_Par)
+ /******************/
+     /* executed once */
+     /* Ptr_Ref_Par becomes Ptr_Glob */
+ 
+ {
+   if (Ptr_Glob != Null)
+     /* then, executed */
+     *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+   Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+ } /* Proc_3 */
+ 
+ 
+void Proc_4 () /* without parameters */
+ /*******/
+     /* executed once */
+ {
+   Boolean Bool_Loc;
+ 
+   Bool_Loc = Ch_1_Glob == 'A';
+   Bool_Glob = Bool_Loc | Bool_Glob;
+   Ch_2_Glob = 'B';
+ } /* Proc_4 */
+ 
+ 
+ void Proc_5 () /* without parameters */
+ /*******/
+     /* executed once */
+ {
+   Ch_1_Glob = 'A';
+   Bool_Glob = false;
+ } /* Proc_5 */
+ 
+ 
+         /* Procedure for the assignment of structures,          */
+         /* if the C compiler doesn't support this feature       */
+ #ifdef  NOSTRUCTASSIGN
+ memcpy (d, s, l)
+ register char   *d;
+ register char   *s;
+ register int    l;
+ {
+         while (l--) *d++ = *s++;
+ }
+ #endif
+
+
+double dtime()
+{
+  
+  /* #include <ctype.h> */
+
+  #define HZ CLOCKS_PER_SEC
+  clock_t tnow;
+
+  double q;
+  tnow = clock();
+  q = (double)tnow / (double)HZ;     
+  return q;
+}
diff --git a/contrib/cortex-strings/benchmarks/dhry/dhry_2.c b/contrib/cortex-strings/benchmarks/dhry/dhry_2.c
new file mode 100644
index 000000000000..434945c99344
--- /dev/null
+++ b/contrib/cortex-strings/benchmarks/dhry/dhry_2.c
@@ -0,0 +1,186 @@
+ /*
+  *************************************************************************
+  *
+  *                   "DHRYSTONE" Benchmark Program
+  *                   -----------------------------
+  *
+  *  Version:    C, Version 2.1
+  *
+  *  File:       dhry_2.c (part 3 of 3)
+  *
+  *  Date:       May 25, 1988
+  *
+  *  Author:     Reinhold P. Weicker
+  *
+  *************************************************************************
+  */
+
+ #include "dhry.h"
+ 
+ #ifndef REG
+ #define REG
+         /* REG becomes defined as empty */
+         /* i.e. no register variables   */
+ #else
+ #define REG register
+ #endif
+ 
+ extern  int     Int_Glob;
+ extern  char    Ch_1_Glob;
+ 
+ Boolean Func_3 (Enumeration Enum_Par_Val); 
+ 
+ void Proc_6 (Enumeration Enum_Val_Par, Enumeration *Enum_Ref_Par)
+ /*********************************/
+     /* executed once */
+     /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+ 
+ {
+   *Enum_Ref_Par = Enum_Val_Par;
+   if (! Func_3 (Enum_Val_Par))
+     /* then, not executed */
+     *Enum_Ref_Par = Ident_4;
+   switch (Enum_Val_Par)
+   {
+     case Ident_1: 
+       *Enum_Ref_Par = Ident_1;
+       break;
+     case Ident_2: 
+       if (Int_Glob > 100)
+         /* then */
+       *Enum_Ref_Par = Ident_1;
+       else *Enum_Ref_Par = Ident_4;
+       break;
+     case Ident_3: /* executed */
+       *Enum_Ref_Par = Ident_2;
+       break;
+     case Ident_4: break;
+     case Ident_5: 
+       *Enum_Ref_Par = Ident_3;
+       break;
+   } /* switch */
+ } /* Proc_6 */
+ 
+ 
+ void Proc_7 (One_Fifty Int_1_Par_Val, One_Fifty Int_2_Par_Val,
+                                              One_Fifty *Int_Par_Ref)
+ /**********************************************/
+     /* executed three times                                      */
+     /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */
+     /*                  Int_Par_Ref becomes 7                    */
+     /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+     /*                  Int_Par_Ref becomes 17                   */
+     /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+     /*                  Int_Par_Ref becomes 18                   */
+
+ {
+   One_Fifty Int_Loc;
+ 
+   Int_Loc = Int_1_Par_Val + 2;
+   *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+ } /* Proc_7 */
+ 
+ 
+ void Proc_8 (Arr_1_Dim Arr_1_Par_Ref, Arr_2_Dim Arr_2_Par_Ref,
+                                  int Int_1_Par_Val, int Int_2_Par_Val)
+ /*********************************************************************/
+     /* executed once      */
+     /* Int_Par_Val_1 == 3 */
+     /* Int_Par_Val_2 == 7 */
+
+ {
+   REG One_Fifty Int_Index;
+   REG One_Fifty Int_Loc;
+ 
+   Int_Loc = Int_1_Par_Val + 5;
+   Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+   Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+   Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+   for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+     Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+   Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+   Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+   Int_Glob = 5;
+ } /* Proc_8 */
+ 
+ 
+ Enumeration Func_1 (Capital_Letter Ch_1_Par_Val,
+                                           Capital_Letter Ch_2_Par_Val)
+ /*************************************************/
+     /* executed three times                                         */
+     /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */
+     /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */
+     /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */
+ 
+ {
+   Capital_Letter        Ch_1_Loc;
+   Capital_Letter        Ch_2_Loc;
+ 
+   Ch_1_Loc = Ch_1_Par_Val;
+   Ch_2_Loc = Ch_1_Loc;
+   if (Ch_2_Loc != Ch_2_Par_Val)
+     /* then, executed */
+     return (Ident_1);
+   else  /* not executed */
+   {
+     Ch_1_Glob = Ch_1_Loc;
+     return (Ident_2);
+    }
+ } /* Func_1 */
+ 
+ 
+ Boolean Func_2 (Str_30 Str_1_Par_Ref, Str_30 Str_2_Par_Ref)
+ /*************************************************/
+     /* executed once */
+     /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+     /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+ 
+ {
+   REG One_Thirty        Int_Loc;
+       Capital_Letter    Ch_Loc;
+ 
+   Int_Loc = 2;
+   while (Int_Loc <= 2) /* loop body executed once */
+     if (Func_1 (Str_1_Par_Ref[Int_Loc],
+                 Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+       /* then, executed */
+     {
+       Ch_Loc = 'A';
+       Int_Loc += 1;
+     } /* if, while */
+   if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+     /* then, not executed */
+     Int_Loc = 7;
+   if (Ch_Loc == 'R')
+     /* then, not executed */
+     return (true);
+   else /* executed */
+   {
+     if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+       /* then, not executed */
+     {
+       Int_Loc += 7;
+       Int_Glob = Int_Loc;
+       return (true);
+     }
+     else /* executed */
+       return (false);
+   } /* if Ch_Loc */
+ } /* Func_2 */
+ 
+ 
+ Boolean Func_3 (Enumeration Enum_Par_Val)
+ /***************************/
+     /* executed once        */
+     /* Enum_Par_Val == Ident_3 */
+     
+ {
+   Enumeration Enum_Loc;
+ 
+   Enum_Loc = Enum_Par_Val;
+   if (Enum_Loc == Ident_3)
+     /* then, executed */
+     return (true);
+   else /* not executed */
+     return (false);
+ } /* Func_3 */
diff --git a/contrib/cortex-strings/benchmarks/multi/harness.c b/contrib/cortex-strings/benchmarks/multi/harness.c
new file mode 100644
index 000000000000..257a308e6b4e
--- /dev/null
+++ b/contrib/cortex-strings/benchmarks/multi/harness.c
@@ -0,0 +1,407 @@
+/*
+ * Copyright (c) 2011, Linaro Limited
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the Linaro nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ */
+
+/** A simple harness that times how long a string function takes to
+ * run.
+ */
+
+/* PENDING: Add EPL */
+
+#include <string.h>
+#include <time.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <assert.h>
+#include <unistd.h>
+#include <errno.h>
+
+#define NUM_ELEMS(_x) (sizeof(_x) / sizeof((_x)[0]))
+
+#ifndef VERSION
+#define VERSION "(unknown version)"
+#endif
+
+/** Make sure a function is called by using the return value */
+#define SPOIL(_x)  volatile long x = (long)(_x); (void)x
+
+/** Type of functions that can be tested */
+typedef void (*stub_t)(void *dest, void *src, size_t n);
+
+/** Meta data about one test */
+struct test
+{
+  /** Test name */
+  const char *name;
+  /** Function to test */
+  stub_t stub;
+};
+
+/** Flush the cache by reading a chunk of memory */
+static void empty(volatile char *against)
+{
+  /* We know that there's a 16 k cache with 64 byte lines giving
+     a total of 256 lines.  Read randomly from 256*5 places should
+     flush everything */
+  int offset = (1024 - 256)*1024;
+
+  for (int i = offset; i < offset + 16*1024*3; i += 64)
+    {
+      against[i];
+    }
+}
+
+/** Stub that does nothing.  Used for calibrating */
+static void xbounce(void *dest, void *src, size_t n)
+{
+  SPOIL(0);
+}
+
+/** Stub that calls memcpy */
+static void xmemcpy(void *dest, void *src, size_t n)
+{
+  SPOIL(memcpy(dest, src, n));
+}
+
+/** Stub that calls memset */
+static void xmemset(void *dest, void *src, size_t n)
+{
+  SPOIL(memset(dest, 0, n));
+}
+
+/** Stub that calls memcmp */
+static void xmemcmp(void *dest, void *src, size_t n)
+{
+  SPOIL(memcmp(dest, src, n));
+}
+
+/** Stub that calls strcpy */
+static void xstrcpy(void *dest, void *src, size_t n)
+{
+  SPOIL(strcpy(dest, src));
+}
+
+/** Stub that calls strlen */
+static void xstrlen(void *dest, void *src, size_t n)
+{
+  SPOIL(strlen(dest));
+}
+
+/** Stub that calls strcmp */
+static void xstrcmp(void *dest, void *src, size_t n)
+{
+  SPOIL(strcmp(dest, src));
+}
+
+/** Stub that calls strchr */
+static void xstrchr(void *dest, void *src, size_t n)
+{
+  /* Put the character at the end of the string and before the null */
+  ((char *)src)[n-1] = 32;
+  SPOIL(strchr(src, 32));
+}
+
+/** Stub that calls memchr */
+static void xmemchr(void *dest, void *src, size_t n)
+{
+  /* Put the character at the end of the block */
+  ((char *)src)[n-1] = 32;
+  SPOIL(memchr(src, 32, n));
+}
+
+/** All functions that can be tested */
+static const struct test tests[] =
+  {
+    { "bounce", xbounce },
+    { "memchr", xmemchr },
+    { "memcpy", xmemcpy },
+    { "memset", xmemset },
+    { "memcmp", xmemcmp },
+    { "strchr", xstrchr },
+    { "strcmp", xstrcmp },
+    { "strcpy", xstrcpy },
+    { "strlen", xstrlen },
+    { NULL }
+  };
+
+/** Show basic usage */
+static void usage(const char* name)
+{
+  printf("%s %s: run a string related benchmark.\n"
+         "usage: %s [-c block-size] [-l loop-count] [-a alignment|src_alignment:dst_alignment] [-f] [-t test-name] [-r run-id]\n"
+         , name, VERSION, name);
+
+  printf("Tests:");
+
+  for (const struct test *ptest = tests; ptest->name != NULL; ptest++)
+    {
+      printf(" %s", ptest->name);
+    }
+
+  printf("\n");
+
+  exit(-1);
+}
+
+/** Find the test by name */
+static const struct test *find_test(const char *name)
+{
+  if (name == NULL)
+    {
+      return tests + 0;
+    }
+  else
+    {
+      for (const struct test *p = tests; p->name != NULL; p++)
+	{
+          if (strcmp(p->name, name) == 0)
+	    {
+              return p;
+	    }
+	}
+    }
+
+  return NULL;
+}
+
+#define MIN_BUFFER_SIZE 1024*1024
+#define MAX_ALIGNMENT	256
+
+/** Take a pointer and ensure that the lower bits == alignment */
+static char *realign(char *p, int alignment)
+{
+  uintptr_t pp = (uintptr_t)p;
+  pp = (pp + (MAX_ALIGNMENT - 1)) & ~(MAX_ALIGNMENT - 1);
+  pp += alignment;
+
+  return (char *)pp;
+}
+
+static int parse_int_arg(const char *arg, const char *exe_name)
+{
+  long int ret;
+
+  errno = 0;
+  ret = strtol(arg, NULL, 0);
+
+  if (errno)
+    {
+      usage(exe_name);
+    }
+
+  return (int)ret;
+}
+
+static void parse_alignment_arg(const char *arg, const char *exe_name,
+				int *src_alignment, int *dst_alignment)
+{
+  long int ret;
+  char *endptr;
+
+  errno = 0;
+  ret = strtol(arg, &endptr, 0);
+
+  if (errno)
+    {
+      usage(exe_name);
+    }
+
+  *src_alignment = (int)ret;
+
+  if (ret > 256 || ret < 1)
+    {
+      printf("Alignment should be in the range [1, 256].\n");
+      usage(exe_name);
+    }
+
+  if (ret == 256)
+    ret = 0;
+
+  if (endptr && *endptr == ':')
+    {
+      errno = 0;
+      ret = strtol(endptr + 1, NULL, 0);
+
+      if (errno)
+	{
+	  usage(exe_name);
+	}
+
+      if (ret > 256 || ret < 1)
+	{
+	  printf("Alignment should be in the range [1, 256].\n");
+	  usage(exe_name);
+	}
+
+      if (ret == 256)
+	ret = 0;
+    }
+
+  *dst_alignment = (int)ret;
+}
+
+/** Setup and run a test */
+int main(int argc, char **argv)
+{
+  /* Size of src and dest buffers */
+  size_t buffer_size = MIN_BUFFER_SIZE;
+
+  /* Number of bytes per call */
+  int count = 31;
+  /* Number of times to run */
+  int loops = 10000000;
+  /* True to flush the cache each time */
+  int flush = 0;
+  /* Name of the test */
+  const char *name = NULL;
+  /* Alignment of buffers */
+  int src_alignment = 8;
+  int dst_alignment = 8;
+  /* Name of the run */
+  const char *run_id = "0";
+
+  int opt;
+
+  while ((opt = getopt(argc, argv, "c:l:ft:r:hva:")) > 0)
+    {
+      switch (opt)
+	{
+	case 'c':
+          count = parse_int_arg(optarg, argv[0]);
+          break;
+	case 'l':
+          loops = parse_int_arg(optarg, argv[0]);
+          break;
+	case 'a':
+          parse_alignment_arg(optarg, argv[0], &src_alignment, &dst_alignment);
+          break;
+	case 'f':
+          flush = 1;
+          break;
+	case 't':
+          name = strdup(optarg);
+          break;
+	case 'r':
+          run_id = strdup(optarg);
+          break;
+	case 'h':
+          usage(argv[0]);
+          break;
+	default:
+          usage(argv[0]);
+          break;
+	}
+    }
+
+  /* Find the test by name */
+  const struct test *ptest = find_test(name);
+
+  if (ptest == NULL)
+    {
+      usage(argv[0]);
+    }
+
+  if (count + MAX_ALIGNMENT * 2 > MIN_BUFFER_SIZE)
+    {
+      buffer_size = count + MAX_ALIGNMENT * 2;
+    }
+
+  /* Buffers to read and write from */
+  char *src = malloc(buffer_size);
+  char *dest = malloc(buffer_size);
+
+  assert(src != NULL && dest != NULL);
+
+  src = realign(src, src_alignment);
+  dest = realign(dest, dst_alignment);
+
+  /* Fill the buffer with non-zero, reproducable random data */
+  srandom(1539);
+
+  for (int i = 0; i < buffer_size; i++)
+    {
+      src[i] = (char)random() | 1;
+      dest[i] = src[i];
+    }
+
+  /* Make sure the buffers are null terminated for any string tests */
+  src[count] = 0;
+  dest[count] = 0;
+
+  struct timespec start, end;
+  int err = clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start);
+  assert(err == 0);
+
+  /* Preload */
+  stub_t stub = ptest->stub;
+
+  /* Run two variants to reduce the cost of testing for the flush */
+  if (flush == 0)
+    {
+      for (int i = 0; i < loops; i++)
+	{
+	  (*stub)(dest, src, count);
+	}
+    }
+  else
+    {
+      for (int i = 0; i < loops; i++)
+	{
+	  (*stub)(dest, src, count);
+	  empty(dest);
+	}
+    }
+
+  err = clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &end);
+  assert(err == 0);
+
+  /* Drop any leading path and pull the variant name out of the executable */
+  char *variant = strrchr(argv[0], '/');
+
+  if (variant == NULL)
+    {
+      variant = argv[0];
+    }
+
+  variant = strstr(variant, "try-");
+  assert(variant != NULL);
+
+  double elapsed = (end.tv_sec - start.tv_sec) + (end.tv_nsec - start.tv_nsec) * 1e-9;
+  /* Estimate the bounce time.  Measured on a Panda. */
+  double bounced = 0.448730 * loops / 50000000;
+
+  /* Dump both machine and human readable versions */
+  printf("%s:%s:%u:%u:%d:%d:%s:%.6f: took %.6f s for %u calls to %s of %u bytes.  ~%.3f MB/s corrected.\n", 
+         variant + 4, ptest->name,
+	 count, loops, src_alignment, dst_alignment, run_id,
+	 elapsed,
+         elapsed, loops, ptest->name, count,
+         (double)loops*count/(elapsed - bounced)/(1024*1024));
+
+  return 0;
+}
diff --git a/contrib/cortex-strings/configure.ac b/contrib/cortex-strings/configure.ac
new file mode 100644
index 000000000000..56f1ced94299
--- /dev/null
+++ b/contrib/cortex-strings/configure.ac
@@ -0,0 +1,88 @@
+# Copyright (c) 2011-2012, Linaro Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of the Linaro nor the
+#       names of its contributors may be used to endorse or promote products
+#       derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+AC_INIT(cortex-strings, 1.1-2012.06~dev)
+AM_INIT_AUTOMAKE(foreign subdir-objects color-tests dist-bzip2)
+AC_CONFIG_HEADERS([config.h])
+AC_CONFIG_FILES(Makefile)
+AC_CANONICAL_HOST
+AM_PROG_AS
+AC_PROG_CC
+AC_PROG_LIBTOOL
+
+default_submachine=
+
+case $host in
+aarch64*-*-*)
+  arch=aarch64
+  ;;
+arm*-*-*)
+  arch=aarch32
+  default_submachine=cortex-a9
+  ;;
+x86_64-*-*-*)
+  arch=generic
+  ;;
+*)
+  AC_MSG_ERROR([unknown architecture $host])
+  ;;
+esac
+
+AM_CONDITIONAL([HOST_AARCH32], [test x$arch = xaarch32])
+AM_CONDITIONAL([HOST_AARCH64], [test x$arch = xaarch64])
+AM_CONDITIONAL([HOST_GENERIC], [test x$arch = xgeneric])
+
+AC_ARG_WITH([cpu],
+	    AS_HELP_STRING([--with-cpu=CPU],
+                           [select code for CPU variant @<:@default=cortex-a9@:>@]]),
+	    [dnl
+  case "$withval" in
+  yes|'') AC_MSG_ERROR([--with-cpu requires an argument]) ;;
+  no) ;;
+  *) submachine="$withval" ;;
+  esac
+],
+[submachine=$default_submachine])
+
+AC_SUBST(submachine)
+AM_CONDITIONAL([WITH_SUBMACHINE], [test x$submachine != x])
+
+AC_ARG_WITH([neon],
+            AC_HELP_STRING([--with-neon],
+                           [include NEON specific routines @<:@default=yes@:>@]),
+	    [with_neon=$withval],
+	    [with_neon=yes])
+AC_SUBST(with_neon)
+AM_CONDITIONAL(WITH_NEON, test x$with_neon = xyes)
+
+AC_ARG_WITH([vfp],
+            AC_HELP_STRING([--with-vfp],
+                           [include VFP specific routines @<:@default=yes@:>@]),
+	    [with_vfp=$withval],
+	    [with_vfp=yes])
+AC_SUBST(with_vfp)
+AM_CONDITIONAL(WITH_VFP, test x$with_vfp = xyes)
+
+AC_OUTPUT
diff --git a/contrib/cortex-strings/scripts/add-license.sh b/contrib/cortex-strings/scripts/add-license.sh
new file mode 100755
index 000000000000..8a6c0710fbbe
--- /dev/null
+++ b/contrib/cortex-strings/scripts/add-license.sh
@@ -0,0 +1,79 @@
+#!/bin/bash
+#
+# Add the modified BSD license to a file
+#
+
+f=`mktemp -d`
+trap "rm -rf $f" EXIT
+
+year=`date +%Y`
+cat > $f/original <<EOF
+Copyright (c) $year, Linaro Limited
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the Linaro nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+EOF
+
+# Translate it to C style
+echo "/*" > $f/c
+sed -r 's/(.*)/ * \1/' $f/original | sed -r 's/ +$//' >> $f/c
+echo " */" >> $f/c
+echo >> $f/c
+
+# ...and shell style
+sed -r 's/(.*)/# \1/' $f/original | sed -r 's/ +$//' >> $f/shell
+echo '#' >> $f/shell
+echo >> $f/shell
+
+for name in $@; do
+    if grep -q Copyright $name; then
+	echo $name already has some type of copyright
+	continue
+    fi
+
+    case $name in
+	# These files don't have an explicit license
+        *autogen.sh*)
+	    continue;;
+	*reference/newlib/*)
+	    continue;;
+	*reference/newlib-xscale/*)
+	    continue;;
+	*/dhry/*)
+	    continue;;
+
+	*.c)
+	    src=$f/c
+	    ;;
+	*.sh|*.am|*.ac)
+	    src=$f/shell
+	    ;;
+	*)
+	    echo Unrecognied extension on $name
+	    continue
+    esac
+
+    cat $src $name > $f/next
+    mv $f/next $name
+    echo Updated $name
+done
diff --git a/contrib/cortex-strings/scripts/bench.py b/contrib/cortex-strings/scripts/bench.py
new file mode 100644
index 000000000000..476a5322a747
--- /dev/null
+++ b/contrib/cortex-strings/scripts/bench.py
@@ -0,0 +1,175 @@
+#!/usr/bin/env python
+
+"""Simple harness that benchmarks different variants of the routines,
+caches the results, and emits all of the records at the end.
+
+Results are generated for different values of:
+ * Source
+ * Routine
+ * Length
+ * Alignment
+"""
+
+import argparse
+import subprocess
+import math
+import sys
+
+# Prefix to the executables
+build = '../build/try-'
+
+ALL = 'memchr memcmp memcpy memset strchr strcmp strcpy strlen'
+
+HAS = {
+    'this': 'bounce memchr memcpy memset strchr strcmp strcpy strlen',
+    'bionic-a9': 'memcmp memcpy memset strcmp strcpy strlen',
+    'bionic-a15': 'memcmp memcpy memset strcmp strcpy strlen',
+    'bionic-c': ALL,
+    'csl': 'memcpy memset',
+    'glibc': 'memcpy memset strchr strlen',
+    'glibc-c': ALL,
+    'newlib': 'memcpy strcmp strcpy strlen',
+    'newlib-c': ALL,
+    'newlib-xscale': 'memchr memcpy memset strchr strcmp strcpy strlen',
+    'plain': 'memset memcpy strcmp strcpy',
+}
+
+BOUNCE_ALIGNMENTS = ['1']
+SINGLE_BUFFER_ALIGNMENTS = ['1', '2', '4', '8', '16', '32']
+DUAL_BUFFER_ALIGNMENTS = ['1:32', '2:32', '4:32', '8:32', '16:32', '32:32']
+
+ALIGNMENTS = {
+    'bounce': BOUNCE_ALIGNMENTS,
+    'memchr': SINGLE_BUFFER_ALIGNMENTS,
+    'memset': SINGLE_BUFFER_ALIGNMENTS,
+    'strchr': SINGLE_BUFFER_ALIGNMENTS,
+    'strlen': SINGLE_BUFFER_ALIGNMENTS,
+    'memcmp': DUAL_BUFFER_ALIGNMENTS,
+    'memcpy': DUAL_BUFFER_ALIGNMENTS,
+    'strcmp': DUAL_BUFFER_ALIGNMENTS,
+    'strcpy': DUAL_BUFFER_ALIGNMENTS,
+}
+
+VARIANTS = sorted(HAS.keys())
+FUNCTIONS = sorted(ALIGNMENTS.keys())
+
+NUM_RUNS = 5
+
+def run(cache, variant, function, bytes, loops, alignment, run_id, quiet=False):
+    """Perform a single run, exercising the cache as appropriate."""
+    key = ':'.join('%s' % x for x in (variant, function, bytes, loops, alignment, run_id))
+
+    if key in cache:
+        got = cache[key]
+    else:
+        xbuild = build
+        cmd = '%(xbuild)s%(variant)s -t %(function)s -c %(bytes)s -l %(loops)s -a %(alignment)s -r %(run_id)s' % locals()
+
+        try:
+            got = subprocess.check_output(cmd.split()).strip()
+        except OSError, ex:
+            assert False, 'Error %s while running %s' % (ex, cmd)
+
+    parts = got.split(':')
+    took = float(parts[7])
+
+    cache[key] = got
+
+    if not quiet:
+        print got
+        sys.stdout.flush()
+
+    return took
+
+def run_many(cache, variants, bytes, all_functions):
+    # We want the data to come out in a useful order.  So fix an
+    # alignment and function, and do all sizes for a variant first
+    bytes = sorted(bytes)
+    mid = bytes[int(len(bytes)/1.5)]
+
+    if not all_functions:
+        # Use the ordering in 'this' as the default
+        all_functions = HAS['this'].split()
+
+        # Find all other functions
+        for functions in HAS.values():
+            for function in functions.split():
+                if function not in all_functions:
+                    all_functions.append(function)
+
+    for function in all_functions:
+        for alignment in ALIGNMENTS[function]:
+            for variant in variants:
+                if function not in HAS[variant].split():
+                    continue
+
+                # Run a tracer through and see how long it takes and
+                # adjust the number of loops based on that.  Not great
+                # for memchr() and similar which are O(n), but it will
+                # do
+                f = 50000000
+                want = 5.0
+
+                loops = int(f / math.sqrt(max(1, mid)))
+                took = run(cache, variant, function, mid, loops, alignment, 0,
+                           quiet=True)
+                # Keep it reasonable for silly routines like bounce
+                factor = min(20, max(0.05, want/took))
+                f = f * factor
+                
+                # Round f to a few significant figures
+                scale = 10**int(math.log10(f) - 1)
+                f = scale*int(f/scale)
+
+                for b in sorted(bytes):
+                    # Figure out the number of loops to give a roughly consistent run
+                    loops = int(f / math.sqrt(max(1, b)))
+                    for run_id in range(0, NUM_RUNS):
+                        run(cache, variant, function, b, loops, alignment,
+                            run_id)
+
+def run_top(cache):
+    parser = argparse.ArgumentParser()
+    parser.add_argument("-v", "--variants", nargs="+", help="library variant to run (run all if not specified)", default = VARIANTS, choices = VARIANTS)
+    parser.add_argument("-f", "--functions", nargs="+", help="function to run (run all if not specified)", default = FUNCTIONS, choices = FUNCTIONS)
+    parser.add_argument("-l", "--limit", type=int, help="upper limit to test to (in bytes)", default = 512*1024)
+    args = parser.parse_args()
+
+    # Test all powers of 2
+    step1 = 2.0
+    # Test intermediate powers of 1.4
+    step2 = 1.4
+    
+    bytes = []
+    
+    for step in [step1, step2]:
+        if step:
+            # Figure out how many steps get us up to the top
+            steps = int(round(math.log(args.limit) / math.log(step)))
+            bytes.extend([int(step**x) for x in range(0, steps+1)])
+
+    run_many(cache, args.variants, bytes, args.functions)
+
+def main():
+    cachename = 'cache.txt'
+
+    cache = {}
+
+    try:
+        with open(cachename) as f:
+            for line in f:
+                line = line.strip()
+                parts = line.split(':')
+                cache[':'.join(parts[:7])] = line
+    except:
+        pass
+
+    try:
+        run_top(cache)
+    finally:
+        with open(cachename, 'w') as f:
+            for line in sorted(cache.values()):
+                print >> f, line
+
+if __name__ == '__main__':
+    main()
diff --git a/contrib/cortex-strings/scripts/fixup.py b/contrib/cortex-strings/scripts/fixup.py
new file mode 100644
index 000000000000..003783a49838
--- /dev/null
+++ b/contrib/cortex-strings/scripts/fixup.py
@@ -0,0 +1,27 @@
+"""Simple script that enables target specific blocks based on the first argument.
+
+Matches comment blocks like this:
+
+/* For Foo: abc
+def
+*/
+
+and de-comments them giving:
+abc
+def
+"""
+import re
+import sys
+
+def main():
+    key = sys.argv[1]
+    expr = re.compile(r'/\* For %s:\s([^*]+)\*/' % key, re.M)
+
+    for arg in sys.argv[2:]:
+        with open(arg) as f:
+            body = f.read()
+        with open(arg, 'w') as f:
+            f.write(expr.sub(r'\1', body))
+
+if __name__ == '__main__':
+    main()
diff --git a/contrib/cortex-strings/scripts/libplot.py b/contrib/cortex-strings/scripts/libplot.py
new file mode 100644
index 000000000000..034ffd331a59
--- /dev/null
+++ b/contrib/cortex-strings/scripts/libplot.py
@@ -0,0 +1,78 @@
+"""Shared routines for the plotters."""
+
+import fileinput
+import collections
+
+Record = collections.namedtuple('Record', 'variant function bytes loops src_alignment dst_alignment run_id elapsed rest')
+
+
+def make_colours():
+    return iter('m b g r c y k pink orange brown grey'.split())
+
+def parse_value(v):
+    """Turn text into a primitive"""
+    try:
+        if '.' in v:
+            return float(v)
+        else:
+            return int(v)
+    except ValueError:
+        return v
+
+def create_column_tuple(record, names):
+    cols = [getattr(record, name) for name in names]
+    return tuple(cols)
+
+def unique(records, name, prefer=''):
+    """Return the unique values of a column in the records"""
+    if type(name) == tuple:
+        values = list(set(create_column_tuple(x, name) for x in records))
+    else:
+        values = list(set(getattr(x, name) for x in records))
+
+    if not values:
+        return values
+    elif type(values[0]) == str:
+        return sorted(values, key=lambda x: '%-06d|%s' % (-prefer.find(x), x))
+    else:
+        return sorted(values)
+
+def alignments_equal(alignments):
+    for alignment in alignments:
+        if alignment[0] != alignment[1]:
+            return False
+    return True
+
+def parse_row(line):
+    return Record(*[parse_value(y) for y in line.split(':')])
+
+def parse():
+    """Parse a record file into named tuples, correcting for loop
+    overhead along the way.
+    """
+    records = [parse_row(x) for x in fileinput.input()]
+
+    # Pull out any bounce values
+    costs = {}
+
+    for record in [x for x in records if x.function=='bounce']:
+        costs[(record.bytes, record.loops)] = record.elapsed
+
+    # Fix up all of the records for cost
+    out = []
+
+    for record in records:
+        if record.function == 'bounce':
+            continue
+
+        cost = costs.get((record.bytes, record.loops), None)
+
+        if not cost:
+            out.append(record)
+        else:
+            # Unfortunately you can't update a namedtuple...
+            values = list(record)
+            values[-2] -= cost
+            out.append(Record(*values))
+
+    return out
diff --git a/contrib/cortex-strings/scripts/plot-align.py b/contrib/cortex-strings/scripts/plot-align.py
new file mode 100644
index 000000000000..524aa20a6c12
--- /dev/null
+++ b/contrib/cortex-strings/scripts/plot-align.py
@@ -0,0 +1,67 @@
+#!/usr/bin/env python
+
+"""Plot the performance of different variants of one routine versus alignment.
+"""
+
+import libplot
+
+import pylab
+
+
+def plot(records, bytes, function):
+    records = [x for x in records if x.bytes==bytes and x.function==function]
+
+    variants = libplot.unique(records, 'variant', prefer='this')
+    alignments = libplot.unique(records, ('src_alignment', 'dst_alignment'))
+
+    X = pylab.arange(len(alignments))
+    width = 1.0/(len(variants)+1)
+
+    colours = libplot.make_colours()
+
+    pylab.figure(1).set_size_inches((16, 12))
+    pylab.clf()
+
+    for i, variant in enumerate(variants):
+        heights = []
+
+        for alignment in alignments:
+            matches = [x for x in records if x.variant==variant and x.src_alignment==alignment[0] and x.dst_alignment==alignment[1]]
+
+            if matches:
+                vals = [match.bytes*match.loops/match.elapsed/(1024*1024) for
+                        match in matches]
+                mean = sum(vals)/len(vals)
+                heights.append(mean)
+            else:
+                heights.append(0)
+
+        pylab.bar(X+i*width, heights, width, color=colours.next(), label=variant)
+
+
+    axes = pylab.axes()
+    if libplot.alignments_equal(alignments):
+        alignment_labels = ["%s" % x[0] for x in alignments]
+    else:
+        alignment_labels = ["%s:%s" % (x[0], x[1]) for x in alignments]
+    axes.set_xticklabels(alignment_labels)
+    axes.set_xticks(X + 0.5)
+
+    pylab.title('Performance of different variants of %(function)s for %(bytes)d byte blocks' % locals())
+    pylab.xlabel('Alignment')
+    pylab.ylabel('Rate (MB/s)')
+    pylab.legend(loc='lower right', ncol=3)
+    pylab.grid()
+    pylab.savefig('alignment-%(function)s-%(bytes)d.png' % locals(), dpi=72)
+
+def main():
+    records = libplot.parse()
+
+    for function in libplot.unique(records, 'function'):
+        for bytes in libplot.unique(records, 'bytes'):
+            plot(records, bytes, function)
+
+    pylab.show()
+
+if __name__ == '__main__':
+    main()
diff --git a/contrib/cortex-strings/scripts/plot-sizes.py b/contrib/cortex-strings/scripts/plot-sizes.py
new file mode 100644
index 000000000000..26a22bc4d6ef
--- /dev/null
+++ b/contrib/cortex-strings/scripts/plot-sizes.py
@@ -0,0 +1,120 @@
+#!/usr/bin/env python
+
+"""Plot the performance for different block sizes of one function across
+variants.
+"""
+
+import libplot
+
+import pylab
+import pdb
+import math
+
+def pretty_kb(v):
+    if v < 1024:
+        return '%d' % v
+    else:
+        if v % 1024 == 0:
+            return '%d k' % (v//1024)
+        else:
+            return '%.1f k' % (v/1024)
+
+def plot(records, function, alignment=None, scale=1):
+    variants = libplot.unique(records, 'variant', prefer='this')
+    records = [x for x in records if x.function==function]
+
+    if alignment != None:
+        records = [x for x in records if x.src_alignment==alignment[0] and
+                   x.dst_alignment==alignment[1]]
+
+    alignments = libplot.unique(records, ('src_alignment', 'dst_alignment'))
+    if len(alignments) != 1:
+        return False
+    if libplot.alignments_equal(alignments):
+        aalignment = alignments[0][0]
+    else:
+        aalignment = "%s:%s" % (alignments[0][0], alignments[0][1])
+
+    bytes = libplot.unique(records, 'bytes')[0]
+
+    colours = libplot.make_colours()
+    all_x = []
+
+    pylab.figure(1).set_size_inches((6.4*scale, 4.8*scale))
+    pylab.clf()
+
+    if 'str' in function:
+        # The harness fills out to 16k.  Anything past that is an
+        # early match
+        top = 16384
+    else:
+        top = 2**31
+
+    for variant in variants:
+        matches = [x for x in records if x.variant==variant and x.bytes <= top]
+        matches.sort(key=lambda x: x.bytes)
+
+        X = sorted(list(set([x.bytes for x in matches])))
+        Y = []
+        Yerr = []
+        for xbytes in X:
+            vals = [x.bytes*x.loops/x.elapsed/(1024*1024) for x in matches if x.bytes == xbytes]
+            if len(vals) > 1:
+                mean = sum(vals)/len(vals)
+                Y.append(mean)
+                if len(Yerr) == 0:
+                    Yerr = [[], []]
+                err1 = max(vals) - mean
+                assert err1 >= 0
+                err2 = min(vals) - mean
+                assert err2 <= 0
+                Yerr[0].append(abs(err2))
+                Yerr[1].append(err1)
+            else:
+                Y.append(vals[0])
+
+        all_x.extend(X)
+        colour = colours.next()
+
+        if X:
+            pylab.plot(X, Y, c=colour)
+            if len(Yerr) > 0:
+                pylab.errorbar(X, Y, yerr=Yerr, c=colour, label=variant, fmt='o')
+            else:
+                pylab.scatter(X, Y, c=colour, label=variant, edgecolors='none')
+
+    pylab.legend(loc='upper left', ncol=3, prop={'size': 'small'})
+    pylab.grid()
+    pylab.title('%(function)s of %(aalignment)s byte aligned blocks' % locals())
+    pylab.xlabel('Size (B)')
+    pylab.ylabel('Rate (MB/s)')
+
+    # Figure out how high the range goes
+    top = max(all_x)
+
+    power = int(round(math.log(max(all_x)) / math.log(2)))
+
+    pylab.semilogx()
+
+    pylab.axes().set_xticks([2**x for x in range(0, power+1)])
+    pylab.axes().set_xticklabels([pretty_kb(2**x) for x in range(0, power+1)])
+    pylab.xlim(0, top)
+    pylab.ylim(0, pylab.ylim()[1])
+    return True
+
+def main():
+    records = libplot.parse()
+
+    functions = libplot.unique(records, 'function')
+    alignments = libplot.unique(records, ('src_alignment', 'dst_alignment'))
+
+    for function in functions:
+        for alignment in alignments:
+            for scale in [1, 2.5]:
+                if plot(records, function, alignment, scale):
+                    pylab.savefig('sizes-%s-%02d-%02d-%.1f.png' % (function, alignment[0], alignment[1], scale), dpi=72)
+
+    pylab.show()
+
+if __name__ == '__main__':
+    main()
diff --git a/contrib/cortex-strings/scripts/plot-top.py b/contrib/cortex-strings/scripts/plot-top.py
new file mode 100644
index 000000000000..4095239ac815
--- /dev/null
+++ b/contrib/cortex-strings/scripts/plot-top.py
@@ -0,0 +1,61 @@
+#!/usr/bin/env python
+
+"""Plot the performance of different variants of the string routines
+for one size.
+"""
+
+import libplot
+
+import pylab
+
+
+def plot(records, bytes):
+    records = [x for x in records if x.bytes==bytes]
+
+    variants = libplot.unique(records, 'variant', prefer='this')
+    functions = libplot.unique(records, 'function')
+
+    X = pylab.arange(len(functions))
+    width = 1.0/(len(variants)+1)
+
+    colours = libplot.make_colours()
+
+    pylab.figure(1).set_size_inches((16, 12))
+    pylab.clf()
+
+    for i, variant in enumerate(variants):
+        heights = []
+
+        for function in functions:
+            matches = [x for x in records if x.variant==variant and x.function==function and x.src_alignment==8]
+
+            if matches:
+                vals = [match.bytes*match.loops/match.elapsed/(1024*1024) for
+                        match in matches]
+                mean = sum(vals)/len(vals)
+                heights.append(mean)
+            else:
+                heights.append(0)
+
+        pylab.bar(X+i*width, heights, width, color=colours.next(), label=variant)
+
+    axes = pylab.axes()
+    axes.set_xticklabels(functions)
+    axes.set_xticks(X + 0.5)
+
+    pylab.title('Performance of different variants for %d byte blocks' % bytes)
+    pylab.ylabel('Rate (MB/s)')
+    pylab.legend(loc='upper left', ncol=3)
+    pylab.grid()
+    pylab.savefig('top-%06d.png' % bytes, dpi=72)
+
+def main():
+    records = libplot.parse()
+
+    for bytes in libplot.unique(records, 'bytes'):
+        plot(records, bytes)
+
+    pylab.show()
+
+if __name__ == '__main__':
+    main()
diff --git a/contrib/cortex-strings/scripts/plot.py b/contrib/cortex-strings/scripts/plot.py
new file mode 100644
index 000000000000..aa2bb1adb560
--- /dev/null
+++ b/contrib/cortex-strings/scripts/plot.py
@@ -0,0 +1,123 @@
+"""Plot the results for each test.  Spits out a set of images into the
+current directory.
+"""
+
+import libplot
+
+import fileinput
+import collections
+import pprint
+
+import pylab
+
+Record = collections.namedtuple('Record', 'variant test size loops src_alignment dst_alignment run_id rawtime comment time bytes rate')
+
+def unique(rows, name):
+    """Takes a list of values, pulls out the named field, and returns
+    a list of the unique values of this field.
+    """
+    return sorted(set(getattr(x, name) for x in rows))
+
+def to_float(v):
+    """Convert a string into a better type.
+
+    >>> to_float('foo')
+    'foo'
+    >>> to_float('1.23')
+    1.23
+    >>> to_float('45')
+    45
+    """
+    try:
+        if '.' in v:
+            return float(v)
+        else:
+            return int(v)
+    except:
+        return v
+
+def parse():
+    # Split the input up
+    rows = [x.strip().split(':') for x in fileinput.input()]
+    # Automatically turn numbers into the base type
+    rows = [[to_float(y) for y in x] for x in rows]
+
+    # Scan once to calculate the overhead
+    r = [Record(*(x + [0, 0, 0])) for x in rows]
+    bounces = pylab.array([(x.loops, x.rawtime) for x in r if x.test == 'bounce'])
+    fit = pylab.polyfit(bounces[:,0], bounces[:,1], 1)
+
+    records = []
+
+    for row in rows:
+        # Make a dummy record so we can use the names
+        r1 = Record(*(row + [0, 0, 0]))
+
+        bytes = r1.size * r1.loops
+        # Calculate the bounce time
+        delta = pylab.polyval(fit, [r1.loops])
+        time = r1.rawtime - delta
+        rate = bytes / time
+
+        records.append(Record(*(row + [time, bytes, rate])))
+
+    return records
+
+def plot(records, field, scale, ylabel):
+    variants = unique(records, 'variant')
+    tests = unique(records, 'test')
+
+    colours = libplot.make_colours()
+
+    # A little hack.  We want the 'all' record to be drawn last so
+    # that it's obvious on the graph.  Assume that no tests come
+    # before it alphabetically
+    variants.reverse()
+
+    for test in tests:
+        for variant in variants:
+            v = [x for x in records if x.test==test and x.variant==variant]
+            v.sort(key=lambda x: x.size)
+            V = pylab.array([(x.size, getattr(x, field)) for x in v])
+
+            # Ensure our results appear
+            order = 1 if variant == 'this' else 0
+
+            try:
+                # A little hack.  We want the 'all' to be obvious on
+                # the graph
+                if variant == 'all':
+                    pylab.scatter(V[:,0], V[:,1]/scale, label=variant)
+                    pylab.plot(V[:,0], V[:,1]/scale)
+                else:
+                    pylab.plot(V[:,0], V[:,1]/scale, label=variant,
+                            zorder=order, c = colours.next())
+
+            except Exception, ex:
+                # michaelh1 likes to run this script while the test is
+                # still running which can lead to bad data
+                print ex, 'on %s of %s' % (variant, test)
+
+        pylab.legend(loc='lower right', ncol=2, prop={'size': 'small'})
+        pylab.xlabel('Block size (B)')
+        pylab.ylabel(ylabel)
+        pylab.title('%s %s' % (test, field))
+        pylab.grid()
+
+        pylab.savefig('%s-%s.png' % (test, field), dpi=100)
+        pylab.semilogx(basex=2)
+        pylab.savefig('%s-%s-semilog.png' % (test, field), dpi=100)
+        pylab.clf()
+
+def test():
+    import doctest
+    doctest.testmod()
+
+def main():
+    records = parse()
+
+    plot(records, 'rate', 1024**2, 'Rate (MB/s)')
+    plot(records, 'time', 1, 'Total time (s)')
+
+if __name__ == '__main__':
+    main()
diff --git a/contrib/cortex-strings/scripts/trim.sh b/contrib/cortex-strings/scripts/trim.sh
new file mode 100755
index 000000000000..dab1047f34f9
--- /dev/null
+++ b/contrib/cortex-strings/scripts/trim.sh
@@ -0,0 +1,9 @@
+#!/bin/bash
+#
+# Trims the whitespace from around any given images
+#
+
+for i in $@; do
+    convert $i -bordercolor white -border 1x1 -trim +repage -alpha off +dither -colors 32 PNG8:next-$i
+    mv next-$i $i
+done
diff --git a/contrib/cortex-strings/src/aarch64/memchr.S b/contrib/cortex-strings/src/aarch64/memchr.S
new file mode 100644
index 000000000000..a3492d4cef40
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/memchr.S
@@ -0,0 +1,172 @@
+/*
+ * memchr - find a character in a memory zone
+ *
+ * Copyright (c) 2014, ARM Limited
+ * All rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the company nor the names of its contributors
+ *       may be used to endorse or promote products derived from this
+ *       software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * Neon Available.
+ */
+
+/* Arguments and results.  */
+#define srcin		x0
+#define chrin		w1
+#define cntin		x2
+
+#define result		x0
+
+#define src		x3
+#define	tmp		x4
+#define wtmp2		w5
+#define synd		x6
+#define soff		x9
+#define cntrem		x10
+
+#define vrepchr		v0
+#define vdata1		v1
+#define vdata2		v2
+#define vhas_chr1	v3
+#define vhas_chr2	v4
+#define vrepmask	v5
+#define vend		v6
+
+/*
+ * Core algorithm:
+ *
+ * For each 32-byte chunk we calculate a 64-bit syndrome value, with two bits
+ * per byte. For each tuple, bit 0 is set if the relevant byte matched the
+ * requested character and bit 1 is not used (faster than using a 32bit
+ * syndrome). Since the bits in the syndrome reflect exactly the order in which
+ * things occur in the original string, counting trailing zeros allows to
+ * identify exactly which byte has matched.
+ */
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+def_fn memchr
+	/* Do not dereference srcin if no bytes to compare.  */
+	cbz	cntin, .Lzero_length
+	/*
+	 * Magic constant 0x40100401 allows us to identify which lane matches
+	 * the requested byte.
+	 */
+	mov	wtmp2, #0x0401
+	movk	wtmp2, #0x4010, lsl #16
+	dup	vrepchr.16b, chrin
+	/* Work with aligned 32-byte chunks */
+	bic	src, srcin, #31
+	dup	vrepmask.4s, wtmp2
+	ands	soff, srcin, #31
+	and	cntrem, cntin, #31
+	b.eq	.Lloop
+
+	/*
+	 * Input string is not 32-byte aligned. We calculate the syndrome
+	 * value for the aligned 32 bytes block containing the first bytes
+	 * and mask the irrelevant part.
+	 */
+
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	sub	tmp, soff, #32
+	adds	cntin, cntin, tmp
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
+	addp	vend.16b, vhas_chr1.16b, vhas_chr2.16b		/* 256->128 */
+	addp	vend.16b, vend.16b, vend.16b			/* 128->64 */
+	mov	synd, vend.d[0]
+	/* Clear the soff*2 lower bits */
+	lsl	tmp, soff, #1
+	lsr	synd, synd, tmp
+	lsl	synd, synd, tmp
+	/* The first block can also be the last */
+	b.ls	.Lmasklast
+	/* Have we found something already? */
+	cbnz	synd, .Ltail
+
+.Lloop:
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	subs	cntin, cntin, #32
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	/* If we're out of data we finish regardless of the result */
+	b.ls	.Lend
+	/* Use a fast check for the termination condition */
+	orr	vend.16b, vhas_chr1.16b, vhas_chr2.16b
+	addp	vend.2d, vend.2d, vend.2d
+	mov	synd, vend.d[0]
+	/* We're not out of data, loop if we haven't found the character */
+	cbz	synd, .Lloop
+
+.Lend:
+	/* Termination condition found, let's calculate the syndrome value */
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
+	addp	vend.16b, vhas_chr1.16b, vhas_chr2.16b		/* 256->128 */
+	addp	vend.16b, vend.16b, vend.16b			/* 128->64 */
+	mov	synd, vend.d[0]
+	/* Only do the clear for the last possible block */
+	b.hi	.Ltail
+
+.Lmasklast:
+	/* Clear the (32 - ((cntrem + soff) % 32)) * 2 upper bits */
+	add	tmp, cntrem, soff
+	and	tmp, tmp, #31
+	sub	tmp, tmp, #32
+	neg	tmp, tmp, lsl #1
+	lsl	synd, synd, tmp
+	lsr	synd, synd, tmp
+
+.Ltail:
+	/* Count the trailing zeros using bit reversing */
+	rbit	synd, synd
+	/* Compensate the last post-increment */
+	sub	src, src, #32
+	/* Check that we have found a character */
+	cmp	synd, #0
+	/* And count the leading zeros */
+	clz	synd, synd
+	/* Compute the potential result */
+	add	result, src, synd, lsr #1
+	/* Select result or NULL */
+	csel	result, xzr, result, eq
+	ret
+
+.Lzero_length:
+	mov	result, #0
+	ret
+
+	.size	memchr, . - memchr
diff --git a/contrib/cortex-strings/src/aarch64/memcmp.S b/contrib/cortex-strings/src/aarch64/memcmp.S
new file mode 100644
index 000000000000..abba416b07a7
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/memcmp.S
@@ -0,0 +1,162 @@
+/* memcmp - compare memory
+
+   Copyright (c) 2013, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the Linaro nor the
+         names of its contributors may be used to endorse or promote products
+         derived from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ */
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+/* Parameters and result.  */
+#define src1		x0
+#define src2		x1
+#define limit		x2
+#define result		x0
+
+/* Internal variables.  */
+#define data1		x3
+#define data1w		w3
+#define data2		x4
+#define data2w		w4
+#define has_nul		x5
+#define diff		x6
+#define endloop		x7
+#define tmp1		x8
+#define tmp2		x9
+#define tmp3		x10
+#define pos		x11
+#define limit_wd	x12
+#define mask		x13
+
+def_fn memcmp p2align=6
+	cbz	limit, .Lret0
+	eor	tmp1, src1, src2
+	tst	tmp1, #7
+	b.ne	.Lmisaligned8
+	ands	tmp1, src1, #7
+	b.ne	.Lmutual_align
+	add	limit_wd, limit, #7
+	lsr	limit_wd, limit_wd, #3
+	/* Start of performance-critical section  -- one 64B cache line.  */
+.Lloop_aligned:
+	ldr	data1, [src1], #8
+	ldr	data2, [src2], #8
+.Lstart_realigned:
+	subs	limit_wd, limit_wd, #1
+	eor	diff, data1, data2	/* Non-zero if differences found.  */
+	csinv	endloop, diff, xzr, ne	/* Last Dword or differences.  */
+	cbz	endloop, .Lloop_aligned
+	/* End of performance-critical section  -- one 64B cache line.  */
+
+	/* Not reached the limit, must have found a diff.  */
+	cbnz	limit_wd, .Lnot_limit
+
+	/* Limit % 8 == 0 => all bytes significant.  */
+	ands	limit, limit, #7
+	b.eq	.Lnot_limit
+
+	lsl	limit, limit, #3	/* Bits -> bytes.  */
+	mov	mask, #~0
+#ifdef __AARCH64EB__
+	lsr	mask, mask, limit
+#else
+	lsl	mask, mask, limit
+#endif
+	bic	data1, data1, mask
+	bic	data2, data2, mask
+
+	orr	diff, diff, mask
+.Lnot_limit:
+
+#ifndef	__AARCH64EB__
+	rev	diff, diff
+	rev	data1, data1
+	rev	data2, data2
+#endif
+	/* The MS-non-zero bit of DIFF marks either the first bit
+	   that is different, or the end of the significant data.
+	   Shifting left now will bring the critical information into the
+	   top bits.  */
+	clz	pos, diff
+	lsl	data1, data1, pos
+	lsl	data2, data2, pos
+	/* But we need to zero-extend (char is unsigned) the value and then
+	   perform a signed 32-bit subtraction.  */
+	lsr	data1, data1, #56
+	sub	result, data1, data2, lsr #56
+	ret
+
+.Lmutual_align:
+	/* Sources are mutually aligned, but are not currently at an
+	   alignment boundary.  Round down the addresses and then mask off
+	   the bytes that precede the start point.  */
+	bic	src1, src1, #7
+	bic	src2, src2, #7
+	add	limit, limit, tmp1	/* Adjust the limit for the extra.  */
+	lsl	tmp1, tmp1, #3		/* Bytes beyond alignment -> bits.  */
+	ldr	data1, [src1], #8
+	neg	tmp1, tmp1		/* Bits to alignment -64.  */
+	ldr	data2, [src2], #8
+	mov	tmp2, #~0
+#ifdef __AARCH64EB__
+	/* Big-endian.  Early bytes are at MSB.  */
+	lsl	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#else
+	/* Little-endian.  Early bytes are at LSB.  */
+	lsr	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#endif
+	add	limit_wd, limit, #7
+	orr	data1, data1, tmp2
+	orr	data2, data2, tmp2
+	lsr	limit_wd, limit_wd, #3
+	b	.Lstart_realigned
+
+.Lret0:
+	mov	result, #0
+	ret
+
+	.p2align 6
+.Lmisaligned8:
+	sub	limit, limit, #1
+1:
+	/* Perhaps we can do better than this.  */
+	ldrb	data1w, [src1], #1
+	ldrb	data2w, [src2], #1
+	subs	limit, limit, #1
+	ccmp	data1w, data2w, #0, cs	/* NZCV = 0b0000.  */
+	b.eq	1b
+	sub	result, data1, data2
+	ret
+	.size memcmp, . - memcmp
diff --git a/contrib/cortex-strings/src/aarch64/memcpy.S b/contrib/cortex-strings/src/aarch64/memcpy.S
new file mode 100644
index 000000000000..cbae37121844
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/memcpy.S
@@ -0,0 +1,225 @@
+/* Copyright (c) 2012, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the Linaro nor the
+         names of its contributors may be used to endorse or promote products
+         derived from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * Copyright (c) 2015 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses.
+ *
+ */
+
+#define dstin	x0
+#define src	x1
+#define count	x2
+#define dst	x3
+#define srcend	x4
+#define dstend	x5
+#define A_l	x6
+#define A_lw	w6
+#define A_h	x7
+#define A_hw	w7
+#define B_l	x8
+#define B_lw	w8
+#define B_h	x9
+#define C_l	x10
+#define C_h	x11
+#define D_l	x12
+#define D_h	x13
+#define E_l	src
+#define E_h	count
+#define F_l	srcend
+#define F_h	dst
+#define tmp1	x9
+
+#define L(l) .L ## l
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+/* Copies are split into 3 main cases: small copies of up to 16 bytes,
+   medium copies of 17..96 bytes which are fully unrolled. Large copies
+   of more than 96 bytes align the destination and use an unrolled loop
+   processing 64 bytes per iteration.
+   Small and medium copies read all data before writing, allowing any
+   kind of overlap, and memmove tailcalls memcpy for these cases as
+   well as non-overlapping copies.
+*/
+
+def_fn memcpy p2align=6
+	prfm	PLDL1KEEP, [src]
+	add	srcend, src, count
+	add	dstend, dstin, count
+	cmp	count, 16
+	b.ls	L(copy16)
+	cmp	count, 96
+	b.hi	L(copy_long)
+
+	/* Medium copies: 17..96 bytes.  */
+	sub	tmp1, count, 1
+	ldp	A_l, A_h, [src]
+	tbnz	tmp1, 6, L(copy96)
+	ldp	D_l, D_h, [srcend, -16]
+	tbz	tmp1, 5, 1f
+	ldp	B_l, B_h, [src, 16]
+	ldp	C_l, C_h, [srcend, -32]
+	stp	B_l, B_h, [dstin, 16]
+	stp	C_l, C_h, [dstend, -32]
+1:
+	stp	A_l, A_h, [dstin]
+	stp	D_l, D_h, [dstend, -16]
+	ret
+
+	.p2align 4
+	/* Small copies: 0..16 bytes.  */
+L(copy16):
+	cmp	count, 8
+	b.lo	1f
+	ldr	A_l, [src]
+	ldr	A_h, [srcend, -8]
+	str	A_l, [dstin]
+	str	A_h, [dstend, -8]
+	ret
+	.p2align 4
+1:
+	tbz	count, 2, 1f
+	ldr	A_lw, [src]
+	ldr	A_hw, [srcend, -4]
+	str	A_lw, [dstin]
+	str	A_hw, [dstend, -4]
+	ret
+
+	/* Copy 0..3 bytes.  Use a branchless sequence that copies the same
+	   byte 3 times if count==1, or the 2nd byte twice if count==2.  */
+1:
+	cbz	count, 2f
+	lsr	tmp1, count, 1
+	ldrb	A_lw, [src]
+	ldrb	A_hw, [srcend, -1]
+	ldrb	B_lw, [src, tmp1]
+	strb	A_lw, [dstin]
+	strb	B_lw, [dstin, tmp1]
+	strb	A_hw, [dstend, -1]
+2:	ret
+
+	.p2align 4
+	/* Copy 64..96 bytes.  Copy 64 bytes from the start and
+	   32 bytes from the end.  */
+L(copy96):
+	ldp	B_l, B_h, [src, 16]
+	ldp	C_l, C_h, [src, 32]
+	ldp	D_l, D_h, [src, 48]
+	ldp	E_l, E_h, [srcend, -32]
+	ldp	F_l, F_h, [srcend, -16]
+	stp	A_l, A_h, [dstin]
+	stp	B_l, B_h, [dstin, 16]
+	stp	C_l, C_h, [dstin, 32]
+	stp	D_l, D_h, [dstin, 48]
+	stp	E_l, E_h, [dstend, -32]
+	stp	F_l, F_h, [dstend, -16]
+	ret
+
+	/* Align DST to 16 byte alignment so that we don't cross cache line
+	   boundaries on both loads and stores.	 There are at least 96 bytes
+	   to copy, so copy 16 bytes unaligned and then align.	The loop
+	   copies 64 bytes per iteration and prefetches one iteration ahead.  */
+
+	.p2align 4
+L(copy_long):
+	and	tmp1, dstin, 15
+	bic	dst, dstin, 15
+	ldp	D_l, D_h, [src]
+	sub	src, src, tmp1
+	add	count, count, tmp1	/* Count is now 16 too large.  */
+	ldp	A_l, A_h, [src, 16]
+	stp	D_l, D_h, [dstin]
+	ldp	B_l, B_h, [src, 32]
+	ldp	C_l, C_h, [src, 48]
+	ldp	D_l, D_h, [src, 64]!
+	subs	count, count, 128 + 16	/* Test and readjust count.  */
+	b.ls	2f
+1:
+	stp	A_l, A_h, [dst, 16]
+	ldp	A_l, A_h, [src, 16]
+	stp	B_l, B_h, [dst, 32]
+	ldp	B_l, B_h, [src, 32]
+	stp	C_l, C_h, [dst, 48]
+	ldp	C_l, C_h, [src, 48]
+	stp	D_l, D_h, [dst, 64]!
+	ldp	D_l, D_h, [src, 64]!
+	subs	count, count, 64
+	b.hi	1b
+
+	/* Write the last full set of 64 bytes.	 The remainder is at most 64
+	   bytes, so it is safe to always copy 64 bytes from the end even if
+	   there is just 1 byte left.  */
+2:
+	ldp	E_l, E_h, [srcend, -64]
+	stp	A_l, A_h, [dst, 16]
+	ldp	A_l, A_h, [srcend, -48]
+	stp	B_l, B_h, [dst, 32]
+	ldp	B_l, B_h, [srcend, -32]
+	stp	C_l, C_h, [dst, 48]
+	ldp	C_l, C_h, [srcend, -16]
+	stp	D_l, D_h, [dst, 64]
+	stp	E_l, E_h, [dstend, -64]
+	stp	A_l, A_h, [dstend, -48]
+	stp	B_l, B_h, [dstend, -32]
+	stp	C_l, C_h, [dstend, -16]
+	ret
+
+	.size	memcpy, . - memcpy
diff --git a/contrib/cortex-strings/src/aarch64/memmove.S b/contrib/cortex-strings/src/aarch64/memmove.S
new file mode 100644
index 000000000000..c9fe6c1f5710
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/memmove.S
@@ -0,0 +1,150 @@
+/* Copyright (c) 2013, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the Linaro nor the
+         names of its contributors may be used to endorse or promote products
+         derived from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * Copyright (c) 2015 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses
+ */
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+/* Parameters and result.  */
+#define dstin	x0
+#define src	x1
+#define count	x2
+#define srcend	x3
+#define dstend	x4
+#define tmp1	x5
+#define A_l	x6
+#define A_h	x7
+#define B_l	x8
+#define B_h	x9
+#define C_l	x10
+#define C_h	x11
+#define D_l	x12
+#define D_h	x13
+#define E_l	count
+#define E_h	tmp1
+
+/* All memmoves up to 96 bytes are done by memcpy as it supports overlaps.
+   Larger backwards copies are also handled by memcpy. The only remaining
+   case is forward large copies.  The destination is aligned, and an
+   unrolled loop processes 64 bytes per iteration.
+*/
+
+def_fn memmove, 6
+	sub	tmp1, dstin, src
+	cmp	count, 96
+	ccmp	tmp1, count, 2, hi
+	b.hs	memcpy
+
+	cbz	tmp1, 3f
+	add	dstend, dstin, count
+	add	srcend, src, count
+
+	/* Align dstend to 16 byte alignment so that we don't cross cache line
+	   boundaries on both loads and stores.	 There are at least 96 bytes
+	   to copy, so copy 16 bytes unaligned and then align.	The loop
+	   copies 64 bytes per iteration and prefetches one iteration ahead.  */
+
+	and	tmp1, dstend, 15
+	ldp	D_l, D_h, [srcend, -16]
+	sub	srcend, srcend, tmp1
+	sub	count, count, tmp1
+	ldp	A_l, A_h, [srcend, -16]
+	stp	D_l, D_h, [dstend, -16]
+	ldp	B_l, B_h, [srcend, -32]
+	ldp	C_l, C_h, [srcend, -48]
+	ldp	D_l, D_h, [srcend, -64]!
+	sub	dstend, dstend, tmp1
+	subs	count, count, 128
+	b.ls	2f
+	nop
+1:
+	stp	A_l, A_h, [dstend, -16]
+	ldp	A_l, A_h, [srcend, -16]
+	stp	B_l, B_h, [dstend, -32]
+	ldp	B_l, B_h, [srcend, -32]
+	stp	C_l, C_h, [dstend, -48]
+	ldp	C_l, C_h, [srcend, -48]
+	stp	D_l, D_h, [dstend, -64]!
+	ldp	D_l, D_h, [srcend, -64]!
+	subs	count, count, 64
+	b.hi	1b
+
+	/* Write the last full set of 64 bytes.	 The remainder is at most 64
+	   bytes, so it is safe to always copy 64 bytes from the start even if
+	   there is just 1 byte left.  */
+2:
+	ldp	E_l, E_h, [src, 48]
+	stp	A_l, A_h, [dstend, -16]
+	ldp	A_l, A_h, [src, 32]
+	stp	B_l, B_h, [dstend, -32]
+	ldp	B_l, B_h, [src, 16]
+	stp	C_l, C_h, [dstend, -48]
+	ldp	C_l, C_h, [src]
+	stp	D_l, D_h, [dstend, -64]
+	stp	E_l, E_h, [dstin, 48]
+	stp	A_l, A_h, [dstin, 32]
+	stp	B_l, B_h, [dstin, 16]
+	stp	C_l, C_h, [dstin]
+3:	ret
+
+	.size	memmove, . - memmove
diff --git a/contrib/cortex-strings/src/aarch64/memset.S b/contrib/cortex-strings/src/aarch64/memset.S
new file mode 100644
index 000000000000..2d6675ad9907
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/memset.S
@@ -0,0 +1,235 @@
+/* Copyright (c) 2012, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the Linaro nor the
+         names of its contributors may be used to endorse or promote products
+         derived from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * Copyright (c) 2015 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses
+ *
+ */
+
+
+#define dstin	x0
+#define val	x1
+#define valw	w1
+#define count	x2
+#define dst	x3
+#define dstend	x4
+#define tmp1	x5
+#define tmp1w	w5
+#define tmp2	x6
+#define tmp2w	w6
+#define zva_len x7
+#define zva_lenw w7
+
+#define L(l) .L ## l
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+def_fn memset p2align=6
+
+	dup	v0.16B, valw
+	add	dstend, dstin, count
+
+	cmp	count, 96
+	b.hi	L(set_long)
+	cmp	count, 16
+	b.hs	L(set_medium)
+	mov	val, v0.D[0]
+
+	/* Set 0..15 bytes.  */
+	tbz	count, 3, 1f
+	str	val, [dstin]
+	str	val, [dstend, -8]
+	ret
+	nop
+1:	tbz	count, 2, 2f
+	str	valw, [dstin]
+	str	valw, [dstend, -4]
+	ret
+2:	cbz	count, 3f
+	strb	valw, [dstin]
+	tbz	count, 1, 3f
+	strh	valw, [dstend, -2]
+3:	ret
+
+	/* Set 17..96 bytes.  */
+L(set_medium):
+	str	q0, [dstin]
+	tbnz	count, 6, L(set96)
+	str	q0, [dstend, -16]
+	tbz	count, 5, 1f
+	str	q0, [dstin, 16]
+	str	q0, [dstend, -32]
+1:	ret
+
+	.p2align 4
+	/* Set 64..96 bytes.  Write 64 bytes from the start and
+	   32 bytes from the end.  */
+L(set96):
+	str	q0, [dstin, 16]
+	stp	q0, q0, [dstin, 32]
+	stp	q0, q0, [dstend, -32]
+	ret
+
+	.p2align 3
+	nop
+L(set_long):
+	and	valw, valw, 255
+	bic	dst, dstin, 15
+	str	q0, [dstin]
+	cmp	count, 256
+	ccmp	valw, 0, 0, cs
+	b.eq	L(try_zva)
+L(no_zva):
+	sub	count, dstend, dst	/* Count is 16 too large.  */
+	add	dst, dst, 16
+	sub	count, count, 64 + 16	/* Adjust count and bias for loop.  */
+1:	stp	q0, q0, [dst], 64
+	stp	q0, q0, [dst, -32]
+L(tail64):
+	subs	count, count, 64
+	b.hi	1b
+2:	stp	q0, q0, [dstend, -64]
+	stp	q0, q0, [dstend, -32]
+	ret
+
+	.p2align 3
+L(try_zva):
+	mrs	tmp1, dczid_el0
+	tbnz	tmp1w, 4, L(no_zva)
+	and	tmp1w, tmp1w, 15
+	cmp	tmp1w, 4	/* ZVA size is 64 bytes.  */
+	b.ne	 L(zva_128)
+
+	/* Write the first and last 64 byte aligned block using stp rather
+	   than using DC ZVA.  This is faster on some cores.
+	 */
+L(zva_64):
+	str	q0, [dst, 16]
+	stp	q0, q0, [dst, 32]
+	bic	dst, dst, 63
+	stp	q0, q0, [dst, 64]
+	stp	q0, q0, [dst, 96]
+	sub	count, dstend, dst	/* Count is now 128 too large.	*/
+	sub	count, count, 128+64+64	/* Adjust count and bias for loop.  */
+	add	dst, dst, 128
+	nop
+1:	dc	zva, dst
+	add	dst, dst, 64
+	subs	count, count, 64
+	b.hi	1b
+	stp	q0, q0, [dst, 0]
+	stp	q0, q0, [dst, 32]
+	stp	q0, q0, [dstend, -64]
+	stp	q0, q0, [dstend, -32]
+	ret
+
+	.p2align 3
+L(zva_128):
+	cmp	tmp1w, 5	/* ZVA size is 128 bytes.  */
+	b.ne	L(zva_other)
+
+	str	q0, [dst, 16]
+	stp	q0, q0, [dst, 32]
+	stp	q0, q0, [dst, 64]
+	stp	q0, q0, [dst, 96]
+	bic	dst, dst, 127
+	sub	count, dstend, dst	/* Count is now 128 too large.	*/
+	sub	count, count, 128+128	/* Adjust count and bias for loop.  */
+	add	dst, dst, 128
+1:	dc	zva, dst
+	add	dst, dst, 128
+	subs	count, count, 128
+	b.hi	1b
+	stp	q0, q0, [dstend, -128]
+	stp	q0, q0, [dstend, -96]
+	stp	q0, q0, [dstend, -64]
+	stp	q0, q0, [dstend, -32]
+	ret
+
+L(zva_other):
+	mov	tmp2w, 4
+	lsl	zva_lenw, tmp2w, tmp1w
+	add	tmp1, zva_len, 64	/* Max alignment bytes written.	 */
+	cmp	count, tmp1
+	blo	L(no_zva)
+
+	sub	tmp2, zva_len, 1
+	add	tmp1, dst, zva_len
+	add	dst, dst, 16
+	subs	count, tmp1, dst	/* Actual alignment bytes to write.  */
+	bic	tmp1, tmp1, tmp2	/* Aligned dc zva start address.  */
+	beq	2f
+1:	stp	q0, q0, [dst], 64
+	stp	q0, q0, [dst, -32]
+	subs	count, count, 64
+	b.hi	1b
+2:	mov	dst, tmp1
+	sub	count, dstend, tmp1	/* Remaining bytes to write.  */
+	subs	count, count, zva_len
+	b.lo	4f
+3:	dc	zva, dst
+	add	dst, dst, zva_len
+	subs	count, count, zva_len
+	b.hs	3b
+4:	add	count, count, zva_len
+	b	L(tail64)
+
+	.size	memset, . - memset
diff --git a/contrib/cortex-strings/src/aarch64/strchr.S b/contrib/cortex-strings/src/aarch64/strchr.S
new file mode 100644
index 000000000000..860db10d3743
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/strchr.S
@@ -0,0 +1,165 @@
+/*
+   strchr - find a character in a string
+
+   Copyright (c) 2014, ARM Limited
+   All rights Reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the company nor the names of its contributors
+         may be used to endorse or promote products derived from this
+         software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * Neon Available.
+ */
+
+/* Arguments and results.  */
+#define srcin		x0
+#define chrin		w1
+
+#define result		x0
+
+#define src		x2
+#define	tmp1		x3
+#define wtmp2		w4
+#define tmp3		x5
+
+#define vrepchr		v0
+#define vdata1		v1
+#define vdata2		v2
+#define vhas_nul1	v3
+#define vhas_nul2	v4
+#define vhas_chr1	v5
+#define vhas_chr2	v6
+#define vrepmask_0	v7
+#define vrepmask_c	v16
+#define vend1		v17
+#define vend2		v18
+
+/* Core algorithm.
+
+   For each 32-byte hunk we calculate a 64-bit syndrome value, with
+   two bits per byte (LSB is always in bits 0 and 1, for both big
+   and little-endian systems).  For each tuple, bit 0 is set iff
+   the relevant byte matched the requested character; bit 1 is set
+   iff the relevant byte matched the NUL end of string (we trigger
+   off bit0 for the special case of looking for NUL).  Since the bits
+   in the syndrome reflect exactly the order in which things occur
+   in the original string a count_trailing_zeros() operation will
+   identify exactly which byte is causing the termination, and why.  */
+
+/* Locals and temporaries.  */
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+	.macro def_alias f a
+	.weak \a
+	.set \a,\f
+	.endm
+
+def_fn strchr
+def_alias strchr index
+	/* Magic constant 0x40100401 to allow us to identify which lane
+	   matches the requested byte.  Magic constant 0x80200802 used
+	   similarly for NUL termination.  */
+	mov	wtmp2, #0x0401
+	movk	wtmp2, #0x4010, lsl #16
+	dup	vrepchr.16b, chrin
+	bic	src, srcin, #31		/* Work with aligned 32-byte hunks.  */
+	dup	vrepmask_c.4s, wtmp2
+	ands	tmp1, srcin, #31
+	add	vrepmask_0.4s, vrepmask_c.4s, vrepmask_c.4s /* equiv: lsl #1 */
+	b.eq	.Lloop
+
+	/* Input string is not 32-byte aligned.  Rather than forcing
+	   the padding bytes to a safe value, we calculate the syndrome
+	   for all the bytes, but then mask off those bits of the
+	   syndrome that are related to the padding.  */
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	neg	tmp1, tmp1
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	and	vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
+	and	vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
+	orr	vend1.16b, vhas_nul1.16b, vhas_chr1.16b
+	orr	vend2.16b, vhas_nul2.16b, vhas_chr2.16b
+	lsl	tmp1, tmp1, #1
+	addp	vend1.16b, vend1.16b, vend2.16b		// 256->128
+	mov	tmp3, #~0
+	addp	vend1.16b, vend1.16b, vend2.16b		// 128->64
+	lsr	tmp1, tmp3, tmp1
+
+	mov	tmp3, vend1.d[0]
+	bic	tmp1, tmp3, tmp1	// Mask padding bits.
+	cbnz	tmp1, .Ltail
+
+.Lloop:
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	/* Use a fast check for the termination condition.  */
+	orr	vend1.16b, vhas_nul1.16b, vhas_chr1.16b
+	orr	vend2.16b, vhas_nul2.16b, vhas_chr2.16b
+	orr	vend1.16b, vend1.16b, vend2.16b
+	addp	vend1.2d, vend1.2d, vend1.2d
+	mov	tmp1, vend1.d[0]
+	cbz	tmp1, .Lloop
+
+	/* Termination condition found.  Now need to establish exactly why
+	   we terminated.  */
+	and	vhas_nul1.16b, vhas_nul1.16b, vrepmask_0.16b
+	and	vhas_nul2.16b, vhas_nul2.16b, vrepmask_0.16b
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask_c.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask_c.16b
+	orr	vend1.16b, vhas_nul1.16b, vhas_chr1.16b
+	orr	vend2.16b, vhas_nul2.16b, vhas_chr2.16b
+	addp	vend1.16b, vend1.16b, vend2.16b		// 256->128
+	addp	vend1.16b, vend1.16b, vend2.16b		// 128->64
+
+	mov	tmp1, vend1.d[0]
+.Ltail:
+	/* Count the trailing zeros, by bit reversing...  */
+	rbit	tmp1, tmp1
+	/* Re-bias source.  */
+	sub	src, src, #32
+	clz	tmp1, tmp1	/* And counting the leading zeros.  */
+	/* Tmp1 is even if the target charager was found first.  Otherwise
+	   we've found the end of string and we weren't looking for NUL.  */
+	tst	tmp1, #1
+	add	result, src, tmp1, lsr #1
+	csel	result, result, xzr, eq
+	ret
+
+	.size	strchr, . - strchr
diff --git a/contrib/cortex-strings/src/aarch64/strchrnul.S b/contrib/cortex-strings/src/aarch64/strchrnul.S
new file mode 100644
index 000000000000..956aa5e9ff77
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/strchrnul.S
@@ -0,0 +1,144 @@
+/*
+   strchrnul - find a character or nul in a string
+
+   Copyright (c) 2014, ARM Limited
+   All rights Reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the company nor the names of its contributors
+         may be used to endorse or promote products derived from this
+         software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ * Neon Available.
+ */
+
+/* Arguments and results.  */
+#define srcin		x0
+#define chrin		w1
+
+#define result		x0
+
+#define src		x2
+#define	tmp1		x3
+#define wtmp2		w4
+#define tmp3		x5
+
+#define vrepchr		v0
+#define vdata1		v1
+#define vdata2		v2
+#define vhas_nul1	v3
+#define vhas_nul2	v4
+#define vhas_chr1	v5
+#define vhas_chr2	v6
+#define vrepmask	v7
+#define vend1		v16
+
+/* Core algorithm.
+
+   For each 32-byte hunk we calculate a 64-bit syndrome value, with
+   two bits per byte (LSB is always in bits 0 and 1, for both big
+   and little-endian systems).  For each tuple, bit 0 is set iff
+   the relevant byte matched the requested character or nul.  Since the
+   bits in the syndrome reflect exactly the order in which things occur
+   in the original string a count_trailing_zeros() operation will
+   identify exactly which byte is causing the termination.  */
+
+/* Locals and temporaries.  */
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+def_fn strchrnul
+	/* Magic constant 0x40100401 to allow us to identify which lane
+	   matches the termination condition.  */
+	mov	wtmp2, #0x0401
+	movk	wtmp2, #0x4010, lsl #16
+	dup	vrepchr.16b, chrin
+	bic	src, srcin, #31		/* Work with aligned 32-byte hunks.  */
+	dup	vrepmask.4s, wtmp2
+	ands	tmp1, srcin, #31
+	b.eq	.Lloop
+
+	/* Input string is not 32-byte aligned.  Rather than forcing
+	   the padding bytes to a safe value, we calculate the syndrome
+	   for all the bytes, but then mask off those bits of the
+	   syndrome that are related to the padding.  */
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	neg	tmp1, tmp1
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	orr	vhas_chr1.16b, vhas_chr1.16b, vhas_nul1.16b
+	orr	vhas_chr2.16b, vhas_chr2.16b, vhas_nul2.16b
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
+	lsl	tmp1, tmp1, #1
+	addp	vend1.16b, vhas_chr1.16b, vhas_chr2.16b	// 256->128
+	mov	tmp3, #~0
+	addp	vend1.16b, vend1.16b, vend1.16b		// 128->64
+	lsr	tmp1, tmp3, tmp1
+
+	mov	tmp3, vend1.d[0]
+	bic	tmp1, tmp3, tmp1	// Mask padding bits.
+	cbnz	tmp1, .Ltail
+
+.Lloop:
+	ld1	{vdata1.16b, vdata2.16b}, [src], #32
+	cmeq	vhas_nul1.16b, vdata1.16b, #0
+	cmeq	vhas_chr1.16b, vdata1.16b, vrepchr.16b
+	cmeq	vhas_nul2.16b, vdata2.16b, #0
+	cmeq	vhas_chr2.16b, vdata2.16b, vrepchr.16b
+	/* Use a fast check for the termination condition.  */
+	orr	vhas_chr1.16b, vhas_nul1.16b, vhas_chr1.16b
+	orr	vhas_chr2.16b, vhas_nul2.16b, vhas_chr2.16b
+	orr	vend1.16b, vhas_chr1.16b, vhas_chr2.16b
+	addp	vend1.2d, vend1.2d, vend1.2d
+	mov	tmp1, vend1.d[0]
+	cbz	tmp1, .Lloop
+
+	/* Termination condition found.  Now need to establish exactly why
+	   we terminated.  */
+	and	vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
+	and	vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
+	addp	vend1.16b, vhas_chr1.16b, vhas_chr2.16b		// 256->128
+	addp	vend1.16b, vend1.16b, vend1.16b		// 128->64
+
+	mov	tmp1, vend1.d[0]
+.Ltail:
+	/* Count the trailing zeros, by bit reversing...  */
+	rbit	tmp1, tmp1
+	/* Re-bias source.  */
+	sub	src, src, #32
+	clz	tmp1, tmp1	/* ... and counting the leading zeros.  */
+	/* tmp1 is twice the offset into the fragment.  */
+	add	result, src, tmp1, lsr #1
+	ret
+
+	.size	strchrnul, . - strchrnul
diff --git a/contrib/cortex-strings/src/aarch64/strcmp.S b/contrib/cortex-strings/src/aarch64/strcmp.S
new file mode 100644
index 000000000000..e5af383ca899
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/strcmp.S
@@ -0,0 +1,166 @@
+/* Copyright (c) 2012, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the Linaro nor the
+         names of its contributors may be used to endorse or promote products
+         derived from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ */
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+/* Parameters and result.  */
+#define src1		x0
+#define src2		x1
+#define result		x0
+
+/* Internal variables.  */
+#define data1		x2
+#define data1w		w2
+#define data2		x3
+#define data2w		w3
+#define has_nul		x4
+#define diff		x5
+#define syndrome	x6
+#define tmp1		x7
+#define tmp2		x8
+#define tmp3		x9
+#define zeroones	x10
+#define pos		x11
+
+	/* Start of performance-critical section  -- one 64B cache line.  */
+def_fn strcmp p2align=6
+	eor	tmp1, src1, src2
+	mov	zeroones, #REP8_01
+	tst	tmp1, #7
+	b.ne	.Lmisaligned8
+	ands	tmp1, src1, #7
+	b.ne	.Lmutual_align
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word.  */
+.Lloop_aligned:
+	ldr	data1, [src1], #8
+	ldr	data2, [src2], #8
+.Lstart_realigned:
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	eor	diff, data1, data2	/* Non-zero if differences found.  */
+	bic	has_nul, tmp1, tmp2	/* Non-zero if NUL terminator.  */
+	orr	syndrome, diff, has_nul
+	cbz	syndrome, .Lloop_aligned
+	/* End of performance-critical section  -- one 64B cache line.  */
+
+#ifndef	__AARCH64EB__
+	rev	syndrome, syndrome
+	rev	data1, data1
+	/* The MS-non-zero bit of the syndrome marks either the first bit
+	   that is different, or the top bit of the first zero byte.
+	   Shifting left now will bring the critical information into the
+	   top bits.  */
+	clz	pos, syndrome
+	rev	data2, data2
+	lsl	data1, data1, pos
+	lsl	data2, data2, pos
+	/* But we need to zero-extend (char is unsigned) the value and then
+	   perform a signed 32-bit subtraction.  */
+	lsr	data1, data1, #56
+	sub	result, data1, data2, lsr #56
+	ret
+#else
+	/* For big-endian we cannot use the trick with the syndrome value
+	   as carry-propagation can corrupt the upper bits if the trailing
+	   bytes in the string contain 0x01.  */
+	/* However, if there is no NUL byte in the dword, we can generate
+	   the result directly.  We can't just subtract the bytes as the
+	   MSB might be significant.  */
+	cbnz	has_nul, 1f
+	cmp	data1, data2
+	cset	result, ne
+	cneg	result, result, lo
+	ret
+1:
+	/* Re-compute the NUL-byte detection, using a byte-reversed value.  */
+	rev	tmp3, data1
+	sub	tmp1, tmp3, zeroones
+	orr	tmp2, tmp3, #REP8_7f
+	bic	has_nul, tmp1, tmp2
+	rev	has_nul, has_nul
+	orr	syndrome, diff, has_nul
+	clz	pos, syndrome
+	/* The MS-non-zero bit of the syndrome marks either the first bit
+	   that is different, or the top bit of the first zero byte.
+	   Shifting left now will bring the critical information into the
+	   top bits.  */
+	lsl	data1, data1, pos
+	lsl	data2, data2, pos
+	/* But we need to zero-extend (char is unsigned) the value and then
+	   perform a signed 32-bit subtraction.  */
+	lsr	data1, data1, #56
+	sub	result, data1, data2, lsr #56
+	ret
+#endif
+
+.Lmutual_align:
+	/* Sources are mutually aligned, but are not currently at an
+	   alignment boundary.  Round down the addresses and then mask off
+	   the bytes that preceed the start point.  */
+	bic	src1, src1, #7
+	bic	src2, src2, #7
+	lsl	tmp1, tmp1, #3		/* Bytes beyond alignment -> bits.  */
+	ldr	data1, [src1], #8
+	neg	tmp1, tmp1		/* Bits to alignment -64.  */
+	ldr	data2, [src2], #8
+	mov	tmp2, #~0
+#ifdef __AARCH64EB__
+	/* Big-endian.  Early bytes are at MSB.  */
+	lsl	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#else
+	/* Little-endian.  Early bytes are at LSB.  */
+	lsr	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#endif
+	orr	data1, data1, tmp2
+	orr	data2, data2, tmp2
+	b	.Lstart_realigned
+
+.Lmisaligned8:
+	/* We can do better than this.  */
+	ldrb	data1w, [src1], #1
+	ldrb	data2w, [src2], #1
+	cmp	data1w, #1
+	ccmp	data1w, data2w, #0, cs	/* NZCV = 0b0000.  */
+	b.eq	.Lmisaligned8
+	sub	result, data1, data2
+	ret
diff --git a/contrib/cortex-strings/src/aarch64/strcpy.S b/contrib/cortex-strings/src/aarch64/strcpy.S
new file mode 100644
index 000000000000..3d0d7f5b8dc8
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/strcpy.S
@@ -0,0 +1,336 @@
+/*
+   strcpy/stpcpy - copy a string returning pointer to start/end.
+
+   Copyright (c) 2013, 2014, 2015 ARM Ltd.
+   All Rights Reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the company nor the names of its contributors
+         may be used to endorse or promote products derived from this
+         software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses, min page size 4k.
+ */
+
+/* To build as stpcpy, define BUILD_STPCPY before compiling this file.
+
+   To test the page crossing code path more thoroughly, compile with
+   -DSTRCPY_TEST_PAGE_CROSS - this will force all copies through the slower
+   entry path.  This option is not intended for production use.  */
+
+/* Arguments and results.  */
+#define dstin		x0
+#define srcin		x1
+
+/* Locals and temporaries.  */
+#define src		x2
+#define dst		x3
+#define data1		x4
+#define data1w		w4
+#define data2		x5
+#define data2w		w5
+#define has_nul1	x6
+#define has_nul2	x7
+#define tmp1		x8
+#define tmp2		x9
+#define tmp3		x10
+#define tmp4		x11
+#define zeroones	x12
+#define data1a		x13
+#define data2a		x14
+#define pos		x15
+#define len		x16
+#define to_align	x17
+
+#ifdef BUILD_STPCPY
+#define STRCPY stpcpy
+#else
+#define STRCPY strcpy
+#endif
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word.  */
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+	/* AArch64 systems have a minimum page size of 4k.  We can do a quick
+	   page size check for crossing this boundary on entry and if we
+	   do not, then we can short-circuit much of the entry code.  We
+	   expect early page-crossing strings to be rare (probability of
+	   16/MIN_PAGE_SIZE ~= 0.4%), so the branch should be quite
+	   predictable, even with random strings.
+
+	   We don't bother checking for larger page sizes, the cost of setting
+	   up the correct page size is just not worth the extra gain from
+	   a small reduction in the cases taking the slow path.  Note that
+	   we only care about whether the first fetch, which may be
+	   misaligned, crosses a page boundary - after that we move to aligned
+	   fetches for the remainder of the string.  */
+
+#ifdef STRCPY_TEST_PAGE_CROSS
+	/* Make everything that isn't Qword aligned look like a page cross.  */
+#define MIN_PAGE_P2 4
+#else
+#define MIN_PAGE_P2 12
+#endif
+
+#define MIN_PAGE_SIZE (1 << MIN_PAGE_P2)
+
+def_fn STRCPY p2align=6
+	/* For moderately short strings, the fastest way to do the copy is to
+	   calculate the length of the string in the same way as strlen, then
+	   essentially do a memcpy of the result.  This avoids the need for
+	   multiple byte copies and further means that by the time we
+	   reach the bulk copy loop we know we can always use DWord
+	   accesses.  We expect strcpy to rarely be called repeatedly
+	   with the same source string, so branch prediction is likely to
+	   always be difficult - we mitigate against this by preferring
+	   conditional select operations over branches whenever this is
+	   feasible.  */
+	and	tmp2, srcin, #(MIN_PAGE_SIZE - 1)
+	mov	zeroones, #REP8_01
+	and	to_align, srcin, #15
+	cmp	tmp2, #(MIN_PAGE_SIZE - 16)
+	neg	tmp1, to_align
+	/* The first fetch will straddle a (possible) page boundary iff
+	   srcin + 15 causes bit[MIN_PAGE_P2] to change value.  A 16-byte
+	   aligned string will never fail the page align check, so will
+	   always take the fast path.  */
+	b.gt	.Lpage_cross
+
+.Lpage_cross_ok:
+	ldp	data1, data2, [srcin]
+#ifdef __AARCH64EB__
+	/* Because we expect the end to be found within 16 characters
+	   (profiling shows this is the most common case), it's worth
+	   swapping the bytes now to save having to recalculate the
+	   termination syndrome later.  We preserve data1 and data2
+	   so that we can re-use the values later on.  */
+	rev	tmp2, data1
+	sub	tmp1, tmp2, zeroones
+	orr	tmp2, tmp2, #REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	b.ne	.Lfp_le8
+	rev	tmp4, data2
+	sub	tmp3, tmp4, zeroones
+	orr	tmp4, tmp4, #REP8_7f
+#else
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	b.ne	.Lfp_le8
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+#endif
+	bics	has_nul2, tmp3, tmp4
+	b.eq	.Lbulk_entry
+
+	/* The string is short (<=16 bytes).  We don't know exactly how
+	   short though, yet.  Work out the exact length so that we can
+	   quickly select the optimal copy strategy.  */
+.Lfp_gt8:
+	rev	has_nul2, has_nul2
+	clz	pos, has_nul2
+	mov	tmp2, #56
+	add	dst, dstin, pos, lsr #3		/* Bits to bytes.  */
+	sub	pos, tmp2, pos
+#ifdef __AARCH64EB__
+	lsr	data2, data2, pos
+#else
+	lsl	data2, data2, pos
+#endif
+	str	data2, [dst, #1]
+	str	data1, [dstin]
+#ifdef BUILD_STPCPY
+	add	dstin, dst, #8
+#endif
+	ret
+
+.Lfp_le8:
+	rev	has_nul1, has_nul1
+	clz	pos, has_nul1
+	add	dst, dstin, pos, lsr #3		/* Bits to bytes.  */
+	subs	tmp2, pos, #24			/* Pos in bits. */
+	b.lt	.Lfp_lt4
+#ifdef __AARCH64EB__
+	mov	tmp2, #56
+	sub	pos, tmp2, pos
+	lsr	data2, data1, pos
+	lsr	data1, data1, #32
+#else
+	lsr	data2, data1, tmp2
+#endif
+	/* 4->7 bytes to copy.  */
+	str	data2w, [dst, #-3]
+	str	data1w, [dstin]
+#ifdef BUILD_STPCPY
+	mov	dstin, dst
+#endif
+	ret
+.Lfp_lt4:
+	cbz	pos, .Lfp_lt2
+	/* 2->3 bytes to copy.  */
+#ifdef __AARCH64EB__
+	lsr	data1, data1, #48
+#endif
+	strh	data1w, [dstin]
+	/* Fall-through, one byte (max) to go.  */
+.Lfp_lt2:
+	/* Null-terminated string.  Last character must be zero!  */
+	strb	wzr, [dst]
+#ifdef BUILD_STPCPY
+	mov	dstin, dst
+#endif
+	ret
+
+	.p2align 6
+	/* Aligning here ensures that the entry code and main loop all lies
+	   within one 64-byte cache line.  */
+.Lbulk_entry:
+	sub	to_align, to_align, #16
+	stp	data1, data2, [dstin]
+	sub	src, srcin, to_align
+	sub	dst, dstin, to_align
+	b	.Lentry_no_page_cross
+
+	/* The inner loop deals with two Dwords at a time.  This has a
+	   slightly higher start-up cost, but we should win quite quickly,
+	   especially on cores with a high number of issue slots per
+	   cycle, as we get much better parallelism out of the operations.  */
+.Lmain_loop:
+	stp	data1, data2, [dst], #16
+.Lentry_no_page_cross:
+	ldp	data1, data2, [src], #16
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+	bic	has_nul1, tmp1, tmp2
+	bics	has_nul2, tmp3, tmp4
+	ccmp	has_nul1, #0, #0, eq	/* NZCV = 0000  */
+	b.eq	.Lmain_loop
+
+	/* Since we know we are copying at least 16 bytes, the fastest way
+	   to deal with the tail is to determine the location of the
+	   trailing NUL, then (re)copy the 16 bytes leading up to that.  */
+	cmp	has_nul1, #0
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul directly.  The
+	   easiest way to get the correct byte is to byte-swap the data
+	   and calculate the syndrome a second time.  */
+	csel	data1, data1, data2, ne
+	rev	data1, data1
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	bic	has_nul1, tmp1, tmp2
+#else
+	csel	has_nul1, has_nul1, has_nul2, ne
+#endif
+	rev	has_nul1, has_nul1
+	clz	pos, has_nul1
+	add	tmp1, pos, #72
+	add	pos, pos, #8
+	csel	pos, pos, tmp1, ne
+	add	src, src, pos, lsr #3
+	add	dst, dst, pos, lsr #3
+	ldp	data1, data2, [src, #-32]
+	stp	data1, data2, [dst, #-16]
+#ifdef BUILD_STPCPY
+	sub	dstin, dst, #1
+#endif
+	ret
+
+.Lpage_cross:
+	bic	src, srcin, #15
+	/* Start by loading two words at [srcin & ~15], then forcing the
+	   bytes that precede srcin to 0xff.  This means they never look
+	   like termination bytes.  */
+	ldp	data1, data2, [src]
+	lsl	tmp1, tmp1, #3	/* Bytes beyond alignment -> bits.  */
+	tst	to_align, #7
+	csetm	tmp2, ne
+#ifdef __AARCH64EB__
+	lsl	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#else
+	lsr	tmp2, tmp2, tmp1	/* Shift (tmp1 & 63).  */
+#endif
+	orr	data1, data1, tmp2
+	orr	data2a, data2, tmp2
+	cmp	to_align, #8
+	csinv	data1, data1, xzr, lt
+	csel	data2, data2, data2a, lt
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+	bic	has_nul1, tmp1, tmp2
+	bics	has_nul2, tmp3, tmp4
+	ccmp	has_nul1, #0, #0, eq	/* NZCV = 0000  */
+	b.eq	.Lpage_cross_ok
+	/* We now need to make data1 and data2 look like they've been
+	   loaded directly from srcin.  Do a rotate on the 128-bit value.  */
+	lsl	tmp1, to_align, #3	/* Bytes->bits.  */
+	neg	tmp2, to_align, lsl #3
+#ifdef __AARCH64EB__
+	lsl	data1a, data1, tmp1
+	lsr	tmp4, data2, tmp2
+	lsl	data2, data2, tmp1
+	orr	tmp4, tmp4, data1a
+	cmp	to_align, #8
+	csel	data1, tmp4, data2, lt
+	rev	tmp2, data1
+	rev	tmp4, data2
+	sub	tmp1, tmp2, zeroones
+	orr	tmp2, tmp2, #REP8_7f
+	sub	tmp3, tmp4, zeroones
+	orr	tmp4, tmp4, #REP8_7f
+#else
+	lsr	data1a, data1, tmp1
+	lsl	tmp4, data2, tmp2
+	lsr	data2, data2, tmp1
+	orr	tmp4, tmp4, data1a
+	cmp	to_align, #8
+	csel	data1, tmp4, data2, lt
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+#endif
+	bic	has_nul1, tmp1, tmp2
+	cbnz	has_nul1, .Lfp_le8
+	bic	has_nul2, tmp3, tmp4
+	b	.Lfp_gt8
+
+	.size	STRCPY, . - STRCPY
diff --git a/contrib/cortex-strings/src/aarch64/strlen.S b/contrib/cortex-strings/src/aarch64/strlen.S
new file mode 100644
index 000000000000..585064002309
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/strlen.S
@@ -0,0 +1,233 @@
+/* Copyright (c) 2013-2015, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+	 notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+	 notice, this list of conditions and the following disclaimer in the
+	 documentation and/or other materials provided with the distribution.
+       * Neither the name of the Linaro nor the
+	 names of its contributors may be used to endorse or promote products
+	 derived from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64, unaligned accesses, min page size 4k.
+ */
+
+/* To test the page crossing code path more thoroughly, compile with
+   -DTEST_PAGE_CROSS - this will force all calls through the slower
+   entry path.  This option is not intended for production use.	 */
+
+/* Arguments and results.  */
+#define srcin		x0
+#define len		x0
+
+/* Locals and temporaries.  */
+#define src		x1
+#define data1		x2
+#define data2		x3
+#define has_nul1	x4
+#define has_nul2	x5
+#define tmp1		x4
+#define tmp2		x5
+#define tmp3		x6
+#define tmp4		x7
+#define zeroones	x8
+
+#define L(l) .L ## l
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word. A faster check
+	   (X - 1) & 0x80 is zero for non-NUL ASCII characters, but gives
+	   false hits for characters 129..255.	*/
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+#ifdef TEST_PAGE_CROSS
+# define MIN_PAGE_SIZE 15
+#else
+# define MIN_PAGE_SIZE 4096
+#endif
+
+	/* Since strings are short on average, we check the first 16 bytes
+	   of the string for a NUL character.  In order to do an unaligned ldp
+	   safely we have to do a page cross check first.  If there is a NUL
+	   byte we calculate the length from the 2 8-byte words using
+	   conditional select to reduce branch mispredictions (it is unlikely
+	   strlen will be repeatedly called on strings with the same length).
+
+	   If the string is longer than 16 bytes, we align src so don't need
+	   further page cross checks, and process 32 bytes per iteration
+	   using the fast NUL check.  If we encounter non-ASCII characters,
+	   fallback to a second loop using the full NUL check.
+
+	   If the page cross check fails, we read 16 bytes from an aligned
+	   address, remove any characters before the string, and continue
+	   in the main loop using aligned loads.  Since strings crossing a
+	   page in the first 16 bytes are rare (probability of
+	   16/MIN_PAGE_SIZE ~= 0.4%), this case does not need to be optimized.
+
+	   AArch64 systems have a minimum page size of 4k.  We don't bother
+	   checking for larger page sizes - the cost of setting up the correct
+	   page size is just not worth the extra gain from a small reduction in
+	   the cases taking the slow path.  Note that we only care about
+	   whether the first fetch, which may be misaligned, crosses a page
+	   boundary.  */
+
+def_fn strlen p2align=6
+	and	tmp1, srcin, MIN_PAGE_SIZE - 1
+	mov	zeroones, REP8_01
+	cmp	tmp1, MIN_PAGE_SIZE - 16
+	b.gt	L(page_cross)
+	ldp	data1, data2, [srcin]
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul1/2 directly.
+	   Since we expect strings to be small and early-exit,
+	   byte-swap the data now so has_null1/2 will be correct.  */
+	rev	data1, data1
+	rev	data2, data2
+#endif
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	beq	L(main_loop_entry)
+
+	/* Enter with C = has_nul1 == 0.  */
+	csel	has_nul1, has_nul1, has_nul2, cc
+	mov	len, 8
+	rev	has_nul1, has_nul1
+	clz	tmp1, has_nul1
+	csel	len, xzr, len, cc
+	add	len, len, tmp1, lsr 3
+	ret
+
+	/* The inner loop processes 32 bytes per iteration and uses the fast
+	   NUL check.  If we encounter non-ASCII characters, use a second
+	   loop with the accurate NUL check.  */
+	.p2align 4
+L(main_loop_entry):
+	bic	src, srcin, 15
+	sub	src, src, 16
+L(main_loop):
+	ldp	data1, data2, [src, 32]!
+.Lpage_cross_entry:
+	sub	tmp1, data1, zeroones
+	sub	tmp3, data2, zeroones
+	orr	tmp2, tmp1, tmp3
+	tst	tmp2, zeroones, lsl 7
+	bne	1f
+	ldp	data1, data2, [src, 16]
+	sub	tmp1, data1, zeroones
+	sub	tmp3, data2, zeroones
+	orr	tmp2, tmp1, tmp3
+	tst	tmp2, zeroones, lsl 7
+	beq	L(main_loop)
+	add	src, src, 16
+1:
+	/* The fast check failed, so do the slower, accurate NUL check.	 */
+	orr	tmp2, data1, REP8_7f
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	beq	L(nonascii_loop)
+
+	/* Enter with C = has_nul1 == 0.  */
+L(tail):
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul1/2 directly.  The
+	   easiest way to get the correct byte is to byte-swap the data
+	   and calculate the syndrome a second time.  */
+	csel	data1, data1, data2, cc
+	rev	data1, data1
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	bic	has_nul1, tmp1, tmp2
+#else
+	csel	has_nul1, has_nul1, has_nul2, cc
+#endif
+	sub	len, src, srcin
+	rev	has_nul1, has_nul1
+	add	tmp2, len, 8
+	clz	tmp1, has_nul1
+	csel	len, len, tmp2, cc
+	add	len, len, tmp1, lsr 3
+	ret
+
+L(nonascii_loop):
+	ldp	data1, data2, [src, 16]!
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	bne	L(tail)
+	ldp	data1, data2, [src, 16]!
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, REP8_7f
+	bics	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	ccmp	has_nul2, 0, 0, eq
+	beq	L(nonascii_loop)
+	b	L(tail)
+
+	/* Load 16 bytes from [srcin & ~15] and force the bytes that precede
+	   srcin to 0x7f, so we ignore any NUL bytes before the string.
+	   Then continue in the aligned loop.  */
+L(page_cross):
+	bic	src, srcin, 15
+	ldp	data1, data2, [src]
+	lsl	tmp1, srcin, 3
+	mov	tmp4, -1
+#ifdef __AARCH64EB__
+	/* Big-endian.	Early bytes are at MSB.	 */
+	lsr	tmp1, tmp4, tmp1	/* Shift (tmp1 & 63).  */
+#else
+	/* Little-endian.  Early bytes are at LSB.  */
+	lsl	tmp1, tmp4, tmp1	/* Shift (tmp1 & 63).  */
+#endif
+	orr	tmp1, tmp1, REP8_80
+	orn	data1, data1, tmp1
+	orn	tmp2, data2, tmp1
+	tst	srcin, 8
+	csel	data1, data1, tmp4, eq
+	csel	data2, data2, tmp2, eq
+	b	L(page_cross_entry)
+
+	.size	strlen, . - strlen
diff --git a/contrib/cortex-strings/src/aarch64/strncmp.S b/contrib/cortex-strings/src/aarch64/strncmp.S
new file mode 100644
index 000000000000..21367877fa4d
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/strncmp.S
@@ -0,0 +1,222 @@
+/* Copyright (c) 2013, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the Linaro nor the
+         names of its contributors may be used to endorse or promote products
+         derived from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ */
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+/* Parameters and result.  */
+#define src1		x0
+#define src2		x1
+#define limit		x2
+#define result		x0
+
+/* Internal variables.  */
+#define data1		x3
+#define data1w		w3
+#define data2		x4
+#define data2w		w4
+#define has_nul		x5
+#define diff		x6
+#define syndrome	x7
+#define tmp1		x8
+#define tmp2		x9
+#define tmp3		x10
+#define zeroones	x11
+#define pos		x12
+#define limit_wd	x13
+#define mask		x14
+#define endloop		x15
+
+	.text
+	.p2align 6
+	.rep 7
+	nop	/* Pad so that the loop below fits a cache line.  */
+	.endr
+def_fn strncmp
+	cbz	limit, .Lret0
+	eor	tmp1, src1, src2
+	mov	zeroones, #REP8_01
+	tst	tmp1, #7
+	b.ne	.Lmisaligned8
+	ands	tmp1, src1, #7
+	b.ne	.Lmutual_align
+	/* Calculate the number of full and partial words -1.  */
+	sub	limit_wd, limit, #1	/* limit != 0, so no underflow.  */
+	lsr	limit_wd, limit_wd, #3	/* Convert to Dwords.  */
+
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word.  */
+	/* Start of performance-critical section  -- one 64B cache line.  */
+.Lloop_aligned:
+	ldr	data1, [src1], #8
+	ldr	data2, [src2], #8
+.Lstart_realigned:
+	subs	limit_wd, limit_wd, #1
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	eor	diff, data1, data2	/* Non-zero if differences found.  */
+	csinv	endloop, diff, xzr, pl	/* Last Dword or differences.  */
+	bics	has_nul, tmp1, tmp2	/* Non-zero if NUL terminator.  */
+	ccmp	endloop, #0, #0, eq
+	b.eq	.Lloop_aligned
+	/* End of performance-critical section  -- one 64B cache line.  */
+
+	/* Not reached the limit, must have found the end or a diff.  */
+	tbz	limit_wd, #63, .Lnot_limit
+
+	/* Limit % 8 == 0 => all bytes significant.  */
+	ands	limit, limit, #7
+	b.eq	.Lnot_limit
+
+	lsl	limit, limit, #3	/* Bits -> bytes.  */
+	mov	mask, #~0
+#ifdef __AARCH64EB__
+	lsr	mask, mask, limit
+#else
+	lsl	mask, mask, limit
+#endif
+	bic	data1, data1, mask
+	bic	data2, data2, mask
+
+	/* Make sure that the NUL byte is marked in the syndrome.  */
+	orr	has_nul, has_nul, mask
+
+.Lnot_limit:
+	orr	syndrome, diff, has_nul
+
+#ifndef	__AARCH64EB__
+	rev	syndrome, syndrome
+	rev	data1, data1
+	/* The MS-non-zero bit of the syndrome marks either the first bit
+	   that is different, or the top bit of the first zero byte.
+	   Shifting left now will bring the critical information into the
+	   top bits.  */
+	clz	pos, syndrome
+	rev	data2, data2
+	lsl	data1, data1, pos
+	lsl	data2, data2, pos
+	/* But we need to zero-extend (char is unsigned) the value and then
+	   perform a signed 32-bit subtraction.  */
+	lsr	data1, data1, #56
+	sub	result, data1, data2, lsr #56
+	ret
+#else
+	/* For big-endian we cannot use the trick with the syndrome value
+	   as carry-propagation can corrupt the upper bits if the trailing
+	   bytes in the string contain 0x01.  */
+	/* However, if there is no NUL byte in the dword, we can generate
+	   the result directly.  We can't just subtract the bytes as the
+	   MSB might be significant.  */
+	cbnz	has_nul, 1f
+	cmp	data1, data2
+	cset	result, ne
+	cneg	result, result, lo
+	ret
+1:
+	/* Re-compute the NUL-byte detection, using a byte-reversed value.  */
+	rev	tmp3, data1
+	sub	tmp1, tmp3, zeroones
+	orr	tmp2, tmp3, #REP8_7f
+	bic	has_nul, tmp1, tmp2
+	rev	has_nul, has_nul
+	orr	syndrome, diff, has_nul
+	clz	pos, syndrome
+	/* The MS-non-zero bit of the syndrome marks either the first bit
+	   that is different, or the top bit of the first zero byte.
+	   Shifting left now will bring the critical information into the
+	   top bits.  */
+	lsl	data1, data1, pos
+	lsl	data2, data2, pos
+	/* But we need to zero-extend (char is unsigned) the value and then
+	   perform a signed 32-bit subtraction.  */
+	lsr	data1, data1, #56
+	sub	result, data1, data2, lsr #56
+	ret
+#endif
+
+.Lmutual_align:
+	/* Sources are mutually aligned, but are not currently at an
+	   alignment boundary.  Round down the addresses and then mask off
+	   the bytes that precede the start point.
+	   We also need to adjust the limit calculations, but without
+	   overflowing if the limit is near ULONG_MAX.  */
+	bic	src1, src1, #7
+	bic	src2, src2, #7
+	ldr	data1, [src1], #8
+	neg	tmp3, tmp1, lsl #3	/* 64 - bits(bytes beyond align). */
+	ldr	data2, [src2], #8
+	mov	tmp2, #~0
+	sub	limit_wd, limit, #1	/* limit != 0, so no underflow.  */
+#ifdef __AARCH64EB__
+	/* Big-endian.  Early bytes are at MSB.  */
+	lsl	tmp2, tmp2, tmp3	/* Shift (tmp1 & 63).  */
+#else
+	/* Little-endian.  Early bytes are at LSB.  */
+	lsr	tmp2, tmp2, tmp3	/* Shift (tmp1 & 63).  */
+#endif
+	and	tmp3, limit_wd, #7
+	lsr	limit_wd, limit_wd, #3
+	/* Adjust the limit. Only low 3 bits used, so overflow irrelevant.  */
+	add	limit, limit, tmp1
+	add	tmp3, tmp3, tmp1
+	orr	data1, data1, tmp2
+	orr	data2, data2, tmp2
+	add	limit_wd, limit_wd, tmp3, lsr #3
+	b	.Lstart_realigned
+
+.Lret0:
+	mov	result, #0
+	ret
+
+	.p2align 6
+.Lmisaligned8:
+	sub	limit, limit, #1
+1:
+	/* Perhaps we can do better than this.  */
+	ldrb	data1w, [src1], #1
+	ldrb	data2w, [src2], #1
+	subs	limit, limit, #1
+	ccmp	data1w, #1, #0, cs	/* NZCV = 0b0000.  */
+	ccmp	data1w, data2w, #0, cs	/* NZCV = 0b0000.  */
+	b.eq	1b
+	sub	result, data1, data2
+	ret
+	.size strncmp, . - strncmp
diff --git a/contrib/cortex-strings/src/aarch64/strnlen.S b/contrib/cortex-strings/src/aarch64/strnlen.S
new file mode 100644
index 000000000000..c0e609871839
--- /dev/null
+++ b/contrib/cortex-strings/src/aarch64/strnlen.S
@@ -0,0 +1,181 @@
+/* strnlen - calculate the length of a string with limit.
+
+   Copyright (c) 2013, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+       * Redistributions of source code must retain the above copyright
+         notice, this list of conditions and the following disclaimer.
+       * Redistributions in binary form must reproduce the above copyright
+         notice, this list of conditions and the following disclaimer in the
+         documentation and/or other materials provided with the distribution.
+       * Neither the name of the Linaro nor the
+         names of its contributors may be used to endorse or promote products
+         derived from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/* Assumptions:
+ *
+ * ARMv8-a, AArch64
+ */
+
+/* Arguments and results.  */
+#define srcin		x0
+#define len		x0
+#define limit		x1
+
+/* Locals and temporaries.  */
+#define src		x2
+#define data1		x3
+#define data2		x4
+#define data2a		x5
+#define has_nul1	x6
+#define has_nul2	x7
+#define tmp1		x8
+#define tmp2		x9
+#define tmp3		x10
+#define tmp4		x11
+#define zeroones	x12
+#define pos		x13
+#define limit_wd	x14
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+#define REP8_01 0x0101010101010101
+#define REP8_7f 0x7f7f7f7f7f7f7f7f
+#define REP8_80 0x8080808080808080
+
+	.text
+	.p2align	6
+.Lstart:
+	/* Pre-pad to ensure critical loop begins an icache line.  */
+	.rep 7
+	nop
+	.endr
+	/* Put this code here to avoid wasting more space with pre-padding.  */
+.Lhit_limit:
+	mov	len, limit
+	ret
+
+def_fn strnlen
+	cbz	limit, .Lhit_limit
+	mov	zeroones, #REP8_01
+	bic	src, srcin, #15
+	ands	tmp1, srcin, #15
+	b.ne	.Lmisaligned
+	/* Calculate the number of full and partial words -1.  */
+	sub	limit_wd, limit, #1	/* Limit != 0, so no underflow.  */
+	lsr	limit_wd, limit_wd, #4	/* Convert to Qwords.  */
+
+	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
+	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
+	   can be done in parallel across the entire word.  */
+	/* The inner loop deals with two Dwords at a time.  This has a
+	   slightly higher start-up cost, but we should win quite quickly,
+	   especially on cores with a high number of issue slots per
+	   cycle, as we get much better parallelism out of the operations.  */
+
+	/* Start of critial section -- keep to one 64Byte cache line.  */
+.Lloop:
+	ldp	data1, data2, [src], #16
+.Lrealigned:
+	sub	tmp1, data1, zeroones
+	orr	tmp2, data1, #REP8_7f
+	sub	tmp3, data2, zeroones
+	orr	tmp4, data2, #REP8_7f
+	bic	has_nul1, tmp1, tmp2
+	bic	has_nul2, tmp3, tmp4
+	subs	limit_wd, limit_wd, #1
+	orr	tmp1, has_nul1, has_nul2
+	ccmp	tmp1, #0, #0, pl	/* NZCV = 0000  */
+	b.eq	.Lloop
+	/* End of critical section -- keep to one 64Byte cache line.  */
+
+	orr	tmp1, has_nul1, has_nul2
+	cbz	tmp1, .Lhit_limit	/* No null in final Qword.  */
+
+	/* We know there's a null in the final Qword.  The easiest thing
+	   to do now is work out the length of the string and return
+	   MIN (len, limit).  */
+
+	sub	len, src, srcin
+	cbz	has_nul1, .Lnul_in_data2
+#ifdef __AARCH64EB__
+	mov	data2, data1
+#endif
+	sub	len, len, #8
+	mov	has_nul2, has_nul1
+.Lnul_in_data2:
+#ifdef __AARCH64EB__
+	/* For big-endian, carry propagation (if the final byte in the
+	   string is 0x01) means we cannot use has_nul directly.  The
+	   easiest way to get the correct byte is to byte-swap the data
+	   and calculate the syndrome a second time.  */
+	rev	data2, data2
+	sub	tmp1, data2, zeroones
+	orr	tmp2, data2, #REP8_7f
+	bic	has_nul2, tmp1, tmp2
+#endif
+	sub	len, len, #8
+	rev	has_nul2, has_nul2
+	clz	pos, has_nul2
+	add	len, len, pos, lsr #3		/* Bits to bytes.  */
+	cmp	len, limit
+	csel	len, len, limit, ls		/* Return the lower value.  */
+	ret
+
+.Lmisaligned:
+	/* Deal with a partial first word.
+	   We're doing two things in parallel here;
+	   1) Calculate the number of words (but avoiding overflow if
+	      limit is near ULONG_MAX) - to do this we need to work out
+	      limit + tmp1 - 1 as a 65-bit value before shifting it;
+	   2) Load and mask the initial data words - we force the bytes
+	      before the ones we are interested in to 0xff - this ensures
+	      early bytes will not hit any zero detection.  */
+	sub	limit_wd, limit, #1
+	neg	tmp4, tmp1
+	cmp	tmp1, #8
+
+	and	tmp3, limit_wd, #15
+	lsr	limit_wd, limit_wd, #4
+	mov	tmp2, #~0
+
+	ldp	data1, data2, [src], #16
+	lsl	tmp4, tmp4, #3		/* Bytes beyond alignment -> bits.  */
+	add	tmp3, tmp3, tmp1
+
+#ifdef __AARCH64EB__
+	/* Big-endian.  Early bytes are at MSB.  */
+	lsl	tmp2, tmp2, tmp4	/* Shift (tmp1 & 63).  */
+#else
+	/* Little-endian.  Early bytes are at LSB.  */
+	lsr	tmp2, tmp2, tmp4	/* Shift (tmp1 & 63).  */
+#endif
+	add	limit_wd, limit_wd, tmp3, lsr #4
+
+	orr	data1, data1, tmp2
+	orr	data2a, data2, tmp2
+
+	csinv	data1, data1, xzr, le
+	csel	data2, data2, data2a, le
+	b	.Lrealigned
+	.size	strnlen, . - .Lstart	/* Include pre-padding in size.  */
diff --git a/contrib/cortex-strings/src/arm/memchr.S b/contrib/cortex-strings/src/arm/memchr.S
new file mode 100644
index 000000000000..92a2d9f0967d
--- /dev/null
+++ b/contrib/cortex-strings/src/arm/memchr.S
@@ -0,0 +1,155 @@
+/* Copyright (c) 2010-2011, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+      * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+      * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+
+      * Neither the name of Linaro Limited nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+   Written by Dave Gilbert <david.gilbert@linaro.org>
+
+   This memchr routine is optimised on a Cortex-A9 and should work on
+   all ARMv7 processors.   It has a fast past for short sizes, and has
+   an optimised path for large data sets; the worst case is finding the
+   match early in a large data set.
+
+ */
+
+@ 2011-02-07 david.gilbert@linaro.org
+@    Extracted from local git a5b438d861
+@ 2011-07-14 david.gilbert@linaro.org
+@    Import endianness fix from local git ea786f1b
+@ 2011-12-07 david.gilbert@linaro.org
+@    Removed unneeded cbz from align loop
+
+	.syntax unified
+	.arch armv7-a
+
+@ this lets us check a flag in a 00/ff byte easily in either endianness
+#ifdef __ARMEB__
+#define CHARTSTMASK(c) 1<<(31-(c*8))
+#else
+#define CHARTSTMASK(c) 1<<(c*8)
+#endif
+	.text
+	.thumb
+
+@ ---------------------------------------------------------------------------
+	.thumb_func
+	.align 2
+	.p2align 4,,15
+	.global memchr
+	.type memchr,%function
+memchr:
+	@ r0 = start of memory to scan
+	@ r1 = character to look for
+	@ r2 = length
+	@ returns r0 = pointer to character or NULL if not found
+	and	r1,r1,#0xff	@ Don't think we can trust the caller to actually pass a char
+
+	cmp	r2,#16		@ If it's short don't bother with anything clever
+	blt	20f 
+
+	tst	r0, #7		@ If it's already aligned skip the next bit
+	beq	10f
+
+	@ Work up to an aligned point
+5:
+	ldrb	r3, [r0],#1
+	subs	r2, r2, #1
+	cmp	r3, r1
+	beq	50f		@ If it matches exit found
+	tst	r0, #7
+	bne	5b		@ If not aligned yet then do next byte
+	
+10:
+	@ At this point, we are aligned, we know we have at least 8 bytes to work with
+	push	{r4,r5,r6,r7}
+	orr	r1, r1, r1, lsl #8	@ expand the match word across to all bytes
+	orr	r1, r1, r1, lsl #16
+	bic	r4, r2, #7	@ Number of double words to work with
+	mvns	r7, #0		@ all F's
+	movs	r3, #0
+	
+15:
+	ldmia	r0!,{r5,r6}
+	subs	r4, r4, #8
+	eor	r5,r5, r1	@ Get it so that r5,r6 have 00's where the bytes match the target
+	eor	r6,r6, r1
+	uadd8	r5, r5, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
+	sel	r5, r3, r7	@ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
+	uadd8	r6, r6, r7	@ Parallel add 0xff - sets the GE bits for anything that wasn't 0
+	sel	r6, r5, r7	@ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
+	cbnz	r6, 60f
+	bne	15b		@ (Flags from the subs above) If not run out of bytes then go around again
+
+	pop	{r4,r5,r6,r7}
+	and	r1,r1,#0xff	@ Get r1 back to a single character from the expansion above
+	and	r2,r2,#7	@ Leave the count remaining as the number after the double words have been done
+ 
+20:
+	cbz	r2, 40f		@ 0 length or hit the end already then not found
+
+21:  @ Post aligned section, or just a short call
+	ldrb	r3,[r0],#1
+	subs	r2,r2,#1
+	eor	r3,r3,r1	@ r3 = 0 if match - doesn't break flags from sub
+	cbz	r3, 50f
+	bne	21b		@ on r2 flags
+
+40:
+	movs	r0,#0		@ not found
+	bx	lr
+
+50:
+	subs	r0,r0,#1	@ found
+	bx	lr
+
+60:  @ We're here because the fast path found a hit - now we have to track down exactly which word it was
+	@ r0 points to the start of the double word after the one that was tested
+	@ r5 has the 00/ff pattern for the first word, r6 has the chained value
+	cmp	r5, #0
+	itte	eq
+	moveq	r5, r6		@ the end is in the 2nd word
+	subeq	r0,r0,#3	@ Points to 2nd byte of 2nd word
+	subne	r0,r0,#7	@ or 2nd byte of 1st word
+
+	@ r0 currently points to the 3rd byte of the word containing the hit
+	tst	r5, # CHARTSTMASK(0)	@ 1st character
+	bne	61f
+	adds	r0,r0,#1
+	tst	r5, # CHARTSTMASK(1)	@ 2nd character
+	ittt	eq
+	addeq	r0,r0,#1
+	tsteq	r5, # (3<<15)		@ 2nd & 3rd character
+	@ If not the 3rd must be the last one
+	addeq	r0,r0,#1
+
+61:
+	pop	{r4,r5,r6,r7}
+	subs	r0,r0,#1
+	bx	lr
diff --git a/contrib/cortex-strings/src/arm/memcpy.S b/contrib/cortex-strings/src/arm/memcpy.S
new file mode 100644
index 000000000000..dd405ec13925
--- /dev/null
+++ b/contrib/cortex-strings/src/arm/memcpy.S
@@ -0,0 +1,617 @@
+/* Copyright (c) 2013, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+      * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+      * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+
+      * Neither the name of Linaro Limited nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+   This memcpy routine is optimised for Cortex-A15 cores and takes advantage
+   of VFP or NEON when built with the appropriate flags.
+
+   Assumptions:
+
+    ARMv6 (ARMv7-a if using Neon)
+    ARM state
+    Unaligned accesses
+
+ */
+
+	.syntax unified
+	/* This implementation requires ARM state.  */
+	.arm
+
+#ifdef __ARM_NEON__
+
+	.fpu	neon
+	.arch	armv7-a
+# define FRAME_SIZE	4
+# define USE_VFP
+# define USE_NEON
+
+#elif !defined (__SOFTFP__)
+
+	.arch	armv6
+	.fpu	vfpv2
+# define FRAME_SIZE	32
+# define USE_VFP
+
+#else
+	.arch	armv6
+# define FRAME_SIZE    32
+
+#endif
+
+/* Old versions of GAS incorrectly implement the NEON align semantics.  */
+#ifdef BROKEN_ASM_NEON_ALIGN
+#define ALIGN(addr, align) addr,:align
+#else
+#define ALIGN(addr, align) addr:align
+#endif
+
+#define PC_OFFSET	8	/* PC pipeline compensation.  */
+#define INSN_SIZE	4
+
+/* Call parameters.  */
+#define dstin	r0
+#define src	r1
+#define count	r2
+
+/* Locals.  */
+#define tmp1	r3
+#define dst	ip
+#define tmp2	r10
+
+#ifndef USE_NEON
+/* For bulk copies using GP registers.  */
+#define	A_l	r2		/* Call-clobbered.  */
+#define	A_h	r3		/* Call-clobbered.  */
+#define	B_l	r4
+#define	B_h	r5
+#define	C_l	r6
+#define	C_h	r7
+#define	D_l	r8
+#define	D_h	r9
+#endif
+
+/* Number of lines ahead to pre-fetch data.  If you change this the code
+   below will need adjustment to compensate.  */
+
+#define prefetch_lines	5
+
+#ifdef USE_VFP
+	.macro	cpy_line_vfp vreg, base
+	vstr	\vreg, [dst, #\base]
+	vldr	\vreg, [src, #\base]
+	vstr	d0, [dst, #\base + 8]
+	vldr	d0, [src, #\base + 8]
+	vstr	d1, [dst, #\base + 16]
+	vldr	d1, [src, #\base + 16]
+	vstr	d2, [dst, #\base + 24]
+	vldr	d2, [src, #\base + 24]
+	vstr	\vreg, [dst, #\base + 32]
+	vldr	\vreg, [src, #\base + prefetch_lines * 64 - 32]
+	vstr	d0, [dst, #\base + 40]
+	vldr	d0, [src, #\base + 40]
+	vstr	d1, [dst, #\base + 48]
+	vldr	d1, [src, #\base + 48]
+	vstr	d2, [dst, #\base + 56]
+	vldr	d2, [src, #\base + 56]
+	.endm
+
+	.macro	cpy_tail_vfp vreg, base
+	vstr	\vreg, [dst, #\base]
+	vldr	\vreg, [src, #\base]
+	vstr	d0, [dst, #\base + 8]
+	vldr	d0, [src, #\base + 8]
+	vstr	d1, [dst, #\base + 16]
+	vldr	d1, [src, #\base + 16]
+	vstr	d2, [dst, #\base + 24]
+	vldr	d2, [src, #\base + 24]
+	vstr	\vreg, [dst, #\base + 32]
+	vstr	d0, [dst, #\base + 40]
+	vldr	d0, [src, #\base + 40]
+	vstr	d1, [dst, #\base + 48]
+	vldr	d1, [src, #\base + 48]
+	vstr	d2, [dst, #\base + 56]
+	vldr	d2, [src, #\base + 56]
+	.endm
+#endif
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+def_fn memcpy p2align=6
+
+	mov	dst, dstin	/* Preserve dstin, we need to return it.  */
+	cmp	count, #64
+	bge	.Lcpy_not_short
+	/* Deal with small copies quickly by dropping straight into the
+	   exit block.  */
+
+.Ltail63unaligned:
+#ifdef USE_NEON
+	and	tmp1, count, #0x38
+	rsb	tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
+	add	pc, pc, tmp1
+	vld1.8	{d0}, [src]!	/* 14 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 12 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 10 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 8 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 6 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 4 words to go.  */
+	vst1.8	{d0}, [dst]!
+	vld1.8	{d0}, [src]!	/* 2 words to go.  */
+	vst1.8	{d0}, [dst]!
+
+	tst	count, #4
+	ldrne	tmp1, [src], #4
+	strne	tmp1, [dst], #4
+#else
+	/* Copy up to 15 full words of data.  May not be aligned.  */
+	/* Cannot use VFP for unaligned data.  */
+	and	tmp1, count, #0x3c
+	add	dst, dst, tmp1
+	add	src, src, tmp1
+	rsb	tmp1, tmp1, #(60 - PC_OFFSET/2 + INSN_SIZE/2)
+	/* Jump directly into the sequence below at the correct offset.  */
+	add	pc, pc, tmp1, lsl #1
+
+	ldr	tmp1, [src, #-60]	/* 15 words to go.  */
+	str	tmp1, [dst, #-60]
+
+	ldr	tmp1, [src, #-56]	/* 14 words to go.  */
+	str	tmp1, [dst, #-56]
+	ldr	tmp1, [src, #-52]
+	str	tmp1, [dst, #-52]
+
+	ldr	tmp1, [src, #-48]	/* 12 words to go.  */
+	str	tmp1, [dst, #-48]
+	ldr	tmp1, [src, #-44]
+	str	tmp1, [dst, #-44]
+
+	ldr	tmp1, [src, #-40]	/* 10 words to go.  */
+	str	tmp1, [dst, #-40]
+	ldr	tmp1, [src, #-36]
+	str	tmp1, [dst, #-36]
+
+	ldr	tmp1, [src, #-32]	/* 8 words to go.  */
+	str	tmp1, [dst, #-32]
+	ldr	tmp1, [src, #-28]
+	str	tmp1, [dst, #-28]
+
+	ldr	tmp1, [src, #-24]	/* 6 words to go.  */
+	str	tmp1, [dst, #-24]
+	ldr	tmp1, [src, #-20]
+	str	tmp1, [dst, #-20]
+
+	ldr	tmp1, [src, #-16]	/* 4 words to go.  */
+	str	tmp1, [dst, #-16]
+	ldr	tmp1, [src, #-12]
+	str	tmp1, [dst, #-12]
+
+	ldr	tmp1, [src, #-8]	/* 2 words to go.  */
+	str	tmp1, [dst, #-8]
+	ldr	tmp1, [src, #-4]
+	str	tmp1, [dst, #-4]
+#endif
+
+	lsls	count, count, #31
+	ldrhcs	tmp1, [src], #2
+	ldrbne	src, [src]		/* Src is dead, use as a scratch.  */
+	strhcs	tmp1, [dst], #2
+	strbne	src, [dst]
+	bx	lr
+
+.Lcpy_not_short:
+	/* At least 64 bytes to copy, but don't know the alignment yet.  */
+	str	tmp2, [sp, #-FRAME_SIZE]!
+	and	tmp2, src, #7
+	and	tmp1, dst, #7
+	cmp	tmp1, tmp2
+	bne	.Lcpy_notaligned
+
+#ifdef USE_VFP
+	/* Magic dust alert!  Force VFP on Cortex-A9.  Experiments show
+	   that the FP pipeline is much better at streaming loads and
+	   stores.  This is outside the critical loop.  */
+	vmov.f32	s0, s0
+#endif
+
+	/* SRC and DST have the same mutual 64-bit alignment, but we may
+	   still need to pre-copy some bytes to get to natural alignment.
+	   We bring SRC and DST into full 64-bit alignment.  */
+	lsls	tmp2, dst, #29
+	beq	1f
+	rsbs	tmp2, tmp2, #0
+	sub	count, count, tmp2, lsr #29
+	ldrmi	tmp1, [src], #4
+	strmi	tmp1, [dst], #4
+	lsls	tmp2, tmp2, #2
+	ldrhcs	tmp1, [src], #2
+	ldrbne	tmp2, [src], #1
+	strhcs	tmp1, [dst], #2
+	strbne	tmp2, [dst], #1
+
+1:
+	subs	tmp2, count, #64	/* Use tmp2 for count.  */
+	blt	.Ltail63aligned
+
+	cmp	tmp2, #512
+	bge	.Lcpy_body_long
+
+.Lcpy_body_medium:			/* Count in tmp2.  */
+#ifdef USE_VFP
+1:
+	vldr	d0, [src, #0]
+	subs	tmp2, tmp2, #64
+	vldr	d1, [src, #8]
+	vstr	d0, [dst, #0]
+	vldr	d0, [src, #16]
+	vstr	d1, [dst, #8]
+	vldr	d1, [src, #24]
+	vstr	d0, [dst, #16]
+	vldr	d0, [src, #32]
+	vstr	d1, [dst, #24]
+	vldr	d1, [src, #40]
+	vstr	d0, [dst, #32]
+	vldr	d0, [src, #48]
+	vstr	d1, [dst, #40]
+	vldr	d1, [src, #56]
+	vstr	d0, [dst, #48]
+	add	src, src, #64
+	vstr	d1, [dst, #56]
+	add	dst, dst, #64
+	bge	1b
+	tst	tmp2, #0x3f
+	beq	.Ldone
+
+.Ltail63aligned:			/* Count in tmp2.  */
+	and	tmp1, tmp2, #0x38
+	add	dst, dst, tmp1
+	add	src, src, tmp1
+	rsb	tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
+	add	pc, pc, tmp1
+
+	vldr	d0, [src, #-56]	/* 14 words to go.  */
+	vstr	d0, [dst, #-56]
+	vldr	d0, [src, #-48]	/* 12 words to go.  */
+	vstr	d0, [dst, #-48]
+	vldr	d0, [src, #-40]	/* 10 words to go.  */
+	vstr	d0, [dst, #-40]
+	vldr	d0, [src, #-32]	/* 8 words to go.  */
+	vstr	d0, [dst, #-32]
+	vldr	d0, [src, #-24]	/* 6 words to go.  */
+	vstr	d0, [dst, #-24]
+	vldr	d0, [src, #-16]	/* 4 words to go.  */
+	vstr	d0, [dst, #-16]
+	vldr	d0, [src, #-8]	/* 2 words to go.  */
+	vstr	d0, [dst, #-8]
+#else
+	sub	src, src, #8
+	sub	dst, dst, #8
+1:
+	ldrd	A_l, A_h, [src, #8]
+	strd	A_l, A_h, [dst, #8]
+	ldrd	A_l, A_h, [src, #16]
+	strd	A_l, A_h, [dst, #16]
+	ldrd	A_l, A_h, [src, #24]
+	strd	A_l, A_h, [dst, #24]
+	ldrd	A_l, A_h, [src, #32]
+	strd	A_l, A_h, [dst, #32]
+	ldrd	A_l, A_h, [src, #40]
+	strd	A_l, A_h, [dst, #40]
+	ldrd	A_l, A_h, [src, #48]
+	strd	A_l, A_h, [dst, #48]
+	ldrd	A_l, A_h, [src, #56]
+	strd	A_l, A_h, [dst, #56]
+	ldrd	A_l, A_h, [src, #64]!
+	strd	A_l, A_h, [dst, #64]!
+	subs	tmp2, tmp2, #64
+	bge	1b
+	tst	tmp2, #0x3f
+	bne	1f
+	ldr	tmp2,[sp], #FRAME_SIZE
+	bx	lr
+1:
+	add	src, src, #8
+	add	dst, dst, #8
+
+.Ltail63aligned:			/* Count in tmp2.  */
+	/* Copy up to 7 d-words of data.  Similar to Ltail63unaligned, but
+	   we know that the src and dest are 64-bit aligned so we can use
+	   LDRD/STRD to improve efficiency.  */
+	/* TMP2 is now negative, but we don't care about that.  The bottom
+	   six bits still tell us how many bytes are left to copy.  */
+
+	and	tmp1, tmp2, #0x38
+	add	dst, dst, tmp1
+	add	src, src, tmp1
+	rsb	tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
+	add	pc, pc, tmp1
+	ldrd	A_l, A_h, [src, #-56]	/* 14 words to go.  */
+	strd	A_l, A_h, [dst, #-56]
+	ldrd	A_l, A_h, [src, #-48]	/* 12 words to go.  */
+	strd	A_l, A_h, [dst, #-48]
+	ldrd	A_l, A_h, [src, #-40]	/* 10 words to go.  */
+	strd	A_l, A_h, [dst, #-40]
+	ldrd	A_l, A_h, [src, #-32]	/* 8 words to go.  */
+	strd	A_l, A_h, [dst, #-32]
+	ldrd	A_l, A_h, [src, #-24]	/* 6 words to go.  */
+	strd	A_l, A_h, [dst, #-24]
+	ldrd	A_l, A_h, [src, #-16]	/* 4 words to go.  */
+	strd	A_l, A_h, [dst, #-16]
+	ldrd	A_l, A_h, [src, #-8]	/* 2 words to go.  */
+	strd	A_l, A_h, [dst, #-8]
+
+#endif
+	tst	tmp2, #4
+	ldrne	tmp1, [src], #4
+	strne	tmp1, [dst], #4
+	lsls	tmp2, tmp2, #31		/* Count (tmp2) now dead. */
+	ldrhcs	tmp1, [src], #2
+	ldrbne	tmp2, [src]
+	strhcs	tmp1, [dst], #2
+	strbne	tmp2, [dst]
+
+.Ldone:
+	ldr	tmp2, [sp], #FRAME_SIZE
+	bx	lr
+
+.Lcpy_body_long:			/* Count in tmp2.  */
+
+	/* Long copy.  We know that there's at least (prefetch_lines * 64)
+	   bytes to go.  */
+#ifdef USE_VFP
+	/* Don't use PLD.  Instead, read some data in advance of the current
+	   copy position into a register.  This should act like a PLD
+	   operation but we won't have to repeat the transfer.  */
+
+	vldr	d3, [src, #0]
+	vldr	d4, [src, #64]
+	vldr	d5, [src, #128]
+	vldr	d6, [src, #192]
+	vldr	d7, [src, #256]
+
+	vldr	d0, [src, #8]
+	vldr	d1, [src, #16]
+	vldr	d2, [src, #24]
+	add	src, src, #32
+
+	subs	tmp2, tmp2, #prefetch_lines * 64 * 2
+	blt	2f
+1:
+	cpy_line_vfp	d3, 0
+	cpy_line_vfp	d4, 64
+	cpy_line_vfp	d5, 128
+	add	dst, dst, #3 * 64
+	add	src, src, #3 * 64
+	cpy_line_vfp	d6, 0
+	cpy_line_vfp	d7, 64
+	add	dst, dst, #2 * 64
+	add	src, src, #2 * 64
+	subs	tmp2, tmp2, #prefetch_lines * 64
+	bge	1b
+
+2:
+	cpy_tail_vfp	d3, 0
+	cpy_tail_vfp	d4, 64
+	cpy_tail_vfp	d5, 128
+	add	src, src, #3 * 64
+	add	dst, dst, #3 * 64
+	cpy_tail_vfp	d6, 0
+	vstr	d7, [dst, #64]
+	vldr	d7, [src, #64]
+	vstr	d0, [dst, #64 + 8]
+	vldr	d0, [src, #64 + 8]
+	vstr	d1, [dst, #64 + 16]
+	vldr	d1, [src, #64 + 16]
+	vstr	d2, [dst, #64 + 24]
+	vldr	d2, [src, #64 + 24]
+	vstr	d7, [dst, #64 + 32]
+	add	src, src, #96
+	vstr	d0, [dst, #64 + 40]
+	vstr	d1, [dst, #64 + 48]
+	vstr	d2, [dst, #64 + 56]
+	add	dst, dst, #128
+	add	tmp2, tmp2, #prefetch_lines * 64
+	b	.Lcpy_body_medium
+#else
+	/* Long copy.  Use an SMS style loop to maximize the I/O
+	   bandwidth of the core.  We don't have enough spare registers
+	   to synthesise prefetching, so use PLD operations.  */
+	/* Pre-bias src and dst.  */
+	sub	src, src, #8
+	sub	dst, dst, #8
+	pld	[src, #8]
+	pld	[src, #72]
+	subs	tmp2, tmp2, #64
+	pld	[src, #136]
+	ldrd	A_l, A_h, [src, #8]
+	strd	B_l, B_h, [sp, #8]
+	ldrd	B_l, B_h, [src, #16]
+	strd	C_l, C_h, [sp, #16]
+	ldrd	C_l, C_h, [src, #24]
+	strd	D_l, D_h, [sp, #24]
+	pld	[src, #200]
+	ldrd	D_l, D_h, [src, #32]!
+	b	1f
+	.p2align	6
+2:
+	pld	[src, #232]
+	strd	A_l, A_h, [dst, #40]
+	ldrd	A_l, A_h, [src, #40]
+	strd	B_l, B_h, [dst, #48]
+	ldrd	B_l, B_h, [src, #48]
+	strd	C_l, C_h, [dst, #56]
+	ldrd	C_l, C_h, [src, #56]
+	strd	D_l, D_h, [dst, #64]!
+	ldrd	D_l, D_h, [src, #64]!
+	subs	tmp2, tmp2, #64
+1:
+	strd	A_l, A_h, [dst, #8]
+	ldrd	A_l, A_h, [src, #8]
+	strd	B_l, B_h, [dst, #16]
+	ldrd	B_l, B_h, [src, #16]
+	strd	C_l, C_h, [dst, #24]
+	ldrd	C_l, C_h, [src, #24]
+	strd	D_l, D_h, [dst, #32]
+	ldrd	D_l, D_h, [src, #32]
+	bcs	2b
+	/* Save the remaining bytes and restore the callee-saved regs.  */
+	strd	A_l, A_h, [dst, #40]
+	add	src, src, #40
+	strd	B_l, B_h, [dst, #48]
+	ldrd	B_l, B_h, [sp, #8]
+	strd	C_l, C_h, [dst, #56]
+	ldrd	C_l, C_h, [sp, #16]
+	strd	D_l, D_h, [dst, #64]
+	ldrd	D_l, D_h, [sp, #24]
+	add	dst, dst, #72
+	tst	tmp2, #0x3f
+	bne	.Ltail63aligned
+	ldr	tmp2, [sp], #FRAME_SIZE
+	bx	lr
+#endif
+
+.Lcpy_notaligned:
+	pld	[src]
+	pld	[src, #64]
+	/* There's at least 64 bytes to copy, but there is no mutual
+	   alignment.  */
+	/* Bring DST to 64-bit alignment.  */
+	lsls	tmp2, dst, #29
+	pld	[src, #(2 * 64)]
+	beq	1f
+	rsbs	tmp2, tmp2, #0
+	sub	count, count, tmp2, lsr #29
+	ldrmi	tmp1, [src], #4
+	strmi	tmp1, [dst], #4
+	lsls	tmp2, tmp2, #2
+	ldrbne	tmp1, [src], #1
+	ldrhcs	tmp2, [src], #2
+	strbne	tmp1, [dst], #1
+	strhcs	tmp2, [dst], #2
+1:
+	pld	[src, #(3 * 64)]
+	subs	count, count, #64
+	ldrmi	tmp2, [sp], #FRAME_SIZE
+	bmi	.Ltail63unaligned
+	pld	[src, #(4 * 64)]
+
+#ifdef USE_NEON
+	vld1.8	{d0-d3}, [src]!
+	vld1.8	{d4-d7}, [src]!
+	subs	count, count, #64
+	bmi	2f
+1:
+	pld	[src, #(4 * 64)]
+	vst1.8	{d0-d3}, [ALIGN (dst, 64)]!
+	vld1.8	{d0-d3}, [src]!
+	vst1.8	{d4-d7}, [ALIGN (dst, 64)]!
+	vld1.8	{d4-d7}, [src]!
+	subs	count, count, #64
+	bpl	1b
+2:
+	vst1.8	{d0-d3}, [ALIGN (dst, 64)]!
+	vst1.8	{d4-d7}, [ALIGN (dst, 64)]!
+	ands	count, count, #0x3f
+#else
+	/* Use an SMS style loop to maximize the I/O bandwidth.  */
+	sub	src, src, #4
+	sub	dst, dst, #8
+	subs	tmp2, count, #64	/* Use tmp2 for count.  */
+	ldr	A_l, [src, #4]
+	ldr	A_h, [src, #8]
+	strd	B_l, B_h, [sp, #8]
+	ldr	B_l, [src, #12]
+	ldr	B_h, [src, #16]
+	strd	C_l, C_h, [sp, #16]
+	ldr	C_l, [src, #20]
+	ldr	C_h, [src, #24]
+	strd	D_l, D_h, [sp, #24]
+	ldr	D_l, [src, #28]
+	ldr	D_h, [src, #32]!
+	b	1f
+	.p2align	6
+2:
+	pld	[src, #(5 * 64) - (32 - 4)]
+	strd	A_l, A_h, [dst, #40]
+	ldr	A_l, [src, #36]
+	ldr	A_h, [src, #40]
+	strd	B_l, B_h, [dst, #48]
+	ldr	B_l, [src, #44]
+	ldr	B_h, [src, #48]
+	strd	C_l, C_h, [dst, #56]
+	ldr	C_l, [src, #52]
+	ldr	C_h, [src, #56]
+	strd	D_l, D_h, [dst, #64]!
+	ldr	D_l, [src, #60]
+	ldr	D_h, [src, #64]!
+	subs	tmp2, tmp2, #64
+1:
+	strd	A_l, A_h, [dst, #8]
+	ldr	A_l, [src, #4]
+	ldr	A_h, [src, #8]
+	strd	B_l, B_h, [dst, #16]
+	ldr	B_l, [src, #12]
+	ldr	B_h, [src, #16]
+	strd	C_l, C_h, [dst, #24]
+	ldr	C_l, [src, #20]
+	ldr	C_h, [src, #24]
+	strd	D_l, D_h, [dst, #32]
+	ldr	D_l, [src, #28]
+	ldr	D_h, [src, #32]
+	bcs	2b
+
+	/* Save the remaining bytes and restore the callee-saved regs.  */
+	strd	A_l, A_h, [dst, #40]
+	add	src, src, #36
+	strd	B_l, B_h, [dst, #48]
+	ldrd	B_l, B_h, [sp, #8]
+	strd	C_l, C_h, [dst, #56]
+	ldrd	C_l, C_h, [sp, #16]
+	strd	D_l, D_h, [dst, #64]
+	ldrd	D_l, D_h, [sp, #24]
+	add	dst, dst, #72
+	ands	count, tmp2, #0x3f
+#endif
+	ldr	tmp2, [sp], #FRAME_SIZE
+	bne	.Ltail63unaligned
+	bx	lr
+
+	.size	memcpy, . - memcpy
diff --git a/contrib/cortex-strings/src/arm/memset.S b/contrib/cortex-strings/src/arm/memset.S
new file mode 100644
index 000000000000..c0ad588ab11e
--- /dev/null
+++ b/contrib/cortex-strings/src/arm/memset.S
@@ -0,0 +1,122 @@
+/* Copyright (c) 2010-2011, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+      * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+      * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+
+      * Neither the name of Linaro Limited nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+   Written by Dave Gilbert <david.gilbert@linaro.org>
+
+   This memset routine is optimised on a Cortex-A9 and should work on
+   all ARMv7 processors.
+
+ */
+
+	.syntax unified
+	.arch armv7-a
+
+@ 2011-08-30 david.gilbert@linaro.org
+@    Extracted from local git 2f11b436
+
+@ this lets us check a flag in a 00/ff byte easily in either endianness
+#ifdef __ARMEB__
+#define CHARTSTMASK(c) 1<<(31-(c*8))
+#else
+#define CHARTSTMASK(c) 1<<(c*8)
+#endif
+	.text
+	.thumb
+
+@ ---------------------------------------------------------------------------
+	.thumb_func
+	.align 2
+	.p2align 4,,15
+	.global memset
+	.type memset,%function
+memset: 
+	@ r0 = address
+	@ r1 = character
+	@ r2 = count
+	@ returns original address in r0
+
+	mov	r3, r0		@ Leave r0 alone
+	cbz	r2, 10f		@ Exit if 0 length
+
+	tst	r0, #7
+	beq	2f		@ Already aligned
+
+	@ Ok, so we're misaligned here
+1:
+	strb	r1, [r3], #1
+	subs	r2,r2,#1
+	tst	r3, #7
+	cbz	r2, 10f		@ Exit if we hit the end
+	bne	1b		@ go round again if still misaligned
+
+2:
+	@ OK, so we're aligned
+	push	{r4,r5,r6,r7}
+	bics	r4, r2, #15	@ if less than 16 bytes then need to finish it off
+	beq	5f
+
+3:
+	@ POSIX says that ch is cast to an unsigned char.  A uxtb is one
+	@ byte and takes two cycles, where an AND is four bytes but one
+	@ cycle.
+	and	r1, #0xFF
+	orr	r1, r1, r1, lsl#8	@ Same character into all bytes
+	orr	r1, r1, r1, lsl#16
+	mov	r5,r1
+	mov	r6,r1
+	mov	r7,r1
+
+4:
+	subs	r4,r4,#16
+	stmia	r3!,{r1,r5,r6,r7}
+	bne	4b
+	and	r2,r2,#15
+
+	@ At this point we're still aligned and we have upto align-1 bytes left to right
+	@ we can avoid some of the byte-at-a time now by testing for some big chunks
+	tst	r2,#8
+	itt	ne 
+	subne	r2,r2,#8
+	stmiane	r3!,{r1,r5}
+
+5:
+	pop	{r4,r5,r6,r7}
+	cbz	r2, 10f
+
+	@ Got to do any last < alignment bytes
+6:
+	subs	r2,r2,#1
+	strb	r1,[r3],#1
+	bne	6b
+
+10:
+	bx	lr		@ goodbye
diff --git a/contrib/cortex-strings/src/arm/strchr.S b/contrib/cortex-strings/src/arm/strchr.S
new file mode 100644
index 000000000000..8e06dd403afd
--- /dev/null
+++ b/contrib/cortex-strings/src/arm/strchr.S
@@ -0,0 +1,80 @@
+/* Copyright (c) 2010-2011, Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+      * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+      * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+
+      * Neither the name of Linaro Limited nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+   Written by Dave Gilbert <david.gilbert@linaro.org>
+
+   A very simple strchr routine, from benchmarks on A9 it's a bit faster than
+   the current version in eglibc (2.12.1-0ubuntu14 package)
+   I don't think doing a word at a time version is worth it since a lot
+   of strchr cases are very short anyway.
+
+ */
+
+@ 2011-02-07 david.gilbert@linaro.org
+@    Extracted from local git a5b438d861
+
+	.syntax unified
+	.arch armv7-a
+
+	.text
+	.thumb
+
+@ ---------------------------------------------------------------------------
+
+	.thumb_func
+	.align 2
+	.p2align 4,,15
+	.global strchr
+	.type strchr,%function
+strchr:
+	@ r0 = start of string
+	@ r1 = character to match
+	@ returns NULL for no match, or a pointer to the match
+	and	r1,r1, #255
+
+1:
+	ldrb	r2,[r0],#1
+	cmp	r2,r1
+	cbz	r2,10f
+	bne	1b
+
+	@ We're here if it matched
+5:
+	subs	r0,r0,#1
+	bx	lr
+
+10:
+	@ We're here if we ran off the end
+	cmp	r1, #0	@ Corner case - you're allowed to search for the nil and get a pointer to it
+	beq	5b	@ A bit messy, if it's common we should branch at the start to a special loop
+	mov	r0,#0
+	bx	lr
diff --git a/contrib/cortex-strings/src/arm/strcmp.S b/contrib/cortex-strings/src/arm/strcmp.S
new file mode 100644
index 000000000000..5fad272e48a6
--- /dev/null
+++ b/contrib/cortex-strings/src/arm/strcmp.S
@@ -0,0 +1,500 @@
+/*
+ * Copyright (c) 2012-2014 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Implementation of strcmp for ARMv7 when DSP instructions are
+   available.  Use ldrd to support wider loads, provided the data
+   is sufficiently aligned.  Use saturating arithmetic to optimize
+   the compares.  */
+
+/* Build Options:
+   STRCMP_NO_PRECHECK: Don't run a quick pre-check of the first
+   byte in the string.  If comparing completely random strings
+   the pre-check will save time, since there is a very high
+   probability of a mismatch in the first character: we save
+   significant overhead if this is the common case.  However,
+   if strings are likely to be identical (eg because we're
+   verifying a hit in a hash table), then this check is largely
+   redundant.  */
+
+#define STRCMP_NO_PRECHECK	0
+
+	/* This version uses Thumb-2 code.  */
+	.thumb
+	.syntax unified
+
+#ifdef __ARM_BIG_ENDIAN
+#define S2LO lsl
+#define S2LOEQ lsleq
+#define S2HI lsr
+#define MSB 0x000000ff
+#define LSB 0xff000000
+#define BYTE0_OFFSET 24
+#define BYTE1_OFFSET 16
+#define BYTE2_OFFSET 8
+#define BYTE3_OFFSET 0
+#else /* not  __ARM_BIG_ENDIAN */
+#define S2LO lsr
+#define S2LOEQ lsreq
+#define S2HI lsl
+#define BYTE0_OFFSET 0
+#define BYTE1_OFFSET 8
+#define BYTE2_OFFSET 16
+#define BYTE3_OFFSET 24
+#define MSB 0xff000000
+#define LSB 0x000000ff
+#endif /* not  __ARM_BIG_ENDIAN */
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+/* Parameters and result.  */
+#define src1		r0
+#define src2		r1
+#define result		r0	/* Overlaps src1.  */
+
+/* Internal variables.  */
+#define tmp1		r4
+#define tmp2		r5
+#define const_m1	r12
+
+/* Additional internal variables for 64-bit aligned data.  */
+#define data1a		r2
+#define data1b		r3
+#define data2a		r6
+#define data2b		r7
+#define syndrome_a	tmp1
+#define syndrome_b	tmp2
+
+/* Additional internal variables for 32-bit aligned data.  */
+#define data1		r2
+#define data2		r3
+#define syndrome	tmp2
+
+
+	/* Macro to compute and return the result value for word-aligned
+	   cases.  */
+	.macro strcmp_epilogue_aligned synd d1 d2 restore_r6
+#ifdef __ARM_BIG_ENDIAN
+	/* If data1 contains a zero byte, then syndrome will contain a 1 in
+	   bit 7 of that byte.  Otherwise, the highest set bit in the
+	   syndrome will highlight the first different bit.  It is therefore
+	   sufficient to extract the eight bits starting with the syndrome
+	   bit.  */
+	clz	tmp1, \synd
+	lsl	r1, \d2, tmp1
+	.if \restore_r6
+	ldrd	r6, r7, [sp, #8]
+	.endif
+	.cfi_restore 6
+	.cfi_restore 7
+	lsl	\d1, \d1, tmp1
+	.cfi_remember_state
+	lsr	result, \d1, #24
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	sub	result, result, r1, lsr #24
+	bx	lr
+#else
+	/* To use the big-endian trick we'd have to reverse all three words.
+	   that's slower than this approach.  */
+	rev	\synd, \synd
+	clz	tmp1, \synd
+	bic	tmp1, tmp1, #7
+	lsr	r1, \d2, tmp1
+	.cfi_remember_state
+	.if \restore_r6
+	ldrd	r6, r7, [sp, #8]
+	.endif
+	.cfi_restore 6
+	.cfi_restore 7
+	lsr	\d1, \d1, tmp1
+	and	result, \d1, #255
+	and	r1, r1, #255
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	sub	result, result, r1
+
+	bx	lr
+#endif
+	.endm
+
+	.text
+	.p2align	5
+.Lstrcmp_start_addr:
+#if STRCMP_NO_PRECHECK == 0
+.Lfastpath_exit:
+	sub	r0, r2, r3
+	bx	lr
+	nop
+#endif
+def_fn	strcmp
+#if STRCMP_NO_PRECHECK == 0
+	ldrb	r2, [src1]
+	ldrb	r3, [src2]
+	cmp	r2, #1
+	it	cs
+	cmpcs	r2, r3
+	bne	.Lfastpath_exit
+#endif
+	.cfi_startproc
+	strd	r4, r5, [sp, #-16]!
+	.cfi_def_cfa_offset 16
+	.cfi_offset 4, -16
+	.cfi_offset 5, -12
+	orr	tmp1, src1, src2
+	strd	r6, r7, [sp, #8]
+	.cfi_offset 6, -8
+	.cfi_offset 7, -4
+	mvn	const_m1, #0
+	lsl	r2, tmp1, #29
+	cbz	r2, .Lloop_aligned8
+
+.Lnot_aligned:
+	eor	tmp1, src1, src2
+	tst	tmp1, #7
+	bne	.Lmisaligned8
+
+	/* Deal with mutual misalignment by aligning downwards and then
+	   masking off the unwanted loaded data to prevent a difference.  */
+	and	tmp1, src1, #7
+	bic	src1, src1, #7
+	and	tmp2, tmp1, #3
+	bic	src2, src2, #7
+	lsl	tmp2, tmp2, #3	/* Bytes -> bits.  */
+	ldrd	data1a, data1b, [src1], #16
+	tst	tmp1, #4
+	ldrd	data2a, data2b, [src2], #16
+	/* In thumb code we can't use MVN with a register shift, but
+	   we do have ORN.  */
+	S2HI	tmp1, const_m1, tmp2
+	orn	data1a, data1a, tmp1
+	orn	data2a, data2a, tmp1
+	beq	.Lstart_realigned8
+	orn	data1b, data1b, tmp1
+	mov	data1a, const_m1
+	orn	data2b, data2b, tmp1
+	mov	data2a, const_m1
+	b	.Lstart_realigned8
+
+	/* Unwind the inner loop by a factor of 2, giving 16 bytes per
+	   pass.  */
+	.p2align 5,,12  /* Don't start in the tail bytes of a cache line.  */
+	.p2align 2	/* Always word aligned.  */
+.Lloop_aligned8:
+	ldrd	data1a, data1b, [src1], #16
+	ldrd	data2a, data2b, [src2], #16
+.Lstart_realigned8:
+	uadd8	syndrome_b, data1a, const_m1	/* Only want GE bits,  */
+	eor	syndrome_a, data1a, data2a
+	sel	syndrome_a, syndrome_a, const_m1
+	cbnz	syndrome_a, .Ldiff_in_a
+	uadd8	syndrome_b, data1b, const_m1	/* Only want GE bits.  */
+	eor	syndrome_b, data1b, data2b
+	sel	syndrome_b, syndrome_b, const_m1
+	cbnz	syndrome_b, .Ldiff_in_b
+
+	ldrd	data1a, data1b, [src1, #-8]
+	ldrd	data2a, data2b, [src2, #-8]
+	uadd8	syndrome_b, data1a, const_m1	/* Only want GE bits,  */
+	eor	syndrome_a, data1a, data2a
+	sel	syndrome_a, syndrome_a, const_m1
+	uadd8	syndrome_b, data1b, const_m1	/* Only want GE bits.  */
+	eor	syndrome_b, data1b, data2b
+	sel	syndrome_b, syndrome_b, const_m1
+	/* Can't use CBZ for backwards branch.  */
+	orrs	syndrome_b, syndrome_b, syndrome_a /* Only need if s_a == 0 */
+	beq	.Lloop_aligned8
+
+.Ldiff_found:
+	cbnz	syndrome_a, .Ldiff_in_a
+
+.Ldiff_in_b:
+	strcmp_epilogue_aligned syndrome_b, data1b, data2b 1
+
+.Ldiff_in_a:
+	.cfi_restore_state
+	strcmp_epilogue_aligned syndrome_a, data1a, data2a 1
+
+	.cfi_restore_state
+.Lmisaligned8:
+	tst	tmp1, #3
+	bne	.Lmisaligned4
+	ands	tmp1, src1, #3
+	bne	.Lmutual_align4
+
+	/* Unrolled by a factor of 2, to reduce the number of post-increment
+	   operations.  */
+.Lloop_aligned4:
+	ldr	data1, [src1], #8
+	ldr	data2, [src2], #8
+.Lstart_realigned4:
+	uadd8	syndrome, data1, const_m1	/* Only need GE bits.  */
+	eor	syndrome, data1, data2
+	sel	syndrome, syndrome, const_m1
+	cbnz	syndrome, .Laligned4_done
+	ldr	data1, [src1, #-4]
+	ldr	data2, [src2, #-4]
+	uadd8	syndrome, data1, const_m1
+	eor	syndrome, data1, data2
+	sel	syndrome, syndrome, const_m1
+	cmp	syndrome, #0
+	beq	.Lloop_aligned4
+
+.Laligned4_done:
+	strcmp_epilogue_aligned syndrome, data1, data2, 0
+
+.Lmutual_align4:
+	.cfi_restore_state
+	/* Deal with mutual misalignment by aligning downwards and then
+	   masking off the unwanted loaded data to prevent a difference.  */
+	lsl	tmp1, tmp1, #3	/* Bytes -> bits.  */
+	bic	src1, src1, #3
+	ldr	data1, [src1], #8
+	bic	src2, src2, #3
+	ldr	data2, [src2], #8
+
+	/* In thumb code we can't use MVN with a register shift, but
+	   we do have ORN.  */
+	S2HI	tmp1, const_m1, tmp1
+	orn	data1, data1, tmp1
+	orn	data2, data2, tmp1
+	b	.Lstart_realigned4
+
+.Lmisaligned4:
+	ands	tmp1, src1, #3
+	beq	.Lsrc1_aligned
+	sub	src2, src2, tmp1
+	bic	src1, src1, #3
+	lsls	tmp1, tmp1, #31
+	ldr	data1, [src1], #4
+	beq	.Laligned_m2
+	bcs	.Laligned_m1
+
+#if STRCMP_NO_PRECHECK == 1
+	ldrb	data2, [src2, #1]
+	uxtb	tmp1, data1, ror #BYTE1_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	.Lmisaligned_exit
+	cbz	data2, .Lmisaligned_exit
+
+.Laligned_m2:
+	ldrb	data2, [src2, #2]
+	uxtb	tmp1, data1, ror #BYTE2_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	.Lmisaligned_exit
+	cbz	data2, .Lmisaligned_exit
+
+.Laligned_m1:
+	ldrb	data2, [src2, #3]
+	uxtb	tmp1, data1, ror #BYTE3_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	.Lmisaligned_exit
+	add	src2, src2, #4
+	cbnz	data2, .Lsrc1_aligned
+#else  /* STRCMP_NO_PRECHECK */
+	/* If we've done the pre-check, then we don't need to check the
+	   first byte again here.  */
+	ldrb	data2, [src2, #2]
+	uxtb	tmp1, data1, ror #BYTE2_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	.Lmisaligned_exit
+	cbz	data2, .Lmisaligned_exit
+
+.Laligned_m2:
+	ldrb	data2, [src2, #3]
+	uxtb	tmp1, data1, ror #BYTE3_OFFSET
+	subs	tmp1, tmp1, data2
+	bne	.Lmisaligned_exit
+	cbnz	data2, .Laligned_m1
+#endif
+
+.Lmisaligned_exit:
+	.cfi_remember_state
+	mov	result, tmp1
+	ldr	r4, [sp], #16
+	.cfi_restore 4
+	bx	lr
+
+#if STRCMP_NO_PRECHECK == 0
+.Laligned_m1:
+	add	src2, src2, #4
+#endif
+.Lsrc1_aligned:
+	.cfi_restore_state
+	/* src1 is word aligned, but src2 has no common alignment
+	   with it.  */
+	ldr	data1, [src1], #4
+	lsls	tmp1, src2, #31		/* C=src2[1], Z=src2[0].  */
+
+	bic	src2, src2, #3
+	ldr	data2, [src2], #4
+	bhi	.Loverlap1		/* C=1, Z=0 => src2[1:0] = 0b11.  */
+	bcs	.Loverlap2		/* C=1, Z=1 => src2[1:0] = 0b10.  */
+
+	/* (overlap3) C=0, Z=0 => src2[1:0] = 0b01.  */
+.Loverlap3:
+	bic	tmp1, data1, #MSB
+	uadd8	syndrome, data1, const_m1
+	eors	syndrome, tmp1, data2, S2LO #8
+	sel	syndrome, syndrome, const_m1
+	bne	4f
+	cbnz	syndrome, 5f
+	ldr	data2, [src2], #4
+	eor	tmp1, tmp1, data1
+	cmp	tmp1, data2, S2HI #24
+	bne	6f
+	ldr	data1, [src1], #4
+	b	.Loverlap3
+4:
+	S2LO	data2, data2, #8
+	b	.Lstrcmp_tail
+
+5:
+	bics	syndrome, syndrome, #MSB
+	bne	.Lstrcmp_done_equal
+
+	/* We can only get here if the MSB of data1 contains 0, so
+	   fast-path the exit.  */
+	ldrb	result, [src2]
+	.cfi_remember_state
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	/* R6/7 Not used in this sequence.  */
+	.cfi_restore 6
+	.cfi_restore 7
+	neg	result, result
+	bx	lr
+
+6:
+	.cfi_restore_state
+	S2LO	data1, data1, #24
+	and	data2, data2, #LSB
+	b	.Lstrcmp_tail
+
+	.p2align 5,,12	/* Ensure at least 3 instructions in cache line.  */
+.Loverlap2:
+	and	tmp1, data1, const_m1, S2LO #16
+	uadd8	syndrome, data1, const_m1
+	eors	syndrome, tmp1, data2, S2LO #16
+	sel	syndrome, syndrome, const_m1
+	bne	4f
+	cbnz	syndrome, 5f
+	ldr	data2, [src2], #4
+	eor	tmp1, tmp1, data1
+	cmp	tmp1, data2, S2HI #16
+	bne	6f
+	ldr	data1, [src1], #4
+	b	.Loverlap2
+4:
+	S2LO	data2, data2, #16
+	b	.Lstrcmp_tail
+5:
+	ands	syndrome, syndrome, const_m1, S2LO #16
+	bne	.Lstrcmp_done_equal
+
+	ldrh	data2, [src2]
+	S2LO	data1, data1, #16
+#ifdef __ARM_BIG_ENDIAN
+	lsl	data2, data2, #16
+#endif
+	b	.Lstrcmp_tail
+
+6:
+	S2LO	data1, data1, #16
+	and	data2, data2, const_m1, S2LO #16
+	b	.Lstrcmp_tail
+
+	.p2align 5,,12	/* Ensure at least 3 instructions in cache line.  */
+.Loverlap1:
+	and	tmp1, data1, #LSB
+	uadd8	syndrome, data1, const_m1
+	eors	syndrome, tmp1, data2, S2LO #24
+	sel	syndrome, syndrome, const_m1
+	bne	4f
+	cbnz	syndrome, 5f
+	ldr	data2, [src2], #4
+	eor	tmp1, tmp1, data1
+	cmp	tmp1, data2, S2HI #8
+	bne	6f
+	ldr	data1, [src1], #4
+	b	.Loverlap1
+4:
+	S2LO	data2, data2, #24
+	b	.Lstrcmp_tail
+5:
+	tst	syndrome, #LSB
+	bne	.Lstrcmp_done_equal
+	ldr	data2, [src2]
+6:
+	S2LO	data1, data1, #8
+	bic	data2, data2, #MSB
+	b	.Lstrcmp_tail
+
+.Lstrcmp_done_equal:
+	mov	result, #0
+	.cfi_remember_state
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	/* R6/7 not used in this sequence.  */
+	.cfi_restore 6
+	.cfi_restore 7
+	bx	lr
+
+.Lstrcmp_tail:
+	.cfi_restore_state
+#ifndef __ARM_BIG_ENDIAN
+	rev	data1, data1
+	rev	data2, data2
+	/* Now everything looks big-endian...  */
+#endif
+	uadd8	tmp1, data1, const_m1
+	eor	tmp1, data1, data2
+	sel	syndrome, tmp1, const_m1
+	clz	tmp1, syndrome
+	lsl	data1, data1, tmp1
+	lsl	data2, data2, tmp1
+	lsr	result, data1, #24
+	ldrd	r4, r5, [sp], #16
+	.cfi_restore 4
+	.cfi_restore 5
+	/* R6/7 not used in this sequence.  */
+	.cfi_restore 6
+	.cfi_restore 7
+	sub	result, result, data2, lsr #24
+	bx	lr
+	.cfi_endproc
+	.size strcmp, . - .Lstrcmp_start_addr
diff --git a/contrib/cortex-strings/src/thumb-2/strcpy.c b/contrib/cortex-strings/src/thumb-2/strcpy.c
new file mode 100644
index 000000000000..78195001a14c
--- /dev/null
+++ b/contrib/cortex-strings/src/thumb-2/strcpy.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2008 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* For GLIBC:
+#include <string.h>
+#include <memcopy.h>
+
+#undef strcmp
+*/
+
+#ifdef __thumb2__
+#define magic1(REG) "#0x01010101"
+#define magic2(REG) "#0x80808080"
+#else
+#define magic1(REG) #REG
+#define magic2(REG) #REG ", lsl #7"
+#endif
+
+char* __attribute__((naked))
+strcpy (char* dst, const char* src)
+{
+  asm (
+#if !(defined(__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \
+      (defined (__thumb__) && !defined (__thumb2__)))
+       "pld	[r1, #0]\n\t"
+       "eor	r2, r0, r1\n\t"
+       "mov	ip, r0\n\t"
+       "tst	r2, #3\n\t"
+       "bne	4f\n\t"
+       "tst	r1, #3\n\t"
+       "bne	3f\n"
+  "5:\n\t"
+#ifndef __thumb2__
+       "str	r5, [sp, #-4]!\n\t"
+       "mov	r5, #0x01\n\t"
+       "orr	r5, r5, r5, lsl #8\n\t"
+       "orr	r5, r5, r5, lsl #16\n\t"
+#endif
+
+       "str	r4, [sp, #-4]!\n\t"
+       "tst	r1, #4\n\t"
+       "ldr	r3, [r1], #4\n\t"
+       "beq	2f\n\t"
+       "sub	r2, r3, "magic1(r5)"\n\t"
+       "bics	r2, r2, r3\n\t"
+       "tst	r2, "magic2(r5)"\n\t"
+       "itt	eq\n\t"
+       "streq	r3, [ip], #4\n\t"
+       "ldreq	r3, [r1], #4\n"
+       "bne	1f\n\t"
+       /* Inner loop.  We now know that r1 is 64-bit aligned, so we
+	  can safely fetch up to two words.  This allows us to avoid
+	  load stalls.  */
+       ".p2align 2\n"
+  "2:\n\t"
+       "pld	[r1, #8]\n\t"
+       "ldr	r4, [r1], #4\n\t"
+       "sub	r2, r3, "magic1(r5)"\n\t"
+       "bics	r2, r2, r3\n\t"
+       "tst	r2, "magic2(r5)"\n\t"
+       "sub	r2, r4, "magic1(r5)"\n\t"
+       "bne	1f\n\t"
+       "str	r3, [ip], #4\n\t"
+       "bics	r2, r2, r4\n\t"
+       "tst	r2, "magic2(r5)"\n\t"
+       "itt	eq\n\t"
+       "ldreq	r3, [r1], #4\n\t"
+       "streq	r4, [ip], #4\n\t"
+       "beq	2b\n\t"
+       "mov	r3, r4\n"
+  "1:\n\t"
+#ifdef __ARMEB__
+       "rors	r3, r3, #24\n\t"
+#endif
+       "strb	r3, [ip], #1\n\t"
+       "tst	r3, #0xff\n\t"
+#ifdef __ARMEL__
+       "ror	r3, r3, #8\n\t"
+#endif
+       "bne	1b\n\t"
+       "ldr	r4, [sp], #4\n\t"
+#ifndef __thumb2__
+       "ldr	r5, [sp], #4\n\t"
+#endif
+       "BX LR\n"
+
+       /* Strings have the same offset from word alignment, but it's
+	  not zero.  */
+  "3:\n\t"
+       "tst	r1, #1\n\t"
+       "beq	1f\n\t"
+       "ldrb	r2, [r1], #1\n\t"
+       "strb	r2, [ip], #1\n\t"
+       "cmp	r2, #0\n\t"
+       "it	eq\n"
+       "BXEQ LR\n"
+  "1:\n\t"
+       "tst	r1, #2\n\t"
+       "beq	5b\n\t"
+       "ldrh	r2, [r1], #2\n\t"
+#ifdef __ARMEB__
+       "tst	r2, #0xff00\n\t"
+       "iteet	ne\n\t"
+       "strneh	r2, [ip], #2\n\t"
+       "lsreq	r2, r2, #8\n\t"
+       "streqb	r2, [ip]\n\t"
+       "tstne	r2, #0xff\n\t"
+#else
+       "tst	r2, #0xff\n\t"
+       "itet	ne\n\t"
+       "strneh	r2, [ip], #2\n\t"
+       "streqb	r2, [ip]\n\t"
+       "tstne	r2, #0xff00\n\t"
+#endif
+       "bne	5b\n\t"
+       "BX LR\n"
+
+       /* src and dst do not have a common word-alignement.  Fall back to
+	  byte copying.  */
+  "4:\n\t"
+       "ldrb	r2, [r1], #1\n\t"
+       "strb	r2, [ip], #1\n\t"
+       "cmp	r2, #0\n\t"
+       "bne	4b\n\t"
+       "BX LR"
+
+#elif !defined (__thumb__) || defined (__thumb2__)
+       "mov	r3, r0\n\t"
+  "1:\n\t"
+       "ldrb	r2, [r1], #1\n\t"
+       "strb	r2, [r3], #1\n\t"
+       "cmp	r2, #0\n\t"
+       "bne	1b\n\t"
+       "BX LR"
+#else
+       "mov	r3, r0\n\t"
+  "1:\n\t"
+       "ldrb	r2, [r1]\n\t"
+       "add	r1, r1, #1\n\t"
+       "strb	r2, [r3]\n\t"
+       "add	r3, r3, #1\n\t"
+       "cmp	r2, #0\n\t"
+       "bne	1b\n\t"
+       "BX LR"
+#endif
+       );
+}
+/* For GLIBC: libc_hidden_builtin_def (strcpy) */
diff --git a/contrib/cortex-strings/src/thumb-2/strlen.S b/contrib/cortex-strings/src/thumb-2/strlen.S
new file mode 100644
index 000000000000..8efa2356fdd1
--- /dev/null
+++ b/contrib/cortex-strings/src/thumb-2/strlen.S
@@ -0,0 +1,150 @@
+/* Copyright (c) 2010-2011,2013 Linaro Limited
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+      * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+      * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+
+      * Neither the name of Linaro Limited nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+   Assumes:
+   ARMv6T2, AArch32
+
+ */
+
+	.macro def_fn f p2align=0
+	.text
+	.p2align \p2align
+	.global \f
+	.type \f, %function
+\f:
+	.endm
+
+#ifdef __ARMEB__
+#define S2LO		lsl
+#define S2HI		lsr
+#else
+#define S2LO		lsr
+#define S2HI		lsl
+#endif
+
+	/* This code requires Thumb.  */
+	.thumb
+	.syntax unified
+
+/* Parameters and result.  */
+#define srcin		r0
+#define result		r0
+
+/* Internal variables.  */
+#define src		r1
+#define data1a		r2
+#define data1b		r3
+#define const_m1	r12
+#define const_0		r4
+#define tmp1		r4		/* Overlaps const_0  */
+#define tmp2		r5
+
+def_fn	strlen p2align=6
+	pld	[srcin, #0]
+	strd	r4, r5, [sp, #-8]!
+	bic	src, srcin, #7
+	mvn	const_m1, #0
+	ands	tmp1, srcin, #7		/* (8 - bytes) to alignment.  */
+	pld	[src, #32]
+	bne.w	.Lmisaligned8
+	mov	const_0, #0
+	mov	result, #-8
+.Lloop_aligned:
+	/* Bytes 0-7.  */
+	ldrd	data1a, data1b, [src]
+	pld	[src, #64]
+	add	result, result, #8
+.Lstart_realigned:
+	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
+	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
+	uadd8	data1b, data1b, const_m1
+	sel	data1b, data1a, const_m1	/* Only used if d1a == 0.  */
+	cbnz	data1b, .Lnull_found
+
+	/* Bytes 8-15.  */
+	ldrd	data1a, data1b, [src, #8]
+	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
+	add	result, result, #8
+	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
+	uadd8	data1b, data1b, const_m1
+	sel	data1b, data1a, const_m1	/* Only used if d1a == 0.  */
+	cbnz	data1b, .Lnull_found
+
+	/* Bytes 16-23.  */
+	ldrd	data1a, data1b, [src, #16]
+	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
+	add	result, result, #8
+	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
+	uadd8	data1b, data1b, const_m1
+	sel	data1b, data1a, const_m1	/* Only used if d1a == 0.  */
+	cbnz	data1b, .Lnull_found
+
+	/* Bytes 24-31.  */
+	ldrd	data1a, data1b, [src, #24]
+	add	src, src, #32
+	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
+	add	result, result, #8
+	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
+	uadd8	data1b, data1b, const_m1
+	sel	data1b, data1a, const_m1	/* Only used if d1a == 0.  */
+	cmp	data1b, #0
+	beq	.Lloop_aligned
+
+.Lnull_found:
+	cmp	data1a, #0
+	itt	eq
+	addeq	result, result, #4
+	moveq	data1a, data1b
+#ifndef __ARMEB__
+	rev	data1a, data1a
+#endif
+	clz	data1a, data1a
+	ldrd	r4, r5, [sp], #8
+	add	result, result, data1a, lsr #3	/* Bits -> Bytes.  */
+	bx	lr
+
+.Lmisaligned8:
+	ldrd	data1a, data1b, [src]
+	and	tmp2, tmp1, #3
+	rsb	result, tmp1, #0
+	lsl	tmp2, tmp2, #3			/* Bytes -> bits.  */
+	tst	tmp1, #4
+	pld	[src, #64]
+	S2HI	tmp2, const_m1, tmp2
+	orn	data1a, data1a, tmp2
+	itt	ne
+	ornne	data1b, data1b, tmp2
+	movne	data1a, const_m1
+	mov	const_0, #0
+	b	.Lstart_realigned
+	.size	strlen, . - strlen
+
diff --git a/contrib/cortex-strings/src/thumb/aeabi_idiv.S b/contrib/cortex-strings/src/thumb/aeabi_idiv.S
new file mode 100644
index 000000000000..b15a02c21932
--- /dev/null
+++ b/contrib/cortex-strings/src/thumb/aeabi_idiv.S
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2014 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* An executable stack is *not* required for these functions.  */
+
+.section .note.GNU-stack,"",%progbits
+.previous
+.eabi_attribute 25, 1
+
+/* ANSI concatenation macros.  */
+
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define CONCAT2(a, b) a ## b
+
+/* Use the right prefix for global labels.  */
+
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+#define TYPE(x) .type SYM(x),function
+#define SIZE(x) .size SYM(x), . - SYM(x)
+#define LSYM(x) .x
+
+.macro cfi_start	start_label, end_label
+	.pushsection	.debug_frame
+LSYM(Lstart_frame):
+	.4byte	LSYM(Lend_cie) - LSYM(Lstart_cie)
+LSYM(Lstart_cie):
+        .4byte	0xffffffff
+        .byte	0x1
+        .ascii	"\0"
+        .uleb128 0x1
+        .sleb128 -4
+        .byte	0xe
+        .byte	0xc
+        .uleb128 0xd
+        .uleb128 0x0
+
+	.align 2
+LSYM(Lend_cie):
+	.4byte	LSYM(Lend_fde)-LSYM(Lstart_fde)
+LSYM(Lstart_fde):
+	.4byte	LSYM(Lstart_frame)
+	.4byte	\start_label
+	.4byte	\end_label-\start_label
+	.popsection
+.endm
+
+.macro cfi_end	end_label
+	.pushsection	.debug_frame
+	.align	2
+LSYM(Lend_fde):
+	.popsection
+\end_label:
+.endm
+
+.macro THUMB_LDIV0 name signed
+	push	{r0, lr}
+	movs	r0, #0
+	bl	SYM(__aeabi_idiv0)
+	pop	{r1, pc}
+.endm
+
+.macro FUNC_END name
+	SIZE (__\name)
+.endm
+
+.macro DIV_FUNC_END name signed
+	cfi_start	__\name, LSYM(Lend_div0)
+LSYM(Ldiv0):
+	THUMB_LDIV0 \name \signed
+	cfi_end	LSYM(Lend_div0)
+	FUNC_END \name
+.endm
+
+.macro THUMB_FUNC_START name
+	.globl	SYM (\name)
+	TYPE	(\name)
+	.thumb_func
+SYM (\name):
+.endm
+
+.macro FUNC_START name
+	.text
+	.globl SYM (__\name)
+	TYPE (__\name)
+	.align 0
+	.force_thumb
+	.thumb_func
+	.syntax unified
+SYM (__\name):
+.endm
+
+.macro	FUNC_ALIAS new old
+	.globl	SYM (__\new)
+	.thumb_set	SYM (__\new), SYM (__\old)
+.endm
+
+/* Register aliases.  */
+work		.req	r4
+dividend	.req	r0
+divisor		.req	r1
+overdone	.req	r2
+result		.req	r2
+curbit		.req	r3
+
+/* ------------------------------------------------------------------------ */
+/*		Bodies of the division and modulo routines.		    */
+/* ------------------------------------------------------------------------ */
+.macro BranchToDiv n, label
+	lsrs	curbit, dividend, \n
+	cmp	curbit, divisor
+	bcc	\label
+.endm
+
+.macro DoDiv n
+	lsrs	curbit, dividend, \n
+	cmp	curbit, divisor
+	bcc	1f
+	lsls	curbit, divisor, \n
+	subs	dividend, dividend, curbit
+
+1:	adcs	result, result
+.endm
+
+.macro THUMB1_Div_Positive
+	movs	result, #0
+	BranchToDiv #1, LSYM(Lthumb1_div1)
+	BranchToDiv #4, LSYM(Lthumb1_div4)
+	BranchToDiv #8, LSYM(Lthumb1_div8)
+	BranchToDiv #12, LSYM(Lthumb1_div12)
+	BranchToDiv #16, LSYM(Lthumb1_div16)
+LSYM(Lthumb1_div_large_positive):
+	movs	result, #0xff
+	lsls	divisor, divisor, #8
+	rev	result, result
+	lsrs	curbit, dividend, #16
+	cmp	curbit, divisor
+	bcc	1f
+	asrs	result, #8
+	lsls	divisor, divisor, #8
+	beq	LSYM(Ldivbyzero_waypoint)
+
+1:	lsrs	curbit, dividend, #12
+	cmp	curbit, divisor
+	bcc	LSYM(Lthumb1_div12)
+	b	LSYM(Lthumb1_div16)
+LSYM(Lthumb1_div_loop):
+	lsrs	divisor, divisor, #8
+LSYM(Lthumb1_div16):
+	Dodiv	#15
+	Dodiv	#14
+	Dodiv	#13
+	Dodiv	#12
+LSYM(Lthumb1_div12):
+	Dodiv	#11
+	Dodiv	#10
+	Dodiv	#9
+	Dodiv	#8
+	bcs	LSYM(Lthumb1_div_loop)
+LSYM(Lthumb1_div8):
+	Dodiv	#7
+	Dodiv	#6
+	Dodiv	#5
+LSYM(Lthumb1_div5):
+	Dodiv	#4
+LSYM(Lthumb1_div4):
+	Dodiv	#3
+LSYM(Lthumb1_div3):
+	Dodiv	#2
+LSYM(Lthumb1_div2):
+	Dodiv	#1
+LSYM(Lthumb1_div1):
+	subs	divisor, dividend, divisor
+	bcs	1f
+	mov	divisor, dividend
+
+1:	adcs	result, result
+	mov	dividend, result
+	bx	lr
+
+LSYM(Ldivbyzero_waypoint):
+	b	LSYM(Ldiv0)
+.endm
+
+.macro THUMB1_Div_Negative
+	lsrs	result, divisor, #31
+	beq	1f
+	rsbs	divisor, divisor, #0
+
+1:	asrs	curbit, dividend, #32
+	bcc	2f
+	rsbs	dividend, dividend, #0
+
+2:	eors	curbit, result
+	movs	result, #0
+	mov	ip, curbit
+	BranchToDiv #4, LSYM(Lthumb1_div_negative4)
+	BranchToDiv #8, LSYM(Lthumb1_div_negative8)
+LSYM(Lthumb1_div_large):
+	movs	result, #0xfc
+	lsls	divisor, divisor, #6
+	rev	result, result
+	lsrs	curbit, dividend, #8
+	cmp	curbit, divisor
+	bcc	LSYM(Lthumb1_div_negative8)
+
+	lsls	divisor, divisor, #6
+	asrs	result, result, #6
+	cmp	curbit, divisor
+	bcc	LSYM(Lthumb1_div_negative8)
+
+	lsls	divisor, divisor, #6
+	asrs	result, result, #6
+	cmp	curbit, divisor
+	bcc	LSYM(Lthumb1_div_negative8)
+
+	lsls	divisor, divisor, #6
+	beq	LSYM(Ldivbyzero_negative)
+	asrs	result, result, #6
+	b	LSYM(Lthumb1_div_negative8)
+LSYM(Lthumb1_div_negative_loop):
+	lsrs	divisor, divisor, #6
+LSYM(Lthumb1_div_negative8):
+	DoDiv	#7
+	DoDiv	#6
+	DoDiv	#5
+	DoDiv	#4
+LSYM(Lthumb1_div_negative4):
+	DoDiv	#3
+	DoDiv	#2
+	bcs	LSYM(Lthumb1_div_negative_loop)
+	DoDiv	#1
+	subs	divisor, dividend, divisor
+	bcs	1f
+	mov	divisor, dividend
+
+1:	mov	curbit, ip
+	adcs	result, result
+	asrs	curbit, curbit, #1
+	mov	dividend, result
+	bcc	2f
+	rsbs	dividend, dividend, #0
+	cmp	curbit, #0
+
+2:	bpl	3f
+	rsbs	divisor, divisor, #0
+
+3:	bx	lr
+
+LSYM(Ldivbyzero_negative):
+	mov	curbit, ip
+	asrs	curbit, curbit, #1
+	bcc	LSYM(Ldiv0)
+	rsbs	dividend, dividend, #0
+.endm
+
+/* ------------------------------------------------------------------------ */
+/*		Start of the Real Functions				    */
+/* ------------------------------------------------------------------------ */
+
+	FUNC_START aeabi_idiv0
+	bx	lr
+	FUNC_END aeabi_idiv0
+
+	FUNC_START divsi3
+	FUNC_ALIAS aeabi_idiv divsi3
+
+LSYM(divsi3_skip_div0_test):
+	mov	curbit, dividend
+	orrs	curbit, divisor
+	bmi	LSYM(Lthumb1_div_negative)
+
+LSYM(Lthumb1_div_positive):
+	THUMB1_Div_Positive
+
+LSYM(Lthumb1_div_negative):
+	THUMB1_Div_Negative
+
+	DIV_FUNC_END divsi3 signed
+
+	FUNC_START aeabi_idivmod
+
+	cmp	r1, #0
+	beq	LSYM(Ldiv0)
+	push	{r0, r1, lr}
+	bl	LSYM(divsi3_skip_div0_test)
+	POP	{r1, r2, r3}
+	mul	r2, r0
+	sub	r1, r1, r2
+	bx	r3
+
+	FUNC_END aeabi_idivmod
+/* ------------------------------------------------------------------------ */
diff --git a/contrib/cortex-strings/src/thumb/strcmp-armv6m.S b/contrib/cortex-strings/src/thumb/strcmp-armv6m.S
new file mode 100644
index 000000000000..d1255e0d36ed
--- /dev/null
+++ b/contrib/cortex-strings/src/thumb/strcmp-armv6m.S
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2014 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Implementation of strcmp for ARMv6m.  This version is only used in
+   ARMv6-M when we want an efficient implementation.  Otherwize if the
+   code size is preferred, strcmp-armv4t.S will be used.  */
+
+	.thumb_func
+	.syntax unified
+	.arch	armv6-m
+
+	.macro DoSub n, label
+	subs	r0, r0, r1
+#ifdef __ARM_BIG_ENDIAN
+	lsrs	r1, r4, \n
+#else
+	lsls	r1, r4, \n
+#endif
+	orrs	r1, r0
+	bne	\label
+	.endm
+
+	.macro Byte_Test n, label
+	lsrs	r0, r2, \n
+	lsrs	r1, r3, \n
+	DoSub	\n, \label
+	.endm
+
+	.text
+	.p2align	0
+	.global	strcmp
+	.type	strcmp, %function
+strcmp:
+	.cfi_startproc
+	mov	r2, r0
+	push	{r4, r5, r6, lr}
+	orrs	r2, r1
+	lsls	r2, r2, #30
+	bne	6f
+	ldr	r5, =0x01010101
+	lsls	r6, r5, #7
+1:
+	ldmia	r0!, {r2}
+	ldmia	r1!, {r3}
+	subs	r4, r2, r5
+	bics	r4, r2
+	ands	r4, r6
+	beq	3f
+
+#ifdef __ARM_BIG_ENDIAN
+	Byte_Test #24, 4f
+	Byte_Test #16, 4f
+	Byte_Test #8, 4f
+
+	b       7f
+3:
+	cmp     r2, r3
+	beq     1b
+	cmp     r2, r3
+#else
+	uxtb    r0, r2
+	uxtb    r1, r3
+	DoSub   #24, 2f
+
+	uxth    r0, r2
+	uxth    r1, r3
+	DoSub   #16, 2f
+
+	lsls    r0, r2, #8
+	lsls    r1, r3, #8
+	lsrs    r0, r0, #8
+	lsrs    r1, r1, #8
+	DoSub   #8, 2f
+
+	lsrs    r0, r2, #24
+	lsrs    r1, r3, #24
+	subs    r0, r0, r1
+2:
+	pop     {r4, r5, r6, pc}
+
+3:
+	cmp     r2, r3
+	beq     1b
+	rev     r0, r2
+	rev     r1, r3
+	cmp     r0, r1
+#endif
+
+	bls	5f
+	movs	r0, #1
+4:
+	pop	{r4, r5, r6, pc}
+5:
+	movs	r0, #0
+	mvns	r0, r0
+	pop	{r4, r5, r6, pc}
+6:
+	ldrb	r2, [r0, #0]
+	ldrb	r3, [r1, #0]
+	adds	r0, #1
+	adds	r1, #1
+	cmp	r2, #0
+	beq	7f
+	cmp	r2, r3
+	bne	7f
+	ldrb	r2, [r0, #0]
+	ldrb	r3, [r1, #0]
+	adds	r0, #1
+	adds	r1, #1
+	cmp	r2, #0
+	beq	7f
+	cmp	r2, r3
+	beq	6b
+7:
+	subs	r0, r2, r3
+	pop	{r4, r5, r6, pc}
+	.cfi_endproc
+	.size	strcmp, . - strcmp
diff --git a/contrib/elftoolchain/libdwarf/dwarf.h b/contrib/elftoolchain/libdwarf/dwarf.h
index c79da96dbb47..f3b85ffc5a97 100644
--- a/contrib/elftoolchain/libdwarf/dwarf.h
+++ b/contrib/elftoolchain/libdwarf/dwarf.h
@@ -234,6 +234,21 @@
 #define	DW_AT_GNU_all_call_sites		0x2117
 #define	DW_AT_GNU_all_source_call_sites		0x2118
 
+/* Apple extensions. */
+#define	DW_AT_APPLE_optimized			0x3fe1
+#define	DW_AT_APPLE_flags			0x3fe2
+#define	DW_AT_APPLE_isa				0x3fe3
+#define	DW_AT_APPLE_block			0x3fe4
+#define	DW_AT_APPLE_major_runtime_vers		0x3fe5
+#define	DW_AT_APPLE_runtime_class		0x3fe6
+#define	DW_AT_APPLE_omit_frame_ptr		0x3fe7
+#define	DW_AT_APPLE_property_name		0x3fe8
+#define	DW_AT_APPLE_property_getter		0x3fe9
+#define	DW_AT_APPLE_property_setter		0x3fea
+#define	DW_AT_APPLE_property_attribute		0x3feb
+#define	DW_AT_APPLE_objc_complete_type		0x3fec
+#define	DW_AT_APPLE_property			0x3fed
+
 #define DW_FORM_addr			0x01
 #define DW_FORM_block2			0x03
 #define DW_FORM_block4			0x04
diff --git a/contrib/elftoolchain/libdwarf/dwarf_dump.c b/contrib/elftoolchain/libdwarf/dwarf_dump.c
index 3219fa4c0c6c..03b6d6cd9756 100644
--- a/contrib/elftoolchain/libdwarf/dwarf_dump.c
+++ b/contrib/elftoolchain/libdwarf/dwarf_dump.c
@@ -298,6 +298,32 @@ dwarf_get_AT_name(unsigned attr, const char **s)
 		*s = "DW_AT_GNU_all_call_sites"; break;
 	case DW_AT_GNU_all_source_call_sites:
 		*s = "DW_AT_GNU_all_source_call_sites"; break;
+	case DW_AT_APPLE_optimized:
+		*s = "DW_AT_APPLE_optimized"; break;
+	case DW_AT_APPLE_flags:
+		*s = "DW_AT_APPLE_flags"; break;
+	case DW_AT_APPLE_isa:
+		*s = "DW_AT_APPLE_isa"; break;
+	case DW_AT_APPLE_block:
+		*s = "DW_AT_APPLE_block"; break;
+	case DW_AT_APPLE_major_runtime_vers:
+		*s = "DW_AT_APPLE_major_runtime_vers"; break;
+	case DW_AT_APPLE_runtime_class:
+		*s = "DW_AT_APPLE_runtime_class"; break;
+	case DW_AT_APPLE_omit_frame_ptr:
+		*s = "DW_AT_APPLE_omit_frame_ptr"; break;
+	case DW_AT_APPLE_property_name:
+		*s = "DW_AT_APPLE_property_name"; break;
+	case DW_AT_APPLE_property_getter:
+		*s = "DW_AT_APPLE_property_getter"; break;
+	case DW_AT_APPLE_property_setter:
+		*s = "DW_AT_APPLE_property_setter"; break;
+	case DW_AT_APPLE_property_attribute:
+		*s = "DW_AT_APPLE_property_attribute"; break;
+	case DW_AT_APPLE_objc_complete_type:
+		*s = "DW_AT_APPLE_objc_complete_type"; break;
+	case DW_AT_APPLE_property:
+		*s = "DW_AT_APPLE_property"; break;
 	default:
 		return (DW_DLV_NO_ENTRY);
 	}
diff --git a/contrib/netbsd-tests/fs/h_funcs.subr b/contrib/netbsd-tests/fs/h_funcs.subr
index 1216aaf2124a..21bdd97163e4 100644
--- a/contrib/netbsd-tests/fs/h_funcs.subr
+++ b/contrib/netbsd-tests/fs/h_funcs.subr
@@ -45,6 +45,15 @@ require_fs() {
 
 	# if we have autoloadable modules, just assume the file system
 	atf_require_prog sysctl
+	# Begin FreeBSD
+	if true; then
+		if kldstat -m ${name}; then
+			found=yes
+		else
+			found=no
+		fi
+	else
+	# End FreeBSD
 	autoload=$(sysctl -n kern.module.autoload)
 	[ "${autoload}" = "1" ] && return 0
 
@@ -57,6 +66,9 @@ require_fs() {
 		fi
 		shift
 	done
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 	[ ${found} = yes ] || \
 		atf_skip "The kernel does not include support the " \
 		         "\`${name}' file system"
diff --git a/contrib/netbsd-tests/fs/tmpfs/t_mknod.sh b/contrib/netbsd-tests/fs/tmpfs/t_mknod.sh
index 62c7cce22834..037dc16ce3b2 100755
--- a/contrib/netbsd-tests/fs/tmpfs/t_mknod.sh
+++ b/contrib/netbsd-tests/fs/tmpfs/t_mknod.sh
@@ -106,7 +106,15 @@ pipe_body() {
 	test_mount
 	umask 022
 
+	# Begin FreeBSD
+	if true; then
+	atf_check -s eq:0 -o empty -e empty mkfifo pipe
+	else
+	# End FreeBSD
 	atf_check -s eq:0 -o empty -e empty mknod pipe p
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 	eval $(stat -s pipe)
 	[ ${st_mode} = 010644 ] || atf_fail "Invalid mode"
 
@@ -124,7 +132,15 @@ pipe_kqueue_body() {
 	umask 022
 
 	atf_check -s eq:0 -o empty -e empty mkdir dir
+	# Begin FreeBSD
+	if true; then
+	echo 'mkfifo dir/pipe' | kqueue_monitor 1 dir
+	else
+	# End FreeBSD
 	echo 'mknod dir/pipe p' | kqueue_monitor 1 dir
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 	kqueue_check dir NOTE_WRITE
 
 	test_unmount
diff --git a/contrib/netbsd-tests/fs/tmpfs/t_readdir.sh b/contrib/netbsd-tests/fs/tmpfs/t_readdir.sh
index 6f5dc3ef2bde..272c7493a204 100755
--- a/contrib/netbsd-tests/fs/tmpfs/t_readdir.sh
+++ b/contrib/netbsd-tests/fs/tmpfs/t_readdir.sh
@@ -59,7 +59,15 @@ types_body() {
 	atf_check -s eq:0 -o empty -e empty ln -s reg lnk
 	atf_check -s eq:0 -o empty -e empty mknod blk b 0 0
 	atf_check -s eq:0 -o empty -e empty mknod chr c 0 0
+	# Begin FreeBSD
+	if true; then
+	atf_check -s eq:0 -o empty -e empty mkfifo fifo
+	else
+	# End FreeBSD
 	atf_check -s eq:0 -o empty -e empty mknod fifo p
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 	atf_check -s eq:0 -o empty -e empty \
 	    $(atf_get_srcdir)/h_tools sockets sock
 
diff --git a/contrib/netbsd-tests/fs/tmpfs/t_sizes.sh b/contrib/netbsd-tests/fs/tmpfs/t_sizes.sh
index 9673b91ea135..35abe8ac25fe 100755
--- a/contrib/netbsd-tests/fs/tmpfs/t_sizes.sh
+++ b/contrib/netbsd-tests/fs/tmpfs/t_sizes.sh
@@ -54,7 +54,15 @@ big_head() {
 big_body() {
 	test_mount -o -s10M
 
+	# Begin FreeBSD
+	if true; then
+		pagesize=$(sysctl -n hw.pagesize)
+	else
+	# End FreeBSD
 	pagesize=$(sysctl hw.pagesize | cut -d ' ' -f 3)
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 	eval $($(atf_get_srcdir)/h_tools statvfs . | sed -e 's|^f_|cf_|')
 	cf_bused=$((${cf_blocks} - ${cf_bfree}))
 
diff --git a/contrib/netbsd-tests/fs/tmpfs/t_statvfs.sh b/contrib/netbsd-tests/fs/tmpfs/t_statvfs.sh
index 21290b6239f9..d0e7ac27ebb9 100755
--- a/contrib/netbsd-tests/fs/tmpfs/t_statvfs.sh
+++ b/contrib/netbsd-tests/fs/tmpfs/t_statvfs.sh
@@ -38,7 +38,15 @@ values_head() {
 values_body() {
 	test_mount -o -s10M
 
+	# Begin FreeBSD
+	if true; then
+		pagesize=$(sysctl -n hw.pagesize)
+	else
+	# End FreeBSD
 	pagesize=$(sysctl hw.pagesize | cut -d ' ' -f 3)
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 	eval $($(atf_get_srcdir)/h_tools statvfs .)
 	[ ${pagesize} -eq ${f_bsize} ] || \
 	    atf_fail "Invalid bsize"
diff --git a/contrib/netbsd-tests/fs/tmpfs/t_vnd.sh b/contrib/netbsd-tests/fs/tmpfs/t_vnd.sh
index e5d0a78e37c5..5c2cf7331ad5 100755
--- a/contrib/netbsd-tests/fs/tmpfs/t_vnd.sh
+++ b/contrib/netbsd-tests/fs/tmpfs/t_vnd.sh
@@ -38,12 +38,21 @@ basic_body() {
 
 	atf_check -s eq:0 -o ignore -e ignore \
 	    dd if=/dev/zero of=disk.img bs=1m count=10
+	# Begin FreeBSD
+	if true; then
+		atf_check -s eq:0 -o empty -e empty mkdir mnt
+		atf_check -s eq:0 -o empty -e empty mdmfs -F disk.img md3 mnt
+	else
+	# End FreeBSD
 	atf_check -s eq:0 -o empty -e empty vndconfig /dev/vnd3 disk.img
 
 	atf_check -s eq:0 -o ignore -e ignore newfs /dev/rvnd3a
 
 	atf_check -s eq:0 -o empty -e empty mkdir mnt
 	atf_check -s eq:0 -o empty -e empty mount /dev/vnd3a mnt
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 
 	echo "Creating test files"
 	for f in $(jot -w %u 100 | uniq); do
@@ -58,7 +67,15 @@ basic_body() {
 	done
 
 	atf_check -s eq:0 -o empty -e empty umount mnt
+	# Begin FreeBSD
+	if true; then
+		atf_check -s eq:0 -o empty -e empty mdconfig -d -u 3
+	else
+	# End FreeBSD
 	atf_check -s eq:0 -o empty -e empty vndconfig -u /dev/vnd3
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 
 	test_unmount
 	touch done
@@ -66,7 +83,15 @@ basic_body() {
 basic_cleanup() {
 	if [ ! -f done ]; then
 		umount mnt 2>/dev/null 1>&2
+		# Begin FreeBSD
+		if true; then
+			atf_check -s eq:0 -o empty -e empty mdconfig -d -u 3
+		else
+		# End FreeBSD
 		vndconfig -u /dev/vnd3 2>/dev/null 1>&2
+		# Begin FreeBSD
+		fi
+		# End FreeBSD
 	fi
 }
 
diff --git a/contrib/netbsd-tests/fs/tmpfs/t_vnode_leak.sh b/contrib/netbsd-tests/fs/tmpfs/t_vnode_leak.sh
index c505ffdbaf9d..4630a7cd97fb 100755
--- a/contrib/netbsd-tests/fs/tmpfs/t_vnode_leak.sh
+++ b/contrib/netbsd-tests/fs/tmpfs/t_vnode_leak.sh
@@ -36,7 +36,15 @@ main_head() {
 }
 main_body() {
 	echo "Lowering kern.maxvnodes to 2000"
+	# Begin FreeBSD
+	if true; then
+		sysctl -n kern.maxvnodes > oldvnodes
+	else
+	# End FreeBSD
 	sysctl kern.maxvnodes | awk '{ print $3; }' >oldvnodes
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 	atf_check -s eq:0 -o ignore -e empty sysctl -w kern.maxvnodes=2000
 
 	test_mount -o -s$(((4000 + 2) * 4096))
diff --git a/contrib/netbsd-tests/usr.bin/dirname/t_dirname.sh b/contrib/netbsd-tests/usr.bin/dirname/t_dirname.sh
index 171fb13ab610..a3935249f47e 100755
--- a/contrib/netbsd-tests/usr.bin/dirname/t_dirname.sh
+++ b/contrib/netbsd-tests/usr.bin/dirname/t_dirname.sh
@@ -32,9 +32,6 @@ basic_head()
 }
 basic_body()
 {
-	# Begin FreeBSD
-	atf_expect_fail "dirname //usr//bin doesn't return //usr like it used to; bug # 212193"
-	# End FreeBSD
 	atf_check -o inline:"/\n" dirname /
 	atf_check -o inline:"/\n" dirname //
 	atf_check -o inline:"/usr\n" dirname /usr/bin/
diff --git a/contrib/ofed/usr.lib/libsdp/Makefile b/contrib/ofed/usr.lib/libsdp/Makefile
index cf7b2e3dfd35..54d09ca4ac81 100644
--- a/contrib/ofed/usr.lib/libsdp/Makefile
+++ b/contrib/ofed/usr.lib/libsdp/Makefile
@@ -22,4 +22,4 @@ CFLAGS+= -I${OFEDSYS}/include
 
 # Remove .[ly] since the checked-in version is preferred.
 .SUFFIXES:
-.SUFFIXES: .o .po .So .c .ln
+.SUFFIXES: .o .po .pico .c .ln
diff --git a/contrib/openbsm/bin/auditdistd/sandbox.c b/contrib/openbsm/bin/auditdistd/sandbox.c
index 53cd6b372307..3e1352a50f05 100644
--- a/contrib/openbsm/bin/auditdistd/sandbox.c
+++ b/contrib/openbsm/bin/auditdistd/sandbox.c
@@ -34,7 +34,7 @@
 #include <sys/jail.h>
 #endif
 #ifdef HAVE_CAP_ENTER
-#include <sys/capability.h>
+#include <sys/capsicum.h>
 #endif
 
 #include <errno.h>
diff --git a/contrib/tcpdump/tcpdump.c b/contrib/tcpdump/tcpdump.c
index 2bec0b8e2d11..937cff760337 100644
--- a/contrib/tcpdump/tcpdump.c
+++ b/contrib/tcpdump/tcpdump.c
@@ -92,7 +92,6 @@ extern int SIZE_BUF;
 #include <libcasper.h>
 #include <casper/cap_dns.h>
 #include <sys/nv.h>
-#include <sys/capability.h>
 #include <sys/ioccom.h>
 #include <net/bpf.h>
 #include <fcntl.h>
diff --git a/crypto/openssl/CHANGES b/crypto/openssl/CHANGES
index 4a557652d5a5..4bdd39064655 100644
--- a/crypto/openssl/CHANGES
+++ b/crypto/openssl/CHANGES
@@ -2,6 +2,166 @@
  OpenSSL CHANGES
  _______________
 
+ Changes between 1.0.2h and 1.0.2i [22 Sep 2016]
+
+  *) OCSP Status Request extension unbounded memory growth
+
+     A malicious client can send an excessively large OCSP Status Request
+     extension. If that client continually requests renegotiation, sending a
+     large OCSP Status Request extension each time, then there will be unbounded
+     memory growth on the server. This will eventually lead to a Denial Of
+     Service attack through memory exhaustion. Servers with a default
+     configuration are vulnerable even if they do not support OCSP. Builds using
+     the "no-ocsp" build time option are not affected.
+
+     This issue was reported to OpenSSL by Shi Lei (Gear Team, Qihoo 360 Inc.)
+     (CVE-2016-6304)
+     [Matt Caswell]
+
+  *) In order to mitigate the SWEET32 attack, the DES ciphers were moved from
+     HIGH to MEDIUM.
+
+     This issue was reported to OpenSSL Karthikeyan Bhargavan and Gaetan
+     Leurent (INRIA)
+     (CVE-2016-2183)
+     [Rich Salz]
+
+  *) OOB write in MDC2_Update()
+
+     An overflow can occur in MDC2_Update() either if called directly or
+     through the EVP_DigestUpdate() function using MDC2. If an attacker
+     is able to supply very large amounts of input data after a previous
+     call to EVP_EncryptUpdate() with a partial block then a length check
+     can overflow resulting in a heap corruption.
+
+     The amount of data needed is comparable to SIZE_MAX which is impractical
+     on most platforms.
+
+     This issue was reported to OpenSSL by Shi Lei (Gear Team, Qihoo 360 Inc.)
+     (CVE-2016-6303)
+     [Stephen Henson]
+
+  *) Malformed SHA512 ticket DoS
+
+     If a server uses SHA512 for TLS session ticket HMAC it is vulnerable to a
+     DoS attack where a malformed ticket will result in an OOB read which will
+     ultimately crash.
+
+     The use of SHA512 in TLS session tickets is comparatively rare as it requires
+     a custom server callback and ticket lookup mechanism.
+
+     This issue was reported to OpenSSL by Shi Lei (Gear Team, Qihoo 360 Inc.)
+     (CVE-2016-6302)
+     [Stephen Henson]
+
+  *) OOB write in BN_bn2dec()
+
+     The function BN_bn2dec() does not check the return value of BN_div_word().
+     This can cause an OOB write if an application uses this function with an
+     overly large BIGNUM. This could be a problem if an overly large certificate
+     or CRL is printed out from an untrusted source. TLS is not affected because
+     record limits will reject an oversized certificate before it is parsed.
+
+     This issue was reported to OpenSSL by Shi Lei (Gear Team, Qihoo 360 Inc.)
+     (CVE-2016-2182)
+     [Stephen Henson]
+
+  *) OOB read in TS_OBJ_print_bio()
+
+     The function TS_OBJ_print_bio() misuses OBJ_obj2txt(): the return value is
+     the total length the OID text representation would use and not the amount
+     of data written. This will result in OOB reads when large OIDs are
+     presented.
+
+     This issue was reported to OpenSSL by Shi Lei (Gear Team, Qihoo 360 Inc.)
+     (CVE-2016-2180)
+     [Stephen Henson]
+
+  *) Pointer arithmetic undefined behaviour
+
+     Avoid some undefined pointer arithmetic
+
+     A common idiom in the codebase is to check limits in the following manner:
+     "p + len > limit"
+
+     Where "p" points to some malloc'd data of SIZE bytes and
+     limit == p + SIZE
+
+     "len" here could be from some externally supplied data (e.g. from a TLS
+     message).
+
+     The rules of C pointer arithmetic are such that "p + len" is only well
+     defined where len <= SIZE. Therefore the above idiom is actually
+     undefined behaviour.
+
+     For example this could cause problems if some malloc implementation
+     provides an address for "p" such that "p + len" actually overflows for
+     values of len that are too big and therefore p + len < limit.
+
+     This issue was reported to OpenSSL by Guido Vranken
+     (CVE-2016-2177)
+     [Matt Caswell]
+
+  *) Constant time flag not preserved in DSA signing
+
+     Operations in the DSA signing algorithm should run in constant time in
+     order to avoid side channel attacks. A flaw in the OpenSSL DSA
+     implementation means that a non-constant time codepath is followed for
+     certain operations. This has been demonstrated through a cache-timing
+     attack to be sufficient for an attacker to recover the private DSA key.
+
+     This issue was reported by César Pereida (Aalto University), Billy Brumley
+     (Tampere University of Technology), and Yuval Yarom (The University of
+     Adelaide and NICTA).
+     (CVE-2016-2178)
+     [César Pereida]
+
+  *) DTLS buffered message DoS
+
+     In a DTLS connection where handshake messages are delivered out-of-order
+     those messages that OpenSSL is not yet ready to process will be buffered
+     for later use. Under certain circumstances, a flaw in the logic means that
+     those messages do not get removed from the buffer even though the handshake
+     has been completed. An attacker could force up to approx. 15 messages to
+     remain in the buffer when they are no longer required. These messages will
+     be cleared when the DTLS connection is closed. The default maximum size for
+     a message is 100k. Therefore the attacker could force an additional 1500k
+     to be consumed per connection. By opening many simulataneous connections an
+     attacker could cause a DoS attack through memory exhaustion.
+
+     This issue was reported to OpenSSL by Quan Luo.
+     (CVE-2016-2179)
+     [Matt Caswell]
+
+  *) DTLS replay protection DoS
+
+     A flaw in the DTLS replay attack protection mechanism means that records
+     that arrive for future epochs update the replay protection "window" before
+     the MAC for the record has been validated. This could be exploited by an
+     attacker by sending a record for the next epoch (which does not have to
+     decrypt or have a valid MAC), with a very large sequence number. This means
+     that all subsequent legitimate packets are dropped causing a denial of
+     service for a specific DTLS connection.
+
+     This issue was reported to OpenSSL by the OCAP audit team.
+     (CVE-2016-2181)
+     [Matt Caswell]
+
+  *) Certificate message OOB reads
+
+     In OpenSSL 1.0.2 and earlier some missing message length checks can result
+     in OOB reads of up to 2 bytes beyond an allocated buffer. There is a
+     theoretical DoS risk but this has not been observed in practice on common
+     platforms.
+
+     The messages affected are client certificate, client certificate request
+     and server certificate. As a result the attack can only be performed
+     against a client or a server which enables client authentication.
+
+     This issue was reported to OpenSSL by Shi Lei (Gear Team, Qihoo 360 Inc.)
+     (CVE-2016-6306)
+     [Stephen Henson]
+
  Changes between 1.0.2g and 1.0.2h [3 May 2016]
 
   *) Prevent padding oracle in AES-NI CBC MAC check
diff --git a/crypto/openssl/CONTRIBUTING b/crypto/openssl/CONTRIBUTING
index 9d63d8abb672..07115e5a7588 100644
--- a/crypto/openssl/CONTRIBUTING
+++ b/crypto/openssl/CONTRIBUTING
@@ -1,38 +1,75 @@
-HOW TO CONTRIBUTE TO OpenSSL
-----------------------------
+HOW TO CONTRIBUTE TO PATCHES OpenSSL
+------------------------------------
 
-Development is coordinated on the openssl-dev mailing list (see
-http://www.openssl.org for information on subscribing). If you
-would like to submit a patch, send it to rt@openssl.org with
-the string "[PATCH]" in the subject. Please be sure to include a
-textual explanation of what your patch does.
-
-You can also make GitHub pull requests. If you do this, please also send
-mail to rt@openssl.org with a brief description and a link to the PR so
-that we can more easily keep track of it.
+(Please visit https://www.openssl.org/community/getting-started.html for
+other ideas about how to contribute.)
 
+Development is coordinated on the openssl-dev mailing list (see the
+above link or https://mta.openssl.org for information on subscribing).
 If you are unsure as to whether a feature will be useful for the general
-OpenSSL community please discuss it on the openssl-dev mailing list first.
-Someone may be already working on the same thing or there may be a good
-reason as to why that feature isn't implemented.
+OpenSSL community you might want to discuss it on the openssl-dev mailing
+list first.  Someone may be already working on the same thing or there
+may be a good reason as to why that feature isn't implemented.
 
-Patches should be as up to date as possible, preferably relative to the
-current Git or the last snapshot. They should follow our coding style
-(see https://www.openssl.org/policies/codingstyle.html) and compile without
-warnings using the --strict-warnings flag.  OpenSSL compiles on many varied
-platforms: try to ensure you only use portable features.
+The best way to submit a patch is to make a pull request on GitHub.
+(It is not necessary to send mail to rt@openssl.org to open a ticket!)
+If you think the patch could use feedback from the community, please
+start a thread on openssl-dev.
 
-Our preferred format for patch files is "git format-patch" output. For example
-to provide a patch file containing the last commit in your local git repository
-use the following command:
+You can also submit patches by sending it as mail to rt@openssl.org.
+Please include the word "PATCH" and an explanation of what the patch
+does in the subject line.  If you do this, our preferred format is "git
+format-patch" output. For example to provide a patch file containing the
+last commit in your local git repository use the following command:
 
-# git format-patch --stdout HEAD^ >mydiffs.patch
+    % git format-patch --stdout HEAD^ >mydiffs.patch
 
 Another method of creating an acceptable patch file without using git is as
 follows:
 
-# cd openssl-work
-# [your changes]
-# ./Configure dist; make clean
-# cd ..
-# diff -ur openssl-orig openssl-work > mydiffs.patch
+    % cd openssl-work
+    ...make your changes...
+    % ./Configure dist; make clean
+    % cd ..
+    % diff -ur openssl-orig openssl-work >mydiffs.patch
+
+Note that pull requests are generally easier for the team, and community, to
+work with.  Pull requests benefit from all of the standard GitHub features,
+including code review tools, simpler integration, and CI build support.
+
+No matter how a patch is submitted, the following items will help make
+the acceptance and review process faster:
+
+    1. Anything other than trivial contributions will require a contributor
+    licensing agreement, giving us permission to use your code. See
+    https://www.openssl.org/policies/cla.html for details.
+
+    2.  All source files should start with the following text (with
+    appropriate comment characters at the start of each line and the
+    year(s) updated):
+
+        Copyright 20xx-20yy The OpenSSL Project Authors. All Rights Reserved.
+
+        Licensed under the OpenSSL license (the "License").  You may not use
+        this file except in compliance with the License.  You can obtain a copy
+        in the file LICENSE in the source distribution or at
+        https://www.openssl.org/source/license.html
+
+    3.  Patches should be as current as possible.  When using GitHub, please
+    expect to have to rebase and update often. Note that we do not accept merge
+    commits. You will be asked to remove them before a patch is considered
+    acceptable.
+
+    4.  Patches should follow our coding style (see
+    https://www.openssl.org/policies/codingstyle.html) and compile without
+    warnings. Where gcc or clang is availble you should use the
+    --strict-warnings Configure option.  OpenSSL compiles on many varied
+    platforms: try to ensure you only use portable features.
+
+    5.  When at all possible, patches should include tests. These can either be
+    added to an existing test, or completely new.  Please see test/README
+    for information on the test framework.
+
+    6.  New features or changed functionality must include documentation. Please
+    look at the "pod" files in doc/apps, doc/crypto and doc/ssl for examples of
+    our style.
diff --git a/crypto/openssl/Configure b/crypto/openssl/Configure
index c98107a48718..c39f71a17910 100755
--- a/crypto/openssl/Configure
+++ b/crypto/openssl/Configure
@@ -799,7 +799,7 @@ my @experimental = ();
 
 # This is what $depflags will look like with the above defaults
 # (we need this to see if we should advise the user to run "make depend"):
-my $default_depflags = " -DOPENSSL_NO_EC_NISTP_64_GCC_128 -DOPENSSL_NO_GMP -DOPENSSL_NO_JPAKE -DOPENSSL_NO_LIBUNBOUND -DOPENSSL_NO_MD2 -DOPENSSL_NO_RC5 -DOPENSSL_NO_RFC3779 -DOPENSSL_NO_SCTP -DOPENSSL_NO_SSL_TRACE -DOPENSSL_NO_STORE -DOPENSSL_NO_UNIT_TEST";
+my $default_depflags = " -DOPENSSL_NO_EC_NISTP_64_GCC_128 -DOPENSSL_NO_GMP -DOPENSSL_NO_JPAKE -DOPENSSL_NO_LIBUNBOUND -DOPENSSL_NO_MD2 -DOPENSSL_NO_RC5 -DOPENSSL_NO_RFC3779 -DOPENSSL_NO_SCTP -DOPENSSL_NO_SSL_TRACE -DOPENSSL_NO_SSL2 -DOPENSSL_NO_STORE -DOPENSSL_NO_UNIT_TEST -DOPENSSL_NO_WEAK_SSL_CIPHERS";
 
 # Explicit "no-..." options will be collected in %disabled along with the defaults.
 # To remove something from %disabled, use "enable-foo" (unless it's experimental).
@@ -1082,11 +1082,6 @@ if (defined($disabled{"md5"}) || defined($disabled{"sha"})
 	$disabled{"tls1"} = "forced";
 	}
 
-if (defined($disabled{"tls1"}))
-	{
-	$disabled{"tlsext"} = "forced";
-	}
-
 if (defined($disabled{"ec"}) || defined($disabled{"dsa"})
     || defined($disabled{"dh"}))
 	{
@@ -1254,6 +1249,7 @@ my $shared_extension = $fields[$idx_shared_extension];
 my $ranlib = $ENV{'RANLIB'} || $fields[$idx_ranlib];
 my $ar = $ENV{'AR'} || "ar";
 my $arflags = $fields[$idx_arflags];
+my $windres = $ENV{'RC'} || $ENV{'WINDRES'} || "windres";
 my $multilib = $fields[$idx_multilib];
 
 # if $prefix/lib$multilib is not an existing directory, then
@@ -1562,8 +1558,15 @@ $cpuid_obj="mem_clr.o"	unless ($cpuid_obj =~ /\.o$/);
 $des_obj=$des_enc	unless ($des_obj =~ /\.o$/);
 $bf_obj=$bf_enc		unless ($bf_obj =~ /\.o$/);
 $cast_obj=$cast_enc	unless ($cast_obj =~ /\.o$/);
-$rc4_obj=$rc4_enc	unless ($rc4_obj =~ /\.o$/);
 $rc5_obj=$rc5_enc	unless ($rc5_obj =~ /\.o$/);
+if ($rc4_obj =~ /\.o$/)
+	{
+	$cflags.=" -DRC4_ASM";
+	}
+else
+	{
+	$rc4_obj=$rc4_enc;
+	}
 if ($sha1_obj =~ /\.o$/)
 	{
 #	$sha1_obj=$sha1_enc;
@@ -1717,12 +1720,14 @@ while (<IN>)
 		s/^AR=\s*/AR= \$\(CROSS_COMPILE\)/;
 		s/^NM=\s*/NM= \$\(CROSS_COMPILE\)/;
 		s/^RANLIB=\s*/RANLIB= \$\(CROSS_COMPILE\)/;
+		s/^RC=\s*/RC= \$\(CROSS_COMPILE\)/;
 		s/^MAKEDEPPROG=.*$/MAKEDEPPROG= \$\(CROSS_COMPILE\)$cc/ if $cc eq "gcc";
 		}
 	else	{
 		s/^CC=.*$/CC= $cc/;
 		s/^AR=\s*ar/AR= $ar/;
 		s/^RANLIB=.*/RANLIB= $ranlib/;
+		s/^RC=.*/RC= $windres/;
 		s/^MAKEDEPPROG=.*$/MAKEDEPPROG= $cc/ if $cc eq "gcc";
 		s/^MAKEDEPPROG=.*$/MAKEDEPPROG= $cc/ if $ecc eq "gcc" || $ecc eq "clang";
 		}
diff --git a/crypto/openssl/Makefile b/crypto/openssl/Makefile
index a26a24ff1757..58daaa5548ce 100644
--- a/crypto/openssl/Makefile
+++ b/crypto/openssl/Makefile
@@ -4,7 +4,7 @@
 ## Makefile for OpenSSL
 ##
 
-VERSION=1.0.2h
+VERSION=1.0.2i
 MAJOR=1
 MINOR=0.2
 SHLIB_VERSION_NUMBER=1.0.0
@@ -68,6 +68,7 @@ EXE_EXT=
 ARFLAGS= 
 AR= ar $(ARFLAGS) r
 RANLIB= /usr/bin/ranlib
+RC= windres
 NM= nm
 PERL= /usr/bin/perl
 TAR= tar
@@ -210,6 +211,7 @@ BUILDENV=	LC_ALL=C PLATFORM='$(PLATFORM)' PROCESSOR='$(PROCESSOR)'\
 		CC='$(CC)' CFLAG='$(CFLAG)' 			\
 		AS='$(CC)' ASFLAG='$(CFLAG) -c'			\
 		AR='$(AR)' NM='$(NM)' RANLIB='$(RANLIB)'	\
+		RC='$(RC)'              			\
 		CROSS_COMPILE='$(CROSS_COMPILE)'	\
 		PERL='$(PERL)' ENGDIRS='$(ENGDIRS)'		\
 		SDIRS='$(SDIRS)' LIBRPATH='$(INSTALLTOP)/$(LIBDIR)'	\
@@ -368,6 +370,7 @@ libcrypto.pc: Makefile
 	    echo 'exec_prefix=$${prefix}'; \
 	    echo 'libdir=$${exec_prefix}/$(LIBDIR)'; \
 	    echo 'includedir=$${prefix}/include'; \
+	    echo 'enginesdir=$${libdir}/engines'; \
 	    echo ''; \
 	    echo 'Name: OpenSSL-libcrypto'; \
 	    echo 'Description: OpenSSL cryptography library'; \
diff --git a/crypto/openssl/Makefile.org b/crypto/openssl/Makefile.org
index 15c1c9f54428..e54402237e63 100644
--- a/crypto/openssl/Makefile.org
+++ b/crypto/openssl/Makefile.org
@@ -66,6 +66,7 @@ EXE_EXT=
 ARFLAGS?= r
 AR=ar $(ARFLAGS)
 RANLIB= ranlib
+RC= windres
 NM= nm
 PERL= perl
 TAR= tar
@@ -208,6 +209,7 @@ BUILDENV=	LC_ALL=C PLATFORM='$(PLATFORM)' PROCESSOR='$(PROCESSOR)'\
 		CC='$(CC)' CFLAG='$(CFLAG)' 			\
 		AS='$(CC)' ASFLAG='$(CFLAG) -c'			\
 		AR='$(AR)' NM='$(NM)' RANLIB='$(RANLIB)'	\
+		RC='$(RC)'              			\
 		CROSS_COMPILE='$(CROSS_COMPILE)'	\
 		PERL='$(PERL)' ENGDIRS='$(ENGDIRS)'		\
 		SDIRS='$(SDIRS)' LIBRPATH='$(INSTALLTOP)/$(LIBDIR)'	\
@@ -366,6 +368,7 @@ libcrypto.pc: Makefile
 	    echo 'exec_prefix=$${prefix}'; \
 	    echo 'libdir=$${exec_prefix}/$(LIBDIR)'; \
 	    echo 'includedir=$${prefix}/include'; \
+	    echo 'enginesdir=$${libdir}/engines'; \
 	    echo ''; \
 	    echo 'Name: OpenSSL-libcrypto'; \
 	    echo 'Description: OpenSSL cryptography library'; \
diff --git a/crypto/openssl/Makefile.shared b/crypto/openssl/Makefile.shared
index a2aa9804c1d9..e8d222ac6a00 100644
--- a/crypto/openssl/Makefile.shared
+++ b/crypto/openssl/Makefile.shared
@@ -293,7 +293,7 @@ link_a.cygwin:
 	fi; \
 	dll_name=$$SHLIB$$SHLIB_SOVER$$SHLIB_SUFFIX; \
 	$(PERL) util/mkrc.pl $$dll_name | \
-		$(CROSS_COMPILE)windres -o rc.o; \
+		$(RC) -o rc.o; \
 	extras="$$extras rc.o"; \
 	ALLSYMSFLAGS='-Wl,--whole-archive'; \
 	NOALLSYMSFLAGS='-Wl,--no-whole-archive'; \
diff --git a/crypto/openssl/NEWS b/crypto/openssl/NEWS
index 6c85116fc87d..5a652841cfcd 100644
--- a/crypto/openssl/NEWS
+++ b/crypto/openssl/NEWS
@@ -5,6 +5,20 @@
   This file gives a brief overview of the major changes between each OpenSSL
   release. For more details please read the CHANGES file.
 
+  Major changes between OpenSSL 1.0.2h and OpenSSL 1.0.2i [22 Sep 2016]
+
+      o OCSP Status Request extension unbounded memory growth (CVE-2016-6304)
+      o SWEET32 Mitigation (CVE-2016-2183)
+      o OOB write in MDC2_Update() (CVE-2016-6303)
+      o Malformed SHA512 ticket DoS (CVE-2016-6302)
+      o OOB write in BN_bn2dec() (CVE-2016-2182)
+      o OOB read in TS_OBJ_print_bio() (CVE-2016-2180)
+      o Pointer arithmetic undefined behaviour (CVE-2016-2177)
+      o Constant time flag not preserved in DSA signing (CVE-2016-2178)
+      o DTLS buffered message DoS (CVE-2016-2179)
+      o DTLS replay protection DoS (CVE-2016-2181)
+      o Certificate message OOB reads (CVE-2016-6306)
+
   Major changes between OpenSSL 1.0.2g and OpenSSL 1.0.2h [3 May 2016]
 
       o Prevent padding oracle in AES-NI CBC MAC check (CVE-2016-2107)
diff --git a/crypto/openssl/README b/crypto/openssl/README
index b880eec2d479..70d4ddd93bea 100644
--- a/crypto/openssl/README
+++ b/crypto/openssl/README
@@ -1,5 +1,5 @@
 
- OpenSSL 1.0.2h 3 May 2016
+ OpenSSL 1.0.2i 22 Sep 2016
 
  Copyright (c) 1998-2015 The OpenSSL Project
  Copyright (c) 1995-1998 Eric A. Young, Tim J. Hudson
diff --git a/crypto/openssl/apps/CA.pl b/crypto/openssl/apps/CA.pl
index a3965ecea96e..43c20b201c79 100755
--- a/crypto/openssl/apps/CA.pl
+++ b/crypto/openssl/apps/CA.pl
@@ -64,7 +64,7 @@ $RET = 0;
 
 foreach (@ARGV) {
 	if ( /^(-\?|-h|-help)$/ ) {
-	    print STDERR "usage: CA -newcert|-newreq|-newreq-nodes|-newca|-sign|-verify\n";
+	    print STDERR "usage: CA -newcert|-newreq|-newreq-nodes|-newca|-sign|-signcert|-verify\n";
 	    exit 0;
 	} elsif (/^-newcert$/) {
 	    # create a certificate
@@ -186,4 +186,3 @@ while (<IN>) {
 	}
 }
 }
-
diff --git a/crypto/openssl/apps/CA.pl.in b/crypto/openssl/apps/CA.pl.in
index c783a6e6a541..3bf4c99f3102 100644
--- a/crypto/openssl/apps/CA.pl.in
+++ b/crypto/openssl/apps/CA.pl.in
@@ -64,7 +64,7 @@ $RET = 0;
 
 foreach (@ARGV) {
 	if ( /^(-\?|-h|-help)$/ ) {
-	    print STDERR "usage: CA -newcert|-newreq|-newreq-nodes|-newca|-sign|-verify\n";
+	    print STDERR "usage: CA -newcert|-newreq|-newreq-nodes|-newca|-sign|-signcert|-verify\n";
 	    exit 0;
 	} elsif (/^-newcert$/) {
 	    # create a certificate
@@ -186,4 +186,3 @@ while (<IN>) {
 	}
 }
 }
-
diff --git a/crypto/openssl/apps/apps.c b/crypto/openssl/apps/apps.c
index b1dd97038f7d..9fdc3e0097c5 100644
--- a/crypto/openssl/apps/apps.c
+++ b/crypto/openssl/apps/apps.c
@@ -215,7 +215,8 @@ int args_from_file(char *file, int *argc, char **argv[])
     if (arg != NULL)
         OPENSSL_free(arg);
     arg = (char **)OPENSSL_malloc(sizeof(char *) * (i * 2));
-
+    if (arg == NULL)
+        return 0;
     *argv = arg;
     num = 0;
     p = buf;
@@ -2374,6 +2375,8 @@ int args_verify(char ***pargs, int *pargc,
         flags |= X509_V_FLAG_PARTIAL_CHAIN;
     else if (!strcmp(arg, "-no_alt_chains"))
         flags |= X509_V_FLAG_NO_ALT_CHAINS;
+    else if (!strcmp(arg, "-allow_proxy_certs"))
+        flags |= X509_V_FLAG_ALLOW_PROXY_CERTS;
     else
         return 0;
 
@@ -3195,6 +3198,36 @@ int app_isdir(const char *name)
 #endif
 
 /* raw_read|write section */
+#if defined(__VMS)
+# include "vms_term_sock.h"
+static int stdin_sock = -1;
+
+static void close_stdin_sock(void)
+{
+    TerminalSocket (TERM_SOCK_DELETE, &stdin_sock);
+}
+
+int fileno_stdin(void)
+{
+    if (stdin_sock == -1) {
+        TerminalSocket(TERM_SOCK_CREATE, &stdin_sock);
+        atexit(close_stdin_sock);
+    }
+
+    return stdin_sock;
+}
+#else
+int fileno_stdin(void)
+{
+    return fileno(stdin);
+}
+#endif
+
+int fileno_stdout(void)
+{
+    return fileno(stdout);
+}
+
 #if defined(_WIN32) && defined(STD_INPUT_HANDLE)
 int raw_read_stdin(void *buf, int siz)
 {
@@ -3204,10 +3237,17 @@ int raw_read_stdin(void *buf, int siz)
     else
         return (-1);
 }
+#elif defined(__VMS)
+#include <sys/socket.h>
+
+int raw_read_stdin(void *buf, int siz)
+{
+    return recv(fileno_stdin(), buf, siz, 0);
+}
 #else
 int raw_read_stdin(void *buf, int siz)
 {
-    return read(fileno(stdin), buf, siz);
+    return read(fileno_stdin(), buf, siz);
 }
 #endif
 
@@ -3223,6 +3263,6 @@ int raw_write_stdout(const void *buf, int siz)
 #else
 int raw_write_stdout(const void *buf, int siz)
 {
-    return write(fileno(stdout), buf, siz);
+    return write(fileno_stdout(), buf, siz);
 }
 #endif
diff --git a/crypto/openssl/apps/apps.h b/crypto/openssl/apps/apps.h
index 19bf5cc3337d..c6c3881f31e1 100644
--- a/crypto/openssl/apps/apps.h
+++ b/crypto/openssl/apps/apps.h
@@ -375,6 +375,8 @@ void store_setup_crl_download(X509_STORE *st);
 # define SERIAL_RAND_BITS        64
 
 int app_isdir(const char *);
+int fileno_stdin(void);
+int fileno_stdout(void);
 int raw_read_stdin(void *, int);
 int raw_write_stdout(const void *, int);
 
diff --git a/crypto/openssl/apps/ca.c b/crypto/openssl/apps/ca.c
index 0b66095b83b6..a0ec5838fa7c 100644
--- a/crypto/openssl/apps/ca.c
+++ b/crypto/openssl/apps/ca.c
@@ -2103,25 +2103,23 @@ static int do_body(X509 **xret, EVP_PKEY *pkey, X509 *x509,
         goto err;
 
     /* We now just add it to the database */
-    row[DB_type] = (char *)OPENSSL_malloc(2);
-
     tm = X509_get_notAfter(ret);
-    row[DB_exp_date] = (char *)OPENSSL_malloc(tm->length + 1);
-    memcpy(row[DB_exp_date], tm->data, tm->length);
-    row[DB_exp_date][tm->length] = '\0';
-
-    row[DB_rev_date] = NULL;
-
-    /* row[DB_serial] done already */
-    row[DB_file] = (char *)OPENSSL_malloc(8);
+    row[DB_type] = OPENSSL_malloc(2);
+    row[DB_exp_date] = OPENSSL_malloc(tm->length + 1);
+    row[DB_rev_date] = OPENSSL_malloc(1);
+    row[DB_file] = OPENSSL_malloc(8);
     row[DB_name] = X509_NAME_oneline(X509_get_subject_name(ret), NULL, 0);
-
     if ((row[DB_type] == NULL) || (row[DB_exp_date] == NULL) ||
+        (row[DB_rev_date] == NULL) ||
         (row[DB_file] == NULL) || (row[DB_name] == NULL)) {
         BIO_printf(bio_err, "Memory allocation failure\n");
         goto err;
     }
-    BUF_strlcpy(row[DB_file], "unknown", 8);
+
+    memcpy(row[DB_exp_date], tm->data, tm->length);
+    row[DB_exp_date][tm->length] = '\0';
+    row[DB_rev_date][0] = '\0';
+    strcpy(row[DB_file], "unknown");
     row[DB_type][0] = 'V';
     row[DB_type][1] = '\0';
 
@@ -2307,6 +2305,7 @@ static int certify_spkac(X509 **xret, char *infile, EVP_PKEY *pkey,
 
     j = NETSCAPE_SPKI_verify(spki, pktmp);
     if (j <= 0) {
+        EVP_PKEY_free(pktmp);
         BIO_printf(bio_err,
                    "signature verification failed on SPKAC public key\n");
         goto err;
diff --git a/crypto/openssl/apps/dgst.c b/crypto/openssl/apps/dgst.c
index 95e5fa3fc7b7..26afcd7b30ba 100644
--- a/crypto/openssl/apps/dgst.c
+++ b/crypto/openssl/apps/dgst.c
@@ -243,6 +243,11 @@ int MAIN(int argc, char **argv)
         argv++;
     }
 
+    if (keyfile != NULL && argc > 1) {
+        BIO_printf(bio_err, "Can only sign or verify one file\n");
+        goto end;
+    }
+
     if (do_verify && !sigfile) {
         BIO_printf(bio_err,
                    "No signature to verify: use the -signature option\n");
diff --git a/crypto/openssl/apps/enc.c b/crypto/openssl/apps/enc.c
index 7b7c70b132d7..8e2ef27aca34 100644
--- a/crypto/openssl/apps/enc.c
+++ b/crypto/openssl/apps/enc.c
@@ -509,7 +509,7 @@ int MAIN(int argc, char **argv)
                             BIO_printf(bio_err, "invalid hex salt value\n");
                             goto end;
                         }
-                    } else if (RAND_pseudo_bytes(salt, sizeof salt) < 0)
+                    } else if (RAND_bytes(salt, sizeof salt) <= 0)
                         goto end;
                     /*
                      * If -P option then don't bother writing
diff --git a/crypto/openssl/apps/passwd.c b/crypto/openssl/apps/passwd.c
index 5ff53b5743c6..798a6d593616 100644
--- a/crypto/openssl/apps/passwd.c
+++ b/crypto/openssl/apps/passwd.c
@@ -416,7 +416,7 @@ static int do_passwd(int passed_salt, char **salt_p, char **salt_malloc_p,
                 if (*salt_malloc_p == NULL)
                     goto err;
             }
-            if (RAND_pseudo_bytes((unsigned char *)*salt_p, 2) < 0)
+            if (RAND_bytes((unsigned char *)*salt_p, 2) <= 0)
                 goto err;
             (*salt_p)[0] = cov_2char[(*salt_p)[0] & 0x3f]; /* 6 bits */
             (*salt_p)[1] = cov_2char[(*salt_p)[1] & 0x3f]; /* 6 bits */
@@ -437,7 +437,7 @@ static int do_passwd(int passed_salt, char **salt_p, char **salt_malloc_p,
                 if (*salt_malloc_p == NULL)
                     goto err;
             }
-            if (RAND_pseudo_bytes((unsigned char *)*salt_p, 8) < 0)
+            if (RAND_bytes((unsigned char *)*salt_p, 8) <= 0)
                 goto err;
 
             for (i = 0; i < 8; i++)
diff --git a/crypto/openssl/apps/pkcs12.c b/crypto/openssl/apps/pkcs12.c
index cbb75b7d5fe4..82182c29b86d 100644
--- a/crypto/openssl/apps/pkcs12.c
+++ b/crypto/openssl/apps/pkcs12.c
@@ -832,6 +832,7 @@ int dump_certs_pkeys_bag(BIO *out, PKCS12_SAFEBAG *bag, char *pass,
     EVP_PKEY *pkey;
     PKCS8_PRIV_KEY_INFO *p8;
     X509 *x509;
+    int ret = 0;
 
     switch (M_PKCS12_bag_type(bag)) {
     case NID_keyBag:
@@ -844,7 +845,7 @@ int dump_certs_pkeys_bag(BIO *out, PKCS12_SAFEBAG *bag, char *pass,
         if (!(pkey = EVP_PKCS82PKEY(p8)))
             return 0;
         print_attribs(out, p8->attributes, "Key Attributes");
-        PEM_write_bio_PrivateKey(out, pkey, enc, NULL, 0, NULL, pempass);
+        ret = PEM_write_bio_PrivateKey(out, pkey, enc, NULL, 0, NULL, pempass);
         EVP_PKEY_free(pkey);
         break;
 
@@ -864,7 +865,7 @@ int dump_certs_pkeys_bag(BIO *out, PKCS12_SAFEBAG *bag, char *pass,
         }
         print_attribs(out, p8->attributes, "Key Attributes");
         PKCS8_PRIV_KEY_INFO_free(p8);
-        PEM_write_bio_PrivateKey(out, pkey, enc, NULL, 0, NULL, pempass);
+        ret = PEM_write_bio_PrivateKey(out, pkey, enc, NULL, 0, NULL, pempass);
         EVP_PKEY_free(pkey);
         break;
 
@@ -884,7 +885,7 @@ int dump_certs_pkeys_bag(BIO *out, PKCS12_SAFEBAG *bag, char *pass,
         if (!(x509 = PKCS12_certbag2x509(bag)))
             return 0;
         dump_cert_text(out, x509);
-        PEM_write_bio_X509(out, x509);
+        ret = PEM_write_bio_X509(out, x509);
         X509_free(x509);
         break;
 
@@ -902,7 +903,7 @@ int dump_certs_pkeys_bag(BIO *out, PKCS12_SAFEBAG *bag, char *pass,
         return 1;
         break;
     }
-    return 1;
+    return ret;
 }
 
 /* Given a single certificate return a verified chain or NULL if error */
@@ -931,16 +932,70 @@ static int get_cert_chain(X509 *cert, X509_STORE *store,
 
 int alg_print(BIO *x, X509_ALGOR *alg)
 {
-    PBEPARAM *pbe;
-    const unsigned char *p;
-    p = alg->parameter->value.sequence->data;
-    pbe = d2i_PBEPARAM(NULL, &p, alg->parameter->value.sequence->length);
-    if (!pbe)
-        return 1;
-    BIO_printf(bio_err, "%s, Iteration %ld\n",
-               OBJ_nid2ln(OBJ_obj2nid(alg->algorithm)),
-               ASN1_INTEGER_get(pbe->iter));
-    PBEPARAM_free(pbe);
+    int pbenid, aparamtype;
+    ASN1_OBJECT *aoid;
+    void *aparam;
+    PBEPARAM *pbe = NULL;
+
+    X509_ALGOR_get0(&aoid, &aparamtype, &aparam, alg);
+
+    pbenid = OBJ_obj2nid(aoid);
+
+    BIO_printf(x, "%s", OBJ_nid2ln(pbenid));
+
+    /*
+     * If PBE algorithm is PBES2 decode algorithm parameters
+     * for additional details.
+     */
+    if (pbenid == NID_pbes2) {
+        PBE2PARAM *pbe2 = NULL;
+        int encnid;
+        if (aparamtype == V_ASN1_SEQUENCE)
+            pbe2 = ASN1_item_unpack(aparam, ASN1_ITEM_rptr(PBE2PARAM));
+        if (pbe2 == NULL) {
+            BIO_puts(x, "<unsupported parameters>");
+            goto done;
+        }
+        X509_ALGOR_get0(&aoid, &aparamtype, &aparam, pbe2->keyfunc);
+        pbenid = OBJ_obj2nid(aoid);
+        X509_ALGOR_get0(&aoid, NULL, NULL, pbe2->encryption);
+        encnid = OBJ_obj2nid(aoid);
+        BIO_printf(x, ", %s, %s", OBJ_nid2ln(pbenid),
+                   OBJ_nid2sn(encnid));
+        /* If KDF is PBKDF2 decode parameters */
+        if (pbenid == NID_id_pbkdf2) {
+            PBKDF2PARAM *kdf = NULL;
+            int prfnid;
+            if (aparamtype == V_ASN1_SEQUENCE)
+                kdf = ASN1_item_unpack(aparam, ASN1_ITEM_rptr(PBKDF2PARAM));
+            if (kdf == NULL) {
+                BIO_puts(x, "<unsupported parameters>");
+                goto done;
+            }
+
+            if (kdf->prf == NULL) {
+                prfnid = NID_hmacWithSHA1;
+            } else {
+                X509_ALGOR_get0(&aoid, NULL, NULL, kdf->prf);
+                prfnid = OBJ_obj2nid(aoid);
+            }
+            BIO_printf(x, ", Iteration %ld, PRF %s",
+                       ASN1_INTEGER_get(kdf->iter), OBJ_nid2sn(prfnid));
+            PBKDF2PARAM_free(kdf);
+        }
+        PBE2PARAM_free(pbe2);
+    } else {
+        if (aparamtype == V_ASN1_SEQUENCE)
+            pbe = ASN1_item_unpack(aparam, ASN1_ITEM_rptr(PBEPARAM));
+        if (pbe == NULL) {
+            BIO_puts(x, "<unsupported parameters>");
+            goto done;
+        }
+        BIO_printf(x, ", Iteration %ld", ASN1_INTEGER_get(pbe->iter));
+        PBEPARAM_free(pbe);
+    }
+ done:
+    BIO_puts(x, "\n");
     return 1;
 }
 
diff --git a/crypto/openssl/apps/req.c b/crypto/openssl/apps/req.c
index e818bd2976d6..d1411c91bbb8 100644
--- a/crypto/openssl/apps/req.c
+++ b/crypto/openssl/apps/req.c
@@ -332,9 +332,10 @@ int MAIN(int argc, char **argv)
             subject = 1;
         else if (strcmp(*argv, "-text") == 0)
             text = 1;
-        else if (strcmp(*argv, "-x509") == 0)
+        else if (strcmp(*argv, "-x509") == 0) {
+            newreq = 1;
             x509 = 1;
-        else if (strcmp(*argv, "-asn1-kludge") == 0)
+        } else if (strcmp(*argv, "-asn1-kludge") == 0)
             kludge = 1;
         else if (strcmp(*argv, "-no-asn1-kludge") == 0)
             kludge = 0;
@@ -756,7 +757,7 @@ int MAIN(int argc, char **argv)
         }
     }
 
-    if (newreq || x509) {
+    if (newreq) {
         if (pkey == NULL) {
             BIO_printf(bio_err, "you need to specify a private key\n");
             goto end;
@@ -1331,12 +1332,11 @@ static int auto_info(X509_REQ *req, STACK_OF(CONF_VALUE) *dn_sk,
                 break;
             }
 #ifndef CHARSET_EBCDIC
-        if (*p == '+')
+        if (*type == '+') {
 #else
-        if (*p == os_toascii['+'])
+        if (*type == os_toascii['+']) {
 #endif
-        {
-            p++;
+            type++;
             mval = -1;
         } else
             mval = 0;
diff --git a/crypto/openssl/apps/s_apps.h b/crypto/openssl/apps/s_apps.h
index 5b54bfdc4e1c..5ba1e1d6d86d 100644
--- a/crypto/openssl/apps/s_apps.h
+++ b/crypto/openssl/apps/s_apps.h
@@ -199,7 +199,8 @@ int load_excert(SSL_EXCERT **pexc, BIO *err);
 void print_ssl_summary(BIO *bio, SSL *s);
 #ifdef HEADER_SSL_H
 int args_ssl(char ***pargs, int *pargc, SSL_CONF_CTX *cctx,
-             int *badarg, BIO *err, STACK_OF(OPENSSL_STRING) **pstr);
+             int *badarg, BIO *err, STACK_OF(OPENSSL_STRING) **pstr,
+             int *no_prot_opt);
 int args_ssl_call(SSL_CTX *ctx, BIO *err, SSL_CONF_CTX *cctx,
                   STACK_OF(OPENSSL_STRING) *str, int no_ecdhe, int no_jpake);
 int ssl_ctx_add_crls(SSL_CTX *ctx, STACK_OF(X509_CRL) *crls,
diff --git a/crypto/openssl/apps/s_cb.c b/crypto/openssl/apps/s_cb.c
index 5b5e711bf2eb..d1a99a7bd605 100644
--- a/crypto/openssl/apps/s_cb.c
+++ b/crypto/openssl/apps/s_cb.c
@@ -1507,11 +1507,18 @@ void print_ssl_summary(BIO *bio, SSL *s)
 }
 
 int args_ssl(char ***pargs, int *pargc, SSL_CONF_CTX *cctx,
-             int *badarg, BIO *err, STACK_OF(OPENSSL_STRING) **pstr)
+             int *badarg, BIO *err, STACK_OF(OPENSSL_STRING) **pstr,
+             int *no_prot_opt)
 {
     char *arg = **pargs, *argn = (*pargs)[1];
     int rv;
 
+    if (strcmp(arg, "-no_ssl2") == 0 || strcmp(arg, "-no_ssl3") == 0
+        || strcmp(arg, "-no_tls1") == 0 || strcmp(arg, "-no_tls1_1") == 0
+        || strcmp(arg, "-no_tls1_2") == 0) {
+        *no_prot_opt = 1;
+    }
+
     /* Attempt to run SSL configuration command */
     rv = SSL_CONF_cmd_argv(cctx, pargc, pargs);
     /* If parameter not recognised just return */
diff --git a/crypto/openssl/apps/s_client.c b/crypto/openssl/apps/s_client.c
index 0c1102b9c36a..41a326fbb859 100644
--- a/crypto/openssl/apps/s_client.c
+++ b/crypto/openssl/apps/s_client.c
@@ -242,9 +242,9 @@ static unsigned int psk_client_cb(SSL *ssl, const char *hint, char *identity,
                                   unsigned char *psk,
                                   unsigned int max_psk_len)
 {
-    unsigned int psk_len = 0;
     int ret;
-    BIGNUM *bn = NULL;
+    long key_len;
+    unsigned char *key;
 
     if (c_debug)
         BIO_printf(bio_c_out, "psk_client_cb\n");
@@ -265,32 +265,29 @@ static unsigned int psk_client_cb(SSL *ssl, const char *hint, char *identity,
     if (c_debug)
         BIO_printf(bio_c_out, "created identity '%s' len=%d\n", identity,
                    ret);
-    ret = BN_hex2bn(&bn, psk_key);
-    if (!ret) {
-        BIO_printf(bio_err, "Could not convert PSK key '%s' to BIGNUM\n",
+
+    /* convert the PSK key to binary */
+    key = string_to_hex(psk_key, &key_len);
+    if (key == NULL) {
+        BIO_printf(bio_err, "Could not convert PSK key '%s' to buffer\n",
                    psk_key);
-        if (bn)
-            BN_free(bn);
         return 0;
     }
-
-    if ((unsigned int)BN_num_bytes(bn) > max_psk_len) {
+    if ((unsigned long)key_len > (unsigned long)max_psk_len) {
         BIO_printf(bio_err,
-                   "psk buffer of callback is too small (%d) for key (%d)\n",
-                   max_psk_len, BN_num_bytes(bn));
-        BN_free(bn);
+                   "psk buffer of callback is too small (%d) for key (%ld)\n",
+                   max_psk_len, key_len);
+        OPENSSL_free(key);
         return 0;
     }
 
-    psk_len = BN_bn2bin(bn, psk);
-    BN_free(bn);
-    if (psk_len == 0)
-        goto out_err;
+    memcpy(psk, key, key_len);
+    OPENSSL_free(key);
 
     if (c_debug)
-        BIO_printf(bio_c_out, "created PSK len=%d\n", psk_len);
+        BIO_printf(bio_c_out, "created PSK len=%ld\n", key_len);
 
-    return psk_len;
+    return key_len;
  out_err:
     if (c_debug)
         BIO_printf(bio_err, "Error in PSK client callback\n");
@@ -747,6 +744,7 @@ int MAIN(int argc, char **argv)
     int crl_format = FORMAT_PEM;
     int crl_download = 0;
     STACK_OF(X509_CRL) *crls = NULL;
+    int prot_opt = 0, no_prot_opt = 0;
 
     meth = SSLv23_client_method();
 
@@ -850,7 +848,8 @@ int MAIN(int argc, char **argv)
             if (badarg)
                 goto bad;
             continue;
-        } else if (args_ssl(&argv, &argc, cctx, &badarg, bio_err, &ssl_args)) {
+        } else if (args_ssl(&argv, &argc, cctx, &badarg, bio_err, &ssl_args,
+                            &no_prot_opt)) {
             if (badarg)
                 goto bad;
             continue;
@@ -942,31 +941,42 @@ int MAIN(int argc, char **argv)
         }
 #endif
 #ifndef OPENSSL_NO_SSL2
-        else if (strcmp(*argv, "-ssl2") == 0)
+        else if (strcmp(*argv, "-ssl2") == 0) {
             meth = SSLv2_client_method();
+            prot_opt++;
+        }
 #endif
 #ifndef OPENSSL_NO_SSL3_METHOD
-        else if (strcmp(*argv, "-ssl3") == 0)
+        else if (strcmp(*argv, "-ssl3") == 0) {
             meth = SSLv3_client_method();
+            prot_opt++;
+        }
 #endif
 #ifndef OPENSSL_NO_TLS1
-        else if (strcmp(*argv, "-tls1_2") == 0)
+        else if (strcmp(*argv, "-tls1_2") == 0) {
             meth = TLSv1_2_client_method();
-        else if (strcmp(*argv, "-tls1_1") == 0)
+            prot_opt++;
+        } else if (strcmp(*argv, "-tls1_1") == 0) {
             meth = TLSv1_1_client_method();
-        else if (strcmp(*argv, "-tls1") == 0)
+            prot_opt++;
+        } else if (strcmp(*argv, "-tls1") == 0) {
             meth = TLSv1_client_method();
+            prot_opt++;
+        }
 #endif
 #ifndef OPENSSL_NO_DTLS1
         else if (strcmp(*argv, "-dtls") == 0) {
             meth = DTLS_client_method();
             socket_type = SOCK_DGRAM;
+            prot_opt++;
         } else if (strcmp(*argv, "-dtls1") == 0) {
             meth = DTLSv1_client_method();
             socket_type = SOCK_DGRAM;
+            prot_opt++;
         } else if (strcmp(*argv, "-dtls1_2") == 0) {
             meth = DTLSv1_2_client_method();
             socket_type = SOCK_DGRAM;
+            prot_opt++;
         } else if (strcmp(*argv, "-timeout") == 0)
             enable_timeouts = 1;
         else if (strcmp(*argv, "-mtu") == 0) {
@@ -1149,6 +1159,17 @@ int MAIN(int argc, char **argv)
     }
 #endif
 
+    if (prot_opt > 1) {
+        BIO_printf(bio_err, "Cannot supply multiple protocol flags\n");
+        goto end;
+    }
+
+    if (prot_opt == 1 && no_prot_opt) {
+        BIO_printf(bio_err, "Cannot supply both a protocol flag and "
+                            "\"-no_<prot>\"\n");
+        goto end;
+    }
+
     OpenSSL_add_ssl_algorithms();
     SSL_load_error_strings();
 
@@ -1540,7 +1561,10 @@ int MAIN(int argc, char **argv)
     SSL_set_connect_state(con);
 
     /* ok, lets connect */
-    width = SSL_get_fd(con) + 1;
+    if (fileno_stdin() > SSL_get_fd(con))
+        width = fileno_stdin() + 1;
+    else
+        width = SSL_get_fd(con) + 1;
 
     read_tty = 1;
     write_tty = 0;
@@ -1723,9 +1747,11 @@ int MAIN(int argc, char **argv)
 #if !defined(OPENSSL_SYS_WINDOWS) && !defined(OPENSSL_SYS_MSDOS) && !defined(OPENSSL_SYS_NETWARE) && !defined (OPENSSL_SYS_BEOS_R5)
             if (tty_on) {
                 if (read_tty)
-                    openssl_fdset(fileno(stdin), &readfds);
+                    openssl_fdset(fileno_stdin(), &readfds);
+#if !defined(OPENSSL_SYS_VMS)
                 if (write_tty)
-                    openssl_fdset(fileno(stdout), &writefds);
+                    openssl_fdset(fileno_stdout(), &writefds);
+#endif
             }
             if (read_ssl)
                 openssl_fdset(SSL_get_fd(con), &readfds);
@@ -1795,14 +1821,14 @@ int MAIN(int argc, char **argv)
             /* Under BeOS-R5 the situation is similar to DOS */
             i = 0;
             stdin_set = 0;
-            (void)fcntl(fileno(stdin), F_SETFL, O_NONBLOCK);
+            (void)fcntl(fileno_stdin(), F_SETFL, O_NONBLOCK);
             if (!write_tty) {
                 if (read_tty) {
                     tv.tv_sec = 1;
                     tv.tv_usec = 0;
                     i = select(width, (void *)&readfds, (void *)&writefds,
                                NULL, &tv);
-                    if (read(fileno(stdin), sbuf, 0) >= 0)
+                    if (read(fileno_stdin(), sbuf, 0) >= 0)
                         stdin_set = 1;
                     if (!i && (stdin_set != 1 || !read_tty))
                         continue;
@@ -1810,7 +1836,7 @@ int MAIN(int argc, char **argv)
                     i = select(width, (void *)&readfds, (void *)&writefds,
                                NULL, timeoutp);
             }
-            (void)fcntl(fileno(stdin), F_SETFL, 0);
+            (void)fcntl(fileno_stdin(), F_SETFL, 0);
 #else
             i = select(width, (void *)&readfds, (void *)&writefds,
                        NULL, timeoutp);
@@ -1886,11 +1912,11 @@ int MAIN(int argc, char **argv)
                 goto shut;
             }
         }
-#if defined(OPENSSL_SYS_WINDOWS) || defined(OPENSSL_SYS_MSDOS) || defined(OPENSSL_SYS_NETWARE) || defined(OPENSSL_SYS_BEOS_R5)
+#if defined(OPENSSL_SYS_WINDOWS) || defined(OPENSSL_SYS_MSDOS) || defined(OPENSSL_SYS_NETWARE) || defined(OPENSSL_SYS_BEOS_R5) || defined(OPENSSL_SYS_VMS)
         /* Assume Windows/DOS/BeOS can always write */
         else if (!ssl_pending && write_tty)
 #else
-        else if (!ssl_pending && FD_ISSET(fileno(stdout), &writefds))
+        else if (!ssl_pending && FD_ISSET(fileno_stdout(), &writefds))
 #endif
         {
 #ifdef CHARSET_EBCDIC
@@ -1988,7 +2014,7 @@ int MAIN(int argc, char **argv)
 #elif defined(OPENSSL_SYS_BEOS_R5)
         else if (stdin_set)
 #else
-        else if (FD_ISSET(fileno(stdin), &readfds))
+        else if (FD_ISSET(fileno_stdin(), &readfds))
 #endif
         {
             if (crlf) {
diff --git a/crypto/openssl/apps/s_server.c b/crypto/openssl/apps/s_server.c
index 09c755b55cfe..857a70e3e4c5 100644
--- a/crypto/openssl/apps/s_server.c
+++ b/crypto/openssl/apps/s_server.c
@@ -353,9 +353,8 @@ static unsigned int psk_server_cb(SSL *ssl, const char *identity,
                                   unsigned char *psk,
                                   unsigned int max_psk_len)
 {
-    unsigned int psk_len = 0;
-    int ret;
-    BIGNUM *bn = NULL;
+    long key_len = 0;
+    unsigned char *key;
 
     if (s_debug)
         BIO_printf(bio_s_out, "psk_server_cb\n");
@@ -377,32 +376,26 @@ static unsigned int psk_server_cb(SSL *ssl, const char *identity,
         BIO_printf(bio_s_out, "PSK client identity found\n");
 
     /* convert the PSK key to binary */
-    ret = BN_hex2bn(&bn, psk_key);
-    if (!ret) {
-        BIO_printf(bio_err, "Could not convert PSK key '%s' to BIGNUM\n",
+    key = string_to_hex(psk_key, &key_len);
+    if (key == NULL) {
+        BIO_printf(bio_err, "Could not convert PSK key '%s' to buffer\n",
                    psk_key);
-        if (bn)
-            BN_free(bn);
         return 0;
     }
-    if (BN_num_bytes(bn) > (int)max_psk_len) {
+    if (key_len > (int)max_psk_len) {
         BIO_printf(bio_err,
-                   "psk buffer of callback is too small (%d) for key (%d)\n",
-                   max_psk_len, BN_num_bytes(bn));
-        BN_free(bn);
+                   "psk buffer of callback is too small (%d) for key (%ld)\n",
+                   max_psk_len, key_len);
+        OPENSSL_free(key);
         return 0;
     }
 
-    ret = BN_bn2bin(bn, psk);
-    BN_free(bn);
-
-    if (ret < 0)
-        goto out_err;
-    psk_len = (unsigned int)ret;
+    memcpy(psk, key, key_len);
+    OPENSSL_free(key);
 
     if (s_debug)
-        BIO_printf(bio_s_out, "fetched PSK len=%d\n", psk_len);
-    return psk_len;
+        BIO_printf(bio_s_out, "fetched PSK len=%ld\n", key_len);
+    return key_len;
  out_err:
     if (s_debug)
         BIO_printf(bio_err, "Error in PSK server callback\n");
@@ -1144,6 +1137,7 @@ int MAIN(int argc, char *argv[])
     int crl_format = FORMAT_PEM;
     int crl_download = 0;
     STACK_OF(X509_CRL) *crls = NULL;
+    int prot_opt = 0, no_prot_opt = 0;
 
     meth = SSLv23_server_method();
 
@@ -1307,7 +1301,8 @@ int MAIN(int argc, char *argv[])
             if (badarg)
                 goto bad;
             continue;
-        } else if (args_ssl(&argv, &argc, cctx, &badarg, bio_err, &ssl_args)) {
+        } else if (args_ssl(&argv, &argc, cctx, &badarg, bio_err, &ssl_args,
+                            &no_prot_opt)) {
             if (badarg)
                 goto bad;
             continue;
@@ -1451,32 +1446,40 @@ int MAIN(int argc, char *argv[])
         else if (strcmp(*argv, "-ssl2") == 0) {
             no_ecdhe = 1;
             meth = SSLv2_server_method();
+            prot_opt++;
         }
 #endif
 #ifndef OPENSSL_NO_SSL3_METHOD
         else if (strcmp(*argv, "-ssl3") == 0) {
             meth = SSLv3_server_method();
+            prot_opt++;
         }
 #endif
 #ifndef OPENSSL_NO_TLS1
         else if (strcmp(*argv, "-tls1") == 0) {
             meth = TLSv1_server_method();
+            prot_opt++;
         } else if (strcmp(*argv, "-tls1_1") == 0) {
             meth = TLSv1_1_server_method();
+            prot_opt++;
         } else if (strcmp(*argv, "-tls1_2") == 0) {
             meth = TLSv1_2_server_method();
+            prot_opt++;
         }
 #endif
 #ifndef OPENSSL_NO_DTLS1
         else if (strcmp(*argv, "-dtls") == 0) {
             meth = DTLS_server_method();
             socket_type = SOCK_DGRAM;
+            prot_opt++;
         } else if (strcmp(*argv, "-dtls1") == 0) {
             meth = DTLSv1_server_method();
             socket_type = SOCK_DGRAM;
+            prot_opt++;
         } else if (strcmp(*argv, "-dtls1_2") == 0) {
             meth = DTLSv1_2_server_method();
             socket_type = SOCK_DGRAM;
+            prot_opt++;
         } else if (strcmp(*argv, "-timeout") == 0)
             enable_timeouts = 1;
         else if (strcmp(*argv, "-mtu") == 0) {
@@ -1586,6 +1589,17 @@ int MAIN(int argc, char *argv[])
     }
 #endif
 
+    if (prot_opt > 1) {
+        BIO_printf(bio_err, "Cannot supply multiple protocol flags\n");
+        goto end;
+    }
+
+    if (prot_opt == 1 && no_prot_opt) {
+        BIO_printf(bio_err, "Cannot supply both a protocol flag and "
+                            "\"-no_<prot>\"\n");
+        goto end;
+    }
+
     SSL_load_error_strings();
     OpenSSL_add_ssl_algorithms();
 
@@ -2293,7 +2307,10 @@ static int sv_body(char *hostname, int s, int stype, unsigned char *context)
     }
 #endif
 
-    width = s + 1;
+    if (fileno_stdin() > s)
+        width = fileno_stdin() + 1;
+    else
+        width = s + 1;
     for (;;) {
         int read_from_terminal;
         int read_from_sslcon;
@@ -2304,7 +2321,7 @@ static int sv_body(char *hostname, int s, int stype, unsigned char *context)
         if (!read_from_sslcon) {
             FD_ZERO(&readfds);
 #if !defined(OPENSSL_SYS_WINDOWS) && !defined(OPENSSL_SYS_MSDOS) && !defined(OPENSSL_SYS_NETWARE) && !defined(OPENSSL_SYS_BEOS_R5)
-            openssl_fdset(fileno(stdin), &readfds);
+            openssl_fdset(fileno_stdin(), &readfds);
 #endif
             openssl_fdset(s, &readfds);
             /*
@@ -2332,13 +2349,13 @@ static int sv_body(char *hostname, int s, int stype, unsigned char *context)
             /* Under BeOS-R5 the situation is similar to DOS */
             tv.tv_sec = 1;
             tv.tv_usec = 0;
-            (void)fcntl(fileno(stdin), F_SETFL, O_NONBLOCK);
+            (void)fcntl(fileno_stdin(), F_SETFL, O_NONBLOCK);
             i = select(width, (void *)&readfds, NULL, NULL, &tv);
-            if ((i < 0) || (!i && read(fileno(stdin), buf, 0) < 0))
+            if ((i < 0) || (!i && read(fileno_stdin(), buf, 0) < 0))
                 continue;
-            if (read(fileno(stdin), buf, 0) >= 0)
+            if (read(fileno_stdin(), buf, 0) >= 0)
                 read_from_terminal = 1;
-            (void)fcntl(fileno(stdin), F_SETFL, 0);
+            (void)fcntl(fileno_stdin(), F_SETFL, 0);
 #else
             if ((SSL_version(con) == DTLS1_VERSION) &&
                 DTLSv1_get_timeout(con, &timeout))
@@ -2355,7 +2372,7 @@ static int sv_body(char *hostname, int s, int stype, unsigned char *context)
 
             if (i <= 0)
                 continue;
-            if (FD_ISSET(fileno(stdin), &readfds))
+            if (FD_ISSET(fileno_stdin(), &readfds))
                 read_from_terminal = 1;
 #endif
             if (FD_ISSET(s, &readfds))
@@ -2382,6 +2399,7 @@ static int sv_body(char *hostname, int s, int stype, unsigned char *context)
                 assert(lf_num == 0);
             } else
                 i = raw_read_stdin(buf, bufsize);
+
             if (!s_quiet && !s_brief) {
                 if ((i <= 0) || (buf[0] == 'Q')) {
                     BIO_printf(bio_s_out, "DONE\n");
@@ -3371,7 +3389,7 @@ static int generate_session_id(const SSL *ssl, unsigned char *id,
 {
     unsigned int count = 0;
     do {
-        if (RAND_pseudo_bytes(id, *id_len) < 0)
+        if (RAND_bytes(id, *id_len) <= 0)
             return 0;
         /*
          * Prefix the session_id with the required prefix. NB: If our prefix
diff --git a/crypto/openssl/apps/speed.c b/crypto/openssl/apps/speed.c
index 95adcc19cc15..b862868eacc7 100644
--- a/crypto/openssl/apps/speed.c
+++ b/crypto/openssl/apps/speed.c
@@ -2614,6 +2614,10 @@ static int do_multi(int multi)
     static char sep[] = ":";
 
     fds = malloc(multi * sizeof *fds);
+    if (fds == NULL) {
+        fprintf(stderr, "Out of memory in speed (do_multi)\n");
+        exit(1);
+    }
     for (n = 0; n < multi; ++n) {
         if (pipe(fd) == -1) {
             fprintf(stderr, "pipe failure\n");
diff --git a/crypto/openssl/apps/srp.c b/crypto/openssl/apps/srp.c
index c0ff4171cabf..c75052f38dd4 100644
--- a/crypto/openssl/apps/srp.c
+++ b/crypto/openssl/apps/srp.c
@@ -765,4 +765,6 @@ int MAIN(int argc, char **argv)
     OPENSSL_EXIT(ret);
 }
 
+#else
+static void *dummy = &dummy;
 #endif
diff --git a/crypto/openssl/apps/verify.c b/crypto/openssl/apps/verify.c
index 78e729fc890f..b5ae6b370e1e 100644
--- a/crypto/openssl/apps/verify.c
+++ b/crypto/openssl/apps/verify.c
@@ -115,43 +115,43 @@ int MAIN(int argc, char **argv)
         if (argc >= 1) {
             if (strcmp(*argv, "-CApath") == 0) {
                 if (argc-- < 1)
-                    goto end;
+                    goto usage;
                 CApath = *(++argv);
             } else if (strcmp(*argv, "-CAfile") == 0) {
                 if (argc-- < 1)
-                    goto end;
+                    goto usage;
                 CAfile = *(++argv);
             } else if (args_verify(&argv, &argc, &badarg, bio_err, &vpm)) {
                 if (badarg)
-                    goto end;
+                    goto usage;
                 continue;
             } else if (strcmp(*argv, "-untrusted") == 0) {
                 if (argc-- < 1)
-                    goto end;
+                    goto usage;
                 untfile = *(++argv);
             } else if (strcmp(*argv, "-trusted") == 0) {
                 if (argc-- < 1)
-                    goto end;
+                    goto usage;
                 trustfile = *(++argv);
             } else if (strcmp(*argv, "-CRLfile") == 0) {
                 if (argc-- < 1)
-                    goto end;
+                    goto usage;
                 crlfile = *(++argv);
             } else if (strcmp(*argv, "-crl_download") == 0)
                 crl_download = 1;
 #ifndef OPENSSL_NO_ENGINE
             else if (strcmp(*argv, "-engine") == 0) {
                 if (--argc < 1)
-                    goto end;
+                    goto usage;
                 engine = *(++argv);
             }
 #endif
             else if (strcmp(*argv, "-help") == 0)
-                goto end;
+                goto usage;
             else if (strcmp(*argv, "-verbose") == 0)
                 v_verbose = 1;
             else if (argv[0][0] == '-')
-                goto end;
+                goto usage;
             else
                 break;
             argc--;
@@ -228,7 +228,7 @@ int MAIN(int argc, char **argv)
                 ret = -1;
     }
 
- end:
+ usage:
     if (ret == 1) {
         BIO_printf(bio_err,
                    "usage: verify [-verbose] [-CApath path] [-CAfile file] [-purpose purpose] [-crl_check]");
@@ -247,6 +247,7 @@ int MAIN(int argc, char **argv)
                        X509_PURPOSE_get0_name(ptmp));
         }
     }
+ end:
     if (vpm)
         X509_VERIFY_PARAM_free(vpm);
     if (cert_ctx != NULL)
diff --git a/crypto/openssl/apps/x509.c b/crypto/openssl/apps/x509.c
index 7c215bced001..17cb62da726d 100644
--- a/crypto/openssl/apps/x509.c
+++ b/crypto/openssl/apps/x509.c
@@ -1105,6 +1105,10 @@ static int x509_certify(X509_STORE *ctx, char *CAfile, const EVP_MD *digest,
     EVP_PKEY *upkey;
 
     upkey = X509_get_pubkey(xca);
+    if (upkey == NULL)  {
+        BIO_printf(bio_err, "Error obtaining CA X509 public key\n");
+        goto end;
+    }
     EVP_PKEY_copy_parameters(upkey, pkey);
     EVP_PKEY_free(upkey);
 
@@ -1217,6 +1221,8 @@ static int sign(X509 *x, EVP_PKEY *pkey, int days, int clrext,
     EVP_PKEY *pktmp;
 
     pktmp = X509_get_pubkey(x);
+    if (pktmp == NULL)
+        goto err;
     EVP_PKEY_copy_parameters(pktmp, pkey);
     EVP_PKEY_save_parameters(pktmp, 1);
     EVP_PKEY_free(pktmp);
diff --git a/crypto/openssl/crypto/LPdir_unix.c b/crypto/openssl/crypto/LPdir_unix.c
index bead6abd7156..c97e260492b9 100644
--- a/crypto/openssl/crypto/LPdir_unix.c
+++ b/crypto/openssl/crypto/LPdir_unix.c
@@ -1,8 +1,4 @@
 /*
- * $LP: LPlib/source/LPdir_unix.c,v 1.11 2004/09/23 22:07:22 _cvs_levitte Exp
- * $
- */
-/*
  * Copyright (c) 2004, Richard Levitte <richard@levitte.org>
  * All rights reserved.
  *
diff --git a/crypto/openssl/crypto/aes/asm/bsaes-armv7.pl b/crypto/openssl/crypto/aes/asm/bsaes-armv7.pl
index fcc81d1a4933..83343e2de1af 100755
--- a/crypto/openssl/crypto/aes/asm/bsaes-armv7.pl
+++ b/crypto/openssl/crypto/aes/asm/bsaes-armv7.pl
@@ -1797,8 +1797,6 @@ $code.=<<___;
 	b		.Lxts_enc_done
 .align	4
 .Lxts_enc_6:
-	vst1.64		{@XMM[14]}, [r0,:128]		@ next round tweak
-
 	veor		@XMM[4], @XMM[4], @XMM[12]
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1834,8 +1832,6 @@ $code.=<<___;
 
 .align	5
 .Lxts_enc_5:
-	vst1.64		{@XMM[13]}, [r0,:128]		@ next round tweak
-
 	veor		@XMM[3], @XMM[3], @XMM[11]
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1864,8 +1860,6 @@ $code.=<<___;
 	b		.Lxts_enc_done
 .align	4
 .Lxts_enc_4:
-	vst1.64		{@XMM[12]}, [r0,:128]		@ next round tweak
-
 	veor		@XMM[2], @XMM[2], @XMM[10]
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1891,8 +1885,6 @@ $code.=<<___;
 	b		.Lxts_enc_done
 .align	4
 .Lxts_enc_3:
-	vst1.64		{@XMM[11]}, [r0,:128]		@ next round tweak
-
 	veor		@XMM[1], @XMM[1], @XMM[9]
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1917,8 +1909,6 @@ $code.=<<___;
 	b		.Lxts_enc_done
 .align	4
 .Lxts_enc_2:
-	vst1.64		{@XMM[10]}, [r0,:128]		@ next round tweak
-
 	veor		@XMM[0], @XMM[0], @XMM[8]
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1941,7 +1931,7 @@ $code.=<<___;
 .align	4
 .Lxts_enc_1:
 	mov		r0, sp
-	veor		@XMM[0], @XMM[8]
+	veor		@XMM[0], @XMM[0], @XMM[8]
 	mov		r1, sp
 	vst1.8		{@XMM[0]}, [sp,:128]
 	mov		r2, $key
@@ -2251,8 +2241,6 @@ $code.=<<___;
 	b		.Lxts_dec_done
 .align	4
 .Lxts_dec_5:
-	vst1.64		{@XMM[13]}, [r0,:128]		@ next round tweak
-
 	veor		@XMM[3], @XMM[3], @XMM[11]
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -2281,8 +2269,6 @@ $code.=<<___;
 	b		.Lxts_dec_done
 .align	4
 .Lxts_dec_4:
-	vst1.64		{@XMM[12]}, [r0,:128]		@ next round tweak
-
 	veor		@XMM[2], @XMM[2], @XMM[10]
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -2308,8 +2294,6 @@ $code.=<<___;
 	b		.Lxts_dec_done
 .align	4
 .Lxts_dec_3:
-	vst1.64		{@XMM[11]}, [r0,:128]		@ next round tweak
-
 	veor		@XMM[1], @XMM[1], @XMM[9]
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -2334,8 +2318,6 @@ $code.=<<___;
 	b		.Lxts_dec_done
 .align	4
 .Lxts_dec_2:
-	vst1.64		{@XMM[10]}, [r0,:128]		@ next round tweak
-
 	veor		@XMM[0], @XMM[0], @XMM[8]
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -2358,12 +2340,12 @@ $code.=<<___;
 .align	4
 .Lxts_dec_1:
 	mov		r0, sp
-	veor		@XMM[0], @XMM[8]
+	veor		@XMM[0], @XMM[0], @XMM[8]
 	mov		r1, sp
 	vst1.8		{@XMM[0]}, [sp,:128]
+	mov		r5, $magic			@ preserve magic
 	mov		r2, $key
 	mov		r4, $fp				@ preserve fp
-	mov		r5, $magic			@ preserve magic
 
 	bl		AES_decrypt
 
diff --git a/crypto/openssl/crypto/asn1/a_bytes.c b/crypto/openssl/crypto/asn1/a_bytes.c
index 385b53986a29..65e5394664a4 100644
--- a/crypto/openssl/crypto/asn1/a_bytes.c
+++ b/crypto/openssl/crypto/asn1/a_bytes.c
@@ -60,7 +60,12 @@
 #include "cryptlib.h"
 #include <openssl/asn1.h>
 
-static int asn1_collate_primitive(ASN1_STRING *a, ASN1_const_CTX *c);
+static int asn1_collate_primitive(ASN1_STRING *a, ASN1_const_CTX *c,
+                                  int depth);
+static ASN1_STRING *int_d2i_ASN1_bytes(ASN1_STRING **a,
+                                       const unsigned char **pp, long length,
+                                       int Ptag, int Pclass, int depth,
+                                       int *perr);
 /*
  * type is a 'bitmap' of acceptable string types.
  */
@@ -99,7 +104,7 @@ ASN1_STRING *d2i_ASN1_type_bytes(ASN1_STRING **a, const unsigned char **pp,
         ret = (*a);
 
     if (len != 0) {
-        s = (unsigned char *)OPENSSL_malloc((int)len + 1);
+        s = OPENSSL_malloc((int)len + 1);
         if (s == NULL) {
             i = ERR_R_MALLOC_FAILURE;
             goto err;
@@ -154,15 +159,38 @@ int i2d_ASN1_bytes(ASN1_STRING *a, unsigned char **pp, int tag, int xclass)
     return (r);
 }
 
+/*
+ * Maximum recursion depth of d2i_ASN1_bytes(): much more than should be
+ * encountered in pratice.
+ */
+
+#define ASN1_BYTES_MAXDEPTH 20
+
 ASN1_STRING *d2i_ASN1_bytes(ASN1_STRING **a, const unsigned char **pp,
                             long length, int Ptag, int Pclass)
 {
+    int err = 0;
+    ASN1_STRING *s = int_d2i_ASN1_bytes(a, pp, length, Ptag, Pclass, 0, &err);
+    if (err != 0)
+        ASN1err(ASN1_F_D2I_ASN1_BYTES, err);
+    return s;
+}
+
+static ASN1_STRING *int_d2i_ASN1_bytes(ASN1_STRING **a,
+                                       const unsigned char **pp, long length,
+                                       int Ptag, int Pclass,
+                                       int depth, int *perr)
+{
     ASN1_STRING *ret = NULL;
     const unsigned char *p;
     unsigned char *s;
     long len;
     int inf, tag, xclass;
-    int i = 0;
+
+    if (depth > ASN1_BYTES_MAXDEPTH) {
+        *perr = ASN1_R_NESTED_ASN1_STRING;
+        return NULL;
+    }
 
     if ((a == NULL) || ((*a) == NULL)) {
         if ((ret = ASN1_STRING_new()) == NULL)
@@ -173,18 +201,19 @@ ASN1_STRING *d2i_ASN1_bytes(ASN1_STRING **a, const unsigned char **pp,
     p = *pp;
     inf = ASN1_get_object(&p, &len, &tag, &xclass, length);
     if (inf & 0x80) {
-        i = ASN1_R_BAD_OBJECT_HEADER;
+        *perr = ASN1_R_BAD_OBJECT_HEADER;
         goto err;
     }
 
     if (tag != Ptag) {
-        i = ASN1_R_WRONG_TAG;
+        *perr = ASN1_R_WRONG_TAG;
         goto err;
     }
 
     if (inf & V_ASN1_CONSTRUCTED) {
         ASN1_const_CTX c;
 
+        c.error = 0;
         c.pp = pp;
         c.p = p;
         c.inf = inf;
@@ -192,17 +221,18 @@ ASN1_STRING *d2i_ASN1_bytes(ASN1_STRING **a, const unsigned char **pp,
         c.tag = Ptag;
         c.xclass = Pclass;
         c.max = (length == 0) ? 0 : (p + length);
-        if (!asn1_collate_primitive(ret, &c))
+        if (!asn1_collate_primitive(ret, &c, depth)) {
+            *perr = c.error;
             goto err;
-        else {
+        } else {
             p = c.p;
         }
     } else {
         if (len != 0) {
             if ((ret->length < len) || (ret->data == NULL)) {
-                s = (unsigned char *)OPENSSL_malloc((int)len + 1);
+                s = OPENSSL_malloc((int)len + 1);
                 if (s == NULL) {
-                    i = ERR_R_MALLOC_FAILURE;
+                    *perr = ERR_R_MALLOC_FAILURE;
                     goto err;
                 }
                 if (ret->data != NULL)
@@ -230,7 +260,6 @@ ASN1_STRING *d2i_ASN1_bytes(ASN1_STRING **a, const unsigned char **pp,
  err:
     if ((ret != NULL) && ((a == NULL) || (*a != ret)))
         ASN1_STRING_free(ret);
-    ASN1err(ASN1_F_D2I_ASN1_BYTES, i);
     return (NULL);
 }
 
@@ -242,7 +271,8 @@ ASN1_STRING *d2i_ASN1_bytes(ASN1_STRING **a, const unsigned char **pp,
  * There have been a few bug fixes for this function from Paul Keogh
  * <paul.keogh@sse.ie>, many thanks to him
  */
-static int asn1_collate_primitive(ASN1_STRING *a, ASN1_const_CTX *c)
+static int asn1_collate_primitive(ASN1_STRING *a, ASN1_const_CTX *c,
+                                  int depth)
 {
     ASN1_STRING *os = NULL;
     BUF_MEM b;
@@ -270,9 +300,8 @@ static int asn1_collate_primitive(ASN1_STRING *a, ASN1_const_CTX *c)
         }
 
         c->q = c->p;
-        if (d2i_ASN1_bytes(&os, &c->p, c->max - c->p, c->tag, c->xclass)
-            == NULL) {
-            c->error = ERR_R_ASN1_LIB;
+        if (int_d2i_ASN1_bytes(&os, &c->p, c->max - c->p, c->tag, c->xclass,
+                               depth + 1, &c->error) == NULL) {
             goto err;
         }
 
@@ -297,7 +326,6 @@ static int asn1_collate_primitive(ASN1_STRING *a, ASN1_const_CTX *c)
         ASN1_STRING_free(os);
     return (1);
  err:
-    ASN1err(ASN1_F_ASN1_COLLATE_PRIMITIVE, c->error);
     if (os != NULL)
         ASN1_STRING_free(os);
     if (b.data != NULL)
diff --git a/crypto/openssl/crypto/asn1/a_object.c b/crypto/openssl/crypto/asn1/a_object.c
index 27f9c1691462..229a40ffa344 100644
--- a/crypto/openssl/crypto/asn1/a_object.c
+++ b/crypto/openssl/crypto/asn1/a_object.c
@@ -73,7 +73,7 @@ int i2d_ASN1_OBJECT(ASN1_OBJECT *a, unsigned char **pp)
         return (0);
 
     objsize = ASN1_object_size(0, a->length, V_ASN1_OBJECT);
-    if (pp == NULL)
+    if (pp == NULL || objsize == -1)
         return objsize;
 
     p = *pp;
@@ -174,8 +174,12 @@ int a2d_ASN1_OBJECT(unsigned char *out, int olen, const char *buf, int num)
                 if (!tmp)
                     goto err;
             }
-            while (blsize--)
-                tmp[i++] = (unsigned char)BN_div_word(bl, 0x80L);
+            while (blsize--) {
+                BN_ULONG t = BN_div_word(bl, 0x80L);
+                if (t == (BN_ULONG)-1)
+                    goto err;
+                tmp[i++] = (unsigned char)t;
+            }
         } else {
 
             for (;;) {
diff --git a/crypto/openssl/crypto/asn1/a_set.c b/crypto/openssl/crypto/asn1/a_set.c
index bf3f97188926..5fb58655757d 100644
--- a/crypto/openssl/crypto/asn1/a_set.c
+++ b/crypto/openssl/crypto/asn1/a_set.c
@@ -57,6 +57,7 @@
  */
 
 #include <stdio.h>
+#include <limits.h>
 #include "cryptlib.h"
 #include <openssl/asn1_mac.h>
 
@@ -98,10 +99,14 @@ int i2d_ASN1_SET(STACK_OF(OPENSSL_BLOCK) *a, unsigned char **pp,
 
     if (a == NULL)
         return (0);
-    for (i = sk_OPENSSL_BLOCK_num(a) - 1; i >= 0; i--)
+    for (i = sk_OPENSSL_BLOCK_num(a) - 1; i >= 0; i--) {
+        int tmplen = i2d(sk_OPENSSL_BLOCK_value(a, i), NULL);
+        if (tmplen > INT_MAX - ret)
+            return -1;
         ret += i2d(sk_OPENSSL_BLOCK_value(a, i), NULL);
+    }
     r = ASN1_object_size(1, ret, ex_tag);
-    if (pp == NULL)
+    if (pp == NULL || r == -1)
         return (r);
 
     p = *pp;
diff --git a/crypto/openssl/crypto/asn1/a_strex.c b/crypto/openssl/crypto/asn1/a_strex.c
index 35fd44cd22b8..2d562f93452f 100644
--- a/crypto/openssl/crypto/asn1/a_strex.c
+++ b/crypto/openssl/crypto/asn1/a_strex.c
@@ -337,7 +337,7 @@ static const signed char tag2nbyte[] = {
     -1, -1, -1, -1, -1,         /* 5-9 */
     -1, -1, 0, -1,              /* 10-13 */
     -1, -1, -1, -1,             /* 15-17 */
-    -1, 1, 1,                   /* 18-20 */
+    1, 1, 1,                    /* 18-20 */
     -1, 1, 1, 1,                /* 21-24 */
     -1, 1, -1,                  /* 25-27 */
     4, -1, 2                    /* 28-30 */
diff --git a/crypto/openssl/crypto/asn1/a_strnid.c b/crypto/openssl/crypto/asn1/a_strnid.c
index 52243453689a..2d2303d8599e 100644
--- a/crypto/openssl/crypto/asn1/a_strnid.c
+++ b/crypto/openssl/crypto/asn1/a_strnid.c
@@ -250,6 +250,7 @@ int ASN1_STRING_TABLE_add(int nid,
         }
         tmp->flags = flags | STABLE_FLAGS_MALLOC;
         tmp->nid = nid;
+        tmp->minsize = tmp->maxsize = -1;
         new_nid = 1;
     } else
         tmp->flags = (tmp->flags & STABLE_FLAGS_MALLOC) | flags;
diff --git a/crypto/openssl/crypto/asn1/ameth_lib.c b/crypto/openssl/crypto/asn1/ameth_lib.c
index 5389c0434740..43ddebba33a6 100644
--- a/crypto/openssl/crypto/asn1/ameth_lib.c
+++ b/crypto/openssl/crypto/asn1/ameth_lib.c
@@ -93,7 +93,9 @@ static const EVP_PKEY_ASN1_METHOD *standard_methods[] = {
     &eckey_asn1_meth,
 #endif
     &hmac_asn1_meth,
+#ifndef OPENSSL_NO_CMAC
     &cmac_asn1_meth,
+#endif
 #ifndef OPENSSL_NO_DH
     &dhx_asn1_meth
 #endif
diff --git a/crypto/openssl/crypto/asn1/asn1_lib.c b/crypto/openssl/crypto/asn1/asn1_lib.c
index 874b1af8b09a..e63e82a8b476 100644
--- a/crypto/openssl/crypto/asn1/asn1_lib.c
+++ b/crypto/openssl/crypto/asn1/asn1_lib.c
@@ -256,26 +256,30 @@ static void asn1_put_length(unsigned char **pp, int length)
 
 int ASN1_object_size(int constructed, int length, int tag)
 {
-    int ret;
-
-    ret = length;
-    ret++;
+    int ret = 1;
+    if (length < 0)
+        return -1;
     if (tag >= 31) {
         while (tag > 0) {
             tag >>= 7;
             ret++;
         }
     }
-    if (constructed == 2)
-        return ret + 3;
-    ret++;
-    if (length > 127) {
-        while (length > 0) {
-            length >>= 8;
-            ret++;
+    if (constructed == 2) {
+        ret += 3;
+    } else {
+        ret++;
+        if (length > 127) {
+            int tmplen = length;
+            while (tmplen > 0) {
+                tmplen >>= 8;
+                ret++;
+            }
         }
     }
-    return (ret);
+    if (ret >= INT_MAX - length)
+        return -1;
+    return ret + length;
 }
 
 static int _asn1_Finish(ASN1_const_CTX *c)
@@ -324,7 +328,7 @@ int asn1_GetSequence(ASN1_const_CTX *c, long *length)
         return (0);
     }
     if (c->inf == (1 | V_ASN1_CONSTRUCTED))
-        c->slen = *length + *(c->pp) - c->p;
+        c->slen = *length;
     c->eos = 0;
     return (1);
 }
@@ -366,7 +370,7 @@ int ASN1_STRING_set(ASN1_STRING *str, const void *_data, int len)
         else
             len = strlen(data);
     }
-    if ((str->length < len) || (str->data == NULL)) {
+    if ((str->length <= len) || (str->data == NULL)) {
         c = str->data;
         if (c == NULL)
             str->data = OPENSSL_malloc(len + 1);
diff --git a/crypto/openssl/crypto/asn1/asn_mime.c b/crypto/openssl/crypto/asn1/asn_mime.c
index 96110c540f3d..5170906c62da 100644
--- a/crypto/openssl/crypto/asn1/asn_mime.c
+++ b/crypto/openssl/crypto/asn1/asn_mime.c
@@ -289,7 +289,7 @@ int SMIME_write_ASN1(BIO *bio, ASN1_VALUE *val, BIO *data, int flags,
     if ((flags & SMIME_DETACHED) && data) {
         /* We want multipart/signed */
         /* Generate a random boundary */
-        if (RAND_pseudo_bytes((unsigned char *)bound, 32) < 0)
+        if (RAND_bytes((unsigned char *)bound, 32) <= 0)
             return 0;
         for (i = 0; i < 32; i++) {
             c = bound[i] & 0xf;
@@ -623,6 +623,8 @@ static int multi_split(BIO *bio, char *bound, STACK_OF(BIO) **ret)
                 if (bpart)
                     sk_BIO_push(parts, bpart);
                 bpart = BIO_new(BIO_s_mem());
+                if (bpart == NULL)
+                    return 1;
                 BIO_set_mem_eof_return(bpart, 0);
             } else if (eol)
                 BIO_write(bpart, "\r\n", 2);
diff --git a/crypto/openssl/crypto/asn1/bio_asn1.c b/crypto/openssl/crypto/asn1/bio_asn1.c
index 60189b3b2c53..c3afff69dc7e 100644
--- a/crypto/openssl/crypto/asn1/bio_asn1.c
+++ b/crypto/openssl/crypto/asn1/bio_asn1.c
@@ -170,10 +170,12 @@ static int asn1_bio_init(BIO_ASN1_BUF_CTX *ctx, int size)
     ctx->copylen = 0;
     ctx->asn1_class = V_ASN1_UNIVERSAL;
     ctx->asn1_tag = V_ASN1_OCTET_STRING;
-    ctx->ex_buf = 0;
-    ctx->ex_pos = 0;
+    ctx->ex_buf = NULL;
     ctx->ex_len = 0;
+    ctx->ex_pos = 0;
     ctx->state = ASN1_STATE_START;
+    ctx->prefix = ctx->prefix_free = ctx->suffix = ctx->suffix_free = NULL;
+    ctx->ex_arg = NULL;
     return 1;
 }
 
diff --git a/crypto/openssl/crypto/asn1/bio_ndef.c b/crypto/openssl/crypto/asn1/bio_ndef.c
index 31949b87940f..8d7046633cfe 100644
--- a/crypto/openssl/crypto/asn1/bio_ndef.c
+++ b/crypto/openssl/crypto/asn1/bio_ndef.c
@@ -136,6 +136,7 @@ BIO *BIO_new_NDEF(BIO *out, ASN1_VALUE *val, const ASN1_ITEM *it)
     ndef_aux->ndef_bio = sarg.ndef_bio;
     ndef_aux->boundary = sarg.boundary;
     ndef_aux->out = out;
+    ndef_aux->derbuf = NULL;
 
     BIO_ctrl(asn_bio, BIO_C_SET_EX_ARG, 0, ndef_aux);
 
diff --git a/crypto/openssl/crypto/asn1/charmap.pl b/crypto/openssl/crypto/asn1/charmap.pl
index 25ebf2c205d0..12ac34ad7423 100644
--- a/crypto/openssl/crypto/asn1/charmap.pl
+++ b/crypto/openssl/crypto/asn1/charmap.pl
@@ -67,17 +67,19 @@ $arr[ord("?")] |= $PSTRING_CHAR;
 # Now generate the C code
 
 print <<EOF;
-/* Auto generated with chartype.pl script.
- * Mask of various character properties
+/*
+ * Auto generated with chartype.pl script. Mask of various character
+ * properties
  */
 
-static unsigned char char_type[] = {
+static const unsigned char char_type[] = {
 EOF
 
+print "   ";
 for($i = 0; $i < 128; $i++) {
-	print("\n") if($i && (($i % 16) == 0));
-	printf("%2d", $arr[$i]);
+	print("\n   ") if($i && (($i % 16) == 0));
+	printf(" %d", $arr[$i]);
 	print(",") if ($i != 127);
 }
-print("\n};\n\n");
+print("\n};\n");
 
diff --git a/crypto/openssl/crypto/asn1/d2i_pr.c b/crypto/openssl/crypto/asn1/d2i_pr.c
index d21829af192f..86dcf5fba9d7 100644
--- a/crypto/openssl/crypto/asn1/d2i_pr.c
+++ b/crypto/openssl/crypto/asn1/d2i_pr.c
@@ -97,15 +97,17 @@ EVP_PKEY *d2i_PrivateKey(int type, EVP_PKEY **a, const unsigned char **pp,
     if (!ret->ameth->old_priv_decode ||
         !ret->ameth->old_priv_decode(ret, &p, length)) {
         if (ret->ameth->priv_decode) {
+            EVP_PKEY *tmp;
             PKCS8_PRIV_KEY_INFO *p8 = NULL;
             p8 = d2i_PKCS8_PRIV_KEY_INFO(NULL, &p, length);
             if (!p8)
                 goto err;
-            EVP_PKEY_free(ret);
-            ret = EVP_PKCS82PKEY(p8);
+            tmp = EVP_PKCS82PKEY(p8);
             PKCS8_PRIV_KEY_INFO_free(p8);
-            if (ret == NULL)
+            if (tmp == NULL)
                 goto err;
+            EVP_PKEY_free(ret);
+            ret = tmp;
         } else {
             ASN1err(ASN1_F_D2I_PRIVATEKEY, ERR_R_ASN1_LIB);
             goto err;
diff --git a/crypto/openssl/crypto/asn1/f_enum.c b/crypto/openssl/crypto/asn1/f_enum.c
index 591c3b578127..94cd54dbeedd 100644
--- a/crypto/openssl/crypto/asn1/f_enum.c
+++ b/crypto/openssl/crypto/asn1/f_enum.c
@@ -160,8 +160,6 @@ int a2i_ASN1_ENUMERATED(BIO *bp, ASN1_ENUMERATED *bs, char *buf, int size)
                                                       i * 2);
             if (sp == NULL) {
                 ASN1err(ASN1_F_A2I_ASN1_ENUMERATED, ERR_R_MALLOC_FAILURE);
-                if (s != NULL)
-                    OPENSSL_free(s);
                 goto err;
             }
             s = sp;
@@ -199,5 +197,7 @@ int a2i_ASN1_ENUMERATED(BIO *bp, ASN1_ENUMERATED *bs, char *buf, int size)
  err_sl:
         ASN1err(ASN1_F_A2I_ASN1_ENUMERATED, ASN1_R_SHORT_LINE);
     }
+    if (ret != 1)
+        OPENSSL_free(s);
     return (ret);
 }
diff --git a/crypto/openssl/crypto/asn1/f_int.c b/crypto/openssl/crypto/asn1/f_int.c
index 4a81f81c8832..2bdc78d74491 100644
--- a/crypto/openssl/crypto/asn1/f_int.c
+++ b/crypto/openssl/crypto/asn1/f_int.c
@@ -172,8 +172,6 @@ int a2i_ASN1_INTEGER(BIO *bp, ASN1_INTEGER *bs, char *buf, int size)
                 sp = OPENSSL_realloc_clean(s, slen, num + i * 2);
             if (sp == NULL) {
                 ASN1err(ASN1_F_A2I_ASN1_INTEGER, ERR_R_MALLOC_FAILURE);
-                if (s != NULL)
-                    OPENSSL_free(s);
                 goto err;
             }
             s = sp;
@@ -211,5 +209,7 @@ int a2i_ASN1_INTEGER(BIO *bp, ASN1_INTEGER *bs, char *buf, int size)
  err_sl:
         ASN1err(ASN1_F_A2I_ASN1_INTEGER, ASN1_R_SHORT_LINE);
     }
+    if (ret != 1)
+        OPENSSL_free(s);
     return (ret);
 }
diff --git a/crypto/openssl/crypto/asn1/f_string.c b/crypto/openssl/crypto/asn1/f_string.c
index 6a6cf3471408..0f7b9cfb119b 100644
--- a/crypto/openssl/crypto/asn1/f_string.c
+++ b/crypto/openssl/crypto/asn1/f_string.c
@@ -166,8 +166,6 @@ int a2i_ASN1_STRING(BIO *bp, ASN1_STRING *bs, char *buf, int size)
                                                       i * 2);
             if (sp == NULL) {
                 ASN1err(ASN1_F_A2I_ASN1_STRING, ERR_R_MALLOC_FAILURE);
-                if (s != NULL)
-                    OPENSSL_free(s);
                 goto err;
             }
             s = sp;
@@ -205,5 +203,7 @@ int a2i_ASN1_STRING(BIO *bp, ASN1_STRING *bs, char *buf, int size)
  err_sl:
         ASN1err(ASN1_F_A2I_ASN1_STRING, ASN1_R_SHORT_LINE);
     }
+    if (ret != 1)
+        OPENSSL_free(s);
     return (ret);
 }
diff --git a/crypto/openssl/crypto/asn1/i2d_pr.c b/crypto/openssl/crypto/asn1/i2d_pr.c
index 4d338ac55aed..12966ec536e1 100644
--- a/crypto/openssl/crypto/asn1/i2d_pr.c
+++ b/crypto/openssl/crypto/asn1/i2d_pr.c
@@ -69,10 +69,13 @@ int i2d_PrivateKey(EVP_PKEY *a, unsigned char **pp)
     }
     if (a->ameth && a->ameth->priv_encode) {
         PKCS8_PRIV_KEY_INFO *p8 = EVP_PKEY2PKCS8(a);
-        int ret = i2d_PKCS8_PRIV_KEY_INFO(p8, pp);
-        PKCS8_PRIV_KEY_INFO_free(p8);
+        int ret = 0;
+        if (p8 != NULL) {
+            ret = i2d_PKCS8_PRIV_KEY_INFO(p8, pp);
+            PKCS8_PRIV_KEY_INFO_free(p8);
+        }
         return ret;
     }
     ASN1err(ASN1_F_I2D_PRIVATEKEY, ASN1_R_UNSUPPORTED_PUBLIC_KEY_TYPE);
-    return (-1);
+    return -1;
 }
diff --git a/crypto/openssl/crypto/asn1/p5_pbe.c b/crypto/openssl/crypto/asn1/p5_pbe.c
index bdbfdcd67c07..e2a1def53f1d 100644
--- a/crypto/openssl/crypto/asn1/p5_pbe.c
+++ b/crypto/openssl/crypto/asn1/p5_pbe.c
@@ -101,7 +101,7 @@ int PKCS5_pbe_set0_algor(X509_ALGOR *algor, int alg, int iter,
     sstr = ASN1_STRING_data(pbe->salt);
     if (salt)
         memcpy(sstr, salt, saltlen);
-    else if (RAND_pseudo_bytes(sstr, saltlen) < 0)
+    else if (RAND_bytes(sstr, saltlen) <= 0)
         goto err;
 
     if (!ASN1_item_pack(pbe, ASN1_ITEM_rptr(PBEPARAM), &pbe_str)) {
diff --git a/crypto/openssl/crypto/asn1/p5_pbev2.c b/crypto/openssl/crypto/asn1/p5_pbev2.c
index 73ba4a3d67aa..388053e0a1bf 100644
--- a/crypto/openssl/crypto/asn1/p5_pbev2.c
+++ b/crypto/openssl/crypto/asn1/p5_pbev2.c
@@ -120,7 +120,7 @@ X509_ALGOR *PKCS5_pbe2_set_iv(const EVP_CIPHER *cipher, int iter,
     if (EVP_CIPHER_iv_length(cipher)) {
         if (aiv)
             memcpy(iv, aiv, EVP_CIPHER_iv_length(cipher));
-        else if (RAND_pseudo_bytes(iv, EVP_CIPHER_iv_length(cipher)) < 0)
+        else if (RAND_bytes(iv, EVP_CIPHER_iv_length(cipher)) <= 0)
             goto err;
     }
 
@@ -225,7 +225,7 @@ X509_ALGOR *PKCS5_pbkdf2_set(int iter, unsigned char *salt, int saltlen,
 
     if (salt)
         memcpy(osalt->data, salt, saltlen);
-    else if (RAND_pseudo_bytes(osalt->data, saltlen) < 0)
+    else if (RAND_bytes(osalt->data, saltlen) <= 0)
         goto merr;
 
     if (iter <= 0)
diff --git a/crypto/openssl/crypto/asn1/t_req.c b/crypto/openssl/crypto/asn1/t_req.c
index 024553ab196f..70aba4cc3b3b 100644
--- a/crypto/openssl/crypto/asn1/t_req.c
+++ b/crypto/openssl/crypto/asn1/t_req.c
@@ -196,6 +196,7 @@ int X509_REQ_print_ex(BIO *bp, X509_REQ *x, unsigned long nmflags,
                 if (BIO_puts(bp, ":") <= 0)
                     goto err;
                 if ((type == V_ASN1_PRINTABLESTRING) ||
+                    (type == V_ASN1_UTF8STRING) ||
                     (type == V_ASN1_T61STRING) ||
                     (type == V_ASN1_IA5STRING)) {
                     if (BIO_write(bp, (char *)bs->data, bs->length)
diff --git a/crypto/openssl/crypto/asn1/tasn_dec.c b/crypto/openssl/crypto/asn1/tasn_dec.c
index 6bdcd5c542ca..d25402730b8b 100644
--- a/crypto/openssl/crypto/asn1/tasn_dec.c
+++ b/crypto/openssl/crypto/asn1/tasn_dec.c
@@ -400,7 +400,9 @@ int ASN1_item_ex_d2i(ASN1_VALUE **pval, const unsigned char **in, long len,
             if (tt->flags & ASN1_TFLG_ADB_MASK) {
                 const ASN1_TEMPLATE *seqtt;
                 ASN1_VALUE **pseqval;
-                seqtt = asn1_do_adb(pval, tt, 1);
+                seqtt = asn1_do_adb(pval, tt, 0);
+                if (seqtt == NULL)
+                    continue;
                 pseqval = asn1_get_field_ptr(pval, seqtt);
                 ASN1_template_free(pseqval, seqtt);
             }
@@ -411,7 +413,7 @@ int ASN1_item_ex_d2i(ASN1_VALUE **pval, const unsigned char **in, long len,
             const ASN1_TEMPLATE *seqtt;
             ASN1_VALUE **pseqval;
             seqtt = asn1_do_adb(pval, tt, 1);
-            if (!seqtt)
+            if (seqtt == NULL)
                 goto err;
             pseqval = asn1_get_field_ptr(pval, seqtt);
             /* Have we ran out of data? */
@@ -476,7 +478,7 @@ int ASN1_item_ex_d2i(ASN1_VALUE **pval, const unsigned char **in, long len,
         for (; i < it->tcount; tt++, i++) {
             const ASN1_TEMPLATE *seqtt;
             seqtt = asn1_do_adb(pval, tt, 1);
-            if (!seqtt)
+            if (seqtt == NULL)
                 goto err;
             if (seqtt->flags & ASN1_TFLG_OPTIONAL) {
                 ASN1_VALUE **pseqval;
diff --git a/crypto/openssl/crypto/asn1/tasn_enc.c b/crypto/openssl/crypto/asn1/tasn_enc.c
index f7f83e56a981..081a9d534f8a 100644
--- a/crypto/openssl/crypto/asn1/tasn_enc.c
+++ b/crypto/openssl/crypto/asn1/tasn_enc.c
@@ -59,6 +59,7 @@
 
 #include <stddef.h>
 #include <string.h>
+#include <limits.h>
 #include "cryptlib.h"
 #include <openssl/asn1.h>
 #include <openssl/asn1t.h>
@@ -216,17 +217,19 @@ int ASN1_item_ex_i2d(ASN1_VALUE **pval, unsigned char **out,
         for (i = 0, tt = it->templates; i < it->tcount; tt++, i++) {
             const ASN1_TEMPLATE *seqtt;
             ASN1_VALUE **pseqval;
+            int tmplen;
             seqtt = asn1_do_adb(pval, tt, 1);
             if (!seqtt)
                 return 0;
             pseqval = asn1_get_field_ptr(pval, seqtt);
-            /* FIXME: check for errors in enhanced version */
-            seqcontlen += asn1_template_ex_i2d(pseqval, NULL, seqtt,
-                                               -1, aclass);
+            tmplen = asn1_template_ex_i2d(pseqval, NULL, seqtt, -1, aclass);
+            if (tmplen == -1 || (tmplen > INT_MAX - seqcontlen))
+                return -1;
+            seqcontlen += tmplen;
         }
 
         seqlen = ASN1_object_size(ndef, seqcontlen, tag);
-        if (!out)
+        if (!out || seqlen == -1)
             return seqlen;
         /* Output SEQUENCE header */
         ASN1_put_object(out, ndef, seqcontlen, tag, aclass);
@@ -339,19 +342,24 @@ static int asn1_template_ex_i2d(ASN1_VALUE **pval, unsigned char **out,
         /* Determine total length of items */
         skcontlen = 0;
         for (i = 0; i < sk_ASN1_VALUE_num(sk); i++) {
+            int tmplen;
             skitem = sk_ASN1_VALUE_value(sk, i);
-            skcontlen += ASN1_item_ex_i2d(&skitem, NULL,
-                                          ASN1_ITEM_ptr(tt->item),
-                                          -1, iclass);
+            tmplen = ASN1_item_ex_i2d(&skitem, NULL, ASN1_ITEM_ptr(tt->item),
+                                      -1, iclass);
+            if (tmplen == -1 || (skcontlen > INT_MAX - tmplen))
+                return -1;
+            skcontlen += tmplen;
         }
         sklen = ASN1_object_size(ndef, skcontlen, sktag);
+        if (sklen == -1)
+            return -1;
         /* If EXPLICIT need length of surrounding tag */
         if (flags & ASN1_TFLG_EXPTAG)
             ret = ASN1_object_size(ndef, sklen, ttag);
         else
             ret = sklen;
 
-        if (!out)
+        if (!out || ret == -1)
             return ret;
 
         /* Now encode this lot... */
@@ -380,7 +388,7 @@ static int asn1_template_ex_i2d(ASN1_VALUE **pval, unsigned char **out,
             return 0;
         /* Find length of EXPLICIT tag */
         ret = ASN1_object_size(ndef, i, ttag);
-        if (out) {
+        if (out && ret != -1) {
             /* Output tag and item */
             ASN1_put_object(out, ndef, i, ttag, tclass);
             ASN1_item_ex_i2d(pval, out, ASN1_ITEM_ptr(tt->item), -1, iclass);
diff --git a/crypto/openssl/crypto/asn1/tasn_prn.c b/crypto/openssl/crypto/asn1/tasn_prn.c
index 5e7d53e9854a..f628caddbd05 100644
--- a/crypto/openssl/crypto/asn1/tasn_prn.c
+++ b/crypto/openssl/crypto/asn1/tasn_prn.c
@@ -204,7 +204,8 @@ static int asn1_item_print_ctx(BIO *out, ASN1_VALUE **fld, int indent,
     } else
         asn1_cb = 0;
 
-    if (*fld == NULL) {
+   if (((it->itype != ASN1_ITYPE_PRIMITIVE)
+       || (it->utype != V_ASN1_BOOLEAN)) && *fld == NULL) {
         if (pctx->flags & ASN1_PCTX_FLAGS_SHOW_ABSENT) {
             if (!nohdr && !asn1_print_fsname(out, indent, fname, sname, pctx))
                 return 0;
@@ -446,6 +447,8 @@ static int asn1_print_integer_ctx(BIO *out, ASN1_INTEGER *str,
     char *s;
     int ret = 1;
     s = i2s_ASN1_INTEGER(NULL, str);
+    if (s == NULL)
+        return 0;
     if (BIO_puts(out, s) <= 0)
         ret = 0;
     OPENSSL_free(s);
@@ -496,11 +499,16 @@ static int asn1_primitive_print(BIO *out, ASN1_VALUE **fld,
         return 0;
     if (pf && pf->prim_print)
         return pf->prim_print(out, fld, it, indent, pctx);
-    str = (ASN1_STRING *)*fld;
-    if (it->itype == ASN1_ITYPE_MSTRING)
+    if (it->itype == ASN1_ITYPE_MSTRING) {
+        str = (ASN1_STRING *)*fld;
         utype = str->type & ~V_ASN1_NEG;
-    else
+    } else {
         utype = it->utype;
+        if (utype == V_ASN1_BOOLEAN)
+            str = NULL;
+        else
+            str = (ASN1_STRING *)*fld;
+    }
     if (utype == V_ASN1_ANY) {
         ASN1_TYPE *atype = (ASN1_TYPE *)*fld;
         utype = atype->type;
diff --git a/crypto/openssl/crypto/asn1/tasn_utl.c b/crypto/openssl/crypto/asn1/tasn_utl.c
index 41726d8feb4e..e14889feb156 100644
--- a/crypto/openssl/crypto/asn1/tasn_utl.c
+++ b/crypto/openssl/crypto/asn1/tasn_utl.c
@@ -234,7 +234,7 @@ const ASN1_TEMPLATE *asn1_do_adb(ASN1_VALUE **pval, const ASN1_TEMPLATE *tt,
     sfld = offset2ptr(*pval, adb->offset);
 
     /* Check if NULL */
-    if (!sfld) {
+    if (*sfld == NULL) {
         if (!adb->null_tt)
             goto err;
         return adb->null_tt;
diff --git a/crypto/openssl/crypto/asn1/x_bignum.c b/crypto/openssl/crypto/asn1/x_bignum.c
index eaf046639d6a..c644199c9f81 100644
--- a/crypto/openssl/crypto/asn1/x_bignum.c
+++ b/crypto/openssl/crypto/asn1/x_bignum.c
@@ -78,6 +78,8 @@ static int bn_i2c(ASN1_VALUE **pval, unsigned char *cont, int *putype,
                   const ASN1_ITEM *it);
 static int bn_c2i(ASN1_VALUE **pval, const unsigned char *cont, int len,
                   int utype, char *free_cont, const ASN1_ITEM *it);
+static int bn_print(BIO *out, ASN1_VALUE **pval, const ASN1_ITEM *it,
+                    int indent, const ASN1_PCTX *pctx);
 
 static ASN1_PRIMITIVE_FUNCS bignum_pf = {
     NULL, 0,
@@ -85,7 +87,8 @@ static ASN1_PRIMITIVE_FUNCS bignum_pf = {
     bn_free,
     0,
     bn_c2i,
-    bn_i2c
+    bn_i2c,
+    bn_print
 };
 
 ASN1_ITEM_start(BIGNUM)
@@ -151,3 +154,13 @@ static int bn_c2i(ASN1_VALUE **pval, const unsigned char *cont, int len,
     }
     return 1;
 }
+
+static int bn_print(BIO *out, ASN1_VALUE **pval, const ASN1_ITEM *it,
+                    int indent, const ASN1_PCTX *pctx)
+{
+    if (!BN_print(out, *(BIGNUM **)pval))
+        return 0;
+    if (BIO_puts(out, "\n") <= 0)
+        return 0;
+    return 1;
+}
diff --git a/crypto/openssl/crypto/asn1/x_name.c b/crypto/openssl/crypto/asn1/x_name.c
index a858c2993b90..26378fdb2a02 100644
--- a/crypto/openssl/crypto/asn1/x_name.c
+++ b/crypto/openssl/crypto/asn1/x_name.c
@@ -199,10 +199,8 @@ static int x509_name_ex_d2i(ASN1_VALUE **val,
     int i, j, ret;
     STACK_OF(X509_NAME_ENTRY) *entries;
     X509_NAME_ENTRY *entry;
-    if (len > X509_NAME_MAX) {
-        ASN1err(ASN1_F_X509_NAME_EX_D2I, ASN1_R_TOO_LONG);
-        return 0;
-    }
+    if (len > X509_NAME_MAX)
+        len = X509_NAME_MAX;
     q = p;
 
     /* Get internal representation of Name */
diff --git a/crypto/openssl/crypto/asn1/x_x509.c b/crypto/openssl/crypto/asn1/x_x509.c
index e31e1e750d9d..aada4a8413f2 100644
--- a/crypto/openssl/crypto/asn1/x_x509.c
+++ b/crypto/openssl/crypto/asn1/x_x509.c
@@ -199,12 +199,26 @@ X509 *d2i_X509_AUX(X509 **a, const unsigned char **pp, long length)
     return NULL;
 }
 
-int i2d_X509_AUX(X509 *a, unsigned char **pp)
+/*
+ * Serialize trusted certificate to *pp or just return the required buffer
+ * length if pp == NULL.  We ultimately want to avoid modifying *pp in the
+ * error path, but that depends on similar hygiene in lower-level functions.
+ * Here we avoid compounding the problem.
+ */
+static int i2d_x509_aux_internal(X509 *a, unsigned char **pp)
 {
     int length, tmplen;
     unsigned char *start = pp != NULL ? *pp : NULL;
+
+    OPENSSL_assert(pp == NULL || *pp != NULL);
+
+    /*
+     * This might perturb *pp on error, but fixing that belongs in i2d_X509()
+     * not here.  It should be that if a == NULL length is zero, but we check
+     * both just in case.
+     */
     length = i2d_X509(a, pp);
-    if (length < 0 || a == NULL)
+    if (length <= 0 || a == NULL)
         return length;
 
     tmplen = i2d_X509_CERT_AUX(a->aux, pp);
@@ -218,6 +232,42 @@ int i2d_X509_AUX(X509 *a, unsigned char **pp)
     return length;
 }
 
+/*
+ * Serialize trusted certificate to *pp, or just return the required buffer
+ * length if pp == NULL.
+ *
+ * When pp is not NULL, but *pp == NULL, we allocate the buffer, but since
+ * we're writing two ASN.1 objects back to back, we can't have i2d_X509() do
+ * the allocation, nor can we allow i2d_X509_CERT_AUX() to increment the
+ * allocated buffer.
+ */
+int i2d_X509_AUX(X509 *a, unsigned char **pp)
+{
+    int length;
+    unsigned char *tmp;
+
+    /* Buffer provided by caller */
+    if (pp == NULL || *pp != NULL)
+        return i2d_x509_aux_internal(a, pp);
+
+    /* Obtain the combined length */
+    if ((length = i2d_x509_aux_internal(a, NULL)) <= 0)
+        return length;
+
+    /* Allocate requisite combined storage */
+    *pp = tmp = OPENSSL_malloc(length);
+    if (tmp == NULL)
+        return -1; /* Push error onto error stack? */
+
+    /* Encode, but keep *pp at the originally malloced pointer */
+    length = i2d_x509_aux_internal(a, &tmp);
+    if (length <= 0) {
+        OPENSSL_free(*pp);
+        *pp = NULL;
+    }
+    return length;
+}
+
 int i2d_re_X509_tbs(X509 *x, unsigned char **pp)
 {
     x->cert_info->enc.modified = 1;
diff --git a/crypto/openssl/crypto/bio/b_print.c b/crypto/openssl/crypto/bio/b_print.c
index 90248fa2aaba..987fe068c6de 100644
--- a/crypto/openssl/crypto/bio/b_print.c
+++ b/crypto/openssl/crypto/bio/b_print.c
@@ -423,9 +423,15 @@ _dopr(char **sbuffer,
             break;
         }
     }
-    *truncated = (currlen > *maxlen - 1);
-    if (*truncated)
-        currlen = *maxlen - 1;
+    /*
+     * We have to truncate if there is no dynamic buffer and we have filled the
+     * static buffer.
+     */
+    if (buffer == NULL) {
+        *truncated = (currlen > *maxlen - 1);
+        if (*truncated)
+            currlen = *maxlen - 1;
+    }
     if(!doapr_outch(sbuffer, buffer, &currlen, maxlen, '\0'))
         return 0;
     *retlen = currlen - 1;
diff --git a/crypto/openssl/crypto/bio/bf_nbio.c b/crypto/openssl/crypto/bio/bf_nbio.c
index a04f32a00817..4842bb4c82ff 100644
--- a/crypto/openssl/crypto/bio/bf_nbio.c
+++ b/crypto/openssl/crypto/bio/bf_nbio.c
@@ -139,7 +139,7 @@ static int nbiof_read(BIO *b, char *out, int outl)
 
     BIO_clear_retry_flags(b);
 #if 1
-    if (RAND_pseudo_bytes(&n, 1) < 0)
+    if (RAND_bytes(&n, 1) <= 0)
         return -1;
     num = (n & 0x07);
 
@@ -179,7 +179,7 @@ static int nbiof_write(BIO *b, const char *in, int inl)
         num = nt->lwn;
         nt->lwn = 0;
     } else {
-        if (RAND_pseudo_bytes(&n, 1) < 0)
+        if (RAND_bytes(&n, 1) <= 0)
             return -1;
         num = (n & 7);
     }
diff --git a/crypto/openssl/crypto/bio/bio.h b/crypto/openssl/crypto/bio/bio.h
index 6790aed28e0b..8f2438cdad70 100644
--- a/crypto/openssl/crypto/bio/bio.h
+++ b/crypto/openssl/crypto/bio/bio.h
@@ -559,11 +559,11 @@ int BIO_read_filename(BIO *b, const char *name);
 # define BIO_get_ssl(b,sslp)     BIO_ctrl(b,BIO_C_GET_SSL,0,(char *)sslp)
 # define BIO_set_ssl_mode(b,client)      BIO_ctrl(b,BIO_C_SSL_MODE,client,NULL)
 # define BIO_set_ssl_renegotiate_bytes(b,num) \
-        BIO_ctrl(b,BIO_C_SET_SSL_RENEGOTIATE_BYTES,num,NULL);
+        BIO_ctrl(b,BIO_C_SET_SSL_RENEGOTIATE_BYTES,num,NULL)
 # define BIO_get_num_renegotiates(b) \
-        BIO_ctrl(b,BIO_C_GET_SSL_NUM_RENEGOTIATES,0,NULL);
+        BIO_ctrl(b,BIO_C_GET_SSL_NUM_RENEGOTIATES,0,NULL)
 # define BIO_set_ssl_renegotiate_timeout(b,seconds) \
-        BIO_ctrl(b,BIO_C_SET_SSL_RENEGOTIATE_TIMEOUT,seconds,NULL);
+        BIO_ctrl(b,BIO_C_SET_SSL_RENEGOTIATE_TIMEOUT,seconds,NULL)
 
 /* defined in evp.h */
 /* #define BIO_set_md(b,md)     BIO_ctrl(b,BIO_C_SET_MD,1,(char *)md) */
diff --git a/crypto/openssl/crypto/bio/bss_bio.c b/crypto/openssl/crypto/bio/bss_bio.c
index 4d8727f8f890..3dd818772942 100644
--- a/crypto/openssl/crypto/bio/bss_bio.c
+++ b/crypto/openssl/crypto/bio/bss_bio.c
@@ -149,9 +149,13 @@ static int bio_new(BIO *bio)
         return 0;
 
     b->peer = NULL;
+    b->closed = 0;
+    b->len = 0;
+    b->offset = 0;
     /* enough for one TLS record (just a default) */
     b->size = 17 * 1024;
     b->buf = NULL;
+    b->request = 0;
 
     bio->ptr = b;
     return 1;
@@ -655,16 +659,15 @@ static long bio_ctrl(BIO *bio, int cmd, long num, void *ptr)
         break;
 
     case BIO_CTRL_EOF:
-        {
-            BIO *other_bio = ptr;
-
-            if (other_bio) {
-                struct bio_bio_st *other_b = other_bio->ptr;
+        if (b->peer != NULL) {
+            struct bio_bio_st *peer_b = b->peer->ptr;
 
-                assert(other_b != NULL);
-                ret = other_b->len == 0 && other_b->closed;
-            } else
+            if (peer_b->len == 0 && peer_b->closed)
                 ret = 1;
+            else
+                ret = 0;
+        } else {
+            ret = 1;
         }
         break;
 
diff --git a/crypto/openssl/crypto/bio/bss_file.c b/crypto/openssl/crypto/bio/bss_file.c
index bfba93e62bbd..a6e3b3ac0130 100644
--- a/crypto/openssl/crypto/bio/bss_file.c
+++ b/crypto/openssl/crypto/bio/bss_file.c
@@ -174,7 +174,11 @@ BIO *BIO_new_file(const char *filename, const char *mode)
     if (file == NULL) {
         SYSerr(SYS_F_FOPEN, get_last_sys_error());
         ERR_add_error_data(5, "fopen('", filename, "','", mode, "')");
-        if (errno == ENOENT)
+        if (errno == ENOENT
+# ifdef ENXIO
+            || errno == ENXIO
+# endif
+            )
             BIOerr(BIO_F_BIO_NEW_FILE, BIO_R_NO_SUCH_FILE);
         else
             BIOerr(BIO_F_BIO_NEW_FILE, ERR_R_SYS_LIB);
diff --git a/crypto/openssl/crypto/bio/bss_rtcp.c b/crypto/openssl/crypto/bio/bss_rtcp.c
index 09f14f48dc03..5c98a8234d42 100644
--- a/crypto/openssl/crypto/bio/bss_rtcp.c
+++ b/crypto/openssl/crypto/bio/bss_rtcp.c
@@ -170,6 +170,8 @@ static int rtcp_new(BIO *bi)
     bi->num = 0;
     bi->flags = 0;
     bi->ptr = OPENSSL_malloc(sizeof(struct rpc_ctx));
+    if (bi->ptr == NULL)
+        return (0);
     ctx = (struct rpc_ctx *)bi->ptr;
     ctx->filled = 0;
     ctx->pos = 0;
diff --git a/crypto/openssl/crypto/bn/asm/x86-mont.pl b/crypto/openssl/crypto/bn/asm/x86-mont.pl
index 89f4de61e896..1c4003efc20a 100755
--- a/crypto/openssl/crypto/bn/asm/x86-mont.pl
+++ b/crypto/openssl/crypto/bn/asm/x86-mont.pl
@@ -63,27 +63,26 @@ $frame=32;				# size of above frame rounded up to 16n
 
 	&lea	("esi",&wparam(0));	# put aside pointer to argument block
 	&lea	("edx",&wparam(1));	# load ap
-	&mov	("ebp","esp");		# saved stack pointer!
 	&add	("edi",2);		# extra two words on top of tp
 	&neg	("edi");
-	&lea	("esp",&DWP(-$frame,"esp","edi",4));	# alloca($frame+4*(num+2))
+	&lea	("ebp",&DWP(-$frame,"esp","edi",4));	# future alloca($frame+4*(num+2))
 	&neg	("edi");
 
 	# minimize cache contention by arraning 2K window between stack
 	# pointer and ap argument [np is also position sensitive vector,
 	# but it's assumed to be near ap, as it's allocated at ~same
 	# time].
-	&mov	("eax","esp");
+	&mov	("eax","ebp");
 	&sub	("eax","edx");
 	&and	("eax",2047);
-	&sub	("esp","eax");		# this aligns sp and ap modulo 2048
+	&sub	("ebp","eax");		# this aligns sp and ap modulo 2048
 
-	&xor	("edx","esp");
+	&xor	("edx","ebp");
 	&and	("edx",2048);
 	&xor	("edx",2048);
-	&sub	("esp","edx");		# this splits them apart modulo 4096
+	&sub	("ebp","edx");		# this splits them apart modulo 4096
 
-	&and	("esp",-64);		# align to cache line
+	&and	("ebp",-64);		# align to cache line
 
 	# Some OSes, *cough*-dows, insist on stack being "wired" to
 	# physical memory in strictly sequential manner, i.e. if stack
@@ -91,20 +90,28 @@ $frame=32;				# size of above frame rounded up to 16n
 	# be punishable by SEGV. But page walking can do good even on
 	# other OSes, because it guarantees that villain thread hits
 	# the guard page before it can make damage to innocent one...
-	&mov	("eax","ebp");
-	&sub	("eax","esp");
+	&mov	("eax","esp");
+	&sub	("eax","ebp");
 	&and	("eax",-4096);
-&set_label("page_walk");
-	&mov	("edx",&DWP(0,"esp","eax"));
-	&sub	("eax",4096);
-	&data_byte(0x2e);
-	&jnc	(&label("page_walk"));
+	&mov	("edx","esp");		# saved stack pointer!
+	&lea	("esp",&DWP(0,"ebp","eax"));
+	&mov	("eax",&DWP(0,"esp"));
+	&cmp	("esp","ebp");
+	&ja	(&label("page_walk"));
+	&jmp	(&label("page_walk_done"));
+
+&set_label("page_walk",16);
+	&lea	("esp",&DWP(-4096,"esp"));
+	&mov	("eax",&DWP(0,"esp"));
+	&cmp	("esp","ebp");
+	&ja	(&label("page_walk"));
+&set_label("page_walk_done");
 
 	################################# load argument block...
 	&mov	("eax",&DWP(0*4,"esi"));# BN_ULONG *rp
 	&mov	("ebx",&DWP(1*4,"esi"));# const BN_ULONG *ap
 	&mov	("ecx",&DWP(2*4,"esi"));# const BN_ULONG *bp
-	&mov	("edx",&DWP(3*4,"esi"));# const BN_ULONG *np
+	&mov	("ebp",&DWP(3*4,"esi"));# const BN_ULONG *np
 	&mov	("esi",&DWP(4*4,"esi"));# const BN_ULONG *n0
 	#&mov	("edi",&DWP(5*4,"esi"));# int num
 
@@ -112,11 +119,11 @@ $frame=32;				# size of above frame rounded up to 16n
 	&mov	($_rp,"eax");		# ... save a copy of argument block
 	&mov	($_ap,"ebx");
 	&mov	($_bp,"ecx");
-	&mov	($_np,"edx");
+	&mov	($_np,"ebp");
 	&mov	($_n0,"esi");
 	&lea	($num,&DWP(-3,"edi"));	# num=num-1 to assist modulo-scheduling
 	#&mov	($_num,$num);		# redundant as $num is not reused
-	&mov	($_sp,"ebp");		# saved stack pointer!
+	&mov	($_sp,"edx");		# saved stack pointer!
 
 if($sse2) {
 $acc0="mm0";	# mmx register bank layout
diff --git a/crypto/openssl/crypto/bn/asm/x86_64-gcc.c b/crypto/openssl/crypto/bn/asm/x86_64-gcc.c
index d77dc433d405..1729b479d43e 100644
--- a/crypto/openssl/crypto/bn/asm/x86_64-gcc.c
+++ b/crypto/openssl/crypto/bn/asm/x86_64-gcc.c
@@ -194,7 +194,7 @@ BN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d)
     BN_ULONG ret, waste;
 
  asm("divq      %4":"=a"(ret), "=d"(waste)
- :     "a"(l), "d"(h), "g"(d)
+ :     "a"(l), "d"(h), "r"(d)
  :     "cc");
 
     return ret;
diff --git a/crypto/openssl/crypto/bn/asm/x86_64-mont.pl b/crypto/openssl/crypto/bn/asm/x86_64-mont.pl
index 8fb6c994e1ef..044fd7ecc0fd 100755
--- a/crypto/openssl/crypto/bn/asm/x86_64-mont.pl
+++ b/crypto/openssl/crypto/bn/asm/x86_64-mont.pl
@@ -97,6 +97,8 @@ $code=<<___;
 .type	bn_mul_mont,\@function,6
 .align	16
 bn_mul_mont:
+	mov	${num}d,${num}d
+	mov	%rsp,%rax
 	test	\$3,${num}d
 	jnz	.Lmul_enter
 	cmp	\$8,${num}d
@@ -121,29 +123,36 @@ $code.=<<___;
 	push	%r14
 	push	%r15
 
-	mov	${num}d,${num}d
-	lea	2($num),%r10
+	neg	$num
 	mov	%rsp,%r11
-	neg	%r10
-	lea	(%rsp,%r10,8),%rsp	# tp=alloca(8*(num+2))
-	and	\$-1024,%rsp		# minimize TLB usage
+	lea	-16(%rsp,$num,8),%r10	# future alloca(8*(num+2))
+	neg	$num			# restore $num
+	and	\$-1024,%r10		# minimize TLB usage
 
-	mov	%r11,8(%rsp,$num,8)	# tp[num+1]=%rsp
-.Lmul_body:
 	# Some OSes, *cough*-dows, insist on stack being "wired" to
 	# physical memory in strictly sequential manner, i.e. if stack
 	# allocation spans two pages, then reference to farmost one can
 	# be punishable by SEGV. But page walking can do good even on
 	# other OSes, because it guarantees that villain thread hits
 	# the guard page before it can make damage to innocent one...
-	sub	%rsp,%r11
+	sub	%r10,%r11
 	and	\$-4096,%r11
+	lea	(%r10,%r11),%rsp
+	mov	(%rsp),%r11
+	cmp	%r10,%rsp
+	ja	.Lmul_page_walk
+	jmp	.Lmul_page_walk_done
+
+.align	16
 .Lmul_page_walk:
-	mov	(%rsp,%r11),%r10
-	sub	\$4096,%r11
-	.byte	0x66,0x2e		# predict non-taken
-	jnc	.Lmul_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r11
+	cmp	%r10,%rsp
+	ja	.Lmul_page_walk
+.Lmul_page_walk_done:
 
+	mov	%rax,8(%rsp,$num,8)	# tp[num+1]=%rsp
+.Lmul_body:
 	mov	$bp,%r12		# reassign $bp
 ___
 		$bp="%r12";
@@ -314,13 +323,13 @@ $code.=<<___;
 
 	mov	8(%rsp,$num,8),%rsi	# restore %rsp
 	mov	\$1,%rax
-	mov	(%rsi),%r15
-	mov	8(%rsi),%r14
-	mov	16(%rsi),%r13
-	mov	24(%rsi),%r12
-	mov	32(%rsi),%rbp
-	mov	40(%rsi),%rbx
-	lea	48(%rsi),%rsp
+	mov	-48(%rsi),%r15
+	mov	-40(%rsi),%r14
+	mov	-32(%rsi),%r13
+	mov	-24(%rsi),%r12
+	mov	-16(%rsi),%rbp
+	mov	-8(%rsi),%rbx
+	lea	(%rsi),%rsp
 .Lmul_epilogue:
 	ret
 .size	bn_mul_mont,.-bn_mul_mont
@@ -332,6 +341,8 @@ $code.=<<___;
 .type	bn_mul4x_mont,\@function,6
 .align	16
 bn_mul4x_mont:
+	mov	${num}d,${num}d
+	mov	%rsp,%rax
 .Lmul4x_enter:
 ___
 $code.=<<___ if ($addx);
@@ -347,23 +358,29 @@ $code.=<<___;
 	push	%r14
 	push	%r15
 
-	mov	${num}d,${num}d
-	lea	4($num),%r10
+	neg	$num
 	mov	%rsp,%r11
-	neg	%r10
-	lea	(%rsp,%r10,8),%rsp	# tp=alloca(8*(num+4))
-	and	\$-1024,%rsp		# minimize TLB usage
+	lea	-32(%rsp,$num,8),%r10	# future alloca(8*(num+4))
+	neg	$num			# restore
+	and	\$-1024,%r10		# minimize TLB usage
 
-	mov	%r11,8(%rsp,$num,8)	# tp[num+1]=%rsp
-.Lmul4x_body:
-	sub	%rsp,%r11
+	sub	%r10,%r11
 	and	\$-4096,%r11
+	lea	(%r10,%r11),%rsp
+	mov	(%rsp),%r11
+	cmp	%r10,%rsp
+	ja	.Lmul4x_page_walk
+	jmp	.Lmul4x_page_walk_done
+
 .Lmul4x_page_walk:
-	mov	(%rsp,%r11),%r10
-	sub	\$4096,%r11
-	.byte	0x2e			# predict non-taken
-	jnc	.Lmul4x_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r11
+	cmp	%r10,%rsp
+	ja	.Lmul4x_page_walk
+.Lmul4x_page_walk_done:
 
+	mov	%rax,8(%rsp,$num,8)	# tp[num+1]=%rsp
+.Lmul4x_body:
 	mov	$rp,16(%rsp,$num,8)	# tp[num+2]=$rp
 	mov	%rdx,%r12		# reassign $bp
 ___
@@ -742,13 +759,13 @@ ___
 $code.=<<___;
 	mov	8(%rsp,$num,8),%rsi	# restore %rsp
 	mov	\$1,%rax
-	mov	(%rsi),%r15
-	mov	8(%rsi),%r14
-	mov	16(%rsi),%r13
-	mov	24(%rsi),%r12
-	mov	32(%rsi),%rbp
-	mov	40(%rsi),%rbx
-	lea	48(%rsi),%rsp
+	mov	-48(%rsi),%r15
+	mov	-40(%rsi),%r14
+	mov	-32(%rsi),%r13
+	mov	-24(%rsi),%r12
+	mov	-16(%rsi),%rbp
+	mov	-8(%rsi),%rbx
+	lea	(%rsi),%rsp
 .Lmul4x_epilogue:
 	ret
 .size	bn_mul4x_mont,.-bn_mul4x_mont
@@ -778,14 +795,15 @@ $code.=<<___;
 .type	bn_sqr8x_mont,\@function,6
 .align	32
 bn_sqr8x_mont:
-.Lsqr8x_enter:
 	mov	%rsp,%rax
+.Lsqr8x_enter:
 	push	%rbx
 	push	%rbp
 	push	%r12
 	push	%r13
 	push	%r14
 	push	%r15
+.Lsqr8x_prologue:
 
 	mov	${num}d,%r10d
 	shl	\$3,${num}d		# convert $num to bytes
@@ -798,33 +816,42 @@ bn_sqr8x_mont:
 	# do its job.
 	#
 	lea	-64(%rsp,$num,2),%r11
+	mov	%rsp,%rbp
 	mov	($n0),$n0		# *n0
 	sub	$aptr,%r11
 	and	\$4095,%r11
 	cmp	%r11,%r10
 	jb	.Lsqr8x_sp_alt
-	sub	%r11,%rsp		# align with $aptr
-	lea	-64(%rsp,$num,2),%rsp	# alloca(frame+2*$num)
+	sub	%r11,%rbp		# align with $aptr
+	lea	-64(%rbp,$num,2),%rbp	# future alloca(frame+2*$num)
 	jmp	.Lsqr8x_sp_done
 
 .align	32
 .Lsqr8x_sp_alt:
 	lea	4096-64(,$num,2),%r10	# 4096-frame-2*$num
-	lea	-64(%rsp,$num,2),%rsp	# alloca(frame+2*$num)
+	lea	-64(%rbp,$num,2),%rbp	# future alloca(frame+2*$num)
 	sub	%r10,%r11
 	mov	\$0,%r10
 	cmovc	%r10,%r11
-	sub	%r11,%rsp
+	sub	%r11,%rbp
 .Lsqr8x_sp_done:
-	and	\$-64,%rsp
-	mov	%rax,%r11
-	sub	%rsp,%r11
+	and	\$-64,%rbp
+	mov	%rsp,%r11
+	sub	%rbp,%r11
 	and	\$-4096,%r11
+	lea	(%rbp,%r11),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lsqr8x_page_walk
+	jmp	.Lsqr8x_page_walk_done
+
+.align	16
 .Lsqr8x_page_walk:
-	mov	(%rsp,%r11),%r10
-	sub	\$4096,%r11
-	.byte	0x2e			# predict non-taken
-	jnc	.Lsqr8x_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lsqr8x_page_walk
+.Lsqr8x_page_walk_done:
 
 	mov	$num,%r10
 	neg	$num
@@ -948,30 +975,38 @@ $code.=<<___;
 .type	bn_mulx4x_mont,\@function,6
 .align	32
 bn_mulx4x_mont:
-.Lmulx4x_enter:
 	mov	%rsp,%rax
+.Lmulx4x_enter:
 	push	%rbx
 	push	%rbp
 	push	%r12
 	push	%r13
 	push	%r14
 	push	%r15
+.Lmulx4x_prologue:
 
 	shl	\$3,${num}d		# convert $num to bytes
-	.byte	0x67
 	xor	%r10,%r10
 	sub	$num,%r10		# -$num
 	mov	($n0),$n0		# *n0
-	lea	-72(%rsp,%r10),%rsp	# alloca(frame+$num+8)
-	and	\$-128,%rsp
-	mov	%rax,%r11
-	sub	%rsp,%r11
+	lea	-72(%rsp,%r10),%rbp	# future alloca(frame+$num+8)
+	and	\$-128,%rbp
+	mov	%rsp,%r11
+	sub	%rbp,%r11
 	and	\$-4096,%r11
+	lea	(%rbp,%r11),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lmulx4x_page_walk
+	jmp	.Lmulx4x_page_walk_done
+
+.align	16
 .Lmulx4x_page_walk:
-	mov	(%rsp,%r11),%r10
-	sub	\$4096,%r11
-	.byte	0x66,0x2e		# predict non-taken
-	jnc	.Lmulx4x_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lmulx4x_page_walk
+.Lmulx4x_page_walk_done:
 
 	lea	($bp,$num),%r10
 	##############################################################
@@ -1332,22 +1367,8 @@ mul_handler:
 
 	mov	192($context),%r10	# pull $num
 	mov	8(%rax,%r10,8),%rax	# pull saved stack pointer
-	lea	48(%rax),%rax
-
-	mov	-8(%rax),%rbx
-	mov	-16(%rax),%rbp
-	mov	-24(%rax),%r12
-	mov	-32(%rax),%r13
-	mov	-40(%rax),%r14
-	mov	-48(%rax),%r15
-	mov	%rbx,144($context)	# restore context->Rbx
-	mov	%rbp,160($context)	# restore context->Rbp
-	mov	%r12,216($context)	# restore context->R12
-	mov	%r13,224($context)	# restore context->R13
-	mov	%r14,232($context)	# restore context->R14
-	mov	%r15,240($context)	# restore context->R15
 
-	jmp	.Lcommon_seh_tail
+	jmp	.Lcommon_pop_regs
 .size	mul_handler,.-mul_handler
 
 .type	sqr_handler,\@abi-omnipotent
@@ -1375,15 +1396,21 @@ sqr_handler:
 	cmp	%r10,%rbx		# context->Rip<.Lsqr_body
 	jb	.Lcommon_seh_tail
 
+	mov	4(%r11),%r10d		# HandlerData[1]
+	lea	(%rsi,%r10),%r10	# body label
+	cmp	%r10,%rbx		# context->Rip>=.Lsqr_epilogue
+	jb	.Lcommon_pop_regs
+
 	mov	152($context),%rax	# pull context->Rsp
 
-	mov	4(%r11),%r10d		# HandlerData[1]
+	mov	8(%r11),%r10d		# HandlerData[2]
 	lea	(%rsi,%r10),%r10	# epilogue label
 	cmp	%r10,%rbx		# context->Rip>=.Lsqr_epilogue
 	jae	.Lcommon_seh_tail
 
 	mov	40(%rax),%rax		# pull saved stack pointer
 
+.Lcommon_pop_regs:
 	mov	-8(%rax),%rbx
 	mov	-16(%rax),%rbp
 	mov	-24(%rax),%r12
@@ -1470,13 +1497,15 @@ $code.=<<___;
 .LSEH_info_bn_sqr8x_mont:
 	.byte	9,0,0,0
 	.rva	sqr_handler
-	.rva	.Lsqr8x_body,.Lsqr8x_epilogue	# HandlerData[]
+	.rva	.Lsqr8x_prologue,.Lsqr8x_body,.Lsqr8x_epilogue		# HandlerData[]
+.align	8
 ___
 $code.=<<___ if ($addx);
 .LSEH_info_bn_mulx4x_mont:
 	.byte	9,0,0,0
 	.rva	sqr_handler
-	.rva	.Lmulx4x_body,.Lmulx4x_epilogue	# HandlerData[]
+	.rva	.Lmulx4x_prologue,.Lmulx4x_body,.Lmulx4x_epilogue	# HandlerData[]
+.align	8
 ___
 }
 
diff --git a/crypto/openssl/crypto/bn/asm/x86_64-mont5.pl b/crypto/openssl/crypto/bn/asm/x86_64-mont5.pl
index 938e17081803..f1fbb45b532b 100755
--- a/crypto/openssl/crypto/bn/asm/x86_64-mont5.pl
+++ b/crypto/openssl/crypto/bn/asm/x86_64-mont5.pl
@@ -86,6 +86,8 @@ $code=<<___;
 .type	bn_mul_mont_gather5,\@function,6
 .align	64
 bn_mul_mont_gather5:
+	mov	${num}d,${num}d
+	mov	%rsp,%rax
 	test	\$7,${num}d
 	jnz	.Lmul_enter
 ___
@@ -97,10 +99,7 @@ $code.=<<___;
 
 .align	16
 .Lmul_enter:
-	mov	${num}d,${num}d
-	mov	%rsp,%rax
 	movd	`($win64?56:8)`(%rsp),%xmm5	# load 7th argument
-	lea	.Linc(%rip),%r10
 	push	%rbx
 	push	%rbp
 	push	%r12
@@ -108,26 +107,36 @@ $code.=<<___;
 	push	%r14
 	push	%r15
 
-	lea	2($num),%r11
-	neg	%r11
-	lea	-264(%rsp,%r11,8),%rsp	# tp=alloca(8*(num+2)+256+8)
-	and	\$-1024,%rsp		# minimize TLB usage
+	neg	$num
+	mov	%rsp,%r11
+	lea	-280(%rsp,$num,8),%r10	# future alloca(8*(num+2)+256+8)
+	neg	$num			# restore $num
+	and	\$-1024,%r10		# minimize TLB usage
 
-	mov	%rax,8(%rsp,$num,8)	# tp[num+1]=%rsp
-.Lmul_body:
 	# Some OSes, *cough*-dows, insist on stack being "wired" to
 	# physical memory in strictly sequential manner, i.e. if stack
 	# allocation spans two pages, then reference to farmost one can
 	# be punishable by SEGV. But page walking can do good even on
 	# other OSes, because it guarantees that villain thread hits
 	# the guard page before it can make damage to innocent one...
-	sub	%rsp,%rax
-	and	\$-4096,%rax
+	sub	%r10,%r11
+	and	\$-4096,%r11
+	lea	(%r10,%r11),%rsp
+	mov	(%rsp),%r11
+	cmp	%r10,%rsp
+	ja	.Lmul_page_walk
+	jmp	.Lmul_page_walk_done
+
 .Lmul_page_walk:
-	mov	(%rsp,%rax),%r11
-	sub	\$4096,%rax
-	.byte	0x2e			# predict non-taken
-	jnc	.Lmul_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r11
+	cmp	%r10,%rsp
+	ja	.Lmul_page_walk
+.Lmul_page_walk_done:
+
+	lea	.Linc(%rip),%r10
+	mov	%rax,8(%rsp,$num,8)	# tp[num+1]=%rsp
+.Lmul_body:
 
 	lea	128($bp),%r12		# reassign $bp (+size optimization)
 ___
@@ -433,6 +442,8 @@ $code.=<<___;
 .type	bn_mul4x_mont_gather5,\@function,6
 .align	32
 bn_mul4x_mont_gather5:
+	.byte	0x67
+	mov	%rsp,%rax
 .Lmul4x_enter:
 ___
 $code.=<<___ if ($addx);
@@ -441,14 +452,13 @@ $code.=<<___ if ($addx);
 	je	.Lmulx4x_enter
 ___
 $code.=<<___;
-	.byte	0x67
-	mov	%rsp,%rax
 	push	%rbx
 	push	%rbp
 	push	%r12
 	push	%r13
 	push	%r14
 	push	%r15
+.Lmul4x_prologue:
 
 	.byte	0x67
 	shl	\$3,${num}d		# convert $num to bytes
@@ -465,32 +475,40 @@ $code.=<<___;
 	# calculated from 7th argument, the index.]
 	#
 	lea	-320(%rsp,$num,2),%r11
+	mov	%rsp,%rbp
 	sub	$rp,%r11
 	and	\$4095,%r11
 	cmp	%r11,%r10
 	jb	.Lmul4xsp_alt
-	sub	%r11,%rsp		# align with $rp
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*num*8+256)
+	sub	%r11,%rbp		# align with $rp
+	lea	-320(%rbp,$num,2),%rbp	# future alloca(frame+2*num*8+256)
 	jmp	.Lmul4xsp_done
 
 .align	32
 .Lmul4xsp_alt:
 	lea	4096-320(,$num,2),%r10
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*num*8+256)
+	lea	-320(%rbp,$num,2),%rbp	# future alloca(frame+2*num*8+256)
 	sub	%r10,%r11
 	mov	\$0,%r10
 	cmovc	%r10,%r11
-	sub	%r11,%rsp
+	sub	%r11,%rbp
 .Lmul4xsp_done:
-	and	\$-64,%rsp
-	mov	%rax,%r11
-	sub	%rsp,%r11
+	and	\$-64,%rbp
+	mov	%rsp,%r11
+	sub	%rbp,%r11
 	and	\$-4096,%r11
+	lea	(%rbp,%r11),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lmul4x_page_walk
+	jmp	.Lmul4x_page_walk_done
+
 .Lmul4x_page_walk:
-	mov	(%rsp,%r11),%r10
-	sub	\$4096,%r11
-	.byte	0x2e			# predict non-taken
-	jnc	.Lmul4x_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lmul4x_page_walk
+.Lmul4x_page_walk_done:
 
 	neg	$num
 
@@ -1034,6 +1052,7 @@ $code.=<<___;
 .type	bn_power5,\@function,6
 .align	32
 bn_power5:
+	mov	%rsp,%rax
 ___
 $code.=<<___ if ($addx);
 	mov	OPENSSL_ia32cap_P+8(%rip),%r11d
@@ -1042,13 +1061,13 @@ $code.=<<___ if ($addx);
 	je	.Lpowerx5_enter
 ___
 $code.=<<___;
-	mov	%rsp,%rax
 	push	%rbx
 	push	%rbp
 	push	%r12
 	push	%r13
 	push	%r14
 	push	%r15
+.Lpower5_prologue:
 
 	shl	\$3,${num}d		# convert $num to bytes
 	lea	($num,$num,2),%r10d	# 3*$num
@@ -1063,32 +1082,40 @@ $code.=<<___;
 	# calculated from 7th argument, the index.]
 	#
 	lea	-320(%rsp,$num,2),%r11
+	mov	%rsp,%rbp
 	sub	$rptr,%r11
 	and	\$4095,%r11
 	cmp	%r11,%r10
 	jb	.Lpwr_sp_alt
-	sub	%r11,%rsp		# align with $aptr
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*num*8+256)
+	sub	%r11,%rbp		# align with $aptr
+	lea	-320(%rbp,$num,2),%rbp	# future alloca(frame+2*num*8+256)
 	jmp	.Lpwr_sp_done
 
 .align	32
 .Lpwr_sp_alt:
 	lea	4096-320(,$num,2),%r10
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*num*8+256)
+	lea	-320(%rbp,$num,2),%rbp	# future alloca(frame+2*num*8+256)
 	sub	%r10,%r11
 	mov	\$0,%r10
 	cmovc	%r10,%r11
-	sub	%r11,%rsp
+	sub	%r11,%rbp
 .Lpwr_sp_done:
-	and	\$-64,%rsp
-	mov	%rax,%r11
-	sub	%rsp,%r11
+	and	\$-64,%rbp
+	mov	%rsp,%r11
+	sub	%rbp,%r11
 	and	\$-4096,%r11
+	lea	(%rbp,%r11),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lpwr_page_walk
+	jmp	.Lpwr_page_walk_done
+
 .Lpwr_page_walk:
-	mov	(%rsp,%r11),%r10
-	sub	\$4096,%r11
-	.byte	0x2e			# predict non-taken
-	jnc	.Lpwr_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lpwr_page_walk
+.Lpwr_page_walk_done:
 
 	mov	$num,%r10	
 	neg	$num
@@ -2028,6 +2055,7 @@ bn_from_mont8x:
 	push	%r13
 	push	%r14
 	push	%r15
+.Lfrom_prologue:
 
 	shl	\$3,${num}d		# convert $num to bytes
 	lea	($num,$num,2),%r10	# 3*$num in bytes
@@ -2042,32 +2070,40 @@ bn_from_mont8x:
 	# last operation, we use the opportunity to cleanse it.
 	#
 	lea	-320(%rsp,$num,2),%r11
+	mov	%rsp,%rbp
 	sub	$rptr,%r11
 	and	\$4095,%r11
 	cmp	%r11,%r10
 	jb	.Lfrom_sp_alt
-	sub	%r11,%rsp		# align with $aptr
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*$num*8+256)
+	sub	%r11,%rbp		# align with $aptr
+	lea	-320(%rbp,$num,2),%rbp	# future alloca(frame+2*$num*8+256)
 	jmp	.Lfrom_sp_done
 
 .align	32
 .Lfrom_sp_alt:
 	lea	4096-320(,$num,2),%r10
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*$num*8+256)
+	lea	-320(%rbp,$num,2),%rbp	# future alloca(frame+2*$num*8+256)
 	sub	%r10,%r11
 	mov	\$0,%r10
 	cmovc	%r10,%r11
-	sub	%r11,%rsp
+	sub	%r11,%rbp
 .Lfrom_sp_done:
-	and	\$-64,%rsp
-	mov	%rax,%r11
-	sub	%rsp,%r11
+	and	\$-64,%rbp
+	mov	%rsp,%r11
+	sub	%rbp,%r11
 	and	\$-4096,%r11
+	lea	(%rbp,%r11),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lfrom_page_walk
+	jmp	.Lfrom_page_walk_done
+
 .Lfrom_page_walk:
-	mov	(%rsp,%r11),%r10
-	sub	\$4096,%r11
-	.byte	0x2e			# predict non-taken
-	jnc	.Lfrom_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lfrom_page_walk
+.Lfrom_page_walk_done:
 
 	mov	$num,%r10
 	neg	$num
@@ -2173,14 +2209,15 @@ $code.=<<___;
 .type	bn_mulx4x_mont_gather5,\@function,6
 .align	32
 bn_mulx4x_mont_gather5:
-.Lmulx4x_enter:
 	mov	%rsp,%rax
+.Lmulx4x_enter:
 	push	%rbx
 	push	%rbp
 	push	%r12
 	push	%r13
 	push	%r14
 	push	%r15
+.Lmulx4x_prologue:
 
 	shl	\$3,${num}d		# convert $num to bytes
 	lea	($num,$num,2),%r10	# 3*$num in bytes
@@ -2197,31 +2234,39 @@ bn_mulx4x_mont_gather5:
 	# calculated from 7th argument, the index.]
 	#
 	lea	-320(%rsp,$num,2),%r11
+	mov	%rsp,%rbp
 	sub	$rp,%r11
 	and	\$4095,%r11
 	cmp	%r11,%r10
 	jb	.Lmulx4xsp_alt
-	sub	%r11,%rsp		# align with $aptr
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*$num*8+256)
+	sub	%r11,%rbp		# align with $aptr
+	lea	-320(%rbp,$num,2),%rbp	# future alloca(frame+2*$num*8+256)
 	jmp	.Lmulx4xsp_done
 
 .Lmulx4xsp_alt:
 	lea	4096-320(,$num,2),%r10
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*$num*8+256)
+	lea	-320(%rbp,$num,2),%rbp	# future alloca(frame+2*$num*8+256)
 	sub	%r10,%r11
 	mov	\$0,%r10
 	cmovc	%r10,%r11
-	sub	%r11,%rsp
+	sub	%r11,%rbp
 .Lmulx4xsp_done:	
-	and	\$-64,%rsp		# ensure alignment
-	mov	%rax,%r11
-	sub	%rsp,%r11
+	and	\$-64,%rbp		# ensure alignment
+	mov	%rsp,%r11
+	sub	%rbp,%r11
 	and	\$-4096,%r11
+	lea	(%rbp,%r11),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lmulx4x_page_walk
+	jmp	.Lmulx4x_page_walk_done
+
 .Lmulx4x_page_walk:
-	mov	(%rsp,%r11),%r10
-	sub	\$4096,%r11
-	.byte	0x2e			# predict non-taken
-	jnc	.Lmulx4x_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lmulx4x_page_walk
+.Lmulx4x_page_walk_done:
 
 	##############################################################
 	# Stack layout
@@ -2629,14 +2674,15 @@ $code.=<<___;
 .type	bn_powerx5,\@function,6
 .align	32
 bn_powerx5:
-.Lpowerx5_enter:
 	mov	%rsp,%rax
+.Lpowerx5_enter:
 	push	%rbx
 	push	%rbp
 	push	%r12
 	push	%r13
 	push	%r14
 	push	%r15
+.Lpowerx5_prologue:
 
 	shl	\$3,${num}d		# convert $num to bytes
 	lea	($num,$num,2),%r10	# 3*$num in bytes
@@ -2651,32 +2697,40 @@ bn_powerx5:
 	# calculated from 7th argument, the index.]
 	#
 	lea	-320(%rsp,$num,2),%r11
+	mov	%rsp,%rbp
 	sub	$rptr,%r11
 	and	\$4095,%r11
 	cmp	%r11,%r10
 	jb	.Lpwrx_sp_alt
-	sub	%r11,%rsp		# align with $aptr
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*$num*8+256)
+	sub	%r11,%rbp		# align with $aptr
+	lea	-320(%rbp,$num,2),%rbp	# future alloca(frame+2*$num*8+256)
 	jmp	.Lpwrx_sp_done
 
 .align	32
 .Lpwrx_sp_alt:
 	lea	4096-320(,$num,2),%r10
-	lea	-320(%rsp,$num,2),%rsp	# alloca(frame+2*$num*8+256)
+	lea	-320(%rbp,$num,2),%rbp	# alloca(frame+2*$num*8+256)
 	sub	%r10,%r11
 	mov	\$0,%r10
 	cmovc	%r10,%r11
-	sub	%r11,%rsp
+	sub	%r11,%rbp
 .Lpwrx_sp_done:
-	and	\$-64,%rsp
-	mov	%rax,%r11
-	sub	%rsp,%r11
+	and	\$-64,%rbp
+	mov	%rsp,%r11
+	sub	%rbp,%r11
 	and	\$-4096,%r11
+	lea	(%rbp,%r11),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lpwrx_page_walk
+	jmp	.Lpwrx_page_walk_done
+
 .Lpwrx_page_walk:
-	mov	(%rsp,%r11),%r10
-	sub	\$4096,%r11
-	.byte	0x2e			# predict non-taken
-	jnc	.Lpwrx_page_walk
+	lea	-4096(%rsp),%rsp
+	mov	(%rsp),%r10
+	cmp	%rbp,%rsp
+	ja	.Lpwrx_page_walk
+.Lpwrx_page_walk_done:
 
 	mov	$num,%r10	
 	neg	$num
@@ -3607,9 +3661,14 @@ mul_handler:
 	cmp	%r10,%rbx		# context->Rip<end of prologue label
 	jb	.Lcommon_seh_tail
 
+	mov	4(%r11),%r10d		# HandlerData[1]
+	lea	(%rsi,%r10),%r10	# epilogue label
+	cmp	%r10,%rbx		# context->Rip>=epilogue label
+	jb	.Lcommon_pop_regs
+
 	mov	152($context),%rax	# pull context->Rsp
 
-	mov	4(%r11),%r10d		# HandlerData[1]
+	mov	8(%r11),%r10d		# HandlerData[2]
 	lea	(%rsi,%r10),%r10	# epilogue label
 	cmp	%r10,%rbx		# context->Rip>=epilogue label
 	jae	.Lcommon_seh_tail
@@ -3621,11 +3680,11 @@ mul_handler:
 	mov	192($context),%r10	# pull $num
 	mov	8(%rax,%r10,8),%rax	# pull saved stack pointer
 
-	jmp	.Lbody_proceed
+	jmp	.Lcommon_pop_regs
 
 .Lbody_40:
 	mov	40(%rax),%rax		# pull saved stack pointer
-.Lbody_proceed:
+.Lcommon_pop_regs:
 	mov	-8(%rax),%rbx
 	mov	-16(%rax),%rbp
 	mov	-24(%rax),%r12
@@ -3716,34 +3775,34 @@ $code.=<<___;
 .LSEH_info_bn_mul_mont_gather5:
 	.byte	9,0,0,0
 	.rva	mul_handler
-	.rva	.Lmul_body,.Lmul_epilogue		# HandlerData[]
+	.rva	.Lmul_body,.Lmul_body,.Lmul_epilogue		# HandlerData[]
 .align	8
 .LSEH_info_bn_mul4x_mont_gather5:
 	.byte	9,0,0,0
 	.rva	mul_handler
-	.rva	.Lmul4x_body,.Lmul4x_epilogue		# HandlerData[]
+	.rva	.Lmul4x_prologue,.Lmul4x_body,.Lmul4x_epilogue		# HandlerData[]
 .align	8
 .LSEH_info_bn_power5:
 	.byte	9,0,0,0
 	.rva	mul_handler
-	.rva	.Lpower5_body,.Lpower5_epilogue		# HandlerData[]
+	.rva	.Lpower5_prologue,.Lpower5_body,.Lpower5_epilogue	# HandlerData[]
 .align	8
 .LSEH_info_bn_from_mont8x:
 	.byte	9,0,0,0
 	.rva	mul_handler
-	.rva	.Lfrom_body,.Lfrom_epilogue		# HandlerData[]
+	.rva	.Lfrom_prologue,.Lfrom_body,.Lfrom_epilogue		# HandlerData[]
 ___
 $code.=<<___ if ($addx);
 .align	8
 .LSEH_info_bn_mulx4x_mont_gather5:
 	.byte	9,0,0,0
 	.rva	mul_handler
-	.rva	.Lmulx4x_body,.Lmulx4x_epilogue		# HandlerData[]
+	.rva	.Lmulx4x_prologue,.Lmulx4x_body,.Lmulx4x_epilogue	# HandlerData[]
 .align	8
 .LSEH_info_bn_powerx5:
 	.byte	9,0,0,0
 	.rva	mul_handler
-	.rva	.Lpowerx5_body,.Lpowerx5_epilogue	# HandlerData[]
+	.rva	.Lpowerx5_prologue,.Lpowerx5_body,.Lpowerx5_epilogue	# HandlerData[]
 ___
 $code.=<<___;
 .align	8
diff --git a/crypto/openssl/crypto/bn/bn.h b/crypto/openssl/crypto/bn/bn.h
index 86264ae6315f..633d1b1f6013 100644
--- a/crypto/openssl/crypto/bn/bn.h
+++ b/crypto/openssl/crypto/bn/bn.h
@@ -842,6 +842,8 @@ int RAND_pseudo_bytes(unsigned char *buf, int num);
                         if (*(ftl--)) break; \
                 (a)->top = tmp_top; \
                 } \
+        if ((a)->top == 0) \
+            (a)->neg = 0; \
         bn_pollute(a); \
         }
 
diff --git a/crypto/openssl/crypto/bn/bn_div.c b/crypto/openssl/crypto/bn/bn_div.c
index 72e6ce3f74c0..bc37671cf138 100644
--- a/crypto/openssl/crypto/bn/bn_div.c
+++ b/crypto/openssl/crypto/bn/bn_div.c
@@ -155,7 +155,7 @@ int BN_div(BIGNUM *dv, BIGNUM *rem, const BIGNUM *m, const BIGNUM *d,
         ({  asm volatile (                      \
                 "divl   %4"                     \
                 : "=a"(q), "=d"(rem)            \
-                : "a"(n1), "d"(n0), "g"(d0)     \
+                : "a"(n1), "d"(n0), "r"(d0)     \
                 : "cc");                        \
             q;                                  \
         })
@@ -170,7 +170,7 @@ int BN_div(BIGNUM *dv, BIGNUM *rem, const BIGNUM *m, const BIGNUM *d,
         ({  asm volatile (                      \
                 "divq   %4"                     \
                 : "=a"(q), "=d"(rem)            \
-                : "a"(n1), "d"(n0), "g"(d0)     \
+                : "a"(n1), "d"(n0), "r"(d0)     \
                 : "cc");                        \
             q;                                  \
         })
diff --git a/crypto/openssl/crypto/bn/bn_lib.c b/crypto/openssl/crypto/bn/bn_lib.c
index 80105fff410c..10b78f512607 100644
--- a/crypto/openssl/crypto/bn/bn_lib.c
+++ b/crypto/openssl/crypto/bn/bn_lib.c
@@ -569,7 +569,7 @@ void BN_clear(BIGNUM *a)
 {
     bn_check_top(a);
     if (a->d != NULL)
-        memset(a->d, 0, a->dmax * sizeof(a->d[0]));
+        OPENSSL_cleanse(a->d, a->dmax * sizeof(a->d[0]));
     a->top = 0;
     a->neg = 0;
 }
diff --git a/crypto/openssl/crypto/bn/bn_print.c b/crypto/openssl/crypto/bn/bn_print.c
index bfa31efc5621..f121fb6e9a08 100644
--- a/crypto/openssl/crypto/bn/bn_print.c
+++ b/crypto/openssl/crypto/bn/bn_print.c
@@ -72,12 +72,9 @@ char *BN_bn2hex(const BIGNUM *a)
     char *buf;
     char *p;
 
-    if (a->neg && BN_is_zero(a)) {
-        /* "-0" == 3 bytes including NULL terminator */
-        buf = OPENSSL_malloc(3);
-    } else {
-        buf = OPENSSL_malloc(a->top * BN_BYTES * 2 + 2);
-    }
+    if (BN_is_zero(a))
+        return OPENSSL_strdup("0");
+    buf = OPENSSL_malloc(a->top * BN_BYTES * 2 + 2);
     if (buf == NULL) {
         BNerr(BN_F_BN_BN2HEX, ERR_R_MALLOC_FAILURE);
         goto err;
@@ -111,6 +108,7 @@ char *BN_bn2dec(const BIGNUM *a)
     char *p;
     BIGNUM *t = NULL;
     BN_ULONG *bn_data = NULL, *lp;
+    int bn_data_num;
 
     /*-
      * get an upper bound for the length of the decimal integer
@@ -120,9 +118,9 @@ char *BN_bn2dec(const BIGNUM *a)
      */
     i = BN_num_bits(a) * 3;
     num = (i / 10 + i / 1000 + 1) + 1;
-    bn_data =
-        (BN_ULONG *)OPENSSL_malloc((num / BN_DEC_NUM + 1) * sizeof(BN_ULONG));
-    buf = (char *)OPENSSL_malloc(num + 3);
+    bn_data_num = num / BN_DEC_NUM + 1;
+    bn_data = OPENSSL_malloc(bn_data_num * sizeof(BN_ULONG));
+    buf = OPENSSL_malloc(num + 3);
     if ((buf == NULL) || (bn_data == NULL)) {
         BNerr(BN_F_BN_BN2DEC, ERR_R_MALLOC_FAILURE);
         goto err;
@@ -140,9 +138,12 @@ char *BN_bn2dec(const BIGNUM *a)
         if (BN_is_negative(t))
             *p++ = '-';
 
-        i = 0;
         while (!BN_is_zero(t)) {
+            if (lp - bn_data >= bn_data_num)
+                goto err;
             *lp = BN_div_word(t, BN_DEC_CONV);
+            if (*lp == (BN_ULONG)-1)
+                goto err;
             lp++;
         }
         lp--;
@@ -240,10 +241,12 @@ int BN_hex2bn(BIGNUM **bn, const char *a)
     }
     ret->top = h;
     bn_correct_top(ret);
-    ret->neg = neg;
 
     *bn = ret;
     bn_check_top(ret);
+    /* Don't set the negative flag if it's zero. */
+    if (ret->top != 0)
+        ret->neg = neg;
     return (num);
  err:
     if (*bn == NULL)
@@ -295,7 +298,7 @@ int BN_dec2bn(BIGNUM **bn, const char *a)
     if (j == BN_DEC_NUM)
         j = 0;
     l = 0;
-    while (*a) {
+    while (--i >= 0) {
         l *= 10;
         l += *a - '0';
         a++;
@@ -306,11 +309,13 @@ int BN_dec2bn(BIGNUM **bn, const char *a)
             j = 0;
         }
     }
-    ret->neg = neg;
 
     bn_correct_top(ret);
     *bn = ret;
     bn_check_top(ret);
+    /* Don't set the negative flag if it's zero. */
+    if (ret->top != 0)
+        ret->neg = neg;
     return (num);
  err:
     if (*bn == NULL)
@@ -321,6 +326,7 @@ int BN_dec2bn(BIGNUM **bn, const char *a)
 int BN_asc2bn(BIGNUM **bn, const char *a)
 {
     const char *p = a;
+
     if (*p == '-')
         p++;
 
@@ -331,7 +337,8 @@ int BN_asc2bn(BIGNUM **bn, const char *a)
         if (!BN_dec2bn(bn, p))
             return 0;
     }
-    if (*a == '-')
+    /* Don't set the negative flag if it's zero. */
+    if (*a == '-' && (*bn)->top != 0)
         (*bn)->neg = 1;
     return 1;
 }
diff --git a/crypto/openssl/crypto/bn/bn_rand.c b/crypto/openssl/crypto/bn/bn_rand.c
index f9fb2e9e45e0..60d3f2260ba1 100644
--- a/crypto/openssl/crypto/bn/bn_rand.c
+++ b/crypto/openssl/crypto/bn/bn_rand.c
@@ -121,15 +121,14 @@ static int bnrand(int pseudorand, BIGNUM *rnd, int bits, int top, int bottom)
     int ret = 0, bit, bytes, mask;
     time_t tim;
 
-    if (bits < 0 || (bits == 1 && top > 0)) {
-        BNerr(BN_F_BNRAND, BN_R_BITS_TOO_SMALL);
-        return 0;
-    }
-
     if (bits == 0) {
+        if (top != -1 || bottom != 0)
+            goto toosmall;
         BN_zero(rnd);
         return 1;
     }
+    if (bits < 0 || (bits == 1 && top > 0))
+        goto toosmall;
 
     bytes = (bits + 7) / 8;
     bit = (bits - 1) % 8;
@@ -145,13 +144,9 @@ static int bnrand(int pseudorand, BIGNUM *rnd, int bits, int top, int bottom)
     time(&tim);
     RAND_add(&tim, sizeof(tim), 0.0);
 
-    if (pseudorand) {
-        if (RAND_pseudo_bytes(buf, bytes) == -1)
-            goto err;
-    } else {
-        if (RAND_bytes(buf, bytes) <= 0)
-            goto err;
-    }
+    /* We ignore the value of pseudorand and always call RAND_bytes */
+    if (RAND_bytes(buf, bytes) <= 0)
+        goto err;
 
 #if 1
     if (pseudorand == 2) {
@@ -199,6 +194,10 @@ static int bnrand(int pseudorand, BIGNUM *rnd, int bits, int top, int bottom)
     }
     bn_check_top(rnd);
     return (ret);
+
+toosmall:
+    BNerr(BN_F_BNRAND, BN_R_BITS_TOO_SMALL);
+    return 0;
 }
 
 int BN_rand(BIGNUM *rnd, int bits, int top, int bottom)
diff --git a/crypto/openssl/crypto/bn/bn_word.c b/crypto/openssl/crypto/bn/bn_word.c
index b031a60b5bf8..9b5f9cb98c3a 100644
--- a/crypto/openssl/crypto/bn/bn_word.c
+++ b/crypto/openssl/crypto/bn/bn_word.c
@@ -72,10 +72,32 @@ BN_ULONG BN_mod_word(const BIGNUM *a, BN_ULONG w)
     if (w == 0)
         return (BN_ULONG)-1;
 
+#ifndef BN_LLONG
+    /*
+     * If |w| is too long and we don't have BN_ULLONG then we need to fall
+     * back to using BN_div_word
+     */
+    if (w > ((BN_ULONG)1 << BN_BITS4)) {
+        BIGNUM *tmp = BN_dup(a);
+        if (tmp == NULL)
+            return (BN_ULONG)-1;
+
+        ret = BN_div_word(tmp, w);
+        BN_free(tmp);
+
+        return ret;
+    }
+#endif
+
     bn_check_top(a);
     w &= BN_MASK2;
     for (i = a->top - 1; i >= 0; i--) {
 #ifndef BN_LLONG
+        /*
+         * We can assume here that | w <= ((BN_ULONG)1 << BN_BITS4) | and so
+         * | ret < ((BN_ULONG)1 << BN_BITS4) | and therefore the shifts here are
+         * safe and will not overflow
+         */
         ret = ((ret << BN_BITS4) | ((a->d[i] >> BN_BITS4) & BN_MASK2l)) % w;
         ret = ((ret << BN_BITS4) | (a->d[i] & BN_MASK2l)) % w;
 #else
diff --git a/crypto/openssl/crypto/bn/bntest.c b/crypto/openssl/crypto/bn/bntest.c
index 1e35988022bb..a327b1a647b2 100644
--- a/crypto/openssl/crypto/bn/bntest.c
+++ b/crypto/openssl/crypto/bn/bntest.c
@@ -514,7 +514,7 @@ static void print_word(BIO *bp, BN_ULONG w)
 int test_div_word(BIO *bp)
 {
     BIGNUM a, b;
-    BN_ULONG r, s;
+    BN_ULONG r, rmod, s;
     int i;
 
     BN_init(&a);
@@ -528,8 +528,14 @@ int test_div_word(BIO *bp)
 
         s = b.d[0];
         BN_copy(&b, &a);
+        rmod = BN_mod_word(&b, s);
         r = BN_div_word(&b, s);
 
+        if (rmod != r) {
+            fprintf(stderr, "Mod (word) test failed!\n");
+            return 0;
+        }
+
         if (bp != NULL) {
             if (!results) {
                 BN_print(bp, &a);
diff --git a/crypto/openssl/crypto/cms/cms_enc.c b/crypto/openssl/crypto/cms/cms_enc.c
index b14b4b68b5c9..90b1fcc75075 100644
--- a/crypto/openssl/crypto/cms/cms_enc.c
+++ b/crypto/openssl/crypto/cms/cms_enc.c
@@ -119,7 +119,7 @@ BIO *cms_EncryptedContent_init_bio(CMS_EncryptedContentInfo *ec)
         /* Generate a random IV if we need one */
         ivlen = EVP_CIPHER_CTX_iv_length(ctx);
         if (ivlen > 0) {
-            if (RAND_pseudo_bytes(iv, ivlen) <= 0)
+            if (RAND_bytes(iv, ivlen) <= 0)
                 goto err;
             piv = iv;
         }
@@ -179,10 +179,9 @@ BIO *cms_EncryptedContent_init_bio(CMS_EncryptedContentInfo *ec)
                CMS_R_CIPHER_INITIALISATION_ERROR);
         goto err;
     }
-
-    if (piv) {
+    if (enc) {
         calg->parameter = ASN1_TYPE_new();
-        if (!calg->parameter) {
+        if (calg->parameter == NULL) {
             CMSerr(CMS_F_CMS_ENCRYPTEDCONTENT_INIT_BIO, ERR_R_MALLOC_FAILURE);
             goto err;
         }
@@ -191,6 +190,11 @@ BIO *cms_EncryptedContent_init_bio(CMS_EncryptedContentInfo *ec)
                    CMS_R_CIPHER_PARAMETER_INITIALISATION_ERROR);
             goto err;
         }
+        /* If parameter type not set omit parameter */
+        if (calg->parameter->type == V_ASN1_UNDEF) {
+            ASN1_TYPE_free(calg->parameter);
+            calg->parameter = NULL;
+        }
     }
     ok = 1;
 
diff --git a/crypto/openssl/crypto/cms/cms_ess.c b/crypto/openssl/crypto/cms/cms_ess.c
index 8631a2eb2b30..8212560628a9 100644
--- a/crypto/openssl/crypto/cms/cms_ess.c
+++ b/crypto/openssl/crypto/cms/cms_ess.c
@@ -107,8 +107,7 @@ CMS_ReceiptRequest *CMS_ReceiptRequest_create0(unsigned char *id, int idlen,
     else {
         if (!ASN1_STRING_set(rr->signedContentIdentifier, NULL, 32))
             goto merr;
-        if (RAND_pseudo_bytes(rr->signedContentIdentifier->data, 32)
-            <= 0)
+        if (RAND_bytes(rr->signedContentIdentifier->data, 32) <= 0)
             goto err;
     }
 
diff --git a/crypto/openssl/crypto/cms/cms_lib.c b/crypto/openssl/crypto/cms/cms_lib.c
index d6cb60d02d15..6d27c4969b92 100644
--- a/crypto/openssl/crypto/cms/cms_lib.c
+++ b/crypto/openssl/crypto/cms/cms_lib.c
@@ -413,6 +413,8 @@ static STACK_OF(CMS_CertificateChoices)
         return &cms->d.signedData->certificates;
 
     case NID_pkcs7_enveloped:
+        if (cms->d.envelopedData->originatorInfo == NULL)
+            return NULL;
         return &cms->d.envelopedData->originatorInfo->certificates;
 
     default:
@@ -488,6 +490,8 @@ static STACK_OF(CMS_RevocationInfoChoice)
         return &cms->d.signedData->crls;
 
     case NID_pkcs7_enveloped:
+        if (cms->d.envelopedData->originatorInfo == NULL)
+            return NULL;
         return &cms->d.envelopedData->originatorInfo->crls;
 
     default:
diff --git a/crypto/openssl/crypto/cms/cms_pwri.c b/crypto/openssl/crypto/cms/cms_pwri.c
index b91c01691fec..5c817caf2f05 100644
--- a/crypto/openssl/crypto/cms/cms_pwri.c
+++ b/crypto/openssl/crypto/cms/cms_pwri.c
@@ -134,7 +134,7 @@ CMS_RecipientInfo *CMS_add0_recipient_password(CMS_ContentInfo *cms,
     ivlen = EVP_CIPHER_CTX_iv_length(&ctx);
 
     if (ivlen > 0) {
-        if (RAND_pseudo_bytes(iv, ivlen) <= 0)
+        if (RAND_bytes(iv, ivlen) <= 0)
             goto err;
         if (EVP_EncryptInit_ex(&ctx, NULL, NULL, NULL, iv) <= 0) {
             CMSerr(CMS_F_CMS_ADD0_RECIPIENT_PASSWORD, ERR_R_EVP_LIB);
@@ -301,7 +301,7 @@ static int kek_wrap_key(unsigned char *out, size_t *outlen,
         memcpy(out + 4, in, inlen);
         /* Add random padding to end */
         if (olen > inlen + 4
-            && RAND_pseudo_bytes(out + 4 + inlen, olen - 4 - inlen) < 0)
+            && RAND_bytes(out + 4 + inlen, olen - 4 - inlen) <= 0)
             return 0;
         /* Encrypt twice */
         EVP_EncryptUpdate(ctx, out, &dummy, out, olen);
diff --git a/crypto/openssl/crypto/comp/comp.h b/crypto/openssl/crypto/comp/comp.h
index 60a073404e92..df599ba3314b 100644
--- a/crypto/openssl/crypto/comp/comp.h
+++ b/crypto/openssl/crypto/comp/comp.h
@@ -14,7 +14,7 @@ extern "C" {
 
 typedef struct comp_ctx_st COMP_CTX;
 
-typedef struct comp_method_st {
+struct comp_method_st {
     int type;                   /* NID for compression library */
     const char *name;           /* A text string to identify the library */
     int (*init) (COMP_CTX *ctx);
@@ -30,7 +30,7 @@ typedef struct comp_method_st {
      */
     long (*ctrl) (void);
     long (*callback_ctrl) (void);
-} COMP_METHOD;
+};
 
 struct comp_ctx_st {
     COMP_METHOD *meth;
diff --git a/crypto/openssl/crypto/conf/conf_def.h b/crypto/openssl/crypto/conf/conf_def.h
index 7d897b89f182..48b344218114 100644
--- a/crypto/openssl/crypto/conf/conf_def.h
+++ b/crypto/openssl/crypto/conf/conf_def.h
@@ -81,34 +81,34 @@
 
 #define KEYTYPES(c)             ((unsigned short *)((c)->meth_data))
 #ifndef CHARSET_EBCDIC
-# define IS_COMMENT(c,a)         (KEYTYPES(c)[(a)&0xff]&CONF_COMMENT)
-# define IS_FCOMMENT(c,a)        (KEYTYPES(c)[(a)&0xff]&CONF_FCOMMENT)
-# define IS_EOF(c,a)             (KEYTYPES(c)[(a)&0xff]&CONF_EOF)
-# define IS_ESC(c,a)             (KEYTYPES(c)[(a)&0xff]&CONF_ESC)
-# define IS_NUMBER(c,a)          (KEYTYPES(c)[(a)&0xff]&CONF_NUMBER)
-# define IS_WS(c,a)              (KEYTYPES(c)[(a)&0xff]&CONF_WS)
-# define IS_ALPHA_NUMERIC(c,a)   (KEYTYPES(c)[(a)&0xff]&CONF_ALPHA_NUMERIC)
+# define IS_COMMENT(c,a)        (KEYTYPES(c)[(a)&0xff]&CONF_COMMENT)
+# define IS_FCOMMENT(c,a)       (KEYTYPES(c)[(a)&0xff]&CONF_FCOMMENT)
+# define IS_EOF(c,a)            (KEYTYPES(c)[(a)&0xff]&CONF_EOF)
+# define IS_ESC(c,a)            (KEYTYPES(c)[(a)&0xff]&CONF_ESC)
+# define IS_NUMBER(c,a)         (KEYTYPES(c)[(a)&0xff]&CONF_NUMBER)
+# define IS_WS(c,a)             (KEYTYPES(c)[(a)&0xff]&CONF_WS)
+# define IS_ALPHA_NUMERIC(c,a)  (KEYTYPES(c)[(a)&0xff]&CONF_ALPHA_NUMERIC)
 # define IS_ALPHA_NUMERIC_PUNCT(c,a) \
                                 (KEYTYPES(c)[(a)&0xff]&CONF_ALPHA_NUMERIC_PUNCT)
-# define IS_QUOTE(c,a)           (KEYTYPES(c)[(a)&0xff]&CONF_QUOTE)
-# define IS_DQUOTE(c,a)          (KEYTYPES(c)[(a)&0xff]&CONF_DQUOTE)
-# define IS_HIGHBIT(c,a)         (KEYTYPES(c)[(a)&0xff]&CONF_HIGHBIT)
+# define IS_QUOTE(c,a)          (KEYTYPES(c)[(a)&0xff]&CONF_QUOTE)
+# define IS_DQUOTE(c,a)         (KEYTYPES(c)[(a)&0xff]&CONF_DQUOTE)
+# define IS_HIGHBIT(c,a)        (KEYTYPES(c)[(a)&0xff]&CONF_HIGHBIT)
 
-#else                           /* CHARSET_EBCDIC */
+#else /*CHARSET_EBCDIC*/
 
-# define IS_COMMENT(c,a)         (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_COMMENT)
-# define IS_FCOMMENT(c,a)        (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_FCOMMENT)
-# define IS_EOF(c,a)             (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_EOF)
-# define IS_ESC(c,a)             (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ESC)
-# define IS_NUMBER(c,a)          (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_NUMBER)
-# define IS_WS(c,a)              (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_WS)
-# define IS_ALPHA_NUMERIC(c,a)   (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ALPHA_NUMERIC)
+# define IS_COMMENT(c,a)        (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_COMMENT)
+# define IS_FCOMMENT(c,a)       (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_FCOMMENT)
+# define IS_EOF(c,a)            (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_EOF)
+# define IS_ESC(c,a)            (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ESC)
+# define IS_NUMBER(c,a)         (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_NUMBER)
+# define IS_WS(c,a)             (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_WS)
+# define IS_ALPHA_NUMERIC(c,a)  (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ALPHA_NUMERIC)
 # define IS_ALPHA_NUMERIC_PUNCT(c,a) \
                                 (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ALPHA_NUMERIC_PUNCT)
-# define IS_QUOTE(c,a)           (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_QUOTE)
-# define IS_DQUOTE(c,a)          (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_DQUOTE)
-# define IS_HIGHBIT(c,a)         (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_HIGHBIT)
-#endif                          /* CHARSET_EBCDIC */
+# define IS_QUOTE(c,a)          (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_QUOTE)
+# define IS_DQUOTE(c,a)         (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_DQUOTE)
+# define IS_HIGHBIT(c,a)        (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_HIGHBIT)
+#endif /*CHARSET_EBCDIC*/
 
 static unsigned short CONF_type_default[256] = {
     0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
diff --git a/crypto/openssl/crypto/conf/conf_mod.c b/crypto/openssl/crypto/conf/conf_mod.c
index 9acfca4f7198..e0c9a67ff68f 100644
--- a/crypto/openssl/crypto/conf/conf_mod.c
+++ b/crypto/openssl/crypto/conf/conf_mod.c
@@ -288,6 +288,10 @@ static CONF_MODULE *module_add(DSO *dso, const char *name,
 
     tmod->dso = dso;
     tmod->name = BUF_strdup(name);
+    if (tmod->name == NULL) {
+        OPENSSL_free(tmod);
+        return NULL;
+    }
     tmod->init = ifunc;
     tmod->finish = ffunc;
     tmod->links = 0;
diff --git a/crypto/openssl/crypto/conf/keysets.pl b/crypto/openssl/crypto/conf/keysets.pl
index 50ed67fa527c..5c9b2aaef8aa 100644
--- a/crypto/openssl/crypto/conf/keysets.pl
+++ b/crypto/openssl/crypto/conf/keysets.pl
@@ -59,21 +59,21 @@ print <<"EOF";
  * This package is an SSL implementation written
  * by Eric Young (eay\@cryptsoft.com).
  * The implementation was written so as to conform with Netscapes SSL.
- * 
+ *
  * This library is free for commercial and non-commercial use as long as
  * the following conditions are aheared to.  The following conditions
  * apply to all code found in this distribution, be it the RC4, RSA,
  * lhash, DES, etc., code; not just the SSL code.  The SSL documentation
  * included with this distribution is covered by the same copyright terms
  * except that the holder is Tim Hudson (tjh\@cryptsoft.com).
- * 
+ *
  * Copyright remains Eric Young's, and as such any Copyright notices in
  * the code are not to be removed.
  * If this package is used in a product, Eric Young should be given attribution
  * as the author of the parts of the library used.
  * This can be in the form of a textual message at program startup or
  * in documentation (online or textual) provided with the package.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -88,10 +88,10 @@ print <<"EOF";
  *     Eric Young (eay\@cryptsoft.com)"
  *    The word 'cryptographic' can be left out if the rouines from the library
  *    being used are not cryptographic related :-).
- * 4. If you include any Windows specific code (or a derivative thereof) from 
+ * 4. If you include any Windows specific code (or a derivative thereof) from
  *    the apps directory (application code) you must include an acknowledgement:
  *    "This product includes software written by Tim Hudson (tjh\@cryptsoft.com)"
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -103,83 +103,85 @@ print <<"EOF";
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- * 
+ *
  * The licence and distribution terms for any publically available version or
  * derivative of this code cannot be changed.  i.e. this code cannot simply be
  * copied and put under another distribution licence
  * [including the GNU Public Licence.]
  */
 
-/* THIS FILE WAS AUTOMAGICALLY GENERATED!
-   Please modify and use keysets.pl to regenerate it. */
-
-#define CONF_NUMBER		$NUMBER
-#define CONF_UPPER		$UPPER
-#define CONF_LOWER		$LOWER
-#define CONF_UNDER		$UNDER
-#define CONF_PUNCTUATION	$PUNCTUATION
-#define CONF_WS			$WS
-#define CONF_ESC		$ESC
-#define CONF_QUOTE		$QUOTE
-#define CONF_DQUOTE		$DQUOTE
-#define CONF_COMMENT		$COMMENT
-#define CONF_FCOMMENT		$FCOMMENT
-#define CONF_EOF		$EOF
-#define CONF_HIGHBIT		$HIGHBIT
-#define CONF_ALPHA		(CONF_UPPER|CONF_LOWER)
-#define CONF_ALPHA_NUMERIC	(CONF_ALPHA|CONF_NUMBER|CONF_UNDER)
+/*
+ * THIS FILE WAS AUTOMAGICALLY GENERATED! Please modify and use keysets.pl to
+ * regenerate it.
+ */
+
+#define CONF_NUMBER             $NUMBER
+#define CONF_UPPER              $UPPER
+#define CONF_LOWER              $LOWER
+#define CONF_UNDER              $UNDER
+#define CONF_PUNCTUATION        $PUNCTUATION
+#define CONF_WS                 $WS
+#define CONF_ESC                $ESC
+#define CONF_QUOTE              $QUOTE
+#define CONF_DQUOTE             $DQUOTE
+#define CONF_COMMENT            $COMMENT
+#define CONF_FCOMMENT           $FCOMMENT
+#define CONF_EOF                $EOF
+#define CONF_HIGHBIT            $HIGHBIT
+#define CONF_ALPHA              (CONF_UPPER|CONF_LOWER)
+#define CONF_ALPHA_NUMERIC      (CONF_ALPHA|CONF_NUMBER|CONF_UNDER)
 #define CONF_ALPHA_NUMERIC_PUNCT (CONF_ALPHA|CONF_NUMBER|CONF_UNDER| \\
-					CONF_PUNCTUATION)
+                                        CONF_PUNCTUATION)
 
-#define KEYTYPES(c)		((unsigned short *)((c)->meth_data))
+#define KEYTYPES(c)             ((unsigned short *)((c)->meth_data))
 #ifndef CHARSET_EBCDIC
-#define IS_COMMENT(c,a)		(KEYTYPES(c)[(a)&0xff]&CONF_COMMENT)
-#define IS_FCOMMENT(c,a)	(KEYTYPES(c)[(a)&0xff]&CONF_FCOMMENT)
-#define IS_EOF(c,a)		(KEYTYPES(c)[(a)&0xff]&CONF_EOF)
-#define IS_ESC(c,a)		(KEYTYPES(c)[(a)&0xff]&CONF_ESC)
-#define IS_NUMBER(c,a)		(KEYTYPES(c)[(a)&0xff]&CONF_NUMBER)
-#define IS_WS(c,a)		(KEYTYPES(c)[(a)&0xff]&CONF_WS)
-#define IS_ALPHA_NUMERIC(c,a)	(KEYTYPES(c)[(a)&0xff]&CONF_ALPHA_NUMERIC)
-#define IS_ALPHA_NUMERIC_PUNCT(c,a) \\
-				(KEYTYPES(c)[(a)&0xff]&CONF_ALPHA_NUMERIC_PUNCT)
-#define IS_QUOTE(c,a)		(KEYTYPES(c)[(a)&0xff]&CONF_QUOTE)
-#define IS_DQUOTE(c,a)		(KEYTYPES(c)[(a)&0xff]&CONF_DQUOTE)
-#define IS_HIGHBIT(c,a)		(KEYTYPES(c)[(a)&0xff]&CONF_HIGHBIT)
+# define IS_COMMENT(c,a)        (KEYTYPES(c)[(a)&0xff]&CONF_COMMENT)
+# define IS_FCOMMENT(c,a)       (KEYTYPES(c)[(a)&0xff]&CONF_FCOMMENT)
+# define IS_EOF(c,a)            (KEYTYPES(c)[(a)&0xff]&CONF_EOF)
+# define IS_ESC(c,a)            (KEYTYPES(c)[(a)&0xff]&CONF_ESC)
+# define IS_NUMBER(c,a)         (KEYTYPES(c)[(a)&0xff]&CONF_NUMBER)
+# define IS_WS(c,a)             (KEYTYPES(c)[(a)&0xff]&CONF_WS)
+# define IS_ALPHA_NUMERIC(c,a)  (KEYTYPES(c)[(a)&0xff]&CONF_ALPHA_NUMERIC)
+# define IS_ALPHA_NUMERIC_PUNCT(c,a) \\
+                                (KEYTYPES(c)[(a)&0xff]&CONF_ALPHA_NUMERIC_PUNCT)
+# define IS_QUOTE(c,a)          (KEYTYPES(c)[(a)&0xff]&CONF_QUOTE)
+# define IS_DQUOTE(c,a)         (KEYTYPES(c)[(a)&0xff]&CONF_DQUOTE)
+# define IS_HIGHBIT(c,a)        (KEYTYPES(c)[(a)&0xff]&CONF_HIGHBIT)
 
 #else /*CHARSET_EBCDIC*/
 
-#define IS_COMMENT(c,a)		(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_COMMENT)
-#define IS_FCOMMENT(c,a)	(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_FCOMMENT)
-#define IS_EOF(c,a)		(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_EOF)
-#define IS_ESC(c,a)		(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ESC)
-#define IS_NUMBER(c,a)		(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_NUMBER)
-#define IS_WS(c,a)		(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_WS)
-#define IS_ALPHA_NUMERIC(c,a)	(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ALPHA_NUMERIC)
-#define IS_ALPHA_NUMERIC_PUNCT(c,a) \\
-				(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ALPHA_NUMERIC_PUNCT)
-#define IS_QUOTE(c,a)		(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_QUOTE)
-#define IS_DQUOTE(c,a)		(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_DQUOTE)
-#define IS_HIGHBIT(c,a)		(KEYTYPES(c)[os_toascii[a]&0xff]&CONF_HIGHBIT)
+# define IS_COMMENT(c,a)        (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_COMMENT)
+# define IS_FCOMMENT(c,a)       (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_FCOMMENT)
+# define IS_EOF(c,a)            (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_EOF)
+# define IS_ESC(c,a)            (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ESC)
+# define IS_NUMBER(c,a)         (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_NUMBER)
+# define IS_WS(c,a)             (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_WS)
+# define IS_ALPHA_NUMERIC(c,a)  (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ALPHA_NUMERIC)
+# define IS_ALPHA_NUMERIC_PUNCT(c,a) \\
+                                (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_ALPHA_NUMERIC_PUNCT)
+# define IS_QUOTE(c,a)          (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_QUOTE)
+# define IS_DQUOTE(c,a)         (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_DQUOTE)
+# define IS_HIGHBIT(c,a)        (KEYTYPES(c)[os_toascii[a]&0xff]&CONF_HIGHBIT)
 #endif /*CHARSET_EBCDIC*/
 
 EOF
 
-print "static unsigned short CONF_type_default[256]={";
+print "static unsigned short CONF_type_default[256] = {";
 
 for ($i=0; $i<256; $i++)
 	{
-	print "\n\t" if ($i % 8) == 0;
-	printf "0x%04X,",$V_def[$i];
+	print "\n   " if ($i % 8) == 0;
+	printf " 0x%04X,",$V_def[$i];
 	}
 
-print "\n\t};\n\n";
+print "\n};\n\n";
 
-print "static unsigned short CONF_type_win32[256]={";
+print "static unsigned short CONF_type_win32[256] = {";
 
 for ($i=0; $i<256; $i++)
 	{
-	print "\n\t" if ($i % 8) == 0;
-	printf "0x%04X,",$V_w32[$i];
+	print "\n   " if ($i % 8) == 0;
+	printf " 0x%04X,",$V_w32[$i];
 	}
 
-print "\n\t};\n\n";
+print "\n};\n";
diff --git a/crypto/openssl/crypto/des/asm/dest4-sparcv9.pl b/crypto/openssl/crypto/des/asm/dest4-sparcv9.pl
index 1dc60243d4fb..5f3a511dba27 100755
--- a/crypto/openssl/crypto/des/asm/dest4-sparcv9.pl
+++ b/crypto/openssl/crypto/des/asm/dest4-sparcv9.pl
@@ -96,7 +96,7 @@ $code.=<<___;
 des_t4_cbc_encrypt:
 	cmp		$len, 0
 	be,pn		$::size_t_cc, .Lcbc_abort
-	nop
+	srln		$len, 0, $len		! needed on v8+, "nop" on v9
 	ld		[$ivec + 0], %f0	! load ivec
 	ld		[$ivec + 4], %f1
 
@@ -197,7 +197,7 @@ des_t4_cbc_encrypt:
 des_t4_cbc_decrypt:
 	cmp		$len, 0
 	be,pn		$::size_t_cc, .Lcbc_abort
-	nop
+	srln		$len, 0, $len		! needed on v8+, "nop" on v9
 	ld		[$ivec + 0], %f2	! load ivec
 	ld		[$ivec + 4], %f3
 
@@ -305,7 +305,7 @@ $code.=<<___;
 des_t4_ede3_cbc_encrypt:
 	cmp		$len, 0
 	be,pn		$::size_t_cc, .Lcbc_abort
-	nop
+	srln		$len, 0, $len		! needed on v8+, "nop" on v9
 	ld		[$ivec + 0], %f0	! load ivec
 	ld		[$ivec + 4], %f1
 
@@ -457,7 +457,7 @@ des_t4_ede3_cbc_encrypt:
 des_t4_ede3_cbc_decrypt:
 	cmp		$len, 0
 	be,pn		$::size_t_cc, .Lcbc_abort
-	nop
+	srln		$len, 0, $len		! needed on v8+, "nop" on v9
 	ld		[$ivec + 0], %f2	! load ivec
 	ld		[$ivec + 4], %f3
 
diff --git a/crypto/openssl/crypto/des/des.c b/crypto/openssl/crypto/des/des.c
index 586aed72378c..d7374382d83a 100644
--- a/crypto/openssl/crypto/des/des.c
+++ b/crypto/openssl/crypto/des/des.c
@@ -456,7 +456,7 @@ void doencryption(void)
             len = l - rem;
             if (feof(DES_IN)) {
                 for (i = 7 - rem; i > 0; i--) {
-                    if (RAND_pseudo_bytes(buf + l++, 1) < 0)
+                    if (RAND_bytes(buf + l++, 1) <= 0)
                         goto problems;
                 }
                 buf[l++] = rem;
diff --git a/crypto/openssl/crypto/des/enc_writ.c b/crypto/openssl/crypto/des/enc_writ.c
index bfaabde516ae..c2aaa8e98ca2 100644
--- a/crypto/openssl/crypto/des/enc_writ.c
+++ b/crypto/openssl/crypto/des/enc_writ.c
@@ -135,7 +135,7 @@ int DES_enc_write(int fd, const void *_buf, int len,
     if (len < 8) {
         cp = shortbuf;
         memcpy(shortbuf, buf, len);
-        if (RAND_pseudo_bytes(shortbuf + len, 8 - len) < 0) {
+        if (RAND_bytes(shortbuf + len, 8 - len) <= 0) {
             return -1;
         }
         rnum = 8;
diff --git a/crypto/openssl/crypto/dh/dh_ameth.c b/crypto/openssl/crypto/dh/dh_ameth.c
index ac72468bd14b..4558283576b3 100644
--- a/crypto/openssl/crypto/dh/dh_ameth.c
+++ b/crypto/openssl/crypto/dh/dh_ameth.c
@@ -519,7 +519,7 @@ static int dh_copy_parameters(EVP_PKEY *to, const EVP_PKEY *from)
 
 static int dh_missing_parameters(const EVP_PKEY *a)
 {
-    if (!a->pkey.dh->p || !a->pkey.dh->g)
+    if (a->pkey.dh == NULL || a->pkey.dh->p == NULL || a->pkey.dh->g == NULL)
         return 1;
     return 0;
 }
diff --git a/crypto/openssl/crypto/dsa/dsa_ameth.c b/crypto/openssl/crypto/dsa/dsa_ameth.c
index cc83d6e6ad3b..c4fa105747fe 100644
--- a/crypto/openssl/crypto/dsa/dsa_ameth.c
+++ b/crypto/openssl/crypto/dsa/dsa_ameth.c
@@ -350,7 +350,7 @@ static int dsa_missing_parameters(const EVP_PKEY *pkey)
 {
     DSA *dsa;
     dsa = pkey->pkey.dsa;
-    if ((dsa->p == NULL) || (dsa->q == NULL) || (dsa->g == NULL))
+    if (dsa == NULL || dsa->p == NULL || dsa->q == NULL || dsa->g == NULL)
         return 1;
     return 0;
 }
diff --git a/crypto/openssl/crypto/dsa/dsa_gen.c b/crypto/openssl/crypto/dsa/dsa_gen.c
index 15f3bb4f3f39..1fce0f81c242 100644
--- a/crypto/openssl/crypto/dsa/dsa_gen.c
+++ b/crypto/openssl/crypto/dsa/dsa_gen.c
@@ -185,6 +185,9 @@ int dsa_builtin_paramgen(DSA *ret, size_t bits, size_t qbits,
     p = BN_CTX_get(ctx);
     test = BN_CTX_get(ctx);
 
+    if (test == NULL)
+        goto err;
+
     if (!BN_lshift(test, BN_value_one(), bits - 1))
         goto err;
 
@@ -197,7 +200,7 @@ int dsa_builtin_paramgen(DSA *ret, size_t bits, size_t qbits,
                 goto err;
 
             if (!seed_len || !seed_in) {
-                if (RAND_pseudo_bytes(seed, qsize) < 0)
+                if (RAND_bytes(seed, qsize) <= 0)
                     goto err;
                 seed_is_random = 1;
             } else {
@@ -491,7 +494,7 @@ int dsa_builtin_paramgen2(DSA *ret, size_t L, size_t N,
                 goto err;
 
             if (!seed_in) {
-                if (RAND_pseudo_bytes(seed, seed_len) < 0)
+                if (RAND_bytes(seed, seed_len) <= 0)
                     goto err;
             }
             /* step 2 */
diff --git a/crypto/openssl/crypto/dsa/dsa_ossl.c b/crypto/openssl/crypto/dsa/dsa_ossl.c
index efc4f1b6aeba..58013a4a13b5 100644
--- a/crypto/openssl/crypto/dsa/dsa_ossl.c
+++ b/crypto/openssl/crypto/dsa/dsa_ossl.c
@@ -247,11 +247,13 @@ static int dsa_sign_setup(DSA *dsa, BN_CTX *ctx_in, BIGNUM **kinvp,
     do
         if (!BN_rand_range(&k, dsa->q))
             goto err;
-    while (BN_is_zero(&k)) ;
+    while (BN_is_zero(&k));
+
     if ((dsa->flags & DSA_FLAG_NO_EXP_CONSTTIME) == 0) {
         BN_set_flags(&k, BN_FLG_CONSTTIME);
     }
 
+
     if (dsa->flags & DSA_FLAG_CACHE_MONT_P) {
         if (!BN_MONT_CTX_set_locked(&dsa->method_mont_p,
                                     CRYPTO_LOCK_DSA, dsa->p, ctx))
@@ -264,6 +266,8 @@ static int dsa_sign_setup(DSA *dsa, BN_CTX *ctx_in, BIGNUM **kinvp,
         if (!BN_copy(&kq, &k))
             goto err;
 
+        BN_set_flags(&kq, BN_FLG_CONSTTIME);
+
         /*
          * We do not want timing information to leak the length of k, so we
          * compute g^k using an equivalent exponent of fixed length. (This
@@ -282,6 +286,7 @@ static int dsa_sign_setup(DSA *dsa, BN_CTX *ctx_in, BIGNUM **kinvp,
     } else {
         K = &k;
     }
+
     DSA_BN_MOD_EXP(goto err, dsa, r, dsa->g, K, dsa->p, ctx,
                    dsa->method_mont_p);
     if (!BN_mod(r, r, dsa->q, ctx))
diff --git a/crypto/openssl/crypto/ec/Makefile b/crypto/openssl/crypto/ec/Makefile
index 89491454a441..6628390ba48e 100644
--- a/crypto/openssl/crypto/ec/Makefile
+++ b/crypto/openssl/crypto/ec/Makefile
@@ -131,7 +131,7 @@ ec_ameth.o: ../../include/openssl/pkcs7.h ../../include/openssl/safestack.h
 ec_ameth.o: ../../include/openssl/sha.h ../../include/openssl/stack.h
 ec_ameth.o: ../../include/openssl/symhacks.h ../../include/openssl/x509.h
 ec_ameth.o: ../../include/openssl/x509_vfy.h ../asn1/asn1_locl.h ../cryptlib.h
-ec_ameth.o: ec_ameth.c
+ec_ameth.o: ec_ameth.c ec_lcl.h
 ec_asn1.o: ../../include/openssl/asn1.h ../../include/openssl/asn1t.h
 ec_asn1.o: ../../include/openssl/bio.h ../../include/openssl/bn.h
 ec_asn1.o: ../../include/openssl/crypto.h ../../include/openssl/e_os2.h
diff --git a/crypto/openssl/crypto/ec/asm/ecp_nistz256-x86_64.pl b/crypto/openssl/crypto/ec/asm/ecp_nistz256-x86_64.pl
index 7140860e245b..7948bf71b51e 100755
--- a/crypto/openssl/crypto/ec/asm/ecp_nistz256-x86_64.pl
+++ b/crypto/openssl/crypto/ec/asm/ecp_nistz256-x86_64.pl
@@ -128,6 +128,7 @@ ecp_nistz256_mul_by_2:
 	push	%r13
 
 	mov	8*0($a_ptr), $a0
+	xor	$t4,$t4
 	mov	8*1($a_ptr), $a1
 	add	$a0, $a0		# a0:a3+a0:a3
 	mov	8*2($a_ptr), $a2
@@ -138,7 +139,7 @@ ecp_nistz256_mul_by_2:
 	adc	$a2, $a2
 	adc	$a3, $a3
 	 mov	$a1, $t1
-	sbb	$t4, $t4
+	adc	\$0, $t4
 
 	sub	8*0($a_ptr), $a0
 	 mov	$a2, $t2
@@ -146,14 +147,14 @@ ecp_nistz256_mul_by_2:
 	sbb	8*2($a_ptr), $a2
 	 mov	$a3, $t3
 	sbb	8*3($a_ptr), $a3
-	test	$t4, $t4
+	sbb	\$0, $t4
 
-	cmovz	$t0, $a0
-	cmovz	$t1, $a1
+	cmovc	$t0, $a0
+	cmovc	$t1, $a1
 	mov	$a0, 8*0($r_ptr)
-	cmovz	$t2, $a2
+	cmovc	$t2, $a2
 	mov	$a1, 8*1($r_ptr)
-	cmovz	$t3, $a3
+	cmovc	$t3, $a3
 	mov	$a2, 8*2($r_ptr)
 	mov	$a3, 8*3($r_ptr)
 
@@ -250,12 +251,12 @@ ecp_nistz256_mul_by_3:
 	sbb	\$0, $a2
 	 mov	$a3, $t3
 	sbb	.Lpoly+8*3(%rip), $a3
-	test	$t4, $t4
+	sbb	\$0, $t4
 
-	cmovz	$t0, $a0
-	cmovz	$t1, $a1
-	cmovz	$t2, $a2
-	cmovz	$t3, $a3
+	cmovc	$t0, $a0
+	cmovc	$t1, $a1
+	cmovc	$t2, $a2
+	cmovc	$t3, $a3
 
 	xor	$t4, $t4
 	add	8*0($a_ptr), $a0	# a0:a3+=a_ptr[0:3]
@@ -272,14 +273,14 @@ ecp_nistz256_mul_by_3:
 	sbb	\$0, $a2
 	 mov	$a3, $t3
 	sbb	.Lpoly+8*3(%rip), $a3
-	test	$t4, $t4
+	sbb	\$0, $t4
 
-	cmovz	$t0, $a0
-	cmovz	$t1, $a1
+	cmovc	$t0, $a0
+	cmovc	$t1, $a1
 	mov	$a0, 8*0($r_ptr)
-	cmovz	$t2, $a2
+	cmovc	$t2, $a2
 	mov	$a1, 8*1($r_ptr)
-	cmovz	$t3, $a3
+	cmovc	$t3, $a3
 	mov	$a2, 8*2($r_ptr)
 	mov	$a3, 8*3($r_ptr)
 
@@ -318,14 +319,14 @@ ecp_nistz256_add:
 	sbb	8*2($a_ptr), $a2
 	 mov	$a3, $t3
 	sbb	8*3($a_ptr), $a3
-	test	$t4, $t4
+	sbb	\$0, $t4
 
-	cmovz	$t0, $a0
-	cmovz	$t1, $a1
+	cmovc	$t0, $a0
+	cmovc	$t1, $a1
 	mov	$a0, 8*0($r_ptr)
-	cmovz	$t2, $a2
+	cmovc	$t2, $a2
 	mov	$a1, 8*1($r_ptr)
-	cmovz	$t3, $a3
+	cmovc	$t3, $a3
 	mov	$a2, 8*2($r_ptr)
 	mov	$a3, 8*3($r_ptr)
 
@@ -1840,13 +1841,14 @@ $code.=<<___;
 .type	__ecp_nistz256_add_toq,\@abi-omnipotent
 .align	32
 __ecp_nistz256_add_toq:
+	xor	$t4,$t4
 	add	8*0($b_ptr), $a0
 	adc	8*1($b_ptr), $a1
 	 mov	$a0, $t0
 	adc	8*2($b_ptr), $a2
 	adc	8*3($b_ptr), $a3
 	 mov	$a1, $t1
-	sbb	$t4, $t4
+	adc	\$0, $t4
 
 	sub	\$-1, $a0
 	 mov	$a2, $t2
@@ -1854,14 +1856,14 @@ __ecp_nistz256_add_toq:
 	sbb	\$0, $a2
 	 mov	$a3, $t3
 	sbb	$poly3, $a3
-	test	$t4, $t4
+	sbb	\$0, $t4
 
-	cmovz	$t0, $a0
-	cmovz	$t1, $a1
+	cmovc	$t0, $a0
+	cmovc	$t1, $a1
 	mov	$a0, 8*0($r_ptr)
-	cmovz	$t2, $a2
+	cmovc	$t2, $a2
 	mov	$a1, 8*1($r_ptr)
-	cmovz	$t3, $a3
+	cmovc	$t3, $a3
 	mov	$a2, 8*2($r_ptr)
 	mov	$a3, 8*3($r_ptr)
 
@@ -1929,13 +1931,14 @@ __ecp_nistz256_subq:
 .type	__ecp_nistz256_mul_by_2q,\@abi-omnipotent
 .align	32
 __ecp_nistz256_mul_by_2q:
+	xor	$t4, $t4
 	add	$a0, $a0		# a0:a3+a0:a3
 	adc	$a1, $a1
 	 mov	$a0, $t0
 	adc	$a2, $a2
 	adc	$a3, $a3
 	 mov	$a1, $t1
-	sbb	$t4, $t4
+	adc	\$0, $t4
 
 	sub	\$-1, $a0
 	 mov	$a2, $t2
@@ -1943,14 +1946,14 @@ __ecp_nistz256_mul_by_2q:
 	sbb	\$0, $a2
 	 mov	$a3, $t3
 	sbb	$poly3, $a3
-	test	$t4, $t4
+	sbb	\$0, $t4
 
-	cmovz	$t0, $a0
-	cmovz	$t1, $a1
+	cmovc	$t0, $a0
+	cmovc	$t1, $a1
 	mov	$a0, 8*0($r_ptr)
-	cmovz	$t2, $a2
+	cmovc	$t2, $a2
 	mov	$a1, 8*1($r_ptr)
-	cmovz	$t3, $a3
+	cmovc	$t3, $a3
 	mov	$a2, 8*2($r_ptr)
 	mov	$a3, 8*3($r_ptr)
 
@@ -2241,16 +2244,14 @@ $code.=<<___;
 	mov	$b_org, $a_ptr			# reassign
 	movdqa	%xmm0, $in1_x(%rsp)
 	movdqa	%xmm1, $in1_x+0x10(%rsp)
-	por	%xmm0, %xmm1
 	movdqa	%xmm2, $in1_y(%rsp)
 	movdqa	%xmm3, $in1_y+0x10(%rsp)
-	por	%xmm2, %xmm3
 	movdqa	%xmm4, $in1_z(%rsp)
 	movdqa	%xmm5, $in1_z+0x10(%rsp)
-	por	%xmm1, %xmm3
+	por	%xmm4, %xmm5
 
 	movdqu	0x00($a_ptr), %xmm0		# copy	*(P256_POINT *)$b_ptr
-	 pshufd	\$0xb1, %xmm3, %xmm5
+	 pshufd	\$0xb1, %xmm5, %xmm3
 	movdqu	0x10($a_ptr), %xmm1
 	movdqu	0x20($a_ptr), %xmm2
 	 por	%xmm3, %xmm5
@@ -2262,14 +2263,14 @@ $code.=<<___;
 	movdqa	%xmm0, $in2_x(%rsp)
 	 pshufd	\$0x1e, %xmm5, %xmm4
 	movdqa	%xmm1, $in2_x+0x10(%rsp)
-	por	%xmm0, %xmm1
-	 movq	$r_ptr, %xmm0			# save $r_ptr
+	movdqu	0x40($a_ptr),%xmm0		# in2_z again
+	movdqu	0x50($a_ptr),%xmm1
 	movdqa	%xmm2, $in2_y(%rsp)
 	movdqa	%xmm3, $in2_y+0x10(%rsp)
-	por	%xmm2, %xmm3
 	 por	%xmm4, %xmm5
 	 pxor	%xmm4, %xmm4
-	por	%xmm1, %xmm3
+	por	%xmm0, %xmm1
+	 movq	$r_ptr, %xmm0			# save $r_ptr
 
 	lea	0x40-$bias($a_ptr), $a_ptr	# $a_ptr is still valid
 	 mov	$src0, $in2_z+8*0(%rsp)		# make in2_z copy
@@ -2280,8 +2281,8 @@ $code.=<<___;
 	call	__ecp_nistz256_sqr_mont$x	# p256_sqr_mont(Z2sqr, in2_z);
 
 	pcmpeqd	%xmm4, %xmm5
-	pshufd	\$0xb1, %xmm3, %xmm4
-	por	%xmm3, %xmm4
+	pshufd	\$0xb1, %xmm1, %xmm4
+	por	%xmm1, %xmm4
 	pshufd	\$0, %xmm5, %xmm5		# in1infty
 	pshufd	\$0x1e, %xmm4, %xmm3
 	por	%xmm3, %xmm4
@@ -2405,6 +2406,7 @@ $code.=<<___;
 	#lea	$Hsqr(%rsp), $r_ptr	# 2*U1*H^2
 	#call	__ecp_nistz256_mul_by_2	# ecp_nistz256_mul_by_2(Hsqr, U2);
 
+	xor	$t4, $t4
 	add	$acc0, $acc0		# a0:a3+a0:a3
 	lea	$Rsqr(%rsp), $a_ptr
 	adc	$acc1, $acc1
@@ -2412,7 +2414,7 @@ $code.=<<___;
 	adc	$acc2, $acc2
 	adc	$acc3, $acc3
 	 mov	$acc1, $t1
-	sbb	$t4, $t4
+	adc	\$0, $t4
 
 	sub	\$-1, $acc0
 	 mov	$acc2, $t2
@@ -2420,15 +2422,15 @@ $code.=<<___;
 	sbb	\$0, $acc2
 	 mov	$acc3, $t3
 	sbb	$poly3, $acc3
-	test	$t4, $t4
+	sbb	\$0, $t4
 
-	cmovz	$t0, $acc0
+	cmovc	$t0, $acc0
 	mov	8*0($a_ptr), $t0
-	cmovz	$t1, $acc1
+	cmovc	$t1, $acc1
 	mov	8*1($a_ptr), $t1
-	cmovz	$t2, $acc2
+	cmovc	$t2, $acc2
 	mov	8*2($a_ptr), $t2
-	cmovz	$t3, $acc3
+	cmovc	$t3, $acc3
 	mov	8*3($a_ptr), $t3
 
 	call	__ecp_nistz256_sub$x		# p256_sub(res_x, Rsqr, Hsqr);
@@ -2612,16 +2614,14 @@ $code.=<<___;
 	 mov	0x40+8*3($a_ptr), $acc0
 	movdqa	%xmm0, $in1_x(%rsp)
 	movdqa	%xmm1, $in1_x+0x10(%rsp)
-	por	%xmm0, %xmm1
 	movdqa	%xmm2, $in1_y(%rsp)
 	movdqa	%xmm3, $in1_y+0x10(%rsp)
-	por	%xmm2, %xmm3
 	movdqa	%xmm4, $in1_z(%rsp)
 	movdqa	%xmm5, $in1_z+0x10(%rsp)
-	por	%xmm1, %xmm3
+	por	%xmm4, %xmm5
 
 	movdqu	0x00($b_ptr), %xmm0	# copy	*(P256_POINT_AFFINE *)$b_ptr
-	 pshufd	\$0xb1, %xmm3, %xmm5
+	 pshufd	\$0xb1, %xmm5, %xmm3
 	movdqu	0x10($b_ptr), %xmm1
 	movdqu	0x20($b_ptr), %xmm2
 	 por	%xmm3, %xmm5
@@ -2710,6 +2710,7 @@ $code.=<<___;
 	#lea	$Hsqr(%rsp), $r_ptr	# 2*U1*H^2
 	#call	__ecp_nistz256_mul_by_2	# ecp_nistz256_mul_by_2(Hsqr, U2);
 
+	xor	$t4, $t4
 	add	$acc0, $acc0		# a0:a3+a0:a3
 	lea	$Rsqr(%rsp), $a_ptr
 	adc	$acc1, $acc1
@@ -2717,7 +2718,7 @@ $code.=<<___;
 	adc	$acc2, $acc2
 	adc	$acc3, $acc3
 	 mov	$acc1, $t1
-	sbb	$t4, $t4
+	adc	\$0, $t4
 
 	sub	\$-1, $acc0
 	 mov	$acc2, $t2
@@ -2725,15 +2726,15 @@ $code.=<<___;
 	sbb	\$0, $acc2
 	 mov	$acc3, $t3
 	sbb	$poly3, $acc3
-	test	$t4, $t4
+	sbb	\$0, $t4
 
-	cmovz	$t0, $acc0
+	cmovc	$t0, $acc0
 	mov	8*0($a_ptr), $t0
-	cmovz	$t1, $acc1
+	cmovc	$t1, $acc1
 	mov	8*1($a_ptr), $t1
-	cmovz	$t2, $acc2
+	cmovc	$t2, $acc2
 	mov	8*2($a_ptr), $t2
-	cmovz	$t3, $acc3
+	cmovc	$t3, $acc3
 	mov	8*3($a_ptr), $t3
 
 	call	__ecp_nistz256_sub$x		# p256_sub(res_x, Rsqr, Hsqr);
@@ -2885,14 +2886,14 @@ __ecp_nistz256_add_tox:
 	sbb	\$0, $a2
 	 mov	$a3, $t3
 	sbb	$poly3, $a3
+	sbb	\$0, $t4
 
-	bt	\$0, $t4
-	cmovnc	$t0, $a0
-	cmovnc	$t1, $a1
+	cmovc	$t0, $a0
+	cmovc	$t1, $a1
 	mov	$a0, 8*0($r_ptr)
-	cmovnc	$t2, $a2
+	cmovc	$t2, $a2
 	mov	$a1, 8*1($r_ptr)
-	cmovnc	$t3, $a3
+	cmovc	$t3, $a3
 	mov	$a2, 8*2($r_ptr)
 	mov	$a3, 8*3($r_ptr)
 
@@ -2980,14 +2981,14 @@ __ecp_nistz256_mul_by_2x:
 	sbb	\$0, $a2
 	 mov	$a3, $t3
 	sbb	$poly3, $a3
+	sbb	\$0, $t4
 
-	bt	\$0, $t4
-	cmovnc	$t0, $a0
-	cmovnc	$t1, $a1
+	cmovc	$t0, $a0
+	cmovc	$t1, $a1
 	mov	$a0, 8*0($r_ptr)
-	cmovnc	$t2, $a2
+	cmovc	$t2, $a2
 	mov	$a1, 8*1($r_ptr)
-	cmovnc	$t3, $a3
+	cmovc	$t3, $a3
 	mov	$a2, 8*2($r_ptr)
 	mov	$a3, 8*3($r_ptr)
 
diff --git a/crypto/openssl/crypto/ec/ec_ameth.c b/crypto/openssl/crypto/ec/ec_ameth.c
index 83e208cfe491..d089af7a2830 100644
--- a/crypto/openssl/crypto/ec/ec_ameth.c
+++ b/crypto/openssl/crypto/ec/ec_ameth.c
@@ -66,9 +66,12 @@
 #endif
 #include <openssl/asn1t.h>
 #include "asn1_locl.h"
+#include "ec_lcl.h"
 
+#ifndef OPENSSL_NO_CMS
 static int ecdh_cms_decrypt(CMS_RecipientInfo *ri);
 static int ecdh_cms_encrypt(CMS_RecipientInfo *ri);
+#endif
 
 static int eckey_param2type(int *pptype, void **ppval, EC_KEY *ec_key)
 {
@@ -221,6 +224,8 @@ static int eckey_pub_cmp(const EVP_PKEY *a, const EVP_PKEY *b)
     const EC_GROUP *group = EC_KEY_get0_group(b->pkey.ec);
     const EC_POINT *pa = EC_KEY_get0_public_key(a->pkey.ec),
         *pb = EC_KEY_get0_public_key(b->pkey.ec);
+    if (group == NULL || pa == NULL || pb == NULL)
+        return -2;
     r = EC_POINT_cmp(group, pa, pb, NULL);
     if (r == 0)
         return 1;
@@ -299,15 +304,13 @@ static int eckey_priv_decode(EVP_PKEY *pkey, PKCS8_PRIV_KEY_INFO *p8)
 
 static int eckey_priv_encode(PKCS8_PRIV_KEY_INFO *p8, const EVP_PKEY *pkey)
 {
-    EC_KEY *ec_key;
+    EC_KEY ec_key = *(pkey->pkey.ec);
     unsigned char *ep, *p;
     int eplen, ptype;
     void *pval;
-    unsigned int tmp_flags, old_flags;
-
-    ec_key = pkey->pkey.ec;
+    unsigned int old_flags;
 
-    if (!eckey_param2type(&ptype, &pval, ec_key)) {
+    if (!eckey_param2type(&ptype, &pval, &ec_key)) {
         ECerr(EC_F_ECKEY_PRIV_ENCODE, EC_R_DECODE_ERROR);
         return 0;
     }
@@ -318,30 +321,25 @@ static int eckey_priv_encode(PKCS8_PRIV_KEY_INFO *p8, const EVP_PKEY *pkey)
      * do not include the parameters in the SEC1 private key see PKCS#11
      * 12.11
      */
-    old_flags = EC_KEY_get_enc_flags(ec_key);
-    tmp_flags = old_flags | EC_PKEY_NO_PARAMETERS;
-    EC_KEY_set_enc_flags(ec_key, tmp_flags);
-    eplen = i2d_ECPrivateKey(ec_key, NULL);
+    old_flags = EC_KEY_get_enc_flags(&ec_key);
+    EC_KEY_set_enc_flags(&ec_key, old_flags | EC_PKEY_NO_PARAMETERS);
+
+    eplen = i2d_ECPrivateKey(&ec_key, NULL);
     if (!eplen) {
-        EC_KEY_set_enc_flags(ec_key, old_flags);
         ECerr(EC_F_ECKEY_PRIV_ENCODE, ERR_R_EC_LIB);
         return 0;
     }
     ep = (unsigned char *)OPENSSL_malloc(eplen);
     if (!ep) {
-        EC_KEY_set_enc_flags(ec_key, old_flags);
         ECerr(EC_F_ECKEY_PRIV_ENCODE, ERR_R_MALLOC_FAILURE);
         return 0;
     }
     p = ep;
-    if (!i2d_ECPrivateKey(ec_key, &p)) {
-        EC_KEY_set_enc_flags(ec_key, old_flags);
+    if (!i2d_ECPrivateKey(&ec_key, &p)) {
         OPENSSL_free(ep);
         ECerr(EC_F_ECKEY_PRIV_ENCODE, ERR_R_EC_LIB);
         return 0;
     }
-    /* restore old encoding flags */
-    EC_KEY_set_enc_flags(ec_key, old_flags);
 
     if (!PKCS8_pkey_set0(p8, OBJ_nid2obj(NID_X9_62_id_ecPublicKey), 0,
                          ptype, pval, ep, eplen))
@@ -378,7 +376,7 @@ static int ec_bits(const EVP_PKEY *pkey)
 
 static int ec_missing_parameters(const EVP_PKEY *pkey)
 {
-    if (EC_KEY_get0_group(pkey->pkey.ec) == NULL)
+    if (pkey->pkey.ec == NULL || EC_KEY_get0_group(pkey->pkey.ec) == NULL)
         return 1;
     return 0;
 }
@@ -398,6 +396,8 @@ static int ec_cmp_parameters(const EVP_PKEY *a, const EVP_PKEY *b)
 {
     const EC_GROUP *group_a = EC_KEY_get0_group(a->pkey.ec),
         *group_b = EC_KEY_get0_group(b->pkey.ec);
+    if (group_a == NULL || group_b == NULL)
+        return -2;
     if (EC_GROUP_cmp(group_a, group_b, NULL))
         return 0;
     else
diff --git a/crypto/openssl/crypto/ec/ec_key.c b/crypto/openssl/crypto/ec/ec_key.c
index bc94ab5661ff..456080ecfede 100644
--- a/crypto/openssl/crypto/ec/ec_key.c
+++ b/crypto/openssl/crypto/ec/ec_key.c
@@ -377,9 +377,9 @@ int EC_KEY_set_public_key_affine_coordinates(EC_KEY *key, BIGNUM *x,
         return 0;
     }
     ctx = BN_CTX_new();
-    if (!ctx)
-        goto err;
-
+    if (ctx == NULL)
+        return 0;
+    BN_CTX_start(ctx);
     point = EC_POINT_new(key->group);
 
     if (!point)
@@ -432,10 +432,9 @@ int EC_KEY_set_public_key_affine_coordinates(EC_KEY *key, BIGNUM *x,
     ok = 1;
 
  err:
-    if (ctx)
-        BN_CTX_free(ctx);
-    if (point)
-        EC_POINT_free(point);
+    BN_CTX_end(ctx);
+    BN_CTX_free(ctx);
+    EC_POINT_free(point);
     return ok;
 
 }
diff --git a/crypto/openssl/crypto/ec/ecp_nistz256.c b/crypto/openssl/crypto/ec/ecp_nistz256.c
index ca44d0aaeec4..99b8d613c833 100644
--- a/crypto/openssl/crypto/ec/ecp_nistz256.c
+++ b/crypto/openssl/crypto/ec/ecp_nistz256.c
@@ -82,19 +82,36 @@ typedef struct ec_pre_comp_st {
 } EC_PRE_COMP;
 
 /* Functions implemented in assembly */
+/*
+ * Most of below mentioned functions *preserve* the property of inputs
+ * being fully reduced, i.e. being in [0, modulus) range. Simply put if
+ * inputs are fully reduced, then output is too. Note that reverse is
+ * not true, in sense that given partially reduced inputs output can be
+ * either, not unlikely reduced. And "most" in first sentence refers to
+ * the fact that given the calculations flow one can tolerate that
+ * addition, 1st function below, produces partially reduced result *if*
+ * multiplications by 2 and 3, which customarily use addition, fully
+ * reduce it. This effectively gives two options: a) addition produces
+ * fully reduced result [as long as inputs are, just like remaining
+ * functions]; b) addition is allowed to produce partially reduced
+ * result, but multiplications by 2 and 3 perform additional reduction
+ * step. Choice between the two can be platform-specific, but it was a)
+ * in all cases so far...
+ */
+/* Modular add: res = a+b mod P   */
+void ecp_nistz256_add(BN_ULONG res[P256_LIMBS],
+                      const BN_ULONG a[P256_LIMBS],
+                      const BN_ULONG b[P256_LIMBS]);
 /* Modular mul by 2: res = 2*a mod P */
 void ecp_nistz256_mul_by_2(BN_ULONG res[P256_LIMBS],
                            const BN_ULONG a[P256_LIMBS]);
-/* Modular div by 2: res = a/2 mod P */
-void ecp_nistz256_div_by_2(BN_ULONG res[P256_LIMBS],
-                           const BN_ULONG a[P256_LIMBS]);
 /* Modular mul by 3: res = 3*a mod P */
 void ecp_nistz256_mul_by_3(BN_ULONG res[P256_LIMBS],
                            const BN_ULONG a[P256_LIMBS]);
-/* Modular add: res = a+b mod P   */
-void ecp_nistz256_add(BN_ULONG res[P256_LIMBS],
-                      const BN_ULONG a[P256_LIMBS],
-                      const BN_ULONG b[P256_LIMBS]);
+
+/* Modular div by 2: res = a/2 mod P */
+void ecp_nistz256_div_by_2(BN_ULONG res[P256_LIMBS],
+                           const BN_ULONG a[P256_LIMBS]);
 /* Modular sub: res = a-b mod P   */
 void ecp_nistz256_sub(BN_ULONG res[P256_LIMBS],
                       const BN_ULONG a[P256_LIMBS],
@@ -205,21 +222,29 @@ static BN_ULONG is_equal(const BN_ULONG a[P256_LIMBS],
     return is_zero(res);
 }
 
-static BN_ULONG is_one(const BN_ULONG a[P256_LIMBS])
+static BN_ULONG is_one(const BIGNUM *z)
 {
-    BN_ULONG res;
-
-    res = a[0] ^ ONE[0];
-    res |= a[1] ^ ONE[1];
-    res |= a[2] ^ ONE[2];
-    res |= a[3] ^ ONE[3];
-    if (P256_LIMBS == 8) {
-        res |= a[4] ^ ONE[4];
-        res |= a[5] ^ ONE[5];
-        res |= a[6] ^ ONE[6];
+    BN_ULONG res = 0;
+    BN_ULONG *a = z->d;
+
+    if (z->top == (P256_LIMBS - P256_LIMBS / 8)) {
+        res = a[0] ^ ONE[0];
+        res |= a[1] ^ ONE[1];
+        res |= a[2] ^ ONE[2];
+        res |= a[3] ^ ONE[3];
+        if (P256_LIMBS == 8) {
+            res |= a[4] ^ ONE[4];
+            res |= a[5] ^ ONE[5];
+            res |= a[6] ^ ONE[6];
+            /*
+             * no check for a[7] (being zero) on 32-bit platforms,
+             * because value of "one" takes only 7 limbs.
+             */
+        }
+        res = is_zero(res);
     }
 
-    return is_zero(res);
+    return res;
 }
 
 static int ecp_nistz256_set_words(BIGNUM *a, BN_ULONG words[P256_LIMBS])
@@ -315,19 +340,16 @@ static void ecp_nistz256_point_add(P256_POINT *r,
     const BN_ULONG *in2_y = b->Y;
     const BN_ULONG *in2_z = b->Z;
 
-    /* We encode infinity as (0,0), which is not on the curve,
-     * so it is OK. */
-    in1infty = (in1_x[0] | in1_x[1] | in1_x[2] | in1_x[3] |
-                in1_y[0] | in1_y[1] | in1_y[2] | in1_y[3]);
+    /*
+     * Infinity in encoded as (,,0)
+     */
+    in1infty = (in1_z[0] | in1_z[1] | in1_z[2] | in1_z[3]);
     if (P256_LIMBS == 8)
-        in1infty |= (in1_x[4] | in1_x[5] | in1_x[6] | in1_x[7] |
-                     in1_y[4] | in1_y[5] | in1_y[6] | in1_y[7]);
+        in1infty |= (in1_z[4] | in1_z[5] | in1_z[6] | in1_z[7]);
 
-    in2infty = (in2_x[0] | in2_x[1] | in2_x[2] | in2_x[3] |
-                in2_y[0] | in2_y[1] | in2_y[2] | in2_y[3]);
+    in2infty = (in2_z[0] | in2_z[1] | in2_z[2] | in2_z[3]);
     if (P256_LIMBS == 8)
-        in2infty |= (in2_x[4] | in2_x[5] | in2_x[6] | in2_x[7] |
-                     in2_y[4] | in2_y[5] | in2_y[6] | in2_y[7]);
+        in2infty |= (in2_z[4] | in2_z[5] | in2_z[6] | in2_z[7]);
 
     in1infty = is_zero(in1infty);
     in2infty = is_zero(in2infty);
@@ -416,15 +438,16 @@ static void ecp_nistz256_point_add_affine(P256_POINT *r,
     const BN_ULONG *in2_y = b->Y;
 
     /*
-     * In affine representation we encode infty as (0,0), which is not on the
-     * curve, so it is OK
+     * Infinity in encoded as (,,0)
      */
-    in1infty = (in1_x[0] | in1_x[1] | in1_x[2] | in1_x[3] |
-                in1_y[0] | in1_y[1] | in1_y[2] | in1_y[3]);
+    in1infty = (in1_z[0] | in1_z[1] | in1_z[2] | in1_z[3]);
     if (P256_LIMBS == 8)
-        in1infty |= (in1_x[4] | in1_x[5] | in1_x[6] | in1_x[7] |
-                     in1_y[4] | in1_y[5] | in1_y[6] | in1_y[7]);
+        in1infty |= (in1_z[4] | in1_z[5] | in1_z[6] | in1_z[7]);
 
+    /*
+     * In affine representation we encode infinity as (0,0), which is
+     * not on the curve, so it is OK
+     */
     in2infty = (in2_x[0] | in2_x[1] | in2_x[2] | in2_x[3] |
                 in2_y[0] | in2_y[1] | in2_y[2] | in2_y[3]);
     if (P256_LIMBS == 8)
@@ -741,9 +764,8 @@ static int ecp_nistz256_is_affine_G(const EC_POINT *generator)
 {
     return (generator->X.top == P256_LIMBS) &&
         (generator->Y.top == P256_LIMBS) &&
-        (generator->Z.top == (P256_LIMBS - P256_LIMBS / 8)) &&
         is_equal(generator->X.d, def_xG) &&
-        is_equal(generator->Y.d, def_yG) && is_one(generator->Z.d);
+        is_equal(generator->Y.d, def_yG) && is_one(&generator->Z);
 }
 
 static int ecp_nistz256_mult_precompute(EC_GROUP *group, BN_CTX *ctx)
@@ -1249,6 +1271,8 @@ static int ecp_nistz256_points_mul(const EC_GROUP *group,
             } else
 #endif
             {
+                BN_ULONG infty;
+
                 /* First window */
                 wvalue = (p_str[0] << 1) & mask;
                 index += window_size;
@@ -1260,7 +1284,30 @@ static int ecp_nistz256_points_mul(const EC_GROUP *group,
                 ecp_nistz256_neg(p.p.Z, p.p.Y);
                 copy_conditional(p.p.Y, p.p.Z, wvalue & 1);
 
-                memcpy(p.p.Z, ONE, sizeof(ONE));
+                /*
+                 * Since affine infinity is encoded as (0,0) and
+                 * Jacobian ias (,,0), we need to harmonize them
+                 * by assigning "one" or zero to Z.
+                 */
+                infty = (p.p.X[0] | p.p.X[1] | p.p.X[2] | p.p.X[3] |
+                         p.p.Y[0] | p.p.Y[1] | p.p.Y[2] | p.p.Y[3]);
+                if (P256_LIMBS == 8)
+                    infty |= (p.p.X[4] | p.p.X[5] | p.p.X[6] | p.p.X[7] |
+                              p.p.Y[4] | p.p.Y[5] | p.p.Y[6] | p.p.Y[7]);
+
+                infty = 0 - is_zero(infty);
+                infty = ~infty;
+
+                p.p.Z[0] = ONE[0] & infty;
+                p.p.Z[1] = ONE[1] & infty;
+                p.p.Z[2] = ONE[2] & infty;
+                p.p.Z[3] = ONE[3] & infty;
+                if (P256_LIMBS == 8) {
+                    p.p.Z[4] = ONE[4] & infty;
+                    p.p.Z[5] = ONE[5] & infty;
+                    p.p.Z[6] = ONE[6] & infty;
+                    p.p.Z[7] = ONE[7] & infty;
+                }
 
                 for (i = 1; i < 37; i++) {
                     unsigned int off = (index - 1) / 8;
@@ -1331,7 +1378,7 @@ static int ecp_nistz256_points_mul(const EC_GROUP *group,
         !ecp_nistz256_set_words(&r->Z, p.p.Z)) {
         goto err;
     }
-    r->Z_is_one = is_one(p.p.Z) & 1;
+    r->Z_is_one = is_one(&r->Z) & 1;
 
     ret = 1;
 
diff --git a/crypto/openssl/crypto/engine/eng_cryptodev.c b/crypto/openssl/crypto/engine/eng_cryptodev.c
index 8fb9c3373dd6..65a74df2362e 100644
--- a/crypto/openssl/crypto/engine/eng_cryptodev.c
+++ b/crypto/openssl/crypto/engine/eng_cryptodev.c
@@ -26,6 +26,7 @@
  *
  */
 
+#include <string.h>
 #include <openssl/objects.h>
 #include <openssl/engine.h>
 #include <openssl/evp.h>
@@ -934,11 +935,15 @@ static int cryptodev_digest_copy(EVP_MD_CTX *to, const EVP_MD_CTX *from)
         return (0);
     }
 
+    dstate->mac_len = fstate->mac_len;
     if (fstate->mac_len != 0) {
         if (fstate->mac_data != NULL) {
             dstate->mac_data = OPENSSL_malloc(fstate->mac_len);
+            if (dstate->ac_data == NULL) {
+                printf("cryptodev_digest_init: malloc failed\n");
+                return 0;
+            }
             memcpy(dstate->mac_data, fstate->mac_data, fstate->mac_len);
-            dstate->mac_len = fstate->mac_len;
         }
     }
 
@@ -1064,8 +1069,7 @@ static void zapparams(struct crypt_kop *kop)
     int i;
 
     for (i = 0; i < kop->crk_iparams + kop->crk_oparams; i++) {
-        if (kop->crk_param[i].crp_p)
-            free(kop->crk_param[i].crp_p);
+        OPENSSL_free(kop->crk_param[i].crp_p);
         kop->crk_param[i].crp_p = NULL;
         kop->crk_param[i].crp_nbits = 0;
     }
@@ -1078,16 +1082,25 @@ cryptodev_asym(struct crypt_kop *kop, int rlen, BIGNUM *r, int slen,
     int fd, ret = -1;
 
     if ((fd = get_asym_dev_crypto()) < 0)
-        return (ret);
+        return ret;
 
     if (r) {
-        kop->crk_param[kop->crk_iparams].crp_p = calloc(rlen, sizeof(char));
+        kop->crk_param[kop->crk_iparams].crp_p = OPENSSL_malloc(rlen);
+        if (kop->crk_param[kop->crk_iparams].crp_p == NULL)
+            return ret;
+        memset(kop->crk_param[kop->crk_iparams].crp_p, 0, (size_t)rlen);
         kop->crk_param[kop->crk_iparams].crp_nbits = rlen * 8;
         kop->crk_oparams++;
     }
     if (s) {
-        kop->crk_param[kop->crk_iparams + 1].crp_p =
-            calloc(slen, sizeof(char));
+        kop->crk_param[kop->crk_iparams + 1].crp_p = OPENSSL_malloc(slen);
+        /* No need to free the kop->crk_iparams parameter if it was allocated,
+         * callers of this routine have to free allocated parameters through
+         * zapparams both in case of success and failure
+         */
+        if (kop->crk_param[kop->crk_iparams+1].crp_p == NULL)
+            return ret;
+        memset(kop->crk_param[kop->crk_iparams + 1].crp_p, 0, (size_t)slen);
         kop->crk_param[kop->crk_iparams + 1].crp_nbits = slen * 8;
         kop->crk_oparams++;
     }
@@ -1100,7 +1113,7 @@ cryptodev_asym(struct crypt_kop *kop, int rlen, BIGNUM *r, int slen,
         ret = 0;
     }
 
-    return (ret);
+    return ret;
 }
 
 static int
diff --git a/crypto/openssl/crypto/evp/bio_enc.c b/crypto/openssl/crypto/evp/bio_enc.c
index 363e0246aedc..0806f233b67d 100644
--- a/crypto/openssl/crypto/evp/bio_enc.c
+++ b/crypto/openssl/crypto/evp/bio_enc.c
@@ -201,9 +201,14 @@ static int enc_read(BIO *b, char *out, int outl)
                 break;
             }
         } else {
-            EVP_CipherUpdate(&(ctx->cipher),
-                             (unsigned char *)ctx->buf, &ctx->buf_len,
-                             (unsigned char *)&(ctx->buf[BUF_OFFSET]), i);
+            if (!EVP_CipherUpdate(&ctx->cipher,
+                                  (unsigned char *)ctx->buf, &ctx->buf_len,
+                                  (unsigned char *)&(ctx->buf[BUF_OFFSET]),
+                                  i)) {
+                BIO_clear_retry_flags(b);
+                ctx->ok = 0;
+                return 0;
+            }
             ctx->cont = 1;
             /*
              * Note: it is possible for EVP_CipherUpdate to decrypt zero
@@ -260,9 +265,13 @@ static int enc_write(BIO *b, const char *in, int inl)
     ctx->buf_off = 0;
     while (inl > 0) {
         n = (inl > ENC_BLOCK_SIZE) ? ENC_BLOCK_SIZE : inl;
-        EVP_CipherUpdate(&(ctx->cipher),
-                         (unsigned char *)ctx->buf, &ctx->buf_len,
-                         (unsigned char *)in, n);
+        if (!EVP_CipherUpdate(&ctx->cipher,
+                              (unsigned char *)ctx->buf, &ctx->buf_len,
+                              (unsigned char *)in, n)) {
+            BIO_clear_retry_flags(b);
+            ctx->ok = 0;
+            return 0;
+        }
         inl -= n;
         in += n;
 
diff --git a/crypto/openssl/crypto/evp/bio_ok.c b/crypto/openssl/crypto/evp/bio_ok.c
index 5c32e35e17b9..16e151f11017 100644
--- a/crypto/openssl/crypto/evp/bio_ok.c
+++ b/crypto/openssl/crypto/evp/bio_ok.c
@@ -491,7 +491,7 @@ static int sig_out(BIO *b)
      * FIXME: there's absolutely no guarantee this makes any sense at all,
      * particularly now EVP_MD_CTX has been restructured.
      */
-    if (RAND_pseudo_bytes(md->md_data, md->digest->md_size) < 0)
+    if (RAND_bytes(md->md_data, md->digest->md_size) <= 0)
         goto berr;
     memcpy(&(ctx->buf[ctx->buf_len]), md->md_data, md->digest->md_size);
     longswap(&(ctx->buf[ctx->buf_len]), md->digest->md_size);
diff --git a/crypto/openssl/crypto/evp/c_all.c b/crypto/openssl/crypto/evp/c_all.c
index a3ed00d4c169..719e34d22fde 100644
--- a/crypto/openssl/crypto/evp/c_all.c
+++ b/crypto/openssl/crypto/evp/c_all.c
@@ -82,9 +82,4 @@ void OPENSSL_add_all_algorithms_noconf(void)
     OPENSSL_cpuid_setup();
     OpenSSL_add_all_ciphers();
     OpenSSL_add_all_digests();
-#ifndef OPENSSL_NO_ENGINE
-# if defined(__OpenBSD__) || defined(__FreeBSD__) || defined(HAVE_CRYPTODEV)
-    ENGINE_setup_bsd_cryptodev();
-# endif
-#endif
 }
diff --git a/crypto/openssl/crypto/evp/digest.c b/crypto/openssl/crypto/evp/digest.c
index 5b642b23fc1c..4db179629d04 100644
--- a/crypto/openssl/crypto/evp/digest.c
+++ b/crypto/openssl/crypto/evp/digest.c
@@ -253,10 +253,10 @@ int EVP_DigestInit_ex(EVP_MD_CTX *ctx, const EVP_MD *type, ENGINE *impl)
 int EVP_DigestUpdate(EVP_MD_CTX *ctx, const void *data, size_t count)
 {
 #ifdef OPENSSL_FIPS
-    return FIPS_digestupdate(ctx, data, count);
-#else
-    return ctx->update(ctx, data, count);
+    if (FIPS_mode())
+        return FIPS_digestupdate(ctx, data, count);
 #endif
+    return ctx->update(ctx, data, count);
 }
 
 /* The caller can assume that this removes any secret data from the context */
@@ -271,10 +271,11 @@ int EVP_DigestFinal(EVP_MD_CTX *ctx, unsigned char *md, unsigned int *size)
 /* The caller can assume that this removes any secret data from the context */
 int EVP_DigestFinal_ex(EVP_MD_CTX *ctx, unsigned char *md, unsigned int *size)
 {
-#ifdef OPENSSL_FIPS
-    return FIPS_digestfinal(ctx, md, size);
-#else
     int ret;
+#ifdef OPENSSL_FIPS
+    if (FIPS_mode())
+        return FIPS_digestfinal(ctx, md, size);
+#endif
 
     OPENSSL_assert(ctx->digest->md_size <= EVP_MAX_MD_SIZE);
     ret = ctx->digest->final(ctx, md);
@@ -284,9 +285,8 @@ int EVP_DigestFinal_ex(EVP_MD_CTX *ctx, unsigned char *md, unsigned int *size)
         ctx->digest->cleanup(ctx);
         EVP_MD_CTX_set_flags(ctx, EVP_MD_CTX_FLAG_CLEANED);
     }
-    memset(ctx->md_data, 0, ctx->digest->ctx_size);
+    OPENSSL_cleanse(ctx->md_data, ctx->digest->ctx_size);
     return ret;
-#endif
 }
 
 int EVP_MD_CTX_copy(EVP_MD_CTX *out, const EVP_MD_CTX *in)
diff --git a/crypto/openssl/crypto/evp/e_rc4_hmac_md5.c b/crypto/openssl/crypto/evp/e_rc4_hmac_md5.c
index 2da11178294d..5e92855dfdc0 100644
--- a/crypto/openssl/crypto/evp/e_rc4_hmac_md5.c
+++ b/crypto/openssl/crypto/evp/e_rc4_hmac_md5.c
@@ -99,7 +99,7 @@ static int rc4_hmac_md5_init_key(EVP_CIPHER_CTX *ctx,
     return 1;
 }
 
-# if     !defined(OPENSSL_NO_ASM) &&     ( \
+# if     defined(RC4_ASM) && defined(MD5_ASM) &&     (	   \
         defined(__x86_64)       || defined(__x86_64__)  || \
         defined(_M_AMD64)       || defined(_M_X64)      || \
         defined(__INTEL__)              ) && \
@@ -254,6 +254,8 @@ static int rc4_hmac_md5_ctrl(EVP_CIPHER_CTX *ctx, int type, int arg,
             MD5_Init(&key->tail);
             MD5_Update(&key->tail, hmac_key, sizeof(hmac_key));
 
+            OPENSSL_cleanse(hmac_key, sizeof(hmac_key));
+
             return 1;
         }
     case EVP_CTRL_AEAD_TLS1_AAD:
diff --git a/crypto/openssl/crypto/evp/e_seed.c b/crypto/openssl/crypto/evp/e_seed.c
index 7249d1b1eecb..3d01eacac06e 100644
--- a/crypto/openssl/crypto/evp/e_seed.c
+++ b/crypto/openssl/crypto/evp/e_seed.c
@@ -70,7 +70,8 @@ typedef struct {
 } EVP_SEED_KEY;
 
 IMPLEMENT_BLOCK_CIPHER(seed, ks, SEED, EVP_SEED_KEY, NID_seed,
-                       16, 16, 16, 128, 0, seed_init_key, 0, 0, 0, 0)
+                       16, 16, 16, 128, EVP_CIPH_FLAG_DEFAULT_ASN1,
+                       seed_init_key, 0, 0, 0, 0)
 
 static int seed_init_key(EVP_CIPHER_CTX *ctx, const unsigned char *key,
                          const unsigned char *iv, int enc)
diff --git a/crypto/openssl/crypto/evp/evp_enc.c b/crypto/openssl/crypto/evp/evp_enc.c
index 7d7be245b021..0e40f09f2f91 100644
--- a/crypto/openssl/crypto/evp/evp_enc.c
+++ b/crypto/openssl/crypto/evp/evp_enc.c
@@ -170,7 +170,7 @@ int EVP_CipherInit_ex(EVP_CIPHER_CTX *ctx, const EVP_CIPHER *cipher,
 
 #ifdef OPENSSL_FIPS
         if (FIPS_mode()) {
-            const EVP_CIPHER *fcipher;
+            const EVP_CIPHER *fcipher = NULL;
             if (cipher)
                 fcipher = evp_get_fips_cipher(cipher);
             if (fcipher)
diff --git a/crypto/openssl/crypto/evp/evp_test.c b/crypto/openssl/crypto/evp/evp_test.c
index d7441ec7b702..98796427bf49 100644
--- a/crypto/openssl/crypto/evp/evp_test.c
+++ b/crypto/openssl/crypto/evp/evp_test.c
@@ -76,6 +76,7 @@ static void hexdump(FILE *f, const char *title, const unsigned char *s, int l)
 static int convert(unsigned char *s)
 {
     unsigned char *d;
+    int digits = 0;
 
     for (d = s; *s; s += 2, ++d) {
         unsigned int n;
@@ -86,8 +87,9 @@ static int convert(unsigned char *s)
         }
         sscanf((char *)s, "%2x", &n);
         *d = (unsigned char)n;
+        digits++;
     }
-    return s - d;
+    return digits;
 }
 
 static char *sstrsep(char **string, const char *delim)
diff --git a/crypto/openssl/crypto/evp/openbsd_hw.c b/crypto/openssl/crypto/evp/openbsd_hw.c
index 75d12e233028..07decf267433 100644
--- a/crypto/openssl/crypto/evp/openbsd_hw.c
+++ b/crypto/openssl/crypto/evp/openbsd_hw.c
@@ -133,6 +133,10 @@ static int dev_crypto_init_key(EVP_CIPHER_CTX *ctx, int cipher,
         return 0;
 
     CDATA(ctx)->key = OPENSSL_malloc(MAX_HW_KEY);
+    if (CDATA(ctx)->key == NULL {
+        err("CDATA(ctx)->key memory allocation failed");
+        return 0;
+    }
 
     assert(ctx->cipher->iv_len <= MAX_HW_IV);
 
@@ -186,6 +190,11 @@ static int dev_crypto_cipher(EVP_CIPHER_CTX *ctx, unsigned char *out,
 
             if (((unsigned long)in & 3) || cinl != inl) {
                 cin = OPENSSL_malloc(cinl);
+                if (cin == NULL) {
+                    err("cin - memory allocation failed");
+                    abort();
+                    return 0;
+                }
                 memcpy(cin, in, inl);
                 cryp.src = cin;
             }
@@ -334,6 +343,11 @@ static int do_digest(int ses, unsigned char *md, const void *data, int len)
             char *dcopy;
 
             dcopy = OPENSSL_malloc(len);
+            if (dcopy == NULL) {
+                err("dcopy - memory allocation failed");
+                abort();
+                return 0;
+            }
             memcpy(dcopy, data, len);
             cryp.src = dcopy;
             cryp.dst = cryp.src; // FIXME!!!
@@ -364,6 +378,10 @@ static int dev_crypto_md5_update(EVP_MD_CTX *ctx, const void *data,
         return do_digest(md_data->sess.ses, md_data->md, data, len);
 
     md_data->data = OPENSSL_realloc(md_data->data, md_data->len + len);
+    if (md_data->data == NULL) {
+        err("DEV_CRYPTO_MD5_UPDATE: unable to allocate memory");
+        abort();
+    }
     memcpy(md_data->data + md_data->len, data, len);
     md_data->len += len;
 
@@ -397,6 +415,10 @@ static int dev_crypto_md5_copy(EVP_MD_CTX *to, const EVP_MD_CTX *from)
     assert(from->digest->flags & EVP_MD_FLAG_ONESHOT);
 
     to_md->data = OPENSSL_malloc(from_md->len);
+    if (to_md->data == NULL) {
+        err("DEV_CRYPTO_MD5_COPY: unable to allocate memory");
+        abort();
+    }
     memcpy(to_md->data, from_md->data, from_md->len);
 
     return 1;
diff --git a/crypto/openssl/crypto/evp/p_lib.c b/crypto/openssl/crypto/evp/p_lib.c
index c0171244d5d0..545d04fd7744 100644
--- a/crypto/openssl/crypto/evp/p_lib.c
+++ b/crypto/openssl/crypto/evp/p_lib.c
@@ -130,6 +130,14 @@ int EVP_PKEY_copy_parameters(EVP_PKEY *to, const EVP_PKEY *from)
         EVPerr(EVP_F_EVP_PKEY_COPY_PARAMETERS, EVP_R_MISSING_PARAMETERS);
         goto err;
     }
+
+    if (!EVP_PKEY_missing_parameters(to)) {
+        if (EVP_PKEY_cmp_parameters(to, from) == 1)
+            return 1;
+        EVPerr(EVP_F_EVP_PKEY_COPY_PARAMETERS, EVP_R_DIFFERENT_PARAMETERS);
+        return 0;
+    }
+
     if (from->ameth && from->ameth->param_copy)
         return from->ameth->param_copy(to, from);
  err:
diff --git a/crypto/openssl/crypto/evp/pmeth_gn.c b/crypto/openssl/crypto/evp/pmeth_gn.c
index 6435f1b632cf..6a4d3573ff76 100644
--- a/crypto/openssl/crypto/evp/pmeth_gn.c
+++ b/crypto/openssl/crypto/evp/pmeth_gn.c
@@ -149,8 +149,10 @@ int EVP_PKEY_keygen(EVP_PKEY_CTX *ctx, EVP_PKEY **ppkey)
     if (!ppkey)
         return -1;
 
-    if (!*ppkey)
+    if (*ppkey == NULL)
         *ppkey = EVP_PKEY_new();
+    if (*ppkey == NULL)
+        return -1;
 
     ret = ctx->pmeth->keygen(ctx, *ppkey);
     if (ret <= 0) {
diff --git a/crypto/openssl/crypto/evp/pmeth_lib.c b/crypto/openssl/crypto/evp/pmeth_lib.c
index 9f81d10021a0..9668b3a9bcfb 100644
--- a/crypto/openssl/crypto/evp/pmeth_lib.c
+++ b/crypto/openssl/crypto/evp/pmeth_lib.c
@@ -91,7 +91,9 @@ static const EVP_PKEY_METHOD *standard_methods[] = {
     &ec_pkey_meth,
 #endif
     &hmac_pkey_meth,
+#ifndef OPENSSL_NO_CMAC
     &cmac_pkey_meth,
+#endif
 #ifndef OPENSSL_NO_DH
     &dhx_pkey_meth
 #endif
diff --git a/crypto/openssl/crypto/hmac/hmac.c b/crypto/openssl/crypto/hmac/hmac.c
index 51a0a3efcd67..213504e85fee 100644
--- a/crypto/openssl/crypto/hmac/hmac.c
+++ b/crypto/openssl/crypto/hmac/hmac.c
@@ -234,7 +234,7 @@ void HMAC_CTX_cleanup(HMAC_CTX *ctx)
     EVP_MD_CTX_cleanup(&ctx->i_ctx);
     EVP_MD_CTX_cleanup(&ctx->o_ctx);
     EVP_MD_CTX_cleanup(&ctx->md_ctx);
-    memset(ctx, 0, sizeof *ctx);
+    OPENSSL_cleanse(ctx, sizeof *ctx);
 }
 
 unsigned char *HMAC(const EVP_MD *evp_md, const void *key, int key_len,
diff --git a/crypto/openssl/crypto/jpake/jpake.c b/crypto/openssl/crypto/jpake/jpake.c
index ebc09755756d..2ba75f0172c1 100644
--- a/crypto/openssl/crypto/jpake/jpake.c
+++ b/crypto/openssl/crypto/jpake/jpake.c
@@ -116,6 +116,8 @@ JPAKE_CTX *JPAKE_CTX_new(const char *name, const char *peer_name,
                          const BIGNUM *secret)
 {
     JPAKE_CTX *ctx = OPENSSL_malloc(sizeof *ctx);
+    if (ctx == NULL)
+        return NULL;
 
     JPAKE_CTX_init(ctx, name, peer_name, p, g, q, secret);
 
@@ -151,6 +153,8 @@ static void hashbn(SHA_CTX *sha, const BIGNUM *bn)
     size_t l = BN_num_bytes(bn);
     unsigned char *bin = OPENSSL_malloc(l);
 
+    if (bin == NULL)
+        return;
     hashlength(sha, l);
     BN_bn2bin(bn, bin);
     SHA1_Update(sha, bin, l);
diff --git a/crypto/openssl/crypto/lhash/lhash.c b/crypto/openssl/crypto/lhash/lhash.c
index 53c5c138bb67..f20353aea33f 100644
--- a/crypto/openssl/crypto/lhash/lhash.c
+++ b/crypto/openssl/crypto/lhash/lhash.c
@@ -335,8 +335,8 @@ static void expand(_LHASH *lh)
         n = (LHASH_NODE **)OPENSSL_realloc(lh->b,
                                            (int)(sizeof(LHASH_NODE *) * j));
         if (n == NULL) {
-/*                      fputs("realloc error in lhash",stderr); */
             lh->error++;
+            lh->num_nodes--;
             lh->p = 0;
             return;
         }
diff --git a/crypto/openssl/crypto/md2/md2_dgst.c b/crypto/openssl/crypto/md2/md2_dgst.c
index 9cd79f8d70c3..7f5d9ba69ba2 100644
--- a/crypto/openssl/crypto/md2/md2_dgst.c
+++ b/crypto/openssl/crypto/md2/md2_dgst.c
@@ -219,6 +219,6 @@ int MD2_Final(unsigned char *md, MD2_CTX *c)
 
     for (i = 0; i < 16; i++)
         md[i] = (UCHAR) (p1[i] & 0xff);
-    memset((char *)&c, 0, sizeof(c));
+    OPENSSL_cleanse(c, sizeof(*c));
     return 1;
 }
diff --git a/crypto/openssl/crypto/md32_common.h b/crypto/openssl/crypto/md32_common.h
index 96828d2693a1..b5a04bf133bd 100644
--- a/crypto/openssl/crypto/md32_common.h
+++ b/crypto/openssl/crypto/md32_common.h
@@ -109,6 +109,8 @@
  *                                      <appro@fy.chalmers.se>
  */
 
+#include <openssl/crypto.h>
+
 #if !defined(DATA_ORDER_IS_BIG_ENDIAN) && !defined(DATA_ORDER_IS_LITTLE_ENDIAN)
 # error "DATA_ORDER must be defined!"
 #endif
@@ -329,6 +331,12 @@ int HASH_UPDATE(HASH_CTX *c, const void *data_, size_t len)
             data += n;
             len -= n;
             c->num = 0;
+            /*
+             * We use memset rather than OPENSSL_cleanse() here deliberately.
+             * Using OPENSSL_cleanse() here could be a performance issue. It
+             * will get properly cleansed on finalisation so this isn't a
+             * security problem.
+             */
             memset(p, 0, HASH_CBLOCK); /* keep it zeroed */
         } else {
             memcpy(p + n, data, len);
@@ -384,7 +392,7 @@ int HASH_FINAL(unsigned char *md, HASH_CTX *c)
     p -= HASH_CBLOCK;
     HASH_BLOCK_DATA_ORDER(c, p, 1);
     c->num = 0;
-    memset(p, 0, HASH_CBLOCK);
+    OPENSSL_cleanse(p, HASH_CBLOCK);
 
 #ifndef HASH_MAKE_STRING
 # error "HASH_MAKE_STRING must be defined!"
diff --git a/crypto/openssl/crypto/mdc2/mdc2dgst.c b/crypto/openssl/crypto/mdc2/mdc2dgst.c
index 6615cf84d7d2..2dce4936337a 100644
--- a/crypto/openssl/crypto/mdc2/mdc2dgst.c
+++ b/crypto/openssl/crypto/mdc2/mdc2dgst.c
@@ -91,7 +91,7 @@ int MDC2_Update(MDC2_CTX *c, const unsigned char *in, size_t len)
 
     i = c->num;
     if (i != 0) {
-        if (i + len < MDC2_BLOCK) {
+        if (len < MDC2_BLOCK - i) {
             /* partial block */
             memcpy(&(c->data[i]), in, len);
             c->num += (int)len;
diff --git a/crypto/openssl/crypto/mem.c b/crypto/openssl/crypto/mem.c
index fdad49b76ec0..06c3960cc6c0 100644
--- a/crypto/openssl/crypto/mem.c
+++ b/crypto/openssl/crypto/mem.c
@@ -82,6 +82,14 @@ static void *default_malloc_ex(size_t num, const char *file, int line)
 static void *(*malloc_ex_func) (size_t, const char *file, int line)
     = default_malloc_ex;
 
+#ifdef OPENSSL_SYS_VMS
+# if __INITIAL_POINTER_SIZE == 64
+#  define realloc _realloc64
+# elif __INITIAL_POINTER_SIZE == 32
+#  define realloc _realloc32
+# endif
+#endif
+
 static void *(*realloc_func) (void *, size_t) = realloc;
 static void *default_realloc_ex(void *str, size_t num,
                                 const char *file, int line)
@@ -92,7 +100,11 @@ static void *default_realloc_ex(void *str, size_t num,
 static void *(*realloc_ex_func) (void *, size_t, const char *file, int line)
     = default_realloc_ex;
 
-static void (*free_func) (void *) = free;
+#ifdef OPENSSL_SYS_VMS
+   static void (*free_func) (__void_ptr64) = free;
+#else
+   static void (*free_func) (void *) = free;
+#endif
 
 static void *(*malloc_locked_func) (size_t) = malloc;
 static void *default_malloc_locked_ex(size_t num, const char *file, int line)
@@ -103,7 +115,11 @@ static void *default_malloc_locked_ex(size_t num, const char *file, int line)
 static void *(*malloc_locked_ex_func) (size_t, const char *file, int line)
     = default_malloc_locked_ex;
 
-static void (*free_locked_func) (void *) = free;
+#ifdef OPENSSL_SYS_VMS
+   static void (*free_locked_func) (__void_ptr64) = free;
+#else
+   static void (*free_locked_func) (void *) = free;
+#endif
 
 /* may be changed as long as 'allow_customize_debug' is set */
 /* XXX use correct function pointer types */
@@ -298,18 +314,6 @@ void *CRYPTO_malloc_locked(int num, const char *file, int line)
     if (malloc_debug_func != NULL)
         malloc_debug_func(ret, num, file, line, 1);
 
-#ifndef OPENSSL_CPUID_OBJ
-    /*
-     * Create a dependency on the value of 'cleanse_ctr' so our memory
-     * sanitisation function can't be optimised out. NB: We only do this for
-     * >2Kb so the overhead doesn't bother us.
-     */
-    if (ret && (num > 2048)) {
-        extern unsigned char cleanse_ctr;
-        ((unsigned char *)ret)[0] = cleanse_ctr;
-    }
-#endif
-
     return ret;
 }
 
@@ -346,18 +350,6 @@ void *CRYPTO_malloc(int num, const char *file, int line)
     if (malloc_debug_func != NULL)
         malloc_debug_func(ret, num, file, line, 1);
 
-#ifndef OPENSSL_CPUID_OBJ
-    /*
-     * Create a dependency on the value of 'cleanse_ctr' so our memory
-     * sanitisation function can't be optimised out. NB: We only do this for
-     * >2Kb so the overhead doesn't bother us.
-     */
-    if (ret && (num > 2048)) {
-        extern unsigned char cleanse_ctr;
-        ((unsigned char *)ret)[0] = cleanse_ctr;
-    }
-#endif
-
     return ret;
 }
 
diff --git a/crypto/openssl/crypto/mem_clr.c b/crypto/openssl/crypto/mem_clr.c
index ab85344eef38..579e9d18251d 100644
--- a/crypto/openssl/crypto/mem_clr.c
+++ b/crypto/openssl/crypto/mem_clr.c
@@ -60,22 +60,16 @@
 #include <string.h>
 #include <openssl/crypto.h>
 
-unsigned char cleanse_ctr = 0;
+/*
+ * Pointer to memset is volatile so that compiler must de-reference
+ * the pointer and can't assume that it points to any function in
+ * particular (such as memset, which it then might further "optimize")
+ */
+typedef void *(*memset_t)(void *,int,size_t);
+
+static volatile memset_t memset_func = memset;
 
 void OPENSSL_cleanse(void *ptr, size_t len)
 {
-    unsigned char *p = ptr;
-    size_t loop = len, ctr = cleanse_ctr;
-
-    if (ptr == NULL)
-        return;
-
-    while (loop--) {
-        *(p++) = (unsigned char)ctr;
-        ctr += (17 + ((size_t)p & 0xF));
-    }
-    p = memchr(ptr, (unsigned char)ctr, len);
-    if (p)
-        ctr += (63 + (size_t)p);
-    cleanse_ctr = (unsigned char)ctr;
+    memset_func(ptr, 0, len);
 }
diff --git a/crypto/openssl/crypto/modes/asm/ghash-sparcv9.pl b/crypto/openssl/crypto/modes/asm/ghash-sparcv9.pl
index 5bc28702019a..b129ba706f0f 100755
--- a/crypto/openssl/crypto/modes/asm/ghash-sparcv9.pl
+++ b/crypto/openssl/crypto/modes/asm/ghash-sparcv9.pl
@@ -445,6 +445,8 @@ gcm_gmult_vis3:
 .align	32
 gcm_ghash_vis3:
 	save	%sp,-$frame,%sp
+	nop
+	srln	$len,0,$len		! needed on v8+, "nop" on v9
 
 	ldx	[$Xip+8],$C2		! load Xi
 	ldx	[$Xip+0],$C3
diff --git a/crypto/openssl/crypto/o_init.c b/crypto/openssl/crypto/o_init.c
index 2088388128e6..185841ea048c 100644
--- a/crypto/openssl/crypto/o_init.c
+++ b/crypto/openssl/crypto/o_init.c
@@ -73,6 +73,9 @@ void OPENSSL_init(void)
     done = 1;
 #ifdef OPENSSL_FIPS
     FIPS_set_locking_callbacks(CRYPTO_lock, CRYPTO_add_lock);
+# ifndef OPENSSL_NO_DEPRECATED
+    FIPS_crypto_set_id_callback(CRYPTO_thread_id);
+# endif
     FIPS_set_error_callbacks(ERR_put_error, ERR_add_error_vdata);
     FIPS_set_malloc_callbacks(CRYPTO_malloc, CRYPTO_free);
     RAND_init_fips();
diff --git a/crypto/openssl/crypto/o_time.c b/crypto/openssl/crypto/o_time.c
index 635dae184d2f..b99e5990b4e4 100644
--- a/crypto/openssl/crypto/o_time.c
+++ b/crypto/openssl/crypto/o_time.c
@@ -78,7 +78,28 @@
 #  include <descrip.h>
 #  include <stdlib.h>
 # endif                         /* ndef VMS_GMTIME_OK */
-#endif
+
+
+/*
+ * Needed to pick up the correct definitions and declarations in some of the
+ * DEC C Header Files (*.H).
+ */
+# define __NEW_STARLET 1
+
+# if (defined(__alpha) || defined(__ia64))
+#  include <iledef.h>
+# else
+
+/* VAX */
+typedef struct _ile3 {          /* Copied from ILEDEF.H for Alpha   */
+#  pragma __nomember_alignment
+    unsigned short int ile3$w_length;        /* Length of buffer in bytes */
+    unsigned short int ile3$w_code;          /* Item code value */
+    void *ile3$ps_bufaddr;                   /* Buffer address */
+    unsigned short int *ile3$ps_retlen_addr; /* Address of word for returned length */
+} ILE3;
+# endif   /* alpha || ia64    */
+#endif    /* OPENSSL_SYS_VMS  */
 
 struct tm *OPENSSL_gmtime(const time_t *timer, struct tm *result)
 {
@@ -105,26 +126,42 @@ struct tm *OPENSSL_gmtime(const time_t *timer, struct tm *result)
         static $DESCRIPTOR(lognam, "SYS$TIMEZONE_DIFFERENTIAL");
         char logvalue[256];
         unsigned int reslen = 0;
-        struct {
-            short buflen;
-            short code;
-            void *bufaddr;
-            unsigned int *reslen;
-        } itemlist[] = {
-            {
-                0, LNM$_STRING, 0, 0
-            },
-            {
-                0, 0, 0, 0
-            },
-        };
+# if __INITIAL_POINTER_SIZE == 64
+        ILEB_64 itemlist[2], *pitem;
+# else
+        ILE3 itemlist[2], *pitem;
+# endif
         int status;
         time_t t;
 
+
+        /*
+         * Setup an itemlist for the call to $TRNLNM - Translate Logical Name.
+         */
+        pitem = itemlist;
+
+# if __INITIAL_POINTER_SIZE == 64
+        pitem->ileb_64$w_mbo = 1;
+        pitem->ileb_64$w_code = LNM$_STRING;
+        pitem->ileb_64$l_mbmo = -1;
+        pitem->ileb_64$q_length = sizeof (logvalue);
+        pitem->ileb_64$pq_bufaddr = logvalue;
+        pitem->ileb_64$pq_retlen_addr = (unsigned __int64 *) &reslen;
+        pitem++;
+        /* Last item of the item list is null terminated */
+        pitem->ileb_64$q_length = pitem->ileb_64$w_code = 0;
+# else
+        pitem->ile3$w_length = sizeof (logvalue);
+        pitem->ile3$w_code = LNM$_STRING;
+        pitem->ile3$ps_bufaddr = logvalue;
+        pitem->ile3$ps_retlen_addr = (unsigned short int *) &reslen;
+        pitem++;
+        /* Last item of the item list is null terminated */
+        pitem->ile3$w_length = pitem->ile3$w_code = 0;
+# endif
+
+
         /* Get the value for SYS$TIMEZONE_DIFFERENTIAL */
-        itemlist[0].buflen = sizeof(logvalue);
-        itemlist[0].bufaddr = logvalue;
-        itemlist[0].reslen = &reslen;
         status = sys$trnlnm(0, &tabnam, &lognam, 0, itemlist);
         if (!(status & 1))
             return NULL;
@@ -132,7 +169,7 @@ struct tm *OPENSSL_gmtime(const time_t *timer, struct tm *result)
 
         t = *timer;
 
-/* The following is extracted from the DEC C header time.h */
+        /* The following is extracted from the DEC C header time.h */
         /*
          **  Beginning in OpenVMS Version 7.0 mktime, time, ctime, strftime
          **  have two implementations.  One implementation is provided
diff --git a/crypto/openssl/crypto/objects/o_names.c b/crypto/openssl/crypto/objects/o_names.c
index 24859926ace6..f106905ffa77 100644
--- a/crypto/openssl/crypto/objects/o_names.c
+++ b/crypto/openssl/crypto/objects/o_names.c
@@ -191,7 +191,7 @@ int OBJ_NAME_add(const char *name, int type, const char *data)
     onp = (OBJ_NAME *)OPENSSL_malloc(sizeof(OBJ_NAME));
     if (onp == NULL) {
         /* ERROR */
-        return (0);
+        return 0;
     }
 
     onp->name = name;
@@ -216,10 +216,11 @@ int OBJ_NAME_add(const char *name, int type, const char *data)
     } else {
         if (lh_OBJ_NAME_error(names_lh)) {
             /* ERROR */
-            return (0);
+            OPENSSL_free(onp);
+            return 0;
         }
     }
-    return (1);
+    return 1;
 }
 
 int OBJ_NAME_remove(const char *name, int type)
diff --git a/crypto/openssl/crypto/ocsp/ocsp_cl.c b/crypto/openssl/crypto/ocsp/ocsp_cl.c
index b3612c8dfc79..fca7db0b71d6 100644
--- a/crypto/openssl/crypto/ocsp/ocsp_cl.c
+++ b/crypto/openssl/crypto/ocsp/ocsp_cl.c
@@ -93,8 +93,10 @@ OCSP_ONEREQ *OCSP_request_add0_id(OCSP_REQUEST *req, OCSP_CERTID *cid)
     if (one->reqCert)
         OCSP_CERTID_free(one->reqCert);
     one->reqCert = cid;
-    if (req && !sk_OCSP_ONEREQ_push(req->tbsRequest->requestList, one))
+    if (req && !sk_OCSP_ONEREQ_push(req->tbsRequest->requestList, one)) {
+        one->reqCert = NULL; /* do not free on error */
         goto err;
+    }
     return one;
  err:
     OCSP_ONEREQ_free(one);
diff --git a/crypto/openssl/crypto/ocsp/ocsp_ext.c b/crypto/openssl/crypto/ocsp/ocsp_ext.c
index c19648c7329b..55af31b5734a 100644
--- a/crypto/openssl/crypto/ocsp/ocsp_ext.c
+++ b/crypto/openssl/crypto/ocsp/ocsp_ext.c
@@ -361,7 +361,7 @@ static int ocsp_add1_nonce(STACK_OF(X509_EXTENSION) **exts,
     ASN1_put_object(&tmpval, 0, len, V_ASN1_OCTET_STRING, V_ASN1_UNIVERSAL);
     if (val)
         memcpy(tmpval, val, len);
-    else if (RAND_pseudo_bytes(tmpval, len) < 0)
+    else if (RAND_bytes(tmpval, len) <= 0)
         goto err;
     if (!X509V3_add1_i2d(exts, NID_id_pkix_OCSP_Nonce,
                          &os, 0, X509V3_ADD_REPLACE))
diff --git a/crypto/openssl/crypto/ocsp/ocsp_lib.c b/crypto/openssl/crypto/ocsp/ocsp_lib.c
index cabf53933a44..ff781e56e73e 100644
--- a/crypto/openssl/crypto/ocsp/ocsp_lib.c
+++ b/crypto/openssl/crypto/ocsp/ocsp_lib.c
@@ -271,12 +271,18 @@ int OCSP_parse_url(const char *url, char **phost, char **pport, char **ppath,
  err:
     if (buf)
         OPENSSL_free(buf);
-    if (*ppath)
+    if (*ppath) {
         OPENSSL_free(*ppath);
-    if (*pport)
+        *ppath = NULL;
+    }
+    if (*pport) {
         OPENSSL_free(*pport);
-    if (*phost)
+        *pport = NULL;
+    }
+    if (*phost) {
         OPENSSL_free(*phost);
+        *phost = NULL;
+    }
     return 0;
 
 }
diff --git a/crypto/openssl/crypto/opensslv.h b/crypto/openssl/crypto/opensslv.h
index 1a67712dedd6..fdc3116f5167 100644
--- a/crypto/openssl/crypto/opensslv.h
+++ b/crypto/openssl/crypto/opensslv.h
@@ -30,11 +30,11 @@ extern "C" {
  * (Prior to 0.9.5a beta1, a different scheme was used: MMNNFFRBB for
  *  major minor fix final patch/beta)
  */
-# define OPENSSL_VERSION_NUMBER  0x1000208fL
+# define OPENSSL_VERSION_NUMBER  0x1000209fL
 # ifdef OPENSSL_FIPS
-#  define OPENSSL_VERSION_TEXT    "OpenSSL 1.0.2h-fips  3 May 2016"
+#  define OPENSSL_VERSION_TEXT    "OpenSSL 1.0.2i-fips  22 Sep 2016"
 # else
-#  define OPENSSL_VERSION_TEXT    "OpenSSL 1.0.2h-freebsd  3 May 2016"
+#  define OPENSSL_VERSION_TEXT    "OpenSSL 1.0.2i-freebsd  22 Sep 2016"
 # endif
 # define OPENSSL_VERSION_PTEXT   " part of " OPENSSL_VERSION_TEXT
 
diff --git a/crypto/openssl/crypto/ossl_typ.h b/crypto/openssl/crypto/ossl_typ.h
index 9144ea2cf60b..364d26238e8c 100644
--- a/crypto/openssl/crypto/ossl_typ.h
+++ b/crypto/openssl/crypto/ossl_typ.h
@@ -178,6 +178,8 @@ typedef struct engine_st ENGINE;
 typedef struct ssl_st SSL;
 typedef struct ssl_ctx_st SSL_CTX;
 
+typedef struct comp_method_st COMP_METHOD;
+
 typedef struct X509_POLICY_NODE_st X509_POLICY_NODE;
 typedef struct X509_POLICY_LEVEL_st X509_POLICY_LEVEL;
 typedef struct X509_POLICY_TREE_st X509_POLICY_TREE;
diff --git a/crypto/openssl/crypto/pem/pem.h b/crypto/openssl/crypto/pem/pem.h
index d3b23fc997d6..aac72fb21eda 100644
--- a/crypto/openssl/crypto/pem/pem.h
+++ b/crypto/openssl/crypto/pem/pem.h
@@ -531,6 +531,7 @@ int i2b_PVK_bio(BIO *out, EVP_PKEY *pk, int enclevel,
  * The following lines are auto generated by the script mkerr.pl. Any changes
  * made after this point may be overwritten when the script is next run.
  */
+
 void ERR_load_PEM_strings(void);
 
 /* Error codes for the PEM functions. */
@@ -592,6 +593,7 @@ void ERR_load_PEM_strings(void);
 # define PEM_R_ERROR_CONVERTING_PRIVATE_KEY               115
 # define PEM_R_EXPECTING_PRIVATE_KEY_BLOB                 119
 # define PEM_R_EXPECTING_PUBLIC_KEY_BLOB                  120
+# define PEM_R_HEADER_TOO_LONG                            128
 # define PEM_R_INCONSISTENT_HEADER                        121
 # define PEM_R_KEYBLOB_HEADER_PARSE_ERROR                 122
 # define PEM_R_KEYBLOB_TOO_SHORT                          123
@@ -609,7 +611,7 @@ void ERR_load_PEM_strings(void);
 # define PEM_R_UNSUPPORTED_ENCRYPTION                     114
 # define PEM_R_UNSUPPORTED_KEY_COMPONENTS                 126
 
-#ifdef  __cplusplus
+# ifdef  __cplusplus
 }
-#endif
+# endif
 #endif
diff --git a/crypto/openssl/crypto/pem/pem_err.c b/crypto/openssl/crypto/pem/pem_err.c
index e1f4fdb432d0..4e5f8e936cd1 100644
--- a/crypto/openssl/crypto/pem/pem_err.c
+++ b/crypto/openssl/crypto/pem/pem_err.c
@@ -1,6 +1,6 @@
 /* crypto/pem/pem_err.c */
 /* ====================================================================
- * Copyright (c) 1999-2011 The OpenSSL Project.  All rights reserved.
+ * Copyright (c) 1999-2016 The OpenSSL Project.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -132,6 +132,7 @@ static ERR_STRING_DATA PEM_str_reasons[] = {
      "expecting private key blob"},
     {ERR_REASON(PEM_R_EXPECTING_PUBLIC_KEY_BLOB),
      "expecting public key blob"},
+    {ERR_REASON(PEM_R_HEADER_TOO_LONG), "header too long"},
     {ERR_REASON(PEM_R_INCONSISTENT_HEADER), "inconsistent header"},
     {ERR_REASON(PEM_R_KEYBLOB_HEADER_PARSE_ERROR),
      "keyblob header parse error"},
diff --git a/crypto/openssl/crypto/pem/pem_lib.c b/crypto/openssl/crypto/pem/pem_lib.c
index fe881d664171..c82b3c0ae263 100644
--- a/crypto/openssl/crypto/pem/pem_lib.c
+++ b/crypto/openssl/crypto/pem/pem_lib.c
@@ -105,17 +105,23 @@ int PEM_def_callback(char *buf, int num, int w, void *key)
         prompt = "Enter PEM pass phrase:";
 
     for (;;) {
-        i = EVP_read_pw_string_min(buf, MIN_LENGTH, num, prompt, w);
+        /*
+         * We assume that w == 0 means decryption,
+         * while w == 1 means encryption
+         */
+        int min_len = w ? MIN_LENGTH : 0;
+
+        i = EVP_read_pw_string_min(buf, min_len, num, prompt, w);
         if (i != 0) {
             PEMerr(PEM_F_PEM_DEF_CALLBACK, PEM_R_PROBLEMS_GETTING_PASSWORD);
             memset(buf, 0, (unsigned int)num);
             return (-1);
         }
         j = strlen(buf);
-        if (j < MIN_LENGTH) {
+        if (min_len && j < min_len) {
             fprintf(stderr,
                     "phrase is too short, needs to be at least %d chars\n",
-                    MIN_LENGTH);
+                    min_len);
         } else
             break;
     }
@@ -387,7 +393,7 @@ int PEM_ASN1_write_bio(i2d_of_void *i2d, const char *name, BIO *bp,
         }
         RAND_add(data, i, 0);   /* put in the RSA key. */
         OPENSSL_assert(enc->iv_len <= (int)sizeof(iv));
-        if (RAND_pseudo_bytes(iv, enc->iv_len) < 0) /* Generate a salt */
+        if (RAND_bytes(iv, enc->iv_len) <= 0) /* Generate a salt */
             goto err;
         /*
          * The 'iv' is used as the iv and as a salt.  It is NOT taken from
diff --git a/crypto/openssl/crypto/pem/pvkfmt.c b/crypto/openssl/crypto/pem/pvkfmt.c
index 61864468f6d4..1ce5a1e319c5 100644
--- a/crypto/openssl/crypto/pem/pvkfmt.c
+++ b/crypto/openssl/crypto/pem/pvkfmt.c
@@ -127,6 +127,9 @@ static int read_lebn(const unsigned char **in, unsigned int nbyte, BIGNUM **r)
 # define MS_KEYTYPE_KEYX         0x1
 # define MS_KEYTYPE_SIGN         0x2
 
+/* Maximum length of a blob after header */
+# define BLOB_MAX_LENGTH          102400
+
 /* The PVK file magic number: seems to spell out "bobsfile", who is Bob? */
 # define MS_PVKMAGIC             0xb0b5f11eL
 /* Salt length for PVK files */
@@ -272,6 +275,10 @@ static EVP_PKEY *do_b2i_bio(BIO *in, int ispub)
         return NULL;
 
     length = blob_length(bitlen, isdss, ispub);
+    if (length > BLOB_MAX_LENGTH) {
+        PEMerr(PEM_F_DO_B2I_BIO, PEM_R_HEADER_TOO_LONG);
+        return NULL;
+    }
     buf = OPENSSL_malloc(length);
     if (!buf) {
         PEMerr(PEM_F_DO_B2I_BIO, ERR_R_MALLOC_FAILURE);
diff --git a/crypto/openssl/crypto/perlasm/sparcv9_modes.pl b/crypto/openssl/crypto/perlasm/sparcv9_modes.pl
index eb267a57ed81..ac8da328b00e 100755
--- a/crypto/openssl/crypto/perlasm/sparcv9_modes.pl
+++ b/crypto/openssl/crypto/perlasm/sparcv9_modes.pl
@@ -37,6 +37,7 @@ ${alg}${bits}_t4_cbc_encrypt:
 	save		%sp, -$::frame, %sp
 	cmp		$len, 0
 	be,pn		$::size_t_cc, .L${bits}_cbc_enc_abort
+	srln		$len, 0, $len		! needed on v8+, "nop" on v9
 	sub		$inp, $out, $blk_init	! $inp!=$out
 ___
 $::code.=<<___ if (!$::evp);
@@ -254,6 +255,7 @@ ${alg}${bits}_t4_cbc_decrypt:
 	save		%sp, -$::frame, %sp
 	cmp		$len, 0
 	be,pn		$::size_t_cc, .L${bits}_cbc_dec_abort
+	srln		$len, 0, $len		! needed on v8+, "nop" on v9
 	sub		$inp, $out, $blk_init	! $inp!=$out
 ___
 $::code.=<<___ if (!$::evp);
@@ -613,6 +615,7 @@ $::code.=<<___;
 .align	32
 ${alg}${bits}_t4_ctr32_encrypt:
 	save		%sp, -$::frame, %sp
+	srln		$len, 0, $len		! needed on v8+, "nop" on v9
 
 	prefetch	[$inp], 20
 	prefetch	[$inp + 63], 20
@@ -916,6 +919,7 @@ $::code.=<<___;
 .align	32
 ${alg}${bits}_t4_xts_${dir}crypt:
 	save		%sp, -$::frame-16, %sp
+	srln		$len, 0, $len		! needed on v8+, "nop" on v9
 
 	mov		$ivec, %o0
 	add		%fp, $::bias-16, %o1
diff --git a/crypto/openssl/crypto/pkcs12/p12_mutl.c b/crypto/openssl/crypto/pkcs12/p12_mutl.c
index a9277827ff2d..cbf34da05ada 100644
--- a/crypto/openssl/crypto/pkcs12/p12_mutl.c
+++ b/crypto/openssl/crypto/pkcs12/p12_mutl.c
@@ -179,7 +179,7 @@ int PKCS12_setup_mac(PKCS12 *p12, int iter, unsigned char *salt, int saltlen,
     }
     p12->mac->salt->length = saltlen;
     if (!salt) {
-        if (RAND_pseudo_bytes(p12->mac->salt->data, saltlen) < 0)
+        if (RAND_bytes(p12->mac->salt->data, saltlen) <= 0)
             return 0;
     } else
         memcpy(p12->mac->salt->data, salt, saltlen);
diff --git a/crypto/openssl/crypto/pkcs12/p12_npas.c b/crypto/openssl/crypto/pkcs12/p12_npas.c
index a89b61abab37..9e8ebb2a78c3 100644
--- a/crypto/openssl/crypto/pkcs12/p12_npas.c
+++ b/crypto/openssl/crypto/pkcs12/p12_npas.c
@@ -66,17 +66,18 @@
 
 /* PKCS#12 password change routine */
 
-static int newpass_p12(PKCS12 *p12, char *oldpass, char *newpass);
-static int newpass_bags(STACK_OF(PKCS12_SAFEBAG) *bags, char *oldpass,
-                        char *newpass);
-static int newpass_bag(PKCS12_SAFEBAG *bag, char *oldpass, char *newpass);
+static int newpass_p12(PKCS12 *p12, const char *oldpass, const char *newpass);
+static int newpass_bags(STACK_OF(PKCS12_SAFEBAG) *bags, const char *oldpass,
+                        const char *newpass);
+static int newpass_bag(PKCS12_SAFEBAG *bag, const char *oldpass,
+                        const char *newpass);
 static int alg_get(X509_ALGOR *alg, int *pnid, int *piter, int *psaltlen);
 
 /*
  * Change the password on a PKCS#12 structure.
  */
 
-int PKCS12_newpass(PKCS12 *p12, char *oldpass, char *newpass)
+int PKCS12_newpass(PKCS12 *p12, const char *oldpass, const char *newpass)
 {
     /* Check for NULL PKCS12 structure */
 
@@ -103,20 +104,21 @@ int PKCS12_newpass(PKCS12 *p12, char *oldpass, char *newpass)
 
 /* Parse the outer PKCS#12 structure */
 
-static int newpass_p12(PKCS12 *p12, char *oldpass, char *newpass)
+static int newpass_p12(PKCS12 *p12, const char *oldpass, const char *newpass)
 {
-    STACK_OF(PKCS7) *asafes, *newsafes;
-    STACK_OF(PKCS12_SAFEBAG) *bags;
+    STACK_OF(PKCS7) *asafes = NULL, *newsafes = NULL;
+    STACK_OF(PKCS12_SAFEBAG) *bags = NULL;
     int i, bagnid, pbe_nid = 0, pbe_iter = 0, pbe_saltlen = 0;
     PKCS7 *p7, *p7new;
-    ASN1_OCTET_STRING *p12_data_tmp = NULL, *macnew = NULL;
+    ASN1_OCTET_STRING *p12_data_tmp = NULL;
     unsigned char mac[EVP_MAX_MD_SIZE];
     unsigned int maclen;
+    int rv = 0;
 
-    if (!(asafes = PKCS12_unpack_authsafes(p12)))
-        return 0;
-    if (!(newsafes = sk_PKCS7_new_null()))
-        return 0;
+    if ((asafes = PKCS12_unpack_authsafes(p12)) == NULL)
+        goto err;
+    if ((newsafes = sk_PKCS7_new_null()) == NULL)
+        goto err;
     for (i = 0; i < sk_PKCS7_num(asafes); i++) {
         p7 = sk_PKCS7_value(asafes, i);
         bagnid = OBJ_obj2nid(p7->type);
@@ -125,67 +127,57 @@ static int newpass_p12(PKCS12 *p12, char *oldpass, char *newpass)
         } else if (bagnid == NID_pkcs7_encrypted) {
             bags = PKCS12_unpack_p7encdata(p7, oldpass, -1);
             if (!alg_get(p7->d.encrypted->enc_data->algorithm,
-                         &pbe_nid, &pbe_iter, &pbe_saltlen)) {
-                sk_PKCS12_SAFEBAG_pop_free(bags, PKCS12_SAFEBAG_free);
-                bags = NULL;
-            }
-        } else
+                         &pbe_nid, &pbe_iter, &pbe_saltlen))
+                goto err;
+        } else {
             continue;
-        if (!bags) {
-            sk_PKCS7_pop_free(asafes, PKCS7_free);
-            return 0;
-        }
-        if (!newpass_bags(bags, oldpass, newpass)) {
-            sk_PKCS12_SAFEBAG_pop_free(bags, PKCS12_SAFEBAG_free);
-            sk_PKCS7_pop_free(asafes, PKCS7_free);
-            return 0;
         }
+        if (bags == NULL)
+            goto err;
+        if (!newpass_bags(bags, oldpass, newpass))
+            goto err;
         /* Repack bag in same form with new password */
         if (bagnid == NID_pkcs7_data)
             p7new = PKCS12_pack_p7data(bags);
         else
             p7new = PKCS12_pack_p7encdata(pbe_nid, newpass, -1, NULL,
                                           pbe_saltlen, pbe_iter, bags);
+        if (!p7new || !sk_PKCS7_push(newsafes, p7new))
+            goto err;
         sk_PKCS12_SAFEBAG_pop_free(bags, PKCS12_SAFEBAG_free);
-        if (!p7new) {
-            sk_PKCS7_pop_free(asafes, PKCS7_free);
-            return 0;
-        }
-        sk_PKCS7_push(newsafes, p7new);
+        bags = NULL;
     }
-    sk_PKCS7_pop_free(asafes, PKCS7_free);
 
     /* Repack safe: save old safe in case of error */
 
     p12_data_tmp = p12->authsafes->d.data;
-    if (!(p12->authsafes->d.data = ASN1_OCTET_STRING_new()))
-        goto saferr;
+    if ((p12->authsafes->d.data = ASN1_OCTET_STRING_new()) == NULL)
+        goto err;
     if (!PKCS12_pack_authsafes(p12, newsafes))
-        goto saferr;
-
+        goto err;
     if (!PKCS12_gen_mac(p12, newpass, -1, mac, &maclen))
-        goto saferr;
-    if (!(macnew = ASN1_OCTET_STRING_new()))
-        goto saferr;
-    if (!ASN1_OCTET_STRING_set(macnew, mac, maclen))
-        goto saferr;
-    ASN1_OCTET_STRING_free(p12->mac->dinfo->digest);
-    p12->mac->dinfo->digest = macnew;
-    ASN1_OCTET_STRING_free(p12_data_tmp);
-
-    return 1;
-
- saferr:
-    /* Restore old safe */
-    ASN1_OCTET_STRING_free(p12->authsafes->d.data);
-    ASN1_OCTET_STRING_free(macnew);
-    p12->authsafes->d.data = p12_data_tmp;
-    return 0;
-
+        goto err;
+    if (!ASN1_OCTET_STRING_set(p12->mac->dinfo->digest, mac, maclen))
+        goto err;
+
+    rv = 1;
+
+err:
+    /* Restore old safe if necessary */
+    if (rv == 1) {
+        ASN1_OCTET_STRING_free(p12_data_tmp);
+    } else if (p12_data_tmp != NULL) {
+        ASN1_OCTET_STRING_free(p12->authsafes->d.data);
+        p12->authsafes->d.data = p12_data_tmp;
+    }
+    sk_PKCS12_SAFEBAG_pop_free(bags, PKCS12_SAFEBAG_free);
+    sk_PKCS7_pop_free(asafes, PKCS7_free);
+    sk_PKCS7_pop_free(newsafes, PKCS7_free);
+    return rv;
 }
 
-static int newpass_bags(STACK_OF(PKCS12_SAFEBAG) *bags, char *oldpass,
-                        char *newpass)
+static int newpass_bags(STACK_OF(PKCS12_SAFEBAG) *bags, const char *oldpass,
+                        const char *newpass)
 {
     int i;
     for (i = 0; i < sk_PKCS12_SAFEBAG_num(bags); i++) {
@@ -197,7 +189,8 @@ static int newpass_bags(STACK_OF(PKCS12_SAFEBAG) *bags, char *oldpass,
 
 /* Change password of safebag: only needs handle shrouded keybags */
 
-static int newpass_bag(PKCS12_SAFEBAG *bag, char *oldpass, char *newpass)
+static int newpass_bag(PKCS12_SAFEBAG *bag, const char *oldpass,
+                       const char *newpass)
 {
     PKCS8_PRIV_KEY_INFO *p8;
     X509_SIG *p8new;
@@ -210,8 +203,10 @@ static int newpass_bag(PKCS12_SAFEBAG *bag, char *oldpass, char *newpass)
         return 0;
     if (!alg_get(bag->value.shkeybag->algor, &p8_nid, &p8_iter, &p8_saltlen))
         return 0;
-    if (!(p8new = PKCS8_encrypt(p8_nid, NULL, newpass, -1, NULL, p8_saltlen,
-                                p8_iter, p8)))
+    p8new = PKCS8_encrypt(p8_nid, NULL, newpass, -1, NULL, p8_saltlen,
+                          p8_iter, p8);
+    PKCS8_PRIV_KEY_INFO_free(p8);
+    if (p8new == NULL)
         return 0;
     X509_SIG_free(bag->value.shkeybag);
     bag->value.shkeybag = p8new;
diff --git a/crypto/openssl/crypto/pkcs12/p12_utl.c b/crypto/openssl/crypto/pkcs12/p12_utl.c
index a0b992eab66c..e466f762ffda 100644
--- a/crypto/openssl/crypto/pkcs12/p12_utl.c
+++ b/crypto/openssl/crypto/pkcs12/p12_utl.c
@@ -91,6 +91,10 @@ char *OPENSSL_uni2asc(unsigned char *uni, int unilen)
 {
     int asclen, i;
     char *asctmp;
+
+    /* string must contain an even number of bytes */
+    if (unilen & 1)
+        return NULL;
     asclen = unilen / 2;
     /* If no terminating zero allow for one */
     if (!unilen || uni[unilen - 1])
diff --git a/crypto/openssl/crypto/pkcs12/pkcs12.h b/crypto/openssl/crypto/pkcs12/pkcs12.h
index a39adf5eb52e..21f1f62b36c6 100644
--- a/crypto/openssl/crypto/pkcs12/pkcs12.h
+++ b/crypto/openssl/crypto/pkcs12/pkcs12.h
@@ -270,7 +270,7 @@ int i2d_PKCS12_bio(BIO *bp, PKCS12 *p12);
 int i2d_PKCS12_fp(FILE *fp, PKCS12 *p12);
 PKCS12 *d2i_PKCS12_bio(BIO *bp, PKCS12 **p12);
 PKCS12 *d2i_PKCS12_fp(FILE *fp, PKCS12 **p12);
-int PKCS12_newpass(PKCS12 *p12, char *oldpass, char *newpass);
+int PKCS12_newpass(PKCS12 *p12, const char *oldpass, const char *newpass);
 
 /* BEGIN ERROR CODES */
 /*
diff --git a/crypto/openssl/crypto/pkcs7/pk7_doit.c b/crypto/openssl/crypto/pkcs7/pk7_doit.c
index 946aaa65435b..6cf8253bc238 100644
--- a/crypto/openssl/crypto/pkcs7/pk7_doit.c
+++ b/crypto/openssl/crypto/pkcs7/pk7_doit.c
@@ -340,7 +340,7 @@ BIO *PKCS7_dataInit(PKCS7 *p7, BIO *bio)
         ivlen = EVP_CIPHER_iv_length(evp_cipher);
         xalg->algorithm = OBJ_nid2obj(EVP_CIPHER_type(evp_cipher));
         if (ivlen > 0)
-            if (RAND_pseudo_bytes(iv, ivlen) <= 0)
+            if (RAND_bytes(iv, ivlen) <= 0)
                 goto err;
         if (EVP_CipherInit_ex(ctx, evp_cipher, NULL, NULL, NULL, 1) <= 0)
             goto err;
@@ -642,6 +642,8 @@ BIO *PKCS7_dataDecode(PKCS7 *p7, EVP_PKEY *pkey, BIO *in_bio, X509 *pcert)
     } else {
 # if 0
         bio = BIO_new(BIO_s_mem());
+        if (bio == NULL)
+            goto err;
         /*
          * We need to set this so that when we have read all the data, the
          * encrypt BIO, if present, will read EOF and encode the last few
diff --git a/crypto/openssl/crypto/rand/md_rand.c b/crypto/openssl/crypto/rand/md_rand.c
index 5c13d57765b0..bd76e23e3deb 100644
--- a/crypto/openssl/crypto/rand/md_rand.c
+++ b/crypto/openssl/crypto/rand/md_rand.c
@@ -136,7 +136,7 @@
 /* #define PREDICT      1 */
 
 #define STATE_SIZE      1023
-static int state_num = 0, state_index = 0;
+static size_t state_num = 0, state_index = 0;
 static unsigned char state[STATE_SIZE + MD_DIGEST_LENGTH];
 static unsigned char md[MD_DIGEST_LENGTH];
 static long md_count[2] = { 0, 0 };
@@ -336,8 +336,8 @@ static void ssleay_rand_seed(const void *buf, int num)
 int ssleay_rand_bytes(unsigned char *buf, int num, int pseudo, int lock)
 {
     static volatile int stirred_pool = 0;
-    int i, j, k, st_num, st_idx;
-    int num_ceil;
+    int i, j, k;
+    size_t num_ceil, st_idx, st_num;
     int ok;
     long md_c[2];
     unsigned char local_md[MD_DIGEST_LENGTH];
diff --git a/crypto/openssl/crypto/rand/rand_unix.c b/crypto/openssl/crypto/rand/rand_unix.c
index bc3f80928224..f51b52f1088f 100644
--- a/crypto/openssl/crypto/rand/rand_unix.c
+++ b/crypto/openssl/crypto/rand/rand_unix.c
@@ -235,7 +235,7 @@ int RAND_poll(void)
         rnd >>= 8;
     }
     RAND_add(buf, sizeof(buf), ENTROPY_NEEDED);
-    memset(buf, 0, sizeof(buf));
+    OPENSSL_cleanse(buf, sizeof(buf));
 
     return 1;
 }
diff --git a/crypto/openssl/crypto/rand/randfile.c b/crypto/openssl/crypto/rand/randfile.c
index 9537c56a7895..728fd0a721b5 100644
--- a/crypto/openssl/crypto/rand/randfile.c
+++ b/crypto/openssl/crypto/rand/randfile.c
@@ -56,11 +56,6 @@
  * [including the GNU Public Licence.]
  */
 
-/* We need to define this to get macros like S_IFBLK and S_IFCHR */
-#if !defined(OPENSSL_SYS_VXWORKS)
-# define _XOPEN_SOURCE 500
-#endif
-
 #include <errno.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -80,6 +75,29 @@
 #ifndef OPENSSL_NO_POSIX_IO
 # include <sys/stat.h>
 # include <fcntl.h>
+/*
+ * Following should not be needed, and we could have been stricter
+ * and demand S_IS*. But some systems just don't comply... Formally
+ * below macros are "anatomically incorrect", because normally they
+ * would look like ((m) & MASK == TYPE), but since MASK availability
+ * is as questionable, we settle for this poor-man fallback...
+ */
+# if !defined(S_ISBLK)
+#  if defined(_S_IFBLK)
+#   define S_ISBLK(m) ((m) & _S_IFBLK)
+#  elif defined(S_IFBLK)
+#   define S_ISBLK(m) ((m) & S_IFBLK)
+#  elif defined(_WIN32)
+#   define S_ISBLK(m) 0 /* no concept of block devices on Windows */
+#  endif
+# endif
+# if !defined(S_ISCHR)
+#  if defined(_S_IFCHR)
+#   define S_ISCHR(m) ((m) & _S_IFCHR)
+#  elif defined(S_IFCHR)
+#   define S_ISCHR(m) ((m) & S_IFCHR)
+#  endif
+# endif
 #endif
 
 #ifdef _WIN32
@@ -93,7 +111,7 @@
 #define BUFSIZE 1024
 #define RAND_DATA 1024
 
-#ifdef OPENSSL_SYS_VMS
+#if (defined(OPENSSL_SYS_VMS) && (defined(__alpha) || defined(__ia64)))
 /*
  * This declaration is a nasty hack to get around vms' extension to fopen for
  * passing in sharing options being disabled by our /STANDARD=ANSI89
@@ -122,7 +140,24 @@ int RAND_load_file(const char *file, long bytes)
     struct stat sb;
 #endif
     int i, ret = 0, n;
+/*
+ * If setvbuf() is to be called, then the FILE pointer
+ * to it must be 32 bit.
+*/
+
+#if !defined OPENSSL_NO_SETVBUF_IONBF && defined(OPENSSL_SYS_VMS) && defined(__VMS_VER) && (__VMS_VER >= 70000000)
+    /* For 64-bit-->32 bit API Support*/
+#if __INITIAL_POINTER_SIZE == 64
+#pragma __required_pointer_size __save
+#pragma __required_pointer_size 32
+#endif
+    FILE *in; /* setvbuf() requires 32-bit pointers */
+#if __INITIAL_POINTER_SIZE == 64
+#pragma __required_pointer_size __restore
+#endif
+#else
     FILE *in;
+#endif /* OPENSSL_SYS_VMS */
 
     if (file == NULL)
         return (0);
@@ -151,8 +186,8 @@ int RAND_load_file(const char *file, long bytes)
 #endif
     if (in == NULL)
         goto err;
-#if defined(S_IFBLK) && defined(S_IFCHR) && !defined(OPENSSL_NO_POSIX_IO)
-    if (sb.st_mode & (S_IFBLK | S_IFCHR)) {
+#if defined(S_ISBLK) && defined(S_ISCHR) && !defined(OPENSSL_NO_POSIX_IO)
+    if (S_ISBLK(sb.st_mode) || S_ISCHR(sb.st_mode)) {
         /*
          * this file is a device. we don't want read an infinite number of
          * bytes from a random device, nor do we want to use buffered I/O
@@ -231,7 +266,7 @@ int RAND_write_file(const char *file)
     }
 #endif
 
-#ifdef OPENSSL_SYS_VMS
+#if (defined(OPENSSL_SYS_VMS) && (defined(__alpha) || defined(__ia64)))
     /*
      * VMS NOTE: Prior versions of this routine created a _new_ version of
      * the rand file for each call into this routine, then deleted all
diff --git a/crypto/openssl/crypto/rsa/rsa_ameth.c b/crypto/openssl/crypto/rsa/rsa_ameth.c
index 4e0621827cf3..951e1d5ca32b 100644
--- a/crypto/openssl/crypto/rsa/rsa_ameth.c
+++ b/crypto/openssl/crypto/rsa/rsa_ameth.c
@@ -68,10 +68,12 @@
 #endif
 #include "asn1_locl.h"
 
+#ifndef OPENSSL_NO_CMS
 static int rsa_cms_sign(CMS_SignerInfo *si);
 static int rsa_cms_verify(CMS_SignerInfo *si);
 static int rsa_cms_decrypt(CMS_RecipientInfo *ri);
 static int rsa_cms_encrypt(CMS_RecipientInfo *ri);
+#endif
 
 static int rsa_pub_encode(X509_PUBKEY *pk, const EVP_PKEY *pkey)
 {
@@ -665,6 +667,7 @@ static int rsa_pss_to_ctx(EVP_MD_CTX *ctx, EVP_PKEY_CTX *pkctx,
     return rv;
 }
 
+#ifndef OPENSSL_NO_CMS
 static int rsa_cms_verify(CMS_SignerInfo *si)
 {
     int nid, nid2;
@@ -683,6 +686,7 @@ static int rsa_cms_verify(CMS_SignerInfo *si)
     }
     return 0;
 }
+#endif
 
 /*
  * Customised RSA item verification routine. This is called when a signature
@@ -705,6 +709,7 @@ static int rsa_item_verify(EVP_MD_CTX *ctx, const ASN1_ITEM *it, void *asn,
     return -1;
 }
 
+#ifndef OPENSSL_NO_CMS
 static int rsa_cms_sign(CMS_SignerInfo *si)
 {
     int pad_mode = RSA_PKCS1_PADDING;
@@ -729,6 +734,7 @@ static int rsa_cms_sign(CMS_SignerInfo *si)
     X509_ALGOR_set0(alg, OBJ_nid2obj(NID_rsassaPss), V_ASN1_SEQUENCE, os);
     return 1;
 }
+#endif
 
 static int rsa_item_sign(EVP_MD_CTX *ctx, const ASN1_ITEM *it, void *asn,
                          X509_ALGOR *alg1, X509_ALGOR *alg2,
@@ -785,6 +791,7 @@ static RSA_OAEP_PARAMS *rsa_oaep_decode(const X509_ALGOR *alg,
     return pss;
 }
 
+#ifndef OPENSSL_NO_CMS
 static int rsa_cms_decrypt(CMS_RecipientInfo *ri)
 {
     EVP_PKEY_CTX *pkctx;
@@ -920,6 +927,7 @@ static int rsa_cms_encrypt(CMS_RecipientInfo *ri)
         ASN1_STRING_free(os);
     return rv;
 }
+#endif
 
 const EVP_PKEY_ASN1_METHOD rsa_asn1_meths[] = {
     {
diff --git a/crypto/openssl/crypto/rsa/rsa_chk.c b/crypto/openssl/crypto/rsa/rsa_chk.c
index 607faa00171e..475dfc56289a 100644
--- a/crypto/openssl/crypto/rsa/rsa_chk.c
+++ b/crypto/openssl/crypto/rsa/rsa_chk.c
@@ -56,7 +56,6 @@ int RSA_check_key(const RSA *key)
 {
     BIGNUM *i, *j, *k, *l, *m;
     BN_CTX *ctx;
-    int r;
     int ret = 1;
 
     if (!key->p || !key->q || !key->n || !key->e || !key->d) {
@@ -70,75 +69,68 @@ int RSA_check_key(const RSA *key)
     l = BN_new();
     m = BN_new();
     ctx = BN_CTX_new();
-    if (i == NULL || j == NULL || k == NULL || l == NULL ||
-        m == NULL || ctx == NULL) {
+    if (i == NULL || j == NULL || k == NULL || l == NULL
+            || m == NULL || ctx == NULL) {
         ret = -1;
         RSAerr(RSA_F_RSA_CHECK_KEY, ERR_R_MALLOC_FAILURE);
         goto err;
     }
 
+    if (BN_is_one(key->e)) {
+        ret = 0;
+        RSAerr(RSA_F_RSA_CHECK_KEY, RSA_R_BAD_E_VALUE);
+    }
+    if (!BN_is_odd(key->e)) {
+        ret = 0;
+        RSAerr(RSA_F_RSA_CHECK_KEY, RSA_R_BAD_E_VALUE);
+    }
+
     /* p prime? */
-    r = BN_is_prime_ex(key->p, BN_prime_checks, NULL, NULL);
-    if (r != 1) {
-        ret = r;
-        if (r != 0)
-            goto err;
+    if (BN_is_prime_ex(key->p, BN_prime_checks, NULL, NULL) != 1) {
+        ret = 0;
         RSAerr(RSA_F_RSA_CHECK_KEY, RSA_R_P_NOT_PRIME);
     }
 
     /* q prime? */
-    r = BN_is_prime_ex(key->q, BN_prime_checks, NULL, NULL);
-    if (r != 1) {
-        ret = r;
-        if (r != 0)
-            goto err;
+    if (BN_is_prime_ex(key->q, BN_prime_checks, NULL, NULL) != 1) {
+        ret = 0;
         RSAerr(RSA_F_RSA_CHECK_KEY, RSA_R_Q_NOT_PRIME);
     }
 
     /* n = p*q? */
-    r = BN_mul(i, key->p, key->q, ctx);
-    if (!r) {
+    if (!BN_mul(i, key->p, key->q, ctx)) {
         ret = -1;
         goto err;
     }
-
     if (BN_cmp(i, key->n) != 0) {
         ret = 0;
         RSAerr(RSA_F_RSA_CHECK_KEY, RSA_R_N_DOES_NOT_EQUAL_P_Q);
     }
 
     /* d*e = 1  mod lcm(p-1,q-1)? */
-
-    r = BN_sub(i, key->p, BN_value_one());
-    if (!r) {
+    if (!BN_sub(i, key->p, BN_value_one())) {
         ret = -1;
         goto err;
     }
-    r = BN_sub(j, key->q, BN_value_one());
-    if (!r) {
+    if (!BN_sub(j, key->q, BN_value_one())) {
         ret = -1;
         goto err;
     }
 
     /* now compute k = lcm(i,j) */
-    r = BN_mul(l, i, j, ctx);
-    if (!r) {
+    if (!BN_mul(l, i, j, ctx)) {
         ret = -1;
         goto err;
     }
-    r = BN_gcd(m, i, j, ctx);
-    if (!r) {
+    if (!BN_gcd(m, i, j, ctx)) {
         ret = -1;
         goto err;
     }
-    r = BN_div(k, NULL, l, m, ctx); /* remainder is 0 */
-    if (!r) {
+    if (!BN_div(k, NULL, l, m, ctx)) { /* remainder is 0 */
         ret = -1;
         goto err;
     }
-
-    r = BN_mod_mul(i, key->d, key->e, k, ctx);
-    if (!r) {
+    if (!BN_mod_mul(i, key->d, key->e, k, ctx)) {
         ret = -1;
         goto err;
     }
@@ -150,36 +142,28 @@ int RSA_check_key(const RSA *key)
 
     if (key->dmp1 != NULL && key->dmq1 != NULL && key->iqmp != NULL) {
         /* dmp1 = d mod (p-1)? */
-        r = BN_sub(i, key->p, BN_value_one());
-        if (!r) {
+        if (!BN_sub(i, key->p, BN_value_one())) {
             ret = -1;
             goto err;
         }
-
-        r = BN_mod(j, key->d, i, ctx);
-        if (!r) {
+        if (!BN_mod(j, key->d, i, ctx)) {
             ret = -1;
             goto err;
         }
-
         if (BN_cmp(j, key->dmp1) != 0) {
             ret = 0;
             RSAerr(RSA_F_RSA_CHECK_KEY, RSA_R_DMP1_NOT_CONGRUENT_TO_D);
         }
 
         /* dmq1 = d mod (q-1)? */
-        r = BN_sub(i, key->q, BN_value_one());
-        if (!r) {
+        if (!BN_sub(i, key->q, BN_value_one())) {
             ret = -1;
             goto err;
         }
-
-        r = BN_mod(j, key->d, i, ctx);
-        if (!r) {
+        if (!BN_mod(j, key->d, i, ctx)) {
             ret = -1;
             goto err;
         }
-
         if (BN_cmp(j, key->dmq1) != 0) {
             ret = 0;
             RSAerr(RSA_F_RSA_CHECK_KEY, RSA_R_DMQ1_NOT_CONGRUENT_TO_D);
@@ -190,7 +174,6 @@ int RSA_check_key(const RSA *key)
             ret = -1;
             goto err;
         }
-
         if (BN_cmp(i, key->iqmp) != 0) {
             ret = 0;
             RSAerr(RSA_F_RSA_CHECK_KEY, RSA_R_IQMP_NOT_INVERSE_OF_Q);
@@ -198,17 +181,11 @@ int RSA_check_key(const RSA *key)
     }
 
  err:
-    if (i != NULL)
-        BN_free(i);
-    if (j != NULL)
-        BN_free(j);
-    if (k != NULL)
-        BN_free(k);
-    if (l != NULL)
-        BN_free(l);
-    if (m != NULL)
-        BN_free(m);
-    if (ctx != NULL)
-        BN_CTX_free(ctx);
-    return (ret);
+    BN_free(i);
+    BN_free(j);
+    BN_free(k);
+    BN_free(l);
+    BN_free(m);
+    BN_CTX_free(ctx);
+    return ret;
 }
diff --git a/crypto/openssl/crypto/rsa/rsa_lib.c b/crypto/openssl/crypto/rsa/rsa_lib.c
index a6805debc890..6ea6b40dc6fd 100644
--- a/crypto/openssl/crypto/rsa/rsa_lib.c
+++ b/crypto/openssl/crypto/rsa/rsa_lib.c
@@ -143,6 +143,7 @@ RSA *RSA_new_method(ENGINE *engine)
         RSAerr(RSA_F_RSA_NEW_METHOD, ERR_R_MALLOC_FAILURE);
         return NULL;
     }
+    memset(ret,0,sizeof(RSA));
 
     ret->meth = RSA_get_default_method();
 #ifndef OPENSSL_NO_ENGINE
diff --git a/crypto/openssl/crypto/rsa/rsa_pmeth.c b/crypto/openssl/crypto/rsa/rsa_pmeth.c
index 203635595f4c..94db87a0637d 100644
--- a/crypto/openssl/crypto/rsa/rsa_pmeth.c
+++ b/crypto/openssl/crypto/rsa/rsa_pmeth.c
@@ -545,8 +545,10 @@ static int pkey_rsa_ctrl(EVP_PKEY_CTX *ctx, int type, int p1, void *p2)
         return 1;
 
     case EVP_PKEY_CTRL_RSA_KEYGEN_PUBEXP:
-        if (!p2)
+        if (p2 == NULL || !BN_is_odd((BIGNUM *)p2) || BN_is_one((BIGNUM *)p2)) {
+            RSAerr(RSA_F_PKEY_RSA_CTRL, RSA_R_BAD_E_VALUE);
             return -2;
+        }
         BN_free(rctx->pub_exp);
         rctx->pub_exp = p2;
         return 1;
diff --git a/crypto/openssl/crypto/sha/asm/sha1-x86_64.pl b/crypto/openssl/crypto/sha/asm/sha1-x86_64.pl
index 5f375fc6886b..752138b0eac1 100755
--- a/crypto/openssl/crypto/sha/asm/sha1-x86_64.pl
+++ b/crypto/openssl/crypto/sha/asm/sha1-x86_64.pl
@@ -372,9 +372,9 @@ $code.=<<___;
 .align	16
 .Loop_shaext:
 	dec		$num
-	lea		0x40($inp),%rax		# next input block
+	lea		0x40($inp),%r8		# next input block
 	paddd		@MSG[0],$E
-	cmovne		%rax,$inp
+	cmovne		%r8,$inp
 	movdqa		$ABCD,$ABCD_SAVE	# offload $ABCD
 ___
 for($i=0;$i<20-4;$i+=2) {
diff --git a/crypto/openssl/crypto/sparccpuid.S b/crypto/openssl/crypto/sparccpuid.S
index 7b12ec293154..51ba441440bb 100644
--- a/crypto/openssl/crypto/sparccpuid.S
+++ b/crypto/openssl/crypto/sparccpuid.S
@@ -429,6 +429,7 @@ OPENSSL_cleanse:
 .size	OPENSSL_cleanse,.-OPENSSL_cleanse
 
 .global	_sparcv9_vis1_instrument_bus
+.weak	_sparcv9_vis1_instrument_bus
 .align	8
 _sparcv9_vis1_instrument_bus:
 	mov	%o1,%o3					! save cnt
@@ -467,6 +468,7 @@ _sparcv9_vis1_instrument_bus:
 .size	_sparcv9_vis1_instrument_bus,.-_sparcv9_vis1_instrument_bus
 
 .global	_sparcv9_vis1_instrument_bus2
+.weak	_sparcv9_vis1_instrument_bus2
 .align	8
 _sparcv9_vis1_instrument_bus2:
 	mov	%o1,%o3					! save cnt
diff --git a/crypto/openssl/crypto/srp/srp_lib.c b/crypto/openssl/crypto/srp/srp_lib.c
index e9a2e058f687..6df3b1cee72e 100644
--- a/crypto/openssl/crypto/srp/srp_lib.c
+++ b/crypto/openssl/crypto/srp/srp_lib.c
@@ -159,8 +159,7 @@ BIGNUM *SRP_Calc_server_key(BIGNUM *A, BIGNUM *v, BIGNUM *u, BIGNUM *b,
     if (u == NULL || A == NULL || v == NULL || b == NULL || N == NULL)
         return NULL;
 
-    if ((bn_ctx = BN_CTX_new()) == NULL ||
-        (tmp = BN_new()) == NULL || (S = BN_new()) == NULL)
+    if ((bn_ctx = BN_CTX_new()) == NULL || (tmp = BN_new()) == NULL)
         goto err;
 
     /* S = (A*v**u) ** b */
@@ -169,8 +168,12 @@ BIGNUM *SRP_Calc_server_key(BIGNUM *A, BIGNUM *v, BIGNUM *u, BIGNUM *b,
         goto err;
     if (!BN_mod_mul(tmp, A, tmp, N, bn_ctx))
         goto err;
-    if (!BN_mod_exp(S, tmp, b, N, bn_ctx))
-        goto err;
+
+    S = BN_new();
+    if (S != NULL && !BN_mod_exp(S, tmp, b, N, bn_ctx)) {
+        BN_free(S);
+        S = NULL;
+    }
  err:
     BN_CTX_free(bn_ctx);
     BN_clear_free(tmp);
@@ -267,7 +270,7 @@ BIGNUM *SRP_Calc_client_key(BIGNUM *N, BIGNUM *B, BIGNUM *g, BIGNUM *x,
 
     if ((tmp = BN_new()) == NULL ||
         (tmp2 = BN_new()) == NULL ||
-        (tmp3 = BN_new()) == NULL || (K = BN_new()) == NULL)
+        (tmp3 = BN_new()) == NULL)
         goto err;
 
     if (!BN_mod_exp(tmp, g, x, N, bn_ctx))
@@ -279,12 +282,15 @@ BIGNUM *SRP_Calc_client_key(BIGNUM *N, BIGNUM *B, BIGNUM *g, BIGNUM *x,
     if (!BN_mod_sub(tmp, B, tmp2, N, bn_ctx))
         goto err;
 
-    if (!BN_mod_mul(tmp3, u, x, N, bn_ctx))
+    if (!BN_mul(tmp3, u, x, bn_ctx))
         goto err;
-    if (!BN_mod_add(tmp2, a, tmp3, N, bn_ctx))
-        goto err;
-    if (!BN_mod_exp(K, tmp, tmp2, N, bn_ctx))
+    if (!BN_add(tmp2, a, tmp3))
         goto err;
+    K = BN_new();
+    if (K != NULL && !BN_mod_exp(K, tmp, tmp2, N, bn_ctx)) {
+        BN_free(K);
+        K = NULL;
+    }
 
  err:
     BN_CTX_free(bn_ctx);
diff --git a/crypto/openssl/crypto/srp/srp_vfy.c b/crypto/openssl/crypto/srp/srp_vfy.c
index 26ad3e07b4bb..a8ec52a4dadc 100644
--- a/crypto/openssl/crypto/srp/srp_vfy.c
+++ b/crypto/openssl/crypto/srp/srp_vfy.c
@@ -80,7 +80,7 @@ static char b64table[] =
 /*
  * Convert a base64 string into raw byte array representation.
  */
-static int t_fromb64(unsigned char *a, const char *src)
+static int t_fromb64(unsigned char *a, size_t alen, const char *src)
 {
     char *loc;
     int i, j;
@@ -89,6 +89,9 @@ static int t_fromb64(unsigned char *a, const char *src)
     while (*src && (*src == ' ' || *src == '\t' || *src == '\n'))
         ++src;
     size = strlen(src);
+    if (alen > INT_MAX || size > (int)alen)
+        return -1;
+
     i = 0;
     while (i < size) {
         loc = strchr(b64table, src[i]);
@@ -231,13 +234,25 @@ static int SRP_user_pwd_set_sv(SRP_user_pwd *vinfo, const char *s,
     unsigned char tmp[MAX_LEN];
     int len;
 
-    if (strlen(s) > MAX_LEN || strlen(v) > MAX_LEN)
+    vinfo->v = NULL;
+    vinfo->s = NULL;
+
+    len = t_fromb64(tmp, sizeof(tmp), v);
+    if (len < 0)
         return 0;
-    len = t_fromb64(tmp, v);
     if (NULL == (vinfo->v = BN_bin2bn(tmp, len, NULL)))
         return 0;
-    len = t_fromb64(tmp, s);
-    return ((vinfo->s = BN_bin2bn(tmp, len, NULL)) != NULL);
+    len = t_fromb64(tmp, sizeof(tmp), s);
+    if (len < 0)
+        goto err;
+    vinfo->s = BN_bin2bn(tmp, len, NULL);
+    if (vinfo->s == NULL)
+        goto err;
+    return 1;
+ err:
+    BN_free(vinfo->v);
+    vinfo->v = NULL;
+    return 0;
 }
 
 static int SRP_user_pwd_set_sv_BN(SRP_user_pwd *vinfo, BIGNUM *s, BIGNUM *v)
@@ -307,10 +322,13 @@ static SRP_gN_cache *SRP_gN_new_init(const char *ch)
     if (newgN == NULL)
         return NULL;
 
+    len = t_fromb64(tmp, sizeof(tmp), ch);
+    if (len < 0)
+        goto err;
+
     if ((newgN->b64_bn = BUF_strdup(ch)) == NULL)
         goto err;
 
-    len = t_fromb64(tmp, ch);
     if ((newgN->bn = BN_bin2bn(tmp, len, NULL)))
         return newgN;
 
@@ -544,7 +562,7 @@ SRP_user_pwd *SRP_VBASE_get1_by_user(SRP_VBASE *vb, char *username)
     if (!SRP_user_pwd_set_ids(user, username, NULL))
         goto err;
 
-    if (RAND_pseudo_bytes(digv, SHA_DIGEST_LENGTH) < 0)
+    if (RAND_bytes(digv, SHA_DIGEST_LENGTH) <= 0)
         goto err;
     EVP_MD_CTX_init(&ctxt);
     EVP_DigestInit_ex(&ctxt, EVP_sha1(), NULL);
@@ -580,10 +598,10 @@ char *SRP_create_verifier(const char *user, const char *pass, char **salt,
         goto err;
 
     if (N) {
-        if (!(len = t_fromb64(tmp, N)))
+        if (!(len = t_fromb64(tmp, sizeof(tmp), N)))
             goto err;
         N_bn = BN_bin2bn(tmp, len, NULL);
-        if (!(len = t_fromb64(tmp, g)))
+        if (!(len = t_fromb64(tmp, sizeof(tmp), g)))
             goto err;
         g_bn = BN_bin2bn(tmp, len, NULL);
         defgNid = "*";
@@ -597,12 +615,12 @@ char *SRP_create_verifier(const char *user, const char *pass, char **salt,
     }
 
     if (*salt == NULL) {
-        if (RAND_pseudo_bytes(tmp2, SRP_RANDOM_SALT_LEN) < 0)
+        if (RAND_bytes(tmp2, SRP_RANDOM_SALT_LEN) <= 0)
             goto err;
 
         s = BN_bin2bn(tmp2, SRP_RANDOM_SALT_LEN, NULL);
     } else {
-        if (!(len = t_fromb64(tmp2, *salt)))
+        if (!(len = t_fromb64(tmp2, sizeof(tmp2), *salt)))
             goto err;
         s = BN_bin2bn(tmp2, len, NULL);
     }
@@ -635,7 +653,8 @@ char *SRP_create_verifier(const char *user, const char *pass, char **salt,
         BN_free(N_bn);
         BN_free(g_bn);
     }
-    OPENSSL_cleanse(vf, vfsize);
+    if (vf != NULL)
+        OPENSSL_cleanse(vf, vfsize);
     OPENSSL_free(vf);
     BN_clear_free(s);
     BN_clear_free(v);
@@ -670,7 +689,7 @@ int SRP_create_verifier_BN(const char *user, const char *pass, BIGNUM **salt,
     srp_bn_print(g);
 
     if (*salt == NULL) {
-        if (RAND_pseudo_bytes(tmp2, SRP_RANDOM_SALT_LEN) < 0)
+        if (RAND_bytes(tmp2, SRP_RANDOM_SALT_LEN) <= 0)
             goto err;
 
         salttmp = BN_bin2bn(tmp2, SRP_RANDOM_SALT_LEN, NULL);
diff --git a/crypto/openssl/crypto/ts/ts.h b/crypto/openssl/crypto/ts/ts.h
index 16eccbb38d95..2daa1b2fb594 100644
--- a/crypto/openssl/crypto/ts/ts.h
+++ b/crypto/openssl/crypto/ts/ts.h
@@ -565,6 +565,9 @@ int TS_RESP_CTX_set_clock_precision_digits(TS_RESP_CTX *ctx,
 /* At most we accept usec precision. */
 # define TS_MAX_CLOCK_PRECISION_DIGITS   6
 
+/* Maximum status message length */
+# define TS_MAX_STATUS_LENGTH   (1024 * 1024)
+
 /* No flags are set by default. */
 void TS_RESP_CTX_add_flags(TS_RESP_CTX *ctx, int flags);
 
diff --git a/crypto/openssl/crypto/ts/ts_lib.c b/crypto/openssl/crypto/ts/ts_lib.c
index c51538a17f42..e0f106353723 100644
--- a/crypto/openssl/crypto/ts/ts_lib.c
+++ b/crypto/openssl/crypto/ts/ts_lib.c
@@ -90,9 +90,8 @@ int TS_OBJ_print_bio(BIO *bio, const ASN1_OBJECT *obj)
 {
     char obj_txt[128];
 
-    int len = OBJ_obj2txt(obj_txt, sizeof(obj_txt), obj, 0);
-    BIO_write(bio, obj_txt, len);
-    BIO_write(bio, "\n", 1);
+    OBJ_obj2txt(obj_txt, sizeof(obj_txt), obj, 0);
+    BIO_printf(bio, "%s\n", obj_txt);
 
     return 1;
 }
diff --git a/crypto/openssl/crypto/ts/ts_rsp_verify.c b/crypto/openssl/crypto/ts/ts_rsp_verify.c
index 29aa5a497e89..7918236287f3 100644
--- a/crypto/openssl/crypto/ts/ts_rsp_verify.c
+++ b/crypto/openssl/crypto/ts/ts_rsp_verify.c
@@ -434,51 +434,58 @@ static int int_TS_RESP_verify_token(TS_VERIFY_CTX *ctx,
     unsigned char *imprint = NULL;
     unsigned imprint_len = 0;
     int ret = 0;
+    int flags = ctx->flags;
+
+    /* Some options require us to also check the signature */
+    if (((flags & TS_VFY_SIGNER) && tsa_name != NULL)
+            || (flags & TS_VFY_TSA_NAME)) {
+        flags |= TS_VFY_SIGNATURE;
+    }
 
     /* Verify the signature. */
-    if ((ctx->flags & TS_VFY_SIGNATURE)
+    if ((flags & TS_VFY_SIGNATURE)
         && !TS_RESP_verify_signature(token, ctx->certs, ctx->store, &signer))
         goto err;
 
     /* Check version number of response. */
-    if ((ctx->flags & TS_VFY_VERSION)
+    if ((flags & TS_VFY_VERSION)
         && TS_TST_INFO_get_version(tst_info) != 1) {
         TSerr(TS_F_INT_TS_RESP_VERIFY_TOKEN, TS_R_UNSUPPORTED_VERSION);
         goto err;
     }
 
     /* Check policies. */
-    if ((ctx->flags & TS_VFY_POLICY)
+    if ((flags & TS_VFY_POLICY)
         && !TS_check_policy(ctx->policy, tst_info))
         goto err;
 
     /* Check message imprints. */
-    if ((ctx->flags & TS_VFY_IMPRINT)
+    if ((flags & TS_VFY_IMPRINT)
         && !TS_check_imprints(ctx->md_alg, ctx->imprint, ctx->imprint_len,
                               tst_info))
         goto err;
 
     /* Compute and check message imprints. */
-    if ((ctx->flags & TS_VFY_DATA)
+    if ((flags & TS_VFY_DATA)
         && (!TS_compute_imprint(ctx->data, tst_info,
                                 &md_alg, &imprint, &imprint_len)
             || !TS_check_imprints(md_alg, imprint, imprint_len, tst_info)))
         goto err;
 
     /* Check nonces. */
-    if ((ctx->flags & TS_VFY_NONCE)
+    if ((flags & TS_VFY_NONCE)
         && !TS_check_nonces(ctx->nonce, tst_info))
         goto err;
 
     /* Check whether TSA name and signer certificate match. */
-    if ((ctx->flags & TS_VFY_SIGNER)
+    if ((flags & TS_VFY_SIGNER)
         && tsa_name && !TS_check_signer_name(tsa_name, signer)) {
         TSerr(TS_F_INT_TS_RESP_VERIFY_TOKEN, TS_R_TSA_NAME_MISMATCH);
         goto err;
     }
 
     /* Check whether the TSA is the expected one. */
-    if ((ctx->flags & TS_VFY_TSA_NAME)
+    if ((flags & TS_VFY_TSA_NAME)
         && !TS_check_signer_name(ctx->tsa_name, signer)) {
         TSerr(TS_F_INT_TS_RESP_VERIFY_TOKEN, TS_R_TSA_UNTRUSTED);
         goto err;
@@ -548,13 +555,15 @@ static int TS_check_status_info(TS_RESP *response)
 static char *TS_get_status_text(STACK_OF(ASN1_UTF8STRING) *text)
 {
     int i;
-    unsigned int length = 0;
+    int length = 0;
     char *result = NULL;
     char *p;
 
     /* Determine length first. */
     for (i = 0; i < sk_ASN1_UTF8STRING_num(text); ++i) {
         ASN1_UTF8STRING *current = sk_ASN1_UTF8STRING_value(text, i);
+        if (ASN1_STRING_length(current) > TS_MAX_STATUS_LENGTH - length - 1)
+            return NULL;
         length += ASN1_STRING_length(current);
         length += 1;            /* separator character */
     }
diff --git a/crypto/openssl/crypto/ui/ui_lib.c b/crypto/openssl/crypto/ui/ui_lib.c
index 2f580352ce8f..d25b4f37bd11 100644
--- a/crypto/openssl/crypto/ui/ui_lib.c
+++ b/crypto/openssl/crypto/ui/ui_lib.c
@@ -413,6 +413,8 @@ char *UI_construct_prompt(UI *ui, const char *object_desc,
         len += sizeof(prompt3) - 1;
 
         prompt = (char *)OPENSSL_malloc(len + 1);
+        if (prompt == NULL)
+            return NULL;
         BUF_strlcpy(prompt, prompt1, len + 1);
         BUF_strlcat(prompt, object_desc, len + 1);
         if (object_name) {
diff --git a/crypto/openssl/crypto/whrlpool/wp_dgst.c b/crypto/openssl/crypto/whrlpool/wp_dgst.c
index e33bb4f833b5..807d1c49b2d3 100644
--- a/crypto/openssl/crypto/whrlpool/wp_dgst.c
+++ b/crypto/openssl/crypto/whrlpool/wp_dgst.c
@@ -51,6 +51,7 @@
  * input. This is done for perfomance.
  */
 
+#include <openssl/crypto.h>
 #include "wp_locl.h"
 #include <openssl/crypto.h>
 #include <string.h>
@@ -237,7 +238,7 @@ int WHIRLPOOL_Final(unsigned char *md, WHIRLPOOL_CTX *c)
 
     if (md) {
         memcpy(md, c->H.c, WHIRLPOOL_DIGEST_LENGTH);
-        memset(c, 0, sizeof(*c));
+        OPENSSL_cleanse(c, sizeof(*c));
         return (1);
     }
     return (0);
diff --git a/crypto/openssl/crypto/x509/by_dir.c b/crypto/openssl/crypto/x509/by_dir.c
index 9ee8f8d8597a..bbc3189381e5 100644
--- a/crypto/openssl/crypto/x509/by_dir.c
+++ b/crypto/openssl/crypto/x509/by_dir.c
@@ -401,6 +401,10 @@ static int get_cert_by_subject(X509_LOOKUP *xl, int type, X509_NAME *name,
             }
             if (!hent) {
                 hent = OPENSSL_malloc(sizeof(BY_DIR_HASH));
+                if (hent == NULL) {
+                    X509err(X509_F_GET_CERT_BY_SUBJECT, ERR_R_MALLOC_FAILURE);
+                    goto finish;
+                }
                 hent->hash = h;
                 hent->suffix = k;
                 if (!sk_BY_DIR_HASH_push(ent->hashes, hent)) {
diff --git a/crypto/openssl/crypto/x509/x509.h b/crypto/openssl/crypto/x509/x509.h
index fc613ce63526..6fa28ebada46 100644
--- a/crypto/openssl/crypto/x509/x509.h
+++ b/crypto/openssl/crypto/x509/x509.h
@@ -1234,6 +1234,7 @@ int X509_TRUST_get_trust(X509_TRUST *xp);
  * The following lines are auto generated by the script mkerr.pl. Any changes
  * made after this point may be overwritten when the script is next run.
  */
+
 void ERR_load_X509_strings(void);
 
 /* Error codes for the X509 functions. */
@@ -1241,6 +1242,7 @@ void ERR_load_X509_strings(void);
 /* Function codes. */
 # define X509_F_ADD_CERT_DIR                              100
 # define X509_F_BY_FILE_CTRL                              101
+# define X509_F_CHECK_NAME_CONSTRAINTS                    106
 # define X509_F_CHECK_POLICY                              145
 # define X509_F_DIR_CTRL                                  102
 # define X509_F_GET_CERT_BY_SUBJECT                       103
@@ -1322,7 +1324,7 @@ void ERR_load_X509_strings(void);
 # define X509_R_WRONG_LOOKUP_TYPE                         112
 # define X509_R_WRONG_TYPE                                122
 
-#ifdef  __cplusplus
+# ifdef  __cplusplus
 }
-#endif
+# endif
 #endif
diff --git a/crypto/openssl/crypto/x509/x509_att.c b/crypto/openssl/crypto/x509/x509_att.c
index bd59281f9dac..25010753078c 100644
--- a/crypto/openssl/crypto/x509/x509_att.c
+++ b/crypto/openssl/crypto/x509/x509_att.c
@@ -296,7 +296,7 @@ int X509_ATTRIBUTE_set1_object(X509_ATTRIBUTE *attr, const ASN1_OBJECT *obj)
 int X509_ATTRIBUTE_set1_data(X509_ATTRIBUTE *attr, int attrtype,
                              const void *data, int len)
 {
-    ASN1_TYPE *ttmp;
+    ASN1_TYPE *ttmp = NULL;
     ASN1_STRING *stmp = NULL;
     int atype = 0;
     if (!attr)
@@ -324,20 +324,26 @@ int X509_ATTRIBUTE_set1_data(X509_ATTRIBUTE *attr, int attrtype,
      * least one value but some types use and zero length SET and require
      * this.
      */
-    if (attrtype == 0)
+    if (attrtype == 0) {
+        ASN1_STRING_free(stmp);
         return 1;
+    }
     if (!(ttmp = ASN1_TYPE_new()))
         goto err;
     if ((len == -1) && !(attrtype & MBSTRING_FLAG)) {
         if (!ASN1_TYPE_set1(ttmp, attrtype, data))
             goto err;
-    } else
+    } else {
         ASN1_TYPE_set(ttmp, atype, stmp);
+        stmp = NULL;
+    }
     if (!sk_ASN1_TYPE_push(attr->value.set, ttmp))
         goto err;
     return 1;
  err:
     X509err(X509_F_X509_ATTRIBUTE_SET1_DATA, ERR_R_MALLOC_FAILURE);
+    ASN1_TYPE_free(ttmp);
+    ASN1_STRING_free(stmp);
     return 0;
 }
 
diff --git a/crypto/openssl/crypto/x509/x509_err.c b/crypto/openssl/crypto/x509/x509_err.c
index 1e779fefd9c1..a2a8e1b08bb2 100644
--- a/crypto/openssl/crypto/x509/x509_err.c
+++ b/crypto/openssl/crypto/x509/x509_err.c
@@ -1,6 +1,6 @@
 /* crypto/x509/x509_err.c */
 /* ====================================================================
- * Copyright (c) 1999-2012 The OpenSSL Project.  All rights reserved.
+ * Copyright (c) 1999-2016 The OpenSSL Project.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -72,6 +72,7 @@
 static ERR_STRING_DATA X509_str_functs[] = {
     {ERR_FUNC(X509_F_ADD_CERT_DIR), "ADD_CERT_DIR"},
     {ERR_FUNC(X509_F_BY_FILE_CTRL), "BY_FILE_CTRL"},
+    {ERR_FUNC(X509_F_CHECK_NAME_CONSTRAINTS), "CHECK_NAME_CONSTRAINTS"},
     {ERR_FUNC(X509_F_CHECK_POLICY), "CHECK_POLICY"},
     {ERR_FUNC(X509_F_DIR_CTRL), "DIR_CTRL"},
     {ERR_FUNC(X509_F_GET_CERT_BY_SUBJECT), "GET_CERT_BY_SUBJECT"},
diff --git a/crypto/openssl/crypto/x509/x509_obj.c b/crypto/openssl/crypto/x509/x509_obj.c
index 3de3ac720411..0a839f3e54ce 100644
--- a/crypto/openssl/crypto/x509/x509_obj.c
+++ b/crypto/openssl/crypto/x509/x509_obj.c
@@ -129,7 +129,7 @@ char *X509_NAME_oneline(X509_NAME *a, char *buf, int len)
             type == V_ASN1_VISIBLESTRING ||
             type == V_ASN1_PRINTABLESTRING ||
             type == V_ASN1_TELETEXSTRING ||
-            type == V_ASN1_VISIBLESTRING || type == V_ASN1_IA5STRING) {
+            type == V_ASN1_IA5STRING) {
             if (num > (int)sizeof(ebcdic_buf))
                 num = sizeof(ebcdic_buf);
             ascii2ebcdic(ebcdic_buf, q, num);
diff --git a/crypto/openssl/crypto/x509/x509_r2x.c b/crypto/openssl/crypto/x509/x509_r2x.c
index 0ff439c99f1b..2879569ead41 100644
--- a/crypto/openssl/crypto/x509/x509_r2x.c
+++ b/crypto/openssl/crypto/x509/x509_r2x.c
@@ -70,10 +70,12 @@ X509 *X509_REQ_to_X509(X509_REQ *r, int days, EVP_PKEY *pkey)
     X509 *ret = NULL;
     X509_CINF *xi = NULL;
     X509_NAME *xn;
+    EVP_PKEY *pubkey = NULL;
+    int res;
 
     if ((ret = X509_new()) == NULL) {
         X509err(X509_F_X509_REQ_TO_X509, ERR_R_MALLOC_FAILURE);
-        goto err;
+        return NULL;
     }
 
     /* duplicate the request */
@@ -89,9 +91,9 @@ X509 *X509_REQ_to_X509(X509_REQ *r, int days, EVP_PKEY *pkey)
     }
 
     xn = X509_REQ_get_subject_name(r);
-    if (X509_set_subject_name(ret, X509_NAME_dup(xn)) == 0)
+    if (X509_set_subject_name(ret, xn) == 0)
         goto err;
-    if (X509_set_issuer_name(ret, X509_NAME_dup(xn)) == 0)
+    if (X509_set_issuer_name(ret, xn) == 0)
         goto err;
 
     if (X509_gmtime_adj(xi->validity->notBefore, 0) == NULL)
@@ -100,9 +102,11 @@ X509 *X509_REQ_to_X509(X509_REQ *r, int days, EVP_PKEY *pkey)
         NULL)
         goto err;
 
-    X509_set_pubkey(ret, X509_REQ_get_pubkey(r));
+    pubkey = X509_REQ_get_pubkey(r);
+    res = X509_set_pubkey(ret, pubkey);
+    EVP_PKEY_free(pubkey);
 
-    if (!X509_sign(ret, pkey, EVP_md5()))
+    if (!res || !X509_sign(ret, pkey, EVP_md5()))
         goto err;
     if (0) {
  err:
diff --git a/crypto/openssl/crypto/x509/x509_txt.c b/crypto/openssl/crypto/x509/x509_txt.c
index 3d46d3ff8366..35db09559133 100644
--- a/crypto/openssl/crypto/x509/x509_txt.c
+++ b/crypto/openssl/crypto/x509/x509_txt.c
@@ -204,6 +204,13 @@ const char *X509_verify_cert_error_string(long n)
     case X509_V_ERR_IP_ADDRESS_MISMATCH:
         return ("IP address mismatch");
 
+    case X509_V_ERR_INVALID_CALL:
+        return ("Invalid certificate verification context");
+    case X509_V_ERR_STORE_LOOKUP:
+        return ("Issuer certificate lookup error");
+    case X509_V_ERR_PROXY_SUBJECT_NAME_VIOLATION:
+        return ("proxy subject name violation");
+
     default:
         BIO_snprintf(buf, sizeof buf, "error number %ld", n);
         return (buf);
diff --git a/crypto/openssl/crypto/x509/x509_vfy.c b/crypto/openssl/crypto/x509/x509_vfy.c
index 4d34dbac9314..8334b3fcff7f 100644
--- a/crypto/openssl/crypto/x509/x509_vfy.c
+++ b/crypto/openssl/crypto/x509/x509_vfy.c
@@ -199,6 +199,7 @@ int X509_verify_cert(X509_STORE_CTX *ctx)
 
     if (ctx->cert == NULL) {
         X509err(X509_F_X509_VERIFY_CERT, X509_R_NO_CERT_SET_FOR_US_TO_VERIFY);
+        ctx->error = X509_V_ERR_INVALID_CALL;
         return -1;
     }
     if (ctx->chain != NULL) {
@@ -207,6 +208,7 @@ int X509_verify_cert(X509_STORE_CTX *ctx)
          * cannot do another one.
          */
         X509err(X509_F_X509_VERIFY_CERT, ERR_R_SHOULD_NOT_HAVE_BEEN_CALLED);
+        ctx->error = X509_V_ERR_INVALID_CALL;
         return -1;
     }
 
@@ -219,6 +221,7 @@ int X509_verify_cert(X509_STORE_CTX *ctx)
     if (((ctx->chain = sk_X509_new_null()) == NULL) ||
         (!sk_X509_push(ctx->chain, ctx->cert))) {
         X509err(X509_F_X509_VERIFY_CERT, ERR_R_MALLOC_FAILURE);
+        ctx->error = X509_V_ERR_OUT_OF_MEM;
         ok = -1;
         goto err;
     }
@@ -229,6 +232,7 @@ int X509_verify_cert(X509_STORE_CTX *ctx)
     if (ctx->untrusted != NULL
         && (sktmp = sk_X509_dup(ctx->untrusted)) == NULL) {
         X509err(X509_F_X509_VERIFY_CERT, ERR_R_MALLOC_FAILURE);
+        ctx->error = X509_V_ERR_OUT_OF_MEM;
         ok = -1;
         goto err;
     }
@@ -253,8 +257,10 @@ int X509_verify_cert(X509_STORE_CTX *ctx)
          */
         if (ctx->param->flags & X509_V_FLAG_TRUSTED_FIRST) {
             ok = ctx->get_issuer(&xtmp, ctx, x);
-            if (ok < 0)
+            if (ok < 0) {
+                ctx->error = X509_V_ERR_STORE_LOOKUP;
                 goto err;
+            }
             /*
              * If successful for now free up cert so it will be picked up
              * again later.
@@ -271,6 +277,7 @@ int X509_verify_cert(X509_STORE_CTX *ctx)
             if (xtmp != NULL) {
                 if (!sk_X509_push(ctx->chain, xtmp)) {
                     X509err(X509_F_X509_VERIFY_CERT, ERR_R_MALLOC_FAILURE);
+                    ctx->error = X509_V_ERR_OUT_OF_MEM;
                     ok = -1;
                     goto err;
                 }
@@ -352,14 +359,17 @@ int X509_verify_cert(X509_STORE_CTX *ctx)
                 break;
             ok = ctx->get_issuer(&xtmp, ctx, x);
 
-            if (ok < 0)
+            if (ok < 0) {
+                ctx->error = X509_V_ERR_STORE_LOOKUP;
                 goto err;
+            }
             if (ok == 0)
                 break;
             x = xtmp;
             if (!sk_X509_push(ctx->chain, x)) {
                 X509_free(xtmp);
                 X509err(X509_F_X509_VERIFY_CERT, ERR_R_MALLOC_FAILURE);
+                ctx->error = X509_V_ERR_OUT_OF_MEM;
                 ok = -1;
                 goto err;
             }
@@ -386,8 +396,10 @@ int X509_verify_cert(X509_STORE_CTX *ctx)
             while (j-- > 1) {
                 xtmp2 = sk_X509_value(ctx->chain, j - 1);
                 ok = ctx->get_issuer(&xtmp, ctx, xtmp2);
-                if (ok < 0)
+                if (ok < 0) {
+                    ctx->error = X509_V_ERR_STORE_LOOKUP;
                     goto err;
+                }
                 /* Check if we found an alternate chain */
                 if (ok > 0) {
                     /*
@@ -515,6 +527,10 @@ int X509_verify_cert(X509_STORE_CTX *ctx)
         sk_X509_free(sktmp);
     if (chain_ss != NULL)
         X509_free(chain_ss);
+
+    /* Safety net, error returns must set ctx->error */
+    if (ok <= 0 && ctx->error == X509_V_OK)
+        ctx->error = X509_V_ERR_UNSPECIFIED;
     return ok;
 }
 
@@ -697,13 +713,27 @@ static int check_chain_extensions(X509_STORE_CTX *ctx)
          * the next certificate must be a CA certificate.
          */
         if (x->ex_flags & EXFLAG_PROXY) {
-            if (x->ex_pcpathlen != -1 && i > x->ex_pcpathlen) {
-                ctx->error = X509_V_ERR_PROXY_PATH_LENGTH_EXCEEDED;
-                ctx->error_depth = i;
-                ctx->current_cert = x;
-                ok = cb(0, ctx);
-                if (!ok)
-                    goto end;
+            /*
+             * RFC3820, 4.1.3 (b)(1) stipulates that if pCPathLengthConstraint
+             * is less than max_path_length, the former should be copied to
+             * the latter, and 4.1.4 (a) stipulates that max_path_length
+             * should be verified to be larger than zero and decrement it.
+             *
+             * Because we're checking the certs in the reverse order, we start
+             * with verifying that proxy_path_length isn't larger than pcPLC,
+             * and copy the latter to the former if it is, and finally,
+             * increment proxy_path_length.
+             */
+            if (x->ex_pcpathlen != -1) {
+                if (proxy_path_length > x->ex_pcpathlen) {
+                    ctx->error = X509_V_ERR_PROXY_PATH_LENGTH_EXCEEDED;
+                    ctx->error_depth = i;
+                    ctx->current_cert = x;
+                    ok = cb(0, ctx);
+                    if (!ok)
+                        goto end;
+                }
+                proxy_path_length = x->ex_pcpathlen;
             }
             proxy_path_length++;
             must_be_ca = 0;
@@ -726,6 +756,81 @@ static int check_name_constraints(X509_STORE_CTX *ctx)
         /* Ignore self issued certs unless last in chain */
         if (i && (x->ex_flags & EXFLAG_SI))
             continue;
+
+        /*
+         * Proxy certificates policy has an extra constraint, where the
+         * certificate subject MUST be the issuer with a single CN entry
+         * added.
+         * (RFC 3820: 3.4, 4.1.3 (a)(4))
+         */
+        if (x->ex_flags & EXFLAG_PROXY) {
+            X509_NAME *tmpsubject = X509_get_subject_name(x);
+            X509_NAME *tmpissuer = X509_get_issuer_name(x);
+            X509_NAME_ENTRY *tmpentry = NULL;
+            int last_object_nid = 0;
+            int err = X509_V_OK;
+            int last_object_loc = X509_NAME_entry_count(tmpsubject) - 1;
+
+            /* Check that there are at least two RDNs */
+            if (last_object_loc < 1) {
+                err = X509_V_ERR_PROXY_SUBJECT_NAME_VIOLATION;
+                goto proxy_name_done;
+            }
+
+            /*
+             * Check that there is exactly one more RDN in subject as
+             * there is in issuer.
+             */
+            if (X509_NAME_entry_count(tmpsubject)
+                != X509_NAME_entry_count(tmpissuer) + 1) {
+                err = X509_V_ERR_PROXY_SUBJECT_NAME_VIOLATION;
+                goto proxy_name_done;
+            }
+
+            /*
+             * Check that the last subject component isn't part of a
+             * multivalued RDN
+             */
+            if (X509_NAME_get_entry(tmpsubject, last_object_loc)->set
+                == X509_NAME_get_entry(tmpsubject, last_object_loc - 1)->set) {
+                err = X509_V_ERR_PROXY_SUBJECT_NAME_VIOLATION;
+                goto proxy_name_done;
+            }
+
+            /*
+             * Check that the last subject RDN is a commonName, and that
+             * all the previous RDNs match the issuer exactly
+             */
+            tmpsubject = X509_NAME_dup(tmpsubject);
+            if (tmpsubject == NULL) {
+                X509err(X509_F_CHECK_NAME_CONSTRAINTS, ERR_R_MALLOC_FAILURE);
+                ctx->error = X509_V_ERR_OUT_OF_MEM;
+                return 0;
+            }
+
+            tmpentry =
+                X509_NAME_delete_entry(tmpsubject, last_object_loc);
+            last_object_nid =
+                OBJ_obj2nid(X509_NAME_ENTRY_get_object(tmpentry));
+
+            if (last_object_nid != NID_commonName
+                || X509_NAME_cmp(tmpsubject, tmpissuer) != 0) {
+                err = X509_V_ERR_PROXY_SUBJECT_NAME_VIOLATION;
+            }
+
+            X509_NAME_ENTRY_free(tmpentry);
+            X509_NAME_free(tmpsubject);
+
+         proxy_name_done:
+            if (err != X509_V_OK) {
+                ctx->error = err;
+                ctx->error_depth = i;
+                ctx->current_cert = x;
+                if (!ctx->verify_cb(0, ctx))
+                    return 0;
+            }
+        }
+
         /*
          * Check against constraints for all certificates higher in chain
          * including trust anchor. Trust anchor not strictly speaking needed
@@ -736,12 +841,19 @@ static int check_name_constraints(X509_STORE_CTX *ctx)
             NAME_CONSTRAINTS *nc = sk_X509_value(ctx->chain, j)->nc;
             if (nc) {
                 rv = NAME_CONSTRAINTS_check(x, nc);
-                if (rv != X509_V_OK) {
+                switch (rv) {
+                case X509_V_OK:
+                    continue;
+                case X509_V_ERR_OUT_OF_MEM:
+                    ctx->error = rv;
+                    return 0;
+                default:
                     ctx->error = rv;
                     ctx->error_depth = i;
                     ctx->current_cert = x;
                     if (!ctx->verify_cb(0, ctx))
                         return 0;
+                    break;
                 }
             }
         }
@@ -880,6 +992,8 @@ static int check_cert(X509_STORE_CTX *ctx)
     ctx->current_issuer = NULL;
     ctx->current_crl_score = 0;
     ctx->current_reasons = 0;
+    if (x->ex_flags & EXFLAG_PROXY)
+        return 1;
     while (ctx->current_reasons != CRLDP_ALL_REASONS) {
         last_reasons = ctx->current_reasons;
         /* Try to retrieve relevant CRL */
@@ -1010,13 +1124,25 @@ static int get_crl_sk(X509_STORE_CTX *ctx, X509_CRL **pcrl, X509_CRL **pdcrl,
         crl = sk_X509_CRL_value(crls, i);
         reasons = *preasons;
         crl_score = get_crl_score(ctx, &crl_issuer, &reasons, crl, x);
-
-        if (crl_score > best_score) {
-            best_crl = crl;
-            best_crl_issuer = crl_issuer;
-            best_score = crl_score;
-            best_reasons = reasons;
+        if (crl_score < best_score)
+            continue;
+        /* If current CRL is equivalent use it if it is newer */
+        if (crl_score == best_score) {
+            int day, sec;
+            if (ASN1_TIME_diff(&day, &sec, X509_CRL_get_lastUpdate(best_crl),
+                               X509_CRL_get_lastUpdate(crl)) == 0)
+                continue;
+            /*
+             * ASN1_TIME_diff never returns inconsistent signs for |day|
+             * and |sec|.
+             */
+            if (day <= 0 && sec <= 0)
+                continue;
         }
+        best_crl = crl;
+        best_crl_issuer = crl_issuer;
+        best_score = crl_score;
+        best_reasons = reasons;
     }
 
     if (best_crl) {
@@ -1630,6 +1756,7 @@ static int check_policy(X509_STORE_CTX *ctx)
                             ctx->param->policies, ctx->param->flags);
     if (ret == 0) {
         X509err(X509_F_CHECK_POLICY, ERR_R_MALLOC_FAILURE);
+        ctx->error = X509_V_ERR_OUT_OF_MEM;
         return 0;
     }
     /* Invalid or inconsistent extensions */
@@ -1658,7 +1785,12 @@ static int check_policy(X509_STORE_CTX *ctx)
 
     if (ctx->param->flags & X509_V_FLAG_NOTIFY_POLICY) {
         ctx->current_cert = NULL;
-        ctx->error = X509_V_OK;
+        /*
+         * Verification errors need to be "sticky", a callback may have allowed
+         * an SSL handshake to continue despite an error, and we must then
+         * remain in an error state.  Therefore, we MUST NOT clear earlier
+         * verification errors by setting the error to X509_V_OK.
+         */
         if (!ctx->verify_cb(2, ctx))
             return 0;
     }
diff --git a/crypto/openssl/crypto/x509/x509_vfy.h b/crypto/openssl/crypto/x509/x509_vfy.h
index 2663e1c0a362..50626826e0b9 100644
--- a/crypto/openssl/crypto/x509/x509_vfy.h
+++ b/crypto/openssl/crypto/x509/x509_vfy.h
@@ -368,6 +368,7 @@ void X509_STORE_CTX_set_depth(X509_STORE_CTX *ctx, int depth);
 # define         X509_V_ERR_PERMITTED_VIOLATION                  47
 # define         X509_V_ERR_EXCLUDED_VIOLATION                   48
 # define         X509_V_ERR_SUBTREE_MINMAX                       49
+# define         X509_V_ERR_APPLICATION_VERIFICATION             50
 # define         X509_V_ERR_UNSUPPORTED_CONSTRAINT_TYPE          51
 # define         X509_V_ERR_UNSUPPORTED_CONSTRAINT_SYNTAX        52
 # define         X509_V_ERR_UNSUPPORTED_NAME_SYNTAX              53
@@ -386,8 +387,12 @@ void X509_STORE_CTX_set_depth(X509_STORE_CTX *ctx, int depth);
 # define         X509_V_ERR_EMAIL_MISMATCH                       63
 # define         X509_V_ERR_IP_ADDRESS_MISMATCH                  64
 
-/* The application is not happy */
-# define         X509_V_ERR_APPLICATION_VERIFICATION             50
+/* Caller error */
+# define         X509_V_ERR_INVALID_CALL                         65
+/* Issuer lookup error */
+# define         X509_V_ERR_STORE_LOOKUP                         66
+
+# define         X509_V_ERR_PROXY_SUBJECT_NAME_VIOLATION         67
 
 /* Certificate verify flags */
 
diff --git a/crypto/openssl/crypto/x509/x509spki.c b/crypto/openssl/crypto/x509/x509spki.c
index 2df84ead9ef9..5ae5d30a3516 100644
--- a/crypto/openssl/crypto/x509/x509spki.c
+++ b/crypto/openssl/crypto/x509/x509spki.c
@@ -112,6 +112,8 @@ char *NETSCAPE_SPKI_b64_encode(NETSCAPE_SPKI *spki)
     der_spki = OPENSSL_malloc(der_len);
     b64_str = OPENSSL_malloc(der_len * 2);
     if (!der_spki || !b64_str) {
+        OPENSSL_free(der_spki);
+        OPENSSL_free(b64_str);
         X509err(X509_F_NETSCAPE_SPKI_B64_ENCODE, ERR_R_MALLOC_FAILURE);
         return NULL;
     }
diff --git a/crypto/openssl/crypto/x509v3/v3_addr.c b/crypto/openssl/crypto/x509v3/v3_addr.c
index 94cfed050910..1290dec9bb8c 100644
--- a/crypto/openssl/crypto/x509v3/v3_addr.c
+++ b/crypto/openssl/crypto/x509v3/v3_addr.c
@@ -1211,6 +1211,11 @@ int v3_addr_subset(IPAddrBlocks *a, IPAddrBlocks *b)
 
 /*
  * Core code for RFC 3779 2.3 path validation.
+ *
+ * Returns 1 for success, 0 on error.
+ *
+ * When returning 0, ctx->error MUST be set to an appropriate value other than
+ * X509_V_OK.
  */
 static int v3_addr_validate_path_internal(X509_STORE_CTX *ctx,
                                           STACK_OF(X509) *chain,
@@ -1245,6 +1250,7 @@ static int v3_addr_validate_path_internal(X509_STORE_CTX *ctx,
     if ((child = sk_IPAddressFamily_dup(ext)) == NULL) {
         X509V3err(X509V3_F_V3_ADDR_VALIDATE_PATH_INTERNAL,
                   ERR_R_MALLOC_FAILURE);
+        ctx->error = X509_V_ERR_OUT_OF_MEM;
         ret = 0;
         goto done;
     }
diff --git a/crypto/openssl/crypto/x509v3/v3_alt.c b/crypto/openssl/crypto/x509v3/v3_alt.c
index 22ec202846ec..7f1e71dd1a42 100644
--- a/crypto/openssl/crypto/x509v3/v3_alt.c
+++ b/crypto/openssl/crypto/x509v3/v3_alt.c
@@ -573,6 +573,8 @@ static int do_othername(GENERAL_NAME *gen, char *value, X509V3_CTX *ctx)
         return 0;
     objlen = p - value;
     objtmp = OPENSSL_malloc(objlen + 1);
+    if (objtmp == NULL)
+        return 0;
     strncpy(objtmp, value, objlen);
     objtmp[objlen] = 0;
     gen->d.otherName->type_id = OBJ_txt2obj(objtmp, 0);
diff --git a/crypto/openssl/crypto/x509v3/v3_conf.c b/crypto/openssl/crypto/x509v3/v3_conf.c
index eeff8bd18502..c1b4c1a89f74 100644
--- a/crypto/openssl/crypto/x509v3/v3_conf.c
+++ b/crypto/openssl/crypto/x509v3/v3_conf.c
@@ -135,11 +135,13 @@ static X509_EXTENSION *do_ext_nconf(CONF *conf, X509V3_CTX *ctx, int ext_nid,
             nval = NCONF_get_section(conf, value + 1);
         else
             nval = X509V3_parse_list(value);
-        if (sk_CONF_VALUE_num(nval) <= 0) {
+        if (nval == NULL || sk_CONF_VALUE_num(nval) <= 0) {
             X509V3err(X509V3_F_DO_EXT_NCONF,
                       X509V3_R_INVALID_EXTENSION_STRING);
             ERR_add_error_data(4, "name=", OBJ_nid2sn(ext_nid), ",section=",
                                value);
+            if (*value != '@')
+                sk_CONF_VALUE_free(nval);
             return NULL;
         }
         ext_struc = method->v2i(method, ctx, nval);
diff --git a/crypto/openssl/doc/apps/cms.pod b/crypto/openssl/doc/apps/cms.pod
index 4eaedbcd34c4..ac69804228cc 100644
--- a/crypto/openssl/doc/apps/cms.pod
+++ b/crypto/openssl/doc/apps/cms.pod
@@ -86,6 +86,9 @@ encrypt mail for the given recipient certificates. Input file is the message
 to be encrypted. The output file is the encrypted mail in MIME format. The
 actual CMS type is <B>EnvelopedData<B>.
 
+Note that no revocation check is done for the recipient cert, so if that
+key has been compromised, others may be able to decrypt the text.
+
 =item B<-decrypt>
 
 decrypt mail using the supplied certificate and private key. Expects an
diff --git a/crypto/openssl/doc/apps/s_client.pod b/crypto/openssl/doc/apps/s_client.pod
index 618df9659d3b..29675dd213f4 100644
--- a/crypto/openssl/doc/apps/s_client.pod
+++ b/crypto/openssl/doc/apps/s_client.pod
@@ -53,6 +53,7 @@ B<openssl> B<s_client>
 [B<-rand file(s)>]
 [B<-serverinfo types>]
 [B<-status>]
+[B<-alpn protocols>]
 [B<-nextprotoneg protocols>]
 
 =head1 DESCRIPTION
@@ -277,9 +278,13 @@ file.
 sends a certificate status request to the server (OCSP stapling). The server
 response (if any) is printed out.
 
-=item B<-nextprotoneg protocols>
+=item B<-alpn protocols>, B<-nextprotoneg protocols>
 
-enable Next Protocol Negotiation TLS extension and provide a list of
+these flags enable the 
+Enable the Application-Layer Protocol Negotiation or Next Protocol
+Negotiation extension, respectively. ALPN is the IETF standard and
+replaces NPN.
+The B<protocols> list is a
 comma-separated protocol names that the client should advertise
 support for. The list should contain most wanted protocols first.
 Protocol names are printable ASCII strings, for example "http/1.1" or
diff --git a/crypto/openssl/doc/apps/s_server.pod b/crypto/openssl/doc/apps/s_server.pod
index 6f4acb7006ff..fa17488d9173 100644
--- a/crypto/openssl/doc/apps/s_server.pod
+++ b/crypto/openssl/doc/apps/s_server.pod
@@ -62,6 +62,7 @@ B<openssl> B<s_server>
 [B<-status_verbose>]
 [B<-status_timeout nsec>]
 [B<-status_url url>]
+[B<-alpn protocols>]
 [B<-nextprotoneg protocols>]
 
 =head1 DESCRIPTION
@@ -327,9 +328,13 @@ sets a fallback responder URL to use if no responder URL is present in the
 server certificate. Without this option an error is returned if the server
 certificate does not contain a responder address.
 
-=item B<-nextprotoneg protocols>
+=item B<-alpn protocols>, B<-nextprotoneg protocols>
 
-enable Next Protocol Negotiation TLS extension and provide a
+these flags enable the 
+Enable the Application-Layer Protocol Negotiation or Next Protocol
+Negotiation extension, respectively. ALPN is the IETF standard and
+replaces NPN.
+The B<protocols> list is a
 comma-separated list of supported protocol names.
 The list should contain most wanted protocols first.
 Protocol names are printable ASCII strings, for example "http/1.1" or
diff --git a/crypto/openssl/doc/apps/smime.pod b/crypto/openssl/doc/apps/smime.pod
index d5618c8ff0df..04a83ca8e427 100644
--- a/crypto/openssl/doc/apps/smime.pod
+++ b/crypto/openssl/doc/apps/smime.pod
@@ -53,6 +53,9 @@ The meaning of the other options varies according to the operation type.
 encrypt mail for the given recipient certificates. Input file is the message
 to be encrypted. The output file is the encrypted mail in MIME format.
 
+Note that no revocation check is done for the recipient cert, so if that
+key has been compromised, others may be able to decrypt the text.
+
 =item B<-decrypt>
 
 decrypt mail using the supplied certificate and private key. Expects an
diff --git a/crypto/openssl/doc/apps/verify.pod b/crypto/openssl/doc/apps/verify.pod
index bffa6c0ec403..b3767325ae07 100644
--- a/crypto/openssl/doc/apps/verify.pod
+++ b/crypto/openssl/doc/apps/verify.pod
@@ -27,6 +27,7 @@ B<openssl> B<verify>
 [B<-use_deltas>]
 [B<-policy_print>]
 [B<-no_alt_chains>]
+[B<-allow_proxy_certs>]
 [B<-untrusted file>]
 [B<-help>]
 [B<-issuer_checks>]
@@ -139,6 +140,10 @@ be found that is trusted. With this option that behaviour is suppressed so that
 only the first chain found is ever used. Using this option will force the
 behaviour to match that of previous OpenSSL versions.
 
+=item B<-allow_proxy_certs>
+
+Allow the verification of proxy certificates.
+
 =item B<-trusted file>
 
 A file of additional trusted certificates. The file should contain multiple
diff --git a/crypto/openssl/doc/apps/x509.pod b/crypto/openssl/doc/apps/x509.pod
index f72e9785ffaa..10e49e5b88b2 100644
--- a/crypto/openssl/doc/apps/x509.pod
+++ b/crypto/openssl/doc/apps/x509.pod
@@ -642,8 +642,8 @@ hex dump unsupported extensions.
 
 =item B<ca_default>
 
-the value used by the B<ca> utility, equivalent to B<no_issuer>, B<no_pubkey>, B<no_header>,
-B<no_version>, B<no_sigdump> and B<no_signame>.
+the value used by the B<ca> utility, equivalent to B<no_issuer>, B<no_pubkey>,
+B<no_header>, and B<no_version>.
 
 =back
 
diff --git a/crypto/openssl/doc/apps/x509v3_config.pod b/crypto/openssl/doc/apps/x509v3_config.pod
index c82cea1da24e..fb5f79c356e6 100644
--- a/crypto/openssl/doc/apps/x509v3_config.pod
+++ b/crypto/openssl/doc/apps/x509v3_config.pod
@@ -104,7 +104,7 @@ Examples:
 This extensions consists of a list of usages indicating purposes for which
 the certificate public key can be used for,
 
-These can either be object short names of the dotted numerical form of OIDs.
+These can either be object short names or the dotted numerical form of OIDs.
 While any OID can be used only certain values make sense. In particular the
 following PKIX, NS and MS values are meaningful:
 
diff --git a/crypto/openssl/doc/crypto/BIO_s_bio.pod b/crypto/openssl/doc/crypto/BIO_s_bio.pod
index 8d0a55a025c7..9fe88b26b0af 100644
--- a/crypto/openssl/doc/crypto/BIO_s_bio.pod
+++ b/crypto/openssl/doc/crypto/BIO_s_bio.pod
@@ -120,6 +120,9 @@ the application then waits for data to be available on the underlying transport
 before flushing the write buffer it will never succeed because the request was
 never sent!
 
+BIO_eof() is true if no data is in the peer BIO and the peer BIO has been
+shutdown.
+
 =head1 RETURN VALUES
 
 BIO_new_bio_pair() returns 1 on success, with the new BIOs available in
diff --git a/crypto/openssl/doc/crypto/BN_bn2bin.pod b/crypto/openssl/doc/crypto/BN_bn2bin.pod
index a4b17ca60a89..3bed47f8f1d5 100644
--- a/crypto/openssl/doc/crypto/BN_bn2bin.pod
+++ b/crypto/openssl/doc/crypto/BN_bn2bin.pod
@@ -42,7 +42,9 @@ BN_hex2bn() converts the string B<str> containing a hexadecimal number
 to a B<BIGNUM> and stores it in **B<bn>. If *B<bn> is NULL, a new
 B<BIGNUM> is created. If B<bn> is NULL, it only computes the number's
 length in hexadecimal digits. If the string starts with '-', the
-number is negative. BN_dec2bn() is the same using the decimal system.
+number is negative.
+A "negative zero" is converted to zero.
+BN_dec2bn() is the same using the decimal system.
 
 BN_print() and BN_print_fp() write the hexadecimal encoding of B<a>,
 with a leading '-' for negative numbers, to the B<BIO> or B<FILE>
diff --git a/crypto/openssl/doc/crypto/BN_rand.pod b/crypto/openssl/doc/crypto/BN_rand.pod
index e8cbf658b47d..a1513a952654 100644
--- a/crypto/openssl/doc/crypto/BN_rand.pod
+++ b/crypto/openssl/doc/crypto/BN_rand.pod
@@ -19,7 +19,11 @@ BN_rand, BN_pseudo_rand, BN_rand_range, BN_pseudo_rand_range - generate pseudo-r
 =head1 DESCRIPTION
 
 BN_rand() generates a cryptographically strong pseudo-random number of
-B<bits> in length and stores it in B<rnd>. If B<top> is -1, the
+B<bits> in length and stores it in B<rnd>.
+If B<bits> is less than zero, or too small to
+accomodate the requirements specified by the B<top> and B<bottom>
+parameters, an error is returned.
+If B<top> is -1, the
 most significant bit of the random number can be zero. If B<top> is 0,
 it is set to 1, and if B<top> is 1, the two most significant bits of
 the number will be set to 1, so that the product of two such random
diff --git a/crypto/openssl/doc/crypto/EVP_EncryptInit.pod b/crypto/openssl/doc/crypto/EVP_EncryptInit.pod
index 9696fd8f7333..9facf51b77f5 100644
--- a/crypto/openssl/doc/crypto/EVP_EncryptInit.pod
+++ b/crypto/openssl/doc/crypto/EVP_EncryptInit.pod
@@ -165,10 +165,11 @@ similar way to EVP_EncryptInit_ex(), EVP_DecryptInit_ex and
 EVP_CipherInit_ex() except the B<ctx> parameter does not need to be
 initialized and they always use the default cipher implementation.
 
-EVP_EncryptFinal(), EVP_DecryptFinal() and EVP_CipherFinal() behave in a
-similar way to EVP_EncryptFinal_ex(), EVP_DecryptFinal_ex() and
-EVP_CipherFinal_ex() except B<ctx> is automatically cleaned up 
-after the call.
+EVP_EncryptFinal(), EVP_DecryptFinal() and EVP_CipherFinal() are
+identical to EVP_EncryptFinal_ex(), EVP_DecryptFinal_ex() and
+EVP_CipherFinal_ex(). In previous releases they also cleaned up
+the B<ctx>, but this is no longer done and EVP_CIPHER_CTX_clean()
+must be called to free any context resources.
 
 EVP_get_cipherbyname(), EVP_get_cipherbynid() and EVP_get_cipherbyobj()
 return an EVP_CIPHER structure when passed a cipher name, a NID or an
diff --git a/crypto/openssl/doc/crypto/EVP_PKEY_cmp.pod b/crypto/openssl/doc/crypto/EVP_PKEY_cmp.pod
index 0ff027c0d5f9..f8e7ff1039ee 100644
--- a/crypto/openssl/doc/crypto/EVP_PKEY_cmp.pod
+++ b/crypto/openssl/doc/crypto/EVP_PKEY_cmp.pod
@@ -21,7 +21,9 @@ parameters of B<pkey> are missing and 0 if they are present or the algorithm
 doesn't use parameters.
 
 The function EVP_PKEY_copy_parameters() copies the parameters from key
-B<from> to key B<to>.
+B<from> to key B<to>. An error is returned if the parameters are missing in
+B<from> or present in both B<from> and B<to> and mismatch. If the parameters
+in B<from> and B<to> are both present and match this function has no effect.
 
 The function EVP_PKEY_cmp_parameters() compares the parameters of keys
 B<a> and B<b>.
diff --git a/crypto/openssl/doc/crypto/OBJ_nid2obj.pod b/crypto/openssl/doc/crypto/OBJ_nid2obj.pod
index 1e45dd40f6bb..b8d289673dee 100644
--- a/crypto/openssl/doc/crypto/OBJ_nid2obj.pod
+++ b/crypto/openssl/doc/crypto/OBJ_nid2obj.pod
@@ -33,6 +33,12 @@ functions
 
 The ASN1 object utility functions process ASN1_OBJECT structures which are
 a representation of the ASN1 OBJECT IDENTIFIER (OID) type.
+For convenience, OIDs are usually represented in source code as numeric
+identifiers, or B<NID>s.  OpenSSL has an internal table of OIDs that
+are generated when the library is built, and their corresponding NIDs
+are available as defined constants.  For the functions below, application
+code should treat all returned values -- OIDs, NIDs, or names -- as
+constants.
 
 OBJ_nid2obj(), OBJ_nid2ln() and OBJ_nid2sn() convert the NID B<n> to 
 an ASN1_OBJECT structure, its long name and its short name respectively,
@@ -96,6 +102,16 @@ Objects do not need to be in the internal tables to be processed,
 the functions OBJ_txt2obj() and OBJ_obj2txt() can process the numerical
 form of an OID.
 
+Some objects are used to represent algorithms which do not have a
+corresponding ASN.1 OBJECT IDENTIFIER encoding (for example no OID currently
+exists for a particular algorithm). As a result they B<cannot> be encoded or
+decoded as part of ASN.1 structures. Applications can determine if there
+is a corresponding OBJECT IDENTIFIER by checking OBJ_length() is not zero.
+
+These functions cannot return B<const> because an B<ASN1_OBJECT> can
+represent both an internal, constant, OID and a dynamically-created one.
+The latter cannot be constant because it needs to be freed after use.
+
 =head1 EXAMPLES
 
 Create an object for B<commonName>:
@@ -106,12 +122,13 @@ Create an object for B<commonName>:
 Check if an object is B<commonName>
 
  if (OBJ_obj2nid(obj) == NID_commonName)
-	/* Do something */
+        /* Do something */
 
 Create a new NID and initialize an object from it:
 
  int new_nid;
  ASN1_OBJECT *obj;
+
  new_nid = OBJ_create("1.2.3.4", "NewOID", "New Object Identifier");
 
  obj = OBJ_nid2obj(new_nid);
@@ -133,6 +150,8 @@ than enough to handle any OID encountered in practice.
 
 OBJ_nid2obj() returns an B<ASN1_OBJECT> structure or B<NULL> is an
 error occurred.
+It returns a pointer to an internal table and does not
+allocate memory; ASN1_OBJECT_free() will have no effect.
 
 OBJ_nid2ln() and OBJ_nid2sn() returns a valid string or B<NULL>
 on error.
diff --git a/crypto/openssl/doc/crypto/OPENSSL_config.pod b/crypto/openssl/doc/crypto/OPENSSL_config.pod
index 2d25b2669512..4e713653d09c 100644
--- a/crypto/openssl/doc/crypto/OPENSSL_config.pod
+++ b/crypto/openssl/doc/crypto/OPENSSL_config.pod
@@ -8,15 +8,14 @@ OPENSSL_config, OPENSSL_no_config - simple OpenSSL configuration functions
 
  #include <openssl/conf.h>
 
- void OPENSSL_config(const char *config_name);
+ void OPENSSL_config(const char *appname);
  void OPENSSL_no_config(void);
 
 =head1 DESCRIPTION
 
-OPENSSL_config() configures OpenSSL using the standard B<openssl.cnf>
-configuration file name using B<config_name>. If B<config_name> is NULL then
-the file specified in the environment variable B<OPENSSL_CONF> will be used,
-and if that is not set then a system default location is used.
+OPENSSL_config() configures OpenSSL using the standard B<openssl.cnf> and
+reads from the application section B<appname>. If B<appname> is NULL then
+the default section, B<openssl_conf>, will be used.
 Errors are silently ignored.
 Multiple calls have no effect.
 
diff --git a/crypto/openssl/doc/crypto/OPENSSL_ia32cap.pod b/crypto/openssl/doc/crypto/OPENSSL_ia32cap.pod
index 90156d21901b..5bcb82e3cfed 100644
--- a/crypto/openssl/doc/crypto/OPENSSL_ia32cap.pod
+++ b/crypto/openssl/doc/crypto/OPENSSL_ia32cap.pod
@@ -6,7 +6,7 @@ OPENSSL_ia32cap, OPENSSL_ia32cap_loc - the IA-32 processor capabilities vector
 
 =head1 SYNOPSIS
 
- unsigned int *OPENSSL_ia32cap_loc(void);
+ unsigned long *OPENSSL_ia32cap_loc(void);
  #define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])
 
 =head1 DESCRIPTION
diff --git a/crypto/openssl/doc/crypto/X509_verify_cert.pod b/crypto/openssl/doc/crypto/X509_verify_cert.pod
index a22e44118cfc..4689e3afea4e 100644
--- a/crypto/openssl/doc/crypto/X509_verify_cert.pod
+++ b/crypto/openssl/doc/crypto/X509_verify_cert.pod
@@ -31,12 +31,13 @@ Applications rarely call this function directly but it is used by
 OpenSSL internally for certificate validation, in both the S/MIME and
 SSL/TLS code.
 
-The negative return value from X509_verify_cert() can only occur if no
-certificate is set in B<ctx> (due to a programming error); if X509_verify_cert()
-twice without reinitialising B<ctx> in between; or if a retry
-operation is requested during internal lookups (which never happens with
-standard lookup methods). It is however recommended that application check
-for <= 0 return value on error.
+A negative return value from X509_verify_cert() can occur if it is invoked
+incorrectly, such as with no certificate set in B<ctx>, or when it is called
+twice in succession without reinitialising B<ctx> for the second call.
+A negative return value can also happen due to internal resource problems or if
+a retry operation is requested during internal lookups (which never happens
+with standard lookup methods).
+Applications must check for <= 0 return value on error.
 
 =head1 BUGS
 
diff --git a/crypto/openssl/doc/crypto/d2i_PrivateKey.pod b/crypto/openssl/doc/crypto/d2i_PrivateKey.pod
new file mode 100644
index 000000000000..e06ab6c5dee8
--- /dev/null
+++ b/crypto/openssl/doc/crypto/d2i_PrivateKey.pod
@@ -0,0 +1,59 @@
+=pod
+
+=head1 NAME
+
+d2i_Private_key, d2i_AutoPrivateKey, i2d_PrivateKey - decode and encode
+functions for reading and saving EVP_PKEY structures.
+
+=head1 SYNOPSIS
+
+ #include <openssl/evp.h>
+
+ EVP_PKEY *d2i_PrivateKey(int type, EVP_PKEY **a, const unsigned char **pp,
+                          long length);
+ EVP_PKEY *d2i_AutoPrivateKey(EVP_PKEY **a, const unsigned char **pp,
+                              long length);
+ int i2d_PrivateKey(EVP_PKEY *a, unsigned char **pp);
+
+=head1 DESCRIPTION
+
+d2i_PrivateKey() decodes a private key using algorithm B<type>. It attempts to
+use any key specific format or PKCS#8 unencrypted PrivateKeyInfo format. The
+B<type> parameter should be a public key algorithm constant such as
+B<EVP_PKEY_RSA>. An error occurs if the decoded key does not match B<type>.
+
+d2i_AutoPrivateKey() is similar to d2i_PrivateKey() except it attempts to
+automatically detect the private key format.
+
+i2d_PrivateKey() encodes B<key>. It uses a key specific format or, if none is
+defined for that key type, PKCS#8 unencrypted PrivateKeyInfo format.
+
+These functions are similar to the d2i_X509() functions, and you should refer to
+that page for a detailed description (see L<d2i_X509(3)>).
+
+=head1 NOTES
+
+All these functions use DER format and unencrypted keys. Applications wishing
+to encrypt or decrypt private keys should use other functions such as
+d2i_PKC8PrivateKey() instead.
+
+If the B<*a> is not NULL when calling d2i_PrivateKey() or d2i_AutoPrivateKey()
+(i.e. an existing structure is being reused) and the key format is PKCS#8
+then B<*a> will be freed and replaced on a successful call.
+
+=head1 RETURN VALUES
+
+d2i_PrivateKey() and d2i_AutoPrivateKey() return a valid B<EVP_KEY> structure
+or B<NULL> if an error occurs. The error code can be obtained by calling
+L<ERR_get_error(3)>.
+
+i2d_PrivateKey() returns the number of bytes successfully encoded or a
+negative value if an error occurs. The error code can be obtained by calling
+L<ERR_get_error(3)>.
+
+=head1 SEE ALSO
+
+L<crypto(3)>,
+L<d2i_PKCS8PrivateKey(3)>
+
+=cut
diff --git a/crypto/openssl/doc/crypto/d2i_X509.pod b/crypto/openssl/doc/crypto/d2i_X509.pod
index 5b7c16fd0316..2743bc73e70e 100644
--- a/crypto/openssl/doc/crypto/d2i_X509.pod
+++ b/crypto/openssl/doc/crypto/d2i_X509.pod
@@ -9,8 +9,10 @@ i2d_X509_fp - X509 encode and decode functions
 
  #include <openssl/x509.h>
 
- X509 *d2i_X509(X509 **px, const unsigned char **in, int len);
+ X509 *d2i_X509(X509 **px, const unsigned char **in, long len);
+ X509 *d2i_X509_AUX(X509 **px, const unsigned char **in, long len);
  int i2d_X509(X509 *x, unsigned char **out);
+ int i2d_X509_AUX(X509 *x, unsigned char **out);
 
  X509 *d2i_X509_bio(BIO *bp, X509 **x);
  X509 *d2i_X509_fp(FILE *fp, X509 **x);
@@ -37,6 +39,11 @@ below, and the discussion in the RETURN VALUES section).
 If the call is successful B<*in> is incremented to the byte following the
 parsed data.
 
+d2i_X509_AUX() is similar to d2i_X509() but the input is expected to consist of
+an X509 certificate followed by auxiliary trust information.
+This is used by the PEM routines to read "TRUSTED CERTIFICATE" objects.
+This function should not be called on untrusted input.
+
 i2d_X509() encodes the structure pointed to by B<x> into DER format.
 If B<out> is not B<NULL> is writes the DER encoded data to the buffer
 at B<*out>, and increments it to point after the data just written.
@@ -48,6 +55,11 @@ allocated for a buffer and the encoded data written to it. In this
 case B<*out> is not incremented and it points to the start of the
 data just written.
 
+i2d_X509_AUX() is similar to i2d_X509(), but the encoded output contains both
+the certificate and any auxiliary trust information.
+This is used by the PEM routines to write "TRUSTED CERTIFICATE" objects.
+Note, this is a non-standard OpenSSL-specific data format.
+
 d2i_X509_bio() is similar to d2i_X509() except it attempts
 to parse data from BIO B<bp>.
 
diff --git a/crypto/openssl/doc/crypto/hmac.pod b/crypto/openssl/doc/crypto/hmac.pod
index 58a57f47bb4f..2c8f20a20188 100644
--- a/crypto/openssl/doc/crypto/hmac.pod
+++ b/crypto/openssl/doc/crypto/hmac.pod
@@ -60,13 +60,17 @@ function B<evp_md> and the key B<key> which is B<key_len> bytes
 long. It is deprecated and only included for backward compatibility
 with OpenSSL 0.9.6b.
 
-HMAC_Init_ex() initializes or reuses a B<HMAC_CTX> structure to use
-the function B<evp_md> and key B<key>. Either can be NULL, in which
-case the existing one will be reused. HMAC_CTX_init() must have been
-called before the first use of an B<HMAC_CTX> in this
-function. B<N.B. HMAC_Init() had this undocumented behaviour in
-previous versions of OpenSSL - failure to switch to HMAC_Init_ex() in
-programs that expect it will cause them to stop working>.
+HMAC_Init_ex() initializes or reuses a B<HMAC_CTX> structure to use the hash
+function B<evp_md> and key B<key>. If both are NULL (or B<evp_md> is the same
+as the previous digest used by B<ctx> and B<key> is NULL) the existing key is
+reused. B<ctx> must have been created with HMAC_CTX_new() before the first use
+of an B<HMAC_CTX> in this function. B<N.B. HMAC_Init() had this undocumented
+behaviour in previous versions of OpenSSL - failure to switch to HMAC_Init_ex()
+in programs that expect it will cause them to stop working>.
+
+B<NB: if HMAC_Init_ex() is called with B<key> NULL and B<evp_md> is not the
+same as the previous digest used by B<ctx> then an error is returned
+because reuse of an existing key with a different digest is not supported.>
 
 HMAC_Update() can be called repeatedly with chunks of the message to
 be authenticated (B<len> bytes at B<data>).
diff --git a/crypto/openssl/doc/crypto/rand.pod b/crypto/openssl/doc/crypto/rand.pod
index d102df2eee80..b754854bcf05 100644
--- a/crypto/openssl/doc/crypto/rand.pod
+++ b/crypto/openssl/doc/crypto/rand.pod
@@ -14,7 +14,7 @@ rand - pseudo-random number generator
  int  RAND_pseudo_bytes(unsigned char *buf, int num);
 
  void RAND_seed(const void *buf, int num);
- void RAND_add(const void *buf, int num, int entropy);
+ void RAND_add(const void *buf, int num, double entropy);
  int  RAND_status(void);
 
  int  RAND_load_file(const char *file, long max_bytes);
diff --git a/crypto/openssl/doc/crypto/ui.pod b/crypto/openssl/doc/crypto/ui.pod
index 04f8e9c360a8..2e94d8c0f689 100644
--- a/crypto/openssl/doc/crypto/ui.pod
+++ b/crypto/openssl/doc/crypto/ui.pod
@@ -109,12 +109,12 @@ that's connected to it, like duplicated input strings, results and others.
 
 UI_add_input_string() and UI_add_verify_string() add a prompt to the UI,
 as well as flags and a result buffer and the desired minimum and maximum
-sizes of the result.  The given information is used to prompt for
-information, for example a password, and to verify a password (i.e. having
-the user enter it twice and check that the same string was entered twice).
-UI_add_verify_string() takes and extra argument that should be a pointer
-to the result buffer of the input string that it's supposed to verify, or
-verification will fail.
+sizes of the result, not counting the final NUL character.  The given
+information is used to prompt for information, for example a password,
+and to verify a password (i.e. having the user enter it twice and check
+that the same string was entered twice).  UI_add_verify_string() takes
+and extra argument that should be a pointer to the result buffer of the
+input string that it's supposed to verify, or verification will fail.
 
 UI_add_input_boolean() adds a prompt to the UI that's supposed to be answered
 in a boolean way, with a single character for yes and a different character
diff --git a/crypto/openssl/engines/ccgost/gost2001.c b/crypto/openssl/engines/ccgost/gost2001.c
index 9536295430d0..881d0d3c9097 100644
--- a/crypto/openssl/engines/ccgost/gost2001.c
+++ b/crypto/openssl/engines/ccgost/gost2001.c
@@ -434,8 +434,16 @@ int gost2001_compute_public(EC_KEY *ec)
 int gost2001_keygen(EC_KEY *ec)
 {
     BIGNUM *order = BN_new(), *d = BN_new();
-    const EC_GROUP *group = EC_KEY_get0_group(ec);
+    const EC_GROUP *group = NULL;
+
+    if (order == NULL || d == NULL) {
+        GOSTerr(GOST_F_GOST2001_KEYGEN, ERR_R_MALLOC_FAILURE);
+        BN_free(d);
+        BN_free(order);
+        return 0;
+    }
 
+    group = EC_KEY_get0_group(ec);
     if(!group || !EC_GROUP_get_order(group, order, NULL)) {
         GOSTerr(GOST_F_GOST2001_KEYGEN, ERR_R_INTERNAL_ERROR);
         BN_free(d);
diff --git a/crypto/openssl/engines/ccgost/gost2001_keyx.c b/crypto/openssl/engines/ccgost/gost2001_keyx.c
index db1bdc18fd76..ac7862eab550 100644
--- a/crypto/openssl/engines/ccgost/gost2001_keyx.c
+++ b/crypto/openssl/engines/ccgost/gost2001_keyx.c
@@ -147,6 +147,8 @@ int pkey_GOST01cp_encrypt(EVP_PKEY_CTX *pctx, unsigned char *out,
         key_is_ephemeral = 1;
         if (out) {
             sec_key = EVP_PKEY_new();
+            if (sec_key == NULL)
+                goto err;
             EVP_PKEY_assign(sec_key, EVP_PKEY_base_id(pubk), EC_KEY_new());
             EVP_PKEY_copy_parameters(sec_key, pubk);
             if (!gost2001_keygen(EVP_PKEY_get0(sec_key))) {
diff --git a/crypto/openssl/engines/ccgost/gost94_keyx.c b/crypto/openssl/engines/ccgost/gost94_keyx.c
index ce57f17cbf32..3532bfff3e96 100644
--- a/crypto/openssl/engines/ccgost/gost94_keyx.c
+++ b/crypto/openssl/engines/ccgost/gost94_keyx.c
@@ -126,6 +126,8 @@ int pkey_GOST94cp_encrypt(EVP_PKEY_CTX *ctx, unsigned char *out,
         key_is_ephemeral = 1;
         if (out) {
             mykey = EVP_PKEY_new();
+            if (!mykey)
+                goto memerr;
             EVP_PKEY_assign(mykey, EVP_PKEY_base_id(pubk), DSA_new());
             EVP_PKEY_copy_parameters(mykey, pubk);
             if (!gost_sign_keygen(EVP_PKEY_get0(mykey))) {
diff --git a/crypto/openssl/engines/ccgost/gost_ameth.c b/crypto/openssl/engines/ccgost/gost_ameth.c
index b7c5354c1ae2..8283f192f4aa 100644
--- a/crypto/openssl/engines/ccgost/gost_ameth.c
+++ b/crypto/openssl/engines/ccgost/gost_ameth.c
@@ -617,6 +617,10 @@ static int pub_decode_gost94(EVP_PKEY *pk, X509_PUBKEY *pub)
         return 0;
     }
     databuf = OPENSSL_malloc(octet->length);
+    if (databuf == NULL) {
+        GOSTerr(GOST_F_PUB_DECODE_GOST94, ERR_R_MALLOC_FAILURE);
+        return 0;
+    }
     for (i = 0, j = octet->length - 1; i < octet->length; i++, j--) {
         databuf[j] = octet->data[i];
     }
@@ -646,6 +650,8 @@ static int pub_encode_gost94(X509_PUBKEY *pub, const EVP_PKEY *pk)
     }
     data_len = BN_num_bytes(dsa->pub_key);
     databuf = OPENSSL_malloc(data_len);
+    if (databuf == NULL)
+        return 0;
     BN_bn2bin(dsa->pub_key, databuf);
     octet = ASN1_OCTET_STRING_new();
     ASN1_STRING_set(octet, NULL, data_len);
@@ -686,6 +692,10 @@ static int pub_decode_gost01(EVP_PKEY *pk, X509_PUBKEY *pub)
         return 0;
     }
     databuf = OPENSSL_malloc(octet->length);
+    if (databuf == NULL) {
+        GOSTerr(GOST_F_PUB_DECODE_GOST01, ERR_R_MALLOC_FAILURE);
+        return 0;
+    }
     for (i = 0, j = octet->length - 1; i < octet->length; i++, j--) {
         databuf[j] = octet->data[i];
     }
@@ -760,6 +770,10 @@ static int pub_encode_gost01(X509_PUBKEY *pub, const EVP_PKEY *pk)
     data_len = 2 * BN_num_bytes(order);
     BN_free(order);
     databuf = OPENSSL_malloc(data_len);
+    if (databuf == NULL) {
+        GOSTerr(GOST_F_PUB_ENCODE_GOST01, ERR_R_MALLOC_FAILURE);
+        return 0;
+    }
     memset(databuf, 0, data_len);
 
     store_bignum(X, databuf + data_len / 2, data_len / 2);
diff --git a/crypto/openssl/engines/ccgost/gost_pmeth.c b/crypto/openssl/engines/ccgost/gost_pmeth.c
index 4a79a85cfc62..696829253b62 100644
--- a/crypto/openssl/engines/ccgost/gost_pmeth.c
+++ b/crypto/openssl/engines/ccgost/gost_pmeth.c
@@ -107,6 +107,8 @@ static int pkey_gost_ctrl(EVP_PKEY_CTX *ctx, int type, int p1, void *p2)
         return 1;
     case EVP_PKEY_CTRL_SET_IV:
         pctx->shared_ukm = OPENSSL_malloc((int)p1);
+        if (pctx->shared_ukm == NULL)
+            return 0;
         memcpy(pctx->shared_ukm, p2, (int)p1);
         return 1;
     case EVP_PKEY_CTRL_PEER_KEY:
@@ -533,6 +535,8 @@ static int pkey_gost_mac_keygen(EVP_PKEY_CTX *ctx, EVP_PKEY *pkey)
         return 0;
     }
     keydata = OPENSSL_malloc(32);
+    if (keydata == NULL)
+        return 0;
     memcpy(keydata, data->key, 32);
     EVP_PKEY_assign(pkey, NID_id_Gost28147_89_MAC, keydata);
     return 1;
diff --git a/crypto/openssl/engines/e_4758cca.c b/crypto/openssl/engines/e_4758cca.c
index 5f771986cfae..60ba4abcdfaf 100644
--- a/crypto/openssl/engines/e_4758cca.c
+++ b/crypto/openssl/engines/e_4758cca.c
@@ -463,6 +463,10 @@ static EVP_PKEY *ibm_4758_load_privkey(ENGINE *e, const char *key_id,
 
     (*(long *)keyToken) = keyTokenLength;
     rtmp = RSA_new_method(e);
+    if (rtmp == NULL) {
+        CCA4758err(CCA4758_F_IBM_4758_LOAD_PRIVKEY, ERR_R_MALLOC_FAILURE);
+        goto err;
+    }
     RSA_set_ex_data(rtmp, hndidx, (char *)keyToken);
 
     rtmp->e = BN_bin2bn(exponent, exponentLength, NULL);
@@ -535,6 +539,10 @@ static EVP_PKEY *ibm_4758_load_pubkey(ENGINE *e, const char *key_id,
 
     (*(long *)keyToken) = keyTokenLength;
     rtmp = RSA_new_method(e);
+    if (rtmp == NULL) {
+        CCA4758err(CCA4758_F_IBM_4758_LOAD_PUBKEY, ERR_R_MALLOC_FAILURE);
+        goto err;
+    }
     RSA_set_ex_data(rtmp, hndidx, (char *)keyToken);
     rtmp->e = BN_bin2bn(exponent, exponentLength, NULL);
     rtmp->n = BN_bin2bn(modulus, modulusFieldLength, NULL);
diff --git a/crypto/openssl/engines/e_aep.c b/crypto/openssl/engines/e_aep.c
index 9bfda76a927d..4e97d29497e7 100644
--- a/crypto/openssl/engines/e_aep.c
+++ b/crypto/openssl/engines/e_aep.c
@@ -1137,7 +1137,8 @@ static AEP_RV ConvertAEPBigNum(void *ArbBigNum, AEP_U32 BigNumSize,
     /*
      * Expand the result bn so that it can hold our big num. Size is in bits
      */
-    bn_expand(bn, (int)(BigNumSize << 3));
+    if (bn_expand(bn, (int)(BigNumSize << 3)) == NULL)
+        return AEP_R_HOST_MEMORY;
 
 #  ifdef SIXTY_FOUR_BIT_LONG
     bn->top = BigNumSize >> 3;
diff --git a/crypto/openssl/engines/e_capi.c b/crypto/openssl/engines/e_capi.c
index 6e524633f3f0..8c08872bfdf4 100644
--- a/crypto/openssl/engines/e_capi.c
+++ b/crypto/openssl/engines/e_capi.c
@@ -1106,6 +1106,10 @@ static int capi_get_provname(CAPI_CTX * ctx, LPSTR * pname, DWORD * ptype,
         name = alloca(len);
     else
         name = OPENSSL_malloc(len);
+    if (name == NULL) {
+        CAPIerr(CAPI_F_CAPI_GET_PROVNAME, ERR_R_MALLOC_FAILURE);
+        return 0;
+    }
     if (!CryptEnumProviders(idx, NULL, 0, ptype, name, &len)) {
         err = GetLastError();
         if (err == ERROR_NO_MORE_ITEMS)
@@ -1286,6 +1290,10 @@ char *capi_cert_get_fname(CAPI_CTX * ctx, PCCERT_CONTEXT cert)
         (cert, CERT_FRIENDLY_NAME_PROP_ID, NULL, &dlen))
         return NULL;
     wfname = OPENSSL_malloc(dlen);
+    if (wfname == NULL) {
+        CAPIerr(CAPI_F_CAPI_CERT_GET_FNAME, ERR_R_MALLOC_FAILURE);
+        return NULL;
+    }
     if (CertGetCertificateContextProperty
         (cert, CERT_FRIENDLY_NAME_PROP_ID, wfname, &dlen)) {
         char *fname = wide_to_asc(wfname);
@@ -1436,6 +1444,11 @@ static CAPI_KEY *capi_get_key(CAPI_CTX * ctx, const TCHAR *contname,
     CAPI_KEY *key;
     DWORD dwFlags = 0;
     key = OPENSSL_malloc(sizeof(CAPI_KEY));
+    if (key == NULL) {
+        CAPIerr(CAPI_F_CAPI_GET_KEY, ERR_R_MALLOC_FAILURE);
+        capi_addlasterror();
+        goto err;
+    }
     if (sizeof(TCHAR) == sizeof(char))
         CAPI_trace(ctx, "capi_get_key, contname=%s, provname=%s, type=%d\n",
                    contname, provname, ptype);
diff --git a/crypto/openssl/engines/e_chil.c b/crypto/openssl/engines/e_chil.c
index 5dfab5134527..d5e4cb67c440 100644
--- a/crypto/openssl/engines/e_chil.c
+++ b/crypto/openssl/engines/e_chil.c
@@ -810,9 +810,17 @@ static EVP_PKEY *hwcrhk_load_privkey(ENGINE *eng, const char *key_id,
 #  endif
 #  ifndef OPENSSL_NO_RSA
     rtmp = RSA_new_method(eng);
+    if (rtmp == NULL) {
+        HWCRHKerr(HWCRHK_F_HWCRHK_LOAD_PRIVKEY, ERR_R_MALLOC_FAILURE);
+        goto err;
+    }
     RSA_set_ex_data(rtmp, hndidx_rsa, (char *)hptr);
     rtmp->e = BN_new();
     rtmp->n = BN_new();
+    if (rtmp->e == NULL || rtmp->n == NULL) {
+        HWCRHKerr(HWCRHK_F_HWCRHK_LOAD_PRIVKEY, ERR_R_MALLOC_FAILURE);
+        goto err;
+    }
     rtmp->flags |= RSA_FLAG_EXT_PKEY;
     MPI2BN(rtmp->e, e);
     MPI2BN(rtmp->n, n);
@@ -823,8 +831,14 @@ static EVP_PKEY *hwcrhk_load_privkey(ENGINE *eng, const char *key_id,
         goto err;
     }
 
-    bn_expand2(rtmp->e, e.size / sizeof(BN_ULONG));
-    bn_expand2(rtmp->n, n.size / sizeof(BN_ULONG));
+    if (bn_expand2(rtmp->e, e.size / sizeof(BN_ULONG)) == NULL) {
+        HWCRHKerr(HWCRHK_F_HWCRHK_LOAD_PRIVKEY, ERR_R_MALLOC_FAILURE);
+        goto err;
+    }
+    if (bn_expand2(rtmp->n, n.size / sizeof(BN_ULONG)) == NULL) {
+        HWCRHKerr(HWCRHK_F_HWCRHK_LOAD_PRIVKEY, ERR_R_MALLOC_FAILURE);
+        goto err;
+    }
     MPI2BN(rtmp->e, e);
     MPI2BN(rtmp->n, n);
 
@@ -923,7 +937,10 @@ static int hwcrhk_mod_exp(BIGNUM *r, const BIGNUM *a, const BIGNUM *p,
         goto err;
     }
     /* Prepare the params */
-    bn_expand2(r, m->top);      /* Check for error !! */
+    if (bn_expand2(r, m->top) == NULL) {     /* Check for error !! */
+        HWCRHKerr(HWCRHK_F_HWCRHK_MOD_EXP, ERR_R_MALLOC_FAILURE);
+        goto err;
+    }
     BN2MPI(m_a, a);
     BN2MPI(m_p, p);
     BN2MPI(m_n, m);
@@ -989,7 +1006,10 @@ static int hwcrhk_rsa_mod_exp(BIGNUM *r, const BIGNUM *I, RSA *rsa,
         }
 
         /* Prepare the params */
-        bn_expand2(r, rsa->n->top); /* Check for error !! */
+        if (bn_expand2(r, rsa->n->top) == NULL) { /* Check for error !! */
+            HWCRHKerr(HWCRHK_F_HWCRHK_RSA_MOD_EXP, ERR_R_MALLOC_FAILURE);
+            goto err;
+        }
         BN2MPI(m_a, I);
         MPI2BN(r, m_r);
 
@@ -1026,7 +1046,10 @@ static int hwcrhk_rsa_mod_exp(BIGNUM *r, const BIGNUM *I, RSA *rsa,
         }
 
         /* Prepare the params */
-        bn_expand2(r, rsa->n->top); /* Check for error !! */
+        if (bn_expand2(r, rsa->n->top) == NULL) { /* Check for error !! */
+            HWCRHKerr(HWCRHK_F_HWCRHK_RSA_MOD_EXP, ERR_R_MALLOC_FAILURE);
+            goto err;
+        }
         BN2MPI(m_a, I);
         BN2MPI(m_p, rsa->p);
         BN2MPI(m_q, rsa->q);
@@ -1272,7 +1295,7 @@ static int hwcrhk_insert_card(const char *prompt_info,
     ui = UI_new_method(ui_method);
 
     if (ui) {
-        char answer;
+        char answer = '\0';
         char buf[BUFSIZ];
         /*
          * Despite what the documentation says wrong_info can be an empty
diff --git a/crypto/openssl/ssl/Makefile b/crypto/openssl/ssl/Makefile
index b6dee5b5ea52..dd1296225006 100644
--- a/crypto/openssl/ssl/Makefile
+++ b/crypto/openssl/ssl/Makefile
@@ -15,7 +15,7 @@ KRB5_INCLUDES=
 CFLAGS= $(INCLUDES) $(CFLAG)
 
 GENERAL=Makefile README ssl-lib.com install.com
-TEST=ssltest.c heartbeat_test.c clienthellotest.c sslv2conftest.c
+TEST=ssltest.c heartbeat_test.c clienthellotest.c sslv2conftest.c dtlstest.c bad_dtls_test.c
 APPS=
 
 LIB=$(TOP)/libssl.a
diff --git a/crypto/openssl/ssl/bad_dtls_test.c b/crypto/openssl/ssl/bad_dtls_test.c
new file mode 100644
index 000000000000..d42817fc329e
--- /dev/null
+++ b/crypto/openssl/ssl/bad_dtls_test.c
@@ -0,0 +1,923 @@
+/*
+ * Copyright 2016 The OpenSSL Project Authors. All Rights Reserved.
+ *
+ * Licensed under the OpenSSL license (the "License").  You may not use
+ * this file except in compliance with the License.  You can obtain a copy
+ * in the file LICENSE in the source distribution or at
+ * https://www.openssl.org/source/license.html
+ */
+
+/*
+ * Unit test for Cisco DTLS1_BAD_VER session resume, as used by
+ * AnyConnect VPN protocol.
+ *
+ * This is designed to exercise the code paths in
+ * http://git.infradead.org/users/dwmw2/openconnect.git/blob/HEAD:/dtls.c
+ * which have frequently been affected by regressions in DTLS1_BAD_VER
+ * support.
+ *
+ * Note that unlike other SSL tests, we don't test against our own SSL
+ * server method. Firstly because we don't have one; we *only* support
+ * DTLS1_BAD_VER as a client. And secondly because even if that were
+ * fixed up it's the wrong thing to test against — because if changes
+ * are made in generic DTLS code which don't take DTLS1_BAD_VER into
+ * account, there's plenty of scope for making those changes such that
+ * they break *both* the client and the server in the same way.
+ *
+ * So we handle the server side manually. In a session resume there isn't
+ * much to be done anyway.
+ */
+#include <string.h>
+
+/* On Windows this will include <winsock2.h> and thus it needs to be
+ * included *before* anything that includes <windows.h>. Ick. */
+#include "e_os.h" /* for 'inline' */
+
+#include <openssl/bio.h>
+#include <openssl/crypto.h>
+#include <openssl/evp.h>
+#include <openssl/ssl.h>
+#include <openssl/err.h>
+#include <openssl/rand.h>
+
+/* PACKET functions lifted from OpenSSL 1.1's ssl/packet_locl.h */
+typedef struct {
+    /* Pointer to where we are currently reading from */
+    const unsigned char *curr;
+    /* Number of bytes remaining */
+    size_t remaining;
+} PACKET;
+
+/* Internal unchecked shorthand; don't use outside this file. */
+static inline void packet_forward(PACKET *pkt, size_t len)
+{
+    pkt->curr += len;
+    pkt->remaining -= len;
+}
+
+/*
+ * Returns the number of bytes remaining to be read in the PACKET
+ */
+static inline size_t PACKET_remaining(const PACKET *pkt)
+{
+    return pkt->remaining;
+}
+
+/*
+ * Initialise a PACKET with |len| bytes held in |buf|. This does not make a
+ * copy of the data so |buf| must be present for the whole time that the PACKET
+ * is being used.
+ */
+static inline int PACKET_buf_init(PACKET *pkt,
+                                              const unsigned char *buf,
+                                              size_t len)
+{
+    /* Sanity check for negative values. */
+    if (len > (size_t)65536)
+        return 0;
+
+    pkt->curr = buf;
+    pkt->remaining = len;
+    return 1;
+}
+
+/*
+ * Returns 1 if the packet has length |num| and its contents equal the |num|
+ * bytes read from |ptr|. Returns 0 otherwise (lengths or contents not equal).
+ * If lengths are equal, performs the comparison in constant time.
+ */
+static inline int PACKET_equal(const PACKET *pkt, const void *ptr,
+                                           size_t num)
+{
+    if (PACKET_remaining(pkt) != num)
+        return 0;
+    return CRYPTO_memcmp(pkt->curr, ptr, num) == 0;
+}
+
+/*
+ * Peek ahead at 2 bytes in network order from |pkt| and store the value in
+ * |*data|
+ */
+static inline int PACKET_peek_net_2(const PACKET *pkt,
+                                                unsigned int *data)
+{
+    if (PACKET_remaining(pkt) < 2)
+        return 0;
+
+    *data = ((unsigned int)(*pkt->curr)) << 8;
+    *data |= *(pkt->curr + 1);
+
+    return 1;
+}
+
+/* Equivalent of n2s */
+/* Get 2 bytes in network order from |pkt| and store the value in |*data| */
+static inline int PACKET_get_net_2(PACKET *pkt,
+                                               unsigned int *data)
+{
+    if (!PACKET_peek_net_2(pkt, data))
+        return 0;
+
+    packet_forward(pkt, 2);
+
+    return 1;
+}
+
+/* Peek ahead at 1 byte from |pkt| and store the value in |*data| */
+static inline int PACKET_peek_1(const PACKET *pkt,
+                                            unsigned int *data)
+{
+    if (!PACKET_remaining(pkt))
+        return 0;
+
+    *data = *pkt->curr;
+
+    return 1;
+}
+
+/* Get 1 byte from |pkt| and store the value in |*data| */
+static inline int PACKET_get_1(PACKET *pkt, unsigned int *data)
+{
+    if (!PACKET_peek_1(pkt, data))
+        return 0;
+
+    packet_forward(pkt, 1);
+
+    return 1;
+}
+
+/*
+ * Peek ahead at |len| bytes from the |pkt| and store a pointer to them in
+ * |*data|. This just points at the underlying buffer that |pkt| is using. The
+ * caller should not free this data directly (it will be freed when the
+ * underlying buffer gets freed
+ */
+static inline int PACKET_peek_bytes(const PACKET *pkt,
+                                                const unsigned char **data,
+                                                size_t len)
+{
+    if (PACKET_remaining(pkt) < len)
+        return 0;
+
+    *data = pkt->curr;
+
+    return 1;
+}
+
+/*
+ * Read |len| bytes from the |pkt| and store a pointer to them in |*data|. This
+ * just points at the underlying buffer that |pkt| is using. The caller should
+ * not free this data directly (it will be freed when the underlying buffer gets
+ * freed
+ */
+static inline int PACKET_get_bytes(PACKET *pkt,
+                                               const unsigned char **data,
+                                               size_t len)
+{
+    if (!PACKET_peek_bytes(pkt, data, len))
+        return 0;
+
+    packet_forward(pkt, len);
+
+    return 1;
+}
+
+/* Peek ahead at |len| bytes from |pkt| and copy them to |data| */
+static inline int PACKET_peek_copy_bytes(const PACKET *pkt,
+                                                     unsigned char *data,
+                                                     size_t len)
+{
+    if (PACKET_remaining(pkt) < len)
+        return 0;
+
+    memcpy(data, pkt->curr, len);
+
+    return 1;
+}
+
+/*
+ * Read |len| bytes from |pkt| and copy them to |data|.
+ * The caller is responsible for ensuring that |data| can hold |len| bytes.
+ */
+static inline int PACKET_copy_bytes(PACKET *pkt,
+                                                unsigned char *data,
+                                                size_t len)
+{
+    if (!PACKET_peek_copy_bytes(pkt, data, len))
+        return 0;
+
+    packet_forward(pkt, len);
+
+    return 1;
+}
+
+
+/* Move the current reading position forward |len| bytes */
+static inline int PACKET_forward(PACKET *pkt, size_t len)
+{
+    if (PACKET_remaining(pkt) < len)
+        return 0;
+
+    packet_forward(pkt, len);
+
+    return 1;
+}
+
+/*
+ * Reads a variable-length vector prefixed with a one-byte length, and stores
+ * the contents in |subpkt|. |pkt| can equal |subpkt|.
+ * Data is not copied: the |subpkt| packet will share its underlying buffer with
+ * the original |pkt|, so data wrapped by |pkt| must outlive the |subpkt|.
+ * Upon failure, the original |pkt| and |subpkt| are not modified.
+ */
+static inline int PACKET_get_length_prefixed_1(PACKET *pkt,
+                                                           PACKET *subpkt)
+{
+    unsigned int length;
+    const unsigned char *data;
+    PACKET tmp = *pkt;
+    if (!PACKET_get_1(&tmp, &length) ||
+        !PACKET_get_bytes(&tmp, &data, (size_t)length)) {
+        return 0;
+    }
+
+    *pkt = tmp;
+    subpkt->curr = data;
+    subpkt->remaining = length;
+
+    return 1;
+}
+
+#define OSSL_NELEM(x)    (sizeof(x)/sizeof(x[0]))
+
+/* For DTLS1_BAD_VER packets the MAC doesn't include the handshake header */
+#define MAC_OFFSET (DTLS1_RT_HEADER_LENGTH + DTLS1_HM_HEADER_LENGTH)
+
+static unsigned char client_random[SSL3_RANDOM_SIZE];
+static unsigned char server_random[SSL3_RANDOM_SIZE];
+
+/* These are all generated locally, sized purely according to our own whim */
+static unsigned char session_id[32];
+static unsigned char master_secret[48];
+static unsigned char cookie[20];
+
+/* We've hard-coded the cipher suite; we know it's 104 bytes */
+static unsigned char key_block[104];
+#define mac_key (key_block + 20)
+#define dec_key (key_block + 40)
+#define enc_key (key_block + 56)
+
+static EVP_MD_CTX handshake_md5;
+static EVP_MD_CTX handshake_sha1;
+
+/* PRF lifted from ssl/t1_enc.c since we can't easily use it directly */
+static int tls1_P_hash(const EVP_MD *md, const unsigned char *sec,
+                       int sec_len,
+                       const void *seed1, int seed1_len,
+                       const void *seed2, int seed2_len,
+                       const void *seed3, int seed3_len,
+                       unsigned char *out, int olen)
+{
+    int chunk;
+    size_t j;
+    EVP_MD_CTX ctx, ctx_tmp, ctx_init;
+    EVP_PKEY *prf_mac_key;
+    unsigned char A1[EVP_MAX_MD_SIZE];
+    size_t A1_len;
+    int ret = 0;
+
+    chunk = EVP_MD_size(md);
+    OPENSSL_assert(chunk >= 0);
+
+    EVP_MD_CTX_init(&ctx);
+    EVP_MD_CTX_init(&ctx_tmp);
+    EVP_MD_CTX_init(&ctx_init);
+    EVP_MD_CTX_set_flags(&ctx_init, EVP_MD_CTX_FLAG_NON_FIPS_ALLOW);
+    prf_mac_key = EVP_PKEY_new_mac_key(EVP_PKEY_HMAC, NULL, sec, sec_len);
+    if (!prf_mac_key)
+        goto err;
+    if (!EVP_DigestSignInit(&ctx_init, NULL, md, NULL, prf_mac_key))
+        goto err;
+    if (!EVP_MD_CTX_copy_ex(&ctx, &ctx_init))
+        goto err;
+    if (seed1 && !EVP_DigestSignUpdate(&ctx, seed1, seed1_len))
+        goto err;
+    if (seed2 && !EVP_DigestSignUpdate(&ctx, seed2, seed2_len))
+        goto err;
+    if (seed3 && !EVP_DigestSignUpdate(&ctx, seed3, seed3_len))
+        goto err;
+    if (!EVP_DigestSignFinal(&ctx, A1, &A1_len))
+        goto err;
+
+    for (;;) {
+        /* Reinit mac contexts */
+        if (!EVP_MD_CTX_copy_ex(&ctx, &ctx_init))
+            goto err;
+        if (!EVP_DigestSignUpdate(&ctx, A1, A1_len))
+            goto err;
+        if (olen > chunk && !EVP_MD_CTX_copy_ex(&ctx_tmp, &ctx))
+            goto err;
+        if (seed1 && !EVP_DigestSignUpdate(&ctx, seed1, seed1_len))
+            goto err;
+        if (seed2 && !EVP_DigestSignUpdate(&ctx, seed2, seed2_len))
+            goto err;
+        if (seed3 && !EVP_DigestSignUpdate(&ctx, seed3, seed3_len))
+            goto err;
+
+        if (olen > chunk) {
+            if (!EVP_DigestSignFinal(&ctx, out, &j))
+                goto err;
+            out += j;
+            olen -= j;
+            /* calc the next A1 value */
+            if (!EVP_DigestSignFinal(&ctx_tmp, A1, &A1_len))
+                goto err;
+        } else {                /* last one */
+
+            if (!EVP_DigestSignFinal(&ctx, A1, &A1_len))
+                goto err;
+            memcpy(out, A1, olen);
+            break;
+        }
+    }
+    ret = 1;
+ err:
+    EVP_PKEY_free(prf_mac_key);
+    EVP_MD_CTX_cleanup(&ctx);
+    EVP_MD_CTX_cleanup(&ctx_tmp);
+    EVP_MD_CTX_cleanup(&ctx_init);
+    OPENSSL_cleanse(A1, sizeof(A1));
+    return ret;
+}
+
+/* seed1 through seed5 are virtually concatenated */
+static int do_PRF(const void *seed1, int seed1_len,
+                  const void *seed2, int seed2_len,
+                  const void *seed3, int seed3_len,
+                  unsigned char *out, int olen)
+{
+    unsigned char out2[104];
+    int i, len;
+
+    if (olen > (int)sizeof(out2))
+        return 0;
+
+    len = sizeof(master_secret) / 2;
+
+    if (!tls1_P_hash(EVP_md5(), master_secret, len,
+                     seed1, seed1_len, seed2, seed2_len, seed3,
+                     seed3_len, out, olen))
+        return 0;
+
+    if (!tls1_P_hash(EVP_sha1(), master_secret + len, len,
+                     seed1, seed1_len, seed2, seed2_len, seed3,
+                     seed3_len, out2, olen))
+        return 0;
+
+    for (i = 0; i < olen; i++) {
+        out[i] ^= out2[i];
+    }
+
+    return 1;
+}
+
+static SSL_SESSION *client_session(void)
+{
+    static unsigned char session_asn1[] = {
+        0x30, 0x5F,              /* SEQUENCE, length 0x5F */
+        0x02, 0x01, 0x01,        /* INTEGER, SSL_SESSION_ASN1_VERSION */
+        0x02, 0x02, 0x01, 0x00,  /* INTEGER, DTLS1_BAD_VER */
+        0x04, 0x02, 0x00, 0x2F,  /* OCTET_STRING, AES128-SHA */
+        0x04, 0x20,              /* OCTET_STRING, session id */
+#define SS_SESSID_OFS 15 /* Session ID goes here */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x04, 0x30,              /* OCTET_STRING, master secret */
+#define SS_SECRET_OFS 49 /* Master secret goes here */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    };
+    const unsigned char *p = session_asn1;
+
+    /* Copy the randomly-generated fields into the above ASN1 */
+    memcpy(session_asn1 + SS_SESSID_OFS, session_id, sizeof(session_id));
+    memcpy(session_asn1 + SS_SECRET_OFS, master_secret, sizeof(master_secret));
+
+    return d2i_SSL_SESSION(NULL, &p, sizeof(session_asn1));
+}
+
+/* Returns 1 for initial ClientHello, 2 for ClientHello with cookie */
+static int validate_client_hello(BIO *wbio)
+{
+    PACKET pkt, pkt2;
+    long len;
+    unsigned char *data;
+    int cookie_found = 0;
+    unsigned int u;
+
+    len = BIO_get_mem_data(wbio, (char **)&data);
+    if (!PACKET_buf_init(&pkt, data, len))
+        return 0;
+
+    /* Check record header type */
+    if (!PACKET_get_1(&pkt, &u) || u != SSL3_RT_HANDSHAKE)
+        return 0;
+    /* Version */
+    if (!PACKET_get_net_2(&pkt, &u) || u != DTLS1_BAD_VER)
+        return 0;
+    /* Skip the rest of the record header */
+    if (!PACKET_forward(&pkt, DTLS1_RT_HEADER_LENGTH - 3))
+        return 0;
+
+    /* Check it's a ClientHello */
+    if (!PACKET_get_1(&pkt, &u) || u != SSL3_MT_CLIENT_HELLO)
+        return 0;
+    /* Skip the rest of the handshake message header */
+    if (!PACKET_forward(&pkt, DTLS1_HM_HEADER_LENGTH - 1))
+        return 0;
+
+    /* Check client version */
+    if (!PACKET_get_net_2(&pkt, &u) || u != DTLS1_BAD_VER)
+        return 0;
+
+    /* Store random */
+    if (!PACKET_copy_bytes(&pkt, client_random, SSL3_RANDOM_SIZE))
+        return 0;
+
+    /* Check session id length and content */
+    if (!PACKET_get_length_prefixed_1(&pkt, &pkt2) ||
+        !PACKET_equal(&pkt2, session_id, sizeof(session_id)))
+        return 0;
+
+    /* Check cookie */
+    if (!PACKET_get_length_prefixed_1(&pkt, &pkt2))
+        return 0;
+    if (PACKET_remaining(&pkt2)) {
+        if (!PACKET_equal(&pkt2, cookie, sizeof(cookie)))
+            return 0;
+        cookie_found = 1;
+    }
+
+    /* Skip ciphers */
+    if (!PACKET_get_net_2(&pkt, &u) || !PACKET_forward(&pkt, u))
+        return 0;
+
+    /* Skip compression */
+    if (!PACKET_get_1(&pkt, &u) || !PACKET_forward(&pkt, u))
+        return 0;
+
+    /* Skip extensions */
+    if (!PACKET_get_net_2(&pkt, &u) || !PACKET_forward(&pkt, u))
+        return 0;
+
+    /* Now we are at the end */
+    if (PACKET_remaining(&pkt))
+        return 0;
+
+    /* Update handshake MAC for second ClientHello (with cookie) */
+    if (cookie_found && (!EVP_DigestUpdate(&handshake_md5, data + MAC_OFFSET,
+                                           len - MAC_OFFSET) ||
+                         !EVP_DigestUpdate(&handshake_sha1, data + MAC_OFFSET,
+                                           len - MAC_OFFSET)))
+        printf("EVP_DigestUpdate() failed\n");
+
+    (void)BIO_reset(wbio);
+
+    return 1 + cookie_found;
+}
+
+static int send_hello_verify(BIO *rbio)
+{
+    static unsigned char hello_verify[] = {
+        0x16, /* Handshake */
+        0x01, 0x00, /* DTLS1_BAD_VER */
+        0x00, 0x00, /* Epoch 0 */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Seq# 0 */
+        0x00, 0x23, /* Length */
+        0x03, /* Hello Verify */
+        0x00, 0x00, 0x17, /* Length */
+        0x00, 0x00, /* Seq# 0 */
+        0x00, 0x00, 0x00, /* Fragment offset */
+        0x00, 0x00, 0x17, /* Fragment length */
+        0x01, 0x00, /* DTLS1_BAD_VER */
+        0x14, /* Cookie length */
+#define HV_COOKIE_OFS 28 /* Cookie goes here */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+    };
+
+    memcpy(hello_verify + HV_COOKIE_OFS, cookie, sizeof(cookie));
+
+    BIO_write(rbio, hello_verify, sizeof(hello_verify));
+
+    return 1;
+}
+
+static int send_server_hello(BIO *rbio)
+{
+    static unsigned char server_hello[] = {
+        0x16, /* Handshake */
+        0x01, 0x00, /* DTLS1_BAD_VER */
+        0x00, 0x00, /* Epoch 0 */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* Seq# 1 */
+        0x00, 0x52, /* Length */
+        0x02, /* Server Hello */
+        0x00, 0x00, 0x46, /* Length */
+        0x00, 0x01, /* Seq# */
+        0x00, 0x00, 0x00, /* Fragment offset */
+        0x00, 0x00, 0x46, /* Fragment length */
+        0x01, 0x00, /* DTLS1_BAD_VER */
+#define SH_RANDOM_OFS 27 /* Server random goes here */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x20, /* Session ID length */
+#define SH_SESSID_OFS 60 /* Session ID goes here */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x2f, /* Cipher suite AES128-SHA */
+        0x00, /* Compression null */
+    };
+    static unsigned char change_cipher_spec[] = {
+        0x14, /* Change Cipher Spec */
+        0x01, 0x00, /* DTLS1_BAD_VER */
+        0x00, 0x00, /* Epoch 0 */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x02, /* Seq# 2 */
+        0x00, 0x03, /* Length */
+        0x01, 0x00, 0x02, /* Message */
+    };
+
+    memcpy(server_hello + SH_RANDOM_OFS, server_random, sizeof(server_random));
+    memcpy(server_hello + SH_SESSID_OFS, session_id, sizeof(session_id));
+
+    if (!EVP_DigestUpdate(&handshake_md5, server_hello + MAC_OFFSET,
+                          sizeof(server_hello) - MAC_OFFSET) ||
+        !EVP_DigestUpdate(&handshake_sha1, server_hello + MAC_OFFSET,
+                          sizeof(server_hello) - MAC_OFFSET))
+        printf("EVP_DigestUpdate() failed\n");
+
+    BIO_write(rbio, server_hello, sizeof(server_hello));
+    BIO_write(rbio, change_cipher_spec, sizeof(change_cipher_spec));
+
+    return 1;
+}
+
+/* Create header, HMAC, pad, encrypt and send a record */
+static int send_record(BIO *rbio, unsigned char type, unsigned long seqnr,
+                       const void *msg, size_t len)
+{
+    /* Note that the order of the record header fields on the wire,
+     * and in the HMAC, is different. So we just keep them in separate
+     * variables and handle them individually. */
+    static unsigned char epoch[2] = { 0x00, 0x01 };
+    static unsigned char seq[6] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+    static unsigned char ver[2] = { 0x01, 0x00 }; /* DTLS1_BAD_VER */
+    unsigned char lenbytes[2];
+    HMAC_CTX ctx;
+    EVP_CIPHER_CTX enc_ctx;
+    unsigned char iv[16];
+    unsigned char pad;
+    unsigned char *enc;
+
+#ifdef SIXTY_FOUR_BIT_LONG
+    seq[0] = (seqnr >> 40) & 0xff;
+    seq[1] = (seqnr >> 32) & 0xff;
+#endif
+    seq[2] = (seqnr >> 24) & 0xff;
+    seq[3] = (seqnr >> 16) & 0xff;
+    seq[4] = (seqnr >> 8) & 0xff;
+    seq[5] = seqnr & 0xff;
+
+    pad = 15 - ((len + SHA_DIGEST_LENGTH) % 16);
+    enc = OPENSSL_malloc(len + SHA_DIGEST_LENGTH + 1 + pad);
+    if (enc == NULL)
+        return 0;
+
+    /* Copy record to encryption buffer */
+    memcpy(enc, msg, len);
+
+    /* Append HMAC to data */
+    HMAC_Init(&ctx, mac_key, 20, EVP_sha1());
+    HMAC_Update(&ctx, epoch, 2);
+    HMAC_Update(&ctx, seq, 6);
+    HMAC_Update(&ctx, &type, 1);
+    HMAC_Update(&ctx, ver, 2); /* Version */
+    lenbytes[0] = len >> 8;
+    lenbytes[1] = len & 0xff;
+    HMAC_Update(&ctx, lenbytes, 2); /* Length */
+    HMAC_Update(&ctx, enc, len); /* Finally the data itself */
+    HMAC_Final(&ctx, enc + len, NULL);
+    HMAC_CTX_cleanup(&ctx);
+
+    /* Append padding bytes */
+    len += SHA_DIGEST_LENGTH;
+    do {
+        enc[len++] = pad;
+    } while (len % 16);
+
+    /* Generate IV, and encrypt */
+    RAND_bytes(iv, sizeof(iv));
+    EVP_CIPHER_CTX_init(&enc_ctx);
+    EVP_CipherInit_ex(&enc_ctx, EVP_aes_128_cbc(), NULL, enc_key, iv, 1);
+    EVP_Cipher(&enc_ctx, enc, enc, len);
+    EVP_CIPHER_CTX_cleanup(&enc_ctx);
+
+    /* Finally write header (from fragmented variables), IV and encrypted record */
+    BIO_write(rbio, &type, 1);
+    BIO_write(rbio, ver, 2);
+    BIO_write(rbio, epoch, 2);
+    BIO_write(rbio, seq, 6);
+    lenbytes[0] = (len + sizeof(iv)) >> 8;
+    lenbytes[1] = (len + sizeof(iv)) & 0xff;
+    BIO_write(rbio, lenbytes, 2);
+
+    BIO_write(rbio, iv, sizeof(iv));
+    BIO_write(rbio, enc, len);
+
+    OPENSSL_free(enc);
+    return 1;
+}
+
+static int send_finished(SSL *s, BIO *rbio)
+{
+    static unsigned char finished_msg[DTLS1_HM_HEADER_LENGTH +
+                                      TLS1_FINISH_MAC_LENGTH] = {
+        0x14, /* Finished */
+        0x00, 0x00, 0x0c, /* Length */
+        0x00, 0x03, /* Seq# 3 */
+        0x00, 0x00, 0x00, /* Fragment offset */
+        0x00, 0x00, 0x0c, /* Fragment length */
+        /* Finished MAC (12 bytes) */
+    };
+    unsigned char handshake_hash[EVP_MAX_MD_SIZE * 2];
+
+    /* Derive key material */
+    do_PRF(TLS_MD_KEY_EXPANSION_CONST, TLS_MD_KEY_EXPANSION_CONST_SIZE,
+           server_random, SSL3_RANDOM_SIZE,
+           client_random, SSL3_RANDOM_SIZE,
+           key_block, sizeof(key_block));
+
+    /* Generate Finished MAC */
+    if (!EVP_DigestFinal_ex(&handshake_md5, handshake_hash, NULL) ||
+        !EVP_DigestFinal_ex(&handshake_sha1, handshake_hash + EVP_MD_CTX_size(&handshake_md5), NULL))
+        printf("EVP_DigestFinal_ex() failed\n");
+
+    do_PRF(TLS_MD_SERVER_FINISH_CONST, TLS_MD_SERVER_FINISH_CONST_SIZE,
+           handshake_hash, EVP_MD_CTX_size(&handshake_md5) + EVP_MD_CTX_size(&handshake_sha1),
+           NULL, 0,
+           finished_msg + DTLS1_HM_HEADER_LENGTH, TLS1_FINISH_MAC_LENGTH);
+
+    return send_record(rbio, SSL3_RT_HANDSHAKE, 0,
+                       finished_msg, sizeof(finished_msg));
+}
+
+static int validate_ccs(BIO *wbio)
+{
+    PACKET pkt;
+    long len;
+    unsigned char *data;
+    unsigned int u;
+
+    len = BIO_get_mem_data(wbio, (char **)&data);
+    if (!PACKET_buf_init(&pkt, data, len))
+        return 0;
+
+    /* Check record header type */
+    if (!PACKET_get_1(&pkt, &u) || u != SSL3_RT_CHANGE_CIPHER_SPEC)
+        return 0;
+    /* Version */
+    if (!PACKET_get_net_2(&pkt, &u) || u != DTLS1_BAD_VER)
+        return 0;
+    /* Skip the rest of the record header */
+    if (!PACKET_forward(&pkt, DTLS1_RT_HEADER_LENGTH - 3))
+        return 0;
+
+    /* Check ChangeCipherSpec message */
+    if (!PACKET_get_1(&pkt, &u) || u != SSL3_MT_CCS)
+        return 0;
+    /* A DTLS1_BAD_VER ChangeCipherSpec also contains the
+     * handshake sequence number (which is 2 here) */
+    if (!PACKET_get_net_2(&pkt, &u) || u != 0x0002)
+        return 0;
+
+    /* Now check the Finished packet */
+    if (!PACKET_get_1(&pkt, &u) || u != SSL3_RT_HANDSHAKE)
+        return 0;
+    if (!PACKET_get_net_2(&pkt, &u) || u != DTLS1_BAD_VER)
+        return 0;
+
+    /* Check epoch is now 1 */
+    if (!PACKET_get_net_2(&pkt, &u) || u != 0x0001)
+        return 0;
+
+    /* That'll do for now. If OpenSSL accepted *our* Finished packet
+     * then it's evidently remembered that DTLS1_BAD_VER doesn't
+     * include the handshake header in the MAC. There's not a lot of
+     * point in implementing decryption here, just to check that it
+     * continues to get it right for one more packet. */
+
+    return 1;
+}
+
+#define NODROP(x) { x##UL, 0 }
+#define DROP(x)   { x##UL, 1 }
+
+static struct {
+    unsigned long seq;
+    int drop;
+} tests[] = {
+    NODROP(1), NODROP(3), NODROP(2),
+    NODROP(0x1234), NODROP(0x1230), NODROP(0x1235),
+    NODROP(0xffff), NODROP(0x10001), NODROP(0xfffe), NODROP(0x10000),
+    DROP(0x10001), DROP(0xff), NODROP(0x100000), NODROP(0x800000), NODROP(0x7fffe1),
+    NODROP(0xffffff), NODROP(0x1000000), NODROP(0xfffffe), DROP(0xffffff), NODROP(0x1000010),
+    NODROP(0xfffffd), NODROP(0x1000011), DROP(0x12), NODROP(0x1000012),
+    NODROP(0x1ffffff), NODROP(0x2000000), DROP(0x1ff00fe), NODROP(0x2000001),
+    NODROP(0x20fffff), NODROP(0x2105500), DROP(0x20ffffe), NODROP(0x21054ff),
+    NODROP(0x211ffff), DROP(0x2110000), NODROP(0x2120000)
+    /* The last test should be NODROP, because a DROP wouldn't get tested. */
+};
+
+int main(int argc, char *argv[])
+{
+    SSL_SESSION *sess;
+    SSL_CTX *ctx;
+    SSL *con;
+    BIO *rbio;
+    BIO *wbio;
+    BIO *err;
+    int testresult = 0;
+    int ret;
+    int i;
+
+    SSL_library_init();
+    SSL_load_error_strings();
+
+    err = BIO_new_fp(stderr, BIO_NOCLOSE | BIO_FP_TEXT);
+
+    CRYPTO_malloc_debug_init();
+    CRYPTO_set_mem_debug_options(V_CRYPTO_MDEBUG_ALL);
+    CRYPTO_mem_ctrl(CRYPTO_MEM_CHECK_ON);
+
+    RAND_bytes(session_id, sizeof(session_id));
+    RAND_bytes(master_secret, sizeof(master_secret));
+    RAND_bytes(cookie, sizeof(cookie));
+    RAND_bytes(server_random + 4, sizeof(server_random) - 4);
+    time((void *)server_random);
+
+    sess = client_session();
+    if (sess == NULL) {
+        printf("Failed to generate SSL_SESSION\n");
+        goto end;
+    }
+
+    if (!EVP_DigestInit_ex(&handshake_md5, EVP_md5(), NULL) ||
+        !EVP_DigestInit_ex(&handshake_sha1, EVP_sha1(), NULL)) {
+        printf("Failed to initialise handshake_md\n");
+        goto end;
+    }
+
+    ctx = SSL_CTX_new(DTLSv1_client_method());
+    if (ctx == NULL) {
+        printf("Failed to allocate SSL_CTX\n");
+        goto end_md;
+    }
+    SSL_CTX_set_options(ctx, SSL_OP_CISCO_ANYCONNECT);
+
+    if (!SSL_CTX_set_cipher_list(ctx, "AES128-SHA")) {
+        printf("SSL_CTX_set_cipher_list() failed\n");
+        goto end_ctx;
+    }
+
+    con = SSL_new(ctx);
+    if (!SSL_set_session(con, sess)) {
+        printf("SSL_set_session() failed\n");
+        goto end_con;
+    }
+    SSL_SESSION_free(sess);
+
+    rbio = BIO_new(BIO_s_mem());
+    wbio = BIO_new(BIO_s_mem());
+
+    BIO_set_nbio(rbio, 1);
+    BIO_set_nbio(wbio, 1);
+
+    SSL_set_bio(con, rbio, wbio);
+    SSL_set_connect_state(con);
+
+    /* Send initial ClientHello */
+    ret = SSL_do_handshake(con);
+    if (ret > 0 || SSL_get_error(con, ret) != SSL_ERROR_WANT_READ) {
+        printf("Unexpected handshake result at initial call!\n");
+        goto end_con;
+    }
+
+    if (validate_client_hello(wbio) != 1) {
+        printf("Initial ClientHello failed validation\n");
+        goto end_con;
+    }
+    if (send_hello_verify(rbio) != 1) {
+        printf("Failed to send HelloVerify\n");
+        goto end_con;
+    }
+    ret = SSL_do_handshake(con);
+    if (ret > 0 || SSL_get_error(con, ret) != SSL_ERROR_WANT_READ) {
+        printf("Unexpected handshake result after HelloVerify!\n");
+        goto end_con;
+    }
+    if (validate_client_hello(wbio) != 2) {
+        printf("Second ClientHello failed validation\n");
+        goto end_con;
+    }
+    if (send_server_hello(rbio) != 1) {
+        printf("Failed to send ServerHello\n");
+        goto end_con;
+    }
+    ret = SSL_do_handshake(con);
+    if (ret > 0 || SSL_get_error(con, ret) != SSL_ERROR_WANT_READ) {
+        printf("Unexpected handshake result after ServerHello!\n");
+        goto end_con;
+    }
+    if (send_finished(con, rbio) != 1) {
+        printf("Failed to send Finished\n");
+        goto end_con;
+    }
+    ret = SSL_do_handshake(con);
+    if (ret < 1) {
+        printf("Handshake not successful after Finished!\n");
+        goto end_con;
+    }
+    if (validate_ccs(wbio) != 1) {
+        printf("Failed to validate client CCS/Finished\n");
+        goto end_con;
+    }
+
+    /* While we're here and crafting packets by hand, we might as well do a
+       bit of a stress test on the DTLS record replay handling. Not Cisco-DTLS
+       specific but useful anyway for the general case. It's been broken
+       before, and in fact was broken even for a basic 0, 2, 1 test case
+       when this test was first added.... */
+    for (i = 0; i < (int)OSSL_NELEM(tests); i++) {
+        unsigned long recv_buf[2];
+
+        if (send_record(rbio, SSL3_RT_APPLICATION_DATA, tests[i].seq,
+                        &tests[i].seq, sizeof(unsigned long)) != 1) {
+            printf("Failed to send data seq #0x%lx (%d)\n",
+                   tests[i].seq, i);
+            goto end_con;
+        }
+
+        if (tests[i].drop)
+            continue;
+
+        ret = SSL_read(con, recv_buf, 2 * sizeof(unsigned long));
+        if (ret != sizeof(unsigned long)) {
+            printf("SSL_read failed or wrong size on seq#0x%lx (%d)\n",
+                   tests[i].seq, i);
+            goto end_con;
+        }
+        if (recv_buf[0] != tests[i].seq) {
+            printf("Wrong data packet received (0x%lx not 0x%lx) at packet %d\n",
+                   recv_buf[0], tests[i].seq, i);
+            goto end_con;
+        }
+    }
+    if (tests[i-1].drop) {
+        printf("Error: last test cannot be DROP()\n");
+        goto end_con;
+    }
+    testresult=1;
+
+ end_con:
+    SSL_free(con);
+ end_ctx:
+    SSL_CTX_free(ctx);
+ end_md:
+    EVP_MD_CTX_cleanup(&handshake_md5);
+    EVP_MD_CTX_cleanup(&handshake_sha1);
+ end:
+    ERR_print_errors_fp(stderr);
+
+    if (!testresult) {
+        printf("Cisco BadDTLS test: FAILED\n");
+    }
+
+    ERR_free_strings();
+    ERR_remove_thread_state(NULL);
+    EVP_cleanup();
+    CRYPTO_cleanup_all_ex_data();
+    CRYPTO_mem_leaks(err);
+    BIO_free(err);
+
+    return testresult?0:1;
+}
diff --git a/crypto/openssl/ssl/d1_both.c b/crypto/openssl/ssl/d1_both.c
index 5d26c949265f..9bc61536101b 100644
--- a/crypto/openssl/ssl/d1_both.c
+++ b/crypto/openssl/ssl/d1_both.c
@@ -581,9 +581,12 @@ static int dtls1_preprocess_fragment(SSL *s, struct hm_header_st *msg_hdr,
         /*
          * msg_len is limited to 2^24, but is effectively checked against max
          * above
+         *
+         * Make buffer slightly larger than message length as a precaution
+         * against small OOB reads e.g. CVE-2016-6306
          */
         if (!BUF_MEM_grow_clean
-            (s->init_buf, msg_len + DTLS1_HM_HEADER_LENGTH)) {
+            (s->init_buf, msg_len + DTLS1_HM_HEADER_LENGTH + 16)) {
             SSLerr(SSL_F_DTLS1_PREPROCESS_FRAGMENT, ERR_R_BUF_LIB);
             return SSL_AD_INTERNAL_ERROR;
         }
@@ -618,11 +621,23 @@ static int dtls1_retrieve_buffered_fragment(SSL *s, long max, int *ok)
     int al;
 
     *ok = 0;
-    item = pqueue_peek(s->d1->buffered_messages);
-    if (item == NULL)
-        return 0;
+    do {
+        item = pqueue_peek(s->d1->buffered_messages);
+        if (item == NULL)
+            return 0;
+
+        frag = (hm_fragment *)item->data;
+
+        if (frag->msg_header.seq < s->d1->handshake_read_seq) {
+            /* This is a stale message that has been buffered so clear it */
+            pqueue_pop(s->d1->buffered_messages);
+            dtls1_hm_fragment_free(frag);
+            pitem_free(item);
+            item = NULL;
+            frag = NULL;
+        }
+    } while (item == NULL);
 
-    frag = (hm_fragment *)item->data;
 
     /* Don't return if reassembly still in progress */
     if (frag->reassembly != NULL)
@@ -1211,7 +1226,7 @@ dtls1_retransmit_message(SSL *s, unsigned short seq, unsigned long frag_off,
     unsigned long header_length;
     unsigned char seq64be[8];
     struct dtls1_retransmit_state saved_state;
-    unsigned char save_write_sequence[8];
+    unsigned char save_write_sequence[8] = {0, 0, 0, 0, 0, 0, 0, 0};
 
     /*-
       OPENSSL_assert(s->init_num == 0);
@@ -1296,18 +1311,6 @@ dtls1_retransmit_message(SSL *s, unsigned short seq, unsigned long frag_off,
     return ret;
 }
 
-/* call this function when the buffered messages are no longer needed */
-void dtls1_clear_record_buffer(SSL *s)
-{
-    pitem *item;
-
-    for (item = pqueue_pop(s->d1->sent_messages);
-         item != NULL; item = pqueue_pop(s->d1->sent_messages)) {
-        dtls1_hm_fragment_free((hm_fragment *)item->data);
-        pitem_free(item);
-    }
-}
-
 unsigned char *dtls1_set_message_header(SSL *s, unsigned char *p,
                                         unsigned char mt, unsigned long len,
                                         unsigned long frag_off,
@@ -1469,7 +1472,7 @@ int dtls1_process_heartbeat(SSL *s)
         memcpy(bp, pl, payload);
         bp += payload;
         /* Random padding */
-        if (RAND_pseudo_bytes(bp, padding) < 0) {
+        if (RAND_bytes(bp, padding) <= 0) {
             OPENSSL_free(buffer);
             return -1;
         }
@@ -1546,6 +1549,8 @@ int dtls1_heartbeat(SSL *s)
      *  - Padding
      */
     buf = OPENSSL_malloc(1 + 2 + payload + padding);
+    if (buf == NULL)
+        goto err;
     p = buf;
     /* Message Type */
     *p++ = TLS1_HB_REQUEST;
@@ -1554,11 +1559,11 @@ int dtls1_heartbeat(SSL *s)
     /* Sequence number */
     s2n(s->tlsext_hb_seq, p);
     /* 16 random bytes */
-    if (RAND_pseudo_bytes(p, 16) < 0)
+    if (RAND_bytes(p, 16) <= 0)
         goto err;
     p += 16;
     /* Random padding */
-    if (RAND_pseudo_bytes(p, padding) < 0)
+    if (RAND_bytes(p, padding) <= 0)
         goto err;
 
     ret = dtls1_write_bytes(s, TLS1_RT_HEARTBEAT, buf, 3 + payload + padding);
diff --git a/crypto/openssl/ssl/d1_clnt.c b/crypto/openssl/ssl/d1_clnt.c
index 3ddfa7bca4b7..7e2f5c2830b5 100644
--- a/crypto/openssl/ssl/d1_clnt.c
+++ b/crypto/openssl/ssl/d1_clnt.c
@@ -769,6 +769,7 @@ int dtls1_connect(SSL *s)
             /* done with handshaking */
             s->d1->handshake_read_seq = 0;
             s->d1->next_handshake_write_seq = 0;
+            dtls1_clear_received_buffer(s);
             goto end;
             /* break; */
 
diff --git a/crypto/openssl/ssl/d1_lib.c b/crypto/openssl/ssl/d1_lib.c
index ee78921ba8b0..debd4fd5dcca 100644
--- a/crypto/openssl/ssl/d1_lib.c
+++ b/crypto/openssl/ssl/d1_lib.c
@@ -170,7 +170,6 @@ int dtls1_new(SSL *s)
 static void dtls1_clear_queues(SSL *s)
 {
     pitem *item = NULL;
-    hm_fragment *frag = NULL;
     DTLS1_RECORD_DATA *rdata;
 
     while ((item = pqueue_pop(s->d1->unprocessed_rcds.q)) != NULL) {
@@ -191,28 +190,44 @@ static void dtls1_clear_queues(SSL *s)
         pitem_free(item);
     }
 
+    while ((item = pqueue_pop(s->d1->buffered_app_data.q)) != NULL) {
+        rdata = (DTLS1_RECORD_DATA *)item->data;
+        if (rdata->rbuf.buf) {
+            OPENSSL_free(rdata->rbuf.buf);
+        }
+        OPENSSL_free(item->data);
+        pitem_free(item);
+    }
+
+    dtls1_clear_received_buffer(s);
+    dtls1_clear_sent_buffer(s);
+}
+
+void dtls1_clear_received_buffer(SSL *s)
+{
+    pitem *item = NULL;
+    hm_fragment *frag = NULL;
+
     while ((item = pqueue_pop(s->d1->buffered_messages)) != NULL) {
         frag = (hm_fragment *)item->data;
         dtls1_hm_fragment_free(frag);
         pitem_free(item);
     }
+}
+
+void dtls1_clear_sent_buffer(SSL *s)
+{
+    pitem *item = NULL;
+    hm_fragment *frag = NULL;
 
     while ((item = pqueue_pop(s->d1->sent_messages)) != NULL) {
         frag = (hm_fragment *)item->data;
         dtls1_hm_fragment_free(frag);
         pitem_free(item);
     }
-
-    while ((item = pqueue_pop(s->d1->buffered_app_data.q)) != NULL) {
-        rdata = (DTLS1_RECORD_DATA *)item->data;
-        if (rdata->rbuf.buf) {
-            OPENSSL_free(rdata->rbuf.buf);
-        }
-        OPENSSL_free(item->data);
-        pitem_free(item);
-    }
 }
 
+
 void dtls1_free(SSL *s)
 {
     ssl3_free(s);
@@ -456,7 +471,7 @@ void dtls1_stop_timer(SSL *s)
     BIO_ctrl(SSL_get_rbio(s), BIO_CTRL_DGRAM_SET_NEXT_TIMEOUT, 0,
              &(s->d1->next_timeout));
     /* Clear retransmission buffer */
-    dtls1_clear_record_buffer(s);
+    dtls1_clear_sent_buffer(s);
 }
 
 int dtls1_check_timeout_num(SSL *s)
diff --git a/crypto/openssl/ssl/d1_pkt.c b/crypto/openssl/ssl/d1_pkt.c
index fe30ec7d0042..7a02459f2b78 100644
--- a/crypto/openssl/ssl/d1_pkt.c
+++ b/crypto/openssl/ssl/d1_pkt.c
@@ -125,7 +125,7 @@
 /* mod 128 saturating subtract of two 64-bit values in big-endian order */
 static int satsub64be(const unsigned char *v1, const unsigned char *v2)
 {
-    int ret, sat, brw, i;
+    int ret, i;
 
     if (sizeof(long) == 8)
         do {
@@ -157,28 +157,51 @@ static int satsub64be(const unsigned char *v1, const unsigned char *v2)
                 return (int)l;
         } while (0);
 
-    ret = (int)v1[7] - (int)v2[7];
-    sat = 0;
-    brw = ret >> 8;             /* brw is either 0 or -1 */
-    if (ret & 0x80) {
-        for (i = 6; i >= 0; i--) {
-            brw += (int)v1[i] - (int)v2[i];
-            sat |= ~brw;
-            brw >>= 8;
-        }
-    } else {
-        for (i = 6; i >= 0; i--) {
-            brw += (int)v1[i] - (int)v2[i];
-            sat |= brw;
-            brw >>= 8;
+    ret = 0;
+    for (i=0; i<7; i++) {
+        if (v1[i] > v2[i]) {
+            /* v1 is larger... but by how much? */
+            if (v1[i] != v2[i] + 1)
+                return 128;
+            while (++i <= 6) {
+                if (v1[i] != 0x00 || v2[i] != 0xff)
+                    return 128; /* too much */
+            }
+            /* We checked all the way to the penultimate byte,
+             * so despite higher bytes changing we actually
+             * know that it only changed from (e.g.)
+             *       ... (xx)  ff ff ff ??
+             * to   ... (xx+1) 00 00 00 ??
+             * so we add a 'bias' of 256 for the carry that
+             * happened, and will eventually return
+             * 256 + v1[7] - v2[7]. */
+            ret = 256;
+            break;
+        } else if (v2[i] > v1[i]) {
+            /* v2 is larger... but by how much? */
+            if (v2[i] != v1[i] + 1)
+                return -128;
+            while (++i <= 6) {
+                if (v2[i] != 0x00 || v1[i] != 0xff)
+                    return -128; /* too much */
+            }
+            /* Similar to the case above, we know it changed
+             * from    ... (xx)  00 00 00 ??
+             * to     ... (xx-1) ff ff ff ??
+             * so we add a 'bias' of -256 for the borrow,
+             * to return -256 + v1[7] - v2[7]. */
+            ret = -256;
         }
     }
-    brw <<= 8;                  /* brw is either 0 or -256 */
 
-    if (sat & 0xff)
-        return brw | 0x80;
+    ret += (int)v1[7] - (int)v2[7];
+
+    if (ret > 128)
+        return 128;
+    else if (ret < -128)
+        return -128;
     else
-        return brw + (ret & 0xFF);
+        return ret;
 }
 
 static int have_handshake_fragment(SSL *s, int type, unsigned char *buf,
@@ -194,7 +217,7 @@ static int dtls1_record_needs_buffering(SSL *s, SSL3_RECORD *rr,
 #endif
 static int dtls1_buffer_record(SSL *s, record_pqueue *q,
                                unsigned char *priority);
-static int dtls1_process_record(SSL *s);
+static int dtls1_process_record(SSL *s, DTLS1_BITMAP *bitmap);
 
 /* copy buffered record into SSL structure */
 static int dtls1_copy_record(SSL *s, pitem *item)
@@ -319,21 +342,70 @@ static int dtls1_retrieve_buffered_record(SSL *s, record_pqueue *queue)
 static int dtls1_process_buffered_records(SSL *s)
 {
     pitem *item;
+    SSL3_BUFFER *rb;
+    SSL3_RECORD *rr;
+    DTLS1_BITMAP *bitmap;
+    unsigned int is_next_epoch;
+    int replayok = 1;
 
     item = pqueue_peek(s->d1->unprocessed_rcds.q);
     if (item) {
         /* Check if epoch is current. */
         if (s->d1->unprocessed_rcds.epoch != s->d1->r_epoch)
-            return (1);         /* Nothing to do. */
+            return 1;         /* Nothing to do. */
+
+        rr = &s->s3->rrec;
+        rb = &s->s3->rbuf;
+
+        if (rb->left > 0) {
+            /*
+             * We've still got data from the current packet to read. There could
+             * be a record from the new epoch in it - so don't overwrite it
+             * with the unprocessed records yet (we'll do it when we've
+             * finished reading the current packet).
+             */
+            return 1;
+        }
+
 
         /* Process all the records. */
         while (pqueue_peek(s->d1->unprocessed_rcds.q)) {
             dtls1_get_unprocessed_record(s);
-            if (!dtls1_process_record(s))
-                return (0);
+            bitmap = dtls1_get_bitmap(s, rr, &is_next_epoch);
+            if (bitmap == NULL) {
+                /*
+                 * Should not happen. This will only ever be NULL when the
+                 * current record is from a different epoch. But that cannot
+                 * be the case because we already checked the epoch above
+                 */
+                 SSLerr(SSL_F_DTLS1_PROCESS_BUFFERED_RECORDS,
+                        ERR_R_INTERNAL_ERROR);
+                 return 0;
+            }
+#ifndef OPENSSL_NO_SCTP
+            /* Only do replay check if no SCTP bio */
+            if (!BIO_dgram_is_sctp(SSL_get_rbio(s)))
+#endif
+            {
+                /*
+                 * Check whether this is a repeat, or aged record. We did this
+                 * check once already when we first received the record - but
+                 * we might have updated the window since then due to
+                 * records we subsequently processed.
+                 */
+                replayok = dtls1_record_replay_check(s, bitmap);
+            }
+
+            if (!replayok || !dtls1_process_record(s, bitmap)) {
+                /* dump this record */
+                rr->length = 0;
+                s->packet_length = 0;
+                continue;
+            }
+
             if (dtls1_buffer_record(s, &(s->d1->processed_rcds),
                                     s->s3->rrec.seq_num) < 0)
-                return -1;
+                return 0;
         }
     }
 
@@ -344,7 +416,7 @@ static int dtls1_process_buffered_records(SSL *s)
     s->d1->processed_rcds.epoch = s->d1->r_epoch;
     s->d1->unprocessed_rcds.epoch = s->d1->r_epoch + 1;
 
-    return (1);
+    return 1;
 }
 
 #if 0
@@ -391,7 +463,7 @@ static int dtls1_get_buffered_record(SSL *s)
 
 #endif
 
-static int dtls1_process_record(SSL *s)
+static int dtls1_process_record(SSL *s, DTLS1_BITMAP *bitmap)
 {
     int i, al;
     int enc_err;
@@ -551,6 +623,10 @@ static int dtls1_process_record(SSL *s)
 
     /* we have pulled in a full packet so zero things */
     s->packet_length = 0;
+
+    /* Mark receipt of record. */
+    dtls1_record_bitmap_update(s, bitmap);
+
     return (1);
 
  f_err:
@@ -581,11 +657,12 @@ int dtls1_get_record(SSL *s)
 
     rr = &(s->s3->rrec);
 
+ again:
     /*
      * The epoch may have changed.  If so, process all the pending records.
      * This is a non-blocking operation.
      */
-    if (dtls1_process_buffered_records(s) < 0)
+    if (!dtls1_process_buffered_records(s))
         return -1;
 
     /* if we're renegotiating, then there may be buffered records */
@@ -593,7 +670,6 @@ int dtls1_get_record(SSL *s)
         return 1;
 
     /* get something from the wire */
- again:
     /* check if we have the header */
     if ((s->rstate != SSL_ST_READ_BODY) ||
         (s->packet_length < DTLS1_RT_HEADER_LENGTH)) {
@@ -721,20 +797,17 @@ int dtls1_get_record(SSL *s)
             if (dtls1_buffer_record
                 (s, &(s->d1->unprocessed_rcds), rr->seq_num) < 0)
                 return -1;
-            /* Mark receipt of record. */
-            dtls1_record_bitmap_update(s, bitmap);
         }
         rr->length = 0;
         s->packet_length = 0;
         goto again;
     }
 
-    if (!dtls1_process_record(s)) {
+    if (!dtls1_process_record(s, bitmap)) {
         rr->length = 0;
         s->packet_length = 0;   /* dump this record */
         goto again;             /* get another record */
     }
-    dtls1_record_bitmap_update(s, bitmap); /* Mark receipt of record. */
 
     return (1);
 
@@ -878,6 +951,13 @@ int dtls1_read_bytes(SSL *s, int type, unsigned char *buf, int len, int peek)
         goto start;
     }
 
+    /*
+     * Reset the count of consecutive warning alerts if we've got a non-empty
+     * record that isn't an alert.
+     */
+    if (rr->type != SSL3_RT_ALERT && rr->length != 0)
+        s->cert->alert_count = 0;
+
     /* we now have a packet which can be read and processed */
 
     if (s->s3->change_cipher_spec /* set when we receive ChangeCipherSpec,
@@ -1144,6 +1224,14 @@ int dtls1_read_bytes(SSL *s, int type, unsigned char *buf, int len, int peek)
 
         if (alert_level == SSL3_AL_WARNING) {
             s->s3->warn_alert = alert_descr;
+
+            s->cert->alert_count++;
+            if (s->cert->alert_count == MAX_WARN_ALERT_COUNT) {
+                al = SSL_AD_UNEXPECTED_MESSAGE;
+                SSLerr(SSL_F_DTLS1_READ_BYTES, SSL_R_TOO_MANY_WARN_ALERTS);
+                goto f_err;
+            }
+
             if (alert_descr == SSL_AD_CLOSE_NOTIFY) {
 #ifndef OPENSSL_NO_SCTP
                 /*
@@ -1201,7 +1289,7 @@ int dtls1_read_bytes(SSL *s, int type, unsigned char *buf, int len, int peek)
             BIO_snprintf(tmp, sizeof tmp, "%d", alert_descr);
             ERR_add_error_data(2, "SSL alert number ", tmp);
             s->shutdown |= SSL_RECEIVED_SHUTDOWN;
-            SSL_CTX_remove_session(s->ctx, s->session);
+            SSL_CTX_remove_session(s->session_ctx, s->session);
             return (0);
         } else {
             al = SSL_AD_ILLEGAL_PARAMETER;
@@ -1830,8 +1918,13 @@ static DTLS1_BITMAP *dtls1_get_bitmap(SSL *s, SSL3_RECORD *rr,
     if (rr->epoch == s->d1->r_epoch)
         return &s->d1->bitmap;
 
-    /* Only HM and ALERT messages can be from the next epoch */
+    /*
+     * Only HM and ALERT messages can be from the next epoch and only if we
+     * have already processed all of the unprocessed records from the last
+     * epoch
+     */
     else if (rr->epoch == (unsigned long)(s->d1->r_epoch + 1) &&
+             s->d1->unprocessed_rcds.epoch != s->d1->r_epoch &&
              (rr->type == SSL3_RT_HANDSHAKE || rr->type == SSL3_RT_ALERT)) {
         *is_next_epoch = 1;
         return &s->d1->next_bitmap;
@@ -1910,6 +2003,12 @@ void dtls1_reset_seq_numbers(SSL *s, int rw)
         s->d1->r_epoch++;
         memcpy(&(s->d1->bitmap), &(s->d1->next_bitmap), sizeof(DTLS1_BITMAP));
         memset(&(s->d1->next_bitmap), 0x00, sizeof(DTLS1_BITMAP));
+
+        /*
+         * We must not use any buffered messages received from the previous
+         * epoch
+         */
+        dtls1_clear_received_buffer(s);
     } else {
         seq = s->s3->write_sequence;
         memcpy(s->d1->last_write_sequence, seq,
diff --git a/crypto/openssl/ssl/d1_srvr.c b/crypto/openssl/ssl/d1_srvr.c
index e677d880f0ac..bc875b53c9a0 100644
--- a/crypto/openssl/ssl/d1_srvr.c
+++ b/crypto/openssl/ssl/d1_srvr.c
@@ -313,7 +313,7 @@ int dtls1_accept(SSL *s)
         case SSL3_ST_SW_HELLO_REQ_B:
 
             s->shutdown = 0;
-            dtls1_clear_record_buffer(s);
+            dtls1_clear_sent_buffer(s);
             dtls1_start_timer(s);
             ret = ssl3_send_hello_request(s);
             if (ret <= 0)
@@ -894,6 +894,7 @@ int dtls1_accept(SSL *s)
             /* next message is server hello */
             s->d1->handshake_write_seq = 0;
             s->d1->next_handshake_write_seq = 0;
+            dtls1_clear_received_buffer(s);
             goto end;
             /* break; */
 
diff --git a/crypto/openssl/ssl/dtlstest.c b/crypto/openssl/ssl/dtlstest.c
new file mode 100644
index 000000000000..78ebc67744c4
--- /dev/null
+++ b/crypto/openssl/ssl/dtlstest.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2016 The OpenSSL Project Authors. All Rights Reserved.
+ *
+ * Licensed under the OpenSSL license (the "License").  You may not use
+ * this file except in compliance with the License.  You can obtain a copy
+ * in the file LICENSE in the source distribution or at
+ * https://www.openssl.org/source/license.html
+ */
+
+#include <openssl/bio.h>
+#include <openssl/crypto.h>
+#include <openssl/ssl.h>
+#include <openssl/err.h>
+
+#include "ssltestlib.h"
+#include "testutil.h"
+
+static char *cert = NULL;
+static char *privkey = NULL;
+
+#define NUM_TESTS   2
+
+
+#define DUMMY_CERT_STATUS_LEN  12
+
+unsigned char certstatus[] = {
+    SSL3_RT_HANDSHAKE, /* Content type */
+    0xfe, 0xfd, /* Record version */
+    0, 1, /* Epoch */
+    0, 0, 0, 0, 0, 0x0f, /* Record sequence number */
+    0, DTLS1_HM_HEADER_LENGTH + DUMMY_CERT_STATUS_LEN - 2,
+    SSL3_MT_CERTIFICATE_STATUS, /* Cert Status handshake message type */
+    0, 0, DUMMY_CERT_STATUS_LEN, /* Message len */
+    0, 5, /* Message sequence */
+    0, 0, 0, /* Fragment offset */
+    0, 0, DUMMY_CERT_STATUS_LEN - 2, /* Fragment len */
+    0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80 /* Dummy data */
+};
+
+#define RECORD_SEQUENCE 10
+
+static int test_dtls_unprocessed(int testidx)
+{
+    SSL_CTX *sctx = NULL, *cctx = NULL;
+    SSL *serverssl1 = NULL, *clientssl1 = NULL;
+    BIO *c_to_s_fbio, *c_to_s_mempacket;
+    int testresult = 0;
+
+    printf("Starting Test %d\n", testidx);
+
+    if (!create_ssl_ctx_pair(DTLS_server_method(), DTLS_client_method(), &sctx,
+                             &cctx, cert, privkey)) {
+        printf("Unable to create SSL_CTX pair\n");
+        return 0;
+    }
+
+    if (!SSL_CTX_set_ecdh_auto(sctx, 1)) {
+        printf("Failed configuring auto ECDH\n");
+    }
+
+    if (!SSL_CTX_set_cipher_list(cctx, "AES128-SHA")) {
+        printf("Failed setting cipher list\n");
+    }
+
+    c_to_s_fbio = BIO_new(bio_f_tls_dump_filter());
+    if (c_to_s_fbio == NULL) {
+        printf("Failed to create filter BIO\n");
+        goto end;
+    }
+
+    /* BIO is freed by create_ssl_connection on error */
+    if (!create_ssl_objects(sctx, cctx, &serverssl1, &clientssl1, NULL,
+                               c_to_s_fbio)) {
+        printf("Unable to create SSL objects\n");
+        ERR_print_errors_fp(stdout);
+        goto end;
+    }
+
+    if (testidx == 1)
+        certstatus[RECORD_SEQUENCE] = 0xff;
+
+    /*
+     * Inject a dummy record from the next epoch. In test 0, this should never
+     * get used because the message sequence number is too big. In test 1 we set
+     * the record sequence number to be way off in the future. This should not
+     * have an impact on the record replay protection because the record should
+     * be dropped before it is marked as arrivedg
+     */
+    c_to_s_mempacket = SSL_get_wbio(clientssl1);
+    c_to_s_mempacket = BIO_next(c_to_s_mempacket);
+    mempacket_test_inject(c_to_s_mempacket, (char *)certstatus,
+                          sizeof(certstatus), 1, INJECT_PACKET_IGNORE_REC_SEQ);
+
+    if (!create_ssl_connection(serverssl1, clientssl1)) {
+        printf("Unable to create SSL connection\n");
+        ERR_print_errors_fp(stdout);
+        goto end;
+    }
+
+    testresult = 1;
+ end:
+    SSL_free(serverssl1);
+    SSL_free(clientssl1);
+    SSL_CTX_free(sctx);
+    SSL_CTX_free(cctx);
+
+    return testresult;
+}
+
+int main(int argc, char *argv[])
+{
+    BIO *err = NULL;
+    int testresult = 0;
+
+    if (argc != 3) {
+        printf("Invalid argument count\n");
+        return 1;
+    }
+
+    cert = argv[1];
+    privkey = argv[2];
+
+    err = BIO_new_fp(stderr, BIO_NOCLOSE | BIO_FP_TEXT);
+
+    SSL_library_init();
+    SSL_load_error_strings();
+
+    CRYPTO_malloc_debug_init();
+    CRYPTO_dbg_set_options(V_CRYPTO_MDEBUG_ALL);
+    CRYPTO_mem_ctrl(CRYPTO_MEM_CHECK_ON);
+
+    if (!test_dtls_unprocessed(0) || !test_dtls_unprocessed(1))
+        testresult = 1;
+
+    ERR_free_strings();
+    ERR_remove_thread_state(NULL);
+    EVP_cleanup();
+    CRYPTO_cleanup_all_ex_data();
+    CRYPTO_mem_leaks(err);
+    BIO_free(err);
+
+    if (!testresult)
+        printf("PASS\n");
+
+    return testresult;
+}
diff --git a/crypto/openssl/ssl/s23_clnt.c b/crypto/openssl/ssl/s23_clnt.c
index f782010c4782..6850dc0c6704 100644
--- a/crypto/openssl/ssl/s23_clnt.c
+++ b/crypto/openssl/ssl/s23_clnt.c
@@ -289,9 +289,9 @@ int ssl_fill_hello_random(SSL *s, int server, unsigned char *result, int len)
         unsigned long Time = (unsigned long)time(NULL);
         unsigned char *p = result;
         l2n(Time, p);
-        return RAND_pseudo_bytes(p, len - 4);
+        return RAND_bytes(p, len - 4);
     } else
-        return RAND_pseudo_bytes(result, len);
+        return RAND_bytes(result, len);
 }
 
 static int ssl23_client_hello(SSL *s)
@@ -466,8 +466,8 @@ static int ssl23_client_hello(SSL *s)
                 i = ch_len;
             s2n(i, d);
             memset(&(s->s3->client_random[0]), 0, SSL3_RANDOM_SIZE);
-            if (RAND_pseudo_bytes
-                (&(s->s3->client_random[SSL3_RANDOM_SIZE - i]), i) <= 0)
+            if (RAND_bytes (&(s->s3->client_random[SSL3_RANDOM_SIZE - i]), i)
+                    <= 0)
                 return -1;
 
             memcpy(p, &(s->s3->client_random[SSL3_RANDOM_SIZE - i]), i);
diff --git a/crypto/openssl/ssl/s2_clnt.c b/crypto/openssl/ssl/s2_clnt.c
index 69da6b1421df..20de1a82178f 100644
--- a/crypto/openssl/ssl/s2_clnt.c
+++ b/crypto/openssl/ssl/s2_clnt.c
@@ -581,7 +581,7 @@ static int client_hello(SSL *s)
         /*
          * challenge id data
          */
-        if (RAND_pseudo_bytes(s->s2->challenge, SSL2_CHALLENGE_LENGTH) <= 0)
+        if (RAND_bytes(s->s2->challenge, SSL2_CHALLENGE_LENGTH) <= 0)
             return -1;
         memcpy(d, s->s2->challenge, SSL2_CHALLENGE_LENGTH);
         d += SSL2_CHALLENGE_LENGTH;
@@ -629,7 +629,7 @@ static int client_master_key(SSL *s)
             return -1;
         }
         if (i > 0)
-            if (RAND_pseudo_bytes(sess->key_arg, i) <= 0)
+            if (RAND_bytes(sess->key_arg, i) <= 0)
                 return -1;
 
         /* make a master key */
diff --git a/crypto/openssl/ssl/s2_srvr.c b/crypto/openssl/ssl/s2_srvr.c
index 07e9df82820a..d3b243c27e02 100644
--- a/crypto/openssl/ssl/s2_srvr.c
+++ b/crypto/openssl/ssl/s2_srvr.c
@@ -526,11 +526,8 @@ static int get_client_master_key(SSL *s)
      * fails. See https://tools.ietf.org/html/rfc5246#section-7.4.7.1
      */
 
-    /*
-     * should be RAND_bytes, but we cannot work around a failure.
-     */
-    if (RAND_pseudo_bytes(rand_premaster_secret,
-                          (int)num_encrypted_key_bytes) <= 0)
+    if (RAND_bytes(rand_premaster_secret,
+                  (int)num_encrypted_key_bytes) <= 0)
         return 0;
 
     i = ssl_rsa_private_decrypt(s->cert, s->s2->tmp.enc,
@@ -822,8 +819,7 @@ static int server_hello(SSL *s)
         /* make and send conn_id */
         s2n(SSL2_CONNECTION_ID_LENGTH, p); /* add conn_id length */
         s->s2->conn_id_length = SSL2_CONNECTION_ID_LENGTH;
-        if (RAND_pseudo_bytes(s->s2->conn_id, (int)s->s2->conn_id_length) <=
-            0)
+        if (RAND_bytes(s->s2->conn_id, (int)s->s2->conn_id_length) <= 0)
             return -1;
         memcpy(d, s->s2->conn_id, SSL2_CONNECTION_ID_LENGTH);
         d += SSL2_CONNECTION_ID_LENGTH;
@@ -962,7 +958,7 @@ static int request_certificate(SSL *s)
         p = (unsigned char *)s->init_buf->data;
         *(p++) = SSL2_MT_REQUEST_CERTIFICATE;
         *(p++) = SSL2_AT_MD5_WITH_RSA_ENCRYPTION;
-        if (RAND_pseudo_bytes(ccd, SSL2_MIN_CERT_CHALLENGE_LENGTH) <= 0)
+        if (RAND_bytes(ccd, SSL2_MIN_CERT_CHALLENGE_LENGTH) <= 0)
             return -1;
         memcpy(p, ccd, SSL2_MIN_CERT_CHALLENGE_LENGTH);
 
diff --git a/crypto/openssl/ssl/s3_both.c b/crypto/openssl/ssl/s3_both.c
index 09d0661e81f6..054ded1c9903 100644
--- a/crypto/openssl/ssl/s3_both.c
+++ b/crypto/openssl/ssl/s3_both.c
@@ -356,21 +356,22 @@ long ssl3_get_message(SSL *s, int st1, int stn, int mt, long max, int *ok)
         }
         *ok = 1;
         s->state = stn;
-        s->init_msg = s->init_buf->data + 4;
+        s->init_msg = s->init_buf->data + SSL3_HM_HEADER_LENGTH;
         s->init_num = (int)s->s3->tmp.message_size;
         return s->init_num;
     }
 
     p = (unsigned char *)s->init_buf->data;
 
-    if (s->state == st1) {      /* s->init_num < 4 */
+    if (s->state == st1) {      /* s->init_num < SSL3_HM_HEADER_LENGTH */
         int skip_message;
 
         do {
-            while (s->init_num < 4) {
+            while (s->init_num < SSL3_HM_HEADER_LENGTH) {
                 i = s->method->ssl_read_bytes(s, SSL3_RT_HANDSHAKE,
                                               &p[s->init_num],
-                                              4 - s->init_num, 0);
+                                              SSL3_HM_HEADER_LENGTH -
+                                              s->init_num, 0);
                 if (i <= 0) {
                     s->rwstate = SSL_READING;
                     *ok = 0;
@@ -394,12 +395,13 @@ long ssl3_get_message(SSL *s, int st1, int stn, int mt, long max, int *ok)
 
                         if (s->msg_callback)
                             s->msg_callback(0, s->version, SSL3_RT_HANDSHAKE,
-                                            p, 4, s, s->msg_callback_arg);
+                                            p, SSL3_HM_HEADER_LENGTH, s,
+                                            s->msg_callback_arg);
                     }
         }
         while (skip_message);
 
-        /* s->init_num == 4 */
+        /* s->init_num == SSL3_HM_HEADER_LENGTH */
 
         if ((mt >= 0) && (*p != mt)) {
             al = SSL_AD_UNEXPECTED_MESSAGE;
@@ -415,19 +417,20 @@ long ssl3_get_message(SSL *s, int st1, int stn, int mt, long max, int *ok)
             SSLerr(SSL_F_SSL3_GET_MESSAGE, SSL_R_EXCESSIVE_MESSAGE_SIZE);
             goto f_err;
         }
-        if (l > (INT_MAX - 4)) { /* BUF_MEM_grow takes an 'int' parameter */
-            al = SSL_AD_ILLEGAL_PARAMETER;
-            SSLerr(SSL_F_SSL3_GET_MESSAGE, SSL_R_EXCESSIVE_MESSAGE_SIZE);
-            goto f_err;
-        }
-        if (l && !BUF_MEM_grow_clean(s->init_buf, (int)l + 4)) {
+        /*
+         * Make buffer slightly larger than message length as a precaution
+         * against small OOB reads e.g. CVE-2016-6306
+         */
+        if (l
+            && !BUF_MEM_grow_clean(s->init_buf,
+                                   (int)l + SSL3_HM_HEADER_LENGTH + 16)) {
             SSLerr(SSL_F_SSL3_GET_MESSAGE, ERR_R_BUF_LIB);
             goto err;
         }
         s->s3->tmp.message_size = l;
         s->state = stn;
 
-        s->init_msg = s->init_buf->data + 4;
+        s->init_msg = s->init_buf->data + SSL3_HM_HEADER_LENGTH;
         s->init_num = 0;
     }
 
@@ -456,10 +459,12 @@ long ssl3_get_message(SSL *s, int st1, int stn, int mt, long max, int *ok)
 #endif
 
     /* Feed this message into MAC computation. */
-    ssl3_finish_mac(s, (unsigned char *)s->init_buf->data, s->init_num + 4);
+    ssl3_finish_mac(s, (unsigned char *)s->init_buf->data,
+                    s->init_num + SSL3_HM_HEADER_LENGTH);
     if (s->msg_callback)
         s->msg_callback(0, s->version, SSL3_RT_HANDSHAKE, s->init_buf->data,
-                        (size_t)s->init_num + 4, s, s->msg_callback_arg);
+                        (size_t)s->init_num + SSL3_HM_HEADER_LENGTH, s,
+                        s->msg_callback_arg);
     *ok = 1;
     return s->init_num;
  f_err:
@@ -535,6 +540,9 @@ int ssl_verify_alarm_type(long type)
     case X509_V_ERR_CRL_NOT_YET_VALID:
     case X509_V_ERR_CERT_UNTRUSTED:
     case X509_V_ERR_CERT_REJECTED:
+    case X509_V_ERR_HOSTNAME_MISMATCH:
+    case X509_V_ERR_EMAIL_MISMATCH:
+    case X509_V_ERR_IP_ADDRESS_MISMATCH:
         al = SSL_AD_BAD_CERTIFICATE;
         break;
     case X509_V_ERR_CERT_SIGNATURE_FAILURE:
@@ -548,7 +556,10 @@ int ssl_verify_alarm_type(long type)
     case X509_V_ERR_CERT_REVOKED:
         al = SSL_AD_CERTIFICATE_REVOKED;
         break;
+    case X509_V_ERR_UNSPECIFIED:
     case X509_V_ERR_OUT_OF_MEM:
+    case X509_V_ERR_INVALID_CALL:
+    case X509_V_ERR_STORE_LOOKUP:
         al = SSL_AD_INTERNAL_ERROR;
         break;
     case X509_V_ERR_DEPTH_ZERO_SELF_SIGNED_CERT:
diff --git a/crypto/openssl/ssl/s3_clnt.c b/crypto/openssl/ssl/s3_clnt.c
index 19dc8648b952..218534734dd7 100644
--- a/crypto/openssl/ssl/s3_clnt.c
+++ b/crypto/openssl/ssl/s3_clnt.c
@@ -1216,6 +1216,12 @@ int ssl3_get_server_certificate(SSL *s)
         goto f_err;
     }
     for (nc = 0; nc < llen;) {
+        if (nc + 3 > llen) {
+            al = SSL_AD_DECODE_ERROR;
+            SSLerr(SSL_F_SSL3_GET_SERVER_CERTIFICATE,
+                   SSL_R_CERT_LENGTH_MISMATCH);
+            goto f_err;
+        }
         n2l3(p, l);
         if ((l + nc + 3) > llen) {
             al = SSL_AD_DECODE_ERROR;
@@ -2111,6 +2117,10 @@ int ssl3_get_certificate_request(SSL *s)
     if (ctype_num > SSL3_CT_NUMBER) {
         /* If we exceed static buffer copy all to cert structure */
         s->cert->ctypes = OPENSSL_malloc(ctype_num);
+        if (s->cert->ctypes == NULL) {
+            SSLerr(SSL_F_SSL3_GET_CERTIFICATE_REQUEST, ERR_R_MALLOC_FAILURE);
+            goto err;
+        }
         memcpy(s->cert->ctypes, p, ctype_num);
         s->cert->ctype_num = (size_t)ctype_num;
         ctype_num = SSL3_CT_NUMBER;
@@ -2167,6 +2177,11 @@ int ssl3_get_certificate_request(SSL *s)
     }
 
     for (nc = 0; nc < llen;) {
+        if (nc + 2 > llen) {
+            ssl3_send_alert(s, SSL3_AL_FATAL, SSL_AD_DECODE_ERROR);
+            SSLerr(SSL_F_SSL3_GET_CERTIFICATE_REQUEST, SSL_R_CA_DN_TOO_LONG);
+            goto err;
+        }
         n2s(p, l);
         if ((l + nc + 2) > llen) {
             if ((s->options & SSL_OP_NETSCAPE_CA_DN_BUG))
@@ -2999,19 +3014,6 @@ int ssl3_send_client_key_exchange(SSL *s)
                 goto err;
             }
             /*
-             * If we have client certificate, use its secret as peer key
-             */
-            if (s->s3->tmp.cert_req && s->cert->key->privatekey) {
-                if (EVP_PKEY_derive_set_peer
-                    (pkey_ctx, s->cert->key->privatekey) <= 0) {
-                    /*
-                     * If there was an error - just ignore it. Ephemeral key
-                     * * would be used
-                     */
-                    ERR_clear_error();
-                }
-            }
-            /*
              * Compute shared IV and store it in algorithm-specific context
              * data
              */
@@ -3057,12 +3059,6 @@ int ssl3_send_client_key_exchange(SSL *s)
                 n = msglen + 2;
             }
             memcpy(p, tmp, msglen);
-            /* Check if pubkey from client certificate was used */
-            if (EVP_PKEY_CTX_ctrl
-                (pkey_ctx, -1, -1, EVP_PKEY_CTRL_PEER_KEY, 2, NULL) > 0) {
-                /* Set flag "skip certificate verify" */
-                s->s3->flags |= TLS1_FLAGS_SKIP_CERT_VERIFY;
-            }
             EVP_PKEY_CTX_free(pkey_ctx);
             s->session->master_key_length =
                 s->method->ssl3_enc->generate_master_secret(s,
diff --git a/crypto/openssl/ssl/s3_enc.c b/crypto/openssl/ssl/s3_enc.c
index 47a0ec9fe04b..fbc954d43c70 100644
--- a/crypto/openssl/ssl/s3_enc.c
+++ b/crypto/openssl/ssl/s3_enc.c
@@ -607,6 +607,10 @@ int ssl3_digest_cached_records(SSL *s)
     ssl3_free_digest_list(s);
     s->s3->handshake_dgst =
         OPENSSL_malloc(SSL_MAX_DIGEST * sizeof(EVP_MD_CTX *));
+    if (s->s3->handshake_dgst == NULL) {
+        SSLerr(SSL_F_SSL3_DIGEST_CACHED_RECORDS, ERR_R_MALLOC_FAILURE);
+        return 0;
+    }
     memset(s->s3->handshake_dgst, 0, SSL_MAX_DIGEST * sizeof(EVP_MD_CTX *));
     hdatalen = BIO_get_mem_data(s->s3->handshake_buffer, &hdata);
     if (hdatalen <= 0) {
@@ -624,8 +628,12 @@ int ssl3_digest_cached_records(SSL *s)
                                      EVP_MD_CTX_FLAG_NON_FIPS_ALLOW);
             }
 #endif
-            EVP_DigestInit_ex(s->s3->handshake_dgst[i], md, NULL);
-            EVP_DigestUpdate(s->s3->handshake_dgst[i], hdata, hdatalen);
+            if (!EVP_DigestInit_ex(s->s3->handshake_dgst[i], md, NULL)
+                || !EVP_DigestUpdate(s->s3->handshake_dgst[i], hdata,
+                                     hdatalen)) {
+                SSLerr(SSL_F_SSL3_DIGEST_CACHED_RECORDS, ERR_R_INTERNAL_ERROR);
+                return 0;
+            }
         } else {
             s->s3->handshake_dgst[i] = NULL;
         }
diff --git a/crypto/openssl/ssl/s3_lib.c b/crypto/openssl/ssl/s3_lib.c
index 872e636af9e1..0385e039c8d4 100644
--- a/crypto/openssl/ssl/s3_lib.c
+++ b/crypto/openssl/ssl/s3_lib.c
@@ -329,7 +329,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_SSLV3,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -382,7 +382,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_SSLV3,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -434,7 +434,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_SSLV3,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -487,7 +487,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_SSLV3,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -539,7 +539,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_SSLV3,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -625,7 +625,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_SSLV3,
-     SSL_NOT_DEFAULT | SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_DEFAULT | SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -712,7 +712,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_SSLV3,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -778,7 +778,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_MD5,
      SSL_SSLV3,
-     SSL_NOT_EXP | SSL_HIGH,
+     SSL_NOT_EXP | SSL_MEDIUM,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -1728,7 +1728,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_TLSV1,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -2120,7 +2120,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_TLSV1,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -2200,7 +2200,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_TLSV1,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -2280,7 +2280,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_TLSV1,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -2360,7 +2360,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_TLSV1,
-     SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -2440,7 +2440,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_TLSV1,
-     SSL_NOT_DEFAULT | SSL_NOT_EXP | SSL_HIGH | SSL_FIPS,
+     SSL_NOT_DEFAULT | SSL_NOT_EXP | SSL_MEDIUM | SSL_FIPS,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -2490,7 +2490,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_TLSV1,
-     SSL_NOT_EXP | SSL_HIGH,
+     SSL_NOT_EXP | SSL_MEDIUM,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -2506,7 +2506,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_TLSV1,
-     SSL_NOT_EXP | SSL_HIGH,
+     SSL_NOT_EXP | SSL_MEDIUM,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -2522,7 +2522,7 @@ OPENSSL_GLOBAL SSL_CIPHER ssl3_ciphers[] = {
      SSL_3DES,
      SSL_SHA1,
      SSL_TLSV1,
-     SSL_NOT_EXP | SSL_HIGH,
+     SSL_NOT_EXP | SSL_MEDIUM,
      SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF,
      112,
      168,
@@ -4528,7 +4528,10 @@ int ssl3_renegotiate_check(SSL *s)
  */
 long ssl_get_algorithm2(SSL *s)
 {
-    long alg2 = s->s3->tmp.new_cipher->algorithm2;
+    long alg2;
+    if (s->s3 == NULL || s->s3->tmp.new_cipher == NULL)
+        return -1;
+    alg2 = s->s3->tmp.new_cipher->algorithm2;
     if (s->method->ssl3_enc->enc_flags & SSL_ENC_FLAG_SHA256_PRF
         && alg2 == (SSL_HANDSHAKE_MAC_DEFAULT | TLS1_PRF))
         return SSL_HANDSHAKE_MAC_SHA256 | TLS1_PRF_SHA256;
diff --git a/crypto/openssl/ssl/s3_pkt.c b/crypto/openssl/ssl/s3_pkt.c
index 379890237e86..be37ef0e50d8 100644
--- a/crypto/openssl/ssl/s3_pkt.c
+++ b/crypto/openssl/ssl/s3_pkt.c
@@ -1229,6 +1229,13 @@ int ssl3_read_bytes(SSL *s, int type, unsigned char *buf, int len, int peek)
             return (ret);
     }
 
+    /*
+     * Reset the count of consecutive warning alerts if we've got a non-empty
+     * record that isn't an alert.
+     */
+    if (rr->type != SSL3_RT_ALERT && rr->length != 0)
+        s->cert->alert_count = 0;
+
     /* we now have a packet which can be read and processed */
 
     if (s->s3->change_cipher_spec /* set when we receive ChangeCipherSpec,
@@ -1443,6 +1450,14 @@ int ssl3_read_bytes(SSL *s, int type, unsigned char *buf, int len, int peek)
 
         if (alert_level == SSL3_AL_WARNING) {
             s->s3->warn_alert = alert_descr;
+
+            s->cert->alert_count++;
+            if (s->cert->alert_count == MAX_WARN_ALERT_COUNT) {
+                al = SSL_AD_UNEXPECTED_MESSAGE;
+                SSLerr(SSL_F_SSL3_READ_BYTES, SSL_R_TOO_MANY_WARN_ALERTS);
+                goto f_err;
+            }
+
             if (alert_descr == SSL_AD_CLOSE_NOTIFY) {
                 s->shutdown |= SSL_RECEIVED_SHUTDOWN;
                 return (0);
@@ -1473,7 +1488,7 @@ int ssl3_read_bytes(SSL *s, int type, unsigned char *buf, int len, int peek)
             BIO_snprintf(tmp, sizeof tmp, "%d", alert_descr);
             ERR_add_error_data(2, "SSL alert number ", tmp);
             s->shutdown |= SSL_RECEIVED_SHUTDOWN;
-            SSL_CTX_remove_session(s->ctx, s->session);
+            SSL_CTX_remove_session(s->session_ctx, s->session);
             return (0);
         } else {
             al = SSL_AD_ILLEGAL_PARAMETER;
@@ -1698,7 +1713,7 @@ int ssl3_send_alert(SSL *s, int level, int desc)
         return -1;
     /* If a fatal one, remove from cache */
     if ((level == 2) && (s->session != NULL))
-        SSL_CTX_remove_session(s->ctx, s->session);
+        SSL_CTX_remove_session(s->session_ctx, s->session);
 
     s->s3->alert_dispatch = 1;
     s->s3->send_alert[0] = level;
diff --git a/crypto/openssl/ssl/s3_srvr.c b/crypto/openssl/ssl/s3_srvr.c
index ab28702ee972..01ccd5d2ae78 100644
--- a/crypto/openssl/ssl/s3_srvr.c
+++ b/crypto/openssl/ssl/s3_srvr.c
@@ -980,7 +980,8 @@ int ssl3_get_client_hello(SSL *s)
 
         session_length = *(p + SSL3_RANDOM_SIZE);
 
-        if (p + SSL3_RANDOM_SIZE + session_length + 1 >= d + n) {
+        if (SSL3_RANDOM_SIZE + session_length + 1
+                >= (unsigned int)((d + n) - p)) {
             al = SSL_AD_DECODE_ERROR;
             SSLerr(SSL_F_SSL3_GET_CLIENT_HELLO, SSL_R_LENGTH_TOO_SHORT);
             goto f_err;
@@ -998,7 +999,7 @@ int ssl3_get_client_hello(SSL *s)
     /* get the session-id */
     j = *(p++);
 
-    if (p + j > d + n) {
+    if ((d + n) - p < j) {
         al = SSL_AD_DECODE_ERROR;
         SSLerr(SSL_F_SSL3_GET_CLIENT_HELLO, SSL_R_LENGTH_TOO_SHORT);
         goto f_err;
@@ -1054,14 +1055,14 @@ int ssl3_get_client_hello(SSL *s)
 
     if (SSL_IS_DTLS(s)) {
         /* cookie stuff */
-        if (p + 1 > d + n) {
+        if ((d + n) - p < 1) {
             al = SSL_AD_DECODE_ERROR;
             SSLerr(SSL_F_SSL3_GET_CLIENT_HELLO, SSL_R_LENGTH_TOO_SHORT);
             goto f_err;
         }
         cookie_len = *(p++);
 
-        if (p + cookie_len > d + n) {
+        if ((unsigned int)((d + n ) - p) < cookie_len) {
             al = SSL_AD_DECODE_ERROR;
             SSLerr(SSL_F_SSL3_GET_CLIENT_HELLO, SSL_R_LENGTH_TOO_SHORT);
             goto f_err;
@@ -1131,7 +1132,7 @@ int ssl3_get_client_hello(SSL *s)
         }
     }
 
-    if (p + 2 > d + n) {
+    if ((d + n ) - p < 2) {
         al = SSL_AD_DECODE_ERROR;
         SSLerr(SSL_F_SSL3_GET_CLIENT_HELLO, SSL_R_LENGTH_TOO_SHORT);
         goto f_err;
@@ -1145,7 +1146,7 @@ int ssl3_get_client_hello(SSL *s)
     }
 
     /* i bytes of cipher data + 1 byte for compression length later */
-    if ((p + i + 1) > (d + n)) {
+    if ((d + n) - p < i + 1) {
         /* not enough data */
         al = SSL_AD_DECODE_ERROR;
         SSLerr(SSL_F_SSL3_GET_CLIENT_HELLO, SSL_R_LENGTH_MISMATCH);
@@ -1211,7 +1212,7 @@ int ssl3_get_client_hello(SSL *s)
 
     /* compression */
     i = *(p++);
-    if ((p + i) > (d + n)) {
+    if ((d + n) - p < i) {
         /* not enough data */
         al = SSL_AD_DECODE_ERROR;
         SSLerr(SSL_F_SSL3_GET_CLIENT_HELLO, SSL_R_LENGTH_MISMATCH);
@@ -1872,6 +1873,11 @@ int ssl3_send_server_key_exchange(SSL *s)
                 goto f_err;
             }
             kn = EVP_PKEY_size(pkey);
+            /* Allow space for signature algorithm */
+            if (SSL_USE_SIGALGS(s))
+                kn += 2;
+            /* Allow space for signature length */
+            kn += 2;
         } else {
             pkey = NULL;
             kn = 0;
@@ -2229,11 +2235,8 @@ int ssl3_get_client_key_exchange(SSL *s)
          * fails. See https://tools.ietf.org/html/rfc5246#section-7.4.7.1
          */
 
-        /*
-         * should be RAND_bytes, but we cannot work around a failure.
-         */
-        if (RAND_pseudo_bytes(rand_premaster_secret,
-                              sizeof(rand_premaster_secret)) <= 0)
+        if (RAND_bytes(rand_premaster_secret,
+                       sizeof(rand_premaster_secret)) <= 0)
             goto err;
         decrypt_len =
             RSA_private_decrypt((int)n, p, p, rsa, RSA_PKCS1_PADDING);
@@ -2323,7 +2326,8 @@ int ssl3_get_client_key_exchange(SSL *s)
             if (!(s->options & SSL_OP_SSLEAY_080_CLIENT_DH_BUG)) {
                 SSLerr(SSL_F_SSL3_GET_CLIENT_KEY_EXCHANGE,
                        SSL_R_DH_PUBLIC_VALUE_LENGTH_IS_WRONG);
-                goto err;
+                al = SSL_AD_HANDSHAKE_FAILURE;
+                goto f_err;
             } else {
                 p -= 2;
                 i = (int)n;
@@ -2376,9 +2380,10 @@ int ssl3_get_client_key_exchange(SSL *s)
         i = DH_compute_key(p, pub, dh_srvr);
 
         if (i <= 0) {
+            al = SSL_AD_HANDSHAKE_FAILURE;
             SSLerr(SSL_F_SSL3_GET_CLIENT_KEY_EXCHANGE, ERR_R_DH_LIB);
             BN_clear_free(pub);
-            goto err;
+            goto f_err;
         }
 
         DH_free(s->s3->tmp.dh);
@@ -2676,12 +2681,14 @@ int ssl3_get_client_key_exchange(SSL *s)
             i = *p;
             p += 1;
             if (n != 1 + i) {
-                SSLerr(SSL_F_SSL3_GET_CLIENT_KEY_EXCHANGE, ERR_R_EC_LIB);
-                goto err;
+                SSLerr(SSL_F_SSL3_GET_CLIENT_KEY_EXCHANGE, SSL_R_LENGTH_MISMATCH);
+                al = SSL_AD_DECODE_ERROR;
+                goto f_err;
             }
             if (EC_POINT_oct2point(group, clnt_ecpoint, p, i, bn_ctx) == 0) {
                 SSLerr(SSL_F_SSL3_GET_CLIENT_KEY_EXCHANGE, ERR_R_EC_LIB);
-                goto err;
+                al = SSL_AD_HANDSHAKE_FAILURE;
+                goto f_err;
             }
             /*
              * p is pointing to somewhere in the buffer currently, so set it
@@ -3213,6 +3220,12 @@ int ssl3_get_client_certificate(SSL *s)
         goto f_err;
     }
     for (nc = 0; nc < llen;) {
+        if (nc + 3 > llen) {
+            al = SSL_AD_DECODE_ERROR;
+            SSLerr(SSL_F_SSL3_GET_CLIENT_CERTIFICATE,
+                   SSL_R_CERT_LENGTH_MISMATCH);
+            goto f_err;
+        }
         n2l3(p, l);
         if ((l + nc + 3) > llen) {
             al = SSL_AD_DECODE_ERROR;
@@ -3497,37 +3510,34 @@ int ssl3_send_cert_status(SSL *s)
 {
     if (s->state == SSL3_ST_SW_CERT_STATUS_A) {
         unsigned char *p;
+        size_t msglen;
+
         /*-
          * Grow buffer if need be: the length calculation is as
-         * follows 1 (message type) + 3 (message length) +
+         * follows handshake_header_length +
          * 1 (ocsp response type) + 3 (ocsp response length)
          * + (ocsp response)
          */
-        if (!BUF_MEM_grow(s->init_buf, 8 + s->tlsext_ocsp_resplen)) {
+        msglen = 4 + s->tlsext_ocsp_resplen;
+        if (!BUF_MEM_grow(s->init_buf, SSL_HM_HEADER_LENGTH(s) + msglen)) {
             s->state = SSL_ST_ERR;
             return -1;
         }
 
-        p = (unsigned char *)s->init_buf->data;
+        p = ssl_handshake_start(s);
 
-        /* do the header */
-        *(p++) = SSL3_MT_CERTIFICATE_STATUS;
-        /* message length */
-        l2n3(s->tlsext_ocsp_resplen + 4, p);
         /* status type */
         *(p++) = s->tlsext_status_type;
         /* length of OCSP response */
         l2n3(s->tlsext_ocsp_resplen, p);
         /* actual response */
         memcpy(p, s->tlsext_ocsp_resp, s->tlsext_ocsp_resplen);
-        /* number of bytes to write */
-        s->init_num = 8 + s->tlsext_ocsp_resplen;
-        s->state = SSL3_ST_SW_CERT_STATUS_B;
-        s->init_off = 0;
+
+        ssl_set_handshake_header(s, SSL3_MT_CERTIFICATE_STATUS, msglen);
     }
 
     /* SSL3_ST_SW_CERT_STATUS_B */
-    return (ssl3_do_write(s, SSL3_RT_HANDSHAKE));
+    return (ssl_do_write(s));
 }
 
 # ifndef OPENSSL_NO_NEXTPROTONEG
diff --git a/crypto/openssl/ssl/ssl.h b/crypto/openssl/ssl/ssl.h
index 5ef56faa5099..90aeb0ce4e1e 100644
--- a/crypto/openssl/ssl/ssl.h
+++ b/crypto/openssl/ssl/ssl.h
@@ -2532,7 +2532,6 @@ void SSL_set_tmp_ecdh_callback(SSL *ssl,
                                                 int keylength));
 # endif
 
-# ifndef OPENSSL_NO_COMP
 const COMP_METHOD *SSL_get_current_compression(SSL *s);
 const COMP_METHOD *SSL_get_current_expansion(SSL *s);
 const char *SSL_COMP_get_name(const COMP_METHOD *comp);
@@ -2541,13 +2540,6 @@ STACK_OF(SSL_COMP) *SSL_COMP_set0_compression_methods(STACK_OF(SSL_COMP)
                                                       *meths);
 void SSL_COMP_free_compression_methods(void);
 int SSL_COMP_add_compression_method(int id, COMP_METHOD *cm);
-# else
-const void *SSL_get_current_compression(SSL *s);
-const void *SSL_get_current_expansion(SSL *s);
-const char *SSL_COMP_get_name(const void *comp);
-void *SSL_COMP_get_compression_methods(void);
-int SSL_COMP_add_compression_method(int id, void *cm);
-# endif
 
 const SSL_CIPHER *SSL_CIPHER_find(SSL *ssl, const unsigned char *ptr);
 
@@ -2623,6 +2615,7 @@ void ERR_load_SSL_strings(void);
 # define SSL_F_DTLS1_HEARTBEAT                            305
 # define SSL_F_DTLS1_OUTPUT_CERT_CHAIN                    255
 # define SSL_F_DTLS1_PREPROCESS_FRAGMENT                  288
+# define SSL_F_DTLS1_PROCESS_BUFFERED_RECORDS             424
 # define SSL_F_DTLS1_PROCESS_OUT_OF_SEQ_MESSAGE           256
 # define SSL_F_DTLS1_PROCESS_RECORD                       257
 # define SSL_F_DTLS1_READ_BYTES                           258
@@ -3114,6 +3107,7 @@ void ERR_load_SSL_strings(void);
 # define SSL_R_TLS_INVALID_ECPOINTFORMAT_LIST             157
 # define SSL_R_TLS_PEER_DID_NOT_RESPOND_WITH_CERTIFICATE_LIST 233
 # define SSL_R_TLS_RSA_ENCRYPTED_VALUE_LENGTH_IS_WRONG    234
+# define SSL_R_TOO_MANY_WARN_ALERTS                       409
 # define SSL_R_TRIED_TO_USE_UNSUPPORTED_CIPHER            235
 # define SSL_R_UNABLE_TO_DECODE_DH_CERTS                  236
 # define SSL_R_UNABLE_TO_DECODE_ECDH_CERTS                313
diff --git a/crypto/openssl/ssl/ssl_asn1.c b/crypto/openssl/ssl/ssl_asn1.c
index 35cc27c5e985..499f0e85addf 100644
--- a/crypto/openssl/ssl/ssl_asn1.c
+++ b/crypto/openssl/ssl/ssl_asn1.c
@@ -527,6 +527,9 @@ SSL_SESSION *d2i_SSL_SESSION(SSL_SESSION **a, const unsigned char **pp,
         if (os.length > SSL_MAX_SID_CTX_LENGTH) {
             c.error = SSL_R_BAD_LENGTH;
             c.line = __LINE__;
+            OPENSSL_free(os.data);
+            os.data = NULL;
+            os.length = 0;
             goto err;
         } else {
             ret->sid_ctx_length = os.length;
diff --git a/crypto/openssl/ssl/ssl_ciph.c b/crypto/openssl/ssl/ssl_ciph.c
index 302464e643ea..2ad8f4392236 100644
--- a/crypto/openssl/ssl/ssl_ciph.c
+++ b/crypto/openssl/ssl/ssl_ciph.c
@@ -1932,17 +1932,27 @@ SSL_COMP *ssl3_comp_find(STACK_OF(SSL_COMP) *sk, int n)
 }
 
 #ifdef OPENSSL_NO_COMP
-void *SSL_COMP_get_compression_methods(void)
+STACK_OF(SSL_COMP) *SSL_COMP_get_compression_methods(void)
 {
     return NULL;
 }
 
-int SSL_COMP_add_compression_method(int id, void *cm)
+STACK_OF(SSL_COMP) *SSL_COMP_set0_compression_methods(STACK_OF(SSL_COMP)
+                                                      *meths)
+{
+    return NULL;
+}
+
+void SSL_COMP_free_compression_methods(void)
+{
+}
+
+int SSL_COMP_add_compression_method(int id, COMP_METHOD *cm)
 {
     return 1;
 }
 
-const char *SSL_COMP_get_name(const void *comp)
+const char *SSL_COMP_get_name(const COMP_METHOD *comp)
 {
     return NULL;
 }
@@ -1996,6 +2006,11 @@ int SSL_COMP_add_compression_method(int id, COMP_METHOD *cm)
 
     MemCheck_off();
     comp = (SSL_COMP *)OPENSSL_malloc(sizeof(SSL_COMP));
+    if (comp == NULL) {
+        MemCheck_on();
+        SSLerr(SSL_F_SSL_COMP_ADD_COMPRESSION_METHOD, ERR_R_MALLOC_FAILURE);
+        return 1;
+    }
     comp->id = id;
     comp->method = cm;
     load_builtin_compressions();
diff --git a/crypto/openssl/ssl/ssl_err.c b/crypto/openssl/ssl/ssl_err.c
index 704088dc469e..79aaf1a838b7 100644
--- a/crypto/openssl/ssl/ssl_err.c
+++ b/crypto/openssl/ssl/ssl_err.c
@@ -1,6 +1,6 @@
 /* ssl/ssl_err.c */
 /* ====================================================================
- * Copyright (c) 1999-2015 The OpenSSL Project.  All rights reserved.
+ * Copyright (c) 1999-2016 The OpenSSL Project.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -93,6 +93,8 @@ static ERR_STRING_DATA SSL_str_functs[] = {
     {ERR_FUNC(SSL_F_DTLS1_HEARTBEAT), "dtls1_heartbeat"},
     {ERR_FUNC(SSL_F_DTLS1_OUTPUT_CERT_CHAIN), "dtls1_output_cert_chain"},
     {ERR_FUNC(SSL_F_DTLS1_PREPROCESS_FRAGMENT), "DTLS1_PREPROCESS_FRAGMENT"},
+    {ERR_FUNC(SSL_F_DTLS1_PROCESS_BUFFERED_RECORDS),
+     "DTLS1_PROCESS_BUFFERED_RECORDS"},
     {ERR_FUNC(SSL_F_DTLS1_PROCESS_OUT_OF_SEQ_MESSAGE),
      "DTLS1_PROCESS_OUT_OF_SEQ_MESSAGE"},
     {ERR_FUNC(SSL_F_DTLS1_PROCESS_RECORD), "DTLS1_PROCESS_RECORD"},
diff --git a/crypto/openssl/ssl/ssl_lib.c b/crypto/openssl/ssl/ssl_lib.c
index fd94325bb3a4..42b980ac26a0 100644
--- a/crypto/openssl/ssl/ssl_lib.c
+++ b/crypto/openssl/ssl/ssl_lib.c
@@ -1828,7 +1828,7 @@ int SSL_export_keying_material(SSL *s, unsigned char *out, size_t olen,
                                const unsigned char *p, size_t plen,
                                int use_context)
 {
-    if (s->version < TLS1_VERSION)
+    if (s->version < TLS1_VERSION && s->version != DTLS1_BAD_VER)
         return -1;
 
     return s->method->ssl3_enc->export_keying_material(s, out, olen, label,
@@ -2000,7 +2000,7 @@ SSL_CTX *SSL_CTX_new(const SSL_METHOD *meth)
     ret->tlsext_servername_callback = 0;
     ret->tlsext_servername_arg = NULL;
     /* Setup RFC4507 ticket keys */
-    if ((RAND_pseudo_bytes(ret->tlsext_tick_key_name, 16) <= 0)
+    if ((RAND_bytes(ret->tlsext_tick_key_name, 16) <= 0)
         || (RAND_bytes(ret->tlsext_tick_hmac_key, 16) <= 0)
         || (RAND_bytes(ret->tlsext_tick_aes_key, 16) <= 0))
         ret->options |= SSL_OP_NO_TICKET;
@@ -3050,12 +3050,12 @@ const SSL_CIPHER *SSL_get_current_cipher(const SSL *s)
 }
 
 #ifdef OPENSSL_NO_COMP
-const void *SSL_get_current_compression(SSL *s)
+const COMP_METHOD *SSL_get_current_compression(SSL *s)
 {
     return NULL;
 }
 
-const void *SSL_get_current_expansion(SSL *s)
+const COMP_METHOD *SSL_get_current_expansion(SSL *s)
 {
     return NULL;
 }
diff --git a/crypto/openssl/ssl/ssl_locl.h b/crypto/openssl/ssl/ssl_locl.h
index 747e718a52bf..6df725f7d73a 100644
--- a/crypto/openssl/ssl/ssl_locl.h
+++ b/crypto/openssl/ssl/ssl_locl.h
@@ -491,6 +491,12 @@
 # define SSL_CLIENT_USE_TLS1_2_CIPHERS(s)        \
                 ((SSL_IS_DTLS(s) && s->client_version <= DTLS1_2_VERSION) || \
                 (!SSL_IS_DTLS(s) && s->client_version >= TLS1_2_VERSION))
+/*
+ * Determine if a client should send signature algorithms extension:
+ * as with TLS1.2 cipher we can't rely on method flags.
+ */
+# define SSL_CLIENT_USE_SIGALGS(s)        \
+    SSL_CLIENT_USE_TLS1_2_CIPHERS(s)
 
 /* Mostly for SSLv3 */
 # define SSL_PKEY_RSA_ENC        0
@@ -585,6 +591,8 @@ typedef struct {
  */
 # define SSL_EXT_FLAG_SENT       0x2
 
+# define MAX_WARN_ALERT_COUNT    5
+
 typedef struct {
     custom_ext_method *meths;
     size_t meths_count;
@@ -692,6 +700,8 @@ typedef struct cert_st {
     unsigned char *alpn_proposed;   /* server */
     unsigned int alpn_proposed_len;
     int alpn_sent;                  /* client */
+    /* Count of the number of consecutive warning alerts received */
+    unsigned int alert_count;
 } CERT;
 
 typedef struct sess_cert_st {
@@ -1242,7 +1252,8 @@ int dtls1_retransmit_message(SSL *s, unsigned short seq,
                              unsigned long frag_off, int *found);
 int dtls1_get_queue_priority(unsigned short seq, int is_ccs);
 int dtls1_retransmit_buffered_messages(SSL *s);
-void dtls1_clear_record_buffer(SSL *s);
+void dtls1_clear_received_buffer(SSL *s);
+void dtls1_clear_sent_buffer(SSL *s);
 void dtls1_get_message_header(unsigned char *data,
                               struct hm_header_st *msg_hdr);
 void dtls1_get_ccs_header(unsigned char *data, struct ccs_header_st *ccs_hdr);
diff --git a/crypto/openssl/ssl/ssl_rsa.c b/crypto/openssl/ssl/ssl_rsa.c
index 82022470bfd7..f679801a297c 100644
--- a/crypto/openssl/ssl/ssl_rsa.c
+++ b/crypto/openssl/ssl/ssl_rsa.c
@@ -912,6 +912,8 @@ static int serverinfo_process_buffer(const unsigned char *serverinfo,
 int SSL_CTX_use_serverinfo(SSL_CTX *ctx, const unsigned char *serverinfo,
                            size_t serverinfo_length)
 {
+    unsigned char *new_serverinfo;
+
     if (ctx == NULL || serverinfo == NULL || serverinfo_length == 0) {
         SSLerr(SSL_F_SSL_CTX_USE_SERVERINFO, ERR_R_PASSED_NULL_PARAMETER);
         return 0;
@@ -928,12 +930,13 @@ int SSL_CTX_use_serverinfo(SSL_CTX *ctx, const unsigned char *serverinfo,
         SSLerr(SSL_F_SSL_CTX_USE_SERVERINFO, ERR_R_INTERNAL_ERROR);
         return 0;
     }
-    ctx->cert->key->serverinfo = OPENSSL_realloc(ctx->cert->key->serverinfo,
-                                                 serverinfo_length);
-    if (ctx->cert->key->serverinfo == NULL) {
+    new_serverinfo = OPENSSL_realloc(ctx->cert->key->serverinfo,
+                                     serverinfo_length);
+    if (new_serverinfo == NULL) {
         SSLerr(SSL_F_SSL_CTX_USE_SERVERINFO, ERR_R_MALLOC_FAILURE);
         return 0;
     }
+    ctx->cert->key->serverinfo = new_serverinfo;
     memcpy(ctx->cert->key->serverinfo, serverinfo, serverinfo_length);
     ctx->cert->key->serverinfo_length = serverinfo_length;
 
diff --git a/crypto/openssl/ssl/ssl_sess.c b/crypto/openssl/ssl/ssl_sess.c
index b18299834384..ed9855f90cf8 100644
--- a/crypto/openssl/ssl/ssl_sess.c
+++ b/crypto/openssl/ssl/ssl_sess.c
@@ -382,7 +382,7 @@ static int def_generate_session_id(const SSL *ssl, unsigned char *id,
 {
     unsigned int retry = 0;
     do
-        if (RAND_pseudo_bytes(id, *id_len) <= 0)
+        if (RAND_bytes(id, *id_len) <= 0)
             return 0;
     while (SSL_has_matching_session_id(ssl, id, *id_len) &&
            (++retry < MAX_SESS_ID_ATTEMPTS)) ;
@@ -573,7 +573,7 @@ int ssl_get_prev_session(SSL *s, unsigned char *session_id, int len,
     int r;
 #endif
 
-    if (session_id + len > limit) {
+    if (limit - session_id < len) {
         fatal = 1;
         goto err;
     }
@@ -919,6 +919,10 @@ int SSL_set_session(SSL *s, SSL_SESSION *session)
             session->krb5_client_princ_len > 0) {
             s->kssl_ctx->client_princ =
                 (char *)OPENSSL_malloc(session->krb5_client_princ_len + 1);
+            if (s->kssl_ctx->client_princ == NULL) {
+                SSLerr(SSL_F_SSL_SET_SESSION, ERR_R_MALLOC_FAILURE);
+                return 0;
+            }
             memcpy(s->kssl_ctx->client_princ, session->krb5_client_princ,
                    session->krb5_client_princ_len);
             s->kssl_ctx->client_princ[session->krb5_client_princ_len] = '\0';
@@ -1123,7 +1127,7 @@ int ssl_clear_bad_session(SSL *s)
     if ((s->session != NULL) &&
         !(s->shutdown & SSL_SENT_SHUTDOWN) &&
         !(SSL_in_init(s) || SSL_in_before(s))) {
-        SSL_CTX_remove_session(s->ctx, s->session);
+        SSL_CTX_remove_session(s->session_ctx, s->session);
         return (1);
     } else
         return (0);
diff --git a/crypto/openssl/ssl/ssltest.c b/crypto/openssl/ssl/ssltest.c
index 1db84ad5f9aa..890e47685350 100644
--- a/crypto/openssl/ssl/ssltest.c
+++ b/crypto/openssl/ssl/ssltest.c
@@ -3141,9 +3141,12 @@ static unsigned int psk_server_callback(SSL *ssl, const char *identity,
 
 static int do_test_cipherlist(void)
 {
+#if !defined(OPENSSL_NO_SSL2) || !defined(OPENSSL_NO_SSL3) || \
+    !defined(OPENSSL_NO_TLS1)
     int i = 0;
     const SSL_METHOD *meth;
     const SSL_CIPHER *ci, *tci = NULL;
+#endif
 
 #ifndef OPENSSL_NO_SSL2
     fprintf(stderr, "testing SSLv2 cipher list order: ");
diff --git a/crypto/openssl/ssl/sslv2conftest.c b/crypto/openssl/ssl/sslv2conftest.c
index 1fd748b11866..2aed9950b91d 100644
--- a/crypto/openssl/ssl/sslv2conftest.c
+++ b/crypto/openssl/ssl/sslv2conftest.c
@@ -84,7 +84,7 @@ int main(int argc, char *argv[])
 {
     BIO *err;
     int testresult = 0;
-    int currtest;
+    int currtest = 0;
 
     SSL_library_init();
     SSL_load_error_strings();
diff --git a/crypto/openssl/ssl/t1_enc.c b/crypto/openssl/ssl/t1_enc.c
index 514fcb3e4e74..b6d1ee95a521 100644
--- a/crypto/openssl/ssl/t1_enc.c
+++ b/crypto/openssl/ssl/t1_enc.c
@@ -673,7 +673,6 @@ int tls1_setup_key_block(SSL *s)
 
     if ((p2 = (unsigned char *)OPENSSL_malloc(num)) == NULL) {
         SSLerr(SSL_F_TLS1_SETUP_KEY_BLOCK, ERR_R_MALLOC_FAILURE);
-        OPENSSL_free(p1);
         goto err;
     }
 #ifdef TLS_DEBUG
diff --git a/crypto/openssl/ssl/t1_lib.c b/crypto/openssl/ssl/t1_lib.c
index dd5bd0050d89..7831046b9261 100644
--- a/crypto/openssl/ssl/t1_lib.c
+++ b/crypto/openssl/ssl/t1_lib.c
@@ -1429,7 +1429,7 @@ unsigned char *ssl_add_clienthello_tlsext(SSL *s, unsigned char *buf,
     }
  skip_ext:
 
-    if (SSL_USE_SIGALGS(s)) {
+    if (SSL_CLIENT_USE_SIGALGS(s)) {
         size_t salglen;
         const unsigned char *salg;
         salglen = tls12_get_psigalgs(s, &salg);
@@ -1867,11 +1867,11 @@ static void ssl_check_for_safari(SSL *s, const unsigned char *data,
         0x02, 0x03,             /* SHA-1/ECDSA */
     };
 
-    if (data >= (limit - 2))
+    if (limit - data <= 2)
         return;
     data += 2;
 
-    if (data > (limit - 4))
+    if (limit - data < 4)
         return;
     n2s(data, type);
     n2s(data, size);
@@ -1879,7 +1879,7 @@ static void ssl_check_for_safari(SSL *s, const unsigned char *data,
     if (type != TLSEXT_TYPE_server_name)
         return;
 
-    if (data + size > limit)
+    if (limit - data < size)
         return;
     data += size;
 
@@ -1887,7 +1887,7 @@ static void ssl_check_for_safari(SSL *s, const unsigned char *data,
         const size_t len1 = sizeof(kSafariExtensionsBlock);
         const size_t len2 = sizeof(kSafariTLS12ExtensionsBlock);
 
-        if (data + len1 + len2 != limit)
+        if (limit - data != (int)(len1 + len2))
             return;
         if (memcmp(data, kSafariExtensionsBlock, len1) != 0)
             return;
@@ -1896,7 +1896,7 @@ static void ssl_check_for_safari(SSL *s, const unsigned char *data,
     } else {
         const size_t len = sizeof(kSafariExtensionsBlock);
 
-        if (data + len != limit)
+        if (limit - data != (int)(len))
             return;
         if (memcmp(data, kSafariExtensionsBlock, len) != 0)
             return;
@@ -2053,19 +2053,19 @@ static int ssl_scan_clienthello_tlsext(SSL *s, unsigned char **p,
     if (data == limit)
         goto ri_check;
 
-    if (data > (limit - 2))
+    if (limit - data < 2)
         goto err;
 
     n2s(data, len);
 
-    if (data + len != limit)
+    if (limit - data != len)
         goto err;
 
-    while (data <= (limit - 4)) {
+    while (limit - data >= 4) {
         n2s(data, type);
         n2s(data, size);
 
-        if (data + size > (limit))
+        if (limit - data < size)
             goto err;
 # if 0
         fprintf(stderr, "Received extension type %d size %d\n", type, size);
@@ -2316,6 +2316,23 @@ static int ssl_scan_clienthello_tlsext(SSL *s, unsigned char **p,
                 size -= 2;
                 if (dsize > size)
                     goto err;
+
+                /*
+                 * We remove any OCSP_RESPIDs from a previous handshake
+                 * to prevent unbounded memory growth - CVE-2016-6304
+                 */
+                sk_OCSP_RESPID_pop_free(s->tlsext_ocsp_ids,
+                                        OCSP_RESPID_free);
+                if (dsize > 0) {
+                    s->tlsext_ocsp_ids = sk_OCSP_RESPID_new_null();
+                    if (s->tlsext_ocsp_ids == NULL) {
+                        *al = SSL_AD_INTERNAL_ERROR;
+                        return 0;
+                    }
+                } else {
+                    s->tlsext_ocsp_ids = NULL;
+                }
+
                 while (dsize > 0) {
                     OCSP_RESPID *id;
                     int idsize;
@@ -2335,13 +2352,6 @@ static int ssl_scan_clienthello_tlsext(SSL *s, unsigned char **p,
                         OCSP_RESPID_free(id);
                         goto err;
                     }
-                    if (!s->tlsext_ocsp_ids
-                        && !(s->tlsext_ocsp_ids =
-                             sk_OCSP_RESPID_new_null())) {
-                        OCSP_RESPID_free(id);
-                        *al = SSL_AD_INTERNAL_ERROR;
-                        return 0;
-                    }
                     if (!sk_OCSP_RESPID_push(s->tlsext_ocsp_ids, id)) {
                         OCSP_RESPID_free(id);
                         *al = SSL_AD_INTERNAL_ERROR;
@@ -2472,18 +2482,18 @@ static int ssl_scan_clienthello_custom_tlsext(SSL *s,
     if (s->hit || s->cert->srv_ext.meths_count == 0)
         return 1;
 
-    if (data >= limit - 2)
+    if (limit - data <= 2)
         return 1;
     n2s(data, len);
 
-    if (data > limit - len)
+    if (limit - data < len)
         return 1;
 
-    while (data <= limit - 4) {
+    while (limit - data >= 4) {
         n2s(data, type);
         n2s(data, size);
 
-        if (data + size > limit)
+        if (limit - data < size)
             return 1;
         if (custom_ext_parse(s, 1 /* server */ , type, data, size, al) <= 0)
             return 0;
@@ -2569,20 +2579,20 @@ static int ssl_scan_serverhello_tlsext(SSL *s, unsigned char **p,
                              SSL_TLSEXT_HB_DONT_SEND_REQUESTS);
 # endif
 
-    if (data >= (d + n - 2))
+    if ((d + n) - data <= 2)
         goto ri_check;
 
     n2s(data, length);
-    if (data + length != d + n) {
+    if ((d + n) - data != length) {
         *al = SSL_AD_DECODE_ERROR;
         return 0;
     }
 
-    while (data <= (d + n - 4)) {
+    while ((d + n) - data >= 4) {
         n2s(data, type);
         n2s(data, size);
 
-        if (data + size > (d + n))
+        if ((d + n) - data < size)
             goto ri_check;
 
         if (s->tlsext_debug_cb)
@@ -2712,6 +2722,11 @@ static int ssl_scan_serverhello_tlsext(SSL *s, unsigned char **p,
                 *al = TLS1_AD_INTERNAL_ERROR;
                 return 0;
             }
+            /*
+             * Could be non-NULL if server has sent multiple NPN extensions in
+             * a single Serverhello
+             */
+            OPENSSL_free(s->next_proto_negotiated);
             s->next_proto_negotiated = OPENSSL_malloc(selected_len);
             if (!s->next_proto_negotiated) {
                 *al = TLS1_AD_INTERNAL_ERROR;
@@ -3307,29 +3322,33 @@ int tls1_process_ticket(SSL *s, unsigned char *session_id, int len,
     /* Skip past DTLS cookie */
     if (SSL_IS_DTLS(s)) {
         i = *(p++);
-        p += i;
-        if (p >= limit)
+
+        if (limit - p <= i)
             return -1;
+
+        p += i;
     }
     /* Skip past cipher list */
     n2s(p, i);
-    p += i;
-    if (p >= limit)
+    if (limit - p <= i)
         return -1;
+    p += i;
+
     /* Skip past compression algorithm list */
     i = *(p++);
-    p += i;
-    if (p > limit)
+    if (limit - p < i)
         return -1;
+    p += i;
+
     /* Now at start of extensions */
-    if ((p + 2) >= limit)
+    if (limit - p <= 2)
         return 0;
     n2s(p, i);
-    while ((p + 4) <= limit) {
+    while (limit - p >= 4) {
         unsigned short type, size;
         n2s(p, type);
         n2s(p, size);
-        if (p + size > limit)
+        if (limit - p < size)
             return 0;
         if (type == TLSEXT_TYPE_session_ticket) {
             int r;
@@ -3397,9 +3416,7 @@ static int tls_decrypt_ticket(SSL *s, const unsigned char *etick,
     HMAC_CTX hctx;
     EVP_CIPHER_CTX ctx;
     SSL_CTX *tctx = s->initial_ctx;
-    /* Need at least keyname + iv + some encrypted data */
-    if (eticklen < 48)
-        return 2;
+
     /* Initialize session ticket encryption and HMAC contexts */
     HMAC_CTX_init(&hctx);
     EVP_CIPHER_CTX_init(&ctx);
@@ -3433,6 +3450,13 @@ static int tls_decrypt_ticket(SSL *s, const unsigned char *etick,
     if (mlen < 0) {
         goto err;
     }
+    /* Sanity check ticket length: must exceed keyname + IV + HMAC */
+    if (eticklen <= 16 + EVP_CIPHER_CTX_iv_length(&ctx) + mlen) {
+        HMAC_CTX_cleanup(&hctx);
+        EVP_CIPHER_CTX_cleanup(&ctx);
+        return 2;
+    }
+
     eticklen -= mlen;
     /* Check HMAC of encrypted ticket */
     if (HMAC_Update(&hctx, etick, eticklen) <= 0
@@ -3902,7 +3926,7 @@ int tls1_process_heartbeat(SSL *s)
         memcpy(bp, pl, payload);
         bp += payload;
         /* Random padding */
-        if (RAND_pseudo_bytes(bp, padding) < 0) {
+        if (RAND_bytes(bp, padding) <= 0) {
             OPENSSL_free(buffer);
             return -1;
         }
@@ -3980,6 +4004,8 @@ int tls1_heartbeat(SSL *s)
      *  - Padding
      */
     buf = OPENSSL_malloc(1 + 2 + payload + padding);
+    if (buf == NULL)
+        return -1;
     p = buf;
     /* Message Type */
     *p++ = TLS1_HB_REQUEST;
@@ -3988,13 +4014,13 @@ int tls1_heartbeat(SSL *s)
     /* Sequence number */
     s2n(s->tlsext_hb_seq, p);
     /* 16 random bytes */
-    if (RAND_pseudo_bytes(p, 16) < 0) {
+    if (RAND_bytes(p, 16) <= 0) {
         SSLerr(SSL_F_TLS1_HEARTBEAT, ERR_R_INTERNAL_ERROR);
         goto err;
     }
     p += 16;
     /* Random padding */
-    if (RAND_pseudo_bytes(p, padding) < 0) {
+    if (RAND_bytes(p, padding) <= 0) {
         SSLerr(SSL_F_TLS1_HEARTBEAT, ERR_R_INTERNAL_ERROR);
         goto err;
     }
diff --git a/crypto/openssl/util/mk1mf.pl b/crypto/openssl/util/mk1mf.pl
index 128a405efc35..7a3ae11f7865 100755
--- a/crypto/openssl/util/mk1mf.pl
+++ b/crypto/openssl/util/mk1mf.pl
@@ -277,6 +277,7 @@ $cflags.=" -DOPENSSL_NO_SOCK" if $no_sock;
 $cflags.=" -DOPENSSL_NO_SSL2" if $no_ssl2;
 $cflags.=" -DOPENSSL_NO_SSL3" if $no_ssl3;
 $cflags.=" -DOPENSSL_NO_TLSEXT" if $no_tlsext;
+$cflags.=" -DOPENSSL_NO_TLS1" if $no_tls1;
 $cflags.=" -DOPENSSL_NO_SRP" if $no_srp;
 $cflags.=" -DOPENSSL_NO_CMS" if $no_cms;
 $cflags.=" -DOPENSSL_NO_ERR"  if $no_err;
@@ -692,8 +693,8 @@ $rules.=&do_copy_rule("\$(INCL_D)",$header,"");
 $defs.=&do_defs("EXHEADER",$exheader,"\$(INCO_D)","");
 $rules.=&do_copy_rule("\$(INCO_D)",$exheader,"");
 
-$defs.=&do_defs("T_OBJ",$test,"\$(OBJ_D)",$obj);
-$rules.=&do_compile_rule("\$(OBJ_D)",$test,"\$(APP_CFLAGS)");
+$defs.=&do_defs("T_OBJ","$test test${o}ssltestlib","\$(OBJ_D)",$obj);
+$rules.=&do_compile_rule("\$(OBJ_D)","$test test${o}ssltestlib","\$(APP_CFLAGS)");
 
 $defs.=&do_defs("E_OBJ",$e_exe,"\$(OBJ_D)",$obj);
 $rules.=&do_compile_rule("\$(OBJ_D)",$e_exe,'-DMONOLITH $(APP_CFLAGS)');
@@ -764,6 +765,7 @@ foreach (split(/\s+/,$test))
 	{
 	$t=&bname($_);
 	$tt="\$(OBJ_D)${o}$t${obj}";
+	$tt.=" \$(OBJ_D)${o}ssltestlib${obj}" if $t eq "dtlstest";
 	$rules.=&do_link_rule("\$(TEST_D)$o$t$exep",$tt,"\$(LIBS_DEP)","\$(L_LIBS) \$(EX_LIBS)");
 	}
 
@@ -1204,6 +1206,7 @@ sub read_options
 		"no-ssl3" => \$no_ssl3,
 		"no-ssl3-method" => 0,
 		"no-tlsext" => \$no_tlsext,
+		"no-tls1" => \$no_tls1,
 		"no-srp" => \$no_srp,
 		"no-cms" => \$no_cms,
 		"no-jpake" => \$no_jpake,
diff --git a/crypto/openssl/util/mkerr.pl b/crypto/openssl/util/mkerr.pl
index 09ebebef9b52..c197f3a9546a 100644
--- a/crypto/openssl/util/mkerr.pl
+++ b/crypto/openssl/util/mkerr.pl
@@ -158,8 +158,8 @@ close IN;
 while (($hdr, $lib) = each %libinc)
 {
 	next if($hdr eq "NONE");
-	print STDERR "Scanning header file $hdr\n" if $debug; 
-	my $line = "", $def= "", $linenr = 0, $gotfile = 0;
+	print STDERR "Scanning header file $hdr\n" if $debug;
+	my $line = "", $def= "", $linenr = 0, $gotfile = 0, $cpp = 0;
 	if (open(IN, "<$hdr")) {
 	    $gotfile = 1;
 	    while(<IN>) {
@@ -382,14 +382,21 @@ foreach $lib (keys %csrc)
 
 	# Rewrite the header file
 
+	$cpp = 0;
+	$cplusplus = 0;
 	if (open(IN, "<$hfile")) {
 	    # Copy across the old file
 	    while(<IN>) {
+		$cplusplus = $cpp if /^#.*ifdef.*cplusplus/;
+		$cpp++ if /^#\s*if/;
+		$cpp-- if /^#\s*endif/;
 		push @out, $_;
 		last if (/BEGIN ERROR CODES/);
 	    }
 	    close IN;
 	} else {
+	    $cpp = 1;
+	    $cplusplus = 1;
 	    push @out,
 "/* ====================================================================\n",
 " * Copyright (c) 2001-$year The OpenSSL Project.  All rights reserved.\n",
@@ -446,11 +453,11 @@ foreach $lib (keys %csrc)
 " */\n",
 "\n",
 "#ifndef HEADER_${lib}_ERR_H\n",
-"#define HEADER_${lib}_ERR_H\n",
+"# define HEADER_${lib}_ERR_H\n",
 "\n",
-"#ifdef  __cplusplus\n",
+"# ifdef  __cplusplus\n",
 "extern \"C\" {\n",
-"#endif\n",
+"# endif\n",
 "\n",
 "/* BEGIN ERROR CODES */\n";
 	}
@@ -463,6 +470,7 @@ foreach $lib (keys %csrc)
  * The following lines are auto generated by the script mkerr.pl. Any changes
  * made after this point may be overwritten when the script is next run.
  */
+
 EOF
 	if($static) {
 		print OUT <<"EOF";
@@ -523,11 +531,17 @@ EOF
 	}
 	print OUT <<"EOF";
 
-#ifdef  __cplusplus
-}
-#endif
-#endif
 EOF
+	do {
+	    if ($cplusplus == $cpp) {
+		print OUT "#", " "x$cpp, "ifdef  __cplusplus\n";
+		print OUT "}\n";
+		print OUT "#", " "x$cpp, "endif\n";
+	    }
+	    if ($cpp-- > 0) {
+		print OUT "#", " "x$cpp, "endif\n";
+	    }
+	} while ($cpp);
 	close OUT;
 
 	# Rewrite the C source file containing the error details.
@@ -559,8 +573,9 @@ EOF
 
 	my $hincf;
 	if($static) {
-		$hfile =~ /([^\/]+)$/;
-		$hincf = "<${hprefix}$1>";
+		$hincf = $hfile;
+		$hincf =~ s|.*/||g;
+		$hincf = "<${hprefix}${hincf}>";
 	} else {
 		$hincf = "\"$hfile\"";
 	}
@@ -665,7 +680,7 @@ EOF
 			$fn = $ftrans{$fn};
 		}
 #		print OUT "{ERR_PACK($pack_errcode,$i,0),\t\"$fn\"},\n";
-		if(length($i) + length($fn) > 58) {
+		if(length($i) + length($fn) > 57) {
 			print OUT "    {ERR_FUNC($i),\n     \"$fn\"},\n";
 		} else {
 			print OUT "    {ERR_FUNC($i), \"$fn\"},\n";
@@ -688,7 +703,7 @@ EOF
 			$rn = $1;
 			$rn =~ tr/_[A-Z]/ [a-z]/;
 		}
-		if(length($i) + length($rn) > 56) {
+		if(length($i) + length($rn) > 55) {
 			print OUT "    {${rstr},\n     \"$rn\"},\n";
 		} else {
 			print OUT "    {${rstr}, \"$rn\"},\n";
diff --git a/crypto/openssl/util/ssleay.num b/crypto/openssl/util/ssleay.num
index 5760bc42a251..e3fdaf2d0a54 100644
--- a/crypto/openssl/util/ssleay.num
+++ b/crypto/openssl/util/ssleay.num
@@ -164,7 +164,7 @@ SSL_CTX_get_cert_store                  180	EXIST::FUNCTION:
 SSL_CTX_set_cert_store                  181	EXIST::FUNCTION:
 SSL_want                                182	EXIST::FUNCTION:
 SSL_library_init                        183	EXIST::FUNCTION:
-SSL_COMP_add_compression_method         184	EXIST::FUNCTION:COMP
+SSL_COMP_add_compression_method         184	EXIST::FUNCTION:
 SSL_add_file_cert_subjects_to_stack     185	EXIST:!VMS:FUNCTION:STDIO
 SSL_add_file_cert_subjs_to_stk          185	EXIST:VMS:FUNCTION:STDIO
 SSL_set_tmp_rsa_callback                186	EXIST::FUNCTION:RSA
@@ -219,13 +219,13 @@ SSL_set_msg_callback                    267	EXIST::FUNCTION:
 DTLSv1_client_method                    268	EXIST::FUNCTION:
 SSL_CTX_set_tmp_ecdh_callback           269	EXIST::FUNCTION:ECDH
 SSL_set_tmp_ecdh_callback               270	EXIST::FUNCTION:ECDH
-SSL_COMP_get_name                       271	EXIST::FUNCTION:COMP
-SSL_get_current_compression             272	EXIST::FUNCTION:COMP
+SSL_COMP_get_name                       271	EXIST::FUNCTION:
+SSL_get_current_compression             272	EXIST::FUNCTION:
 DTLSv1_method                           273	EXIST::FUNCTION:
-SSL_get_current_expansion               274	EXIST::FUNCTION:COMP
+SSL_get_current_expansion               274	EXIST::FUNCTION:
 DTLSv1_server_method                    275	EXIST::FUNCTION:
-SSL_COMP_get_compression_methods        276	EXIST:!VMS:FUNCTION:COMP
-SSL_COMP_get_compress_methods           276	EXIST:VMS:FUNCTION:COMP
+SSL_COMP_get_compression_methods        276	EXIST:!VMS:FUNCTION:
+SSL_COMP_get_compress_methods           276	EXIST:VMS:FUNCTION:
 SSL_SESSION_get_id                      277	EXIST::FUNCTION:
 SSL_CTX_sess_set_new_cb                 278	EXIST::FUNCTION:
 SSL_CTX_sess_get_get_cb                 279	EXIST::FUNCTION:
@@ -332,8 +332,8 @@ SSL_set_alpn_protos                     370	EXIST::FUNCTION:
 SSL_CTX_set_srv_supp_data               371	NOEXIST::FUNCTION:
 SSL_CONF_cmd_argv                       372	EXIST::FUNCTION:
 DTLSv1_2_server_method                  373	EXIST::FUNCTION:
-SSL_COMP_set0_compression_methods       374	EXIST:!VMS:FUNCTION:COMP
-SSL_COMP_set0_compress_methods          374	EXIST:VMS:FUNCTION:COMP
+SSL_COMP_set0_compression_methods       374	EXIST:!VMS:FUNCTION:
+SSL_COMP_set0_compress_methods          374	EXIST:VMS:FUNCTION:
 SSL_CTX_set_cert_cb                     375	EXIST::FUNCTION:
 SSL_CTX_add_client_custom_ext           376	EXIST::FUNCTION:TLSEXT
 SSL_is_server                           377	EXIST::FUNCTION:
@@ -365,6 +365,6 @@ SSL_CTX_set_cli_supp_data               403	NOEXIST::FUNCTION:
 DTLSv1_2_method                         404	EXIST::FUNCTION:
 DTLS_server_method                      405	EXIST::FUNCTION:
 SSL_CTX_use_serverinfo_file             406	EXIST::FUNCTION:STDIO,TLSEXT
-SSL_COMP_free_compression_methods       407	EXIST:!VMS:FUNCTION:COMP
-SSL_COMP_free_compress_methods          407	EXIST:VMS:FUNCTION:COMP
+SSL_COMP_free_compression_methods       407	EXIST:!VMS:FUNCTION:
+SSL_COMP_free_compress_methods          407	EXIST:VMS:FUNCTION:
 SSL_extension_supported                 409	EXIST::FUNCTION:TLSEXT
diff --git a/etc/auto_master b/etc/auto_master
index 255b7f861b84..55ee99172ea0 100644
--- a/etc/auto_master
+++ b/etc/auto_master
@@ -5,5 +5,5 @@
 /net		-hosts		-nobrowse,nosuid,intr
 # When using the -media special map, make sure to edit devd.conf(5)
 # to move the call to "automount -c" out of the comments section.
-#/media		-media		-nosuid
+#/media		-media		-nosuid,noatime
 #/-		-noauto
diff --git a/etc/autofs/special_media b/etc/autofs/special_media
index 1e2c2552183e..c825d0eb7cc4 100755
--- a/etc/autofs/special_media
+++ b/etc/autofs/special_media
@@ -38,7 +38,8 @@ print_map_entry() {
 	_fstype="$1"
 	_p="$2"
 
-	if [ "${_fstype}" = "ntfs" ]; then
+	case "${_fstype}" in
+	"ntfs")
 		if [ -f "/usr/local/bin/ntfs-3g" ]; then
 			echo "-mountprog=/usr/local/bin/ntfs-3g,fstype=${_fstype},nosuid	:/dev/${_p}" 
 		else
@@ -46,9 +47,14 @@ print_map_entry() {
 			    "Cannot mount ${_fstype} formatted device /dev/${_p}: Install sysutils/fusefs-ntfs first"
 			exit 1
 		fi
-	else
+		;;
+	"ext2fs" | "msdosfs")
+		echo "-fstype=${_fstype},nosuid,async	:/dev/${_p}" 
+		;;
+	*)
 		echo "-fstype=${_fstype},nosuid	:/dev/${_p}" 
-	fi
+		;;
+	esac
 }
 
 # Determine map entry contents for the given key and print out the entry.
diff --git a/etc/periodic/security/100.chksetuid b/etc/periodic/security/100.chksetuid
index 95920a6faf90..da8d29d985ea 100755
--- a/etc/periodic/security/100.chksetuid
+++ b/etc/periodic/security/100.chksetuid
@@ -46,7 +46,7 @@ then
 	echo ""
 	echo 'Checking setuid files and devices:'
 	MP=`mount -t ufs,zfs | awk '$0 !~ /no(suid|exec)/ { print $3 }'`
-	find -sx $MP /dev/null -type f \
+	find -sx $MP /dev/null \( ! -fstype local \) -prune -o -type f \
 	    \( -perm -u+x -or -perm -g+x -or -perm -o+x \) \
 	    \( -perm -u+s -or -perm -g+s \) -exec ls -liTd \{\} \+ |
 	check_diff setuid - "${host} setuid diffs:"
diff --git a/etc/periodic/security/110.neggrpperm b/etc/periodic/security/110.neggrpperm
index 1d545ac5f7b6..bd94015951bd 100755
--- a/etc/periodic/security/110.neggrpperm
+++ b/etc/periodic/security/110.neggrpperm
@@ -44,7 +44,7 @@ then
 	echo ""
 	echo 'Checking negative group permissions:'
 	MP=`mount -t ufs,zfs | awk '$0 !~ /no(suid|exec)/ { print $3 }'`
-	n=$(find -sx $MP /dev/null -type f \
+	n=$(find -sx $MP /dev/null \( ! -fstype local \) -prune -o -type f \
 	    \( \( ! -perm +010 -and -perm +001 \) -or \
 	    \( ! -perm +020 -and -perm +002 \) -or \
 	    \( ! -perm +040 -and -perm +004 \) \) \
diff --git a/etc/rc.subr b/etc/rc.subr
index 8da111acec8f..5b29ccf2e0b7 100644
--- a/etc/rc.subr
+++ b/etc/rc.subr
@@ -1532,28 +1532,20 @@ debug()
 #
 # backup_file action file cur backup
 #	Make a backup copy of `file' into `cur', and save the previous
-#	version of `cur' as `backup' or use rcs for archiving.
-#
-#	This routine checks the value of the backup_uses_rcs variable,
-#	which can be either YES or NO.
+#	version of `cur' as `backup'.
 #
 #	The `action' keyword can be one of the following:
 #
 #	add		`file' is now being backed up (and is possibly
 #			being reentered into the backups system).  `cur'
-#			is created and RCS files, if necessary, are
-#			created as well.
+#			is created.
 #
 #	update		`file' has changed and needs to be backed up.
-#			If `cur' exists, it is copied to to `back' or
-#			checked into RCS (if the repository file is old),
-#			and then `file' is copied to `cur'.  Another RCS
-#			check in done here if RCS is being used.
+#			If `cur' exists, it is copied to to `back'
+#			and then `file' is copied to `cur'.
 #
 #	remove		`file' is no longer being tracked by the backups
-#			system.  If RCS is not being used, `cur' is moved
-#			to `back', otherwise an empty file is checked in,
-#			and then `cur' is removed.
+#			system.  `cur' is moved `back'.
 #
 #
 backup_file()
@@ -1563,56 +1555,18 @@ backup_file()
 	_cur=$3
 	_back=$4
 
-	if checkyesno backup_uses_rcs; then
-		_msg0="backup archive"
-		_msg1="update"
-
-		# ensure that history file is not locked
-		if [ -f $_cur,v ]; then
-			rcs -q -u -U -M $_cur
-		fi
-
-		# ensure after switching to rcs that the
-		# current backup is not lost
+	case $_action in
+	add|update)
 		if [ -f $_cur ]; then
-			# no archive, or current newer than archive
-			if [ ! -f $_cur,v -o $_cur -nt $_cur,v ]; then
-				ci -q -f -u -t-"$_msg0" -m"$_msg1" $_cur
-				rcs -q -kb -U $_cur
-				co -q -f -u $_cur
-			fi
+			cp -p $_cur $_back
 		fi
-
-		case $_action in
-		add|update)
-			cp -p $_file $_cur
-			ci -q -f -u -t-"$_msg0" -m"$_msg1" $_cur
-			rcs -q -kb -U $_cur
-			co -q -f -u $_cur
-			chown root:wheel $_cur $_cur,v
-			;;
-		remove)
-			cp /dev/null $_cur
-			ci -q -f -u -t-"$_msg0" -m"$_msg1" $_cur
-			rcs -q -kb -U $_cur
-			chown root:wheel $_cur $_cur,v
-			rm $_cur
-			;;
-		esac
-	else
-		case $_action in
-		add|update)
-			if [ -f $_cur ]; then
-				cp -p $_cur $_back
-			fi
-			cp -p $_file $_cur
-			chown root:wheel $_cur
-			;;
-		remove)
-			mv -f $_cur $_back
-			;;
-		esac
-	fi
+		cp -p $_file $_cur
+		chown root:wheel $_cur
+		;;
+	remove)
+		mv -f $_cur $_back
+		;;
+	esac
 }
 
 # make_symlink src link
diff --git a/gnu/lib/libgcc/Makefile b/gnu/lib/libgcc/Makefile
index d9837cc3a7cd..b101b4f2ea91 100644
--- a/gnu/lib/libgcc/Makefile
+++ b/gnu/lib/libgcc/Makefile
@@ -258,8 +258,8 @@ OBJ_GRPS +=	FPBIT DPBIT
 .for T in ${OBJ_GRPS}
 ${T}_OBJS_T =	${${T}_FUNCS:S/$/.o/}
 ${T}_OBJS_P =	${${T}_FUNCS:S/$/.po/}
-${T}_OBJS_S =	${${T}_FUNCS:S/$/.So/}
-SOBJS +=	${${T}_FUNCS:S/$/.So/}
+${T}_OBJS_S =	${${T}_FUNCS:S/$/.pico/}
+SOBJS +=	${${T}_FUNCS:S/$/.pico/}
 
 ${${T}_OBJS_T}: ${${T}_CFILE} ${COMMONHDRS}
 	${CC_T} ${${T}_CFLAGS} -DL${.PREFIX} -o ${.TARGET} ${.ALLSRC:M*.c}
@@ -274,7 +274,7 @@ ${${T}_OBJS_S}: ${${T}_CFILE} ${COMMONHDRS}
 # Extra objects coming from separate files
 #
 .if !empty(LIB2ADD)
-SOBJS +=	${LIB2ADD:R:S/$/.So/}
+SOBJS +=	${LIB2ADD:R:S/$/.pico/}
 .endif
 
 #-----------------------------------------------------------------------
@@ -298,9 +298,9 @@ ${STAT_OBJS_P}:	${STD_CFILE} ${COMMONHDRS}
 .if defined(LIB1ASMSRC)
 ASM_T =		${LIB1ASMFUNCS:S/$/.o/}
 ASM_P =		${LIB1ASMFUNCS:S/$/.po/}
-ASM_S =		${LIB1ASMFUNCS:S/$/.So/}
+ASM_S =		${LIB1ASMFUNCS:S/$/.pico/}
 ASM_V =		${LIB1ASMFUNCS:S/$/.vis/}
-SOBJS +=	${LIB1ASMFUNCS:S/$/.So/}
+SOBJS +=	${LIB1ASMFUNCS:S/$/.pico/}
 
 ${ASM_T}: ${LIB1ASMSRC} ${.PREFIX}.vis
 	${CC} -x assembler-with-cpp -c ${CFLAGS} -DL${.PREFIX} \
@@ -327,7 +327,7 @@ CLEANFILES += ${ASM_V} ${ASM_V:R:S/$/.vo/}
 #
 EH_OBJS_T = ${LIB2ADDEHSTATIC:R:S/$/.o/}
 EH_OBJS_P = ${LIB2ADDEHSTATIC:R:S/$/.po/}
-EH_OBJS_S = ${LIB2ADDEHSHARED:R:S/$/.So/}
+EH_OBJS_S = ${LIB2ADDEHSHARED:R:S/$/.pico/}
 EH_CFLAGS = -fexceptions -D__GLIBC__=3 -DElfW=__ElfN
 .if ${TARGET_CPUARCH} != "riscv64"
 # RISCVTODO: unwinding support
@@ -341,7 +341,7 @@ ${_src:R:S/$/.po/}: ${_src} ${COMMONHDRS}
 	${CC_P} ${EH_CFLAGS} -o ${.TARGET} ${.IMPSRC}
 .endfor
 .for _src in ${LIB2ADDEHSHARED:M*.c}
-${_src:R:S/$/.So/}: ${_src} ${COMMONHDRS}
+${_src:R:S/$/.pico/}: ${_src} ${COMMONHDRS}
 	${CC_S} ${EH_CFLAGS} -o ${.TARGET} ${.IMPSRC}
 .endfor
 
diff --git a/gnu/lib/libgcov/Makefile b/gnu/lib/libgcov/Makefile
index 65d0fdb55a7f..740b1101e5a6 100644
--- a/gnu/lib/libgcov/Makefile
+++ b/gnu/lib/libgcov/Makefile
@@ -35,7 +35,7 @@ SYMS = _gcov _gcov_merge_add _gcov_merge_single _gcov_merge_delta \
 OBJS=		${SYMS:S/$/.o/}
 OBJS_T=		${SYMS:S/$/.o/}
 OBJS_P=		${SYMS:S/$/.po/}
-OBJS_S=		${SYMS:S/$/.So/}
+OBJS_S=		${SYMS:S/$/.pico/}
 
 #-----------------------------------------------------------------------
 #
diff --git a/include/libgen.h b/include/libgen.h
index ef871afbf4b2..5b79f3619d80 100644
--- a/include/libgen.h
+++ b/include/libgen.h
@@ -48,11 +48,11 @@ __END_DECLS
  *
  * Apply a workaround where we explicitly link against dirname@FBSD_1.0
  * in case this function is called on constant strings, instead of
- * making the build fail.
+ * making the program crash at runtime.
  */
 #if defined(__generic) && !defined(__cplusplus)
 __BEGIN_DECLS
-char	*__old_dirname(const char *);
+char	*__old_dirname(char *);
 __END_DECLS
 __sym_compat(dirname, __old_dirname, FBSD_1.0);
 #define	dirname(x)	__generic(x, const char *, __old_dirname, dirname)(x)
diff --git a/lib/libc/aarch64/string/Makefile.inc b/lib/libc/aarch64/string/Makefile.inc
new file mode 100644
index 000000000000..218a635da1e1
--- /dev/null
+++ b/lib/libc/aarch64/string/Makefile.inc
@@ -0,0 +1,19 @@
+# $FreeBSD$
+#
+# String handling from the Cortex Strings library
+# https://git.linaro.org/toolchain/cortex-strings.git
+#
+
+.PATH: ${LIBC_SRCTOP}/../../contrib/cortex-strings/src/aarch64
+
+MDSRCS+=memchr.S \
+	memcmp.S \
+	memcpy.S \
+	memmove.S \
+	memset.S \
+	strchr.S \
+	strcmp.S \
+	strcpy.S \
+	strlen.S \
+	strncmp.S \
+	strnlen.S
diff --git a/lib/libc/gen/dirname.3 b/lib/libc/gen/dirname.3
index 18405f9af6ef..60f44e298614 100644
--- a/lib/libc/gen/dirname.3
+++ b/lib/libc/gen/dirname.3
@@ -16,7 +16,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd August 12, 2016
+.Dd September 5, 2016
 .Dt DIRNAME 3
 .Os
 .Sh NAME
@@ -60,11 +60,6 @@ space instead.
 The advantage of the former approach is that it ensures thread-safety,
 while also placing no upper limit on the supported length of the
 pathname.
-.Pp
-The algorithm used by this implementation also discards redundant
-slashes and
-.Qq \&.
-pathname components from the pathname string.
 .Sh SEE ALSO
 .Xr basename 1 ,
 .Xr dirname 1 ,
diff --git a/lib/libc/gen/dirname.c b/lib/libc/gen/dirname.c
index 621122b90c40..ae7b928d54eb 100644
--- a/lib/libc/gen/dirname.c
+++ b/lib/libc/gen/dirname.c
@@ -27,64 +27,47 @@
 __FBSDID("$FreeBSD$");
 
 #include <libgen.h>
-#include <stdbool.h>
 #include <string.h>
 
 char *
 (dirname)(char *path)
 {
-	const char *in, *prev, *begin, *end;
-	char *out;
-	size_t prevlen;
-	bool skipslash;
+	char *end;
 
 	/*
 	 * If path is a null pointer or points to an empty string,
 	 * dirname() shall return a pointer to the string ".".
 	 */
 	if (path == NULL || *path == '\0')
-		return ((char *)".");
+		return (__DECONST(char *, "."));
 
-	/* Retain at least one leading slash character. */
-	in = out = *path == '/' ? path + 1 : path;
+	/* Find end of last pathname component. */
+	end = path + strlen(path);
+	while (end > path + 1 && *(end - 1) == '/')
+		--end;
 
-	skipslash = true;
-	prev = ".";
-	prevlen = 1;
-	for (;;) {
-		/* Extract the next pathname component. */
-		while (*in == '/')
-			++in;
-		begin = in;
-		while (*in != '/' && *in != '\0')
-			++in;
-		end = in;
-		if (begin == end)
-			break;
-
-		/*
-		 * Copy over the previous pathname component, except if
-		 * it's dot. There is no point in retaining those.
-		 */
-		if (prevlen != 1 || *prev != '.') {
-			if (!skipslash)
-				*out++ = '/';
-			skipslash = false;
-			memmove(out, prev, prevlen);
-			out += prevlen;
-		}
-
-		/* Preserve the pathname component for the next iteration. */
-		prev = begin;
-		prevlen = end - begin;
-	}
+	/* Strip off the last pathname component. */
+	while (end > path && *(end - 1) != '/')
+		--end;
 
 	/*
 	 * If path does not contain a '/', then dirname() shall return a
 	 * pointer to the string ".".
 	 */
-	if (out == path)
-		*out++ = '.';
-	*out = '\0';
+	if (end == path) {
+		path[0] = '.';
+		path[1] = '\0';
+		return (path);
+	}
+
+	/*
+	 * Remove trailing slashes from the resulting directory name. Ensure
+	 * that at least one character remains.
+	 */
+	while (end > path + 1 && *(end - 1) == '/')
+		--end;
+
+	/* Null terminate directory name and return it. */
+	*end = '\0';
 	return (path);
 }
diff --git a/lib/libc/stdtime/strptime.c b/lib/libc/stdtime/strptime.c
index 2be6358fdde7..89703ec8be3c 100644
--- a/lib/libc/stdtime/strptime.c
+++ b/lib/libc/stdtime/strptime.c
@@ -301,10 +301,11 @@ label:
 			 * XXX This is bogus if parsed before hour-related
 			 * specifiers.
 			 */
+			if (tm->tm_hour > 12)
+				return (NULL);
+
 			len = strlen(tptr->am);
 			if (strncasecmp_l(buf, tptr->am, len, locale) == 0) {
-				if (tm->tm_hour > 12)
-					return (NULL);
 				if (tm->tm_hour == 12)
 					tm->tm_hour = 0;
 				buf += len;
@@ -313,8 +314,6 @@ label:
 
 			len = strlen(tptr->pm);
 			if (strncasecmp_l(buf, tptr->pm, len, locale) == 0) {
-				if (tm->tm_hour > 12)
-					return (NULL);
 				if (tm->tm_hour != 12)
 					tm->tm_hour += 12;
 				buf += len;
@@ -374,15 +373,17 @@ label:
 
 			break;
 
+		case 'u':
 		case 'w':
 			if (!isdigit_l((unsigned char)*buf, locale))
 				return (NULL);
 
-			i = *buf - '0';
-			if (i > 6)
+			i = *buf++ - '0';
+			if (i < 0 || i > 7 || (c == 'u' && i < 1) ||
+			    (c == 'w' && i > 6))
 				return (NULL);
 
-			tm->tm_wday = i;
+			tm->tm_wday = i % 7;
 			flags |= FLAG_WDAY;
 
 			break;
@@ -581,10 +582,16 @@ label:
 					i *= 10;
 					i += *buf - '0';
 					buf++;
+				} else if (len == 2) {
+					i *= 100;
+					break;
 				} else
 					return (NULL);
 			}
 
+			if (i > 1400 || (sign == -1 && i > 1200) ||
+			    (i % 100) >= 60)
+				return (NULL);
 			tm->tm_hour -= sign * (i / 100);
 			tm->tm_min  -= sign * (i % 100);
 			*GMTp = 1;
@@ -609,17 +616,28 @@ label:
 			    TM_YEAR_BASE)][tm->tm_mon] + (tm->tm_mday - 1);
 			flags |= FLAG_YDAY;
 		} else if (day_offset != -1) {
+			int tmpwday, tmpyday, fwo;
+
+			fwo = first_wday_of(tm->tm_year + TM_YEAR_BASE);
+			/* No incomplete week (week 0). */
+			if (week_offset == 0 && fwo == day_offset)
+				return (NULL);
+
 			/* Set the date to the first Sunday (or Monday)
 			 * of the specified week of the year.
 			 */
-			if (!(flags & FLAG_WDAY)) {
-				tm->tm_wday = day_offset;
-				flags |= FLAG_WDAY;
+			tmpwday = (flags & FLAG_WDAY) ? tm->tm_wday :
+			    day_offset;
+			tmpyday = (7 - fwo + day_offset) % 7 +
+			    (week_offset - 1) * 7 +
+			    (tmpwday - day_offset + 7) % 7;
+			/* Impossible yday for incomplete week (week 0). */
+			if (tmpyday < 0) {
+				if (flags & FLAG_WDAY)
+					return (NULL);
+				tmpyday = 0;
 			}
-			tm->tm_yday = (7 -
-			    first_wday_of(tm->tm_year + TM_YEAR_BASE) +
-			    day_offset) % 7 + (week_offset - 1) * 7 +
-			    tm->tm_wday - day_offset;
+			tm->tm_yday = tmpyday;
 			flags |= FLAG_YDAY;
 		}
 	}
diff --git a/lib/libc/sys/Makefile.inc b/lib/libc/sys/Makefile.inc
index 1a00cab687d2..9e83a7f1e3ff 100644
--- a/lib/libc/sys/Makefile.inc
+++ b/lib/libc/sys/Makefile.inc
@@ -260,6 +260,7 @@ MAN+=	abort2.2 \
 	pselect.2 \
 	ptrace.2 \
 	quotactl.2 \
+	rctl_add_rule.2 \
 	read.2 \
 	readlink.2 \
 	reboot.2 \
@@ -423,6 +424,10 @@ MLINKS+=pdfork.2 pdgetpid.2\
 	pdfork.2 pdwait4.2
 MLINKS+=pipe.2 pipe2.2
 MLINKS+=poll.2 ppoll.2
+MLINKS+=rctl_add_rule.2 rctl_get_limits.2 \
+	rctl_add_rule.2 rctl_get_racct.2 \
+	rctl_add_rule.2 rctl_get_rules.2 \
+	rctl_add_rule.2 rctl_remove_rule.2
 MLINKS+=read.2 pread.2 \
 	read.2 preadv.2 \
 	read.2 readv.2
diff --git a/lib/libc/sys/cap_enter.2 b/lib/libc/sys/cap_enter.2
index 6879b4b57821..1186f22d5e6a 100644
--- a/lib/libc/sys/cap_enter.2
+++ b/lib/libc/sys/cap_enter.2
@@ -28,7 +28,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd September 10, 2016
+.Dd September 22, 2016
 .Dt CAP_ENTER 2
 .Os
 .Sh NAME
@@ -69,6 +69,34 @@ appropriately-crafted applications or application components may be run.
 .Fn cap_getmode
 returns a flag indicating whether or not the process is in a capability mode
 sandbox.
+.Sh RUN-TIME SETTINGS
+If the
+.Dv kern.trap_enocap
+sysctl MIB is set to non-zero value, then for any process executing in a
+capability mode sandbox, any syscall which results in either
+.Er ENOTCAPABLE
+or
+.Er ECAPMODE
+error, also generates the synchronous
+.Dv SIGTRAP
+signal to the thread on the syscall return.
+On the signal delivery, the
+.Va si_errno
+member of the
+.Fa siginfo
+signal handler parameter is set to the syscall error value,
+and the
+.Va si_code
+member is set to
+.Dv TRAP_CAP .
+.Pp
+See also the
+.Dv PROC_TRAPCAP_CTL
+and
+.Dv PROC_TRAPCAP_STATUS
+operations of the
+.Xr procctl 2
+function for similar per-process functionality.
 .Sh CAVEAT
 Creating effective process sandboxes is a tricky process that involves
 identifying the least possible rights required by the process and then
@@ -116,6 +144,8 @@ points outside the process's allocated address space.
 .Xr cap_fcntls_limit 2 ,
 .Xr cap_ioctls_limit 2 ,
 .Xr cap_rights_limit 2 ,
+.Xr procctl 2 ,
+.Xr sysctl 2 ,
 .Xr fexecve 2 ,
 .Xr cap_sandboxed 3 ,
 .Xr capsicum 4
diff --git a/lib/libc/sys/posix_openpt.2 b/lib/libc/sys/posix_openpt.2
index b7e345c159f4..01a372931af8 100644
--- a/lib/libc/sys/posix_openpt.2
+++ b/lib/libc/sys/posix_openpt.2
@@ -37,7 +37,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd March 21, 2013
+.Dd September 21, 2016
 .Dt POSIX_OPENPT 2
 .Os
 .Sh NAME
@@ -46,8 +46,8 @@
 .Sh LIBRARY
 .Lb libc
 .Sh SYNOPSIS
-.In stdlib.h
 .In fcntl.h
+.In stdlib.h
 .Ft int
 .Fn posix_openpt "int oflag"
 .Sh DESCRIPTION
diff --git a/lib/libc/sys/procctl.2 b/lib/libc/sys/procctl.2
index 88dcfd3d405b..7d2fc728206b 100644
--- a/lib/libc/sys/procctl.2
+++ b/lib/libc/sys/procctl.2
@@ -29,7 +29,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd August 21, 2015
+.Dd September 22, 2016
 .Dt PROCCTL 2
 .Os
 .Sh NAME
@@ -71,7 +71,7 @@ The control request to perform is specified by the
 .Fa cmd
 argument.
 The following commands are supported:
-.Bl -tag -width "PROC_REAP_GETPIDS"
+.Bl -tag -width "Dv PROC_TRAPCAP_STATUS"
 .It Dv PROC_SPROTECT
 Set process protection state.
 This is used to mark a process as protected from being killed if the system
@@ -327,6 +327,63 @@ is set to 0.
 If a debugger is attached,
 .Fa data
 is set to the pid of the debugger process.
+.It Dv PROC_TRAPCAP_CTL
+Enable or disable, for the specified processes which are executing in a
+capability mode sandbox, the synchronous
+.Dv SIGTRAP
+signal on return from any syscall which gives either
+.Er ENOTCAPABLE
+or
+.Er ECAPMODE
+error.
+.Pp
+Possible values for the
+.Fa data
+argument are:
+.Bl -tag -width "Dv PROC_TRAPCAP_CTL_DISABLE"
+.It Dv PROC_TRAPCAP_CTL_ENABLE
+Enable the
+.Dv SIGTRAP
+signal delivery on capability mode access violations.
+The enabled mode is inherited by the children of the process,
+and is kept after
+.Xr fexecve 2
+calls.
+.It Dv PROC_TRAPCAP_CTL_DISABLE
+Disable the signal delivery on capability mode access violations.
+Note that the global sysctl
+.Dv kern.trap_enocap
+might still cause the signal to be delivered; see
+.Xr capsicum 4 .
+.El
+.Pp
+On signal delivery, the
+.Va si_errno
+member of the
+.Fa siginfo
+signal handler parameter is set to the syscall error value,
+and the
+.Va si_code
+member is set to
+.Dv TRAP_CAP .
+.Pp
+See
+.Xr capsicum 4
+for more information about the capability mode.
+.It Dv PROC_TRAPCAP_STATUS
+Returns the current status of signalling capability mode access
+violations for the specified process.
+The integer value pointed to by the
+.Fa data
+argument is set to the
+.Dv PROC_TRAPCAP_CTL_ENABLE
+value if the process control enables signal delivery, and to
+.Dv PROC_TRAPCAP_CTL_DISABLE
+otherwise.
+.Pp
+See the note about sysctl
+.Dv kern.trap_enocap
+above, which gives independent global control of signal delivery.
 .El
 .Sh NOTES
 Disabling tracing on a process should not be considered a security
@@ -420,14 +477,18 @@ The value of the integer
 .Fa data
 parameter for the
 .Dv PROC_TRACE_CTL
+or
+.Dv PROC_TRAPCAP_CTL
 request is invalid.
 .El
 .Sh SEE ALSO
 .Xr dtrace 1 ,
+.Xr cap_enter 2,
 .Xr kill 2 ,
 .Xr ktrace 2 ,
 .Xr ptrace 2 ,
 .Xr wait 2 ,
+.Xr capsicum 4 ,
 .Xr hwpmc 4 ,
 .Xr init 8
 .Sh HISTORY
diff --git a/lib/libc/sys/rctl_add_rule.2 b/lib/libc/sys/rctl_add_rule.2
new file mode 100644
index 000000000000..667a0059470d
--- /dev/null
+++ b/lib/libc/sys/rctl_add_rule.2
@@ -0,0 +1,220 @@
+.\" Copyright (c) 2016 Eric Badger
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd September 14, 2016
+.Dt RCTL_ADD_RULE 2
+.Os
+.Sh NAME
+.Nm rctl_add_rule,
+.Nm rctl_get_limits
+.Nm rctl_get_racct,
+.Nm rctl_get_rules,
+.Nm rctl_remove_rule
+.Nd manipulate and query the resource limits database
+.Sh LIBRARY
+.Lb libc
+.Sh SYNOPSIS
+.In sys/rctl.h
+.Ft int
+.Fo rctl_add_rule
+.Fa "const char *inbufp" "size_t inbuflen" "char *outbufp" "size_t outbuflen"
+.Fc
+.Ft int
+.Fo rctl_get_limits
+.Fa "const char *inbufp" "size_t inbuflen" "char *outbufp" "size_t outbuflen"
+.Fc
+.Ft int
+.Fo rctl_get_racct
+.Fa "const char *inbufp" "size_t inbuflen" "char *outbufp" "size_t outbuflen"
+.Fc
+.Ft int
+.Fo rctl_get_rules
+.Fa "const char *inbufp" "size_t inbuflen" "char *outbufp" "size_t outbuflen"
+.Fc
+.Ft int
+.Fo rctl_remove_rule
+.Fa "const char *inbufp" "size_t inbuflen" "char *outbufp" "size_t outbuflen"
+.Fc
+.Sh DESCRIPTION
+These system calls are used to manipulate and query the resource limits
+database.
+For all functions,
+.Fa inbuflen
+refers to the length of the buffer pointed to by
+.Fa inbufp
+and
+.Fa outbuflen
+refers to the length of the buffer pointed to by
+.Fa outbufp .
+.Pp
+The
+.Fn rctl_add_rule
+function adds the rule pointed to by
+.Fa inbufp
+to the resource limits database.
+The
+.Fa outbufp
+and
+.Fa outbuflen
+arguments are unused.
+Rule format is as described in
+.Xr rctl 8 ,
+with exceptions noted in the
+.Sx RULES AND FILTERS
+section.
+.Pp
+The
+.Fn rctl_get_limits
+function returns in
+.Fa outbufp
+a comma-separated list of rules that apply to the process that
+matches the filter specified in
+.Fa inbufp .
+This includes rules with a subject of the process itself as well as rules
+with a different subject (such as user or loginclass) that apply to the
+process.
+.Pp
+The
+.Fn rctl_get_racct
+function returns resource usage information for a given subject.
+The subject is specified by passing a filter in
+.Fa inbufp .
+Filter syntax is as described in
+.Xr rctl 8 ,
+with exceptions noted in the
+.Sx RULES AND FILTERS
+section.
+A comma-separated list of resources and the amount used of each by the
+specified subject is returned in
+.Fa outbufp .
+The resource and amount is formatted as
+.Qq resource=amount .
+.Pp
+The
+.Fn rctl_get_rules
+function returns in
+.Fa outbufp
+a comma-separated list of rules from the resource limits database that
+match the filter passed in
+.Fa inbufp .
+Filter syntax is as described in
+.Xr rctl 8 ,
+with exceptions noted in the
+.Sx RULES AND FILTERS
+section.
+A filter of
+.Va ::
+may be passed to return all rules.
+.Pp
+The
+.Fn rctl_remove_rule
+function removes all rules matching the filter passed in
+.Fa inbufp
+from the resource limits database.
+Filter syntax is as described in
+.Xr rctl 8 ,
+with exceptions noted in the
+.Sx RULES AND FILTERS
+section.
+.Fa outbufp
+and
+.Fa outbuflen
+are unused.
+.Sh RULES AND FILTERS
+This section explains how the rule and filter format described in
+.Xr rctl 8
+differs from the format passed to the system calls themselves.
+The rctl tool provides several conveniences that the system calls do not.
+When using the system call:
+.Bl -dash -offset indent
+.It
+The subject must be fully specified.
+For example, abbreviating
+.Ql user
+to
+.Ql u
+is not acceptable.
+.It
+User and group IDs must be numeric.
+For example,
+.Ql root
+must be expressed as
+.Ql 0 .
+.It
+Units are not permitted on resource amounts.
+For example, a quantity of 1024 bytes must be expressed as
+.Ql 1024
+and not
+.Ql 1k .
+.El
+.Sh RETURN VALUES
+.Rv -std
+.Sh ERRORS
+The rctl system calls may fail if:
+.Bl -tag -width Er
+.It Bq Er ENOSYS
+RACCT/RCTL support is not present in the kernel or the
+.Va kern.racct.enable
+sysctl is 0.
+.It Bq Er EINVAL
+The rule or filter passed in
+.Fa inbufp
+is invalid.
+.It Bq Er EPERM
+User has insufficient privileges to carry out the requested operation.
+.It Bq Er E2BIG
+.Fa inbufp
+or
+.Fa outbufp
+are too large.
+.It Bq Er ESRCH
+No process matched the provided rule or filter.
+.It Bq Er ENAMETOOLONG
+The loginclass or jail name specified is too long.
+.It Bq Er ERANGE
+The rule amount is outside of the allowable range or
+.Fa outbufp
+is too small.
+.It Bq Er EOPNOTSUPP
+The requested operation is not supported for the given rule or filter.
+.It Bq Er EFAULT
+.Fa inbufp
+or
+.Fa outbufp
+refer to invalid addresses.
+.El
+.Sh SEE ALSO
+.Xr rctl 8
+.Sh HISTORY
+The rctl family of system calls appeared in
+.Fx 9.0 .
+.Sh AUTHORS
+.An -nosplit
+The rctl system calls were developed by
+.An Edward Tomasz Napierala Aq Mt trasz@FreeBSD.org
+under sponsorship from the FreeBSD Foundation.
+This manual page was written by
+.An Eric Badger Aq Mt badger@FreeBSD.org .
diff --git a/lib/libc/tests/iconv/Makefile b/lib/libc/tests/iconv/Makefile
index e6ae03e9d324..635c26c7cfb7 100644
--- a/lib/libc/tests/iconv/Makefile
+++ b/lib/libc/tests/iconv/Makefile
@@ -1,7 +1,5 @@
 # $FreeBSD$
 
-PACKAGE=	tests
-
 TESTSDIR=	${TESTSBASE}/lib/libc/iconv
 
 ATF_TESTS_C+=	iconvctl_test
diff --git a/lib/libc/tests/stdio/open_memstream2_test.c b/lib/libc/tests/stdio/open_memstream2_test.c
index 3c9e3ec30eb2..21ea64c7c669 100644
--- a/lib/libc/tests/stdio/open_memstream2_test.c
+++ b/lib/libc/tests/stdio/open_memstream2_test.c
@@ -159,11 +159,11 @@ ATF_TC_BODY(seek_tests, tc)
 #define SEEK_FAIL(offset, whence, error) do {			\
 	errno = 0;						\
 	ATF_REQUIRE_MSG(fseeko(fp, (offset), (whence)) != 0,	\
-	    "fseeko(%s, %s) did not fail, set pos to %jd\n",	\
+	    "fseeko(%s, %s) did not fail, set pos to %jd",	\
 	    __STRING(offset), __STRING(whence),			\
 	    (intmax_t)ftello(fp));				\
 	ATF_REQUIRE_MSG(errno == (error),			\
-	    "fseeko(%s, %s) failed with %d rather than %s\n",	\
+	    "fseeko(%s, %s) failed with %d rather than %s",	\
 	    __STRING(offset), __STRING(whence),	errno,		\
 	    __STRING(error));					\
 } while (0)
@@ -173,7 +173,7 @@ ATF_TC_BODY(seek_tests, tc)
 	    "fseeko(%s, %s) failed: %s",			\
 	    __STRING(offset), __STRING(whence), strerror(errno)); \
 	ATF_REQUIRE_MSG(ftello(fp) == (result),			\
-	    "fseeko(%s, %s) seeked to %jd rather than %s\n",	\
+	    "fseeko(%s, %s) seeked to %jd rather than %s",	\
 	    __STRING(offset), __STRING(whence),			\
 	    (intmax_t)ftello(fp), __STRING(result));		\
 } while (0)
diff --git a/lib/libc/tests/stdio/open_wmemstream_test.c b/lib/libc/tests/stdio/open_wmemstream_test.c
index d6ae2ea88e2c..324bcf3d3482 100644
--- a/lib/libc/tests/stdio/open_wmemstream_test.c
+++ b/lib/libc/tests/stdio/open_wmemstream_test.c
@@ -159,11 +159,11 @@ ATF_TC_BODY(seek_tests, tc)
 #define SEEK_FAIL(offset, whence, error) do {			\
 	errno = 0;						\
 	ATF_REQUIRE_MSG(fseeko(fp, (offset), (whence)) != 0,	\
-	    "fseeko(%s, %s) did not fail, set pos to %jd\n",	\
+	    "fseeko(%s, %s) did not fail, set pos to %jd",	\
 	    __STRING(offset), __STRING(whence),			\
 	    (intmax_t)ftello(fp));				\
 	ATF_REQUIRE_MSG(errno == (error),			\
-	    "fseeko(%s, %s) failed with %d rather than %s\n",	\
+	    "fseeko(%s, %s) failed with %d rather than %s",	\
 	    __STRING(offset), __STRING(whence),	errno,		\
 	    __STRING(error));					\
 } while (0)
@@ -173,7 +173,7 @@ ATF_TC_BODY(seek_tests, tc)
 	    "fseeko(%s, %s) failed: %s",			\
 	    __STRING(offset), __STRING(whence), strerror(errno)); \
 	ATF_REQUIRE_MSG(ftello(fp) == (result),			\
-	    "fseeko(%s, %s) seeked to %jd rather than %s\n",	\
+	    "fseeko(%s, %s) seeked to %jd rather than %s",	\
 	    __STRING(offset), __STRING(whence),			\
 	    (intmax_t)ftello(fp), __STRING(result));		\
 } while (0)
diff --git a/lib/libc/tests/stdio/printbasic_test.c b/lib/libc/tests/stdio/printbasic_test.c
index 376981e1855a..bebb73427bb3 100644
--- a/lib/libc/tests/stdio/printbasic_test.c
+++ b/lib/libc/tests/stdio/printbasic_test.c
@@ -80,7 +80,7 @@ _testfmt(const char *result, const char *argstr, const char *fmt,...)
 	vsnprintf(s, sizeof(s), fmt, ap);
 	if (strcmp(result, s) != 0) {
 		atf_tc_fail(
-		    "printf(\"%s\", %s) ==> [%s], expected [%s]\n",
+		    "printf(\"%s\", %s) ==> [%s], expected [%s]",
 		    fmt, argstr, s, result);
 	}
 
@@ -91,7 +91,7 @@ _testfmt(const char *result, const char *argstr, const char *fmt,...)
 	vswprintf(ws, sizeof(ws) / sizeof(ws[0]), wfmt, ap2);
 	if (wcscmp(wresult, ws) != 0) {
 		atf_tc_fail(
-		    "wprintf(\"%ls\", %s) ==> [%ls], expected [%ls]\n",
+		    "wprintf(\"%ls\", %s) ==> [%ls], expected [%ls]",
 		    wfmt, argstr, ws, wresult);
 	}
 	va_end(ap);
diff --git a/lib/libc/tests/stdio/printfloat_test.c b/lib/libc/tests/stdio/printfloat_test.c
index 2319747ceceb..974374fae5ca 100644
--- a/lib/libc/tests/stdio/printfloat_test.c
+++ b/lib/libc/tests/stdio/printfloat_test.c
@@ -72,7 +72,7 @@ _testfmt(const char *result, const char *argstr, const char *fmt,...)
 	vsnprintf(s, sizeof(s), fmt, ap);
 	if (strcmp(result, s) != 0) {
 		atf_tc_fail(
-		    "printf(\"%s\", %s) ==> [%s], expected [%s]\n",
+		    "printf(\"%s\", %s) ==> [%s], expected [%s]",
 		    fmt, argstr, s, result);
 	}
 
@@ -83,7 +83,7 @@ _testfmt(const char *result, const char *argstr, const char *fmt,...)
 	vswprintf(ws, sizeof(ws) / sizeof(ws[0]), wfmt, ap2);
 	if (wcscmp(wresult, ws) != 0) {
 		atf_tc_fail(
-		    "wprintf(\"%ls\", %s) ==> [%ls], expected [%ls]\n",
+		    "wprintf(\"%ls\", %s) ==> [%ls], expected [%ls]",
 		    wfmt, argstr, ws, wresult);
 	}
 	va_end(ap);
diff --git a/lib/libc/tests/sys/Makefile b/lib/libc/tests/sys/Makefile
index 4c2b3cf58554..42427e841dc0 100644
--- a/lib/libc/tests/sys/Makefile
+++ b/lib/libc/tests/sys/Makefile
@@ -1,5 +1,7 @@
 # $FreeBSD$
 
+PACKAGE=			tests
+
 .include <bsd.own.mk>
 
 ATF_TESTS_C+=			queue_test
diff --git a/lib/libedit/Makefile b/lib/libedit/Makefile
index 14c9cbbcc175..a75c9d2fcb6d 100644
--- a/lib/libedit/Makefile
+++ b/lib/libedit/Makefile
@@ -76,7 +76,7 @@ historyn.c: makelist Makefile
 	sh ${.CURDIR}/makelist -n history.c > ${.TARGET}
 
 # minimal dependency to make "make depend" optional
-editline.o editline.po editline.So editline.ln:	\
+editline.o editline.po editline.pico editline.ln:	\
 	common.h emacs.h fcns.c fcns.h help.c help.h vi.h
 
 tc1.o: ${.CURDIR}/TEST/tc1.c
diff --git a/lib/libprocstat/Makefile b/lib/libprocstat/Makefile
index 240718dd9cd6..1e6f43686157 100644
--- a/lib/libprocstat/Makefile
+++ b/lib/libprocstat/Makefile
@@ -58,13 +58,13 @@ MLINKS+=libprocstat.3 procstat_close.3 \
 .if ${MK_CDDL} != "no"
 CFLAGS+=	-DLIBPROCSTAT_ZFS
 OBJS+=	zfs/zfs.o
-SOBJS+=	zfs/zfs.So
+SOBJS+=	zfs/zfs.pico
 POBJS+=	zfs/zfs.po
 SUBDIR=	zfs
 zfs/zfs.o: .PHONY
 	@cd ${.CURDIR}/zfs && ${MAKE} zfs.o
-zfs/zfs.So: .PHONY
-	@cd ${.CURDIR}/zfs && ${MAKE} zfs.So
+zfs/zfs.pico: .PHONY
+	@cd ${.CURDIR}/zfs && ${MAKE} zfs.pico
 zfs/zfs.po: .PHONY
 	@cd ${.CURDIR}/zfs && ${MAKE} zfs.po
 .endif
diff --git a/lib/libprocstat/common_kvm.c b/lib/libprocstat/common_kvm.c
index be05980f183f..4ca25145b75d 100644
--- a/lib/libprocstat/common_kvm.c
+++ b/lib/libprocstat/common_kvm.c
@@ -45,6 +45,8 @@ __FBSDID("$FreeBSD$");
 #include <sys/mount.h>
 #include <ufs/ufs/quota.h>
 #include <ufs/ufs/inode.h>
+#include <ufs/ufs/extattr.h>
+#include <ufs/ufs/ufsmount.h>
 #include <fs/devfs/devfs.h>
 #include <fs/devfs/devfs_int.h>
 #undef _KERNEL
@@ -88,17 +90,22 @@ int
 ufs_filestat(kvm_t *kd, struct vnode *vp, struct vnstat *vn)
 {
 	struct inode inode;
+	struct ufsmount um;
 
 	if (!kvm_read_all(kd, (unsigned long)VTOI(vp), &inode, sizeof(inode))) {
 		warnx("can't read inode at %p", (void *)VTOI(vp));
 		return (1);
 	}
+	if (!kvm_read_all(kd, (unsigned long)inode.i_ump, &um, sizeof(um))) {
+		warnx("can't read ufsmount at %p", (void *)inode.i_ump);
+		return (1);
+	}
 	/*
 	 * The st_dev from stat(2) is a dev_t. These kernel structures
 	 * contain cdev pointers. We need to convert to dev_t to make
 	 * comparisons
 	 */
-	vn->vn_fsid = dev2udev(kd, inode.i_dev);
+	vn->vn_fsid = dev2udev(kd, um.um_dev);
 	vn->vn_fileid = inode.i_number;
 	vn->vn_mode = (mode_t)inode.i_mode;
 	vn->vn_size = inode.i_size;
diff --git a/lib/libthr/support/Makefile.inc b/lib/libthr/support/Makefile.inc
index 35a15f859264..1814f8a5f3da 100644
--- a/lib/libthr/support/Makefile.inc
+++ b/lib/libthr/support/Makefile.inc
@@ -15,15 +15,15 @@ CFLAGS+= -I${.CURDIR}/../libc/${MACHINE_CPUARCH}
 SYSCALLS= thr_new
 
 SYSCALL_SRC=   ${SYSCALLS:S/$/.S/}
-SYSCALL_OBJ=   ${SYSCALLS:S/$/.So/}
+SYSCALL_OBJ=   ${SYSCALLS:S/$/.pico/}
 
 ${SYSCALL_SRC}:
 	printf '#include "SYS.h"\nRSYSCALL(${.PREFIX})\n' > ${.TARGET}
 
 LIBC_OBJS=
 
-SOBJS+=	thr_libc.So
+SOBJS+=	thr_libc.pico
 CLEANFILES+= ${SYSCALL_SRC} ${SYSCALL_OBJ} ${LIBC_OBJS}
 
-thr_libc.So: ${SYSCALL_OBJ} ${LIBC_OBJS}
+thr_libc.pico: ${SYSCALL_OBJ} ${LIBC_OBJS}
 	${CC} -fPIC -nostdlib -o ${.TARGET} -r ${.ALLSRC}
diff --git a/lib/libutil/tests/pidfile_test.c b/lib/libutil/tests/pidfile_test.c
index 0b70bc80152b..42a7be4db849 100644
--- a/lib/libutil/tests/pidfile_test.c
+++ b/lib/libutil/tests/pidfile_test.c
@@ -30,6 +30,7 @@ __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
 #include <sys/wait.h>
+#include <sys/event.h>
 
 #include <fcntl.h>
 #include <errno.h>
@@ -43,8 +44,8 @@ __FBSDID("$FreeBSD$");
 #include <libutil.h>
 
 /*
- * We need a signal handler so kill(2) will interrupt our child's
- * select(2) instead of killing it.
+ * We need a signal handler so kill(2) will interrupt the child
+ * instead of killing it.
  */
 static void
 signal_handler(int sig)
@@ -129,7 +130,9 @@ common_test_pidfile_child(const char *fn, int parent_open)
 	struct pidfh *pf = NULL;
 	pid_t other = 0, pid = 0;
 	int fd[2], serrno, status;
+	struct kevent event, ke;
 	char ch;
+	int kq;
 
 	unlink(fn);
 	if (pipe(fd) != 0)
@@ -166,10 +169,20 @@ common_test_pidfile_child(const char *fn, int parent_open)
 		if (pf == NULL)
 			_exit(1);
 		if (pidfile_write(pf) != 0)
-			_exit(1);
+			_exit(2);
+		kq = kqueue();
+		if (kq == -1)
+			_exit(3);
+		EV_SET(&ke, SIGINT, EVFILT_SIGNAL, EV_ADD, 0, 0, NULL);
+		/* Attach event to the kqueue. */
+		if (kevent(kq, &ke, 1, NULL, 0, NULL) != 0)
+			_exit(4);
+		/* Inform the parent we are ready to receive SIGINT */
 		if (write(fd[1], "*", 1) != 1)
-			_exit(1);
-		select(0, 0, 0, 0, 0);
+			_exit(5);
+		/* Wait for SIGINT received */
+		if (kevent(kq, NULL, 0, &event, 1, NULL) != 1)
+			_exit(6);
 		_exit(0);
 	}
 	// parent
diff --git a/libexec/atf/atf-check/Makefile b/libexec/atf/atf-check/Makefile
index 5bef488fc1b1..ca3c2efb6bfa 100644
--- a/libexec/atf/atf-check/Makefile
+++ b/libexec/atf/atf-check/Makefile
@@ -28,7 +28,7 @@
 .include <src.opts.mk>
 .include <bsd.init.mk>
 
-ATF=		${.CURDIR:H:H:H}/contrib/atf
+ATF=		${SRCTOP}/contrib/atf
 .PATH:		${ATF}/atf-sh
 
 PROG_CXX=	atf-check
diff --git a/libexec/atf/atf-sh/Makefile b/libexec/atf/atf-sh/Makefile
index f00683fa1e58..42cf5a5ed046 100644
--- a/libexec/atf/atf-sh/Makefile
+++ b/libexec/atf/atf-sh/Makefile
@@ -28,7 +28,7 @@
 .include <src.opts.mk>
 .include <bsd.init.mk>
 
-ATF=		${.CURDIR:H:H:H}/contrib/atf
+ATF=		${SRCTOP}/contrib/atf
 .PATH:		${ATF}/atf-sh
 
 PROG_CXX=	atf-sh
diff --git a/sbin/dhclient/tables.c b/sbin/dhclient/tables.c
index c7bac57e4772..1dcace9bdb04 100644
--- a/sbin/dhclient/tables.c
+++ b/sbin/dhclient/tables.c
@@ -400,6 +400,7 @@ unsigned char dhcp_option_default_priority_list[] = {
 	DHO_IRC_SERVER,
 	DHO_STREETTALK_SERVER,
 	DHO_STREETTALK_DA_SERVER,
+	DHO_DHCP_USER_CLASS_ID,
 	DHO_DOMAIN_SEARCH,
 
 	/* Presently-undefined options... */
diff --git a/sbin/mount/mount.c b/sbin/mount/mount.c
index debe3547a8ff..b33d9a3f71ef 100644
--- a/sbin/mount/mount.c
+++ b/sbin/mount/mount.c
@@ -705,17 +705,14 @@ getmntpt(const char *name)
 char *
 catopt(char *s0, const char *s1)
 {
-	size_t i;
 	char *cp;
 
 	if (s1 == NULL || *s1 == '\0')
 		return (s0);
 
 	if (s0 && *s0) {
-		i = strlen(s0) + strlen(s1) + 1 + 1;
-		if ((cp = malloc(i)) == NULL)
-			errx(1, "malloc failed");
-		(void)snprintf(cp, i, "%s,%s", s0, s1);
+		if (asprintf(&cp, "%s,%s", s0, s1) == -1)
+			errx(1, "asprintf failed");
 	} else
 		cp = strdup(s1);
 
diff --git a/sbin/mount_msdosfs/mount_msdosfs.8 b/sbin/mount_msdosfs/mount_msdosfs.8
index ae69aeb52e46..0f2da9cda0fd 100644
--- a/sbin/mount_msdosfs/mount_msdosfs.8
+++ b/sbin/mount_msdosfs/mount_msdosfs.8
@@ -142,15 +142,8 @@ If neither
 nor
 .Fl l
 are given,
-.Nm
-searches the root directory of the file system to
-be mounted for any existing Win'95 long filenames.
-If no such entries are found, but short DOS filenames are found,
-.Fl s
-is the default.
-Otherwise
 .Fl l
-is assumed.
+is the default.
 .It Fl 9
 Ignore the special Win'95 directory entries even
 if deleting or renaming a file.
diff --git a/sbin/sysctl/sysctl.c b/sbin/sysctl/sysctl.c
index f2d42a86405d..d9bd94d28bab 100644
--- a/sbin/sysctl/sysctl.c
+++ b/sbin/sysctl/sysctl.c
@@ -637,9 +637,6 @@ S_vmtotal(size_t l2, void *p)
 }
 
 #ifdef __amd64__
-#define efi_next_descriptor(ptr, size) \
-	((struct efi_md *)(((uint8_t *) ptr) + size))
-
 static int
 S_efi_map(size_t l2, void *p)
 {
diff --git a/secure/lib/libcrypto/Makefile.inc b/secure/lib/libcrypto/Makefile.inc
index 87cd37d7011d..7a95f5989ba2 100644
--- a/secure/lib/libcrypto/Makefile.inc
+++ b/secure/lib/libcrypto/Makefile.inc
@@ -3,8 +3,8 @@
 .include <bsd.own.mk>
 
 # OpenSSL version used for manual page generation
-OPENSSL_VER=	1.0.2h
-OPENSSL_DATE=	2016-05-03
+OPENSSL_VER=	1.0.2i
+OPENSSL_DATE=	2016-09-22
 
 LCRYPTO_SRC=	${.CURDIR}/../../../crypto/openssl
 LCRYPTO_DOC=	${LCRYPTO_SRC}/doc
diff --git a/secure/lib/libcrypto/Makefile.man b/secure/lib/libcrypto/Makefile.man
index 333aaaa4a7ea..0edce399e129 100644
--- a/secure/lib/libcrypto/Makefile.man
+++ b/secure/lib/libcrypto/Makefile.man
@@ -187,6 +187,7 @@ MAN+= d2i_DSAPublicKey.3
 MAN+= d2i_ECPKParameters.3
 MAN+= d2i_ECPrivateKey.3
 MAN+= d2i_PKCS8PrivateKey.3
+MAN+= d2i_PrivateKey.3
 MAN+= d2i_RSAPublicKey.3
 MAN+= d2i_X509.3
 MAN+= d2i_X509_ALGOR.3
@@ -977,6 +978,9 @@ MLINKS+= d2i_PKCS8PrivateKey.3 i2d_PKCS8PrivateKey_bio.3
 MLINKS+= d2i_PKCS8PrivateKey.3 i2d_PKCS8PrivateKey_fp.3
 MLINKS+= d2i_PKCS8PrivateKey.3 i2d_PKCS8PrivateKey_nid_bio.3
 MLINKS+= d2i_PKCS8PrivateKey.3 i2d_PKCS8PrivateKey_nid_fp.3
+MLINKS+= d2i_PrivateKey.3 d2i_Private_key.3
+MLINKS+= d2i_PrivateKey.3 d2i_AutoPrivateKey.3
+MLINKS+= d2i_PrivateKey.3 i2d_PrivateKey.3
 MLINKS+= d2i_RSAPublicKey.3 i2d_RSAPublicKey.3
 MLINKS+= d2i_RSAPublicKey.3 d2i_RSAPrivateKey.3
 MLINKS+= d2i_RSAPublicKey.3 i2d_RSAPrivateKey.3
diff --git a/secure/lib/libcrypto/amd64/ecp_nistz256-x86_64.S b/secure/lib/libcrypto/amd64/ecp_nistz256-x86_64.S
index fcaa9c1fb27e..7cd1db07d002 100644
--- a/secure/lib/libcrypto/amd64/ecp_nistz256-x86_64.S
+++ b/secure/lib/libcrypto/amd64/ecp_nistz256-x86_64.S
@@ -29,6 +29,7 @@ ecp_nistz256_mul_by_2:
 	pushq	%r13
 
 	movq	0(%rsi),%r8
+	xorq	%r13,%r13
 	movq	8(%rsi),%r9
 	addq	%r8,%r8
 	movq	16(%rsi),%r10
@@ -39,7 +40,7 @@ ecp_nistz256_mul_by_2:
 	adcq	%r10,%r10
 	adcq	%r11,%r11
 	movq	%r9,%rdx
-	sbbq	%r13,%r13
+	adcq	$0,%r13
 
 	subq	0(%rsi),%r8
 	movq	%r10,%rcx
@@ -47,14 +48,14 @@ ecp_nistz256_mul_by_2:
 	sbbq	16(%rsi),%r10
 	movq	%r11,%r12
 	sbbq	24(%rsi),%r11
-	testq	%r13,%r13
+	sbbq	$0,%r13
 
-	cmovzq	%rax,%r8
-	cmovzq	%rdx,%r9
+	cmovcq	%rax,%r8
+	cmovcq	%rdx,%r9
 	movq	%r8,0(%rdi)
-	cmovzq	%rcx,%r10
+	cmovcq	%rcx,%r10
 	movq	%r9,8(%rdi)
-	cmovzq	%r12,%r11
+	cmovcq	%r12,%r11
 	movq	%r10,16(%rdi)
 	movq	%r11,24(%rdi)
 
@@ -151,12 +152,12 @@ ecp_nistz256_mul_by_3:
 	sbbq	$0,%r10
 	movq	%r11,%r12
 	sbbq	.Lpoly+24(%rip),%r11
-	testq	%r13,%r13
+	sbbq	$0,%r13
 
-	cmovzq	%rax,%r8
-	cmovzq	%rdx,%r9
-	cmovzq	%rcx,%r10
-	cmovzq	%r12,%r11
+	cmovcq	%rax,%r8
+	cmovcq	%rdx,%r9
+	cmovcq	%rcx,%r10
+	cmovcq	%r12,%r11
 
 	xorq	%r13,%r13
 	addq	0(%rsi),%r8
@@ -173,14 +174,14 @@ ecp_nistz256_mul_by_3:
 	sbbq	$0,%r10
 	movq	%r11,%r12
 	sbbq	.Lpoly+24(%rip),%r11
-	testq	%r13,%r13
+	sbbq	$0,%r13
 
-	cmovzq	%rax,%r8
-	cmovzq	%rdx,%r9
+	cmovcq	%rax,%r8
+	cmovcq	%rdx,%r9
 	movq	%r8,0(%rdi)
-	cmovzq	%rcx,%r10
+	cmovcq	%rcx,%r10
 	movq	%r9,8(%rdi)
-	cmovzq	%r12,%r11
+	cmovcq	%r12,%r11
 	movq	%r10,16(%rdi)
 	movq	%r11,24(%rdi)
 
@@ -219,14 +220,14 @@ ecp_nistz256_add:
 	sbbq	16(%rsi),%r10
 	movq	%r11,%r12
 	sbbq	24(%rsi),%r11
-	testq	%r13,%r13
+	sbbq	$0,%r13
 
-	cmovzq	%rax,%r8
-	cmovzq	%rdx,%r9
+	cmovcq	%rax,%r8
+	cmovcq	%rdx,%r9
 	movq	%r8,0(%rdi)
-	cmovzq	%rcx,%r10
+	cmovcq	%rcx,%r10
 	movq	%r9,8(%rdi)
-	cmovzq	%r12,%r11
+	cmovcq	%r12,%r11
 	movq	%r10,16(%rdi)
 	movq	%r11,24(%rdi)
 
@@ -1463,13 +1464,14 @@ ecp_nistz256_avx2_select_w7:
 .type	__ecp_nistz256_add_toq,@function
 .align	32
 __ecp_nistz256_add_toq:
+	xorq	%r11,%r11
 	addq	0(%rbx),%r12
 	adcq	8(%rbx),%r13
 	movq	%r12,%rax
 	adcq	16(%rbx),%r8
 	adcq	24(%rbx),%r9
 	movq	%r13,%rbp
-	sbbq	%r11,%r11
+	adcq	$0,%r11
 
 	subq	$-1,%r12
 	movq	%r8,%rcx
@@ -1477,14 +1479,14 @@ __ecp_nistz256_add_toq:
 	sbbq	$0,%r8
 	movq	%r9,%r10
 	sbbq	%r15,%r9
-	testq	%r11,%r11
+	sbbq	$0,%r11
 
-	cmovzq	%rax,%r12
-	cmovzq	%rbp,%r13
+	cmovcq	%rax,%r12
+	cmovcq	%rbp,%r13
 	movq	%r12,0(%rdi)
-	cmovzq	%rcx,%r8
+	cmovcq	%rcx,%r8
 	movq	%r13,8(%rdi)
-	cmovzq	%r10,%r9
+	cmovcq	%r10,%r9
 	movq	%r8,16(%rdi)
 	movq	%r9,24(%rdi)
 
@@ -1552,13 +1554,14 @@ __ecp_nistz256_subq:
 .type	__ecp_nistz256_mul_by_2q,@function
 .align	32
 __ecp_nistz256_mul_by_2q:
+	xorq	%r11,%r11
 	addq	%r12,%r12
 	adcq	%r13,%r13
 	movq	%r12,%rax
 	adcq	%r8,%r8
 	adcq	%r9,%r9
 	movq	%r13,%rbp
-	sbbq	%r11,%r11
+	adcq	$0,%r11
 
 	subq	$-1,%r12
 	movq	%r8,%rcx
@@ -1566,14 +1569,14 @@ __ecp_nistz256_mul_by_2q:
 	sbbq	$0,%r8
 	movq	%r9,%r10
 	sbbq	%r15,%r9
-	testq	%r11,%r11
+	sbbq	$0,%r11
 
-	cmovzq	%rax,%r12
-	cmovzq	%rbp,%r13
+	cmovcq	%rax,%r12
+	cmovcq	%rbp,%r13
 	movq	%r12,0(%rdi)
-	cmovzq	%rcx,%r8
+	cmovcq	%rcx,%r8
 	movq	%r13,8(%rdi)
-	cmovzq	%r10,%r9
+	cmovcq	%r10,%r9
 	movq	%r8,16(%rdi)
 	movq	%r9,24(%rdi)
 
@@ -1811,16 +1814,14 @@ ecp_nistz256_point_add:
 	movq	%rdx,%rsi
 	movdqa	%xmm0,384(%rsp)
 	movdqa	%xmm1,384+16(%rsp)
-	por	%xmm0,%xmm1
 	movdqa	%xmm2,416(%rsp)
 	movdqa	%xmm3,416+16(%rsp)
-	por	%xmm2,%xmm3
 	movdqa	%xmm4,448(%rsp)
 	movdqa	%xmm5,448+16(%rsp)
-	por	%xmm1,%xmm3
+	por	%xmm4,%xmm5
 
 	movdqu	0(%rsi),%xmm0
-	pshufd	$0xb1,%xmm3,%xmm5
+	pshufd	$0xb1,%xmm5,%xmm3
 	movdqu	16(%rsi),%xmm1
 	movdqu	32(%rsi),%xmm2
 	por	%xmm3,%xmm5
@@ -1832,14 +1833,14 @@ ecp_nistz256_point_add:
 	movdqa	%xmm0,480(%rsp)
 	pshufd	$0x1e,%xmm5,%xmm4
 	movdqa	%xmm1,480+16(%rsp)
-	por	%xmm0,%xmm1
-.byte	102,72,15,110,199
+	movdqu	64(%rsi),%xmm0
+	movdqu	80(%rsi),%xmm1
 	movdqa	%xmm2,512(%rsp)
 	movdqa	%xmm3,512+16(%rsp)
-	por	%xmm2,%xmm3
 	por	%xmm4,%xmm5
 	pxor	%xmm4,%xmm4
-	por	%xmm1,%xmm3
+	por	%xmm0,%xmm1
+.byte	102,72,15,110,199
 
 	leaq	64-0(%rsi),%rsi
 	movq	%rax,544+0(%rsp)
@@ -1850,8 +1851,8 @@ ecp_nistz256_point_add:
 	call	__ecp_nistz256_sqr_montq
 
 	pcmpeqd	%xmm4,%xmm5
-	pshufd	$0xb1,%xmm3,%xmm4
-	por	%xmm3,%xmm4
+	pshufd	$0xb1,%xmm1,%xmm4
+	por	%xmm1,%xmm4
 	pshufd	$0,%xmm5,%xmm5
 	pshufd	$0x1e,%xmm4,%xmm3
 	por	%xmm3,%xmm4
@@ -2034,6 +2035,7 @@ ecp_nistz256_point_add:
 
 
 
+	xorq	%r11,%r11
 	addq	%r12,%r12
 	leaq	96(%rsp),%rsi
 	adcq	%r13,%r13
@@ -2041,7 +2043,7 @@ ecp_nistz256_point_add:
 	adcq	%r8,%r8
 	adcq	%r9,%r9
 	movq	%r13,%rbp
-	sbbq	%r11,%r11
+	adcq	$0,%r11
 
 	subq	$-1,%r12
 	movq	%r8,%rcx
@@ -2049,15 +2051,15 @@ ecp_nistz256_point_add:
 	sbbq	$0,%r8
 	movq	%r9,%r10
 	sbbq	%r15,%r9
-	testq	%r11,%r11
+	sbbq	$0,%r11
 
-	cmovzq	%rax,%r12
+	cmovcq	%rax,%r12
 	movq	0(%rsi),%rax
-	cmovzq	%rbp,%r13
+	cmovcq	%rbp,%r13
 	movq	8(%rsi),%rbp
-	cmovzq	%rcx,%r8
+	cmovcq	%rcx,%r8
 	movq	16(%rsi),%rcx
-	cmovzq	%r10,%r9
+	cmovcq	%r10,%r9
 	movq	24(%rsi),%r10
 
 	call	__ecp_nistz256_subq
@@ -2215,16 +2217,14 @@ ecp_nistz256_point_add_affine:
 	movq	64+24(%rsi),%r8
 	movdqa	%xmm0,320(%rsp)
 	movdqa	%xmm1,320+16(%rsp)
-	por	%xmm0,%xmm1
 	movdqa	%xmm2,352(%rsp)
 	movdqa	%xmm3,352+16(%rsp)
-	por	%xmm2,%xmm3
 	movdqa	%xmm4,384(%rsp)
 	movdqa	%xmm5,384+16(%rsp)
-	por	%xmm1,%xmm3
+	por	%xmm4,%xmm5
 
 	movdqu	0(%rbx),%xmm0
-	pshufd	$0xb1,%xmm3,%xmm5
+	pshufd	$0xb1,%xmm5,%xmm3
 	movdqu	16(%rbx),%xmm1
 	movdqu	32(%rbx),%xmm2
 	por	%xmm3,%xmm5
@@ -2342,6 +2342,7 @@ ecp_nistz256_point_add_affine:
 
 
 
+	xorq	%r11,%r11
 	addq	%r12,%r12
 	leaq	192(%rsp),%rsi
 	adcq	%r13,%r13
@@ -2349,7 +2350,7 @@ ecp_nistz256_point_add_affine:
 	adcq	%r8,%r8
 	adcq	%r9,%r9
 	movq	%r13,%rbp
-	sbbq	%r11,%r11
+	adcq	$0,%r11
 
 	subq	$-1,%r12
 	movq	%r8,%rcx
@@ -2357,15 +2358,15 @@ ecp_nistz256_point_add_affine:
 	sbbq	$0,%r8
 	movq	%r9,%r10
 	sbbq	%r15,%r9
-	testq	%r11,%r11
+	sbbq	$0,%r11
 
-	cmovzq	%rax,%r12
+	cmovcq	%rax,%r12
 	movq	0(%rsi),%rax
-	cmovzq	%rbp,%r13
+	cmovcq	%rbp,%r13
 	movq	8(%rsi),%rbp
-	cmovzq	%rcx,%r8
+	cmovcq	%rcx,%r8
 	movq	16(%rsi),%rcx
-	cmovzq	%r10,%r9
+	cmovcq	%r10,%r9
 	movq	24(%rsi),%r10
 
 	call	__ecp_nistz256_subq
@@ -2512,14 +2513,14 @@ __ecp_nistz256_add_tox:
 	sbbq	$0,%r8
 	movq	%r9,%r10
 	sbbq	%r15,%r9
+	sbbq	$0,%r11
 
-	btq	$0,%r11
-	cmovncq	%rax,%r12
-	cmovncq	%rbp,%r13
+	cmovcq	%rax,%r12
+	cmovcq	%rbp,%r13
 	movq	%r12,0(%rdi)
-	cmovncq	%rcx,%r8
+	cmovcq	%rcx,%r8
 	movq	%r13,8(%rdi)
-	cmovncq	%r10,%r9
+	cmovcq	%r10,%r9
 	movq	%r8,16(%rdi)
 	movq	%r9,24(%rdi)
 
@@ -2607,14 +2608,14 @@ __ecp_nistz256_mul_by_2x:
 	sbbq	$0,%r8
 	movq	%r9,%r10
 	sbbq	%r15,%r9
+	sbbq	$0,%r11
 
-	btq	$0,%r11
-	cmovncq	%rax,%r12
-	cmovncq	%rbp,%r13
+	cmovcq	%rax,%r12
+	cmovcq	%rbp,%r13
 	movq	%r12,0(%rdi)
-	cmovncq	%rcx,%r8
+	cmovcq	%rcx,%r8
 	movq	%r13,8(%rdi)
-	cmovncq	%r10,%r9
+	cmovcq	%r10,%r9
 	movq	%r8,16(%rdi)
 	movq	%r9,24(%rdi)
 
@@ -2844,16 +2845,14 @@ ecp_nistz256_point_addx:
 	movq	%rdx,%rsi
 	movdqa	%xmm0,384(%rsp)
 	movdqa	%xmm1,384+16(%rsp)
-	por	%xmm0,%xmm1
 	movdqa	%xmm2,416(%rsp)
 	movdqa	%xmm3,416+16(%rsp)
-	por	%xmm2,%xmm3
 	movdqa	%xmm4,448(%rsp)
 	movdqa	%xmm5,448+16(%rsp)
-	por	%xmm1,%xmm3
+	por	%xmm4,%xmm5
 
 	movdqu	0(%rsi),%xmm0
-	pshufd	$0xb1,%xmm3,%xmm5
+	pshufd	$0xb1,%xmm5,%xmm3
 	movdqu	16(%rsi),%xmm1
 	movdqu	32(%rsi),%xmm2
 	por	%xmm3,%xmm5
@@ -2865,14 +2864,14 @@ ecp_nistz256_point_addx:
 	movdqa	%xmm0,480(%rsp)
 	pshufd	$0x1e,%xmm5,%xmm4
 	movdqa	%xmm1,480+16(%rsp)
-	por	%xmm0,%xmm1
-.byte	102,72,15,110,199
+	movdqu	64(%rsi),%xmm0
+	movdqu	80(%rsi),%xmm1
 	movdqa	%xmm2,512(%rsp)
 	movdqa	%xmm3,512+16(%rsp)
-	por	%xmm2,%xmm3
 	por	%xmm4,%xmm5
 	pxor	%xmm4,%xmm4
-	por	%xmm1,%xmm3
+	por	%xmm0,%xmm1
+.byte	102,72,15,110,199
 
 	leaq	64-128(%rsi),%rsi
 	movq	%rdx,544+0(%rsp)
@@ -2883,8 +2882,8 @@ ecp_nistz256_point_addx:
 	call	__ecp_nistz256_sqr_montx
 
 	pcmpeqd	%xmm4,%xmm5
-	pshufd	$0xb1,%xmm3,%xmm4
-	por	%xmm3,%xmm4
+	pshufd	$0xb1,%xmm1,%xmm4
+	por	%xmm1,%xmm4
 	pshufd	$0,%xmm5,%xmm5
 	pshufd	$0x1e,%xmm4,%xmm3
 	por	%xmm3,%xmm4
@@ -3067,6 +3066,7 @@ ecp_nistz256_point_addx:
 
 
 
+	xorq	%r11,%r11
 	addq	%r12,%r12
 	leaq	96(%rsp),%rsi
 	adcq	%r13,%r13
@@ -3074,7 +3074,7 @@ ecp_nistz256_point_addx:
 	adcq	%r8,%r8
 	adcq	%r9,%r9
 	movq	%r13,%rbp
-	sbbq	%r11,%r11
+	adcq	$0,%r11
 
 	subq	$-1,%r12
 	movq	%r8,%rcx
@@ -3082,15 +3082,15 @@ ecp_nistz256_point_addx:
 	sbbq	$0,%r8
 	movq	%r9,%r10
 	sbbq	%r15,%r9
-	testq	%r11,%r11
+	sbbq	$0,%r11
 
-	cmovzq	%rax,%r12
+	cmovcq	%rax,%r12
 	movq	0(%rsi),%rax
-	cmovzq	%rbp,%r13
+	cmovcq	%rbp,%r13
 	movq	8(%rsi),%rbp
-	cmovzq	%rcx,%r8
+	cmovcq	%rcx,%r8
 	movq	16(%rsi),%rcx
-	cmovzq	%r10,%r9
+	cmovcq	%r10,%r9
 	movq	24(%rsi),%r10
 
 	call	__ecp_nistz256_subx
@@ -3244,16 +3244,14 @@ ecp_nistz256_point_add_affinex:
 	movq	64+24(%rsi),%r8
 	movdqa	%xmm0,320(%rsp)
 	movdqa	%xmm1,320+16(%rsp)
-	por	%xmm0,%xmm1
 	movdqa	%xmm2,352(%rsp)
 	movdqa	%xmm3,352+16(%rsp)
-	por	%xmm2,%xmm3
 	movdqa	%xmm4,384(%rsp)
 	movdqa	%xmm5,384+16(%rsp)
-	por	%xmm1,%xmm3
+	por	%xmm4,%xmm5
 
 	movdqu	0(%rbx),%xmm0
-	pshufd	$0xb1,%xmm3,%xmm5
+	pshufd	$0xb1,%xmm5,%xmm3
 	movdqu	16(%rbx),%xmm1
 	movdqu	32(%rbx),%xmm2
 	por	%xmm3,%xmm5
@@ -3371,6 +3369,7 @@ ecp_nistz256_point_add_affinex:
 
 
 
+	xorq	%r11,%r11
 	addq	%r12,%r12
 	leaq	192(%rsp),%rsi
 	adcq	%r13,%r13
@@ -3378,7 +3377,7 @@ ecp_nistz256_point_add_affinex:
 	adcq	%r8,%r8
 	adcq	%r9,%r9
 	movq	%r13,%rbp
-	sbbq	%r11,%r11
+	adcq	$0,%r11
 
 	subq	$-1,%r12
 	movq	%r8,%rcx
@@ -3386,15 +3385,15 @@ ecp_nistz256_point_add_affinex:
 	sbbq	$0,%r8
 	movq	%r9,%r10
 	sbbq	%r15,%r9
-	testq	%r11,%r11
+	sbbq	$0,%r11
 
-	cmovzq	%rax,%r12
+	cmovcq	%rax,%r12
 	movq	0(%rsi),%rax
-	cmovzq	%rbp,%r13
+	cmovcq	%rbp,%r13
 	movq	8(%rsi),%rbp
-	cmovzq	%rcx,%r8
+	cmovcq	%rcx,%r8
 	movq	16(%rsi),%rcx
-	cmovzq	%r10,%r9
+	cmovcq	%r10,%r9
 	movq	24(%rsi),%r10
 
 	call	__ecp_nistz256_subx
diff --git a/secure/lib/libcrypto/amd64/sha1-x86_64.S b/secure/lib/libcrypto/amd64/sha1-x86_64.S
index cdb7fdf6943e..9912d76bc81e 100644
--- a/secure/lib/libcrypto/amd64/sha1-x86_64.S
+++ b/secure/lib/libcrypto/amd64/sha1-x86_64.S
@@ -1265,9 +1265,9 @@ _shaext_shortcut:
 .align	16
 .Loop_shaext:
 	decq	%rdx
-	leaq	64(%rsi),%rax
+	leaq	64(%rsi),%r8
 	paddd	%xmm4,%xmm1
-	cmovneq	%rax,%rsi
+	cmovneq	%r8,%rsi
 	movdqa	%xmm0,%xmm8
 .byte	15,56,201,229
 	movdqa	%xmm0,%xmm2
diff --git a/secure/lib/libcrypto/amd64/x86_64-mont.S b/secure/lib/libcrypto/amd64/x86_64-mont.S
index adbc9624be82..6b6f97b2d209 100644
--- a/secure/lib/libcrypto/amd64/x86_64-mont.S
+++ b/secure/lib/libcrypto/amd64/x86_64-mont.S
@@ -8,6 +8,8 @@
 .type	bn_mul_mont,@function
 .align	16
 bn_mul_mont:
+	movl	%r9d,%r9d
+	movq	%rsp,%rax
 	testl	$3,%r9d
 	jnz	.Lmul_enter
 	cmpl	$8,%r9d
@@ -28,29 +30,36 @@ bn_mul_mont:
 	pushq	%r14
 	pushq	%r15
 
-	movl	%r9d,%r9d
-	leaq	2(%r9),%r10
+	negq	%r9
 	movq	%rsp,%r11
-	negq	%r10
-	leaq	(%rsp,%r10,8),%rsp
-	andq	$-1024,%rsp
+	leaq	-16(%rsp,%r9,8),%r10
+	negq	%r9
+	andq	$-1024,%r10
 
-	movq	%r11,8(%rsp,%r9,8)
-.Lmul_body:
 
 
 
 
 
 
-	subq	%rsp,%r11
+	subq	%r10,%r11
 	andq	$-4096,%r11
+	leaq	(%r10,%r11,1),%rsp
+	movq	(%rsp),%r11
+	cmpq	%r10,%rsp
+	ja	.Lmul_page_walk
+	jmp	.Lmul_page_walk_done
+
+.align	16
 .Lmul_page_walk:
-	movq	(%rsp,%r11,1),%r10
-	subq	$4096,%r11
-.byte	0x66,0x2e
-	jnc	.Lmul_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r11
+	cmpq	%r10,%rsp
+	ja	.Lmul_page_walk
+.Lmul_page_walk_done:
 
+	movq	%rax,8(%rsp,%r9,8)
+.Lmul_body:
 	movq	%rdx,%r12
 	movq	(%r8),%r8
 	movq	(%r12),%rbx
@@ -218,19 +227,21 @@ bn_mul_mont:
 
 	movq	8(%rsp,%r9,8),%rsi
 	movq	$1,%rax
-	movq	(%rsi),%r15
-	movq	8(%rsi),%r14
-	movq	16(%rsi),%r13
-	movq	24(%rsi),%r12
-	movq	32(%rsi),%rbp
-	movq	40(%rsi),%rbx
-	leaq	48(%rsi),%rsp
+	movq	-48(%rsi),%r15
+	movq	-40(%rsi),%r14
+	movq	-32(%rsi),%r13
+	movq	-24(%rsi),%r12
+	movq	-16(%rsi),%rbp
+	movq	-8(%rsi),%rbx
+	leaq	(%rsi),%rsp
 .Lmul_epilogue:
 	.byte	0xf3,0xc3
 .size	bn_mul_mont,.-bn_mul_mont
 .type	bn_mul4x_mont,@function
 .align	16
 bn_mul4x_mont:
+	movl	%r9d,%r9d
+	movq	%rsp,%rax
 .Lmul4x_enter:
 	andl	$0x80100,%r11d
 	cmpl	$0x80100,%r11d
@@ -242,23 +253,29 @@ bn_mul4x_mont:
 	pushq	%r14
 	pushq	%r15
 
-	movl	%r9d,%r9d
-	leaq	4(%r9),%r10
+	negq	%r9
 	movq	%rsp,%r11
-	negq	%r10
-	leaq	(%rsp,%r10,8),%rsp
-	andq	$-1024,%rsp
+	leaq	-32(%rsp,%r9,8),%r10
+	negq	%r9
+	andq	$-1024,%r10
 
-	movq	%r11,8(%rsp,%r9,8)
-.Lmul4x_body:
-	subq	%rsp,%r11
+	subq	%r10,%r11
 	andq	$-4096,%r11
+	leaq	(%r10,%r11,1),%rsp
+	movq	(%rsp),%r11
+	cmpq	%r10,%rsp
+	ja	.Lmul4x_page_walk
+	jmp	.Lmul4x_page_walk_done
+
 .Lmul4x_page_walk:
-	movq	(%rsp,%r11,1),%r10
-	subq	$4096,%r11
-.byte	0x2e
-	jnc	.Lmul4x_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r11
+	cmpq	%r10,%rsp
+	ja	.Lmul4x_page_walk
+.Lmul4x_page_walk_done:
 
+	movq	%rax,8(%rsp,%r9,8)
+.Lmul4x_body:
 	movq	%rdi,16(%rsp,%r9,8)
 	movq	%rdx,%r12
 	movq	(%r8),%r8
@@ -627,13 +644,13 @@ bn_mul4x_mont:
 	movdqu	%xmm2,16(%rdi,%r14,1)
 	movq	8(%rsp,%r9,8),%rsi
 	movq	$1,%rax
-	movq	(%rsi),%r15
-	movq	8(%rsi),%r14
-	movq	16(%rsi),%r13
-	movq	24(%rsi),%r12
-	movq	32(%rsi),%rbp
-	movq	40(%rsi),%rbx
-	leaq	48(%rsi),%rsp
+	movq	-48(%rsi),%r15
+	movq	-40(%rsi),%r14
+	movq	-32(%rsi),%r13
+	movq	-24(%rsi),%r12
+	movq	-16(%rsi),%rbp
+	movq	-8(%rsi),%rbx
+	leaq	(%rsi),%rsp
 .Lmul4x_epilogue:
 	.byte	0xf3,0xc3
 .size	bn_mul4x_mont,.-bn_mul4x_mont
@@ -643,14 +660,15 @@ bn_mul4x_mont:
 .type	bn_sqr8x_mont,@function
 .align	32
 bn_sqr8x_mont:
-.Lsqr8x_enter:
 	movq	%rsp,%rax
+.Lsqr8x_enter:
 	pushq	%rbx
 	pushq	%rbp
 	pushq	%r12
 	pushq	%r13
 	pushq	%r14
 	pushq	%r15
+.Lsqr8x_prologue:
 
 	movl	%r9d,%r10d
 	shll	$3,%r9d
@@ -663,33 +681,42 @@ bn_sqr8x_mont:
 
 
 	leaq	-64(%rsp,%r9,2),%r11
+	movq	%rsp,%rbp
 	movq	(%r8),%r8
 	subq	%rsi,%r11
 	andq	$4095,%r11
 	cmpq	%r11,%r10
 	jb	.Lsqr8x_sp_alt
-	subq	%r11,%rsp
-	leaq	-64(%rsp,%r9,2),%rsp
+	subq	%r11,%rbp
+	leaq	-64(%rbp,%r9,2),%rbp
 	jmp	.Lsqr8x_sp_done
 
 .align	32
 .Lsqr8x_sp_alt:
 	leaq	4096-64(,%r9,2),%r10
-	leaq	-64(%rsp,%r9,2),%rsp
+	leaq	-64(%rbp,%r9,2),%rbp
 	subq	%r10,%r11
 	movq	$0,%r10
 	cmovcq	%r10,%r11
-	subq	%r11,%rsp
+	subq	%r11,%rbp
 .Lsqr8x_sp_done:
-	andq	$-64,%rsp
-	movq	%rax,%r11
-	subq	%rsp,%r11
+	andq	$-64,%rbp
+	movq	%rsp,%r11
+	subq	%rbp,%r11
 	andq	$-4096,%r11
+	leaq	(%r11,%rbp,1),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lsqr8x_page_walk
+	jmp	.Lsqr8x_page_walk_done
+
+.align	16
 .Lsqr8x_page_walk:
-	movq	(%rsp,%r11,1),%r10
-	subq	$4096,%r11
-.byte	0x2e
-	jnc	.Lsqr8x_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lsqr8x_page_walk
+.Lsqr8x_page_walk_done:
 
 	movq	%r9,%r10
 	negq	%r9
@@ -802,30 +829,38 @@ bn_sqr8x_mont:
 .type	bn_mulx4x_mont,@function
 .align	32
 bn_mulx4x_mont:
-.Lmulx4x_enter:
 	movq	%rsp,%rax
+.Lmulx4x_enter:
 	pushq	%rbx
 	pushq	%rbp
 	pushq	%r12
 	pushq	%r13
 	pushq	%r14
 	pushq	%r15
+.Lmulx4x_prologue:
 
 	shll	$3,%r9d
-.byte	0x67
 	xorq	%r10,%r10
 	subq	%r9,%r10
 	movq	(%r8),%r8
-	leaq	-72(%rsp,%r10,1),%rsp
-	andq	$-128,%rsp
-	movq	%rax,%r11
-	subq	%rsp,%r11
+	leaq	-72(%rsp,%r10,1),%rbp
+	andq	$-128,%rbp
+	movq	%rsp,%r11
+	subq	%rbp,%r11
 	andq	$-4096,%r11
+	leaq	(%r11,%rbp,1),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lmulx4x_page_walk
+	jmp	.Lmulx4x_page_walk_done
+
+.align	16
 .Lmulx4x_page_walk:
-	movq	(%rsp,%r11,1),%r10
-	subq	$4096,%r11
-.byte	0x66,0x2e
-	jnc	.Lmulx4x_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lmulx4x_page_walk
+.Lmulx4x_page_walk_done:
 
 	leaq	(%rdx,%r9,1),%r10
 
diff --git a/secure/lib/libcrypto/amd64/x86_64-mont5.S b/secure/lib/libcrypto/amd64/x86_64-mont5.S
index 7e8d43f66c10..bbfba026a119 100644
--- a/secure/lib/libcrypto/amd64/x86_64-mont5.S
+++ b/secure/lib/libcrypto/amd64/x86_64-mont5.S
@@ -8,6 +8,8 @@
 .type	bn_mul_mont_gather5,@function
 .align	64
 bn_mul_mont_gather5:
+	movl	%r9d,%r9d
+	movq	%rsp,%rax
 	testl	$7,%r9d
 	jnz	.Lmul_enter
 	movl	OPENSSL_ia32cap_P+8(%rip),%r11d
@@ -15,10 +17,7 @@ bn_mul_mont_gather5:
 
 .align	16
 .Lmul_enter:
-	movl	%r9d,%r9d
-	movq	%rsp,%rax
 	movd	8(%rsp),%xmm5
-	leaq	.Linc(%rip),%r10
 	pushq	%rbx
 	pushq	%rbp
 	pushq	%r12
@@ -26,26 +25,36 @@ bn_mul_mont_gather5:
 	pushq	%r14
 	pushq	%r15
 
-	leaq	2(%r9),%r11
-	negq	%r11
-	leaq	-264(%rsp,%r11,8),%rsp
-	andq	$-1024,%rsp
+	negq	%r9
+	movq	%rsp,%r11
+	leaq	-280(%rsp,%r9,8),%r10
+	negq	%r9
+	andq	$-1024,%r10
 
-	movq	%rax,8(%rsp,%r9,8)
-.Lmul_body:
 
 
 
 
 
 
-	subq	%rsp,%rax
-	andq	$-4096,%rax
+	subq	%r10,%r11
+	andq	$-4096,%r11
+	leaq	(%r10,%r11,1),%rsp
+	movq	(%rsp),%r11
+	cmpq	%r10,%rsp
+	ja	.Lmul_page_walk
+	jmp	.Lmul_page_walk_done
+
 .Lmul_page_walk:
-	movq	(%rsp,%rax,1),%r11
-	subq	$4096,%rax
-.byte	0x2e
-	jnc	.Lmul_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r11
+	cmpq	%r10,%rsp
+	ja	.Lmul_page_walk
+.Lmul_page_walk_done:
+
+	leaq	.Linc(%rip),%r10
+	movq	%rax,8(%rsp,%r9,8)
+.Lmul_body:
 
 	leaq	128(%rdx),%r12
 	movdqa	0(%r10),%xmm0
@@ -416,18 +425,19 @@ bn_mul_mont_gather5:
 .type	bn_mul4x_mont_gather5,@function
 .align	32
 bn_mul4x_mont_gather5:
+.byte	0x67
+	movq	%rsp,%rax
 .Lmul4x_enter:
 	andl	$0x80108,%r11d
 	cmpl	$0x80108,%r11d
 	je	.Lmulx4x_enter
-.byte	0x67
-	movq	%rsp,%rax
 	pushq	%rbx
 	pushq	%rbp
 	pushq	%r12
 	pushq	%r13
 	pushq	%r14
 	pushq	%r15
+.Lmul4x_prologue:
 
 .byte	0x67
 	shll	$3,%r9d
@@ -444,32 +454,40 @@ bn_mul4x_mont_gather5:
 
 
 	leaq	-320(%rsp,%r9,2),%r11
+	movq	%rsp,%rbp
 	subq	%rdi,%r11
 	andq	$4095,%r11
 	cmpq	%r11,%r10
 	jb	.Lmul4xsp_alt
-	subq	%r11,%rsp
-	leaq	-320(%rsp,%r9,2),%rsp
+	subq	%r11,%rbp
+	leaq	-320(%rbp,%r9,2),%rbp
 	jmp	.Lmul4xsp_done
 
 .align	32
 .Lmul4xsp_alt:
 	leaq	4096-320(,%r9,2),%r10
-	leaq	-320(%rsp,%r9,2),%rsp
+	leaq	-320(%rbp,%r9,2),%rbp
 	subq	%r10,%r11
 	movq	$0,%r10
 	cmovcq	%r10,%r11
-	subq	%r11,%rsp
+	subq	%r11,%rbp
 .Lmul4xsp_done:
-	andq	$-64,%rsp
-	movq	%rax,%r11
-	subq	%rsp,%r11
+	andq	$-64,%rbp
+	movq	%rsp,%r11
+	subq	%rbp,%r11
 	andq	$-4096,%r11
+	leaq	(%r11,%rbp,1),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lmul4x_page_walk
+	jmp	.Lmul4x_page_walk_done
+
 .Lmul4x_page_walk:
-	movq	(%rsp,%r11,1),%r10
-	subq	$4096,%r11
-.byte	0x2e
-	jnc	.Lmul4x_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lmul4x_page_walk
+.Lmul4x_page_walk_done:
 
 	negq	%r9
 
@@ -1021,17 +1039,18 @@ mul4x_internal:
 .type	bn_power5,@function
 .align	32
 bn_power5:
+	movq	%rsp,%rax
 	movl	OPENSSL_ia32cap_P+8(%rip),%r11d
 	andl	$0x80108,%r11d
 	cmpl	$0x80108,%r11d
 	je	.Lpowerx5_enter
-	movq	%rsp,%rax
 	pushq	%rbx
 	pushq	%rbp
 	pushq	%r12
 	pushq	%r13
 	pushq	%r14
 	pushq	%r15
+.Lpower5_prologue:
 
 	shll	$3,%r9d
 	leal	(%r9,%r9,2),%r10d
@@ -1046,32 +1065,40 @@ bn_power5:
 
 
 	leaq	-320(%rsp,%r9,2),%r11
+	movq	%rsp,%rbp
 	subq	%rdi,%r11
 	andq	$4095,%r11
 	cmpq	%r11,%r10
 	jb	.Lpwr_sp_alt
-	subq	%r11,%rsp
-	leaq	-320(%rsp,%r9,2),%rsp
+	subq	%r11,%rbp
+	leaq	-320(%rbp,%r9,2),%rbp
 	jmp	.Lpwr_sp_done
 
 .align	32
 .Lpwr_sp_alt:
 	leaq	4096-320(,%r9,2),%r10
-	leaq	-320(%rsp,%r9,2),%rsp
+	leaq	-320(%rbp,%r9,2),%rbp
 	subq	%r10,%r11
 	movq	$0,%r10
 	cmovcq	%r10,%r11
-	subq	%r11,%rsp
+	subq	%r11,%rbp
 .Lpwr_sp_done:
-	andq	$-64,%rsp
-	movq	%rax,%r11
-	subq	%rsp,%r11
+	andq	$-64,%rbp
+	movq	%rsp,%r11
+	subq	%rbp,%r11
 	andq	$-4096,%r11
+	leaq	(%r11,%rbp,1),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lpwr_page_walk
+	jmp	.Lpwr_page_walk_done
+
 .Lpwr_page_walk:
-	movq	(%rsp,%r11,1),%r10
-	subq	$4096,%r11
-.byte	0x2e
-	jnc	.Lpwr_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lpwr_page_walk
+.Lpwr_page_walk_done:
 
 	movq	%r9,%r10
 	negq	%r9
@@ -1982,6 +2009,7 @@ bn_from_mont8x:
 	pushq	%r13
 	pushq	%r14
 	pushq	%r15
+.Lfrom_prologue:
 
 	shll	$3,%r9d
 	leaq	(%r9,%r9,2),%r10
@@ -1996,32 +2024,40 @@ bn_from_mont8x:
 
 
 	leaq	-320(%rsp,%r9,2),%r11
+	movq	%rsp,%rbp
 	subq	%rdi,%r11
 	andq	$4095,%r11
 	cmpq	%r11,%r10
 	jb	.Lfrom_sp_alt
-	subq	%r11,%rsp
-	leaq	-320(%rsp,%r9,2),%rsp
+	subq	%r11,%rbp
+	leaq	-320(%rbp,%r9,2),%rbp
 	jmp	.Lfrom_sp_done
 
 .align	32
 .Lfrom_sp_alt:
 	leaq	4096-320(,%r9,2),%r10
-	leaq	-320(%rsp,%r9,2),%rsp
+	leaq	-320(%rbp,%r9,2),%rbp
 	subq	%r10,%r11
 	movq	$0,%r10
 	cmovcq	%r10,%r11
-	subq	%r11,%rsp
+	subq	%r11,%rbp
 .Lfrom_sp_done:
-	andq	$-64,%rsp
-	movq	%rax,%r11
-	subq	%rsp,%r11
+	andq	$-64,%rbp
+	movq	%rsp,%r11
+	subq	%rbp,%r11
 	andq	$-4096,%r11
+	leaq	(%r11,%rbp,1),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lfrom_page_walk
+	jmp	.Lfrom_page_walk_done
+
 .Lfrom_page_walk:
-	movq	(%rsp,%r11,1),%r10
-	subq	$4096,%r11
-.byte	0x2e
-	jnc	.Lfrom_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lfrom_page_walk
+.Lfrom_page_walk_done:
 
 	movq	%r9,%r10
 	negq	%r9
@@ -2115,14 +2151,15 @@ bn_from_mont8x:
 .type	bn_mulx4x_mont_gather5,@function
 .align	32
 bn_mulx4x_mont_gather5:
-.Lmulx4x_enter:
 	movq	%rsp,%rax
+.Lmulx4x_enter:
 	pushq	%rbx
 	pushq	%rbp
 	pushq	%r12
 	pushq	%r13
 	pushq	%r14
 	pushq	%r15
+.Lmulx4x_prologue:
 
 	shll	$3,%r9d
 	leaq	(%r9,%r9,2),%r10
@@ -2139,31 +2176,39 @@ bn_mulx4x_mont_gather5:
 
 
 	leaq	-320(%rsp,%r9,2),%r11
+	movq	%rsp,%rbp
 	subq	%rdi,%r11
 	andq	$4095,%r11
 	cmpq	%r11,%r10
 	jb	.Lmulx4xsp_alt
-	subq	%r11,%rsp
-	leaq	-320(%rsp,%r9,2),%rsp
+	subq	%r11,%rbp
+	leaq	-320(%rbp,%r9,2),%rbp
 	jmp	.Lmulx4xsp_done
 
 .Lmulx4xsp_alt:
 	leaq	4096-320(,%r9,2),%r10
-	leaq	-320(%rsp,%r9,2),%rsp
+	leaq	-320(%rbp,%r9,2),%rbp
 	subq	%r10,%r11
 	movq	$0,%r10
 	cmovcq	%r10,%r11
-	subq	%r11,%rsp
+	subq	%r11,%rbp
 .Lmulx4xsp_done:
-	andq	$-64,%rsp
-	movq	%rax,%r11
-	subq	%rsp,%r11
+	andq	$-64,%rbp
+	movq	%rsp,%r11
+	subq	%rbp,%r11
 	andq	$-4096,%r11
+	leaq	(%r11,%rbp,1),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lmulx4x_page_walk
+	jmp	.Lmulx4x_page_walk_done
+
 .Lmulx4x_page_walk:
-	movq	(%rsp,%r11,1),%r10
-	subq	$4096,%r11
-.byte	0x2e
-	jnc	.Lmulx4x_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lmulx4x_page_walk
+.Lmulx4x_page_walk_done:
 
 
 
@@ -2621,14 +2666,15 @@ mulx4x_internal:
 .type	bn_powerx5,@function
 .align	32
 bn_powerx5:
-.Lpowerx5_enter:
 	movq	%rsp,%rax
+.Lpowerx5_enter:
 	pushq	%rbx
 	pushq	%rbp
 	pushq	%r12
 	pushq	%r13
 	pushq	%r14
 	pushq	%r15
+.Lpowerx5_prologue:
 
 	shll	$3,%r9d
 	leaq	(%r9,%r9,2),%r10
@@ -2643,32 +2689,40 @@ bn_powerx5:
 
 
 	leaq	-320(%rsp,%r9,2),%r11
+	movq	%rsp,%rbp
 	subq	%rdi,%r11
 	andq	$4095,%r11
 	cmpq	%r11,%r10
 	jb	.Lpwrx_sp_alt
-	subq	%r11,%rsp
-	leaq	-320(%rsp,%r9,2),%rsp
+	subq	%r11,%rbp
+	leaq	-320(%rbp,%r9,2),%rbp
 	jmp	.Lpwrx_sp_done
 
 .align	32
 .Lpwrx_sp_alt:
 	leaq	4096-320(,%r9,2),%r10
-	leaq	-320(%rsp,%r9,2),%rsp
+	leaq	-320(%rbp,%r9,2),%rbp
 	subq	%r10,%r11
 	movq	$0,%r10
 	cmovcq	%r10,%r11
-	subq	%r11,%rsp
+	subq	%r11,%rbp
 .Lpwrx_sp_done:
-	andq	$-64,%rsp
-	movq	%rax,%r11
-	subq	%rsp,%r11
+	andq	$-64,%rbp
+	movq	%rsp,%r11
+	subq	%rbp,%r11
 	andq	$-4096,%r11
+	leaq	(%r11,%rbp,1),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lpwrx_page_walk
+	jmp	.Lpwrx_page_walk_done
+
 .Lpwrx_page_walk:
-	movq	(%rsp,%r11,1),%r10
-	subq	$4096,%r11
-.byte	0x2e
-	jnc	.Lpwrx_page_walk
+	leaq	-4096(%rsp),%rsp
+	movq	(%rsp),%r10
+	cmpq	%rbp,%rsp
+	ja	.Lpwrx_page_walk
+.Lpwrx_page_walk_done:
 
 	movq	%r9,%r10
 	negq	%r9
diff --git a/secure/lib/libcrypto/arm/bsaes-armv7.S b/secure/lib/libcrypto/arm/bsaes-armv7.S
index ae9fa05c5b00..c766d9db0e5f 100644
--- a/secure/lib/libcrypto/arm/bsaes-armv7.S
+++ b/secure/lib/libcrypto/arm/bsaes-armv7.S
@@ -1818,8 +1818,6 @@ bsaes_xts_encrypt:
 	b		.Lxts_enc_done
 .align	4
 .Lxts_enc_6:
-	vst1.64		{q14}, [r0,:128]		@ next round tweak
-
 	veor		q4, q4, q12
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1855,8 +1853,6 @@ bsaes_xts_encrypt:
 
 .align	5
 .Lxts_enc_5:
-	vst1.64		{q13}, [r0,:128]		@ next round tweak
-
 	veor		q3, q3, q11
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1885,8 +1881,6 @@ bsaes_xts_encrypt:
 	b		.Lxts_enc_done
 .align	4
 .Lxts_enc_4:
-	vst1.64		{q12}, [r0,:128]		@ next round tweak
-
 	veor		q2, q2, q10
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1912,8 +1906,6 @@ bsaes_xts_encrypt:
 	b		.Lxts_enc_done
 .align	4
 .Lxts_enc_3:
-	vst1.64		{q11}, [r0,:128]		@ next round tweak
-
 	veor		q1, q1, q9
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1938,8 +1930,6 @@ bsaes_xts_encrypt:
 	b		.Lxts_enc_done
 .align	4
 .Lxts_enc_2:
-	vst1.64		{q10}, [r0,:128]		@ next round tweak
-
 	veor		q0, q0, q8
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -1962,7 +1952,7 @@ bsaes_xts_encrypt:
 .align	4
 .Lxts_enc_1:
 	mov		r0, sp
-	veor		q0, q8
+	veor		q0, q0, q8
 	mov		r1, sp
 	vst1.8		{q0}, [sp,:128]
 	mov		r2, r10
@@ -2348,8 +2338,6 @@ bsaes_xts_decrypt:
 	b		.Lxts_dec_done
 .align	4
 .Lxts_dec_5:
-	vst1.64		{q13}, [r0,:128]		@ next round tweak
-
 	veor		q3, q3, q11
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -2378,8 +2366,6 @@ bsaes_xts_decrypt:
 	b		.Lxts_dec_done
 .align	4
 .Lxts_dec_4:
-	vst1.64		{q12}, [r0,:128]		@ next round tweak
-
 	veor		q2, q2, q10
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -2405,8 +2391,6 @@ bsaes_xts_decrypt:
 	b		.Lxts_dec_done
 .align	4
 .Lxts_dec_3:
-	vst1.64		{q11}, [r0,:128]		@ next round tweak
-
 	veor		q1, q1, q9
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -2431,8 +2415,6 @@ bsaes_xts_decrypt:
 	b		.Lxts_dec_done
 .align	4
 .Lxts_dec_2:
-	vst1.64		{q10}, [r0,:128]		@ next round tweak
-
 	veor		q0, q0, q8
 #ifndef	BSAES_ASM_EXTENDED_KEY
 	add		r4, sp, #0x90			@ pass key schedule
@@ -2455,12 +2437,12 @@ bsaes_xts_decrypt:
 .align	4
 .Lxts_dec_1:
 	mov		r0, sp
-	veor		q0, q8
+	veor		q0, q0, q8
 	mov		r1, sp
 	vst1.8		{q0}, [sp,:128]
+	mov		r5, r2			@ preserve magic
 	mov		r2, r10
 	mov		r4, r3				@ preserve fp
-	mov		r5, r2			@ preserve magic
 
 	bl		AES_decrypt
 
diff --git a/secure/lib/libcrypto/i386/x86-mont.S b/secure/lib/libcrypto/i386/x86-mont.S
index 0988d8fb25da..11b2eb4de24c 100644
--- a/secure/lib/libcrypto/i386/x86-mont.S
+++ b/secure/lib/libcrypto/i386/x86-mont.S
@@ -18,47 +18,54 @@ bn_mul_mont:
 	jl	.L000just_leave
 	leal	20(%esp),%esi
 	leal	24(%esp),%edx
-	movl	%esp,%ebp
 	addl	$2,%edi
 	negl	%edi
-	leal	-32(%esp,%edi,4),%esp
+	leal	-32(%esp,%edi,4),%ebp
 	negl	%edi
-	movl	%esp,%eax
+	movl	%ebp,%eax
 	subl	%edx,%eax
 	andl	$2047,%eax
-	subl	%eax,%esp
-	xorl	%esp,%edx
+	subl	%eax,%ebp
+	xorl	%ebp,%edx
 	andl	$2048,%edx
 	xorl	$2048,%edx
-	subl	%edx,%esp
-	andl	$-64,%esp
-	movl	%ebp,%eax
-	subl	%esp,%eax
+	subl	%edx,%ebp
+	andl	$-64,%ebp
+	movl	%esp,%eax
+	subl	%ebp,%eax
 	andl	$-4096,%eax
+	movl	%esp,%edx
+	leal	(%ebp,%eax,1),%esp
+	movl	(%esp),%eax
+	cmpl	%ebp,%esp
+	ja	.L001page_walk
+	jmp	.L002page_walk_done
+.align	16
 .L001page_walk:
-	movl	(%esp,%eax,1),%edx
-	subl	$4096,%eax
-.byte	46
-	jnc	.L001page_walk
+	leal	-4096(%esp),%esp
+	movl	(%esp),%eax
+	cmpl	%ebp,%esp
+	ja	.L001page_walk
+.L002page_walk_done:
 	movl	(%esi),%eax
 	movl	4(%esi),%ebx
 	movl	8(%esi),%ecx
-	movl	12(%esi),%edx
+	movl	12(%esi),%ebp
 	movl	16(%esi),%esi
 	movl	(%esi),%esi
 	movl	%eax,4(%esp)
 	movl	%ebx,8(%esp)
 	movl	%ecx,12(%esp)
-	movl	%edx,16(%esp)
+	movl	%ebp,16(%esp)
 	movl	%esi,20(%esp)
 	leal	-3(%edi),%ebx
-	movl	%ebp,24(%esp)
-	call	.L002PIC_me_up
-.L002PIC_me_up:
+	movl	%edx,24(%esp)
+	call	.L003PIC_me_up
+.L003PIC_me_up:
 	popl	%eax
-	leal	OPENSSL_ia32cap_P-.L002PIC_me_up(%eax),%eax
+	leal	OPENSSL_ia32cap_P-.L003PIC_me_up(%eax),%eax
 	btl	$26,(%eax)
-	jnc	.L003non_sse2
+	jnc	.L004non_sse2
 	movl	$-1,%eax
 	movd	%eax,%mm7
 	movl	8(%esp),%esi
@@ -82,7 +89,7 @@ bn_mul_mont:
 	psrlq	$32,%mm3
 	incl	%ecx
 .align	16
-.L0041st:
+.L0051st:
 	pmuludq	%mm4,%mm0
 	pmuludq	%mm5,%mm1
 	paddq	%mm0,%mm2
@@ -97,7 +104,7 @@ bn_mul_mont:
 	psrlq	$32,%mm3
 	leal	1(%ecx),%ecx
 	cmpl	%ebx,%ecx
-	jl	.L0041st
+	jl	.L0051st
 	pmuludq	%mm4,%mm0
 	pmuludq	%mm5,%mm1
 	paddq	%mm0,%mm2
@@ -111,7 +118,7 @@ bn_mul_mont:
 	paddq	%mm2,%mm3
 	movq	%mm3,32(%esp,%ebx,4)
 	incl	%edx
-.L005outer:
+.L006outer:
 	xorl	%ecx,%ecx
 	movd	(%edi,%edx,4),%mm4
 	movd	(%esi),%mm5
@@ -133,7 +140,7 @@ bn_mul_mont:
 	paddq	%mm6,%mm2
 	incl	%ecx
 	decl	%ebx
-.L006inner:
+.L007inner:
 	pmuludq	%mm4,%mm0
 	pmuludq	%mm5,%mm1
 	paddq	%mm0,%mm2
@@ -150,7 +157,7 @@ bn_mul_mont:
 	paddq	%mm6,%mm2
 	decl	%ebx
 	leal	1(%ecx),%ecx
-	jnz	.L006inner
+	jnz	.L007inner
 	movl	%ecx,%ebx
 	pmuludq	%mm4,%mm0
 	pmuludq	%mm5,%mm1
@@ -168,11 +175,11 @@ bn_mul_mont:
 	movq	%mm3,32(%esp,%ebx,4)
 	leal	1(%edx),%edx
 	cmpl	%ebx,%edx
-	jle	.L005outer
+	jle	.L006outer
 	emms
-	jmp	.L007common_tail
+	jmp	.L008common_tail
 .align	16
-.L003non_sse2:
+.L004non_sse2:
 	movl	8(%esp),%esi
 	leal	1(%ebx),%ebp
 	movl	12(%esp),%edi
@@ -183,12 +190,12 @@ bn_mul_mont:
 	leal	4(%edi,%ebx,4),%eax
 	orl	%edx,%ebp
 	movl	(%edi),%edi
-	jz	.L008bn_sqr_mont
+	jz	.L009bn_sqr_mont
 	movl	%eax,28(%esp)
 	movl	(%esi),%eax
 	xorl	%edx,%edx
 .align	16
-.L009mull:
+.L010mull:
 	movl	%edx,%ebp
 	mull	%edi
 	addl	%eax,%ebp
@@ -197,7 +204,7 @@ bn_mul_mont:
 	movl	(%esi,%ecx,4),%eax
 	cmpl	%ebx,%ecx
 	movl	%ebp,28(%esp,%ecx,4)
-	jl	.L009mull
+	jl	.L010mull
 	movl	%edx,%ebp
 	mull	%edi
 	movl	20(%esp),%edi
@@ -215,9 +222,9 @@ bn_mul_mont:
 	movl	4(%esi),%eax
 	adcl	$0,%edx
 	incl	%ecx
-	jmp	.L0102ndmadd
+	jmp	.L0112ndmadd
 .align	16
-.L0111stmadd:
+.L0121stmadd:
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ecx,4),%ebp
@@ -228,7 +235,7 @@ bn_mul_mont:
 	adcl	$0,%edx
 	cmpl	%ebx,%ecx
 	movl	%ebp,28(%esp,%ecx,4)
-	jl	.L0111stmadd
+	jl	.L0121stmadd
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ebx,4),%eax
@@ -251,7 +258,7 @@ bn_mul_mont:
 	adcl	$0,%edx
 	movl	$1,%ecx
 .align	16
-.L0102ndmadd:
+.L0112ndmadd:
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ecx,4),%ebp
@@ -262,7 +269,7 @@ bn_mul_mont:
 	adcl	$0,%edx
 	cmpl	%ebx,%ecx
 	movl	%ebp,24(%esp,%ecx,4)
-	jl	.L0102ndmadd
+	jl	.L0112ndmadd
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ebx,4),%ebp
@@ -278,16 +285,16 @@ bn_mul_mont:
 	movl	%edx,32(%esp,%ebx,4)
 	cmpl	28(%esp),%ecx
 	movl	%eax,36(%esp,%ebx,4)
-	je	.L007common_tail
+	je	.L008common_tail
 	movl	(%ecx),%edi
 	movl	8(%esp),%esi
 	movl	%ecx,12(%esp)
 	xorl	%ecx,%ecx
 	xorl	%edx,%edx
 	movl	(%esi),%eax
-	jmp	.L0111stmadd
+	jmp	.L0121stmadd
 .align	16
-.L008bn_sqr_mont:
+.L009bn_sqr_mont:
 	movl	%ebx,(%esp)
 	movl	%ecx,12(%esp)
 	movl	%edi,%eax
@@ -298,7 +305,7 @@ bn_mul_mont:
 	andl	$1,%ebx
 	incl	%ecx
 .align	16
-.L012sqr:
+.L013sqr:
 	movl	(%esi,%ecx,4),%eax
 	movl	%edx,%ebp
 	mull	%edi
@@ -310,7 +317,7 @@ bn_mul_mont:
 	cmpl	(%esp),%ecx
 	movl	%eax,%ebx
 	movl	%ebp,28(%esp,%ecx,4)
-	jl	.L012sqr
+	jl	.L013sqr
 	movl	(%esi,%ecx,4),%eax
 	movl	%edx,%ebp
 	mull	%edi
@@ -334,7 +341,7 @@ bn_mul_mont:
 	movl	4(%esi),%eax
 	movl	$1,%ecx
 .align	16
-.L0133rdmadd:
+.L0143rdmadd:
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ecx,4),%ebp
@@ -353,7 +360,7 @@ bn_mul_mont:
 	adcl	$0,%edx
 	cmpl	%ebx,%ecx
 	movl	%ebp,24(%esp,%ecx,4)
-	jl	.L0133rdmadd
+	jl	.L0143rdmadd
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ebx,4),%ebp
@@ -369,7 +376,7 @@ bn_mul_mont:
 	movl	%edx,32(%esp,%ebx,4)
 	cmpl	%ebx,%ecx
 	movl	%eax,36(%esp,%ebx,4)
-	je	.L007common_tail
+	je	.L008common_tail
 	movl	4(%esi,%ecx,4),%edi
 	leal	1(%ecx),%ecx
 	movl	%edi,%eax
@@ -381,12 +388,12 @@ bn_mul_mont:
 	xorl	%ebp,%ebp
 	cmpl	%ebx,%ecx
 	leal	1(%ecx),%ecx
-	je	.L014sqrlast
+	je	.L015sqrlast
 	movl	%edx,%ebx
 	shrl	$1,%edx
 	andl	$1,%ebx
 .align	16
-.L015sqradd:
+.L016sqradd:
 	movl	(%esi,%ecx,4),%eax
 	movl	%edx,%ebp
 	mull	%edi
@@ -402,13 +409,13 @@ bn_mul_mont:
 	cmpl	(%esp),%ecx
 	movl	%ebp,28(%esp,%ecx,4)
 	movl	%eax,%ebx
-	jle	.L015sqradd
+	jle	.L016sqradd
 	movl	%edx,%ebp
 	addl	%edx,%edx
 	shrl	$31,%ebp
 	addl	%ebx,%edx
 	adcl	$0,%ebp
-.L014sqrlast:
+.L015sqrlast:
 	movl	20(%esp),%edi
 	movl	16(%esp),%esi
 	imull	32(%esp),%edi
@@ -423,9 +430,9 @@ bn_mul_mont:
 	adcl	$0,%edx
 	movl	$1,%ecx
 	movl	4(%esi),%eax
-	jmp	.L0133rdmadd
+	jmp	.L0143rdmadd
 .align	16
-.L007common_tail:
+.L008common_tail:
 	movl	16(%esp),%ebp
 	movl	4(%esp),%edi
 	leal	32(%esp),%esi
@@ -433,13 +440,13 @@ bn_mul_mont:
 	movl	%ebx,%ecx
 	xorl	%edx,%edx
 .align	16
-.L016sub:
+.L017sub:
 	sbbl	(%ebp,%edx,4),%eax
 	movl	%eax,(%edi,%edx,4)
 	decl	%ecx
 	movl	4(%esi,%edx,4),%eax
 	leal	1(%edx),%edx
-	jge	.L016sub
+	jge	.L017sub
 	sbbl	$0,%eax
 	andl	%eax,%esi
 	notl	%eax
@@ -447,12 +454,12 @@ bn_mul_mont:
 	andl	%eax,%ebp
 	orl	%ebp,%esi
 .align	16
-.L017copy:
+.L018copy:
 	movl	(%esi,%ebx,4),%eax
 	movl	%eax,(%edi,%ebx,4)
 	movl	%ecx,32(%esp,%ebx,4)
 	decl	%ebx
-	jge	.L017copy
+	jge	.L018copy
 	movl	24(%esp),%esp
 	movl	$1,%eax
 .L000just_leave:
@@ -486,44 +493,51 @@ bn_mul_mont:
 	jl	.L000just_leave
 	leal	20(%esp),%esi
 	leal	24(%esp),%edx
-	movl	%esp,%ebp
 	addl	$2,%edi
 	negl	%edi
-	leal	-32(%esp,%edi,4),%esp
+	leal	-32(%esp,%edi,4),%ebp
 	negl	%edi
-	movl	%esp,%eax
+	movl	%ebp,%eax
 	subl	%edx,%eax
 	andl	$2047,%eax
-	subl	%eax,%esp
-	xorl	%esp,%edx
+	subl	%eax,%ebp
+	xorl	%ebp,%edx
 	andl	$2048,%edx
 	xorl	$2048,%edx
-	subl	%edx,%esp
-	andl	$-64,%esp
-	movl	%ebp,%eax
-	subl	%esp,%eax
+	subl	%edx,%ebp
+	andl	$-64,%ebp
+	movl	%esp,%eax
+	subl	%ebp,%eax
 	andl	$-4096,%eax
+	movl	%esp,%edx
+	leal	(%ebp,%eax,1),%esp
+	movl	(%esp),%eax
+	cmpl	%ebp,%esp
+	ja	.L001page_walk
+	jmp	.L002page_walk_done
+.align	16
 .L001page_walk:
-	movl	(%esp,%eax,1),%edx
-	subl	$4096,%eax
-.byte	46
-	jnc	.L001page_walk
+	leal	-4096(%esp),%esp
+	movl	(%esp),%eax
+	cmpl	%ebp,%esp
+	ja	.L001page_walk
+.L002page_walk_done:
 	movl	(%esi),%eax
 	movl	4(%esi),%ebx
 	movl	8(%esi),%ecx
-	movl	12(%esi),%edx
+	movl	12(%esi),%ebp
 	movl	16(%esi),%esi
 	movl	(%esi),%esi
 	movl	%eax,4(%esp)
 	movl	%ebx,8(%esp)
 	movl	%ecx,12(%esp)
-	movl	%edx,16(%esp)
+	movl	%ebp,16(%esp)
 	movl	%esi,20(%esp)
 	leal	-3(%edi),%ebx
-	movl	%ebp,24(%esp)
+	movl	%edx,24(%esp)
 	leal	OPENSSL_ia32cap_P,%eax
 	btl	$26,(%eax)
-	jnc	.L002non_sse2
+	jnc	.L003non_sse2
 	movl	$-1,%eax
 	movd	%eax,%mm7
 	movl	8(%esp),%esi
@@ -547,7 +561,7 @@ bn_mul_mont:
 	psrlq	$32,%mm3
 	incl	%ecx
 .align	16
-.L0031st:
+.L0041st:
 	pmuludq	%mm4,%mm0
 	pmuludq	%mm5,%mm1
 	paddq	%mm0,%mm2
@@ -562,7 +576,7 @@ bn_mul_mont:
 	psrlq	$32,%mm3
 	leal	1(%ecx),%ecx
 	cmpl	%ebx,%ecx
-	jl	.L0031st
+	jl	.L0041st
 	pmuludq	%mm4,%mm0
 	pmuludq	%mm5,%mm1
 	paddq	%mm0,%mm2
@@ -576,7 +590,7 @@ bn_mul_mont:
 	paddq	%mm2,%mm3
 	movq	%mm3,32(%esp,%ebx,4)
 	incl	%edx
-.L004outer:
+.L005outer:
 	xorl	%ecx,%ecx
 	movd	(%edi,%edx,4),%mm4
 	movd	(%esi),%mm5
@@ -598,7 +612,7 @@ bn_mul_mont:
 	paddq	%mm6,%mm2
 	incl	%ecx
 	decl	%ebx
-.L005inner:
+.L006inner:
 	pmuludq	%mm4,%mm0
 	pmuludq	%mm5,%mm1
 	paddq	%mm0,%mm2
@@ -615,7 +629,7 @@ bn_mul_mont:
 	paddq	%mm6,%mm2
 	decl	%ebx
 	leal	1(%ecx),%ecx
-	jnz	.L005inner
+	jnz	.L006inner
 	movl	%ecx,%ebx
 	pmuludq	%mm4,%mm0
 	pmuludq	%mm5,%mm1
@@ -633,11 +647,11 @@ bn_mul_mont:
 	movq	%mm3,32(%esp,%ebx,4)
 	leal	1(%edx),%edx
 	cmpl	%ebx,%edx
-	jle	.L004outer
+	jle	.L005outer
 	emms
-	jmp	.L006common_tail
+	jmp	.L007common_tail
 .align	16
-.L002non_sse2:
+.L003non_sse2:
 	movl	8(%esp),%esi
 	leal	1(%ebx),%ebp
 	movl	12(%esp),%edi
@@ -648,12 +662,12 @@ bn_mul_mont:
 	leal	4(%edi,%ebx,4),%eax
 	orl	%edx,%ebp
 	movl	(%edi),%edi
-	jz	.L007bn_sqr_mont
+	jz	.L008bn_sqr_mont
 	movl	%eax,28(%esp)
 	movl	(%esi),%eax
 	xorl	%edx,%edx
 .align	16
-.L008mull:
+.L009mull:
 	movl	%edx,%ebp
 	mull	%edi
 	addl	%eax,%ebp
@@ -662,7 +676,7 @@ bn_mul_mont:
 	movl	(%esi,%ecx,4),%eax
 	cmpl	%ebx,%ecx
 	movl	%ebp,28(%esp,%ecx,4)
-	jl	.L008mull
+	jl	.L009mull
 	movl	%edx,%ebp
 	mull	%edi
 	movl	20(%esp),%edi
@@ -680,9 +694,9 @@ bn_mul_mont:
 	movl	4(%esi),%eax
 	adcl	$0,%edx
 	incl	%ecx
-	jmp	.L0092ndmadd
+	jmp	.L0102ndmadd
 .align	16
-.L0101stmadd:
+.L0111stmadd:
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ecx,4),%ebp
@@ -693,7 +707,7 @@ bn_mul_mont:
 	adcl	$0,%edx
 	cmpl	%ebx,%ecx
 	movl	%ebp,28(%esp,%ecx,4)
-	jl	.L0101stmadd
+	jl	.L0111stmadd
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ebx,4),%eax
@@ -716,7 +730,7 @@ bn_mul_mont:
 	adcl	$0,%edx
 	movl	$1,%ecx
 .align	16
-.L0092ndmadd:
+.L0102ndmadd:
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ecx,4),%ebp
@@ -727,7 +741,7 @@ bn_mul_mont:
 	adcl	$0,%edx
 	cmpl	%ebx,%ecx
 	movl	%ebp,24(%esp,%ecx,4)
-	jl	.L0092ndmadd
+	jl	.L0102ndmadd
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ebx,4),%ebp
@@ -743,16 +757,16 @@ bn_mul_mont:
 	movl	%edx,32(%esp,%ebx,4)
 	cmpl	28(%esp),%ecx
 	movl	%eax,36(%esp,%ebx,4)
-	je	.L006common_tail
+	je	.L007common_tail
 	movl	(%ecx),%edi
 	movl	8(%esp),%esi
 	movl	%ecx,12(%esp)
 	xorl	%ecx,%ecx
 	xorl	%edx,%edx
 	movl	(%esi),%eax
-	jmp	.L0101stmadd
+	jmp	.L0111stmadd
 .align	16
-.L007bn_sqr_mont:
+.L008bn_sqr_mont:
 	movl	%ebx,(%esp)
 	movl	%ecx,12(%esp)
 	movl	%edi,%eax
@@ -763,7 +777,7 @@ bn_mul_mont:
 	andl	$1,%ebx
 	incl	%ecx
 .align	16
-.L011sqr:
+.L012sqr:
 	movl	(%esi,%ecx,4),%eax
 	movl	%edx,%ebp
 	mull	%edi
@@ -775,7 +789,7 @@ bn_mul_mont:
 	cmpl	(%esp),%ecx
 	movl	%eax,%ebx
 	movl	%ebp,28(%esp,%ecx,4)
-	jl	.L011sqr
+	jl	.L012sqr
 	movl	(%esi,%ecx,4),%eax
 	movl	%edx,%ebp
 	mull	%edi
@@ -799,7 +813,7 @@ bn_mul_mont:
 	movl	4(%esi),%eax
 	movl	$1,%ecx
 .align	16
-.L0123rdmadd:
+.L0133rdmadd:
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ecx,4),%ebp
@@ -818,7 +832,7 @@ bn_mul_mont:
 	adcl	$0,%edx
 	cmpl	%ebx,%ecx
 	movl	%ebp,24(%esp,%ecx,4)
-	jl	.L0123rdmadd
+	jl	.L0133rdmadd
 	movl	%edx,%ebp
 	mull	%edi
 	addl	32(%esp,%ebx,4),%ebp
@@ -834,7 +848,7 @@ bn_mul_mont:
 	movl	%edx,32(%esp,%ebx,4)
 	cmpl	%ebx,%ecx
 	movl	%eax,36(%esp,%ebx,4)
-	je	.L006common_tail
+	je	.L007common_tail
 	movl	4(%esi,%ecx,4),%edi
 	leal	1(%ecx),%ecx
 	movl	%edi,%eax
@@ -846,12 +860,12 @@ bn_mul_mont:
 	xorl	%ebp,%ebp
 	cmpl	%ebx,%ecx
 	leal	1(%ecx),%ecx
-	je	.L013sqrlast
+	je	.L014sqrlast
 	movl	%edx,%ebx
 	shrl	$1,%edx
 	andl	$1,%ebx
 .align	16
-.L014sqradd:
+.L015sqradd:
 	movl	(%esi,%ecx,4),%eax
 	movl	%edx,%ebp
 	mull	%edi
@@ -867,13 +881,13 @@ bn_mul_mont:
 	cmpl	(%esp),%ecx
 	movl	%ebp,28(%esp,%ecx,4)
 	movl	%eax,%ebx
-	jle	.L014sqradd
+	jle	.L015sqradd
 	movl	%edx,%ebp
 	addl	%edx,%edx
 	shrl	$31,%ebp
 	addl	%ebx,%edx
 	adcl	$0,%ebp
-.L013sqrlast:
+.L014sqrlast:
 	movl	20(%esp),%edi
 	movl	16(%esp),%esi
 	imull	32(%esp),%edi
@@ -888,9 +902,9 @@ bn_mul_mont:
 	adcl	$0,%edx
 	movl	$1,%ecx
 	movl	4(%esi),%eax
-	jmp	.L0123rdmadd
+	jmp	.L0133rdmadd
 .align	16
-.L006common_tail:
+.L007common_tail:
 	movl	16(%esp),%ebp
 	movl	4(%esp),%edi
 	leal	32(%esp),%esi
@@ -898,13 +912,13 @@ bn_mul_mont:
 	movl	%ebx,%ecx
 	xorl	%edx,%edx
 .align	16
-.L015sub:
+.L016sub:
 	sbbl	(%ebp,%edx,4),%eax
 	movl	%eax,(%edi,%edx,4)
 	decl	%ecx
 	movl	4(%esi,%edx,4),%eax
 	leal	1(%edx),%edx
-	jge	.L015sub
+	jge	.L016sub
 	sbbl	$0,%eax
 	andl	%eax,%esi
 	notl	%eax
@@ -912,12 +926,12 @@ bn_mul_mont:
 	andl	%eax,%ebp
 	orl	%ebp,%esi
 .align	16
-.L016copy:
+.L017copy:
 	movl	(%esi,%ebx,4),%eax
 	movl	%eax,(%edi,%ebx,4)
 	movl	%ecx,32(%esp,%ebx,4)
 	decl	%ebx
-	jge	.L016copy
+	jge	.L017copy
 	movl	24(%esp),%esp
 	movl	$1,%eax
 .L000just_leave:
diff --git a/secure/lib/libcrypto/man/ASN1_OBJECT_new.3 b/secure/lib/libcrypto/man/ASN1_OBJECT_new.3
index 7e2d83aa0902..36b372707e44 100644
--- a/secure/lib/libcrypto/man/ASN1_OBJECT_new.3
+++ b/secure/lib/libcrypto/man/ASN1_OBJECT_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ASN1_OBJECT_new 3"
-.TH ASN1_OBJECT_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ASN1_OBJECT_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ASN1_STRING_length.3 b/secure/lib/libcrypto/man/ASN1_STRING_length.3
index 834e7aa9b533..17618b0bfbf6 100644
--- a/secure/lib/libcrypto/man/ASN1_STRING_length.3
+++ b/secure/lib/libcrypto/man/ASN1_STRING_length.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ASN1_STRING_length 3"
-.TH ASN1_STRING_length 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ASN1_STRING_length 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ASN1_STRING_new.3 b/secure/lib/libcrypto/man/ASN1_STRING_new.3
index dfb9bbf1cabb..011cfb53f680 100644
--- a/secure/lib/libcrypto/man/ASN1_STRING_new.3
+++ b/secure/lib/libcrypto/man/ASN1_STRING_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ASN1_STRING_new 3"
-.TH ASN1_STRING_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ASN1_STRING_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ASN1_STRING_print_ex.3 b/secure/lib/libcrypto/man/ASN1_STRING_print_ex.3
index 3dd133487f94..08209a41a06b 100644
--- a/secure/lib/libcrypto/man/ASN1_STRING_print_ex.3
+++ b/secure/lib/libcrypto/man/ASN1_STRING_print_ex.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ASN1_STRING_print_ex 3"
-.TH ASN1_STRING_print_ex 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ASN1_STRING_print_ex 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ASN1_TIME_set.3 b/secure/lib/libcrypto/man/ASN1_TIME_set.3
index 161e44bc6a61..aa7d1bdbc2d8 100644
--- a/secure/lib/libcrypto/man/ASN1_TIME_set.3
+++ b/secure/lib/libcrypto/man/ASN1_TIME_set.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ASN1_TIME_set 3"
-.TH ASN1_TIME_set 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ASN1_TIME_set 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ASN1_generate_nconf.3 b/secure/lib/libcrypto/man/ASN1_generate_nconf.3
index 79a462e9760b..fac552d714f9 100644
--- a/secure/lib/libcrypto/man/ASN1_generate_nconf.3
+++ b/secure/lib/libcrypto/man/ASN1_generate_nconf.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ASN1_generate_nconf 3"
-.TH ASN1_generate_nconf 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ASN1_generate_nconf 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_ctrl.3 b/secure/lib/libcrypto/man/BIO_ctrl.3
index 3bfaa4baa7ed..3506e5c5a637 100644
--- a/secure/lib/libcrypto/man/BIO_ctrl.3
+++ b/secure/lib/libcrypto/man/BIO_ctrl.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_ctrl 3"
-.TH BIO_ctrl 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_ctrl 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_f_base64.3 b/secure/lib/libcrypto/man/BIO_f_base64.3
index 844c999c5b1b..6be4f5488943 100644
--- a/secure/lib/libcrypto/man/BIO_f_base64.3
+++ b/secure/lib/libcrypto/man/BIO_f_base64.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_f_base64 3"
-.TH BIO_f_base64 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_f_base64 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_f_buffer.3 b/secure/lib/libcrypto/man/BIO_f_buffer.3
index 4e5cbc45d11c..c16dbd67e10b 100644
--- a/secure/lib/libcrypto/man/BIO_f_buffer.3
+++ b/secure/lib/libcrypto/man/BIO_f_buffer.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_f_buffer 3"
-.TH BIO_f_buffer 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_f_buffer 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_f_cipher.3 b/secure/lib/libcrypto/man/BIO_f_cipher.3
index cc767cf3ac91..c2a5327c123b 100644
--- a/secure/lib/libcrypto/man/BIO_f_cipher.3
+++ b/secure/lib/libcrypto/man/BIO_f_cipher.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_f_cipher 3"
-.TH BIO_f_cipher 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_f_cipher 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_f_md.3 b/secure/lib/libcrypto/man/BIO_f_md.3
index 4955022cbb51..0e230eda9132 100644
--- a/secure/lib/libcrypto/man/BIO_f_md.3
+++ b/secure/lib/libcrypto/man/BIO_f_md.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_f_md 3"
-.TH BIO_f_md 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_f_md 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_f_null.3 b/secure/lib/libcrypto/man/BIO_f_null.3
index 59f1211fde3e..c78009d99683 100644
--- a/secure/lib/libcrypto/man/BIO_f_null.3
+++ b/secure/lib/libcrypto/man/BIO_f_null.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_f_null 3"
-.TH BIO_f_null 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_f_null 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_f_ssl.3 b/secure/lib/libcrypto/man/BIO_f_ssl.3
index da8633944f6d..eb43bff531c7 100644
--- a/secure/lib/libcrypto/man/BIO_f_ssl.3
+++ b/secure/lib/libcrypto/man/BIO_f_ssl.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_f_ssl 3"
-.TH BIO_f_ssl 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_f_ssl 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_find_type.3 b/secure/lib/libcrypto/man/BIO_find_type.3
index ace956766b91..d13c9c70ccf7 100644
--- a/secure/lib/libcrypto/man/BIO_find_type.3
+++ b/secure/lib/libcrypto/man/BIO_find_type.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_find_type 3"
-.TH BIO_find_type 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_find_type 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_new.3 b/secure/lib/libcrypto/man/BIO_new.3
index 214734ebd6ae..41a989995d21 100644
--- a/secure/lib/libcrypto/man/BIO_new.3
+++ b/secure/lib/libcrypto/man/BIO_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_new 3"
-.TH BIO_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_new_CMS.3 b/secure/lib/libcrypto/man/BIO_new_CMS.3
index b0fdc496dae0..9f35882ab213 100644
--- a/secure/lib/libcrypto/man/BIO_new_CMS.3
+++ b/secure/lib/libcrypto/man/BIO_new_CMS.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_new_CMS 3"
-.TH BIO_new_CMS 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_new_CMS 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_push.3 b/secure/lib/libcrypto/man/BIO_push.3
index 44395c15b00c..3247ae34bebd 100644
--- a/secure/lib/libcrypto/man/BIO_push.3
+++ b/secure/lib/libcrypto/man/BIO_push.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_push 3"
-.TH BIO_push 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_push 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_read.3 b/secure/lib/libcrypto/man/BIO_read.3
index 3365c1abccc2..5ad569593935 100644
--- a/secure/lib/libcrypto/man/BIO_read.3
+++ b/secure/lib/libcrypto/man/BIO_read.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_read 3"
-.TH BIO_read 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_read 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_s_accept.3 b/secure/lib/libcrypto/man/BIO_s_accept.3
index 1a6b5d1785f8..205dbdafd9dc 100644
--- a/secure/lib/libcrypto/man/BIO_s_accept.3
+++ b/secure/lib/libcrypto/man/BIO_s_accept.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_s_accept 3"
-.TH BIO_s_accept 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_s_accept 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_s_bio.3 b/secure/lib/libcrypto/man/BIO_s_bio.3
index 0c0873d174cf..e56503b45860 100644
--- a/secure/lib/libcrypto/man/BIO_s_bio.3
+++ b/secure/lib/libcrypto/man/BIO_s_bio.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_s_bio 3"
-.TH BIO_s_bio 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_s_bio 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -255,6 +255,9 @@ buffer. \fIBIO_read()\fR will initially fail and \fIBIO_should_read()\fR will be
 the application then waits for data to be available on the underlying transport
 before flushing the write buffer it will never succeed because the request was
 never sent!
+.PP
+\&\fIBIO_eof()\fR is true if no data is in the peer \s-1BIO\s0 and the peer \s-1BIO\s0 has been
+shutdown.
 .SH "RETURN VALUES"
 .IX Header "RETURN VALUES"
 \&\fIBIO_new_bio_pair()\fR returns 1 on success, with the new BIOs available in
diff --git a/secure/lib/libcrypto/man/BIO_s_connect.3 b/secure/lib/libcrypto/man/BIO_s_connect.3
index 4101280048a2..762a6ab5cc1c 100644
--- a/secure/lib/libcrypto/man/BIO_s_connect.3
+++ b/secure/lib/libcrypto/man/BIO_s_connect.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_s_connect 3"
-.TH BIO_s_connect 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_s_connect 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_s_fd.3 b/secure/lib/libcrypto/man/BIO_s_fd.3
index cd5311a06239..d5afdb7b7de3 100644
--- a/secure/lib/libcrypto/man/BIO_s_fd.3
+++ b/secure/lib/libcrypto/man/BIO_s_fd.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_s_fd 3"
-.TH BIO_s_fd 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_s_fd 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_s_file.3 b/secure/lib/libcrypto/man/BIO_s_file.3
index 0872cbd6cc60..52863936808d 100644
--- a/secure/lib/libcrypto/man/BIO_s_file.3
+++ b/secure/lib/libcrypto/man/BIO_s_file.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_s_file 3"
-.TH BIO_s_file 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_s_file 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_s_mem.3 b/secure/lib/libcrypto/man/BIO_s_mem.3
index 43527bdd9ad3..6b4898c861bc 100644
--- a/secure/lib/libcrypto/man/BIO_s_mem.3
+++ b/secure/lib/libcrypto/man/BIO_s_mem.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_s_mem 3"
-.TH BIO_s_mem 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_s_mem 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_s_null.3 b/secure/lib/libcrypto/man/BIO_s_null.3
index 73e5fe7d1407..af9bc4a54319 100644
--- a/secure/lib/libcrypto/man/BIO_s_null.3
+++ b/secure/lib/libcrypto/man/BIO_s_null.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_s_null 3"
-.TH BIO_s_null 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_s_null 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_s_socket.3 b/secure/lib/libcrypto/man/BIO_s_socket.3
index c6268ee5d307..e6af124c1531 100644
--- a/secure/lib/libcrypto/man/BIO_s_socket.3
+++ b/secure/lib/libcrypto/man/BIO_s_socket.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_s_socket 3"
-.TH BIO_s_socket 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_s_socket 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_set_callback.3 b/secure/lib/libcrypto/man/BIO_set_callback.3
index 9a8c50e79aee..b5b3533d4c18 100644
--- a/secure/lib/libcrypto/man/BIO_set_callback.3
+++ b/secure/lib/libcrypto/man/BIO_set_callback.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_set_callback 3"
-.TH BIO_set_callback 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_set_callback 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BIO_should_retry.3 b/secure/lib/libcrypto/man/BIO_should_retry.3
index cf85903ec934..1280917791e5 100644
--- a/secure/lib/libcrypto/man/BIO_should_retry.3
+++ b/secure/lib/libcrypto/man/BIO_should_retry.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BIO_should_retry 3"
-.TH BIO_should_retry 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BIO_should_retry 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_BLINDING_new.3 b/secure/lib/libcrypto/man/BN_BLINDING_new.3
index 8c1abad44cfa..907209aca501 100644
--- a/secure/lib/libcrypto/man/BN_BLINDING_new.3
+++ b/secure/lib/libcrypto/man/BN_BLINDING_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_BLINDING_new 3"
-.TH BN_BLINDING_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_BLINDING_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_CTX_new.3 b/secure/lib/libcrypto/man/BN_CTX_new.3
index fd365feacddb..f487609f6686 100644
--- a/secure/lib/libcrypto/man/BN_CTX_new.3
+++ b/secure/lib/libcrypto/man/BN_CTX_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_CTX_new 3"
-.TH BN_CTX_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_CTX_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_CTX_start.3 b/secure/lib/libcrypto/man/BN_CTX_start.3
index 68d5353fb693..aa9f57908b3e 100644
--- a/secure/lib/libcrypto/man/BN_CTX_start.3
+++ b/secure/lib/libcrypto/man/BN_CTX_start.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_CTX_start 3"
-.TH BN_CTX_start 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_CTX_start 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_add.3 b/secure/lib/libcrypto/man/BN_add.3
index 00b5fb656ba7..7d72d7b97bc5 100644
--- a/secure/lib/libcrypto/man/BN_add.3
+++ b/secure/lib/libcrypto/man/BN_add.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_add 3"
-.TH BN_add 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_add 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_add_word.3 b/secure/lib/libcrypto/man/BN_add_word.3
index b6fa3c1a760a..ebe98f3a0bc5 100644
--- a/secure/lib/libcrypto/man/BN_add_word.3
+++ b/secure/lib/libcrypto/man/BN_add_word.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_add_word 3"
-.TH BN_add_word 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_add_word 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_bn2bin.3 b/secure/lib/libcrypto/man/BN_bn2bin.3
index 41a4fd335ed5..bee8781e5c3c 100644
--- a/secure/lib/libcrypto/man/BN_bn2bin.3
+++ b/secure/lib/libcrypto/man/BN_bn2bin.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_bn2bin 3"
-.TH BN_bn2bin 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_bn2bin 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -179,7 +179,9 @@ freed later using \fIOPENSSL_free()\fR.
 to a \fB\s-1BIGNUM\s0\fR and stores it in **\fBbn\fR. If *\fBbn\fR is \s-1NULL,\s0 a new
 \&\fB\s-1BIGNUM\s0\fR is created. If \fBbn\fR is \s-1NULL,\s0 it only computes the number's
 length in hexadecimal digits. If the string starts with '\-', the
-number is negative. \fIBN_dec2bn()\fR is the same using the decimal system.
+number is negative.
+A \*(L"negative zero\*(R" is converted to zero.
+\&\fIBN_dec2bn()\fR is the same using the decimal system.
 .PP
 \&\fIBN_print()\fR and \fIBN_print_fp()\fR write the hexadecimal encoding of \fBa\fR,
 with a leading '\-' for negative numbers, to the \fB\s-1BIO\s0\fR or \fB\s-1FILE\s0\fR
diff --git a/secure/lib/libcrypto/man/BN_cmp.3 b/secure/lib/libcrypto/man/BN_cmp.3
index 1a440b30c06b..8769dd1c21e2 100644
--- a/secure/lib/libcrypto/man/BN_cmp.3
+++ b/secure/lib/libcrypto/man/BN_cmp.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_cmp 3"
-.TH BN_cmp 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_cmp 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_copy.3 b/secure/lib/libcrypto/man/BN_copy.3
index 7417d203e1b3..ef83d72cec39 100644
--- a/secure/lib/libcrypto/man/BN_copy.3
+++ b/secure/lib/libcrypto/man/BN_copy.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_copy 3"
-.TH BN_copy 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_copy 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_generate_prime.3 b/secure/lib/libcrypto/man/BN_generate_prime.3
index f2ba19329999..0af3cc6e7617 100644
--- a/secure/lib/libcrypto/man/BN_generate_prime.3
+++ b/secure/lib/libcrypto/man/BN_generate_prime.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_generate_prime 3"
-.TH BN_generate_prime 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_generate_prime 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_mod_inverse.3 b/secure/lib/libcrypto/man/BN_mod_inverse.3
index 192d649c3fcc..d6654eb1f1bb 100644
--- a/secure/lib/libcrypto/man/BN_mod_inverse.3
+++ b/secure/lib/libcrypto/man/BN_mod_inverse.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_mod_inverse 3"
-.TH BN_mod_inverse 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_mod_inverse 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_mod_mul_montgomery.3 b/secure/lib/libcrypto/man/BN_mod_mul_montgomery.3
index 003f207addd8..17e3b68f7fd2 100644
--- a/secure/lib/libcrypto/man/BN_mod_mul_montgomery.3
+++ b/secure/lib/libcrypto/man/BN_mod_mul_montgomery.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_mod_mul_montgomery 3"
-.TH BN_mod_mul_montgomery 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_mod_mul_montgomery 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_mod_mul_reciprocal.3 b/secure/lib/libcrypto/man/BN_mod_mul_reciprocal.3
index b3a70cefc6aa..d2ab42e36154 100644
--- a/secure/lib/libcrypto/man/BN_mod_mul_reciprocal.3
+++ b/secure/lib/libcrypto/man/BN_mod_mul_reciprocal.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_mod_mul_reciprocal 3"
-.TH BN_mod_mul_reciprocal 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_mod_mul_reciprocal 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_new.3 b/secure/lib/libcrypto/man/BN_new.3
index 0622ba4fb7fa..653a6478d0c9 100644
--- a/secure/lib/libcrypto/man/BN_new.3
+++ b/secure/lib/libcrypto/man/BN_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_new 3"
-.TH BN_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_num_bytes.3 b/secure/lib/libcrypto/man/BN_num_bytes.3
index 00a488f77f43..3ac779900f11 100644
--- a/secure/lib/libcrypto/man/BN_num_bytes.3
+++ b/secure/lib/libcrypto/man/BN_num_bytes.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_num_bytes 3"
-.TH BN_num_bytes 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_num_bytes 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_rand.3 b/secure/lib/libcrypto/man/BN_rand.3
index 2715533902dc..83ada14156f3 100644
--- a/secure/lib/libcrypto/man/BN_rand.3
+++ b/secure/lib/libcrypto/man/BN_rand.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_rand 3"
-.TH BN_rand 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_rand 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -156,7 +156,11 @@ BN_rand, BN_pseudo_rand, BN_rand_range, BN_pseudo_rand_range \- generate pseudo\
 .SH "DESCRIPTION"
 .IX Header "DESCRIPTION"
 \&\fIBN_rand()\fR generates a cryptographically strong pseudo-random number of
-\&\fBbits\fR in length and stores it in \fBrnd\fR. If \fBtop\fR is \-1, the
+\&\fBbits\fR in length and stores it in \fBrnd\fR.
+If \fBbits\fR is less than zero, or too small to
+accomodate the requirements specified by the \fBtop\fR and \fBbottom\fR
+parameters, an error is returned.
+If \fBtop\fR is \-1, the
 most significant bit of the random number can be zero. If \fBtop\fR is 0,
 it is set to 1, and if \fBtop\fR is 1, the two most significant bits of
 the number will be set to 1, so that the product of two such random
diff --git a/secure/lib/libcrypto/man/BN_set_bit.3 b/secure/lib/libcrypto/man/BN_set_bit.3
index 6438b982c029..b5095498c516 100644
--- a/secure/lib/libcrypto/man/BN_set_bit.3
+++ b/secure/lib/libcrypto/man/BN_set_bit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_set_bit 3"
-.TH BN_set_bit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_set_bit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_swap.3 b/secure/lib/libcrypto/man/BN_swap.3
index 22e5d46d24f2..ec51fbbd3d2d 100644
--- a/secure/lib/libcrypto/man/BN_swap.3
+++ b/secure/lib/libcrypto/man/BN_swap.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_swap 3"
-.TH BN_swap 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_swap 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/BN_zero.3 b/secure/lib/libcrypto/man/BN_zero.3
index 34009adaff64..f5b72e4a9fdf 100644
--- a/secure/lib/libcrypto/man/BN_zero.3
+++ b/secure/lib/libcrypto/man/BN_zero.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "BN_zero 3"
-.TH BN_zero 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH BN_zero 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_add0_cert.3 b/secure/lib/libcrypto/man/CMS_add0_cert.3
index ec65c59be743..5c68fe3b2fc3 100644
--- a/secure/lib/libcrypto/man/CMS_add0_cert.3
+++ b/secure/lib/libcrypto/man/CMS_add0_cert.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_add0_cert 3"
-.TH CMS_add0_cert 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_add0_cert 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_add1_recipient_cert.3 b/secure/lib/libcrypto/man/CMS_add1_recipient_cert.3
index b87427ffe76d..cef940262a54 100644
--- a/secure/lib/libcrypto/man/CMS_add1_recipient_cert.3
+++ b/secure/lib/libcrypto/man/CMS_add1_recipient_cert.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_add1_recipient_cert 3"
-.TH CMS_add1_recipient_cert 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_add1_recipient_cert 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_add1_signer.3 b/secure/lib/libcrypto/man/CMS_add1_signer.3
index 97e721f2f506..201943097191 100644
--- a/secure/lib/libcrypto/man/CMS_add1_signer.3
+++ b/secure/lib/libcrypto/man/CMS_add1_signer.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_add1_signer 3"
-.TH CMS_add1_signer 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_add1_signer 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_compress.3 b/secure/lib/libcrypto/man/CMS_compress.3
index e2542eaadd61..0dc09c35dea7 100644
--- a/secure/lib/libcrypto/man/CMS_compress.3
+++ b/secure/lib/libcrypto/man/CMS_compress.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_compress 3"
-.TH CMS_compress 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_compress 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_decrypt.3 b/secure/lib/libcrypto/man/CMS_decrypt.3
index 3dea2963fc05..b626d33898b9 100644
--- a/secure/lib/libcrypto/man/CMS_decrypt.3
+++ b/secure/lib/libcrypto/man/CMS_decrypt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_decrypt 3"
-.TH CMS_decrypt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_decrypt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_encrypt.3 b/secure/lib/libcrypto/man/CMS_encrypt.3
index 267b0da1f6a4..fb0f48e1b4ee 100644
--- a/secure/lib/libcrypto/man/CMS_encrypt.3
+++ b/secure/lib/libcrypto/man/CMS_encrypt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_encrypt 3"
-.TH CMS_encrypt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_encrypt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_final.3 b/secure/lib/libcrypto/man/CMS_final.3
index 0c7e396e4c03..5969055c6491 100644
--- a/secure/lib/libcrypto/man/CMS_final.3
+++ b/secure/lib/libcrypto/man/CMS_final.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_final 3"
-.TH CMS_final 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_final 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_get0_RecipientInfos.3 b/secure/lib/libcrypto/man/CMS_get0_RecipientInfos.3
index 871fa05a3ce9..a3f2d28522f2 100644
--- a/secure/lib/libcrypto/man/CMS_get0_RecipientInfos.3
+++ b/secure/lib/libcrypto/man/CMS_get0_RecipientInfos.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_get0_RecipientInfos 3"
-.TH CMS_get0_RecipientInfos 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_get0_RecipientInfos 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_get0_SignerInfos.3 b/secure/lib/libcrypto/man/CMS_get0_SignerInfos.3
index 7c2ae28bc8ca..3e75dc6cbe7b 100644
--- a/secure/lib/libcrypto/man/CMS_get0_SignerInfos.3
+++ b/secure/lib/libcrypto/man/CMS_get0_SignerInfos.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_get0_SignerInfos 3"
-.TH CMS_get0_SignerInfos 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_get0_SignerInfos 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_get0_type.3 b/secure/lib/libcrypto/man/CMS_get0_type.3
index 12723030cc17..410e94e95c7b 100644
--- a/secure/lib/libcrypto/man/CMS_get0_type.3
+++ b/secure/lib/libcrypto/man/CMS_get0_type.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_get0_type 3"
-.TH CMS_get0_type 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_get0_type 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_get1_ReceiptRequest.3 b/secure/lib/libcrypto/man/CMS_get1_ReceiptRequest.3
index 75e804b22714..de5f90c9ba6d 100644
--- a/secure/lib/libcrypto/man/CMS_get1_ReceiptRequest.3
+++ b/secure/lib/libcrypto/man/CMS_get1_ReceiptRequest.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_get1_ReceiptRequest 3"
-.TH CMS_get1_ReceiptRequest 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_get1_ReceiptRequest 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_sign.3 b/secure/lib/libcrypto/man/CMS_sign.3
index 5e5c6ccc690a..37709d9391ec 100644
--- a/secure/lib/libcrypto/man/CMS_sign.3
+++ b/secure/lib/libcrypto/man/CMS_sign.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_sign 3"
-.TH CMS_sign 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_sign 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_sign_receipt.3 b/secure/lib/libcrypto/man/CMS_sign_receipt.3
index 06c58d820217..61a3821fd925 100644
--- a/secure/lib/libcrypto/man/CMS_sign_receipt.3
+++ b/secure/lib/libcrypto/man/CMS_sign_receipt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_sign_receipt 3"
-.TH CMS_sign_receipt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_sign_receipt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_uncompress.3 b/secure/lib/libcrypto/man/CMS_uncompress.3
index 3a2ecad3deae..cbf69c34db25 100644
--- a/secure/lib/libcrypto/man/CMS_uncompress.3
+++ b/secure/lib/libcrypto/man/CMS_uncompress.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_uncompress 3"
-.TH CMS_uncompress 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_uncompress 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_verify.3 b/secure/lib/libcrypto/man/CMS_verify.3
index 433ab804a592..fc4012ebc2e3 100644
--- a/secure/lib/libcrypto/man/CMS_verify.3
+++ b/secure/lib/libcrypto/man/CMS_verify.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_verify 3"
-.TH CMS_verify 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_verify 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CMS_verify_receipt.3 b/secure/lib/libcrypto/man/CMS_verify_receipt.3
index 8784d12c39a0..25e3bc230d91 100644
--- a/secure/lib/libcrypto/man/CMS_verify_receipt.3
+++ b/secure/lib/libcrypto/man/CMS_verify_receipt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS_verify_receipt 3"
-.TH CMS_verify_receipt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS_verify_receipt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CONF_modules_free.3 b/secure/lib/libcrypto/man/CONF_modules_free.3
index 1ebb45966357..53ae4547b90a 100644
--- a/secure/lib/libcrypto/man/CONF_modules_free.3
+++ b/secure/lib/libcrypto/man/CONF_modules_free.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CONF_modules_free 3"
-.TH CONF_modules_free 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CONF_modules_free 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CONF_modules_load_file.3 b/secure/lib/libcrypto/man/CONF_modules_load_file.3
index 82f0b8b77794..98c4d993de0a 100644
--- a/secure/lib/libcrypto/man/CONF_modules_load_file.3
+++ b/secure/lib/libcrypto/man/CONF_modules_load_file.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CONF_modules_load_file 3"
-.TH CONF_modules_load_file 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CONF_modules_load_file 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/CRYPTO_set_ex_data.3 b/secure/lib/libcrypto/man/CRYPTO_set_ex_data.3
index 2d643041db6f..f85a676066df 100644
--- a/secure/lib/libcrypto/man/CRYPTO_set_ex_data.3
+++ b/secure/lib/libcrypto/man/CRYPTO_set_ex_data.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CRYPTO_set_ex_data 3"
-.TH CRYPTO_set_ex_data 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CRYPTO_set_ex_data 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DH_generate_key.3 b/secure/lib/libcrypto/man/DH_generate_key.3
index d219ecfa6a28..4fdd72fa3d8d 100644
--- a/secure/lib/libcrypto/man/DH_generate_key.3
+++ b/secure/lib/libcrypto/man/DH_generate_key.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DH_generate_key 3"
-.TH DH_generate_key 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DH_generate_key 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DH_generate_parameters.3 b/secure/lib/libcrypto/man/DH_generate_parameters.3
index 55118a06de7a..5370a0f44770 100644
--- a/secure/lib/libcrypto/man/DH_generate_parameters.3
+++ b/secure/lib/libcrypto/man/DH_generate_parameters.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DH_generate_parameters 3"
-.TH DH_generate_parameters 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DH_generate_parameters 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DH_get_ex_new_index.3 b/secure/lib/libcrypto/man/DH_get_ex_new_index.3
index 56d5d9c96d88..175a5047c5c5 100644
--- a/secure/lib/libcrypto/man/DH_get_ex_new_index.3
+++ b/secure/lib/libcrypto/man/DH_get_ex_new_index.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DH_get_ex_new_index 3"
-.TH DH_get_ex_new_index 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DH_get_ex_new_index 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DH_new.3 b/secure/lib/libcrypto/man/DH_new.3
index 60e8f2a2830b..e138fd94284e 100644
--- a/secure/lib/libcrypto/man/DH_new.3
+++ b/secure/lib/libcrypto/man/DH_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DH_new 3"
-.TH DH_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DH_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DH_set_method.3 b/secure/lib/libcrypto/man/DH_set_method.3
index 7e721865c541..1ef0de0df98f 100644
--- a/secure/lib/libcrypto/man/DH_set_method.3
+++ b/secure/lib/libcrypto/man/DH_set_method.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DH_set_method 3"
-.TH DH_set_method 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DH_set_method 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DH_size.3 b/secure/lib/libcrypto/man/DH_size.3
index 4ee2f3fdfec2..b6d0cdd47f60 100644
--- a/secure/lib/libcrypto/man/DH_size.3
+++ b/secure/lib/libcrypto/man/DH_size.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DH_size 3"
-.TH DH_size 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DH_size 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_SIG_new.3 b/secure/lib/libcrypto/man/DSA_SIG_new.3
index 12ddf827073a..96029230f7f3 100644
--- a/secure/lib/libcrypto/man/DSA_SIG_new.3
+++ b/secure/lib/libcrypto/man/DSA_SIG_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_SIG_new 3"
-.TH DSA_SIG_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_SIG_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_do_sign.3 b/secure/lib/libcrypto/man/DSA_do_sign.3
index 5428896295ec..5f6f170e505e 100644
--- a/secure/lib/libcrypto/man/DSA_do_sign.3
+++ b/secure/lib/libcrypto/man/DSA_do_sign.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_do_sign 3"
-.TH DSA_do_sign 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_do_sign 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_dup_DH.3 b/secure/lib/libcrypto/man/DSA_dup_DH.3
index d8bdb9cf0230..6f09340fecdc 100644
--- a/secure/lib/libcrypto/man/DSA_dup_DH.3
+++ b/secure/lib/libcrypto/man/DSA_dup_DH.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_dup_DH 3"
-.TH DSA_dup_DH 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_dup_DH 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_generate_key.3 b/secure/lib/libcrypto/man/DSA_generate_key.3
index 5d0babb53194..9f025b4b0848 100644
--- a/secure/lib/libcrypto/man/DSA_generate_key.3
+++ b/secure/lib/libcrypto/man/DSA_generate_key.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_generate_key 3"
-.TH DSA_generate_key 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_generate_key 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_generate_parameters.3 b/secure/lib/libcrypto/man/DSA_generate_parameters.3
index 6f567a955318..265207d8b363 100644
--- a/secure/lib/libcrypto/man/DSA_generate_parameters.3
+++ b/secure/lib/libcrypto/man/DSA_generate_parameters.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_generate_parameters 3"
-.TH DSA_generate_parameters 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_generate_parameters 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_get_ex_new_index.3 b/secure/lib/libcrypto/man/DSA_get_ex_new_index.3
index 0131d0c8d3c7..073a56019781 100644
--- a/secure/lib/libcrypto/man/DSA_get_ex_new_index.3
+++ b/secure/lib/libcrypto/man/DSA_get_ex_new_index.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_get_ex_new_index 3"
-.TH DSA_get_ex_new_index 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_get_ex_new_index 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_new.3 b/secure/lib/libcrypto/man/DSA_new.3
index c94d518c281f..abf8c4c0a44a 100644
--- a/secure/lib/libcrypto/man/DSA_new.3
+++ b/secure/lib/libcrypto/man/DSA_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_new 3"
-.TH DSA_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_set_method.3 b/secure/lib/libcrypto/man/DSA_set_method.3
index a623ad26690e..736e8e4589dc 100644
--- a/secure/lib/libcrypto/man/DSA_set_method.3
+++ b/secure/lib/libcrypto/man/DSA_set_method.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_set_method 3"
-.TH DSA_set_method 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_set_method 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_sign.3 b/secure/lib/libcrypto/man/DSA_sign.3
index d8d3057265b4..01a281a9f810 100644
--- a/secure/lib/libcrypto/man/DSA_sign.3
+++ b/secure/lib/libcrypto/man/DSA_sign.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_sign 3"
-.TH DSA_sign 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_sign 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/DSA_size.3 b/secure/lib/libcrypto/man/DSA_size.3
index f6fbe0ed2189..9ba45ceaac24 100644
--- a/secure/lib/libcrypto/man/DSA_size.3
+++ b/secure/lib/libcrypto/man/DSA_size.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA_size 3"
-.TH DSA_size 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA_size 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EC_GFp_simple_method.3 b/secure/lib/libcrypto/man/EC_GFp_simple_method.3
index b5b2da49717f..921250fb7710 100644
--- a/secure/lib/libcrypto/man/EC_GFp_simple_method.3
+++ b/secure/lib/libcrypto/man/EC_GFp_simple_method.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EC_GFp_simple_method 3"
-.TH EC_GFp_simple_method 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EC_GFp_simple_method 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EC_GROUP_copy.3 b/secure/lib/libcrypto/man/EC_GROUP_copy.3
index 5e312cb59d90..7d3e2d9d6ab7 100644
--- a/secure/lib/libcrypto/man/EC_GROUP_copy.3
+++ b/secure/lib/libcrypto/man/EC_GROUP_copy.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EC_GROUP_copy 3"
-.TH EC_GROUP_copy 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EC_GROUP_copy 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EC_GROUP_new.3 b/secure/lib/libcrypto/man/EC_GROUP_new.3
index 95e47c189348..c3f225bb6799 100644
--- a/secure/lib/libcrypto/man/EC_GROUP_new.3
+++ b/secure/lib/libcrypto/man/EC_GROUP_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EC_GROUP_new 3"
-.TH EC_GROUP_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EC_GROUP_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EC_KEY_new.3 b/secure/lib/libcrypto/man/EC_KEY_new.3
index a096d5979e2c..a3b5be5c0f1a 100644
--- a/secure/lib/libcrypto/man/EC_KEY_new.3
+++ b/secure/lib/libcrypto/man/EC_KEY_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EC_KEY_new 3"
-.TH EC_KEY_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EC_KEY_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EC_POINT_add.3 b/secure/lib/libcrypto/man/EC_POINT_add.3
index fe37dee31019..2ed896bdaa53 100644
--- a/secure/lib/libcrypto/man/EC_POINT_add.3
+++ b/secure/lib/libcrypto/man/EC_POINT_add.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EC_POINT_add 3"
-.TH EC_POINT_add 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EC_POINT_add 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EC_POINT_new.3 b/secure/lib/libcrypto/man/EC_POINT_new.3
index 8e7168767e03..a425156f530a 100644
--- a/secure/lib/libcrypto/man/EC_POINT_new.3
+++ b/secure/lib/libcrypto/man/EC_POINT_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EC_POINT_new 3"
-.TH EC_POINT_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EC_POINT_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_GET_LIB.3 b/secure/lib/libcrypto/man/ERR_GET_LIB.3
index 2bec9e9fc54e..8f480057739a 100644
--- a/secure/lib/libcrypto/man/ERR_GET_LIB.3
+++ b/secure/lib/libcrypto/man/ERR_GET_LIB.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_GET_LIB 3"
-.TH ERR_GET_LIB 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_GET_LIB 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_clear_error.3 b/secure/lib/libcrypto/man/ERR_clear_error.3
index be1107e9b401..36fe425ee10c 100644
--- a/secure/lib/libcrypto/man/ERR_clear_error.3
+++ b/secure/lib/libcrypto/man/ERR_clear_error.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_clear_error 3"
-.TH ERR_clear_error 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_clear_error 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_error_string.3 b/secure/lib/libcrypto/man/ERR_error_string.3
index 7b8e196d1554..4d24b0af2041 100644
--- a/secure/lib/libcrypto/man/ERR_error_string.3
+++ b/secure/lib/libcrypto/man/ERR_error_string.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_error_string 3"
-.TH ERR_error_string 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_error_string 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_get_error.3 b/secure/lib/libcrypto/man/ERR_get_error.3
index 72b6747610bb..3cdfb1d1ad73 100644
--- a/secure/lib/libcrypto/man/ERR_get_error.3
+++ b/secure/lib/libcrypto/man/ERR_get_error.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_get_error 3"
-.TH ERR_get_error 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_get_error 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_load_crypto_strings.3 b/secure/lib/libcrypto/man/ERR_load_crypto_strings.3
index 72ab69508280..76625072781a 100644
--- a/secure/lib/libcrypto/man/ERR_load_crypto_strings.3
+++ b/secure/lib/libcrypto/man/ERR_load_crypto_strings.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_load_crypto_strings 3"
-.TH ERR_load_crypto_strings 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_load_crypto_strings 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_load_strings.3 b/secure/lib/libcrypto/man/ERR_load_strings.3
index 7650c160d2a3..6684b04eeb2b 100644
--- a/secure/lib/libcrypto/man/ERR_load_strings.3
+++ b/secure/lib/libcrypto/man/ERR_load_strings.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_load_strings 3"
-.TH ERR_load_strings 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_load_strings 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_print_errors.3 b/secure/lib/libcrypto/man/ERR_print_errors.3
index 46e0d0dc6e65..6baea0b9d39f 100644
--- a/secure/lib/libcrypto/man/ERR_print_errors.3
+++ b/secure/lib/libcrypto/man/ERR_print_errors.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_print_errors 3"
-.TH ERR_print_errors 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_print_errors 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_put_error.3 b/secure/lib/libcrypto/man/ERR_put_error.3
index b9e39da83a60..e4befadfb9ee 100644
--- a/secure/lib/libcrypto/man/ERR_put_error.3
+++ b/secure/lib/libcrypto/man/ERR_put_error.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_put_error 3"
-.TH ERR_put_error 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_put_error 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_remove_state.3 b/secure/lib/libcrypto/man/ERR_remove_state.3
index 24f0ef9f8f2f..149fc8b0ef9a 100644
--- a/secure/lib/libcrypto/man/ERR_remove_state.3
+++ b/secure/lib/libcrypto/man/ERR_remove_state.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_remove_state 3"
-.TH ERR_remove_state 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_remove_state 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ERR_set_mark.3 b/secure/lib/libcrypto/man/ERR_set_mark.3
index fbb56e966b0b..6ef06fab84d8 100644
--- a/secure/lib/libcrypto/man/ERR_set_mark.3
+++ b/secure/lib/libcrypto/man/ERR_set_mark.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERR_set_mark 3"
-.TH ERR_set_mark 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERR_set_mark 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_BytesToKey.3 b/secure/lib/libcrypto/man/EVP_BytesToKey.3
index 9d4252e1811b..e8f770285a7e 100644
--- a/secure/lib/libcrypto/man/EVP_BytesToKey.3
+++ b/secure/lib/libcrypto/man/EVP_BytesToKey.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_BytesToKey 3"
-.TH EVP_BytesToKey 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_BytesToKey 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_DigestInit.3 b/secure/lib/libcrypto/man/EVP_DigestInit.3
index bd94a6423b34..fffd3342600a 100644
--- a/secure/lib/libcrypto/man/EVP_DigestInit.3
+++ b/secure/lib/libcrypto/man/EVP_DigestInit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_DigestInit 3"
-.TH EVP_DigestInit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_DigestInit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_DigestSignInit.3 b/secure/lib/libcrypto/man/EVP_DigestSignInit.3
index dfb1c5ecc757..73e8cddd9702 100644
--- a/secure/lib/libcrypto/man/EVP_DigestSignInit.3
+++ b/secure/lib/libcrypto/man/EVP_DigestSignInit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_DigestSignInit 3"
-.TH EVP_DigestSignInit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_DigestSignInit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_DigestVerifyInit.3 b/secure/lib/libcrypto/man/EVP_DigestVerifyInit.3
index 13e705271e59..8df778edf250 100644
--- a/secure/lib/libcrypto/man/EVP_DigestVerifyInit.3
+++ b/secure/lib/libcrypto/man/EVP_DigestVerifyInit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_DigestVerifyInit 3"
-.TH EVP_DigestVerifyInit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_DigestVerifyInit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_EncodeInit.3 b/secure/lib/libcrypto/man/EVP_EncodeInit.3
index c9f04dda84ae..c63d633bf70b 100644
--- a/secure/lib/libcrypto/man/EVP_EncodeInit.3
+++ b/secure/lib/libcrypto/man/EVP_EncodeInit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_EncodeInit 3"
-.TH EVP_EncodeInit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_EncodeInit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_EncryptInit.3 b/secure/lib/libcrypto/man/EVP_EncryptInit.3
index a78c7e8ad293..d3f98e83d627 100644
--- a/secure/lib/libcrypto/man/EVP_EncryptInit.3
+++ b/secure/lib/libcrypto/man/EVP_EncryptInit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_EncryptInit 3"
-.TH EVP_EncryptInit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_EncryptInit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -302,10 +302,11 @@ similar way to \fIEVP_EncryptInit_ex()\fR, EVP_DecryptInit_ex and
 \&\fIEVP_CipherInit_ex()\fR except the \fBctx\fR parameter does not need to be
 initialized and they always use the default cipher implementation.
 .PP
-\&\fIEVP_EncryptFinal()\fR, \fIEVP_DecryptFinal()\fR and \fIEVP_CipherFinal()\fR behave in a
-similar way to \fIEVP_EncryptFinal_ex()\fR, \fIEVP_DecryptFinal_ex()\fR and
-\&\fIEVP_CipherFinal_ex()\fR except \fBctx\fR is automatically cleaned up 
-after the call.
+\&\fIEVP_EncryptFinal()\fR, \fIEVP_DecryptFinal()\fR and \fIEVP_CipherFinal()\fR are
+identical to \fIEVP_EncryptFinal_ex()\fR, \fIEVP_DecryptFinal_ex()\fR and
+\&\fIEVP_CipherFinal_ex()\fR. In previous releases they also cleaned up
+the \fBctx\fR, but this is no longer done and \fIEVP_CIPHER_CTX_clean()\fR
+must be called to free any context resources.
 .PP
 \&\fIEVP_get_cipherbyname()\fR, \fIEVP_get_cipherbynid()\fR and \fIEVP_get_cipherbyobj()\fR
 return an \s-1EVP_CIPHER\s0 structure when passed a cipher name, a \s-1NID\s0 or an
diff --git a/secure/lib/libcrypto/man/EVP_OpenInit.3 b/secure/lib/libcrypto/man/EVP_OpenInit.3
index 05a2b53bdc72..f8cbfd99047b 100644
--- a/secure/lib/libcrypto/man/EVP_OpenInit.3
+++ b/secure/lib/libcrypto/man/EVP_OpenInit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_OpenInit 3"
-.TH EVP_OpenInit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_OpenInit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_CTX_ctrl.3 b/secure/lib/libcrypto/man/EVP_PKEY_CTX_ctrl.3
index 6560af4b08b6..584cb5a0a69f 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_CTX_ctrl.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_CTX_ctrl.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_CTX_ctrl 3"
-.TH EVP_PKEY_CTX_ctrl 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_CTX_ctrl 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_CTX_new.3 b/secure/lib/libcrypto/man/EVP_PKEY_CTX_new.3
index c15160beb782..56c1e6fb6ecd 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_CTX_new.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_CTX_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_CTX_new 3"
-.TH EVP_PKEY_CTX_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_CTX_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_cmp.3 b/secure/lib/libcrypto/man/EVP_PKEY_cmp.3
index 286743b630ca..6d836b685b51 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_cmp.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_cmp.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_cmp 3"
-.TH EVP_PKEY_cmp 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_cmp 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -158,7 +158,9 @@ parameters of \fBpkey\fR are missing and 0 if they are present or the algorithm
 doesn't use parameters.
 .PP
 The function \fIEVP_PKEY_copy_parameters()\fR copies the parameters from key
-\&\fBfrom\fR to key \fBto\fR.
+\&\fBfrom\fR to key \fBto\fR. An error is returned if the parameters are missing in
+\&\fBfrom\fR or present in both \fBfrom\fR and \fBto\fR and mismatch. If the parameters
+in \fBfrom\fR and \fBto\fR are both present and match this function has no effect.
 .PP
 The function \fIEVP_PKEY_cmp_parameters()\fR compares the parameters of keys
 \&\fBa\fR and \fBb\fR.
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_decrypt.3 b/secure/lib/libcrypto/man/EVP_PKEY_decrypt.3
index 8df16a030ab0..bb788ecb853c 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_decrypt.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_decrypt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_decrypt 3"
-.TH EVP_PKEY_decrypt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_decrypt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_derive.3 b/secure/lib/libcrypto/man/EVP_PKEY_derive.3
index ea32e114fb10..9934edd7595f 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_derive.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_derive.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_derive 3"
-.TH EVP_PKEY_derive 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_derive 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_encrypt.3 b/secure/lib/libcrypto/man/EVP_PKEY_encrypt.3
index dd5de681a788..7fa0671692d8 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_encrypt.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_encrypt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_encrypt 3"
-.TH EVP_PKEY_encrypt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_encrypt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_get_default_digest.3 b/secure/lib/libcrypto/man/EVP_PKEY_get_default_digest.3
index a48abb29115e..a3790e847843 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_get_default_digest.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_get_default_digest.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_get_default_digest 3"
-.TH EVP_PKEY_get_default_digest 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_get_default_digest 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_keygen.3 b/secure/lib/libcrypto/man/EVP_PKEY_keygen.3
index 4009e46dca9e..843750be0c72 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_keygen.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_keygen.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_keygen 3"
-.TH EVP_PKEY_keygen 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_keygen 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_new.3 b/secure/lib/libcrypto/man/EVP_PKEY_new.3
index 92d5be2cbf0f..4887e173121c 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_new.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_new 3"
-.TH EVP_PKEY_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_print_private.3 b/secure/lib/libcrypto/man/EVP_PKEY_print_private.3
index 0d6d1600cb87..03fb07d4935d 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_print_private.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_print_private.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_print_private 3"
-.TH EVP_PKEY_print_private 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_print_private 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_set1_RSA.3 b/secure/lib/libcrypto/man/EVP_PKEY_set1_RSA.3
index f002892d6cfa..8794c20f868b 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_set1_RSA.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_set1_RSA.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_set1_RSA 3"
-.TH EVP_PKEY_set1_RSA 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_set1_RSA 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_sign.3 b/secure/lib/libcrypto/man/EVP_PKEY_sign.3
index efa1eb5e05bb..87344c54cf3a 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_sign.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_sign.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_sign 3"
-.TH EVP_PKEY_sign 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_sign 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_verify.3 b/secure/lib/libcrypto/man/EVP_PKEY_verify.3
index e3ea4872cc80..8eb5495eb391 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_verify.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_verify.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_verify 3"
-.TH EVP_PKEY_verify 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_verify 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_PKEY_verify_recover.3 b/secure/lib/libcrypto/man/EVP_PKEY_verify_recover.3
index b9601229432c..c8b8f3b13425 100644
--- a/secure/lib/libcrypto/man/EVP_PKEY_verify_recover.3
+++ b/secure/lib/libcrypto/man/EVP_PKEY_verify_recover.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_PKEY_verify_recover 3"
-.TH EVP_PKEY_verify_recover 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_PKEY_verify_recover 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_SealInit.3 b/secure/lib/libcrypto/man/EVP_SealInit.3
index 35a4f11c3c5d..f54157eb4d34 100644
--- a/secure/lib/libcrypto/man/EVP_SealInit.3
+++ b/secure/lib/libcrypto/man/EVP_SealInit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_SealInit 3"
-.TH EVP_SealInit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_SealInit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_SignInit.3 b/secure/lib/libcrypto/man/EVP_SignInit.3
index cffec40823e8..1cc2e6255425 100644
--- a/secure/lib/libcrypto/man/EVP_SignInit.3
+++ b/secure/lib/libcrypto/man/EVP_SignInit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_SignInit 3"
-.TH EVP_SignInit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_SignInit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/EVP_VerifyInit.3 b/secure/lib/libcrypto/man/EVP_VerifyInit.3
index 444ad45e17f7..4743cfac47da 100644
--- a/secure/lib/libcrypto/man/EVP_VerifyInit.3
+++ b/secure/lib/libcrypto/man/EVP_VerifyInit.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EVP_VerifyInit 3"
-.TH EVP_VerifyInit 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EVP_VerifyInit 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/OBJ_nid2obj.3 b/secure/lib/libcrypto/man/OBJ_nid2obj.3
index 9ca4f3fe0deb..e95f3dbfc71b 100644
--- a/secure/lib/libcrypto/man/OBJ_nid2obj.3
+++ b/secure/lib/libcrypto/man/OBJ_nid2obj.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OBJ_nid2obj 3"
-.TH OBJ_nid2obj 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OBJ_nid2obj 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -170,6 +170,12 @@ functions
 .IX Header "DESCRIPTION"
 The \s-1ASN1\s0 object utility functions process \s-1ASN1_OBJECT\s0 structures which are
 a representation of the \s-1ASN1 OBJECT IDENTIFIER \s0(\s-1OID\s0) type.
+For convenience, OIDs are usually represented in source code as numeric
+identifiers, or \fB\s-1NID\s0\fRs.  OpenSSL has an internal table of OIDs that
+are generated when the library is built, and their corresponding NIDs
+are available as defined constants.  For the functions below, application
+code should treat all returned values \*(-- OIDs, NIDs, or names \*(-- as
+constants.
 .PP
 \&\fIOBJ_nid2obj()\fR, \fIOBJ_nid2ln()\fR and \fIOBJ_nid2sn()\fR convert the \s-1NID \s0\fBn\fR to 
 an \s-1ASN1_OBJECT\s0 structure, its long name and its short name respectively,
@@ -233,6 +239,16 @@ Objects which are not in the table have the \s-1NID\s0 value NID_undef.
 Objects do not need to be in the internal tables to be processed,
 the functions \fIOBJ_txt2obj()\fR and \fIOBJ_obj2txt()\fR can process the numerical
 form of an \s-1OID.\s0
+.PP
+Some objects are used to represent algorithms which do not have a
+corresponding \s-1ASN.1 OBJECT IDENTIFIER\s0 encoding (for example no \s-1OID\s0 currently
+exists for a particular algorithm). As a result they \fBcannot\fR be encoded or
+decoded as part of \s-1ASN.1\s0 structures. Applications can determine if there
+is a corresponding \s-1OBJECT IDENTIFIER\s0 by checking \fIOBJ_length()\fR is not zero.
+.PP
+These functions cannot return \fBconst\fR because an \fB\s-1ASN1_OBJECT\s0\fR can
+represent both an internal, constant, \s-1OID\s0 and a dynamically-created one.
+The latter cannot be constant because it needs to be freed after use.
 .SH "EXAMPLES"
 .IX Header "EXAMPLES"
 Create an object for \fBcommonName\fR:
@@ -251,9 +267,10 @@ Check if an object is \fBcommonName\fR
 .PP
 Create a new \s-1NID\s0 and initialize an object from it:
 .PP
-.Vb 3
+.Vb 2
 \& int new_nid;
 \& ASN1_OBJECT *obj;
+\&
 \& new_nid = OBJ_create("1.2.3.4", "NewOID", "New Object Identifier");
 \&
 \& obj = OBJ_nid2obj(new_nid);
@@ -276,6 +293,8 @@ than enough to handle any \s-1OID\s0 encountered in practice.
 .IX Header "RETURN VALUES"
 \&\fIOBJ_nid2obj()\fR returns an \fB\s-1ASN1_OBJECT\s0\fR structure or \fB\s-1NULL\s0\fR is an
 error occurred.
+It returns a pointer to an internal table and does not
+allocate memory; \fIASN1_OBJECT_free()\fR will have no effect.
 .PP
 \&\fIOBJ_nid2ln()\fR and \fIOBJ_nid2sn()\fR returns a valid string or \fB\s-1NULL\s0\fR
 on error.
diff --git a/secure/lib/libcrypto/man/OPENSSL_Applink.3 b/secure/lib/libcrypto/man/OPENSSL_Applink.3
index 0a191db27fa8..550572775fe6 100644
--- a/secure/lib/libcrypto/man/OPENSSL_Applink.3
+++ b/secure/lib/libcrypto/man/OPENSSL_Applink.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OPENSSL_Applink 3"
-.TH OPENSSL_Applink 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OPENSSL_Applink 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/OPENSSL_VERSION_NUMBER.3 b/secure/lib/libcrypto/man/OPENSSL_VERSION_NUMBER.3
index bdc89b04e14b..49daff637d8d 100644
--- a/secure/lib/libcrypto/man/OPENSSL_VERSION_NUMBER.3
+++ b/secure/lib/libcrypto/man/OPENSSL_VERSION_NUMBER.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OPENSSL_VERSION_NUMBER 3"
-.TH OPENSSL_VERSION_NUMBER 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OPENSSL_VERSION_NUMBER 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/OPENSSL_config.3 b/secure/lib/libcrypto/man/OPENSSL_config.3
index 7b41a8e51525..a78fc4068344 100644
--- a/secure/lib/libcrypto/man/OPENSSL_config.3
+++ b/secure/lib/libcrypto/man/OPENSSL_config.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OPENSSL_config 3"
-.TH OPENSSL_config 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OPENSSL_config 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -145,15 +145,14 @@ OPENSSL_config, OPENSSL_no_config \- simple OpenSSL configuration functions
 .Vb 1
 \& #include <openssl/conf.h>
 \&
-\& void OPENSSL_config(const char *config_name);
+\& void OPENSSL_config(const char *appname);
 \& void OPENSSL_no_config(void);
 .Ve
 .SH "DESCRIPTION"
 .IX Header "DESCRIPTION"
-\&\fIOPENSSL_config()\fR configures OpenSSL using the standard \fBopenssl.cnf\fR
-configuration file name using \fBconfig_name\fR. If \fBconfig_name\fR is \s-1NULL\s0 then
-the file specified in the environment variable \fB\s-1OPENSSL_CONF\s0\fR will be used,
-and if that is not set then a system default location is used.
+\&\fIOPENSSL_config()\fR configures OpenSSL using the standard \fBopenssl.cnf\fR and
+reads from the application section \fBappname\fR. If \fBappname\fR is \s-1NULL\s0 then
+the default section, \fBopenssl_conf\fR, will be used.
 Errors are silently ignored.
 Multiple calls have no effect.
 .PP
diff --git a/secure/lib/libcrypto/man/OPENSSL_ia32cap.3 b/secure/lib/libcrypto/man/OPENSSL_ia32cap.3
index a5deed5c9505..5c1ea50971ae 100644
--- a/secure/lib/libcrypto/man/OPENSSL_ia32cap.3
+++ b/secure/lib/libcrypto/man/OPENSSL_ia32cap.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OPENSSL_ia32cap 3"
-.TH OPENSSL_ia32cap 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OPENSSL_ia32cap 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -143,7 +143,7 @@ OPENSSL_ia32cap, OPENSSL_ia32cap_loc \- the IA\-32 processor capabilities vector
 .SH "SYNOPSIS"
 .IX Header "SYNOPSIS"
 .Vb 2
-\& unsigned int *OPENSSL_ia32cap_loc(void);
+\& unsigned long *OPENSSL_ia32cap_loc(void);
 \& #define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])
 .Ve
 .SH "DESCRIPTION"
diff --git a/secure/lib/libcrypto/man/OPENSSL_instrument_bus.3 b/secure/lib/libcrypto/man/OPENSSL_instrument_bus.3
index 9ad8f59aaf59..2ac44f62d46f 100644
--- a/secure/lib/libcrypto/man/OPENSSL_instrument_bus.3
+++ b/secure/lib/libcrypto/man/OPENSSL_instrument_bus.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OPENSSL_instrument_bus 3"
-.TH OPENSSL_instrument_bus 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OPENSSL_instrument_bus 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/OPENSSL_load_builtin_modules.3 b/secure/lib/libcrypto/man/OPENSSL_load_builtin_modules.3
index 84cb598bde68..0e3f21569bd2 100644
--- a/secure/lib/libcrypto/man/OPENSSL_load_builtin_modules.3
+++ b/secure/lib/libcrypto/man/OPENSSL_load_builtin_modules.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OPENSSL_load_builtin_modules 3"
-.TH OPENSSL_load_builtin_modules 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OPENSSL_load_builtin_modules 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/OpenSSL_add_all_algorithms.3 b/secure/lib/libcrypto/man/OpenSSL_add_all_algorithms.3
index d9b48bfd997e..be5fc20aca4d 100644
--- a/secure/lib/libcrypto/man/OpenSSL_add_all_algorithms.3
+++ b/secure/lib/libcrypto/man/OpenSSL_add_all_algorithms.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OpenSSL_add_all_algorithms 3"
-.TH OpenSSL_add_all_algorithms 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OpenSSL_add_all_algorithms 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/PEM_write_bio_CMS_stream.3 b/secure/lib/libcrypto/man/PEM_write_bio_CMS_stream.3
index 7a2f43e3306d..026ae1285461 100644
--- a/secure/lib/libcrypto/man/PEM_write_bio_CMS_stream.3
+++ b/secure/lib/libcrypto/man/PEM_write_bio_CMS_stream.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PEM_write_bio_CMS_stream 3"
-.TH PEM_write_bio_CMS_stream 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PEM_write_bio_CMS_stream 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/PEM_write_bio_PKCS7_stream.3 b/secure/lib/libcrypto/man/PEM_write_bio_PKCS7_stream.3
index b0d3eaf46ff8..c45fbbc5964a 100644
--- a/secure/lib/libcrypto/man/PEM_write_bio_PKCS7_stream.3
+++ b/secure/lib/libcrypto/man/PEM_write_bio_PKCS7_stream.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PEM_write_bio_PKCS7_stream 3"
-.TH PEM_write_bio_PKCS7_stream 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PEM_write_bio_PKCS7_stream 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/PKCS12_create.3 b/secure/lib/libcrypto/man/PKCS12_create.3
index 3681346156ff..6bda8d2f427e 100644
--- a/secure/lib/libcrypto/man/PKCS12_create.3
+++ b/secure/lib/libcrypto/man/PKCS12_create.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS12_create 3"
-.TH PKCS12_create 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS12_create 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/PKCS12_parse.3 b/secure/lib/libcrypto/man/PKCS12_parse.3
index 29d12969c71c..34418fbf6655 100644
--- a/secure/lib/libcrypto/man/PKCS12_parse.3
+++ b/secure/lib/libcrypto/man/PKCS12_parse.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS12_parse 3"
-.TH PKCS12_parse 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS12_parse 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/PKCS7_decrypt.3 b/secure/lib/libcrypto/man/PKCS7_decrypt.3
index 26619d316cb1..418fe7477f9f 100644
--- a/secure/lib/libcrypto/man/PKCS7_decrypt.3
+++ b/secure/lib/libcrypto/man/PKCS7_decrypt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS7_decrypt 3"
-.TH PKCS7_decrypt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS7_decrypt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/PKCS7_encrypt.3 b/secure/lib/libcrypto/man/PKCS7_encrypt.3
index 82d3c48fcdf1..9bcd924468fe 100644
--- a/secure/lib/libcrypto/man/PKCS7_encrypt.3
+++ b/secure/lib/libcrypto/man/PKCS7_encrypt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS7_encrypt 3"
-.TH PKCS7_encrypt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS7_encrypt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/PKCS7_sign.3 b/secure/lib/libcrypto/man/PKCS7_sign.3
index 29324cbd6bf7..503f67cd6957 100644
--- a/secure/lib/libcrypto/man/PKCS7_sign.3
+++ b/secure/lib/libcrypto/man/PKCS7_sign.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS7_sign 3"
-.TH PKCS7_sign 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS7_sign 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/PKCS7_sign_add_signer.3 b/secure/lib/libcrypto/man/PKCS7_sign_add_signer.3
index 823069cbe013..34ee51675a7f 100644
--- a/secure/lib/libcrypto/man/PKCS7_sign_add_signer.3
+++ b/secure/lib/libcrypto/man/PKCS7_sign_add_signer.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS7_sign_add_signer 3"
-.TH PKCS7_sign_add_signer 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS7_sign_add_signer 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/PKCS7_verify.3 b/secure/lib/libcrypto/man/PKCS7_verify.3
index f5efeb3865fe..f9c4acf5fead 100644
--- a/secure/lib/libcrypto/man/PKCS7_verify.3
+++ b/secure/lib/libcrypto/man/PKCS7_verify.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS7_verify 3"
-.TH PKCS7_verify 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS7_verify 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RAND_add.3 b/secure/lib/libcrypto/man/RAND_add.3
index 17127bfd026b..9809e3fb80b8 100644
--- a/secure/lib/libcrypto/man/RAND_add.3
+++ b/secure/lib/libcrypto/man/RAND_add.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RAND_add 3"
-.TH RAND_add 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RAND_add 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RAND_bytes.3 b/secure/lib/libcrypto/man/RAND_bytes.3
index b8f9e1e4c0f9..a0678184b4e5 100644
--- a/secure/lib/libcrypto/man/RAND_bytes.3
+++ b/secure/lib/libcrypto/man/RAND_bytes.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RAND_bytes 3"
-.TH RAND_bytes 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RAND_bytes 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RAND_cleanup.3 b/secure/lib/libcrypto/man/RAND_cleanup.3
index f83bfcac59f2..dbfa18dfe1e4 100644
--- a/secure/lib/libcrypto/man/RAND_cleanup.3
+++ b/secure/lib/libcrypto/man/RAND_cleanup.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RAND_cleanup 3"
-.TH RAND_cleanup 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RAND_cleanup 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RAND_egd.3 b/secure/lib/libcrypto/man/RAND_egd.3
index 04975194c14e..0e7081645ca0 100644
--- a/secure/lib/libcrypto/man/RAND_egd.3
+++ b/secure/lib/libcrypto/man/RAND_egd.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RAND_egd 3"
-.TH RAND_egd 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RAND_egd 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RAND_load_file.3 b/secure/lib/libcrypto/man/RAND_load_file.3
index adb4b69cf65e..ce108194ceb7 100644
--- a/secure/lib/libcrypto/man/RAND_load_file.3
+++ b/secure/lib/libcrypto/man/RAND_load_file.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RAND_load_file 3"
-.TH RAND_load_file 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RAND_load_file 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RAND_set_rand_method.3 b/secure/lib/libcrypto/man/RAND_set_rand_method.3
index 1daaa7c595cc..b162736107f2 100644
--- a/secure/lib/libcrypto/man/RAND_set_rand_method.3
+++ b/secure/lib/libcrypto/man/RAND_set_rand_method.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RAND_set_rand_method 3"
-.TH RAND_set_rand_method 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RAND_set_rand_method 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_blinding_on.3 b/secure/lib/libcrypto/man/RSA_blinding_on.3
index e1cb8bce8f98..d2c20708355f 100644
--- a/secure/lib/libcrypto/man/RSA_blinding_on.3
+++ b/secure/lib/libcrypto/man/RSA_blinding_on.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_blinding_on 3"
-.TH RSA_blinding_on 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_blinding_on 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_check_key.3 b/secure/lib/libcrypto/man/RSA_check_key.3
index ceba228b7208..a0faa9c84230 100644
--- a/secure/lib/libcrypto/man/RSA_check_key.3
+++ b/secure/lib/libcrypto/man/RSA_check_key.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_check_key 3"
-.TH RSA_check_key 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_check_key 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_generate_key.3 b/secure/lib/libcrypto/man/RSA_generate_key.3
index 20ef7a7c958e..dc20a29f27f3 100644
--- a/secure/lib/libcrypto/man/RSA_generate_key.3
+++ b/secure/lib/libcrypto/man/RSA_generate_key.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_generate_key 3"
-.TH RSA_generate_key 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_generate_key 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_get_ex_new_index.3 b/secure/lib/libcrypto/man/RSA_get_ex_new_index.3
index e4b37d9b7e4f..a5be4f1920ba 100644
--- a/secure/lib/libcrypto/man/RSA_get_ex_new_index.3
+++ b/secure/lib/libcrypto/man/RSA_get_ex_new_index.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_get_ex_new_index 3"
-.TH RSA_get_ex_new_index 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_get_ex_new_index 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_new.3 b/secure/lib/libcrypto/man/RSA_new.3
index 69194eb217a8..ddbdcaf19775 100644
--- a/secure/lib/libcrypto/man/RSA_new.3
+++ b/secure/lib/libcrypto/man/RSA_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_new 3"
-.TH RSA_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_padding_add_PKCS1_type_1.3 b/secure/lib/libcrypto/man/RSA_padding_add_PKCS1_type_1.3
index 15eee1e900d2..62009693d325 100644
--- a/secure/lib/libcrypto/man/RSA_padding_add_PKCS1_type_1.3
+++ b/secure/lib/libcrypto/man/RSA_padding_add_PKCS1_type_1.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_padding_add_PKCS1_type_1 3"
-.TH RSA_padding_add_PKCS1_type_1 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_padding_add_PKCS1_type_1 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_print.3 b/secure/lib/libcrypto/man/RSA_print.3
index 42ef2e2d9bc7..90e7ec5353cb 100644
--- a/secure/lib/libcrypto/man/RSA_print.3
+++ b/secure/lib/libcrypto/man/RSA_print.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_print 3"
-.TH RSA_print 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_print 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_private_encrypt.3 b/secure/lib/libcrypto/man/RSA_private_encrypt.3
index b65208f1e5c2..95e1023411f2 100644
--- a/secure/lib/libcrypto/man/RSA_private_encrypt.3
+++ b/secure/lib/libcrypto/man/RSA_private_encrypt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_private_encrypt 3"
-.TH RSA_private_encrypt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_private_encrypt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_public_encrypt.3 b/secure/lib/libcrypto/man/RSA_public_encrypt.3
index 693be67e90be..c46869bf690e 100644
--- a/secure/lib/libcrypto/man/RSA_public_encrypt.3
+++ b/secure/lib/libcrypto/man/RSA_public_encrypt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_public_encrypt 3"
-.TH RSA_public_encrypt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_public_encrypt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_set_method.3 b/secure/lib/libcrypto/man/RSA_set_method.3
index 5fbf8ee6cb37..550218d133bc 100644
--- a/secure/lib/libcrypto/man/RSA_set_method.3
+++ b/secure/lib/libcrypto/man/RSA_set_method.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_set_method 3"
-.TH RSA_set_method 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_set_method 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_sign.3 b/secure/lib/libcrypto/man/RSA_sign.3
index 5db8c2948cf0..527ed8dfcd44 100644
--- a/secure/lib/libcrypto/man/RSA_sign.3
+++ b/secure/lib/libcrypto/man/RSA_sign.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_sign 3"
-.TH RSA_sign 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_sign 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_sign_ASN1_OCTET_STRING.3 b/secure/lib/libcrypto/man/RSA_sign_ASN1_OCTET_STRING.3
index 200b820a2c4c..a587ce0bd31a 100644
--- a/secure/lib/libcrypto/man/RSA_sign_ASN1_OCTET_STRING.3
+++ b/secure/lib/libcrypto/man/RSA_sign_ASN1_OCTET_STRING.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_sign_ASN1_OCTET_STRING 3"
-.TH RSA_sign_ASN1_OCTET_STRING 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_sign_ASN1_OCTET_STRING 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/RSA_size.3 b/secure/lib/libcrypto/man/RSA_size.3
index 70c9f15e7cd3..8598f6876f12 100644
--- a/secure/lib/libcrypto/man/RSA_size.3
+++ b/secure/lib/libcrypto/man/RSA_size.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA_size 3"
-.TH RSA_size 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA_size 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/SMIME_read_CMS.3 b/secure/lib/libcrypto/man/SMIME_read_CMS.3
index e14a3e516089..9a564620aa69 100644
--- a/secure/lib/libcrypto/man/SMIME_read_CMS.3
+++ b/secure/lib/libcrypto/man/SMIME_read_CMS.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SMIME_read_CMS 3"
-.TH SMIME_read_CMS 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SMIME_read_CMS 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/SMIME_read_PKCS7.3 b/secure/lib/libcrypto/man/SMIME_read_PKCS7.3
index 2b9f4d7bb448..229b20901595 100644
--- a/secure/lib/libcrypto/man/SMIME_read_PKCS7.3
+++ b/secure/lib/libcrypto/man/SMIME_read_PKCS7.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SMIME_read_PKCS7 3"
-.TH SMIME_read_PKCS7 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SMIME_read_PKCS7 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/SMIME_write_CMS.3 b/secure/lib/libcrypto/man/SMIME_write_CMS.3
index 259a8d039b7c..8c9b98176dd4 100644
--- a/secure/lib/libcrypto/man/SMIME_write_CMS.3
+++ b/secure/lib/libcrypto/man/SMIME_write_CMS.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SMIME_write_CMS 3"
-.TH SMIME_write_CMS 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SMIME_write_CMS 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/SMIME_write_PKCS7.3 b/secure/lib/libcrypto/man/SMIME_write_PKCS7.3
index 00be44d5484d..13ee6033945e 100644
--- a/secure/lib/libcrypto/man/SMIME_write_PKCS7.3
+++ b/secure/lib/libcrypto/man/SMIME_write_PKCS7.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SMIME_write_PKCS7 3"
-.TH SMIME_write_PKCS7 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SMIME_write_PKCS7 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_NAME_ENTRY_get_object.3 b/secure/lib/libcrypto/man/X509_NAME_ENTRY_get_object.3
index df27e84414ca..0486e812a01d 100644
--- a/secure/lib/libcrypto/man/X509_NAME_ENTRY_get_object.3
+++ b/secure/lib/libcrypto/man/X509_NAME_ENTRY_get_object.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_NAME_ENTRY_get_object 3"
-.TH X509_NAME_ENTRY_get_object 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_NAME_ENTRY_get_object 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_NAME_add_entry_by_txt.3 b/secure/lib/libcrypto/man/X509_NAME_add_entry_by_txt.3
index f0d260b3e806..1cdd302fa6e0 100644
--- a/secure/lib/libcrypto/man/X509_NAME_add_entry_by_txt.3
+++ b/secure/lib/libcrypto/man/X509_NAME_add_entry_by_txt.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_NAME_add_entry_by_txt 3"
-.TH X509_NAME_add_entry_by_txt 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_NAME_add_entry_by_txt 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_NAME_get_index_by_NID.3 b/secure/lib/libcrypto/man/X509_NAME_get_index_by_NID.3
index 187aa94dc5ca..3ac6c1d30efd 100644
--- a/secure/lib/libcrypto/man/X509_NAME_get_index_by_NID.3
+++ b/secure/lib/libcrypto/man/X509_NAME_get_index_by_NID.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_NAME_get_index_by_NID 3"
-.TH X509_NAME_get_index_by_NID 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_NAME_get_index_by_NID 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_NAME_print_ex.3 b/secure/lib/libcrypto/man/X509_NAME_print_ex.3
index bd90bb80b9b6..e69d87874277 100644
--- a/secure/lib/libcrypto/man/X509_NAME_print_ex.3
+++ b/secure/lib/libcrypto/man/X509_NAME_print_ex.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_NAME_print_ex 3"
-.TH X509_NAME_print_ex 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_NAME_print_ex 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_STORE_CTX_get_error.3 b/secure/lib/libcrypto/man/X509_STORE_CTX_get_error.3
index 3ae94d665029..2bed2495b92d 100644
--- a/secure/lib/libcrypto/man/X509_STORE_CTX_get_error.3
+++ b/secure/lib/libcrypto/man/X509_STORE_CTX_get_error.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_STORE_CTX_get_error 3"
-.TH X509_STORE_CTX_get_error 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_STORE_CTX_get_error 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_STORE_CTX_get_ex_new_index.3 b/secure/lib/libcrypto/man/X509_STORE_CTX_get_ex_new_index.3
index 72a14a5104b5..c8c883124bb0 100644
--- a/secure/lib/libcrypto/man/X509_STORE_CTX_get_ex_new_index.3
+++ b/secure/lib/libcrypto/man/X509_STORE_CTX_get_ex_new_index.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_STORE_CTX_get_ex_new_index 3"
-.TH X509_STORE_CTX_get_ex_new_index 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_STORE_CTX_get_ex_new_index 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_STORE_CTX_new.3 b/secure/lib/libcrypto/man/X509_STORE_CTX_new.3
index 33cf8754cf52..bdb1bd27e406 100644
--- a/secure/lib/libcrypto/man/X509_STORE_CTX_new.3
+++ b/secure/lib/libcrypto/man/X509_STORE_CTX_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_STORE_CTX_new 3"
-.TH X509_STORE_CTX_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_STORE_CTX_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_STORE_CTX_set_verify_cb.3 b/secure/lib/libcrypto/man/X509_STORE_CTX_set_verify_cb.3
index 5ce634844d06..1064755d92fb 100644
--- a/secure/lib/libcrypto/man/X509_STORE_CTX_set_verify_cb.3
+++ b/secure/lib/libcrypto/man/X509_STORE_CTX_set_verify_cb.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_STORE_CTX_set_verify_cb 3"
-.TH X509_STORE_CTX_set_verify_cb 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_STORE_CTX_set_verify_cb 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_STORE_set_verify_cb_func.3 b/secure/lib/libcrypto/man/X509_STORE_set_verify_cb_func.3
index 695bd65c99a8..8ad600e69955 100644
--- a/secure/lib/libcrypto/man/X509_STORE_set_verify_cb_func.3
+++ b/secure/lib/libcrypto/man/X509_STORE_set_verify_cb_func.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_STORE_set_verify_cb_func 3"
-.TH X509_STORE_set_verify_cb_func 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_STORE_set_verify_cb_func 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_VERIFY_PARAM_set_flags.3 b/secure/lib/libcrypto/man/X509_VERIFY_PARAM_set_flags.3
index 9e9ee24e81d9..cb0c50338a46 100644
--- a/secure/lib/libcrypto/man/X509_VERIFY_PARAM_set_flags.3
+++ b/secure/lib/libcrypto/man/X509_VERIFY_PARAM_set_flags.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_VERIFY_PARAM_set_flags 3"
-.TH X509_VERIFY_PARAM_set_flags 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_VERIFY_PARAM_set_flags 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_check_host.3 b/secure/lib/libcrypto/man/X509_check_host.3
index aa0941f8918d..afb35c5ccb1a 100644
--- a/secure/lib/libcrypto/man/X509_check_host.3
+++ b/secure/lib/libcrypto/man/X509_check_host.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_check_host 3"
-.TH X509_check_host 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_check_host 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_new.3 b/secure/lib/libcrypto/man/X509_new.3
index f934540adcb4..b829e0941cc9 100644
--- a/secure/lib/libcrypto/man/X509_new.3
+++ b/secure/lib/libcrypto/man/X509_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_new 3"
-.TH X509_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/X509_verify_cert.3 b/secure/lib/libcrypto/man/X509_verify_cert.3
index a0205faab395..864e1ab1c8d2 100644
--- a/secure/lib/libcrypto/man/X509_verify_cert.3
+++ b/secure/lib/libcrypto/man/X509_verify_cert.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509_verify_cert 3"
-.TH X509_verify_cert 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509_verify_cert 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -166,12 +166,13 @@ Applications rarely call this function directly but it is used by
 OpenSSL internally for certificate validation, in both the S/MIME and
 \&\s-1SSL/TLS\s0 code.
 .PP
-The negative return value from \fIX509_verify_cert()\fR can only occur if no
-certificate is set in \fBctx\fR (due to a programming error); if \fIX509_verify_cert()\fR
-twice without reinitialising \fBctx\fR in between; or if a retry
-operation is requested during internal lookups (which never happens with
-standard lookup methods). It is however recommended that application check
-for <= 0 return value on error.
+A negative return value from \fIX509_verify_cert()\fR can occur if it is invoked
+incorrectly, such as with no certificate set in \fBctx\fR, or when it is called
+twice in succession without reinitialising \fBctx\fR for the second call.
+A negative return value can also happen due to internal resource problems or if
+a retry operation is requested during internal lookups (which never happens
+with standard lookup methods).
+Applications must check for <= 0 return value on error.
 .SH "BUGS"
 .IX Header "BUGS"
 This function uses the header \fBx509.h\fR as opposed to most chain verification
diff --git a/secure/lib/libcrypto/man/bio.3 b/secure/lib/libcrypto/man/bio.3
index 241d75f5157f..2074cacdade2 100644
--- a/secure/lib/libcrypto/man/bio.3
+++ b/secure/lib/libcrypto/man/bio.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "bio 3"
-.TH bio 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH bio 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/blowfish.3 b/secure/lib/libcrypto/man/blowfish.3
index 9f062b17971a..aa5b8f7ae6a7 100644
--- a/secure/lib/libcrypto/man/blowfish.3
+++ b/secure/lib/libcrypto/man/blowfish.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "blowfish 3"
-.TH blowfish 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH blowfish 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/bn.3 b/secure/lib/libcrypto/man/bn.3
index 23d4d0f09ac6..1bc3380d8699 100644
--- a/secure/lib/libcrypto/man/bn.3
+++ b/secure/lib/libcrypto/man/bn.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "bn 3"
-.TH bn 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH bn 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/bn_internal.3 b/secure/lib/libcrypto/man/bn_internal.3
index d369997ad832..b6bfc91e5377 100644
--- a/secure/lib/libcrypto/man/bn_internal.3
+++ b/secure/lib/libcrypto/man/bn_internal.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "bn_internal 3"
-.TH bn_internal 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH bn_internal 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/buffer.3 b/secure/lib/libcrypto/man/buffer.3
index f5000c4ea0c7..499ca394deb9 100644
--- a/secure/lib/libcrypto/man/buffer.3
+++ b/secure/lib/libcrypto/man/buffer.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "buffer 3"
-.TH buffer 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH buffer 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/crypto.3 b/secure/lib/libcrypto/man/crypto.3
index e20144c42165..0be252c80365 100644
--- a/secure/lib/libcrypto/man/crypto.3
+++ b/secure/lib/libcrypto/man/crypto.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "crypto 3"
-.TH crypto 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH crypto 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_ASN1_OBJECT.3 b/secure/lib/libcrypto/man/d2i_ASN1_OBJECT.3
index 231ef61abce6..d9f62149dcde 100644
--- a/secure/lib/libcrypto/man/d2i_ASN1_OBJECT.3
+++ b/secure/lib/libcrypto/man/d2i_ASN1_OBJECT.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_ASN1_OBJECT 3"
-.TH d2i_ASN1_OBJECT 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_ASN1_OBJECT 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_CMS_ContentInfo.3 b/secure/lib/libcrypto/man/d2i_CMS_ContentInfo.3
index deb4f144506a..2123e2f11c4f 100644
--- a/secure/lib/libcrypto/man/d2i_CMS_ContentInfo.3
+++ b/secure/lib/libcrypto/man/d2i_CMS_ContentInfo.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_CMS_ContentInfo 3"
-.TH d2i_CMS_ContentInfo 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_CMS_ContentInfo 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_DHparams.3 b/secure/lib/libcrypto/man/d2i_DHparams.3
index 97df19358519..e4152d0faf35 100644
--- a/secure/lib/libcrypto/man/d2i_DHparams.3
+++ b/secure/lib/libcrypto/man/d2i_DHparams.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_DHparams 3"
-.TH d2i_DHparams 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_DHparams 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_DSAPublicKey.3 b/secure/lib/libcrypto/man/d2i_DSAPublicKey.3
index 791bf3eb3383..753506f635cc 100644
--- a/secure/lib/libcrypto/man/d2i_DSAPublicKey.3
+++ b/secure/lib/libcrypto/man/d2i_DSAPublicKey.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_DSAPublicKey 3"
-.TH d2i_DSAPublicKey 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_DSAPublicKey 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_ECPKParameters.3 b/secure/lib/libcrypto/man/d2i_ECPKParameters.3
index e86d51f23fb4..6beead1f41f2 100644
--- a/secure/lib/libcrypto/man/d2i_ECPKParameters.3
+++ b/secure/lib/libcrypto/man/d2i_ECPKParameters.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_ECPKParameters 3"
-.TH d2i_ECPKParameters 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_ECPKParameters 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_ECPrivateKey.3 b/secure/lib/libcrypto/man/d2i_ECPrivateKey.3
index a9613bbd8d3c..a275fe764219 100644
--- a/secure/lib/libcrypto/man/d2i_ECPrivateKey.3
+++ b/secure/lib/libcrypto/man/d2i_ECPrivateKey.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_ECPrivateKey 3"
-.TH d2i_ECPrivateKey 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_ECPrivateKey 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_PKCS8PrivateKey.3 b/secure/lib/libcrypto/man/d2i_PKCS8PrivateKey.3
index 838df0555ef5..71891adbe907 100644
--- a/secure/lib/libcrypto/man/d2i_PKCS8PrivateKey.3
+++ b/secure/lib/libcrypto/man/d2i_PKCS8PrivateKey.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_PKCS8PrivateKey 3"
-.TH d2i_PKCS8PrivateKey 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_PKCS8PrivateKey 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_PrivateKey.3 b/secure/lib/libcrypto/man/d2i_PrivateKey.3
new file mode 100644
index 000000000000..80423add15d8
--- /dev/null
+++ b/secure/lib/libcrypto/man/d2i_PrivateKey.3
@@ -0,0 +1,191 @@
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
+.\"
+.\" Standard preamble:
+.\" ========================================================================
+.de Sp \" Vertical space (when we can't use .PP)
+.if t .sp .5v
+.if n .sp
+..
+.de Vb \" Begin verbatim text
+.ft CW
+.nf
+.ne \\$1
+..
+.de Ve \" End verbatim text
+.ft R
+.fi
+..
+.\" Set up some character translations and predefined strings.  \*(-- will
+.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
+.\" double quote, and \*(R" will give a right double quote.  \*(C+ will
+.\" give a nicer C++.  Capital omega is used to do unbreakable dashes and
+.\" therefore won't be available.  \*(C` and \*(C' expand to `' in nroff,
+.\" nothing in troff, for use with C<>.
+.tr \(*W-
+.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
+.ie n \{\
+.    ds -- \(*W-
+.    ds PI pi
+.    if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
+.    if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\"  diablo 12 pitch
+.    ds L" ""
+.    ds R" ""
+.    ds C` ""
+.    ds C' ""
+'br\}
+.el\{\
+.    ds -- \|\(em\|
+.    ds PI \(*p
+.    ds L" ``
+.    ds R" ''
+.    ds C`
+.    ds C'
+'br\}
+.\"
+.\" Escape single quotes in literal strings from groff's Unicode transform.
+.ie \n(.g .ds Aq \(aq
+.el       .ds Aq '
+.\"
+.\" If the F register is turned on, we'll generate index entries on stderr for
+.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
+.\" entries marked with X<> in POD.  Of course, you'll have to process the
+.\" output yourself in some meaningful fashion.
+.\"
+.\" Avoid warning from groff about undefined register 'F'.
+.de IX
+..
+.nr rF 0
+.if \n(.g .if rF .nr rF 1
+.if (\n(rF:(\n(.g==0)) \{
+.    if \nF \{
+.        de IX
+.        tm Index:\\$1\t\\n%\t"\\$2"
+..
+.        if !\nF==2 \{
+.            nr % 0
+.            nr F 2
+.        \}
+.    \}
+.\}
+.rr rF
+.\"
+.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
+.\" Fear.  Run.  Save yourself.  No user-serviceable parts.
+.    \" fudge factors for nroff and troff
+.if n \{\
+.    ds #H 0
+.    ds #V .8m
+.    ds #F .3m
+.    ds #[ \f1
+.    ds #] \fP
+.\}
+.if t \{\
+.    ds #H ((1u-(\\\\n(.fu%2u))*.13m)
+.    ds #V .6m
+.    ds #F 0
+.    ds #[ \&
+.    ds #] \&
+.\}
+.    \" simple accents for nroff and troff
+.if n \{\
+.    ds ' \&
+.    ds ` \&
+.    ds ^ \&
+.    ds , \&
+.    ds ~ ~
+.    ds /
+.\}
+.if t \{\
+.    ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
+.    ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
+.    ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
+.    ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
+.    ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
+.    ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
+.\}
+.    \" troff and (daisy-wheel) nroff accents
+.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
+.ds 8 \h'\*(#H'\(*b\h'-\*(#H'
+.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#]
+.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H'
+.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u'
+.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#]
+.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#]
+.ds ae a\h'-(\w'a'u*4/10)'e
+.ds Ae A\h'-(\w'A'u*4/10)'E
+.    \" corrections for vroff
+.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u'
+.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u'
+.    \" for low resolution devices (crt and lpr)
+.if \n(.H>23 .if \n(.V>19 \
+\{\
+.    ds : e
+.    ds 8 ss
+.    ds o a
+.    ds d- d\h'-1'\(ga
+.    ds D- D\h'-1'\(hy
+.    ds th \o'bp'
+.    ds Th \o'LP'
+.    ds ae ae
+.    ds Ae AE
+.\}
+.rm #[ #] #H #V #F C
+.\" ========================================================================
+.\"
+.IX Title "d2i_PrivateKey 3"
+.TH d2i_PrivateKey 3 "2016-09-22" "1.0.2i" "OpenSSL"
+.\" For nroff, turn off justification.  Always turn off hyphenation; it makes
+.\" way too many mistakes in technical documents.
+.if n .ad l
+.nh
+.SH "NAME"
+d2i_Private_key, d2i_AutoPrivateKey, i2d_PrivateKey \- decode and encode
+functions for reading and saving EVP_PKEY structures.
+.SH "SYNOPSIS"
+.IX Header "SYNOPSIS"
+.Vb 1
+\& #include <openssl/evp.h>
+\&
+\& EVP_PKEY *d2i_PrivateKey(int type, EVP_PKEY **a, const unsigned char **pp,
+\&                          long length);
+\& EVP_PKEY *d2i_AutoPrivateKey(EVP_PKEY **a, const unsigned char **pp,
+\&                              long length);
+\& int i2d_PrivateKey(EVP_PKEY *a, unsigned char **pp);
+.Ve
+.SH "DESCRIPTION"
+.IX Header "DESCRIPTION"
+\&\fId2i_PrivateKey()\fR decodes a private key using algorithm \fBtype\fR. It attempts to
+use any key specific format or PKCS#8 unencrypted PrivateKeyInfo format. The
+\&\fBtype\fR parameter should be a public key algorithm constant such as
+\&\fB\s-1EVP_PKEY_RSA\s0\fR. An error occurs if the decoded key does not match \fBtype\fR.
+.PP
+\&\fId2i_AutoPrivateKey()\fR is similar to \fId2i_PrivateKey()\fR except it attempts to
+automatically detect the private key format.
+.PP
+\&\fIi2d_PrivateKey()\fR encodes \fBkey\fR. It uses a key specific format or, if none is
+defined for that key type, PKCS#8 unencrypted PrivateKeyInfo format.
+.PP
+These functions are similar to the \fId2i_X509()\fR functions, and you should refer to
+that page for a detailed description (see \fId2i_X509\fR\|(3)).
+.SH "NOTES"
+.IX Header "NOTES"
+All these functions use \s-1DER\s0 format and unencrypted keys. Applications wishing
+to encrypt or decrypt private keys should use other functions such as
+\&\fId2i_PKC8PrivateKey()\fR instead.
+.PP
+If the \fB*a\fR is not \s-1NULL\s0 when calling \fId2i_PrivateKey()\fR or \fId2i_AutoPrivateKey()\fR
+(i.e. an existing structure is being reused) and the key format is PKCS#8
+then \fB*a\fR will be freed and replaced on a successful call.
+.SH "RETURN VALUES"
+.IX Header "RETURN VALUES"
+\&\fId2i_PrivateKey()\fR and \fId2i_AutoPrivateKey()\fR return a valid \fB\s-1EVP_KEY\s0\fR structure
+or \fB\s-1NULL\s0\fR if an error occurs. The error code can be obtained by calling
+\&\fIERR_get_error\fR\|(3).
+.PP
+\&\fIi2d_PrivateKey()\fR returns the number of bytes successfully encoded or a
+negative value if an error occurs. The error code can be obtained by calling
+\&\fIERR_get_error\fR\|(3).
+.SH "SEE ALSO"
+.IX Header "SEE ALSO"
+\&\fIcrypto\fR\|(3),
+\&\fId2i_PKCS8PrivateKey\fR\|(3)
diff --git a/secure/lib/libcrypto/man/d2i_RSAPublicKey.3 b/secure/lib/libcrypto/man/d2i_RSAPublicKey.3
index 236648367891..b293ac86509f 100644
--- a/secure/lib/libcrypto/man/d2i_RSAPublicKey.3
+++ b/secure/lib/libcrypto/man/d2i_RSAPublicKey.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_RSAPublicKey 3"
-.TH d2i_RSAPublicKey 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_RSAPublicKey 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_X509.3 b/secure/lib/libcrypto/man/d2i_X509.3
index 1bd2fcee2726..ba77425c900d 100644
--- a/secure/lib/libcrypto/man/d2i_X509.3
+++ b/secure/lib/libcrypto/man/d2i_X509.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_X509 3"
-.TH d2i_X509 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_X509 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -146,8 +146,10 @@ i2d_X509_fp \- X509 encode and decode functions
 .Vb 1
 \& #include <openssl/x509.h>
 \&
-\& X509 *d2i_X509(X509 **px, const unsigned char **in, int len);
+\& X509 *d2i_X509(X509 **px, const unsigned char **in, long len);
+\& X509 *d2i_X509_AUX(X509 **px, const unsigned char **in, long len);
 \& int i2d_X509(X509 *x, unsigned char **out);
+\& int i2d_X509_AUX(X509 *x, unsigned char **out);
 \&
 \& X509 *d2i_X509_bio(BIO *bp, X509 **x);
 \& X509 *d2i_X509_fp(FILE *fp, X509 **x);
@@ -174,6 +176,11 @@ below, and the discussion in the \s-1RETURN VALUES\s0 section).
 If the call is successful \fB*in\fR is incremented to the byte following the
 parsed data.
 .PP
+\&\fId2i_X509_AUX()\fR is similar to \fId2i_X509()\fR but the input is expected to consist of
+an X509 certificate followed by auxiliary trust information.
+This is used by the \s-1PEM\s0 routines to read \*(L"\s-1TRUSTED CERTIFICATE\*(R"\s0 objects.
+This function should not be called on untrusted input.
+.PP
 \&\fIi2d_X509()\fR encodes the structure pointed to by \fBx\fR into \s-1DER\s0 format.
 If \fBout\fR is not \fB\s-1NULL\s0\fR is writes the \s-1DER\s0 encoded data to the buffer
 at \fB*out\fR, and increments it to point after the data just written.
@@ -185,6 +192,11 @@ allocated for a buffer and the encoded data written to it. In this
 case \fB*out\fR is not incremented and it points to the start of the
 data just written.
 .PP
+\&\fIi2d_X509_AUX()\fR is similar to \fIi2d_X509()\fR, but the encoded output contains both
+the certificate and any auxiliary trust information.
+This is used by the \s-1PEM\s0 routines to write \*(L"\s-1TRUSTED CERTIFICATE\*(R"\s0 objects.
+Note, this is a non-standard OpenSSL-specific data format.
+.PP
 \&\fId2i_X509_bio()\fR is similar to \fId2i_X509()\fR except it attempts
 to parse data from \s-1BIO \s0\fBbp\fR.
 .PP
diff --git a/secure/lib/libcrypto/man/d2i_X509_ALGOR.3 b/secure/lib/libcrypto/man/d2i_X509_ALGOR.3
index 1065a0b1f222..f7c99f31fdf5 100644
--- a/secure/lib/libcrypto/man/d2i_X509_ALGOR.3
+++ b/secure/lib/libcrypto/man/d2i_X509_ALGOR.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_X509_ALGOR 3"
-.TH d2i_X509_ALGOR 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_X509_ALGOR 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_X509_CRL.3 b/secure/lib/libcrypto/man/d2i_X509_CRL.3
index bb0c4c23b071..82a5fcab9603 100644
--- a/secure/lib/libcrypto/man/d2i_X509_CRL.3
+++ b/secure/lib/libcrypto/man/d2i_X509_CRL.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_X509_CRL 3"
-.TH d2i_X509_CRL 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_X509_CRL 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_X509_NAME.3 b/secure/lib/libcrypto/man/d2i_X509_NAME.3
index c1679b4fa7a5..89a08d428818 100644
--- a/secure/lib/libcrypto/man/d2i_X509_NAME.3
+++ b/secure/lib/libcrypto/man/d2i_X509_NAME.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_X509_NAME 3"
-.TH d2i_X509_NAME 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_X509_NAME 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_X509_REQ.3 b/secure/lib/libcrypto/man/d2i_X509_REQ.3
index 2541ae61f69e..18172546c685 100644
--- a/secure/lib/libcrypto/man/d2i_X509_REQ.3
+++ b/secure/lib/libcrypto/man/d2i_X509_REQ.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_X509_REQ 3"
-.TH d2i_X509_REQ 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_X509_REQ 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/d2i_X509_SIG.3 b/secure/lib/libcrypto/man/d2i_X509_SIG.3
index 5d9bdeedf2f5..72ab9dbbdde9 100644
--- a/secure/lib/libcrypto/man/d2i_X509_SIG.3
+++ b/secure/lib/libcrypto/man/d2i_X509_SIG.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_X509_SIG 3"
-.TH d2i_X509_SIG 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_X509_SIG 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/des.3 b/secure/lib/libcrypto/man/des.3
index a71801743dc6..757fb5e12652 100644
--- a/secure/lib/libcrypto/man/des.3
+++ b/secure/lib/libcrypto/man/des.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "des 3"
-.TH des 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH des 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/dh.3 b/secure/lib/libcrypto/man/dh.3
index a8a674aa2881..03b6fc547441 100644
--- a/secure/lib/libcrypto/man/dh.3
+++ b/secure/lib/libcrypto/man/dh.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "dh 3"
-.TH dh 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH dh 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/dsa.3 b/secure/lib/libcrypto/man/dsa.3
index 1ed0fda69fd2..49d536f79b2a 100644
--- a/secure/lib/libcrypto/man/dsa.3
+++ b/secure/lib/libcrypto/man/dsa.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "dsa 3"
-.TH dsa 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH dsa 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ec.3 b/secure/lib/libcrypto/man/ec.3
index dde29273c0e6..a6e0acda9948 100644
--- a/secure/lib/libcrypto/man/ec.3
+++ b/secure/lib/libcrypto/man/ec.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ec 3"
-.TH ec 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ec 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ecdsa.3 b/secure/lib/libcrypto/man/ecdsa.3
index 6cd945d7c355..95b3c55085a7 100644
--- a/secure/lib/libcrypto/man/ecdsa.3
+++ b/secure/lib/libcrypto/man/ecdsa.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ecdsa 3"
-.TH ecdsa 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ecdsa 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/engine.3 b/secure/lib/libcrypto/man/engine.3
index 55ca22948a50..50d2e8a439f8 100644
--- a/secure/lib/libcrypto/man/engine.3
+++ b/secure/lib/libcrypto/man/engine.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "engine 3"
-.TH engine 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH engine 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/err.3 b/secure/lib/libcrypto/man/err.3
index 2670c587148b..a4b13c65b6b2 100644
--- a/secure/lib/libcrypto/man/err.3
+++ b/secure/lib/libcrypto/man/err.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "err 3"
-.TH err 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH err 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/evp.3 b/secure/lib/libcrypto/man/evp.3
index f9d14ba8ca2b..327c97065f6c 100644
--- a/secure/lib/libcrypto/man/evp.3
+++ b/secure/lib/libcrypto/man/evp.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "evp 3"
-.TH evp 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH evp 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/hmac.3 b/secure/lib/libcrypto/man/hmac.3
index 85e1af83702f..cd71e7db0724 100644
--- a/secure/lib/libcrypto/man/hmac.3
+++ b/secure/lib/libcrypto/man/hmac.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "hmac 3"
-.TH hmac 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH hmac 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -197,13 +197,17 @@ function \fBevp_md\fR and the key \fBkey\fR which is \fBkey_len\fR bytes
 long. It is deprecated and only included for backward compatibility
 with OpenSSL 0.9.6b.
 .PP
-\&\fIHMAC_Init_ex()\fR initializes or reuses a \fB\s-1HMAC_CTX\s0\fR structure to use
-the function \fBevp_md\fR and key \fBkey\fR. Either can be \s-1NULL,\s0 in which
-case the existing one will be reused. \fIHMAC_CTX_init()\fR must have been
-called before the first use of an \fB\s-1HMAC_CTX\s0\fR in this
-function. \fBN.B. \f(BIHMAC_Init()\fB had this undocumented behaviour in
-previous versions of OpenSSL \- failure to switch to \f(BIHMAC_Init_ex()\fB in
-programs that expect it will cause them to stop working\fR.
+\&\fIHMAC_Init_ex()\fR initializes or reuses a \fB\s-1HMAC_CTX\s0\fR structure to use the hash
+function \fBevp_md\fR and key \fBkey\fR. If both are \s-1NULL \s0(or \fBevp_md\fR is the same
+as the previous digest used by \fBctx\fR and \fBkey\fR is \s-1NULL\s0) the existing key is
+reused. \fBctx\fR must have been created with \fIHMAC_CTX_new()\fR before the first use
+of an \fB\s-1HMAC_CTX\s0\fR in this function. \fBN.B. \f(BIHMAC_Init()\fB had this undocumented
+behaviour in previous versions of OpenSSL \- failure to switch to \f(BIHMAC_Init_ex()\fB
+in programs that expect it will cause them to stop working\fR.
+.PP
+\&\fB\s-1NB:\s0 if \f(BIHMAC_Init_ex()\fB is called with \fBkey\fB \s-1NULL\s0 and \fBevp_md\fB is not the
+same as the previous digest used by \fBctx\fB then an error is returned
+because reuse of an existing key with a different digest is not supported.\fR
 .PP
 \&\fIHMAC_Update()\fR can be called repeatedly with chunks of the message to
 be authenticated (\fBlen\fR bytes at \fBdata\fR).
diff --git a/secure/lib/libcrypto/man/i2d_CMS_bio_stream.3 b/secure/lib/libcrypto/man/i2d_CMS_bio_stream.3
index ac071b37f9da..04c065a1a607 100644
--- a/secure/lib/libcrypto/man/i2d_CMS_bio_stream.3
+++ b/secure/lib/libcrypto/man/i2d_CMS_bio_stream.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "i2d_CMS_bio_stream 3"
-.TH i2d_CMS_bio_stream 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH i2d_CMS_bio_stream 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/i2d_PKCS7_bio_stream.3 b/secure/lib/libcrypto/man/i2d_PKCS7_bio_stream.3
index c816811c5203..2503258e0fec 100644
--- a/secure/lib/libcrypto/man/i2d_PKCS7_bio_stream.3
+++ b/secure/lib/libcrypto/man/i2d_PKCS7_bio_stream.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "i2d_PKCS7_bio_stream 3"
-.TH i2d_PKCS7_bio_stream 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH i2d_PKCS7_bio_stream 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/lh_stats.3 b/secure/lib/libcrypto/man/lh_stats.3
index 95087a1b5d49..444394efb9e6 100644
--- a/secure/lib/libcrypto/man/lh_stats.3
+++ b/secure/lib/libcrypto/man/lh_stats.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "lh_stats 3"
-.TH lh_stats 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH lh_stats 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/lhash.3 b/secure/lib/libcrypto/man/lhash.3
index ce5d143e2cd1..06d1237fc4ef 100644
--- a/secure/lib/libcrypto/man/lhash.3
+++ b/secure/lib/libcrypto/man/lhash.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "lhash 3"
-.TH lhash 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH lhash 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/md5.3 b/secure/lib/libcrypto/man/md5.3
index e4154bb5817a..bb9ff53c419b 100644
--- a/secure/lib/libcrypto/man/md5.3
+++ b/secure/lib/libcrypto/man/md5.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "md5 3"
-.TH md5 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH md5 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/mdc2.3 b/secure/lib/libcrypto/man/mdc2.3
index 044c4a284289..216c60cfc772 100644
--- a/secure/lib/libcrypto/man/mdc2.3
+++ b/secure/lib/libcrypto/man/mdc2.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "mdc2 3"
-.TH mdc2 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH mdc2 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/pem.3 b/secure/lib/libcrypto/man/pem.3
index ac25de1fef76..48dbf22173f2 100644
--- a/secure/lib/libcrypto/man/pem.3
+++ b/secure/lib/libcrypto/man/pem.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "pem 3"
-.TH pem 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH pem 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/rand.3 b/secure/lib/libcrypto/man/rand.3
index e9d985ac4490..2d741ef836c0 100644
--- a/secure/lib/libcrypto/man/rand.3
+++ b/secure/lib/libcrypto/man/rand.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "rand 3"
-.TH rand 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH rand 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -151,7 +151,7 @@ rand \- pseudo\-random number generator
 \& int  RAND_pseudo_bytes(unsigned char *buf, int num);
 \&
 \& void RAND_seed(const void *buf, int num);
-\& void RAND_add(const void *buf, int num, int entropy);
+\& void RAND_add(const void *buf, int num, double entropy);
 \& int  RAND_status(void);
 \&
 \& int  RAND_load_file(const char *file, long max_bytes);
diff --git a/secure/lib/libcrypto/man/rc4.3 b/secure/lib/libcrypto/man/rc4.3
index a74e522a7b3f..ee9f91512f62 100644
--- a/secure/lib/libcrypto/man/rc4.3
+++ b/secure/lib/libcrypto/man/rc4.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "rc4 3"
-.TH rc4 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH rc4 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ripemd.3 b/secure/lib/libcrypto/man/ripemd.3
index 59b32f0c9bb4..112c9fed031d 100644
--- a/secure/lib/libcrypto/man/ripemd.3
+++ b/secure/lib/libcrypto/man/ripemd.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ripemd 3"
-.TH ripemd 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ripemd 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/rsa.3 b/secure/lib/libcrypto/man/rsa.3
index 4d2a63f54fa3..276f5535e246 100644
--- a/secure/lib/libcrypto/man/rsa.3
+++ b/secure/lib/libcrypto/man/rsa.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "rsa 3"
-.TH rsa 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH rsa 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/sha.3 b/secure/lib/libcrypto/man/sha.3
index b793f02df405..d4f1a5eb6ffc 100644
--- a/secure/lib/libcrypto/man/sha.3
+++ b/secure/lib/libcrypto/man/sha.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "sha 3"
-.TH sha 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH sha 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/threads.3 b/secure/lib/libcrypto/man/threads.3
index 15f3a5290596..75e2b75e1509 100644
--- a/secure/lib/libcrypto/man/threads.3
+++ b/secure/lib/libcrypto/man/threads.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "threads 3"
-.TH threads 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH threads 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/ui.3 b/secure/lib/libcrypto/man/ui.3
index 0f918cd49242..b19e28e4f22a 100644
--- a/secure/lib/libcrypto/man/ui.3
+++ b/secure/lib/libcrypto/man/ui.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ui 3"
-.TH ui 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ui 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -246,12 +246,12 @@ that's connected to it, like duplicated input strings, results and others.
 .PP
 \&\fIUI_add_input_string()\fR and \fIUI_add_verify_string()\fR add a prompt to the \s-1UI,\s0
 as well as flags and a result buffer and the desired minimum and maximum
-sizes of the result.  The given information is used to prompt for
-information, for example a password, and to verify a password (i.e. having
-the user enter it twice and check that the same string was entered twice).
-\&\fIUI_add_verify_string()\fR takes and extra argument that should be a pointer
-to the result buffer of the input string that it's supposed to verify, or
-verification will fail.
+sizes of the result, not counting the final \s-1NUL\s0 character.  The given
+information is used to prompt for information, for example a password,
+and to verify a password (i.e. having the user enter it twice and check
+that the same string was entered twice).  \fIUI_add_verify_string()\fR takes
+and extra argument that should be a pointer to the result buffer of the
+input string that it's supposed to verify, or verification will fail.
 .PP
 \&\fIUI_add_input_boolean()\fR adds a prompt to the \s-1UI\s0 that's supposed to be answered
 in a boolean way, with a single character for yes and a different character
diff --git a/secure/lib/libcrypto/man/ui_compat.3 b/secure/lib/libcrypto/man/ui_compat.3
index 4889884e8fda..88879b8d4f67 100644
--- a/secure/lib/libcrypto/man/ui_compat.3
+++ b/secure/lib/libcrypto/man/ui_compat.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ui_compat 3"
-.TH ui_compat 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ui_compat 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libcrypto/man/x509.3 b/secure/lib/libcrypto/man/x509.3
index 38dcbe97a732..c28211493dc0 100644
--- a/secure/lib/libcrypto/man/x509.3
+++ b/secure/lib/libcrypto/man/x509.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "x509 3"
-.TH x509 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH x509 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CIPHER_get_name.3 b/secure/lib/libssl/man/SSL_CIPHER_get_name.3
index c4eeb37486ee..95c0d1f6f58e 100644
--- a/secure/lib/libssl/man/SSL_CIPHER_get_name.3
+++ b/secure/lib/libssl/man/SSL_CIPHER_get_name.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CIPHER_get_name 3"
-.TH SSL_CIPHER_get_name 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CIPHER_get_name 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_COMP_add_compression_method.3 b/secure/lib/libssl/man/SSL_COMP_add_compression_method.3
index bc84d336e5f0..03e4c8a8f230 100644
--- a/secure/lib/libssl/man/SSL_COMP_add_compression_method.3
+++ b/secure/lib/libssl/man/SSL_COMP_add_compression_method.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_COMP_add_compression_method 3"
-.TH SSL_COMP_add_compression_method 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_COMP_add_compression_method 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CONF_CTX_new.3 b/secure/lib/libssl/man/SSL_CONF_CTX_new.3
index e84d67f6d77f..fd9ab18cedee 100644
--- a/secure/lib/libssl/man/SSL_CONF_CTX_new.3
+++ b/secure/lib/libssl/man/SSL_CONF_CTX_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CONF_CTX_new 3"
-.TH SSL_CONF_CTX_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CONF_CTX_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CONF_CTX_set1_prefix.3 b/secure/lib/libssl/man/SSL_CONF_CTX_set1_prefix.3
index 8aa030b7bb33..c4c58bdc2f43 100644
--- a/secure/lib/libssl/man/SSL_CONF_CTX_set1_prefix.3
+++ b/secure/lib/libssl/man/SSL_CONF_CTX_set1_prefix.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CONF_CTX_set1_prefix 3"
-.TH SSL_CONF_CTX_set1_prefix 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CONF_CTX_set1_prefix 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CONF_CTX_set_flags.3 b/secure/lib/libssl/man/SSL_CONF_CTX_set_flags.3
index 4d53609e3b76..165a0586d5c9 100644
--- a/secure/lib/libssl/man/SSL_CONF_CTX_set_flags.3
+++ b/secure/lib/libssl/man/SSL_CONF_CTX_set_flags.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CONF_CTX_set_flags 3"
-.TH SSL_CONF_CTX_set_flags 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CONF_CTX_set_flags 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CONF_CTX_set_ssl_ctx.3 b/secure/lib/libssl/man/SSL_CONF_CTX_set_ssl_ctx.3
index d54a5ec4005a..cc9b8960a53f 100644
--- a/secure/lib/libssl/man/SSL_CONF_CTX_set_ssl_ctx.3
+++ b/secure/lib/libssl/man/SSL_CONF_CTX_set_ssl_ctx.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CONF_CTX_set_ssl_ctx 3"
-.TH SSL_CONF_CTX_set_ssl_ctx 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CONF_CTX_set_ssl_ctx 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CONF_cmd.3 b/secure/lib/libssl/man/SSL_CONF_cmd.3
index 52759e215486..34b447ce169f 100644
--- a/secure/lib/libssl/man/SSL_CONF_cmd.3
+++ b/secure/lib/libssl/man/SSL_CONF_cmd.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CONF_cmd 3"
-.TH SSL_CONF_cmd 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CONF_cmd 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CONF_cmd_argv.3 b/secure/lib/libssl/man/SSL_CONF_cmd_argv.3
index 24cc08b6408b..013c5906d4c9 100644
--- a/secure/lib/libssl/man/SSL_CONF_cmd_argv.3
+++ b/secure/lib/libssl/man/SSL_CONF_cmd_argv.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CONF_cmd_argv 3"
-.TH SSL_CONF_cmd_argv 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CONF_cmd_argv 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_add1_chain_cert.3 b/secure/lib/libssl/man/SSL_CTX_add1_chain_cert.3
index 1e3b8be8126f..59b7b160bbb4 100644
--- a/secure/lib/libssl/man/SSL_CTX_add1_chain_cert.3
+++ b/secure/lib/libssl/man/SSL_CTX_add1_chain_cert.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_add1_chain_cert 3"
-.TH SSL_CTX_add1_chain_cert 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_add1_chain_cert 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_add_extra_chain_cert.3 b/secure/lib/libssl/man/SSL_CTX_add_extra_chain_cert.3
index a8302931582c..a29cb794a719 100644
--- a/secure/lib/libssl/man/SSL_CTX_add_extra_chain_cert.3
+++ b/secure/lib/libssl/man/SSL_CTX_add_extra_chain_cert.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_add_extra_chain_cert 3"
-.TH SSL_CTX_add_extra_chain_cert 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_add_extra_chain_cert 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_add_session.3 b/secure/lib/libssl/man/SSL_CTX_add_session.3
index 25fc9a831dbf..8367538d9fdc 100644
--- a/secure/lib/libssl/man/SSL_CTX_add_session.3
+++ b/secure/lib/libssl/man/SSL_CTX_add_session.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_add_session 3"
-.TH SSL_CTX_add_session 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_add_session 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_ctrl.3 b/secure/lib/libssl/man/SSL_CTX_ctrl.3
index 1d8005d7a94e..7da3853eedd0 100644
--- a/secure/lib/libssl/man/SSL_CTX_ctrl.3
+++ b/secure/lib/libssl/man/SSL_CTX_ctrl.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_ctrl 3"
-.TH SSL_CTX_ctrl 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_ctrl 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_flush_sessions.3 b/secure/lib/libssl/man/SSL_CTX_flush_sessions.3
index 738e2a8bd6e8..a055a1a60fe0 100644
--- a/secure/lib/libssl/man/SSL_CTX_flush_sessions.3
+++ b/secure/lib/libssl/man/SSL_CTX_flush_sessions.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_flush_sessions 3"
-.TH SSL_CTX_flush_sessions 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_flush_sessions 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_free.3 b/secure/lib/libssl/man/SSL_CTX_free.3
index af9e4ddc8e97..ea5d96b0aadf 100644
--- a/secure/lib/libssl/man/SSL_CTX_free.3
+++ b/secure/lib/libssl/man/SSL_CTX_free.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_free 3"
-.TH SSL_CTX_free 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_free 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_get0_param.3 b/secure/lib/libssl/man/SSL_CTX_get0_param.3
index 689ac4dcff44..9a20d4f29e91 100644
--- a/secure/lib/libssl/man/SSL_CTX_get0_param.3
+++ b/secure/lib/libssl/man/SSL_CTX_get0_param.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_get0_param 3"
-.TH SSL_CTX_get0_param 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_get0_param 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_get_ex_new_index.3 b/secure/lib/libssl/man/SSL_CTX_get_ex_new_index.3
index 8958feb3a265..f9206572db86 100644
--- a/secure/lib/libssl/man/SSL_CTX_get_ex_new_index.3
+++ b/secure/lib/libssl/man/SSL_CTX_get_ex_new_index.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_get_ex_new_index 3"
-.TH SSL_CTX_get_ex_new_index 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_get_ex_new_index 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_get_verify_mode.3 b/secure/lib/libssl/man/SSL_CTX_get_verify_mode.3
index 38878e18091b..af08998d9cea 100644
--- a/secure/lib/libssl/man/SSL_CTX_get_verify_mode.3
+++ b/secure/lib/libssl/man/SSL_CTX_get_verify_mode.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_get_verify_mode 3"
-.TH SSL_CTX_get_verify_mode 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_get_verify_mode 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_load_verify_locations.3 b/secure/lib/libssl/man/SSL_CTX_load_verify_locations.3
index 9c45f5ce0ae2..5e4863d36631 100644
--- a/secure/lib/libssl/man/SSL_CTX_load_verify_locations.3
+++ b/secure/lib/libssl/man/SSL_CTX_load_verify_locations.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_load_verify_locations 3"
-.TH SSL_CTX_load_verify_locations 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_load_verify_locations 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_new.3 b/secure/lib/libssl/man/SSL_CTX_new.3
index 754893470da3..78d94c822f01 100644
--- a/secure/lib/libssl/man/SSL_CTX_new.3
+++ b/secure/lib/libssl/man/SSL_CTX_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_new 3"
-.TH SSL_CTX_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_sess_number.3 b/secure/lib/libssl/man/SSL_CTX_sess_number.3
index c4dd1193774b..574fe2a123e9 100644
--- a/secure/lib/libssl/man/SSL_CTX_sess_number.3
+++ b/secure/lib/libssl/man/SSL_CTX_sess_number.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_sess_number 3"
-.TH SSL_CTX_sess_number 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_sess_number 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_sess_set_cache_size.3 b/secure/lib/libssl/man/SSL_CTX_sess_set_cache_size.3
index 635f6c7cf11a..51827b680277 100644
--- a/secure/lib/libssl/man/SSL_CTX_sess_set_cache_size.3
+++ b/secure/lib/libssl/man/SSL_CTX_sess_set_cache_size.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_sess_set_cache_size 3"
-.TH SSL_CTX_sess_set_cache_size 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_sess_set_cache_size 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_sess_set_get_cb.3 b/secure/lib/libssl/man/SSL_CTX_sess_set_get_cb.3
index 2cc5096268a1..4d727f4bc9a1 100644
--- a/secure/lib/libssl/man/SSL_CTX_sess_set_get_cb.3
+++ b/secure/lib/libssl/man/SSL_CTX_sess_set_get_cb.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_sess_set_get_cb 3"
-.TH SSL_CTX_sess_set_get_cb 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_sess_set_get_cb 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_sessions.3 b/secure/lib/libssl/man/SSL_CTX_sessions.3
index 6fc61a3f33ee..5081e5421999 100644
--- a/secure/lib/libssl/man/SSL_CTX_sessions.3
+++ b/secure/lib/libssl/man/SSL_CTX_sessions.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_sessions 3"
-.TH SSL_CTX_sessions 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_sessions 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set1_curves.3 b/secure/lib/libssl/man/SSL_CTX_set1_curves.3
index a2f9e2f8682c..8c24662bbad6 100644
--- a/secure/lib/libssl/man/SSL_CTX_set1_curves.3
+++ b/secure/lib/libssl/man/SSL_CTX_set1_curves.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set1_curves 3"
-.TH SSL_CTX_set1_curves 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set1_curves 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set1_verify_cert_store.3 b/secure/lib/libssl/man/SSL_CTX_set1_verify_cert_store.3
index 6e330282a5c7..afe656f6aee4 100644
--- a/secure/lib/libssl/man/SSL_CTX_set1_verify_cert_store.3
+++ b/secure/lib/libssl/man/SSL_CTX_set1_verify_cert_store.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set1_verify_cert_store 3"
-.TH SSL_CTX_set1_verify_cert_store 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set1_verify_cert_store 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_alpn_select_cb.3 b/secure/lib/libssl/man/SSL_CTX_set_alpn_select_cb.3
index d899d754b3c3..bdcc48832caa 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_alpn_select_cb.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_alpn_select_cb.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_alpn_select_cb 3"
-.TH SSL_CTX_set_alpn_select_cb 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_alpn_select_cb 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_cert_cb.3 b/secure/lib/libssl/man/SSL_CTX_set_cert_cb.3
index 8c2b0589b72c..e1207d05fa57 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_cert_cb.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_cert_cb.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_cert_cb 3"
-.TH SSL_CTX_set_cert_cb 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_cert_cb 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_cert_store.3 b/secure/lib/libssl/man/SSL_CTX_set_cert_store.3
index e7c54a6a2dc6..a280c64ab0f5 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_cert_store.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_cert_store.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_cert_store 3"
-.TH SSL_CTX_set_cert_store 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_cert_store 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_cert_verify_callback.3 b/secure/lib/libssl/man/SSL_CTX_set_cert_verify_callback.3
index fdc262f268a7..3f3b963a4958 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_cert_verify_callback.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_cert_verify_callback.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_cert_verify_callback 3"
-.TH SSL_CTX_set_cert_verify_callback 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_cert_verify_callback 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_cipher_list.3 b/secure/lib/libssl/man/SSL_CTX_set_cipher_list.3
index 34e058abad3f..701b694d3e94 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_cipher_list.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_cipher_list.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_cipher_list 3"
-.TH SSL_CTX_set_cipher_list 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_cipher_list 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_client_CA_list.3 b/secure/lib/libssl/man/SSL_CTX_set_client_CA_list.3
index 7d7c7fa9681b..227dbaa81a03 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_client_CA_list.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_client_CA_list.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_client_CA_list 3"
-.TH SSL_CTX_set_client_CA_list 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_client_CA_list 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_client_cert_cb.3 b/secure/lib/libssl/man/SSL_CTX_set_client_cert_cb.3
index c0cb51ee2986..cf380371aa7d 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_client_cert_cb.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_client_cert_cb.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_client_cert_cb 3"
-.TH SSL_CTX_set_client_cert_cb 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_client_cert_cb 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_custom_cli_ext.3 b/secure/lib/libssl/man/SSL_CTX_set_custom_cli_ext.3
index ea930e3290fa..32f2cb2216dd 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_custom_cli_ext.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_custom_cli_ext.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_custom_cli_ext 3"
-.TH SSL_CTX_set_custom_cli_ext 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_custom_cli_ext 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_default_passwd_cb.3 b/secure/lib/libssl/man/SSL_CTX_set_default_passwd_cb.3
index 95787aa31c42..63e87c861383 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_default_passwd_cb.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_default_passwd_cb.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_default_passwd_cb 3"
-.TH SSL_CTX_set_default_passwd_cb 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_default_passwd_cb 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_generate_session_id.3 b/secure/lib/libssl/man/SSL_CTX_set_generate_session_id.3
index ec045284df46..8bfc1c48be80 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_generate_session_id.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_generate_session_id.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_generate_session_id 3"
-.TH SSL_CTX_set_generate_session_id 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_generate_session_id 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_info_callback.3 b/secure/lib/libssl/man/SSL_CTX_set_info_callback.3
index e1cac3233503..10f441ae8aa5 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_info_callback.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_info_callback.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_info_callback 3"
-.TH SSL_CTX_set_info_callback 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_info_callback 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_max_cert_list.3 b/secure/lib/libssl/man/SSL_CTX_set_max_cert_list.3
index bdd8fe7a8de2..ba7d3e0bc580 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_max_cert_list.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_max_cert_list.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_max_cert_list 3"
-.TH SSL_CTX_set_max_cert_list 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_max_cert_list 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_mode.3 b/secure/lib/libssl/man/SSL_CTX_set_mode.3
index 320e1732552b..2796358bd504 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_mode.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_mode.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_mode 3"
-.TH SSL_CTX_set_mode 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_mode 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_msg_callback.3 b/secure/lib/libssl/man/SSL_CTX_set_msg_callback.3
index 925b5b642f1e..a6a30f909c5d 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_msg_callback.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_msg_callback.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_msg_callback 3"
-.TH SSL_CTX_set_msg_callback 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_msg_callback 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_options.3 b/secure/lib/libssl/man/SSL_CTX_set_options.3
index 98e06368e362..43008b2d4d0e 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_options.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_options.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_options 3"
-.TH SSL_CTX_set_options 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_options 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_psk_client_callback.3 b/secure/lib/libssl/man/SSL_CTX_set_psk_client_callback.3
index 98ed47812417..b847b3abc761 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_psk_client_callback.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_psk_client_callback.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_psk_client_callback 3"
-.TH SSL_CTX_set_psk_client_callback 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_psk_client_callback 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_quiet_shutdown.3 b/secure/lib/libssl/man/SSL_CTX_set_quiet_shutdown.3
index c79cc0f817c3..50f4d0ea4160 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_quiet_shutdown.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_quiet_shutdown.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_quiet_shutdown 3"
-.TH SSL_CTX_set_quiet_shutdown 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_quiet_shutdown 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_read_ahead.3 b/secure/lib/libssl/man/SSL_CTX_set_read_ahead.3
index 7f27bfd12008..8a6a0448a416 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_read_ahead.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_read_ahead.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_read_ahead 3"
-.TH SSL_CTX_set_read_ahead 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_read_ahead 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_session_cache_mode.3 b/secure/lib/libssl/man/SSL_CTX_set_session_cache_mode.3
index a8770302f1ef..aa3004b25e0d 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_session_cache_mode.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_session_cache_mode.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_session_cache_mode 3"
-.TH SSL_CTX_set_session_cache_mode 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_session_cache_mode 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_session_id_context.3 b/secure/lib/libssl/man/SSL_CTX_set_session_id_context.3
index 88a1b29ad2d1..46f2a405e03a 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_session_id_context.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_session_id_context.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_session_id_context 3"
-.TH SSL_CTX_set_session_id_context 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_session_id_context 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_ssl_version.3 b/secure/lib/libssl/man/SSL_CTX_set_ssl_version.3
index a003e3cca4ba..3609726fcae4 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_ssl_version.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_ssl_version.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_ssl_version 3"
-.TH SSL_CTX_set_ssl_version 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_ssl_version 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_timeout.3 b/secure/lib/libssl/man/SSL_CTX_set_timeout.3
index 4e4879694b74..259b7a2bf52a 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_timeout.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_timeout.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_timeout 3"
-.TH SSL_CTX_set_timeout 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_timeout 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_tlsext_status_cb.3 b/secure/lib/libssl/man/SSL_CTX_set_tlsext_status_cb.3
index fcc79a35d192..e79ab6461efc 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_tlsext_status_cb.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_tlsext_status_cb.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_tlsext_status_cb 3"
-.TH SSL_CTX_set_tlsext_status_cb 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_tlsext_status_cb 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_tlsext_ticket_key_cb.3 b/secure/lib/libssl/man/SSL_CTX_set_tlsext_ticket_key_cb.3
index 5bd0a9b59233..d228d3417e80 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_tlsext_ticket_key_cb.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_tlsext_ticket_key_cb.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_tlsext_ticket_key_cb 3"
-.TH SSL_CTX_set_tlsext_ticket_key_cb 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_tlsext_ticket_key_cb 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_tmp_dh_callback.3 b/secure/lib/libssl/man/SSL_CTX_set_tmp_dh_callback.3
index 755450afb9af..ddd968ee82ab 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_tmp_dh_callback.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_tmp_dh_callback.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_tmp_dh_callback 3"
-.TH SSL_CTX_set_tmp_dh_callback 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_tmp_dh_callback 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_tmp_rsa_callback.3 b/secure/lib/libssl/man/SSL_CTX_set_tmp_rsa_callback.3
index fed99e209dbd..cedeaabd88f6 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_tmp_rsa_callback.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_tmp_rsa_callback.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_tmp_rsa_callback 3"
-.TH SSL_CTX_set_tmp_rsa_callback 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_tmp_rsa_callback 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_set_verify.3 b/secure/lib/libssl/man/SSL_CTX_set_verify.3
index 2a49511c0c07..0df23dbe4f7c 100644
--- a/secure/lib/libssl/man/SSL_CTX_set_verify.3
+++ b/secure/lib/libssl/man/SSL_CTX_set_verify.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_set_verify 3"
-.TH SSL_CTX_set_verify 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_set_verify 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_use_certificate.3 b/secure/lib/libssl/man/SSL_CTX_use_certificate.3
index 40bb8bbc0d55..bf6384ef9abb 100644
--- a/secure/lib/libssl/man/SSL_CTX_use_certificate.3
+++ b/secure/lib/libssl/man/SSL_CTX_use_certificate.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_use_certificate 3"
-.TH SSL_CTX_use_certificate 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_use_certificate 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_use_psk_identity_hint.3 b/secure/lib/libssl/man/SSL_CTX_use_psk_identity_hint.3
index f0b9d999be65..cb881e4616d1 100644
--- a/secure/lib/libssl/man/SSL_CTX_use_psk_identity_hint.3
+++ b/secure/lib/libssl/man/SSL_CTX_use_psk_identity_hint.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_use_psk_identity_hint 3"
-.TH SSL_CTX_use_psk_identity_hint 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_use_psk_identity_hint 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_CTX_use_serverinfo.3 b/secure/lib/libssl/man/SSL_CTX_use_serverinfo.3
index 12d0d6a36a9f..33b76bfc7afa 100644
--- a/secure/lib/libssl/man/SSL_CTX_use_serverinfo.3
+++ b/secure/lib/libssl/man/SSL_CTX_use_serverinfo.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_CTX_use_serverinfo 3"
-.TH SSL_CTX_use_serverinfo 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_CTX_use_serverinfo 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_SESSION_free.3 b/secure/lib/libssl/man/SSL_SESSION_free.3
index 4a9afa0d7082..4ecc36f5c2d5 100644
--- a/secure/lib/libssl/man/SSL_SESSION_free.3
+++ b/secure/lib/libssl/man/SSL_SESSION_free.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_SESSION_free 3"
-.TH SSL_SESSION_free 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_SESSION_free 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_SESSION_get_ex_new_index.3 b/secure/lib/libssl/man/SSL_SESSION_get_ex_new_index.3
index 0be5602a522b..edcc38d4667c 100644
--- a/secure/lib/libssl/man/SSL_SESSION_get_ex_new_index.3
+++ b/secure/lib/libssl/man/SSL_SESSION_get_ex_new_index.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_SESSION_get_ex_new_index 3"
-.TH SSL_SESSION_get_ex_new_index 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_SESSION_get_ex_new_index 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_SESSION_get_time.3 b/secure/lib/libssl/man/SSL_SESSION_get_time.3
index 3e8fdc711b7d..914a2c442955 100644
--- a/secure/lib/libssl/man/SSL_SESSION_get_time.3
+++ b/secure/lib/libssl/man/SSL_SESSION_get_time.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_SESSION_get_time 3"
-.TH SSL_SESSION_get_time 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_SESSION_get_time 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_accept.3 b/secure/lib/libssl/man/SSL_accept.3
index ba89bfd8fe44..0d69ebf6c9bb 100644
--- a/secure/lib/libssl/man/SSL_accept.3
+++ b/secure/lib/libssl/man/SSL_accept.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_accept 3"
-.TH SSL_accept 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_accept 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_alert_type_string.3 b/secure/lib/libssl/man/SSL_alert_type_string.3
index 6a36a1360f98..fd0c0c6ae53b 100644
--- a/secure/lib/libssl/man/SSL_alert_type_string.3
+++ b/secure/lib/libssl/man/SSL_alert_type_string.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_alert_type_string 3"
-.TH SSL_alert_type_string 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_alert_type_string 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_check_chain.3 b/secure/lib/libssl/man/SSL_check_chain.3
index 71cab640fdff..b2ed8c300e13 100644
--- a/secure/lib/libssl/man/SSL_check_chain.3
+++ b/secure/lib/libssl/man/SSL_check_chain.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_check_chain 3"
-.TH SSL_check_chain 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_check_chain 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_clear.3 b/secure/lib/libssl/man/SSL_clear.3
index c2caf8d7944c..4426ef62bbe6 100644
--- a/secure/lib/libssl/man/SSL_clear.3
+++ b/secure/lib/libssl/man/SSL_clear.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_clear 3"
-.TH SSL_clear 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_clear 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_connect.3 b/secure/lib/libssl/man/SSL_connect.3
index ec279579aa71..4e05eb17cf75 100644
--- a/secure/lib/libssl/man/SSL_connect.3
+++ b/secure/lib/libssl/man/SSL_connect.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_connect 3"
-.TH SSL_connect 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_connect 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_do_handshake.3 b/secure/lib/libssl/man/SSL_do_handshake.3
index 270b3f5f9e99..8339391bfafa 100644
--- a/secure/lib/libssl/man/SSL_do_handshake.3
+++ b/secure/lib/libssl/man/SSL_do_handshake.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_do_handshake 3"
-.TH SSL_do_handshake 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_do_handshake 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_free.3 b/secure/lib/libssl/man/SSL_free.3
index bc62f69eb526..7792fa77d4c5 100644
--- a/secure/lib/libssl/man/SSL_free.3
+++ b/secure/lib/libssl/man/SSL_free.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_free 3"
-.TH SSL_free 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_free 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_SSL_CTX.3 b/secure/lib/libssl/man/SSL_get_SSL_CTX.3
index 114653783020..4d5b7891cee4 100644
--- a/secure/lib/libssl/man/SSL_get_SSL_CTX.3
+++ b/secure/lib/libssl/man/SSL_get_SSL_CTX.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_SSL_CTX 3"
-.TH SSL_get_SSL_CTX 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_SSL_CTX 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_ciphers.3 b/secure/lib/libssl/man/SSL_get_ciphers.3
index 0af65cde043f..701e3b51d1d5 100644
--- a/secure/lib/libssl/man/SSL_get_ciphers.3
+++ b/secure/lib/libssl/man/SSL_get_ciphers.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_ciphers 3"
-.TH SSL_get_ciphers 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_ciphers 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_client_CA_list.3 b/secure/lib/libssl/man/SSL_get_client_CA_list.3
index 0d204fb30cbf..60c3e49ef74f 100644
--- a/secure/lib/libssl/man/SSL_get_client_CA_list.3
+++ b/secure/lib/libssl/man/SSL_get_client_CA_list.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_client_CA_list 3"
-.TH SSL_get_client_CA_list 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_client_CA_list 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_current_cipher.3 b/secure/lib/libssl/man/SSL_get_current_cipher.3
index 4ac58ad8aba8..32339038f3cf 100644
--- a/secure/lib/libssl/man/SSL_get_current_cipher.3
+++ b/secure/lib/libssl/man/SSL_get_current_cipher.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_current_cipher 3"
-.TH SSL_get_current_cipher 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_current_cipher 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_default_timeout.3 b/secure/lib/libssl/man/SSL_get_default_timeout.3
index 179c7879ef41..9837bdd65c69 100644
--- a/secure/lib/libssl/man/SSL_get_default_timeout.3
+++ b/secure/lib/libssl/man/SSL_get_default_timeout.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_default_timeout 3"
-.TH SSL_get_default_timeout 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_default_timeout 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_error.3 b/secure/lib/libssl/man/SSL_get_error.3
index be6a1e4feddb..54588fc832c3 100644
--- a/secure/lib/libssl/man/SSL_get_error.3
+++ b/secure/lib/libssl/man/SSL_get_error.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_error 3"
-.TH SSL_get_error 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_error 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_ex_data_X509_STORE_CTX_idx.3 b/secure/lib/libssl/man/SSL_get_ex_data_X509_STORE_CTX_idx.3
index 455b2525c1cd..3de44fcc954e 100644
--- a/secure/lib/libssl/man/SSL_get_ex_data_X509_STORE_CTX_idx.3
+++ b/secure/lib/libssl/man/SSL_get_ex_data_X509_STORE_CTX_idx.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_ex_data_X509_STORE_CTX_idx 3"
-.TH SSL_get_ex_data_X509_STORE_CTX_idx 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_ex_data_X509_STORE_CTX_idx 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_ex_new_index.3 b/secure/lib/libssl/man/SSL_get_ex_new_index.3
index 38353c9d08f6..e55b50e45f19 100644
--- a/secure/lib/libssl/man/SSL_get_ex_new_index.3
+++ b/secure/lib/libssl/man/SSL_get_ex_new_index.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_ex_new_index 3"
-.TH SSL_get_ex_new_index 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_ex_new_index 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_fd.3 b/secure/lib/libssl/man/SSL_get_fd.3
index f6b1393ae5f7..bb763e362f05 100644
--- a/secure/lib/libssl/man/SSL_get_fd.3
+++ b/secure/lib/libssl/man/SSL_get_fd.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_fd 3"
-.TH SSL_get_fd 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_fd 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_peer_cert_chain.3 b/secure/lib/libssl/man/SSL_get_peer_cert_chain.3
index 63d880e06350..b6c252097650 100644
--- a/secure/lib/libssl/man/SSL_get_peer_cert_chain.3
+++ b/secure/lib/libssl/man/SSL_get_peer_cert_chain.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_peer_cert_chain 3"
-.TH SSL_get_peer_cert_chain 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_peer_cert_chain 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_peer_certificate.3 b/secure/lib/libssl/man/SSL_get_peer_certificate.3
index dd016887e010..4f79206097cf 100644
--- a/secure/lib/libssl/man/SSL_get_peer_certificate.3
+++ b/secure/lib/libssl/man/SSL_get_peer_certificate.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_peer_certificate 3"
-.TH SSL_get_peer_certificate 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_peer_certificate 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_psk_identity.3 b/secure/lib/libssl/man/SSL_get_psk_identity.3
index 1e853129fdfe..f541c29ec353 100644
--- a/secure/lib/libssl/man/SSL_get_psk_identity.3
+++ b/secure/lib/libssl/man/SSL_get_psk_identity.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_psk_identity 3"
-.TH SSL_get_psk_identity 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_psk_identity 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_rbio.3 b/secure/lib/libssl/man/SSL_get_rbio.3
index 4cf9840d66b2..5b4c3707d4f1 100644
--- a/secure/lib/libssl/man/SSL_get_rbio.3
+++ b/secure/lib/libssl/man/SSL_get_rbio.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_rbio 3"
-.TH SSL_get_rbio 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_rbio 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_session.3 b/secure/lib/libssl/man/SSL_get_session.3
index 79a870a60231..089fc4d0dcf6 100644
--- a/secure/lib/libssl/man/SSL_get_session.3
+++ b/secure/lib/libssl/man/SSL_get_session.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_session 3"
-.TH SSL_get_session 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_session 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_verify_result.3 b/secure/lib/libssl/man/SSL_get_verify_result.3
index 5925616d41b4..e185a38052db 100644
--- a/secure/lib/libssl/man/SSL_get_verify_result.3
+++ b/secure/lib/libssl/man/SSL_get_verify_result.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_verify_result 3"
-.TH SSL_get_verify_result 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_verify_result 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_get_version.3 b/secure/lib/libssl/man/SSL_get_version.3
index 5189ed26d261..1e6be3c653eb 100644
--- a/secure/lib/libssl/man/SSL_get_version.3
+++ b/secure/lib/libssl/man/SSL_get_version.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_get_version 3"
-.TH SSL_get_version 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_get_version 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_library_init.3 b/secure/lib/libssl/man/SSL_library_init.3
index d784fddf0a68..ac916abc5add 100644
--- a/secure/lib/libssl/man/SSL_library_init.3
+++ b/secure/lib/libssl/man/SSL_library_init.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_library_init 3"
-.TH SSL_library_init 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_library_init 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_load_client_CA_file.3 b/secure/lib/libssl/man/SSL_load_client_CA_file.3
index 700964df7e89..3973dfbf18df 100644
--- a/secure/lib/libssl/man/SSL_load_client_CA_file.3
+++ b/secure/lib/libssl/man/SSL_load_client_CA_file.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_load_client_CA_file 3"
-.TH SSL_load_client_CA_file 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_load_client_CA_file 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_new.3 b/secure/lib/libssl/man/SSL_new.3
index b254d65a1488..0f4850474c61 100644
--- a/secure/lib/libssl/man/SSL_new.3
+++ b/secure/lib/libssl/man/SSL_new.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_new 3"
-.TH SSL_new 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_new 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_pending.3 b/secure/lib/libssl/man/SSL_pending.3
index ced3a9b47b04..8c3cf4b8b629 100644
--- a/secure/lib/libssl/man/SSL_pending.3
+++ b/secure/lib/libssl/man/SSL_pending.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_pending 3"
-.TH SSL_pending 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_pending 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_read.3 b/secure/lib/libssl/man/SSL_read.3
index da372bba211f..f8cfcdc4bcdd 100644
--- a/secure/lib/libssl/man/SSL_read.3
+++ b/secure/lib/libssl/man/SSL_read.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_read 3"
-.TH SSL_read 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_read 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_rstate_string.3 b/secure/lib/libssl/man/SSL_rstate_string.3
index 4ebe24fc1a59..047d85460ba6 100644
--- a/secure/lib/libssl/man/SSL_rstate_string.3
+++ b/secure/lib/libssl/man/SSL_rstate_string.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_rstate_string 3"
-.TH SSL_rstate_string 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_rstate_string 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_session_reused.3 b/secure/lib/libssl/man/SSL_session_reused.3
index 91848b22c17d..56ec9a405f40 100644
--- a/secure/lib/libssl/man/SSL_session_reused.3
+++ b/secure/lib/libssl/man/SSL_session_reused.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_session_reused 3"
-.TH SSL_session_reused 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_session_reused 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_set_bio.3 b/secure/lib/libssl/man/SSL_set_bio.3
index 2d053b5e8801..06f1b972025a 100644
--- a/secure/lib/libssl/man/SSL_set_bio.3
+++ b/secure/lib/libssl/man/SSL_set_bio.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_set_bio 3"
-.TH SSL_set_bio 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_set_bio 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_set_connect_state.3 b/secure/lib/libssl/man/SSL_set_connect_state.3
index d4794f5ee78f..e9081535a437 100644
--- a/secure/lib/libssl/man/SSL_set_connect_state.3
+++ b/secure/lib/libssl/man/SSL_set_connect_state.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_set_connect_state 3"
-.TH SSL_set_connect_state 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_set_connect_state 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_set_fd.3 b/secure/lib/libssl/man/SSL_set_fd.3
index 8d8830d525ac..2354a93861ed 100644
--- a/secure/lib/libssl/man/SSL_set_fd.3
+++ b/secure/lib/libssl/man/SSL_set_fd.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_set_fd 3"
-.TH SSL_set_fd 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_set_fd 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_set_session.3 b/secure/lib/libssl/man/SSL_set_session.3
index 076c8ae71f27..0f37a58e26f4 100644
--- a/secure/lib/libssl/man/SSL_set_session.3
+++ b/secure/lib/libssl/man/SSL_set_session.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_set_session 3"
-.TH SSL_set_session 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_set_session 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_set_shutdown.3 b/secure/lib/libssl/man/SSL_set_shutdown.3
index cfb0615ed343..ed00917dfdb1 100644
--- a/secure/lib/libssl/man/SSL_set_shutdown.3
+++ b/secure/lib/libssl/man/SSL_set_shutdown.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_set_shutdown 3"
-.TH SSL_set_shutdown 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_set_shutdown 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_set_verify_result.3 b/secure/lib/libssl/man/SSL_set_verify_result.3
index 9187a50629dc..354105ac1070 100644
--- a/secure/lib/libssl/man/SSL_set_verify_result.3
+++ b/secure/lib/libssl/man/SSL_set_verify_result.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_set_verify_result 3"
-.TH SSL_set_verify_result 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_set_verify_result 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_shutdown.3 b/secure/lib/libssl/man/SSL_shutdown.3
index a8a321a31ab3..af785d3caeb4 100644
--- a/secure/lib/libssl/man/SSL_shutdown.3
+++ b/secure/lib/libssl/man/SSL_shutdown.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_shutdown 3"
-.TH SSL_shutdown 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_shutdown 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_state_string.3 b/secure/lib/libssl/man/SSL_state_string.3
index 6d0a8fdc87a5..1e290027a768 100644
--- a/secure/lib/libssl/man/SSL_state_string.3
+++ b/secure/lib/libssl/man/SSL_state_string.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_state_string 3"
-.TH SSL_state_string 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_state_string 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_want.3 b/secure/lib/libssl/man/SSL_want.3
index 9a69e5c45bcf..ab20b9a0fbc0 100644
--- a/secure/lib/libssl/man/SSL_want.3
+++ b/secure/lib/libssl/man/SSL_want.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_want 3"
-.TH SSL_want 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_want 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/SSL_write.3 b/secure/lib/libssl/man/SSL_write.3
index 02808ae49d09..922d41150278 100644
--- a/secure/lib/libssl/man/SSL_write.3
+++ b/secure/lib/libssl/man/SSL_write.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SSL_write 3"
-.TH SSL_write 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SSL_write 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/d2i_SSL_SESSION.3 b/secure/lib/libssl/man/d2i_SSL_SESSION.3
index 3934b0f7d32f..d17568888227 100644
--- a/secure/lib/libssl/man/d2i_SSL_SESSION.3
+++ b/secure/lib/libssl/man/d2i_SSL_SESSION.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "d2i_SSL_SESSION 3"
-.TH d2i_SSL_SESSION 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH d2i_SSL_SESSION 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/lib/libssl/man/ssl.3 b/secure/lib/libssl/man/ssl.3
index d40bdd87b5be..cd42641e0fa4 100644
--- a/secure/lib/libssl/man/ssl.3
+++ b/secure/lib/libssl/man/ssl.3
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ssl 3"
-.TH ssl 3 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ssl 3 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/CA.pl.1 b/secure/usr.bin/openssl/man/CA.pl.1
index 798aace101b1..bdfcc1673716 100644
--- a/secure/usr.bin/openssl/man/CA.pl.1
+++ b/secure/usr.bin/openssl/man/CA.pl.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CA.PL 1"
-.TH CA.PL 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CA.PL 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/asn1parse.1 b/secure/usr.bin/openssl/man/asn1parse.1
index f03174b4cd64..6c3a563c3165 100644
--- a/secure/usr.bin/openssl/man/asn1parse.1
+++ b/secure/usr.bin/openssl/man/asn1parse.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ASN1PARSE 1"
-.TH ASN1PARSE 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ASN1PARSE 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/c_rehash.1 b/secure/usr.bin/openssl/man/c_rehash.1
index c7812b5c7a64..e5beb5068230 100644
--- a/secure/usr.bin/openssl/man/c_rehash.1
+++ b/secure/usr.bin/openssl/man/c_rehash.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "C_REHASH 1"
-.TH C_REHASH 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH C_REHASH 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/ca.1 b/secure/usr.bin/openssl/man/ca.1
index 688beeaaf5dd..113bc408dbf6 100644
--- a/secure/usr.bin/openssl/man/ca.1
+++ b/secure/usr.bin/openssl/man/ca.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CA 1"
-.TH CA 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CA 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/ciphers.1 b/secure/usr.bin/openssl/man/ciphers.1
index abf05c5bba08..8aea03ebd2df 100644
--- a/secure/usr.bin/openssl/man/ciphers.1
+++ b/secure/usr.bin/openssl/man/ciphers.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CIPHERS 1"
-.TH CIPHERS 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CIPHERS 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/cms.1 b/secure/usr.bin/openssl/man/cms.1
index 378b33f21f78..73087e5db47d 100644
--- a/secure/usr.bin/openssl/man/cms.1
+++ b/secure/usr.bin/openssl/man/cms.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CMS 1"
-.TH CMS 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CMS 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -216,6 +216,9 @@ type.
 encrypt mail for the given recipient certificates. Input file is the message
 to be encrypted. The output file is the encrypted mail in \s-1MIME\s0 format. The
 actual \s-1CMS\s0 type is <B>EnvelopedData<B>.
+.Sp
+Note that no revocation check is done for the recipient cert, so if that
+key has been compromised, others may be able to decrypt the text.
 .IP "\fB\-decrypt\fR" 4
 .IX Item "-decrypt"
 decrypt mail using the supplied certificate and private key. Expects an
diff --git a/secure/usr.bin/openssl/man/crl.1 b/secure/usr.bin/openssl/man/crl.1
index c48fbf396d83..2d84357057b3 100644
--- a/secure/usr.bin/openssl/man/crl.1
+++ b/secure/usr.bin/openssl/man/crl.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CRL 1"
-.TH CRL 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CRL 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/crl2pkcs7.1 b/secure/usr.bin/openssl/man/crl2pkcs7.1
index 08315a5647fd..7bcc8d8fbf5f 100644
--- a/secure/usr.bin/openssl/man/crl2pkcs7.1
+++ b/secure/usr.bin/openssl/man/crl2pkcs7.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "CRL2PKCS7 1"
-.TH CRL2PKCS7 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH CRL2PKCS7 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/dgst.1 b/secure/usr.bin/openssl/man/dgst.1
index d65b99bb47f4..ec8feab438f7 100644
--- a/secure/usr.bin/openssl/man/dgst.1
+++ b/secure/usr.bin/openssl/man/dgst.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DGST 1"
-.TH DGST 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DGST 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/dhparam.1 b/secure/usr.bin/openssl/man/dhparam.1
index 9d0288f73b71..f802fdebd19a 100644
--- a/secure/usr.bin/openssl/man/dhparam.1
+++ b/secure/usr.bin/openssl/man/dhparam.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DHPARAM 1"
-.TH DHPARAM 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DHPARAM 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/dsa.1 b/secure/usr.bin/openssl/man/dsa.1
index 35acb74b99df..5075f26c30df 100644
--- a/secure/usr.bin/openssl/man/dsa.1
+++ b/secure/usr.bin/openssl/man/dsa.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSA 1"
-.TH DSA 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSA 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/dsaparam.1 b/secure/usr.bin/openssl/man/dsaparam.1
index 2a760aa9df11..f7e83f8c2485 100644
--- a/secure/usr.bin/openssl/man/dsaparam.1
+++ b/secure/usr.bin/openssl/man/dsaparam.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "DSAPARAM 1"
-.TH DSAPARAM 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH DSAPARAM 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/ec.1 b/secure/usr.bin/openssl/man/ec.1
index dd15921cde69..5e10e0a6a32a 100644
--- a/secure/usr.bin/openssl/man/ec.1
+++ b/secure/usr.bin/openssl/man/ec.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "EC 1"
-.TH EC 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH EC 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/ecparam.1 b/secure/usr.bin/openssl/man/ecparam.1
index 80f00468d7a9..68c30c1e84c7 100644
--- a/secure/usr.bin/openssl/man/ecparam.1
+++ b/secure/usr.bin/openssl/man/ecparam.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ECPARAM 1"
-.TH ECPARAM 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ECPARAM 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/enc.1 b/secure/usr.bin/openssl/man/enc.1
index d4ffb0f56ec5..da567c22e185 100644
--- a/secure/usr.bin/openssl/man/enc.1
+++ b/secure/usr.bin/openssl/man/enc.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ENC 1"
-.TH ENC 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ENC 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/errstr.1 b/secure/usr.bin/openssl/man/errstr.1
index f41965ce9a07..c5e4d453e7c7 100644
--- a/secure/usr.bin/openssl/man/errstr.1
+++ b/secure/usr.bin/openssl/man/errstr.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "ERRSTR 1"
-.TH ERRSTR 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH ERRSTR 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/gendsa.1 b/secure/usr.bin/openssl/man/gendsa.1
index eda28c0d4e42..aa85d3f48cf7 100644
--- a/secure/usr.bin/openssl/man/gendsa.1
+++ b/secure/usr.bin/openssl/man/gendsa.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "GENDSA 1"
-.TH GENDSA 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH GENDSA 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/genpkey.1 b/secure/usr.bin/openssl/man/genpkey.1
index ab8bf2b8f0ab..96bf07f42c2a 100644
--- a/secure/usr.bin/openssl/man/genpkey.1
+++ b/secure/usr.bin/openssl/man/genpkey.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "GENPKEY 1"
-.TH GENPKEY 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH GENPKEY 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/genrsa.1 b/secure/usr.bin/openssl/man/genrsa.1
index 74cd467a1d49..9a118bd191bd 100644
--- a/secure/usr.bin/openssl/man/genrsa.1
+++ b/secure/usr.bin/openssl/man/genrsa.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "GENRSA 1"
-.TH GENRSA 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH GENRSA 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/nseq.1 b/secure/usr.bin/openssl/man/nseq.1
index 3c3fc5bc9af8..b0397f48096f 100644
--- a/secure/usr.bin/openssl/man/nseq.1
+++ b/secure/usr.bin/openssl/man/nseq.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "NSEQ 1"
-.TH NSEQ 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH NSEQ 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/ocsp.1 b/secure/usr.bin/openssl/man/ocsp.1
index 9871db5d8d27..856d17bc8ab6 100644
--- a/secure/usr.bin/openssl/man/ocsp.1
+++ b/secure/usr.bin/openssl/man/ocsp.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OCSP 1"
-.TH OCSP 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OCSP 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/openssl.1 b/secure/usr.bin/openssl/man/openssl.1
index f97895032f66..55dce5973c98 100644
--- a/secure/usr.bin/openssl/man/openssl.1
+++ b/secure/usr.bin/openssl/man/openssl.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "OPENSSL 1"
-.TH OPENSSL 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH OPENSSL 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/passwd.1 b/secure/usr.bin/openssl/man/passwd.1
index c3045a8fbaea..57de3998a487 100644
--- a/secure/usr.bin/openssl/man/passwd.1
+++ b/secure/usr.bin/openssl/man/passwd.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PASSWD 1"
-.TH PASSWD 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PASSWD 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/pkcs12.1 b/secure/usr.bin/openssl/man/pkcs12.1
index 71340a2ca83a..ef0451a01058 100644
--- a/secure/usr.bin/openssl/man/pkcs12.1
+++ b/secure/usr.bin/openssl/man/pkcs12.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS12 1"
-.TH PKCS12 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS12 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/pkcs7.1 b/secure/usr.bin/openssl/man/pkcs7.1
index bb0539315b99..32c61345685a 100644
--- a/secure/usr.bin/openssl/man/pkcs7.1
+++ b/secure/usr.bin/openssl/man/pkcs7.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS7 1"
-.TH PKCS7 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS7 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/pkcs8.1 b/secure/usr.bin/openssl/man/pkcs8.1
index 2dabe9e5d927..aadfecbe3f39 100644
--- a/secure/usr.bin/openssl/man/pkcs8.1
+++ b/secure/usr.bin/openssl/man/pkcs8.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKCS8 1"
-.TH PKCS8 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKCS8 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/pkey.1 b/secure/usr.bin/openssl/man/pkey.1
index b5422eecaa02..90cfbfcc8084 100644
--- a/secure/usr.bin/openssl/man/pkey.1
+++ b/secure/usr.bin/openssl/man/pkey.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKEY 1"
-.TH PKEY 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKEY 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/pkeyparam.1 b/secure/usr.bin/openssl/man/pkeyparam.1
index f189f685da82..02e391c69de2 100644
--- a/secure/usr.bin/openssl/man/pkeyparam.1
+++ b/secure/usr.bin/openssl/man/pkeyparam.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKEYPARAM 1"
-.TH PKEYPARAM 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKEYPARAM 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/pkeyutl.1 b/secure/usr.bin/openssl/man/pkeyutl.1
index bba029f5b9eb..6c25a10b53ab 100644
--- a/secure/usr.bin/openssl/man/pkeyutl.1
+++ b/secure/usr.bin/openssl/man/pkeyutl.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "PKEYUTL 1"
-.TH PKEYUTL 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH PKEYUTL 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/rand.1 b/secure/usr.bin/openssl/man/rand.1
index 79490d462ae9..3f2fc40fe551 100644
--- a/secure/usr.bin/openssl/man/rand.1
+++ b/secure/usr.bin/openssl/man/rand.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RAND 1"
-.TH RAND 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RAND 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/req.1 b/secure/usr.bin/openssl/man/req.1
index e946bd5c98d4..0fec01a83ed3 100644
--- a/secure/usr.bin/openssl/man/req.1
+++ b/secure/usr.bin/openssl/man/req.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "REQ 1"
-.TH REQ 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH REQ 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/rsa.1 b/secure/usr.bin/openssl/man/rsa.1
index 39803ab6651c..e4459caa62dc 100644
--- a/secure/usr.bin/openssl/man/rsa.1
+++ b/secure/usr.bin/openssl/man/rsa.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSA 1"
-.TH RSA 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSA 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/rsautl.1 b/secure/usr.bin/openssl/man/rsautl.1
index 3ec6999f70ac..9e6cad292b30 100644
--- a/secure/usr.bin/openssl/man/rsautl.1
+++ b/secure/usr.bin/openssl/man/rsautl.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "RSAUTL 1"
-.TH RSAUTL 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH RSAUTL 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/s_client.1 b/secure/usr.bin/openssl/man/s_client.1
index ef6dd9b7ed42..7a874cdbe39f 100644
--- a/secure/usr.bin/openssl/man/s_client.1
+++ b/secure/usr.bin/openssl/man/s_client.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "S_CLIENT 1"
-.TH S_CLIENT 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH S_CLIENT 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -188,6 +188,7 @@ s_client \- SSL/TLS client program
 [\fB\-rand file(s)\fR]
 [\fB\-serverinfo types\fR]
 [\fB\-status\fR]
+[\fB\-alpn protocols\fR]
 [\fB\-nextprotoneg protocols\fR]
 .SH "DESCRIPTION"
 .IX Header "DESCRIPTION"
@@ -367,9 +368,13 @@ file.
 .IX Item "-status"
 sends a certificate status request to the server (\s-1OCSP\s0 stapling). The server
 response (if any) is printed out.
-.IP "\fB\-nextprotoneg protocols\fR" 4
-.IX Item "-nextprotoneg protocols"
-enable Next Protocol Negotiation \s-1TLS\s0 extension and provide a list of
+.IP "\fB\-alpn protocols\fR, \fB\-nextprotoneg protocols\fR" 4
+.IX Item "-alpn protocols, -nextprotoneg protocols"
+these flags enable the 
+Enable the Application-Layer Protocol Negotiation or Next Protocol
+Negotiation extension, respectively. \s-1ALPN\s0 is the \s-1IETF\s0 standard and
+replaces \s-1NPN.\s0
+The \fBprotocols\fR list is a
 comma-separated protocol names that the client should advertise
 support for. The list should contain most wanted protocols first.
 Protocol names are printable \s-1ASCII\s0 strings, for example \*(L"http/1.1\*(R" or
diff --git a/secure/usr.bin/openssl/man/s_server.1 b/secure/usr.bin/openssl/man/s_server.1
index 0dd0d4bedea9..dc951e0357ad 100644
--- a/secure/usr.bin/openssl/man/s_server.1
+++ b/secure/usr.bin/openssl/man/s_server.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "S_SERVER 1"
-.TH S_SERVER 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH S_SERVER 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -197,6 +197,7 @@ s_server \- SSL/TLS server program
 [\fB\-status_verbose\fR]
 [\fB\-status_timeout nsec\fR]
 [\fB\-status_url url\fR]
+[\fB\-alpn protocols\fR]
 [\fB\-nextprotoneg protocols\fR]
 .SH "DESCRIPTION"
 .IX Header "DESCRIPTION"
@@ -412,9 +413,13 @@ sets the timeout for \s-1OCSP\s0 response to \fBnsec\fR seconds.
 sets a fallback responder \s-1URL\s0 to use if no responder \s-1URL\s0 is present in the
 server certificate. Without this option an error is returned if the server
 certificate does not contain a responder address.
-.IP "\fB\-nextprotoneg protocols\fR" 4
-.IX Item "-nextprotoneg protocols"
-enable Next Protocol Negotiation \s-1TLS\s0 extension and provide a
+.IP "\fB\-alpn protocols\fR, \fB\-nextprotoneg protocols\fR" 4
+.IX Item "-alpn protocols, -nextprotoneg protocols"
+these flags enable the 
+Enable the Application-Layer Protocol Negotiation or Next Protocol
+Negotiation extension, respectively. \s-1ALPN\s0 is the \s-1IETF\s0 standard and
+replaces \s-1NPN.\s0
+The \fBprotocols\fR list is a
 comma-separated list of supported protocol names.
 The list should contain most wanted protocols first.
 Protocol names are printable \s-1ASCII\s0 strings, for example \*(L"http/1.1\*(R" or
diff --git a/secure/usr.bin/openssl/man/s_time.1 b/secure/usr.bin/openssl/man/s_time.1
index 17f1f12e8021..b58f7b5caffe 100644
--- a/secure/usr.bin/openssl/man/s_time.1
+++ b/secure/usr.bin/openssl/man/s_time.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "S_TIME 1"
-.TH S_TIME 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH S_TIME 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/sess_id.1 b/secure/usr.bin/openssl/man/sess_id.1
index 69ada284613c..b08257b44c3d 100644
--- a/secure/usr.bin/openssl/man/sess_id.1
+++ b/secure/usr.bin/openssl/man/sess_id.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SESS_ID 1"
-.TH SESS_ID 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SESS_ID 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/smime.1 b/secure/usr.bin/openssl/man/smime.1
index cb6b187b31ef..c696a6725852 100644
--- a/secure/usr.bin/openssl/man/smime.1
+++ b/secure/usr.bin/openssl/man/smime.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SMIME 1"
-.TH SMIME 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SMIME 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -183,6 +183,9 @@ The meaning of the other options varies according to the operation type.
 .IX Item "-encrypt"
 encrypt mail for the given recipient certificates. Input file is the message
 to be encrypted. The output file is the encrypted mail in \s-1MIME\s0 format.
+.Sp
+Note that no revocation check is done for the recipient cert, so if that
+key has been compromised, others may be able to decrypt the text.
 .IP "\fB\-decrypt\fR" 4
 .IX Item "-decrypt"
 decrypt mail using the supplied certificate and private key. Expects an
diff --git a/secure/usr.bin/openssl/man/speed.1 b/secure/usr.bin/openssl/man/speed.1
index 39f01501b7da..14d849da3d4a 100644
--- a/secure/usr.bin/openssl/man/speed.1
+++ b/secure/usr.bin/openssl/man/speed.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SPEED 1"
-.TH SPEED 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SPEED 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/spkac.1 b/secure/usr.bin/openssl/man/spkac.1
index 4cf9babddd39..7c1ce8cfde14 100644
--- a/secure/usr.bin/openssl/man/spkac.1
+++ b/secure/usr.bin/openssl/man/spkac.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "SPKAC 1"
-.TH SPKAC 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH SPKAC 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/ts.1 b/secure/usr.bin/openssl/man/ts.1
index 37716b28bec5..c5c3d3e0c179 100644
--- a/secure/usr.bin/openssl/man/ts.1
+++ b/secure/usr.bin/openssl/man/ts.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "TS 1"
-.TH TS 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH TS 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/tsget.1 b/secure/usr.bin/openssl/man/tsget.1
index 42ca602e992e..9def7ade66f2 100644
--- a/secure/usr.bin/openssl/man/tsget.1
+++ b/secure/usr.bin/openssl/man/tsget.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "TSGET 1"
-.TH TSGET 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH TSGET 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/verify.1 b/secure/usr.bin/openssl/man/verify.1
index 3f38c297db70..b8479767809a 100644
--- a/secure/usr.bin/openssl/man/verify.1
+++ b/secure/usr.bin/openssl/man/verify.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "VERIFY 1"
-.TH VERIFY 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH VERIFY 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -163,6 +163,7 @@ verify \- Utility to verify certificates.
 [\fB\-use_deltas\fR]
 [\fB\-policy_print\fR]
 [\fB\-no_alt_chains\fR]
+[\fB\-allow_proxy_certs\fR]
 [\fB\-untrusted file\fR]
 [\fB\-help\fR]
 [\fB\-issuer_checks\fR]
@@ -253,6 +254,9 @@ trusted, then OpenSSL will continue to check to see if an alternative chain can
 be found that is trusted. With this option that behaviour is suppressed so that
 only the first chain found is ever used. Using this option will force the
 behaviour to match that of previous OpenSSL versions.
+.IP "\fB\-allow_proxy_certs\fR" 4
+.IX Item "-allow_proxy_certs"
+Allow the verification of proxy certificates.
 .IP "\fB\-trusted file\fR" 4
 .IX Item "-trusted file"
 A file of additional trusted certificates. The file should contain multiple
diff --git a/secure/usr.bin/openssl/man/version.1 b/secure/usr.bin/openssl/man/version.1
index affdffa10bec..0a9e0a032377 100644
--- a/secure/usr.bin/openssl/man/version.1
+++ b/secure/usr.bin/openssl/man/version.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "VERSION 1"
-.TH VERSION 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH VERSION 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
diff --git a/secure/usr.bin/openssl/man/x509.1 b/secure/usr.bin/openssl/man/x509.1
index 002173075396..bd61c2e0a479 100644
--- a/secure/usr.bin/openssl/man/x509.1
+++ b/secure/usr.bin/openssl/man/x509.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509 1"
-.TH X509 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -658,8 +658,8 @@ print an error message for unsupported certificate extensions.
 hex dump unsupported extensions.
 .IP "\fBca_default\fR" 4
 .IX Item "ca_default"
-the value used by the \fBca\fR utility, equivalent to \fBno_issuer\fR, \fBno_pubkey\fR, \fBno_header\fR,
-\&\fBno_version\fR, \fBno_sigdump\fR and \fBno_signame\fR.
+the value used by the \fBca\fR utility, equivalent to \fBno_issuer\fR, \fBno_pubkey\fR,
+\&\fBno_header\fR, and \fBno_version\fR.
 .SH "EXAMPLES"
 .IX Header "EXAMPLES"
 Note: in these examples the '\e' means the example should be all on one
diff --git a/secure/usr.bin/openssl/man/x509v3_config.1 b/secure/usr.bin/openssl/man/x509v3_config.1
index 054e3ed4c524..e32533b41ef6 100644
--- a/secure/usr.bin/openssl/man/x509v3_config.1
+++ b/secure/usr.bin/openssl/man/x509v3_config.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.30)
+.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.28)
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -133,7 +133,7 @@
 .\" ========================================================================
 .\"
 .IX Title "X509V3_CONFIG 1"
-.TH X509V3_CONFIG 1 "2016-05-03" "1.0.2h" "OpenSSL"
+.TH X509V3_CONFIG 1 "2016-09-22" "1.0.2i" "OpenSSL"
 .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
 .\" way too many mistakes in technical documents.
 .if n .ad l
@@ -244,7 +244,7 @@ Examples:
 This extensions consists of a list of usages indicating purposes for which
 the certificate public key can be used for,
 .PP
-These can either be object short names of the dotted numerical form of OIDs.
+These can either be object short names or the dotted numerical form of OIDs.
 While any \s-1OID\s0 can be used only certain values make sense. In particular the
 following \s-1PKIX, NS\s0 and \s-1MS\s0 values are meaningful:
 .PP
diff --git a/share/man/man4/cloudabi.4 b/share/man/man4/cloudabi.4
index 7652b0d055fb..a387c77ce66e 100644
--- a/share/man/man4/cloudabi.4
+++ b/share/man/man4/cloudabi.4
@@ -22,7 +22,7 @@
 .\" SUCH DAMAGE.
 .\"
 .\" $FreeBSD$
-.Dd August 24, 2016
+.Dd September 22, 2016
 .Dt CLOUDABI 4
 .Os
 .Sh NAME
@@ -84,7 +84,7 @@ module can be loaded on any architecture supported by
 .Fx ,
 the
 .Nm cloudabi32
-module is only available on i386 and amd64.
+module is only available on amd64, armv6 and i386.
 The same holds for the
 .Nm cloudabi64
 module,
diff --git a/share/man/man4/intpm.4 b/share/man/man4/intpm.4
index 92ad89b681aa..4ece9359c03f 100644
--- a/share/man/man4/intpm.4
+++ b/share/man/man4/intpm.4
@@ -24,7 +24,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd July 20, 2016
+.Dd September 22, 2016
 .Dt INTPM 4
 .Os
 .Sh NAME
@@ -59,7 +59,9 @@ AMD SB600/7x0/8x0/9x0 southbridges
 .It
 AMD Axx/Hudson/Bolton FCHs
 .It
-AMD FCH integrated into Family 16h Models 00h-0Fh Processors
+AMD FCH integrated into Family 15h Models 60h-6Fh, 70h-7Fh Processors
+.It
+AMD FCH integrated into Family 16h Models 00h-0Fh, 30h-3Fh Processors
 .El
 .Sh SEE ALSO
 .Xr amdpm 4 ,
diff --git a/share/man/man4/re.4 b/share/man/man4/re.4
index e5fc7b05a0d2..70c932afb4c0 100644
--- a/share/man/man4/re.4
+++ b/share/man/man4/re.4
@@ -30,7 +30,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd January 26, 2011
+.Dd September 21, 2016
 .Dt RE 4
 .Os
 .Sh NAME
@@ -165,6 +165,8 @@ LinkSys EG1032 (32-bit PCI)
 .It
 PLANEX COMMUNICATIONS Inc.\& GN-1200TC (8169S)
 .It
+TP-Link TG-3468 v2 Gigabit Ethernet (8168)
+.It
 USRobotics USR997902 Gigabit Ethernet (8169S)
 .It
 Xterasys XN-152 10/100/1000 NIC (8169)
diff --git a/share/man/man5/src.conf.5 b/share/man/man5/src.conf.5
index 586acae3d4cd..730651654e20 100644
--- a/share/man/man5/src.conf.5
+++ b/share/man/man5/src.conf.5
@@ -1,7 +1,7 @@
 .\" DO NOT EDIT-- this file is automatically generated.
 .\" from FreeBSD: head/tools/build/options/makeman 292283 2015-12-15 18:42:30Z bdrewery
 .\" $FreeBSD$
-.Dd August 23, 2016
+.Dd September 21, 2016
 .Dt SRC.CONF 5
 .Os
 .Sh NAME
@@ -1089,7 +1089,7 @@ Set to not build utilities for manual pages,
 .Xr manctl 8 ,
 and related support files.
 .It Va WITH_META_MODE
-.\" from FreeBSD: head/tools/build/options/WITH_META_MODE 301889 2016-06-14 16:20:25Z bdrewery
+.\" from FreeBSD: head/tools/build/options/WITH_META_MODE 306145 2016-09-21 21:32:05Z bdrewery
 Creates
 .Xr make 1
 meta files when building, which can provide a reliable incremental build when
@@ -1141,9 +1141,6 @@ This option originally invoked a different build system but that was renamed
 to
 .Va WITH_DIRDEPS_BUILD .
 .Pp
-Currently this also enforces
-.Va WITHOUT_SYSTEM_COMPILER .
-.Pp
 This must be set in the environment, make command line, or
 .Pa /etc/src-env.conf ,
 not
@@ -1319,11 +1316,10 @@ This includes
 .Xr rlogin 1 ,
 .Xr rsh 1 ,
 etc.
-.It Va WITHOUT_RCS
-.\" from FreeBSD: head/tools/build/options/WITHOUT_RCS 275138 2014-11-26 20:43:09Z gjb
-Set to not build
-.Xr rcs 1 ,
-.Xr etcupdate 8 ,
+.It Va WITH_RCS
+.\" from FreeBSD: head/tools/build/options/WITH_RCS 305931 2016-09-18 15:01:11Z bapt
+Set to build
+.Xr rcs 1
 and related utilities.
 .It Va WITHOUT_RESCUE
 .\" from FreeBSD: head/tools/build/options/WITHOUT_RESCUE 156932 2006-03-21 07:50:50Z ru
diff --git a/share/man/man8/rc.subr.8 b/share/man/man8/rc.subr.8
index 47959f3ea0a5..2d49c3547cfb 100644
--- a/share/man/man8/rc.subr.8
+++ b/share/man/man8/rc.subr.8
@@ -29,7 +29,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd February 4, 2016
+.Dd September 18, 2016
 .Dt RC.SUBR 8
 .Os
 .Sh NAME
@@ -105,17 +105,7 @@ Make a backup copy of
 .Ar file
 into
 .Ar current .
-If the
-.Xr rc.conf 5
-variable
-.Va backup_uses_rcs
-is
-.Dq Li YES ,
-use
-.Xr rcs 1
-to archive the previous version of
-.Ar current ,
-otherwise save the previous version of
+Save the previous version of
 .Ar current
 as
 .Ar backup .
@@ -129,9 +119,7 @@ may be one of the following:
 .Ar file
 is now being backed up by or possibly re-entered into this backup mechanism.
 .Ar current
-is created, and if necessary, the
-.Xr rcs 1
-files are created as well.
+is created.
 .It Cm update
 .Ar file
 has changed and needs to be backed up.
@@ -139,9 +127,6 @@ If
 .Ar current
 exists, it is copied to
 .Ar backup
-or checked into
-.Xr rcs 1
-(if the repository file is old),
 and then
 .Ar file
 is copied to
@@ -149,12 +134,6 @@ is copied to
 .It Cm remove
 .Ar file
 is no longer being tracked by this backup mechanism.
-If
-.Xr rcs 1
-is being used, an empty file is checked in and
-.Ar current
-is removed,
-otherwise
 .Ar current
 is moved to
 .Ar backup .
diff --git a/share/man/man9/ieee80211_radiotap.9 b/share/man/man9/ieee80211_radiotap.9
index 3a6700710519..cb8f3acc47b5 100644
--- a/share/man/man9/ieee80211_radiotap.9
+++ b/share/man/man9/ieee80211_radiotap.9
@@ -263,7 +263,6 @@ struct wi_rx_radiotap_header {
 and transmit definitions for the Atheros driver:
 .Bd -literal -offset indent
 #define ATH_TX_RADIOTAP_PRESENT (               \\
-        (1 << IEEE80211_RADIOTAP_TSFT)          | \\
         (1 << IEEE80211_RADIOTAP_FLAGS)         | \\
         (1 << IEEE80211_RADIOTAP_RATE)          | \\
         (1 << IEEE80211_RADIOTAP_DBM_TX_POWER)  | \\
@@ -273,7 +272,6 @@ and transmit definitions for the Atheros driver:
 
 struct ath_tx_radiotap_header {
         struct ieee80211_radiotap_header wt_ihdr;
-        uint64_t       wt_tsf;
         uint8_t        wt_flags;
         uint8_t        wt_rate;
         uint8_t        wt_txpower;
diff --git a/share/man/man9/owll.9 b/share/man/man9/owll.9
index 2737eccd308c..cbe38f1d66b5 100644
--- a/share/man/man9/owll.9
+++ b/share/man/man9/owll.9
@@ -24,7 +24,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd July 20, 2015
+.Dd September 22, 2016
 .Dt OWLL 9
 .Os
 .Sh NAME
@@ -52,7 +52,7 @@ Semiconductor 1-Wire from upper layers of the protocol.
 .Fn OWLL_WRITE_ONE
 and
 .Fn OWLL_WRITE_ZERO
-writes a one bitor a zero bit respectively on the 1-Wire bus.
+writes a one bit or a zero bit respectively on the 1-Wire bus.
 .Pp
 .Fn OWLL_READ_DATA
 reads one bit from the 1-Wire bus.
diff --git a/share/man/man9/style.9 b/share/man/man9/style.9
index 946df1486372..4ddcc0ac3cbf 100644
--- a/share/man/man9/style.9
+++ b/share/man/man9/style.9
@@ -118,17 +118,21 @@ Leave another blank line before the header files.
 .Pp
 Kernel include files (i.e.\&
 .Pa sys/*.h )
-come first; normally, include
+come first sorted alphabetically where possible.
+Include
 .In sys/types.h
 OR
 .In sys/param.h ,
-but not both.
+but not both and include it first.
 .In sys/types.h
 includes
 .In sys/cdefs.h ,
 and it is okay to depend on that.
 .Bd -literal
 #include <sys/types.h>	/* Non-local includes in angle brackets. */
+#include <sys/endian.h>
+#include <sys/lock.h>
+#include <sys/queue.h>
 .Ed
 .Pp
 For a network program, put the network include files next.
diff --git a/share/misc/committers-ports.dot b/share/misc/committers-ports.dot
index 6908d33b26be..fe23d0b0bcd2 100644
--- a/share/misc/committers-ports.dot
+++ b/share/misc/committers-ports.dot
@@ -129,6 +129,7 @@ joerg [label="Joerg Wunsch\njoerg@FreeBSD.org\n1994/08/22"]
 johans [label="Johan Selst\njohans@FreeBSD.org\n2006/04/01"]
 josef [label="Josef El-Rayes\njosef@FreeBSD.org\n2004/12/20"]
 jpaetzel [label="Josh Paetzel\njpaetzel@FreeBSD.org\n2008/09/05"]
+jrm [label="Joseph R. Mingrone\njrm@FreeBSD.org\n2016/09/17"]
 jsa [label="Joseph S. Atkinson\njsa@FreeBSD.org\n2010/07/15"]
 junovitch [label="Jason Unovitch\njunovitch@FreeBSD.org\n2015/07/27"]
 jylefort [label="Jean-Yves Lefort\njylefort@FreeBSD.org\n2005/04/12"]
@@ -258,6 +259,8 @@ ade -> jpaetzel
 ahze -> shaun
 ahze -> tmclaugh
 
+amdmi3 -> jrm
+
 araujo -> lippe
 araujo -> pclin
 araujo -> pgollucci
@@ -577,6 +580,7 @@ stas -> araujo
 steve -> netchild
 
 swills -> feld
+swills -> jrm
 swills -> milki
 swills -> pclin
 swills -> robak
diff --git a/share/misc/organization.dot b/share/misc/organization.dot
index 82f862235e02..5877593347d6 100644
--- a/share/misc/organization.dot
+++ b/share/misc/organization.dot
@@ -30,7 +30,7 @@ coresecretary [label="Core Team Secretary\ncore-secretary@FreeBSD.org\nmatthew"]
 doccommitters [label="Doc/www Committers\ndoc-committers@FreeBSD.org"]
 doceng [label="Documentation Engineering Team\ndoceng@FreeBSD.org\ngjb, blackend,\ngabor, hrs"]
 portscommitters [label="Ports Committers\nports-committers@FreeBSD.org"]
-portmgr [label="Port Management Team\nportmgr@FreeBSD.org\nantoine, bapt, bdrewery,\nmat, swills"]
+portmgr [label="Port Management Team\nportmgr@FreeBSD.org\nantoine, bdrewery,\nmat, swills"]
 portmgrsecretary [label="Port Management Team Secretary\nportmgr-secretary@FreeBSD.org\nrene"]
 re [label="Primary Release Engineering Team\nre@FreeBSD.org\nkib, blackend, jpaetzel, hrs, kensmith"]
 secteam [label="Security Team\nsecteam@FreeBSD.org\ndelphij,\ndes, gavin, gjb,\nglebius, remko"]
diff --git a/share/mk/bsd.dep.mk b/share/mk/bsd.dep.mk
index d3591b9eafbe..c5d242f166e2 100644
--- a/share/mk/bsd.dep.mk
+++ b/share/mk/bsd.dep.mk
@@ -152,8 +152,8 @@ ${_D}.o: ${_DSRC} ${OBJS:S/^${_D}.o$//}
 	@rm -f ${.TARGET}
 	${DTRACE} ${DTRACEFLAGS} -G -o ${.TARGET} -s ${.ALLSRC:N*.h}
 .if defined(LIB)
-CLEANFILES+= ${_D}.So ${_D}.po
-${_D}.So: ${_DSRC} ${SOBJS:S/^${_D}.So$//}
+CLEANFILES+= ${_D}.pico ${_D}.po
+${_D}.pico: ${_DSRC} ${SOBJS:S/^${_D}.pico$//}
 	@rm -f ${.TARGET}
 	${DTRACE} ${DTRACEFLAGS} -G -o ${.TARGET} -s ${.ALLSRC:N*.h}
 ${_D}.po: ${_DSRC} ${POBJS:S/^${_D}.po$//}
diff --git a/share/mk/bsd.lib.mk b/share/mk/bsd.lib.mk
index ffb03c020ff6..f3b9f146d282 100644
--- a/share/mk/bsd.lib.mk
+++ b/share/mk/bsd.lib.mk
@@ -77,9 +77,9 @@ CTFFLAGS+= -g
 .include <bsd.libnames.mk>
 
 # prefer .s to a .c, add .po, remove stuff not used in the BSD libraries
-# .So used for PIC object files
+# .pico used for PIC object files
 .SUFFIXES:
-.SUFFIXES: .out .o .po .So .S .asm .s .c .cc .cpp .cxx .C .f .y .l .ln
+.SUFFIXES: .out .o .po .pico .S .asm .s .c .cc .cpp .cxx .C .f .y .l .ln
 
 .if !defined(PICFLAG)
 .if ${MACHINE_CPUARCH} == "sparc64"
@@ -99,7 +99,7 @@ PO_FLAG=-pg
 	${CC} ${PO_FLAG} ${STATIC_CFLAGS} ${PO_CFLAGS} -c ${.IMPSRC} -o ${.TARGET}
 	${CTFCONVERT_CMD}
 
-.c.So:
+.c.pico:
 	${CC} ${PICFLAG} -DPIC ${SHARED_CFLAGS} ${CFLAGS} -c ${.IMPSRC} -o ${.TARGET}
 	${CTFCONVERT_CMD}
 
@@ -109,18 +109,18 @@ PO_FLAG=-pg
 .cc.po .C.po .cpp.po .cxx.po:
 	${CXX} ${PO_FLAG} ${STATIC_CXXFLAGS} ${PO_CXXFLAGS} -c ${.IMPSRC} -o ${.TARGET}
 
-.cc.So .C.So .cpp.So .cxx.So:
+.cc.pico .C.pico .cpp.pico .cxx.pico:
 	${CXX} ${PICFLAG} -DPIC ${SHARED_CXXFLAGS} ${CXXFLAGS} -c ${.IMPSRC} -o ${.TARGET}
 
 .f.po:
 	${FC} -pg ${FFLAGS} -o ${.TARGET} -c ${.IMPSRC}
 	${CTFCONVERT_CMD}
 
-.f.So:
+.f.pico:
 	${FC} ${PICFLAG} -DPIC ${FFLAGS} -o ${.TARGET} -c ${.IMPSRC}
 	${CTFCONVERT_CMD}
 
-.s.po .s.So:
+.s.po .s.pico:
 	${AS} ${AFLAGS} -o ${.TARGET} ${.IMPSRC}
 	${CTFCONVERT_CMD}
 
@@ -129,7 +129,7 @@ PO_FLAG=-pg
 	    ${ACFLAGS} -c ${.IMPSRC} -o ${.TARGET}
 	${CTFCONVERT_CMD}
 
-.asm.So:
+.asm.pico:
 	${CC:N${CCACHE_BIN}} -x assembler-with-cpp ${PICFLAG} -DPIC \
 	    ${CFLAGS} ${ACFLAGS} -c ${.IMPSRC} -o ${.TARGET}
 	${CTFCONVERT_CMD}
@@ -139,7 +139,7 @@ PO_FLAG=-pg
 	    -o ${.TARGET}
 	${CTFCONVERT_CMD}
 
-.S.So:
+.S.pico:
 	${CC:N${CCACHE_BIN}} ${PICFLAG} -DPIC ${CFLAGS} ${ACFLAGS} \
 	    -c ${.IMPSRC} -o ${.TARGET}
 	${CTFCONVERT_CMD}
@@ -207,7 +207,7 @@ lib${LIB_PRIVATE}${LIB}_p.a: ${POBJS}
 
 .if defined(SHLIB_NAME) || \
     defined(INSTALL_PIC_ARCHIVE) && defined(LIB) && !empty(LIB)
-SOBJS+=		${OBJS:.o=.So}
+SOBJS+=		${OBJS:.o=.pico}
 DEPENDOBJS+=	${SOBJS}
 CLEANFILES+=	${SOBJS}
 .endif
@@ -430,7 +430,7 @@ OBJS_DEPEND_GUESS.${_S:R}.po+=	${_S}
 .if defined(SHLIB_NAME) || \
     defined(INSTALL_PIC_ARCHIVE) && defined(LIB) && !empty(LIB)
 .for _S in ${SRCS:N*.[hly]}
-OBJS_DEPEND_GUESS.${_S:R}.So+=	${_S}
+OBJS_DEPEND_GUESS.${_S:R}.pico+=	${_S}
 .endfor
 .endif
 
diff --git a/share/mk/meta.autodep.mk b/share/mk/meta.autodep.mk
index 7095b1f21a40..7df58bc9d0eb 100644
--- a/share/mk/meta.autodep.mk
+++ b/share/mk/meta.autodep.mk
@@ -23,7 +23,7 @@ __${_this}__: .NOTMAIN
 
 .if defined(SRCS)
 # it would be nice to be able to query .SUFFIXES
-OBJ_EXTENSIONS+= .o .po .lo .So
+OBJ_EXTENSIONS+= .o .po .lo .pico
 
 # explicit dependencies help short-circuit .SUFFIX searches
 SRCS_DEP_FILTER+= N*.[hly]
@@ -179,7 +179,7 @@ DEPEND_SUFFIXES += .c .h .cpp .hpp .cxx .hxx .cc .hh
 	@case "${.MAKE.META.FILES:T:M*.po.*}" in \
 	*.po.*) mv $@.${.MAKE.PID} $@;; \
 	*) { cat $@.${.MAKE.PID}; \
-	sed 's,\.So:,.o:,;s,\.o:,.po:,' $@.${.MAKE.PID}; } | sort -u > $@; \
+	sed 's,\.pico:,.o:,;s,\.o:,.po:,' $@.${.MAKE.PID}; } | sort -u > $@; \
 	rm -f $@.${.MAKE.PID};; \
 	esac
 .else
@@ -244,7 +244,7 @@ META_FILES = *.meta
 .elif ${OPTIMIZE_OBJECT_META_FILES:Uno:tl} == "no"
 META_FILES = ${.MAKE.META.FILES:T:N.depend*:O:u}
 .else
-# if we have 1000's of .o.meta, .So.meta etc we need only look at one set
+# if we have 1000's of .o.meta, .pico.meta etc we need only look at one set
 # it is left as an exercise for the reader to work out what this does
 META_FILES = ${.MAKE.META.FILES:T:N.depend*:N*o.meta:O:u} \
 	${.MAKE.META.FILES:T:M*.${.MAKE.META.FILES:M*o.meta:R:E:O:u:[1]}.meta:O:u}
diff --git a/share/mk/src.opts.mk b/share/mk/src.opts.mk
index 436303c7c70f..5d72237a42fd 100644
--- a/share/mk/src.opts.mk
+++ b/share/mk/src.opts.mk
@@ -147,7 +147,6 @@ __DEFAULT_YES_OPTIONS = \
     RADIUS_SUPPORT \
     RCMDS \
     RBOOTD \
-    RCS \
     RESCUE \
     ROUTED \
     SENDMAIL \
@@ -187,6 +186,7 @@ __DEFAULT_NO_OPTIONS = \
     NAND \
     OFED \
     OPENLDAP \
+    RCS \
     SHARED_TOOLCHAIN \
     SORT_THREADS \
     SVN \
@@ -289,6 +289,10 @@ MK_${var}:=	no
 # Force some options off if their dependencies are off.
 # Order is somewhat important.
 #
+.if !${COMPILER_FEATURES:Mc++11}
+MK_LLVM_LIBUNWIND:=	no
+.endif
+
 .if ${MK_LIBPTHREAD} == "no"
 MK_LIBTHR:=	no
 .endif
diff --git a/sys/amd64/amd64/efirt.c b/sys/amd64/amd64/efirt.c
new file mode 100644
index 000000000000..626cfb0232b0
--- /dev/null
+++ b/sys/amd64/amd64/efirt.c
@@ -0,0 +1,595 @@
+/*-
+ * Copyright (c) 2004 Marcel Moolenaar
+ * Copyright (c) 2001 Doug Rabson
+ * Copyright (c) 2016 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Portions of this software were developed by Konstantin Belousov
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/efi.h>
+#include <sys/kernel.h>
+#include <sys/linker.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/clock.h>
+#include <sys/proc.h>
+#include <sys/rwlock.h>
+#include <sys/sched.h>
+#include <sys/sysctl.h>
+#include <sys/systm.h>
+#include <machine/fpu.h>
+#include <machine/efi.h>
+#include <machine/metadata.h>
+#include <machine/md_var.h>
+#include <machine/smp.h>
+#include <machine/vmparam.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+#include <vm/vm_pager.h>
+
+static struct efi_systbl *efi_systbl;
+static struct efi_cfgtbl *efi_cfgtbl;
+static struct efi_rt *efi_runtime;
+
+static int efi_status2err[25] = {
+	0,		/* EFI_SUCCESS */
+	ENOEXEC,	/* EFI_LOAD_ERROR */
+	EINVAL,		/* EFI_INVALID_PARAMETER */
+	ENOSYS,		/* EFI_UNSUPPORTED */
+	EMSGSIZE, 	/* EFI_BAD_BUFFER_SIZE */
+	EOVERFLOW,	/* EFI_BUFFER_TOO_SMALL */
+	EBUSY,		/* EFI_NOT_READY */
+	EIO,		/* EFI_DEVICE_ERROR */
+	EROFS,		/* EFI_WRITE_PROTECTED */
+	EAGAIN,		/* EFI_OUT_OF_RESOURCES */
+	EIO,		/* EFI_VOLUME_CORRUPTED */
+	ENOSPC,		/* EFI_VOLUME_FULL */
+	ENXIO,		/* EFI_NO_MEDIA */
+	ESTALE,		/* EFI_MEDIA_CHANGED */
+	ENOENT,		/* EFI_NOT_FOUND */
+	EACCES,		/* EFI_ACCESS_DENIED */
+	ETIMEDOUT,	/* EFI_NO_RESPONSE */
+	EADDRNOTAVAIL,	/* EFI_NO_MAPPING */
+	ETIMEDOUT,	/* EFI_TIMEOUT */
+	EDOOFUS,	/* EFI_NOT_STARTED */
+	EALREADY,	/* EFI_ALREADY_STARTED */
+	ECANCELED,	/* EFI_ABORTED */
+	EPROTO,		/* EFI_ICMP_ERROR */
+	EPROTO,		/* EFI_TFTP_ERROR */
+	EPROTO		/* EFI_PROTOCOL_ERROR */
+};
+
+static int
+efi_status_to_errno(efi_status status)
+{
+	u_long code;
+
+	code = status & 0x3ffffffffffffffful;
+	return (code < nitems(efi_status2err) ? efi_status2err[code] : EDOOFUS);
+}
+
+static struct mtx efi_lock;
+static pml4_entry_t *efi_pml4;
+static vm_object_t obj_1t1_pt;
+static vm_page_t efi_pml4_page;
+
+static void
+efi_destroy_1t1_map(void)
+{
+	vm_page_t m;
+
+	if (obj_1t1_pt != NULL) {
+		VM_OBJECT_RLOCK(obj_1t1_pt);
+		TAILQ_FOREACH(m, &obj_1t1_pt->memq, listq)
+			m->wire_count = 0;
+		atomic_subtract_int(&vm_cnt.v_wire_count,
+		    obj_1t1_pt->resident_page_count);
+		VM_OBJECT_RUNLOCK(obj_1t1_pt);
+		vm_object_deallocate(obj_1t1_pt);
+	}
+
+	obj_1t1_pt = NULL;
+	efi_pml4 = NULL;
+	efi_pml4_page = NULL;
+}
+
+static vm_page_t
+efi_1t1_page(vm_pindex_t idx)
+{
+
+	return (vm_page_grab(obj_1t1_pt, idx, VM_ALLOC_NOBUSY |
+	    VM_ALLOC_WIRED | VM_ALLOC_ZERO));
+}
+
+static pt_entry_t *
+efi_1t1_pte(vm_offset_t va)
+{
+	pml4_entry_t *pml4e;
+	pdp_entry_t *pdpe;
+	pd_entry_t *pde;
+	pt_entry_t *pte;
+	vm_page_t m;
+	vm_pindex_t pml4_idx, pdp_idx, pd_idx;
+	vm_paddr_t mphys;
+
+	pml4_idx = pmap_pml4e_index(va);
+	pml4e = &efi_pml4[pml4_idx];
+	if (*pml4e == 0) {
+		m = efi_1t1_page(1 + pml4_idx);
+		mphys =  VM_PAGE_TO_PHYS(m);
+		*pml4e = mphys | X86_PG_RW | X86_PG_V;
+	} else {
+		mphys = *pml4e & ~PAGE_MASK;
+	}
+
+	pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys);
+	pdp_idx = pmap_pdpe_index(va);
+	pdpe += pdp_idx;
+	if (*pdpe == 0) {
+		m = efi_1t1_page(1 + NPML4EPG + (pml4_idx + 1) * (pdp_idx + 1));
+		mphys =  VM_PAGE_TO_PHYS(m);
+		*pdpe = mphys | X86_PG_RW | X86_PG_V;
+	} else {
+		mphys = *pdpe & ~PAGE_MASK;
+	}
+
+	pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
+	pd_idx = pmap_pde_index(va);
+	pde += pd_idx;
+	if (*pde == 0) {
+		m = efi_1t1_page(1 + NPML4EPG + NPML4EPG * NPDPEPG +
+		    (pml4_idx + 1) * (pdp_idx + 1) * (pd_idx + 1));
+		mphys = VM_PAGE_TO_PHYS(m);
+		*pde = mphys | X86_PG_RW | X86_PG_V;
+	} else {
+		mphys = *pde & ~PAGE_MASK;
+	}
+
+	pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
+	pte += pmap_pte_index(va);
+	KASSERT(*pte == 0, ("va %#jx *pt %#jx", va, *pte));
+
+	return (pte);
+}
+
+static bool
+efi_create_1t1_map(struct efi_md *map, int ndesc, int descsz)
+{
+	struct efi_md *p;
+	pt_entry_t *pte;
+	vm_offset_t va;
+	uint64_t idx;
+	int bits, i, mode;
+
+	obj_1t1_pt = vm_pager_allocate(OBJT_PHYS, NULL, 1 + NPML4EPG +
+	    NPML4EPG * NPDPEPG + NPML4EPG * NPDPEPG * NPDEPG,
+	    VM_PROT_ALL, 0, NULL);
+	VM_OBJECT_WLOCK(obj_1t1_pt);
+	efi_pml4_page = efi_1t1_page(0);
+	VM_OBJECT_WUNLOCK(obj_1t1_pt);
+	efi_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(efi_pml4_page));
+	pmap_pinit_pml4(efi_pml4_page);
+
+	for (i = 0, p = map; i < ndesc; i++, p = efi_next_descriptor(p,
+	    descsz)) {
+		if ((p->md_attr & EFI_MD_ATTR_RT) == 0)
+			continue;
+		if (p->md_virt != NULL) {
+			if (bootverbose)
+				printf("EFI Runtime entry %d is mapped\n", i);
+			goto fail;
+		}
+		if ((p->md_phys & EFI_PAGE_MASK) != 0) {
+			if (bootverbose)
+				printf("EFI Runtime entry %d is not aligned\n",
+				    i);
+			goto fail;
+		}
+		if (p->md_phys + p->md_pages * EFI_PAGE_SIZE < p->md_phys ||
+		    p->md_phys + p->md_pages * EFI_PAGE_SIZE >=
+		    VM_MAXUSER_ADDRESS) {
+			printf("EFI Runtime entry %d is not in mappable for RT:"
+			    "base %#016jx %#jx pages\n",
+			    i, (uintmax_t)p->md_phys,
+			    (uintmax_t)p->md_pages);
+			goto fail;
+		}
+		if ((p->md_attr & EFI_MD_ATTR_WB) != 0)
+			mode = VM_MEMATTR_WRITE_BACK;
+		else if ((p->md_attr & EFI_MD_ATTR_WT) != 0)
+			mode = VM_MEMATTR_WRITE_THROUGH;
+		else if ((p->md_attr & EFI_MD_ATTR_WC) != 0)
+			mode = VM_MEMATTR_WRITE_COMBINING;
+		else if ((p->md_attr & EFI_MD_ATTR_WP) != 0)
+			mode = VM_MEMATTR_WRITE_PROTECTED;
+		else if ((p->md_attr & EFI_MD_ATTR_UC) != 0)
+			mode = VM_MEMATTR_UNCACHEABLE;
+		else {
+			if (bootverbose)
+				printf("EFI Runtime entry %d mapping "
+				    "attributes unsupported\n", i);
+			mode = VM_MEMATTR_UNCACHEABLE;
+		}
+		bits = pmap_cache_bits(kernel_pmap, mode, FALSE) | X86_PG_RW |
+		    X86_PG_V;
+		VM_OBJECT_WLOCK(obj_1t1_pt);
+		for (va = p->md_phys, idx = 0; idx < p->md_pages; idx++,
+		    va += PAGE_SIZE) {
+			pte = efi_1t1_pte(va);
+			pte_store(pte, va | bits);
+		}
+		VM_OBJECT_WUNLOCK(obj_1t1_pt);
+	}
+
+	return (true);
+
+fail:
+	efi_destroy_1t1_map();
+	return (false);
+}
+
+/*
+ * Create an environment for the EFI runtime code call.  The most
+ * important part is creating the required 1:1 physical->virtual
+ * mappings for the runtime segments.  To do that, we manually create
+ * page table which unmap userspace but gives correct kernel mapping.
+ * The 1:1 mappings for runtime segments usually occupy low 4G of the
+ * physical address map.
+ *
+ * The 1:1 mappings were chosen over the SetVirtualAddressMap() EFI RT
+ * service, because there are some BIOSes which fail to correctly
+ * relocate itself on the call, requiring both 1:1 and virtual
+ * mapping.  As result, we must provide 1:1 mapping anyway, so no
+ * reason to bother with the virtual map, and no need to add a
+ * complexity into loader.
+ *
+ * The fpu_kern_enter() call allows firmware to use FPU, as mandated
+ * by the specification.  In particular, CR0.TS bit is cleared.  Also
+ * it enters critical section, giving us neccessary protection against
+ * context switch.
+ *
+ * There is no need to disable interrupts around the change of %cr3,
+ * the kernel mappings are correct, while we only grabbed the
+ * userspace portion of VA.  Interrupts handlers must not access
+ * userspace.  Having interrupts enabled fixes the issue with
+ * firmware/SMM long operation, which would negatively affect IPIs,
+ * esp. TLB shootdown requests.
+ */
+static int
+efi_enter(void)
+{
+	pmap_t curpmap;
+	int error;
+
+	if (efi_runtime == NULL)
+		return (ENXIO);
+	curpmap = PCPU_GET(curpmap);
+	PMAP_LOCK(curpmap);
+	mtx_lock(&efi_lock);
+	error = fpu_kern_enter(curthread, NULL, FPU_KERN_NOCTX);
+	if (error != 0) {
+		PMAP_UNLOCK(curpmap);
+		return (error);
+	}
+	load_cr3(VM_PAGE_TO_PHYS(efi_pml4_page) | (pmap_pcid_enabled ?
+	    curpmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid : 0));
+	/*
+	 * If PCID is enabled, the clear CR3_PCID_SAVE bit in the loaded %cr3
+	 * causes TLB invalidation.
+	 */
+	if (!pmap_pcid_enabled)
+		invltlb();
+	return (0);
+}
+
+static void
+efi_leave(void)
+{
+	pmap_t curpmap;
+
+	curpmap = PCPU_GET(curpmap);
+	load_cr3(curpmap->pm_cr3 | (pmap_pcid_enabled ?
+	    curpmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid : 0));
+	if (!pmap_pcid_enabled)
+		invltlb();
+
+	fpu_kern_leave(curthread, NULL);
+	mtx_unlock(&efi_lock);
+	PMAP_UNLOCK(curpmap);
+}
+
+static int
+efi_init(void)
+{
+	struct efi_map_header *efihdr;
+	struct efi_md *map;
+	caddr_t kmdp;
+	size_t efisz;
+
+	mtx_init(&efi_lock, "efi", NULL, MTX_DEF);
+
+	if (efi_systbl_phys == 0) {
+		if (bootverbose)
+			printf("EFI systbl not available\n");
+		return (ENXIO);
+	}
+	efi_systbl = (struct efi_systbl *)PHYS_TO_DMAP(efi_systbl_phys);
+	if (efi_systbl->st_hdr.th_sig != EFI_SYSTBL_SIG) {
+		efi_systbl = NULL;
+		if (bootverbose)
+			printf("EFI systbl signature invalid\n");
+		return (ENXIO);
+	}
+	efi_cfgtbl = (efi_systbl->st_cfgtbl == 0) ? NULL :
+	    (struct efi_cfgtbl *)efi_systbl->st_cfgtbl;
+	if (efi_cfgtbl == NULL) {
+		if (bootverbose)
+			printf("EFI config table is not present\n");
+	}
+
+	kmdp = preload_search_by_type("elf kernel");
+	if (kmdp == NULL)
+		kmdp = preload_search_by_type("elf64 kernel");
+	efihdr = (struct efi_map_header *)preload_search_info(kmdp,
+	    MODINFO_METADATA | MODINFOMD_EFI_MAP);
+	if (efihdr == NULL) {
+		if (bootverbose)
+			printf("EFI map is not present\n");
+		return (ENXIO);
+	}
+	efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf;
+	map = (struct efi_md *)((uint8_t *)efihdr + efisz);
+	if (efihdr->descriptor_size == 0)
+		return (ENOMEM);
+
+	if (!efi_create_1t1_map(map, efihdr->memory_size /
+	    efihdr->descriptor_size, efihdr->descriptor_size)) {
+		if (bootverbose)
+			printf("EFI cannot create runtime map\n");
+		return (ENOMEM);
+	}
+
+	efi_runtime = (efi_systbl->st_rt == 0) ? NULL :
+	    (struct efi_rt *)efi_systbl->st_rt;
+	if (efi_runtime == NULL) {
+		if (bootverbose)
+			printf("EFI runtime services table is not present\n");
+		efi_destroy_1t1_map();
+		return (ENXIO);
+	}
+
+	return (0);
+}
+
+static void
+efi_uninit(void)
+{
+
+	efi_destroy_1t1_map();
+
+	efi_systbl = NULL;
+	efi_cfgtbl = NULL;
+	efi_runtime = NULL;
+
+	mtx_destroy(&efi_lock);
+}
+
+int
+efi_get_table(struct uuid *uuid, void **ptr)
+{
+	struct efi_cfgtbl *ct;
+	u_long count;
+
+	if (efi_cfgtbl == NULL)
+		return (ENXIO);
+	count = efi_systbl->st_entries;
+	ct = efi_cfgtbl;
+	while (count--) {
+		if (!bcmp(&ct->ct_uuid, uuid, sizeof(*uuid))) {
+			*ptr = (void *)PHYS_TO_DMAP(ct->ct_data);
+			return (0);
+		}
+		ct++;
+	}
+	return (ENOENT);
+}
+
+int
+efi_get_time_locked(struct efi_tm *tm)
+{
+	efi_status status;
+	int error;
+
+	mtx_assert(&resettodr_lock, MA_OWNED);
+	error = efi_enter();
+	if (error != 0)
+		return (error);
+	status = efi_runtime->rt_gettime(tm, NULL);
+	efi_leave();
+	error = efi_status_to_errno(status);
+	return (error);
+}
+
+int
+efi_get_time(struct efi_tm *tm)
+{
+	int error;
+
+	if (efi_runtime == NULL)
+		return (ENXIO);
+	mtx_lock(&resettodr_lock);
+	error = efi_get_time_locked(tm);
+	mtx_unlock(&resettodr_lock);
+	return (error);
+}
+
+int
+efi_reset_system(void)
+{
+	int error;
+
+	error = efi_enter();
+	if (error != 0)
+		return (error);
+	efi_runtime->rt_reset(EFI_RESET_WARM, 0, 0, NULL);
+	efi_leave();
+	return (EIO);
+}
+
+int
+efi_set_time_locked(struct efi_tm *tm)
+{
+	efi_status status;
+	int error;
+
+	mtx_assert(&resettodr_lock, MA_OWNED);
+	error = efi_enter();
+	if (error != 0)
+		return (error);
+	status = efi_runtime->rt_settime(tm);
+	efi_leave();
+	error = efi_status_to_errno(status);
+	return (error);
+}
+
+int
+efi_set_time(struct efi_tm *tm)
+{
+	int error;
+
+	if (efi_runtime == NULL)
+		return (ENXIO);
+	mtx_lock(&resettodr_lock);
+	error = efi_set_time_locked(tm);
+	mtx_unlock(&resettodr_lock);
+	return (error);
+}
+
+int
+efi_var_get(efi_char *name, struct uuid *vendor, uint32_t *attrib,
+    size_t *datasize, void *data)
+{
+	efi_status status;
+	int error;
+
+	error = efi_enter();
+	if (error != 0)
+		return (error);
+	status = efi_runtime->rt_getvar(name, vendor, attrib, datasize, data);
+	efi_leave();
+	error = efi_status_to_errno(status);
+	return (error);
+}
+
+int
+efi_var_nextname(size_t *namesize, efi_char *name, struct uuid *vendor)
+{
+	efi_status status;
+	int error;
+
+	error = efi_enter();
+	if (error != 0)
+		return (error);
+	status = efi_runtime->rt_scanvar(namesize, name, vendor);
+	efi_leave();
+	error = efi_status_to_errno(status);
+	return (error);
+}
+
+int
+efi_var_set(efi_char *name, struct uuid *vendor, uint32_t attrib,
+    size_t datasize, void *data)
+{
+	efi_status status;
+	int error;
+
+	error = efi_enter();
+	if (error != 0)
+		return (error);
+	status = efi_runtime->rt_setvar(name, vendor, attrib, datasize, data);
+	efi_leave();
+	error = efi_status_to_errno(status);
+	return (error);
+}
+
+static int
+efirt_modevents(module_t m, int event, void *arg __unused)
+{
+
+	switch (event) {
+	case MOD_LOAD:
+		return (efi_init());
+		break;
+
+	case MOD_UNLOAD:
+		efi_uninit();
+		return (0);
+
+	case MOD_SHUTDOWN:
+		return (0);
+
+	default:
+		return (EOPNOTSUPP);
+	}
+}
+
+static moduledata_t efirt_moddata = {
+	.name = "efirt",
+	.evhand = efirt_modevents,
+	.priv = NULL,
+};
+DECLARE_MODULE(efirt, efirt_moddata, SI_SUB_VM_CONF, SI_ORDER_ANY);
+MODULE_VERSION(efirt, 1);
+
+/* XXX debug stuff */
+static int
+efi_time_sysctl_handler(SYSCTL_HANDLER_ARGS)
+{
+	struct efi_tm tm;
+	int error, val;
+
+	val = 0;
+	error = sysctl_handle_int(oidp, &val, 0, req);
+	if (error != 0 || req->newptr == NULL)
+		return (error);
+	error = efi_get_time(&tm);
+	if (error == 0) {
+		uprintf("EFI reports: Year %d Month %d Day %d Hour %d Min %d "
+		    "Sec %d\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour,
+		    tm.tm_min, tm.tm_sec);
+	}
+	return (error);
+}
+
+SYSCTL_PROC(_debug, OID_AUTO, efi_time, CTLTYPE_INT | CTLFLAG_RW, NULL, 0,
+    efi_time_sysctl_handler, "I", "");
diff --git a/sys/amd64/amd64/machdep.c b/sys/amd64/amd64/machdep.c
index f6a4a2ef886a..c814f6c796b6 100644
--- a/sys/amd64/amd64/machdep.c
+++ b/sys/amd64/amd64/machdep.c
@@ -188,7 +188,7 @@ struct msgbuf *msgbufp;
  * Physical address of the EFI System Table. Stashed from the metadata hints
  * passed into the kernel and used by the EFI code to call runtime services.
  */
-vm_paddr_t efi_systbl;
+vm_paddr_t efi_systbl_phys;
 
 /* Intel ICH registers */
 #define ICH_PMBASE	0x400
@@ -1056,9 +1056,6 @@ bios_add_smap_entries(struct bios_smap *smapbase, u_int32_t smapsize,
 	}
 }
 
-#define efi_next_descriptor(ptr, size) \
-	((struct efi_md *)(((uint8_t *) ptr) + size))
-
 static void
 add_efi_map_entries(struct efi_map_header *efihdr, vm_paddr_t *physmap,
     int *physmap_idx)
@@ -1091,7 +1088,7 @@ add_efi_map_entries(struct efi_map_header *efihdr, vm_paddr_t *physmap,
 	 * Boot Services API.
 	 */
 	efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf;
-	map = (struct efi_md *)((uint8_t *)efihdr + efisz); 
+	map = (struct efi_md *)((uint8_t *)efihdr + efisz);
 
 	if (efihdr->descriptor_size == 0)
 		return;
@@ -1504,7 +1501,7 @@ native_parse_preload_data(u_int64_t modulep)
 	ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
 	db_fetch_ksymtab(ksym_start, ksym_end);
 #endif
-	efi_systbl = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t);
+	efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t);
 
 	return (kmdp);
 }
diff --git a/sys/amd64/amd64/minidump_machdep.c b/sys/amd64/amd64/minidump_machdep.c
index df04f425100c..442819b35973 100644
--- a/sys/amd64/amd64/minidump_machdep.c
+++ b/sys/amd64/amd64/minidump_machdep.c
@@ -239,10 +239,10 @@ minidumpsys(struct dumperinfo *di)
 		 * page written corresponds to 1GB of space
 		 */
 		pmapsize += PAGE_SIZE;
-		ii = (va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1);
+		ii = pmap_pml4e_index(va);
 		pml4 = (uint64_t *)PHYS_TO_DMAP(KPML4phys) + ii;
 		pdp = (uint64_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
-		i = (va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1);
+		i = pmap_pdpe_index(va);
 		if ((pdp[i] & PG_V) == 0) {
 			va += NBPDP;
 			continue;
@@ -264,7 +264,7 @@ minidumpsys(struct dumperinfo *di)
 
 		pd = (uint64_t *)PHYS_TO_DMAP(pdp[i] & PG_FRAME);
 		for (n = 0; n < NPDEPG; n++, va += NBPDR) {
-			j = (va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1);
+			j = pmap_pde_index(va);
 
 			if ((pd[j] & PG_V) == 0)
 				continue;
@@ -368,10 +368,10 @@ minidumpsys(struct dumperinfo *di)
 	bzero(fakepd, sizeof(fakepd));
 	for (va = VM_MIN_KERNEL_ADDRESS; va < MAX(KERNBASE + nkpt * NBPDR,
 	    kernel_vm_end); va += NBPDP) {
-		ii = (va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1);
+		ii = pmap_pml4e_index(va);
 		pml4 = (uint64_t *)PHYS_TO_DMAP(KPML4phys) + ii;
 		pdp = (uint64_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
-		i = (va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1);
+		i = pmap_pdpe_index(va);
 
 		/* We always write a page, even if it is zero */
 		if ((pdp[i] & PG_V) == 0) {
diff --git a/sys/amd64/amd64/pmap.c b/sys/amd64/amd64/pmap.c
index b9fd42de656c..63042e41dd14 100644
--- a/sys/amd64/amd64/pmap.c
+++ b/sys/amd64/amd64/pmap.c
@@ -673,35 +673,6 @@ pmap_pde_pindex(vm_offset_t va)
 }
 
 
-/* Return various clipped indexes for a given VA */
-static __inline vm_pindex_t
-pmap_pte_index(vm_offset_t va)
-{
-
-	return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
-}
-
-static __inline vm_pindex_t
-pmap_pde_index(vm_offset_t va)
-{
-
-	return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
-}
-
-static __inline vm_pindex_t
-pmap_pdpe_index(vm_offset_t va)
-{
-
-	return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
-}
-
-static __inline vm_pindex_t
-pmap_pml4e_index(vm_offset_t va)
-{
-
-	return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
-}
-
 /* Return a pointer to the PML4 slot that corresponds to a VA */
 static __inline pml4_entry_t *
 pmap_pml4e(pmap_t pmap, vm_offset_t va)
@@ -1353,7 +1324,7 @@ pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
  * Determine the appropriate bits to set in a PTE or PDE for a specified
  * caching mode.
  */
-static int
+int
 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
 {
 	int cache_bits, pat_flag, pat_idx;
@@ -2374,6 +2345,29 @@ pmap_pinit0(pmap_t pmap)
 	CPU_FILL(&kernel_pmap->pm_active);
 }
 
+void
+pmap_pinit_pml4(vm_page_t pml4pg)
+{
+	pml4_entry_t *pm_pml4;
+	int i;
+
+	pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
+
+	/* Wire in kernel global address entries. */
+	for (i = 0; i < NKPML4E; i++) {
+		pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
+		    X86_PG_V | PG_U;
+	}
+	for (i = 0; i < ndmpdpphys; i++) {
+		pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
+		    X86_PG_V | PG_U;
+	}
+
+	/* install self-referential address mapping entry(s) */
+	pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
+	    X86_PG_A | X86_PG_M;
+}
+
 /*
  * Initialize a preallocated and zeroed pmap structure,
  * such as one in a vmspace structure.
@@ -2410,20 +2404,7 @@ pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
 	 */
 	if ((pmap->pm_type = pm_type) == PT_X86) {
 		pmap->pm_cr3 = pml4phys;
-
-		/* Wire in kernel global address entries. */
-		for (i = 0; i < NKPML4E; i++) {
-			pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) |
-			    X86_PG_RW | X86_PG_V | PG_U;
-		}
-		for (i = 0; i < ndmpdpphys; i++) {
-			pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) |
-			    X86_PG_RW | X86_PG_V | PG_U;
-		}
-
-		/* install self-referential address mapping entry(s) */
-		pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) |
-		    X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
+		pmap_pinit_pml4(pml4pg);
 	}
 
 	pmap->pm_root.rt_root = 0;
diff --git a/sys/amd64/conf/NOTES b/sys/amd64/conf/NOTES
index 2c3ca3e78d03..bafaef55a7aa 100644
--- a/sys/amd64/conf/NOTES
+++ b/sys/amd64/conf/NOTES
@@ -592,6 +592,9 @@ options 	ENABLE_ALART		# Control alarm on Intel intpm driver
 #
 options 	NKPT=31
 
+# EFI Runtime Services support (not functional yet).
+options 	EFIRT
+
 
 #####################################################################
 # ABI Emulation
diff --git a/sys/amd64/include/cpufunc.h b/sys/amd64/include/cpufunc.h
index f2348739d6d9..4b7df46ce9c6 100644
--- a/sys/amd64/include/cpufunc.h
+++ b/sys/amd64/include/cpufunc.h
@@ -645,12 +645,36 @@ load_gs(u_short sel)
 #endif
 
 static __inline void
+bare_lgdt(struct region_descriptor *addr)
+{
+	__asm __volatile("lgdt (%0)" : : "r" (addr));
+}
+
+static __inline void
+sgdt(struct region_descriptor *addr)
+{
+	char *loc;
+
+	loc = (char *)addr;
+	__asm __volatile("sgdt %0" : "=m" (*loc) : : "memory");
+}
+
+static __inline void
 lidt(struct region_descriptor *addr)
 {
 	__asm __volatile("lidt (%0)" : : "r" (addr));
 }
 
 static __inline void
+sidt(struct region_descriptor *addr)
+{
+	char *loc;
+
+	loc = (char *)addr;
+	__asm __volatile("sidt %0" : "=m" (*loc) : : "memory");
+}
+
+static __inline void
 lldt(u_short sel)
 {
 	__asm __volatile("lldt %0" : : "r" (sel));
@@ -662,6 +686,15 @@ ltr(u_short sel)
 	__asm __volatile("ltr %0" : : "r" (sel));
 }
 
+static __inline uint32_t
+read_tr(void)
+{
+	u_short sel;
+
+	__asm __volatile("str %0" : "=r" (sel));
+	return (sel);
+}
+
 static __inline uint64_t
 rdr0(void)
 {
diff --git a/sys/amd64/include/efi.h b/sys/amd64/include/efi.h
new file mode 100644
index 000000000000..272d5a8f3a83
--- /dev/null
+++ b/sys/amd64/include/efi.h
@@ -0,0 +1,59 @@
+/*-
+ * Copyright (c) 2016 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef __AMD64_INCLUDE_EFI_H_
+#define __AMD64_INCLUDE_EFI_H_
+
+/*
+ * XXX: from gcc 6.2 manual:
+ * Note, the ms_abi attribute for Microsoft Windows 64-bit targets
+ * currently requires the -maccumulate-outgoing-args option.
+ */
+#define	EFIABI_ATTR	__attribute__((ms_abi))
+
+#ifdef _KERNEL
+struct uuid;
+struct efi_tm;
+
+int efi_get_table(struct uuid *uuid, void **ptr);
+int efi_get_time(struct efi_tm *tm);
+int efi_get_time_locked(struct efi_tm *tm);
+int efi_reset_system(void);
+int efi_set_time(struct efi_tm *tm);
+int efi_set_time_locked(struct efi_tm *tm);
+int efi_var_get(uint16_t *name, struct uuid *vendor, uint32_t *attrib,
+    size_t *datasize, void *data);
+int efi_var_nextname(size_t *namesize, uint16_t *name, struct uuid *vendor);
+int efi_var_set(uint16_t *name, struct uuid *vendor, uint32_t attrib,
+    size_t datasize, void *data);
+#endif
+
+#endif /* __AMD64_INCLUDE_EFI_H_ */
diff --git a/sys/amd64/include/pmap.h b/sys/amd64/include/pmap.h
index 90546f57052b..4d924bdbf31e 100644
--- a/sys/amd64/include/pmap.h
+++ b/sys/amd64/include/pmap.h
@@ -391,6 +391,7 @@ struct thread;
 
 void	pmap_activate_sw(struct thread *);
 void	pmap_bootstrap(vm_paddr_t *);
+int	pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde);
 int	pmap_change_attr(vm_offset_t, vm_size_t, int);
 void	pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate);
 void	pmap_init_pat(void);
@@ -403,6 +404,7 @@ void	*pmap_mapdev(vm_paddr_t, vm_size_t);
 void	*pmap_mapdev_attr(vm_paddr_t, vm_size_t, int);
 boolean_t pmap_page_is_mapped(vm_page_t m);
 void	pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
+void	pmap_pinit_pml4(vm_page_t);
 void	pmap_unmapdev(vm_offset_t, vm_size_t);
 void	pmap_invalidate_page(pmap_t, vm_offset_t);
 void	pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t);
@@ -416,6 +418,35 @@ boolean_t pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
 void	pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, boolean_t);
 #endif /* _KERNEL */
 
+/* Return various clipped indexes for a given VA */
+static __inline vm_pindex_t
+pmap_pte_index(vm_offset_t va)
+{
+
+	return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
+}
+
+static __inline vm_pindex_t
+pmap_pde_index(vm_offset_t va)
+{
+
+	return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
+}
+
+static __inline vm_pindex_t
+pmap_pdpe_index(vm_offset_t va)
+{
+
+	return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
+}
+
+static __inline vm_pindex_t
+pmap_pml4e_index(vm_offset_t va)
+{
+
+	return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
+}
+
 #endif /* !LOCORE */
 
 #endif /* !_MACHINE_PMAP_H_ */
diff --git a/sys/amd64/linux/linux_machdep.c b/sys/amd64/linux/linux_machdep.c
index 80c48aa68944..3a6db17bc502 100644
--- a/sys/amd64/linux/linux_machdep.c
+++ b/sys/amd64/linux/linux_machdep.c
@@ -35,7 +35,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
-#include <sys/capability.h>
+#include <sys/capsicum.h>
 #include <sys/dirent.h>
 #include <sys/file.h>
 #include <sys/fcntl.h>
diff --git a/sys/amd64/linux/linux_systrace_args.c b/sys/amd64/linux/linux_systrace_args.c
index db26824d41b4..afb91630d251 100644
--- a/sys/amd64/linux/linux_systrace_args.c
+++ b/sys/amd64/linux/linux_systrace_args.c
@@ -2286,7 +2286,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "u_int";
@@ -2302,7 +2302,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "u_int";
@@ -2315,7 +2315,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 2:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2341,10 +2341,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 4:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_newstat *";
+			p = "userland struct l_newstat *";
 			break;
 		default:
 			break;
@@ -2357,7 +2357,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_newstat *";
+			p = "userland struct l_newstat *";
 			break;
 		default:
 			break;
@@ -2367,10 +2367,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 6:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_newstat *";
+			p = "userland struct l_newstat *";
 			break;
 		default:
 			break;
@@ -2380,7 +2380,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 7:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "u_int";
@@ -2479,10 +2479,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_sigaction_t *";
+			p = "userland l_sigaction_t *";
 			break;
 		case 2:
-			p = "l_sigaction_t *";
+			p = "userland l_sigaction_t *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -2498,10 +2498,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 2:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -2514,7 +2514,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 15:
 		switch(ndx) {
 		case 0:
-			p = "struct l_ucontext *";
+			p = "userland struct l_ucontext *";
 			break;
 		default:
 			break;
@@ -2543,7 +2543,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_size_t";
@@ -2562,7 +2562,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_size_t";
@@ -2581,7 +2581,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "u_int";
@@ -2597,7 +2597,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "u_int";
@@ -2610,7 +2610,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 21:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2623,7 +2623,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 22:
 		switch(ndx) {
 		case 0:
-			p = "l_ulong *";
+			p = "userland l_ulong *";
 			break;
 		default:
 			break;
@@ -2636,16 +2636,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 2:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 3:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 4:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		default:
 			break;
@@ -2702,7 +2702,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_size_t";
 			break;
 		case 2:
-			p = "u_char *";
+			p = "userland u_char *";
 			break;
 		default:
 			break;
@@ -2712,7 +2712,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 28:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -2747,7 +2747,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -2766,7 +2766,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "struct l_shmid_ds *";
+			p = "userland struct l_shmid_ds *";
 			break;
 		default:
 			break;
@@ -2802,10 +2802,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 35:
 		switch(ndx) {
 		case 0:
-			p = "const struct l_timespec *";
+			p = "userland const struct l_timespec *";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -2818,7 +2818,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_itimerval *";
+			p = "userland struct l_itimerval *";
 			break;
 		default:
 			break;
@@ -2841,10 +2841,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_itimerval *";
+			p = "userland struct l_itimerval *";
 			break;
 		case 2:
-			p = "struct l_itimerval *";
+			p = "userland struct l_itimerval *";
 			break;
 		default:
 			break;
@@ -2863,7 +2863,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "l_long *";
+			p = "userland l_long *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -3146,16 +3146,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -3171,13 +3171,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 59:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char **";
+			p = "userland char **";
 			break;
 		case 2:
-			p = "char **";
+			p = "userland char **";
 			break;
 		default:
 			break;
@@ -3200,13 +3200,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		case 2:
 			p = "l_int";
 			break;
 		case 3:
-			p = "struct rusage *";
+			p = "userland struct rusage *";
 			break;
 		default:
 			break;
@@ -3229,7 +3229,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 63:
 		switch(ndx) {
 		case 0:
-			p = "struct l_new_utsname *";
+			p = "userland struct l_new_utsname *";
 			break;
 		default:
 			break;
@@ -3258,7 +3258,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_sembuf *";
+			p = "userland struct l_sembuf *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -3290,7 +3290,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 67:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3316,7 +3316,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_msgbuf *";
+			p = "userland struct l_msgbuf *";
 			break;
 		case 2:
 			p = "l_size_t";
@@ -3335,7 +3335,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_msgbuf *";
+			p = "userland struct l_msgbuf *";
 			break;
 		case 2:
 			p = "l_size_t";
@@ -3360,7 +3360,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "struct l_msqid_ds *";
+			p = "userland struct l_msqid_ds *";
 			break;
 		default:
 			break;
@@ -3419,7 +3419,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 76:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_ulong";
@@ -3448,7 +3448,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -3461,7 +3461,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 79:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_ulong";
@@ -3474,7 +3474,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 80:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3494,10 +3494,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 82:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3507,7 +3507,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 83:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -3520,7 +3520,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 84:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3530,7 +3530,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 85:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -3543,10 +3543,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 86:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3556,7 +3556,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 87:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3566,10 +3566,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 88:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3579,10 +3579,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 89:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -3595,7 +3595,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 90:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_mode_t";
@@ -3621,7 +3621,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 92:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid_t";
@@ -3653,7 +3653,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 94:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid_t";
@@ -3679,10 +3679,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 96:
 		switch(ndx) {
 		case 0:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -3695,7 +3695,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_rlimit *";
+			p = "userland struct l_rlimit *";
 			break;
 		default:
 			break;
@@ -3708,7 +3708,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct rusage *";
+			p = "userland struct rusage *";
 			break;
 		default:
 			break;
@@ -3718,7 +3718,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 99:
 		switch(ndx) {
 		case 0:
-			p = "struct l_sysinfo *";
+			p = "userland struct l_sysinfo *";
 			break;
 		default:
 			break;
@@ -3728,7 +3728,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 100:
 		switch(ndx) {
 		case 0:
-			p = "struct l_times_argv *";
+			p = "userland struct l_times_argv *";
 			break;
 		default:
 			break;
@@ -3763,7 +3763,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -3856,7 +3856,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_gid_t *";
+			p = "userland l_gid_t *";
 			break;
 		default:
 			break;
@@ -3869,7 +3869,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_gid_t *";
+			p = "userland l_gid_t *";
 			break;
 		default:
 			break;
@@ -3895,13 +3895,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 118:
 		switch(ndx) {
 		case 0:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 1:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 2:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		default:
 			break;
@@ -3927,13 +3927,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 120:
 		switch(ndx) {
 		case 0:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 1:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 2:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		default:
 			break;
@@ -3983,10 +3983,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 125:
 		switch(ndx) {
 		case 0:
-			p = "struct l_user_cap_header *";
+			p = "userland struct l_user_cap_header *";
 			break;
 		case 1:
-			p = "struct l_user_cap_data *";
+			p = "userland struct l_user_cap_data *";
 			break;
 		default:
 			break;
@@ -3996,10 +3996,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 126:
 		switch(ndx) {
 		case 0:
-			p = "struct l_user_cap_header *";
+			p = "userland struct l_user_cap_header *";
 			break;
 		case 1:
-			p = "struct l_user_cap_data *";
+			p = "userland struct l_user_cap_data *";
 			break;
 		default:
 			break;
@@ -4009,7 +4009,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 127:
 		switch(ndx) {
 		case 0:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 1:
 			p = "l_size_t";
@@ -4022,13 +4022,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 128:
 		switch(ndx) {
 		case 0:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 1:
-			p = "l_siginfo_t *";
+			p = "userland l_siginfo_t *";
 			break;
 		case 2:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -4047,7 +4047,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "l_siginfo_t *";
+			p = "userland l_siginfo_t *";
 			break;
 		default:
 			break;
@@ -4057,7 +4057,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 130:
 		switch(ndx) {
 		case 0:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 1:
 			p = "l_size_t";
@@ -4070,10 +4070,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 131:
 		switch(ndx) {
 		case 0:
-			p = "l_stack_t *";
+			p = "userland l_stack_t *";
 			break;
 		case 1:
-			p = "l_stack_t *";
+			p = "userland l_stack_t *";
 			break;
 		default:
 			break;
@@ -4083,10 +4083,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 132:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_utimbuf *";
+			p = "userland struct l_utimbuf *";
 			break;
 		default:
 			break;
@@ -4096,7 +4096,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 133:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -4125,7 +4125,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_dev_t";
 			break;
 		case 1:
-			p = "struct l_ustat *";
+			p = "userland struct l_ustat *";
 			break;
 		default:
 			break;
@@ -4135,10 +4135,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 137:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_statfs_buf *";
+			p = "userland struct l_statfs_buf *";
 			break;
 		default:
 			break;
@@ -4151,7 +4151,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_statfs_buf *";
+			p = "userland struct l_statfs_buf *";
 			break;
 		default:
 			break;
@@ -4209,7 +4209,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -4222,7 +4222,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -4238,7 +4238,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -4281,7 +4281,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -4291,7 +4291,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 149:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4304,7 +4304,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 150:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4336,7 +4336,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 156:
 		switch(ndx) {
 		case 0:
-			p = "struct l___sysctl_args *";
+			p = "userland struct l___sysctl_args *";
 			break;
 		default:
 			break;
@@ -4387,7 +4387,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_rlimit *";
+			p = "userland struct l_rlimit *";
 			break;
 		default:
 			break;
@@ -4397,7 +4397,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 161:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4410,7 +4410,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 163:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4420,10 +4420,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 164:
 		switch(ndx) {
 		case 0:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -4433,19 +4433,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 165:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "l_ulong";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -4455,7 +4455,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 166:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -4468,7 +4468,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 167:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4490,7 +4490,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -4500,7 +4500,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 170:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uint";
@@ -4513,7 +4513,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 171:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -4624,7 +4624,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 201:
 		switch(ndx) {
 		case 0:
-			p = "l_time_t *";
+			p = "userland l_time_t *";
 			break;
 		default:
 			break;
@@ -4634,7 +4634,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 202:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "int";
@@ -4643,10 +4643,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 3:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 5:
 			p = "int";
@@ -4665,7 +4665,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 2:
-			p = "l_ulong *";
+			p = "userland l_ulong *";
 			break;
 		default:
 			break;
@@ -4681,7 +4681,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 2:
-			p = "l_ulong *";
+			p = "userland l_ulong *";
 			break;
 		default:
 			break;
@@ -4719,7 +4719,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -4732,7 +4732,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 218:
 		switch(ndx) {
 		case 0:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -4767,10 +4767,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct sigevent *";
+			p = "userland struct sigevent *";
 			break;
 		case 2:
-			p = "l_timer_t *";
+			p = "userland l_timer_t *";
 			break;
 		default:
 			break;
@@ -4786,10 +4786,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "const struct itimerspec *";
+			p = "userland const struct itimerspec *";
 			break;
 		case 3:
-			p = "struct itimerspec *";
+			p = "userland struct itimerspec *";
 			break;
 		default:
 			break;
@@ -4802,7 +4802,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_timer_t";
 			break;
 		case 1:
-			p = "struct itimerspec *";
+			p = "userland struct itimerspec *";
 			break;
 		default:
 			break;
@@ -4835,7 +4835,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -4848,7 +4848,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -4861,7 +4861,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -4877,10 +4877,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 3:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -4903,7 +4903,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct epoll_event *";
+			p = "userland struct epoll_event *";
 			break;
 		case 2:
 			p = "l_int";
@@ -4928,7 +4928,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 3:
-			p = "struct epoll_event *";
+			p = "userland struct epoll_event *";
 			break;
 		default:
 			break;
@@ -4954,10 +4954,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 235:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		default:
 			break;
@@ -5003,13 +5003,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 2:
-			p = "l_siginfo_t *";
+			p = "userland l_siginfo_t *";
 			break;
 		case 3:
 			p = "int";
 			break;
 		case 4:
-			p = "struct rusage *";
+			p = "userland struct rusage *";
 			break;
 		default:
 			break;
@@ -5049,7 +5049,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5068,7 +5068,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5084,7 +5084,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5103,7 +5103,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_uid_t";
@@ -5125,10 +5125,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		default:
 			break;
@@ -5141,10 +5141,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct l_stat64 *";
+			p = "userland struct l_stat64 *";
 			break;
 		case 3:
 			p = "l_int";
@@ -5160,7 +5160,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5176,13 +5176,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
 			break;
 		case 3:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5195,13 +5195,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
 			break;
 		case 3:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 4:
 			p = "l_int";
@@ -5214,13 +5214,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 266:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "l_int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5233,10 +5233,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "l_int";
@@ -5252,7 +5252,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_mode_t";
@@ -5268,7 +5268,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5284,19 +5284,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 2:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 3:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 4:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 5:
-			p = "l_uintptr_t *";
+			p = "userland l_uintptr_t *";
 			break;
 		default:
 			break;
@@ -5306,16 +5306,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 271:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "uint32_t";
 			break;
 		case 2:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 3:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 4:
 			p = "l_size_t";
@@ -5331,7 +5331,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 273:
 		switch(ndx) {
 		case 0:
-			p = "struct linux_robust_list_head *";
+			p = "userland struct linux_robust_list_head *";
 			break;
 		case 1:
 			p = "l_size_t";
@@ -5347,10 +5347,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct linux_robust_list_head **";
+			p = "userland struct linux_robust_list_head **";
 			break;
 		case 2:
-			p = "l_size_t *";
+			p = "userland l_size_t *";
 			break;
 		default:
 			break;
@@ -5378,10 +5378,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
-			p = "const struct l_timespec *";
+			p = "userland const struct l_timespec *";
 			break;
 		case 3:
 			p = "l_int";
@@ -5397,7 +5397,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct epoll_event *";
+			p = "userland struct epoll_event *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5406,7 +5406,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 4:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		default:
 			break;
@@ -5518,7 +5518,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 293:
 		switch(ndx) {
 		case 0:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		case 1:
 			p = "l_int";
@@ -5549,7 +5549,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_mmsghdr *";
+			p = "userland struct l_mmsghdr *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -5558,7 +5558,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 4:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5580,10 +5580,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 2:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		case 3:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		default:
 			break;
@@ -5615,7 +5615,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_mmsghdr *";
+			p = "userland struct l_mmsghdr *";
 			break;
 		case 2:
 			p = "l_uint";
diff --git a/sys/amd64/linux32/linux32_systrace_args.c b/sys/amd64/linux32/linux32_systrace_args.c
index f3bde855e84d..90edc4c13112 100644
--- a/sys/amd64/linux32/linux32_systrace_args.c
+++ b/sys/amd64/linux32/linux32_systrace_args.c
@@ -2390,7 +2390,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "u_int";
@@ -2406,7 +2406,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "u_int";
@@ -2419,7 +2419,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 5:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2448,7 +2448,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		case 2:
 			p = "l_int";
@@ -2461,7 +2461,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 8:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2474,10 +2474,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 9:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2487,7 +2487,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 10:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2497,13 +2497,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 11:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		case 2:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		default:
 			break;
@@ -2513,7 +2513,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 12:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2523,7 +2523,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 13:
 		switch(ndx) {
 		case 0:
-			p = "l_time_t *";
+			p = "userland l_time_t *";
 			break;
 		default:
 			break;
@@ -2533,7 +2533,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 14:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2549,7 +2549,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 15:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_mode_t";
@@ -2562,7 +2562,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 16:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid16_t";
@@ -2578,10 +2578,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 18:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct linux_stat *";
+			p = "userland struct linux_stat *";
 			break;
 		default:
 			break;
@@ -2610,19 +2610,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 21:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "l_ulong";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -2632,7 +2632,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 22:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2690,10 +2690,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 30:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_utimbuf *";
+			p = "userland struct l_utimbuf *";
 			break;
 		default:
 			break;
@@ -2703,7 +2703,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 33:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2742,10 +2742,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 38:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2755,7 +2755,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 39:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2768,7 +2768,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 40:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2788,7 +2788,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 42:
 		switch(ndx) {
 		case 0:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		default:
 			break;
@@ -2798,7 +2798,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 43:
 		switch(ndx) {
 		case 0:
-			p = "struct l_times_argv *";
+			p = "userland struct l_times_argv *";
 			break;
 		default:
 			break;
@@ -2850,7 +2850,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 51:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2860,7 +2860,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 52:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2931,7 +2931,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 61:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2944,7 +2944,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_dev_t";
 			break;
 		case 1:
-			p = "struct l_ustat *";
+			p = "userland struct l_ustat *";
 			break;
 		default:
 			break;
@@ -2979,10 +2979,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_osigaction_t *";
+			p = "userland l_osigaction_t *";
 			break;
 		case 2:
-			p = "l_osigaction_t *";
+			p = "userland l_osigaction_t *";
 			break;
 		default:
 			break;
@@ -3047,7 +3047,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 73:
 		switch(ndx) {
 		case 0:
-			p = "l_osigset_t *";
+			p = "userland l_osigset_t *";
 			break;
 		default:
 			break;
@@ -3057,7 +3057,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 74:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "u_int";
@@ -3073,7 +3073,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_rlimit *";
+			p = "userland struct l_rlimit *";
 			break;
 		default:
 			break;
@@ -3086,7 +3086,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_rlimit *";
+			p = "userland struct l_rlimit *";
 			break;
 		default:
 			break;
@@ -3099,7 +3099,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct l_rusage *";
+			p = "userland struct l_rusage *";
 			break;
 		default:
 			break;
@@ -3109,10 +3109,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 78:
 		switch(ndx) {
 		case 0:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -3122,10 +3122,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 79:
 		switch(ndx) {
 		case 0:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -3138,7 +3138,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		default:
 			break;
@@ -3151,7 +3151,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		default:
 			break;
@@ -3161,7 +3161,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 82:
 		switch(ndx) {
 		case 0:
-			p = "struct l_old_select_argv *";
+			p = "userland struct l_old_select_argv *";
 			break;
 		default:
 			break;
@@ -3171,10 +3171,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 83:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3184,10 +3184,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 84:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct linux_lstat *";
+			p = "userland struct linux_lstat *";
 			break;
 		default:
 			break;
@@ -3197,10 +3197,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 85:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -3213,7 +3213,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 87:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3232,7 +3232,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -3245,7 +3245,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_dirent *";
+			p = "userland struct l_dirent *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -3258,7 +3258,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 90:
 		switch(ndx) {
 		case 0:
-			p = "struct l_mmap_argv *";
+			p = "userland struct l_mmap_argv *";
 			break;
 		default:
 			break;
@@ -3281,7 +3281,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 92:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_ulong";
@@ -3365,10 +3365,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 99:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_statfs_buf *";
+			p = "userland struct l_statfs_buf *";
 			break;
 		default:
 			break;
@@ -3381,7 +3381,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_statfs_buf *";
+			p = "userland struct l_statfs_buf *";
 			break;
 		default:
 			break;
@@ -3407,7 +3407,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -3423,10 +3423,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_itimerval *";
+			p = "userland struct l_itimerval *";
 			break;
 		case 2:
-			p = "struct l_itimerval *";
+			p = "userland struct l_itimerval *";
 			break;
 		default:
 			break;
@@ -3439,7 +3439,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_itimerval *";
+			p = "userland struct l_itimerval *";
 			break;
 		default:
 			break;
@@ -3449,10 +3449,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 106:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_newstat *";
+			p = "userland struct l_newstat *";
 			break;
 		default:
 			break;
@@ -3462,10 +3462,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 107:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_newstat *";
+			p = "userland struct l_newstat *";
 			break;
 		default:
 			break;
@@ -3478,7 +3478,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_newstat *";
+			p = "userland struct l_newstat *";
 			break;
 		default:
 			break;
@@ -3507,13 +3507,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		case 2:
 			p = "l_int";
 			break;
 		case 3:
-			p = "struct l_rusage *";
+			p = "userland struct l_rusage *";
 			break;
 		default:
 			break;
@@ -3526,7 +3526,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 116:
 		switch(ndx) {
 		case 0:
-			p = "struct l_sysinfo *";
+			p = "userland struct l_sysinfo *";
 			break;
 		default:
 			break;
@@ -3548,7 +3548,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 5:
 			p = "l_long";
@@ -3571,7 +3571,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 119:
 		switch(ndx) {
 		case 0:
-			p = "struct l_sigframe *";
+			p = "userland struct l_sigframe *";
 			break;
 		default:
 			break;
@@ -3584,16 +3584,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -3603,7 +3603,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 121:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3616,7 +3616,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 122:
 		switch(ndx) {
 		case 0:
-			p = "struct l_new_utsname *";
+			p = "userland struct l_new_utsname *";
 			break;
 		default:
 			break;
@@ -3648,10 +3648,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_osigset_t *";
+			p = "userland l_osigset_t *";
 			break;
 		case 2:
-			p = "l_osigset_t *";
+			p = "userland l_osigset_t *";
 			break;
 		default:
 			break;
@@ -3754,7 +3754,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_ulong";
 			break;
 		case 3:
-			p = "l_loff_t *";
+			p = "userland l_loff_t *";
 			break;
 		case 4:
 			p = "l_uint";
@@ -3770,7 +3770,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -3786,16 +3786,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 2:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 3:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 4:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		default:
 			break;
@@ -3837,7 +3837,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_ulong";
 			break;
 		case 1:
-			p = "struct l_iovec32 *";
+			p = "userland struct l_iovec32 *";
 			break;
 		case 2:
 			p = "l_ulong";
@@ -3853,7 +3853,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_ulong";
 			break;
 		case 1:
-			p = "struct l_iovec32 *";
+			p = "userland struct l_iovec32 *";
 			break;
 		case 2:
 			p = "l_ulong";
@@ -3886,7 +3886,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 149:
 		switch(ndx) {
 		case 0:
-			p = "struct l___sysctl_args *";
+			p = "userland struct l___sysctl_args *";
 			break;
 		default:
 			break;
@@ -3896,7 +3896,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 150:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -3909,7 +3909,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 151:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -3938,7 +3938,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -3951,7 +3951,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -3967,7 +3967,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -4013,7 +4013,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -4023,10 +4023,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 162:
 		switch(ndx) {
 		case 0:
-			p = "const struct l_timespec *";
+			p = "userland const struct l_timespec *";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -4074,13 +4074,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 165:
 		switch(ndx) {
 		case 0:
-			p = "l_uid16_t *";
+			p = "userland l_uid16_t *";
 			break;
 		case 1:
-			p = "l_uid16_t *";
+			p = "userland l_uid16_t *";
 			break;
 		case 2:
-			p = "l_uid16_t *";
+			p = "userland l_uid16_t *";
 			break;
 		default:
 			break;
@@ -4093,7 +4093,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 168:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -4128,13 +4128,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 171:
 		switch(ndx) {
 		case 0:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		case 1:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		case 2:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		default:
 			break;
@@ -4166,7 +4166,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 173:
 		switch(ndx) {
 		case 0:
-			p = "struct l_ucontext *";
+			p = "userland struct l_ucontext *";
 			break;
 		default:
 			break;
@@ -4179,10 +4179,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_sigaction_t *";
+			p = "userland l_sigaction_t *";
 			break;
 		case 2:
-			p = "l_sigaction_t *";
+			p = "userland l_sigaction_t *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -4198,10 +4198,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 2:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -4214,7 +4214,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 176:
 		switch(ndx) {
 		case 0:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 1:
 			p = "l_size_t";
@@ -4227,13 +4227,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 177:
 		switch(ndx) {
 		case 0:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 1:
-			p = "l_siginfo_t *";
+			p = "userland l_siginfo_t *";
 			break;
 		case 2:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -4252,7 +4252,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "l_siginfo_t *";
+			p = "userland l_siginfo_t *";
 			break;
 		default:
 			break;
@@ -4262,7 +4262,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 179:
 		switch(ndx) {
 		case 0:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 1:
 			p = "l_size_t";
@@ -4278,7 +4278,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_size_t";
@@ -4297,7 +4297,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_size_t";
@@ -4313,7 +4313,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 182:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid16_t";
@@ -4329,7 +4329,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 183:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_ulong";
@@ -4342,10 +4342,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 184:
 		switch(ndx) {
 		case 0:
-			p = "struct l_user_cap_header *";
+			p = "userland struct l_user_cap_header *";
 			break;
 		case 1:
-			p = "struct l_user_cap_data *";
+			p = "userland struct l_user_cap_data *";
 			break;
 		default:
 			break;
@@ -4355,10 +4355,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 185:
 		switch(ndx) {
 		case 0:
-			p = "struct l_user_cap_header *";
+			p = "userland struct l_user_cap_header *";
 			break;
 		case 1:
-			p = "struct l_user_cap_data *";
+			p = "userland struct l_user_cap_data *";
 			break;
 		default:
 			break;
@@ -4368,10 +4368,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 186:
 		switch(ndx) {
 		case 0:
-			p = "l_stack_t *";
+			p = "userland l_stack_t *";
 			break;
 		case 1:
-			p = "l_stack_t *";
+			p = "userland l_stack_t *";
 			break;
 		default:
 			break;
@@ -4390,7 +4390,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_rlimit *";
+			p = "userland struct l_rlimit *";
 			break;
 		default:
 			break;
@@ -4425,7 +4425,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 193:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_loff_t";
@@ -4451,10 +4451,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 195:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
-			p = "struct l_stat64 *";
+			p = "userland struct l_stat64 *";
 			break;
 		default:
 			break;
@@ -4464,10 +4464,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 196:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
-			p = "struct l_stat64 *";
+			p = "userland struct l_stat64 *";
 			break;
 		default:
 			break;
@@ -4480,7 +4480,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_stat64 *";
+			p = "userland struct l_stat64 *";
 			break;
 		default:
 			break;
@@ -4490,7 +4490,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 198:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid_t";
@@ -4547,7 +4547,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_gid_t *";
+			p = "userland l_gid_t *";
 			break;
 		default:
 			break;
@@ -4560,7 +4560,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_gid_t *";
+			p = "userland l_gid_t *";
 			break;
 		default:
 			break;
@@ -4589,13 +4589,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 209:
 		switch(ndx) {
 		case 0:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 1:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 2:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		default:
 			break;
@@ -4621,13 +4621,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 211:
 		switch(ndx) {
 		case 0:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 1:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 2:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		default:
 			break;
@@ -4637,7 +4637,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 212:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid_t";
@@ -4693,10 +4693,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 217:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4712,7 +4712,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_size_t";
 			break;
 		case 2:
-			p = "u_char *";
+			p = "userland u_char *";
 			break;
 		default:
 			break;
@@ -4722,7 +4722,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 219:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4741,7 +4741,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -4822,7 +4822,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 240:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "int";
@@ -4831,10 +4831,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "uint32_t";
 			break;
 		case 3:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 4:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		case 5:
 			p = "uint32_t";
@@ -4853,7 +4853,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 2:
-			p = "l_ulong *";
+			p = "userland l_ulong *";
 			break;
 		default:
 			break;
@@ -4869,7 +4869,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 2:
-			p = "l_ulong *";
+			p = "userland l_ulong *";
 			break;
 		default:
 			break;
@@ -4879,7 +4879,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 243:
 		switch(ndx) {
 		case 0:
-			p = "struct l_user_desc *";
+			p = "userland struct l_user_desc *";
 			break;
 		default:
 			break;
@@ -4940,7 +4940,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 3:
-			p = "struct epoll_event *";
+			p = "userland struct epoll_event *";
 			break;
 		default:
 			break;
@@ -4953,7 +4953,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct epoll_event *";
+			p = "userland struct epoll_event *";
 			break;
 		case 2:
 			p = "l_int";
@@ -4972,7 +4972,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 258:
 		switch(ndx) {
 		case 0:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -4985,10 +4985,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct sigevent *";
+			p = "userland struct sigevent *";
 			break;
 		case 2:
-			p = "l_timer_t *";
+			p = "userland l_timer_t *";
 			break;
 		default:
 			break;
@@ -5004,10 +5004,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "const struct itimerspec *";
+			p = "userland const struct itimerspec *";
 			break;
 		case 3:
-			p = "struct itimerspec *";
+			p = "userland struct itimerspec *";
 			break;
 		default:
 			break;
@@ -5020,7 +5020,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_timer_t";
 			break;
 		case 1:
-			p = "struct itimerspec *";
+			p = "userland struct itimerspec *";
 			break;
 		default:
 			break;
@@ -5053,7 +5053,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5066,7 +5066,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5079,7 +5079,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5095,10 +5095,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 3:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5108,13 +5108,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 268:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "struct l_statfs64_buf *";
+			p = "userland struct l_statfs64_buf *";
 			break;
 		default:
 			break;
@@ -5130,7 +5130,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "size_t";
 			break;
 		case 2:
-			p = "struct l_statfs64_buf *";
+			p = "userland struct l_statfs64_buf *";
 			break;
 		default:
 			break;
@@ -5156,10 +5156,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 271:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		default:
 			break;
@@ -5224,13 +5224,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 2:
-			p = "l_siginfo_t *";
+			p = "userland l_siginfo_t *";
 			break;
 		case 3:
 			p = "int";
 			break;
 		case 4:
-			p = "struct l_rusage *";
+			p = "userland struct l_rusage *";
 			break;
 		default:
 			break;
@@ -5270,7 +5270,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5289,7 +5289,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5305,7 +5305,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5324,7 +5324,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_uid16_t";
@@ -5346,10 +5346,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		default:
 			break;
@@ -5362,10 +5362,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct l_stat64 *";
+			p = "userland struct l_stat64 *";
 			break;
 		case 3:
 			p = "l_int";
@@ -5381,7 +5381,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5397,13 +5397,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
 			break;
 		case 3:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5416,13 +5416,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
 			break;
 		case 3:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 4:
 			p = "l_int";
@@ -5435,13 +5435,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 304:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "l_int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5454,10 +5454,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "l_int";
@@ -5473,7 +5473,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_mode_t";
@@ -5489,7 +5489,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5505,19 +5505,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 2:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 3:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 4:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 5:
-			p = "l_uintptr_t *";
+			p = "userland l_uintptr_t *";
 			break;
 		default:
 			break;
@@ -5527,16 +5527,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 309:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "uint32_t";
 			break;
 		case 2:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 3:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 4:
 			p = "l_size_t";
@@ -5552,7 +5552,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 311:
 		switch(ndx) {
 		case 0:
-			p = "struct linux_robust_list_head *";
+			p = "userland struct linux_robust_list_head *";
 			break;
 		case 1:
 			p = "l_size_t";
@@ -5568,10 +5568,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct linux_robust_list_head **";
+			p = "userland struct linux_robust_list_head **";
 			break;
 		case 2:
-			p = "l_size_t *";
+			p = "userland l_size_t *";
 			break;
 		default:
 			break;
@@ -5602,7 +5602,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct epoll_event *";
+			p = "userland struct epoll_event *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5611,7 +5611,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 4:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		default:
 			break;
@@ -5624,10 +5624,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
-			p = "const struct l_timespec *";
+			p = "userland const struct l_timespec *";
 			break;
 		case 3:
 			p = "l_int";
@@ -5723,7 +5723,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 331:
 		switch(ndx) {
 		case 0:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		case 1:
 			p = "l_int";
@@ -5754,7 +5754,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_mmsghdr *";
+			p = "userland struct l_mmsghdr *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -5763,7 +5763,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 4:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5785,10 +5785,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 2:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		case 3:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		default:
 			break;
@@ -5820,7 +5820,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_mmsghdr *";
+			p = "userland struct l_mmsghdr *";
 			break;
 		case 2:
 			p = "l_uint";
diff --git a/sys/arm/allwinner/a10_common.c b/sys/arm/allwinner/a10_common.c
index 82be0c043ab5..6b3fded7a3ab 100644
--- a/sys/arm/allwinner/a10_common.c
+++ b/sys/arm/allwinner/a10_common.c
@@ -38,10 +38,6 @@ __FBSDID("$FreeBSD$");
 #include <machine/bus.h>
 #include <machine/vmparam.h>
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 
 static int
diff --git a/sys/arm/allwinner/aw_machdep.c b/sys/arm/allwinner/aw_machdep.c
index 3fab0a15986d..73b1e58f9491 100644
--- a/sys/arm/allwinner/aw_machdep.c
+++ b/sys/arm/allwinner/aw_machdep.c
@@ -36,7 +36,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -147,20 +146,8 @@ allwinner_devmap_init(platform_t plat)
 	return (0);
 }
 
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-	return (0);
-}
-
-void
-cpu_reset()
+static void
+allwinner_cpu_reset(platform_t plat)
 {
 	aw_wdog_watchdog_reset();
 	printf("Reset failed!\n");
@@ -172,6 +159,7 @@ static platform_method_t a10_methods[] = {
 	PLATFORMMETHOD(platform_attach,         a10_attach),
 	PLATFORMMETHOD(platform_lastaddr,       allwinner_lastaddr),
 	PLATFORMMETHOD(platform_devmap_init,    allwinner_devmap_init),
+	PLATFORMMETHOD(platform_cpu_reset,	allwinner_cpu_reset),
 
 	PLATFORMMETHOD_END,
 };
@@ -183,6 +171,7 @@ static platform_method_t a13_methods[] = {
 	PLATFORMMETHOD(platform_attach,         a13_attach),
 	PLATFORMMETHOD(platform_lastaddr,       allwinner_lastaddr),
 	PLATFORMMETHOD(platform_devmap_init,    allwinner_devmap_init),
+	PLATFORMMETHOD(platform_cpu_reset,	allwinner_cpu_reset),
 
 	PLATFORMMETHOD_END,
 };
@@ -194,6 +183,7 @@ static platform_method_t a20_methods[] = {
 	PLATFORMMETHOD(platform_attach,         a20_attach),
 	PLATFORMMETHOD(platform_lastaddr,       allwinner_lastaddr),
 	PLATFORMMETHOD(platform_devmap_init,    allwinner_devmap_init),
+	PLATFORMMETHOD(platform_cpu_reset,	allwinner_cpu_reset),
 
 #ifdef SMP
 	PLATFORMMETHOD(platform_mp_start_ap,	aw_mp_start_ap),
@@ -209,6 +199,7 @@ static platform_method_t a31_methods[] = {
 	PLATFORMMETHOD(platform_attach,         a31_attach),
 	PLATFORMMETHOD(platform_lastaddr,       allwinner_lastaddr),
 	PLATFORMMETHOD(platform_devmap_init,    allwinner_devmap_init),
+	PLATFORMMETHOD(platform_cpu_reset,	allwinner_cpu_reset),
 
 #ifdef SMP
 	PLATFORMMETHOD(platform_mp_start_ap,	aw_mp_start_ap),
@@ -224,6 +215,7 @@ static platform_method_t a31s_methods[] = {
 	PLATFORMMETHOD(platform_attach,         a31s_attach),
 	PLATFORMMETHOD(platform_lastaddr,       allwinner_lastaddr),
 	PLATFORMMETHOD(platform_devmap_init,    allwinner_devmap_init),
+	PLATFORMMETHOD(platform_cpu_reset,	allwinner_cpu_reset),
 
 #ifdef SMP
 	PLATFORMMETHOD(platform_mp_start_ap,	aw_mp_start_ap),
@@ -239,6 +231,7 @@ static platform_method_t a83t_methods[] = {
 	PLATFORMMETHOD(platform_attach,         a83t_attach),
 	PLATFORMMETHOD(platform_lastaddr,       allwinner_lastaddr),
 	PLATFORMMETHOD(platform_devmap_init,    allwinner_devmap_init),
+	PLATFORMMETHOD(platform_cpu_reset,	allwinner_cpu_reset),
 
 #ifdef SMP
 	PLATFORMMETHOD(platform_mp_start_ap,	a83t_mp_start_ap),
@@ -254,6 +247,7 @@ static platform_method_t h3_methods[] = {
 	PLATFORMMETHOD(platform_attach,         h3_attach),
 	PLATFORMMETHOD(platform_lastaddr,       allwinner_lastaddr),
 	PLATFORMMETHOD(platform_devmap_init,    allwinner_devmap_init),
+	PLATFORMMETHOD(platform_cpu_reset,	allwinner_cpu_reset),
 
 #ifdef SMP
 	PLATFORMMETHOD(platform_mp_start_ap,	aw_mp_start_ap),
diff --git a/sys/arm/altera/socfpga/socfpga_common.c b/sys/arm/altera/socfpga/socfpga_common.c
index 740d342f6792..9944b90e8b52 100644
--- a/sys/arm/altera/socfpga/socfpga_common.c
+++ b/sys/arm/altera/socfpga/socfpga_common.c
@@ -70,10 +70,6 @@ end:
 	while (1);
 }
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
diff --git a/sys/arm/altera/socfpga/socfpga_machdep.c b/sys/arm/altera/socfpga/socfpga_machdep.c
index 9ae868a3936d..bcfdd5ceded8 100644
--- a/sys/arm/altera/socfpga/socfpga_machdep.c
+++ b/sys/arm/altera/socfpga/socfpga_machdep.c
@@ -34,7 +34,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define	_ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -100,17 +99,3 @@ platform_devmap_init(void)
 
 	return (0);
 }
-
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
diff --git a/sys/arm/amlogic/aml8726/aml8726_machdep.c b/sys/arm/amlogic/aml8726/aml8726_machdep.c
index 58cf9b2fa0da..7ab7f5ec975f 100644
--- a/sys/arm/amlogic/aml8726/aml8726_machdep.c
+++ b/sys/arm/amlogic/aml8726/aml8726_machdep.c
@@ -31,7 +31,6 @@ __FBSDID("$FreeBSD$");
 
 #include "opt_platform.h"
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -166,24 +165,6 @@ platform_devmap_init(void)
 	return (0);
 }
 
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
-
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 #ifndef DEV_GIC
 static int
diff --git a/sys/arm/annapurna/alpine/alpine_machdep.c b/sys/arm/annapurna/alpine/alpine_machdep.c
index 8c00303b5310..3d35834f1ca7 100644
--- a/sys/arm/annapurna/alpine/alpine_machdep.c
+++ b/sys/arm/annapurna/alpine/alpine_machdep.c
@@ -29,7 +29,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -92,17 +91,3 @@ platform_devmap_init(void)
 	devmap_add_entry(al_devmap_pa, al_devmap_size);
 	return (0);
 }
-
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
diff --git a/sys/arm/annapurna/alpine/alpine_pci.c b/sys/arm/annapurna/alpine/alpine_pci.c
new file mode 100644
index 000000000000..4d5072605795
--- /dev/null
+++ b/sys/arm/annapurna/alpine/alpine_pci.c
@@ -0,0 +1,158 @@
+/*-
+ * Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates
+ * All rights reserved.
+ *
+ * Developed by Semihalf.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Alpine PCI/PCI-Express controller driver.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/intr.h>
+
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+#include <dev/pci/pci_host_generic.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+#include "pcib_if.h"
+
+#include "contrib/alpine-hal/al_hal_unit_adapter_regs.h"
+#include "contrib/alpine-hal/al_hal_pcie.h"
+#include "contrib/alpine-hal/al_hal_pcie_axi_reg.h"
+
+#define ANNAPURNA_VENDOR_ID		0x1c36
+
+/* Forward prototypes */
+static int al_pcib_probe(device_t);
+static int al_pcib_attach(device_t);
+static void al_pcib_fixup(device_t);
+
+static struct ofw_compat_data compat_data[] = {
+	{"annapurna-labs,al-internal-pcie",	true},
+	{"annapurna-labs,alpine-internal-pcie",	true},
+	{NULL,					false}
+};
+
+/*
+ * Bus interface definitions.
+ */
+static device_method_t al_pcib_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,			al_pcib_probe),
+	DEVMETHOD(device_attach,		al_pcib_attach),
+
+	DEVMETHOD_END
+};
+
+DEFINE_CLASS_1(pcib, al_pcib_driver, al_pcib_methods,
+    sizeof(struct generic_pcie_softc), generic_pcie_driver);
+
+static devclass_t anpa_pcib_devclass;
+
+DRIVER_MODULE(alpine_pcib, simplebus, al_pcib_driver, anpa_pcib_devclass, 0, 0);
+DRIVER_MODULE(alpine_pcib, ofwbus, al_pcib_driver, anpa_pcib_devclass, 0, 0);
+
+static int
+al_pcib_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
+		return (ENXIO);
+
+	device_set_desc(dev,
+	    "Annapurna-Labs Integrated Internal PCI-E Controller");
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+al_pcib_attach(device_t dev)
+{
+	int rv;
+
+	rv = pci_host_generic_attach(dev);
+
+	/* Annapurna quirk: configure vendor-specific registers */
+	if (rv == 0)
+		al_pcib_fixup(dev);
+
+	return (rv);
+}
+
+static void
+al_pcib_fixup(device_t dev)
+{
+	uint32_t val;
+	uint16_t vid;
+	uint8_t hdrtype;
+	int bus, slot, func, maxfunc;
+
+	/* Fixup is only needed on bus 0 */
+	bus = 0;
+	for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
+		maxfunc = 0;
+		for (func = 0; func <= maxfunc; func++) {
+			hdrtype = PCIB_READ_CONFIG(dev, bus, slot, func,
+			    PCIR_HDRTYPE, 1);
+
+			if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
+				continue;
+
+			if (func == 0 && (hdrtype & PCIM_MFDEV) != 0)
+				maxfunc = PCI_FUNCMAX;
+
+			vid = PCIB_READ_CONFIG(dev, bus, slot, func,
+			    PCIR_VENDOR, 2);
+			if (vid == ANNAPURNA_VENDOR_ID) {
+				val = PCIB_READ_CONFIG(dev, bus, slot, func,
+				    AL_PCI_AXI_CFG_AND_CTR_0, 4);
+				val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK;
+				PCIB_WRITE_CONFIG(dev, bus, slot, func,
+				    AL_PCI_AXI_CFG_AND_CTR_0, val, 4);
+
+				val = PCIB_READ_CONFIG(dev, bus, slot, func,
+				    AL_PCI_APP_CONTROL, 4);
+				val &= ~0xffff;
+				val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK;
+				PCIB_WRITE_CONFIG(dev, bus, slot, func,
+				    AL_PCI_APP_CONTROL, val, 4);
+			}
+		}
+	}
+}
diff --git a/sys/arm/annapurna/alpine/common.c b/sys/arm/annapurna/alpine/common.c
index cf905569275d..b03c3a487552 100644
--- a/sys/arm/annapurna/alpine/common.c
+++ b/sys/arm/annapurna/alpine/common.c
@@ -56,9 +56,6 @@ __FBSDID("$FreeBSD$");
 #define LOCK		0x00000001
 
 extern bus_addr_t  al_devmap_pa;
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
 
 static int alpine_get_wdt_base(uint32_t *pbase, uint32_t *psize);
 static int alpine_pic_decode_fdt(uint32_t iparent, uint32_t *intr,
diff --git a/sys/arm/arm/busdma_machdep-v6.c b/sys/arm/arm/busdma_machdep-v6.c
index fe446b90f610..72a041cf47d1 100644
--- a/sys/arm/arm/busdma_machdep-v6.c
+++ b/sys/arm/arm/busdma_machdep-v6.c
@@ -33,7 +33,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/malloc.h>
@@ -95,14 +94,6 @@ struct bus_dma_tag {
 	bus_dma_lock_t		*lockfunc;
 	void			*lockfuncarg;
 	struct bounce_zone	*bounce_zone;
-	/*
-	 * DMA range for this tag.  If the page doesn't fall within
-	 * one of these ranges, an error is returned.  The caller
-	 * may then decide what to do with the transfer.  If the
-	 * range pointer is NULL, it is ignored.
-	 */
-	struct arm32_dma_range	*ranges;
-	int			_nranges;
 };
 
 struct bounce_page {
@@ -407,22 +398,6 @@ must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr,
 	return (0);
 }
 
-static __inline struct arm32_dma_range *
-_bus_dma_inrange(struct arm32_dma_range *ranges, int nranges,
-    bus_addr_t curaddr)
-{
-	struct arm32_dma_range *dr;
-	int i;
-
-	for (i = 0, dr = ranges; i < nranges; i++, dr++) {
-		if (curaddr >= dr->dr_sysbase &&
-		    round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len))
-			return (dr);
-	}
-
-	return (NULL);
-}
-
 /*
  * Convenience function for manipulating driver locks from busdma (during
  * busdma_swi, for example).  Drivers that don't provide their own locks
@@ -507,8 +482,6 @@ bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment,
 	newtag->flags = flags;
 	newtag->ref_count = 1; /* Count ourself */
 	newtag->map_count = 0;
-	newtag->ranges = bus_dma_get_range();
-	newtag->_nranges = bus_dma_get_range_nb();
 	if (lockfunc != NULL) {
 		newtag->lockfunc = lockfunc;
 		newtag->lockfuncarg = lockfuncarg;
@@ -992,22 +965,6 @@ _bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr,
 			sgsize = (baddr - curaddr);
 	}
 
-	if (dmat->ranges) {
-		struct arm32_dma_range *dr;
-
-		dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges,
-		    curaddr);
-		if (dr == NULL) {
-			_bus_dmamap_unload(dmat, map);
-			return (0);
-		}
-		/*
-		 * In a valid DMA range.  Translate the physical
-		 * memory address to an address in the DMA window.
-		 */
-		curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase;
-	}
-
 	/*
 	 * Insert chunk into a segment, coalescing with
 	 * previous segment if possible.
diff --git a/sys/arm/arm/genassym.c b/sys/arm/arm/genassym.c
index 34df028ae056..bdcb9cb25ed8 100644
--- a/sys/arm/arm/genassym.c
+++ b/sys/arm/arm/genassym.c
@@ -81,6 +81,9 @@ ASSYM(PCB_R12, offsetof(struct pcb, pcb_regs.sf_r12));
 ASSYM(PCB_SP, offsetof(struct pcb, pcb_regs.sf_sp));
 ASSYM(PCB_LR, offsetof(struct pcb, pcb_regs.sf_lr));
 ASSYM(PCB_PC, offsetof(struct pcb, pcb_regs.sf_pc));
+#if __ARM_ARCH >= 6
+ASSYM(PCB_TPIDRURW, offsetof(struct pcb, pcb_regs.sf_tpidrurw));
+#endif
 
 ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb));
 ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread));
@@ -100,8 +103,8 @@ ASSYM(TD_FLAGS, offsetof(struct thread, td_flags));
 ASSYM(TD_PROC, offsetof(struct thread, td_proc));
 ASSYM(TD_MD, offsetof(struct thread, td_md));
 ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
-ASSYM(MD_TP, offsetof(struct mdthread, md_tp));
 #if __ARM_ARCH < 6
+ASSYM(MD_TP, offsetof(struct mdthread, md_tp));
 ASSYM(MD_RAS_START, offsetof(struct mdthread, md_ras_start));
 ASSYM(MD_RAS_END, offsetof(struct mdthread, md_ras_end));
 #endif
diff --git a/sys/arm/arm/gic.c b/sys/arm/arm/gic.c
index 4425c7cb3f67..85bf9b2476f0 100644
--- a/sys/arm/arm/gic.c
+++ b/sys/arm/arm/gic.c
@@ -835,6 +835,26 @@ gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
 #endif
 
 static int
+gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
+    enum intr_polarity *polp, enum intr_trigger *trigp)
+{
+	struct gic_irqsrc *gi;
+
+	/* Map a non-GICv2m MSI */
+	gi = (struct gic_irqsrc *)msi_data->isrc;
+	if (gi == NULL)
+		return (ENXIO);
+
+	*irqp = gi->gi_irq;
+
+	/* MSI/MSI-X interrupts are always edge triggered with high polarity */
+	*polp = INTR_POLARITY_HIGH;
+	*trigp = INTR_TRIGGER_EDGE;
+
+	return (0);
+}
+
+static int
 gic_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
     enum intr_polarity *polp, enum intr_trigger *trigp)
 {
@@ -842,6 +862,7 @@ gic_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
 	enum intr_polarity pol;
 	enum intr_trigger trig;
 	struct arm_gic_softc *sc;
+	struct intr_map_data_msi *dam;
 #ifdef FDT
 	struct intr_map_data_fdt *daf;
 #endif
@@ -860,6 +881,12 @@ gic_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
 		    __func__));
 		break;
 #endif
+	case INTR_MAP_DATA_MSI:
+		/* Non-GICv2m MSI */
+		dam = (struct intr_map_data_msi *)data;
+		if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
+			return (EINVAL);
+		break;
 	default:
 		return (ENOTSUP);
 	}
@@ -907,6 +934,7 @@ arm_gic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
 	enum intr_polarity pol;
 
 	if ((gi->gi_flags & GI_FLAG_MSI) == GI_FLAG_MSI) {
+		/* GICv2m MSI */
 		pol = gi->gi_pol;
 		trig = gi->gi_trig;
 		KASSERT(pol == INTR_POLARITY_HIGH,
diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c
index 203568e6d2f8..4a9dd99dd85d 100644
--- a/sys/arm/arm/machdep.c
+++ b/sys/arm/arm/machdep.c
@@ -1398,9 +1398,6 @@ set_stackptrs(int cpu)
 #endif
 
 #ifdef EFI
-#define efi_next_descriptor(ptr, size) \
-	((struct efi_md *)(((uint8_t *) ptr) + size))
-
 static void
 add_efi_map_entries(struct efi_map_header *efihdr, struct mem_region *mr,
     int *mrcnt)
diff --git a/sys/arm/arm/platform.c b/sys/arm/arm/platform.c
index 85e60c6533ac..7703be63f11f 100644
--- a/sys/arm/arm/platform.c
+++ b/sys/arm/arm/platform.c
@@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$");
  * through a previously registered kernel object.
  */
 
-#define	_ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/kernel.h>
@@ -189,6 +188,20 @@ platform_late_init(void)
 	PLATFORM_LATE_INIT(plat_obj);
 }
 
+void
+cpu_reset(void)
+{
+
+	PLATFORM_CPU_RESET(plat_obj);
+
+	printf("cpu_reset failed");
+
+	intr_disable();
+	while(1) {
+		cpu_sleep(0);
+	}
+}
+
 #ifdef MULTIDELAY
 static void
 platform_delay(int usec, void *arg __unused)
diff --git a/sys/arm/arm/platform_if.m b/sys/arm/arm/platform_if.m
index e17cab8468e8..5647b22867c9 100644
--- a/sys/arm/arm/platform_if.m
+++ b/sys/arm/arm/platform_if.m
@@ -133,3 +133,10 @@ METHOD void mp_setmaxid {
 METHOD void mp_start_ap {
 	platform_t	_plat;
 };
+
+/**
+ * @brief Called by cpu_reset to reboot.
+ */
+METHOD void cpu_reset {
+	platform_t	_plat;
+};
diff --git a/sys/arm/arm/swtch-v6.S b/sys/arm/arm/swtch-v6.S
index d63661a9666d..8bbaac9df74c 100644
--- a/sys/arm/arm/swtch-v6.S
+++ b/sys/arm/arm/swtch-v6.S
@@ -291,6 +291,8 @@ ENTRY(cpu_switch)
 	ldr	r3, [r0, #(TD_PCB)]
 	add	r3, #(PCB_R4)
 	stmia	r3, {r4-r12, sp, lr, pc}
+	mrc	CP15_TPIDRURW(r4)
+	str	r4, [r3, #(PCB_TPIDRURW - PCB_R4)]
 
 #ifdef INVARIANTS
 	cmp	r1, #0			/* new thread? */
@@ -437,9 +439,6 @@ sw1:
 	cmp	r3, r6
 	beq	1b
 #endif
-	/* Set the new tls */
-	ldr	r0, [r11, #(TD_MD + MD_TP)]
-	mcr	CP15_TPIDRURO(r0)	/* write tls thread reg 2 */
 
 	/* We have a new curthread now so make a note it */
 	str	r11, [r8, #PC_CURTHREAD]
@@ -452,7 +451,14 @@ sw1:
 	 * Restore all saved registers and return. Note that some saved
 	 * registers can be changed when either cpu_fork(), cpu_copy_thread(),
 	 * cpu_fork_kthread_handler(), or makectx() was called.
+	 *
+	 * The value of TPIDRURW is also written into TPIDRURO, as
+	 * userspace still uses TPIDRURO, modifying it through
+	 * sysarch(ARM_SET_TP, addr).
 	 */
+	ldr	r3, [r7, #PCB_TPIDRURW]
+	mcr	CP15_TPIDRURW(r3)	/* write tls thread reg 2 */
+	mcr	CP15_TPIDRURO(r3)	/* write tls thread reg 3 */
 	add	r3, r7, #PCB_R4
 	ldmia	r3, {r4-r12, sp, pc}
 
diff --git a/sys/arm/arm/sys_machdep.c b/sys/arm/arm/sys_machdep.c
index 678157290d2f..087afbdca6ee 100644
--- a/sys/arm/arm/sys_machdep.c
+++ b/sys/arm/arm/sys_machdep.c
@@ -166,10 +166,10 @@ static int
 arm32_set_tp(struct thread *td, void *args)
 {
 
-	td->td_md.md_tp = (register_t)args;
 #if __ARM_ARCH >= 6
 	set_tls(args);
 #else
+	td->td_md.md_tp = (register_t)args;
 	*(register_t *)ARM_TP_ADDRESS = (register_t)args;
 #endif
 	return (0);
@@ -180,7 +180,7 @@ arm32_get_tp(struct thread *td, void *args)
 {
 
 #if __ARM_ARCH >= 6
-	td->td_retval[0] = td->td_md.md_tp;
+	td->td_retval[0] = (register_t)get_tls();
 #else
 	td->td_retval[0] = *(register_t *)ARM_TP_ADDRESS;
 #endif
diff --git a/sys/arm/arm/vm_machdep.c b/sys/arm/arm/vm_machdep.c
index e0b7892b1f84..ac525431baa4 100644
--- a/sys/arm/arm/vm_machdep.c
+++ b/sys/arm/arm/vm_machdep.c
@@ -82,8 +82,8 @@ __FBSDID("$FreeBSD$");
  * struct switchframe and trapframe must both be a multiple of 8
  * for correct stack alignment.
  */
-CTASSERT(sizeof(struct switchframe) == 48);
-CTASSERT(sizeof(struct trapframe) == 80);
+_Static_assert((sizeof(struct switchframe) % 8) == 0, "Bad alignment");
+_Static_assert((sizeof(struct trapframe) % 8) == 0, "Bad alignment");
 
 uint32_t initial_fpscr = VFPSCR_DN | VFPSCR_FZ;
 
@@ -134,6 +134,9 @@ cpu_fork(register struct thread *td1, register struct proc *p2,
 	pcb2->pcb_regs.sf_r5 = (register_t)td2;
 	pcb2->pcb_regs.sf_lr = (register_t)fork_trampoline;
 	pcb2->pcb_regs.sf_sp = STACKALIGN(td2->td_frame);
+#if __ARM_ARCH >= 6
+	pcb2->pcb_regs.sf_tpidrurw = (register_t)get_tls();
+#endif
 
 	pcb2->pcb_vfpcpu = -1;
 	pcb2->pcb_vfpstate.fpscr = initial_fpscr;
@@ -147,9 +150,7 @@ cpu_fork(register struct thread *td1, register struct proc *p2,
 	/* Setup to release spin count in fork_exit(). */
 	td2->td_md.md_spinlock_count = 1;
 	td2->td_md.md_saved_cspr = PSR_SVC32_MODE;
-#if __ARM_ARCH >= 6
-	td2->td_md.md_tp = td1->td_md.md_tp;
-#else
+#if __ARM_ARCH < 6
 	td2->td_md.md_tp = *(register_t *)ARM_TP_ADDRESS;
 #endif
 }
@@ -272,16 +273,18 @@ int
 cpu_set_user_tls(struct thread *td, void *tls_base)
 {
 
-	td->td_md.md_tp = (register_t)tls_base;
-	if (td == curthread) {
-		critical_enter();
 #if __ARM_ARCH >= 6
+	td->td_pcb->pcb_regs.sf_tpidrurw = (register_t)tls_base;
+	if (td == curthread)
 		set_tls(tls_base);
 #else
+	td->td_md.md_tp = (register_t)tls_base;
+	if (td == curthread) {
+		critical_enter();
 		*(register_t *)ARM_TP_ADDRESS = (register_t)tls_base;
-#endif
 		critical_exit();
 	}
+#endif
 	return (0);
 }
 
diff --git a/sys/arm/at91/at91_common.c b/sys/arm/at91/at91_common.c
index 49ad0659b7ac..696161f34001 100644
--- a/sys/arm/at91/at91_common.c
+++ b/sys/arm/at91/at91_common.c
@@ -49,10 +49,6 @@ __FBSDID("$FreeBSD$");
 
 extern const struct devmap_entry at91_devmap[];
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_aic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_common.c b/sys/arm/broadcom/bcm2835/bcm2835_common.c
index e7ce52b2a898..6f136f81da99 100644
--- a/sys/arm/broadcom/bcm2835/bcm2835_common.c
+++ b/sys/arm/broadcom/bcm2835/bcm2835_common.c
@@ -46,10 +46,6 @@ __FBSDID("$FreeBSD$");
 #include <machine/bus.h>
 #include <machine/vmparam.h>
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_machdep.c b/sys/arm/broadcom/bcm2835/bcm2835_machdep.c
index 811c1088d8b0..87275ae6c59e 100644
--- a/sys/arm/broadcom/bcm2835/bcm2835_machdep.c
+++ b/sys/arm/broadcom/bcm2835/bcm2835_machdep.c
@@ -42,7 +42,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -113,25 +112,12 @@ bcm2836_devmap_init(platform_t plat)
 }
 #endif
 
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
 
-	return (0);
-}
 
-void
-cpu_reset()
+static void
+bcm2835_cpu_reset(platform_t plat)
 {
 	bcmwd_watchdog_reset();
-	while (1);
 }
 
 #ifdef SOC_BCM2835
@@ -139,6 +125,7 @@ static platform_method_t bcm2835_methods[] = {
 	PLATFORMMETHOD(platform_devmap_init,	bcm2835_devmap_init),
 	PLATFORMMETHOD(platform_lastaddr,	bcm2835_lastaddr),
 	PLATFORMMETHOD(platform_late_init,	bcm2835_late_init),
+	PLATFORMMETHOD(platform_cpu_reset,	bcm2835_cpu_reset),
 
 	PLATFORMMETHOD_END,
 };
@@ -150,6 +137,7 @@ static platform_method_t bcm2836_methods[] = {
 	PLATFORMMETHOD(platform_devmap_init,	bcm2836_devmap_init),
 	PLATFORMMETHOD(platform_lastaddr,	bcm2835_lastaddr),
 	PLATFORMMETHOD(platform_late_init,	bcm2835_late_init),
+	PLATFORMMETHOD(platform_cpu_reset,	bcm2835_cpu_reset),
 
 	PLATFORMMETHOD_END,
 };
diff --git a/sys/arm/cloudabi32/cloudabi32_sysvec.c b/sys/arm/cloudabi32/cloudabi32_sysvec.c
new file mode 100644
index 000000000000..040dcc323c9f
--- /dev/null
+++ b/sys/arm/cloudabi32/cloudabi32_sysvec.c
@@ -0,0 +1,193 @@
+/*-
+ * Copyright (c) 2015-2016 Nuxi, https://nuxi.nl/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/imgact.h>
+#include <sys/kernel.h>
+#include <sys/proc.h>
+#include <sys/sysent.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <machine/frame.h>
+#include <machine/pcb.h>
+#include <machine/vmparam.h>
+
+#include <compat/cloudabi/cloudabi_util.h>
+
+#include <compat/cloudabi32/cloudabi32_syscall.h>
+#include <compat/cloudabi32/cloudabi32_util.h>
+
+extern const char *cloudabi32_syscallnames[];
+extern struct sysent cloudabi32_sysent[];
+
+static void
+cloudabi32_proc_setregs(struct thread *td, struct image_params *imgp,
+    unsigned long stack)
+{
+	struct trapframe *regs;
+
+	exec_setregs(td, imgp, stack);
+
+	/*
+	 * The stack now contains a pointer to the TCB and the auxiliary
+	 * vector. Let r0 point to the auxiliary vector, and set
+	 * tpidrurw to the TCB.
+	 */
+	regs = td->td_frame;
+	regs->tf_r0 = td->td_retval[0] =
+	    stack + roundup(sizeof(cloudabi32_tcb_t), sizeof(register_t));
+	(void)cpu_set_user_tls(td, (void *)stack);
+}
+
+static int
+cloudabi32_fetch_syscall_args(struct thread *td, struct syscall_args *sa)
+{
+	struct trapframe *frame = td->td_frame;
+	int error;
+
+	/* Obtain system call number. */
+	sa->code = frame->tf_r12;
+	if (sa->code >= CLOUDABI32_SYS_MAXSYSCALL)
+		return (ENOSYS);
+	sa->callp = &cloudabi32_sysent[sa->code];
+	sa->narg = sa->callp->sy_narg;
+
+	/* Fetch system call arguments from registers and the stack. */
+	sa->args[0] = frame->tf_r0;
+	sa->args[1] = frame->tf_r1;
+	sa->args[2] = frame->tf_r2;
+	sa->args[3] = frame->tf_r3;
+	if (sa->narg > 4) {
+		error = copyin((void *)td->td_frame->tf_usr_sp, &sa->args[4],
+		    (sa->narg - 4) * sizeof(register_t));
+		if (error != 0)
+			return (error);
+	}
+
+	/* Default system call return values. */
+	td->td_retval[0] = 0;
+	td->td_retval[1] = frame->tf_r1;
+	return (0);
+}
+
+static void
+cloudabi32_set_syscall_retval(struct thread *td, int error)
+{
+	struct trapframe *frame = td->td_frame;
+
+	switch (error) {
+	case 0:
+		/* System call succeeded. */
+		frame->tf_r0 = td->td_retval[0];
+		frame->tf_r1 = td->td_retval[1];
+		frame->tf_spsr &= ~PSR_C;
+		break;
+	case ERESTART:
+		/* Restart system call. */
+		frame->tf_pc -= 4;
+		break;
+	case EJUSTRETURN:
+		break;
+	default:
+		/* System call returned an error. */
+		frame->tf_r0 = cloudabi_convert_errno(error);
+		frame->tf_spsr |= PSR_C;
+		break;
+	}
+}
+
+static void
+cloudabi32_schedtail(struct thread *td)
+{
+	struct trapframe *frame = td->td_frame;
+
+	/*
+	 * Initial register values for processes returning from fork.
+	 * Make sure that we only set these values when forking, not
+	 * when creating a new thread.
+	 */
+	if ((td->td_pflags & TDP_FORKING) != 0) {
+		frame->tf_r0 = CLOUDABI_PROCESS_CHILD;
+		frame->tf_r1 = td->td_tid;
+	}
+}
+
+int
+cloudabi32_thread_setregs(struct thread *td,
+    const cloudabi32_threadattr_t *attr, uint32_t tcb)
+{
+	struct trapframe *frame;
+	stack_t stack;
+
+	/* Perform standard register initialization. */
+	stack.ss_sp = TO_PTR(attr->stack);
+	stack.ss_size = attr->stack_size;
+	cpu_set_upcall(td, TO_PTR(attr->entry_point), NULL, &stack);
+
+	/*
+	 * Pass in the thread ID of the new thread and the argument
+	 * pointer provided by the parent thread in as arguments to the
+	 * entry point.
+	 */
+	frame = td->td_frame;
+	frame->tf_r0 = td->td_tid;
+	frame->tf_r1 = attr->argument;
+
+	/* Set up TLS. */
+	return (cpu_set_user_tls(td, (void *)tcb));
+}
+
+static struct sysentvec cloudabi32_elf_sysvec = {
+	.sv_size		= CLOUDABI32_SYS_MAXSYSCALL,
+	.sv_table		= cloudabi32_sysent,
+	.sv_fixup		= cloudabi32_fixup,
+	.sv_name		= "CloudABI ELF32",
+	.sv_coredump		= elf32_coredump,
+	.sv_pagesize		= PAGE_SIZE,
+	.sv_minuser		= VM_MIN_ADDRESS,
+	.sv_maxuser		= VM_MAXUSER_ADDRESS,
+	.sv_stackprot		= VM_PROT_READ | VM_PROT_WRITE,
+	.sv_copyout_strings	= cloudabi32_copyout_strings,
+	.sv_setregs		= cloudabi32_proc_setregs,
+	.sv_flags		= SV_ABI_CLOUDABI | SV_CAPSICUM | SV_ILP32,
+	.sv_set_syscall_retval	= cloudabi32_set_syscall_retval,
+	.sv_fetch_syscall_args	= cloudabi32_fetch_syscall_args,
+	.sv_syscallnames	= cloudabi32_syscallnames,
+	.sv_schedtail		= cloudabi32_schedtail,
+};
+
+INIT_SYSENTVEC(elf_sysvec, &cloudabi32_elf_sysvec);
+
+Elf32_Brandinfo cloudabi32_brand = {
+	.brand		= ELFOSABI_CLOUDABI,
+	.machine	= EM_ARM,
+	.sysvec		= &cloudabi32_elf_sysvec,
+	.compat_3_brand	= "CloudABI",
+};
diff --git a/sys/arm/conf/ALPINE b/sys/arm/conf/ALPINE
index c1f4eca3efce..b231df14f3c3 100644
--- a/sys/arm/conf/ALPINE
+++ b/sys/arm/conf/ALPINE
@@ -60,6 +60,11 @@ device		ses		# Enclosure Services (SES and SAF-TE)
 # Serial ports
 device		uart
 
+# PCI/PCIE
+device		pci
+device		pci_host_generic
+device		al_pci		# Annapurna Alpine PCI-E
+
 # Ethernet
 device		ether
 device		mii
diff --git a/sys/arm/freescale/imx/imx51_machdep.c b/sys/arm/freescale/imx/imx51_machdep.c
index 748cb108467f..645d2810b3dd 100644
--- a/sys/arm/freescale/imx/imx51_machdep.c
+++ b/sys/arm/freescale/imx/imx51_machdep.c
@@ -81,8 +81,8 @@ imx51_devmap_init(platform_t plat)
 	return (0);
 }
 
-void
-cpu_reset(void)
+static void
+imx51_cpu_reset(platform_t plat)
 {
 
 	imx_wdog_cpu_reset(0x73F98000);
@@ -97,6 +97,7 @@ static platform_method_t imx51_methods[] = {
 	PLATFORMMETHOD(platform_attach,		imx51_attach),
 	PLATFORMMETHOD(platform_devmap_init,	imx51_devmap_init),
 	PLATFORMMETHOD(platform_lastaddr,	imx51_lastaddr),
+	PLATFORMMETHOD(platform_cpu_reset,	imx51_cpu_reset),
 
 	PLATFORMMETHOD_END,
 };
diff --git a/sys/arm/freescale/imx/imx53_machdep.c b/sys/arm/freescale/imx/imx53_machdep.c
index 96d0f5a4f74a..7596a2082f57 100644
--- a/sys/arm/freescale/imx/imx53_machdep.c
+++ b/sys/arm/freescale/imx/imx53_machdep.c
@@ -81,8 +81,8 @@ imx53_devmap_init(platform_t plat)
 	return (0);
 }
 
-void
-cpu_reset(void)
+static void
+imx53_cpu_reset(platform_t plat)
 {
 
 	imx_wdog_cpu_reset(0x53F98000);
@@ -97,6 +97,7 @@ static platform_method_t imx53_methods[] = {
 	PLATFORMMETHOD(platform_attach,		imx53_attach),
 	PLATFORMMETHOD(platform_devmap_init,	imx53_devmap_init),
 	PLATFORMMETHOD(platform_lastaddr,	imx53_lastaddr),
+	PLATFORMMETHOD(platform_cpu_reset,	imx53_cpu_reset),
 
 	PLATFORMMETHOD_END,
 };
diff --git a/sys/arm/freescale/imx/imx6_machdep.c b/sys/arm/freescale/imx/imx6_machdep.c
index 7a4311d807a8..ad826787a1a6 100644
--- a/sys/arm/freescale/imx/imx6_machdep.c
+++ b/sys/arm/freescale/imx/imx6_machdep.c
@@ -52,10 +52,6 @@ __FBSDID("$FreeBSD$");
 
 #include "platform_if.h"
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 static uint32_t gpio1_node;
 
 #ifndef INTRNG
@@ -227,8 +223,8 @@ imx6_devmap_init(platform_t plat)
 	return (0);
 }
 
-void
-cpu_reset(void)
+static void
+imx6_cpu_reset(platform_t plat)
 {
 	const uint32_t IMX6_WDOG_CR_PHYS = 0x020bc000;
 
@@ -350,6 +346,7 @@ static platform_method_t imx6_methods[] = {
 	PLATFORMMETHOD(platform_lastaddr,	imx6_lastaddr),
 	PLATFORMMETHOD(platform_devmap_init,	imx6_devmap_init),
 	PLATFORMMETHOD(platform_late_init,	imx6_late_init),
+	PLATFORMMETHOD(platform_cpu_reset,	imx6_cpu_reset),
 
 	PLATFORMMETHOD_END,
 };
diff --git a/sys/arm/freescale/imx/imx_common.c b/sys/arm/freescale/imx/imx_common.c
index c423873c80c3..3eb076e0b51f 100644
--- a/sys/arm/freescale/imx/imx_common.c
+++ b/sys/arm/freescale/imx/imx_common.c
@@ -50,10 +50,6 @@ __FBSDID("$FreeBSD$");
 #include <machine/bus.h>
 #include <machine/vmparam.h>
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
diff --git a/sys/arm/freescale/imx/imx_machdep.c b/sys/arm/freescale/imx/imx_machdep.c
index 6ef44a4e6220..3c607140c605 100644
--- a/sys/arm/freescale/imx/imx_machdep.c
+++ b/sys/arm/freescale/imx/imx_machdep.c
@@ -29,7 +29,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/reboot.h>
@@ -54,20 +53,6 @@ SYSCTL_UINT(_hw_imx, OID_AUTO, last_reset_status, CTLFLAG_RD,
 SYSCTL_STRING(_hw_imx, OID_AUTO, last_reset_reason, CTLFLAG_RD, 
     "unknown", 0, "Last reset reason");
 
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
-
 /*
  * This code which manipulates the watchdog hardware is here to implement
  * cpu_reset() because the watchdog is the only way for software to reset the
diff --git a/sys/arm/freescale/vybrid/vf_common.c b/sys/arm/freescale/vybrid/vf_common.c
index 494f5d60e0c1..d57748172822 100644
--- a/sys/arm/freescale/vybrid/vf_common.c
+++ b/sys/arm/freescale/vybrid/vf_common.c
@@ -62,10 +62,6 @@ end:
 	while (1);
 }
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
diff --git a/sys/arm/freescale/vybrid/vf_machdep.c b/sys/arm/freescale/vybrid/vf_machdep.c
index d32ba0d527a4..15566a4f3837 100644
--- a/sys/arm/freescale/vybrid/vf_machdep.c
+++ b/sys/arm/freescale/vybrid/vf_machdep.c
@@ -30,7 +30,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define	_ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -78,17 +77,3 @@ platform_devmap_init(void)
 
 	return (0);
 }
-
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
diff --git a/sys/arm/include/bus_dma.h b/sys/arm/include/bus_dma.h
index ddf5504dbafd..129511871f42 100644
--- a/sys/arm/include/bus_dma.h
+++ b/sys/arm/include/bus_dma.h
@@ -72,7 +72,7 @@
 
 #define BUS_DMA_TAG_VALID(t)    ((t) != (bus_dma_tag_t)0)
 
-#ifdef _ARM32_BUS_DMA_PRIVATE
+#if defined(_ARM32_BUS_DMA_PRIVATE) && __ARM_ARCH < 6
 /*
  *	arm32_dma_range
  *
diff --git a/sys/arm/include/efi.h b/sys/arm/include/efi.h
new file mode 100644
index 000000000000..476e18428c4b
--- /dev/null
+++ b/sys/arm/include/efi.h
@@ -0,0 +1,37 @@
+/*-
+ * Copyright (c) 2016 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef __ARM_INCLUDE_EFI_H_
+#define __ARM_INCLUDE_EFI_H_
+
+#define	EFIABI_ATTR
+
+#endif /* __ARM_INCLUDE_EFI_H_ */
diff --git a/sys/arm/include/frame.h b/sys/arm/include/frame.h
index 7655d89cadc2..929bc962d756 100644
--- a/sys/arm/include/frame.h
+++ b/sys/arm/include/frame.h
@@ -117,6 +117,10 @@ struct switchframe
         register_t sf_sp;
         register_t sf_lr;
         register_t sf_pc;
+#if __ARM_ARCH >= 6
+        register_t sf_tpidrurw;
+        register_t sf_spare0;
+#endif
 };
 
 
diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h
index 19cb666b42d0..c9ebd5e3156f 100644
--- a/sys/arm/include/pcpu.h
+++ b/sys/arm/include/pcpu.h
@@ -103,7 +103,8 @@ get_tls(void)
 {
 	void *tls;
 
-	__asm __volatile("mrc p15, 0, %0, c13, c0, 3" : "=r" (tls));
+	/* TPIDRURW contains the authoritative value. */
+	__asm __volatile("mrc p15, 0, %0, c13, c0, 2" : "=r" (tls));
 	return (tls);
 }
 
@@ -111,7 +112,15 @@ static inline void
 set_tls(void *tls)
 {
 
-	__asm __volatile("mcr p15, 0, %0, c13, c0, 3" : : "r" (tls));
+	/*
+	 * Update both TPIDRURW and TPIDRURO. TPIDRURW needs to be written
+	 * first to ensure that a context switch between the two writes will
+	 * still give the desired result of updating both.
+	 */
+	__asm __volatile(
+	    "mcr p15, 0, %0, c13, c0, 2\n"
+	    "mcr p15, 0, %0, c13, c0, 3\n"
+	     : : "r" (tls));
 }
 
 #define curthread get_curthread()
diff --git a/sys/arm/include/proc.h b/sys/arm/include/proc.h
index 5d42d0748128..fc4b31eabac1 100644
--- a/sys/arm/include/proc.h
+++ b/sys/arm/include/proc.h
@@ -53,8 +53,8 @@ struct mdthread {
 	int md_ptrace_addr;
 	int md_ptrace_instr_alt;
 	int md_ptrace_addr_alt;
-	register_t md_tp;
 #if __ARM_ARCH < 6
+	register_t md_tp;
 	void *md_ras_start;
 	void *md_ras_end;
 #endif
diff --git a/sys/arm/lpc/lpc_intc.c b/sys/arm/lpc/lpc_intc.c
index db7c300aa326..d26ef9099c74 100644
--- a/sys/arm/lpc/lpc_intc.c
+++ b/sys/arm/lpc/lpc_intc.c
@@ -227,10 +227,6 @@ lpc_intc_eoi(void *data)
 
 }
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
diff --git a/sys/arm/mv/mv_machdep.c b/sys/arm/mv/mv_machdep.c
index a1d7d49fbd33..ce9766370ddc 100644
--- a/sys/arm/mv/mv_machdep.c
+++ b/sys/arm/mv/mv_machdep.c
@@ -432,6 +432,7 @@ platform_devmap_init(void)
 	return (0);
 }
 
+#if __ARM_ARCH < 6
 struct arm32_dma_range *
 bus_dma_get_range(void)
 {
@@ -445,6 +446,7 @@ bus_dma_get_range_nb(void)
 
 	return (0);
 }
+#endif
 
 #if defined(CPU_MV_PJ4B)
 #ifdef DDB
diff --git a/sys/arm/nvidia/tegra124/tegra124_machdep.c b/sys/arm/nvidia/tegra124/tegra124_machdep.c
index 70c31da5f81f..dba6b6ec8b9f 100644
--- a/sys/arm/nvidia/tegra124/tegra124_machdep.c
+++ b/sys/arm/nvidia/tegra124/tegra124_machdep.c
@@ -24,7 +24,6 @@
  * SUCH DAMAGE.
  */
 
-#define	_ARM32_BUS_DMA_PRIVATE
 #include "opt_platform.h"
 
 #include <sys/cdefs.h>
@@ -62,24 +61,6 @@ __FBSDID("$FreeBSD$");
 					PMC_SCRATCH0_MODE_BOOTLOADER | \
 					PMC_SCRATCH0_MODE_RCM)
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
-
 static vm_offset_t
 tegra124_lastaddr(platform_t plat)
 {
@@ -112,8 +93,8 @@ tegra124_devmap_init(platform_t plat)
 	return (0);
 }
 
-void
-cpu_reset(void)
+static void
+tegra124_cpu_reset(platform_t plat)
 {
 	bus_space_handle_t pmc;
 	uint32_t reg;
@@ -163,6 +144,8 @@ static platform_method_t tegra124_methods[] = {
 	PLATFORMMETHOD(platform_lastaddr,	tegra124_lastaddr),
 	PLATFORMMETHOD(platform_devmap_init,	tegra124_devmap_init),
 	PLATFORMMETHOD(platform_late_init,	tegra124_late_init),
+	PLATFORMMETHOD(platform_cpu_reset,	tegra124_cpu_reset),
+
 #ifdef SMP
 	PLATFORMMETHOD(platform_mp_start_ap,	tegra124_mp_start_ap),
 	PLATFORMMETHOD(platform_mp_setmaxid,	tegra124_mp_setmaxid),
diff --git a/sys/arm/qemu/virt_common.c b/sys/arm/qemu/virt_common.c
index 03cba309308d..cda02e539e66 100644
--- a/sys/arm/qemu/virt_common.c
+++ b/sys/arm/qemu/virt_common.c
@@ -37,10 +37,6 @@ __FBSDID("$FreeBSD$");
 
 #include <machine/intr.h>
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 fdt_pic_decode_t fdt_pic_table[] = {
 	&gic_decode_fdt,
diff --git a/sys/arm/qemu/virt_machdep.c b/sys/arm/qemu/virt_machdep.c
index d15b97c5e071..08ea4602dd33 100644
--- a/sys/arm/qemu/virt_machdep.c
+++ b/sys/arm/qemu/virt_machdep.c
@@ -30,7 +30,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/devmap.h>
@@ -45,27 +44,6 @@ __FBSDID("$FreeBSD$");
 
 #include "platform_if.h"
 
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
-
-void
-cpu_reset(void)
-{
-
-	while (1);
-}
-
 static vm_offset_t
 virt_lastaddr(platform_t plat)
 {
diff --git a/sys/arm/rockchip/rk30xx_common.c b/sys/arm/rockchip/rk30xx_common.c
index aa66b72101a3..826ebda79817 100644
--- a/sys/arm/rockchip/rk30xx_common.c
+++ b/sys/arm/rockchip/rk30xx_common.c
@@ -38,10 +38,6 @@ __FBSDID("$FreeBSD$");
 #include <machine/bus.h>
 #include <machine/vmparam.h>
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_aintc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
diff --git a/sys/arm/rockchip/rk30xx_machdep.c b/sys/arm/rockchip/rk30xx_machdep.c
index db34d332d67b..bb3731504d90 100644
--- a/sys/arm/rockchip/rk30xx_machdep.c
+++ b/sys/arm/rockchip/rk30xx_machdep.c
@@ -34,7 +34,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -92,20 +91,6 @@ platform_devmap_init(void)
 	return (0);
 }
 
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
-
 void
 cpu_reset()
 {
diff --git a/sys/arm/samsung/exynos/exynos5_common.c b/sys/arm/samsung/exynos/exynos5_common.c
index b91e0830e1ec..04021c1cb919 100644
--- a/sys/arm/samsung/exynos/exynos5_common.c
+++ b/sys/arm/samsung/exynos/exynos5_common.c
@@ -49,10 +49,6 @@ cpu_reset(void)
 	while (1);
 }
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
diff --git a/sys/arm/samsung/exynos/exynos5_machdep.c b/sys/arm/samsung/exynos/exynos5_machdep.c
index 6483a7a00e9d..76a5af13bb19 100644
--- a/sys/arm/samsung/exynos/exynos5_machdep.c
+++ b/sys/arm/samsung/exynos/exynos5_machdep.c
@@ -30,7 +30,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define	_ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -83,17 +82,3 @@ platform_devmap_init(void)
 
 	return (0);
 }
-
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
diff --git a/sys/arm/ti/am335x/am335x_musb.c b/sys/arm/ti/am335x/am335x_musb.c
index b92be0d20dec..4dc96c35a114 100644
--- a/sys/arm/ti/am335x/am335x_musb.c
+++ b/sys/arm/ti/am335x/am335x_musb.c
@@ -237,6 +237,7 @@ static int
 musbotg_attach(device_t dev)
 {
 	struct musbotg_super_softc *sc = device_get_softc(dev);
+	char mode[16];
 	int err;
 	uint32_t reg;
 
@@ -308,10 +309,19 @@ musbotg_attach(device_t dev)
 	}
 
 	sc->sc_otg.sc_platform_data = sc;
-	if (sc->sc_otg.sc_id == 0)
-		sc->sc_otg.sc_mode = MUSB2_DEVICE_MODE;
-	else
-		sc->sc_otg.sc_mode = MUSB2_HOST_MODE;
+	if (OF_getprop(ofw_bus_get_node(dev), "dr_mode", mode,
+	    sizeof(mode)) > 0) {
+		if (strcasecmp(mode, "host") == 0)
+			sc->sc_otg.sc_mode = MUSB2_HOST_MODE;
+		else
+			sc->sc_otg.sc_mode = MUSB2_DEVICE_MODE;
+	} else {
+		/* Beaglebone defaults: USB0 device, USB1 HOST. */
+		if (sc->sc_otg.sc_id == 0)
+			sc->sc_otg.sc_mode = MUSB2_DEVICE_MODE;
+		else
+			sc->sc_otg.sc_mode = MUSB2_HOST_MODE;
+	}
 
 	/*
 	 * software-controlled function
diff --git a/sys/arm/ti/ti_common.c b/sys/arm/ti/ti_common.c
index 41c5a72c210c..64a7830f6a5c 100644
--- a/sys/arm/ti/ti_common.c
+++ b/sys/arm/ti/ti_common.c
@@ -49,10 +49,6 @@ __FBSDID("$FreeBSD$");
 #include <machine/intr.h>
 #include <machine/vmparam.h>
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 #ifdef SOC_TI_AM335X
 static int
diff --git a/sys/arm/ti/ti_machdep.c b/sys/arm/ti/ti_machdep.c
index f8d53952b010..0e10f765ff15 100644
--- a/sys/arm/ti/ti_machdep.c
+++ b/sys/arm/ti/ti_machdep.c
@@ -40,7 +40,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -96,35 +95,20 @@ ti_am335x_devmap_init(platform_t plat)
 }
 #endif
 
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
-
-void
-cpu_reset()
+static void
+ti_plat_cpu_reset(platform_t plat)
 {
 	if (ti_cpu_reset)
 		(*ti_cpu_reset)();
 	else
 		printf("no cpu_reset implementation\n");
-	printf("Reset failed!\n");
-	while (1);
 }
 
 #if defined(SOC_OMAP4)
 static platform_method_t omap4_methods[] = {
 	PLATFORMMETHOD(platform_devmap_init,	ti_omap4_devmap_init),
 	PLATFORMMETHOD(platform_lastaddr,	ti_lastaddr),
+	PLATFORMMETHOD(platform_cpu_reset,	ti_plat_cpu_reset),
 
 	PLATFORMMETHOD_END,
 };
@@ -135,6 +119,7 @@ FDT_PLATFORM_DEF(omap4, "omap4", 0, "ti,omap4430", 0);
 static platform_method_t am335x_methods[] = {
 	PLATFORMMETHOD(platform_devmap_init,	ti_am335x_devmap_init),
 	PLATFORMMETHOD(platform_lastaddr,	ti_lastaddr),
+	PLATFORMMETHOD(platform_cpu_reset,	ti_plat_cpu_reset),
 
 	PLATFORMMETHOD_END,
 };
diff --git a/sys/arm/versatile/versatile_common.c b/sys/arm/versatile/versatile_common.c
index aca54b7eb8ee..983b3ce018b5 100644
--- a/sys/arm/versatile/versatile_common.c
+++ b/sys/arm/versatile/versatile_common.c
@@ -46,10 +46,6 @@ __FBSDID("$FreeBSD$");
 #include <machine/bus.h>
 #include <machine/vmparam.h>
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
diff --git a/sys/arm/versatile/versatile_machdep.c b/sys/arm/versatile/versatile_machdep.c
index adaff7aeeec1..a0c97eeed154 100644
--- a/sys/arm/versatile/versatile_machdep.c
+++ b/sys/arm/versatile/versatile_machdep.c
@@ -39,7 +39,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -102,20 +101,6 @@ platform_devmap_init(void)
 	return (0);
 }
 
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
-
 void
 cpu_reset()
 {
diff --git a/sys/arm/xilinx/zy7_machdep.c b/sys/arm/xilinx/zy7_machdep.c
index 47768782188c..771503d7dd38 100644
--- a/sys/arm/xilinx/zy7_machdep.c
+++ b/sys/arm/xilinx/zy7_machdep.c
@@ -36,7 +36,6 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define _ARM32_BUS_DMA_PRIVATE
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -94,10 +93,6 @@ platform_devmap_init(void)
 }
 
 
-struct fdt_fixup_entry fdt_fixup_table[] = {
-	{ NULL, NULL }
-};
-
 #ifndef INTRNG
 static int
 fdt_gic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
@@ -120,20 +115,6 @@ fdt_pic_decode_t fdt_pic_table[] = {
 };
 #endif
 
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-
-	return (NULL);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-
-	return (0);
-}
-
 void
 cpu_reset()
 {
diff --git a/sys/arm64/arm64/gic_v3.c b/sys/arm64/arm64/gic_v3.c
index 85f58a98c956..0110ebd734f2 100644
--- a/sys/arm64/arm64/gic_v3.c
+++ b/sys/arm64/arm64/gic_v3.c
@@ -503,12 +503,33 @@ gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
 #endif
 
 static int
+gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp,
+    enum intr_polarity *polp, enum intr_trigger *trigp)
+{
+	struct gic_v3_irqsrc *gi;
+
+	/* SPI-mapped MSI */
+	gi = (struct gic_v3_irqsrc *)msi_data->isrc;
+	if (gi == NULL)
+		return (ENXIO);
+
+	*irqp = gi->gi_irq;
+
+	/* MSI/MSI-X interrupts are always edge triggered with high polarity */
+	*polp = INTR_POLARITY_HIGH;
+	*trigp = INTR_TRIGGER_EDGE;
+
+	return (0);
+}
+
+static int
 do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
     enum intr_polarity *polp, enum intr_trigger *trigp)
 {
 	struct gic_v3_softc *sc;
 	enum intr_polarity pol;
 	enum intr_trigger trig;
+	struct intr_map_data_msi *dam;
 #ifdef FDT
 	struct intr_map_data_fdt *daf;
 #endif
@@ -525,6 +546,12 @@ do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp,
 			return (EINVAL);
 		break;
 #endif
+	case INTR_MAP_DATA_MSI:
+		/* SPI-mapped MSI */
+		dam = (struct intr_map_data_msi *)data;
+		if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0)
+			return (EINVAL);
+		break;
 	default:
 		return (EINVAL);
 	}
diff --git a/sys/arm64/arm64/gic_v3_fdt.c b/sys/arm64/arm64/gic_v3_fdt.c
index c3f50f06d032..88b879224ecd 100644
--- a/sys/arm64/arm64/gic_v3_fdt.c
+++ b/sys/arm64/arm64/gic_v3_fdt.c
@@ -145,6 +145,9 @@ gic_v3_fdt_attach(device_t dev)
 		goto error;
 	}
 
+	/* Register xref */
+	OF_device_register_xref(xref, dev);
+
 	if (intr_pic_claim_root(dev, xref, arm_gic_v3_intr, sc,
 	    GIC_LAST_SGI - GIC_FIRST_SGI + 1) != 0) {
 		err = ENXIO;
diff --git a/sys/arm64/arm64/machdep.c b/sys/arm64/arm64/machdep.c
index 3d2e6fb81b9f..0826938436ca 100644
--- a/sys/arm64/arm64/machdep.c
+++ b/sys/arm64/arm64/machdep.c
@@ -699,9 +699,6 @@ add_fdt_mem_regions(struct mem_region *mr, int mrcnt, vm_paddr_t *physmap,
 }
 #endif
 
-#define efi_next_descriptor(ptr, size) \
-	((struct efi_md *)(((uint8_t *) ptr) + size))
-
 static void
 add_efi_map_entries(struct efi_map_header *efihdr, vm_paddr_t *physmap,
     u_int *physmap_idxp)
diff --git a/sys/arm64/conf/GENERIC b/sys/arm64/conf/GENERIC
index 35633ec5c055..f2d0e34c280f 100644
--- a/sys/arm64/conf/GENERIC
+++ b/sys/arm64/conf/GENERIC
@@ -105,6 +105,7 @@ device		cpufreq
 
 # Bus drivers
 device		pci
+device		al_pci		# Annapurna Alpine PCI-E
 options 	PCI_HP			# PCI-Express native HotPlug
 options 	PCI_IOV		# PCI SR-IOV support
 
diff --git a/sys/arm64/include/efi.h b/sys/arm64/include/efi.h
new file mode 100644
index 000000000000..5b5a7c49b503
--- /dev/null
+++ b/sys/arm64/include/efi.h
@@ -0,0 +1,37 @@
+/*-
+ * Copyright (c) 2016 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef __ARM64_INCLUDE_EFI_H_
+#define __ARM64_INCLUDE_EFI_H_
+
+#define	EFIABI_ATTR
+
+#endif /* __ARM64_INCLUDE_EFI_H_ */
diff --git a/sys/boot/efi/include/efilib.h b/sys/boot/efi/include/efilib.h
index 46c57d5ce746..09ccc2f36477 100644
--- a/sys/boot/efi/include/efilib.h
+++ b/sys/boot/efi/include/efilib.h
@@ -27,6 +27,9 @@
  * $FreeBSD$
  */
 
+#ifndef _LOADER_EFILIB_H
+#define	_LOADER_EFILIB_H
+
 #include <stand.h>
 
 extern EFI_HANDLE		IH;
@@ -61,3 +64,5 @@ void efi_time_fini(void);
 EFI_STATUS main(int argc, CHAR16 *argv[]);
 void exit(EFI_STATUS status);
 void delay(int usecs);
+
+#endif	/* _LOADER_EFILIB_H */
diff --git a/sys/boot/efi/libefi/time.c b/sys/boot/efi/libefi/time.c
index b73c8ccf2c90..99831e1cf1a8 100644
--- a/sys/boot/efi/libefi/time.c
+++ b/sys/boot/efi/libefi/time.c
@@ -228,7 +228,7 @@ time(time_t *tloc)
 }
 
 time_t
-getsecs()
+getsecs(void)
 {
     return time(0);
 }
diff --git a/sys/boot/efi/libefi/time_event.c b/sys/boot/efi/libefi/time_event.c
index 370a73c0edea..f96f1d845f6a 100644
--- a/sys/boot/efi/libefi/time_event.c
+++ b/sys/boot/efi/libefi/time_event.c
@@ -76,7 +76,7 @@ time(time_t *tloc)
 }
 
 time_t
-getsecs()
+getsecs(void)
 {
     return time(0);
 }
diff --git a/sys/boot/efi/loader/arch/amd64/Makefile.inc b/sys/boot/efi/loader/arch/amd64/Makefile.inc
index fee959b283d3..5649c1271f18 100644
--- a/sys/boot/efi/loader/arch/amd64/Makefile.inc
+++ b/sys/boot/efi/loader/arch/amd64/Makefile.inc
@@ -3,7 +3,9 @@
 SRCS+=	amd64_tramp.S \
 	start.S \
 	framebuffer.c \
-	elf64_freebsd.c
+	elf64_freebsd.c \
+	trap.c \
+	exc.S
 
 .PATH:	${.CURDIR}/../../i386/libi386
 SRCS+=	nullconsole.c \
diff --git a/sys/boot/efi/loader/arch/amd64/elf64_freebsd.c b/sys/boot/efi/loader/arch/amd64/elf64_freebsd.c
index a1d1a0f4bc98..37e9fe1b4b18 100644
--- a/sys/boot/efi/loader/arch/amd64/elf64_freebsd.c
+++ b/sys/boot/efi/loader/arch/amd64/elf64_freebsd.c
@@ -35,6 +35,8 @@ __FBSDID("$FreeBSD$");
 #include <string.h>
 #include <machine/elf.h>
 #include <stand.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
 
 #include <efi.h>
 #include <efilib.h>
@@ -57,8 +59,14 @@ extern int bi_load(char *args, vm_offset_t *modulep, vm_offset_t *kernendp);
 static int	elf64_exec(struct preloaded_file *amp);
 static int	elf64_obj_exec(struct preloaded_file *amp);
 
-static struct file_format amd64_elf = { elf64_loadfile, elf64_exec };
-static struct file_format amd64_elf_obj = { elf64_obj_loadfile, elf64_obj_exec };
+static struct file_format amd64_elf = {
+	.l_load = elf64_loadfile,
+	.l_exec = elf64_exec,
+};
+static struct file_format amd64_elf_obj = {
+	.l_load = elf64_obj_loadfile,
+	.l_exec = elf64_obj_exec,
+};
 
 struct file_format *file_formats[] = {
 	&amd64_elf,
@@ -66,21 +74,12 @@ struct file_format *file_formats[] = {
 	NULL
 };
 
-#define PG_V    0x001
-#define PG_RW   0x002
-#define PG_U    0x004
-#define PG_PS   0x080
-
-typedef u_int64_t p4_entry_t;
-typedef u_int64_t p3_entry_t;
-typedef u_int64_t p2_entry_t;
-static p4_entry_t *PT4;
-static p3_entry_t *PT3;
-static p2_entry_t *PT2;
+static pml4_entry_t *PT4;
+static pdp_entry_t *PT3;
+static pd_entry_t *PT2;
 
 static void (*trampoline)(uint64_t stack, void *copy_finish, uint64_t kernend,
-			  uint64_t modulep, p4_entry_t *pagetable,
-			  uint64_t entry);
+    uint64_t modulep, pml4_entry_t *pagetable, uint64_t entry);
 
 extern uintptr_t amd64_tramp;
 extern uint32_t amd64_tramp_size;
@@ -157,7 +156,7 @@ elf64_exec(struct preloaded_file *fp)
 	bcopy((void *)&amd64_tramp, (void *)trampcode, amd64_tramp_size);
 	trampoline = (void *)trampcode;
 
-	PT4 = (p4_entry_t *)0x0000000040000000;
+	PT4 = (pml4_entry_t *)0x0000000040000000;
 	err = BS->AllocatePages(AllocateMaxAddress, EfiLoaderData, 3,
 	    (EFI_PHYSICAL_ADDRESS *)&PT4);
 	bzero(PT4, 3 * EFI_PAGE_SIZE);
@@ -172,11 +171,11 @@ elf64_exec(struct preloaded_file *fp)
 	 */
 	for (i = 0; i < 512; i++) {
 		/* Each slot of the L4 pages points to the same L3 page. */
-		PT4[i] = (p4_entry_t)PT3;
+		PT4[i] = (pml4_entry_t)PT3;
 		PT4[i] |= PG_V | PG_RW | PG_U;
 
 		/* Each slot of the L3 pages points to the same L2 page. */
-		PT3[i] = (p3_entry_t)PT2;
+		PT3[i] = (pdp_entry_t)PT2;
 		PT3[i] |= PG_V | PG_RW | PG_U;
 
 		/* The L2 page slots are mapped with 2MB pages for 1GB. */
@@ -204,5 +203,6 @@ elf64_exec(struct preloaded_file *fp)
 static int
 elf64_obj_exec(struct preloaded_file *fp)
 {
+
 	return (EFTYPE);
 }
diff --git a/sys/boot/efi/loader/arch/amd64/exc.S b/sys/boot/efi/loader/arch/amd64/exc.S
new file mode 100644
index 000000000000..0035d4a37e20
--- /dev/null
+++ b/sys/boot/efi/loader/arch/amd64/exc.S
@@ -0,0 +1,165 @@
+/*-
+ * Copyright (c) 2016 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Konstantin Belousov under sponsorship
+ * from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+	.macro	EH	N, err=1
+	.align	8
+	.globl	EXC\N\()_handler
+EXC\N\()_handler:
+	.if	\err != 1
+	pushq	$0
+	.endif
+	pushq	%rax
+	pushq	%rdx
+	pushq	%rcx
+	movl	$\N,%ecx
+	jmp	all_handlers
+	.endm
+
+	.text
+	EH	0,0
+	EH	1,0
+	EH	2,0
+	EH	3,0
+	EH	4,0
+	EH	5,0
+	EH	6,0
+	EH	7,0
+	EH	8
+	EH	9,0
+	EH	10
+	EH	11
+	EH	12
+	EH	13
+	EH	14
+	EH	16,0
+	EH	17
+	EH	18,0
+	EH	19,0
+	EH	20,0
+
+	.globl	exc_rsp
+all_handlers:
+	cmpq	%rsp,exc_rsp(%rip)
+	je	exception
+
+	/*
+	 * Interrupt, not exception.
+	 * First, copy the hardware interrupt frame to the previous stack.
+	 * Our handler always has private IST stack.
+	 */
+	movq	(6*8)(%rsp),%rax	/* saved %rsp value, AKA old stack */
+	subq	(5*8),%rax
+	movq	(3*8)(%rsp),%rdx	/* copy %rip to old stack */
+	movq	%rdx,(%rax)
+	movq	(4*8)(%rsp),%rdx	/* copy %cs */
+	movq	%rdx,(1*8)(%rax)
+	movq	(5*8)(%rsp),%rdx	/* copy %rflags */
+	movq	%rdx,(2*8)(%rax)
+	movq	(6*8)(%rsp),%rdx	/* copy %rsp */
+	movq	%rdx,(3*8)(%rax)
+	movq	(7*8)(%rsp),%rdx	/* copy %ss */
+	movq	%rdx,(4*8)(%rax)
+
+	/*
+	 * Now simulate invocation of the original interrupt handler
+	 * with retq.  We switch stacks and execute retq from the old
+	 * stack since there is no free registers at the last moment.
+	 */
+	subq	$16,%rax
+	leaq	fw_intr_handlers(%rip),%rdx
+	movq	(%rdx,%rcx,8),%rdx /* push intr handler address on old stack */
+	movq	%rdx,8(%rax)
+	movq	(2*8)(%rsp),%rcx   /* saved %rax is put on top of old stack */
+	movq	%rcx,(%rax)
+	movq	(%rsp),%rcx
+	movq	8(%rsp),%rdx
+
+	movq	32(%rsp),%rsp	/* switch to old stack */
+	popq	%rax
+	retq
+
+exception:
+	/*
+	 * Form the struct trapframe on our IST stack.
+	 * Skip three words, which are currently busy with temporal
+	 * saves.
+	 */
+	pushq	%r15
+	pushq	%r14
+	pushq	%r13
+	pushq	%r12
+	pushq	%r11
+	pushq	%r10
+	pushq	%rbp
+	pushq	%rbx
+	pushq	$0	/* %rax	*/
+	pushq	%r9
+	pushq	%r8
+	pushq	$0	/* %rcx */
+	pushq	$0	/* %rdx	*/
+	pushq	%rsi
+	pushq	%rdi
+
+	/*
+	 * Move %rax, %rdx, %rcx values into the final location,
+	 * from the three words which were skipped above.
+	 */
+	movq	0x88(%rsp),%rax
+	movq	%rax,0x30(%rsp)	/* tf_rax */
+	movq	0x78(%rsp),%rax
+	movq	%rax,0x18(%rsp)	/* tf_rcx */
+	movq	0x80(%rsp),%rax
+	movq	%rax,0x10(%rsp)	/* tf_rdx */
+
+	/*
+	 * And fill the three words themself.
+	 */
+	movq	%cr2,%rax
+	movq	%rax,0x80(%rsp)	/* tf_addr */
+	movl	%ecx,0x78(%rsp)	/* tf_trapno */
+	movw	%ds,0x8e(%rsp)
+	movw	%es,0x8c(%rsp)
+	movw	%fs,0x7c(%rsp)
+	movw	%gs,0x7e(%rsp)
+	movw	$0,0x88(%rsp)	/* tf_flags */
+
+	/*
+	 * Call dump routine.
+	 */
+	movq	%rsp,%rdi
+	callq	report_exc
+
+	/*
+	 * Hang after reporting. Interrupts are already disabled.
+	 */
+1:
+	hlt
+	jmp	1b
diff --git a/sys/boot/efi/loader/arch/amd64/ldscript.amd64 b/sys/boot/efi/loader/arch/amd64/ldscript.amd64
index 609aedf2385d..53d9d760e0d0 100644
--- a/sys/boot/efi/loader/arch/amd64/ldscript.amd64
+++ b/sys/boot/efi/loader/arch/amd64/ldscript.amd64
@@ -19,7 +19,7 @@ SECTIONS
     /* .gnu.warning sections are handled specially by elf32.em. */
     *(.gnu.warning)
     *(.plt)
-  } =0xCC
+  } =0xCCCCCCCC
   . = ALIGN(4096);
   .data		: {
     *(.rodata .rodata.* .gnu.linkonce.r.*)
diff --git a/sys/boot/efi/loader/arch/amd64/trap.c b/sys/boot/efi/loader/arch/amd64/trap.c
new file mode 100644
index 000000000000..c8213495bf78
--- /dev/null
+++ b/sys/boot/efi/loader/arch/amd64/trap.c
@@ -0,0 +1,398 @@
+/*-
+ * Copyright (c) 2016 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Konstantin Belousov under sponsorship
+ * from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <stand.h>
+#include <string.h>
+#include <sys/param.h>
+#include <machine/cpufunc.h>
+#include <machine/psl.h>
+#include <machine/segments.h>
+#include <machine/frame.h>
+#include <machine/tss.h>
+
+#include <efi.h>
+#include <efilib.h>
+
+#include "bootstrap.h"
+#include "loader_efi.h"
+
+#define	NUM_IST	8
+#define	NUM_EXC	32
+
+/*
+ * This code catches exceptions but forwards hardware interrupts to
+ * handlers installed by firmware.  It differentiates exceptions
+ * vs. interrupts by presence of the error code on the stack, which
+ * causes different stack pointer value on trap handler entry.
+ *
+ * Use kernel layout for the trapframe just to not be original.
+ *
+ * Use free IST slot in existing TSS, or create our own TSS if
+ * firmware did not configured any, to have stack switched to
+ * IST-specified one, e.g. to handle #SS.  If hand-off cannot find
+ * unused IST slot, or create a new descriptor in GDT, we bail out.
+ */
+
+static struct region_descriptor fw_idt;	/* Descriptor for pristine fw IDT */
+static struct region_descriptor loader_idt;/* Descriptor for loader
+					   shadow IDT */
+static EFI_PHYSICAL_ADDRESS lidt_pa;	/* Address of loader shadow IDT */
+static EFI_PHYSICAL_ADDRESS tss_pa;	/* Address of TSS */
+static EFI_PHYSICAL_ADDRESS exc_stack_pa;/* Address of IST stack for loader */
+EFI_PHYSICAL_ADDRESS exc_rsp;	/* %rsp value on our IST stack when
+				   exception happens */
+EFI_PHYSICAL_ADDRESS fw_intr_handlers[NUM_EXC]; /* fw handlers for < 32 IDT
+						   vectors */
+static int intercepted[NUM_EXC];
+static int ist;				/* IST for exception handlers */
+static uint32_t tss_fw_seg;		/* Fw TSS segment */
+static uint32_t loader_tss;		/* Loader TSS segment */
+static struct region_descriptor fw_gdt;	/* Descriptor of pristine GDT */
+static EFI_PHYSICAL_ADDRESS loader_gdt_pa; /* Address of loader shadow GDT */
+
+void report_exc(struct trapframe *tf);
+void
+report_exc(struct trapframe *tf)
+{
+
+	/* XXX using printf */
+	printf("===================================================="
+	    "============================\n");
+	printf("Exception %u\n", tf->tf_trapno);
+	printf("ss 0x%04hx cs 0x%04hx ds 0x%04hx es 0x%04hx fs 0x%04hx "
+	    "gs 0x%04hx\n",
+	    (uint16_t)tf->tf_ss, (uint16_t)tf->tf_cs, (uint16_t)tf->tf_ds,
+	    (uint16_t)tf->tf_es, (uint16_t)tf->tf_fs, (uint16_t)tf->tf_gs);
+	printf("err 0x%08x rfl 0x%08x addr 0x%016lx\n"
+	    "rsp 0x%016lx rip 0x%016lx\n",
+	    (uint32_t)tf->tf_err, (uint32_t)tf->tf_rflags, tf->tf_addr,
+	    tf->tf_rsp, tf->tf_rip);
+	printf(
+	    "rdi 0x%016lx rsi 0x%016lx rdx 0x%016lx\n"
+	    "rcx 0x%016lx r8  0x%016lx r9  0x%016lx\n"
+	    "rax 0x%016lx rbx 0x%016lx rbp 0x%016lx\n"
+	    "r10 0x%016lx r11 0x%016lx r12 0x%016lx\n"
+	    "r13 0x%016lx r14 0x%016lx r15 0x%016lx\n",
+	    tf->tf_rdi, tf->tf_rsi, tf->tf_rdx, tf->tf_rcx, tf->tf_r8,
+	    tf->tf_r9, tf->tf_rax, tf->tf_rbx, tf->tf_rbp, tf->tf_r10,
+	    tf->tf_r11, tf->tf_r12, tf->tf_r13, tf->tf_r14, tf->tf_r15);
+	printf("Machine stopped.\n");
+}
+
+static void
+prepare_exception(unsigned idx, uint64_t my_handler,
+    int ist_use_table[static NUM_IST])
+{
+	struct gate_descriptor *fw_idt_e, *loader_idt_e;
+
+	fw_idt_e = &((struct gate_descriptor *)fw_idt.rd_base)[idx];
+	loader_idt_e = &((struct gate_descriptor *)loader_idt.rd_base)[idx];
+	fw_intr_handlers[idx] = fw_idt_e->gd_looffset +
+	    (fw_idt_e->gd_hioffset << 16);
+	intercepted[idx] = 1;
+	ist_use_table[fw_idt_e->gd_ist]++;
+	loader_idt_e->gd_looffset = my_handler;
+	loader_idt_e->gd_hioffset = my_handler >> 16;
+	loader_idt_e->gd_selector = fw_idt_e->gd_selector; /* XXX */
+	loader_idt_e->gd_ist = 0;
+	loader_idt_e->gd_type = SDT_SYSIGT;
+	loader_idt_e->gd_dpl = 0;
+	loader_idt_e->gd_p = 1;
+	loader_idt_e->gd_xx = 0;
+	loader_idt_e->sd_xx1 = 0;
+}
+#define	PREPARE_EXCEPTION(N)						\
+    extern char EXC##N##_handler[];					\
+    prepare_exception(N, (uintptr_t)EXC##N##_handler, ist_use_table);
+
+static void
+free_tables(void)
+{
+
+	if (lidt_pa != 0) {
+		BS->FreePages(lidt_pa, EFI_SIZE_TO_PAGES(fw_idt.rd_limit));
+		lidt_pa = 0;
+	}
+	if (exc_stack_pa != 0) {
+		BS->FreePages(exc_stack_pa, 1);
+		exc_stack_pa = 0;
+	}
+	if (tss_pa != 0 && tss_fw_seg == 0) {
+		BS->FreePages(tss_pa, EFI_SIZE_TO_PAGES(sizeof(struct
+		    amd64tss)));
+		tss_pa = 0;
+	}
+	if (loader_gdt_pa != 0) {
+		BS->FreePages(tss_pa, 2);
+		loader_gdt_pa = 0;
+	}
+	ist = 0;
+	loader_tss = 0;
+}
+
+static int
+efi_setup_tss(struct region_descriptor *gdt, uint32_t loader_tss_idx,
+    struct amd64tss **tss)
+{
+	EFI_STATUS status;
+	struct system_segment_descriptor *tss_desc;
+
+	tss_desc = (struct system_segment_descriptor *)(gdt->rd_base +
+	    (loader_tss_idx << 3));
+	status = BS->AllocatePages(AllocateAnyPages, EfiLoaderData,
+	    EFI_SIZE_TO_PAGES(sizeof(struct amd64tss)), &tss_pa);
+	if (EFI_ERROR(status)) {
+		printf("efi_setup_tss: AllocatePages tss error %lu\n",
+		    EFI_ERROR_CODE(status));
+		return (0);
+	}
+	*tss = (struct amd64tss *)tss_pa;
+	bzero(*tss, sizeof(**tss));
+	tss_desc->sd_lolimit = sizeof(struct amd64tss);
+	tss_desc->sd_lobase = tss_pa;
+	tss_desc->sd_type = SDT_SYSTSS;
+	tss_desc->sd_dpl = 0;
+	tss_desc->sd_p = 1;
+	tss_desc->sd_hilimit = sizeof(struct amd64tss) >> 16;
+	tss_desc->sd_gran = 0;
+	tss_desc->sd_hibase = tss_pa >> 24;
+	tss_desc->sd_xx0 = 0;
+	tss_desc->sd_xx1 = 0;
+	tss_desc->sd_mbz = 0;
+	tss_desc->sd_xx2 = 0;
+	return (1);
+}
+
+static int
+efi_redirect_exceptions(void)
+{
+	int ist_use_table[NUM_IST];
+	struct gate_descriptor *loader_idt_e;
+	struct system_segment_descriptor *tss_desc, *gdt_desc;
+	struct amd64tss *tss;
+	struct region_descriptor *gdt_rd, loader_gdt;
+	uint32_t i;
+	EFI_STATUS status;
+	register_t rfl;
+
+	sidt(&fw_idt);
+	status = BS->AllocatePages(AllocateAnyPages, EfiLoaderData,
+	    EFI_SIZE_TO_PAGES(fw_idt.rd_limit), &lidt_pa);
+	if (EFI_ERROR(status)) {
+		printf("efi_redirect_exceptions: AllocatePages IDT error %lu\n",
+		    EFI_ERROR_CODE(status));
+		lidt_pa = 0;
+		return (0);
+	}
+	status = BS->AllocatePages(AllocateAnyPages, EfiLoaderData, 1,
+	    &exc_stack_pa);
+	if (EFI_ERROR(status)) {
+		printf("efi_redirect_exceptions: AllocatePages stk error %lu\n",
+		    EFI_ERROR_CODE(status));
+		exc_stack_pa = 0;
+		free_tables();
+		return (0);
+	}
+	loader_idt.rd_limit = fw_idt.rd_limit;
+	bcopy((void *)fw_idt.rd_base, (void *)loader_idt.rd_base,
+	    loader_idt.rd_limit);
+	bzero(ist_use_table, sizeof(ist_use_table));
+	bzero(fw_intr_handlers, sizeof(fw_intr_handlers));
+	bzero(intercepted, sizeof(intercepted));
+
+	sgdt(&fw_gdt);
+	tss_fw_seg = read_tr();
+	gdt_rd = NULL;
+	if (tss_fw_seg == 0) {
+		for (i = 2; (i << 3) + sizeof(*gdt_desc) <= fw_gdt.rd_limit;
+		    i += 2) {
+			gdt_desc = (struct system_segment_descriptor *)(
+			    fw_gdt.rd_base + (i << 3));
+			if (gdt_desc->sd_type == 0 && gdt_desc->sd_mbz == 0) {
+				gdt_rd = &fw_gdt;
+				break;
+			}
+		}
+		if (gdt_rd == NULL) {
+			if (i >= 8190) {
+				printf("efi_redirect_exceptions: all slots "
+				    "in gdt are used\n");
+				free_tables();
+				return (0);
+			}
+			loader_gdt.rd_limit = roundup2(fw_gdt.rd_limit +
+			    sizeof(struct system_segment_descriptor),
+			    sizeof(struct system_segment_descriptor)) - 1;
+			i = (loader_gdt.rd_limit + 1 -
+			    sizeof(struct system_segment_descriptor)) /
+			    sizeof(struct system_segment_descriptor) * 2;
+			status = BS->AllocatePages(AllocateAnyPages,
+			    EfiLoaderData,
+			    EFI_SIZE_TO_PAGES(loader_gdt.rd_limit),
+			    &loader_gdt_pa);
+			if (EFI_ERROR(status)) {
+				printf("efi_setup_tss: AllocatePages gdt error "
+				    "%lu\n",  EFI_ERROR_CODE(status));
+				loader_gdt_pa = 0;
+				free_tables();
+				return (0);
+			}
+			loader_gdt.rd_base = loader_gdt_pa;
+			bzero((void *)loader_gdt.rd_base, loader_gdt.rd_limit);
+			bcopy((void *)fw_gdt.rd_base,
+			    (void *)loader_gdt.rd_base, fw_gdt.rd_limit);
+			gdt_rd = &loader_gdt;
+		}
+		loader_tss = i << 3;
+		if (!efi_setup_tss(gdt_rd, i, &tss)) {
+			tss_pa = 0;
+			free_tables();
+			return (0);
+		}
+	} else {
+		tss_desc = (struct system_segment_descriptor *)((char *)
+		    fw_gdt.rd_base + tss_fw_seg);
+		if (tss_desc->sd_type != SDT_SYSTSS &&
+		    tss_desc->sd_type != SDT_SYSBSY) {
+			printf("LTR points to non-TSS descriptor\n");
+			free_tables();
+			return (0);
+		}
+		tss_pa = tss_desc->sd_lobase + (tss_desc->sd_hibase << 16);
+		tss = (struct amd64tss *)tss_pa;
+		tss_desc->sd_type = SDT_SYSTSS; /* unbusy */
+	}
+
+	PREPARE_EXCEPTION(0);
+	PREPARE_EXCEPTION(1);
+	PREPARE_EXCEPTION(2);
+	PREPARE_EXCEPTION(3);
+	PREPARE_EXCEPTION(4);
+	PREPARE_EXCEPTION(5);
+	PREPARE_EXCEPTION(6);
+	PREPARE_EXCEPTION(7);
+	PREPARE_EXCEPTION(8);
+	PREPARE_EXCEPTION(9);
+	PREPARE_EXCEPTION(10);
+	PREPARE_EXCEPTION(11);
+	PREPARE_EXCEPTION(12);
+	PREPARE_EXCEPTION(13);
+	PREPARE_EXCEPTION(14);
+	PREPARE_EXCEPTION(16);
+	PREPARE_EXCEPTION(17);
+	PREPARE_EXCEPTION(18);
+	PREPARE_EXCEPTION(19);
+	PREPARE_EXCEPTION(20);
+
+	exc_rsp = exc_stack_pa + PAGE_SIZE -
+	    (6 /* hw exception frame */ + 3 /* scratch regs */) * 8;
+
+	/* Find free IST and use it */
+	for (ist = 1; ist < NUM_IST; ist++) {
+		if (ist_use_table[ist] == 0)
+			break;
+	}
+	if (ist == NUM_IST) {
+		printf("efi_redirect_exceptions: all ISTs used\n");
+		free_tables();
+		lidt_pa = 0;
+		return (0);
+	}
+	for (i = 0; i < NUM_EXC; i++) {
+		loader_idt_e = &((struct gate_descriptor *)loader_idt.
+		    rd_base)[i];
+		if (intercepted[i])
+			loader_idt_e->gd_ist = ist;
+	}
+	(&(tss->tss_ist1))[ist - 1] = exc_stack_pa + PAGE_SIZE;
+
+	/* Switch to new IDT */
+	rfl = intr_disable();
+	if (loader_gdt_pa != 0)
+		bare_lgdt(&loader_gdt);
+	if (loader_tss != 0)
+		ltr(loader_tss);
+	lidt(&loader_idt);
+	intr_restore(rfl);
+	return (1);
+}
+
+static void
+efi_unredirect_exceptions(void)
+{
+	register_t rfl;
+
+	if (lidt_pa == 0)
+		return;
+
+	rfl = intr_disable();
+	if (ist != 0)
+		(&(((struct amd64tss *)tss_pa)->tss_ist1))[ist - 1] = 0;
+	if (loader_gdt_pa != 0)
+		bare_lgdt(&fw_gdt);
+	if (loader_tss != 0)
+		ltr(tss_fw_seg);
+	lidt(&fw_idt);
+	intr_restore(rfl);
+	free_tables();
+}
+
+static int
+command_grab_faults(int argc, char *argv[])
+{
+	int res;
+
+	res = efi_redirect_exceptions();
+	if (!res)
+		printf("failed\n");
+	return (CMD_OK);
+}
+COMMAND_SET(grap_faults, "grab_faults", "grab faults", command_grab_faults);
+
+static int
+command_ungrab_faults(int argc, char *argv[])
+{
+
+	efi_unredirect_exceptions();
+	return (CMD_OK);
+}
+COMMAND_SET(ungrab_faults, "ungrab_faults", "ungrab faults",
+    command_ungrab_faults);
+
+static int
+command_fault(int argc, char *argv[])
+{
+
+	__asm("ud2");
+	return (CMD_OK);
+}
+COMMAND_SET(fault, "fault", "generate fault", command_fault);
diff --git a/sys/boot/efi/loader/arch/i386/ldscript.i386 b/sys/boot/efi/loader/arch/i386/ldscript.i386
index 0201269158a0..4b28c104a3fe 100644
--- a/sys/boot/efi/loader/arch/i386/ldscript.i386
+++ b/sys/boot/efi/loader/arch/i386/ldscript.i386
@@ -14,7 +14,7 @@ SECTIONS
     /* .gnu.warning sections are handled specially by elf32.em. */
     *(.gnu.warning)
     *(.plt)
-  } =0xCC
+  } =0xCCCCCCCC
   . = ALIGN(4096);
   .data		: {
     *(.rodata .rodata.* .gnu.linkonce.r.*)
diff --git a/sys/boot/fdt/dts/arm/annapurna-alpine.dts b/sys/boot/fdt/dts/arm/annapurna-alpine.dts
index f6768db7882e..2172ed3a45a1 100644
--- a/sys/boot/fdt/dts/arm/annapurna-alpine.dts
+++ b/sys/boot/fdt/dts/arm/annapurna-alpine.dts
@@ -175,6 +175,7 @@
 		device_type = "pci";
 		#size-cells = <2>;
 		#address-cells = <3>;
+		reg = <0xfbc00000 0x100000>;
 		interrupt-parent = <&MPIC>;
 		interrupt-map-mask = <0xf800 0 0 7>;
 		interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter
diff --git a/sys/boot/i386/libi386/pxe.c b/sys/boot/i386/libi386/pxe.c
index 28046f3ba1d1..f947ef6ddbe2 100644
--- a/sys/boot/i386/libi386/pxe.c
+++ b/sys/boot/i386/libi386/pxe.c
@@ -586,7 +586,7 @@ bangpxe_call(int func)
 
 
 time_t
-getsecs()
+getsecs(void)
 {
 	time_t n = 0;
 	time(&n);
diff --git a/sys/boot/ofw/libofw/ofw_time.c b/sys/boot/ofw/libofw/ofw_time.c
index f53997dc059f..d5ca271564de 100644
--- a/sys/boot/ofw/libofw/ofw_time.c
+++ b/sys/boot/ofw/libofw/ofw_time.c
@@ -41,8 +41,8 @@ time(time_t *tloc)
 	return secs;
 }
 
-int
-getsecs()
+time_t
+getsecs(void)
 {
 	time_t	n = 0;
 	time(&n);
diff --git a/sys/boot/powerpc/boot1.chrp/Makefile.hfs b/sys/boot/powerpc/boot1.chrp/Makefile.hfs
index 7f35cc32512d..c6c2d866f6bf 100644
--- a/sys/boot/powerpc/boot1.chrp/Makefile.hfs
+++ b/sys/boot/powerpc/boot1.chrp/Makefile.hfs
@@ -1,4 +1,4 @@
 # This file autogenerated by generate-hfs.sh - DO NOT EDIT
 # $FreeBSD$
-BOOTINFO_OFFSET=0x58
+BOOTINFO_OFFSET=0x9c
 BOOT1_OFFSET=0x1c
diff --git a/sys/boot/powerpc/boot1.chrp/generate-hfs.sh b/sys/boot/powerpc/boot1.chrp/generate-hfs.sh
index 2ed6f38f1682..ef368d1566b4 100755
--- a/sys/boot/powerpc/boot1.chrp/generate-hfs.sh
+++ b/sys/boot/powerpc/boot1.chrp/generate-hfs.sh
@@ -15,7 +15,7 @@
 HFS_SIZE=1600 			#Size in 512-byte blocks of the produced image
 
 CHRPBOOT_SIZE=2k
-BOOT1_SIZE=30k
+BOOT1_SIZE=64k
 
 # Generate 800K HFS image
 OUTPUT_FILE=hfs.tmpl
diff --git a/sys/boot/powerpc/boot1.chrp/hfs.tmpl.bz2.uu b/sys/boot/powerpc/boot1.chrp/hfs.tmpl.bz2.uu
index 4ef435e6d028..20b7695e6db4 100644
--- a/sys/boot/powerpc/boot1.chrp/hfs.tmpl.bz2.uu
+++ b/sys/boot/powerpc/boot1.chrp/hfs.tmpl.bz2.uu
@@ -2,17 +2,17 @@ HFS template boot filesystem created by generate-hfs.sh
 DO NOT EDIT
 $FreeBSD$
 begin 644 hfs.tmpl.bz2
-M0EIH.3%!62936?(HJX\``"]_]?___O)20>!4M2$>0#MUW$1$``$!$``"2!`(
-M4EG``>G*VV3"22334_2(/*>ID,@``:#U&"-#(!IZ0`)$HIY0>B-#(/4T```&
-M@R:`&@``<:,F1A&(!A-!@$T&@9,FC)D,(#!4E-*--31ZAB!DT!ID:#$81HT&
-M@9-!Z::C:E=SZCC1((92M^1Q@3&>="[<2FD((A[AT#`[('#?MSV(S,><P)B_
-M'31",-UG78$CN,$&,P3:!)"2/J]\T9KP63TV)"&Y8"1B*E$I(H935A3LKL9M
-M74FBH6E17;ETD`2U#;5%_9P+&>HOI'#2,"EJ0PU5)<J26E2$`KSGEA(F9(P%
-M4&+M\K54E21K+%@1UU%`;'(KZQS5)SNB[)4WUZY`"6K8U]=8Z-W*[M[UXWZ.
-M`DAMLBTF-IC8Z77:KA%),$[3LHK,^`EA`+E,(2&TIFEA-;:US^NQ)+<8%WIC
-M59:&JR9^`#&G)-N@DK.0#ZQ_>.T`PX,54O,RTW8-",N1`R>?SL"+?Q51[H]#
-MJ1C5"]BDBF1UJ!Y`J$WTC]QAFZ%Q21$J,I&0,0?9?DPU!Z>$9.380JJCO$Q8
-MXZTX)GQCCGNC%G1BIDBHTK#J9N0,M[85QC:.'>]#,GPRAALU*=)2`$ND22<.
--VK/^+N2*<*$AY%%7'@``
+M0EIH.3%!629365^MV6L``"]__O___M)20>!0O2$>0#MUW$!$``%%$``@``!`
+M!`!R2<`![@H2"2A2-Z)-HC]4`:`-``T:&@&@#0/TTH<`PC":8A@$`R`&$:9,
+MF$8"&AP#",)IB&`0#(`81IDR81@(:")0HT*>4,:0TT`:!ZC0/*/4/1&@;4>H
+M&@RYG-FL-,\=C91FTSS@99`O+OA;*$ZN3-&UF`W@#SP:;MVF_EN,-]P$ZN2B
+M=";7YHA7VT!#<@,B`H*?S#?Q;CUJ8H8+9:E)+4"L7'CL5&D.IO4;H98%^4@[
+M9`*L&1``5*0#A(E<M\J&(@6BZXC<0K!#!)!H05`5*L!^DNM12_"L`<9!Y.7T
+M<I94[[MT$^$30P-DYBVI.X7R<KY7&H$DA(<S;NW1PB7-47*Q>B8BH`S'1O^N
+M)Y6'!#N:*:<E!+,#/,\;M_FXRP![+P44D6],L'G1X7Q&[JI6WN@&KCIW8:".
+MTP=Y77`%67""`=I/UR500#!=DD+!>JYTEX\:%'"?.G$FCP8TM_0/ND`^IG3[
+M.QUEDP&P>3+Z442Q!:S.A1>00]'X'D%)UX9QZ>$Q?(808QB-4%9BBTL"L(BB
+MEJ*'HH820Q$'%G':JF.:>$U4H`0S`:GSZM-C5BNX(2&$B"J*45`"4FEZ__%W
+))%.%"07ZW9:P
 `
 end
diff --git a/sys/boot/powerpc/kboot/main.c b/sys/boot/powerpc/kboot/main.c
index ec5ba6b651a2..50f63b11699b 100644
--- a/sys/boot/powerpc/kboot/main.c
+++ b/sys/boot/powerpc/kboot/main.c
@@ -151,8 +151,8 @@ delay(int usecs)
 	} while (t < ti + usecs);
 }
 
-int
-getsecs()
+time_t
+getsecs(void)
 {
 	struct host_timeval tv;
 	host_gettimeofday(&tv, NULL);
diff --git a/sys/boot/powerpc/ps3/main.c b/sys/boot/powerpc/ps3/main.c
index bb1fd84c4b70..bcfd7c9ef9ae 100644
--- a/sys/boot/powerpc/ps3/main.c
+++ b/sys/boot/powerpc/ps3/main.c
@@ -179,10 +179,10 @@ delay(int usecs)
 		tb = mftb();
 }
 
-int
-getsecs()
+time_t
+getsecs(void)
 {
-	return ((mftb() - basetb)*ns_per_tick/1000000000);
+	return ((time_t)((mftb() - basetb)*ns_per_tick/1000000000));
 }
 
 time_t
diff --git a/sys/boot/uboot/lib/time.c b/sys/boot/uboot/lib/time.c
index 9083675b75d7..a3c73f471a25 100644
--- a/sys/boot/uboot/lib/time.c
+++ b/sys/boot/uboot/lib/time.c
@@ -47,7 +47,7 @@ time(time_t *tloc)
 	return (secs);
 }
 
-int
+time_t
 getsecs(void)
 {
 
diff --git a/sys/cam/cam_xpt.c b/sys/cam/cam_xpt.c
index 859ed9a4f634..cfca7807c781 100644
--- a/sys/cam/cam_xpt.c
+++ b/sys/cam/cam_xpt.c
@@ -2578,21 +2578,25 @@ xpt_action_default(union ccb *start_ccb)
 
 		abort_ccb = start_ccb->cab.abort_ccb;
 		if (XPT_FC_IS_DEV_QUEUED(abort_ccb)) {
+			struct cam_ed *device;
+			struct cam_devq *devq;
 
-			if (abort_ccb->ccb_h.pinfo.index >= 0) {
-				struct cam_ccbq *ccbq;
-				struct cam_ed *device;
+			device = abort_ccb->ccb_h.path->device;
+			devq = device->sim->devq;
 
-				device = abort_ccb->ccb_h.path->device;
-				ccbq = &device->ccbq;
-				cam_ccbq_remove_ccb(ccbq, abort_ccb);
+			mtx_lock(&devq->send_mtx);
+			if (abort_ccb->ccb_h.pinfo.index > 0) {
+				cam_ccbq_remove_ccb(&device->ccbq, abort_ccb);
 				abort_ccb->ccb_h.status =
 				    CAM_REQ_ABORTED|CAM_DEV_QFRZN;
-				xpt_freeze_devq(abort_ccb->ccb_h.path, 1);
+				xpt_freeze_devq_device(device, 1);
+				mtx_unlock(&devq->send_mtx);
 				xpt_done(abort_ccb);
 				start_ccb->ccb_h.status = CAM_REQ_CMP;
 				break;
 			}
+			mtx_unlock(&devq->send_mtx);
+
 			if (abort_ccb->ccb_h.pinfo.index == CAM_UNQUEUED_INDEX
 			 && (abort_ccb->ccb_h.status & CAM_SIM_QUEUED) == 0) {
 				/*
diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c
index 46935429ae15..31fe4e0ab24b 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c
@@ -3197,6 +3197,11 @@ zfs_setattr(vnode_t *vp, vattr_t *vap, int flags, cred_t *cr,
 
 		if (err == 0 && xattr_obj) {
 			err = zfs_zget(zp->z_zfsvfs, xattr_obj, &attrzp);
+			if (err == 0) {
+				err = vn_lock(ZTOV(attrzp), LK_EXCLUSIVE);
+				if (err != 0)
+					vrele(ZTOV(attrzp));
+			}
 			if (err)
 				goto out2;
 		}
@@ -3206,7 +3211,7 @@ zfs_setattr(vnode_t *vp, vattr_t *vap, int flags, cred_t *cr,
 			if (new_uid != zp->z_uid &&
 			    zfs_fuid_overquota(zfsvfs, B_FALSE, new_uid)) {
 				if (attrzp)
-					vrele(ZTOV(attrzp));
+					vput(ZTOV(attrzp));
 				err = SET_ERROR(EDQUOT);
 				goto out2;
 			}
@@ -3218,7 +3223,7 @@ zfs_setattr(vnode_t *vp, vattr_t *vap, int flags, cred_t *cr,
 			if (new_gid != zp->z_gid &&
 			    zfs_fuid_overquota(zfsvfs, B_TRUE, new_gid)) {
 				if (attrzp)
-					vrele(ZTOV(attrzp));
+					vput(ZTOV(attrzp));
 				err = SET_ERROR(EDQUOT);
 				goto out2;
 			}
@@ -3449,7 +3454,7 @@ out:
 	}
 
 	if (attrzp)
-		vrele(ZTOV(attrzp));
+		vput(ZTOV(attrzp));
 
 	if (aclp)
 		zfs_acl_free(aclp);
diff --git a/sys/cddl/dev/systrace/systrace.c b/sys/cddl/dev/systrace/systrace.c
index 88e680a755f7..014a0078197b 100644
--- a/sys/cddl/dev/systrace/systrace.c
+++ b/sys/cddl/dev/systrace/systrace.c
@@ -193,7 +193,8 @@ systrace_probe(struct syscall_args *sa, enum systrace_probe_t type, int retval)
 	memset(uargs, 0, sizeof(uargs));
 
 	if (type == SYSTRACE_ENTRY) {
-		id = sa->callp->sy_entry;
+		if ((id = sa->callp->sy_entry) == DTRACE_IDNONE)
+			return;
 
 		if (sa->callp->sy_systrace_args_func != NULL)
 			/*
@@ -215,7 +216,8 @@ systrace_probe(struct syscall_args *sa, enum systrace_probe_t type, int retval)
 		 */
 		curthread->t_dtrace_systrace_args = uargs;
 	} else {
-		id = sa->callp->sy_return;
+		if ((id = sa->callp->sy_return) == DTRACE_IDNONE)
+			return;
 
 		curthread->t_dtrace_systrace_args = NULL;
 		/* Set arg0 and arg1 as the return value of this syscall. */
diff --git a/sys/compat/cloudabi/cloudabi_fd.c b/sys/compat/cloudabi/cloudabi_fd.c
index 5500e3920e17..2f2725ec716d 100644
--- a/sys/compat/cloudabi/cloudabi_fd.c
+++ b/sys/compat/cloudabi/cloudabi_fd.c
@@ -456,32 +456,19 @@ cloudabi_sys_fd_stat_get(struct thread *td,
     struct cloudabi_sys_fd_stat_get_args *uap)
 {
 	cloudabi_fdstat_t fsb = {};
-	struct filedesc *fdp;
 	struct file *fp;
-	seq_t seq;
 	cap_rights_t rights;
+	struct filecaps fcaps;
 	int error, oflags;
-	bool modified;
 
 	/* Obtain file descriptor properties. */
-	fdp = td->td_proc->p_fd;
-	do {
-		error = fget_unlocked(fdp, uap->fd, cap_rights_init(&rights),
-		    &fp, &seq);
-		if (error != 0)
-			return (error);
-		if (fp->f_ops == &badfileops) {
-			fdrop(fp, td);
-			return (EBADF);
-		}
-
-		rights = *cap_rights(fdp, uap->fd);
-		oflags = OFLAGS(fp->f_flag);
-		fsb.fs_filetype = cloudabi_convert_filetype(fp);
-
-		modified = fd_modified(fdp, uap->fd, seq);
-		fdrop(fp, td);
-	} while (modified);
+	error = fget_cap(td, uap->fd, cap_rights_init(&rights), &fp,
+	    &fcaps);
+	if (error != 0)
+		return (error);
+	oflags = OFLAGS(fp->f_flag);
+	fsb.fs_filetype = cloudabi_convert_filetype(fp);
+	fdrop(fp, td);
 
 	/* Convert file descriptor flags. */
 	if (oflags & O_APPEND)
@@ -492,8 +479,9 @@ cloudabi_sys_fd_stat_get(struct thread *td,
 		fsb.fs_flags |= CLOUDABI_FDFLAG_SYNC;
 
 	/* Convert capabilities to CloudABI rights. */
-	convert_capabilities(&rights, fsb.fs_filetype,
+	convert_capabilities(&fcaps.fc_rights, fsb.fs_filetype,
 	    &fsb.fs_rights_base, &fsb.fs_rights_inheriting);
+	filecaps_free(&fcaps);
 	return (copyout(&fsb, (void *)uap->buf, sizeof(fsb)));
 }
 
diff --git a/sys/compat/cloudabi/cloudabi_sock.c b/sys/compat/cloudabi/cloudabi_sock.c
index b66f0ab13504..c66e2096f5b0 100644
--- a/sys/compat/cloudabi/cloudabi_sock.c
+++ b/sys/compat/cloudabi/cloudabi_sock.c
@@ -210,7 +210,7 @@ cloudabi_sys_sock_stat_get(struct thread *td,
 	int error;
 
 	error = getsock_cap(td, uap->sock, cap_rights_init(&rights,
-	    CAP_GETSOCKOPT, CAP_GETPEERNAME, CAP_GETSOCKNAME), &fp, NULL);
+	    CAP_GETSOCKOPT, CAP_GETPEERNAME, CAP_GETSOCKNAME), &fp, NULL, NULL);
 	if (error != 0)
 		return (error);
 	so = fp->f_data;
diff --git a/sys/compat/cloudabi32/cloudabi32_systrace_args.c b/sys/compat/cloudabi32/cloudabi32_systrace_args.c
index 0ba5ec558afe..1b49a5d5eabd 100644
--- a/sys/compat/cloudabi32/cloudabi32_systrace_args.c
+++ b/sys/compat/cloudabi32/cloudabi32_systrace_args.c
@@ -551,7 +551,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 2:
 		switch(ndx) {
 		case 0:
-			p = "cloudabi_condvar_t *";
+			p = "userland cloudabi_condvar_t *";
 			break;
 		case 1:
 			p = "cloudabi_scope_t";
@@ -620,7 +620,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi32_iovec_t *";
+			p = "userland const cloudabi32_iovec_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -639,7 +639,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi32_ciovec_t *";
+			p = "userland const cloudabi32_ciovec_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -658,7 +658,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi32_iovec_t *";
+			p = "userland const cloudabi32_iovec_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -703,7 +703,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "cloudabi_fdstat_t *";
+			p = "userland cloudabi_fdstat_t *";
 			break;
 		default:
 			break;
@@ -716,7 +716,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi_fdstat_t *";
+			p = "userland const cloudabi_fdstat_t *";
 			break;
 		case 2:
 			p = "cloudabi_fdsflags_t";
@@ -742,7 +742,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi32_ciovec_t *";
+			p = "userland const cloudabi32_ciovec_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -793,7 +793,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -812,7 +812,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_lookup_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -821,7 +821,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 4:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 5:
 			p = "size_t";
@@ -837,7 +837,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_lookup_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -846,7 +846,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_oflags_t";
 			break;
 		case 4:
-			p = "const cloudabi_fdstat_t *";
+			p = "userland const cloudabi_fdstat_t *";
 			break;
 		default:
 			break;
@@ -859,7 +859,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -878,13 +878,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 4:
 			p = "size_t";
@@ -900,7 +900,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -909,7 +909,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 4:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 5:
 			p = "size_t";
@@ -925,7 +925,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "cloudabi_filestat_t *";
+			p = "userland cloudabi_filestat_t *";
 			break;
 		default:
 			break;
@@ -938,7 +938,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi_filestat_t *";
+			p = "userland const cloudabi_filestat_t *";
 			break;
 		case 2:
 			p = "cloudabi_fsflags_t";
@@ -954,13 +954,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_lookup_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "cloudabi_filestat_t *";
+			p = "userland cloudabi_filestat_t *";
 			break;
 		default:
 			break;
@@ -973,13 +973,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_lookup_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "const cloudabi_filestat_t *";
+			p = "userland const cloudabi_filestat_t *";
 			break;
 		case 4:
 			p = "cloudabi_fsflags_t";
@@ -992,7 +992,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 29:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1001,7 +1001,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 3:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 4:
 			p = "size_t";
@@ -1017,7 +1017,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -1033,7 +1033,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 31:
 		switch(ndx) {
 		case 0:
-			p = "cloudabi_lock_t *";
+			p = "userland cloudabi_lock_t *";
 			break;
 		case 1:
 			p = "cloudabi_scope_t";
@@ -1046,7 +1046,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 32:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1062,7 +1062,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 33:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1075,7 +1075,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 34:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1100,7 +1100,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 35:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1116,7 +1116,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 36:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1132,7 +1132,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 37:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1145,7 +1145,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 38:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1158,10 +1158,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 39:
 		switch(ndx) {
 		case 0:
-			p = "const cloudabi32_subscription_t *";
+			p = "userland const cloudabi32_subscription_t *";
 			break;
 		case 1:
-			p = "cloudabi32_event_t *";
+			p = "userland cloudabi32_event_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -1177,19 +1177,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi32_subscription_t *";
+			p = "userland const cloudabi32_subscription_t *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "cloudabi32_event_t *";
+			p = "userland cloudabi32_event_t *";
 			break;
 		case 4:
 			p = "size_t";
 			break;
 		case 5:
-			p = "const cloudabi32_subscription_t *";
+			p = "userland const cloudabi32_subscription_t *";
 			break;
 		default:
 			break;
@@ -1202,13 +1202,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "const cloudabi_fd_t *";
+			p = "userland const cloudabi_fd_t *";
 			break;
 		case 4:
 			p = "size_t";
@@ -1244,7 +1244,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 45:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1260,7 +1260,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "cloudabi_sockstat_t *";
+			p = "userland cloudabi_sockstat_t *";
 			break;
 		default:
 			break;
@@ -1276,7 +1276,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
 			p = "size_t";
@@ -1295,7 +1295,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
 			p = "size_t";
@@ -1324,10 +1324,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi32_recv_in_t *";
+			p = "userland const cloudabi32_recv_in_t *";
 			break;
 		case 2:
-			p = "cloudabi32_recv_out_t *";
+			p = "userland cloudabi32_recv_out_t *";
 			break;
 		default:
 			break;
@@ -1340,10 +1340,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi32_send_in_t *";
+			p = "userland const cloudabi32_send_in_t *";
 			break;
 		case 2:
-			p = "cloudabi32_send_out_t *";
+			p = "userland cloudabi32_send_out_t *";
 			break;
 		default:
 			break;
@@ -1369,7 +1369,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "cloudabi_sockstat_t *";
+			p = "userland cloudabi_sockstat_t *";
 			break;
 		case 2:
 			p = "cloudabi_ssflags_t";
@@ -1382,7 +1382,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 54:
 		switch(ndx) {
 		case 0:
-			p = "cloudabi32_threadattr_t *";
+			p = "userland cloudabi32_threadattr_t *";
 			break;
 		default:
 			break;
@@ -1392,7 +1392,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 55:
 		switch(ndx) {
 		case 0:
-			p = "cloudabi_lock_t *";
+			p = "userland cloudabi_lock_t *";
 			break;
 		case 1:
 			p = "cloudabi_scope_t";
diff --git a/sys/compat/cloudabi64/cloudabi64_systrace_args.c b/sys/compat/cloudabi64/cloudabi64_systrace_args.c
index 3e97b25a04ba..032eefd05f47 100644
--- a/sys/compat/cloudabi64/cloudabi64_systrace_args.c
+++ b/sys/compat/cloudabi64/cloudabi64_systrace_args.c
@@ -551,7 +551,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 2:
 		switch(ndx) {
 		case 0:
-			p = "cloudabi_condvar_t *";
+			p = "userland cloudabi_condvar_t *";
 			break;
 		case 1:
 			p = "cloudabi_scope_t";
@@ -620,7 +620,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi64_iovec_t *";
+			p = "userland const cloudabi64_iovec_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -639,7 +639,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi64_ciovec_t *";
+			p = "userland const cloudabi64_ciovec_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -658,7 +658,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi64_iovec_t *";
+			p = "userland const cloudabi64_iovec_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -703,7 +703,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "cloudabi_fdstat_t *";
+			p = "userland cloudabi_fdstat_t *";
 			break;
 		default:
 			break;
@@ -716,7 +716,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi_fdstat_t *";
+			p = "userland const cloudabi_fdstat_t *";
 			break;
 		case 2:
 			p = "cloudabi_fdsflags_t";
@@ -742,7 +742,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi64_ciovec_t *";
+			p = "userland const cloudabi64_ciovec_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -793,7 +793,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -812,7 +812,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_lookup_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -821,7 +821,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 4:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 5:
 			p = "size_t";
@@ -837,7 +837,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_lookup_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -846,7 +846,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_oflags_t";
 			break;
 		case 4:
-			p = "const cloudabi_fdstat_t *";
+			p = "userland const cloudabi_fdstat_t *";
 			break;
 		default:
 			break;
@@ -859,7 +859,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -878,13 +878,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 4:
 			p = "size_t";
@@ -900,7 +900,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -909,7 +909,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 4:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 5:
 			p = "size_t";
@@ -925,7 +925,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "cloudabi_filestat_t *";
+			p = "userland cloudabi_filestat_t *";
 			break;
 		default:
 			break;
@@ -938,7 +938,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi_filestat_t *";
+			p = "userland const cloudabi_filestat_t *";
 			break;
 		case 2:
 			p = "cloudabi_fsflags_t";
@@ -954,13 +954,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_lookup_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "cloudabi_filestat_t *";
+			p = "userland cloudabi_filestat_t *";
 			break;
 		default:
 			break;
@@ -973,13 +973,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_lookup_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "const cloudabi_filestat_t *";
+			p = "userland const cloudabi_filestat_t *";
 			break;
 		case 4:
 			p = "cloudabi_fsflags_t";
@@ -992,7 +992,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 29:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1001,7 +1001,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 3:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 4:
 			p = "size_t";
@@ -1017,7 +1017,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -1033,7 +1033,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 31:
 		switch(ndx) {
 		case 0:
-			p = "cloudabi_lock_t *";
+			p = "userland cloudabi_lock_t *";
 			break;
 		case 1:
 			p = "cloudabi_scope_t";
@@ -1046,7 +1046,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 32:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1062,7 +1062,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 33:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1075,7 +1075,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 34:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1100,7 +1100,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 35:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1116,7 +1116,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 36:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1132,7 +1132,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 37:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1145,7 +1145,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 38:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1158,10 +1158,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 39:
 		switch(ndx) {
 		case 0:
-			p = "const cloudabi64_subscription_t *";
+			p = "userland const cloudabi64_subscription_t *";
 			break;
 		case 1:
-			p = "cloudabi64_event_t *";
+			p = "userland cloudabi64_event_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -1177,19 +1177,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi64_subscription_t *";
+			p = "userland const cloudabi64_subscription_t *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "cloudabi64_event_t *";
+			p = "userland cloudabi64_event_t *";
 			break;
 		case 4:
 			p = "size_t";
 			break;
 		case 5:
-			p = "const cloudabi64_subscription_t *";
+			p = "userland const cloudabi64_subscription_t *";
 			break;
 		default:
 			break;
@@ -1202,13 +1202,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "const cloudabi_fd_t *";
+			p = "userland const cloudabi_fd_t *";
 			break;
 		case 4:
 			p = "size_t";
@@ -1244,7 +1244,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 45:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -1260,7 +1260,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "cloudabi_sockstat_t *";
+			p = "userland cloudabi_sockstat_t *";
 			break;
 		default:
 			break;
@@ -1276,7 +1276,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
 			p = "size_t";
@@ -1295,7 +1295,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
 			p = "size_t";
@@ -1324,10 +1324,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi64_recv_in_t *";
+			p = "userland const cloudabi64_recv_in_t *";
 			break;
 		case 2:
-			p = "cloudabi64_recv_out_t *";
+			p = "userland cloudabi64_recv_out_t *";
 			break;
 		default:
 			break;
@@ -1340,10 +1340,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "const cloudabi64_send_in_t *";
+			p = "userland const cloudabi64_send_in_t *";
 			break;
 		case 2:
-			p = "cloudabi64_send_out_t *";
+			p = "userland cloudabi64_send_out_t *";
 			break;
 		default:
 			break;
@@ -1369,7 +1369,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "cloudabi_fd_t";
 			break;
 		case 1:
-			p = "cloudabi_sockstat_t *";
+			p = "userland cloudabi_sockstat_t *";
 			break;
 		case 2:
 			p = "cloudabi_ssflags_t";
@@ -1382,7 +1382,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 54:
 		switch(ndx) {
 		case 0:
-			p = "cloudabi64_threadattr_t *";
+			p = "userland cloudabi64_threadattr_t *";
 			break;
 		default:
 			break;
@@ -1392,7 +1392,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 55:
 		switch(ndx) {
 		case 0:
-			p = "cloudabi_lock_t *";
+			p = "userland cloudabi_lock_t *";
 			break;
 		case 1:
 			p = "cloudabi_scope_t";
diff --git a/sys/compat/freebsd32/Makefile b/sys/compat/freebsd32/Makefile
index 777b7355b50e..e91e04218254 100644
--- a/sys/compat/freebsd32/Makefile
+++ b/sys/compat/freebsd32/Makefile
@@ -8,7 +8,7 @@ all:
 sysent:  freebsd32_sysent.c freebsd32_syscall.h freebsd32_proto.h freebsd32_systrace_args.c
 
 freebsd32_sysent.c freebsd32_syscalls.c freebsd32_syscall.h freebsd32_proto.h freebsd32_systrace_args.c : \
-	    ../../kern/makesyscalls.sh syscalls.master syscalls.conf
+	    ../../kern/makesyscalls.sh syscalls.master syscalls.conf capabilities.conf
 	sh ../../kern/makesyscalls.sh syscalls.master syscalls.conf
 
 clean:
diff --git a/sys/compat/freebsd32/capabilities.conf b/sys/compat/freebsd32/capabilities.conf
new file mode 100644
index 000000000000..e14ff2db6371
--- /dev/null
+++ b/sys/compat/freebsd32/capabilities.conf
@@ -0,0 +1,284 @@
+##
+## Copyright (c) 2008-2010 Robert N. M. Watson
+## Copyright (c) 2016 The FreeBSD Foundation
+## All rights reserved.
+##
+## This software was developed at the University of Cambridge Computer
+## Laboratory with support from a grant from Google, Inc.
+##
+## Portions of this software were developed by Konstantin Belousov
+## under sponsorship from the FreeBSD Foundation.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+##    notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+##    notice, this list of conditions and the following disclaimer in the
+##    documentation and/or other materials provided with the distribution.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+## List of system calls enabled in freebsd32 capability mode, one name
+## per line.  See the original list in the sys/kern/capabilities.conf.
+## Position of the compat syscall in this file must be identical to
+## the master, to facilitate comparision and diagnostic.
+##
+## $FreeBSD$
+##
+
+__acl_aclcheck_fd
+__acl_delete_fd
+__acl_get_fd
+__acl_set_fd
+__mac_get_fd
+#__mac_get_pid
+__mac_get_proc
+__mac_set_fd
+__mac_set_proc
+freebsd32_sysctl
+freebsd32_umtx_op
+abort2
+accept
+accept4
+aio_cancel
+freebsd32_aio_error
+aio_fsync
+freebsd32_aio_read
+freebsd32_aio_return
+freebsd32_aio_suspend
+freebsd32_aio_waitcomplete
+freebsd32_aio_write
+#audit
+bindat
+cap_enter
+cap_fcntls_get
+cap_fcntls_limit
+cap_getmode
+freebsd32_cap_ioctls_get
+freebsd32_cap_ioctls_limit
+__cap_rights_get
+cap_rights_limit
+freebsd32_clock_getres
+freebsd32_clock_gettime
+close
+closefrom
+connectat
+#cpuset
+#freebsd32_cpuset_getaffinity
+#freebsd32_cpuset_getid
+#freebsd32_cpuset_setaffinity
+#freebsd32_cpuset_setid
+dup
+dup2
+extattr_delete_fd
+extattr_get_fd
+extattr_list_fd
+extattr_set_fd
+fchflags
+fchmod
+fchown
+freebsd32_fcntl
+freebsd32_fexecve
+flock
+fork
+fpathconf
+freebsd6_freebsd32_ftruncate
+freebsd6_freebsd32_lseek
+freebsd6_freebsd32_mmap
+freebsd6_freebsd32_pread
+freebsd6_freebsd32_pwrite
+freebsd32_fstat
+fstatfs
+fsync
+ftruncate
+freebsd32_futimens
+freebsd32_futimes
+getaudit
+getaudit_addr
+getauid
+freebsd32_getcontext
+getdents
+freebsd32_getdirentries
+getdomainname
+getdtablesize
+getegid
+geteuid
+gethostid
+gethostname
+freebsd32_getitimer
+getgid
+getgroups
+getlogin
+freebsd32_getpagesize
+getpeername
+getpgid
+getpgrp
+getpid
+getppid
+getpriority
+getresgid
+getresuid
+getrlimit
+freebsd32_getrusage
+getsid
+getsockname
+getsockopt
+freebsd32_gettimeofday
+getuid
+freebsd32_ioctl
+issetugid
+freebsd32_kevent
+kill
+freebsd32_kmq_notify
+freebsd32_kmq_setattr
+freebsd32_kmq_timedreceive
+freebsd32_kmq_timedsend
+kqueue
+freebsd32_ktimer_create
+ktimer_delete
+ktimer_getoverrun
+freebsd32_ktimer_gettime
+freebsd32_ktimer_settime
+#ktrace
+freebsd32_lio_listio
+listen
+freebsd32_lseek
+madvise
+mincore
+minherit
+mlock
+mlockall
+freebsd32_mmap
+freebsd32_mprotect
+msync
+munlock
+munlockall
+munmap
+freebsd32_nanosleep
+ntp_gettime
+freebsd6_freebsd32_aio_read
+freebsd6_freebsd32_aio_write
+obreak
+freebsd6_freebsd32_lio_listio
+chflagsat
+faccessat
+fchmodat
+fchownat
+freebsd32_fstatat
+freebsd32_futimesat
+linkat
+mkdirat
+mkfifoat
+mknodat
+openat
+readlinkat
+renameat
+symlinkat
+unlinkat
+freebsd32_utimensat
+open
+pdfork
+pdgetpid
+pdkill
+#pdwait4	# not yet implemented
+freebsd32_pipe
+pipe2
+poll
+freebsd32_pread
+freebsd32_preadv
+profil
+#ptrace
+freebsd32_pwrite
+freebsd32_pwritev
+read
+freebsd32_readv
+freebsd6_freebsd32_recv
+freebsd32_recvfrom
+freebsd32_recvmsg
+rtprio
+rtprio_thread
+sbrk
+sched_get_priority_max
+sched_get_priority_min
+sched_getparam
+sched_getscheduler
+sched_rr_get_interval
+sched_setparam
+sched_setscheduler
+sched_yield
+sctp_generic_recvmsg
+sctp_generic_sendmsg
+sctp_generic_sendmsg_iov
+sctp_peeloff
+freebsd32_pselect
+freebsd32_select
+freebsd6_freebsd32_send
+freebsd32_sendfile
+freebsd32_sendmsg
+sendto
+setaudit
+setaudit_addr
+setauid
+freebsd32_setcontext
+setegid
+seteuid
+setgid
+freebsd32_setitimer
+setpriority
+setregid
+setresgid
+setresuid
+setreuid
+setrlimit
+setsid
+setsockopt
+setuid
+shm_open
+shutdown
+freebsd32_sigaction
+freebsd32_sigaltstack
+freebsd32_sigblock
+freebsd32_sigpending
+sigprocmask
+sigqueue
+freebsd32_sigreturn
+freebsd32_sigsetmask
+ofreebsd32_sigstack
+sigsuspend
+freebsd32_sigtimedwait
+freebsd32_sigvec
+freebsd32_sigwaitinfo
+sigwait
+socket
+socketpair
+sstk
+sync
+sys_exit
+freebsd32_sysarch
+thr_create
+thr_exit
+thr_kill
+#thr_kill2
+freebsd32_thr_new
+thr_self
+thr_set_name
+freebsd32_thr_suspend
+thr_wake
+umask
+utrace
+uuidgen
+write
+freebsd32_writev
+yield
diff --git a/sys/compat/freebsd32/freebsd32_capability.c b/sys/compat/freebsd32/freebsd32_capability.c
index 2aee10bda733..cc4cad2c2077 100644
--- a/sys/compat/freebsd32/freebsd32_capability.c
+++ b/sys/compat/freebsd32/freebsd32_capability.c
@@ -49,18 +49,6 @@ __FBSDID("$FreeBSD$");
 MALLOC_DECLARE(M_FILECAPS);
 
 int
-freebsd32_cap_enter(struct thread *td,
-    struct freebsd32_cap_enter_args *uap)
-{
-
-	/*
-	 * We do not have an equivalent of capabilities.conf for freebsd32
-	 * compatibility, so do not allow capability mode for now.
-	 */
-	return (ENOSYS);
-}
-
-int
 freebsd32_cap_ioctls_limit(struct thread *td,
     struct freebsd32_cap_ioctls_limit_args *uap)
 {
@@ -148,14 +136,6 @@ out:
 #else /* !CAPABILITIES */
 
 int
-freebsd32_cap_enter(struct thread *td,
-    struct freebsd32_cap_enter_args *uap)
-{
-
-	return (ENOSYS);
-}
-
-int
 freebsd32_cap_ioctls_limit(struct thread *td,
     struct freebsd32_cap_ioctls_limit_args *uap)
 {
diff --git a/sys/compat/freebsd32/freebsd32_misc.c b/sys/compat/freebsd32/freebsd32_misc.c
index 893ad9859da2..838d1aa08bd0 100644
--- a/sys/compat/freebsd32/freebsd32_misc.c
+++ b/sys/compat/freebsd32/freebsd32_misc.c
@@ -3048,6 +3048,7 @@ freebsd32_procctl(struct thread *td, struct freebsd32_procctl_args *uap)
 	switch (uap->com) {
 	case PROC_SPROTECT:
 	case PROC_TRACE_CTL:
+	case PROC_TRAPCAP_CTL:
 		error = copyin(PTRIN(uap->data), &flags, sizeof(flags));
 		if (error != 0)
 			return (error);
@@ -3077,6 +3078,7 @@ freebsd32_procctl(struct thread *td, struct freebsd32_procctl_args *uap)
 		data = &x.rk;
 		break;
 	case PROC_TRACE_STATUS:
+	case PROC_TRAPCAP_STATUS:
 		data = &flags;
 		break;
 	default:
@@ -3095,6 +3097,7 @@ freebsd32_procctl(struct thread *td, struct freebsd32_procctl_args *uap)
 			error = error1;
 		break;
 	case PROC_TRACE_STATUS:
+	case PROC_TRAPCAP_STATUS:
 		if (error == 0)
 			error = copyout(&flags, uap->data, sizeof(flags));
 		break;
diff --git a/sys/compat/freebsd32/freebsd32_proto.h b/sys/compat/freebsd32/freebsd32_proto.h
index 7f4948cec6e9..f87cee0c70d6 100644
--- a/sys/compat/freebsd32/freebsd32_proto.h
+++ b/sys/compat/freebsd32/freebsd32_proto.h
@@ -3,7 +3,7 @@
  *
  * DO NOT EDIT-- this file is automatically generated.
  * $FreeBSD$
- * created from FreeBSD: head/sys/compat/freebsd32/syscalls.master 304395 2016-08-18 10:50:40Z gnn 
+ * created from FreeBSD: head/sys/compat/freebsd32/syscalls.master 305954 2016-09-18 22:03:07Z kib 
  */
 
 #ifndef _FREEBSD32_SYSPROTO_H_
@@ -578,9 +578,6 @@ struct freebsd32_shmctl_args {
 	char cmd_l_[PADL_(int)]; int cmd; char cmd_r_[PADR_(int)];
 	char buf_l_[PADL_(struct shmid_ds32 *)]; struct shmid_ds32 * buf; char buf_r_[PADR_(struct shmid_ds32 *)];
 };
-struct freebsd32_cap_enter_args {
-	register_t dummy;
-};
 struct freebsd32_pselect_args {
 	char nd_l_[PADL_(int)]; int nd; char nd_r_[PADR_(int)];
 	char in_l_[PADL_(fd_set *)]; fd_set * in; char in_r_[PADR_(fd_set *)];
@@ -798,7 +795,6 @@ int	freebsd32_jail_set(struct thread *, struct freebsd32_jail_set_args *);
 int	freebsd32_semctl(struct thread *, struct freebsd32_semctl_args *);
 int	freebsd32_msgctl(struct thread *, struct freebsd32_msgctl_args *);
 int	freebsd32_shmctl(struct thread *, struct freebsd32_shmctl_args *);
-int	freebsd32_cap_enter(struct thread *, struct freebsd32_cap_enter_args *);
 int	freebsd32_pselect(struct thread *, struct freebsd32_pselect_args *);
 #ifdef PAD64_REQUIRED
 int	freebsd32_posix_fallocate(struct thread *, struct freebsd32_posix_fallocate_args *);
@@ -1258,7 +1254,6 @@ int	freebsd10_freebsd32_pipe(struct thread *, struct freebsd10_freebsd32_pipe_ar
 #define	FREEBSD32_SYS_AUE_freebsd32_semctl	AUE_SEMCTL
 #define	FREEBSD32_SYS_AUE_freebsd32_msgctl	AUE_MSGCTL
 #define	FREEBSD32_SYS_AUE_freebsd32_shmctl	AUE_SHMCTL
-#define	FREEBSD32_SYS_AUE_freebsd32_cap_enter	AUE_CAP_ENTER
 #define	FREEBSD32_SYS_AUE_freebsd32_pselect	AUE_SELECT
 #define	FREEBSD32_SYS_AUE_freebsd32_posix_fallocate	AUE_NULL
 #define	FREEBSD32_SYS_AUE_freebsd32_posix_fadvise	AUE_NULL
diff --git a/sys/compat/freebsd32/freebsd32_syscall.h b/sys/compat/freebsd32/freebsd32_syscall.h
index fb56fd50a5db..159a2a710ec1 100644
--- a/sys/compat/freebsd32/freebsd32_syscall.h
+++ b/sys/compat/freebsd32/freebsd32_syscall.h
@@ -3,7 +3,7 @@
  *
  * DO NOT EDIT-- this file is automatically generated.
  * $FreeBSD$
- * created from FreeBSD: head/sys/compat/freebsd32/syscalls.master 304395 2016-08-18 10:50:40Z gnn 
+ * created from FreeBSD: head/sys/compat/freebsd32/syscalls.master 305954 2016-09-18 22:03:07Z kib 
  */
 
 #define	FREEBSD32_SYS_syscall	0
@@ -420,7 +420,7 @@
 #define	FREEBSD32_SYS_lpathconf	513
 				/* 514 is obsolete cap_new */
 #define	FREEBSD32_SYS___cap_rights_get	515
-#define	FREEBSD32_SYS_freebsd32_cap_enter	516
+#define	FREEBSD32_SYS_cap_enter	516
 #define	FREEBSD32_SYS_cap_getmode	517
 #define	FREEBSD32_SYS_pdfork	518
 #define	FREEBSD32_SYS_pdkill	519
diff --git a/sys/compat/freebsd32/freebsd32_syscalls.c b/sys/compat/freebsd32/freebsd32_syscalls.c
index 878ab9a0aa3c..dc2b557bd9c4 100644
--- a/sys/compat/freebsd32/freebsd32_syscalls.c
+++ b/sys/compat/freebsd32/freebsd32_syscalls.c
@@ -3,7 +3,7 @@
  *
  * DO NOT EDIT-- this file is automatically generated.
  * $FreeBSD$
- * created from FreeBSD: head/sys/compat/freebsd32/syscalls.master 304395 2016-08-18 10:50:40Z gnn 
+ * created from FreeBSD: head/sys/compat/freebsd32/syscalls.master 305954 2016-09-18 22:03:07Z kib 
  */
 
 const char *freebsd32_syscallnames[] = {
@@ -539,7 +539,7 @@ const char *freebsd32_syscallnames[] = {
 	"lpathconf",			/* 513 = lpathconf */
 	"obs_cap_new",			/* 514 = obsolete cap_new */
 	"__cap_rights_get",			/* 515 = __cap_rights_get */
-	"freebsd32_cap_enter",			/* 516 = freebsd32_cap_enter */
+	"cap_enter",			/* 516 = cap_enter */
 	"cap_getmode",			/* 517 = cap_getmode */
 	"pdfork",			/* 518 = pdfork */
 	"pdkill",			/* 519 = pdkill */
diff --git a/sys/compat/freebsd32/freebsd32_sysent.c b/sys/compat/freebsd32/freebsd32_sysent.c
index d9b42edc29a9..d52a6646c77e 100644
--- a/sys/compat/freebsd32/freebsd32_sysent.c
+++ b/sys/compat/freebsd32/freebsd32_sysent.c
@@ -3,7 +3,7 @@
  *
  * DO NOT EDIT-- this file is automatically generated.
  * $FreeBSD$
- * created from FreeBSD: head/sys/compat/freebsd32/syscalls.master 304395 2016-08-18 10:50:40Z gnn 
+ * created from FreeBSD: head/sys/compat/freebsd32/syscalls.master 305954 2016-09-18 22:03:07Z kib 
  */
 
 #include "opt_compat.h"
@@ -54,12 +54,12 @@ struct sysent freebsd32_sysent[] = {
 #define PAD64_REQUIRED
 #endif
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },		/* 0 = syscall */
-	{ AS(sys_exit_args), (sy_call_t *)sys_sys_exit, AUE_EXIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 1 = exit */
-	{ 0, (sy_call_t *)sys_fork, AUE_FORK, NULL, 0, 0, 0, SY_THR_STATIC },		/* 2 = fork */
-	{ AS(read_args), (sy_call_t *)sys_read, AUE_READ, NULL, 0, 0, 0, SY_THR_STATIC },	/* 3 = read */
-	{ AS(write_args), (sy_call_t *)sys_write, AUE_WRITE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 4 = write */
-	{ AS(open_args), (sy_call_t *)sys_open, AUE_OPEN_RWTC, NULL, 0, 0, 0, SY_THR_STATIC },	/* 5 = open */
-	{ AS(close_args), (sy_call_t *)sys_close, AUE_CLOSE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 6 = close */
+	{ AS(sys_exit_args), (sy_call_t *)sys_sys_exit, AUE_EXIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 1 = exit */
+	{ 0, (sy_call_t *)sys_fork, AUE_FORK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 2 = fork */
+	{ AS(read_args), (sy_call_t *)sys_read, AUE_READ, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 3 = read */
+	{ AS(write_args), (sy_call_t *)sys_write, AUE_WRITE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 4 = write */
+	{ AS(open_args), (sy_call_t *)sys_open, AUE_OPEN_RWTC, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 5 = open */
+	{ AS(close_args), (sy_call_t *)sys_close, AUE_CLOSE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 6 = close */
 	{ AS(freebsd32_wait4_args), (sy_call_t *)freebsd32_wait4, AUE_WAIT4, NULL, 0, 0, 0, SY_THR_STATIC },	/* 7 = freebsd32_wait4 */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 8 = obsolete old creat */
 	{ AS(link_args), (sy_call_t *)sys_link, AUE_LINK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 9 = link */
@@ -70,125 +70,125 @@ struct sysent freebsd32_sysent[] = {
 	{ AS(mknod_args), (sy_call_t *)sys_mknod, AUE_MKNOD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 14 = mknod */
 	{ AS(chmod_args), (sy_call_t *)sys_chmod, AUE_CHMOD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 15 = chmod */
 	{ AS(chown_args), (sy_call_t *)sys_chown, AUE_CHOWN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 16 = chown */
-	{ AS(obreak_args), (sy_call_t *)sys_obreak, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 17 = break */
+	{ AS(obreak_args), (sy_call_t *)sys_obreak, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 17 = break */
 	{ compat4(AS(freebsd4_freebsd32_getfsstat_args),freebsd32_getfsstat), AUE_GETFSSTAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 18 = freebsd4 freebsd32_getfsstat */
-	{ compat(AS(ofreebsd32_lseek_args),freebsd32_lseek), AUE_LSEEK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 19 = old freebsd32_lseek */
-	{ 0, (sy_call_t *)sys_getpid, AUE_GETPID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 20 = getpid */
+	{ compat(AS(ofreebsd32_lseek_args),freebsd32_lseek), AUE_LSEEK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 19 = old freebsd32_lseek */
+	{ 0, (sy_call_t *)sys_getpid, AUE_GETPID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 20 = getpid */
 	{ AS(mount_args), (sy_call_t *)sys_mount, AUE_MOUNT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 21 = mount */
 	{ AS(unmount_args), (sy_call_t *)sys_unmount, AUE_UMOUNT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 22 = unmount */
-	{ AS(setuid_args), (sy_call_t *)sys_setuid, AUE_SETUID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 23 = setuid */
-	{ 0, (sy_call_t *)sys_getuid, AUE_GETUID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 24 = getuid */
-	{ 0, (sy_call_t *)sys_geteuid, AUE_GETEUID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 25 = geteuid */
+	{ AS(setuid_args), (sy_call_t *)sys_setuid, AUE_SETUID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 23 = setuid */
+	{ 0, (sy_call_t *)sys_getuid, AUE_GETUID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 24 = getuid */
+	{ 0, (sy_call_t *)sys_geteuid, AUE_GETEUID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 25 = geteuid */
 	{ AS(ptrace_args), (sy_call_t *)sys_ptrace, AUE_PTRACE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 26 = ptrace */
-	{ AS(freebsd32_recvmsg_args), (sy_call_t *)freebsd32_recvmsg, AUE_RECVMSG, NULL, 0, 0, 0, SY_THR_STATIC },	/* 27 = freebsd32_recvmsg */
-	{ AS(freebsd32_sendmsg_args), (sy_call_t *)freebsd32_sendmsg, AUE_SENDMSG, NULL, 0, 0, 0, SY_THR_STATIC },	/* 28 = freebsd32_sendmsg */
-	{ AS(freebsd32_recvfrom_args), (sy_call_t *)freebsd32_recvfrom, AUE_RECVFROM, NULL, 0, 0, 0, SY_THR_STATIC },	/* 29 = freebsd32_recvfrom */
-	{ AS(accept_args), (sy_call_t *)sys_accept, AUE_ACCEPT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 30 = accept */
-	{ AS(getpeername_args), (sy_call_t *)sys_getpeername, AUE_GETPEERNAME, NULL, 0, 0, 0, SY_THR_STATIC },	/* 31 = getpeername */
-	{ AS(getsockname_args), (sy_call_t *)sys_getsockname, AUE_GETSOCKNAME, NULL, 0, 0, 0, SY_THR_STATIC },	/* 32 = getsockname */
+	{ AS(freebsd32_recvmsg_args), (sy_call_t *)freebsd32_recvmsg, AUE_RECVMSG, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 27 = freebsd32_recvmsg */
+	{ AS(freebsd32_sendmsg_args), (sy_call_t *)freebsd32_sendmsg, AUE_SENDMSG, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 28 = freebsd32_sendmsg */
+	{ AS(freebsd32_recvfrom_args), (sy_call_t *)freebsd32_recvfrom, AUE_RECVFROM, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 29 = freebsd32_recvfrom */
+	{ AS(accept_args), (sy_call_t *)sys_accept, AUE_ACCEPT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 30 = accept */
+	{ AS(getpeername_args), (sy_call_t *)sys_getpeername, AUE_GETPEERNAME, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 31 = getpeername */
+	{ AS(getsockname_args), (sy_call_t *)sys_getsockname, AUE_GETSOCKNAME, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 32 = getsockname */
 	{ AS(access_args), (sy_call_t *)sys_access, AUE_ACCESS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 33 = access */
 	{ AS(chflags_args), (sy_call_t *)sys_chflags, AUE_CHFLAGS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 34 = chflags */
-	{ AS(fchflags_args), (sy_call_t *)sys_fchflags, AUE_FCHFLAGS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 35 = fchflags */
-	{ 0, (sy_call_t *)sys_sync, AUE_SYNC, NULL, 0, 0, 0, SY_THR_STATIC },		/* 36 = sync */
-	{ AS(kill_args), (sy_call_t *)sys_kill, AUE_KILL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 37 = kill */
+	{ AS(fchflags_args), (sy_call_t *)sys_fchflags, AUE_FCHFLAGS, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 35 = fchflags */
+	{ 0, (sy_call_t *)sys_sync, AUE_SYNC, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 36 = sync */
+	{ AS(kill_args), (sy_call_t *)sys_kill, AUE_KILL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 37 = kill */
 	{ compat(AS(ofreebsd32_stat_args),freebsd32_stat), AUE_STAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 38 = old freebsd32_stat */
-	{ 0, (sy_call_t *)sys_getppid, AUE_GETPPID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 39 = getppid */
+	{ 0, (sy_call_t *)sys_getppid, AUE_GETPPID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 39 = getppid */
 	{ compat(AS(ofreebsd32_lstat_args),freebsd32_lstat), AUE_LSTAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 40 = old freebsd32_lstat */
-	{ AS(dup_args), (sy_call_t *)sys_dup, AUE_DUP, NULL, 0, 0, 0, SY_THR_STATIC },	/* 41 = dup */
-	{ compat10(0,freebsd32_pipe), AUE_PIPE, NULL, 0, 0, 0, SY_THR_STATIC },		/* 42 = freebsd10 freebsd32_pipe */
-	{ 0, (sy_call_t *)sys_getegid, AUE_GETEGID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 43 = getegid */
-	{ AS(profil_args), (sy_call_t *)sys_profil, AUE_PROFILE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 44 = profil */
+	{ AS(dup_args), (sy_call_t *)sys_dup, AUE_DUP, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 41 = dup */
+	{ compat10(0,freebsd32_pipe), AUE_PIPE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 42 = freebsd10 freebsd32_pipe */
+	{ 0, (sy_call_t *)sys_getegid, AUE_GETEGID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 43 = getegid */
+	{ AS(profil_args), (sy_call_t *)sys_profil, AUE_PROFILE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 44 = profil */
 	{ AS(ktrace_args), (sy_call_t *)sys_ktrace, AUE_KTRACE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 45 = ktrace */
-	{ compat(AS(ofreebsd32_sigaction_args),freebsd32_sigaction), AUE_SIGACTION, NULL, 0, 0, 0, SY_THR_STATIC },	/* 46 = old freebsd32_sigaction */
-	{ 0, (sy_call_t *)sys_getgid, AUE_GETGID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 47 = getgid */
+	{ compat(AS(ofreebsd32_sigaction_args),freebsd32_sigaction), AUE_SIGACTION, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 46 = old freebsd32_sigaction */
+	{ 0, (sy_call_t *)sys_getgid, AUE_GETGID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 47 = getgid */
 	{ compat(AS(ofreebsd32_sigprocmask_args),freebsd32_sigprocmask), AUE_SIGPROCMASK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 48 = old freebsd32_sigprocmask */
-	{ AS(getlogin_args), (sy_call_t *)sys_getlogin, AUE_GETLOGIN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 49 = getlogin */
+	{ AS(getlogin_args), (sy_call_t *)sys_getlogin, AUE_GETLOGIN, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 49 = getlogin */
 	{ AS(setlogin_args), (sy_call_t *)sys_setlogin, AUE_SETLOGIN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 50 = setlogin */
 	{ AS(acct_args), (sy_call_t *)sys_acct, AUE_ACCT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 51 = acct */
-	{ compat(0,freebsd32_sigpending), AUE_SIGPENDING, NULL, 0, 0, 0, SY_THR_STATIC },	/* 52 = old freebsd32_sigpending */
-	{ AS(freebsd32_sigaltstack_args), (sy_call_t *)freebsd32_sigaltstack, AUE_SIGALTSTACK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 53 = freebsd32_sigaltstack */
-	{ AS(freebsd32_ioctl_args), (sy_call_t *)freebsd32_ioctl, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 54 = freebsd32_ioctl */
+	{ compat(0,freebsd32_sigpending), AUE_SIGPENDING, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 52 = old freebsd32_sigpending */
+	{ AS(freebsd32_sigaltstack_args), (sy_call_t *)freebsd32_sigaltstack, AUE_SIGALTSTACK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 53 = freebsd32_sigaltstack */
+	{ AS(freebsd32_ioctl_args), (sy_call_t *)freebsd32_ioctl, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 54 = freebsd32_ioctl */
 	{ AS(reboot_args), (sy_call_t *)sys_reboot, AUE_REBOOT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 55 = reboot */
 	{ AS(revoke_args), (sy_call_t *)sys_revoke, AUE_REVOKE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 56 = revoke */
 	{ AS(symlink_args), (sy_call_t *)sys_symlink, AUE_SYMLINK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 57 = symlink */
 	{ AS(readlink_args), (sy_call_t *)sys_readlink, AUE_READLINK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 58 = readlink */
 	{ AS(freebsd32_execve_args), (sy_call_t *)freebsd32_execve, AUE_EXECVE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 59 = freebsd32_execve */
-	{ AS(umask_args), (sy_call_t *)sys_umask, AUE_UMASK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 60 = umask */
+	{ AS(umask_args), (sy_call_t *)sys_umask, AUE_UMASK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 60 = umask */
 	{ AS(chroot_args), (sy_call_t *)sys_chroot, AUE_CHROOT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 61 = chroot */
-	{ compat(AS(ofreebsd32_fstat_args),freebsd32_fstat), AUE_FSTAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 62 = old freebsd32_fstat */
+	{ compat(AS(ofreebsd32_fstat_args),freebsd32_fstat), AUE_FSTAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 62 = old freebsd32_fstat */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 63 = obsolete ogetkerninfo */
-	{ compat(AS(ofreebsd32_getpagesize_args),freebsd32_getpagesize), AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 64 = old freebsd32_getpagesize */
-	{ AS(msync_args), (sy_call_t *)sys_msync, AUE_MSYNC, NULL, 0, 0, 0, SY_THR_STATIC },	/* 65 = msync */
+	{ compat(AS(ofreebsd32_getpagesize_args),freebsd32_getpagesize), AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 64 = old freebsd32_getpagesize */
+	{ AS(msync_args), (sy_call_t *)sys_msync, AUE_MSYNC, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 65 = msync */
 	{ 0, (sy_call_t *)sys_vfork, AUE_VFORK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 66 = vfork */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 67 = obsolete vread */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 68 = obsolete vwrite */
-	{ AS(sbrk_args), (sy_call_t *)sys_sbrk, AUE_SBRK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 69 = sbrk */
-	{ AS(sstk_args), (sy_call_t *)sys_sstk, AUE_SSTK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 70 = sstk */
+	{ AS(sbrk_args), (sy_call_t *)sys_sbrk, AUE_SBRK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 69 = sbrk */
+	{ AS(sstk_args), (sy_call_t *)sys_sstk, AUE_SSTK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 70 = sstk */
 	{ compat(AS(ommap_args),mmap), AUE_MMAP, NULL, 0, 0, 0, SY_THR_STATIC },	/* 71 = old mmap */
 	{ AS(ovadvise_args), (sy_call_t *)sys_ovadvise, AUE_O_VADVISE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 72 = vadvise */
-	{ AS(munmap_args), (sy_call_t *)sys_munmap, AUE_MUNMAP, NULL, 0, 0, 0, SY_THR_STATIC },	/* 73 = munmap */
-	{ AS(freebsd32_mprotect_args), (sy_call_t *)freebsd32_mprotect, AUE_MPROTECT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 74 = freebsd32_mprotect */
-	{ AS(madvise_args), (sy_call_t *)sys_madvise, AUE_MADVISE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 75 = madvise */
+	{ AS(munmap_args), (sy_call_t *)sys_munmap, AUE_MUNMAP, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 73 = munmap */
+	{ AS(freebsd32_mprotect_args), (sy_call_t *)freebsd32_mprotect, AUE_MPROTECT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 74 = freebsd32_mprotect */
+	{ AS(madvise_args), (sy_call_t *)sys_madvise, AUE_MADVISE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 75 = madvise */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 76 = obsolete vhangup */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 77 = obsolete vlimit */
-	{ AS(mincore_args), (sy_call_t *)sys_mincore, AUE_MINCORE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 78 = mincore */
-	{ AS(getgroups_args), (sy_call_t *)sys_getgroups, AUE_GETGROUPS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 79 = getgroups */
+	{ AS(mincore_args), (sy_call_t *)sys_mincore, AUE_MINCORE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 78 = mincore */
+	{ AS(getgroups_args), (sy_call_t *)sys_getgroups, AUE_GETGROUPS, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 79 = getgroups */
 	{ AS(setgroups_args), (sy_call_t *)sys_setgroups, AUE_SETGROUPS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 80 = setgroups */
-	{ 0, (sy_call_t *)sys_getpgrp, AUE_GETPGRP, NULL, 0, 0, 0, SY_THR_STATIC },	/* 81 = getpgrp */
+	{ 0, (sy_call_t *)sys_getpgrp, AUE_GETPGRP, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 81 = getpgrp */
 	{ AS(setpgid_args), (sy_call_t *)sys_setpgid, AUE_SETPGRP, NULL, 0, 0, 0, SY_THR_STATIC },	/* 82 = setpgid */
-	{ AS(freebsd32_setitimer_args), (sy_call_t *)freebsd32_setitimer, AUE_SETITIMER, NULL, 0, 0, 0, SY_THR_STATIC },	/* 83 = freebsd32_setitimer */
+	{ AS(freebsd32_setitimer_args), (sy_call_t *)freebsd32_setitimer, AUE_SETITIMER, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 83 = freebsd32_setitimer */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 84 = obsolete owait */
 	{ AS(swapon_args), (sy_call_t *)sys_swapon, AUE_SWAPON, NULL, 0, 0, 0, SY_THR_STATIC },	/* 85 = swapon */
-	{ AS(freebsd32_getitimer_args), (sy_call_t *)freebsd32_getitimer, AUE_GETITIMER, NULL, 0, 0, 0, SY_THR_STATIC },	/* 86 = freebsd32_getitimer */
+	{ AS(freebsd32_getitimer_args), (sy_call_t *)freebsd32_getitimer, AUE_GETITIMER, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 86 = freebsd32_getitimer */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 87 = obsolete ogethostname */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 88 = obsolete osethostname */
-	{ 0, (sy_call_t *)sys_getdtablesize, AUE_GETDTABLESIZE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 89 = getdtablesize */
-	{ AS(dup2_args), (sy_call_t *)sys_dup2, AUE_DUP2, NULL, 0, 0, 0, SY_THR_STATIC },	/* 90 = dup2 */
+	{ 0, (sy_call_t *)sys_getdtablesize, AUE_GETDTABLESIZE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 89 = getdtablesize */
+	{ AS(dup2_args), (sy_call_t *)sys_dup2, AUE_DUP2, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 90 = dup2 */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 91 = getdopt */
-	{ AS(freebsd32_fcntl_args), (sy_call_t *)freebsd32_fcntl, AUE_FCNTL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 92 = freebsd32_fcntl */
-	{ AS(freebsd32_select_args), (sy_call_t *)freebsd32_select, AUE_SELECT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 93 = freebsd32_select */
+	{ AS(freebsd32_fcntl_args), (sy_call_t *)freebsd32_fcntl, AUE_FCNTL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 92 = freebsd32_fcntl */
+	{ AS(freebsd32_select_args), (sy_call_t *)freebsd32_select, AUE_SELECT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 93 = freebsd32_select */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 94 = setdopt */
-	{ AS(fsync_args), (sy_call_t *)sys_fsync, AUE_FSYNC, NULL, 0, 0, 0, SY_THR_STATIC },	/* 95 = fsync */
-	{ AS(setpriority_args), (sy_call_t *)sys_setpriority, AUE_SETPRIORITY, NULL, 0, 0, 0, SY_THR_STATIC },	/* 96 = setpriority */
-	{ AS(socket_args), (sy_call_t *)sys_socket, AUE_SOCKET, NULL, 0, 0, 0, SY_THR_STATIC },	/* 97 = socket */
+	{ AS(fsync_args), (sy_call_t *)sys_fsync, AUE_FSYNC, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 95 = fsync */
+	{ AS(setpriority_args), (sy_call_t *)sys_setpriority, AUE_SETPRIORITY, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 96 = setpriority */
+	{ AS(socket_args), (sy_call_t *)sys_socket, AUE_SOCKET, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 97 = socket */
 	{ AS(connect_args), (sy_call_t *)sys_connect, AUE_CONNECT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 98 = connect */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 99 = obsolete oaccept */
-	{ AS(getpriority_args), (sy_call_t *)sys_getpriority, AUE_GETPRIORITY, NULL, 0, 0, 0, SY_THR_STATIC },	/* 100 = getpriority */
+	{ AS(getpriority_args), (sy_call_t *)sys_getpriority, AUE_GETPRIORITY, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 100 = getpriority */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 101 = obsolete osend */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 102 = obsolete orecv */
-	{ compat(AS(ofreebsd32_sigreturn_args),freebsd32_sigreturn), AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 103 = old freebsd32_sigreturn */
+	{ compat(AS(ofreebsd32_sigreturn_args),freebsd32_sigreturn), AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 103 = old freebsd32_sigreturn */
 	{ AS(bind_args), (sy_call_t *)sys_bind, AUE_BIND, NULL, 0, 0, 0, SY_THR_STATIC },	/* 104 = bind */
-	{ AS(setsockopt_args), (sy_call_t *)sys_setsockopt, AUE_SETSOCKOPT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 105 = setsockopt */
-	{ AS(listen_args), (sy_call_t *)sys_listen, AUE_LISTEN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 106 = listen */
+	{ AS(setsockopt_args), (sy_call_t *)sys_setsockopt, AUE_SETSOCKOPT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 105 = setsockopt */
+	{ AS(listen_args), (sy_call_t *)sys_listen, AUE_LISTEN, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 106 = listen */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 107 = obsolete vtimes */
-	{ compat(AS(ofreebsd32_sigvec_args),freebsd32_sigvec), AUE_O_SIGVEC, NULL, 0, 0, 0, SY_THR_STATIC },	/* 108 = old freebsd32_sigvec */
-	{ compat(AS(ofreebsd32_sigblock_args),freebsd32_sigblock), AUE_O_SIGBLOCK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 109 = old freebsd32_sigblock */
-	{ compat(AS(ofreebsd32_sigsetmask_args),freebsd32_sigsetmask), AUE_O_SIGSETMASK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 110 = old freebsd32_sigsetmask */
+	{ compat(AS(ofreebsd32_sigvec_args),freebsd32_sigvec), AUE_O_SIGVEC, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 108 = old freebsd32_sigvec */
+	{ compat(AS(ofreebsd32_sigblock_args),freebsd32_sigblock), AUE_O_SIGBLOCK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 109 = old freebsd32_sigblock */
+	{ compat(AS(ofreebsd32_sigsetmask_args),freebsd32_sigsetmask), AUE_O_SIGSETMASK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 110 = old freebsd32_sigsetmask */
 	{ compat(AS(ofreebsd32_sigsuspend_args),freebsd32_sigsuspend), AUE_SIGSUSPEND, NULL, 0, 0, 0, SY_THR_STATIC },	/* 111 = old freebsd32_sigsuspend */
 	{ compat(AS(ofreebsd32_sigstack_args),freebsd32_sigstack), AUE_O_SIGSTACK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 112 = old freebsd32_sigstack */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 113 = obsolete orecvmsg */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 114 = obsolete osendmsg */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 115 = obsolete vtrace */
-	{ AS(freebsd32_gettimeofday_args), (sy_call_t *)freebsd32_gettimeofday, AUE_GETTIMEOFDAY, NULL, 0, 0, 0, SY_THR_STATIC },	/* 116 = freebsd32_gettimeofday */
-	{ AS(freebsd32_getrusage_args), (sy_call_t *)freebsd32_getrusage, AUE_GETRUSAGE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 117 = freebsd32_getrusage */
-	{ AS(getsockopt_args), (sy_call_t *)sys_getsockopt, AUE_GETSOCKOPT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 118 = getsockopt */
+	{ AS(freebsd32_gettimeofday_args), (sy_call_t *)freebsd32_gettimeofday, AUE_GETTIMEOFDAY, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 116 = freebsd32_gettimeofday */
+	{ AS(freebsd32_getrusage_args), (sy_call_t *)freebsd32_getrusage, AUE_GETRUSAGE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 117 = freebsd32_getrusage */
+	{ AS(getsockopt_args), (sy_call_t *)sys_getsockopt, AUE_GETSOCKOPT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 118 = getsockopt */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 119 = resuba */
-	{ AS(freebsd32_readv_args), (sy_call_t *)freebsd32_readv, AUE_READV, NULL, 0, 0, 0, SY_THR_STATIC },	/* 120 = freebsd32_readv */
-	{ AS(freebsd32_writev_args), (sy_call_t *)freebsd32_writev, AUE_WRITEV, NULL, 0, 0, 0, SY_THR_STATIC },	/* 121 = freebsd32_writev */
+	{ AS(freebsd32_readv_args), (sy_call_t *)freebsd32_readv, AUE_READV, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 120 = freebsd32_readv */
+	{ AS(freebsd32_writev_args), (sy_call_t *)freebsd32_writev, AUE_WRITEV, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 121 = freebsd32_writev */
 	{ AS(freebsd32_settimeofday_args), (sy_call_t *)freebsd32_settimeofday, AUE_SETTIMEOFDAY, NULL, 0, 0, 0, SY_THR_STATIC },	/* 122 = freebsd32_settimeofday */
-	{ AS(fchown_args), (sy_call_t *)sys_fchown, AUE_FCHOWN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 123 = fchown */
-	{ AS(fchmod_args), (sy_call_t *)sys_fchmod, AUE_FCHMOD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 124 = fchmod */
+	{ AS(fchown_args), (sy_call_t *)sys_fchown, AUE_FCHOWN, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 123 = fchown */
+	{ AS(fchmod_args), (sy_call_t *)sys_fchmod, AUE_FCHMOD, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 124 = fchmod */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 125 = obsolete orecvfrom */
-	{ AS(setreuid_args), (sy_call_t *)sys_setreuid, AUE_SETREUID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 126 = setreuid */
-	{ AS(setregid_args), (sy_call_t *)sys_setregid, AUE_SETREGID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 127 = setregid */
+	{ AS(setreuid_args), (sy_call_t *)sys_setreuid, AUE_SETREUID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 126 = setreuid */
+	{ AS(setregid_args), (sy_call_t *)sys_setregid, AUE_SETREGID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 127 = setregid */
 	{ AS(rename_args), (sy_call_t *)sys_rename, AUE_RENAME, NULL, 0, 0, 0, SY_THR_STATIC },	/* 128 = rename */
 	{ compat(AS(otruncate_args),truncate), AUE_TRUNCATE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 129 = old truncate */
-	{ compat(AS(oftruncate_args),ftruncate), AUE_FTRUNCATE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 130 = old ftruncate */
-	{ AS(flock_args), (sy_call_t *)sys_flock, AUE_FLOCK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 131 = flock */
+	{ compat(AS(oftruncate_args),ftruncate), AUE_FTRUNCATE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 130 = old ftruncate */
+	{ AS(flock_args), (sy_call_t *)sys_flock, AUE_FLOCK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 131 = flock */
 	{ AS(mkfifo_args), (sy_call_t *)sys_mkfifo, AUE_MKFIFO, NULL, 0, 0, 0, SY_THR_STATIC },	/* 132 = mkfifo */
-	{ AS(sendto_args), (sy_call_t *)sys_sendto, AUE_SENDTO, NULL, 0, 0, 0, SY_THR_STATIC },	/* 133 = sendto */
-	{ AS(shutdown_args), (sy_call_t *)sys_shutdown, AUE_SHUTDOWN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 134 = shutdown */
-	{ AS(socketpair_args), (sy_call_t *)sys_socketpair, AUE_SOCKETPAIR, NULL, 0, 0, 0, SY_THR_STATIC },	/* 135 = socketpair */
+	{ AS(sendto_args), (sy_call_t *)sys_sendto, AUE_SENDTO, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 133 = sendto */
+	{ AS(shutdown_args), (sy_call_t *)sys_shutdown, AUE_SHUTDOWN, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 134 = shutdown */
+	{ AS(socketpair_args), (sy_call_t *)sys_socketpair, AUE_SOCKETPAIR, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 135 = socketpair */
 	{ AS(mkdir_args), (sy_call_t *)sys_mkdir, AUE_MKDIR, NULL, 0, 0, 0, SY_THR_STATIC },	/* 136 = mkdir */
 	{ AS(rmdir_args), (sy_call_t *)sys_rmdir, AUE_RMDIR, NULL, 0, 0, 0, SY_THR_STATIC },	/* 137 = rmdir */
 	{ AS(freebsd32_utimes_args), (sy_call_t *)freebsd32_utimes, AUE_UTIMES, NULL, 0, 0, 0, SY_THR_STATIC },	/* 138 = freebsd32_utimes */
@@ -200,7 +200,7 @@ struct sysent freebsd32_sysent[] = {
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 144 = obsolete getrlimit */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 145 = obsolete setrlimit */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 146 = obsolete killpg */
-	{ 0, (sy_call_t *)sys_setsid, AUE_SETSID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 147 = setsid */
+	{ 0, (sy_call_t *)sys_setsid, AUE_SETSID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 147 = setsid */
 	{ AS(quotactl_args), (sy_call_t *)sys_quotactl, AUE_QUOTACTL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 148 = quotactl */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 149 = obsolete oquota */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 150 = obsolete ogetsockname */
@@ -209,7 +209,7 @@ struct sysent freebsd32_sysent[] = {
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 153 = asyncdaemon */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 154 = nlm_syscall */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 155 = nfssvc */
-	{ compat(AS(ofreebsd32_getdirentries_args),freebsd32_getdirentries), AUE_GETDIRENTRIES, NULL, 0, 0, 0, SY_THR_STATIC },	/* 156 = old freebsd32_getdirentries */
+	{ compat(AS(ofreebsd32_getdirentries_args),freebsd32_getdirentries), AUE_GETDIRENTRIES, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 156 = old freebsd32_getdirentries */
 	{ compat4(AS(freebsd4_freebsd32_statfs_args),freebsd32_statfs), AUE_STATFS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 157 = freebsd4 freebsd32_statfs */
 	{ compat4(AS(freebsd4_freebsd32_fstatfs_args),freebsd32_fstatfs), AUE_FSTATFS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 158 = freebsd4 freebsd32_fstatfs */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 159 = nosys */
@@ -218,51 +218,51 @@ struct sysent freebsd32_sysent[] = {
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 162 = obsolete getdomainname */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 163 = obsolete setdomainname */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 164 = obsolete uname */
-	{ AS(freebsd32_sysarch_args), (sy_call_t *)freebsd32_sysarch, AUE_SYSARCH, NULL, 0, 0, 0, SY_THR_STATIC },	/* 165 = freebsd32_sysarch */
-	{ AS(rtprio_args), (sy_call_t *)sys_rtprio, AUE_RTPRIO, NULL, 0, 0, 0, SY_THR_STATIC },	/* 166 = rtprio */
+	{ AS(freebsd32_sysarch_args), (sy_call_t *)freebsd32_sysarch, AUE_SYSARCH, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 165 = freebsd32_sysarch */
+	{ AS(rtprio_args), (sy_call_t *)sys_rtprio, AUE_RTPRIO, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 166 = rtprio */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 167 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 168 = nosys */
 	{ AS(freebsd32_semsys_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 169 = freebsd32_semsys */
 	{ AS(freebsd32_msgsys_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 170 = freebsd32_msgsys */
 	{ AS(freebsd32_shmsys_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 171 = freebsd32_shmsys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 172 = nosys */
-	{ compat6(AS(freebsd6_freebsd32_pread_args),freebsd32_pread), AUE_PREAD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 173 = freebsd6 freebsd32_pread */
-	{ compat6(AS(freebsd6_freebsd32_pwrite_args),freebsd32_pwrite), AUE_PWRITE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 174 = freebsd6 freebsd32_pwrite */
+	{ compat6(AS(freebsd6_freebsd32_pread_args),freebsd32_pread), AUE_PREAD, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 173 = freebsd6 freebsd32_pread */
+	{ compat6(AS(freebsd6_freebsd32_pwrite_args),freebsd32_pwrite), AUE_PWRITE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 174 = freebsd6 freebsd32_pwrite */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 175 = nosys */
 	{ AS(ntp_adjtime_args), (sy_call_t *)sys_ntp_adjtime, AUE_NTP_ADJTIME, NULL, 0, 0, 0, SY_THR_STATIC },	/* 176 = ntp_adjtime */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 177 = sfork */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 178 = getdescriptor */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 179 = setdescriptor */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 180 = nosys */
-	{ AS(setgid_args), (sy_call_t *)sys_setgid, AUE_SETGID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 181 = setgid */
-	{ AS(setegid_args), (sy_call_t *)sys_setegid, AUE_SETEGID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 182 = setegid */
-	{ AS(seteuid_args), (sy_call_t *)sys_seteuid, AUE_SETEUID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 183 = seteuid */
+	{ AS(setgid_args), (sy_call_t *)sys_setgid, AUE_SETGID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 181 = setgid */
+	{ AS(setegid_args), (sy_call_t *)sys_setegid, AUE_SETEGID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 182 = setegid */
+	{ AS(seteuid_args), (sy_call_t *)sys_seteuid, AUE_SETEUID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 183 = seteuid */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 184 = lfs_bmapv */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 185 = lfs_markv */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 186 = lfs_segclean */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 187 = lfs_segwait */
 	{ AS(freebsd32_stat_args), (sy_call_t *)freebsd32_stat, AUE_STAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 188 = freebsd32_stat */
-	{ AS(freebsd32_fstat_args), (sy_call_t *)freebsd32_fstat, AUE_FSTAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 189 = freebsd32_fstat */
+	{ AS(freebsd32_fstat_args), (sy_call_t *)freebsd32_fstat, AUE_FSTAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 189 = freebsd32_fstat */
 	{ AS(freebsd32_lstat_args), (sy_call_t *)freebsd32_lstat, AUE_LSTAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 190 = freebsd32_lstat */
 	{ AS(pathconf_args), (sy_call_t *)sys_pathconf, AUE_PATHCONF, NULL, 0, 0, 0, SY_THR_STATIC },	/* 191 = pathconf */
-	{ AS(fpathconf_args), (sy_call_t *)sys_fpathconf, AUE_FPATHCONF, NULL, 0, 0, 0, SY_THR_STATIC },	/* 192 = fpathconf */
+	{ AS(fpathconf_args), (sy_call_t *)sys_fpathconf, AUE_FPATHCONF, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 192 = fpathconf */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 193 = nosys */
-	{ AS(__getrlimit_args), (sy_call_t *)sys_getrlimit, AUE_GETRLIMIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 194 = getrlimit */
-	{ AS(__setrlimit_args), (sy_call_t *)sys_setrlimit, AUE_SETRLIMIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 195 = setrlimit */
-	{ AS(freebsd32_getdirentries_args), (sy_call_t *)freebsd32_getdirentries, AUE_GETDIRENTRIES, NULL, 0, 0, 0, SY_THR_STATIC },	/* 196 = freebsd32_getdirentries */
-	{ compat6(AS(freebsd6_freebsd32_mmap_args),freebsd32_mmap), AUE_MMAP, NULL, 0, 0, 0, SY_THR_STATIC },	/* 197 = freebsd6 freebsd32_mmap */
+	{ AS(__getrlimit_args), (sy_call_t *)sys_getrlimit, AUE_GETRLIMIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 194 = getrlimit */
+	{ AS(__setrlimit_args), (sy_call_t *)sys_setrlimit, AUE_SETRLIMIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 195 = setrlimit */
+	{ AS(freebsd32_getdirentries_args), (sy_call_t *)freebsd32_getdirentries, AUE_GETDIRENTRIES, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 196 = freebsd32_getdirentries */
+	{ compat6(AS(freebsd6_freebsd32_mmap_args),freebsd32_mmap), AUE_MMAP, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 197 = freebsd6 freebsd32_mmap */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },		/* 198 = __syscall */
-	{ compat6(AS(freebsd6_freebsd32_lseek_args),freebsd32_lseek), AUE_LSEEK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 199 = freebsd6 freebsd32_lseek */
+	{ compat6(AS(freebsd6_freebsd32_lseek_args),freebsd32_lseek), AUE_LSEEK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 199 = freebsd6 freebsd32_lseek */
 	{ compat6(AS(freebsd6_freebsd32_truncate_args),freebsd32_truncate), AUE_TRUNCATE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 200 = freebsd6 freebsd32_truncate */
 	{ compat6(AS(freebsd6_freebsd32_ftruncate_args),freebsd32_ftruncate), AUE_FTRUNCATE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 201 = freebsd6 freebsd32_ftruncate */
-	{ AS(freebsd32_sysctl_args), (sy_call_t *)freebsd32_sysctl, AUE_SYSCTL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 202 = freebsd32_sysctl */
-	{ AS(mlock_args), (sy_call_t *)sys_mlock, AUE_MLOCK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 203 = mlock */
-	{ AS(munlock_args), (sy_call_t *)sys_munlock, AUE_MUNLOCK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 204 = munlock */
+	{ AS(freebsd32_sysctl_args), (sy_call_t *)freebsd32_sysctl, AUE_SYSCTL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 202 = freebsd32_sysctl */
+	{ AS(mlock_args), (sy_call_t *)sys_mlock, AUE_MLOCK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 203 = mlock */
+	{ AS(munlock_args), (sy_call_t *)sys_munlock, AUE_MUNLOCK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 204 = munlock */
 	{ AS(undelete_args), (sy_call_t *)sys_undelete, AUE_UNDELETE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 205 = undelete */
-	{ AS(freebsd32_futimes_args), (sy_call_t *)freebsd32_futimes, AUE_FUTIMES, NULL, 0, 0, 0, SY_THR_STATIC },	/* 206 = freebsd32_futimes */
-	{ AS(getpgid_args), (sy_call_t *)sys_getpgid, AUE_GETPGID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 207 = getpgid */
+	{ AS(freebsd32_futimes_args), (sy_call_t *)freebsd32_futimes, AUE_FUTIMES, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 206 = freebsd32_futimes */
+	{ AS(getpgid_args), (sy_call_t *)sys_getpgid, AUE_GETPGID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 207 = getpgid */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 208 = newreboot */
-	{ AS(poll_args), (sy_call_t *)sys_poll, AUE_POLL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 209 = poll */
+	{ AS(poll_args), (sy_call_t *)sys_poll, AUE_POLL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 209 = poll */
 	{ AS(nosys_args), (sy_call_t *)lkmnosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 210 = lkmnosys */
 	{ AS(nosys_args), (sy_call_t *)lkmnosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 211 = lkmnosys */
 	{ AS(nosys_args), (sy_call_t *)lkmnosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 212 = lkmnosys */
@@ -285,15 +285,15 @@ struct sysent freebsd32_sysent[] = {
 	{ 0, (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },		/* 229 = freebsd7 freebsd32_shmctl */
 	{ AS(shmdt_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 230 = shmdt */
 	{ AS(shmget_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 231 = shmget */
-	{ AS(freebsd32_clock_gettime_args), (sy_call_t *)freebsd32_clock_gettime, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 232 = freebsd32_clock_gettime */
+	{ AS(freebsd32_clock_gettime_args), (sy_call_t *)freebsd32_clock_gettime, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 232 = freebsd32_clock_gettime */
 	{ AS(freebsd32_clock_settime_args), (sy_call_t *)freebsd32_clock_settime, AUE_CLOCK_SETTIME, NULL, 0, 0, 0, SY_THR_STATIC },	/* 233 = freebsd32_clock_settime */
-	{ AS(freebsd32_clock_getres_args), (sy_call_t *)freebsd32_clock_getres, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 234 = freebsd32_clock_getres */
-	{ AS(freebsd32_ktimer_create_args), (sy_call_t *)freebsd32_ktimer_create, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 235 = freebsd32_ktimer_create */
-	{ AS(ktimer_delete_args), (sy_call_t *)sys_ktimer_delete, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 236 = ktimer_delete */
-	{ AS(freebsd32_ktimer_settime_args), (sy_call_t *)freebsd32_ktimer_settime, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 237 = freebsd32_ktimer_settime */
-	{ AS(freebsd32_ktimer_gettime_args), (sy_call_t *)freebsd32_ktimer_gettime, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 238 = freebsd32_ktimer_gettime */
-	{ AS(ktimer_getoverrun_args), (sy_call_t *)sys_ktimer_getoverrun, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 239 = ktimer_getoverrun */
-	{ AS(freebsd32_nanosleep_args), (sy_call_t *)freebsd32_nanosleep, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 240 = freebsd32_nanosleep */
+	{ AS(freebsd32_clock_getres_args), (sy_call_t *)freebsd32_clock_getres, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 234 = freebsd32_clock_getres */
+	{ AS(freebsd32_ktimer_create_args), (sy_call_t *)freebsd32_ktimer_create, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 235 = freebsd32_ktimer_create */
+	{ AS(ktimer_delete_args), (sy_call_t *)sys_ktimer_delete, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 236 = ktimer_delete */
+	{ AS(freebsd32_ktimer_settime_args), (sy_call_t *)freebsd32_ktimer_settime, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 237 = freebsd32_ktimer_settime */
+	{ AS(freebsd32_ktimer_gettime_args), (sy_call_t *)freebsd32_ktimer_gettime, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 238 = freebsd32_ktimer_gettime */
+	{ AS(ktimer_getoverrun_args), (sy_call_t *)sys_ktimer_getoverrun, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 239 = ktimer_getoverrun */
+	{ AS(freebsd32_nanosleep_args), (sy_call_t *)freebsd32_nanosleep, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 240 = freebsd32_nanosleep */
 	{ AS(ffclock_getcounter_args), (sy_call_t *)sys_ffclock_getcounter, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 241 = ffclock_getcounter */
 	{ AS(ffclock_setestimate_args), (sy_call_t *)sys_ffclock_setestimate, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 242 = ffclock_setestimate */
 	{ AS(ffclock_getestimate_args), (sy_call_t *)sys_ffclock_getestimate, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 243 = ffclock_getestimate */
@@ -303,14 +303,14 @@ struct sysent freebsd32_sysent[] = {
 	{ AS(freebsd32_clock_getcpuclockid2_args), (sy_call_t *)freebsd32_clock_getcpuclockid2, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 247 = freebsd32_clock_getcpuclockid2 */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 248 = ntp_gettime */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 249 = nosys */
-	{ AS(minherit_args), (sy_call_t *)sys_minherit, AUE_MINHERIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 250 = minherit */
+	{ AS(minherit_args), (sy_call_t *)sys_minherit, AUE_MINHERIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 250 = minherit */
 	{ AS(rfork_args), (sy_call_t *)sys_rfork, AUE_RFORK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 251 = rfork */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 252 = obsolete openbsd_poll */
-	{ 0, (sy_call_t *)sys_issetugid, AUE_ISSETUGID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 253 = issetugid */
+	{ 0, (sy_call_t *)sys_issetugid, AUE_ISSETUGID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 253 = issetugid */
 	{ AS(lchown_args), (sy_call_t *)sys_lchown, AUE_LCHOWN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 254 = lchown */
-	{ AS(freebsd32_aio_read_args), (sy_call_t *)freebsd32_aio_read, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 255 = freebsd32_aio_read */
-	{ AS(freebsd32_aio_write_args), (sy_call_t *)freebsd32_aio_write, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 256 = freebsd32_aio_write */
-	{ AS(freebsd32_lio_listio_args), (sy_call_t *)freebsd32_lio_listio, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 257 = freebsd32_lio_listio */
+	{ AS(freebsd32_aio_read_args), (sy_call_t *)freebsd32_aio_read, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 255 = freebsd32_aio_read */
+	{ AS(freebsd32_aio_write_args), (sy_call_t *)freebsd32_aio_write, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 256 = freebsd32_aio_write */
+	{ AS(freebsd32_lio_listio_args), (sy_call_t *)freebsd32_lio_listio, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 257 = freebsd32_lio_listio */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 258 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 259 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 260 = nosys */
@@ -325,12 +325,12 @@ struct sysent freebsd32_sysent[] = {
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 269 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 270 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 271 = nosys */
-	{ AS(getdents_args), (sy_call_t *)sys_getdents, AUE_O_GETDENTS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 272 = getdents */
+	{ AS(getdents_args), (sy_call_t *)sys_getdents, AUE_O_GETDENTS, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 272 = getdents */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 273 = nosys */
 	{ AS(lchmod_args), (sy_call_t *)sys_lchmod, AUE_LCHMOD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 274 = lchmod */
 	{ AS(lchown_args), (sy_call_t *)sys_lchown, AUE_LCHOWN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 275 = netbsd_lchown */
 	{ AS(freebsd32_lutimes_args), (sy_call_t *)freebsd32_lutimes, AUE_LUTIMES, NULL, 0, 0, 0, SY_THR_STATIC },	/* 276 = freebsd32_lutimes */
-	{ AS(msync_args), (sy_call_t *)sys_msync, AUE_MSYNC, NULL, 0, 0, 0, SY_THR_STATIC },	/* 277 = netbsd_msync */
+	{ AS(msync_args), (sy_call_t *)sys_msync, AUE_MSYNC, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 277 = netbsd_msync */
 	{ AS(nstat_args), (sy_call_t *)sys_nstat, AUE_STAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 278 = nstat */
 	{ AS(nfstat_args), (sy_call_t *)sys_nfstat, AUE_FSTAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 279 = nfstat */
 	{ AS(nlstat_args), (sy_call_t *)sys_nlstat, AUE_LSTAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 280 = nlstat */
@@ -342,8 +342,8 @@ struct sysent freebsd32_sysent[] = {
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 286 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 287 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 288 = nosys */
-	{ AS(freebsd32_preadv_args), (sy_call_t *)freebsd32_preadv, AUE_PREADV, NULL, 0, 0, 0, SY_THR_STATIC },	/* 289 = freebsd32_preadv */
-	{ AS(freebsd32_pwritev_args), (sy_call_t *)freebsd32_pwritev, AUE_PWRITEV, NULL, 0, 0, 0, SY_THR_STATIC },	/* 290 = freebsd32_pwritev */
+	{ AS(freebsd32_preadv_args), (sy_call_t *)freebsd32_preadv, AUE_PREADV, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 289 = freebsd32_preadv */
+	{ AS(freebsd32_pwritev_args), (sy_call_t *)freebsd32_pwritev, AUE_PWRITEV, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 290 = freebsd32_pwritev */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 291 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 292 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 293 = nosys */
@@ -363,60 +363,60 @@ struct sysent freebsd32_sysent[] = {
 	{ AS(kldnext_args), (sy_call_t *)sys_kldnext, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 307 = kldnext */
 	{ AS(freebsd32_kldstat_args), (sy_call_t *)freebsd32_kldstat, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 308 = freebsd32_kldstat */
 	{ AS(kldfirstmod_args), (sy_call_t *)sys_kldfirstmod, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 309 = kldfirstmod */
-	{ AS(getsid_args), (sy_call_t *)sys_getsid, AUE_GETSID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 310 = getsid */
-	{ AS(setresuid_args), (sy_call_t *)sys_setresuid, AUE_SETRESUID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 311 = setresuid */
-	{ AS(setresgid_args), (sy_call_t *)sys_setresgid, AUE_SETRESGID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 312 = setresgid */
+	{ AS(getsid_args), (sy_call_t *)sys_getsid, AUE_GETSID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 310 = getsid */
+	{ AS(setresuid_args), (sy_call_t *)sys_setresuid, AUE_SETRESUID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 311 = setresuid */
+	{ AS(setresgid_args), (sy_call_t *)sys_setresgid, AUE_SETRESGID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 312 = setresgid */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 313 = obsolete signanosleep */
-	{ AS(freebsd32_aio_return_args), (sy_call_t *)freebsd32_aio_return, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 314 = freebsd32_aio_return */
-	{ AS(freebsd32_aio_suspend_args), (sy_call_t *)freebsd32_aio_suspend, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 315 = freebsd32_aio_suspend */
-	{ AS(aio_cancel_args), (sy_call_t *)sys_aio_cancel, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 316 = aio_cancel */
-	{ AS(freebsd32_aio_error_args), (sy_call_t *)freebsd32_aio_error, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 317 = freebsd32_aio_error */
-	{ compat6(AS(freebsd6_freebsd32_aio_read_args),freebsd32_aio_read), AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 318 = freebsd6 freebsd32_aio_read */
-	{ compat6(AS(freebsd6_freebsd32_aio_write_args),freebsd32_aio_write), AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 319 = freebsd6 freebsd32_aio_write */
-	{ compat6(AS(freebsd6_freebsd32_lio_listio_args),freebsd32_lio_listio), AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 320 = freebsd6 freebsd32_lio_listio */
-	{ 0, (sy_call_t *)sys_yield, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },		/* 321 = yield */
+	{ AS(freebsd32_aio_return_args), (sy_call_t *)freebsd32_aio_return, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 314 = freebsd32_aio_return */
+	{ AS(freebsd32_aio_suspend_args), (sy_call_t *)freebsd32_aio_suspend, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 315 = freebsd32_aio_suspend */
+	{ AS(aio_cancel_args), (sy_call_t *)sys_aio_cancel, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 316 = aio_cancel */
+	{ AS(freebsd32_aio_error_args), (sy_call_t *)freebsd32_aio_error, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 317 = freebsd32_aio_error */
+	{ compat6(AS(freebsd6_freebsd32_aio_read_args),freebsd32_aio_read), AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 318 = freebsd6 freebsd32_aio_read */
+	{ compat6(AS(freebsd6_freebsd32_aio_write_args),freebsd32_aio_write), AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 319 = freebsd6 freebsd32_aio_write */
+	{ compat6(AS(freebsd6_freebsd32_lio_listio_args),freebsd32_lio_listio), AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 320 = freebsd6 freebsd32_lio_listio */
+	{ 0, (sy_call_t *)sys_yield, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 321 = yield */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 322 = obsolete thr_sleep */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 323 = obsolete thr_wakeup */
-	{ AS(mlockall_args), (sy_call_t *)sys_mlockall, AUE_MLOCKALL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 324 = mlockall */
-	{ 0, (sy_call_t *)sys_munlockall, AUE_MUNLOCKALL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 325 = munlockall */
+	{ AS(mlockall_args), (sy_call_t *)sys_mlockall, AUE_MLOCKALL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 324 = mlockall */
+	{ 0, (sy_call_t *)sys_munlockall, AUE_MUNLOCKALL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 325 = munlockall */
 	{ AS(__getcwd_args), (sy_call_t *)sys___getcwd, AUE_GETCWD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 326 = __getcwd */
-	{ AS(sched_setparam_args), (sy_call_t *)sys_sched_setparam, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 327 = sched_setparam */
-	{ AS(sched_getparam_args), (sy_call_t *)sys_sched_getparam, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 328 = sched_getparam */
-	{ AS(sched_setscheduler_args), (sy_call_t *)sys_sched_setscheduler, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 329 = sched_setscheduler */
-	{ AS(sched_getscheduler_args), (sy_call_t *)sys_sched_getscheduler, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 330 = sched_getscheduler */
-	{ 0, (sy_call_t *)sys_sched_yield, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 331 = sched_yield */
-	{ AS(sched_get_priority_max_args), (sy_call_t *)sys_sched_get_priority_max, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 332 = sched_get_priority_max */
-	{ AS(sched_get_priority_min_args), (sy_call_t *)sys_sched_get_priority_min, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 333 = sched_get_priority_min */
-	{ AS(sched_rr_get_interval_args), (sy_call_t *)sys_sched_rr_get_interval, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 334 = sched_rr_get_interval */
-	{ AS(utrace_args), (sy_call_t *)sys_utrace, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 335 = utrace */
-	{ compat4(AS(freebsd4_freebsd32_sendfile_args),freebsd32_sendfile), AUE_SENDFILE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 336 = freebsd4 freebsd32_sendfile */
+	{ AS(sched_setparam_args), (sy_call_t *)sys_sched_setparam, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 327 = sched_setparam */
+	{ AS(sched_getparam_args), (sy_call_t *)sys_sched_getparam, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 328 = sched_getparam */
+	{ AS(sched_setscheduler_args), (sy_call_t *)sys_sched_setscheduler, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 329 = sched_setscheduler */
+	{ AS(sched_getscheduler_args), (sy_call_t *)sys_sched_getscheduler, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 330 = sched_getscheduler */
+	{ 0, (sy_call_t *)sys_sched_yield, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 331 = sched_yield */
+	{ AS(sched_get_priority_max_args), (sy_call_t *)sys_sched_get_priority_max, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 332 = sched_get_priority_max */
+	{ AS(sched_get_priority_min_args), (sy_call_t *)sys_sched_get_priority_min, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 333 = sched_get_priority_min */
+	{ AS(sched_rr_get_interval_args), (sy_call_t *)sys_sched_rr_get_interval, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 334 = sched_rr_get_interval */
+	{ AS(utrace_args), (sy_call_t *)sys_utrace, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 335 = utrace */
+	{ compat4(AS(freebsd4_freebsd32_sendfile_args),freebsd32_sendfile), AUE_SENDFILE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 336 = freebsd4 freebsd32_sendfile */
 	{ AS(kldsym_args), (sy_call_t *)sys_kldsym, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 337 = kldsym */
 	{ AS(freebsd32_jail_args), (sy_call_t *)freebsd32_jail, AUE_JAIL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 338 = freebsd32_jail */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 339 = pioctl */
-	{ AS(sigprocmask_args), (sy_call_t *)sys_sigprocmask, AUE_SIGPROCMASK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 340 = sigprocmask */
-	{ AS(sigsuspend_args), (sy_call_t *)sys_sigsuspend, AUE_SIGSUSPEND, NULL, 0, 0, 0, SY_THR_STATIC },	/* 341 = sigsuspend */
-	{ compat4(AS(freebsd4_freebsd32_sigaction_args),freebsd32_sigaction), AUE_SIGACTION, NULL, 0, 0, 0, SY_THR_STATIC },	/* 342 = freebsd4 freebsd32_sigaction */
+	{ AS(sigprocmask_args), (sy_call_t *)sys_sigprocmask, AUE_SIGPROCMASK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 340 = sigprocmask */
+	{ AS(sigsuspend_args), (sy_call_t *)sys_sigsuspend, AUE_SIGSUSPEND, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 341 = sigsuspend */
+	{ compat4(AS(freebsd4_freebsd32_sigaction_args),freebsd32_sigaction), AUE_SIGACTION, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 342 = freebsd4 freebsd32_sigaction */
 	{ AS(sigpending_args), (sy_call_t *)sys_sigpending, AUE_SIGPENDING, NULL, 0, 0, 0, SY_THR_STATIC },	/* 343 = sigpending */
-	{ compat4(AS(freebsd4_freebsd32_sigreturn_args),freebsd32_sigreturn), AUE_SIGRETURN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 344 = freebsd4 freebsd32_sigreturn */
-	{ AS(freebsd32_sigtimedwait_args), (sy_call_t *)freebsd32_sigtimedwait, AUE_SIGWAIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 345 = freebsd32_sigtimedwait */
-	{ AS(freebsd32_sigwaitinfo_args), (sy_call_t *)freebsd32_sigwaitinfo, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 346 = freebsd32_sigwaitinfo */
+	{ compat4(AS(freebsd4_freebsd32_sigreturn_args),freebsd32_sigreturn), AUE_SIGRETURN, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 344 = freebsd4 freebsd32_sigreturn */
+	{ AS(freebsd32_sigtimedwait_args), (sy_call_t *)freebsd32_sigtimedwait, AUE_SIGWAIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 345 = freebsd32_sigtimedwait */
+	{ AS(freebsd32_sigwaitinfo_args), (sy_call_t *)freebsd32_sigwaitinfo, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 346 = freebsd32_sigwaitinfo */
 	{ AS(__acl_get_file_args), (sy_call_t *)sys___acl_get_file, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 347 = __acl_get_file */
 	{ AS(__acl_set_file_args), (sy_call_t *)sys___acl_set_file, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 348 = __acl_set_file */
-	{ AS(__acl_get_fd_args), (sy_call_t *)sys___acl_get_fd, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 349 = __acl_get_fd */
-	{ AS(__acl_set_fd_args), (sy_call_t *)sys___acl_set_fd, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 350 = __acl_set_fd */
+	{ AS(__acl_get_fd_args), (sy_call_t *)sys___acl_get_fd, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 349 = __acl_get_fd */
+	{ AS(__acl_set_fd_args), (sy_call_t *)sys___acl_set_fd, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 350 = __acl_set_fd */
 	{ AS(__acl_delete_file_args), (sy_call_t *)sys___acl_delete_file, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 351 = __acl_delete_file */
-	{ AS(__acl_delete_fd_args), (sy_call_t *)sys___acl_delete_fd, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 352 = __acl_delete_fd */
+	{ AS(__acl_delete_fd_args), (sy_call_t *)sys___acl_delete_fd, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 352 = __acl_delete_fd */
 	{ AS(__acl_aclcheck_file_args), (sy_call_t *)sys___acl_aclcheck_file, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 353 = __acl_aclcheck_file */
-	{ AS(__acl_aclcheck_fd_args), (sy_call_t *)sys___acl_aclcheck_fd, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 354 = __acl_aclcheck_fd */
+	{ AS(__acl_aclcheck_fd_args), (sy_call_t *)sys___acl_aclcheck_fd, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 354 = __acl_aclcheck_fd */
 	{ AS(extattrctl_args), (sy_call_t *)sys_extattrctl, AUE_EXTATTRCTL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 355 = extattrctl */
 	{ AS(extattr_set_file_args), (sy_call_t *)sys_extattr_set_file, AUE_EXTATTR_SET_FILE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 356 = extattr_set_file */
 	{ AS(extattr_get_file_args), (sy_call_t *)sys_extattr_get_file, AUE_EXTATTR_GET_FILE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 357 = extattr_get_file */
 	{ AS(extattr_delete_file_args), (sy_call_t *)sys_extattr_delete_file, AUE_EXTATTR_DELETE_FILE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 358 = extattr_delete_file */
-	{ AS(freebsd32_aio_waitcomplete_args), (sy_call_t *)freebsd32_aio_waitcomplete, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 359 = freebsd32_aio_waitcomplete */
-	{ AS(getresuid_args), (sy_call_t *)sys_getresuid, AUE_GETRESUID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 360 = getresuid */
-	{ AS(getresgid_args), (sy_call_t *)sys_getresgid, AUE_GETRESGID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 361 = getresgid */
-	{ 0, (sy_call_t *)sys_kqueue, AUE_KQUEUE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 362 = kqueue */
-	{ AS(freebsd32_kevent_args), (sy_call_t *)freebsd32_kevent, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 363 = freebsd32_kevent */
+	{ AS(freebsd32_aio_waitcomplete_args), (sy_call_t *)freebsd32_aio_waitcomplete, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 359 = freebsd32_aio_waitcomplete */
+	{ AS(getresuid_args), (sy_call_t *)sys_getresuid, AUE_GETRESUID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 360 = getresuid */
+	{ AS(getresgid_args), (sy_call_t *)sys_getresgid, AUE_GETRESGID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 361 = getresgid */
+	{ 0, (sy_call_t *)sys_kqueue, AUE_KQUEUE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 362 = kqueue */
+	{ AS(freebsd32_kevent_args), (sy_call_t *)freebsd32_kevent, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 363 = freebsd32_kevent */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 364 = __cap_get_proc */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 365 = __cap_set_proc */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 366 = __cap_get_fd */
@@ -424,9 +424,9 @@ struct sysent freebsd32_sysent[] = {
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 368 = __cap_set_fd */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 369 = __cap_set_file */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 370 = nosys */
-	{ AS(extattr_set_fd_args), (sy_call_t *)sys_extattr_set_fd, AUE_EXTATTR_SET_FD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 371 = extattr_set_fd */
-	{ AS(extattr_get_fd_args), (sy_call_t *)sys_extattr_get_fd, AUE_EXTATTR_GET_FD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 372 = extattr_get_fd */
-	{ AS(extattr_delete_fd_args), (sy_call_t *)sys_extattr_delete_fd, AUE_EXTATTR_DELETE_FD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 373 = extattr_delete_fd */
+	{ AS(extattr_set_fd_args), (sy_call_t *)sys_extattr_set_fd, AUE_EXTATTR_SET_FD, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 371 = extattr_set_fd */
+	{ AS(extattr_get_fd_args), (sy_call_t *)sys_extattr_get_fd, AUE_EXTATTR_GET_FD, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 372 = extattr_get_fd */
+	{ AS(extattr_delete_fd_args), (sy_call_t *)sys_extattr_delete_fd, AUE_EXTATTR_DELETE_FD, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 373 = extattr_delete_fd */
 	{ AS(__setugid_args), (sy_call_t *)sys___setugid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 374 = __setugid */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 375 = nfsclnt */
 	{ AS(eaccess_args), (sy_call_t *)sys_eaccess, AUE_EACCESS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 376 = eaccess */
@@ -445,12 +445,12 @@ struct sysent freebsd32_sysent[] = {
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 389 = __mac_set_file */
 	{ AS(kenv_args), (sy_call_t *)sys_kenv, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 390 = kenv */
 	{ AS(lchflags_args), (sy_call_t *)sys_lchflags, AUE_LCHFLAGS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 391 = lchflags */
-	{ AS(uuidgen_args), (sy_call_t *)sys_uuidgen, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 392 = uuidgen */
-	{ AS(freebsd32_sendfile_args), (sy_call_t *)freebsd32_sendfile, AUE_SENDFILE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 393 = freebsd32_sendfile */
+	{ AS(uuidgen_args), (sy_call_t *)sys_uuidgen, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 392 = uuidgen */
+	{ AS(freebsd32_sendfile_args), (sy_call_t *)freebsd32_sendfile, AUE_SENDFILE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 393 = freebsd32_sendfile */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 394 = mac_syscall */
 	{ AS(getfsstat_args), (sy_call_t *)sys_getfsstat, AUE_GETFSSTAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 395 = getfsstat */
 	{ AS(statfs_args), (sy_call_t *)sys_statfs, AUE_STATFS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 396 = statfs */
-	{ AS(fstatfs_args), (sy_call_t *)sys_fstatfs, AUE_FSTATFS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 397 = fstatfs */
+	{ AS(fstatfs_args), (sy_call_t *)sys_fstatfs, AUE_FSTATFS, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 397 = fstatfs */
 	{ AS(fhstatfs_args), (sy_call_t *)sys_fhstatfs, AUE_FHSTATFS, NULL, 0, 0, 0, SY_THR_STATIC },	/* 398 = fhstatfs */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 399 = nosys */
 	{ AS(ksem_close_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 400 = ksem_close */
@@ -469,82 +469,82 @@ struct sysent freebsd32_sysent[] = {
 	{ AS(extattr_get_link_args), (sy_call_t *)sys_extattr_get_link, AUE_EXTATTR_GET_LINK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 413 = extattr_get_link */
 	{ AS(extattr_delete_link_args), (sy_call_t *)sys_extattr_delete_link, AUE_EXTATTR_DELETE_LINK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 414 = extattr_delete_link */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 415 = __mac_execve */
-	{ AS(freebsd32_sigaction_args), (sy_call_t *)freebsd32_sigaction, AUE_SIGACTION, NULL, 0, 0, 0, SY_THR_STATIC },	/* 416 = freebsd32_sigaction */
-	{ AS(freebsd32_sigreturn_args), (sy_call_t *)freebsd32_sigreturn, AUE_SIGRETURN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 417 = freebsd32_sigreturn */
+	{ AS(freebsd32_sigaction_args), (sy_call_t *)freebsd32_sigaction, AUE_SIGACTION, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 416 = freebsd32_sigaction */
+	{ AS(freebsd32_sigreturn_args), (sy_call_t *)freebsd32_sigreturn, AUE_SIGRETURN, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 417 = freebsd32_sigreturn */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 418 = __xstat */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 419 = __xfstat */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 420 = __xlstat */
-	{ AS(freebsd32_getcontext_args), (sy_call_t *)freebsd32_getcontext, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 421 = freebsd32_getcontext */
-	{ AS(freebsd32_setcontext_args), (sy_call_t *)freebsd32_setcontext, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 422 = freebsd32_setcontext */
+	{ AS(freebsd32_getcontext_args), (sy_call_t *)freebsd32_getcontext, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 421 = freebsd32_getcontext */
+	{ AS(freebsd32_setcontext_args), (sy_call_t *)freebsd32_setcontext, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 422 = freebsd32_setcontext */
 	{ AS(freebsd32_swapcontext_args), (sy_call_t *)freebsd32_swapcontext, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 423 = freebsd32_swapcontext */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 424 = swapoff */
 	{ AS(__acl_get_link_args), (sy_call_t *)sys___acl_get_link, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 425 = __acl_get_link */
 	{ AS(__acl_set_link_args), (sy_call_t *)sys___acl_set_link, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 426 = __acl_set_link */
 	{ AS(__acl_delete_link_args), (sy_call_t *)sys___acl_delete_link, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 427 = __acl_delete_link */
 	{ AS(__acl_aclcheck_link_args), (sy_call_t *)sys___acl_aclcheck_link, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 428 = __acl_aclcheck_link */
-	{ AS(sigwait_args), (sy_call_t *)sys_sigwait, AUE_SIGWAIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 429 = sigwait */
+	{ AS(sigwait_args), (sy_call_t *)sys_sigwait, AUE_SIGWAIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 429 = sigwait */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 430 = thr_create; */
-	{ AS(thr_exit_args), (sy_call_t *)sys_thr_exit, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 431 = thr_exit */
-	{ AS(thr_self_args), (sy_call_t *)sys_thr_self, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 432 = thr_self */
-	{ AS(thr_kill_args), (sy_call_t *)sys_thr_kill, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 433 = thr_kill */
+	{ AS(thr_exit_args), (sy_call_t *)sys_thr_exit, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 431 = thr_exit */
+	{ AS(thr_self_args), (sy_call_t *)sys_thr_self, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 432 = thr_self */
+	{ AS(thr_kill_args), (sy_call_t *)sys_thr_kill, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 433 = thr_kill */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 434 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 435 = nosys */
 	{ AS(jail_attach_args), (sy_call_t *)sys_jail_attach, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 436 = jail_attach */
-	{ AS(extattr_list_fd_args), (sy_call_t *)sys_extattr_list_fd, AUE_EXTATTR_LIST_FD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 437 = extattr_list_fd */
+	{ AS(extattr_list_fd_args), (sy_call_t *)sys_extattr_list_fd, AUE_EXTATTR_LIST_FD, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 437 = extattr_list_fd */
 	{ AS(extattr_list_file_args), (sy_call_t *)sys_extattr_list_file, AUE_EXTATTR_LIST_FILE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 438 = extattr_list_file */
 	{ AS(extattr_list_link_args), (sy_call_t *)sys_extattr_list_link, AUE_EXTATTR_LIST_LINK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 439 = extattr_list_link */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 440 = kse_switchin */
 	{ AS(freebsd32_ksem_timedwait_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 441 = freebsd32_ksem_timedwait */
-	{ AS(freebsd32_thr_suspend_args), (sy_call_t *)freebsd32_thr_suspend, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 442 = freebsd32_thr_suspend */
-	{ AS(thr_wake_args), (sy_call_t *)sys_thr_wake, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 443 = thr_wake */
+	{ AS(freebsd32_thr_suspend_args), (sy_call_t *)freebsd32_thr_suspend, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 442 = freebsd32_thr_suspend */
+	{ AS(thr_wake_args), (sy_call_t *)sys_thr_wake, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 443 = thr_wake */
 	{ AS(kldunloadf_args), (sy_call_t *)sys_kldunloadf, AUE_MODUNLOAD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 444 = kldunloadf */
 	{ AS(audit_args), (sy_call_t *)sys_audit, AUE_AUDIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 445 = audit */
 	{ AS(auditon_args), (sy_call_t *)sys_auditon, AUE_AUDITON, NULL, 0, 0, 0, SY_THR_STATIC },	/* 446 = auditon */
-	{ AS(getauid_args), (sy_call_t *)sys_getauid, AUE_GETAUID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 447 = getauid */
-	{ AS(setauid_args), (sy_call_t *)sys_setauid, AUE_SETAUID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 448 = setauid */
-	{ AS(getaudit_args), (sy_call_t *)sys_getaudit, AUE_GETAUDIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 449 = getaudit */
-	{ AS(setaudit_args), (sy_call_t *)sys_setaudit, AUE_SETAUDIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 450 = setaudit */
-	{ AS(getaudit_addr_args), (sy_call_t *)sys_getaudit_addr, AUE_GETAUDIT_ADDR, NULL, 0, 0, 0, SY_THR_STATIC },	/* 451 = getaudit_addr */
-	{ AS(setaudit_addr_args), (sy_call_t *)sys_setaudit_addr, AUE_SETAUDIT_ADDR, NULL, 0, 0, 0, SY_THR_STATIC },	/* 452 = setaudit_addr */
+	{ AS(getauid_args), (sy_call_t *)sys_getauid, AUE_GETAUID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 447 = getauid */
+	{ AS(setauid_args), (sy_call_t *)sys_setauid, AUE_SETAUID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 448 = setauid */
+	{ AS(getaudit_args), (sy_call_t *)sys_getaudit, AUE_GETAUDIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 449 = getaudit */
+	{ AS(setaudit_args), (sy_call_t *)sys_setaudit, AUE_SETAUDIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 450 = setaudit */
+	{ AS(getaudit_addr_args), (sy_call_t *)sys_getaudit_addr, AUE_GETAUDIT_ADDR, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 451 = getaudit_addr */
+	{ AS(setaudit_addr_args), (sy_call_t *)sys_setaudit_addr, AUE_SETAUDIT_ADDR, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 452 = setaudit_addr */
 	{ AS(auditctl_args), (sy_call_t *)sys_auditctl, AUE_AUDITCTL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 453 = auditctl */
-	{ AS(freebsd32_umtx_op_args), (sy_call_t *)freebsd32_umtx_op, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 454 = freebsd32_umtx_op */
-	{ AS(freebsd32_thr_new_args), (sy_call_t *)freebsd32_thr_new, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 455 = freebsd32_thr_new */
-	{ AS(sigqueue_args), (sy_call_t *)sys_sigqueue, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 456 = sigqueue */
+	{ AS(freebsd32_umtx_op_args), (sy_call_t *)freebsd32_umtx_op, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 454 = freebsd32_umtx_op */
+	{ AS(freebsd32_thr_new_args), (sy_call_t *)freebsd32_thr_new, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 455 = freebsd32_thr_new */
+	{ AS(sigqueue_args), (sy_call_t *)sys_sigqueue, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 456 = sigqueue */
 	{ AS(freebsd32_kmq_open_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 457 = freebsd32_kmq_open */
-	{ AS(freebsd32_kmq_setattr_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 458 = freebsd32_kmq_setattr */
-	{ AS(freebsd32_kmq_timedreceive_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 459 = freebsd32_kmq_timedreceive */
-	{ AS(freebsd32_kmq_timedsend_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 460 = freebsd32_kmq_timedsend */
-	{ AS(freebsd32_kmq_notify_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 461 = freebsd32_kmq_notify */
+	{ AS(freebsd32_kmq_setattr_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_ABSENT },	/* 458 = freebsd32_kmq_setattr */
+	{ AS(freebsd32_kmq_timedreceive_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_ABSENT },	/* 459 = freebsd32_kmq_timedreceive */
+	{ AS(freebsd32_kmq_timedsend_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_ABSENT },	/* 460 = freebsd32_kmq_timedsend */
+	{ AS(freebsd32_kmq_notify_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_ABSENT },	/* 461 = freebsd32_kmq_notify */
 	{ AS(kmq_unlink_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 462 = kmq_unlink */
-	{ AS(abort2_args), (sy_call_t *)sys_abort2, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 463 = abort2 */
-	{ AS(thr_set_name_args), (sy_call_t *)sys_thr_set_name, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 464 = thr_set_name */
+	{ AS(abort2_args), (sy_call_t *)sys_abort2, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 463 = abort2 */
+	{ AS(thr_set_name_args), (sy_call_t *)sys_thr_set_name, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 464 = thr_set_name */
 	{ AS(freebsd32_aio_fsync_args), (sy_call_t *)freebsd32_aio_fsync, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 465 = freebsd32_aio_fsync */
-	{ AS(rtprio_thread_args), (sy_call_t *)sys_rtprio_thread, AUE_RTPRIO, NULL, 0, 0, 0, SY_THR_STATIC },	/* 466 = rtprio_thread */
+	{ AS(rtprio_thread_args), (sy_call_t *)sys_rtprio_thread, AUE_RTPRIO, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 466 = rtprio_thread */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 467 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 468 = nosys */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 469 = __getpath_fromfd */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 470 = __getpath_fromaddr */
-	{ AS(sctp_peeloff_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 471 = sctp_peeloff */
-	{ AS(sctp_generic_sendmsg_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 472 = sctp_generic_sendmsg */
-	{ AS(sctp_generic_sendmsg_iov_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 473 = sctp_generic_sendmsg_iov */
-	{ AS(sctp_generic_recvmsg_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 474 = sctp_generic_recvmsg */
+	{ AS(sctp_peeloff_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_ABSENT },	/* 471 = sctp_peeloff */
+	{ AS(sctp_generic_sendmsg_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_ABSENT },	/* 472 = sctp_generic_sendmsg */
+	{ AS(sctp_generic_sendmsg_iov_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_ABSENT },	/* 473 = sctp_generic_sendmsg_iov */
+	{ AS(sctp_generic_recvmsg_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_ABSENT },	/* 474 = sctp_generic_recvmsg */
 #ifdef PAD64_REQUIRED
-	{ AS(freebsd32_pread_args), (sy_call_t *)freebsd32_pread, AUE_PREAD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 475 = freebsd32_pread */
-	{ AS(freebsd32_pwrite_args), (sy_call_t *)freebsd32_pwrite, AUE_PWRITE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 476 = freebsd32_pwrite */
-	{ AS(freebsd32_mmap_args), (sy_call_t *)freebsd32_mmap, AUE_MMAP, NULL, 0, 0, 0, SY_THR_STATIC },	/* 477 = freebsd32_mmap */
-	{ AS(freebsd32_lseek_args), (sy_call_t *)freebsd32_lseek, AUE_LSEEK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 478 = freebsd32_lseek */
+	{ AS(freebsd32_pread_args), (sy_call_t *)freebsd32_pread, AUE_PREAD, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 475 = freebsd32_pread */
+	{ AS(freebsd32_pwrite_args), (sy_call_t *)freebsd32_pwrite, AUE_PWRITE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 476 = freebsd32_pwrite */
+	{ AS(freebsd32_mmap_args), (sy_call_t *)freebsd32_mmap, AUE_MMAP, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 477 = freebsd32_mmap */
+	{ AS(freebsd32_lseek_args), (sy_call_t *)freebsd32_lseek, AUE_LSEEK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 478 = freebsd32_lseek */
 	{ AS(freebsd32_truncate_args), (sy_call_t *)freebsd32_truncate, AUE_TRUNCATE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 479 = freebsd32_truncate */
 	{ AS(freebsd32_ftruncate_args), (sy_call_t *)freebsd32_ftruncate, AUE_FTRUNCATE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 480 = freebsd32_ftruncate */
 #else
-	{ AS(freebsd32_pread_args), (sy_call_t *)freebsd32_pread, AUE_PREAD, NULL, 0, 0, 0, SY_THR_STATIC },	/* 475 = freebsd32_pread */
-	{ AS(freebsd32_pwrite_args), (sy_call_t *)freebsd32_pwrite, AUE_PWRITE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 476 = freebsd32_pwrite */
-	{ AS(freebsd32_mmap_args), (sy_call_t *)freebsd32_mmap, AUE_MMAP, NULL, 0, 0, 0, SY_THR_STATIC },	/* 477 = freebsd32_mmap */
-	{ AS(freebsd32_lseek_args), (sy_call_t *)freebsd32_lseek, AUE_LSEEK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 478 = freebsd32_lseek */
+	{ AS(freebsd32_pread_args), (sy_call_t *)freebsd32_pread, AUE_PREAD, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 475 = freebsd32_pread */
+	{ AS(freebsd32_pwrite_args), (sy_call_t *)freebsd32_pwrite, AUE_PWRITE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 476 = freebsd32_pwrite */
+	{ AS(freebsd32_mmap_args), (sy_call_t *)freebsd32_mmap, AUE_MMAP, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 477 = freebsd32_mmap */
+	{ AS(freebsd32_lseek_args), (sy_call_t *)freebsd32_lseek, AUE_LSEEK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 478 = freebsd32_lseek */
 	{ AS(freebsd32_truncate_args), (sy_call_t *)freebsd32_truncate, AUE_TRUNCATE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 479 = freebsd32_truncate */
 	{ AS(freebsd32_ftruncate_args), (sy_call_t *)freebsd32_ftruncate, AUE_FTRUNCATE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 480 = freebsd32_ftruncate */
 #endif
 	{ AS(thr_kill2_args), (sy_call_t *)sys_thr_kill2, AUE_KILL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 481 = thr_kill2 */
-	{ AS(shm_open_args), (sy_call_t *)sys_shm_open, AUE_SHMOPEN, NULL, 0, 0, 0, SY_THR_STATIC },	/* 482 = shm_open */
+	{ AS(shm_open_args), (sy_call_t *)sys_shm_open, AUE_SHMOPEN, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 482 = shm_open */
 	{ AS(shm_unlink_args), (sy_call_t *)sys_shm_unlink, AUE_SHMUNLINK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 483 = shm_unlink */
 	{ AS(cpuset_args), (sy_call_t *)sys_cpuset, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 484 = cpuset */
 #ifdef PAD64_REQUIRED
@@ -555,40 +555,40 @@ struct sysent freebsd32_sysent[] = {
 	{ AS(freebsd32_cpuset_getid_args), (sy_call_t *)freebsd32_cpuset_getid, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 486 = freebsd32_cpuset_getid */
 	{ AS(freebsd32_cpuset_getaffinity_args), (sy_call_t *)freebsd32_cpuset_getaffinity, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 487 = freebsd32_cpuset_getaffinity */
 	{ AS(freebsd32_cpuset_setaffinity_args), (sy_call_t *)freebsd32_cpuset_setaffinity, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 488 = freebsd32_cpuset_setaffinity */
-	{ AS(faccessat_args), (sy_call_t *)sys_faccessat, AUE_FACCESSAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 489 = faccessat */
-	{ AS(fchmodat_args), (sy_call_t *)sys_fchmodat, AUE_FCHMODAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 490 = fchmodat */
-	{ AS(fchownat_args), (sy_call_t *)sys_fchownat, AUE_FCHOWNAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 491 = fchownat */
-	{ AS(freebsd32_fexecve_args), (sy_call_t *)freebsd32_fexecve, AUE_FEXECVE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 492 = freebsd32_fexecve */
-	{ AS(freebsd32_fstatat_args), (sy_call_t *)freebsd32_fstatat, AUE_FSTATAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 493 = freebsd32_fstatat */
-	{ AS(freebsd32_futimesat_args), (sy_call_t *)freebsd32_futimesat, AUE_FUTIMESAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 494 = freebsd32_futimesat */
-	{ AS(linkat_args), (sy_call_t *)sys_linkat, AUE_LINKAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 495 = linkat */
-	{ AS(mkdirat_args), (sy_call_t *)sys_mkdirat, AUE_MKDIRAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 496 = mkdirat */
-	{ AS(mkfifoat_args), (sy_call_t *)sys_mkfifoat, AUE_MKFIFOAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 497 = mkfifoat */
-	{ AS(mknodat_args), (sy_call_t *)sys_mknodat, AUE_MKNODAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 498 = mknodat */
-	{ AS(openat_args), (sy_call_t *)sys_openat, AUE_OPENAT_RWTC, NULL, 0, 0, 0, SY_THR_STATIC },	/* 499 = openat */
-	{ AS(readlinkat_args), (sy_call_t *)sys_readlinkat, AUE_READLINKAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 500 = readlinkat */
-	{ AS(renameat_args), (sy_call_t *)sys_renameat, AUE_RENAMEAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 501 = renameat */
-	{ AS(symlinkat_args), (sy_call_t *)sys_symlinkat, AUE_SYMLINKAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 502 = symlinkat */
-	{ AS(unlinkat_args), (sy_call_t *)sys_unlinkat, AUE_UNLINKAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 503 = unlinkat */
+	{ AS(faccessat_args), (sy_call_t *)sys_faccessat, AUE_FACCESSAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 489 = faccessat */
+	{ AS(fchmodat_args), (sy_call_t *)sys_fchmodat, AUE_FCHMODAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 490 = fchmodat */
+	{ AS(fchownat_args), (sy_call_t *)sys_fchownat, AUE_FCHOWNAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 491 = fchownat */
+	{ AS(freebsd32_fexecve_args), (sy_call_t *)freebsd32_fexecve, AUE_FEXECVE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 492 = freebsd32_fexecve */
+	{ AS(freebsd32_fstatat_args), (sy_call_t *)freebsd32_fstatat, AUE_FSTATAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 493 = freebsd32_fstatat */
+	{ AS(freebsd32_futimesat_args), (sy_call_t *)freebsd32_futimesat, AUE_FUTIMESAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 494 = freebsd32_futimesat */
+	{ AS(linkat_args), (sy_call_t *)sys_linkat, AUE_LINKAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 495 = linkat */
+	{ AS(mkdirat_args), (sy_call_t *)sys_mkdirat, AUE_MKDIRAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 496 = mkdirat */
+	{ AS(mkfifoat_args), (sy_call_t *)sys_mkfifoat, AUE_MKFIFOAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 497 = mkfifoat */
+	{ AS(mknodat_args), (sy_call_t *)sys_mknodat, AUE_MKNODAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 498 = mknodat */
+	{ AS(openat_args), (sy_call_t *)sys_openat, AUE_OPENAT_RWTC, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 499 = openat */
+	{ AS(readlinkat_args), (sy_call_t *)sys_readlinkat, AUE_READLINKAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 500 = readlinkat */
+	{ AS(renameat_args), (sy_call_t *)sys_renameat, AUE_RENAMEAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 501 = renameat */
+	{ AS(symlinkat_args), (sy_call_t *)sys_symlinkat, AUE_SYMLINKAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 502 = symlinkat */
+	{ AS(unlinkat_args), (sy_call_t *)sys_unlinkat, AUE_UNLINKAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 503 = unlinkat */
 	{ AS(posix_openpt_args), (sy_call_t *)sys_posix_openpt, AUE_POSIX_OPENPT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 504 = posix_openpt */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 505 = gssd_syscall */
 	{ AS(freebsd32_jail_get_args), (sy_call_t *)freebsd32_jail_get, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 506 = freebsd32_jail_get */
 	{ AS(freebsd32_jail_set_args), (sy_call_t *)freebsd32_jail_set, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 507 = freebsd32_jail_set */
 	{ AS(jail_remove_args), (sy_call_t *)sys_jail_remove, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 508 = jail_remove */
-	{ AS(closefrom_args), (sy_call_t *)sys_closefrom, AUE_CLOSEFROM, NULL, 0, 0, 0, SY_THR_STATIC },	/* 509 = closefrom */
+	{ AS(closefrom_args), (sy_call_t *)sys_closefrom, AUE_CLOSEFROM, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 509 = closefrom */
 	{ AS(freebsd32_semctl_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 510 = freebsd32_semctl */
 	{ AS(freebsd32_msgctl_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 511 = freebsd32_msgctl */
 	{ AS(freebsd32_shmctl_args), (sy_call_t *)lkmressys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },	/* 512 = freebsd32_shmctl */
 	{ AS(lpathconf_args), (sy_call_t *)sys_lpathconf, AUE_LPATHCONF, NULL, 0, 0, 0, SY_THR_STATIC },	/* 513 = lpathconf */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 514 = obsolete cap_new */
-	{ AS(__cap_rights_get_args), (sy_call_t *)sys___cap_rights_get, AUE_CAP_RIGHTS_GET, NULL, 0, 0, 0, SY_THR_STATIC },	/* 515 = __cap_rights_get */
-	{ 0, (sy_call_t *)freebsd32_cap_enter, AUE_CAP_ENTER, NULL, 0, 0, 0, SY_THR_STATIC },	/* 516 = freebsd32_cap_enter */
-	{ AS(cap_getmode_args), (sy_call_t *)sys_cap_getmode, AUE_CAP_GETMODE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 517 = cap_getmode */
-	{ AS(pdfork_args), (sy_call_t *)sys_pdfork, AUE_PDFORK, NULL, 0, 0, 0, SY_THR_STATIC },	/* 518 = pdfork */
-	{ AS(pdkill_args), (sy_call_t *)sys_pdkill, AUE_PDKILL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 519 = pdkill */
-	{ AS(pdgetpid_args), (sy_call_t *)sys_pdgetpid, AUE_PDGETPID, NULL, 0, 0, 0, SY_THR_STATIC },	/* 520 = pdgetpid */
+	{ AS(__cap_rights_get_args), (sy_call_t *)sys___cap_rights_get, AUE_CAP_RIGHTS_GET, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 515 = __cap_rights_get */
+	{ 0, (sy_call_t *)sys_cap_enter, AUE_CAP_ENTER, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 516 = cap_enter */
+	{ AS(cap_getmode_args), (sy_call_t *)sys_cap_getmode, AUE_CAP_GETMODE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 517 = cap_getmode */
+	{ AS(pdfork_args), (sy_call_t *)sys_pdfork, AUE_PDFORK, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 518 = pdfork */
+	{ AS(pdkill_args), (sy_call_t *)sys_pdkill, AUE_PDKILL, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 519 = pdkill */
+	{ AS(pdgetpid_args), (sy_call_t *)sys_pdgetpid, AUE_PDGETPID, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 520 = pdgetpid */
 	{ 0, (sy_call_t *)nosys, AUE_NULL, NULL, 0, 0, 0, SY_THR_ABSENT },			/* 521 = pdwait4 */
-	{ AS(freebsd32_pselect_args), (sy_call_t *)freebsd32_pselect, AUE_SELECT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 522 = freebsd32_pselect */
+	{ AS(freebsd32_pselect_args), (sy_call_t *)freebsd32_pselect, AUE_SELECT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 522 = freebsd32_pselect */
 	{ AS(getloginclass_args), (sy_call_t *)sys_getloginclass, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 523 = getloginclass */
 	{ AS(setloginclass_args), (sy_call_t *)sys_setloginclass, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 524 = setloginclass */
 	{ AS(rctl_get_racct_args), (sy_call_t *)sys_rctl_get_racct, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 525 = rctl_get_racct */
@@ -605,16 +605,16 @@ struct sysent freebsd32_sysent[] = {
 	{ AS(freebsd32_posix_fadvise_args), (sy_call_t *)freebsd32_posix_fadvise, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 531 = freebsd32_posix_fadvise */
 	{ AS(freebsd32_wait6_args), (sy_call_t *)freebsd32_wait6, AUE_WAIT6, NULL, 0, 0, 0, SY_THR_STATIC },	/* 532 = freebsd32_wait6 */
 #endif
-	{ AS(cap_rights_limit_args), (sy_call_t *)sys_cap_rights_limit, AUE_CAP_RIGHTS_LIMIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 533 = cap_rights_limit */
-	{ AS(freebsd32_cap_ioctls_limit_args), (sy_call_t *)freebsd32_cap_ioctls_limit, AUE_CAP_IOCTLS_LIMIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 534 = freebsd32_cap_ioctls_limit */
-	{ AS(freebsd32_cap_ioctls_get_args), (sy_call_t *)freebsd32_cap_ioctls_get, AUE_CAP_IOCTLS_GET, NULL, 0, 0, 0, SY_THR_STATIC },	/* 535 = freebsd32_cap_ioctls_get */
-	{ AS(cap_fcntls_limit_args), (sy_call_t *)sys_cap_fcntls_limit, AUE_CAP_FCNTLS_LIMIT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 536 = cap_fcntls_limit */
-	{ AS(cap_fcntls_get_args), (sy_call_t *)sys_cap_fcntls_get, AUE_CAP_FCNTLS_GET, NULL, 0, 0, 0, SY_THR_STATIC },	/* 537 = cap_fcntls_get */
-	{ AS(bindat_args), (sy_call_t *)sys_bindat, AUE_BINDAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 538 = bindat */
-	{ AS(connectat_args), (sy_call_t *)sys_connectat, AUE_CONNECTAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 539 = connectat */
-	{ AS(chflagsat_args), (sy_call_t *)sys_chflagsat, AUE_CHFLAGSAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 540 = chflagsat */
-	{ AS(accept4_args), (sy_call_t *)sys_accept4, AUE_ACCEPT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 541 = accept4 */
-	{ AS(pipe2_args), (sy_call_t *)sys_pipe2, AUE_PIPE, NULL, 0, 0, 0, SY_THR_STATIC },	/* 542 = pipe2 */
+	{ AS(cap_rights_limit_args), (sy_call_t *)sys_cap_rights_limit, AUE_CAP_RIGHTS_LIMIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 533 = cap_rights_limit */
+	{ AS(freebsd32_cap_ioctls_limit_args), (sy_call_t *)freebsd32_cap_ioctls_limit, AUE_CAP_IOCTLS_LIMIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 534 = freebsd32_cap_ioctls_limit */
+	{ AS(freebsd32_cap_ioctls_get_args), (sy_call_t *)freebsd32_cap_ioctls_get, AUE_CAP_IOCTLS_GET, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 535 = freebsd32_cap_ioctls_get */
+	{ AS(cap_fcntls_limit_args), (sy_call_t *)sys_cap_fcntls_limit, AUE_CAP_FCNTLS_LIMIT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 536 = cap_fcntls_limit */
+	{ AS(cap_fcntls_get_args), (sy_call_t *)sys_cap_fcntls_get, AUE_CAP_FCNTLS_GET, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 537 = cap_fcntls_get */
+	{ AS(bindat_args), (sy_call_t *)sys_bindat, AUE_BINDAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 538 = bindat */
+	{ AS(connectat_args), (sy_call_t *)sys_connectat, AUE_CONNECTAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 539 = connectat */
+	{ AS(chflagsat_args), (sy_call_t *)sys_chflagsat, AUE_CHFLAGSAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 540 = chflagsat */
+	{ AS(accept4_args), (sy_call_t *)sys_accept4, AUE_ACCEPT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 541 = accept4 */
+	{ AS(pipe2_args), (sy_call_t *)sys_pipe2, AUE_PIPE, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 542 = pipe2 */
 	{ AS(freebsd32_aio_mlock_args), (sy_call_t *)freebsd32_aio_mlock, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 543 = freebsd32_aio_mlock */
 #ifdef PAD64_REQUIRED
 	{ AS(freebsd32_procctl_args), (sy_call_t *)freebsd32_procctl, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 544 = freebsd32_procctl */
@@ -622,8 +622,8 @@ struct sysent freebsd32_sysent[] = {
 	{ AS(freebsd32_procctl_args), (sy_call_t *)freebsd32_procctl, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 544 = freebsd32_procctl */
 #endif
 	{ AS(freebsd32_ppoll_args), (sy_call_t *)freebsd32_ppoll, AUE_POLL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 545 = freebsd32_ppoll */
-	{ AS(freebsd32_futimens_args), (sy_call_t *)freebsd32_futimens, AUE_FUTIMES, NULL, 0, 0, 0, SY_THR_STATIC },	/* 546 = freebsd32_futimens */
-	{ AS(freebsd32_utimensat_args), (sy_call_t *)freebsd32_utimensat, AUE_FUTIMESAT, NULL, 0, 0, 0, SY_THR_STATIC },	/* 547 = freebsd32_utimensat */
+	{ AS(freebsd32_futimens_args), (sy_call_t *)freebsd32_futimens, AUE_FUTIMES, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 546 = freebsd32_futimens */
+	{ AS(freebsd32_utimensat_args), (sy_call_t *)freebsd32_utimensat, AUE_FUTIMESAT, NULL, 0, 0, SYF_CAPENABLED, SY_THR_STATIC },	/* 547 = freebsd32_utimensat */
 	{ AS(numa_getaffinity_args), (sy_call_t *)sys_numa_getaffinity, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 548 = numa_getaffinity */
 	{ AS(numa_setaffinity_args), (sy_call_t *)sys_numa_setaffinity, AUE_NULL, NULL, 0, 0, 0, SY_THR_STATIC },	/* 549 = numa_setaffinity */
 	{ AS(fdatasync_args), (sy_call_t *)sys_fdatasync, AUE_FSYNC, NULL, 0, 0, 0, SY_THR_STATIC },	/* 550 = fdatasync */
diff --git a/sys/compat/freebsd32/freebsd32_systrace_args.c b/sys/compat/freebsd32/freebsd32_systrace_args.c
index f64674bbee1f..7e3b10a950c8 100644
--- a/sys/compat/freebsd32/freebsd32_systrace_args.c
+++ b/sys/compat/freebsd32/freebsd32_systrace_args.c
@@ -2947,7 +2947,7 @@ systrace_args(int sysnum, void *params, uint64_t *uarg, int *n_args)
 		*n_args = 3;
 		break;
 	}
-	/* freebsd32_cap_enter */
+	/* cap_enter */
 	case 516: {
 		*n_args = 0;
 		break;
@@ -3350,7 +3350,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -3366,7 +3366,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -3379,7 +3379,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 5:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3408,13 +3408,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "struct rusage32 *";
+			p = "userland struct rusage32 *";
 			break;
 		default:
 			break;
@@ -3424,10 +3424,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 9:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3437,7 +3437,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 10:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3447,7 +3447,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 12:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3467,7 +3467,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 14:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3483,7 +3483,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 15:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3496,7 +3496,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 16:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3512,7 +3512,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 17:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3525,10 +3525,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 21:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
@@ -3544,7 +3544,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 22:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3595,7 +3595,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct msghdr32 *";
+			p = "userland struct msghdr32 *";
 			break;
 		case 2:
 			p = "int";
@@ -3611,7 +3611,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct msghdr32 *";
+			p = "userland struct msghdr32 *";
 			break;
 		case 2:
 			p = "int";
@@ -3655,7 +3655,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "caddr_t";
 			break;
 		case 2:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -3671,7 +3671,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "caddr_t";
 			break;
 		case 2:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -3687,7 +3687,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "caddr_t";
 			break;
 		case 2:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -3697,7 +3697,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 33:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3710,7 +3710,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 34:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "u_long";
@@ -3787,7 +3787,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 45:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
@@ -3809,7 +3809,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 49:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "u_int";
@@ -3822,7 +3822,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 50:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3832,7 +3832,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 51:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3842,10 +3842,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 53:
 		switch(ndx) {
 		case 0:
-			p = "struct sigaltstack32 *";
+			p = "userland struct sigaltstack32 *";
 			break;
 		case 1:
-			p = "struct sigaltstack32 *";
+			p = "userland struct sigaltstack32 *";
 			break;
 		default:
 			break;
@@ -3861,7 +3861,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "uint32_t";
 			break;
 		case 2:
-			p = "struct md_ioctl32 *";
+			p = "userland struct md_ioctl32 *";
 			break;
 		default:
 			break;
@@ -3881,7 +3881,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 56:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3891,10 +3891,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 57:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3904,10 +3904,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 58:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -3920,13 +3920,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 59:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		case 2:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		default:
 			break;
@@ -3946,7 +3946,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 61:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3956,7 +3956,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 65:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4005,7 +4005,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 73:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4018,7 +4018,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 74:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4034,7 +4034,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 75:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4050,13 +4050,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 78:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4069,7 +4069,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		default:
 			break;
@@ -4082,7 +4082,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		default:
 			break;
@@ -4111,10 +4111,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "struct itimerval32 *";
+			p = "userland struct itimerval32 *";
 			break;
 		case 2:
-			p = "struct itimerval32 *";
+			p = "userland struct itimerval32 *";
 			break;
 		default:
 			break;
@@ -4124,7 +4124,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 85:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4137,7 +4137,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "struct itimerval32 *";
+			p = "userland struct itimerval32 *";
 			break;
 		default:
 			break;
@@ -4182,16 +4182,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 2:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 3:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 4:
-			p = "struct timeval32 *";
+			p = "userland struct timeval32 *";
 			break;
 		default:
 			break;
@@ -4323,10 +4323,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 116:
 		switch(ndx) {
 		case 0:
-			p = "struct timeval32 *";
+			p = "userland struct timeval32 *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -4339,7 +4339,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct rusage32 *";
+			p = "userland struct rusage32 *";
 			break;
 		default:
 			break;
@@ -4361,7 +4361,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "caddr_t";
 			break;
 		case 4:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -4374,7 +4374,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec32 *";
+			p = "userland struct iovec32 *";
 			break;
 		case 2:
 			p = "u_int";
@@ -4390,7 +4390,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec32 *";
+			p = "userland struct iovec32 *";
 			break;
 		case 2:
 			p = "u_int";
@@ -4403,10 +4403,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 122:
 		switch(ndx) {
 		case 0:
-			p = "struct timeval32 *";
+			p = "userland struct timeval32 *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -4471,10 +4471,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 128:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4497,7 +4497,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 132:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -4557,7 +4557,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 3:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -4567,7 +4567,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 136:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -4580,7 +4580,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 137:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4590,10 +4590,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 138:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct timeval32 *";
+			p = "userland struct timeval32 *";
 			break;
 		default:
 			break;
@@ -4603,10 +4603,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 140:
 		switch(ndx) {
 		case 0:
-			p = "struct timeval32 *";
+			p = "userland struct timeval32 *";
 			break;
 		case 1:
-			p = "struct timeval32 *";
+			p = "userland struct timeval32 *";
 			break;
 		default:
 			break;
@@ -4619,7 +4619,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 148:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -4638,10 +4638,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 161:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct fhandle *";
+			p = "userland struct fhandle *";
 			break;
 		default:
 			break;
@@ -4654,7 +4654,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4670,7 +4670,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "pid_t";
 			break;
 		case 2:
-			p = "struct rtprio *";
+			p = "userland struct rtprio *";
 			break;
 		default:
 			break;
@@ -4746,7 +4746,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 176:
 		switch(ndx) {
 		case 0:
-			p = "struct timex *";
+			p = "userland struct timex *";
 			break;
 		default:
 			break;
@@ -4786,10 +4786,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 188:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct stat32 *";
+			p = "userland struct stat32 *";
 			break;
 		default:
 			break;
@@ -4802,7 +4802,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct stat32 *";
+			p = "userland struct stat32 *";
 			break;
 		default:
 			break;
@@ -4812,10 +4812,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 190:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct stat32 *";
+			p = "userland struct stat32 *";
 			break;
 		default:
 			break;
@@ -4825,7 +4825,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 191:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -4854,7 +4854,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		default:
 			break;
@@ -4867,7 +4867,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		default:
 			break;
@@ -4880,13 +4880,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "u_int";
 			break;
 		case 3:
-			p = "int32_t *";
+			p = "userland int32_t *";
 			break;
 		default:
 			break;
@@ -4899,19 +4899,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 202:
 		switch(ndx) {
 		case 0:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 1:
 			p = "u_int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 5:
 			p = "uint32_t";
@@ -4924,7 +4924,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 203:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4937,7 +4937,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 204:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4950,7 +4950,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 205:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4963,7 +4963,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct timeval32 *";
+			p = "userland struct timeval32 *";
 			break;
 		default:
 			break;
@@ -4983,7 +4983,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 209:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "u_int";
@@ -5048,7 +5048,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct sembuf *";
+			p = "userland struct sembuf *";
 			break;
 		case 2:
 			p = "u_int";
@@ -5077,7 +5077,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -5096,7 +5096,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -5118,7 +5118,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "int";
@@ -5131,7 +5131,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 230:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -5160,7 +5160,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct timespec32 *";
+			p = "userland struct timespec32 *";
 			break;
 		default:
 			break;
@@ -5173,7 +5173,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		default:
 			break;
@@ -5186,7 +5186,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct timespec32 *";
+			p = "userland struct timespec32 *";
 			break;
 		default:
 			break;
@@ -5199,10 +5199,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct sigevent32 *";
+			p = "userland struct sigevent32 *";
 			break;
 		case 2:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -5228,10 +5228,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const struct itimerspec32 *";
+			p = "userland const struct itimerspec32 *";
 			break;
 		case 3:
-			p = "struct itimerspec32 *";
+			p = "userland struct itimerspec32 *";
 			break;
 		default:
 			break;
@@ -5244,7 +5244,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct itimerspec32 *";
+			p = "userland struct itimerspec32 *";
 			break;
 		default:
 			break;
@@ -5264,10 +5264,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 240:
 		switch(ndx) {
 		case 0:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		case 1:
-			p = "struct timespec32 *";
+			p = "userland struct timespec32 *";
 			break;
 		default:
 			break;
@@ -5277,7 +5277,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 241:
 		switch(ndx) {
 		case 0:
-			p = "ffcounter *";
+			p = "userland ffcounter *";
 			break;
 		default:
 			break;
@@ -5287,7 +5287,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 242:
 		switch(ndx) {
 		case 0:
-			p = "struct ffclock_estimate *";
+			p = "userland struct ffclock_estimate *";
 			break;
 		default:
 			break;
@@ -5297,7 +5297,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 243:
 		switch(ndx) {
 		case 0:
-			p = "struct ffclock_estimate *";
+			p = "userland struct ffclock_estimate *";
 			break;
 		default:
 			break;
@@ -5316,7 +5316,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 3:
-			p = "clockid_t *";
+			p = "userland clockid_t *";
 			break;
 		default:
 			break;
@@ -5326,7 +5326,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 250:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -5355,7 +5355,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 254:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -5371,7 +5371,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 255:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb32 *";
+			p = "userland struct aiocb32 *";
 			break;
 		default:
 			break;
@@ -5381,7 +5381,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 256:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb32 *";
+			p = "userland struct aiocb32 *";
 			break;
 		default:
 			break;
@@ -5394,13 +5394,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct aiocb32 *const *";
+			p = "userland struct aiocb32 *const *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "struct sigevent32 *";
+			p = "userland struct sigevent32 *";
 			break;
 		default:
 			break;
@@ -5413,7 +5413,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -5426,7 +5426,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 274:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "mode_t";
@@ -5439,7 +5439,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 275:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "uid_t";
@@ -5455,10 +5455,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 276:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct timeval32 *";
+			p = "userland struct timeval32 *";
 			break;
 		default:
 			break;
@@ -5468,7 +5468,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 277:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -5484,10 +5484,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 278:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct nstat *";
+			p = "userland struct nstat *";
 			break;
 		default:
 			break;
@@ -5500,7 +5500,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct nstat *";
+			p = "userland struct nstat *";
 			break;
 		default:
 			break;
@@ -5510,10 +5510,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 280:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct nstat *";
+			p = "userland struct nstat *";
 			break;
 		default:
 			break;
@@ -5526,7 +5526,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec32 *";
+			p = "userland struct iovec32 *";
 			break;
 		case 2:
 			p = "u_int";
@@ -5548,7 +5548,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec32 *";
+			p = "userland struct iovec32 *";
 			break;
 		case 2:
 			p = "u_int";
@@ -5567,7 +5567,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 298:
 		switch(ndx) {
 		case 0:
-			p = "const struct fhandle *";
+			p = "userland const struct fhandle *";
 			break;
 		case 1:
 			p = "int";
@@ -5580,10 +5580,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 299:
 		switch(ndx) {
 		case 0:
-			p = "const struct fhandle *";
+			p = "userland const struct fhandle *";
 			break;
 		case 1:
-			p = "struct stat *";
+			p = "userland struct stat *";
 			break;
 		default:
 			break;
@@ -5606,7 +5606,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct module_stat32 *";
+			p = "userland struct module_stat32 *";
 			break;
 		default:
 			break;
@@ -5626,7 +5626,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 303:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5636,7 +5636,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 304:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5656,7 +5656,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 306:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5679,7 +5679,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct kld32_file_stat *";
+			p = "userland struct kld32_file_stat *";
 			break;
 		default:
 			break;
@@ -5741,7 +5741,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 314:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb32 *";
+			p = "userland struct aiocb32 *";
 			break;
 		default:
 			break;
@@ -5751,13 +5751,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 315:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb32 *const *";
+			p = "userland struct aiocb32 *const *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		default:
 			break;
@@ -5770,7 +5770,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct aiocb *";
+			p = "userland struct aiocb *";
 			break;
 		default:
 			break;
@@ -5780,7 +5780,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 317:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb32 *";
+			p = "userland struct aiocb32 *";
 			break;
 		default:
 			break;
@@ -5806,7 +5806,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 326:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "u_int";
@@ -5822,7 +5822,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "pid_t";
 			break;
 		case 1:
-			p = "const struct sched_param *";
+			p = "userland const struct sched_param *";
 			break;
 		default:
 			break;
@@ -5835,7 +5835,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "pid_t";
 			break;
 		case 1:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -5851,7 +5851,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const struct sched_param *";
+			p = "userland const struct sched_param *";
 			break;
 		default:
 			break;
@@ -5897,7 +5897,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "pid_t";
 			break;
 		case 1:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		default:
 			break;
@@ -5907,7 +5907,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 335:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -5926,7 +5926,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -5936,7 +5936,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 338:
 		switch(ndx) {
 		case 0:
-			p = "struct jail32 *";
+			p = "userland struct jail32 *";
 			break;
 		default:
 			break;
@@ -5949,10 +5949,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		case 2:
-			p = "sigset_t *";
+			p = "userland sigset_t *";
 			break;
 		default:
 			break;
@@ -5962,7 +5962,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 341:
 		switch(ndx) {
 		case 0:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		default:
 			break;
@@ -5972,7 +5972,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 343:
 		switch(ndx) {
 		case 0:
-			p = "sigset_t *";
+			p = "userland sigset_t *";
 			break;
 		default:
 			break;
@@ -5982,13 +5982,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 345:
 		switch(ndx) {
 		case 0:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		case 1:
-			p = "siginfo_t *";
+			p = "userland siginfo_t *";
 			break;
 		case 2:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		default:
 			break;
@@ -5998,10 +5998,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 346:
 		switch(ndx) {
 		case 0:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		case 1:
-			p = "siginfo_t *";
+			p = "userland siginfo_t *";
 			break;
 		default:
 			break;
@@ -6011,13 +6011,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 347:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6027,13 +6027,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 348:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6049,7 +6049,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6065,7 +6065,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6075,7 +6075,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 351:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
@@ -6101,13 +6101,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 353:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6123,7 +6123,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6133,19 +6133,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 355:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
 			p = "int";
 			break;
 		case 4:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6155,16 +6155,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 356:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6177,16 +6177,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 357:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6199,13 +6199,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 358:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6215,10 +6215,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 359:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb32 **";
+			p = "userland struct aiocb32 **";
 			break;
 		case 1:
-			p = "struct timespec32 *";
+			p = "userland struct timespec32 *";
 			break;
 		default:
 			break;
@@ -6228,13 +6228,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 360:
 		switch(ndx) {
 		case 0:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 1:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 2:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		default:
 			break;
@@ -6244,13 +6244,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 361:
 		switch(ndx) {
 		case 0:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 1:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 2:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		default:
 			break;
@@ -6266,19 +6266,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const struct kevent32 *";
+			p = "userland const struct kevent32 *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "struct kevent32 *";
+			p = "userland struct kevent32 *";
 			break;
 		case 4:
 			p = "int";
 			break;
 		case 5:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		default:
 			break;
@@ -6294,10 +6294,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6316,10 +6316,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6338,7 +6338,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6358,7 +6358,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 376:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -6371,7 +6371,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 378:
 		switch(ndx) {
 		case 0:
-			p = "struct iovec32 *";
+			p = "userland struct iovec32 *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -6390,10 +6390,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "int";
@@ -6406,7 +6406,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 391:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "u_long";
@@ -6419,7 +6419,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 392:
 		switch(ndx) {
 		case 0:
-			p = "struct uuid *";
+			p = "userland struct uuid *";
 			break;
 		case 1:
 			p = "int";
@@ -6447,10 +6447,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "size_t";
 			break;
 		case 5:
-			p = "struct sf_hdtr32 *";
+			p = "userland struct sf_hdtr32 *";
 			break;
 		case 6:
-			p = "off_t *";
+			p = "userland off_t *";
 			break;
 		case 7:
 			p = "int";
@@ -6463,7 +6463,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 395:
 		switch(ndx) {
 		case 0:
-			p = "struct statfs *";
+			p = "userland struct statfs *";
 			break;
 		case 1:
 			p = "long";
@@ -6479,10 +6479,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 396:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct statfs *";
+			p = "userland struct statfs *";
 			break;
 		default:
 			break;
@@ -6495,7 +6495,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct statfs *";
+			p = "userland struct statfs *";
 			break;
 		default:
 			break;
@@ -6505,10 +6505,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 398:
 		switch(ndx) {
 		case 0:
-			p = "const struct fhandle *";
+			p = "userland const struct fhandle *";
 			break;
 		case 1:
-			p = "struct statfs *";
+			p = "userland struct statfs *";
 			break;
 		default:
 			break;
@@ -6558,7 +6558,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 404:
 		switch(ndx) {
 		case 0:
-			p = "semid_t *";
+			p = "userland semid_t *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -6571,10 +6571,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 405:
 		switch(ndx) {
 		case 0:
-			p = "semid_t *";
+			p = "userland semid_t *";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "int";
@@ -6593,7 +6593,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 406:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6606,7 +6606,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "semid_t";
 			break;
 		case 1:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -6626,16 +6626,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 412:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6648,16 +6648,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 413:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6670,13 +6670,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 414:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6689,10 +6689,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct sigaction32 *";
+			p = "userland struct sigaction32 *";
 			break;
 		case 2:
-			p = "struct sigaction32 *";
+			p = "userland struct sigaction32 *";
 			break;
 		default:
 			break;
@@ -6702,7 +6702,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 417:
 		switch(ndx) {
 		case 0:
-			p = "const struct freebsd32_ucontext *";
+			p = "userland const struct freebsd32_ucontext *";
 			break;
 		default:
 			break;
@@ -6712,7 +6712,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 421:
 		switch(ndx) {
 		case 0:
-			p = "struct freebsd32_ucontext *";
+			p = "userland struct freebsd32_ucontext *";
 			break;
 		default:
 			break;
@@ -6722,7 +6722,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 422:
 		switch(ndx) {
 		case 0:
-			p = "const struct freebsd32_ucontext *";
+			p = "userland const struct freebsd32_ucontext *";
 			break;
 		default:
 			break;
@@ -6732,10 +6732,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 423:
 		switch(ndx) {
 		case 0:
-			p = "struct freebsd32_ucontext *";
+			p = "userland struct freebsd32_ucontext *";
 			break;
 		case 1:
-			p = "const struct freebsd32_ucontext *";
+			p = "userland const struct freebsd32_ucontext *";
 			break;
 		default:
 			break;
@@ -6745,13 +6745,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 425:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6761,13 +6761,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 426:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6777,7 +6777,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 427:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
@@ -6790,13 +6790,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 428:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6806,10 +6806,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 429:
 		switch(ndx) {
 		case 0:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		case 1:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -6819,7 +6819,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 431:
 		switch(ndx) {
 		case 0:
-			p = "long *";
+			p = "userland long *";
 			break;
 		default:
 			break;
@@ -6829,7 +6829,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 432:
 		switch(ndx) {
 		case 0:
-			p = "long *";
+			p = "userland long *";
 			break;
 		default:
 			break;
@@ -6868,7 +6868,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -6881,13 +6881,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 438:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -6900,13 +6900,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 439:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -6922,7 +6922,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "semid_t";
 			break;
 		case 1:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		default:
 			break;
@@ -6932,7 +6932,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 442:
 		switch(ndx) {
 		case 0:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		default:
 			break;
@@ -6965,7 +6965,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 445:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "u_int";
@@ -6981,7 +6981,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "u_int";
@@ -6994,7 +6994,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 447:
 		switch(ndx) {
 		case 0:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		default:
 			break;
@@ -7004,7 +7004,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 448:
 		switch(ndx) {
 		case 0:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		default:
 			break;
@@ -7014,7 +7014,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 449:
 		switch(ndx) {
 		case 0:
-			p = "struct auditinfo *";
+			p = "userland struct auditinfo *";
 			break;
 		default:
 			break;
@@ -7024,7 +7024,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 450:
 		switch(ndx) {
 		case 0:
-			p = "struct auditinfo *";
+			p = "userland struct auditinfo *";
 			break;
 		default:
 			break;
@@ -7034,7 +7034,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 451:
 		switch(ndx) {
 		case 0:
-			p = "struct auditinfo_addr *";
+			p = "userland struct auditinfo_addr *";
 			break;
 		case 1:
 			p = "u_int";
@@ -7047,7 +7047,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 452:
 		switch(ndx) {
 		case 0:
-			p = "struct auditinfo_addr *";
+			p = "userland struct auditinfo_addr *";
 			break;
 		case 1:
 			p = "u_int";
@@ -7060,7 +7060,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 453:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -7070,7 +7070,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 454:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "int";
@@ -7079,10 +7079,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_long";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -7092,7 +7092,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 455:
 		switch(ndx) {
 		case 0:
-			p = "struct thr_param32 *";
+			p = "userland struct thr_param32 *";
 			break;
 		case 1:
 			p = "int";
@@ -7111,7 +7111,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -7121,7 +7121,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 457:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
@@ -7130,7 +7130,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "mode_t";
 			break;
 		case 3:
-			p = "const struct mq_attr32 *";
+			p = "userland const struct mq_attr32 *";
 			break;
 		default:
 			break;
@@ -7143,10 +7143,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const struct mq_attr32 *";
+			p = "userland const struct mq_attr32 *";
 			break;
 		case 2:
-			p = "struct mq_attr32 *";
+			p = "userland struct mq_attr32 *";
 			break;
 		default:
 			break;
@@ -7159,16 +7159,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "unsigned *";
+			p = "userland unsigned *";
 			break;
 		case 4:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		default:
 			break;
@@ -7181,7 +7181,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -7190,7 +7190,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "unsigned";
 			break;
 		case 4:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		default:
 			break;
@@ -7203,7 +7203,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const struct sigevent32 *";
+			p = "userland const struct sigevent32 *";
 			break;
 		default:
 			break;
@@ -7213,7 +7213,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 462:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -7223,13 +7223,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 463:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "void **";
+			p = "userland void **";
 			break;
 		default:
 			break;
@@ -7242,7 +7242,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "long";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -7255,7 +7255,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct aiocb32 *";
+			p = "userland struct aiocb32 *";
 			break;
 		default:
 			break;
@@ -7271,7 +7271,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "lwpid_t";
 			break;
 		case 2:
-			p = "struct rtprio *";
+			p = "userland struct rtprio *";
 			break;
 		default:
 			break;
@@ -7309,7 +7309,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "__socklen_t";
 			break;
 		case 5:
-			p = "struct sctp_sndrcvinfo *";
+			p = "userland struct sctp_sndrcvinfo *";
 			break;
 		case 6:
 			p = "int";
@@ -7325,7 +7325,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "int";
@@ -7337,7 +7337,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "__socklen_t";
 			break;
 		case 5:
-			p = "struct sctp_sndrcvinfo *";
+			p = "userland struct sctp_sndrcvinfo *";
 			break;
 		case 6:
 			p = "int";
@@ -7353,22 +7353,22 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "struct sockaddr *";
+			p = "userland struct sockaddr *";
 			break;
 		case 4:
-			p = "__socklen_t *";
+			p = "userland __socklen_t *";
 			break;
 		case 5:
-			p = "struct sctp_sndrcvinfo *";
+			p = "userland struct sctp_sndrcvinfo *";
 			break;
 		case 6:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -7382,7 +7382,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -7407,7 +7407,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -7482,7 +7482,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 479:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -7524,7 +7524,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -7546,7 +7546,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -7612,7 +7612,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 479:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "uint32_t";
@@ -7661,7 +7661,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 482:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
@@ -7677,7 +7677,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 483:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -7687,7 +7687,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 484:
 		switch(ndx) {
 		case 0:
-			p = "cpusetid_t *";
+			p = "userland cpusetid_t *";
 			break;
 		default:
 			break;
@@ -7753,7 +7753,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "uint32_t";
 			break;
 		case 4:
-			p = "cpusetid_t *";
+			p = "userland cpusetid_t *";
 			break;
 		default:
 			break;
@@ -7778,7 +7778,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "size_t";
 			break;
 		case 5:
-			p = "cpuset_t *";
+			p = "userland cpuset_t *";
 			break;
 		default:
 			break;
@@ -7803,7 +7803,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "size_t";
 			break;
 		case 5:
-			p = "const cpuset_t *";
+			p = "userland const cpuset_t *";
 			break;
 		default:
 			break;
@@ -7816,7 +7816,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
@@ -7835,7 +7835,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "mode_t";
@@ -7854,7 +7854,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "uid_t";
@@ -7876,10 +7876,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		case 2:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		default:
 			break;
@@ -7892,10 +7892,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct stat *";
+			p = "userland struct stat *";
 			break;
 		case 3:
 			p = "int";
@@ -7911,10 +7911,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		default:
 			break;
@@ -7927,13 +7927,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 4:
 			p = "int";
@@ -7949,7 +7949,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "mode_t";
@@ -7965,7 +7965,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "mode_t";
@@ -7981,7 +7981,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "mode_t";
@@ -8000,7 +8000,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
@@ -8019,10 +8019,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8038,13 +8038,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -8054,13 +8054,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 502:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -8073,7 +8073,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
@@ -8096,7 +8096,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 506:
 		switch(ndx) {
 		case 0:
-			p = "struct iovec32 *";
+			p = "userland struct iovec32 *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -8112,7 +8112,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 507:
 		switch(ndx) {
 		case 0:
-			p = "struct iovec32 *";
+			p = "userland struct iovec32 *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -8157,7 +8157,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 3:
-			p = "union semun32 *";
+			p = "userland union semun32 *";
 			break;
 		default:
 			break;
@@ -8173,7 +8173,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "struct msqid_ds32 *";
+			p = "userland struct msqid_ds32 *";
 			break;
 		default:
 			break;
@@ -8189,7 +8189,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "struct shmid_ds32 *";
+			p = "userland struct shmid_ds32 *";
 			break;
 		default:
 			break;
@@ -8199,7 +8199,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 513:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -8218,20 +8218,20 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "cap_rights_t *";
+			p = "userland cap_rights_t *";
 			break;
 		default:
 			break;
 		};
 		break;
-	/* freebsd32_cap_enter */
+	/* cap_enter */
 	case 516:
 		break;
 	/* cap_getmode */
 	case 517:
 		switch(ndx) {
 		case 0:
-			p = "u_int *";
+			p = "userland u_int *";
 			break;
 		default:
 			break;
@@ -8241,7 +8241,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 518:
 		switch(ndx) {
 		case 0:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 1:
 			p = "int";
@@ -8270,7 +8270,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "pid_t *";
+			p = "userland pid_t *";
 			break;
 		default:
 			break;
@@ -8283,19 +8283,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 2:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 3:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 4:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		case 5:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		default:
 			break;
@@ -8305,7 +8305,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 523:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "size_t";
@@ -8318,7 +8318,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 524:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -8328,13 +8328,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 525:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8347,13 +8347,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 526:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8366,13 +8366,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 527:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8385,13 +8385,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 528:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8404,13 +8404,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 529:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8489,16 +8489,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "uint32_t";
 			break;
 		case 4:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 5:
 			p = "int";
 			break;
 		case 6:
-			p = "struct wrusage32 *";
+			p = "userland struct wrusage32 *";
 			break;
 		case 7:
-			p = "siginfo_t *";
+			p = "userland siginfo_t *";
 			break;
 		default:
 			break;
@@ -8565,16 +8565,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "uint32_t";
 			break;
 		case 3:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 4:
 			p = "int";
 			break;
 		case 5:
-			p = "struct wrusage32 *";
+			p = "userland struct wrusage32 *";
 			break;
 		case 6:
-			p = "siginfo_t *";
+			p = "userland siginfo_t *";
 			break;
 		default:
 			break;
@@ -8588,7 +8588,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "cap_rights_t *";
+			p = "userland cap_rights_t *";
 			break;
 		default:
 			break;
@@ -8601,7 +8601,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const uint32_t *";
+			p = "userland const uint32_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -8617,7 +8617,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		case 2:
 			p = "size_t";
@@ -8646,7 +8646,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		default:
 			break;
@@ -8697,7 +8697,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "u_long";
@@ -8716,10 +8716,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct sockaddr *";
+			p = "userland struct sockaddr *";
 			break;
 		case 2:
-			p = "__socklen_t *";
+			p = "userland __socklen_t *";
 			break;
 		case 3:
 			p = "int";
@@ -8732,7 +8732,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 542:
 		switch(ndx) {
 		case 0:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 1:
 			p = "int";
@@ -8745,7 +8745,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 543:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb32 *";
+			p = "userland struct aiocb32 *";
 			break;
 		default:
 			break;
@@ -8771,7 +8771,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 5:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -8794,7 +8794,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -8805,16 +8805,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 545:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "u_int";
 			break;
 		case 2:
-			p = "const struct timespec32 *";
+			p = "userland const struct timespec32 *";
 			break;
 		case 3:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		default:
 			break;
@@ -8827,7 +8827,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		default:
 			break;
@@ -8840,10 +8840,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		case 3:
 			p = "int";
@@ -8862,7 +8862,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "id_t";
 			break;
 		case 2:
-			p = "struct vm_domain_policy *";
+			p = "userland struct vm_domain_policy *";
 			break;
 		default:
 			break;
@@ -8878,7 +8878,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "id_t";
 			break;
 		case 2:
-			p = "const struct vm_domain_policy *";
+			p = "userland const struct vm_domain_policy *";
 			break;
 		default:
 			break;
@@ -10582,7 +10582,7 @@ systrace_return_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 		if (ndx == 0 || ndx == 1)
 			p = "int";
 		break;
-	/* freebsd32_cap_enter */
+	/* cap_enter */
 	case 516:
 	/* cap_getmode */
 	case 517:
diff --git a/sys/compat/freebsd32/syscalls.master b/sys/compat/freebsd32/syscalls.master
index db3adfd60235..72b8d1faa109 100644
--- a/sys/compat/freebsd32/syscalls.master
+++ b/sys/compat/freebsd32/syscalls.master
@@ -974,7 +974,7 @@
 514	AUE_NULL	OBSOL	cap_new
 515	AUE_CAP_RIGHTS_GET	NOPROTO	{ int __cap_rights_get(int version, \
 				    int fd, cap_rights_t *rightsp); }
-516	AUE_CAP_ENTER	STD	{ int freebsd32_cap_enter(void); }
+516	AUE_CAP_ENTER	NOPROTO	{ int cap_enter(void); }
 517	AUE_CAP_GETMODE	NOPROTO	{ int cap_getmode(u_int *modep); }
 518	AUE_PDFORK	NOPROTO	{ int pdfork(int *fdp, int flags); }
 519	AUE_PDKILL	NOPROTO	{ int pdkill(int fd, int signum); }
diff --git a/sys/compat/linux/linux_event.c b/sys/compat/linux/linux_event.c
index 3e5a15c35aa0..c2a381fde8e5 100644
--- a/sys/compat/linux/linux_event.c
+++ b/sys/compat/linux/linux_event.c
@@ -37,7 +37,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/limits.h>
 #include <sys/lock.h>
 #include <sys/mutex.h>
-#include <sys/capability.h>
+#include <sys/capsicum.h>
 #include <sys/types.h>
 #include <sys/user.h>
 #include <sys/file.h>
diff --git a/sys/compat/linux/linux_ioctl.c b/sys/compat/linux/linux_ioctl.c
index 824bcf053b5f..de5ad41aaeb0 100644
--- a/sys/compat/linux/linux_ioctl.c
+++ b/sys/compat/linux/linux_ioctl.c
@@ -297,6 +297,15 @@ linux_ioctl_disk(struct thread *td, struct linux_ioctl_args *args)
 		return (copyout(&sectorsize, (void *)args->arg,
 		    sizeof(sectorsize)));
 		break;
+	case LINUX_BLKSSZGET:
+		error = fo_ioctl(fp, DIOCGSECTORSIZE,
+		    (caddr_t)&sectorsize, td->td_ucred, td);
+		fdrop(fp, td);
+		if (error)
+			return (error);
+		return (copyout(&sectorsize, (void *)args->arg,
+		    sizeof(sectorsize)));
+		break;
 	}
 	fdrop(fp, td);
 	return (ENOIOCTL);
diff --git a/sys/compat/linux/linux_socket.c b/sys/compat/linux/linux_socket.c
index 680f3c0cb6aa..2fc4418014b7 100644
--- a/sys/compat/linux/linux_socket.c
+++ b/sys/compat/linux/linux_socket.c
@@ -855,7 +855,7 @@ linux_accept_common(struct thread *td, int s, l_uintptr_t addr,
 		if (error == EFAULT && namelen != sizeof(struct sockaddr_in))
 			return (EINVAL);
 		if (error == EINVAL) {
-			error1 = getsock_cap(td, s, &rights, &fp, NULL);
+			error1 = getsock_cap(td, s, &rights, &fp, NULL, NULL);
 			if (error1 != 0)
 				return (error1);
 			so = fp->f_data;
diff --git a/sys/conf/files b/sys/conf/files
index 17a82b77de0d..37683bd47eed 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -2226,6 +2226,7 @@ dev/oce/oce_sysctl.c		optional oce pci
 dev/oce/oce_util.c		optional oce pci
 dev/ofw/ofw_bus_if.m		optional fdt
 dev/ofw/ofw_bus_subr.c		optional fdt
+dev/ofw/ofw_cpu.c		optional fdt
 dev/ofw/ofw_fdt.c		optional fdt
 dev/ofw/ofw_if.m		optional fdt
 dev/ofw/ofw_subr.c		optional fdt
diff --git a/sys/conf/files.amd64 b/sys/conf/files.amd64
index f4c2bb7724b2..f6488257245b 100644
--- a/sys/conf/files.amd64
+++ b/sys/conf/files.amd64
@@ -134,6 +134,7 @@ amd64/amd64/cpu_switch.S	standard
 amd64/amd64/db_disasm.c		optional	ddb
 amd64/amd64/db_interface.c	optional	ddb
 amd64/amd64/db_trace.c		optional	ddb
+amd64/amd64/efirt.c		optional	efirt
 amd64/amd64/elf_machdep.c	standard
 amd64/amd64/exception.S		standard
 amd64/amd64/fpu.c		standard
diff --git a/sys/conf/files.arm b/sys/conf/files.arm
index 86ae79e96dd1..39817427352b 100644
--- a/sys/conf/files.arm
+++ b/sys/conf/files.arm
@@ -1,6 +1,19 @@
 # $FreeBSD$
+cloudabi32_vdso.o		optional	compat_cloudabi32	\
+	dependency	"$S/contrib/cloudabi/cloudabi_vdso_armv6.S" \
+	compile-with	"${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6.S -o ${.TARGET}" \
+	no-obj no-implicit-rule						\
+	clean		"cloudabi32_vdso.o"
+#
+cloudabi32_vdso_blob.o		optional	compat_cloudabi32	\
+	dependency 	"cloudabi32_vdso.o"				\
+	compile-with	"${OBJCOPY} --input-target binary --output-target elf32-littlearm --binary-architecture arm cloudabi32_vdso.o ${.TARGET}" \
+	no-implicit-rule						\
+	clean		"cloudabi32_vdso_blob.o"
+#
 arm/annapurna/alpine/alpine_ccu.c		optional al_ccu fdt
 arm/annapurna/alpine/alpine_nb_service.c	optional al_nb_service fdt
+arm/annapurna/alpine/alpine_pci.c		optional al_pci fdt
 arm/arm/autoconf.c		standard
 arm/arm/bcopy_page.S		standard
 arm/arm/bcopyinout.S		standard
@@ -85,6 +98,7 @@ arm/arm/undefined.c		standard
 arm/arm/unwind.c		optional	ddb | kdtrace_hooks
 arm/arm/vm_machdep.c		standard
 arm/arm/vfp.c			standard
+arm/cloudabi32/cloudabi32_sysvec.c	optional compat_cloudabi32
 board_id.h			standard				   \
 	dependency	"$S/arm/conf/genboardid.awk $S/arm/conf/mach-types" \
 	compile-with	"${AWK} -f $S/arm/conf/genboardid.awk $S/arm/conf/mach-types > board_id.h" \
@@ -104,7 +118,6 @@ dev/fdt/fdt_arm_platform.c	optional	platform fdt
 dev/hwpmc/hwpmc_arm.c		optional	hwpmc
 dev/hwpmc/hwpmc_armv7.c		optional	hwpmc armv6
 dev/iicbus/twsi/twsi.c		optional	twsi
-dev/ofw/ofw_cpu.c		optional	fdt
 dev/ofw/ofwpci.c		optional	fdt pci
 dev/pci/pci_host_generic.c	optional	pci_host_generic pci fdt
 dev/psci/psci.c			optional	psci
diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index bbdd4c9a4d80..332fd66b6eab 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -40,6 +40,7 @@ arm/allwinner/clk/aw_usbclk.c	optional	aw_ccu
 arm/allwinner/if_awg.c		optional	awg
 arm/annapurna/alpine/alpine_ccu.c		optional	al_ccu fdt
 arm/annapurna/alpine/alpine_nb_service.c	optional	al_nb_service fdt
+arm/annapurna/alpine/alpine_pci.c		optional	al_pci fdt
 arm/arm/generic_timer.c		standard
 arm/arm/gic.c			standard
 arm/arm/gic_fdt.c		optional	fdt
diff --git a/sys/conf/kern.mk b/sys/conf/kern.mk
index 31dae462c012..0ba4aa3d4e65 100644
--- a/sys/conf/kern.mk
+++ b/sys/conf/kern.mk
@@ -244,3 +244,23 @@ CFLAGS+=        -std=iso9899:1999
 .else # CSTD
 CFLAGS+=        -std=${CSTD}
 .endif # CSTD
+
+# Set target-specific linker emulation name. Used by ld -b binary to convert
+# binary files into ELF objects.
+LD_EMULATION_aarch64=aarch64elf
+LD_EMULATION_amd64=elf_x86_64_fbsd
+LD_EMULATION_arm=armelf_fbsd
+LD_EMULATION_armeb=armelf_fbsd
+LD_EMULATION_armv6=armelf_fbsd
+LD_EMULATION_i386=elf_i386_fbsd
+LD_EMULATION_mips= elf32btsmip_fbsd
+LD_EMULATION_mips64= elf64btsmip_fbsd
+LD_EMULATION_mipsel= elf32ltsmip_fbsd
+LD_EMULATION_mips64el= elf64ltsmip_fbsd
+LD_EMULATION_mipsn32= elf32btsmipn32_fbsd
+LD_EMULATION_mipsn32el= elf32btsmipn32_fbsd   # I don't think this is a thing that works
+LD_EMULATION_powerpc= elf32ppc_fbsd
+LD_EMULATION_powerpc64= elf64ppc_fbsd
+LD_EMULATION_riscv= elf64riscv
+LD_EMULATION_sparc64= elf64_sparc_fbsd
+LD_EMULATION=${LD_EMULATION_${MACHINE_ARCH}}
diff --git a/sys/conf/kern.post.mk b/sys/conf/kern.post.mk
index f44645c8287b..128e47d67432 100644
--- a/sys/conf/kern.post.mk
+++ b/sys/conf/kern.post.mk
@@ -165,7 +165,7 @@ ${mfile:T:S/.m$/.h/}: ${mfile}
 .endfor
 
 kernel-clean:
-	rm -f *.o *.so *.So *.ko *.s eddep errs \
+	rm -f *.o *.so *.pico *.ko *.s eddep errs \
 	    ${FULLKERNEL} ${KERNEL_KO} ${KERNEL_KO}.debug \
 	    linterrs tags vers.c \
 	    vnode_if.c vnode_if.h vnode_if_newproto.h vnode_if_typedef.h \
@@ -180,9 +180,9 @@ lint: ${LNFILES}
 # dynamic references.  We could probably do a '-Bforcedynamic' mode like
 # in the a.out ld.  For now, this works.
 HACK_EXTRA_FLAGS?= -shared
-hack.So: Makefile
+hack.pico: Makefile
 	:> hack.c
-	${CC} ${HACK_EXTRA_FLAGS} -nostdlib hack.c -o hack.So
+	${CC} ${HACK_EXTRA_FLAGS} -nostdlib hack.c -o hack.pico
 	rm -f hack.c
 
 assym.s: $S/kern/genassym.sh genassym.o
diff --git a/sys/conf/kern.pre.mk b/sys/conf/kern.pre.mk
index 6b2bd141554f..0a2d9a65ee76 100644
--- a/sys/conf/kern.pre.mk
+++ b/sys/conf/kern.pre.mk
@@ -119,7 +119,7 @@ NORMAL_M= ${AWK} -f $S/tools/makeobjops.awk ${.IMPSRC} -c ; \
 
 NORMAL_FW= uudecode -o ${.TARGET} ${.ALLSRC}
 NORMAL_FWO= ${LD} -b binary --no-warn-mismatch -d -warn-common -r \
-	-o ${.TARGET} ${.ALLSRC:M*.fw}
+	-m ${LD_EMULATION} -o ${.TARGET} ${.ALLSRC:M*.fw}
 
 # Common for dtrace / zfs
 CDDL_CFLAGS=	-DFREEBSD_NAMECACHE -nostdinc -I$S/cddl/compat/opensolaris -I$S/cddl/contrib/opensolaris/uts/common -I$S -I$S/cddl/contrib/opensolaris/common ${CFLAGS} -Wno-unknown-pragmas -Wno-missing-prototypes -Wno-undef -Wno-strict-prototypes -Wno-cast-qual -Wno-parentheses -Wno-redundant-decls -Wno-missing-braces -Wno-uninitialized -Wno-unused -Wno-inline -Wno-switch -Wno-pointer-arith -Wno-unknown-pragmas
@@ -176,7 +176,7 @@ SYSTEM_CFILES= config.c env.c hints.c vnode_if.c
 SYSTEM_DEP= Makefile ${SYSTEM_OBJS}
 SYSTEM_OBJS= locore.o ${MDOBJS} ${OBJS}
 SYSTEM_OBJS+= ${SYSTEM_CFILES:.c=.o}
-SYSTEM_OBJS+= hack.So
+SYSTEM_OBJS+= hack.pico
 
 MD_ROOT_SIZE_CONFIGURED!=	grep MD_ROOT_SIZE opt_md.h || true ; echo
 .if ${MFS_IMAGE:Uno} != "no"
diff --git a/sys/conf/kmod.mk b/sys/conf/kmod.mk
index cc9190ca99b6..5a1e611e8793 100644
--- a/sys/conf/kmod.mk
+++ b/sys/conf/kmod.mk
@@ -171,11 +171,13 @@ ${_firmw:C/\:.*$/.fwo/:T}:	${_firmw:C/\:.*$//}
 	@${ECHO} ${_firmw:C/\:.*$//} ${.ALLSRC:M*${_firmw:C/\:.*$//}}
 	@if [ -e ${_firmw:C/\:.*$//} ]; then			\
 		${LD} -b binary --no-warn-mismatch ${_LDFLAGS}	\
-		    -r -d -o ${.TARGET}	${_firmw:C/\:.*$//};	\
+		    -m ${LD_EMULATION} -r -d			\
+		    -o ${.TARGET} ${_firmw:C/\:.*$//};		\
 	else							\
 		ln -s ${.ALLSRC:M*${_firmw:C/\:.*$//}} ${_firmw:C/\:.*$//}; \
 		${LD} -b binary --no-warn-mismatch ${_LDFLAGS}	\
-		    -r -d -o ${.TARGET}	${_firmw:C/\:.*$//};	\
+		    -m ${LD_EMULATION} -r -d			\
+		    -o ${.TARGET} ${_firmw:C/\:.*$//};		\
 		rm ${_firmw:C/\:.*$//};				\
 	fi
 
diff --git a/sys/conf/options.amd64 b/sys/conf/options.amd64
index 532df6fb92f8..42349ebd6f32 100644
--- a/sys/conf/options.amd64
+++ b/sys/conf/options.amd64
@@ -64,3 +64,6 @@ XENHVM			opt_global.h
 
 # options for the Intel C600 SAS driver (isci)
 ISCI_LOGGING	opt_isci.h
+
+# EFI Runtime services support
+EFIRT			opt_efirt.h
diff --git a/sys/contrib/alpine-hal/al_hal_serdes.c b/sys/contrib/alpine-hal/al_hal_serdes_hssp.c
index d45a9438eeb4..d45a9438eeb4 100644
--- a/sys/contrib/alpine-hal/al_hal_serdes.c
+++ b/sys/contrib/alpine-hal/al_hal_serdes_hssp.c
diff --git a/sys/contrib/alpine-hal/eth/al_hal_common.h b/sys/contrib/alpine-hal/eth/al_hal_common.h
deleted file mode 100644
index 6e27e1795cb1..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_common.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_common HAL Common Layer
- * Includes all common header files used by HAL
- *  @{
- * @file   al_hal_common.h
- *
- */
-
-#ifndef __AL_HAL_COMMON_H__
-#define __AL_HAL_COMMON_H__
-
-#include "al_hal_plat_types.h"
-#include "al_hal_plat_services.h"
-
-#include "al_hal_types.h"
-#include "al_hal_reg_utils.h"
-
-/* Get the maximal value out of two typed values */
-#define al_max_t(type, x, y) ({		\
-	type __max1 = (x);			\
-	type __max2 = (y);			\
-	__max1 > __max2 ? __max1 : __max2; })
-
-/* Get the minimal value out of two typed values */
-#define al_min_t(type, x, y) ({		\
-	type __min1 = (x);			\
-	type __min2 = (y);			\
-	__min1 < __min2 ? __min1 : __min2; })
-
-/* Get the number of elements in an array */
-#define AL_ARR_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-
-/** @} end of Common group */
-#endif				/* __AL_HAL_COMMON_H__ */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_iofic.c b/sys/contrib/alpine-hal/eth/al_hal_iofic.c
deleted file mode 100644
index 28467f2e3b87..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_iofic.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_iofic.c
- *
- * @brief  interrupt controller hal
- *
- */
-
-#include "al_hal_iofic.h"
-#include "al_hal_iofic_regs.h"
-
-/*
- * configure the interrupt registers, interrupts will are kept masked
- */
-int al_iofic_config(void __iomem *regs_base, int group, uint32_t flags)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	al_reg_write32(&regs->ctrl[group].int_control_grp, flags);
-
-	return 0;
-}
-
-/*
- * configure the moderation timer resolution for a given group
- */
-int al_iofic_moder_res_config(void __iomem *regs_base, int group,
-			     uint8_t resolution)
-
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-	uint32_t reg;
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	reg = al_reg_read32(&regs->ctrl[group].int_control_grp);
-	AL_REG_FIELD_SET(reg,
-			 INT_CONTROL_GRP_MOD_RES_MASK,
-			 INT_CONTROL_GRP_MOD_RES_SHIFT,
-			 resolution);
-	al_reg_write32(&regs->ctrl[group].int_control_grp, reg);
-
-	return 0;
-}
-
-/*
- * configure the moderation timer interval for a given legacy interrupt group
- */
-int al_iofic_legacy_moder_interval_config(void __iomem *regs_base, int group,
-				     uint8_t interval)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-	uint32_t reg;
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	reg = al_reg_read32(&regs->ctrl[group].int_control_grp);
-	AL_REG_FIELD_SET(reg,
-			 INT_CONTROL_GRP_MOD_INTV_MASK,
-			 INT_CONTROL_GRP_MOD_INTV_SHIFT,
-			 interval);
-	al_reg_write32(&regs->ctrl[group].int_control_grp, reg);
-
-	return 0;
-}
-
-
-/*
- * configure the moderation timer interval for a given msix vector.
- */
-int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
-				       uint8_t vector, uint8_t interval)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-	uint32_t reg;
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	reg = al_reg_read32(&regs->grp_int_mod[group][vector].grp_int_mod_reg);
-	AL_REG_FIELD_SET(reg,
-			 INT_MOD_INTV_MASK,
-			 INT_MOD_INTV_SHIFT,
-			 interval);
-	al_reg_write32(&regs->grp_int_mod[group][vector].grp_int_mod_reg, reg);
-
-	return 0;
-}
-
-/*
- * configure the vmid attributes for a given msix vector.
- */
-int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group,
-				       uint8_t vector, uint32_t vmid, uint8_t vmid_en)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-	uint32_t reg = 0;
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	AL_REG_FIELD_SET(reg,
-			 INT_MSIX_VMID_MASK,
-			 INT_MSIX_VMID_SHIFT,
-			 vmid);
-	AL_REG_BIT_VAL_SET(reg,
-			 INT_MSIX_VMID_EN_SHIFT,
-			 vmid_en);
-
-	al_reg_write32(&regs->grp_int_mod[group][vector].grp_int_vmid_reg, reg);
-
-	return 0;
-}
-
-/*
- * return the offset of the unmask register for a given group
- */
-uint32_t __iomem * al_iofic_unmask_offset_get(void __iomem *regs_base, int group)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	return &regs->ctrl[group].int_mask_clear_grp;
-}
-
-
-/*
- * unmask specific interrupts for a given group
- */
-void al_iofic_unmask(void __iomem *regs_base, int group, uint32_t mask)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	/*
-	 * use the mask clear register, no need to read the mask register
-	 * itself. write 0 to unmask, 1 has no effect
-	 */
-	al_reg_write32_relaxed(&regs->ctrl[group].int_mask_clear_grp, ~mask);
-}
-
-/*
- * mask specific interrupts for a given group
- */
-void al_iofic_mask(void __iomem *regs_base, int group, uint32_t mask)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-	uint32_t reg;
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	reg = al_reg_read32(&regs->ctrl[group].int_mask_grp);
-
-	al_reg_write32(&regs->ctrl[group].int_mask_grp, reg | mask);
-}
-
-/*
- * read the mask for a given group
- */
-uint32_t al_iofic_read_mask(void __iomem *regs_base, int group)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	return al_reg_read32(&regs->ctrl[group].int_mask_grp);
-}
-
-/*
- * read interrupt cause register for a given group
- */
-uint32_t al_iofic_read_cause(void __iomem *regs_base, int group)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	return al_reg_read32(&regs->ctrl[group].int_cause_grp);
-}
-
-/*
- * clear bits in the interrupt cause register for a given group
- */
-void al_iofic_clear_cause(void __iomem *regs_base, int group, uint32_t mask)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	/* inverse mask, writing 1 has no effect */
-	al_reg_write32(&regs->ctrl[group].int_cause_grp, ~mask);
-}
-
-/*
- * Set the cause register for a given group
- */
-void al_iofic_set_cause(void __iomem *regs_base, int group, uint32_t mask)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	al_reg_write32(&regs->ctrl[group].int_cause_set_grp, mask);
-}
-
-
-/*
- * unmask specific interrupts from aborting the udma a given group
- */
-void al_iofic_abort_mask(void __iomem *regs_base, int group, uint32_t mask)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	al_reg_write32(&regs->ctrl[group].int_abort_msk_grp, mask);
-
-}
-
-/*
- * trigger all interrupts that are waiting for moderation timers to expire
- */
-void al_iofic_interrupt_moderation_reset(void __iomem *regs_base, int group)
-{
-	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
-	uint32_t reg = 0;
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	al_assert(regs_base);
-	al_assert(group < AL_IOFIC_MAX_GROUPS);
-
-	reg = al_reg_read32(&regs->ctrl[group].int_control_grp);
-	reg |= INT_CONTROL_GRP_MOD_RST;
-
-	al_reg_write32(&regs->ctrl[group].int_control_grp, reg);
-}
-
-/** @} end of interrupt controller group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_iofic.h b/sys/contrib/alpine-hal/eth/al_hal_iofic.h
deleted file mode 100644
index 5c19e0a12606..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_iofic.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_interrupts Common I/O Fabric Interrupt Controller
- * This HAL provides the API for programming the Common I/O Fabric Interrupt
- * Controller (IOFIC) found in most of the units attached to the I/O Fabric of
- * Alpine platform
- *  @{
- * @file   al_hal_iofic.h
- *
- * @brief Header file for the interrupt controller that's embedded in various units
- *
- */
-
-#ifndef __AL_HAL_IOFIC_H__
-#define __AL_HAL_IOFIC_H__
-
-#include <al_hal_common.h>
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#define AL_IOFIC_MAX_GROUPS	4
-
-/*
- * Configurations
- */
-
-/**
- * Configure the interrupt controller registers, actual interrupts are still
- * masked at this stage.
- *
- * @param regs_base regs pointer to interrupt controller registers
- * @param group the interrupt group.
- * @param flags flags of Interrupt Control Register
- *
- * @return 0 on success. -EINVAL otherwise.
- */
-int al_iofic_config(void __iomem *regs_base, int group,
-		   uint32_t flags);
-
-/**
- * configure the moderation timer resolution for a given group
- * Applies for both msix and legacy mode.
- *
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- * @param resolution resolution of the timer interval, the resolution determines the rate
- * of decrementing the interval timer, setting value N means that the interval
- * timer will be decremented each (N+1) * (0.68) micro seconds.
- *
- * @return 0 on success. -EINVAL otherwise.
- */
-int al_iofic_moder_res_config(void __iomem *regs_base, int group,
-			     uint8_t resolution);
-
-/**
- * configure the moderation timer interval for a given legacy interrupt group
- *
- * @param regs_base regs pointer to unit registers
- * @param group the interrupt group
- * @param interval between interrupts in resolution units. 0 disable
- *
- * @return 0 on success. -EINVAL otherwise.
- */
-int al_iofic_legacy_moder_interval_config(void __iomem *regs_base, int group,
-					 uint8_t interval);
-
-/**
- * configure the moderation timer interval for a given msix vector
- *
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- * @param vector vector index
- * @param interval interval between interrupts, 0 disable
- *
- * @return 0 on success. -EINVAL otherwise.
- */
-int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
-				       uint8_t vector, uint8_t interval);
-
-/**
-* configure the vmid attributes for a given msix vector.
-*
-* @param group the interrupt group
-* @param vector index
-* @param vmid the vmid value
-* @param vmid_en take vmid from the intc
-*
-* @return 0 on success. -EINVAL otherwise.
-*/
-int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group,
-				       uint8_t vector, uint32_t vmid, uint8_t vmid_en);
-
-/**
- * return the offset of the unmask register for a given group.
- * this function can be used when the upper layer wants to directly
- * access the unmask regiter and bypass the al_iofic_unmask() API.
- *
- * @param regs_base regs pointer to unit registers
- * @param group the interrupt group
- * @return the offset of the unmask register.
- */
-uint32_t __iomem * al_iofic_unmask_offset_get(void __iomem *regs_base, int group);
-
-/**
- * unmask specific interrupts for a given group
- * this functions guarantees atomic operations, it is performance optimized as
- * it will not require read-modify-write. The unmask done using the interrupt
- * mask clear register, so it's safe to call it while the mask is changed by
- * the HW (auto mask) or another core.
- *
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- * @param mask bitwise of interrupts to unmask, set bits will be unmasked.
- */
-void al_iofic_unmask(void __iomem *regs_base, int group, uint32_t mask);
-
-/**
- * mask specific interrupts for a given group
- * this functions modifies interrupt mask register, the callee must make sure
- * the mask is not changed by another cpu.
- *
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- * @param mask bitwise of interrupts to mask, set bits will be masked.
- */
-void al_iofic_mask(void __iomem *regs_base, int group, uint32_t mask);
-
-/**
- * read the mask register for a given group
- * this functions return the interrupt mask register
- *
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- */
-uint32_t al_iofic_read_mask(void __iomem *regs_base, int group);
-
-/**
- * read interrupt cause register for a given group
- * this will clear the set bits if the Clear on Read mode enabled.
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- */
-uint32_t al_iofic_read_cause(void __iomem *regs_base, int group);
-
-/**
- * clear bits in the interrupt cause register for a given group
- *
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- * @param mask bitwise of bits to be cleared, set bits will be cleared.
- */
-void al_iofic_clear_cause(void __iomem *regs_base, int group, uint32_t mask);
-
-/**
- * set the cause register for a given group
- * this function set the cause register. It will generate an interrupt (if
- * the the interrupt isn't masked )
- *
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- * @param mask bitwise of bits to be set.
- */
-void al_iofic_set_cause(void __iomem *regs_base, int group, uint32_t mask);
-
-/**
- * unmask specific interrupts from aborting the udma a given group
- *
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- * @param mask bitwise of interrupts to mask
- */
-void al_iofic_abort_mask(void __iomem *regs_base, int group, uint32_t mask);
-
-/**
- * trigger all interrupts that are waiting for moderation timers to expire
- *
- * @param regs_base pointer to unit registers
- * @param group the interrupt group
- */
-void al_iofic_interrupt_moderation_reset(void __iomem *regs_base, int group);
-
-#endif
-/** @} end of interrupt controller group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_iofic_regs.h b/sys/contrib/alpine-hal/eth/al_hal_iofic_regs.h
deleted file mode 100644
index 81ba20fc9676..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_iofic_regs.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*_
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-
-#ifndef __AL_HAL_IOFIC_REG_H
-#define __AL_HAL_IOFIC_REG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-struct al_iofic_grp_ctrl {
-	uint32_t int_cause_grp;         /* Interrupt Cause RegisterSet by hardware */
-	uint32_t rsrvd1;
-	uint32_t int_cause_set_grp;     /* Interrupt Cause Set RegisterWriting 1 to a bit in t ... */
-	uint32_t rsrvd2;
-	uint32_t int_mask_grp;          /* Interrupt Mask RegisterIf Auto-mask control bit =TR ... */
-	uint32_t rsrvd3;
-	uint32_t int_mask_clear_grp;    /* Interrupt Mask Clear RegisterUsed when auto-mask co ... */
-	uint32_t rsrvd4;
-	uint32_t int_status_grp;        /* Interrupt status RegisterThis register latch the st ... */
-	uint32_t rsrvd5;
-	uint32_t int_control_grp;       /* Interrupt Control Register */
-	uint32_t rsrvd6;
-	uint32_t int_abort_msk_grp;     /* Interrupt Mask RegisterEach bit in this register ma ... */
-	uint32_t rsrvd7;
-	uint32_t int_log_msk_grp;       /* Interrupt Log RegisterEach bit in this register mas ... */
-	uint32_t rsrvd8;
-};
-
-struct al_iofic_grp_mod {
-	uint32_t grp_int_mod_reg;      /* Interrupt moderation registerDedicated moderation in ... */
-	uint32_t grp_int_vmid_reg;
-};
-
-struct al_iofic_regs {
-	struct al_iofic_grp_ctrl ctrl[0];
-	uint32_t rsrvd1[0x400 >> 2];
-	struct al_iofic_grp_mod grp_int_mod[0][32];
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** int_control_grp register ****/
-/* When Clear_on_Read =1, All bits of  Cause register  ... */
-#define INT_CONTROL_GRP_CLEAR_ON_READ (1 << 0)
-/* (must be set only when MSIX is enabled)When Auto-Ma ... */
-#define INT_CONTROL_GRP_AUTO_MASK (1 << 1)
-/* Auto_Clear (RW)When Auto-Clear =1, the bits in the  ... */
-#define INT_CONTROL_GRP_AUTO_CLEAR (1 << 2)
-/* When Set_on_Posedge =1, the bits in the interrupt c ... */
-#define INT_CONTROL_GRP_SET_ON_POSEDGE (1 << 3)
-/* When Moderation_Reset =1, all Moderation timers ass ... */
-#define INT_CONTROL_GRP_MOD_RST (1 << 4)
-/* When mask_msi_x =1, No MSI-X from this group is sen ... */
-#define INT_CONTROL_GRP_MASK_MSI_X (1 << 5)
-/* MSI-X AWID value, same ID for all cause bits */
-#define INT_CONTROL_GRP_AWID_MASK 0x00000F00
-#define INT_CONTROL_GRP_AWID_SHIFT 8
-/* This value determines the interval between interrup ... */
-#define INT_CONTROL_GRP_MOD_INTV_MASK 0x00FF0000
-#define INT_CONTROL_GRP_MOD_INTV_SHIFT 16
-/* This value determines the Moderation_Timer_Clock sp ... */
-#define INT_CONTROL_GRP_MOD_RES_MASK 0x0F000000
-#define INT_CONTROL_GRP_MOD_RES_SHIFT 24
-
-/**** grp_int_mod_reg register ****/
-/* Interrupt Moderation Interval registerDedicated reg ... */
-#define INT_MOD_INTV_MASK 0x000000FF
-#define INT_MOD_INTV_SHIFT 0
-
-/**** grp_int_vmid_reg register ****/
-/* Interrupt vmid value registerDedicated reg ... */
-#define INT_MSIX_VMID_MASK 0x0000FFFF
-#define INT_MSIX_VMID_SHIFT 0
-/* Interrupt vmid_en value registerDedicated reg ... */
-#define INT_MSIX_VMID_EN_SHIFT 31
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_IOFIC_REG_H */
-
-
-
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_nb_regs.h b/sys/contrib/alpine-hal/eth/al_hal_nb_regs.h
deleted file mode 100644
index 9de3bd246865..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_nb_regs.h
+++ /dev/null
@@ -1,1823 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_nb_regs.h
- *
- * @brief North Bridge service registers
- *
- */
-
-#ifndef __AL_HAL_NB_REGS_H__
-#define __AL_HAL_NB_REGS_H__
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-
-
-struct al_nb_global {
-	/* [0x0]  */
-	uint32_t cpus_config;
-	/* [0x4]  */
-	uint32_t cpus_secure;
-	/* [0x8] Force init reset. */
-	uint32_t cpus_init_control;
-	/* [0xc] Force init reset per DECEI mode. */
-	uint32_t cpus_init_status;
-	/* [0x10]  */
-	uint32_t nb_int_cause;
-	/* [0x14]  */
-	uint32_t sev_int_cause;
-	/* [0x18]  */
-	uint32_t pmus_int_cause;
-	/* [0x1c]  */
-	uint32_t sev_mask;
-	/* [0x20]  */
-	uint32_t cpus_hold_reset;
-	/* [0x24]  */
-	uint32_t cpus_software_reset;
-	/* [0x28]  */
-	uint32_t wd_timer0_reset;
-	/* [0x2c]  */
-	uint32_t wd_timer1_reset;
-	/* [0x30]  */
-	uint32_t wd_timer2_reset;
-	/* [0x34]  */
-	uint32_t wd_timer3_reset;
-	/* [0x38]  */
-	uint32_t ddrc_hold_reset;
-	/* [0x3c]  */
-	uint32_t fabric_software_reset;
-	/* [0x40]  */
-	uint32_t cpus_power_ctrl;
-	uint32_t rsrvd_0[7];
-	/* [0x60]  */
-	uint32_t acf_base_high;
-	/* [0x64]  */
-	uint32_t acf_base_low;
-	/* [0x68]  */
-	uint32_t acf_control_override;
-	/* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address  */
-	uint32_t lgic_base_high;
-	/* [0x70] Read-only that reflects CPU Cluster Local GIC base low address   */
-	uint32_t lgic_base_low;
-	/* [0x74] Read-only that reflects the device's IOGIC base high address.  */
-	uint32_t iogic_base_high;
-	/* [0x78] Read-only that reflects IOGIC base low address  */
-	uint32_t iogic_base_low;
-	/* [0x7c]  */
-	uint32_t io_wr_split_control;
-	/* [0x80]  */
-	uint32_t io_rd_rob_control;
-	/* [0x84]  */
-	uint32_t sb_pos_error_log_1;
-	/* [0x88]  */
-	uint32_t sb_pos_error_log_0;
-	/* [0x8c]  */
-	uint32_t c2swb_config;
-	/* [0x90]  */
-	uint32_t msix_error_log;
-	/* [0x94]  */
-	uint32_t error_cause;
-	/* [0x98]  */
-	uint32_t error_mask;
-	uint32_t rsrvd_1;
-	/* [0xa0]  */
-	uint32_t qos_peak_control;
-	/* [0xa4]  */
-	uint32_t qos_set_control;
-	/* [0xa8]  */
-	uint32_t ddr_qos;
-	uint32_t rsrvd_2[9];
-	/* [0xd0]  */
-	uint32_t acf_misc;
-	/* [0xd4]  */
-	uint32_t config_bus_control;
-	uint32_t rsrvd_3[2];
-	/* [0xe0]  */
-	uint32_t pos_id_match;
-	uint32_t rsrvd_4[3];
-	/* [0xf0]  */
-	uint32_t sb_sel_override_awuser;
-	/* [0xf4]  */
-	uint32_t sb_override_awuser;
-	/* [0xf8]  */
-	uint32_t sb_sel_override_aruser;
-	/* [0xfc]  */
-	uint32_t sb_override_aruser;
-	/* [0x100]  */
-	uint32_t cpu_max_pd_timer;
-	/* [0x104]  */
-	uint32_t cpu_max_pu_timer;
-	uint32_t rsrvd_5[2];
-	/* [0x110]  */
-	uint32_t auto_ddr_self_refresh_counter;
-	uint32_t rsrvd_6[3];
-	/* [0x120]  */
-	uint32_t coresight_pd;
-	/* [0x124]  */
-	uint32_t coresight_internal_0;
-	/* [0x128]  */
-	uint32_t coresight_dbgromaddr;
-	/* [0x12c]  */
-	uint32_t coresight_dbgselfaddr;
-	/* [0x130]  */
-	uint32_t coresght_targetid;
-	/* [0x134]  */
-	uint32_t coresght_targetid0;
-	uint32_t rsrvd_7[10];
-	/* [0x160]  */
-	uint32_t sb_force_same_id_cfg_0;
-	/* [0x164]  */
-	uint32_t sb_mstr_force_same_id_sel_0;
-	/* [0x168]  */
-	uint32_t sb_force_same_id_cfg_1;
-	/* [0x16c]  */
-	uint32_t sb_mstr_force_same_id_sel_1;
-	uint32_t rsrvd[932];
-};
-struct al_nb_system_counter {
-	/* [0x0]  */
-	uint32_t cnt_control;
-	/* [0x4]  */
-	uint32_t cnt_base_freq;
-	/* [0x8]  */
-	uint32_t cnt_low;
-	/* [0xc]  */
-	uint32_t cnt_high;
-	/* [0x10]  */
-	uint32_t cnt_init_low;
-	/* [0x14]  */
-	uint32_t cnt_init_high;
-	uint32_t rsrvd[58];
-};
-struct al_nb_rams_control_misc {
-	/* [0x0]  */
-	uint32_t ca15_rf_misc;
-	uint32_t rsrvd_0;
-	/* [0x8]  */
-	uint32_t nb_rf_misc;
-	uint32_t rsrvd[61];
-};
-struct al_nb_ca15_rams_control {
-	/* [0x0]  */
-	uint32_t rf_0;
-	/* [0x4]  */
-	uint32_t rf_1;
-	/* [0x8]  */
-	uint32_t rf_2;
-	uint32_t rsrvd;
-};
-struct al_nb_semaphores {
-	/* [0x0] This configuration is only sampled during reset of the processor */
-	uint32_t lockn;
-};
-struct al_nb_debug {
-	/* [0x0]  */
-	uint32_t ca15_outputs_1;
-	/* [0x4]  */
-	uint32_t ca15_outputs_2;
-	uint32_t rsrvd_0[2];
-	/* [0x10]  */
-	uint32_t cpu_msg[4];
-	/* [0x20]  */
-	uint32_t rsv0_config;
-	/* [0x24]  */
-	uint32_t rsv1_config;
-	uint32_t rsrvd_1[2];
-	/* [0x30]  */
-	uint32_t rsv0_status;
-	/* [0x34]  */
-	uint32_t rsv1_status;
-	uint32_t rsrvd_2[2];
-	/* [0x40]  */
-	uint32_t ddrc;
-	/* [0x44]  */
-	uint32_t ddrc_phy_smode_control;
-	/* [0x48]  */
-	uint32_t ddrc_phy_smode_status;
-	uint32_t rsrvd_3[5];
-	/* [0x60]  */
-	uint32_t pmc;
-	uint32_t rsrvd_4[3];
-	/* [0x70]  */
-	uint32_t cpus_general;
-	/* [0x74]  */
-	uint32_t cpus_general_1;
-	uint32_t rsrvd_5[2];
-	/* [0x80]  */
-	uint32_t cpus_int_out;
-	uint32_t rsrvd_6[3];
-	/* [0x90]  */
-	uint32_t latch_pc_req;
-	uint32_t rsrvd_7;
-	/* [0x98]  */
-	uint32_t latch_pc_low;
-	/* [0x9c]  */
-	uint32_t latch_pc_high;
-	uint32_t rsrvd_8[24];
-	/* [0x100]  */
-	uint32_t track_dump_ctrl;
-	/* [0x104]  */
-	uint32_t track_dump_rdata_0;
-	/* [0x108]  */
-	uint32_t track_dump_rdata_1;
-	uint32_t rsrvd_9[5];
-	/* [0x120]  */
-	uint32_t track_events;
-	uint32_t rsrvd_10[3];
-	/* [0x130]  */
-	uint32_t pos_track_dump_ctrl;
-	/* [0x134]  */
-	uint32_t pos_track_dump_rdata_0;
-	/* [0x138]  */
-	uint32_t pos_track_dump_rdata_1;
-	uint32_t rsrvd_11;
-	/* [0x140]  */
-	uint32_t c2swb_track_dump_ctrl;
-	/* [0x144]  */
-	uint32_t c2swb_track_dump_rdata_0;
-	/* [0x148]  */
-	uint32_t c2swb_track_dump_rdata_1;
-	uint32_t rsrvd_12;
-	/* [0x150]  */
-	uint32_t cpus_track_dump_ctrl;
-	/* [0x154]  */
-	uint32_t cpus_track_dump_rdata_0;
-	/* [0x158]  */
-	uint32_t cpus_track_dump_rdata_1;
-	uint32_t rsrvd_13;
-	/* [0x160]  */
-	uint32_t c2swb_bar_ovrd_high;
-	/* [0x164]  */
-	uint32_t c2swb_bar_ovrd_low;
-	uint32_t rsrvd[38];
-};
-struct al_nb_cpun_config_status {
-	/* [0x0] This configuration is only sampled during reset of the processor. */
-	uint32_t config;
-	/* [0x4] This configuration is only sampled during reset of the processor. */
-	uint32_t config_aarch64;
-	/* [0x8]  */
-	uint32_t local_cause_mask;
-	uint32_t rsrvd_0;
-	/* [0x10]  */
-	uint32_t pmus_cause_mask;
-	/* [0x14]  */
-	uint32_t sei_cause_mask;
-	uint32_t rsrvd_1[2];
-	/* [0x20] Specifies the state of the CPU with reference to power modes. */
-	uint32_t power_ctrl;
-	/* [0x24]  */
-	uint32_t power_status;
-	/* [0x28]  */
-	uint32_t resume_addr_l;
-	/* [0x2c]  */
-	uint32_t resume_addr_h;
-	uint32_t rsrvd_2[4];
-	/* [0x40]  */
-	uint32_t warm_rst_ctl;
-	uint32_t rsrvd_3;
-	/* [0x48]  */
-	uint32_t rvbar_low;
-	/* [0x4c]  */
-	uint32_t rvbar_high;
-	/* [0x50]  */
-	uint32_t pmu_snapshot;
-	uint32_t rsrvd_4[3];
-	/* [0x60]  */
-	uint32_t cpu_msg_in;
-	uint32_t rsrvd[39];
-};
-struct al_nb_mc_pmu {
-	/* [0x0] PMU Global Control Register */
-	uint32_t pmu_control;
-	/* [0x4] PMU Global Control Register */
-	uint32_t overflow;
-	uint32_t rsrvd[62];
-};
-struct al_nb_mc_pmu_counters {
-	/* [0x0] Counter Configuration Register */
-	uint32_t cfg;
-	/* [0x4] Counter Control Register */
-	uint32_t cntl;
-	/* [0x8] Counter Control Register */
-	uint32_t low;
-	/* [0xc] Counter Control Register */
-	uint32_t high;
-	uint32_t rsrvd[4];
-};
-struct al_nb_nb_version {
-	/* [0x0] Northbridge Revision */
-	uint32_t version;
-	uint32_t rsrvd;
-};
-struct al_nb_sriov {
-	/* [0x0]  */
-	uint32_t cpu_vmid[4];
-	uint32_t rsrvd[4];
-};
-struct al_nb_dram_channels {
-	/* [0x0]  */
-	uint32_t dram_0_control;
-	uint32_t rsrvd_0;
-	/* [0x8]  */
-	uint32_t dram_0_status;
-	uint32_t rsrvd_1;
-	/* [0x10]  */
-	uint32_t ddr_int_cause;
-	uint32_t rsrvd_2;
-	/* [0x18]  */
-	uint32_t ddr_cause_mask;
-	uint32_t rsrvd_3;
-	/* [0x20]  */
-	uint32_t address_map;
-	uint32_t rsrvd_4[3];
-	/* [0x30]  */
-	uint32_t reorder_id_mask_0;
-	/* [0x34]  */
-	uint32_t reorder_id_value_0;
-	/* [0x38]  */
-	uint32_t reorder_id_mask_1;
-	/* [0x3c]  */
-	uint32_t reorder_id_value_1;
-	/* [0x40]  */
-	uint32_t reorder_id_mask_2;
-	/* [0x44]  */
-	uint32_t reorder_id_value_2;
-	/* [0x48]  */
-	uint32_t reorder_id_mask_3;
-	/* [0x4c]  */
-	uint32_t reorder_id_value_3;
-	/* [0x50]  */
-	uint32_t mrr_control_status;
-	uint32_t rsrvd[43];
-};
-struct al_nb_ddr_0_mrr {
-	/* [0x0] Counter Configuration Register */
-	uint32_t val;
-};
-struct al_nb_push_packet {
-	/* [0x0]  */
-	uint32_t pp_config;
-	uint32_t rsrvd_0[3];
-	/* [0x10]  */
-	uint32_t pp_ext_awuser;
-	uint32_t rsrvd_1[3];
-	/* [0x20]  */
-	uint32_t pp_base_low;
-	/* [0x24]  */
-	uint32_t pp_base_high;
-	uint32_t rsrvd_2[2];
-	/* [0x30]  */
-	uint32_t pp_sel_awuser;
-	uint32_t rsrvd[51];
-};
-
-struct al_nb_regs {
-	struct al_nb_global global;                             /* [0x0] */
-	struct al_nb_system_counter system_counter;             /* [0x1000] */
-	struct al_nb_rams_control_misc rams_control_misc;       /* [0x1100] */
-	struct al_nb_ca15_rams_control ca15_rams_control[5];    /* [0x1200] */
-	uint32_t rsrvd_0[108];
-	struct al_nb_semaphores semaphores[64];                 /* [0x1400] */
-	uint32_t rsrvd_1[320];
-	struct al_nb_debug debug;                               /* [0x1a00] */
-	uint32_t rsrvd_2[256];
-	struct al_nb_cpun_config_status cpun_config_status[4];  /* [0x2000] */
-	uint32_t rsrvd_3[1792];
-	struct al_nb_mc_pmu mc_pmu;                             /* [0x4000] */
-	struct al_nb_mc_pmu_counters mc_pmu_counters[4];        /* [0x4100] */
-	uint32_t rsrvd_4[160];
-	struct al_nb_nb_version nb_version;                     /* [0x4400] */
-	uint32_t rsrvd_5[126];
-	struct al_nb_sriov sriov;                               /* [0x4600] */
-	uint32_t rsrvd_6[120];
-	struct al_nb_dram_channels dram_channels;               /* [0x4800] */
-	struct al_nb_ddr_0_mrr ddr_0_mrr[9];                    /* [0x4900] */
-	uint32_t rsrvd_7[439];
-	uint32_t rsrvd_8[1024];					/* [0x5000] */
-	struct al_nb_push_packet push_packet;                   /* [0x6000] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** CPUs_Config register ****/
-/* Disable broadcast of barrier onto system bus.
-Connect to Processor Cluster SYSBARDISABLE. */
-#define NB_GLOBAL_CPUS_CONFIG_SYSBARDISABLE (1 << 0)
-/* Enable broadcast of inner shareable transactions from CPUs.
-Connect to Processor Cluster BROADCASTINNER. */
-#define NB_GLOBAL_CPUS_CONFIG_BROADCASTINNER (1 << 1)
-/* Disable broadcast of cache maintenance system bus.
-Connect to Processor Cluster BROADCASTCACHEMAIN */
-#define NB_GLOBAL_CPUS_CONFIG_BROADCASTCACHEMAINT (1 << 2)
-/* Enable broadcast of outer shareable transactions from CPUs.
-Connect to Processor Cluster  BROADCASTOUTER. */
-#define NB_GLOBAL_CPUS_CONFIG_BROADCASTOUTER (1 << 3)
-/* Defines the internal CPU GIC operating frequency ratio with the main CPU clock.
-0x0: 1:1
-0x1: 1:2
-0x2: 1:3
-0x3: 1:4
-
-Note: This is not in used with CA57 */
-#define NB_GLOBAL_CPUS_CONFIG_PERIPHCLKEN_MASK 0x00000030
-#define NB_GLOBAL_CPUS_CONFIG_PERIPHCLKEN_SHIFT 4
-/* Disables the GIC CPU interface logic and routes the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ
-signals directly to the processor:
-0 Enable the GIC CPU interface logic.
-1 Disable the GIC CPU interface logic.
-The processor only samples this signal as it exits reset. */
-#define NB_GLOBAL_CPUS_CONFIG_GIC_DISABLE (1 << 6)
-/* Disable L1 data cache and L2 snoop tag RAMs automatic invalidate on reset functionality  */
-#define NB_GLOBAL_CPUS_CONFIG_DBG_L1_RESET_DISABLE (1 << 7)
-/* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
-Register (MPIDR).
-This signal is only sampled during reset of the processor. */
-#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF1_MASK 0x00FF0000
-#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF1_SHIFT 16
-/* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
-Register (MPIDR).
-This signal is only sampled during reset of the processor.. */
-#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF2_MASK 0xFF000000
-#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF2_SHIFT 24
-
-/**** CPUs_Secure register ****/
-/* DBGEN
- */
-#define NB_GLOBAL_CPUS_SECURE_DBGEN      (1 << 0)
-/* NIDEN
- */
-#define NB_GLOBAL_CPUS_SECURE_NIDEN      (1 << 1)
-/* SPIDEN
- */
-#define NB_GLOBAL_CPUS_SECURE_SPIDEN     (1 << 2)
-/* SPNIDEN
- */
-#define NB_GLOBAL_CPUS_SECURE_SPNIDEN    (1 << 3)
-/* Disable write access to some secure GIC registers */
-#define NB_GLOBAL_CPUS_SECURE_CFGSDISABLE (1 << 4)
-/* Disable write access to some secure IOGIC registers */
-#define NB_GLOBAL_CPUS_SECURE_IOGIC_CFGSDISABLE (1 << 5)
-
-/**** CPUs_Init_Control register ****/
-/* CPU Init Done
-Specifies which CPUs' inits are done and can exit poreset.
-By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other CPUs.
-If this bit is cleared for a specific CPU, setting it by primary CPU as part of the initialization process will initiate power-on-reset to this specific CPU. */
-#define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_MASK 0x0000000F
-#define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_SHIFT 0
-/* DBGPWRDNREQ Mask
-When CPU does not exist, its DBGPWRDNREQ must be asserted.
-If corresponding mask bit is set, the DBGPWDNREQ is deasserted. */
-#define NB_GLOBAL_CPUS_INIT_CONTROL_DBGPWRDNREQ_MASK_MASK 0x000000F0
-#define NB_GLOBAL_CPUS_INIT_CONTROL_DBGPWRDNREQ_MASK_SHIFT 4
-/* Force CPU init power-on-reset exit.
-For debug purposes only. */
-#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_CPUPOR_MASK 0x00000F00
-#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_CPUPOR_SHIFT 8
-/* Force dbgpwrdup signal high
-If dbgpwrdup is clear on the processor interface it indicates that the process debug resources are not available for APB access. */
-#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_DBGPWRDUP_MASK 0x0000F000
-#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_DBGPWRDUP_SHIFT 12
-
-/**** CPUs_Init_Status register ****/
-/* Specifies which CPUs are enabled in the device configuration.
-sample at rst_cpus_exist[3:0] reset strap. */
-#define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_MASK 0x0000000F
-#define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_SHIFT 0
-
-/**** NB_Int_Cause register ****/
-/*
- * Each bit corresponds to an IRQ.
- * value is 1 for level irq, 0 for trigger irq
- * Level IRQ indices: 12-13, 23, 24, 26-29
- */
-#define NB_GLOBAL_NB_INT_CAUSE_LEVEL_IRQ_MASK	0x3D803000
-/* Cross trigger interrupt  */
-#define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_MASK 0x0000000F
-#define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_SHIFT 0
-/* Communications channel receive. Receive portion of Data Transfer Register full flag */
-#define NB_GLOBAL_NB_INT_CAUSE_COMMRX_MASK 0x000000F0
-#define NB_GLOBAL_NB_INT_CAUSE_COMMRX_SHIFT 4
-/* Communication channel transmit. Transmit portion of Data Transfer Register empty flag. */
-#define NB_GLOBAL_NB_INT_CAUSE_COMMTX_MASK 0x00000F00
-#define NB_GLOBAL_NB_INT_CAUSE_COMMTX_SHIFT 8
-/* Reserved, read undefined must write as zeros. */
-#define NB_GLOBAL_NB_INT_CAUSE_RESERVED_15_15 (1 << 15)
-/* Error indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of the L2ECTLR clears the error indicator connected to CA15 nAXIERRIRQ. */
-#define NB_GLOBAL_NB_INT_CAUSE_CPU_AXIERRIRQ (1 << 16)
-/* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */
-#define NB_GLOBAL_NB_INT_CAUSE_CPU_INTERRIRQ (1 << 17)
-/* Coherent fabric error summary interrupt */
-#define NB_GLOBAL_NB_INT_CAUSE_ACF_ERRORIRQ (1 << 18)
-/* DDR Controller ECC Correctable error summary interrupt */
-#define NB_GLOBAL_NB_INT_CAUSE_MCTL_ECC_CORR_ERR (1 << 19)
-/* DDR Controller ECC Uncorrectable error summary interrupt */
-#define NB_GLOBAL_NB_INT_CAUSE_MCTL_ECC_UNCORR_ERR (1 << 20)
-/* DRAM parity error interrupt */
-#define NB_GLOBAL_NB_INT_CAUSE_MCTL_PARITY_ERR (1 << 21)
-/* Reserved, not functional */
-#define NB_GLOBAL_NB_INT_CAUSE_MCTL_WDATARAM_PAR (1 << 22)
-/* Error cause summary interrupt */
-#define NB_GLOBAL_NB_INT_CAUSE_ERR_CAUSE_SUM_A0 (1 << 23)
-/* SB PoS error */
-#define NB_GLOBAL_NB_INT_CAUSE_SB_POS_ERR (1 << 24)
-/* Received msix is not mapped to local GIC or IO-GIC spin */
-#define NB_GLOBAL_NB_INT_CAUSE_MSIX_ERR_INT_M0 (1 << 25)
-/* Coresight timestamp overflow */
-#define NB_GLOBAL_NB_INT_CAUSE_CORESIGHT_TS_OVERFLOW_M0 (1 << 26)
-
-/**** SEV_Int_Cause register ****/
-/* SMMU 0/1 global non-secure fault interrupt */
-#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_GBL_FLT_IRPT_NS_MASK 0x00000003
-#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_GBL_FLT_IRPT_NS_SHIFT 0
-/* SMMU 0/1 non-secure context interrupt */
-#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CXT_IRPT_NS_MASK 0x0000000C
-#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CXT_IRPT_NS_SHIFT 2
-/* SMMU0/1 Non-secure configuration access fault interrupt */
-#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CFG_FLT_IRPT_S_MASK 0x00000030
-#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CFG_FLT_IRPT_S_SHIFT 4
-/* Reserved. Read undefined; must write as zeros. */
-#define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_11_6_MASK 0x00000FC0
-#define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_11_6_SHIFT 6
-/* Reserved. Read undefined; must write as zeros. */
-#define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_31_20_MASK 0xFFF00000
-#define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_31_20_SHIFT 20
-
-/**** PMUs_Int_Cause register ****/
-/* CPUs PMU Overflow interrupt */
-#define NB_GLOBAL_PMUS_INT_CAUSE_CPUS_OVFL_MASK 0x0000000F
-#define NB_GLOBAL_PMUS_INT_CAUSE_CPUS_OVFL_SHIFT 0
-/* Northbridge PMU overflow */
-#define NB_GLOBAL_PMUS_INT_CAUSE_NB_OVFL (1 << 4)
-/* Memory Controller PMU overflow */
-#define NB_GLOBAL_PMUS_INT_CAUSE_MCTL_OVFL (1 << 5)
-/* Coherency Interconnect PMU overflow */
-#define NB_GLOBAL_PMUS_INT_CAUSE_CCI_OVFL_MASK 0x000007C0
-#define NB_GLOBAL_PMUS_INT_CAUSE_CCI_OVFL_SHIFT 6
-/* Coherency Interconnect PMU overflow */
-#define NB_GLOBAL_PMUS_INT_CAUSE_SMMU_OVFL_MASK 0x00001800
-#define NB_GLOBAL_PMUS_INT_CAUSE_SMMU_OVFL_SHIFT 11
-/* Reserved. Read undefined; must write as zeros. */
-#define NB_GLOBAL_PMUS_INT_CAUSE_RESERVED_23_13_MASK 0x00FFE000
-#define NB_GLOBAL_PMUS_INT_CAUSE_RESERVED_23_13_SHIFT 13
-/* Southbridge PMUs overflow */
-#define NB_GLOBAL_PMUS_INT_CAUSE_SB_PMUS_OVFL_MASK 0xFF000000
-#define NB_GLOBAL_PMUS_INT_CAUSE_SB_PMUS_OVFL_SHIFT 24
-
-/**** CPUs_Hold_Reset register ****/
-/* Shared L2 memory system, interrupt controller and timer logic reset.
-Reset is applied only when all processors are in STNDBYWFI state. */
-#define NB_GLOBAL_CPUS_HOLD_RESET_L2RESET (1 << 0)
-/* Shared debug domain reset */
-#define NB_GLOBAL_CPUS_HOLD_RESET_PRESETDBG (1 << 1)
-/* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
-#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_DBGRESET_MASK 0x000000F0
-#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_DBGRESET_SHIFT 4
-/* Individual CPU core and VFP/NEON logic reset.
-Reset is applied only when specific CPU is in STNDBYWFI state. */
-#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_CORERESET_MASK 0x00000F00
-#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_CORERESET_SHIFT 8
-/* Individual CPU por-on-reset.
-Reset is applied only when specific CPU is in STNDBYWFI state. */
-#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_PORESET_MASK 0x0000F000
-#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_PORESET_SHIFT 12
-/* Wait for interrupt mask.
-If set, reset is applied without waiting for the specified CPU's STNDBYWFI state. */
-#define NB_GLOBAL_CPUS_HOLD_RESET_WFI_MASK_MASK 0x000F0000
-#define NB_GLOBAL_CPUS_HOLD_RESET_WFI_MASK_SHIFT 16
-
-/**** CPUs_Software_Reset register ****/
-/* Write 1. Apply the software reset. */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_SWRESET_REQ (1 << 0)
-/* Defines the level of software reset.
-0x0 - cpu_core: Individual CPU core reset.
-0x1 - cpu_poreset: Individual CPU power-on-reset.
-0x2 - cpu_dbg: Individual CPU debug reset.
-0x3 - cluster_no_dbg: A Cluster reset puts each core into core reset (no dbg) and also resets the interrupt controller and L2 logic.
-0x4 - cluster: A Cluster reset puts each core into power-on-reset and also resets the interrupt controller and L2 logic. Debug is active.
-0x5 - cluster_poreset: A Cluster power-on-reset puts each core into power-on-reset and also resets the interrupt controller and L2 logic. This include the cluster debug logic.  */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_MASK 0x0000000E
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT 1
-/* Individual CPU core reset. */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CPU_CORE \
-		(0x0 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
-/* Individual CPU power-on-reset. */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CPU_PORESET \
-		(0x1 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
-/* Individual CPU debug reset. */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CPU_DBG \
-		(0x2 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
-/* A Cluster reset puts each core into core reset (no dbg) and a ... */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CLUSTER_NO_DBG \
-		(0x3 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
-/* A Cluster reset puts each core into power-on-reset and also r ... */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CLUSTER \
-		(0x4 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
-/* A Cluster power-on-reset puts each core into power-on-reset a ... */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CLUSTER_PORESET \
-		(0x5 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
-/* Defines which cores to reset when no cluster_poreset is requested. */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_CORES_MASK 0x000000F0
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_CORES_SHIFT 4
-/* CPUn wait for interrupt enable.
-Defines which CPU WFI indication to wait for before applying the software reset. */
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_WFI_MASK_MASK 0x000F0000
-#define NB_GLOBAL_CPUS_SOFTWARE_RESET_WFI_MASK_SHIFT 16
-
-/**** WD_Timer0_Reset register ****/
-/* Shared L2 memory system, interrupt controller and timer logic reset */
-#define NB_GLOBAL_WD_TIMER0_RESET_L2RESET (1 << 0)
-/* Shared debug domain reset */
-#define NB_GLOBAL_WD_TIMER0_RESET_PRESETDBG (1 << 1)
-/* Individual CPU debug PTM, watchpoint and breakpoint logic reset */
-#define NB_GLOBAL_WD_TIMER0_RESET_CPU_DBGRESET_MASK 0x000000F0
-#define NB_GLOBAL_WD_TIMER0_RESET_CPU_DBGRESET_SHIFT 4
-/* Individual CPU core and VFP/NEON logic reset */
-#define NB_GLOBAL_WD_TIMER0_RESET_CPU_CORERESET_MASK 0x00000F00
-#define NB_GLOBAL_WD_TIMER0_RESET_CPU_CORERESET_SHIFT 8
-/* Individual CPU por-on-reset */
-#define NB_GLOBAL_WD_TIMER0_RESET_CPU_PORESET_MASK 0x0000F000
-#define NB_GLOBAL_WD_TIMER0_RESET_CPU_PORESET_SHIFT 12
-
-/**** WD_Timer1_Reset register ****/
-/* Shared L2 memory system, interrupt controller and timer logic reset */
-#define NB_GLOBAL_WD_TIMER1_RESET_L2RESET (1 << 0)
-/* Shared debug domain reset */
-#define NB_GLOBAL_WD_TIMER1_RESET_PRESETDBG (1 << 1)
-/* Individual CPU debug PTM, watchpoint and breakpoint logic reset */
-#define NB_GLOBAL_WD_TIMER1_RESET_CPU_DBGRESET_MASK 0x000000F0
-#define NB_GLOBAL_WD_TIMER1_RESET_CPU_DBGRESET_SHIFT 4
-/* Individual CPU core and VFP/NEON logic reset */
-#define NB_GLOBAL_WD_TIMER1_RESET_CPU_CORERESET_MASK 0x00000F00
-#define NB_GLOBAL_WD_TIMER1_RESET_CPU_CORERESET_SHIFT 8
-/* Individual CPU por-on-reset */
-#define NB_GLOBAL_WD_TIMER1_RESET_CPU_PORESET_MASK 0x0000F000
-#define NB_GLOBAL_WD_TIMER1_RESET_CPU_PORESET_SHIFT 12
-
-/**** WD_Timer2_Reset register ****/
-/* Shared L2 memory system, interrupt controller and timer logic reset */
-#define NB_GLOBAL_WD_TIMER2_RESET_L2RESET (1 << 0)
-/* Shared debug domain reset */
-#define NB_GLOBAL_WD_TIMER2_RESET_PRESETDBG (1 << 1)
-/* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
-#define NB_GLOBAL_WD_TIMER2_RESET_CPU_DBGRESET_MASK 0x000000F0
-#define NB_GLOBAL_WD_TIMER2_RESET_CPU_DBGRESET_SHIFT 4
-/* Individual CPU core and VFP/NEON logic reset */
-#define NB_GLOBAL_WD_TIMER2_RESET_CPU_CORERESET_MASK 0x00000F00
-#define NB_GLOBAL_WD_TIMER2_RESET_CPU_CORERESET_SHIFT 8
-/* Individual CPU por-on-reset */
-#define NB_GLOBAL_WD_TIMER2_RESET_CPU_PORESET_MASK 0x0000F000
-#define NB_GLOBAL_WD_TIMER2_RESET_CPU_PORESET_SHIFT 12
-
-/**** WD_Timer3_Reset register ****/
-/* Shared L2 memory system, interrupt controller and timer logic reset */
-#define NB_GLOBAL_WD_TIMER3_RESET_L2RESET (1 << 0)
-/* Shared debug domain reset */
-#define NB_GLOBAL_WD_TIMER3_RESET_PRESETDBG (1 << 1)
-/* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
-#define NB_GLOBAL_WD_TIMER3_RESET_CPU_DBGRESET_MASK 0x000000F0
-#define NB_GLOBAL_WD_TIMER3_RESET_CPU_DBGRESET_SHIFT 4
-/* Individual CPU core and VFP/NEON logic reset */
-#define NB_GLOBAL_WD_TIMER3_RESET_CPU_CORERESET_MASK 0x00000F00
-#define NB_GLOBAL_WD_TIMER3_RESET_CPU_CORERESET_SHIFT 8
-/* Individual CPU por-on-reset */
-#define NB_GLOBAL_WD_TIMER3_RESET_CPU_PORESET_MASK 0x0000F000
-#define NB_GLOBAL_WD_TIMER3_RESET_CPU_PORESET_SHIFT 12
-
-/**** DDRC_Hold_Reset register ****/
-/* DDR Control and PHY memory mapped registers reset control
-0 - Reset is deasserted.
-1 - Reset is asserted (active). */
-#define NB_GLOBAL_DDRC_HOLD_RESET_APB_SYNC_RESET (1 << 0)
-/* DDR Control Core reset control
-0 - Reset is deasserted.
-1 - Reset is asserted.
-This field must be set to 0 to start the initialization process after configuring the DDR Controller registers. */
-#define NB_GLOBAL_DDRC_HOLD_RESET_CORE_SYNC_RESET (1 << 1)
-/* DDR Control AXI Interface reset control
-0 - Reset is deasserted.
-1 - Reset is asserted.
-This field must not be set to 0 while core_sync_reset is set to 1. */
-#define NB_GLOBAL_DDRC_HOLD_RESET_AXI_SYNC_RESET (1 << 2)
-/* DDR PUB Controller reset control
-0 - Reset is deasserted.
-1 - Reset is asserted.
-This field must be set to 0 to start the initialization process after configuring the PUB Controller registers. */
-#define NB_GLOBAL_DDRC_HOLD_RESET_PUB_CTL_SYNC_RESET (1 << 3)
-/* DDR PUB SDR Controller reset control
-0 - Reset is deasserted.
-1 - Reset is asserted.
-This field must be set to 0 to start the initialization process after configuring the PUB Controller registers. */
-#define NB_GLOBAL_DDRC_HOLD_RESET_PUB_SDR_SYNC_RESET (1 << 4)
-/* DDR PHY reset control
-0 - Reset is deasserted.
-1 - Reset is asserted.  */
-#define NB_GLOBAL_DDRC_HOLD_RESET_PHY_SYNC_RESET (1 << 5)
-/* Memory initialization input to DDR SRAM for parity check support */
-#define NB_GLOBAL_DDRC_HOLD_RESET_DDR_UNIT_MEM_INIT (1 << 6)
-
-/**** Fabric_Software_Reset register ****/
-/* Write 1 apply the software reset. */
-#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_SWRESET_REQ (1 << 0)
-/* Defines the level of software reset:
-0x0 -  fabric: Fabric reset
-0x1 - gic: GIC reset
-0x2 - smmu: SMMU reset */
-#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_MASK 0x0000000E
-#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT 1
-/* Fabric reset */
-#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_FABRIC \
-		(0x0 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT)
-/* GIC reset */
-#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_GIC \
-		(0x1 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT)
-/* SMMU reset */
-#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SMMU \
-		(0x2 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT)
-/* CPUn waiting for interrupt enable.
-Defines which CPU WFI indication to wait before applying the software reset. */
-#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_WFI_MASK_MASK 0x000F0000
-#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_WFI_MASK_SHIFT 16
-
-/**** CPUs_Power_Ctrl register ****/
-/* L2 WFI enable
-When all the processors are in WFI mode or powered-down, the shared L2 memory system Power Management controller resumes clock on any interrupt.
-Power management controller resumes clock on snoop request.
-NOT IMPLEMENTED */
-#define NB_GLOBAL_CPUS_POWER_CTRL_L2WFI_EN (1 << 0)
-/* L2 WFI status */
-#define NB_GLOBAL_CPUS_POWER_CTRL_L2WFI_STATUS (1 << 1)
-/* L2 RAMs Power Down
-Power down the L2 RAMs. L2 caches must be flushed prior to entering this state. */
-#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_EN (1 << 2)
-/* L2 RAMs power down status */
-#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_STATUS (1 << 3)
-/* CPU state condition to enable L2 RAM power down
-0 - Power down
-1 - WFI
-NOT IMPLEMENTED */
-#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_CPUS_STATE_MASK 0x000000F0
-#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_CPUS_STATE_SHIFT 4
-/* Enable external debugger over power-down.
-Provides support for external debug over power down. If any or all of the processors are powered down, the SoC can still use the debug facilities if the debug PCLKDBG domain is powered up. */
-#define NB_GLOBAL_CPUS_POWER_CTRL_EXT_DEBUGGER_OVER_PD_EN (1 << 8)
-/* L2 hardware flush request. This signal indicates:
-0 L2 hardware flush request is not asserted. flush is performed by SW
-1 L2 hardware flush request is asserted by power management block as part of cluster rams power down flow. HW starts L2 flush flow when all CPUs are in WFI */
-#define NB_GLOBAL_CPUS_POWER_CTRL_L2FLUSH_EN (1 << 9)
-/* Force wakeup the CPU in L2RAM power down
-INTERNAL DEBUG PURPOSE ONLY */
-#define NB_GLOBAL_CPUS_POWER_CTRL_FORCE_CPUS_OK_PWRUP (1 << 27)
-/* L2 RAMs power down SM status */
-#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_SM_STATUS_MASK 0xF0000000
-#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_SM_STATUS_SHIFT 28
-
-/**** ACF_Base_High register ****/
-/* Coherency Fabric registers base [39:32]. */
-#define NB_GLOBAL_ACF_BASE_HIGH_BASE_39_32_MASK 0x000000FF
-#define NB_GLOBAL_ACF_BASE_HIGH_BASE_39_32_SHIFT 0
-/* Coherency Fabric registers base [31:15] */
-#define NB_GLOBAL_ACF_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
-#define NB_GLOBAL_ACF_BASE_LOW_BASED_31_15_SHIFT 15
-
-/**** ACF_Control_Override register ****/
-/* Override the AWCACHE[0] and ARCACHE[0] outputs to be
-non-bufferable. One bit exists for each master interface.
-Connected to BUFFERABLEOVERRIDE[2:0] */
-#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_BUFFOVRD_MASK 0x00000007
-#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_BUFFOVRD_SHIFT 0
-/* Overrides the ARQOS and AWQOS input signals. One bit exists for each slave
-interface.
-Connected to QOSOVERRIDE[4:0] */
-#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_QOSOVRD_MASK 0x000000F8
-#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_QOSOVRD_SHIFT 3
-/* If LOW, then AC requests are never issued on the corresponding slave
-interface. One bit exists for each slave interface.
-Connected to ACCHANNELEN[4:0]. */
-#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_ACE_CH_EN_MASK 0x00001F00
-#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_ACE_CH_EN_SHIFT 8
-/* Internal register:
-Enables 4k hazard of post-barrier vs pre-barrier transactions. Otherwise, 64B hazard granularity is applied. */
-#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_DMB_4K_HAZARD_EN (1 << 13)
-
-/**** LGIC_Base_High register ****/
-/* GIC registers base [39:32].
-This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset. */
-#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF
-#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_SHIFT 0
-#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_MASK_PKR 0x00000FFF
-#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_SHIFT_PKR 0
-/* GIC registers base [31:15].
-This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset */
-#define NB_GLOBAL_LGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
-#define NB_GLOBAL_LGIC_BASE_LOW_BASED_31_15_SHIFT 15
-
-/**** IOGIC_Base_High register ****/
-/* IOGIC registers base [39:32] */
-#define NB_GLOBAL_IOGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF
-#define NB_GLOBAL_IOGIC_BASE_HIGH_BASE_39_32_SHIFT 0
-/* IOGIC registers base [31:15] */
-#define NB_GLOBAL_IOGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
-#define NB_GLOBAL_IOGIC_BASE_LOW_BASED_31_15_SHIFT 15
-
-/**** IO_Wr_Split_Control register ****/
-/* Write splitters bypass.
-[0] Splitter 0 bypass enable
-[1] Splitter 1 bypass enable */
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_BYPASS_MASK 0x00000003
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_BYPASS_SHIFT 0
-/* Write splitters store and forward.
-If store and forward is disabled, splitter does not check non-active BE in the middle of a transaction. */
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_ST_FW_MASK 0x0000000C
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_ST_FW_SHIFT 2
-/* Write splitters unmodify snoop type.
-Disables modifying snoop type from Clean & Invalidate to Invalidate when conditions enable it. Only split operation to 64B is applied. */
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNMODIFY_SNP_MASK 0x00000030
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNMODIFY_SNP_SHIFT 4
-/* Write splitters unsplit non-coherent access.
-Disables splitting of non-coherent access to cache-line chunks. */
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNSPLIT_NOSNP_MASK 0x000000C0
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNSPLIT_NOSNP_SHIFT 6
-/* Write splitter rate limit. */
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR0_SPLT_RATE_LIMIT_MASK 0x00001F00
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR0_SPLT_RATE_LIMIT_SHIFT 8
-/* Write splitter rate limit  */
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR1_SPLT_RATE_LIMIT_MASK 0x0003E000
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR1_SPLT_RATE_LIMIT_SHIFT 13
-/* Write splitters 64bit remap enable
-Enables remapping of 64bit transactions */
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_REMAP_64BIT_EN_MASK 0x000C0000
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_REMAP_64BIT_EN_SHIFT 18
-/* Clear is not supported. This bit was changed to wr_pack_disable.
-In default mode, AWADDR waits for WDATA. */
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_CLEAR_MASK 0xC0000000
-#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_CLEAR_SHIFT 30
-
-/**** IO_Rd_ROB_Control register ****/
-/* Read ROB Bypass
-[0] Rd ROB 0 bypass enable.
-[1] Rd ROB 1 bypass enable. */
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_BYPASS_MASK 0x00000003
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_BYPASS_SHIFT 0
-/* Read ROB in order.
-Return data in the order of request acceptance. */
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_INORDER_MASK 0x0000000C
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_INORDER_SHIFT 2
-/* Read ROB response rate
-When enabled drops one cycle from back to back read responses */
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_RSP_RATE_MASK 0x00000030
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_RSP_RATE_SHIFT 4
-/* Read splitter rate limit */
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD0_ROB_RATE_LIMIT_MASK 0x00001F00
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD0_ROB_RATE_LIMIT_SHIFT 8
-/* Read splitter rate limit */
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD1_ROB_RATE_LIMIT_MASK 0x0003E000
-#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD1_ROB_RATE_LIMIT_SHIFT 13
-
-/**** SB_PoS_Error_Log_1 register ****/
-/* Error Log 1
-[7:0] address_high
-[16:8] request id
-[18:17] bresp  */
-#define NB_GLOBAL_SB_POS_ERROR_LOG_1_ERR_LOG_MASK 0x7FFFFFFF
-#define NB_GLOBAL_SB_POS_ERROR_LOG_1_ERR_LOG_SHIFT 0
-/* Valid logged error
-Set on SB PoS error occurrence on capturing the error information. Subsequent errors will not be captured until the valid bit is cleared.
-The SB PoS reports on write errors.
-When valid, an interrupt is set in the NB Cause Register. */
-#define NB_GLOBAL_SB_POS_ERROR_LOG_1_VALID (1 << 31)
-
-/**** MSIx_Error_Log register ****/
-/* Error Log
-Corresponds to MSIx address message [30:0]. */
-#define NB_GLOBAL_MSIX_ERROR_LOG_ERR_LOG_MASK 0x7FFFFFFF
-#define NB_GLOBAL_MSIX_ERROR_LOG_ERR_LOG_SHIFT 0
-/* Valid logged error */
-#define NB_GLOBAL_MSIX_ERROR_LOG_VALID   (1 << 31)
-
-/**** Error_Cause register ****/
-/* Received msix is not mapped to local GIC or IO-GIC spin */
-#define NB_GLOBAL_ERROR_CAUSE_MSIX_ERR_INT (1 << 2)
-/* Coresight timestamp overflow */
-#define NB_GLOBAL_ERROR_CAUSE_CORESIGHT_TS_OVERFLOW (1 << 3)
-/* Write data parity error from SB channel 0. */
-#define NB_GLOBAL_ERROR_CAUSE_SB0_WRDATA_PERR (1 << 4)
-/* Write data parity error from SB channel 1. */
-#define NB_GLOBAL_ERROR_CAUSE_SB1_WRDATA_PERR (1 << 5)
-/* Read data parity error from SB slaves. */
-#define NB_GLOBAL_ERROR_CAUSE_SB_SLV_RDATA_PERR (1 << 6)
-/* Local GIC uncorrectable ECC error */
-#define NB_GLOBAL_ERROR_CAUSE_LOCAL_GIC_ECC_FATAL (1 << 7)
-/* SB PoS error */
-#define NB_GLOBAL_ERROR_CAUSE_SB_POS_ERR (1 << 8)
-/* Coherent fabric error summary interrupt */
-#define NB_GLOBAL_ERROR_CAUSE_ACF_ERRORIRQ (1 << 9)
-/* Error indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of the L2ECTLR clears the error indicator connected to CA15 nAXIERRIRQ. */
-#define NB_GLOBAL_ERROR_CAUSE_CPU_AXIERRIRQ (1 << 10)
-/* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */
-#define NB_GLOBAL_ERROR_CAUSE_CPU_INTERRIRQ (1 << 12)
-/* DDR cause summery interrupt */
-#define NB_GLOBAL_ERROR_CAUSE_DDR_CAUSE_SUM (1 << 14)
-
-/**** QoS_Peak_Control register ****/
-/* Peak Read Low Threshold
-When the number of outstanding read transactions from SB masters is below this value, the CPU is assigned high-priority QoS.  */
-#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_L_THRESHOLD_MASK 0x0000007F
-#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_L_THRESHOLD_SHIFT 0
-/* Peak Read High Threshold
-When the number of outstanding read transactions from SB masters exceeds this value, the CPU is assigned high-priority QoS.  */
-#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_H_THRESHOLD_MASK 0x00007F00
-#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_H_THRESHOLD_SHIFT 8
-/* Peak Write Low Threshold
-When the number of outstanding write transactions from SB masters is below this value, the CPU is assigned high-priority QoS  */
-#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_L_THRESHOLD_MASK 0x007F0000
-#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_L_THRESHOLD_SHIFT 16
-/* Peak Write High Threshold
-When the number of outstanding write transactions from SB masters exceeds this value, the CPU is assigned high-priority QoS.  */
-#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_H_THRESHOLD_MASK 0x7F000000
-#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_H_THRESHOLD_SHIFT 24
-
-/**** QoS_Set_Control register ****/
-/* CPU Low priority Read QoS */
-#define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_ARQOS_MASK 0x0000000F
-#define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_ARQOS_SHIFT 0
-/* CPU High priority Read QoS */
-#define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_ARQOS_MASK 0x000000F0
-#define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_ARQOS_SHIFT 4
-/* CPU Low priority Write QoS */
-#define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_AWQOS_MASK 0x00000F00
-#define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_AWQOS_SHIFT 8
-/* CPU High priority Write QoS */
-#define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_AWQOS_MASK 0x0000F000
-#define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_AWQOS_SHIFT 12
-/* SB Low priority Read QoS */
-#define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_ARQOS_MASK 0x000F0000
-#define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_ARQOS_SHIFT 16
-/* SB Low-priority Write QoS */
-#define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_AWQOS_MASK 0x00F00000
-#define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_AWQOS_SHIFT 20
-
-/**** DDR_QoS register ****/
-/* High Priority Read Threshold
-Limits the number of outstanding high priority reads in the system through the memory controller.
-This parameter is programmed in conjunction with number of outstanding high priority reads supported by the DDR controller. */
-#define NB_GLOBAL_DDR_QOS_HIGH_PRIO_THRESHOLD_MASK 0x0000007F
-#define NB_GLOBAL_DDR_QOS_HIGH_PRIO_THRESHOLD_SHIFT 0
-/* DDR Low Priority QoS
-Fabric priority below this value is mapped to DDR low priority queue. */
-#define NB_GLOBAL_DDR_QOS_LP_QOS_MASK    0x00000F00
-#define NB_GLOBAL_DDR_QOS_LP_QOS_SHIFT   8
-
-/**** ACF_Misc register ****/
-/* Disable DDR Write Chop
-Performance optimization feature to chop non-active data beats to the DDR. */
-#define NB_GLOBAL_ACF_MISC_DDR_WR_CHOP_DIS (1 << 0)
-/* Disable SB-2-SB path through NB fabric. */
-#define NB_GLOBAL_ACF_MISC_SB2SB_PATH_DIS (1 << 1)
-/* Disable ETR tracing to non-DDR. */
-#define NB_GLOBAL_ACF_MISC_ETR2SB_PATH_DIS (1 << 2)
-/* Disable ETR tracing to non-DDR. */
-#define NB_GLOBAL_ACF_MISC_CPU2MSIX_DIS  (1 << 3)
-/* Disable CPU generation of MSIx
-By default, the CPU can set any MSIx message results by setting any SPIn bit in the local and IO-GIC. */
-#define NB_GLOBAL_ACF_MISC_MSIX_TERMINATE_DIS (1 << 4)
-/* Disable snoop override for MSIx
-By default, an MSIx transaction is downgraded to non-coherent. */
-#define NB_GLOBAL_ACF_MISC_MSIX_SNOOPOVRD_DIS (1 << 5)
-/* POS bypass */
-#define NB_GLOBAL_ACF_MISC_POS_BYPASS    (1 << 6)
-/* PoS ReadStronglyOrdered enable
-SO read forces flushing of all prior writes */
-#define NB_GLOBAL_ACF_MISC_POS_RSO_EN    (1 << 7)
-/* WRAP to INC transfer enable */
-#define NB_GLOBAL_ACF_MISC_POS_WRAP2INC  (1 << 8)
-/* PoS DSB flush Disable
-On DSB from CPU, PoS blocks the progress of post-barrier reads and writes until all pre-barrier writes have been completed. */
-#define NB_GLOBAL_ACF_MISC_POS_DSB_FLUSH_DIS (1 << 9)
-/* PoS DMB Flush Disable
-On DMB from CPU, the PoS blocks the progress of post-barrier non-buffereable reads or writes when there are outstanding non-bufferable writes that have not yet been completed.
-Other access types are  hazard check against the pre-barrier requests. */
-#define NB_GLOBAL_ACF_MISC_POS_DMB_FLUSH_DIS (1 << 10)
-/* change DMB functionality to DSB (block and drain) */
-#define NB_GLOBAL_ACF_MISC_POS_DMB_TO_DSB_EN (1 << 11)
-/* Disable write after read stall when accessing IO fabric slaves.  */
-#define NB_GLOBAL_ACF_MISC_M0_WAR_STALL_DIS (1 << 12)
-/* Disable write after read stall when accessing DDR  */
-#define NB_GLOBAL_ACF_MISC_M1_WAR_STALL_DIS (1 << 13)
-/* Disable counter (wait 1000 NB cycles) before applying PoS enable/disable configuration */
-#define NB_GLOBAL_ACF_MISC_POS_CONFIG_CNT_DIS (1 << 14)
-/* Disable wr spliter A0 bug fixes */
-#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_M0_MODE (1 << 16)
-/* Disable wr spliter PKR bug fixes */
-#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_A0_MODE (1 << 17)
-/* Override the address parity calucation for write transactions going to IO-fabric */
-#define NB_GLOBAL_ACF_MISC_NB_NIC_AWADDR_PAR_OVRD (1 << 18)
-/* Override the data parity calucation for write transactions going to IO-fabric */
-#define NB_GLOBAL_ACF_MISC_NB_NIC_WDATA_PAR_OVRD (1 << 19)
-/* Override the address parity calucation for read transactions going to IO-fabric */
-#define NB_GLOBAL_ACF_MISC_NB_NIC_ARADDR_PAR_OVRD (1 << 20)
-/* Halts CPU AXI interface (Ar/Aw channels), not allowing the CPU to send additional transactions */
-#define NB_GLOBAL_ACF_MISC_CPU_AXI_HALT  (1 << 23)
-/* Disable early arbar termination when fabric write buffer is enabled.  */
-#define NB_GLOBAL_ACF_MISC_CCIWB_EARLY_ARBAR_TERM_DIS (1 << 24)
-/* Enable wire interrupts connectivity to IO-GIC IRQs */
-#define NB_GLOBAL_ACF_MISC_IOGIC_CHIP_SPI_EN (1 << 25)
-/* Enable DMB flush request to NB to SB PoS when barrier is terminted inside the processor cluster */
-#define NB_GLOBAL_ACF_MISC_CPU_DSB_FLUSH_DIS (1 << 26)
-/* Enable DMB flush request to NB to SB PoS when barrier is terminted inside the processor cluster */
-#define NB_GLOBAL_ACF_MISC_CPU_DMB_FLUSH_DIS (1 << 27)
-/* Peakrock only: remap CPU address above 40 bits to Slave Error
-INTERNAL  */
-#define NB_GLOBAL_ACF_MISC_ADDR43_40_REMAP_DIS (1 << 28)
-/* Enable CPU WriteUnique to WriteNoSnoop trasform */
-#define NB_GLOBAL_ACF_MISC_CPU_WU2WNS_EN (1 << 29)
-/* Disable device after device check */
-#define NB_GLOBAL_ACF_MISC_WR_POS_DEV_AFTER_DEV_DIS (1 << 30)
-/* Disable wrap to inc on write */
-#define NB_GLOBAL_ACF_MISC_WR_INC2WRAP_EN (1 << 31)
-
-/**** Config_Bus_Control register ****/
-/* Write slave error enable */
-#define NB_GLOBAL_CONFIG_BUS_CONTROL_WR_SLV_ERR_EN (1 << 0)
-/* Write decode error enable */
-#define NB_GLOBAL_CONFIG_BUS_CONTROL_WR_DEC_ERR_EN (1 << 1)
-/* Read slave error enable */
-#define NB_GLOBAL_CONFIG_BUS_CONTROL_RD_SLV_ERR_EN (1 << 2)
-/* Read decode error enable */
-#define NB_GLOBAL_CONFIG_BUS_CONTROL_RD_DEC_ERR_EN (1 << 3)
-/* Ignore Write ID */
-#define NB_GLOBAL_CONFIG_BUS_CONTROL_IGNORE_WR_ID (1 << 4)
-/* Timeout limit before terminating configuration bus access with slave error */
-#define NB_GLOBAL_CONFIG_BUS_CONTROL_TIMEOUT_LIMIT_MASK 0xFFFFFF00
-#define NB_GLOBAL_CONFIG_BUS_CONTROL_TIMEOUT_LIMIT_SHIFT 8
-
-/**** Pos_ID_Match register ****/
-/* Enable Device (GRE and nGRE) after Device ID hazard */
-#define NB_GLOBAL_POS_ID_MATCH_ENABLE    (1 << 0)
-/* ID Field Mask
-If set, corresonpding ID bits are not used for ID match */
-#define NB_GLOBAL_POS_ID_MATCH_MASK_MASK 0xFFFF0000
-#define NB_GLOBAL_POS_ID_MATCH_MASK_SHIFT 16
-
-/**** sb_sel_override_awuser register ****/
-/* Select whether to use transaction awuser or sb_override_awuser value for awuser field on outgoing write transactions to SB.
-Each bit if set to 1 selects the corresponding sb_override_awuser bit. Otherwise, selects the corersponding transaction awuser bit. */
-#define NB_GLOBAL_SB_SEL_OVERRIDE_AWUSER_SEL_MASK 0x03FFFFFF
-#define NB_GLOBAL_SB_SEL_OVERRIDE_AWUSER_SEL_SHIFT 0
-
-/**** sb_override_awuser register ****/
-/* Awuser to use on overriden transactions
-Only applicable if sel_override_awuser.sel is set to 1'b1 for the coressponding bit */
-#define NB_GLOBAL_SB_OVERRIDE_AWUSER_AWUSER_MASK 0x03FFFFFF
-#define NB_GLOBAL_SB_OVERRIDE_AWUSER_AWUSER_SHIFT 0
-
-/**** sb_sel_override_aruser register ****/
-/* Select whether to use transaction aruser or sb_override_aruser value for aruser field on outgoing read transactions to SB.
-Each bit if set to 1 selects the corresponding sb_override_aruser bit. Otherwise, selects the corersponding transaction aruser bit. */
-#define NB_GLOBAL_SB_SEL_OVERRIDE_ARUSER_SEL_MASK 0x03FFFFFF
-#define NB_GLOBAL_SB_SEL_OVERRIDE_ARUSER_SEL_SHIFT 0
-
-/**** sb_override_aruser register ****/
-/* Aruser to use on overriden transactions
-Only applicable if sb_sel_override_aruser.sel is set to 1'b1 for the coressponding bit */
-#define NB_GLOBAL_SB_OVERRIDE_ARUSER_ARUSER_MASK 0x03FFFFFF
-#define NB_GLOBAL_SB_OVERRIDE_ARUSER_ARUSER_SHIFT 0
-
-/**** Coresight_PD register ****/
-/* ETF0 RAM force power down */
-#define NB_GLOBAL_CORESIGHT_PD_ETF0_RAM_FORCE_PD (1 << 0)
-/* ETF1 RAM force power down */
-#define NB_GLOBAL_CORESIGHT_PD_ETF1_RAM_FORCE_PD (1 << 1)
-/* ETF0 RAM force clock gate */
-#define NB_GLOBAL_CORESIGHT_PD_ETF0_RAM_FORCE_CG (1 << 2)
-/* ETF1 RAM force clock gate */
-#define NB_GLOBAL_CORESIGHT_PD_ETF1_RAM_FORCE_CG (1 << 3)
-/* APBIC clock enable */
-#define NB_GLOBAL_CORESIGHT_PD_APBICLKEN (1 << 4)
-/* DAP system clock enable */
-#define NB_GLOBAL_CORESIGHT_PD_DAP_SYS_CLKEN (1 << 5)
-
-/**** Coresight_INTERNAL_0 register ****/
-
-#define NB_GLOBAL_CORESIGHT_INTERNAL_0_CTIAPBSBYPASS (1 << 0)
-/* CA15 CTM and Coresight CTI operate at same clock, bypass modes can be enabled but it's being set to bypass disable to break timing path. */
-#define NB_GLOBAL_CORESIGHT_INTERNAL_0_CISBYPASS (1 << 1)
-/* CA15 CTM and Coresight CTI operate according to the same clock.
-Bypass modes can be enabled, but it is set to bypass disable, to break the timing path. */
-#define NB_GLOBAL_CORESIGHT_INTERNAL_0_CIHSBYPASS_MASK 0x0000003C
-#define NB_GLOBAL_CORESIGHT_INTERNAL_0_CIHSBYPASS_SHIFT 2
-
-/**** Coresight_DBGROMADDR register ****/
-/* Valid signal for DBGROMADDR.
-Connected to DBGROMADDRV */
-#define NB_GLOBAL_CORESIGHT_DBGROMADDR_VALID (1 << 0)
-/* Specifies bits [39:12] of the ROM table physical address. */
-#define NB_GLOBAL_CORESIGHT_DBGROMADDR_ADDR_39_12_MASK 0x3FFFFFFC
-#define NB_GLOBAL_CORESIGHT_DBGROMADDR_ADDR_39_12_SHIFT 2
-
-/**** Coresight_DBGSELFADDR register ****/
-/* Valid signal for DBGROMADDR.
-Connected to DBGROMADDRV */
-#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_VALID (1 << 0)
-/* Specifies bits [18:17] of the two's complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped.
-Note: The CA15 debug unit starts at offset 0x1 within the Coresight cluster. */
-#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_18_17_MASK 0x00000180
-#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_18_17_SHIFT 7
-/* Specifies bits [39:19] of the two's complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped.
-Note: The CA15 debug unit starts at offset 0x1 within the Coresight cluster, so this offset if fixed to zero. */
-#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_39_19_MASK 0x3FFFFE00
-#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_39_19_SHIFT 9
-
-/**** SB_force_same_id_cfg_0 register ****/
-/* Enables force same id mechanism for SB port 0 */
-#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_FORCE_SAME_ID_EN (1 << 0)
-/* Enables MSIx stall when write transactions from same ID mechanism are in progress for SB port 0 */
-#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_FORCE_SAME_ID_MSIX_STALL_EN (1 << 1)
-/* Mask for choosing which ID bits to match for indicating the originating master */
-#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_SB_MSTR_ID_MASK_MASK 0x000000F8
-#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_SB_MSTR_ID_MASK_SHIFT 3
-
-/**** SB_force_same_id_cfg_1 register ****/
-/* Enables force same id mechanism for SB port 1 */
-#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_FORCE_SAME_ID_EN (1 << 0)
-/* Enables MSIx stall when write transactions from same ID mechanism are in progress for SB port 1 */
-#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_FORCE_SAME_ID_MSIX_STALL_EN (1 << 1)
-/* Mask for choosing which ID bits to match for indicating the originating master */
-#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_SB_MSTR_ID_MASK_MASK 0x000000F8
-#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_SB_MSTR_ID_MASK_SHIFT 3
-
-/**** Cnt_Control register ****/
-/* System counter enable
-Counter is enabled after reset. */
-#define NB_SYSTEM_COUNTER_CNT_CONTROL_EN (1 << 0)
-/* System counter restart
-Initial value is reloaded from Counter_Init_L and Counter_Init_H registers.
-Transition from 0 to 1 reloads the register. */
-#define NB_SYSTEM_COUNTER_CNT_CONTROL_RESTART (1 << 1)
-/* Disable CTI trigger out that halt the counter progress */
-#define NB_SYSTEM_COUNTER_CNT_CONTROL_CTI_TRIGOUT_HALT_DIS (1 << 2)
-/* System counter tick
-Specifies the counter tick rate relative to the Northbridge clock, e.g., the counter is incremented every 16 NB cycles if programmed to 0x0f. */
-#define NB_SYSTEM_COUNTER_CNT_CONTROL_SCALE_MASK 0x0000FF00
-#define NB_SYSTEM_COUNTER_CNT_CONTROL_SCALE_SHIFT 8
-
-/**** CA15_RF_Misc register ****/
-
-#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_NONECPU_RF_MISC_MASK 0x0000000F
-#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_NONECPU_RF_MISC_SHIFT 0
-
-#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_CPU_RF_MISC_MASK 0x00FFFF00
-#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_CPU_RF_MISC_SHIFT 8
-/* Pause for CPUs from the time all power is up to the time the SRAMs start opening. */
-#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_PWR_UP_PAUSE_MASK 0xF8000000
-#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_PWR_UP_PAUSE_SHIFT 27
-
-/**** NB_RF_Misc register ****/
-/* SMMU TLB RAMs force power down */
-#define NB_RAMS_CONTROL_MISC_NB_RF_MISC_SMMU_RAM_FORCE_PD (1 << 0)
-
-/**** Lockn register ****/
-/* Semaphore Lock
-CPU reads it:
-If current value ==0,  return 0 to CPU but set bit to 1. (CPU knows it captured the semaphore.)
-If current value ==1, return 1 to CPU. (CPU knows it is already used and waits.)
-CPU writes 0 to it to release the semaphore. */
-#define NB_SEMAPHORES_LOCKN_LOCK         (1 << 0)
-
-/**** CA15_outputs_1 register ****/
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_1_STANDBYWFI_MASK 0x0000000F
-#define NB_DEBUG_CA15_OUTPUTS_1_STANDBYWFI_SHIFT 0
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_1_CPU_PWR_DN_ACK_MASK 0x000000F0
-#define NB_DEBUG_CA15_OUTPUTS_1_CPU_PWR_DN_ACK_SHIFT 4
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_1_IRQOUT_N_MASK 0x00000F00
-#define NB_DEBUG_CA15_OUTPUTS_1_IRQOUT_N_SHIFT 8
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_1_FIQOUT_N_MASK 0x0000F000
-#define NB_DEBUG_CA15_OUTPUTS_1_FIQOUT_N_SHIFT 12
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_1_CNTHPIRQ_N_MASK 0x000F0000
-#define NB_DEBUG_CA15_OUTPUTS_1_CNTHPIRQ_N_SHIFT 16
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_1_NCNTPNSIRQ_N_MASK 0x00F00000
-#define NB_DEBUG_CA15_OUTPUTS_1_NCNTPNSIRQ_N_SHIFT 20
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_1_NCNTPSIRQ_N_MASK 0x0F000000
-#define NB_DEBUG_CA15_OUTPUTS_1_NCNTPSIRQ_N_SHIFT 24
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_1_NCNTVIRQ_N_MASK 0xF0000000
-#define NB_DEBUG_CA15_OUTPUTS_1_NCNTVIRQ_N_SHIFT 28
-
-/**** CA15_outputs_2 register ****/
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_2_STANDBYWFIL2 (1 << 0)
-/*
- */
-#define NB_DEBUG_CA15_OUTPUTS_2_L2RAM_PWR_DN_ACK (1 << 1)
-/* Indicates for each CPU if coherency is enabled
- */
-#define NB_DEBUG_CA15_OUTPUTS_2_SMPEN_MASK 0x0000003C
-#define NB_DEBUG_CA15_OUTPUTS_2_SMPEN_SHIFT 2
-
-/**** cpu_msg register ****/
-/* Status/ASCII code */
-#define NB_DEBUG_CPU_MSG_STATUS_MASK     0x000000FF
-#define NB_DEBUG_CPU_MSG_STATUS_SHIFT    0
-/* Toggle with each ASCII write */
-#define NB_DEBUG_CPU_MSG_ASCII_TOGGLE    (1 << 8)
-/* Signals ASCII */
-#define NB_DEBUG_CPU_MSG_ASCII           (1 << 9)
-
-#define NB_DEBUG_CPU_MSG_RESERVED_11_10_MASK 0x00000C00
-#define NB_DEBUG_CPU_MSG_RESERVED_11_10_SHIFT 10
-/* Signals new section started in S/W */
-#define NB_DEBUG_CPU_MSG_SECTION_START   (1 << 12)
-
-#define NB_DEBUG_CPU_MSG_RESERVED_13     (1 << 13)
-/* Signals a single CPU is done. */
-#define NB_DEBUG_CPU_MSG_CPU_DONE        (1 << 14)
-/* Signals test is done */
-#define NB_DEBUG_CPU_MSG_TEST_DONE       (1 << 15)
-
-/**** ddrc register ****/
-/* External DLL calibration request. Also compensates for VT variations, such as an external request for the controller (can be performed automatically by the controller at the normal settings). */
-#define NB_DEBUG_DDRC_DLL_CALIB_EXT_REQ  (1 << 0)
-/* External request to perform short (long is performed during initialization) and/or ODT calibration. */
-#define NB_DEBUG_DDRC_ZQ_SHORT_CALIB_EXT_REQ (1 << 1)
-/* External request to perform a refresh command to a specific bank. Usually performed automatically by the controller, however, the controller supports disabling of the automatic mechanism, and use of an external pulse instead.  */
-#define NB_DEBUG_DDRC_RANK_REFRESH_EXT_REQ_MASK 0x0000003C
-#define NB_DEBUG_DDRC_RANK_REFRESH_EXT_REQ_SHIFT 2
-
-/**** ddrc_phy_smode_control register ****/
-/* DDR PHY special mode */
-#define NB_DEBUG_DDRC_PHY_SMODE_CONTROL_CTL_MASK 0x0000FFFF
-#define NB_DEBUG_DDRC_PHY_SMODE_CONTROL_CTL_SHIFT 0
-
-/**** ddrc_phy_smode_status register ****/
-/* DDR PHY special mode */
-#define NB_DEBUG_DDRC_PHY_SMODE_STATUS_STT_MASK 0x0000FFFF
-#define NB_DEBUG_DDRC_PHY_SMODE_STATUS_STT_SHIFT 0
-
-/**** pmc register ****/
-/* Enable system control on NB DRO */
-#define NB_DEBUG_PMC_SYS_EN              (1 << 0)
-/* NB PMC HVT35 counter value */
-#define NB_DEBUG_PMC_HVT35_VAL_14_0_MASK 0x0000FFFE
-#define NB_DEBUG_PMC_HVT35_VAL_14_0_SHIFT 1
-/* NB PMC SVT31 counter value */
-#define NB_DEBUG_PMC_SVT31_VAL_14_0_MASK 0x7FFF0000
-#define NB_DEBUG_PMC_SVT31_VAL_14_0_SHIFT 16
-
-/**** cpus_general register ****/
-/* Swaps sysaddr[16:14] with sysaddr[19:17] for DDR access*/
-#define NB_DEBUG_CPUS_GENERAL_ADDR_MAP_ECO (1 << 23)
-
-/**** cpus_int_out register ****/
-/* Defines which CPUs' FIQ will be triggered out through the cpus_int_out[1] pinout. */
-#define NB_DEBUG_CPUS_INT_OUT_FIQ_EN_MASK 0x0000000F
-#define NB_DEBUG_CPUS_INT_OUT_FIQ_EN_SHIFT 0
-/* Defines which CPUs' IRQ will be triggered out through the cpus_int_out[0] pinout. */
-#define NB_DEBUG_CPUS_INT_OUT_IRQ_EN_MASK 0x000000F0
-#define NB_DEBUG_CPUS_INT_OUT_IRQ_EN_SHIFT 4
-/* Defines which CPUs' SEI will be triggered out through the cpus_int_out[0] pinout. */
-#define NB_DEBUG_CPUS_INT_OUT_IRQ_SEI_EN_MASK 0x00000F00
-#define NB_DEBUG_CPUS_INT_OUT_IRQ_SEI_EN_SHIFT 8
-
-/**** latch_pc_req register ****/
-/* If set, request to latch execution  PC from processor cluster */
-#define NB_DEBUG_LATCH_PC_REQ_EN         (1 << 0)
-/* target CPU id to latch its execution PC */
-#define NB_DEBUG_LATCH_PC_REQ_CPU_ID_MASK 0x000000F0
-#define NB_DEBUG_LATCH_PC_REQ_CPU_ID_SHIFT 4
-
-/**** latch_pc_low register ****/
-/* Set by hardware when the processor cluster ack the PC latch request.
-Clear on read latch_pc_high */
-#define NB_DEBUG_LATCH_PC_LOW_VALID      (1 << 0)
-/* Latched PC value [31:1] */
-#define NB_DEBUG_LATCH_PC_LOW_VAL_MASK   0xFFFFFFFE
-#define NB_DEBUG_LATCH_PC_LOW_VAL_SHIFT  1
-
-/**** track_dump_ctrl register ****/
-/* [24:16]: Queue entry pointer
-[2] Target queue:  1'b0: HazardTrack or 1'b1: AmiRMI queues
-[1:0]: CCI target master: 2'b00: M0, 2'b01: M1, 2'b10: M2 */
-#define NB_DEBUG_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
-#define NB_DEBUG_TRACK_DUMP_CTRL_PTR_SHIFT 0
-/* Track Dump Request
-If set, queue entry info is latched on track_dump_rdata register.
-Program the pointer and target queue.
-This is a full handshake register.
-Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */
-#define NB_DEBUG_TRACK_DUMP_CTRL_REQ     (1 << 31)
-
-/**** track_dump_rdata_0 register ****/
-/* Valid */
-#define NB_DEBUG_TRACK_DUMP_RDATA_0_VALID (1 << 0)
-/* Low data */
-#define NB_DEBUG_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
-#define NB_DEBUG_TRACK_DUMP_RDATA_0_DATA_SHIFT 1
-
-/**** pos_track_dump_ctrl register ****/
-/* [24:16]: queue entry pointer */
-#define NB_DEBUG_POS_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
-#define NB_DEBUG_POS_TRACK_DUMP_CTRL_PTR_SHIFT 0
-/* Track Dump Request
-If set, queue entry info is latched on track_dump_rdata register.
-Program the pointer and target queue.
-This is a  full handshake register
-Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */
-#define NB_DEBUG_POS_TRACK_DUMP_CTRL_REQ (1 << 31)
-
-/**** pos_track_dump_rdata_0 register ****/
-/* Valid */
-#define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_VALID (1 << 0)
-/* Low data */
-#define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
-#define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_DATA_SHIFT 1
-
-/**** c2swb_track_dump_ctrl register ****/
-/* [24:16]: Queue entry pointer */
-#define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
-#define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_PTR_SHIFT 0
-/* Track Dump Request
-If set, queue entry info is latched on track_dump_rdata register.
-Program the pointer and target queue.
-This is a full handshake register
-Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */
-#define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_REQ (1 << 31)
-
-/**** c2swb_track_dump_rdata_0 register ****/
-/* Valid */
-#define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_VALID (1 << 0)
-/* Low data */
-#define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
-#define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_DATA_SHIFT 1
-
-/**** cpus_track_dump_ctrl register ****/
-/* [24:16]: Queue entry pointer
-[3:2] Target queue - 0:ASI, 1: AMI
-[1:0]: Target Processor Cluster - 0: Cluster0, 1: Cluster1 */
-#define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
-#define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_PTR_SHIFT 0
-/* Track Dump Request
-If set, queue entry info is latched on track_dump_rdata register.
-Program the pointer and target queue.
-This is a  full handshake register
-Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */
-#define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_REQ (1 << 31)
-
-/**** cpus_track_dump_rdata_0 register ****/
-/* Valid */
-#define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_VALID (1 << 0)
-/* Low data */
-#define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
-#define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_DATA_SHIFT 1
-
-/**** c2swb_bar_ovrd_high register ****/
-/* Read barrier is progressed downstream when not terminated in the CCI.
-By specification, barrier address is 0x0.
-This register enables barrier address OVRD to a programmable value. */
-#define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_RD_ADDR_OVRD_EN (1 << 0)
-/* Address bits 39:32 */
-#define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_ADDR_39_32_MASK 0x00FF0000
-#define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_ADDR_39_32_SHIFT 16
-
-/**** Config register ****/
-/* Individual processor control of the endianness configuration at reset. It sets the initial value of the EE bit in the CP15 System Control Register (SCTLR) related to CFGEND<n> input:
-little - 0x0: Little endian
-bit - 0x1: Bit endian */
-#define NB_CPUN_CONFIG_STATUS_CONFIG_ENDIAN (1 << 0)
-/* Individual processor control of the default exception handling state. It sets the initial value of the TE bit in the CP15 System Control Register (SCTLR) related to CFGTE<n> input:
-arm: 0x0: Exception operates ARM code.
-Thumb: 0x1: Exception operates Thumb code. */
-#define NB_CPUN_CONFIG_STATUS_CONFIG_TE  (1 << 1)
-/* Individual processor control of the location of the exception vectors at reset. It sets the initial value of the V bit in the CP15 System Control Register (SCTLR).
-Connected to VINITHIGH<n> input.
-low - 0x0: Exception vectors start at address 0x00000000.
-high - 0x1: Exception vectors start at address 0xFFFF0000. */
-#define NB_CPUN_CONFIG_STATUS_CONFIG_VINITHI (1 << 2)
-/* Individual processor control to disable write access to some secure CP15 registers
-connected to CP15SDISABLE<n> input. */
-#define NB_CPUN_CONFIG_STATUS_CONFIG_CP15DISABLE (1 << 3)
-/* Force Write init implementation to ConfigAARch64 register */
-#define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_REG_FORCE_WINIT (1 << 4)
-/* Force Write Once implementation to ConfigAARch64 register. */
-#define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_REG_FORCE_WONCE (1 << 5)
-
-/**** Config_AARch64 register ****/
-/* Individual processor register width state. The register width states are:
-0 AArch32.
-1 AArch64.
-This signal is only sampled during reset of the processor.
-This is Write Init register */
-#define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_AA64_NAA32 (1 << 0)
-/* Individual processor Cryptography engine disable:
-0 Enable the Cryptography engine.
-1 Disable the Cryptography engine.
-This signal is only sampled during reset of the processor */
-#define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_CRYPTO_DIS (1 << 1)
-
-/**** Power_Ctrl register ****/
-/* Individual CPU power mode transition request
-If requested to enter power mode other than normal mode, low power state is resumed whenever CPU reenters STNDBYWFI state:
-normal: 0x0: normal power state
-deep_idle: 0x2: Dormant power mode state
-poweredoff: 0x3: Powered-off power mode */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_MASK 0x00000003
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT 0
-/* Normal power mode state */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_NORMAL \
-		(0x0 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT)
-/* Dormant power mode state */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_DEEP_IDLE \
-		(0x2 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT)
-/* Powered-off power mode */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_POWEREDOFF \
-		(0x3 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT)
-/* Power down regret disable
-When power down regret is enabled, the powerdown enter flow can be halted whenever a valid wakeup event occurs. */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PWRDN_RGRT_DIS (1 << 16)
-/* Power down emulation enable
-If set, the entire power down sequence is applied, but the CPU is placed in soft reset instead of hardware power down. */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PWRDN_EMULATE (1 << 17)
-/* Disable wakeup from Local--GIC FIQ. */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_LGIC_FIQ_DIS (1 << 18)
-/* Disable wakeup from Local-GIC IRQ. */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_LGIC_IRQ_DIS (1 << 19)
-/* Disable wakeup from IO-GIC FIQ. */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_IOGIC_FIQ_DIS (1 << 20)
-/* Disable wakeup from IO-GIC IRQ. */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_IOGIC_IRQ_DIS (1 << 21)
-/* Disable scheduling of interrrupts in GIC(500) to non-active CPU */
-#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_IOGIC_DIS_CPU (1 << 22)
-
-/**** Power_Status register ****/
-/* Read-only bits that reflect the individual CPU power mode status.
-Default value for non-exist CPU is 2b11:
-normal - 0x0: Normal mode
-por - 0x1: por on reset mode
-deep_idle - 0x2: Dormant power mode state
-poweredoff - 0x3: Powered-off power mode */
-#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_MASK 0x00000003
-#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT 0
-/* Normal power mode state */
-#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_NORMAL \
-		(0x0 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
-/* Idle power mode state (WFI) */
-#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_IDLE \
-		(0x1 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
-/* Dormant power mode state */
-#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_DEEP_IDLE \
-		(0x2 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
-/* Powered-off power mode */
-#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_POWEREDOFF \
-		(0x3 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
-/* WFI status */
-#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_WFI (1 << 2)
-/* WFE status */
-#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_WFE (1 << 3)
-
-/**** Warm_Rst_Ctl register ****/
-/* Disable CPU Warm Reset when warmrstreq is asserted
-
-When the Reset Request bit in the RMR or RMR_EL3 register is set to 1 in the CPU Core , the processor asserts the WARMRSTREQ signal and the SoC reset controller use this request to trigger a Warm reset of the processor and change the register width state. */
-#define NB_CPUN_CONFIG_STATUS_WARM_RST_CTL_REQ_DIS (1 << 0)
-/* Disable waiting WFI on Warm Reset */
-#define NB_CPUN_CONFIG_STATUS_WARM_RST_CTL_WFI_DIS (1 << 1)
-/* CPU Core AARach64 reset vector bar
-This is Write Once register (controlled by aarch64_reg_force_* fields) */
-#define NB_CPUN_CONFIG_STATUS_RVBAR_LOW_ADDR_31_2_MASK 0xFFFFFFFC
-#define NB_CPUN_CONFIG_STATUS_RVBAR_LOW_ADDR_31_2_SHIFT 2
-
-/**** Rvbar_High register ****/
-/* CPU Core AARach64 reset vector bar high bits
-This is Write Once register (controlled by aarch64_reg_force_* fields) */
-#define NB_CPUN_CONFIG_STATUS_RVBAR_HIGH_ADDR_43_32_MASK 0x00000FFF
-#define NB_CPUN_CONFIG_STATUS_RVBAR_HIGH_ADDR_43_32_SHIFT 0
-
-/**** pmu_snapshot register ****/
-/* PMU Snapshot Request */
-#define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_REQ (1 << 0)
-/* 0:  HW deassert requests when received ack
-1: SW deasserts request when received done */
-#define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_MODE (1 << 1)
-/* Snapshot process completed */
-#define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_DONE (1 << 31)
-
-/**** cpu_msg_in register ****/
-/* CPU read this register to receive input (char) from simulation. */
-#define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_DATA_MASK 0x000000FF
-#define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_DATA_SHIFT 0
-/* Indicates the data is valid.
-Cleared on read */
-#define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_VALID (1 << 8)
-
-/**** PMU_Control register ****/
-/* Disable all counters
-When this bit is clear, counter state is determined through the specific counter control register */
-#define NB_MC_PMU_PMU_CONTROL_DISABLE_ALL (1 << 0)
-/* Pause all counters.
-When this bit is clear, counter state is determined through the specific counter control register. */
-#define NB_MC_PMU_PMU_CONTROL_PAUSE_ALL  (1 << 1)
-/* Overflow interrupt enable:
-disable - 0x0: Disable interrupt on overflow.
-enable - 0x1: Enable interrupt on overflow. */
-#define NB_MC_PMU_PMU_CONTROL_OVRF_INTR_EN (1 << 2)
-/* Number of monitored events supported by the PMU. */
-#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_MASK 0x00FC0000
-#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT 18
-#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT_ALPINE 19
-/* Number of counters implemented by PMU. */
-#define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_MASK 0x0F000000
-#define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_SHIFT 24
-
-/**** Cfg register ****/
-/* Event select */
-#define NB_MC_PMU_COUNTERS_CFG_EVENT_SEL_MASK 0x0000003F
-#define NB_MC_PMU_COUNTERS_CFG_EVENT_SEL_SHIFT 0
-/* Enable setting of counter low overflow status bit:
-disable - 0x0: Disable setting.
-enable - 0x1: Enable setting. */
-#define NB_MC_PMU_COUNTERS_CFG_OVRF_LOW_STT_EN (1 << 6)
-/* Enable setting of counter high overflow status bit:
-disable - 0x0: Disable setting.
-enable - 0x1: Enable setting. */
-#define NB_MC_PMU_COUNTERS_CFG_OVRF_HIGH_STT_EN (1 << 7)
-/* Enable pause on trigger in assertion:
-disable - 0x0: Disable pause.
-enable - 0x1: Enable pause. */
-#define NB_MC_PMU_COUNTERS_CFG_TRIGIN_PAUSE_EN (1 << 8)
-/* Enable increment trigger out for trace.
-Trigger is generated whenever counter reaches <granule> value:
-disable - 0x0: Disable trigger out.
-enable - 0x1: Enable trigger out. */
-#define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_EN (1 << 9)
-/* Trigger out granule value
-Specifies the number of events counted between two consecutive trigger out events
-0x0: 1 - Trigger out on every event occurrence.
-0x1: 2 - Trigger out on every two events.
-...
-0xn: 2^(n-1) - Trigger out on event 2^(n-1) events.
-...
-0x1F: 2^31 */
-#define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_GRANULA_MASK 0x00007C00
-#define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_GRANULA_SHIFT 10
-/* Pause on overflow bitmask
-If set for counter <i>, current counter pauses counting when counter<i> is overflowed, including self-pause.
-Bit [16]: counter 0
-Bit [17]: counter 1
-Note: This field must be changed for larger counters. */
-#define NB_MC_PMU_COUNTERS_CFG_PAUSE_ON_OVRF_BITMASK_MASK 0x000F0000
-#define NB_MC_PMU_COUNTERS_CFG_PAUSE_ON_OVRF_BITMASK_SHIFT 16
-
-/**** Cntl register ****/
-/* Set the counter state to disable, enable, or pause:
-0x0 - disable: Disable counter.
-0x1 - enable: Enable counter.
-0x3 - pause: Pause counter. */
-#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_MASK 0x00000003
-#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT 0
-/* Disable counter. */
-#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_DISABLE \
-		(0x0 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT)
-/* Enable counter.  */
-#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_ENABLE \
-		(0x1 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT)
-/* Pause counter.  */
-#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_PAUSE \
-		(0x3 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT)
-
-/**** High register ****/
-/* Counter high value */
-#define NB_MC_PMU_COUNTERS_HIGH_COUNTER_MASK 0x0000FFFF
-#define NB_MC_PMU_COUNTERS_HIGH_COUNTER_SHIFT 0
-
-/**** version register ****/
-/*  Revision number (Minor) */
-#define NB_NB_VERSION_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
-#define NB_NB_VERSION_VERSION_RELEASE_NUM_MINOR_SHIFT 0
-/*  Revision number (Major) */
-#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
-#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
-/*  Date of release */
-#define NB_NB_VERSION_VERSION_DATE_DAY_MASK 0x001F0000
-#define NB_NB_VERSION_VERSION_DATE_DAY_SHIFT 16
-/*  Month of release */
-#define NB_NB_VERSION_VERSION_DATA_MONTH_MASK 0x01E00000
-#define NB_NB_VERSION_VERSION_DATA_MONTH_SHIFT 21
-/*  Year of release (starting from 2000) */
-#define NB_NB_VERSION_VERSION_DATE_YEAR_MASK 0x3E000000
-#define NB_NB_VERSION_VERSION_DATE_YEAR_SHIFT 25
-/*  Reserved */
-#define NB_NB_VERSION_VERSION_RESERVED_MASK 0xC0000000
-#define NB_NB_VERSION_VERSION_RESERVED_SHIFT 30
-
-/**** cpu_vmid register ****/
-/* Target VMID */
-#define NB_SRIOV_CPU_VMID_VAL_MASK      0x000000FF
-#define NB_SRIOV_CPU_VMID_VAL_SHIFT     0
-
-/**** DRAM_0_Control register ****/
-/* Controller Idle
-Indicates to the DDR PHY, if set, that the memory controller is idle */
-#define NB_DRAM_CHANNELS_DRAM_0_CONTROL_DDR_PHY_CTL_IDLE (1 << 0)
-/* Disable clear exclusive monitor request from DDR controller to CPU
-Clear request is triggered whenever an exlusive monitor inside the DDR controller is being invalidated. */
-#define NB_DRAM_CHANNELS_DRAM_0_CONTROL_DDR_EXMON_REQ_DIS (1 << 1)
-
-/**** DRAM_0_Status register ****/
-/* Bypass Mode: Indicates if set that the PHY is in PLL bypass mod */
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_DDR_PHY_BYP_MODE (1 << 0)
-/* Number of available AXI transactions (used positions) in the DDR controller read address FIFO. */
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_RAQ_WCOUNT_MASK 0x00000030
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_RAQ_WCOUNT_SHIFT 4
-/* Number of available AXI transactions (used positions) in the DDR controller write address FIFO */
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_WAQ_WCOUNT_0_MASK 0x000000C0
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_WAQ_WCOUNT_0_SHIFT 6
-/* Number of available Low priority read CAM slots (free positions) in  the DDR controller.
-Each slots holds a DRAM burst */
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_LPR_CREDIT_CNT_MASK 0x00007F00
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_LPR_CREDIT_CNT_SHIFT 8
-/* Number of available High priority read CAM slots (free positions) in  the DDR controller.
-Each slots holds a DRAM burst */
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_HPR_CREDIT_CNT_MASK 0x003F8000
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_HPR_CREDIT_CNT_SHIFT 15
-/* Number of available write CAM slots (free positions) in  the DDR controller.
-Each slots holds a DRAM burst */
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_WR_CREDIT_CNT_MASK 0x1FC00000
-#define NB_DRAM_CHANNELS_DRAM_0_STATUS_WR_CREDIT_CNT_SHIFT 22
-
-/**** DDR_Int_Cause register ****/
-/* This interrupt is asserted when a correctable ECC error is detected */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_ECC_CORRECTED_ERR (1 << 0)
-/* This interrupt is asserted when a uncorrectable ECC error is detected */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_ECC_UNCORRECTED_ERR (1 << 1)
-/* This interrupt is asserted when a parity or CRC error is detected on the DFI interface */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_DFI_ALERT_ERR (1 << 2)
-/* On-Chip Write data parity error interrupt on output */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_WDATA_OUT_ERR (1 << 3)
-/* This interrupt is asserted when a parity error due to MRS is detected on the DFI interface */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_DFI_ALERT_ERR_FATL (1 << 4)
-/* This interrupt is asserted when the CRC/parity retry counter reaches it maximum value */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_DFI_ALERT_ERR_MAX_REACHED (1 << 5)
-/* AXI Read address parity error interrupt.
-This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read address. */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_RADDR_ERR (1 << 6)
-/* AXI Read data parity error interrupt.
-This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read data */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_RDATA_ERR (1 << 7)
-/* AXI Write address parity error interrupt.
-This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write address. */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_WADDR_ERR (1 << 8)
-/* AXI Write data parity error interrupt on input.
-This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write data */
-#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_WDATA_IN_ERR (1 << 9)
-
-/**** Address_Map register ****/
-/* Controls which system address bit will be mapped to DDR row bit 2.
-This field is only used when addrmap_part_en == 1 */
-#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B2_MASK 0x0000000F
-#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B2_SHIFT 0
-/* Controls which system address bit will be mapped to DDR row bit 3.
-This field is only used when addrmap_part_en == 1 */
-#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B3_MASK 0x000003C0
-#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B3_SHIFT 6
-/* Controls which system address bit will be mapped to DDR row bit 4.
-This field is only used when addrmap_part_en == 1 */
-#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B4_MASK 0x0000F000
-#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B4_SHIFT 12
-/* Controls which system address bit will be mapped to DDR row bit 5.
-This field is only used when addrmap_part_en == 1 */
-#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B5_MASK 0x003C0000
-#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B5_SHIFT 18
-/* Enables partitioning of the address mapping control.
-When set, addrmap_row_b2-5 are used inside DDR controler instead of the built in address mapping registers */
-#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_PART_EN (1 << 31)
-
-/**** Reorder_ID_Mask register ****/
-/* DDR Read Reorder buffer ID mask.
-If incoming read transaction ID ANDed with mask is equal Reorder_ID_Value, then the transaction is mapped to the DDR controller bypass channel.
-Setting this register to 0 will disable the check */
-#define NB_DRAM_CHANNELS_REORDER_ID_MASK_MASK_MASK 0x003FFFFF
-#define NB_DRAM_CHANNELS_REORDER_ID_MASK_MASK_SHIFT 0
-
-/**** Reorder_ID_Value register ****/
-/* DDR Read Reorder buffer ID value
-If incoming read transaction ID ANDed with Reorder_ID_Mask is equal to this register, then the transaction is mapped to the DDR controller bypass channel */
-#define NB_DRAM_CHANNELS_REORDER_ID_VALUE_VALUE_MASK 0x003FFFFF
-#define NB_DRAM_CHANNELS_REORDER_ID_VALUE_VALUE_SHIFT 0
-
-/**** MRR_Control_Status register ****/
-/* DDR4 Mode Register Read Data Valid */
-#define NB_DRAM_CHANNELS_MRR_CONTROL_STATUS_MRR_VLD (1 << 0)
-/* MRR Ack, when asserted it clears the mrr_val indication and ready to load new MRR data. Write 1 to clear and then 0 */
-#define NB_DRAM_CHANNELS_MRR_CONTROL_STATUS_MRR_ACK (1 << 16)
-
-/**** pp_config register ****/
-/* Bypass PP module (formality equivalent) */
-#define NB_PUSH_PACKET_PP_CONFIG_FM_BYPASS (1 << 0)
-/* Bypass PP module */
-#define NB_PUSH_PACKET_PP_CONFIG_BYPASS  (1 << 1)
-/* Force Cleanup of entries */
-#define NB_PUSH_PACKET_PP_CONFIG_CLEAR   (1 << 2)
-/* Enable forwarding DECERR response */
-#define NB_PUSH_PACKET_PP_CONFIG_DECERR_EN (1 << 3)
-/* Enable forwarding SLVERR response */
-#define NB_PUSH_PACKET_PP_CONFIG_SLVERR_EN (1 << 4)
-/* Enable forwarding of data parity generation */
-#define NB_PUSH_PACKET_PP_CONFIG_PAR_GEN_EN (1 << 5)
-/* Select channel on 8K boundaries ([15:13]) instead of 64k boundaries ([18:16]). */
-#define NB_PUSH_PACKET_PP_CONFIG_SEL_8K  (1 << 6)
-/* Forces awuser to be as configured in ext_awuser register.
-Not functional */
-#define NB_PUSH_PACKET_PP_CONFIG_SEL_EXT_AWUSER (1 << 7)
-/* Enables PP channel.
-1 bit per channel */
-#define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_MASK 0x00030000
-#define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_SHIFT 16
-
-#define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE(i) \
-		(1 << (NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_SHIFT + i))
-
-/**** pp_ext_awuser register ****/
-/* Awuser to use on PP transactions
-Only applicable if config.sel_ext_awuser is set to 1'b1
-Parity bits are still generated per transaction */
-#define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_MASK 0x03FFFFFF
-#define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_SHIFT 0
-
-/**** pp_sel_awuser register ****/
-/* Select whether to use addr[63:48] or PP awmisc as vmid.
-Each bit if set to 1 selects the corresponding address bit. Otherwise, selects the corersponding awmis bit. */
-#define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_MASK 0x0000FFFF
-#define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_SHIFT 0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_NB_REGS_H__ */
-
-/** @} end of ... group */
-
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_pbs_regs.h b/sys/contrib/alpine-hal/eth/al_hal_pbs_regs.h
deleted file mode 100644
index b1f9c4f44d93..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_pbs_regs.h
+++ /dev/null
@@ -1,2751 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_pbs_regs.h
- *
- * @brief ... registers
- *
- */
-
-#ifndef __AL_HAL_PBS_REGS_H__
-#define __AL_HAL_PBS_REGS_H__
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-
-
-struct al_pbs_unit {
-	/* [0x0] Conf_bus, Configuration of the SB */
-	uint32_t conf_bus;
-	/* [0x4] PASW high */
-	uint32_t dram_0_nb_bar_high;
-	/* [0x8] PASW low */
-	uint32_t dram_0_nb_bar_low;
-	/* [0xc] PASW high */
-	uint32_t dram_1_nb_bar_high;
-	/* [0x10] PASW low */
-	uint32_t dram_1_nb_bar_low;
-	/* [0x14] PASW high */
-	uint32_t dram_2_nb_bar_high;
-	/* [0x18] PASW low */
-	uint32_t dram_2_nb_bar_low;
-	/* [0x1c] PASW high */
-	uint32_t dram_3_nb_bar_high;
-	/* [0x20] PASW low */
-	uint32_t dram_3_nb_bar_low;
-	/* [0x24] PASW high */
-	uint32_t msix_nb_bar_high;
-	/* [0x28] PASW low */
-	uint32_t msix_nb_bar_low;
-	/* [0x2c] PASW high */
-	uint32_t dram_0_sb_bar_high;
-	/* [0x30] PASW low */
-	uint32_t dram_0_sb_bar_low;
-	/* [0x34] PASW high */
-	uint32_t dram_1_sb_bar_high;
-	/* [0x38] PASW low */
-	uint32_t dram_1_sb_bar_low;
-	/* [0x3c] PASW high */
-	uint32_t dram_2_sb_bar_high;
-	/* [0x40] PASW low */
-	uint32_t dram_2_sb_bar_low;
-	/* [0x44] PASW high */
-	uint32_t dram_3_sb_bar_high;
-	/* [0x48] PASW low */
-	uint32_t dram_3_sb_bar_low;
-	/* [0x4c] PASW high */
-	uint32_t msix_sb_bar_high;
-	/* [0x50] PASW low */
-	uint32_t msix_sb_bar_low;
-	/* [0x54] PASW high */
-	uint32_t pcie_mem0_bar_high;
-	/* [0x58] PASW low */
-	uint32_t pcie_mem0_bar_low;
-	/* [0x5c] PASW high */
-	uint32_t pcie_mem1_bar_high;
-	/* [0x60] PASW low */
-	uint32_t pcie_mem1_bar_low;
-	/* [0x64] PASW high */
-	uint32_t pcie_mem2_bar_high;
-	/* [0x68] PASW low */
-	uint32_t pcie_mem2_bar_low;
-	/* [0x6c] PASW high */
-	uint32_t pcie_ext_ecam0_bar_high;
-	/* [0x70] PASW low */
-	uint32_t pcie_ext_ecam0_bar_low;
-	/* [0x74] PASW high */
-	uint32_t pcie_ext_ecam1_bar_high;
-	/* [0x78] PASW low */
-	uint32_t pcie_ext_ecam1_bar_low;
-	/* [0x7c] PASW high */
-	uint32_t pcie_ext_ecam2_bar_high;
-	/* [0x80] PASW low */
-	uint32_t pcie_ext_ecam2_bar_low;
-	/* [0x84] PASW high */
-	uint32_t pbs_nor_bar_high;
-	/* [0x88] PASW low */
-	uint32_t pbs_nor_bar_low;
-	/* [0x8c] PASW high */
-	uint32_t pbs_spi_bar_high;
-	/* [0x90] PASW low */
-	uint32_t pbs_spi_bar_low;
-	uint32_t rsrvd_0[3];
-	/* [0xa0] PASW high */
-	uint32_t pbs_nand_bar_high;
-	/* [0xa4] PASW low */
-	uint32_t pbs_nand_bar_low;
-	/* [0xa8] PASW high */
-	uint32_t pbs_int_mem_bar_high;
-	/* [0xac] PASW low */
-	uint32_t pbs_int_mem_bar_low;
-	/* [0xb0] PASW high */
-	uint32_t pbs_boot_bar_high;
-	/* [0xb4] PASW low */
-	uint32_t pbs_boot_bar_low;
-	/* [0xb8] PASW high */
-	uint32_t nb_int_bar_high;
-	/* [0xbc] PASW low */
-	uint32_t nb_int_bar_low;
-	/* [0xc0] PASW high */
-	uint32_t nb_stm_bar_high;
-	/* [0xc4] PASW low */
-	uint32_t nb_stm_bar_low;
-	/* [0xc8] PASW high */
-	uint32_t pcie_ecam_int_bar_high;
-	/* [0xcc] PASW low */
-	uint32_t pcie_ecam_int_bar_low;
-	/* [0xd0] PASW high */
-	uint32_t pcie_mem_int_bar_high;
-	/* [0xd4] PASW low */
-	uint32_t pcie_mem_int_bar_low;
-	/* [0xd8] Control */
-	uint32_t winit_cntl;
-	/* [0xdc] Control */
-	uint32_t latch_bars;
-	/* [0xe0] Control */
-	uint32_t pcie_conf_0;
-	/* [0xe4] Control */
-	uint32_t pcie_conf_1;
-	/* [0xe8] Control */
-	uint32_t serdes_mux_pipe;
-	/* [0xec] Control */
-	uint32_t dma_io_master_map;
-	/* [0xf0] Status */
-	uint32_t i2c_pld_status_high;
-	/* [0xf4] Status */
-	uint32_t i2c_pld_status_low;
-	/* [0xf8] Status */
-	uint32_t spi_dbg_status_high;
-	/* [0xfc] Status */
-	uint32_t spi_dbg_status_low;
-	/* [0x100] Status */
-	uint32_t spi_mst_status_high;
-	/* [0x104] Status */
-	uint32_t spi_mst_status_low;
-	/* [0x108] Log */
-	uint32_t mem_pbs_parity_err_high;
-	/* [0x10c] Log */
-	uint32_t mem_pbs_parity_err_low;
-	/* [0x110] Log */
-	uint32_t boot_strap;
-	/* [0x114] Conf */
-	uint32_t cfg_axi_conf_0;
-	/* [0x118] Conf */
-	uint32_t cfg_axi_conf_1;
-	/* [0x11c] Conf */
-	uint32_t cfg_axi_conf_2;
-	/* [0x120] Conf */
-	uint32_t cfg_axi_conf_3;
-	/* [0x124] Conf */
-	uint32_t spi_mst_conf_0;
-	/* [0x128] Conf */
-	uint32_t spi_mst_conf_1;
-	/* [0x12c] Conf */
-	uint32_t spi_slv_conf_0;
-	/* [0x130] Conf */
-	uint32_t apb_mem_conf_int;
-	/* [0x134] PASW remap register */
-	uint32_t sb2nb_cfg_dram_remap;
-	/* [0x138] Control */
-	uint32_t pbs_mux_sel_0;
-	/* [0x13c] Control */
-	uint32_t pbs_mux_sel_1;
-	/* [0x140] Control */
-	uint32_t pbs_mux_sel_2;
-	/* [0x144] Control */
-	uint32_t pbs_mux_sel_3;
-	/* [0x148] PASW high */
-	uint32_t sb_int_bar_high;
-	/* [0x14c] PASW low */
-	uint32_t sb_int_bar_low;
-	/* [0x150] log */
-	uint32_t ufc_pbs_parity_err_high;
-	/* [0x154] log */
-	uint32_t ufc_pbs_parity_err_low;
-	/* [0x158] Cntl - internal */
-	uint32_t gen_conf;
-	/* [0x15c] Device ID and Rev ID */
-	uint32_t chip_id;
-	/* [0x160] Status - internal */
-	uint32_t uart0_debug;
-	/* [0x164] Status - internal */
-	uint32_t uart1_debug;
-	/* [0x168] Status - internal */
-	uint32_t uart2_debug;
-	/* [0x16c] Status - internal */
-	uint32_t uart3_debug;
-	/* [0x170] Control - internal */
-	uint32_t uart0_conf_status;
-	/* [0x174] Control - internal */
-	uint32_t uart1_conf_status;
-	/* [0x178] Control - internal */
-	uint32_t uart2_conf_status;
-	/* [0x17c] Control - internal */
-	uint32_t uart3_conf_status;
-	/* [0x180] Control - internal */
-	uint32_t gpio0_conf_status;
-	/* [0x184] Control - internal */
-	uint32_t gpio1_conf_status;
-	/* [0x188] Control - internal */
-	uint32_t gpio2_conf_status;
-	/* [0x18c] Control - internal */
-	uint32_t gpio3_conf_status;
-	/* [0x190] Control - internal */
-	uint32_t gpio4_conf_status;
-	/* [0x194] Control - internal */
-	uint32_t i2c_gen_conf_status;
-	/* [0x198] Control - internal */
-	uint32_t i2c_gen_debug;
-	/* [0x19c] Cntl */
-	uint32_t watch_dog_reset_out;
-	/* [0x1a0] Cntl */
-	uint32_t otp_magic_num;
-	/*
-	 * [0x1a4] Control - internal
-	 */
-	uint32_t otp_cntl;
-	/* [0x1a8] Cfg - internal */
-	uint32_t otp_cfg_0;
-	/* [0x1ac] Cfg - internal */
-	uint32_t otp_cfg_1;
-	/* [0x1b0] Cfg - internal */
-	uint32_t otp_cfg_3;
-	/* [0x1b4] Cfg */
-	uint32_t cfg_nand_0;
-	/* [0x1b8] Cfg */
-	uint32_t cfg_nand_1;
-	/* [0x1bc] Cfg-- timing parameters internal. */
-	uint32_t cfg_nand_2;
-	/* [0x1c0] Cfg - internal */
-	uint32_t cfg_nand_3;
-	/* [0x1c4] PASW high */
-	uint32_t nb_nic_regs_bar_high;
-	/* [0x1c8] PASW low */
-	uint32_t nb_nic_regs_bar_low;
-	/* [0x1cc] PASW high */
-	uint32_t sb_nic_regs_bar_high;
-	/* [0x1d0] PASW low */
-	uint32_t sb_nic_regs_bar_low;
-	/* [0x1d4] Control */
-	uint32_t serdes_mux_multi_0;
-	/* [0x1d8] Control */
-	uint32_t serdes_mux_multi_1;
-	/* [0x1dc] Control - not in use any more - internal */
-	uint32_t pbs_ulpi_mux_conf;
-	/* [0x1e0] Cntl */
-	uint32_t wr_once_dbg_dis_ovrd_reg;
-	/* [0x1e4] Cntl - internal */
-	uint32_t gpio5_conf_status;
-	/* [0x1e8] PASW high */
-	uint32_t pcie_mem3_bar_high;
-	/* [0x1ec] PASW low */
-	uint32_t pcie_mem3_bar_low;
-	/* [0x1f0] PASW high */
-	uint32_t pcie_mem4_bar_high;
-	/* [0x1f4] PASW low */
-	uint32_t pcie_mem4_bar_low;
-	/* [0x1f8] PASW high */
-	uint32_t pcie_mem5_bar_high;
-	/* [0x1fc] PASW low */
-	uint32_t pcie_mem5_bar_low;
-	/* [0x200] PASW high */
-	uint32_t pcie_ext_ecam3_bar_high;
-	/* [0x204] PASW low */
-	uint32_t pcie_ext_ecam3_bar_low;
-	/* [0x208] PASW high */
-	uint32_t pcie_ext_ecam4_bar_high;
-	/* [0x20c] PASW low */
-	uint32_t pcie_ext_ecam4_bar_low;
-	/* [0x210] PASW high */
-	uint32_t pcie_ext_ecam5_bar_high;
-	/* [0x214] PASW low */
-	uint32_t pcie_ext_ecam5_bar_low;
-	/* [0x218] PASW high */
-	uint32_t low_latency_sram_bar_high;
-	/* [0x21c] PASW low */
-	uint32_t low_latency_sram_bar_low;
-	/* [0x220] Control */
-	uint32_t pbs_mux_sel_4;
-	/* [0x224] Control */
-	uint32_t pbs_mux_sel_5;
-	/* [0x228] Control */
-	uint32_t serdes_mux_eth;
-	/* [0x22c] Control */
-	uint32_t serdes_mux_pcie;
-	/* [0x230] Control */
-	uint32_t serdes_mux_sata;
-	uint32_t rsrvd[7];
-};
-struct al_pbs_low_latency_sram_remap {
-	/* [0x0] PBS MEM Remap */
-	uint32_t bar1_orig;
-	/* [0x4] PBS MEM Remap */
-	uint32_t bar1_remap;
-	/* [0x8] ETH0 MEM Remap */
-	uint32_t bar2_orig;
-	/* [0xc] ETH0 MEM Remap */
-	uint32_t bar2_remap;
-	/* [0x10] ETH1 MEM Remap */
-	uint32_t bar3_orig;
-	/* [0x14] ETH1 MEM Remap */
-	uint32_t bar3_remap;
-	/* [0x18] ETH2 MEM Remap */
-	uint32_t bar4_orig;
-	/* [0x1c] ETH2 MEM Remap */
-	uint32_t bar4_remap;
-	/* [0x20] ETH3 MEM Remap */
-	uint32_t bar5_orig;
-	/* [0x24] ETH3 MEM Remap */
-	uint32_t bar5_remap;
-	/* [0x28] CRYPTO0 MEM Remap */
-	uint32_t bar6_orig;
-	/* [0x2c] CRYPTO0 MEM Remap */
-	uint32_t bar6_remap;
-	/* [0x30] RAID0 MEM Remap */
-	uint32_t bar7_orig;
-	/* [0x34] RAID0 MEM Remap */
-	uint32_t bar7_remap;
-	/* [0x38] CRYPTO1 MEM Remap */
-	uint32_t bar8_orig;
-	/* [0x3c] CRYPTO1 MEM Remap */
-	uint32_t bar8_remap;
-	/* [0x40] RAID1 MEM Remap */
-	uint32_t bar9_orig;
-	/* [0x44] RAID2 MEM Remap */
-	uint32_t bar9_remap;
-	/* [0x48] RESERVED MEM Remap */
-	uint32_t bar10_orig;
-	/* [0x4c] RESERVED MEM Remap */
-	uint32_t bar10_remap;
-};
-struct al_pbs_target_id_enforcement {
-	/* [0x0] target enforcement */
-	uint32_t cpu;
-	/* [0x4] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t cpu_mask;
-	/* [0x8] target enforcement */
-	uint32_t debug_nb;
-	/* [0xc] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t debug_nb_mask;
-	/* [0x10] target enforcement */
-	uint32_t debug_sb;
-	/* [0x14] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t debug_sb_mask;
-	/* [0x18] target enforcement */
-	uint32_t eth_0;
-	/* [0x1c] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t eth_0_mask;
-	/* [0x20] target enforcement */
-	uint32_t eth_1;
-	/* [0x24] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t eth_1_mask;
-	/* [0x28] target enforcement */
-	uint32_t eth_2;
-	/* [0x2c] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t eth_2_mask;
-	/* [0x30] target enforcement */
-	uint32_t eth_3;
-	/* [0x34] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t eth_3_mask;
-	/* [0x38] target enforcement */
-	uint32_t sata_0;
-	/* [0x3c] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t sata_0_mask;
-	/* [0x40] target enforcement */
-	uint32_t sata_1;
-	/* [0x44] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t sata_1_mask;
-	/* [0x48] target enforcement */
-	uint32_t crypto_0;
-	/* [0x4c] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t crypto_0_mask;
-	/* [0x50] target enforcement */
-	uint32_t crypto_1;
-	/* [0x54] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t crypto_1_mask;
-	/* [0x58] target enforcement */
-	uint32_t pcie_0;
-	/* [0x5c] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t pcie_0_mask;
-	/* [0x60] target enforcement */
-	uint32_t pcie_1;
-	/* [0x64] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t pcie_1_mask;
-	/* [0x68] target enforcement */
-	uint32_t pcie_2;
-	/* [0x6c] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t pcie_2_mask;
-	/* [0x70] target enforcement */
-	uint32_t pcie_3;
-	/* [0x74] target enforcement mask (bits which are 0 are not compared) */
-	uint32_t pcie_3_mask;
-	/* [0x78] Control */
-	uint32_t latch;
-	uint32_t rsrvd[9];
-};
-
-struct al_pbs_regs {
-	struct al_pbs_unit unit;                                /* [0x0] */
-struct al_pbs_low_latency_sram_remap low_latency_sram_remap;
-/* [0x250] */
-	uint32_t rsrvd_0[88];
-	struct al_pbs_target_id_enforcement target_id_enforcement; /* [0x400] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** conf_bus register ****/
-/* Read slave error enable */
-#define PBS_UNIT_CONF_BUS_RD_SLVERR_EN   (1 << 0)
-/* Write slave error enable */
-#define PBS_UNIT_CONF_BUS_WR_SLVERR_EN   (1 << 1)
-/* Read decode error enable */
-#define PBS_UNIT_CONF_BUS_RD_DECERR_EN   (1 << 2)
-/* Write decode error enable */
-#define PBS_UNIT_CONF_BUS_WR_DECERR_EN   (1 << 3)
-/* For debug clear the APB SM */
-#define PBS_UNIT_CONF_BUS_CLR_APB_FSM    (1 << 4)
-/* For debug clear the WFIFO */
-#define PBS_UNIT_CONF_BUS_CLR_WFIFO_CLEAR (1 << 5)
-/* Arbiter between read and write channel */
-#define PBS_UNIT_CONF_BUS_WRR_CNT_MASK   0x000001C0
-#define PBS_UNIT_CONF_BUS_WRR_CNT_SHIFT  6
-
-
-/* general PASWS */
-/* window size = 2 ^ (15 + win_size), zero value disable the win ... */
-#define PBS_PASW_WIN_SIZE_MASK 0x0000003F
-#define PBS_PASW_WIN_SIZE_SHIFT 0
-/* reserved fields */
-#define PBS_PASW_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_PASW_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_PASW_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_PASW_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** dram_0_nb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** dram_1_nb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** dram_2_nb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** dram_3_nb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** msix_nb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** dram_0_sb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** dram_1_sb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** dram_2_sb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** dram_3_sb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** msix_sb_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_mem0_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_mem1_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_mem2_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_ext_ecam0_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_ext_ecam1_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_ext_ecam2_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pbs_nor_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pbs_spi_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pbs_nand_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pbs_int_mem_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pbs_boot_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** nb_int_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** nb_stm_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_ecam_int_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_mem_int_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** winit_cntl register ****/
-/* When set, enables access to winit regs, in normal mode. */
-#define PBS_UNIT_WINIT_CNTL_ENABLE_WINIT_REGS_ACCESS (1 << 0)
-/* Reserved */
-#define PBS_UNIT_WINIT_CNTL_RSRVD_MASK   0xFFFFFFFE
-#define PBS_UNIT_WINIT_CNTL_RSRVD_SHIFT  1
-
-/**** latch_bars register ****/
-/*
- * Software clears this bit before any bar update, and set it after all bars
- * updated.
- */
-#define PBS_UNIT_LATCH_BARS_ENABLE       (1 << 0)
-/* Reserved */
-#define PBS_UNIT_LATCH_BARS_RSRVD_MASK   0xFFFFFFFE
-#define PBS_UNIT_LATCH_BARS_RSRVD_SHIFT  1
-
-/**** pcie_conf_0 register ****/
-/* NOT_use, config internal inside each PCIe core */
-#define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_MASK 0x00000FFF
-#define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_SHIFT 0
-/* sys_aux_det value */
-#define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_MASK 0x00007000
-#define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_SHIFT 12
-/* Reserved */
-#define PBS_UNIT_PCIE_CONF_0_RSRVD_MASK  0xFFFF8000
-#define PBS_UNIT_PCIE_CONF_0_RSRVD_SHIFT 15
-
-/**** pcie_conf_1 register ****/
-/*
- * Which PCIe exists? The PCIe device is under reset until the corresponding bit
- * is set.
- */
-#define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_MASK 0x0000003F
-#define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT 0
-/* Reserved */
-#define PBS_UNIT_PCIE_CONF_1_RSRVD_MASK  0xFFFFFFC0
-#define PBS_UNIT_PCIE_CONF_1_RSRVD_SHIFT 6
-
-/**** serdes_mux_pipe register ****/
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_MASK 0x00000007
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_SHIFT 0
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_3 (1 << 3)
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_MASK 0x00000070
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_SHIFT 4
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_7 (1 << 7)
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_MASK 0x00000300
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_SHIFT 8
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_MASK 0x00000C00
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_SHIFT 10
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_MASK 0x00003000
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_SHIFT 12
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_MASK 0x0000C000
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_SHIFT 14
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_MASK 0x00030000
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_SHIFT 16
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_MASK 0x000C0000
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_SHIFT 18
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_MASK 0x00300000
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_SHIFT 20
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_MASK 0x00C00000
-#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_SHIFT 22
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_MASK 0x07000000
-#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_SHIFT 24
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_MASK 0xF8000000
-#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_SHIFT 27
-
-/*
- * 2'b01 - select pcie_b[0]
- * 2'b10 - select pcie_a[2]
- */
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_SHIFT 0
-/*
- * 2'b01 - select pcie_b[1]
- * 2'b10 - select pcie_a[3]
- */
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_MASK 0x00000030
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_SHIFT 4
-/*
- * 2'b01 - select pcie_b[0]
- * 2'b10 - select pcie_a[4]
- */
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_MASK 0x00000300
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_SHIFT 8
-/*
- * 2'b01 - select pcie_b[1]
- * 2'b10 - select pcie_a[5]
- */
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_MASK 0x00003000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_SHIFT 12
-/*
- * 2'b01 - select pcie_b[2]
- * 2'b10 - select pcie_a[6]
- */
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_MASK 0x00030000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_SHIFT 16
-/*
- * 2'b01 - select pcie_b[3]
- * 2'b10 - select pcie_a[7]
- */
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_MASK 0x00300000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_SHIFT 20
-/*
- * 2'b01 - select pcie_d[0]
- * 2'b10 - select pcie_c[2]
- */
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_MASK 0x03000000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_SHIFT 24
-/*
- * 2'b01 - select pcie_d[1]
- * 2'b10 - select pcie_c[3]
- */
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_MASK 0x30000000
-#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_SHIFT 28
-
-/**** dma_io_master_map register ****/
-/*
- * [0]: When set, maps all the io_dma transactions to the NB/DRAM, regardless of
- * the window hit.
- * [1]: When set, maps all the eth_0 transactions to the NB/DRAM, regardless of
- * the window hit.
- * [2]: When set, maps all the eth_2 transaction to the NB/DRAM, regardless of
- * the window hit.
- * [3]: When set, maps all the sata_0 transactions to the NB/DRAM, regardless of
- * the window hit.
- * [4]: When set, maps all the sata_1 transactions to the NB/DRAM, regardless of
- * the window hit.
- * [5]: When set, maps all the pcie_0 master transactions to the NB/DRAM,
- * regardless of the window hit.
- * [6]: When set, maps all the SPI debug port transactions to the NB/DRAM,
- * regardless of the window hit.
- * [7]: When set, maps all the CPU debug port transactions to the NB/DRAM,
- * regardless of the window hit.
- * [8] When set, maps all the Crypto transactions to the NB/DRAM, regardless of
- * the window hit.
- * [15:9] - Reserved
- */
-#define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_MASK 0x0000FFFF
-#define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_MASK 0xFFFF0000
-#define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_SHIFT 16
-
-/**** i2c_pld_status_high register ****/
-/* I2C pre-load status  */
-#define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_MASK 0x000000FF
-#define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_SHIFT 0
-
-/**** spi_dbg_status_high register ****/
-/* SPI DBG load status */
-#define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_MASK 0x000000FF
-#define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_SHIFT 0
-
-/**** spi_mst_status_high register ****/
-/* SP IMST load status */
-#define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_MASK 0x000000FF
-#define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_SHIFT 0
-
-/**** mem_pbs_parity_err_high register ****/
-/* Address latch in the case of a parity error */
-#define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF
-#define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0
-
-/**** cfg_axi_conf_0 register ****/
-/* Sets the AXI field in the I2C preloader  interface. */
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_MASK 0x0000007F
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_SHIFT 0
-/* Sets the AXI field in the I2C preloader  interface. */
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_MASK 0x00003F80
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_SHIFT 7
-/* Sets the AXI field in the I2C preloader  interface. */
-#define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_MASK 0x001FC000
-#define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_SHIFT 14
-/* Sets the AXI field in the SPI debug interface. */
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_MASK 0x01E00000
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_SHIFT 21
-/* Sets the AXI field in the SPI debug interface. */
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_MASK 0x1E000000
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_SHIFT 25
-/* Sets the AXI field in the SPI debug interface. */
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_MASK 0xE0000000
-#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_SHIFT 29
-
-/**** cfg_axi_conf_1 register ****/
-/* Sets the AXI field in the SPI debug interface. */
-#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_MASK 0x03FFFFFF
-#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_SHIFT 0
-/* Sets the AXI field in the SPI debug interface. */
-#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_MASK 0x3C000000
-#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_SHIFT 26
-
-/**** cfg_axi_conf_2 register ****/
-/* Sets the AXI field in the SPI debug interface. */
-#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_MASK 0x03FFFFFF
-#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_SHIFT 0
-/* Sets the AXI field in the SPI debug interface. */
-#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_MASK 0x3C000000
-#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_SHIFT 26
-
-/**** spi_mst_conf_0 register ****/
-/*
- * Sets the SPI master Configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SRL (1 << 0)
-/*
- * Sets the SPI master Configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPOL (1 << 1)
-/*
- * Sets the SPI master Configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPH (1 << 2)
-/*
- * Set the SPI master configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_MASK 0x00000078
-#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_SHIFT 3
-/*
- * Set the SPI master configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_MASK 0x007FFF80
-#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_SHIFT 7
-/*
- * Sets the SPI master configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_MASK 0x7F800000
-#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_SHIFT 23
-
-/**** spi_mst_conf_1 register ****/
-/*
- * Sets the SPI master Configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_MASK 0x000000FF
-#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_SHIFT 0
-/*
- * Sets the SPI master Configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_MASK 0x00000700
-#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_SHIFT 8
-/*
- * Sets the SPI master Configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_MASK 0x00001800
-#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_SHIFT 11
-/*
- * Sets the SPI master Configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_FAST_RD (1 << 13)
-
-/**** spi_slv_conf_0 register ****/
-/*
- * Sets the SPI slave configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_MASK 0x0000FFFF
-#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_SHIFT 0
-/* Value. The reset value is according to bootstrap. */
-#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPOL (1 << 16)
-/* Value. The reset value is according to bootstrap. */
-#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPH (1 << 17)
-/*
- * Sets the SPI slave configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_MASK 0x03FC0000
-#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_SHIFT 18
-/*
- * Sets the SPI slave configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SRL (1 << 26)
-/*
- * Sets the SPI slave configuration. For details see the SPI section in the
- * documentation.
- */
-#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_MASK 0x18000000
-#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_SHIFT 27
-
-/**** apb_mem_conf_int register ****/
-/* Value-- internal */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_MASK 0x00000007
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_SHIFT 0
-/* Value-- internal */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_APB_MIX_ARB (1 << 3)
-/* Value-- internal */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_APB_MIX_ARB (1 << 4)
-/* Value-- internal */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_APB_MIX_ARB (1 << 5)
-/* Value-- internal */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_CLEAR_FSM (1 << 6)
-/* Value-- internal */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_CLEAR_FSM (1 << 7)
-/* Value-- internal */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_CLEAR_FSM (1 << 8)
-/* Value-- internal */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FSM_CLEAR (1 << 9)
-/* Value-- internal */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FIFOS_CLEAR (1 << 10)
-/* Enables parity protection on the integrated SRAM. */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_BOOTROM_PARITY_EN (1 << 11)
-/*
- * When set, reports a slave error whenthe slave returns an AXI slave error, for
- * configuration access to the internal configuration space.
- */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_SLV_ERR_EN (1 << 12)
-/*
- * When set, reports a decode error when timeout has occurred for configuration
- * access to the internal configuration space.
- */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_DEC_ERR_EN (1 << 13)
-/*
- * When set, reports a slave error, when the slave returns an AXI slave error,
- * for configuration access to the internal configuration space.
- */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_SLV_ERR_EN (1 << 14)
-/*
- * When set, reports a decode error when timeout has occurred for configuration
- * access to the internal configuration space.
- */
-#define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_DEC_ERR_EN (1 << 15)
-
-/**** sb_int_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** ufc_pbs_parity_err_high register ****/
-/*
- * Address latch in the case of a parity error in the Flash Controller internal
- * memories.
- */
-#define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF
-#define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0
-
-/**** chip_id register ****/
-/* [15:0] : Dev Rev ID */
-#define PBS_UNIT_CHIP_ID_DEV_REV_ID_MASK 0x0000FFFF
-#define PBS_UNIT_CHIP_ID_DEV_REV_ID_SHIFT 0
-/* [31:16] : 0x0 - Dev ID */
-#define PBS_UNIT_CHIP_ID_DEV_ID_MASK     0xFFFF0000
-#define PBS_UNIT_CHIP_ID_DEV_ID_SHIFT    16
-
-#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE       	0
-#define PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK		1
-#define PBS_UNIT_CHIP_ID_DEV_ID_COYOTE			2
-
-/**** uart0_conf_status register ****/
-/*
- * Conf:
- * // [0] -- DSR_N RW bit
- * // [1] -- DCD_N RW bit
- * // [2] -- RI_N bit
- * // [3] -- dma_tx_ack_n
- * // [4] -- dma_rx_ack_n
- */
-#define PBS_UNIT_UART0_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_UART0_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status:
- * // [16] -- dtr_n RO bit
- * // [17] -- OUT1_N RO bit
- * // [18] -- OUT2_N RO bit
- * // [19] -- dma_tx_req_n RO bit
- * // [20] -- dma_tx_single_n RO bit
- * // [21] -- dma_rx_req_n RO bit
- * // [22] -- dma_rx_single_n RO bit
- * // [23] -- uart_lp_req_pclk RO bit
- * // [24] -- baudout_n RO bit
- */
-#define PBS_UNIT_UART0_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_UART0_CONF_STATUS_STATUS_SHIFT 16
-
-/**** uart1_conf_status register ****/
-/*
- * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3]
- * -- dma_tx_ack_n // [4] - dma_rx_ack_n
- */
-#define PBS_UNIT_UART1_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_UART1_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO
- * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21]
- * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] --
- * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit
- */
-#define PBS_UNIT_UART1_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_UART1_CONF_STATUS_STATUS_SHIFT 16
-
-/**** uart2_conf_status register ****/
-/*
- * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3]
- * -- dma_tx_ack_n // [4] - dma_rx_ack_n
- */
-#define PBS_UNIT_UART2_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_UART2_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO
- * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21]
- * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] --
- * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit
- */
-#define PBS_UNIT_UART2_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_UART2_CONF_STATUS_STATUS_SHIFT 16
-
-/**** uart3_conf_status register ****/
-/*
- * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3]
- * -- dma_tx_ack_n // [4] - dma_rx_ack_n
- */
-#define PBS_UNIT_UART3_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_UART3_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO
- * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21]
- * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] --
- * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit
- */
-#define PBS_UNIT_UART3_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_UART3_CONF_STATUS_STATUS_SHIFT 16
-
-/**** gpio0_conf_status register ****/
-/*
- * Cntl:
- * //  [7:0] nGPAFEN;              // from regfile
- * //  [15:8] GPAFOUT;             // from regfile
- */
-#define PBS_UNIT_GPIO0_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_GPIO0_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status:
- * //  [24:16] GPAFIN;             // to regfile
- */
-#define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_SHIFT 16
-
-/**** gpio1_conf_status register ****/
-/*
- * Cntl:
- * //  [7:0] nGPAFEN;              // from regfile
- * //  [15:8] GPAFOUT;             // from regfile
- */
-#define PBS_UNIT_GPIO1_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_GPIO1_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status:
- * //  [24:16] GPAFIN;             // to regfile
- */
-#define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_SHIFT 16
-
-/**** gpio2_conf_status register ****/
-/*
- * Cntl:
- * //  [7:0] nGPAFEN;              // from regfile
- * //  [15:8] GPAFOUT;             // from regfile
- */
-#define PBS_UNIT_GPIO2_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_GPIO2_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status:
- * //  [24:16] GPAFIN;             // to regfile
- */
-#define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_SHIFT 16
-
-/**** gpio3_conf_status register ****/
-/*
- * Cntl:
- * //  [7:0] nGPAFEN;              // from regfile
- * //  [15:8] GPAFOUT;             // from regfile
- */
-#define PBS_UNIT_GPIO3_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_GPIO3_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status:
- * //  [24:16] GPAFIN;             // to regfile
- */
-#define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_SHIFT 16
-
-/**** gpio4_conf_status register ****/
-/*
- * Cntl:
- * //  [7:0] nGPAFEN;              // from regfile
- * //  [15:8] GPAFOUT;             // from regfile
- */
-#define PBS_UNIT_GPIO4_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_GPIO4_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status:
- * //  [24:16] GPAFIN;             // to regfile
- */
-#define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_SHIFT 16
-
-/**** i2c_gen_conf_status register ****/
-/*
- * cntl
- * // [0] -- dma_tx_ack
- * // [1] -- dma_rx_ack
- */
-#define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_SHIFT 0
-/*
- * Status
- *
- * // [16] -- dma_tx_req RO bit
- * // [17] -- dma_tx_single RO bit
- * // [18] -- dma_rx_req RO bit
- * // [19] -- dma_rx_single RO bit
- */
-#define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_SHIFT 16
-
-/**** watch_dog_reset_out register ****/
-/*
- * [0] If set to 1'b1, WD0 cannot generate reset_out_n
- * [1] If set to 1'b1, WD1 cannot generate reset_out_n
- * [2] If set to 1'b1, WD2 cannot generate reset_out_n
- * [3] If set to 1'b1, WD3 cannot generate reset_out_n
- * [4] If set to 1'b1, WD4 cannot generate reset_out_n
- * [5] If set to 1'b1, WD5 cannot generate reset_out_n
- * [6] If set to 1'b1, WD6 cannot generate reset_out_n
- * [7] If set to 1'b1, WD7 cannot generate reset_out_n
- */
-#define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_MASK 0x000000FF
-#define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_SHIFT 0
-
-/**** otp_cntl register ****/
-/* from reg file Config To bypass the copy from OTPW to OTPR */
-#define PBS_UNIT_OTP_CNTL_IGNORE_OTPW    (1 << 0)
-/* Not in use.Comes from bond. */
-#define PBS_UNIT_OTP_CNTL_IGNORE_PRELOAD (1 << 1)
-/* Margin read from the fuse box */
-#define PBS_UNIT_OTP_CNTL_OTPW_MARGIN_READ (1 << 2)
-/* Indicates when OTPis  busy.  */
-#define PBS_UNIT_OTP_CNTL_OTP_BUSY       (1 << 3)
-
-/**** otp_cfg_0 register ****/
-/* Cfg  to OTP cntl. */
-#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_MASK 0x0000FFFF
-#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_SHIFT 0
-/* Cfg  to OTP cntl. */
-#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_MASK 0xFFFF0000
-#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_SHIFT 16
-
-/**** otp_cfg_1 register ****/
-/* Cfg  to OTP cntl.  */
-#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_MASK 0x0000FFFF
-#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_SHIFT 0
-/* Cfg  to OTP cntl. */
-#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_MASK 0xFFFF0000
-#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_SHIFT 16
-
-/**** otp_cfg_3 register ****/
-/* Cfg  to OTP cntl. */
-#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_MASK 0x0000FFFF
-#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_SHIFT 0
-/* Cfg  to OTP cntl. */
-#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_MASK 0xFFFF0000
-#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_SHIFT 16
-
-/**** nb_nic_regs_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** sb_nic_regs_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6
-/* bar low address 16 MSB bits */
-#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** serdes_mux_multi_0 register ****/
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_MASK 0x00000007
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_SHIFT 0
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_3 (1 << 3)
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_MASK 0x00000070
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_SHIFT 4
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_7 (1 << 7)
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_MASK 0x00000700
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_SHIFT 8
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_11 (1 << 11)
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_MASK 0x00007000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_SHIFT 12
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_15 (1 << 15)
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_MASK 0x00030000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_SHIFT 16
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_MASK 0x000C0000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_SHIFT 18
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_MASK 0x00300000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_SHIFT 20
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_MASK 0x00C00000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_SHIFT 22
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_MASK 0xFF000000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_SHIFT 24
-
-/*
- * 2'b01 - select sata_b[0]
- * 2'b10 - select eth_a[0]
- */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_SHIFT 0
-/*
- * 3'b001 - select sata_b[1]
- * 3'b010 - select eth_b[0]
- * 3'b100 - select eth_a[1]
- */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_MASK 0x00000070
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_SHIFT 4
-/*
- * 3'b001 - select sata_b[2]
- * 3'b010 - select eth_c[0]
- * 3'b100 - select eth_a[2]
- */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_MASK 0x00000700
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_SHIFT 8
-/*
- * 3'b001 - select sata_b[3]
- * 3'b010 - select eth_d[0]
- * 3'b100 - select eth_a[3]
- */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_MASK 0x00007000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_SHIFT 12
-/*
- * 2'b01 - select eth_a[0]
- * 2'b10 - select sata_a[0]
- */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_MASK 0x00030000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_SHIFT 16
-/*
- * 3'b001 - select eth_b[0]
- * 3'b010 - select eth_c[1]
- * 3'b100 - select sata_a[1]
- */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_MASK 0x00700000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_SHIFT 20
-/*
- * 3'b001 - select eth_a[0]
- * 3'b010 - select eth_c[2]
- * 3'b100 - select sata_a[2]
- */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_MASK 0x07000000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_SHIFT 24
-/*
- * 3'b001 - select eth_d[0]
- * 3'b010 - select eth_c[3]
- * 3'b100 - select sata_a[3]
- */
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_MASK 0x70000000
-#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_SHIFT 28
-
-/**** serdes_mux_multi_1 register ****/
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_SHIFT 0
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_MASK 0x0000000C
-#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_SHIFT 2
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_MASK 0x00000070
-#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_SHIFT 4
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_7 (1 << 7)
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_MASK 0x00000300
-#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_SHIFT 8
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_MASK 0x00000C00
-#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_SHIFT 10
-/* SerDes one hot mux control.  For details see datasheet.  */
-#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_MASK 0x00007000
-#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_SHIFT 12
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_MASK 0xFFFF8000
-#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_SHIFT 15
-
-/**** pbs_ulpi_mux_conf register ****/
-/*
- * Value 0 - Select dedicated pins for the USB-1 inputs.
- * Value 1 - Select PBS mux pins for the USB-1 inputs.
- * [0] ULPI_B_CLK
- * [1] ULPI_B_DIR
- * [2] ULPI_B_NXT
- * [10:3] ULPI_B_DATA[7:0]
- */
-#define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_MASK 0x000007FF
-#define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_SHIFT 0
-/*
- * [3] - Force to zero
- * [2] == 1 - Force register selection
- * [1 : 0] -Binary selection of the input in bypass mode
- */
-#define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_MASK 0x0000F000
-#define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_SHIFT 12
-/*
- * [0] Sets the clk_ulpi OE for USB0, 1'b0 set to input, 1'b1 set to output.
- * [1] Sets the clk_ulpi OE for USB01, 1'b0 set to input, 1'b1 set to output.
- */
-#define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_MASK 0xFFFF0000
-#define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_SHIFT 16
-
-/**** wr_once_dbg_dis_ovrd_reg register ****/
-/* This register can be written only once. Use in the secure boot process. */
-#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_WR_ONCE_DBG_DIS_OVRD (1 << 0)
-
-#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_MASK 0xFFFFFFFE
-#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_SHIFT 1
-
-/**** gpio5_conf_status register ****/
-/*
- * Cntl: // [7:0] nGPAFEN; // from regfile // [15:8] GPAFOUT; // from regfile
- */
-#define PBS_UNIT_GPIO5_CONF_STATUS_CONF_MASK 0x0000FFFF
-#define PBS_UNIT_GPIO5_CONF_STATUS_CONF_SHIFT 0
-/* Status: //  [24:16] GPAFIN;             // to regfile */
-#define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_MASK 0xFFFF0000
-#define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_SHIFT 16
-
-/**** pcie_mem3_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_SHIFT 6
-/* Reserved */
-#define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_mem4_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_SHIFT 6
-/* Reserved */
-#define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_mem5_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_SHIFT 6
-/* Reserved */
-#define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_ext_ecam3_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_SHIFT 6
-/* Reserved */
-#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_ext_ecam4_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_SHIFT 6
-/* Reserved */
-#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pcie_ext_ecam5_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_SHIFT 6
-/* Reserved */
-#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** low_latency_sram_bar_low register ****/
-/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
-#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_MASK 0x0000003F
-#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_MASK 0x0000FFC0
-#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_SHIFT 6
-/* Reserved */
-#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
-#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_SHIFT 16
-
-/**** pbs_sb2nb_cfg_dram_remap register ****/
-#define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_SHIFT		5
-#define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_MASK		0x0000FFE0
-#define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_SHIFT	21
-#define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_MASK	0xFFE00000
-
-/* For remapping are used bits [39 - 29] of DRAM 40bit Physical address */
-#define PBS_UNIT_DRAM_SRC_REMAP_BASE_ADDR_SHIFT	29
-#define PBS_UNIT_DRAM_DST_REMAP_BASE_ADDR_SHIFT	29
-#define PBS_UNIT_DRAM_REMAP_BASE_ADDR_MASK	0xFFE0000000UL
-
-
-/**** serdes_mux_eth register ****/
-/*
- * 2'b01 - eth_a[0] from serdes_8
- * 2'b10 - eth_a[0] from serdes_14
- */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_SHIFT 0
-/*
- * 2'b01 - eth_b[0] from serdes_9
- * 2'b10 - eth_b[0] from serdes_13
- */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_MASK 0x00000030
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_SHIFT 4
-/*
- * 2'b01 - eth_c[0] from serdes_10
- * 2'b10 - eth_c[0] from serdes_12
- */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_MASK 0x00000300
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_SHIFT 8
-/*
- * 2'b01 - eth_d[0] from serdes_11
- * 2'b10 - eth_d[0] from serdes_15
- */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_MASK 0x00003000
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_SHIFT 12
-/* which lane's is master clk */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_MASK 0x00030000
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_SHIFT 16
-/* which lane's is master clk */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_MASK 0x00300000
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_SHIFT 20
-/* enable xlaui on eth a */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_XLAUI_ENABLE (1 << 24)
-/* enable xlaui on eth c */
-#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_XLAUI_ENABLE (1 << 28)
-
-/**** serdes_mux_pcie register ****/
-/*
- * 2'b01 - select pcie_b[0] from serdes 2
- * 2'b10 - select pcie_b[0] from serdes 4
- */
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_SHIFT 0
-/*
- * 2'b01 - select pcie_b[1] from serdes 3
- * 2'b10 - select pcie_b[1] from serdes 5
- */
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_MASK 0x00000030
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_SHIFT 4
-/*
- * 2'b01 - select pcie_d[0] from serdes 10
- * 2'b10 - select pcie_d[0] from serdes 12
- */
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_MASK 0x00000300
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_SHIFT 8
-/*
- * 2'b01 - select pcie_d[1] from serdes 11
- * 2'b10 - select pcie_d[1] from serdes 13
- */
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_MASK 0x00003000
-#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_SHIFT 12
-
-/**** serdes_mux_sata register ****/
-/*
- * 2'b01 - select sata_a from serdes group 1
- * 2'b10 - select sata_a from serdes group 3
- */
-#define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_MASK 0x00000003
-#define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_SHIFT 0
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_MASK 0x0000000C
-#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_SHIFT 2
-/* Reserved */
-#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_MASK 0xFFFFFFF0
-#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_SHIFT 4
-
-/**** bar1_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar1_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** bar2_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar2_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** bar3_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar3_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** bar4_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar4_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** bar5_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar5_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** bar6_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar6_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** bar7_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar7_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** bar8_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar8_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** bar9_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar9_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** bar10_orig register ****/
-/*
- * Window size = 2 ^ (11 + win_size).
- * Zero value: disable the window.
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_MASK 0x00000007
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_SHIFT 0
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_MASK 0x00000FF8
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_SHIFT 3
-/*
- * offset within the SRAM, in resolution of 4KB.
- * Only offsets which are inside the boundaries of the SRAM bar are allowed
- */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_SHIFT 12
-
-/**** bar10_remap register ****/
-/* Reserved fields */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_MASK 0x00000FFF
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_SHIFT 0
-/* remapped address */
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_MASK 0xFFFFF000
-#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_SHIFT 12
-
-/**** cpu register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_SHIFT 28
-
-/**** cpu_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_SHIFT 28
-
-/**** debug_nb register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_SHIFT 28
-
-/**** debug_nb_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_SHIFT 28
-
-/**** debug_sb register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_SHIFT 28
-
-/**** debug_sb_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_SHIFT 28
-
-/**** eth_0 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_SHIFT 28
-
-/**** eth_0_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_SHIFT 28
-
-/**** eth_1 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_SHIFT 28
-
-/**** eth_1_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_SHIFT 28
-
-/**** eth_2 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_SHIFT 28
-
-/**** eth_2_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_SHIFT 28
-
-/**** eth_3 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_SHIFT 28
-
-/**** eth_3_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_SHIFT 28
-
-/**** sata_0 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_SHIFT 28
-
-/**** sata_0_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_SHIFT 28
-
-/**** sata_1 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_SHIFT 28
-
-/**** sata_1_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_SHIFT 28
-
-/**** crypto_0 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_SHIFT 28
-
-/**** crypto_0_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_SHIFT 28
-
-/**** crypto_1 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_SHIFT 28
-
-/**** crypto_1_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_SHIFT 28
-
-/**** pcie_0 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_SHIFT 28
-
-/**** pcie_0_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_SHIFT 28
-
-/**** pcie_1 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_SHIFT 28
-
-/**** pcie_1_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_SHIFT 28
-
-/**** pcie_2 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_SHIFT 28
-
-/**** pcie_2_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_SHIFT 28
-
-/**** pcie_3 register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_SHIFT 28
-
-/**** pcie_3_mask register ****/
-/* map transactions according to address decoding */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_SHIFT 0
-/* map transactions to pcie_0 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_MASK 0x000000F0
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_SHIFT 4
-/* map transactions to pcie_1 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_MASK 0x00000F00
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_SHIFT 8
-/* map transactions to pcie_2 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_MASK 0x0000F000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_SHIFT 12
-/* map transactions to pcie_3 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_MASK 0x000F0000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_SHIFT 16
-/* map transactions to pcie_4 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_MASK 0x00F00000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_SHIFT 20
-/* map transactions to pcie_5 */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_MASK 0x0F000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_SHIFT 24
-/* map transactions to dram */
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_MASK 0xF0000000
-#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_SHIFT 28
-
-/**** latch register ****/
-/*
- * Software clears this bit before any bar update, and set it after all bars
- * updated.
- */
-#define PBS_TARGET_ID_ENFORCEMENT_LATCH_ENABLE (1 << 0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_PBS_REGS_H__ */
-
-/** @} end of ... group */
-
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_pcie.c b/sys/contrib/alpine-hal/eth/al_hal_pcie.c
deleted file mode 100644
index 3a221d365732..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_pcie.c
+++ /dev/null
@@ -1,2788 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-
-#include "al_hal_pcie.h"
-#include "al_hal_pbs_regs.h"
-#include "al_hal_unit_adapter_regs.h"
-
-/**
- * Parameter definitions
- */
-#define AL_PCIE_AXI_REGS_OFFSET			0x0
-
-#define AL_PCIE_LTSSM_STATE_L0			0x11
-#define AL_PCIE_LTSSM_STATE_L0S			0x12
-#define AL_PCIE_DEVCTL_PAYLOAD_128B		0x00
-#define AL_PCIE_DEVCTL_PAYLOAD_256B		0x20
-
-#define AL_PCIE_SECBUS_DEFAULT			0x1
-#define AL_PCIE_SUBBUS_DEFAULT			0x1
-#define AL_PCIE_LINKUP_WAIT_INTERVAL		50	/* measured in usec */
-#define AL_PCIE_LINKUP_WAIT_INTERVALS_PER_SEC	20
-
-#define AL_PCIE_LINKUP_RETRIES			8
-
-#define AL_PCIE_MAX_32_MEMORY_BAR_SIZE		(0x100000000ULL)
-#define AL_PCIE_MIN_MEMORY_BAR_SIZE		(1 << 12)
-#define AL_PCIE_MIN_IO_BAR_SIZE			(1 << 8)
-
-/**
- * inbound header credits and outstanding outbound reads defaults
- */
-/** RC - Revisions 1/2 */
-#define AL_PCIE_REV_1_2_RC_OB_OS_READS_DEFAULT	(8)
-#define AL_PCIE_REV_1_2_RC_NOF_CPL_HDR_DEFAULT	(41)
-#define AL_PCIE_REV_1_2_RC_NOF_NP_HDR_DEFAULT	(25)
-#define AL_PCIE_REV_1_2_RC_NOF_P_HDR_DEFAULT	(31)
-/** EP - Revisions 1/2 */
-#define AL_PCIE_REV_1_2_EP_OB_OS_READS_DEFAULT	(15)
-#define AL_PCIE_REV_1_2_EP_NOF_CPL_HDR_DEFAULT	(76)
-#define AL_PCIE_REV_1_2_EP_NOF_NP_HDR_DEFAULT	(6)
-#define AL_PCIE_REV_1_2_EP_NOF_P_HDR_DEFAULT	(15)
-/** RC - Revision 3 */
-#define AL_PCIE_REV_3_RC_OB_OS_READS_DEFAULT	(32)
-#define AL_PCIE_REV_3_RC_NOF_CPL_HDR_DEFAULT	(161)
-#define AL_PCIE_REV_3_RC_NOF_NP_HDR_DEFAULT	(38)
-#define AL_PCIE_REV_3_RC_NOF_P_HDR_DEFAULT	(60)
-/** EP - Revision 3 */
-#define AL_PCIE_REV_3_EP_OB_OS_READS_DEFAULT	(32)
-#define AL_PCIE_REV_3_EP_NOF_CPL_HDR_DEFAULT	(161)
-#define AL_PCIE_REV_3_EP_NOF_NP_HDR_DEFAULT	(38)
-#define AL_PCIE_REV_3_EP_NOF_P_HDR_DEFAULT	(60)
-
-/**
- * MACROS
- */
-#define AL_PCIE_PARSE_LANES(v)		(((1 << v) - 1) << \
-		PCIE_REVX_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_SHIFT)
-
-/**
- * Static functions
- */
-static void
-al_pcie_port_wr_to_ro_set(struct al_pcie_port *pcie_port, al_bool enable)
-{
-	/* when disabling writes to RO, make sure any previous writes to
-	 * config space were committed
-	 */
-	if (enable == AL_FALSE)
-		al_local_data_memory_barrier();
-
-	al_reg_write32(&pcie_port->regs->port_regs->rd_only_wr_en,
-		       (enable == AL_TRUE) ? 1 : 0);
-
-	/* when enabling writes to RO, make sure it is committed before trying
-	 * to write to RO config space
-	 */
-	if (enable == AL_TRUE)
-		al_local_data_memory_barrier();
-}
-
-/** helper function to access dbi_cs2 registers */
-static void
-al_reg_write32_dbi_cs2(
-	struct al_pcie_port	*pcie_port,
-	uint32_t		*offset,
-	uint32_t		val)
-{
-	uintptr_t cs2_bit =
-		(pcie_port->rev_id == AL_PCIE_REV_ID_3) ? 0x4000 : 0x1000;
-
-	al_reg_write32((uint32_t *)((uintptr_t)offset | cs2_bit), val);
-}
-
-static unsigned int
-al_pcie_speed_gen_code(enum al_pcie_link_speed speed)
-{
-	if (speed == AL_PCIE_LINK_SPEED_GEN1)
-		return 1;
-	if (speed == AL_PCIE_LINK_SPEED_GEN2)
-		return 2;
-	if (speed == AL_PCIE_LINK_SPEED_GEN3)
-		return 3;
-	/* must not be reached */
-	return 0;
-}
-
-static inline void
-al_pcie_port_link_speed_ctrl_set(
-	struct al_pcie_port *pcie_port,
-	enum al_pcie_link_speed max_speed)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
-
-	if (max_speed != AL_PCIE_LINK_SPEED_DEFAULT) {
-		uint16_t max_speed_val = (uint16_t)al_pcie_speed_gen_code(max_speed);
-		al_reg_write32_masked(
-			(uint32_t __iomem *)(regs->core_space[0].pcie_link_cap_base),
-			0xF, max_speed_val);
-		al_reg_write32_masked(
-			(uint32_t __iomem *)(regs->core_space[0].pcie_cap_base
-			+ (AL_PCI_EXP_LNKCTL2 >> 2)),
-			0xF, max_speed_val);
-	}
-
-	al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
-}
-
-static int
-al_pcie_port_link_config(
-	struct al_pcie_port *pcie_port,
-	const struct al_pcie_link_params *link_params)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint8_t max_lanes = pcie_port->max_lanes;
-
-	if ((link_params->max_payload_size != AL_PCIE_MPS_DEFAULT)	&&
-	    (link_params->max_payload_size != AL_PCIE_MPS_128)		&&
-	    (link_params->max_payload_size != AL_PCIE_MPS_256)) {
-		al_err("PCIe %d: unsupported Max Payload Size (%u)\n",
-		       pcie_port->port_id, link_params->max_payload_size);
-		return -EINVAL;
-	}
-
-	al_dbg("PCIe %d: link config: max speed gen %d, max lanes %d, reversal %s\n",
-	       pcie_port->port_id, link_params->max_speed,
-	       pcie_port->max_lanes, link_params->enable_reversal? "enable" : "disable");
-
-	al_pcie_port_link_speed_ctrl_set(pcie_port, link_params->max_speed);
-
-	/* Change Max Payload Size, if needed.
-	 * The Max Payload Size is only valid for PF0.
-	 */
-	if (link_params->max_payload_size != AL_PCIE_MPS_DEFAULT)
-		al_reg_write32_masked(regs->core_space[0].pcie_dev_ctrl_status,
-				      PCIE_PORT_DEV_CTRL_STATUS_MPS_MASK,
-				      link_params->max_payload_size <<
-					PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT);
-
-	/** Snap from PCIe core spec:
-	 * Link Mode Enable. Sets the number of lanes in the link that you want
-	 * to connect to the link partner. When you have unused lanes in your
-	 * system, then you must change the value in this register to reflect
-	 * the number of lanes. You must also change the value in the
-	 * "Predetermined Number of Lanes" field of the "Link Width and Speed
-	 * Change Control Register".
-	 * 000001: x1
-	 * 000011: x2
-	 * 000111: x4
-	 * 001111: x8
-	 * 011111: x16
-	 * 111111: x32 (not supported)
-	 */
-	al_reg_write32_masked(&regs->port_regs->gen2_ctrl,
-				PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_MASK,
-				max_lanes << PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_SHIFT);
-	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
-				PCIE_PORT_LINK_CTRL_LINK_CAPABLE_MASK,
-				(max_lanes + (max_lanes-1))
-				<< PCIE_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT);
-
-	/* TODO: add support for reversal mode */
-	if (link_params->enable_reversal) {
-		al_err("PCIe %d: enabling reversal mode not implemented\n",
-			pcie_port->port_id);
-		return -ENOSYS;
-	}
-	return 0;
-}
-
-static void
-al_pcie_port_ram_parity_int_config(
-	struct al_pcie_port *pcie_port,
-	al_bool enable)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	al_reg_write32(&regs->app.parity->en_core,
-		(enable == AL_TRUE) ? 0xffffffff : 0x0);
-
-	al_reg_write32_masked(&regs->app.int_grp_b->mask,
-	      PCIE_W_INT_GRP_B_CAUSE_B_PARITY_ERROR_CORE,
-	      (enable != AL_TRUE) ?
-	      PCIE_W_INT_GRP_B_CAUSE_B_PARITY_ERROR_CORE : 0);
-
-}
-
-static void
-al_pcie_port_axi_parity_int_config(
-	struct al_pcie_port *pcie_port,
-	al_bool enable)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t parity_enable_mask = 0xffffffff;
-
-	/**
-	 * Addressing RMN: 5603
-	 *
-	 * RMN description:
-	 * u4_ram2p signal false parity error
-	 *
-	 * Software flow:
-	 * Disable parity check for this memory
-	 */
-	if (pcie_port->rev_id >= AL_PCIE_REV_ID_3)
-		parity_enable_mask &= ~PCIE_AXI_PARITY_EN_AXI_U4_RAM2P;
-
-	al_reg_write32(regs->axi.parity.en_axi,
-		       (enable == AL_TRUE) ? parity_enable_mask : 0x0);
-
-	if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
-		al_reg_write32_masked(regs->axi.ctrl.global,
-			PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR |
-			PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD |
-			PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV |
-			PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR,
-			(enable == AL_TRUE) ?
-			PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR |
-			PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD |
-			PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV |
-			PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR :
-			PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV);
-	} else {
-		al_reg_write32_masked(regs->axi.ctrl.global,
-			PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR |
-			PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD |
-			PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV |
-			PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR,
-			(enable == AL_TRUE) ?
-			PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR |
-			PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD |
-			PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV |
-			PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR :
-			PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV);
-	}
-
-	al_reg_write32_masked(&regs->axi.int_grp_a->mask,
-		PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_DATA_PATH_RD |
-		PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_RD |
-		PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_WR |
-		PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_DATA_WR |
-		PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERROR_AXI,
-		(enable != AL_TRUE) ?
-		(PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_DATA_PATH_RD |
-		PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_RD |
-		PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_WR |
-		PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_DATA_WR |
-		PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERROR_AXI) : 0);
-}
-
-static void
-al_pcie_port_relaxed_pcie_ordering_config(
-	struct al_pcie_port *pcie_port,
-	struct al_pcie_relaxed_ordering_params *relaxed_ordering_params)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
-	/**
-	 * Default:
-	 *  - RC: Rx relaxed ordering only
-	 *  - EP: TX relaxed ordering only
-	 */
-	al_bool tx_relaxed_ordering = (op_mode == AL_PCIE_OPERATING_MODE_RC ? AL_FALSE : AL_TRUE);
-	al_bool rx_relaxed_ordering = (op_mode == AL_PCIE_OPERATING_MODE_RC ? AL_TRUE : AL_FALSE);
-
-	if (relaxed_ordering_params) {
-		tx_relaxed_ordering = relaxed_ordering_params->enable_tx_relaxed_ordering;
-		rx_relaxed_ordering = relaxed_ordering_params->enable_rx_relaxed_ordering;
-	}
-
-	/** PCIe ordering:
-	 *  - disable outbound completion must be stalled behind outbound write
-	 *    ordering rule enforcement is disabled for root-port
-	 *  - disables read completion on the master port push slave writes for end-point
-	 */
-	al_reg_write32_masked(
-		regs->axi.ordering.pos_cntl,
-		PCIE_AXI_POS_ORDER_BYPASS_CMPL_AFTER_WR_FIX |
-		PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_DIS |
-		PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_SUPPORT_INTERLV_DIS |
-		PCIE_AXI_POS_ORDER_SEGMENT_BUFFER_DONT_WAIT_FOR_P_WRITES,
-		(tx_relaxed_ordering ?
-		(PCIE_AXI_POS_ORDER_BYPASS_CMPL_AFTER_WR_FIX |
-		PCIE_AXI_POS_ORDER_SEGMENT_BUFFER_DONT_WAIT_FOR_P_WRITES) : 0) |
-		(rx_relaxed_ordering ?
-		(PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_DIS |
-		PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_SUPPORT_INTERLV_DIS) : 0));
-}
-
-static int
-al_pcie_rev_id_get(
-	void __iomem *pbs_reg_base,
-	void __iomem *pcie_reg_base)
-{
-	uint32_t chip_id;
-	uint16_t chip_id_dev;
-	uint8_t rev_id;
-	struct al_pbs_regs *pbs_regs = pbs_reg_base;
-
-	/* get revision ID from PBS' chip_id register */
-	chip_id = al_reg_read32(&pbs_regs->unit.chip_id);
-	chip_id_dev = AL_REG_FIELD_GET(chip_id,
-				       PBS_UNIT_CHIP_ID_DEV_ID_MASK,
-				       PBS_UNIT_CHIP_ID_DEV_ID_SHIFT);
-
-	if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_ALPINE) {
-		rev_id = AL_REG_FIELD_GET(
-						chip_id,
-						PBS_UNIT_CHIP_ID_DEV_REV_ID_MASK,
-						PBS_UNIT_CHIP_ID_DEV_REV_ID_SHIFT);
-	} else if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK) {
-		struct al_pcie_revx_regs __iomem *regs =
-			(struct al_pcie_revx_regs __iomem *)pcie_reg_base;
-		uint32_t dev_id;
-
-		dev_id = al_reg_read32(&regs->axi.device_id.device_rev_id) &
-			PCIE_AXI_DEVICE_ID_REG_DEV_ID_MASK;
-		if (dev_id == PCIE_AXI_DEVICE_ID_REG_DEV_ID_X4) {
-			rev_id = AL_PCIE_REV_ID_2;
-		} else if (dev_id == PCIE_AXI_DEVICE_ID_REG_DEV_ID_X8) {
-			rev_id = AL_PCIE_REV_ID_3;
-		} else {
-			al_warn("%s: Revision ID is unknown\n",
-				__func__);
-			return -EINVAL;
-		}
-	} else {
-		al_warn("%s: Revision ID is unknown\n",
-			__func__);
-		return -EINVAL;
-	}
-	return rev_id;
-}
-
-static int
-al_pcie_port_lat_rply_timers_config(
-	struct al_pcie_port *pcie_port,
-	const struct al_pcie_latency_replay_timers  *lat_rply_timers)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t	reg = 0;
-
-	AL_REG_FIELD_SET(reg, 0xFFFF, 0, lat_rply_timers->round_trip_lat_limit);
-	AL_REG_FIELD_SET(reg, 0xFFFF0000, 16, lat_rply_timers->replay_timer_limit);
-
-	al_reg_write32(&regs->port_regs->ack_lat_rply_timer, reg);
-	return 0;
-}
-
-static void
-al_pcie_ib_hcrd_os_ob_reads_config_default(
-	struct al_pcie_port *pcie_port)
-{
-
-	struct al_pcie_ib_hcrd_os_ob_reads_config ib_hcrd_os_ob_reads_config;
-
-	switch (al_pcie_operating_mode_get(pcie_port)) {
-	case AL_PCIE_OPERATING_MODE_RC:
-		if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
-			ib_hcrd_os_ob_reads_config.nof_outstanding_ob_reads =
-				AL_PCIE_REV_3_RC_OB_OS_READS_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_cpl_hdr =
-				AL_PCIE_REV_3_RC_NOF_CPL_HDR_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_np_hdr =
-				AL_PCIE_REV_3_RC_NOF_NP_HDR_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_p_hdr =
-				AL_PCIE_REV_3_RC_NOF_P_HDR_DEFAULT;
-		} else {
-			ib_hcrd_os_ob_reads_config.nof_outstanding_ob_reads =
-				AL_PCIE_REV_1_2_RC_OB_OS_READS_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_cpl_hdr =
-				AL_PCIE_REV_1_2_RC_NOF_CPL_HDR_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_np_hdr =
-				AL_PCIE_REV_1_2_RC_NOF_NP_HDR_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_p_hdr =
-				AL_PCIE_REV_1_2_RC_NOF_P_HDR_DEFAULT;
-		}
-		break;
-
-	case AL_PCIE_OPERATING_MODE_EP:
-		if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
-			ib_hcrd_os_ob_reads_config.nof_outstanding_ob_reads =
-				AL_PCIE_REV_3_EP_OB_OS_READS_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_cpl_hdr =
-				AL_PCIE_REV_3_EP_NOF_CPL_HDR_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_np_hdr =
-				AL_PCIE_REV_3_EP_NOF_NP_HDR_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_p_hdr =
-				AL_PCIE_REV_3_EP_NOF_P_HDR_DEFAULT;
-		} else {
-			ib_hcrd_os_ob_reads_config.nof_outstanding_ob_reads =
-				AL_PCIE_REV_1_2_EP_OB_OS_READS_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_cpl_hdr =
-				AL_PCIE_REV_1_2_EP_NOF_CPL_HDR_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_np_hdr =
-				AL_PCIE_REV_1_2_EP_NOF_NP_HDR_DEFAULT;
-			ib_hcrd_os_ob_reads_config.nof_p_hdr =
-				AL_PCIE_REV_1_2_EP_NOF_P_HDR_DEFAULT;
-		}
-		break;
-
-	default:
-		al_err("PCIe %d: outstanding outbound transactions could not be configured - unknown operating mode\n",
-			pcie_port->port_id);
-		al_assert(0);
-	}
-
-	al_pcie_port_ib_hcrd_os_ob_reads_config(pcie_port, &ib_hcrd_os_ob_reads_config);
-};
-
-/** return AL_TRUE is link started (LTSSM enabled) and AL_FALSE otherwise */
-static al_bool
-al_pcie_is_link_started(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;
-
-	uint32_t port_init = al_reg_read32(regs->app.global_ctrl.port_init);
-	uint8_t ltssm_en = AL_REG_FIELD_GET(port_init,
-		PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK,
-		PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_SHIFT);
-
-	return ltssm_en;
-}
-
-/** return AL_TRUE if link is up, AL_FALSE otherwise */
-static al_bool
-al_pcie_check_link(
-	struct al_pcie_port *pcie_port,
-	uint8_t *ltssm_ret)
-{
-	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;
-	uint32_t info_0;
-	uint8_t	ltssm_state;
-
-	info_0 = al_reg_read32(&regs->app.debug->info_0);
-
-	ltssm_state = AL_REG_FIELD_GET(info_0,
-			PCIE_W_DEBUG_INFO_0_LTSSM_STATE_MASK,
-			PCIE_W_DEBUG_INFO_0_LTSSM_STATE_SHIFT);
-
-	al_dbg("PCIe %d: Port Debug 0: 0x%08x. LTSSM state :0x%x\n",
-		pcie_port->port_id, info_0, ltssm_state);
-
-	if (ltssm_ret)
-		*ltssm_ret = ltssm_state;
-
-	if ((ltssm_state == AL_PCIE_LTSSM_STATE_L0) ||
-			(ltssm_state == AL_PCIE_LTSSM_STATE_L0S))
-		return AL_TRUE;
-	return AL_FALSE;
-}
-
-static int
-al_pcie_port_gen2_params_config(struct al_pcie_port *pcie_port,
-				const struct al_pcie_gen2_params *gen2_params)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t gen2_ctrl;
-
-	al_dbg("PCIe %d: Gen2 params config: Tx Swing %s, interrupt on link Eq %s, set Deemphasis %s\n",
-	       pcie_port->port_id,
-	       gen2_params->tx_swing_low ? "Low" : "Full",
-	       gen2_params->tx_compliance_receive_enable? "enable" : "disable",
-	       gen2_params->set_deemphasis? "enable" : "disable");
-
-	gen2_ctrl = al_reg_read32(&regs->port_regs->gen2_ctrl);
-
-	if (gen2_params->tx_swing_low)
-		AL_REG_BIT_SET(gen2_ctrl, PCIE_PORT_GEN2_CTRL_TX_SWING_LOW_SHIFT);
-	else
-		AL_REG_BIT_CLEAR(gen2_ctrl, PCIE_PORT_GEN2_CTRL_TX_SWING_LOW_SHIFT);
-
-	if (gen2_params->tx_compliance_receive_enable)
-		AL_REG_BIT_SET(gen2_ctrl, PCIE_PORT_GEN2_CTRL_TX_COMPLIANCE_RCV_SHIFT);
-	else
-		AL_REG_BIT_CLEAR(gen2_ctrl, PCIE_PORT_GEN2_CTRL_TX_COMPLIANCE_RCV_SHIFT);
-
-	if (gen2_params->set_deemphasis)
-		AL_REG_BIT_SET(gen2_ctrl, PCIE_PORT_GEN2_CTRL_DEEMPHASIS_SET_SHIFT);
-	else
-		AL_REG_BIT_CLEAR(gen2_ctrl, PCIE_PORT_GEN2_CTRL_DEEMPHASIS_SET_SHIFT);
-
-	al_reg_write32(&regs->port_regs->gen2_ctrl, gen2_ctrl);
-
-	return 0;
-}
-
-
-static uint16_t
-gen3_lane_eq_param_to_val(const struct al_pcie_gen3_lane_eq_params *eq_params)
-{
-	uint16_t eq_control = 0;
-
-	eq_control = eq_params->downstream_port_transmitter_preset & 0xF;
-	eq_control |= (eq_params->downstream_port_receiver_preset_hint & 0x7) << 4;
-	eq_control |= (eq_params->upstream_port_transmitter_preset & 0xF) << 8;
-	eq_control |= (eq_params->upstream_port_receiver_preset_hint & 0x7) << 12;
-
-	return eq_control;
-}
-
-static int
-al_pcie_port_gen3_params_config(struct al_pcie_port *pcie_port,
-				const struct al_pcie_gen3_params *gen3_params)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t reg = 0;
-	uint16_t __iomem *lanes_eq_base = (uint16_t __iomem *)(regs->core_space[0].pcie_sec_ext_cap_base + (0xC >> 2));
-	int i;
-
-	al_dbg("PCIe %d: Gen3 params config: Equalization %s, interrupt on link Eq %s\n",
-	       pcie_port->port_id,
-	       gen3_params->perform_eq ? "enable" : "disable",
-	       gen3_params->interrupt_enable_on_link_eq_request? "enable" : "disable");
-
-	if (gen3_params->perform_eq)
-		AL_REG_BIT_SET(reg, 0);
-	if (gen3_params->interrupt_enable_on_link_eq_request)
-		AL_REG_BIT_SET(reg, 1);
-
-	al_reg_write32(regs->core_space[0].pcie_sec_ext_cap_base + (4 >> 2),
-		       reg);
-
-	al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
-
-	for (i = 0; i < gen3_params->eq_params_elements; i += 2) {
-		uint32_t eq_control =
-			(uint32_t)gen3_lane_eq_param_to_val(gen3_params->eq_params + i) |
-			(uint32_t)gen3_lane_eq_param_to_val(gen3_params->eq_params + i + 1) << 16;
-
-		al_dbg("PCIe %d: Set EQ (0x%08x) for lane %d, %d\n", pcie_port->port_id, eq_control, i, i + 1);
-		al_reg_write32((uint32_t *)(lanes_eq_base + i), eq_control);
-	}
-
-	al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
-
-	reg = al_reg_read32(&regs->port_regs->gen3_ctrl);
-	if (gen3_params->eq_disable)
-		AL_REG_BIT_SET(reg, PCIE_PORT_GEN3_CTRL_EQ_DISABLE_SHIFT);
-	else
-		AL_REG_BIT_CLEAR(reg, PCIE_PORT_GEN3_CTRL_EQ_DISABLE_SHIFT);
-
-	if (gen3_params->eq_phase2_3_disable)
-		AL_REG_BIT_SET(reg, PCIE_PORT_GEN3_CTRL_EQ_PHASE_2_3_DISABLE_SHIFT);
-	else
-		AL_REG_BIT_CLEAR(reg, PCIE_PORT_GEN3_CTRL_EQ_PHASE_2_3_DISABLE_SHIFT);
-
-	al_reg_write32(&regs->port_regs->gen3_ctrl, reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_LF_MASK,
-			 PCIE_PORT_GEN3_EQ_LF_SHIFT,
-			 gen3_params->local_lf);
-	AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_FS_MASK,
-			 PCIE_PORT_GEN3_EQ_FS_SHIFT,
-			 gen3_params->local_fs);
-
-	al_reg_write32(&regs->port_regs->gen3_eq_fs_lf, reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_MASK,
-			 PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_SHIFT,
-			 gen3_params->local_lf);
-	AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_MASK,
-			 PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_SHIFT,
-			 gen3_params->local_fs);
-	al_reg_write32(regs->axi.conf.zero_lane0, reg);
-	al_reg_write32(regs->axi.conf.zero_lane1, reg);
-	al_reg_write32(regs->axi.conf.zero_lane2, reg);
-	al_reg_write32(regs->axi.conf.zero_lane3, reg);
-	if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
-		al_reg_write32(regs->axi.conf.zero_lane4, reg);
-		al_reg_write32(regs->axi.conf.zero_lane5, reg);
-		al_reg_write32(regs->axi.conf.zero_lane6, reg);
-		al_reg_write32(regs->axi.conf.zero_lane7, reg);
-	}
-
-	/*
-	 * Gen3 EQ Control Register:
-	 * - Preset Request Vector - request 9
-	 * - Behavior After 24 ms Timeout (when optimal settings are not
-	 *   found): Recovery.Equalization.RcvrLock
-	 * - Phase2_3 2 ms Timeout Disable
-	 * - Feedback Mode - Figure Of Merit
-	 */
-	reg = 0x00020031;
-	al_reg_write32(&regs->port_regs->gen3_eq_ctrl, reg);
-
-	return 0;
-}
-
-static int
-al_pcie_port_tl_credits_config(
-	struct al_pcie_port *pcie_port,
-	const struct al_pcie_tl_credits_params  *tl_credits __attribute__((__unused__)))
-{
-	al_err("PCIe %d: transport layer credits config not implemented\n",
-		pcie_port->port_id);
-
-	return -ENOSYS;
-
-}
-
-static int
-al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf,
-			      const struct al_pcie_pf_config_params *pf_params)
-{
-	struct al_pcie_port *pcie_port = pcie_pf->pcie_port;
-	struct al_pcie_regs *regs = pcie_port->regs;
-	unsigned int pf_num = pcie_pf->pf_num;
-	int bar_idx;
-	int ret;
-
-	al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
-
-	/* Disable D1 and D3hot capabilities */
-	if (pf_params->cap_d1_d3hot_dis)
-		al_reg_write32_masked(
-			regs->core_space[pf_num].pcie_pm_cap_base,
-			AL_FIELD_MASK(26, 25) | AL_FIELD_MASK(31, 28), 0);
-
-	/* Disable FLR capability */
-	if (pf_params->cap_flr_dis)
-		al_reg_write32_masked(
-			regs->core_space[pf_num].pcie_dev_cap_base,
-			AL_BIT(28), 0);
-
-	/* Disable ASPM capability */
-	if (pf_params->cap_aspm_dis) {
-		al_reg_write32_masked(
-			regs->core_space[pf_num].pcie_cap_base + (AL_PCI_EXP_LNKCAP >> 2),
-			AL_PCI_EXP_LNKCAP_ASPMS, 0);
-	} else if (pcie_port->rev_id == AL_PCIE_REV_ID_0) {
-		al_warn("%s: ASPM support is enabled, please disable it\n",
-			__func__);
-		ret = -EINVAL;
-		goto done;
-	}
-
-	if (!pf_params->bar_params_valid) {
-		ret = 0;
-		goto done;
-	}
-
-	for (bar_idx = 0; bar_idx < 6;){ /* bar_idx will be incremented depending on bar type */
-		const struct al_pcie_ep_bar_params *params = pf_params->bar_params + bar_idx;
-		uint32_t mask = 0;
-		uint32_t ctrl = 0;
-		uint32_t __iomem *bar_addr = &regs->core_space[pf_num].config_header[(AL_PCI_BASE_ADDRESS_0 >> 2) + bar_idx];
-
-		if (params->enable) {
-			uint64_t size = params->size;
-
-			if (params->memory_64_bit) {
-				const struct al_pcie_ep_bar_params *next_params = params + 1;
-				/* 64 bars start at even index (BAR0, BAR 2 or BAR 4) */
-				if (bar_idx & 1) {
-					ret = -EINVAL;
-					goto done;
-				}
-
-				/* next BAR must be disabled */
-				if (next_params->enable) {
-					ret = -EINVAL;
-					goto done;
-				}
-
-				/* 64 bar must be memory bar */
-				if (!params->memory_space) {
-					ret = -EINVAL;
-					goto done;
-				}
-			} else {
-				if (size > AL_PCIE_MAX_32_MEMORY_BAR_SIZE)
-					return -EINVAL;
-				/* 32 bit space can't be prefetchable */
-				if (params->memory_is_prefetchable) {
-					ret = -EINVAL;
-					goto done;
-				}
-			}
-
-			if (params->memory_space) {
-				if (size < AL_PCIE_MIN_MEMORY_BAR_SIZE) {
-					al_err("PCIe %d: memory BAR %d: size (0x%llx) less that minimal allowed value\n",
-						pcie_port->port_id, bar_idx, size);
-					ret = -EINVAL;
-					goto done;
-				}
-			} else {
-				/* IO can't be prefetchable */
-				if (params->memory_is_prefetchable) {
-					ret = -EINVAL;
-					goto done;
-				}
-
-				if (size < AL_PCIE_MIN_IO_BAR_SIZE) {
-					al_err("PCIe %d: IO BAR %d: size (0x%llx) less that minimal allowed value\n",
-						pcie_port->port_id, bar_idx, size);
-					ret = -EINVAL;
-					goto done;
-				}
-			}
-
-			/* size must be power of 2 */
-			if (size & (size - 1)) {
-				al_err("PCIe %d: BAR %d:size (0x%llx) must be "
-					"power of 2\n",
-					pcie_port->port_id, bar_idx, size);
-				ret = -EINVAL;
-				goto done;
-			}
-
-			/* If BAR is 64-bit, disable the next BAR before
-			 * configuring this one
-			 */
-			if (params->memory_64_bit)
-				al_reg_write32_dbi_cs2(pcie_port, bar_addr + 1, 0);
-
-			mask = 1; /* enable bit*/
-			mask |= (params->size - 1) & 0xFFFFFFFF;
-
-			al_reg_write32_dbi_cs2(pcie_port, bar_addr , mask);
-
-			if (params->memory_space == AL_FALSE)
-				ctrl = AL_PCI_BASE_ADDRESS_SPACE_IO;
-			if (params->memory_64_bit)
-				ctrl |= AL_PCI_BASE_ADDRESS_MEM_TYPE_64;
-			if (params->memory_is_prefetchable)
-				ctrl |= AL_PCI_BASE_ADDRESS_MEM_PREFETCH;
-			al_reg_write32(bar_addr, ctrl);
-
-			if (params->memory_64_bit) {
-				mask = ((params->size - 1) >> 32) & 0xFFFFFFFF;
-				al_reg_write32_dbi_cs2(pcie_port, bar_addr + 1, mask);
-			}
-
-		} else {
-			al_reg_write32_dbi_cs2(pcie_port, bar_addr , mask);
-		}
-		if (params->enable && params->memory_64_bit)
-			bar_idx += 2;
-		else
-			bar_idx += 1;
-	}
-
-	if (pf_params->exp_bar_params.enable) {
-		if (pcie_port->rev_id != AL_PCIE_REV_ID_3) {
-			al_err("PCIe %d: Expansion BAR enable not supported\n", pcie_port->port_id);
-			ret = -ENOSYS;
-			goto done;
-		} else {
-			/* Enable exp ROM */
-			uint32_t __iomem *exp_rom_bar_addr =
-			&regs->core_space[pf_num].config_header[AL_PCI_EXP_ROM_BASE_ADDRESS >> 2];
-			uint32_t mask = 1; /* enable bit*/
-			mask |= (pf_params->exp_bar_params.size - 1) & 0xFFFFFFFF;
-			al_reg_write32_dbi_cs2(pcie_port, exp_rom_bar_addr , mask);
-		}
-	} else if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
-		/* Disable exp ROM */
-		uint32_t __iomem *exp_rom_bar_addr =
-			&regs->core_space[pf_num].config_header[AL_PCI_EXP_ROM_BASE_ADDRESS >> 2];
-		al_reg_write32_dbi_cs2(pcie_port, exp_rom_bar_addr , 0);
-	}
-
-	/* Open CPU generated msi and legacy interrupts in pcie wrapper logic */
-	if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) ||
-		(pcie_port->rev_id == AL_PCIE_REV_ID_1)) {
-		al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_0, (1 << 21));
-	} else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) ||
-		(pcie_port->rev_id == AL_PCIE_REV_ID_3)) {
-		al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_3, (1 << 18));
-	} else {
-		al_assert(0);
-		ret = -ENOSYS;
-		goto done;
-	}
-
-	/**
-	 * Addressing RMN: 1547
-	 *
-	 * RMN description:
-	 * 1. Whenever writing to 0x2xx offset, the write also happens to
-	 * 0x3xx address, meaning two registers are written instead of one.
-	 * 2. Read and write from 0x3xx work ok.
-	 *
-	 * Software flow:
-	 * Backup the value of the app.int_grp_a.mask_a register, because
-	 * app.int_grp_a.mask_clear_a gets overwritten during the write to
-	 * app.soc.mask_msi_leg_0 register.
-	 * Restore the original value after the write to app.soc.mask_msi_leg_0
-	 * register.
-	 */
-	if (pcie_port->rev_id == AL_PCIE_REV_ID_0) {
-		uint32_t backup;
-
-		backup = al_reg_read32(&regs->app.int_grp_a->mask);
-		al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));
-		al_reg_write32(&regs->app.int_grp_a->mask, backup);
-	} else if (pcie_port->rev_id == AL_PCIE_REV_ID_1) {
-		al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));
-	} else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) ||
-		(pcie_port->rev_id == AL_PCIE_REV_ID_3)) {
-		al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_3, (1 << 19));
-	} else {
-		al_assert(0);
-		ret = -ENOSYS;
-		goto done;
-	}
-
-	ret = 0;
-
-done:
-	al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
-
-	return ret;
-}
-
-static void
-al_pcie_port_features_config(
-	struct al_pcie_port *pcie_port,
-	const struct al_pcie_features *features)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	al_assert(pcie_port->rev_id > AL_PCIE_REV_ID_0);
-
-	al_reg_write32_masked(
-		&regs->app.ctrl_gen->features,
-		PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX,
-		features->sata_ep_msi_fix ?
-		PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX : 0);
-}
-
-static int
-al_pcie_port_sris_config(
-	struct al_pcie_port *pcie_port,
-	struct al_pcie_sris_params *sris_params,
-	enum al_pcie_link_speed link_speed)
-{
-	int rc = 0;
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	if (sris_params->use_defaults) {
-		sris_params->kp_counter_gen3 = (pcie_port->rev_id > AL_PCIE_REV_ID_1) ?
-						PCIE_SRIS_KP_COUNTER_GEN3_DEFAULT_VAL : 0;
-		sris_params->kp_counter_gen21 = PCIE_SRIS_KP_COUNTER_GEN21_DEFAULT_VAL;
-
-		al_dbg("PCIe %d: configuring SRIS with default values kp_gen3[%d] kp_gen21[%d]\n",
-			pcie_port->port_id,
-			sris_params->kp_counter_gen3,
-			sris_params->kp_counter_gen21);
-	}
-
-	switch (pcie_port->rev_id) {
-	case AL_PCIE_REV_ID_3:
-	case AL_PCIE_REV_ID_2:
-		al_reg_write32_masked(regs->app.global_ctrl.sris_kp_counter,
-			PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_MASK |
-			PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_MASK |
-			PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_PCIE_X4_SRIS_EN,
-			(sris_params->kp_counter_gen3 <<
-				PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_SHIFT) |
-			(sris_params->kp_counter_gen21 <<
-				PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_SHIFT) |
-			PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_PCIE_X4_SRIS_EN);
-		break;
-
-	case AL_PCIE_REV_ID_1:
-		if ((link_speed == AL_PCIE_LINK_SPEED_GEN3) && (sris_params->kp_counter_gen3)) {
-			al_err("PCIe %d: cannot config Gen%d SRIS with rev_id[%d]\n",
-				pcie_port->port_id, al_pcie_speed_gen_code(link_speed),
-				pcie_port->rev_id);
-			return -EINVAL;
-		}
-
-		al_reg_write32_masked(&regs->port_regs->filter_mask_reg_1,
-			PCIE_FLT_MASK_SKP_INT_VAL_MASK,
-			sris_params->kp_counter_gen21);
-		break;
-
-	default:
-		al_err("PCIe %d: SRIS config is not supported in rev_id[%d]\n",
-			pcie_port->port_id, pcie_port->rev_id);
-		al_assert(0);
-		return -EINVAL;
-	}
-
-	return rc;
-}
-
-static void
-al_pcie_port_ib_hcrd_config(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	al_reg_write32_masked(
-		&regs->port_regs->vc0_posted_rcv_q_ctrl,
-		RADM_PQ_HCRD_VC0_MASK,
-		(pcie_port->ib_hcrd_config.nof_p_hdr - 1)
-			<< RADM_PQ_HCRD_VC0_SHIFT);
-
-	al_reg_write32_masked(
-		&regs->port_regs->vc0_non_posted_rcv_q_ctrl,
-		RADM_NPQ_HCRD_VC0_MASK,
-		(pcie_port->ib_hcrd_config.nof_np_hdr - 1)
-			<< RADM_NPQ_HCRD_VC0_SHIFT);
-}
-
-static unsigned int
-al_pcie_port_max_num_of_pfs_get(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t max_func_num;
-	uint32_t max_num_of_pfs;
-
-	/**
-	 * Only in REV3, when port is already enabled, max_num_of_pfs is already
-	 * initialized, return it. Otherwise, return default: 1 PF
-	 */
-	if ((pcie_port->rev_id == AL_PCIE_REV_ID_3)
-		&& al_pcie_port_is_enabled(pcie_port)) {
-		max_func_num = al_reg_read32(&regs->port_regs->timer_ctrl_max_func_num);
-		max_num_of_pfs = AL_REG_FIELD_GET(max_func_num, PCIE_PORT_GEN3_MAX_FUNC_NUM, 0) + 1;
-		return max_num_of_pfs;
-	}
-	return 1;
-}
-
-/******************************************************************************/
-/***************************** API Implementation *****************************/
-/******************************************************************************/
-
-/*************************** PCIe Initialization API **************************/
-
-/**
- * Initializes a PCIe port handle structure
- * Caution: this function should not read/write to any register except for
- * reading RO register (REV_ID for example)
- */
-int
-al_pcie_port_handle_init(
-	struct al_pcie_port 	*pcie_port,
-	void __iomem		*pcie_reg_base,
-	void __iomem		*pbs_reg_base,
-	unsigned int		port_id)
-{
-	int i, ret;
-
-	pcie_port->pcie_reg_base = pcie_reg_base;
-	pcie_port->regs = &pcie_port->regs_ptrs;
-	pcie_port->ex_regs = NULL;
-	pcie_port->pbs_regs = pbs_reg_base;
-	pcie_port->port_id = port_id;
-	pcie_port->max_lanes = 0;
-
-	ret = al_pcie_rev_id_get(pbs_reg_base, pcie_reg_base);
-	if (ret < 0)
-		return ret;
-
-	pcie_port->rev_id = ret;
-
-	/* Zero all regs */
-	al_memset(pcie_port->regs, 0, sizeof(struct al_pcie_regs));
-
-	if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) ||
-		(pcie_port->rev_id == AL_PCIE_REV_ID_1)) {
-		struct al_pcie_rev1_regs __iomem *regs =
-			(struct al_pcie_rev1_regs __iomem *)pcie_reg_base;
-
-		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;
-		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;
-		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;
-		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;
-		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;
-		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;
-		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;
-		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;
-		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;
-		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;
-		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;
-		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;
-		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;
-		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;
-		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;
-		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;
-		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;
-		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;
-		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;
-		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;
-		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;
-		pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_setup;
-		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;
-		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;
-
-		pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;
-		pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;
-		pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;
-		pcie_port->regs->app.debug = &regs->app.debug;
-		pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;
-		pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;
-		pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;
-		pcie_port->regs->app.parity = &regs->app.parity;
-		pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
-		pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
-
-		if (pcie_port->rev_id == AL_PCIE_REV_ID_0) {
-			pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a_m0;
-			pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b_m0;
-		} else {
-			pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;
-			pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;
-		}
-
-		pcie_port->regs->core_space[0].config_header = regs->core_space.config_header;
-		pcie_port->regs->core_space[0].pcie_pm_cap_base = &regs->core_space.pcie_pm_cap_base;
-		pcie_port->regs->core_space[0].pcie_cap_base = &regs->core_space.pcie_cap_base;
-		pcie_port->regs->core_space[0].pcie_dev_cap_base = &regs->core_space.pcie_dev_cap_base;
-		pcie_port->regs->core_space[0].pcie_dev_ctrl_status = &regs->core_space.pcie_dev_ctrl_status;
-		pcie_port->regs->core_space[0].pcie_link_cap_base = &regs->core_space.pcie_link_cap_base;
-		pcie_port->regs->core_space[0].msix_cap_base = &regs->core_space.msix_cap_base;
-		pcie_port->regs->core_space[0].aer = &regs->core_space.aer;
-		pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.pcie_sec_ext_cap_base;
-
-		pcie_port->regs->port_regs = &regs->core_space.port_regs;
-
-	} else if (pcie_port->rev_id == AL_PCIE_REV_ID_2) {
-		struct al_pcie_rev2_regs __iomem *regs =
-			(struct al_pcie_rev2_regs __iomem *)pcie_reg_base;
-
-		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;
-		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;
-		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;
-		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;
-		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;
-		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;
-		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;
-		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;
-		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;
-		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;
-		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;
-		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;
-		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;
-		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;
-		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;
-		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;
-		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;
-		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;
-		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;
-		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;
-		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;
-		pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_setup;
-		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;
-		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;
-
-		pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;
-		pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;
-		pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;
-		pcie_port->regs->app.global_ctrl.corr_err_sts_int = &regs->app.global_ctrl.pended_corr_err_sts_int;
-		pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = &regs->app.global_ctrl.pended_uncorr_err_sts_int;
-		pcie_port->regs->app.debug = &regs->app.debug;
-		pcie_port->regs->app.ap_user_send_msg = &regs->app.ap_user_send_msg;
-		pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;
-		pcie_port->regs->app.soc_int[0].mask_inta_leg_3 = &regs->app.soc_int.mask_inta_leg_3;
-		pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;
-		pcie_port->regs->app.soc_int[0].mask_msi_leg_3 = &regs->app.soc_int.mask_msi_leg_3;
-		pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;
-		pcie_port->regs->app.parity = &regs->app.parity;
-		pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
-		pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
-		pcie_port->regs->app.status_per_func[0] = &regs->app.status_per_func;
-		pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;
-		pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;
-
-		pcie_port->regs->core_space[0].config_header = regs->core_space.config_header;
-		pcie_port->regs->core_space[0].pcie_pm_cap_base = &regs->core_space.pcie_pm_cap_base;
-		pcie_port->regs->core_space[0].pcie_cap_base = &regs->core_space.pcie_cap_base;
-		pcie_port->regs->core_space[0].pcie_dev_cap_base = &regs->core_space.pcie_dev_cap_base;
-		pcie_port->regs->core_space[0].pcie_dev_ctrl_status = &regs->core_space.pcie_dev_ctrl_status;
-		pcie_port->regs->core_space[0].pcie_link_cap_base = &regs->core_space.pcie_link_cap_base;
-		pcie_port->regs->core_space[0].msix_cap_base = &regs->core_space.msix_cap_base;
-		pcie_port->regs->core_space[0].aer = &regs->core_space.aer;
-		pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.pcie_sec_ext_cap_base;
-
-		pcie_port->regs->port_regs = &regs->core_space.port_regs;
-
-	} else if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
-		struct al_pcie_rev3_regs __iomem *regs =
-			(struct al_pcie_rev3_regs __iomem *)pcie_reg_base;
-		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;
-		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;
-		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;
-		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;
-		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;
-		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;
-		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;
-		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;
-		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;
-		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;
-		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;
-		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;
-		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;
-		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;
-		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;
-		pcie_port->regs->axi.conf.zero_lane4 = &regs->axi.conf.zero_lane4;
-		pcie_port->regs->axi.conf.zero_lane5 = &regs->axi.conf.zero_lane5;
-		pcie_port->regs->axi.conf.zero_lane6 = &regs->axi.conf.zero_lane6;
-		pcie_port->regs->axi.conf.zero_lane7 = &regs->axi.conf.zero_lane7;
-		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;
-		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;
-		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;
-		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;
-		pcie_port->regs->axi.status.lane[4] = &regs->axi.status.lane4;
-		pcie_port->regs->axi.status.lane[5] = &regs->axi.status.lane5;
-		pcie_port->regs->axi.status.lane[6] = &regs->axi.status.lane6;
-		pcie_port->regs->axi.status.lane[7] = &regs->axi.status.lane7;
-		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;
-		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;
-		pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_setup;
-		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;
-		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;
-		pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_0 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_0;
-		pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_1 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_1;
-		pcie_port->regs->axi.axi_attr_ovrd.pf_sel = &regs->axi.axi_attr_ovrd.pf_sel;
-
-		for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0;
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1;
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2;
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3;
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4;
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5;
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6;
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7;
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8;
-			pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9;
-		}
-
-		pcie_port->regs->axi.msg_attr_axuser_table.entry_vec = &regs->axi.msg_attr_axuser_table.entry_vec;
-
-		pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;
-		pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;
-		pcie_port->regs->app.global_ctrl.corr_err_sts_int = &regs->app.global_ctrl.pended_corr_err_sts_int;
-		pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = &regs->app.global_ctrl.pended_uncorr_err_sts_int;
-
-		for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
-			pcie_port->regs->app.global_ctrl.events_gen[i] = &regs->app.events_gen_per_func[i].events_gen;
-		}
-
-		pcie_port->regs->app.global_ctrl.sris_kp_counter = &regs->app.global_ctrl.sris_kp_counter_value;
-		pcie_port->regs->app.debug = &regs->app.debug;
-
-		for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
-			pcie_port->regs->app.soc_int[i].mask_inta_leg_0 = &regs->app.soc_int_per_func[i].mask_inta_leg_0;
-			pcie_port->regs->app.soc_int[i].mask_inta_leg_3 = &regs->app.soc_int_per_func[i].mask_inta_leg_3;
-			pcie_port->regs->app.soc_int[i].mask_msi_leg_0 = &regs->app.soc_int_per_func[i].mask_msi_leg_0;
-			pcie_port->regs->app.soc_int[i].mask_msi_leg_3 = &regs->app.soc_int_per_func[i].mask_msi_leg_3;
-		}
-
-		pcie_port->regs->app.ap_user_send_msg = &regs->app.ap_user_send_msg;
-		pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;
-		pcie_port->regs->app.parity = &regs->app.parity;
-		pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
-		pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
-
-		for (i = 0; i < AL_MAX_NUM_OF_PFS; i++)
-			pcie_port->regs->app.status_per_func[i] = &regs->app.status_per_func[i];
-
-		pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;
-		pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;
-		pcie_port->regs->app.int_grp_c = &regs->app.int_grp_c;
-		pcie_port->regs->app.int_grp_d = &regs->app.int_grp_d;
-
-		for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
-			pcie_port->regs->core_space[i].config_header = regs->core_space.func[i].config_header;
-			pcie_port->regs->core_space[i].pcie_pm_cap_base = &regs->core_space.func[i].pcie_pm_cap_base;
-			pcie_port->regs->core_space[i].pcie_cap_base = &regs->core_space.func[i].pcie_cap_base;
-			pcie_port->regs->core_space[i].pcie_dev_cap_base = &regs->core_space.func[i].pcie_dev_cap_base;
-			pcie_port->regs->core_space[i].pcie_dev_ctrl_status = &regs->core_space.func[i].pcie_dev_ctrl_status;
-			pcie_port->regs->core_space[i].pcie_link_cap_base = &regs->core_space.func[i].pcie_link_cap_base;
-			pcie_port->regs->core_space[i].msix_cap_base = &regs->core_space.func[i].msix_cap_base;
-			pcie_port->regs->core_space[i].aer = &regs->core_space.func[i].aer;
-			pcie_port->regs->core_space[i].tph_cap_base = &regs->core_space.func[i].tph_cap_base;
-
-		}
-
-		/* secondary extension capability only for PF0 */
-		pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.func[0].pcie_sec_ext_cap_base;
-
-		pcie_port->regs->port_regs = &regs->core_space.func[0].port_regs;
-
-	} else {
-		al_warn("%s: Revision ID is unknown\n",
-			__func__);
-		return -EINVAL;
-	}
-
-	/* set maximum number of physical functions */
-	pcie_port->max_num_of_pfs = al_pcie_port_max_num_of_pfs_get(pcie_port);
-
-	al_dbg("pcie port handle initialized. port id: %d, rev_id %d, regs base %p\n",
-	       port_id, pcie_port->rev_id, pcie_reg_base);
-	return 0;
-}
-
-/**
- * Initializes a PCIe Physical function handle structure
- * Caution: this function should not read/write to any register except for
- * reading RO register (REV_ID for example)
- */
-int
-al_pcie_pf_handle_init(
-	struct al_pcie_pf *pcie_pf,
-	struct al_pcie_port *pcie_port,
-	unsigned int pf_num)
-{
-	enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
-	al_assert(pf_num < pcie_port->max_num_of_pfs);
-
-	if (op_mode != AL_PCIE_OPERATING_MODE_EP) {
-		al_err("PCIe %d: can't init PF handle with operating mode [%d]\n",
-			pcie_port->port_id, op_mode);
-		return -EINVAL;
-	}
-
-	pcie_pf->pf_num = pf_num;
-	pcie_pf->pcie_port = pcie_port;
-
-	al_dbg("PCIe %d: pf handle initialized. pf number: %d, rev_id %d, regs %p\n",
-	       pcie_port->port_id, pcie_pf->pf_num, pcie_port->rev_id,
-	       pcie_port->regs);
-	return 0;
-}
-
-/************************** Pre PCIe Port Enable API **************************/
-
-/** configure pcie operating mode (root complex or endpoint) */
-int
-al_pcie_port_operating_mode_config(
-	struct al_pcie_port *pcie_port,
-	enum al_pcie_operating_mode mode)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t reg, device_type, new_device_type;
-
-	if (al_pcie_port_is_enabled(pcie_port)) {
-		al_err("PCIe %d: already enabled, cannot set operating mode\n",
-			pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	reg = al_reg_read32(regs->axi.pcie_global.conf);
-
-	device_type = AL_REG_FIELD_GET(reg,
-			PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK,
-			PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT);
-	if (mode == AL_PCIE_OPERATING_MODE_EP) {
-		new_device_type = PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_EP;
-	} else if (mode == AL_PCIE_OPERATING_MODE_RC) {
-		new_device_type = PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_RC;
-
-		if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
-			/* config 1 PF in RC mode */
-			al_reg_write32_masked(regs->axi.axi_attr_ovrd.pf_sel,
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_AXUSER |
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_REG |
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_ADDR_OFFSET_MASK |
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT0_OVRD |
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_AXUSER |
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_REG |
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_ADDR_OFFSET_MASK |
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT1_OVRD,
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_REG |
-				PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_REG);
-		}
-	} else {
-		al_err("PCIe %d: unknown operating mode: %d\n", pcie_port->port_id, mode);
-		return -EINVAL;
-	}
-
-	if (new_device_type == device_type) {
-		al_dbg("PCIe %d: operating mode already set to %s\n",
-		       pcie_port->port_id, (mode == AL_PCIE_OPERATING_MODE_EP) ?
-		       "EndPoint" : "Root Complex");
-		return 0;
-	}
-	al_info("PCIe %d: set operating mode to %s\n",
-		pcie_port->port_id, (mode == AL_PCIE_OPERATING_MODE_EP) ?
-		"EndPoint" : "Root Complex");
-	AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK,
-			 PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT,
-			 new_device_type);
-
-	al_reg_write32(regs->axi.pcie_global.conf, reg);
-
-	return 0;
-}
-
-int
-al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	if (al_pcie_port_is_enabled(pcie_port)) {
-		al_err("PCIe %d: already enabled, cannot set max lanes\n",
-			pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	/* convert to bitmask format (4 ->'b1111, 2 ->'b11, 1 -> 'b1) */
-	uint32_t active_lanes_val = AL_PCIE_PARSE_LANES(lanes);
-
-	al_reg_write32_masked(regs->axi.pcie_global.conf,
-		(pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
-		PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK :
-		PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK,
-		active_lanes_val);
-
-	pcie_port->max_lanes = lanes;
-	return 0;
-}
-
-int
-al_pcie_port_max_num_of_pfs_set(
-	struct al_pcie_port *pcie_port,
-	uint8_t max_num_of_pfs)
-{
-	if (al_pcie_port_is_enabled(pcie_port)) {
-		al_err("PCIe %d: already enabled, cannot set max num of PFs\n",
-			pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	if (pcie_port->rev_id == AL_PCIE_REV_ID_3)
-		al_assert(max_num_of_pfs <= REV3_MAX_NUM_OF_PFS);
-	else
-		al_assert(max_num_of_pfs == REV1_2_MAX_NUM_OF_PFS);
-
-	pcie_port->max_num_of_pfs = max_num_of_pfs;
-
-	return 0;
-}
-
-/* Inbound header credits and outstanding outbound reads configuration */
-int
-al_pcie_port_ib_hcrd_os_ob_reads_config(
-	struct al_pcie_port *pcie_port,
-	struct al_pcie_ib_hcrd_os_ob_reads_config *ib_hcrd_os_ob_reads_config)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	if (al_pcie_port_is_enabled(pcie_port)) {
-		al_err("PCIe %d: already enabled, cannot configure IB credits and OB OS reads\n",
-			pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	al_assert(ib_hcrd_os_ob_reads_config->nof_np_hdr > 0);
-
-	al_assert(ib_hcrd_os_ob_reads_config->nof_p_hdr > 0);
-
-	al_assert(ib_hcrd_os_ob_reads_config->nof_cpl_hdr > 0);
-
-	if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
-		al_assert(
-			(ib_hcrd_os_ob_reads_config->nof_cpl_hdr +
-			ib_hcrd_os_ob_reads_config->nof_np_hdr +
-			ib_hcrd_os_ob_reads_config->nof_p_hdr) ==
-			AL_PCIE_REV3_IB_HCRD_SUM);
-
-		al_reg_write32_masked(
-			regs->axi.init_fc.cfg,
-			PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_MASK |
-			PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_MASK |
-			PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_MASK,
-			(ib_hcrd_os_ob_reads_config->nof_p_hdr <<
-			 PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_SHIFT) |
-			(ib_hcrd_os_ob_reads_config->nof_np_hdr <<
-			 PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_SHIFT) |
-			(ib_hcrd_os_ob_reads_config->nof_cpl_hdr <<
-			 PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_SHIFT));
-	} else {
-		al_assert(
-			(ib_hcrd_os_ob_reads_config->nof_cpl_hdr +
-			ib_hcrd_os_ob_reads_config->nof_np_hdr +
-			ib_hcrd_os_ob_reads_config->nof_p_hdr) ==
-			AL_PCIE_REV_1_2_IB_HCRD_SUM);
-
-		al_reg_write32_masked(
-			regs->axi.init_fc.cfg,
-			PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_MASK |
-			PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_MASK |
-			PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_MASK,
-			(ib_hcrd_os_ob_reads_config->nof_p_hdr <<
-			 PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_SHIFT) |
-			(ib_hcrd_os_ob_reads_config->nof_np_hdr <<
-			 PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_SHIFT) |
-			(ib_hcrd_os_ob_reads_config->nof_cpl_hdr <<
-			 PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_SHIFT));
-	}
-
-	al_reg_write32_masked(
-		regs->axi.pre_configuration.pcie_core_setup,
-		PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_MASK,
-		ib_hcrd_os_ob_reads_config->nof_outstanding_ob_reads <<
-		PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_SHIFT);
-
-	/* Store 'nof_p_hdr' and 'nof_np_hdr' to be set in the core later */
-	pcie_port->ib_hcrd_config.nof_np_hdr =
-		ib_hcrd_os_ob_reads_config->nof_np_hdr;
-	pcie_port->ib_hcrd_config.nof_p_hdr =
-		ib_hcrd_os_ob_reads_config->nof_p_hdr;
-
-	return 0;
-}
-
-enum al_pcie_operating_mode
-al_pcie_operating_mode_get(
-	struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t reg, device_type;
-
-	al_assert(pcie_port);
-
-	reg = al_reg_read32(regs->axi.pcie_global.conf);
-
-	device_type = AL_REG_FIELD_GET(reg,
-			PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK,
-			PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT);
-
-	switch (device_type) {
-	case PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_EP:
-		return AL_PCIE_OPERATING_MODE_EP;
-	case PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_RC:
-		return AL_PCIE_OPERATING_MODE_RC;
-	default:
-		al_err("PCIe %d: unknown device type (%d) in global conf register.\n",
-			pcie_port->port_id, device_type);
-	}
-	return AL_PCIE_OPERATING_MODE_UNKNOWN;
-}
-
-/**************************** PCIe Port Enable API ****************************/
-
-/** Enable PCIe port (deassert reset) */
-int
-al_pcie_port_enable(struct al_pcie_port *pcie_port)
-{
-	struct al_pbs_regs *pbs_reg_base =
-				(struct al_pbs_regs *)pcie_port->pbs_regs;
-	struct al_pcie_regs *regs = pcie_port->regs;
-	unsigned int port_id = pcie_port->port_id;
-
-	/* pre-port-enable default functionality should be here */
-
-	/**
-	 * Set inbound header credit and outstanding outbound reads defaults
-	 * Must be called before port enable (PCIE_EXIST)
-	 */
-	al_pcie_ib_hcrd_os_ob_reads_config_default(pcie_port);
-
-	/*
-	 * Disable ATS capability
-	 * - must be done before core reset deasserted
-	 * - rev_id 0 - no effect, but no harm
-	 */
-	if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) ||
-		(pcie_port->rev_id == AL_PCIE_REV_ID_1) ||
-		(pcie_port->rev_id == AL_PCIE_REV_ID_2)) {
-		al_reg_write32_masked(
-			regs->axi.ordering.pos_cntl,
-			PCIE_AXI_CORE_SETUP_ATS_CAP_DIS,
-			PCIE_AXI_CORE_SETUP_ATS_CAP_DIS);
-	}
-
-	/* Deassert core reset */
-	al_reg_write32_masked(
-		&pbs_reg_base->unit.pcie_conf_1,
-		1 << (port_id + PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT),
-		1 << (port_id + PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT));
-
-	return 0;
-}
-
-/** Disable PCIe port (assert reset) */
-void
-al_pcie_port_disable(struct al_pcie_port *pcie_port)
-{
-	struct al_pbs_regs *pbs_reg_base =
-				(struct al_pbs_regs *)pcie_port->pbs_regs;
-	unsigned int port_id = pcie_port->port_id;
-
-	if (!al_pcie_port_is_enabled(pcie_port)) {
-		al_warn("PCIe %d: trying to disable a non-enabled port\n",
-			pcie_port->port_id);
-	}
-
-	/* Assert core reset */
-	al_reg_write32_masked(
-		&pbs_reg_base->unit.pcie_conf_1,
-		1 << (port_id + PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT),
-		0);
-}
-
-int
-al_pcie_port_memory_shutdown_set(
-	struct al_pcie_port	*pcie_port,
-	al_bool			enable)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t mask = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
-		PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN :
-		PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN;
-
-	if (!al_pcie_port_is_enabled(pcie_port)) {
-		al_err("PCIe %d: not enabled, cannot shutdown memory\n",
-			pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	al_reg_write32_masked(regs->axi.pcie_global.conf,
-		mask, enable == AL_TRUE ? mask : 0);
-
-	return 0;
-}
-
-al_bool
-al_pcie_port_is_enabled(struct al_pcie_port *pcie_port)
-{
-	struct al_pbs_regs *pbs_reg_base = (struct al_pbs_regs *)pcie_port->pbs_regs;
-	uint32_t pcie_exist = al_reg_read32(&pbs_reg_base->unit.pcie_conf_1);
-
-	uint32_t ports_enabled = AL_REG_FIELD_GET(pcie_exist,
-		PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_MASK,
-		PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT);
-
-	return (AL_REG_FIELD_GET(ports_enabled, AL_BIT(pcie_port->port_id),
-		pcie_port->port_id) == 1);
-}
-
-/*************************** PCIe Configuration API ***************************/
-
-/** configure pcie port (link params, etc..) */
-int
-al_pcie_port_config(struct al_pcie_port *pcie_port,
-			const struct al_pcie_port_config_params *params)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	enum al_pcie_operating_mode op_mode;
-	int status = 0;
-	int i;
-
-	if (!al_pcie_port_is_enabled(pcie_port)) {
-		al_err("PCIe %d: port not enabled, cannot configure port\n",
-			pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	if (al_pcie_is_link_started(pcie_port)) {
-		al_err("PCIe %d: link already started, cannot configure port\n",
-			pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	al_assert(pcie_port);
-	al_assert(params);
-
-	al_dbg("PCIe %d: port config\n", pcie_port->port_id);
-
-	op_mode = al_pcie_operating_mode_get(pcie_port);
-
-	/* if max lanes not specifies, read it from register */
-	if (pcie_port->max_lanes == 0) {
-		uint32_t global_conf = al_reg_read32(regs->axi.pcie_global.conf);
-		uint32_t act_lanes = AL_REG_FIELD_GET(global_conf,
-			(pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
-			PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK :
-			PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK,
-			PCIE_REVX_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_SHIFT);
-
-		switch(act_lanes) {
-		case 0x1:
-			pcie_port->max_lanes = 1;
-			break;
-		case 0x3:
-			pcie_port->max_lanes = 2;
-			break;
-		case 0xf:
-			pcie_port->max_lanes = 4;
-			break;
-		case 0xff:
-			pcie_port->max_lanes = 8;
-			break;
-		default:
-			pcie_port->max_lanes = 0;
-			al_err("PCIe %d: invalid max lanes val (0x%x)\n", pcie_port->port_id, act_lanes);
-			break;
-		}
-	}
-
-	if (params->link_params)
-		status = al_pcie_port_link_config(pcie_port, params->link_params);
-	if (status)
-		goto done;
-
-	/* Change max read request size to 256 bytes
-	 * Max Payload Size is remained untouched- it is the responsibility of
-	 * the host to change the MPS, if needed.
-	 */
-	for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
-		al_reg_write32_masked(regs->core_space[i].pcie_dev_ctrl_status,
-			PCIE_PORT_DEV_CTRL_STATUS_MRRS_MASK,
-			PCIE_PORT_DEV_CTRL_STATUS_MRRS_VAL_256);
-		if (pcie_port->rev_id != AL_PCIE_REV_ID_3)
-			break;
-	}
-
-	if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
-		/* Set maximum physical function numbers */
-		al_reg_write32_masked(
-			&regs->port_regs->timer_ctrl_max_func_num,
-			PCIE_PORT_GEN3_MAX_FUNC_NUM,
-			pcie_port->max_num_of_pfs - 1);
-
-		al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
-
-		/**
-		 * in EP mode, when we have more than 1 PF we need to assert
-		 * multi-pf support so the host scan all PFs
-		 */
-		if ((op_mode == AL_PCIE_OPERATING_MODE_EP) && (pcie_port->max_num_of_pfs > 1)) {
-			al_reg_write32_masked((uint32_t __iomem *)
-				(&regs->core_space[0].config_header[0] +
-				(PCIE_BIST_HEADER_TYPE_BASE >> 2)),
-				PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK,
-				PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK);
-		}
-
-		/* Disable TPH next pointer */
-		for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
-			al_reg_write32_masked(regs->core_space[i].tph_cap_base,
-			PCIE_TPH_NEXT_POINTER, 0);
-		}
-
-		al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
-	}
-
-
-	status = al_pcie_port_snoop_config(pcie_port, params->enable_axi_snoop);
-	if (status)
-		goto done;
-
-	al_pcie_port_ram_parity_int_config(pcie_port, params->enable_ram_parity_int);
-
-	al_pcie_port_axi_parity_int_config(pcie_port, params->enable_axi_parity_int);
-
-	al_pcie_port_relaxed_pcie_ordering_config(pcie_port, params->relaxed_ordering_params);
-
-	if (params->lat_rply_timers)
-		status = al_pcie_port_lat_rply_timers_config(pcie_port, params->lat_rply_timers);
-	if (status)
-		goto done;
-
-	if (params->gen2_params)
-		status = al_pcie_port_gen2_params_config(pcie_port, params->gen2_params);
-	if (status)
-		goto done;
-
-	if (params->gen3_params)
-		status = al_pcie_port_gen3_params_config(pcie_port, params->gen3_params);
-	if (status)
-		goto done;
-
-	if (params->tl_credits)
-		status = al_pcie_port_tl_credits_config(pcie_port, params->tl_credits);
-	if (status)
-		goto done;
-
-	if (params->features)
-		al_pcie_port_features_config(pcie_port, params->features);
-
-	if (params->sris_params)
-		status = al_pcie_port_sris_config(pcie_port, params->sris_params,
-						params->link_params->max_speed);
-	if (status)
-		goto done;
-
-	al_pcie_port_ib_hcrd_config(pcie_port);
-
-	if (params->fast_link_mode) {
-		al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
-			      1 << PCIE_PORT_LINK_CTRL_FAST_LINK_EN_SHIFT,
-			      1 << PCIE_PORT_LINK_CTRL_FAST_LINK_EN_SHIFT);
-	}
-
-	if (params->enable_axi_slave_err_resp)
-		al_reg_write32_masked(&regs->port_regs->axi_slave_err_resp,
-				1 << PCIE_PORT_AXI_SLAVE_ERR_RESP_ALL_MAPPING_SHIFT,
-				1 << PCIE_PORT_AXI_SLAVE_ERR_RESP_ALL_MAPPING_SHIFT);
-
-	/**
-	 * Addressing RMN: 5477
-	 *
-	 * RMN description:
-	 * address-decoder logic performs sub-target decoding even for transactions
-	 * which undergo target enforcement. thus, in case transaction's address is
-	 * inside any ECAM bar, the sub-target decoding will be set to ECAM, which
-	 * causes wrong handling by PCIe unit
-	 *
-	 * Software flow:
-	 * on EP mode only, turning on the iATU-enable bit (with the relevant mask
-	 * below) allows the PCIe unit to discard the ECAM bit which was asserted
-	 * by-mistake in the address-decoder
-	 */
-	if (op_mode == AL_PCIE_OPERATING_MODE_EP) {
-		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,
-			PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
-			(0) << PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT);
-		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_control,
-			PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_IATU_EN,
-			PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_IATU_EN);
-	}
-
-	if (op_mode == AL_PCIE_OPERATING_MODE_RC) {
-		/**
-		 * enable memory and I/O access from port when in RC mode
-		 * in RC mode, only core_space[0] is valid.
-		 */
-		al_reg_write16_masked(
-			(uint16_t __iomem *)(&regs->core_space[0].config_header[0] + (0x4 >> 2)),
-			0x7, /* Mem, MSE, IO */
-			0x7);
-
-		/* change the class code to match pci bridge */
-		al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
-
-		al_reg_write32_masked(
-			(uint32_t __iomem *)(&regs->core_space[0].config_header[0]
-			+ (PCI_CLASS_REVISION >> 2)),
-			0xFFFFFF00,
-			0x06040000);
-
-		al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
-
-		/**
-		 * Addressing RMN: 5702
-		 *
-		 * RMN description:
-		 * target bus mask default value in HW is: 0xFE, this enforces
-		 * setting the target bus for ports 1 and 3 when running on RC
-		 * mode since bit[20] in ECAM address in these cases is set
-		 *
-		 * Software flow:
-		 * on RC mode only, set target-bus value to 0xFF to prevent this
-		 * enforcement
-		 */
-		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,
-			PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
-			PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK);
-	}
-done:
-	al_dbg("PCIe %d: port config %s\n", pcie_port->port_id, status? "failed": "done");
-
-	return status;
-}
-
-int
-al_pcie_pf_config(
-	struct al_pcie_pf *pcie_pf,
-	const struct al_pcie_pf_config_params *params)
-{
-	struct al_pcie_port *pcie_port;
-	int status = 0;
-
-	al_assert(pcie_pf);
-	al_assert(params);
-
-	pcie_port = pcie_pf->pcie_port;
-
-	if (!al_pcie_port_is_enabled(pcie_port)) {
-		al_err("PCIe %d: port not enabled, cannot configure port\n", pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	al_dbg("PCIe %d: pf %d config\n", pcie_port->port_id, pcie_pf->pf_num);
-
-	if (params)
-		status = al_pcie_port_pf_params_config(pcie_pf, params);
-	if (status)
-		goto done;
-
-done:
-	al_dbg("PCIe %d: pf %d config %s\n",
-		pcie_port->port_id, pcie_pf->pf_num, status ? "failed" : "done");
-
-	return status;
-}
-
-/************************** PCIe Link Operations API **************************/
-
-/* start pcie link */
-int
-al_pcie_link_start(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;
-
-	if (!al_pcie_port_is_enabled(pcie_port)) {
-		al_err("PCIe %d: port not enabled, cannot start link\n",
-			pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	al_dbg("PCIe_%d: start port link.\n", pcie_port->port_id);
-
-	al_reg_write32_masked(
-			regs->app.global_ctrl.port_init,
-			PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK,
-			PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK);
-
-	return 0;
-}
-
-/* stop pcie link */
-int
-al_pcie_link_stop(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;
-
-	if (!al_pcie_is_link_started(pcie_port)) {
-		al_warn("PCIe %d: trying to stop a non-started link\n",
-			pcie_port->port_id);
-	}
-
-	al_dbg("PCIe_%d: stop port link.\n", pcie_port->port_id);
-
-	al_reg_write32_masked(
-			regs->app.global_ctrl.port_init,
-			PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK,
-			~PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK);
-
-	return 0;
-}
-
-/* wait for link up indication */
-int
-al_pcie_link_up_wait(struct al_pcie_port *pcie_port, uint32_t timeout_ms)
-{
-	int wait_count = timeout_ms * AL_PCIE_LINKUP_WAIT_INTERVALS_PER_SEC;
-
-	while (wait_count-- > 0)	{
-		if (al_pcie_check_link(pcie_port, NULL)) {
-			al_info("PCIe_%d: <<<<<<<<< Link up >>>>>>>>>\n", pcie_port->port_id);
-			return 0;
-		} else
-			al_dbg("PCIe_%d: No link up, %d attempts remaining\n",
-				pcie_port->port_id, wait_count);
-
-		al_udelay(AL_PCIE_LINKUP_WAIT_INTERVAL);
-	}
-	al_info("PCIE_%d: link is not established in time\n",
-				pcie_port->port_id);
-
-	return ETIMEDOUT;
-}
-
-/** get link status */
-int
-al_pcie_link_status(struct al_pcie_port *pcie_port,
-			struct al_pcie_link_status *status)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint16_t	pcie_lnksta;
-
-	al_assert(status);
-
-	status->link_up = al_pcie_check_link(pcie_port, &status->ltssm_state);
-
-	if (!status->link_up) {
-		status->speed = AL_PCIE_LINK_SPEED_DEFAULT;
-		status->lanes = 0;
-		return 0;
-	}
-
-	pcie_lnksta = al_reg_read16((uint16_t __iomem *)regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKSTA >> 1));
-
-	switch(pcie_lnksta & AL_PCI_EXP_LNKSTA_CLS) {
-		case AL_PCI_EXP_LNKSTA_CLS_2_5GB:
-			status->speed = AL_PCIE_LINK_SPEED_GEN1;
-			break;
-		case AL_PCI_EXP_LNKSTA_CLS_5_0GB:
-			status->speed = AL_PCIE_LINK_SPEED_GEN2;
-			break;
-		case AL_PCI_EXP_LNKSTA_CLS_8_0GB:
-			status->speed = AL_PCIE_LINK_SPEED_GEN3;
-			break;
-		default:
-			status->speed = AL_PCIE_LINK_SPEED_DEFAULT;
-			al_err("PCIe %d: unknown link speed indication. PCIE LINK STATUS %x\n",
-				pcie_port->port_id, pcie_lnksta);
-	}
-	status->lanes = (pcie_lnksta & AL_PCI_EXP_LNKSTA_NLW) >> AL_PCI_EXP_LNKSTA_NLW_SHIFT;
-	al_info("PCIe %d: Link up. speed gen%d negotiated width %d\n",
-		pcie_port->port_id, status->speed, status->lanes);
-
-	return 0;
-}
-
-/** get lane status */
-void
-al_pcie_lane_status_get(
-	struct al_pcie_port		*pcie_port,
-	unsigned int			lane,
-	struct al_pcie_lane_status	*status)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t lane_status;
-	uint32_t *reg_ptr;
-
-	al_assert(pcie_port);
-	al_assert(status);
-	al_assert((pcie_port->rev_id != AL_PCIE_REV_ID_1) || (lane < REV1_2_MAX_NUM_LANES));
-	al_assert((pcie_port->rev_id != AL_PCIE_REV_ID_2) || (lane < REV1_2_MAX_NUM_LANES));
-	al_assert((pcie_port->rev_id != AL_PCIE_REV_ID_3) || (lane < REV3_MAX_NUM_LANES));
-
-	reg_ptr = regs->axi.status.lane[lane];
-
-	/* Reset field is valid only when same value is read twice */
-	do {
-		lane_status = al_reg_read32(reg_ptr);
-		status->is_reset = !!(lane_status & PCIE_AXI_STATUS_LANE_IS_RESET);
-	} while (status->is_reset != (!!(al_reg_read32(reg_ptr) & PCIE_AXI_STATUS_LANE_IS_RESET)));
-
-	status->requested_speed =
-		(lane_status & PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_MASK) >>
-		PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_SHIFT;
-}
-
-/** trigger hot reset */
-int
-al_pcie_link_hot_reset(struct al_pcie_port *pcie_port, al_bool enable)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t events_gen;
-	al_bool app_reset_state;
-	enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
-
-	if (op_mode != AL_PCIE_OPERATING_MODE_RC) {
-		al_err("PCIe %d: hot-reset is applicable only for RC mode\n", pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	if (!al_pcie_is_link_started(pcie_port)) {
-		al_err("PCIe %d: link not started, cannot trigger hot-reset\n", pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	events_gen = al_reg_read32(regs->app.global_ctrl.events_gen[0]);
-	app_reset_state = events_gen & PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT;
-
-	if (enable && app_reset_state) {
-		al_err("PCIe %d: link is already in hot-reset state\n", pcie_port->port_id);
-		return -EINVAL;
-	} else if ((!enable) && (!(app_reset_state))) {
-		al_err("PCIe %d: link is already in non-hot-reset state\n", pcie_port->port_id);
-		return -EINVAL;
-	} else {
-		al_dbg("PCIe %d: %s hot-reset\n", pcie_port->port_id,
-			(enable ? "enabling" : "disabling"));
-		/* hot-reset functionality is implemented only for function 0 */
-		al_reg_write32_masked(regs->app.global_ctrl.events_gen[0],
-			PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT,
-			(enable ? PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT
-				: ~PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT));
-		return 0;
-	}
-}
-
-/** disable port link */
-int
-al_pcie_link_disable(struct al_pcie_port *pcie_port, al_bool disable)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t pcie_lnkctl;
-	al_bool link_disable_state;
-	enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
-
-	if (op_mode != AL_PCIE_OPERATING_MODE_RC) {
-		al_err("PCIe %d: hot-reset is applicable only for RC mode\n", pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	if (!al_pcie_is_link_started(pcie_port)) {
-		al_err("PCIe %d: link not started, cannot disable link\n", pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	pcie_lnkctl = al_reg_read32(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1));
-	link_disable_state = pcie_lnkctl & AL_PCI_EXP_LNKCTL_LNK_DIS;
-
-	if (disable && link_disable_state) {
-		al_err("PCIe %d: link is already in disable state\n", pcie_port->port_id);
-		return -EINVAL;
-	} else if ((!disable) && (!(link_disable_state))) {
-		al_err("PCIe %d: link is already in enable state\n", pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	al_dbg("PCIe %d: %s port\n", pcie_port->port_id, (disable ? "disabling" : "enabling"));
-	al_reg_write32_masked(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1),
-		AL_PCI_EXP_LNKCTL_LNK_DIS,
-		(disable ? AL_PCI_EXP_LNKCTL_LNK_DIS : ~AL_PCI_EXP_LNKCTL_LNK_DIS));
-	return 0;
-}
-
-/** retrain link */
-int
-al_pcie_link_retrain(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
-
-	if (op_mode != AL_PCIE_OPERATING_MODE_RC) {
-		al_err("PCIe %d: link-retrain is applicable only for RC mode\n",
-			pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	if (!al_pcie_is_link_started(pcie_port)) {
-		al_err("PCIe %d: link not started, cannot link-retrain\n", pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	al_reg_write32_masked(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1),
-	AL_PCI_EXP_LNKCTL_LNK_RTRN, AL_PCI_EXP_LNKCTL_LNK_RTRN);
-
-	return 0;
-}
-
-/* trigger speed change */
-int
-al_pcie_link_change_speed(struct al_pcie_port *pcie_port,
-			      enum al_pcie_link_speed new_speed)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	if (!al_pcie_is_link_started(pcie_port)) {
-		al_err("PCIe %d: link not started, cannot change speed\n", pcie_port->port_id);
-		return -EINVAL;
-	}
-
-	al_dbg("PCIe %d: changing speed to %d\n", pcie_port->port_id, new_speed);
-
-	al_pcie_port_link_speed_ctrl_set(pcie_port, new_speed);
-
-	al_reg_write32_masked(&regs->port_regs->gen2_ctrl,
-		PCIE_PORT_GEN2_CTRL_DIRECT_SPEED_CHANGE,
-		PCIE_PORT_GEN2_CTRL_DIRECT_SPEED_CHANGE);
-
-	return 0;
-}
-
-/* TODO: check if this function needed */
-int
-al_pcie_link_change_width(struct al_pcie_port *pcie_port,
-			      uint8_t width __attribute__((__unused__)))
-{
-	al_err("PCIe %d: link change width not implemented\n",
-		pcie_port->port_id);
-
-	return -ENOSYS;
-}
-
-/**************************** Post Link Start API *****************************/
-
-/************************** Snoop Configuration API ***************************/
-
-int
-al_pcie_port_snoop_config(struct al_pcie_port *pcie_port, al_bool enable_axi_snoop)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	/* Set snoop mode */
-	al_info("PCIE_%d: snoop mode %s\n",
-			pcie_port->port_id, enable_axi_snoop ? "enable" : "disable");
-
-	if (enable_axi_snoop) {
-		al_reg_write32_masked(regs->axi.ctrl.master_arctl,
-			PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP | PCIE_AXI_CTRL_MASTER_ARCTL_SNOOP,
-			PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP | PCIE_AXI_CTRL_MASTER_ARCTL_SNOOP);
-
-		al_reg_write32_masked(regs->axi.ctrl.master_awctl,
-			PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP | PCIE_AXI_CTRL_MASTER_AWCTL_SNOOP,
-			PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP | PCIE_AXI_CTRL_MASTER_AWCTL_SNOOP);
-	} else {
-		al_reg_write32_masked(regs->axi.ctrl.master_arctl,
-			PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP | PCIE_AXI_CTRL_MASTER_ARCTL_SNOOP,
-			PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP);
-
-		al_reg_write32_masked(regs->axi.ctrl.master_awctl,
-			PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP | PCIE_AXI_CTRL_MASTER_AWCTL_SNOOP,
-			PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP);
-	}
-	return 0;
-}
-
-/************************** Configuration Space API ***************************/
-
-/** get base address of pci configuration space header */
-int
-al_pcie_config_space_get(struct al_pcie_pf *pcie_pf,
-			     uint8_t __iomem **addr)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-
-	*addr = (uint8_t __iomem *)&regs->core_space[pcie_pf->pf_num].config_header[0];
-	return 0;
-}
-
-/* Read data from the local configuration space */
-uint32_t
-al_pcie_local_cfg_space_read(
-	struct al_pcie_pf	*pcie_pf,
-	unsigned int		reg_offset)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	uint32_t data;
-
-	data = al_reg_read32(&regs->core_space[pcie_pf->pf_num].config_header[reg_offset]);
-
-	return data;
-}
-
-/* Write data to the local configuration space */
-void
-al_pcie_local_cfg_space_write(
-	struct al_pcie_pf	*pcie_pf,
-	unsigned int		reg_offset,
-	uint32_t		data,
-	al_bool			cs2,
-	al_bool			allow_ro_wr)
-{
-	struct al_pcie_port *pcie_port = pcie_pf->pcie_port;
-	struct al_pcie_regs *regs = pcie_port->regs;
-	unsigned int pf_num = pcie_pf->pf_num;
-	uint32_t *offset = &regs->core_space[pf_num].config_header[reg_offset];
-
-	if (allow_ro_wr)
-		al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
-
-	if (cs2 == AL_FALSE)
-		al_reg_write32(offset, data);
-	else
-		al_reg_write32_dbi_cs2(pcie_port, offset, data);
-
-	if (allow_ro_wr)
-		al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
-}
-
-/** set target_bus and mask_target_bus */
-int
-al_pcie_target_bus_set(
-	struct al_pcie_port *pcie_port,
-	uint8_t target_bus,
-	uint8_t mask_target_bus)
-{
-	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;
-	uint32_t reg;
-
-	reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);
-	AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
-			PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT,
-			mask_target_bus);
-	AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK,
-			PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_SHIFT,
-			target_bus);
-	al_reg_write32(regs->axi.ob_ctrl.cfg_target_bus, reg);
-	return 0;
-}
-
-/** get target_bus and mask_target_bus */
-int
-al_pcie_target_bus_get(
-	struct al_pcie_port *pcie_port,
-	uint8_t *target_bus,
-	uint8_t *mask_target_bus)
-{
-	struct al_pcie_regs *regs = (struct al_pcie_regs *)pcie_port->regs;
-	uint32_t reg;
-
-	al_assert(target_bus);
-	al_assert(mask_target_bus);
-
-	reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);
-
-	*mask_target_bus = AL_REG_FIELD_GET(reg,
-				PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
-				PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT);
-	*target_bus = AL_REG_FIELD_GET(reg,
-			PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK,
-			PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_SHIFT);
-	return 0;
-}
-
-/** Set secondary bus number */
-int
-al_pcie_secondary_bus_set(struct al_pcie_port *pcie_port, uint8_t secbus)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	uint32_t secbus_val = (secbus <<
-			PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_SHIFT);
-
-	al_reg_write32_masked(
-		regs->axi.ob_ctrl.cfg_control,
-		PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_MASK,
-		secbus_val);
-	return 0;
-}
-
-/** Set sub-ordinary bus number */
-int
-al_pcie_subordinary_bus_set(struct al_pcie_port *pcie_port, uint8_t subbus)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	uint32_t subbus_val = (subbus <<
-			PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_SHIFT);
-
-	al_reg_write32_masked(
-		regs->axi.ob_ctrl.cfg_control,
-		PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_MASK,
-		subbus_val);
-	return 0;
-}
-
-/* Enable/disable deferring incoming configuration requests */
-void
-al_pcie_app_req_retry_set(
-	struct al_pcie_port	*pcie_port,
-	al_bool			en)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint32_t mask = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
-		PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN :
-		PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN;
-
-	al_reg_write32_masked(regs->app.global_ctrl.pm_control,
-		mask, (en == AL_TRUE) ? mask : 0);
-}
-
-/*************** Internal Address Translation Unit (ATU) API ******************/
-
-/** program internal ATU region entry */
-int
-al_pcie_atu_region_set(
-	struct al_pcie_port *pcie_port,
-	struct al_pcie_atu_region *atu_region)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
-	uint32_t reg = 0;
-
-	/**
-	 * Addressing RMN: 5384
-	 *
-	 * RMN description:
-	 * From SNPS (also included in the data book) Dynamic iATU Programming
-	 * With AHB/AXI Bridge Module When the bridge slave interface clock
-	 * (hresetn or slv_aclk) is asynchronous to the PCIe native core clock
-	 * (core_clk), you must not update the iATU registers while operations
-	 * are in progress on the AHB/AXI bridge slave interface. The iATU
-	 * registers are in the core_clk clock domain. The register outputs are
-	 * used in the AHB/AXI bridge slave interface clock domain. There is no
-	 * synchronization logic between these registers and the AHB/AXI bridge
-	 * slave interface.
-	 *
-	 * Software flow:
-	 * Do not allow configuring Outbound iATU after link is started
-	 */
-	if ((atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND)
-		&& (al_pcie_is_link_started(pcie_port))) {
-		if (!atu_region->enforce_ob_atu_region_set) {
-			al_err("PCIe %d: setting OB iATU after link is started is not allowed\n",
-				pcie_port->port_id);
-			return -EINVAL;
-		} else {
-			al_info("PCIe %d: setting OB iATU even after link is started\n",
-				pcie_port->port_id);
-		}
-	}
-
-	/*TODO : add sanity check */
-	AL_REG_FIELD_SET(reg, 0xF, 0, atu_region->index);
-	AL_REG_BIT_VAL_SET(reg, 31, atu_region->direction);
-	al_reg_write32(&regs->port_regs->iatu.index, reg);
-
-	al_reg_write32(&regs->port_regs->iatu.lower_base_addr,
-			(uint32_t)(atu_region->base_addr & 0xFFFFFFFF));
-	al_reg_write32(&regs->port_regs->iatu.upper_base_addr,
-			(uint32_t)((atu_region->base_addr >> 32)& 0xFFFFFFFF));
-	al_reg_write32(&regs->port_regs->iatu.lower_target_addr,
-			(uint32_t)(atu_region->target_addr & 0xFFFFFFFF));
-	al_reg_write32(&regs->port_regs->iatu.upper_target_addr,
-			(uint32_t)((atu_region->target_addr >> 32)& 0xFFFFFFFF));
-
-	/* configure the limit, not needed when working in BAR match mode */
-	if (atu_region->match_mode == 0) {
-		uint32_t limit_reg_val;
-		if (pcie_port->rev_id > AL_PCIE_REV_ID_0) {
-			uint32_t *limit_ext_reg =
-				(atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND) ?
-				&regs->app.atu.out_mask_pair[atu_region->index / 2] :
-				&regs->app.atu.in_mask_pair[atu_region->index / 2];
-			uint32_t limit_ext_reg_mask =
-				(atu_region->index % 2) ?
-				PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_MASK :
-				PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_MASK;
-			unsigned int limit_ext_reg_shift =
-				(atu_region->index % 2) ?
-				PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_SHIFT :
-				PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_SHIFT;
-			uint64_t limit_sz_msk =
-				atu_region->limit - atu_region->base_addr;
-			uint32_t limit_ext_reg_val = (uint32_t)(((limit_sz_msk) >>
-						32) & 0xFFFFFFFF);
-
-			if (limit_ext_reg_val) {
-				limit_reg_val =	(uint32_t)((limit_sz_msk) & 0xFFFFFFFF);
-				al_assert(limit_reg_val == 0xFFFFFFFF);
-			} else {
-				limit_reg_val = (uint32_t)(atu_region->limit &
-						0xFFFFFFFF);
-			}
-
-			al_reg_write32_masked(
-					limit_ext_reg,
-					limit_ext_reg_mask,
-					limit_ext_reg_val << limit_ext_reg_shift);
-		} else {
-			limit_reg_val = (uint32_t)(atu_region->limit & 0xFFFFFFFF);
-		}
-
-		al_reg_write32(&regs->port_regs->iatu.limit_addr,
-				limit_reg_val);
-	}
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg, 0x1F, 0, atu_region->tlp_type);
-	AL_REG_FIELD_SET(reg, 0x3 << 9, 9, atu_region->attr);
-
-
-	if ((pcie_port->rev_id == AL_PCIE_REV_ID_3)
-		&& (op_mode == AL_PCIE_OPERATING_MODE_EP)
-		&& (atu_region->function_match_bypass_mode)) {
-		AL_REG_FIELD_SET(reg,
-			PCIE_IATU_CR1_FUNC_NUM_MASK,
-			PCIE_IATU_CR1_FUNC_NUM_SHIFT,
-			atu_region->function_match_bypass_mode_number);
-	}
-
-	al_reg_write32(&regs->port_regs->iatu.cr1, reg);
-
-	/* Enable/disable the region. */
-	reg = 0;
-	AL_REG_FIELD_SET(reg, 0xFF, 0, atu_region->msg_code);
-	AL_REG_FIELD_SET(reg, 0x700, 8, atu_region->bar_number);
-	AL_REG_FIELD_SET(reg, 0x3 << 24, 24, atu_region->response);
-	AL_REG_BIT_VAL_SET(reg, 16, atu_region->enable_attr_match_mode == AL_TRUE);
-	AL_REG_BIT_VAL_SET(reg, 21, atu_region->enable_msg_match_mode == AL_TRUE);
-	AL_REG_BIT_VAL_SET(reg, 28, atu_region->cfg_shift_mode == AL_TRUE);
-	AL_REG_BIT_VAL_SET(reg, 29, atu_region->invert_matching == AL_TRUE);
-	if (atu_region->tlp_type == AL_PCIE_TLP_TYPE_MEM || atu_region->tlp_type == AL_PCIE_TLP_TYPE_IO)
-		AL_REG_BIT_VAL_SET(reg, 30, !!atu_region->match_mode);
-	AL_REG_BIT_VAL_SET(reg, 31, !!atu_region->enable);
-
-	/* In outbound, enable function bypass
-	 * In inbound, enable function match mode
-	 * Note: this is the same bit, has different meanings in ob/ib ATUs
-	 */
-	if (op_mode == AL_PCIE_OPERATING_MODE_EP)
-		AL_REG_FIELD_SET(reg,
-			PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_MASK,
-			PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_SHIFT,
-			atu_region->function_match_bypass_mode ? 0x1 : 0x0);
-
-	al_reg_write32(&regs->port_regs->iatu.cr2, reg);
-
-	return 0;
-}
-
-/** obtains internal ATU region base/target addresses */
-void
-al_pcie_atu_region_get_fields(
-	struct al_pcie_port *pcie_port,
-	enum al_pcie_atu_dir direction, uint8_t index,
-	al_bool *enable, uint64_t *base_addr, uint64_t *target_addr)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-	uint64_t high_addr;
-	uint32_t reg = 0;
-
-	AL_REG_FIELD_SET(reg, 0xF, 0, index);
-	AL_REG_BIT_VAL_SET(reg, 31, direction);
-	al_reg_write32(&regs->port_regs->iatu.index, reg);
-
-	*base_addr = al_reg_read32(&regs->port_regs->iatu.lower_base_addr);
-	high_addr = al_reg_read32(&regs->port_regs->iatu.upper_base_addr);
-	high_addr <<= 32;
-	*base_addr |= high_addr;
-
-	*target_addr = al_reg_read32(&regs->port_regs->iatu.lower_target_addr);
-	high_addr = al_reg_read32(&regs->port_regs->iatu.upper_target_addr);
-	high_addr <<= 32;
-	*target_addr |= high_addr;
-
-	reg = al_reg_read32(&regs->port_regs->iatu.cr1);
-	*enable = AL_REG_BIT_GET(reg, 31) ? AL_TRUE : AL_FALSE;
-}
-
-void
-al_pcie_axi_io_config(
-	struct al_pcie_port *pcie_port,
-	al_phys_addr_t start,
-	al_phys_addr_t end)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	al_reg_write32(regs->axi.ob_ctrl.io_start_h,
-			(uint32_t)((start >> 32) & 0xFFFFFFFF));
-
-	al_reg_write32(regs->axi.ob_ctrl.io_start_l,
-			(uint32_t)(start & 0xFFFFFFFF));
-
-	al_reg_write32(regs->axi.ob_ctrl.io_limit_h,
-			(uint32_t)((end >> 32) & 0xFFFFFFFF));
-
-	al_reg_write32(regs->axi.ob_ctrl.io_limit_l,
-			(uint32_t)(end & 0xFFFFFFFF));
-
-	al_reg_write32_masked(regs->axi.ctrl.slv_ctl,
-			      PCIE_AXI_CTRL_SLV_CTRL_IO_BAR_EN,
-			      PCIE_AXI_CTRL_SLV_CTRL_IO_BAR_EN);
-}
-
-/************** Interrupt generation (Endpoint mode Only) API *****************/
-
-/** generate INTx Assert/DeAssert Message */
-int
-al_pcie_legacy_int_gen(
-	struct al_pcie_pf		*pcie_pf,
-	al_bool				assert,
-	enum al_pcie_legacy_int_type	type)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	unsigned int pf_num = pcie_pf->pf_num;
-	uint32_t reg;
-
-	al_assert(type == AL_PCIE_LEGACY_INTA); /* only INTA supported */
-	reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);
-	AL_REG_BIT_VAL_SET(reg, 3, !!assert);
-	al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);
-
-	return 0;
-}
-
-/** generate MSI interrupt */
-int
-al_pcie_msi_int_gen(struct al_pcie_pf *pcie_pf, uint8_t vector)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	unsigned int pf_num = pcie_pf->pf_num;
-	uint32_t reg;
-
-	/* set msi vector and clear MSI request */
-	reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);
-	AL_REG_BIT_CLEAR(reg, 4);
-	AL_REG_FIELD_SET(reg,
-			PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK,
-			PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_SHIFT,
-			vector);
-	al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);
-	/* set MSI request */
-	AL_REG_BIT_SET(reg, 4);
-	al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);
-
-	return 0;
-}
-
-/** configure MSIX capability */
-int
-al_pcie_msix_config(
-	struct al_pcie_pf *pcie_pf,
-	struct al_pcie_msix_params *msix_params)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	unsigned int pf_num = pcie_pf->pf_num;
-	uint32_t msix_reg0;
-
-	al_pcie_port_wr_to_ro_set(pcie_pf->pcie_port, AL_TRUE);
-
-	msix_reg0 = al_reg_read32(regs->core_space[pf_num].msix_cap_base);
-
-	msix_reg0 &= ~(AL_PCI_MSIX_MSGCTRL_TBL_SIZE << AL_PCI_MSIX_MSGCTRL_TBL_SIZE_SHIFT);
-	msix_reg0 |= ((msix_params->table_size - 1) & AL_PCI_MSIX_MSGCTRL_TBL_SIZE) <<
-			AL_PCI_MSIX_MSGCTRL_TBL_SIZE_SHIFT;
-	al_reg_write32(regs->core_space[pf_num].msix_cap_base, msix_reg0);
-
-	/* Table offset & BAR */
-	al_reg_write32(regs->core_space[pf_num].msix_cap_base + (AL_PCI_MSIX_TABLE >> 2),
-		       (msix_params->table_offset & AL_PCI_MSIX_TABLE_OFFSET) |
-			       (msix_params->table_bar & AL_PCI_MSIX_TABLE_BAR));
-	/* PBA offset & BAR */
-	al_reg_write32(regs->core_space[pf_num].msix_cap_base + (AL_PCI_MSIX_PBA >> 2),
-		       (msix_params->pba_offset & AL_PCI_MSIX_PBA_OFFSET) |
-			       (msix_params->pba_bar & AL_PCI_MSIX_PBA_BAR));
-
-	al_pcie_port_wr_to_ro_set(pcie_pf->pcie_port, AL_FALSE);
-
-	return 0;
-}
-
-/** check whether MSIX is enabled */
-al_bool
-al_pcie_msix_enabled(struct al_pcie_pf	*pcie_pf)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	uint32_t msix_reg0 = al_reg_read32(regs->core_space[pcie_pf->pf_num].msix_cap_base);
-
-	if (msix_reg0 & AL_PCI_MSIX_MSGCTRL_EN)
-		return AL_TRUE;
-	return AL_FALSE;
-}
-
-/** check whether MSIX is masked */
-al_bool
-al_pcie_msix_masked(struct al_pcie_pf *pcie_pf)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	uint32_t msix_reg0 = al_reg_read32(regs->core_space[pcie_pf->pf_num].msix_cap_base);
-
-	if (msix_reg0 & AL_PCI_MSIX_MSGCTRL_MASK)
-		return AL_TRUE;
-	return AL_FALSE;
-}
-
-/******************** Advanced Error Reporting (AER) API **********************/
-
-/** configure AER capability */
-int
-al_pcie_aer_config(
-	struct al_pcie_pf		*pcie_pf,
-	struct al_pcie_aer_params	*params)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
-	uint32_t reg_val;
-
-	reg_val = al_reg_read32(&aer_regs->header);
-
-	if (((reg_val & PCIE_AER_CAP_ID_MASK) >> PCIE_AER_CAP_ID_SHIFT) !=
-		PCIE_AER_CAP_ID_VAL)
-		return -EIO;
-
-	if (((reg_val & PCIE_AER_CAP_VER_MASK) >> PCIE_AER_CAP_VER_SHIFT) !=
-		PCIE_AER_CAP_VER_VAL)
-		return -EIO;
-
-	al_reg_write32(&aer_regs->corr_err_mask, ~params->enabled_corr_err);
-
-	al_reg_write32(&aer_regs->uncorr_err_mask,
-		(~params->enabled_uncorr_non_fatal_err) |
-		(~params->enabled_uncorr_fatal_err));
-
-	al_reg_write32(&aer_regs->uncorr_err_severity,
-		params->enabled_uncorr_fatal_err);
-
-	al_reg_write32(&aer_regs->cap_and_ctrl,
-		(params->ecrc_gen_en ? PCIE_AER_CTRL_STAT_ECRC_GEN_EN : 0) |
-		(params->ecrc_chk_en ? PCIE_AER_CTRL_STAT_ECRC_CHK_EN : 0));
-
-	al_reg_write32_masked(
-		regs->core_space[pcie_pf->pf_num].pcie_dev_ctrl_status,
-		PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN |
-		PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN |
-		PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN |
-		PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN,
-		(params->enabled_corr_err ?
-		 PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN : 0) |
-		(params->enabled_uncorr_non_fatal_err ?
-		 PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN : 0) |
-		(params->enabled_uncorr_fatal_err ?
-		 PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN : 0) |
-		((params->enabled_uncorr_non_fatal_err &
-		  AL_PCIE_AER_UNCORR_UNSUPRT_REQ_ERR) ?
-		 PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN : 0) |
-		((params->enabled_uncorr_fatal_err &
-		  AL_PCIE_AER_UNCORR_UNSUPRT_REQ_ERR) ?
-		 PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN : 0));
-
-	return 0;
-}
-
-/** AER uncorretable errors get and clear */
-unsigned int
-al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf	*pcie_pf)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
-	uint32_t reg_val;
-
-	reg_val = al_reg_read32(&aer_regs->uncorr_err_stat);
-	al_reg_write32(&aer_regs->uncorr_err_stat, reg_val);
-
-	return reg_val;
-}
-
-/** AER corretable errors get and clear */
-unsigned int
-al_pcie_aer_corr_get_and_clear(struct al_pcie_pf *pcie_pf)
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
-	uint32_t reg_val;
-
-	reg_val = al_reg_read32(&aer_regs->corr_err_stat);
-	al_reg_write32(&aer_regs->corr_err_stat, reg_val);
-
-	return reg_val;
-}
-
-#if (AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS != 4)
-#error Wrong assumption!
-#endif
-
-/** AER get the header for the TLP corresponding to a detected error */
-void
-al_pcie_aer_err_tlp_hdr_get(
-	struct al_pcie_pf *pcie_pf,
-	uint32_t hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS])
-{
-	struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
-	struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
-	int i;
-
-	for (i = 0; i < AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS; i++)
-		hdr[i] = al_reg_read32(&aer_regs->header_log[i]);
-}
-
-/********************** Loopback mode (RC and Endpoint modes) ************/
-
-/** enter local pipe loopback mode */
-int
-al_pcie_local_pipe_loopback_enter(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	al_dbg("PCIe %d: Enter LOCAL PIPE Loopback mode", pcie_port->port_id);
-
-	al_reg_write32_masked(&regs->port_regs->pipe_loopback_ctrl,
-			      1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT,
-			      1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT);
-
-	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
-			      1 << PCIE_PORT_LINK_CTRL_LB_EN_SHIFT,
-			      1 << PCIE_PORT_LINK_CTRL_LB_EN_SHIFT);
-
-	return 0;
-}
-
-/**
- * @brief exit local pipe loopback mode
- *
- * @param pcie_port	pcie port handle
- * @return		0 if no error found
- */
-int
-al_pcie_local_pipe_loopback_exit(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	al_dbg("PCIe %d: Exit LOCAL PIPE Loopback mode", pcie_port->port_id);
-
-	al_reg_write32_masked(&regs->port_regs->pipe_loopback_ctrl,
-			      1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT,
-			      0);
-
-	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
-			      1 << PCIE_PORT_LINK_CTRL_LB_EN_SHIFT,
-			      0);
-	return 0;
-}
-
-/** enter remote loopback mode */
-int
-al_pcie_remote_loopback_enter(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	al_dbg("PCIe %d: Enter REMOTE Loopback mode", pcie_port->port_id);
-
-	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
-			      1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT,
-			      1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT);
-
-	return 0;
-}
-
-/**
- * @brief   exit remote loopback mode
- *
- * @param   pcie_port pcie port handle
- * @return  0 if no error found
- */
-int
-al_pcie_remote_loopback_exit(struct al_pcie_port *pcie_port)
-{
-	struct al_pcie_regs *regs = pcie_port->regs;
-
-	al_dbg("PCIe %d: Exit REMOTE Loopback mode", pcie_port->port_id);
-
-	al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
-			      1 << PCIE_PORT_LINK_CTRL_LB_EN_SHIFT,
-			      0);
-	return 0;
-}
diff --git a/sys/contrib/alpine-hal/eth/al_hal_pcie.h b/sys/contrib/alpine-hal/eth/al_hal_pcie.h
deleted file mode 100644
index 1ddc8eb70749..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_pcie.h
+++ /dev/null
@@ -1,1157 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup grouppcie PCI Express Controller
- *  @{
- * @section overview Overview
- * This header file provide API for the HAL driver of the pcie port, the driver
- * provides the following functionalities:
- * - Port initialization
- * - Link operation
- * - Interrupts transactions generation (Endpoint mode).
- * - Configuration Access management functions
- * - Internal Translation Unit programming
- *
- * This API does not provide the following:
- * - PCIe transactions generation and reception (except interrupts as mentioned
- *   above) as this functionality is done by the port without need for sw
- *   intervention.
- * - Configuration Access: those transactions are generated automatically by
- *   the port (ECAM or ATU mode) when the CPU issues memory transaction
- *   through the fabric toward the PCIe port. This API provides management
- *   function for controlling the Configuration Access type and bus destination
- * - Interrupt Handling.
- * - Message Generation: common used messages are automatically generated, also,
- *   the ATU generic mechanism for generating various kind of messages.
- * - PCIe Port Management: both link and port power management features can be
- *   managed using the PCI/PCIe standard power management and PCIe capabilities
- *   registers.
- * - PCIe link and protocol error handling: the feature can be managed using
- *   the Advanced Error Handling PCIe capability registers.
- *
- * @section flows Software Flows
- * @subsection init Initialization
- *   - allocation and set zeros al_pcie_port and al_pcie_pf structures handles
- *   - call al_pcie_port_handle_init() with pointer to the allocated
- *     al_pcie_port handle, address of the port internal registers space, and
- *     port id.
- *   - call al_pcie_pf_handle_init() with pointer to the al_pcie_port handle
- *     and pf_number.
- *   - set the port mode, End-Point or Root-Compex (default).
- *   - set number of lanes connected to the controller.
- *   - enable the controller using the al_pcie_port_enable(). note that this
- *     function expect the virtual address of the PBS Functional Registers.
- *   - wait for 2000 South-bridge cycles.
- *   - prepare al_pcie_port_config_params and al_pcie_pf_config_params
- *     structures depending on chip, board and system configuration.
- *     for example, when using the port as root complex, the operating_mode
- *     field should be set to AL_PCIE_OPERATING_MODE_RC. In this example we
- *     prepare the following configuration:
- *     For port configuration
- *     - Root Complex mode
- *     - Set the Max Link Speed to Gen2
- *     - Set the max lanes width to 2 (x2)
- *     - Disable reversal mode
- *     - Enable Snoops to support I/O Hardware cache coherency
- *     - Enable pcie core RAM parity
- *     - Enable pcie core AXI parity
- *     - Keep transaction layer default credits
- *     For pf configuration
- *     - No EP parameters
- *     - No SR-IOV parameters
- *     so the structures we prepare:
- *     @code
- *     - struct al_pcie_link_params link_params = {
- *		AL_PCIE_LINK_SPEED_GEN2,
- *		AL_FALSE,	// disable reversal mode
- *		AL_PCIE_MPS_DEFAULT};
- *
- *     - struct al_pcie_port_config_params config_params = {
- *		&link_params,
- *		AL_TRUE, // enable Snoop for inbound memory transactions
- *		AL_TRUE, // enable pcie port RAM parity
- *		AL_TRUE, // enable pcie port AXI parity
- *		NULL, // use default latency/replay timers
- *		NULL, // use default gen2 pipe params
- *		NULL, // gen3_params not needed when max speed set to Gen2
- *		NULL, // don't change TL credits
- *		NULL, // end point params not needed
- *		AL_FALSE, //no fast link
- *		AL_FALSE};	//return 0xFFFFFFFF for read transactions with
- *				//pci target error
- *	@endcode
- *	- now call al_pcie_port_config() with pcie_port and port_config_params
- * @subsection link-init Link Initialization
- *  - once the port configured, we can start PCIe link:
- *  - call al_pcie_link_start()
- *  - call al_pcie_link_up_wait()
- *  - allocate al_pcie_link_status struct and call al_pcie_link_status() and
- *    check the link is established.
- *
- *  @subsection  cap Configuration Access Preparation
- *  - Once the link is established, we can prepare the port for pci
- *  configuration access, this stage requires system knowledge about the PCI
- *  buses enumeration. For example, if 5 buses were discovered on previously
- *  scanned root complex port, then we should start enumeration from bus 5 (PCI
- *  secondary bus), the sub-ordinary bus will be temporarily set to maximum
- *  value (255) until the scan process under this bus is finished, then it will
- *  updated to the maximum bus value found. So we use the following sequence:
- *  - call al_pcie_secondary_bus_set() with sec-bus = 5
- *  - call al_pcie_subordinary_bus_set() with sub-bus = 255
- *
- *  @subsection cfg Configuration (Cfg) Access Generation
- *  - we assume using ECAM method, in this method, the software issues pcie Cfg
- *  access by accessing the ECAM memory space of the pcie port. For example, to
- *  issue 4 byte Cfg Read from bus B, Device D, Function F and register R, the
- *  software issues 4 byte read access to the following physical address
- *  ECAM base address of the port + (B << 20) + (D << 15) + (F << 12) + R.
- *  But, as the default size of the ECAM address space is less than
- *  needed full range (256MB), we modify the target_bus value prior to Cfg
- *  access in order make the port generate Cfg access with bus value set to the
- *  value of the target_bus rather than bits 27:20 of the physical address.
- *  - call al_pcie_target_bus_set() with target_bus set to the required bus of
- *   the next Cfg access to be issued, mask_target_bus will be set to 0xff.
- *   no need to call that function if the next Cfg access bus equals to the last
- *   value set to target_bus.
- *
- *      @file  al_hal_pcie.h
- *      @brief HAL Driver Header for the Annapurna Labs PCI Express port.
- */
-
-#ifndef _AL_HAL_PCIE_H_
-#define _AL_HAL_PCIE_H_
-
-#include "al_hal_common.h"
-#include "al_hal_pcie_regs.h"
-
-/******************************************************************************/
-/********************************* Constants **********************************/
-/******************************************************************************/
-
-/** Inbound header credits sum - rev 0/1/2 */
-#define AL_PCIE_REV_1_2_IB_HCRD_SUM			97
-/** Inbound header credits sum - rev 3 */
-#define AL_PCIE_REV3_IB_HCRD_SUM			259
-
-/** Number of extended registers */
-#define AL_PCIE_EX_REGS_NUM				40
-
-/*******************************************************************************
- * PCIe AER uncorrectable error bits
- * To be used with the following functions:
- * - al_pcie_aer_config
- * - al_pcie_aer_uncorr_get_and_clear
- ******************************************************************************/
-/** Data Link Protocol Error */
-#define AL_PCIE_AER_UNCORR_DLP_ERR			AL_BIT(4)
-/** Poisoned TLP */
-#define AL_PCIE_AER_UNCORR_POISIONED_TLP		AL_BIT(12)
-/** Flow Control Protocol Error */
-#define AL_PCIE_AER_UNCORR_FLOW_CTRL_ERR		AL_BIT(13)
-/** Completion Timeout */
-#define AL_PCIE_AER_UNCORR_COMPL_TO			AL_BIT(14)
-/** Completer Abort */
-#define AL_PCIE_AER_UNCORR_COMPL_ABT			AL_BIT(15)
-/** Unexpected Completion */
-#define AL_PCIE_AER_UNCORR_UNEXPCTED_COMPL		AL_BIT(16)
-/** Receiver Overflow */
-#define AL_PCIE_AER_UNCORR_RCV_OVRFLW			AL_BIT(17)
-/** Malformed TLP */
-#define AL_PCIE_AER_UNCORR_MLFRM_TLP			AL_BIT(18)
-/** ECRC Error */
-#define AL_PCIE_AER_UNCORR_ECRC_ERR			AL_BIT(19)
-/** Unsupported Request Error */
-#define AL_PCIE_AER_UNCORR_UNSUPRT_REQ_ERR		AL_BIT(20)
-/** Uncorrectable Internal Error */
-#define AL_PCIE_AER_UNCORR_INT_ERR			AL_BIT(22)
-/** AtomicOp Egress Blocked */
-#define AL_PCIE_AER_UNCORR_ATOMIC_EGRESS_BLK		AL_BIT(24)
-
-/*******************************************************************************
- * PCIe AER correctable error bits
- * To be used with the following functions:
- * - al_pcie_aer_config
- * - al_pcie_aer_corr_get_and_clear
- ******************************************************************************/
-/** Receiver Error */
-#define AL_PCIE_AER_CORR_RCV_ERR			AL_BIT(0)
-/** Bad TLP */
-#define AL_PCIE_AER_CORR_BAD_TLP			AL_BIT(6)
-/** Bad DLLP */
-#define AL_PCIE_AER_CORR_BAD_DLLP			AL_BIT(7)
-/** REPLAY_NUM Rollover */
-#define AL_PCIE_AER_CORR_RPLY_NUM_ROLL_OVR		AL_BIT(8)
-/** Replay Timer Timeout */
-#define AL_PCIE_AER_CORR_RPLY_TMR_TO			AL_BIT(12)
-/** Advisory Non-Fatal Error */
-#define AL_PCIE_AER_CORR_ADVISORY_NON_FTL_ERR		AL_BIT(13)
-/** Corrected Internal Error */
-#define AL_PCIE_AER_CORR_INT_ERR			AL_BIT(14)
-
-/** The AER erroneous TLP header length [num DWORDs] */
-#define AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS		4
-
-/******************************************************************************/
-/************************* Data Structures and Types **************************/
-/******************************************************************************/
-
-/**
- * al_pcie_ib_hcrd_config: data structure internally used in order to config
- * inbound posted/non-posted parameters.
- * Note: it's required to have this structure in pcie_port handle since it has
- *	 a state (required/not-required) which is determined by outbound
- *	 outstanding configuration
- */
-struct al_pcie_ib_hcrd_config {
-	/* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */
-	unsigned int	nof_np_hdr;
-
-	/* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */
-	unsigned int	nof_p_hdr;
-};
-
-/* The Max Payload Size. Measured in bytes.
- *   DEFAULT: do not change the current MPS
- */
-enum al_pcie_max_payload_size {
-	AL_PCIE_MPS_DEFAULT,
-	AL_PCIE_MPS_128		= 0,
-	AL_PCIE_MPS_256		= 1,
-	AL_PCIE_MPS_512		= 2,
-	AL_PCIE_MPS_1024	= 3,
-	AL_PCIE_MPS_2048	= 4,
-	AL_PCIE_MPS_4096	= 5,
-};
-
-/**
- * al_pcie_port: data structure used by the HAL to handle a specific pcie port.
- * this structure is allocated and set to zeros by the upper layer, then it is
- * initialized by the al_pcie_port_handle_init() that should be called before any
- * other function of this API. later, this handle passed to the API functions.
- */
-struct al_pcie_port {
-	void __iomem		*pcie_reg_base;
-	struct al_pcie_regs 	regs_ptrs;
-	struct al_pcie_regs	*regs;
-	uint32_t		*ex_regs_ptrs[AL_PCIE_EX_REGS_NUM];
-	void			*ex_regs;
-	void __iomem		*pbs_regs;
-
-	/* Revision ID */
-	uint8_t		rev_id;
-	unsigned int	port_id;
-	uint8_t		max_lanes;
-	uint8_t		max_num_of_pfs;
-
-	/* Internally used */
-	struct al_pcie_ib_hcrd_config ib_hcrd_config;
-};
-
-/**
- * al_pcie_pf: the pf handle, a data structure used to handle PF specific
- * functionality. Initialized using "al_pcie_pf_handle_init()"
- */
-struct al_pcie_pf {
-	unsigned int		pf_num;
-	struct al_pcie_port	*pcie_port;
-};
-
-/** Operating mode (endpoint, root complex) */
-enum al_pcie_operating_mode {
-	AL_PCIE_OPERATING_MODE_EP,
-	AL_PCIE_OPERATING_MODE_RC,
-	AL_PCIE_OPERATING_MODE_UNKNOWN
-};
-
-/* The maximum link speed, measured GT/s (Giga transfer / second)
- *   DEFAULT: do not change the current speed
- *   GEN1: 2.5 GT/s
- *   GEN2: 5 GT/s
- *   GEN3: 8GT/s
- *
- *   Note: The values of this enumerator are important for proper behavior
- */
-enum al_pcie_link_speed {
-	AL_PCIE_LINK_SPEED_DEFAULT,
-	AL_PCIE_LINK_SPEED_GEN1 = 1,
-	AL_PCIE_LINK_SPEED_GEN2 = 2,
-	AL_PCIE_LINK_SPEED_GEN3 = 3
-};
-
-/** PCIe capabilities that supported by a specific port */
-struct al_pcie_max_capability {
-	al_bool		end_point_mode_supported;
-	al_bool		root_complex_mode_supported;
-	enum al_pcie_link_speed	max_speed;
-	uint8_t		max_lanes;
-	al_bool		reversal_supported;
-	uint8_t		atu_regions_num;
-	uint32_t	atu_min_size;
-};
-
-/** PCIe link related parameters */
-struct al_pcie_link_params {
-	enum al_pcie_link_speed	max_speed;
-	al_bool			enable_reversal;
-	enum al_pcie_max_payload_size	max_payload_size;
-
-};
-
-/** PCIe gen2 link parameters */
-struct al_pcie_gen2_params {
-	al_bool	tx_swing_low; /* set tx swing low when true, and tx swing full when false */
-	al_bool	tx_compliance_receive_enable;
-	al_bool	set_deemphasis;
-};
-
-/** PCIe gen 3 standard per lane equalization parameters */
-struct al_pcie_gen3_lane_eq_params {
-	uint8_t		downstream_port_transmitter_preset;
-	uint8_t		downstream_port_receiver_preset_hint;
-	uint8_t		upstream_port_transmitter_preset;
-	uint8_t		upstream_port_receiver_preset_hint;
-};
-
-/** PCIe gen 3 equalization parameters */
-struct al_pcie_gen3_params {
-	al_bool	perform_eq;
-	al_bool	interrupt_enable_on_link_eq_request;
-	struct al_pcie_gen3_lane_eq_params *eq_params; /* array of lanes params */
-	int	eq_params_elements; /* number of elements in the eq_params array */
-
-	al_bool	eq_disable; /* disables the equalization feature */
-	al_bool eq_phase2_3_disable; /* Equalization Phase 2 and Phase 3 */
-				     /* Disable (RC mode only) */
-	uint8_t local_lf; /* Full Swing (FS) Value for Gen3 Transmit Equalization */
-			  /* Value Range: 12 through 63 (decimal).*/
-
-	uint8_t	local_fs; /* Low Frequency (LF) Value for Gen3 Transmit Equalization */
-};
-
-/** Transport Layer credits parameters */
-struct al_pcie_tl_credits_params {
-};
-
-/** Various configuration features */
-struct al_pcie_features {
-	/**
-	 * Enable MSI fix from the SATA to the PCIe EP
-	 * Only valid for port 0, when enabled as EP
-	 */
-	al_bool sata_ep_msi_fix;
-};
-
-/**
- * Inbound posted/non-posted header credits and outstanding outbound reads
- * completion header configuration
- *
- * Constraints:
- * - nof_cpl_hdr + nof_np_hdr + nof_p_hdr ==
- *			AL_PCIE_REV_1_2_IB_HCRD_SUM/AL_PCIE_REV3_IB_HCRD_SUM
- * - nof_cpl_hdr > 0
- * - nof_p_hdr > 0
- * - nof_np_hdr > 0
- */
-struct al_pcie_ib_hcrd_os_ob_reads_config {
-	/** Max number of outstanding outbound reads */
-	uint8_t nof_outstanding_ob_reads;
-
-	/**
-	 * This value set the possible outstanding headers CMPLs , the core
-	 * can get (the core always advertise infinite credits for CMPLs).
-	 */
-	unsigned int nof_cpl_hdr;
-
-	/**
-	 * This value set the possible outstanding headers reads (non-posted
-	 * transactions), the core can get  (it set the value in the init FC
-	 * process).
-	 */
-	unsigned int nof_np_hdr;
-
-	/**
-	 * This value set the possible outstanding headers writes (posted
-	 * transactions), the core can get  (it set the value in the init FC
-	 * process).
-	 */
-	unsigned int nof_p_hdr;
-};
-
-/** PCIe Ack/Nak Latency and Replay timers */
-struct al_pcie_latency_replay_timers {
-	uint16_t	round_trip_lat_limit;
-	uint16_t	replay_timer_limit;
-};
-
-/* SRIS KP counter values */
-struct al_pcie_sris_params {
-	/** set to AL_TRUE to use defaults and ignore the other parameters */
-	al_bool		use_defaults;
-	uint16_t	kp_counter_gen3;	/* only for Gen3 */
-	uint16_t	kp_counter_gen21;
-};
-
-/** Relaxed ordering params */
-struct al_pcie_relaxed_ordering_params {
-	al_bool		enable_tx_relaxed_ordering;
-	al_bool		enable_rx_relaxed_ordering;
-};
-
-/** PCIe port configuration parameters
- * This structure includes the parameters that the HAL should apply to the port
- * (by al_pcie_port_config()).
- * The fields that are pointers (e.g. link_params) can be set to NULL, in that
- * case, the al_pcie_port_config() will keep the current HW settings.
- */
-struct al_pcie_port_config_params {
-	struct al_pcie_link_params		*link_params;
-	al_bool					enable_axi_snoop;
-	al_bool					enable_ram_parity_int;
-	al_bool					enable_axi_parity_int;
-	struct al_pcie_latency_replay_timers	*lat_rply_timers;
-	struct al_pcie_gen2_params		*gen2_params;
-	struct al_pcie_gen3_params		*gen3_params;
-	struct al_pcie_tl_credits_params	*tl_credits;
-	struct al_pcie_features			*features;
-	/* Sets all internal timers to Fast Mode for speeding up simulation.*/
-	al_bool					fast_link_mode;
-	/*
-	 * when true, the PCI unit will return Slave Error/Decoding Error to the master unit in case
-	 * of error. when false, the value 0xFFFFFFFF will be returned without error indication.
-	 */
-	al_bool					enable_axi_slave_err_resp;
-	struct al_pcie_sris_params		*sris_params;
-	struct al_pcie_relaxed_ordering_params	*relaxed_ordering_params;
-};
-
-/** BAR register configuration parameters (Endpoint Mode only) */
-struct al_pcie_ep_bar_params {
-	al_bool		enable;
-	al_bool		memory_space; /**< memory or io */
-	al_bool		memory_64_bit; /**< is memory space is 64 bit */
-	al_bool		memory_is_prefetchable;
-	uint64_t	size; /* the bar size in bytes */
-};
-
-/** PF config params (EP mode only) */
-struct al_pcie_pf_config_params {
-	al_bool				cap_d1_d3hot_dis;
-	al_bool				cap_flr_dis;
-	al_bool				cap_aspm_dis;
-	al_bool				bar_params_valid;
-	struct al_pcie_ep_bar_params	bar_params[6];
-	struct al_pcie_ep_bar_params	exp_bar_params;/* expansion ROM BAR*/
-};
-
-/** PCIe link status */
-struct al_pcie_link_status {
-	al_bool			link_up;
-	enum al_pcie_link_speed	speed;
-	uint8_t			lanes;
-	uint8_t			ltssm_state;
-};
-
-/** PCIe lane status */
-struct al_pcie_lane_status {
-	al_bool			is_reset;
-	enum al_pcie_link_speed	requested_speed;
-};
-
-/** PCIe MSIX capability configuration parameters */
-struct al_pcie_msix_params {
-	uint16_t	table_size;
-	uint16_t	table_offset;
-	uint8_t		table_bar;
-	uint16_t	pba_offset;
-	uint16_t	pba_bar;
-};
-
-/** PCIE AER capability parameters */
-struct al_pcie_aer_params {
-	/** ECRC Generation Enable */
-	al_bool		ecrc_gen_en;
-	/** ECRC Check Enable */
-	al_bool		ecrc_chk_en;
-
-	/**
-	 * Enabled reporting of correctable errors (bit mask)
-	 * See 'AL_PCIE_AER_CORR_*' for details
-	 * 0 - no reporting at all
-	 */
-	unsigned int	enabled_corr_err;
-	/**
-	 * Enabled reporting of non-fatal uncorrectable errors (bit mask)
-	 * See 'AL_PCIE_AER_UNCORR_*' for details
-	 * 0 - no reporting at all
-	 */
-	unsigned int	enabled_uncorr_non_fatal_err;
-	/**
-	 * Enabled reporting of fatal uncorrectable errors (bit mask)
-	 * See 'AL_PCIE_AER_UNCORR_*' for details
-	 * 0 - no reporting at all
-	 */
-	unsigned int	enabled_uncorr_fatal_err;
-};
-
-/******************************************************************************/
-/********************************** PCIe API **********************************/
-/******************************************************************************/
-
-/*************************** PCIe Initialization API **************************/
-
-/**
- * Initializes a PCIe port handle structure.
- *
- * @param   pcie_port		an allocated, non-initialized instance.
- * @param   pcie_reg_base	the virtual base address of the port internal
- *				registers
- * @param   pbs_reg_base	the virtual base address of the pbs functional
- *				registers
- * @param   port_id		the port id (used mainly for debug messages)
- *
- * @return 0 if no error found.
- */
-int al_pcie_port_handle_init(struct al_pcie_port *pcie_port,
-			 void __iomem *pcie_reg_base,
-			 void __iomem *pbs_reg_base,
-			 unsigned int port_id);
-
-/**
- * Initializes a PCIe pf handle structure
- * @param  pcie_pf   an allocated, non-initialized instance of pf handle
- * @param  pcie_port pcie port handle
- * @param  pf_num    physical function number
- * @return           0 if no error found
- */
-int al_pcie_pf_handle_init(
-	struct al_pcie_pf *pcie_pf,
-	struct al_pcie_port *pcie_port,
-	unsigned int pf_num);
-
-/************************** Pre PCIe Port Enable API **************************/
-
-/**
- * @brief set current pcie operating mode (root complex or endpoint)
- * This function can be called only before enabling the controller using
- * al_pcie_port_enable().
- *
- * @param pcie_port pcie port handle
- * @param mode pcie operating mode
- *
- * @return 0 if no error found.
- */
-int al_pcie_port_operating_mode_config(struct al_pcie_port *pcie_port,
-				  enum al_pcie_operating_mode mode);
-
-/**
- * Configure number of lanes connected to this port.
- * This function can be called only before enabling the controller using al_pcie_port_enable().
- *
- * @param pcie_port pcie port handle
- * @param lanes number of lanes
- * Note: this function must be called before any al_pcie_port_config() calls
- *
- * @return 0 if no error found.
- */
-int al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes);
-
-/**
- * Set maximum physical function numbers
- * @param pcie_port      pcie port handle
- * @param max_num_of_pfs number of physical functions
- * Note: this function must be called before any al_pcie_pf_config() calls
- */
-int al_pcie_port_max_num_of_pfs_set(
-	struct al_pcie_port *pcie_port,
-	uint8_t max_num_of_pfs);
-
-/**
- * @brief Inbound posted/non-posted header credits and outstanding outbound
- *        reads completion header configuration
- *
- * @param	pcie_port pcie port handle
- * @param	ib_hcrd_os_ob_reads_config
- * 		Inbound header credits and outstanding outbound reads
- * 		configuration
- */
-int al_pcie_port_ib_hcrd_os_ob_reads_config(
-	struct al_pcie_port *pcie_port,
-	struct al_pcie_ib_hcrd_os_ob_reads_config *ib_hcrd_os_ob_reads_config);
-
-/** return PCIe operating mode
- * @param pcie_port	pcie port handle
- * @return		operating mode
- */
-enum al_pcie_operating_mode al_pcie_operating_mode_get(
-	struct al_pcie_port *pcie_port);
-
-/**************************** PCIe Port Enable API ****************************/
-
-/** Enable PCIe unit (deassert reset)
- *
- * @param   pcie_port pcie port handle
- *
- * @return 0 if no error found.
- */
-int al_pcie_port_enable(struct al_pcie_port *pcie_port);
-
-/** Disable PCIe unit (assert reset)
- *
- * @param   pcie_port pcie port handle
- */
-void al_pcie_port_disable(struct al_pcie_port *pcie_port);
-
-/**
- * Port memory shutdown/up
- * Caution: This function can be called only when the controller is disabled
- *
- * @param pcie_port pcie port handle
- * @param enable memory shutdown enable or disable
- *
- */
-int al_pcie_port_memory_shutdown_set(
-	struct al_pcie_port	*pcie_port,
-	al_bool			enable);
-
-/**
- * Check if port enabled or not
- * @param  pcie_port pcie port handle
- * @return           AL_TRUE of port enabled and AL_FALSE otherwise
- */
-al_bool al_pcie_port_is_enabled(struct al_pcie_port *pcie_port);
-
-/*************************** PCIe Configuration API ***************************/
-
-/**
- * @brief   configure pcie port (mode, link params, etc..)
- * this function must be called before initializing the link
- *
- * @param pcie_port pcie port handle
- * @param params configuration structure.
- *
- * @return  0 if no error found
- */
-int al_pcie_port_config(struct al_pcie_port *pcie_port,
-			const struct al_pcie_port_config_params *params);
-
-/**
- * @brief Configure a specific PF (EP params, sriov params, ...)
- * this function must be called before any datapath transactions
- *
- * @param pcie_pf	pcie pf handle
- * @param params	configuration structure.
- *
- * @return		0 if no error found
- */
-int al_pcie_pf_config(
-	struct al_pcie_pf *pcie_pf,
-	const struct al_pcie_pf_config_params *params);
-
-/************************** PCIe Link Operations API **************************/
-
-/**
- * @brief   start pcie link
- *
- * @param   pcie_port pcie port handle
- *
- * @return  0 if no error found
- */
-int al_pcie_link_start(struct al_pcie_port *pcie_port);
-
-/**
- * @brief   stop pcie link
- *
- * @param   pcie_port pcie port handle
- *
- * @return  0 if no error found
- */
-int al_pcie_link_stop(struct al_pcie_port *pcie_port);
-
-/**
- * @brief   trigger link-disable
- *
- * @param   pcie_port pcie port handle
- * @param   disable   AL_TRUE to disable the link and AL_FALSE to enable it
- *
- * Note: this functionality differs from "al_pcie_link_stop" as it's a spec
- *       functionality where both sides of the PCIe agrees to disable the link
- * @return  0 if no error found
- */
-int al_pcie_link_disable(struct al_pcie_port *pcie_port, al_bool disable);
-
-/**
- * @brief   wait for link up indication
- * this function waits for link up indication, it polls LTSSM state until link is ready
- *
- * @param   pcie_port pcie port handle
- * @param   timeout_ms maximum timeout in milli-seconds to wait for link up
- *
- * @return  0 if link up indication detected
- * 	    -ETIME if not.
- */
-int al_pcie_link_up_wait(struct al_pcie_port *pcie_port, uint32_t timeout_ms);
-
-/**
- * @brief   get link status
- *
- * @param   pcie_port pcie port handle
- * @param   status structure for link status
- *
- * @return  0 if no error found
- */
-int al_pcie_link_status(struct al_pcie_port *pcie_port, struct al_pcie_link_status *status);
-
-/**
- * @brief   get lane status
- *
- * @param	pcie_port
- *		pcie port handle
- * @param	lane
- *		PCIe lane
- * @param	status
- *		Pointer to returned structure for lane status
- *
- */
-void al_pcie_lane_status_get(
-	struct al_pcie_port		*pcie_port,
-	unsigned int			lane,
-	struct al_pcie_lane_status	*status);
-
-/**
- * @brief   trigger hot reset
- *
- * @param   pcie_port pcie port handle
- * @param   enable   AL_TRUE to enable hot-reset and AL_FALSE to disable it
- *
- * @return  0 if no error found
- */
-int al_pcie_link_hot_reset(struct al_pcie_port *pcie_port, al_bool enable);
-
-/**
- * @brief   trigger link-retain
- * this function initiates Link retraining by directing the Physical Layer LTSSM
- * to the Recovery state. If the LTSSM is already in Recovery or Configuration,
- * re-entering Recovery is permitted but not required.
-
- * @param   pcie_port pcie port handle
- *
- * Note: there's no need to disable initiating link-retrain
- * @return  0 if no error found
- */
-int al_pcie_link_retrain(struct al_pcie_port *pcie_port);
-
-/**
- * @brief   change port speed
- * this function changes the port speed, it doesn't wait for link re-establishment
- *
- * @param   pcie_port pcie port handle
- * @param   new_speed the new speed gen to set
- *
- * @return  0 if no error found
- */
-int al_pcie_link_change_speed(struct al_pcie_port *pcie_port, enum al_pcie_link_speed new_speed);
-
-/* TODO: check if this function needed */
-int al_pcie_link_change_width(struct al_pcie_port *pcie_port, uint8_t width);
-
-/**************************** Post Link Start API *****************************/
-
-/************************** Snoop Configuration API ***************************/
-
-/**
- * @brief   configure pcie port axi snoop
- *
- * @param pcie_port pcie port handle
- * @param enable_axi_snoop enable snoop.
- *
- * @return  0 if no error found
- */
-/* TODO: Can this API be called after port enable? */
-int al_pcie_port_snoop_config(struct al_pcie_port *pcie_port,
-				al_bool enable_axi_snoop);
-
-/************************** Configuration Space API ***************************/
-
-/**
- * Configuration Space Access Through PCI-E_ECAM_Ext PASW (RC mode only)
- */
-
-/**
- * @brief   get base address of pci configuration space header
- * @param   pcie_pf	pcie pf handle
- * @param   addr	pointer for returned address;
- * @return              0 if no error found
- */
-int al_pcie_config_space_get(
-	struct al_pcie_pf *pcie_pf,
-	uint8_t __iomem **addr);
-
-/**
- * Read data from the local configuration space
- *
- * @param	pcie_pf	pcie	pf handle
- * @param	reg_offset	Configuration space register offset
- * @return	Read data
- */
-uint32_t al_pcie_local_cfg_space_read(
-	struct al_pcie_pf	*pcie_pf,
-	unsigned int		reg_offset);
-
-/**
- * Write data to the local configuration space
- *
- * @param	pcie_pf		PCIe pf handle
- * @param	reg_offset	Configuration space register offset
- * @param	data		Data to write
- * @param	cs2		Should be AL_TRUE if dbi_cs2 must be asserted
- *				to enable writing to this register, according to
- *				the PCIe Core specifications
- * @param	allow_ro_wr	AL_TRUE to allow writing into read-only regs
- *
- */
-void al_pcie_local_cfg_space_write(
-	struct al_pcie_pf	*pcie_pf,
-	unsigned int		reg_offset,
-	uint32_t		data,
-	al_bool			cs2,
-	al_bool			allow_ro_wr);
-
-/**
- * @brief   set target_bus and mask_target_bus
- * @param   pcie_port pcie port handle
- * @param   target_bus
- * @param   mask_target_bus
- * @return  0 if no error found
- */
-int al_pcie_target_bus_set(struct al_pcie_port *pcie_port,
-			   uint8_t target_bus,
-			   uint8_t mask_target_bus);
-
-/**
- * @brief   get target_bus and mask_target_bus
- * @param   pcie_port pcie port handle
- * @param   target_bus
- * @param   mask_target_bus
- * @return  0 if no error found
- */
-int al_pcie_target_bus_get(struct al_pcie_port *pcie_port,
-			   uint8_t *target_bus,
-			   uint8_t *mask_target_bus);
-
-/**
- * Set secondary bus number
- *
- * @param pcie_port pcie port handle
- * @param secbus pci secondary bus number
- *
- * @return 0 if no error found.
- */
-int al_pcie_secondary_bus_set(struct al_pcie_port *pcie_port, uint8_t secbus);
-
-/**
- * Set subordinary bus number
- *
- * @param   pcie_port pcie port handle
- * @param   subbus the highest bus number of all of the buses that can be reached
- *		downstream of the PCIE instance.
- *
- * @return 0 if no error found.
- */
-int al_pcie_subordinary_bus_set(struct al_pcie_port *pcie_port,uint8_t subbus);
-
-/**
- * @brief Enable/disable deferring incoming configuration requests until
- * initialization is complete. When enabled, the core completes incoming
- * configuration requests with a Configuration Request Retry Status.
- * Other incoming Requests complete with Unsupported Request status.
- *
- * @param pcie_port pcie port handle
- * @param en enable/disable
- */
-void al_pcie_app_req_retry_set(struct al_pcie_port *pcie_port, al_bool en);
-
-/*************** Internal Address Translation Unit (ATU) API ******************/
-
-enum al_pcie_atu_dir {
-	AL_PCIE_ATU_DIR_OUTBOUND = 0,
-	AL_PCIE_ATU_DIR_INBOUND = 1,
-};
-
-enum al_pcie_atu_tlp {
-	AL_PCIE_TLP_TYPE_MEM = 0,
-	AL_PCIE_TLP_TYPE_IO = 2,
-	AL_PCIE_TLP_TYPE_CFG0 = 4,
-	AL_PCIE_TLP_TYPE_CFG1 = 5,
-	AL_PCIE_TLP_TYPE_MSG = 0x10,
-	AL_PCIE_TLP_TYPE_RESERVED = 0x1f
-};
-
-enum al_pcie_atu_response {
-	AL_PCIE_RESPONSE_NORMAL = 0,
-	AL_PCIE_RESPONSE_UR = 1,
-	AL_PCIE_RESPONSE_CA = 2
-};
-
-struct al_pcie_atu_region {
-	al_bool			enable;
-	/* outbound or inbound */
-	enum al_pcie_atu_dir	direction;
-	/* region index */
-	uint8_t			index;
-	uint64_t		base_addr;
-	/** limit marks the region's end address. only bits [39:0] are valid
-	 * given the Alpine PoC maximum physical address space
-	 */
-	uint64_t		limit;
-	/** the address that matches will be translated to this address + offset
-	 */
-	uint64_t		target_addr;
-	al_bool			invert_matching;
-	/* pcie tlp type*/
-	enum al_pcie_atu_tlp	tlp_type;
-	/* pcie frame header attr field*/
-	uint8_t			attr;
-	/**
-	 * outbound specific params
-	 */
-	/* pcie message code */
-	uint8_t			msg_code;
-	al_bool			cfg_shift_mode;
-	/**
-	 * inbound specific params
-	 */
-	uint8_t			bar_number;
-	/* BAR match mode, used in EP for MEM and IO tlps*/
-	uint8_t			match_mode;
-	/**
-	 * For outbound: enables taking the function number of the translated
-	 * TLP from the PCIe core. For inbound: enables ATU function match mode
-	 * Note: this boolean is ignored in RC mode
-	 */
-	al_bool			function_match_bypass_mode;
-	/**
-	 * The function number to match/bypass (see previous parameter)
-	 * Note: this parameter is ignored when previous param is FALSE
-	 */
-	uint8_t			function_match_bypass_mode_number;
-	/* response code */
-	enum al_pcie_atu_response response;
-	al_bool			enable_attr_match_mode;
-	al_bool			enable_msg_match_mode;
-	/**
-	 * USE WITH CAUTION: setting this boolean to AL_TRUE allows setting the
-	 * outbound ATU even after link is already started. DO NOT SET this
-	 * boolean to AL_TRUE unless there have been NO traffic before calling
-	 * al_pcie_atu_region_set function
-	 */
-	al_bool			enforce_ob_atu_region_set;
-};
-
-/**
- * @brief   program internal ATU region entry
- * @param   pcie_port	pcie port handle
- * @param   atu_region	data structure that contains the region index and the
- *          translation parameters
- * @return  0 if no error
- */
-int al_pcie_atu_region_set(
-	struct al_pcie_port *pcie_port,
-	struct al_pcie_atu_region *atu_region);
-
-/**
- * @brief  get internal ATU is enabled and base/target addresses
- * @param  pcie_port   pcie port handle
- * @param  direction   input: iATU direction (IB/OB)
- * @param  index       input: iATU index
- * @param  enable      output: AL_TRUE if the iATU is enabled
- * @param  base_addr   output: the iATU base address
- * @param  target_addr output: the iATU target address
- */
-void al_pcie_atu_region_get_fields(
-	struct al_pcie_port *pcie_port,
-	enum al_pcie_atu_dir direction, uint8_t index,
-	al_bool *enable, uint64_t *base_addr, uint64_t *target_addr);
-
-/**
- * @brief   Configure axi io bar.
- *          every hit to this bar will override size to 4 bytes.
- * @param   pcie_port pcie port handle
- * @param   start the first address of the memory
- * @param   end the last address of the memory
- * @return
- */
-void al_pcie_axi_io_config(
-	struct al_pcie_port *pcie_port,
-	al_phys_addr_t start,
-	al_phys_addr_t end);
-
-/************** Interrupt generation (Endpoint mode Only) API *****************/
-
-enum al_pcie_legacy_int_type{
-	AL_PCIE_LEGACY_INTA = 0,
-	AL_PCIE_LEGACY_INTB,
-	AL_PCIE_LEGACY_INTC,
-	AL_PCIE_LEGACY_INTD
-};
-
-/**
- * @brief		generate INTx Assert/DeAssert Message
- * @param  pcie_pf	pcie pf handle
- * @param  assert	when true, Assert Message is sent
- * @param  type		type of message (INTA, INTB, etc)
- * @return		0 if no error found
- */
-int al_pcie_legacy_int_gen(
-	struct al_pcie_pf		*pcie_pf,
-	al_bool				assert,
-	enum al_pcie_legacy_int_type	type);
-
-/**
- * @brief		generate MSI interrupt
- * @param  pcie_pf	pcie pf handle
- * @param  vector	the vector index to send interrupt for.
- * @return		0 if no error found
- */
-int al_pcie_msi_int_gen(struct al_pcie_pf *pcie_pf, uint8_t vector);
-
-/**
- * @brief   configure MSIX capability
- * @param   pcie_pf	pcie pf handle
- * @param   msix_params	MSIX capability configuration parameters
- * @return  0 if no error found
- */
-int al_pcie_msix_config(
-		struct al_pcie_pf		*pcie_pf,
-		struct al_pcie_msix_params	*msix_params);
-
-/**
- * @brief   check whether MSIX capability is enabled
- * @param   pcie_pf	pcie pf handle
- * @return  AL_TRUE if MSIX capability is enabled, AL_FALSE otherwise
- */
-al_bool al_pcie_msix_enabled(struct al_pcie_pf	*pcie_pf);
-
-/**
- * @brief   check whether MSIX capability is masked
- * @param   pcie_pf	pcie pf handle
- * @return  AL_TRUE if MSIX capability is masked, AL_FALSE otherwise
- */
-al_bool al_pcie_msix_masked(struct al_pcie_pf *pcie_pf);
-
-/******************** Advanced Error Reporting (AER) API **********************/
-
-/**
- * @brief   configure AER capability
- * @param   pcie_pf	pcie pf handle
- * @param   params	AER capability configuration parameters
- * @return  0 if no error found
- */
-int al_pcie_aer_config(
-	struct al_pcie_pf		*pcie_pf,
-	struct al_pcie_aer_params	*params);
-
-/**
- * @brief   AER uncorretable errors get and clear
- * @param   pcie_pf	pcie pf handle
- * @return  bit mask of uncorrectable errors - see 'AL_PCIE_AER_UNCORR_*' for
- *          details
- */
-unsigned int al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf	*pcie_pf);
-
-/**
- * @brief   AER corretable errors get and clear
- * @param   pcie_pf	pcie pf handle
- * @return  bit mask of correctable errors - see 'AL_PCIE_AER_CORR_*' for
- *          details
- */
-unsigned int al_pcie_aer_corr_get_and_clear(struct al_pcie_pf	*pcie_pf);
-
-/**
- * @brief   AER get the header for the TLP corresponding to a detected error
- * @param   pcie_pf	pcie pf handle
- * @param   hdr		pointer to an array for getting the header
- */
-void al_pcie_aer_err_tlp_hdr_get(
-	struct al_pcie_pf	*pcie_pf,
-	uint32_t		hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS]);
-
-/******************** Loop-Back mode (RC and Endpoint modes) ******************/
-
-/**
- * @brief   enter local pipe loop-back mode
- *  This mode will connect the pipe RX signals to TX.
- *  no need to start link when using this mode.
- *  Gen3 equalization must be disabled before enabling this mode
- *  The caller must make sure the port is ready to accept the TLPs it sends to
- *  itself. for example, BARs should be initialized before sending memory TLPs.
- *
- * @param   pcie_port pcie port handle
- * @return  0 if no error found
- */
-int al_pcie_local_pipe_loopback_enter(struct al_pcie_port *pcie_port);
-
-/**
- * @brief   exit local pipe loopback mode
- *
- * @param   pcie_port pcie port handle
- * @return  0 if no error found
- */
-int al_pcie_local_pipe_loopback_exit(struct al_pcie_port *pcie_port);
-
-/**
- * @brief   enter master remote loopback mode
- *  No need to configure the link partner to enter slave remote loopback mode
- *  as this should be done as response to special training sequence directives
- *  when master works in remote loopback mode.
- *  The caller must make sure the port is ready to accept the TLPs it sends to
- *  itself. for example, BARs should be initialized before sending memory TLPs.
- *
- * @param   pcie_port pcie port handle
- * @return  0 if no error found
- */
-int al_pcie_remote_loopback_enter(struct al_pcie_port *pcie_port);
-
-/**
- * @brief   exit remote loopback mode
- *
- * @param   pcie_port pcie port handle
- * @return  0 if no error found
- */
-int al_pcie_remote_loopback_exit(struct al_pcie_port *pcie_port);
-
-#endif
-/** @} end of grouppcie group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_pcie_axi_reg.h b/sys/contrib/alpine-hal/eth/al_hal_pcie_axi_reg.h
deleted file mode 100644
index 04d4bfdbca3f..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_pcie_axi_reg.h
+++ /dev/null
@@ -1,1501 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-
-#ifndef __AL_PCIE_HAL_AXI_REG_H__
-#define __AL_PCIE_HAL_AXI_REG_H__
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-
-
-struct al_pcie_rev1_2_axi_ctrl {
-	/* [0x0]  */
-	uint32_t global;
-	uint32_t rsrvd_0;
-	/* [0x8]  */
-	uint32_t master_bctl;
-	/* [0xc]  */
-	uint32_t master_rctl;
-	/* [0x10]  */
-	uint32_t master_ctl;
-	/* [0x14]  */
-	uint32_t master_arctl;
-	/* [0x18]  */
-	uint32_t master_awctl;
-	/* [0x1c]  */
-	uint32_t slave_rctl;
-	/* [0x20]  */
-	uint32_t slv_wctl;
-	/* [0x24]  */
-	uint32_t slv_ctl;
-	/* [0x28]  */
-	uint32_t dbi_ctl;
-	/* [0x2c]  */
-	uint32_t vmid_mask;
-	uint32_t rsrvd[4];
-};
-struct al_pcie_rev3_axi_ctrl {
-	/* [0x0]  */
-	uint32_t global;
-	uint32_t rsrvd_0;
-	/* [0x8]  */
-	uint32_t master_bctl;
-	/* [0xc]  */
-	uint32_t master_rctl;
-	/* [0x10]  */
-	uint32_t master_ctl;
-	/* [0x14]  */
-	uint32_t master_arctl;
-	/* [0x18]  */
-	uint32_t master_awctl;
-	/* [0x1c]  */
-	uint32_t slave_rctl;
-	/* [0x20]  */
-	uint32_t slv_wctl;
-	/* [0x24]  */
-	uint32_t slv_ctl;
-	/* [0x28]  */
-	uint32_t dbi_ctl;
-	/* [0x2c]  */
-	uint32_t vmid_mask;
-};
-struct al_pcie_rev1_axi_ob_ctrl {
-	/* [0x0]  */
-	uint32_t cfg_target_bus;
-	/* [0x4]  */
-	uint32_t cfg_control;
-	/* [0x8]  */
-	uint32_t io_start_l;
-	/* [0xc]  */
-	uint32_t io_start_h;
-	/* [0x10]  */
-	uint32_t io_limit_l;
-	/* [0x14]  */
-	uint32_t io_limit_h;
-	/* [0x18]  */
-	uint32_t msg_start_l;
-	/* [0x1c]  */
-	uint32_t msg_start_h;
-	/* [0x20]  */
-	uint32_t msg_limit_l;
-	/* [0x24]  */
-	uint32_t msg_limit_h;
-	uint32_t rsrvd[6];
-};
-struct al_pcie_rev2_axi_ob_ctrl {
-	/* [0x0]  */
-	uint32_t cfg_target_bus;
-	/* [0x4]  */
-	uint32_t cfg_control;
-	/* [0x8]  */
-	uint32_t io_start_l;
-	/* [0xc]  */
-	uint32_t io_start_h;
-	/* [0x10]  */
-	uint32_t io_limit_l;
-	/* [0x14]  */
-	uint32_t io_limit_h;
-	/* [0x18]  */
-	uint32_t msg_start_l;
-	/* [0x1c]  */
-	uint32_t msg_start_h;
-	/* [0x20]  */
-	uint32_t msg_limit_l;
-	/* [0x24]  */
-	uint32_t msg_limit_h;
-	/*
-	 * [0x28] this register override the VMID field in the AXUSER [19:4],
-	 * for the AXI master port.
-	 */
-	uint32_t vmid_reg_ovrd;
-	/* [0x2c] this register override the ADDR[63:32] AXI master port. */
-	uint32_t addr_high_reg_ovrd_value;
-	/* [0x30] this register override the ADDR[63:32] AXI master port. */
-	uint32_t addr_high_reg_ovrd_sel;
-	/*
-	 * [0x34] Define the size to replace in the master axi address bits
-	 * [63:32]
-	 */
-	uint32_t addr_size_replace;
-	uint32_t rsrvd[2];
-};
-struct al_pcie_rev3_axi_ob_ctrl {
-	/* [0x0]  */
-	uint32_t cfg_target_bus;
-	/* [0x4]  */
-	uint32_t cfg_control;
-	/* [0x8]  */
-	uint32_t io_start_l;
-	/* [0xc]  */
-	uint32_t io_start_h;
-	/* [0x10]  */
-	uint32_t io_limit_l;
-	/* [0x14]  */
-	uint32_t io_limit_h;
-	/* [0x18]  */
-	uint32_t aw_msg_start_l;
-	/* [0x1c]  */
-	uint32_t aw_msg_start_h;
-	/* [0x20]  */
-	uint32_t aw_msg_limit_l;
-	/* [0x24]  */
-	uint32_t aw_msg_limit_h;
-	/* [0x28]  */
-	uint32_t ar_msg_start_l;
-	/* [0x2c]  */
-	uint32_t ar_msg_start_h;
-	/* [0x30]  */
-	uint32_t ar_msg_limit_l;
-	/* [0x34]  */
-	uint32_t ar_msg_limit_h;
-	/* [0x38]  */
-	uint32_t io_addr_mask_h;
-	/* [0x3c]  */
-	uint32_t ar_msg_addr_mask_h;
-	/* [0x40]  */
-	uint32_t aw_msg_addr_mask_h;
-	/*
-	 * [0x44] this register override the VMID field in the AXUSER [19:4],
-	 * for the AXI master port.
-	 */
-	uint32_t vmid_reg_ovrd;
-	/* [0x48] this register override the ADDR[63:32] AXI master port. */
-	uint32_t addr_high_reg_ovrd_value;
-	/* [0x4c] this register override the ADDR[63:32] AXI master port. */
-	uint32_t addr_high_reg_ovrd_sel;
-	/*
-	 * [0x50] Define the size to replace in the master axi address bits
-	 * [63:32]
-	 */
-	uint32_t addr_size_replace;
-	uint32_t rsrvd[3];
-};
-struct al_pcie_revx_axi_msg {
-	/* [0x0]  */
-	uint32_t addr_high;
-	/* [0x4]  */
-	uint32_t addr_low;
-	/* [0x8]  */
-	uint32_t type;
-};
-struct al_pcie_revx_axi_pcie_status {
-	/* [0x0]  */
-	uint32_t debug;
-};
-struct al_pcie_revx_axi_rd_parity {
-	/* [0x0]  */
-	uint32_t log_high;
-	/* [0x4]  */
-	uint32_t log_low;
-};
-struct al_pcie_revx_axi_rd_cmpl {
-	/* [0x0]  */
-	uint32_t cmpl_log_high;
-	/* [0x4]  */
-	uint32_t cmpl_log_low;
-};
-struct al_pcie_revx_axi_rd_to {
-	/* [0x0]  */
-	uint32_t to_log_high;
-	/* [0x4]  */
-	uint32_t to_log_low;
-};
-struct al_pcie_revx_axi_wr_cmpl {
-	/* [0x0]  */
-	uint32_t wr_cmpl_log_high;
-	/* [0x4]  */
-	uint32_t wr_cmpl_log_low;
-};
-struct al_pcie_revx_axi_wr_to {
-	/* [0x0]  */
-	uint32_t wr_to_log_high;
-	/* [0x4]  */
-	uint32_t wr_to_log_low;
-};
-struct al_pcie_revx_axi_pcie_global {
-	/* [0x0]  */
-	uint32_t conf;
-};
-struct al_pcie_rev1_2_axi_status {
-	/* [0x0]  */
-	uint32_t lane0;
-	/* [0x4]  */
-	uint32_t lane1;
-	/* [0x8]  */
-	uint32_t lane2;
-	/* [0xc]  */
-	uint32_t lane3;
-};
-struct al_pcie_rev3_axi_status {
-	/* [0x0]  */
-	uint32_t lane0;
-	/* [0x4]  */
-	uint32_t lane1;
-	/* [0x8]  */
-	uint32_t lane2;
-	/* [0xc]  */
-	uint32_t lane3;
-	/* [0x10]  */
-	uint32_t lane4;
-	/* [0x14]  */
-	uint32_t lane5;
-	/* [0x18]  */
-	uint32_t lane6;
-	/* [0x1c]  */
-	uint32_t lane7;
-	uint32_t rsrvd[8];
-};
-struct al_pcie_rev1_2_axi_conf {
-	/* [0x0]  */
-	uint32_t zero_lane0;
-	/* [0x4]  */
-	uint32_t zero_lane1;
-	/* [0x8]  */
-	uint32_t zero_lane2;
-	/* [0xc]  */
-	uint32_t zero_lane3;
-	/* [0x10]  */
-	uint32_t one_lane0;
-	/* [0x14]  */
-	uint32_t one_lane1;
-	/* [0x18]  */
-	uint32_t one_lane2;
-	/* [0x1c]  */
-	uint32_t one_lane3;
-};
-struct al_pcie_rev3_axi_conf {
-	/* [0x0]  */
-	uint32_t zero_lane0;
-	/* [0x4]  */
-	uint32_t zero_lane1;
-	/* [0x8]  */
-	uint32_t zero_lane2;
-	/* [0xc]  */
-	uint32_t zero_lane3;
-	/* [0x10]  */
-	uint32_t zero_lane4;
-	/* [0x14]  */
-	uint32_t zero_lane5;
-	/* [0x18]  */
-	uint32_t zero_lane6;
-	/* [0x1c]  */
-	uint32_t zero_lane7;
-	/* [0x20]  */
-	uint32_t one_lane0;
-	/* [0x24]  */
-	uint32_t one_lane1;
-	/* [0x28]  */
-	uint32_t one_lane2;
-	/* [0x2c]  */
-	uint32_t one_lane3;
-	/* [0x30]  */
-	uint32_t one_lane4;
-	/* [0x34]  */
-	uint32_t one_lane5;
-	/* [0x38]  */
-	uint32_t one_lane6;
-	/* [0x3c]  */
-	uint32_t one_lane7;
-	uint32_t rsrvd[16];
-};
-
-struct al_pcie_revx_axi_msg_attr_axuser_table {
-	/* [0x0] 4 option, the index comes from  */
-	uint32_t entry_vec;
-};
-
-struct al_pcie_revx_axi_parity {
-	/* [0x0]  */
-	uint32_t en_axi;
-	/* [0x4]  */
-	uint32_t status_axi;
-};
-struct al_pcie_revx_axi_pos_logged {
-	/* [0x0]  */
-	uint32_t error_low;
-	/* [0x4]  */
-	uint32_t error_high;
-};
-struct al_pcie_revx_axi_ordering {
-	/* [0x0]  */
-	uint32_t pos_cntl;
-};
-struct al_pcie_revx_axi_link_down {
-	/* [0x0]  */
-	uint32_t reset_extend;
-};
-struct al_pcie_revx_axi_pre_configuration {
-	/* [0x0]  */
-	uint32_t pcie_core_setup;
-};
-struct al_pcie_revx_axi_init_fc {
-	/*
-	 * Revision 1/2:
-	 * [0x0] The sum of all the fields below must be 97
-	 * Revision 3:
-	 * [0x0] The sum of all the fields below must be 259
-	 * */
-	uint32_t cfg;
-};
-struct al_pcie_revx_axi_int_grp_a_axi {
-	/*
-	 * [0x0] Interrupt Cause Register
-	 * Set by hardware.
-	 * - If MSI-X is enabled, and auto_clear control bit =TRUE,
-	 * automatically cleared after MSI-X message associated with this
-	 * specific interrupt bit is sent (MSI-X acknowledge is received).
-	 * - Software can set a bit in this register by writing 1 to the
-	 * associated bit in the Interrupt Cause Set register.
-	 * Write-0 clears a bit. Write-1 has no effect.
-	 * - On CPU Read -- If clear_on_read control bit =TRUE, automatically
-	 * cleared (all bits are cleared).
-	 * When there is a conflict, and on the same clock cycle hardware tries
-	 * to set a bit in the Interrupt Cause register, the specific bit is set
-	 * to ensure the interrupt indication is not lost.
-	 */
-	uint32_t cause;
-	uint32_t rsrvd_0;
-	/*
-	 * [0x8] Interrupt Cause Set Register
-	 * Writing 1 to a bit in this register sets its corresponding cause bit,
-	 * enabling software to generate a hardware interrupt. Write 0 has no
-	 * effect.
-	 */
-	uint32_t cause_set;
-	uint32_t rsrvd_1;
-	/*
-	 * [0x10] Interrupt Mask Register
-	 * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X
-	 * message associate to the associate interrupt bit is sent (AXI write
-	 * acknowledge is received)
-	 */
-	uint32_t mask;
-	uint32_t rsrvd_2;
-	/*
-	 * [0x18] Interrupt Mask Clear Register
-	 * Used when auto-mask control bit=True. It enables the CPU to clear a
-	 * specific bit, preventing a scenario in which the CPU overrides
-	 * another bit with 1 (old value) that hardware has just cleared to 0.
-	 * Writing 0 to this register clears its corresponding mask bit. Write 1
-	 * has no effect.
-	 */
-	uint32_t mask_clear;
-	uint32_t rsrvd_3;
-	/*
-	 * [0x20] Interrupt Status Register
-	 * This register latches the status of the interrupt source.
-	 */
-	uint32_t status;
-	uint32_t rsrvd_4;
-	/* [0x28] Interrupt Control Register */
-	uint32_t control;
-	uint32_t rsrvd_5;
-	/*
-	 * [0x30] Interrupt Mask Register
-	 * Each bit in this register masks the corresponding cause bit for
-	 * generating an Abort signal. Its default value is determined by unit
-	 * instantiation.
-	 * Abort = Wire-OR of Cause & !Interrupt_Abort_Mask).
-	 * This register provides an error handling configuration for error
-	 * interrupts.
-	 */
-	uint32_t abort_mask;
-	uint32_t rsrvd_6;
-	/*
-	 * [0x38] Interrupt Log Register
-	 * Each bit in this register masks the corresponding cause bit for
-	 * capturing the log registers. Its default value is determined by unit
-	 * instantiatio.n
-	 * Log_capture = Wire-OR of Cause & !Interrupt_Log_Mask).
-	 * This register provides an error handling configuration for error
-	 * interrupts.
-	 */
-	uint32_t log_mask;
-	uint32_t rsrvd;
-};
-
-struct al_pcie_rev3_axi_eq_ovrd_tx_rx_values {
-	/* [0x0]  */
-	uint32_t cfg_0;
-	/* [0x4]  */
-	uint32_t cfg_1;
-	/* [0x8]  */
-	uint32_t cfg_2;
-	/* [0xc]  */
-	uint32_t cfg_3;
-	/* [0x10]  */
-	uint32_t cfg_4;
-	/* [0x14]  */
-	uint32_t cfg_5;
-	/* [0x18]  */
-	uint32_t cfg_6;
-	/* [0x1c]  */
-	uint32_t cfg_7;
-	/* [0x20]  */
-	uint32_t cfg_8;
-	/* [0x24]  */
-	uint32_t cfg_9;
-	/* [0x28]  */
-	uint32_t cfg_10;
-	/* [0x2c]  */
-	uint32_t cfg_11;
-	uint32_t rsrvd[12];
-};
-struct al_pcie_rev3_axi_dbg_outstading_trans_axi {
-	/* [0x0]  */
-	uint32_t read_master_counter;
-	/* [0x4]  */
-	uint32_t write_master_counter;
-	/* [0x8]  */
-	uint32_t read_slave_counter;
-};
-struct al_pcie_revx_axi_device_id {
-	/* [0x0] */
-	uint32_t device_rev_id;
-};
-struct al_pcie_revx_axi_power_mang_ovrd_cntl {
-	/* [0x0]  */
-	uint32_t cfg_static_nof_elidle;
-	/* [0x4]  */
-	uint32_t cfg_l0s_wait_ovrd;
-	/* [0x8]  */
-	uint32_t cfg_l12_wait_ovrd;
-	/* [0xc]  */
-	uint32_t cfg_l0s_delay_in_p0s;
-	/* [0x10]  */
-	uint32_t cfg_l12_delay_in_p12;
-	/* [0x14]  */
-	uint32_t cfg_l12_delay_in_p12_clk_rst;
-	/* [0x18]  */
-	uint32_t cfg_delay_powerdown_bus;
-	uint32_t rsrvd;
-};
-struct al_pcie_rev3_axi_dbg_outstading_trans_axi_write {
-	/* [0x0]  */
-	uint32_t slave_counter;
-};
-struct al_pcie_rev3_axi_attr_ovrd {
-	/*
-	 * [0x0] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t write_msg_ctrl_0;
-	/* [0x4] in case of message this register set the below attributes  */
-	uint32_t write_msg_ctrl_1;
-	/*
-	 * [0x8] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t read_msg_ctrl_0;
-	/* [0xc] in case of message this register set the below attributes  */
-	uint32_t read_msg_ctrl_1;
-	/* [0x10] in case of message this register set the below attributes  */
-	uint32_t pf_sel;
-	uint32_t rsrvd[3];
-};
-struct al_pcie_rev3_axi_pf_axi_attr_ovrd {
-	/*
-	 * [0x0] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t func_ctrl_0;
-	/* [0x4] in case of message this register set the below attributes  */
-	uint32_t func_ctrl_1;
-	/*
-	 * [0x8] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t func_ctrl_2;
-	/*
-	 * [0xc] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t func_ctrl_3;
-	/*
-	 * [0x10] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t func_ctrl_4;
-	/*
-	 * [0x14] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t func_ctrl_5;
-	/*
-	 * [0x18] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t func_ctrl_6;
-	/*
-	 * [0x1c] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t func_ctrl_7;
-	/*
-	 * [0x20] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t func_ctrl_8;
-	/*
-	 * [0x24] In case of hit on the io message bar and
-	 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
-	 * register
-	 */
-	uint32_t func_ctrl_9;
-	uint32_t rsrvd[6];
-};
-
-struct al_pcie_revx_axi_regs {
-	uint32_t rsrvd_0[91];
-	struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
-};
-
-struct al_pcie_rev1_axi_regs {
-	struct al_pcie_rev1_2_axi_ctrl ctrl;     /* [0x0] */
-	struct al_pcie_rev1_axi_ob_ctrl ob_ctrl; /* [0x40] */
-	uint32_t rsrvd_0[4];
-	struct al_pcie_revx_axi_msg msg;                     /* [0x90] */
-	struct al_pcie_revx_axi_pcie_status pcie_status;     /* [0x9c] */
-	struct al_pcie_revx_axi_rd_parity rd_parity;         /* [0xa0] */
-	struct al_pcie_revx_axi_rd_cmpl rd_cmpl;             /* [0xa8] */
-	struct al_pcie_revx_axi_rd_to rd_to;                 /* [0xb0] */
-	struct al_pcie_revx_axi_wr_cmpl wr_cmpl;             /* [0xb8] */
-	struct al_pcie_revx_axi_wr_to wr_to;                 /* [0xc0] */
-	struct al_pcie_revx_axi_pcie_global pcie_global;     /* [0xc8] */
-	struct al_pcie_rev1_2_axi_status status;               /* [0xcc] */
-	struct al_pcie_rev1_2_axi_conf conf;                   /* [0xdc] */
-	struct al_pcie_revx_axi_parity parity;               /* [0xfc] */
-	struct al_pcie_revx_axi_pos_logged pos_logged;       /* [0x104] */
-	struct al_pcie_revx_axi_ordering ordering;           /* [0x10c] */
-	struct al_pcie_revx_axi_link_down link_down;         /* [0x110] */
-	struct al_pcie_revx_axi_pre_configuration pre_configuration; /* [0x114] */
-	struct al_pcie_revx_axi_init_fc init_fc;             /* [0x118] */
-	uint32_t rsrvd_1[20];
-	struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
-	uint32_t rsrvd_2[36];
-	struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x200] */
-};
-
-struct al_pcie_rev2_axi_regs {
-	struct al_pcie_rev1_2_axi_ctrl ctrl;     /* [0x0] */
-	struct al_pcie_rev2_axi_ob_ctrl ob_ctrl; /* [0x40] */
-	uint32_t rsrvd_0[4];
-	struct al_pcie_revx_axi_msg msg;                     /* [0x90] */
-	struct al_pcie_revx_axi_pcie_status pcie_status;     /* [0x9c] */
-	struct al_pcie_revx_axi_rd_parity rd_parity;         /* [0xa0] */
-	struct al_pcie_revx_axi_rd_cmpl rd_cmpl;             /* [0xa8] */
-	struct al_pcie_revx_axi_rd_to rd_to;                 /* [0xb0] */
-	struct al_pcie_revx_axi_wr_cmpl wr_cmpl;             /* [0xb8] */
-	struct al_pcie_revx_axi_wr_to wr_to;                 /* [0xc0] */
-	struct al_pcie_revx_axi_pcie_global pcie_global;     /* [0xc8] */
-	struct al_pcie_rev1_2_axi_status status;               /* [0xcc] */
-	struct al_pcie_rev1_2_axi_conf conf;                   /* [0xdc] */
-	struct al_pcie_revx_axi_parity parity;               /* [0xfc] */
-	struct al_pcie_revx_axi_pos_logged pos_logged;       /* [0x104] */
-	struct al_pcie_revx_axi_ordering ordering;           /* [0x10c] */
-	struct al_pcie_revx_axi_link_down link_down;         /* [0x110] */
-	struct al_pcie_revx_axi_pre_configuration pre_configuration; /* [0x114] */
-	struct al_pcie_revx_axi_init_fc init_fc;             /* [0x118] */
-	uint32_t rsrvd_1[20];
-	struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
-	uint32_t rsrvd_2[36];
-	struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x200] */
-};
-
-struct al_pcie_rev3_axi_regs {
-	struct al_pcie_rev3_axi_ctrl ctrl;  /* [0x0] */
-	struct al_pcie_rev3_axi_ob_ctrl ob_ctrl;/* [0x30] */
-	struct al_pcie_revx_axi_msg msg;                  /* [0x90] */
-	struct al_pcie_revx_axi_pcie_status pcie_status;  /* [0x9c] */
-	struct al_pcie_revx_axi_rd_parity rd_parity;      /* [0xa0] */
-	struct al_pcie_revx_axi_rd_cmpl rd_cmpl;          /* [0xa8] */
-	struct al_pcie_revx_axi_rd_to rd_to;              /* [0xb0] */
-	struct al_pcie_revx_axi_wr_cmpl wr_cmpl;          /* [0xb8] */
-	struct al_pcie_revx_axi_wr_to wr_to;              /* [0xc0] */
-	struct al_pcie_revx_axi_pcie_global pcie_global;  /* [0xc8] */
-	uint32_t rsrvd_0;
-	struct al_pcie_revx_axi_parity parity;            /* [0xd0] */
-	struct al_pcie_revx_axi_pos_logged pos_logged;    /* [0xd8] */
-	struct al_pcie_revx_axi_ordering ordering;        /* [0xe0] */
-	struct al_pcie_revx_axi_link_down link_down;      /* [0xe4] */
-	struct al_pcie_revx_axi_pre_configuration pre_configuration;/* [0xe8] */
-	struct al_pcie_revx_axi_init_fc init_fc;          /* [0xec] */
-	uint32_t rsrvd_1[4];
-	struct al_pcie_rev3_axi_eq_ovrd_tx_rx_values eq_ovrd_tx_rx_values;/* [0x100] */
-	struct al_pcie_rev3_axi_dbg_outstading_trans_axi dbg_outstading_trans_axi;/* [0x160] */
-	struct al_pcie_revx_axi_device_id device_id;      /* [0x16c] */
-	struct al_pcie_revx_axi_power_mang_ovrd_cntl power_mang_ovrd_cntl;/* [0x170] */
-	struct al_pcie_rev3_axi_dbg_outstading_trans_axi_write dbg_outstading_trans_axi_write;/* [0x190] */
-	uint32_t rsrvd_2[3];
-	struct al_pcie_rev3_axi_attr_ovrd axi_attr_ovrd; /* [0x1a0] */
-	struct al_pcie_rev3_axi_pf_axi_attr_ovrd pf_axi_attr_ovrd[REV3_MAX_NUM_OF_PFS];/* [0x1c0] */
-	uint32_t rsrvd_3[64];
-	struct al_pcie_rev3_axi_status status;            /* [0x3c0] */
-	struct al_pcie_rev3_axi_conf conf;                /* [0x400] */
-	uint32_t rsrvd_4[32];
-	struct al_pcie_revx_axi_msg_attr_axuser_table msg_attr_axuser_table; /* [0x500] */
-	uint32_t rsrvd_5[191];
-	struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x800] */
-};
-
-/*
-* Registers Fields
-*/
-
-/**** Device ID register ****/
-#define PCIE_AXI_DEVICE_ID_REG_DEV_ID_MASK	AL_FIELD_MASK(31, 16)
-#define PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT	16
-#define PCIE_AXI_DEVICE_ID_REG_DEV_ID_X4	(0 << PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT)
-#define PCIE_AXI_DEVICE_ID_REG_DEV_ID_X8	(2 << PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT)
-#define PCIE_AXI_DEVICE_ID_REG_REV_ID_MASK	AL_FIELD_MASK(15, 0)
-#define PCIE_AXI_DEVICE_ID_REG_REV_ID_SHIFT	0
-
-/**** Global register ****/
-/*
- * Not in use.
- * Disable completion after inbound posted ordering enforcement to AXI bridge.
- */
-#define PCIE_AXI_CTRL_GLOBAL_CPL_AFTER_P_ORDER_DIS (1 << 0)
-/*
- * Not in use.
- * Enforce completion after write ordering on AXI bridge. Only for CPU read
- * requests.
- */
-#define PCIE_AXI_CTRL_GLOBAL_CPU_CPL_ONLY_EN (1 << 1)
-/* When linked down, map all transactions to PCIe to DEC ERR. */
-#define PCIE_AXI_CTRL_GLOBAL_BLOCK_PCIE_SLAVE_EN (1 << 2)
-/*
- * Wait for the NIC to flush before enabling reset to the PCIe core, on a link
- * down event.
- */
-#define PCIE_AXI_CTRL_GLOBAL_WAIT_SLV_FLUSH_EN (1 << 3)
-/*
- * When the BME is cleared and this bit is set, it causes all transactions that
- * do not get to the PCIe to be returned with DECERR.
- */
-#define PCIE_REV1_2_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR (1 << 4)
-#define PCIE_REV3_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR_MASK 0x00000FF0
-#define PCIE_REV3_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR_SHIFT 4
-/*
- * Wait for the DBI port (the port that enables access to the internal PCIe core
- * registers) to flush before enabling reset to the PCIe core on link down
- * event.
- */
-#define PCIE_REV1_2_AXI_CTRL_GLOBAL_WAIT_DBI_FLUSH_EN (1 << 5)
-#define PCIE_REV3_AXI_CTRL_GLOBAL_WAIT_DBI_FLUSH_EN (1 << 12)
-/* Reserved. Read undefined; must read as zeros. */
-#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_FLUSH_DBI_AXI (1 << 13)
-/* Reserved. Read undefined; must read as zeros. */
-#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_HOLD_LNKDWN_RESET_SW (1 << 14)
-/* Reserved. Read undefined; must read as zeros. */
-#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_MASK_CORECLK_ACT_CLK_RST (1 << 15)
-/* Reserved. Read undefined; must read as zeros. */
-#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_MASK_RXELECIDLE_CLK_RST (1 << 16)
-/* Reserved. Read undefined; must read as zeros. */
-#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_ALLOW_NONSTICKY_RESET_WHEN_LNKDOWN_CLK_RST (1 << 17)
-
-/*
- * When set, adds parity on the write and read address channels, and write data
- * channel.
- */
-#define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR (1 << 16)
-#define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR (1 << 18)
-/* When set, enables parity check on the read data. */
-#define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD (1 << 17)
-#define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD (1 << 19)
-/*
- * When set, adds parity on the RD data channel.
- */
-#define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV (1 << 18)
-#define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV (1 << 20)
-/*
- * When set, enables parity check on the write data.
- */
-#define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR (1 << 19)
-#define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR (1 << 21)
-/*
- * When set, error track for timeout and parity is disabled, i.e., the logged
- * address for parity/timeout/cmpl errors on the AXI master port is not valid,
- * and timeout and completion errors check are disabled.
- */
-#define PCIE_REV1_2_AXI_CTRL_GLOBAL_ERROR_TRACK_DIS (1 << 20)
-#define PCIE_REV3_AXI_CTRL_GLOBAL_ERROR_TRACK_DIS (1 << 22)
-
-/**** Master_Arctl register ****/
-/* override arcache */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_OVR_ARCACHE (1 << 0)
-/* arache value */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_ARACHE_VA_MASK 0x0000001E
-#define PCIE_AXI_CTRL_MASTER_ARCTL_ARACHE_VA_SHIFT 1
-/* arprot override */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_OVR (1 << 5)
-/* arprot value */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_VALUE_MASK 0x000001C0
-#define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_VALUE_SHIFT 6
-/* vmid val */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_VMID_VAL_MASK 0x01FFFE00
-#define PCIE_AXI_CTRL_MASTER_ARCTL_VMID_VAL_SHIFT 9
-/* IPA value */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_IPA_VAL (1 << 25)
-/* overide snoop inidcation, if not set take it from mstr_armisc ... */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP (1 << 26)
-/*
-snoop indication value when override */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_SNOOP (1 << 27)
-/*
-arqos value */
-#define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_MASK 0xF0000000
-#define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_SHIFT 28
-
-/**** Master_Awctl register ****/
-/* override arcache */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_OVR_ARCACHE (1 << 0)
-/* awache value */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_AWACHE_VA_MASK 0x0000001E
-#define PCIE_AXI_CTRL_MASTER_AWCTL_AWACHE_VA_SHIFT 1
-/* awprot override */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_OVR (1 << 5)
-/* awprot value */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_VALUE_MASK 0x000001C0
-#define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_VALUE_SHIFT 6
-/* vmid val */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_VMID_VAL_MASK 0x01FFFE00
-#define PCIE_AXI_CTRL_MASTER_AWCTL_VMID_VAL_SHIFT 9
-/* IPA value */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_IPA_VAL (1 << 25)
-/* overide snoop inidcation, if not set take it from mstr_armisc ... */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP (1 << 26)
-/*
-snoop indication value when override */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_SNOOP (1 << 27)
-/*
-awqos value */
-#define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_MASK 0xF0000000
-#define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_SHIFT 28
-
-/**** slv_ctl register ****/
-#define PCIE_AXI_CTRL_SLV_CTRL_IO_BAR_EN	(1 << 6)
-
-/**** Cfg_Target_Bus register ****/
-/*
- * Defines which MSBs to complete the number of the bust that arrived from ECAM.
- * If set to 0, take the bit from the ECAM bar, otherwise from the busnum of
- * this register.
- * The LSB for the bus number comes on the addr[*:20].
- */
-#define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK 0x000000FF
-#define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT 0
-/* Target bus number for outbound configuration type0 and type1 access */
-#define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK 0x0000FF00
-#define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_SHIFT 8
-
-/**** Cfg_Control register ****/
-/* Primary bus number */
-#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_PBUS_MASK 0x000000FF
-#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_PBUS_SHIFT 0
-/*
- *
- * Subordinate bus number
- */
-#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_MASK 0x0000FF00
-#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_SHIFT 8
-/* Secondary bus nnumber */
-#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_MASK 0x00FF0000
-#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_SHIFT 16
-/* Enable outbound configuration access through iATU.  */
-#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_IATU_EN (1 << 31)
-
-/**** IO_Start_H register ****/
-/*
- *
- * Outbound ATIU I/O start address high
- */
-#define PCIE_AXI_MISC_OB_CTRL_IO_START_H_ADDR_MASK 0x000003FF
-#define PCIE_AXI_MISC_OB_CTRL_IO_START_H_ADDR_SHIFT 0
-
-/**** IO_Limit_H register ****/
-/*
- *
- * Outbound ATIU I/O limit address high
- */
-#define PCIE_AXI_MISC_OB_CTRL_IO_LIMIT_H_ADDR_MASK 0x000003FF
-#define PCIE_AXI_MISC_OB_CTRL_IO_LIMIT_H_ADDR_SHIFT 0
-
-/**** Msg_Start_H register ****/
-/*
- *
- * Outbound ATIU msg-no-data start address high
- */
-#define PCIE_AXI_MISC_OB_CTRL_MSG_START_H_ADDR_MASK 0x000003FF
-#define PCIE_AXI_MISC_OB_CTRL_MSG_START_H_ADDR_SHIFT 0
-
-/**** Msg_Limit_H register ****/
-/*
- *
- * Outbound ATIU msg-no-data limit address high
- */
-#define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_MASK 0x000003FF
-#define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_SHIFT 0
-
-/**** vmid_reg_ovrd register ****/
-/*
- * select if to take the value from register or from address[63:48]:
- * 1'b1: register value.
- * 1'b0: from address[63:48]
- */
-#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_SEL_MASK 0x0000FFFF
-#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_SEL_SHIFT 0
-/* vmid override value. */
-#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_VALUE_MASK 0xFFFF0000
-#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_VALUE_SHIFT 16
-
-/**** addr_size_replace register ****/
-/*
- * Size in bits to replace from bit [63:64-N], when equal zero no replace is
- * done.
- */
-#define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_VALUE_MASK 0x0000FFFF
-#define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_VALUE_SHIFT 0
-/* Reserved. */
-#define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_RSRVD_MASK 0xFFFF0000
-#define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_RSRVD_SHIFT 16
-
-/**** type register ****/
-/* Type of message */
-#define PCIE_AXI_MISC_MSG_TYPE_TYPE_MASK 0x00FFFFFF
-#define PCIE_AXI_MISC_MSG_TYPE_TYPE_SHIFT 0
-/* Reserved */
-#define PCIE_AXI_MISC_MSG_TYPE_RSRVD_MASK 0xFF000000
-#define PCIE_AXI_MISC_MSG_TYPE_RSRVD_SHIFT 24
-
-/**** debug register ****/
-/* Causes ACI PCIe reset, including ,master/slave/DBI (registers). */
-#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_AXI_BRIDGE_RESET (1 << 0)
-/*
- * Causes reset of the entire PCIe core (including the AXI bridge).
- * When set, the software must not address the PCI core (through the MEM space
- * and REG space).
- */
-#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_CORE_RESET (1 << 1)
-/*
- * Indicates that the SB is empty from the request to the PCIe (not including
- * registers).
- */
-#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_SB_FLUSH_OB_STATUS (1 << 2)
-/* MAP and transaction to the PCIe core to ERROR. */
-#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_SB_MAP_TO_ERR (1 << 3)
-/* Indicates that the pcie_core clock is gated off */
-#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_CORE_CLK_GATE_OFF (1 << 4)
-/* Reserved */
-#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_RSRVD_MASK 0xFFFFFFE0
-#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_RSRVD_SHIFT 5
-
-/**** conf register ****/
-/*
- * Device Type
- * Indicates the specific type of this PCI Express Function. It is also used to
- * set the
- * Device/Port Type field.
- *
- * 4'b0000: PCI Express Endpoint
- * 4'b0001: Legacy PCI Express Endpoint
- * 4'b0100: Root Port of PCI Express Root Complex
- *
- * Must be programmed before link training sequence, according to the reset
- * strap.
- * Change this register should be when the pci_exist (in the PBS regfile) is
- * zero.
- */
-#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK 0x0000000F
-#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT 0
-/*
- * [i] - Lane i active
- * Change this register should be when the pci_exist (in the PBS regfile) is
- * zero.
- */
-#define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK 0x000000F0
-#define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_MASK 0xFFFFFF00
-#define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_SHIFT 8
-#define PCIE_REVX_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_SHIFT 4
-#define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK 0x000FFFF0
-#define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_MASK 0xFFF00000
-#define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_SHIFT 20
-
-#define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN 0x100
-#define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN 0x100000
-
-/**** laneX register ****/
-#define PCIE_AXI_STATUS_LANE_IS_RESET				AL_BIT(13)
-#define PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_MASK		AL_FIELD_MASK(2, 0)
-#define PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_SHIFT		0
-
-/**** zero_laneX register ****/
-/* phy_mac_local_fs */
-#define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_MASK		0x0000003f
-#define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_SHIFT	0
-/* phy_mac_local_lf */
-#define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_MASK		0x00000fc0
-#define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_SHIFT	6
-
-/**** en_axi register ****/
-/* u4_ram2p */
-#define PCIE_AXI_PARITY_EN_AXI_U4_RAM2P				AL_BIT(1)
-
-/**** pos_cntl register ****/
-/* Disables POS. */
-#define PCIE_AXI_POS_ORDER_AXI_POS_BYPASS (1 << 0)
-/* Clear the POS data structure. */
-#define PCIE_AXI_POS_ORDER_AXI_POS_CLEAR (1 << 1)
-/* Read push all write. */
-#define PCIE_AXI_POS_ORDER_AXI_POS_RSO_ENABLE (1 << 2)
-/*
- * Causes the PCIe core to wait for all the BRESPs before issuing a read
- * request.
- */
-#define PCIE_AXI_POS_ORDER_AXI_DW_RD_FLUSH_WR (1 << 3)
-/*
- * When set, to 1'b1 supports interleaving data return from the PCIe core. Valid
- * only when cfg_bypass_cmpl_after_write_fix is set.
- */
-#define PCIE_AXI_POS_ORDER_RD_CMPL_AFTER_WR_SUPPORT_RD_INTERLV (1 << 4)
-/* When set, to 1'b1 disables read completion after write ordering. */
-#define PCIE_AXI_POS_ORDER_BYPASS_CMPL_AFTER_WR_FIX (1 << 5)
-/*
- * When set, disables EP mode read cmpl on the master port push slave writes,
- * when each read response from the master is not interleaved.
- */
-#define PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_DIS (1 << 6)
-/* When set, disables EP mode read cmpl on the master port push slave writes. */
-#define PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_SUPPORT_INTERLV_DIS (1 << 7)
-/* should be zero */
-#define PCIE_AXI_POS_ORDER_9_8 AL_FIELD_MASK(9, 8)
-/* Give the segmentation buffer not to wait for P writes to end in the AXI
- * bridge before releasing the CMPL.
- */
-#define PCIE_AXI_POS_ORDER_SEGMENT_BUFFER_DONT_WAIT_FOR_P_WRITES AL_BIT(10)
-/* should be zero */
-#define PCIE_AXI_POS_ORDER_11 AL_BIT(11)
-/**
- * When set cause pcie core to send ready in the middle of the read data
- * burst returning from the DRAM to the PCIe core
- */
-#define PCIE_AXI_POS_ORDER_SEND_READY_ON_READ_DATA_BURST AL_BIT(12)
-/* When set disable the ATS CAP.  */
-#define PCIE_AXI_CORE_SETUP_ATS_CAP_DIS	AL_BIT(13)
-/* When set disable D3/D2/D1 PME support */
-#define PCIE_AXI_POS_ORDER_DISABLE_DX_PME AL_BIT(14)
-/* When set enable nonsticky reset when linkdown hot reset */
-#define PCIE_AXI_POS_ORDER_ENABLE_NONSTICKY_RESET_ON_HOT_RESET AL_BIT(15)
-/* When set, terminate message with data as UR request */
-#define PCIE_AXI_TERMINATE_DATA_MSG_AS_UR_REQ AL_BIT(16)
-
-/**** pcie_core_setup register ****/
-/*
- * This Value delay the rate change to the serdes, until the EIOS is sent by the
- * serdes. Should be program before the pcie_exist, is asserted.
- */
-#define PCIE_AXI_CORE_SETUP_DELAY_MAC_PHY_RATE_MASK 0x000000FF
-#define PCIE_AXI_CORE_SETUP_DELAY_MAC_PHY_RATE_SHIFT 0
-/*
- * Limit the number of outstanding AXI reads that the PCIe core can get. Should
- * be program before the pcie_exist, is asserted.
- */
-#define PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_MASK 0x0000FF00
-#define PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_SHIFT 8
-/* Enable the sriov feature. */
-#define PCIE_AXI_REV1_2_CORE_SETUP_SRIOV_ENABLE AL_BIT(16)
-/* not in use */
-#define PCIE_AXI_REV3_CORE_SETUP_NOT_IN_USE (1 << 16)
-/* Reserved. Read undefined; must read as zeros. */
-#define PCIE_AXI_REV3_CORE_SETUP_CFG_DELAY_AFTER_PCIE_EXIST_MASK 0x0FFE0000
-#define PCIE_AXI_REV3_CORE_SETUP_CFG_DELAY_AFTER_PCIE_EXIST_SHIFT 17
-
-/**** cfg register ****/
-/* This value set the possible out standing headers writes (post ... */
-#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_MASK 0x0000007F
-#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_SHIFT 0
-/* This value set the possible out standing headers reads (non-p ... */
-#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_MASK 0x00003F80
-#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_SHIFT 7
-/* This value set the possible out standing headers CMPLs , the  ... */
-#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_MASK 0x001FC000
-#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_SHIFT 14
-
-#define PCIE_AXI_REV1_2_INIT_FC_CFG_RSRVD_MASK 0xFFE00000
-#define PCIE_AXI_REV1_2_INIT_FC_CFG_RSRVD_SHIFT 21
-
-/* This value set the possible out standing headers writes (post ... */
-#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_MASK 0x000001FF
-#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_SHIFT 0
-/* This value set the possible out standing headers reads (non-p ... */
-#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_MASK 0x0003FE00
-#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_SHIFT 9
-/* This value set the possible out standing headers CMPLs , the  ... */
-#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_MASK 0x07FC0000
-#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_SHIFT 18
- /*
- * [27] cfg_cpl_p_rr: do round robin on the SB output btw Posted and CPL.
- * [28] cfg_np_pass_p_rr, in case RR between CPL AND P, allow to pass NP in case
- * p is empty.
- * [29] cfg_np_part_of_rr_arb: NP also is a part of the round robin arbiter.
- */
-#define PCIE_AXI_REV3_INIT_FC_CFG_RSRVD_MASK 0xF8000000
-#define PCIE_AXI_REV3_INIT_FC_CFG_RSRVD_SHIFT 27
-
-/**** write_msg_ctrl_0 register ****/
-/*
- * choose if 17 in the AXUSER indicate message hint (1'b1) or no snoop
- * indication (1'b0)
- */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_OUTBOUND_MSG_NO_SNOOP_N (1 << 0)
-/* this bit define if the message is with data or without  */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_WITH_DATA (1 << 1)
-/* message code for message with data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_DATA_MASK 0x000003FC
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_DATA_SHIFT 2
-/* message code for message without data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_MASK 0x0003FC00
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_SHIFT 10
-/* message ST value */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_ST_MASK 0x03FC0000
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_ST_SHIFT 18
-/* message NO-SNOOP */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_NO_SNOOP (1 << 26)
-/* message TH bit */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_TH (1 << 27)
-/* message PH bits */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_PH_MASK 0x30000000
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_PH_SHIFT 28
-/* Rsrvd */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_RSRVD_MASK 0xC0000000
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_RSRVD_SHIFT 30
-
-/**** write_msg_ctrl_1 register ****/
-/* message type */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MISC_MSG_TYPE_VALUE_MASK 0x0000001F
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MISC_MSG_TYPE_VALUE_SHIFT 0
-/* this bit define if the message is with data or without  */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_TYPE_VALUE_MASK 0x000003E0
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_TYPE_VALUE_SHIFT 5
-/* override axi size for message with no data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_OVRD (1 << 10)
-/* override the AXI size to the pcie core for message with no data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_MSG_MASK 0x00003800
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_MSG_SHIFT 11
-/* override axi size for message with data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_OVRD (1 << 14)
-/* override the AXI size to the pcie core for message with data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_MSG_MASK 0x00038000
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_MSG_SHIFT 15
-/* Rsrvd */
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_RSRVD_MASK 0xFFFC0000
-#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_RSRVD_SHIFT 18
-
-/**** read_msg_ctrl_0 register ****/
-/*
- * choose if 17 in the AXUSER indicate message hint (1'b1) or no snoop
- * indication (1'b0)
- */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_OUTBOUND_MSG_NO_SNOOP_N (1 << 0)
-/* this bit define if the message is with data or without  */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_WITH_DATA (1 << 1)
-/* message code for message with data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_DATA_MASK 0x000003FC
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_DATA_SHIFT 2
-/* message code for message without data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_MASK 0x0003FC00
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_SHIFT 10
-/* message ST value */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_ST_MASK 0x03FC0000
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_ST_SHIFT 18
-/* message NO-SNOOP */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_NO_SNOOP (1 << 26)
-/* message TH bit */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_TH (1 << 27)
-/* message PH bits */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_PH_MASK 0x30000000
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_PH_SHIFT 28
-/* Rsrvd */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_RSRVD_MASK 0xC0000000
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_RSRVD_SHIFT 30
-
-/**** read_msg_ctrl_1 register ****/
-/* message type */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MISC_MSG_TYPE_VALUE_MASK 0x0000001F
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MISC_MSG_TYPE_VALUE_SHIFT 0
-/* this bit define if the message is with data or without  */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_TYPE_VALUE_MASK 0x000003E0
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_TYPE_VALUE_SHIFT 5
-/* override axi size for message with no data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_OVRD (1 << 10)
-/* override the AXI size to the pcie core for message with no data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_MSG_MASK 0x00003800
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_MSG_SHIFT 11
-/* override axi size for message with data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_OVRD (1 << 14)
-/* override the AXI size to the pcie core for message with data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_MSG_MASK 0x00038000
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_MSG_SHIFT 15
-/* Rsrvd */
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_RSRVD_MASK 0xFFFC0000
-#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_RSRVD_SHIFT 18
-
-/**** pf_sel register ****/
-/* message type */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_AXUSER (1 << 0)
-/* this bit define if the message is with data or without  */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_REG (1 << 1)
-/* override axi size for message with no data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_ADDR_OFFSET_MASK 0x0000003C
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_ADDR_OFFSET_SHIFT 2
-/* override the AXI size to the pcie core for message with no data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT0_OVRD (1 << 6)
-/* Rsrvd */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_7 (1 << 7)
-/* message type */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_AXUSER (1 << 8)
-/* this bit define if the message is with data or without  */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_REG (1 << 9)
-/* override axi size for message with no data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_ADDR_OFFSET_MASK 0x00003C00
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_ADDR_OFFSET_SHIFT 10
-/* override the AXI size to the pcie core for message with no data. */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT1_OVRD (1 << 14)
-/* Rsrvd */
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_MASK 0xFFFF8000
-#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_SHIFT 15
-
- /**** func_ctrl_0 register ****/
-/* choose the field  from the axuser */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_OVRD_FROM_AXUSER (1 << 0)
-/* choose the field  from register */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_OVRD_FROM_REG (1 << 1)
-/* field offset from the address portions according to the spec */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_ADDR_OFFSET_MASK 0x0000003C
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_ADDR_OFFSET_SHIFT 2
-/* register value override */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_TH_OVRD (1 << 6)
-/* choose the field  from the axuser */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_AXUSER_MASK 0x00007F80
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_AXUSER_SHIFT 7
-/* choose the field  from register */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_REG_MASK 0x007F8000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_REG_SHIFT 15
-/* register value override */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_ST_VEC_OVRD_MASK 0x7F800000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_ST_VEC_OVRD_SHIFT 23
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_RSRVD (1 << 31)
-
-/**** func_ctrl_2 register ****/
-/* choose the field  from the axuser */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK 0x00000003
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_SHIFT 0
-/* choose the field  from register */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_REG_MASK 0x0000000C
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_REG_SHIFT 2
-/* in case the field take from the address, offset field for each bit. */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_ADDR_OFFSET_MASK 0x00000FF0
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_ADDR_OFFSET_SHIFT 4
-/* register value override */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_PH_VEC_OVRD_MASK 0x00003000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_PH_VEC_OVRD_SHIFT 12
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_14_15_MASK 0x0000C000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_14_15_SHIFT 14
-/* choose the field  from the axuser */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_AXUSER_MASK 0x00030000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_AXUSER_SHIFT 16
-/* choose the field  from register */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_REG_MASK 0x000C0000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_REG_SHIFT 18
-/* in case the field take from the address, offset field for each bit. */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_ADDR_OFFSET_MASK 0x0FF00000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_ADDR_OFFSET_SHIFT 20
-/* register value override */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_VMID89_VEC_OVRD_MASK 0x30000000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_VMID89_VEC_OVRD_SHIFT 28
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_MASK 0xC0000000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_SHIFT 30
-
-/**** func_ctrl_3 register ****/
-/*
- * When set take the corresponding bit address from register
- * pf_vec_mem_addr44_53_ovrd
- */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_SEL_MASK 0x000003FF
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_SEL_SHIFT 0
-/* override value. */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_OVRD_MASK 0x000FFC00
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_OVRD_SHIFT 10
-/*
- * When set take the corresponding bit address from register
- * pf_vec_mem_addr54_63_ovrd
- */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR54_63_SEL_MASK 0x3FF00000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR54_63_SEL_SHIFT 20
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_RSRVD_MASK 0xC0000000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_RSRVD_SHIFT 30
-
-/**** func_ctrl_4 register ****/
-/* When set take the corresponding bit address from vmid value. */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_VMID_MASK 0x000003FF
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_VMID_SHIFT 0
-/* override value. */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_OVRD_MASK 0x000FFC00
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_OVRD_SHIFT 10
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_RSRVD_MASK 0xFFF00000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_RSRVD_SHIFT 20
-
-/**** func_ctrl_5 register ****/
-/*
- * When set take the corresponding bit address [63:44] from
- * aw_pf_vec_msg_addr_ovrd
- */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_AW_PF_VEC_MSG_ADDR_SEL_MASK 0x000FFFFF
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_AW_PF_VEC_MSG_ADDR_SEL_SHIFT 0
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_RSRVD_MASK 0xFFF00000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_RSRVD_SHIFT 20
-
-/**** func_ctrl_6 register ****/
-/* override value. */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_AW_PF_VEC_MSG_ADDR_OVRD_MASK 0x000FFFFF
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_AW_PF_VEC_MSG_ADDR_OVRD_SHIFT 0
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_RSRVD_MASK 0xFFF00000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_RSRVD_SHIFT 20
-
-/**** func_ctrl_7 register ****/
-/*
- * When set take the corresponding bit address [63:44] from
- * ar_pf_vec_msg_addr_ovrd
- */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_AR_PF_VEC_MSG_ADDR_SEL_MASK 0x000FFFFF
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_AR_PF_VEC_MSG_ADDR_SEL_SHIFT 0
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_RSRVD_MASK 0xFFF00000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_RSRVD_SHIFT 20
-
-/**** func_ctrl_8 register ****/
-/* override value. */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_AR_PF_VEC_MSG_ADDR_OVRD_MASK 0x000FFFFF
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_AR_PF_VEC_MSG_ADDR_OVRD_SHIFT 0
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_RSRVD_MASK 0xFFF00000
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_RSRVD_SHIFT 20
-
-/**** func_ctrl_9 register ****/
-/* no snoop override  */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_NO_SNOOP_OVRD (1 << 0)
-/* no snoop override value  */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_NO_SNOOP_OVRD_VALUE (1 << 1)
-/* atu bypass override  */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_ATU_BYPASS_OVRD (1 << 2)
-/* atu bypass override value */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_ATU_BYPASS_OVRD_VALUE (1 << 3)
-/* Rsrvd */
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_RSRVD_MASK 0xFFFFFFF0
-#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_RSRVD_SHIFT 4
-
-/**** entry_vec register ****/
-/* entry0 */
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_0_MASK	0x0000001F
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_0_SHIFT	0
-/* entry1 */
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_1_MASK	0x000003E0
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_1_SHIFT	5
-/* entry2 */
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_2_MASK	0x00007C00
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_2_SHIFT	10
-/* entry3 */
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_3_MASK	0x000F8000
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_3_SHIFT	15
-/* atu bypass for message "write" */
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_AW_MSG_ATU_BYPASS (1 << 20)
-/* atu bypass for message "read" */
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_AR_MSG_ATU_BYPASS (1 << 21)
-/* Rsrvd */
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_RSRVD_MASK	0xFFC00000
-#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_RSRVD_SHIFT	22
-
-/**** int_cause_grp_A_axi register ****/
-/*
- * Master Response Composer Lookup Error
- * Overflow that occurred in a lookup table of the Outbound responses. This
- * indicates that there was a violation for the number of outstanding NP
- * requests issued for the Inbound direction.
- * Write zero to clear.
- */
-#define PCIE_AXI_INT_GRP_A_CAUSE_GM_COMPOSER_LOOKUP_ERR (1 << 0)
-/*
- * Indicates a PARITY ERROR on the master data read channel.
- * Write zero to clear.
- */
-#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_DATA_PATH_RD (1 << 2)
-/*
- * Indicates a PARITY ERROR on the slave addr read channel.
- * Write zero to clear.
- */
-#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_RD (1 << 3)
-/*
- * Indicates a PARITY ERROR on the slave addr write channel.
- * Write zero to clear.
- */
-#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_WR (1 << 4)
-/*
- * Indicates a PARITY ERROR on the slave data write channel.
- * Write zero to clear.
- */
-#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_DATA_WR (1 << 5)
-/* Reserved */
-#define PCIE_AXI_INT_GRP_A_CAUSE_RESERVED_6 (1 << 6)
-/*
- * Software error: ECAM write request with invalid bus number.
- * Write Zero to clear
- */
-#define PCIE_AXI_INT_GRP_A_CAUSE_SW_ECAM_ERR_RD (1 << 7)
-/*
- * Software error: ECAM read request with invalid bus number.
- * Write Zero to clear.
- */
-#define PCIE_AXI_INT_GRP_A_CAUSE_SW_ECAM_ERR_WR (1 << 8)
-/* Indicates an ERROR in the PCIe application cause register. */
-#define PCIE_AXI_INT_GRP_A_CAUSE_PCIE_CORE_INT (1 << 9)
-/*
- * Whenever the Master AXI finishes writing a message, it sets this bit.
- * Whenever the int is cleared, the message information MSG_* regs are no longer
- * valid.
- */
-#define PCIE_AXI_INT_GRP_A_CAUSE_MSTR_AXI_GETOUT_MSG (1 << 10)
-/* Read AXI compilation has ERROR. */
-#define PCIE_AXI_INT_GRP_A_CAUSE_RD_CMPL_ERR (1 << 11)
-/* Write AXI compilation has ERROR. */
-#define PCIE_AXI_INT_GRP_A_CAUSE_WR_CMPL_ERR (1 << 12)
-/* Read AXI compilation has timed out. */
-#define PCIE_AXI_INT_GRP_A_CAUSE_RD_CMPL_TO (1 << 13)
-/* Write AXI compilation has timed out. */
-#define PCIE_AXI_INT_GRP_A_CAUSE_WR_CMPL_TO (1 << 14)
-/* Parity error AXI domain */
-#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERROR_AXI (1 << 15)
-/* POS error interrupt */
-#define PCIE_AXI_INT_GRP_A_CAUSE_POS_AXI_BRESP (1 << 16)
-/* The outstanding write counter become  full should never happen */
-#define PCIE_AXI_INT_GRP_A_CAUSE_WRITE_CNT_FULL_ERR (1 << 17)
-/* BRESP received before the write counter increment.  */
-#define PCIE_AXI_INT_GRP_A_CAUSE_BRESP_BEFORE_WR_CNT_INC_ERR (1 << 18)
-
-/**** int_control_grp_A_axi register ****/
-/* When Clear_on_Read =1, all bits of the Cause register are cleared on read. */
-#define PCIE_AXI_INT_GRP_A_CTRL_CLEAR_ON_READ (1 << 0)
-/*
- * (Must be set only when MSIX is enabled.)
- * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
- * corresponding bit in the mask register is set, masking future interrupts.
- */
-#define PCIE_AXI_INT_GRP_A_CTRL_AUTO_MASK (1 << 1)
-/*
- * Auto_Clear (RW)
- * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
- * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
- */
-#define PCIE_AXI_INT_GRP_A_CTRL_AUTO_CLEAR (1 << 2)
-/*
- * When set,_on_Posedge =1, the bits in the Interrupt Cause register are set on
- * the posedge of the interrupt source, i.e., when interrupt source =1 and
- * Interrupt Status = 0.
- * When set,_on_Posedge =0, the bits in the Interrupt Cause register are set
- * when interrupt source =1.
- */
-#define PCIE_AXI_INT_GRP_A_CTRL_SET_ON_POS (1 << 3)
-/*
- * When Moderation_Reset =1, all Moderation timers associated with the interrupt
- * cause bits are cleared to 0, enabling immediate interrupt assertion if any
- * unmasked cause bit is set to 1. This bit is self-negated.
- */
-#define PCIE_AXI_INT_GRP_A_CTRL_MOD_RST (1 << 4)
-/*
- * When mask_msi_x =1, no MSI-X from this group is sent. This bit is set to 1
- * when the associate summary bit in this group is used to generate a single
- * MSI-X for this group.
- */
-#define PCIE_AXI_INT_GRP_A_CTRL_MASK_MSI_X (1 << 5)
-/* MSI-X AWID value. Same ID for all cause bits. */
-#define PCIE_AXI_INT_GRP_A_CTRL_AWID_MASK 0x00000F00
-#define PCIE_AXI_INT_GRP_A_CTRL_AWID_SHIFT 8
-/*
- * This value determines the interval between interrupts. Writing ZERO disables
- * Moderation.
- */
-#define PCIE_AXI_INT_GRP_A_CTRL_MOD_INTV_MASK 0x00FF0000
-#define PCIE_AXI_INT_GRP_A_CTRL_MOD_INTV_SHIFT 16
-/*
- * This value determines the Moderation_Timer_Clock speed.
- * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
- * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
- * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
- */
-#define PCIE_AXI_INT_GRP_A_CTRL_MOD_RES_MASK 0x0F000000
-#define PCIE_AXI_INT_GRP_A_CTRL_MOD_RES_SHIFT 24
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_pcie_axi_REG_H */
-
-/** @} end of ... group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_pcie_interrupts.h b/sys/contrib/alpine-hal/eth/al_hal_pcie_interrupts.h
deleted file mode 100644
index 357971ca63cb..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_pcie_interrupts.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#ifndef _AL_HAL_PCIE_INTERRUPTS_H_
-#define _AL_HAL_PCIE_INTERRUPTS_H_
-
-#include "al_hal_common.h"
-#include "al_hal_pcie.h"
-#include "al_hal_iofic.h"
-
-/**
- * @defgroup group_pcie_interrupts PCIe interrupts
- * @ingroup grouppcie
- *  @{
- *  The PCIe interrupts HAL can be used to control PCIe unit interrupts.
- *  There are 5 groups of interrupts: app group A, B, C, D and AXI.
- *  Only 2 interrupts go from the pcie unit to the GIC:
- *  1. Summary for all the int groups (AXI+APP CORE).
- *  2. INTA assert/deassert (RC only).
- *  For the specific GIC interrupt line, please check the architecture reference
- *  manual.
- *  The reset mask state of all interrupts is: Masked
- *
- * @file   al_hal_pcie_interrupts.h
- *
- */
-
-/**
- * PCIe interrupt groups
- */
-enum al_pcie_int_group {
-	AL_PCIE_INT_GRP_A,
-	AL_PCIE_INT_GRP_B,
-	AL_PCIE_INT_GRP_C, /* Rev3 only */
-	AL_PCIE_INT_GRP_D, /* Rev3 only */
-	AL_PCIE_INT_GRP_AXI_A,
-};
-
-/**
- * App group A interrupts mask - don't change
- * All interrupts not listed below should be masked
- */
-enum al_pcie_app_int_grp_a {
-	/** [RC only] Deassert_INTD received */
-	AL_PCIE_APP_INT_DEASSERT_INTD = AL_BIT(0),
-	/** [RC only] Deassert_INTC received */
-	AL_PCIE_APP_INT_DEASSERT_INTC = AL_BIT(1),
-	/** [RC only] Deassert_INTB received */
-	AL_PCIE_APP_INT_DEASSERT_INTB = AL_BIT(2),
-	/**
-	 * [RC only] Deassert_INTA received - there's a didcated GIC interrupt
-	 * line that reflects the status of ASSERT/DEASSERT of INTA
-	 */
-	AL_PCIE_APP_INT_DEASSERT_INTA = AL_BIT(3),
-	/** [RC only] Assert_INTD received */
-	AL_PCIE_APP_INT_ASSERT_INTD = AL_BIT(4),
-	/** [RC only] Assert_INTC received */
-	AL_PCIE_APP_INT_ASSERT_INTC = AL_BIT(5),
-	/** [RC only] Assert_INTB received */
-	AL_PCIE_APP_INT_ASSERT_INTB = AL_BIT(6),
-	/**
-	 * [RC only] Assert_INTA received - there's a didcated GIC interrupt
-	 * line that reflects the status of ASSERT/DEASSERT of INTA
-	 */
-	AL_PCIE_APP_INT_ASSERT_INTA = AL_BIT(7),
-	/** [RC only] MSI Controller Interrupt */
-	AL_PCIE_APP_INT_MSI_CNTR_RCV_INT = AL_BIT(8),
-	/** [EP only] MSI sent grant */
-	AL_PCIE_APP_INT_MSI_TRNS_GNT = AL_BIT(9),
-	/** [RC only] System error detected  (ERR_COR, ERR_FATAL, ERR_NONFATAL) */
-	AL_PCIE_APP_INT_SYS_ERR_RC = AL_BIT(10),
-	/** [EP only] Software initiates FLR on a Physical Function */
-	AL_PCIE_APP_INT_FLR_PF_ACTIVE = AL_BIT(11),
-	/** [RC only] Root Error Command register assertion notification */
-	AL_PCIE_APP_INT_AER_RC_ERR = AL_BIT(12),
-	/** [RC only] Root Error Command register assertion notification With MSI or MSIX enabled */
-	AL_PCIE_APP_INT_AER_RC_ERR_MSI = AL_BIT(13),
-	/** [RC only] PME Status bit assertion in the Root Status register With INTA */
-	AL_PCIE_APP_INT_PME_INT = AL_BIT(15),
-	/** [RC only] PME Status bit assertion in the Root Status register With MSI or MSIX enabled */
-	AL_PCIE_APP_INT_PME_MSI = AL_BIT(16),
-	/** [RC/EP] The core assert link down event, whenever the link is going down */
-	AL_PCIE_APP_INT_LINK_DOWN = AL_BIT(21),
-	/** [EP only] When the EP gets a command to shut down, signal the software to block any new TLP. */
-	AL_PCIE_APP_INT_PM_XTLH_BLOCK_TLP = AL_BIT(22),
-	/** [RC/EP] PHY/MAC link up */
-	AL_PCIE_APP_INT_XMLH_LINK_UP = AL_BIT(23),
-	/** [RC/EP] Data link up */
-	AL_PCIE_APP_INT_RDLH_LINK_UP = AL_BIT(24),
-	/** [RC/EP] The LTSSM is in RCVRY_LOCK state. */
-	AL_PCIE_APP_INT_LTSSM_RCVRY_STATE = AL_BIT(25),
-	/**
-	 * [RC/EP] CFG write transaction to the configuration space by the RC peer
-	 * For RC the int/ will be set from DBI write (internal SoC write)]
-	 */
-	AL_PCIE_APP_INT_CFG_WR = AL_BIT(26),
-	/** [EP only] CFG access in EP mode */
-	AL_PCIE_APP_INT_CFG_ACCESS = AL_BIT(31),
-};
-
-/**
- * App group B interrupts mask - don't change
- * All interrupts not listed below should be masked
- */
-enum al_pcie_app_int_grp_b {
-	/** [RC only] PM_PME Message received */
-	AL_PCIE_APP_INT_GRP_B_PM_PME_MSG_RCVD = AL_BIT(0),
-	/** [RC only] PME_TO_Ack Message received */
-	AL_PCIE_APP_INT_GRP_B_PME_TO_ACK_MSG_RCVD = AL_BIT(1),
-	/** [EP only] PME_Turn_Off Message received */
-	AL_PCIE_APP_INT_GRP_B_PME_TURN_OFF_MSG_RCVD = AL_BIT(2),
-	/** [RC only] ERR_CORR Message received */
-	AL_PCIE_APP_INT_GRP_B_CORR_ERR_MSG_RCVD = AL_BIT(3),
-	/** [RC only] ERR_NONFATAL Message received */
-	AL_PCIE_APP_INT_GRP_B_NON_FTL_ERR_MSG_RCVD = AL_BIT(4),
-	/** [RC only] ERR_FATAL Message received */
-	AL_PCIE_APP_INT_GRP_B_FTL_ERR_MSG_RCVD = AL_BIT(5),
-	/**
-	 * [RC/EP] Vendor Defined Message received
-	 * Asserted when a vevdor message is received (with no data), buffers 2
-	 * messages only, and latch the headers in registers
-	 */
-	AL_PCIE_APP_INT_GRP_B_VNDR_MSG_A_RCVD = AL_BIT(6),
-	/**
-	 * [RC/EP] Vendor Defined Message received
-	 * Asserted when a vevdor message is received (with no data), buffers 2
-	 * messages only, and latch the headers in registers
-	 */
-	AL_PCIE_APP_INT_GRP_B_VNDR_MSG_B_RCVD = AL_BIT(7),
-	/** [EP only] Link Autonomous Bandwidth Status is updated */
-	AL_PCIE_APP_INT_GRP_B_LNK_BW_UPD = AL_BIT(12),
-	/** [EP only] Link Equalization Request bit in the Link Status 2 Register has been set */
-	AL_PCIE_APP_INT_GRP_B_LNK_EQ_REQ = AL_BIT(13),
-	/** [RC/EP] OB Vendor message request is granted by the PCIe core */
-	AL_PCIE_APP_INT_GRP_B_OB_VNDR_MSG_REQ_GRNT = AL_BIT(14),
-	/** [RC only] CPL timeout from the PCIe core indiication */
-	AL_PCIE_APP_INT_GRP_B_CPL_TO = AL_BIT(15),
-	/** [RC/EP] Slave Response Composer Lookup Error */
-	AL_PCIE_APP_INT_GRP_B_SLV_RESP_COMP_LKUP_ERR = AL_BIT(16),
-	/** [RC/EP] Parity Error */
-	AL_PCIE_APP_INT_GRP_B_PARITY_ERR = AL_BIT(17),
-	/** [EP only] Speed change request */
-	AL_PCIE_APP_INT_GRP_B_SPEED_CHANGE = AL_BIT(31),
-};
-
-/**
- * AXI interrupts mask - don't change
- * These are internal errors that can happen on the internal chip interface
- * between the PCIe port and the I/O Fabric over the AXI bus. The notion of
- * master and slave refer to the PCIe port master interface towards the I/O
- * Fabric (i.e. for inbound PCIe writes/reads toward the I/O Fabric), while the
- * slave interface refer to the I/O Fabric to PCIe port interface where the
- * internal chip DMAs and CPU cluster is initiating transactions.
- * All interrupts not listed below should be masked.
- */
-enum al_pcie_axi_int {
-	/** [RC/EP] Master Response Composer Lookup Error */
-	AL_PCIE_AXI_INT_MSTR_RESP_COMP_LKUP_ERR = AL_BIT(0),
-	/** [RC/EP] PARITY ERROR on the master data read channel */
-	AL_PCIE_AXI_INT_PARITY_ERR_MSTR_DATA_RD_CHNL = AL_BIT(2),
-	/** [RC/EP] PARITY ERROR on the slave addr read channel */
-	AL_PCIE_AXI_INT_PARITY_ERR_SLV_ADDR_RD_CHNL = AL_BIT(3),
-	/** [RC/EP] PARITY ERROR on the slave addr write channel */
-	AL_PCIE_AXI_INT_PARITY_ERR_SLV_ADDR_WR_CHNL = AL_BIT(4),
-	/** [RC/EP] PARITY ERROR on the slave data write channel */
-	AL_PCIE_AXI_INT_PARITY_ERR_SLV_DATA_WR_CHNL = AL_BIT(5),
-	/** [RC only] Software error: ECAM write request with invalid bus number */
-	AL_PCIE_AXI_INT_ECAM_WR_REQ_INVLD_BUS_NUM = AL_BIT(7),
-	/** [RC only] Software error: ECAM read request with invalid bus number */
-	AL_PCIE_AXI_INT_ECAM_RD_REQ_INVLD_BUS_NUM = AL_BIT(8),
-	/** [RC/EP] Read AXI completion has ERROR */
-	AL_PCIE_AXI_INT_RD_AXI_COMPL_ERR = AL_BIT(11),
-	/** [RC/EP] Write AXI completion has ERROR */
-	AL_PCIE_AXI_INT_WR_AXI_COMPL_ERR = AL_BIT(12),
-	/** [RC/EP] Read AXI completion has timed out */
-	AL_PCIE_AXI_INT_RD_AXI_COMPL_TO = AL_BIT(13),
-	/** [RC/EP] Write AXI completion has timed out */
-	AL_PCIE_AXI_INT_WR_AXI_COMPL_TO = AL_BIT(14),
-	/** [RC/EP] Parity error AXI domain */
-	AL_PCIE_AXI_INT_AXI_DOM_PARITY_ERR = AL_BIT(15),
-	/** [RC/EP] POS error interrupt */
-	AL_PCIE_AXI_INT_POS_ERR = AL_BIT(16),
-};
-
-/**
- * @brief   Initialize and configure PCIe controller interrupts
- * 	    Doesn't change the mask state of the interrupts
- * 	    The reset mask state of all interrupts is: Masked
- *
- * @param   pcie_port pcie port handle
- */
-void al_pcie_ints_config(struct al_pcie_port *pcie_port);
-
-/**
- * Unmask PCIe app group interrupts
- * @param  pcie_port pcie_port pcie port handle
- * @param  int_group interrupt group
- * @param  int_mask  int_mask interrupts to unmask ('1' to unmask)
- */
-void al_pcie_app_int_grp_unmask(
-	struct al_pcie_port *pcie_port,
-	enum al_pcie_int_group int_group,
-	uint32_t int_mask);
-
-/**
- * Mask PCIe app group interrupts
- * @param  pcie_port pcie_port pcie port handle
- * @param  int_group interrupt group
- * @param  int_mask  int_mask interrupts to unmask ('1' to mask)
- */
-void al_pcie_app_int_grp_mask(
-	struct al_pcie_port *pcie_port,
-	enum al_pcie_int_group int_group,
-	uint32_t int_mask);
-
-/**
- * Clear the PCIe app group interrupt cause
- * @param  pcie_port pcie port handle
- * @param  int_group interrupt group
- * @param  int_cause interrupt cause
- */
-void al_pcie_app_int_grp_cause_clear(
-	struct al_pcie_port *pcie_port,
-	enum al_pcie_int_group int_group,
-	uint32_t int_cause);
-
-/**
- * Read PCIe app group interrupt cause
- * @param  pcie_port pcie port handle
- * @param  int_group interrupt group
- * @return interrupt cause or 0 in case the group is not supported
- */
-uint32_t al_pcie_app_int_grp_cause_read(
-	struct al_pcie_port *pcie_port,
-	enum al_pcie_int_group int_group);
-
-#endif
-/** @} end of group_pcie_interrupts group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_pcie_regs.h b/sys/contrib/alpine-hal/eth/al_hal_pcie_regs.h
deleted file mode 100644
index 15c5735e279f..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_pcie_regs.h
+++ /dev/null
@@ -1,594 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#ifndef __AL_HAL_PCIE_REGS_H__
-#define __AL_HAL_PCIE_REGS_H__
-
-/* Note: Definitions before the includes so axi/wrapper regs sees them */
-
-/** Maximum physical functions supported */
-#define REV1_2_MAX_NUM_OF_PFS	1
-#define REV3_MAX_NUM_OF_PFS	4
-#define AL_MAX_NUM_OF_PFS	4 /* the maximum between all Revisions */
-
-#include "al_hal_pcie_axi_reg.h"
-#ifndef AL_PCIE_EX
-#include "al_hal_pcie_w_reg.h"
-#else
-#include "al_hal_pcie_w_reg_ex.h"
-#endif
-
-/**
- * Revision IDs:
- * ID_0: SlickRock M0
- * ID_1: SlickRock A0
- * ID_2: PeakRock  x4
- * ID_3: PeakRock  x8
- */
-#define AL_PCIE_REV_ID_0			0
-#define AL_PCIE_REV_ID_1			1
-#define AL_PCIE_REV_ID_2			2
-#define AL_PCIE_REV_ID_3			3
-
-#define AL_PCIE_AXI_REGS_OFFSET			0x0
-#define AL_PCIE_REV_1_2_APP_REGS_OFFSET		0x1000
-#define AL_PCIE_REV_3_APP_REGS_OFFSET		0x2000
-#define AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET	0x2000
-#define AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET	0x10000
-
-/** Maximum number of lanes supported */
-#define REV1_2_MAX_NUM_LANES	4
-#define REV3_MAX_NUM_LANES	8
-#define AL_MAX_NUM_OF_LANES	8 /* the maximum between all Revisions */
-
-struct al_pcie_core_iatu_regs {
-	uint32_t index;
-	uint32_t cr1;
-	uint32_t cr2;
-	uint32_t lower_base_addr;
-	uint32_t upper_base_addr;
-	uint32_t limit_addr;
-	uint32_t lower_target_addr;
-	uint32_t upper_target_addr;
-	uint32_t cr3;
-	uint32_t rsrvd[(0x270 - 0x224) >> 2];
-};
-
-struct al_pcie_core_port_regs {
-	uint32_t ack_lat_rply_timer;
-	uint32_t reserved1[(0x10 - 0x4) >> 2];
-	uint32_t port_link_ctrl;
-	uint32_t reserved2[(0x18 - 0x14) >> 2];
-	uint32_t timer_ctrl_max_func_num;
-	uint32_t filter_mask_reg_1;
-	uint32_t reserved3[(0x48 - 0x20) >> 2];
-	uint32_t vc0_posted_rcv_q_ctrl;
-	uint32_t vc0_non_posted_rcv_q_ctrl;
-	uint32_t vc0_comp_rcv_q_ctrl;
-	uint32_t reserved4[(0x10C - 0x54) >> 2];
-	uint32_t gen2_ctrl;
-	uint32_t reserved5[(0x190 - 0x110) >> 2];
-	uint32_t gen3_ctrl;
-	uint32_t gen3_eq_fs_lf;
-	uint32_t gen3_eq_preset_to_coef_map;
-	uint32_t gen3_eq_preset_idx;
-	uint32_t reserved6;
-	uint32_t gen3_eq_status;
-	uint32_t gen3_eq_ctrl;
-	uint32_t reserved7[(0x1B8 - 0x1AC) >> 2];
-	uint32_t pipe_loopback_ctrl;
-	uint32_t rd_only_wr_en;
-	uint32_t reserved8[(0x1D0 - 0x1C0) >> 2];
-	uint32_t axi_slave_err_resp;
-	uint32_t reserved9[(0x200 - 0x1D4) >> 2];
-	struct al_pcie_core_iatu_regs iatu;
-	uint32_t reserved10[(0x448 - 0x270) >> 2];
-};
-
-struct al_pcie_core_aer_regs {
-	/* 0x0 - PCI Express Extended Capability Header */
-	uint32_t header;
-	/* 0x4 - Uncorrectable Error Status Register */
-	uint32_t uncorr_err_stat;
-	/* 0x8 - Uncorrectable Error Mask Register */
-	uint32_t uncorr_err_mask;
-	/* 0xc - Uncorrectable Error Severity Register */
-	uint32_t uncorr_err_severity;
-	/* 0x10 - Correctable Error Status Register */
-	uint32_t corr_err_stat;
-	/* 0x14 - Correctable Error Mask Register */
-	uint32_t corr_err_mask;
-	/* 0x18 - Advanced Error Capabilities and Control Register */
-	uint32_t cap_and_ctrl;
-	/* 0x1c - Header Log Registers */
-	uint32_t header_log[4];
-	/* 0x2c - Root Error Command Register */
-	uint32_t root_err_cmd;
-	/* 0x30 - Root Error Status Register */
-	uint32_t root_err_stat;
-	/* 0x34 - Error Source Identification Register */
-	uint32_t err_src_id;
-};
-
-struct al_pcie_core_reg_space_rev_1_2 {
-	uint32_t			config_header[0x40 >> 2];
-	uint32_t			pcie_pm_cap_base;
-	uint32_t			reserved1[(0x70 - 0x44) >> 2];
-	uint32_t			pcie_cap_base;
-	uint32_t			pcie_dev_cap_base;
-	uint32_t			pcie_dev_ctrl_status;
-	uint32_t			pcie_link_cap_base;
-	uint32_t			reserved2[(0xB0 - 0x80) >> 2];
-	uint32_t			msix_cap_base;
-	uint32_t			reserved3[(0x100 - 0xB4) >> 2];
-	struct al_pcie_core_aer_regs	aer;
-	uint32_t			reserved4[(0x150 -
-						   (0x100 +
-						    sizeof(struct al_pcie_core_aer_regs))) >> 2];
-	uint32_t			pcie_sec_ext_cap_base;
-	uint32_t			reserved5[(0x700 - 0x154) >> 2];
-	struct al_pcie_core_port_regs	port_regs;
-	uint32_t			reserved6[(0x1000 -
-						   (0x700 +
-						    sizeof(struct al_pcie_core_port_regs))) >> 2];
-};
-
-struct al_pcie_core_reg_space_rev_3 {
-	uint32_t			config_header[0x40 >> 2];
-	uint32_t			pcie_pm_cap_base;
-	uint32_t			reserved1[(0x70 - 0x44) >> 2];
-	uint32_t			pcie_cap_base;
-	uint32_t			pcie_dev_cap_base;
-	uint32_t			pcie_dev_ctrl_status;
-	uint32_t			pcie_link_cap_base;
-	uint32_t			reserved2[(0xB0 - 0x80) >> 2];
-	uint32_t			msix_cap_base;
-	uint32_t			reserved3[(0x100 - 0xB4) >> 2];
-	struct al_pcie_core_aer_regs	aer;
-	uint32_t			reserved4[(0x158 -
-						   (0x100 +
-						    sizeof(struct al_pcie_core_aer_regs))) >> 2];
-	/* pcie_sec_cap is only applicable for function 0 */
-	uint32_t			pcie_sec_ext_cap_base;
-	uint32_t			reserved5[(0x178 - 0x15C) >> 2];
-	/* tph capability is only applicable for rev3 */
-	uint32_t			tph_cap_base;
-	uint32_t			reserved6[(0x700 - 0x17C) >> 2];
-	/* port_regs is only applicable for function 0 */
-	struct al_pcie_core_port_regs	port_regs;
-	uint32_t			reserved7[(0x1000 -
-						   (0x700 +
-						    sizeof(struct al_pcie_core_port_regs))) >> 2];
-};
-
-struct al_pcie_rev3_core_reg_space {
-	struct al_pcie_core_reg_space_rev_3 func[REV3_MAX_NUM_OF_PFS];
-};
-
-struct al_pcie_core_reg_space {
-	uint32_t			*config_header;
-	uint32_t			*pcie_pm_cap_base;
-	uint32_t			*pcie_cap_base;
-	uint32_t			*pcie_dev_cap_base;
-	uint32_t			*pcie_dev_ctrl_status;
-	uint32_t			*pcie_link_cap_base;
-	uint32_t			*msix_cap_base;
-	struct al_pcie_core_aer_regs	*aer;
-	uint32_t			*pcie_sec_ext_cap_base;
-	uint32_t			*tph_cap_base;
-};
-
-struct al_pcie_revx_regs {
-	struct al_pcie_revx_axi_regs __iomem	axi;
-};
-
-struct al_pcie_rev1_regs {
-	struct al_pcie_rev1_axi_regs __iomem	axi;
-	uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
-				(AL_PCIE_AXI_REGS_OFFSET +
-				sizeof(struct al_pcie_rev1_axi_regs))) >> 2];
-	struct al_pcie_rev1_w_regs __iomem	app;
-	uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
-				(AL_PCIE_REV_1_2_APP_REGS_OFFSET +
-				sizeof(struct al_pcie_rev1_w_regs))) >> 2];
-	struct al_pcie_core_reg_space_rev_1_2	core_space;
-};
-
-struct al_pcie_rev2_regs {
-	struct al_pcie_rev2_axi_regs __iomem	axi;
-	uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
-				(AL_PCIE_AXI_REGS_OFFSET +
-				sizeof(struct al_pcie_rev2_axi_regs))) >> 2];
-	struct al_pcie_rev2_w_regs __iomem	app;
-	uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
-				(AL_PCIE_REV_1_2_APP_REGS_OFFSET +
-				sizeof(struct al_pcie_rev2_w_regs))) >> 2];
-	struct al_pcie_core_reg_space_rev_1_2	core_space;
-};
-
-struct al_pcie_rev3_regs {
-	struct al_pcie_rev3_axi_regs __iomem	axi;
-	uint32_t reserved1[(AL_PCIE_REV_3_APP_REGS_OFFSET -
-				(AL_PCIE_AXI_REGS_OFFSET +
-				sizeof(struct al_pcie_rev3_axi_regs))) >> 2];
-	struct al_pcie_rev3_w_regs __iomem	app;
-	uint32_t reserved2[(AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET -
-				(AL_PCIE_REV_3_APP_REGS_OFFSET +
-				sizeof(struct al_pcie_rev3_w_regs))) >> 2];
-	struct al_pcie_rev3_core_reg_space	core_space;
-};
-
-struct al_pcie_axi_ctrl {
-	uint32_t *global;
-	uint32_t *master_arctl;
-	uint32_t *master_awctl;
-	uint32_t *slv_ctl;
-};
-
-struct al_pcie_axi_ob_ctrl {
-	uint32_t *cfg_target_bus;
-	uint32_t *cfg_control;
-	uint32_t *io_start_l;
-	uint32_t *io_start_h;
-	uint32_t *io_limit_l;
-	uint32_t *io_limit_h;
-};
-
-struct al_pcie_axi_pcie_global {
-	uint32_t *conf;
-};
-
-struct al_pcie_axi_conf {
-	uint32_t *zero_lane0;
-	uint32_t *zero_lane1;
-	uint32_t *zero_lane2;
-	uint32_t *zero_lane3;
-	uint32_t *zero_lane4;
-	uint32_t *zero_lane5;
-	uint32_t *zero_lane6;
-	uint32_t *zero_lane7;
-};
-
-struct al_pcie_axi_status {
-	uint32_t *lane[AL_MAX_NUM_OF_LANES];
-};
-
-struct al_pcie_axi_parity {
-	uint32_t *en_axi;
-};
-
-struct al_pcie_axi_ordering {
-	uint32_t *pos_cntl;
-};
-
-struct al_pcie_axi_pre_configuration {
-	uint32_t *pcie_core_setup;
-};
-
-struct al_pcie_axi_init_fc {
-	uint32_t *cfg;
-};
-
-struct al_pcie_axi_attr_ovrd {
-	uint32_t *write_msg_ctrl_0;
-	uint32_t *write_msg_ctrl_1;
-	uint32_t *pf_sel;
-};
-
-struct al_pcie_axi_pf_axi_attr_ovrd {
-	uint32_t *func_ctrl_0;
-	uint32_t *func_ctrl_1;
-	uint32_t *func_ctrl_2;
-	uint32_t *func_ctrl_3;
-	uint32_t *func_ctrl_4;
-	uint32_t *func_ctrl_5;
-	uint32_t *func_ctrl_6;
-	uint32_t *func_ctrl_7;
-	uint32_t *func_ctrl_8;
-	uint32_t *func_ctrl_9;
-};
-
-struct al_pcie_axi_msg_attr_axuser_table {
-	uint32_t *entry_vec;
-};
-
-struct al_pcie_axi_regs {
-	struct al_pcie_axi_ctrl ctrl;
-	struct al_pcie_axi_ob_ctrl ob_ctrl;
-	struct al_pcie_axi_pcie_global pcie_global;
-	struct al_pcie_axi_conf conf;
-	struct al_pcie_axi_status status;
-	struct al_pcie_axi_parity parity;
-	struct al_pcie_axi_ordering ordering;
-	struct al_pcie_axi_pre_configuration pre_configuration;
-	struct al_pcie_axi_init_fc init_fc;
-	struct al_pcie_revx_axi_int_grp_a_axi *int_grp_a;
-	/* Rev3 only */
-	struct al_pcie_axi_attr_ovrd axi_attr_ovrd;
-	struct al_pcie_axi_pf_axi_attr_ovrd pf_axi_attr_ovrd[REV3_MAX_NUM_OF_PFS];
-	struct al_pcie_axi_msg_attr_axuser_table msg_attr_axuser_table;
-};
-
-struct al_pcie_w_global_ctrl {
-	uint32_t *port_init;
-	uint32_t *pm_control;
-	uint32_t *events_gen[REV3_MAX_NUM_OF_PFS];
-	uint32_t *corr_err_sts_int;
-	uint32_t *uncorr_err_sts_int;
-	uint32_t *sris_kp_counter;
-};
-
-struct al_pcie_w_soc_int {
-	uint32_t *mask_inta_leg_0;
-	uint32_t *mask_inta_leg_3; /* Rev 2/3 only */
-	uint32_t *mask_msi_leg_0;
-	uint32_t *mask_msi_leg_3; /* Rev 2/3 only */
-};
-struct al_pcie_w_atu {
-	uint32_t *in_mask_pair;
-	uint32_t *out_mask_pair;
-};
-
-struct al_pcie_w_regs {
-	struct al_pcie_w_global_ctrl		global_ctrl;
-	struct al_pcie_revx_w_debug		*debug;
-	struct al_pcie_revx_w_ap_user_send_msg	*ap_user_send_msg;
-	struct al_pcie_w_soc_int		soc_int[REV3_MAX_NUM_OF_PFS];
-	struct al_pcie_revx_w_cntl_gen		*ctrl_gen;
-	struct al_pcie_revx_w_parity		*parity;
-	struct al_pcie_w_atu			atu;
-	struct al_pcie_revx_w_status_per_func	*status_per_func[REV3_MAX_NUM_OF_PFS];
-	struct al_pcie_revx_w_int_grp		*int_grp_a;
-	struct al_pcie_revx_w_int_grp		*int_grp_b;
-	struct al_pcie_revx_w_int_grp		*int_grp_c;
-	struct al_pcie_revx_w_int_grp		*int_grp_d;
-};
-
-struct al_pcie_regs {
-	struct al_pcie_axi_regs		axi;
-	struct al_pcie_w_regs		app;
-	struct al_pcie_core_port_regs	*port_regs;
-	struct al_pcie_core_reg_space	core_space[REV3_MAX_NUM_OF_PFS];
-};
-
-#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_EP	0
-#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_RC	4
-
-#define PCIE_PORT_GEN2_CTRL_DIRECT_SPEED_CHANGE		AL_BIT(17)
-#define PCIE_PORT_GEN2_CTRL_TX_SWING_LOW_SHIFT		18
-#define PCIE_PORT_GEN2_CTRL_TX_COMPLIANCE_RCV_SHIFT	19
-#define PCIE_PORT_GEN2_CTRL_DEEMPHASIS_SET_SHIFT	20
-#define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_MASK		AL_FIELD_MASK(12, 8)
-#define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_SHIFT		8
-
-#define PCIE_PORT_GEN3_CTRL_EQ_PHASE_2_3_DISABLE_SHIFT	9
-#define PCIE_PORT_GEN3_CTRL_EQ_DISABLE_SHIFT		16
-
-#define PCIE_PORT_GEN3_EQ_LF_SHIFT			0
-#define PCIE_PORT_GEN3_EQ_LF_MASK			0x3f
-#define PCIE_PORT_GEN3_EQ_FS_SHIFT			6
-#define PCIE_PORT_GEN3_EQ_FS_MASK			(0x3f << PCIE_PORT_GEN3_EQ_FS_SHIFT)
-
-#define PCIE_PORT_LINK_CTRL_LB_EN_SHIFT			2
-#define PCIE_PORT_LINK_CTRL_FAST_LINK_EN_SHIFT		7
-#define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_MASK		AL_FIELD_MASK(21, 16)
-#define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT		16
-
-#define PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT	31
-
-#define PCIE_PORT_AXI_SLAVE_ERR_RESP_ALL_MAPPING_SHIFT	0
-
-/** timer_ctrl_max_func_num register
- * Max physical function number (for example: 0 for 1PF, 3 for 4PFs)
- */
-#define PCIE_PORT_GEN3_MAX_FUNC_NUM			AL_FIELD_MASK(7, 0)
-
-/* filter_mask_reg_1 register */
-/**
- * SKP Interval Value.
- * The number of symbol times to wait between transmitting SKP ordered sets
- */
-#define PCIE_FLT_MASK_SKP_INT_VAL_MASK			AL_FIELD_MASK(10, 0)
-
-/*
- * 0: Treat Function MisMatched TLPs as UR
- * 1: Treat Function MisMatched TLPs as Supported
- */
-#define CX_FLT_MASK_UR_FUNC_MISMATCH			AL_BIT(16)
-
-/*
- * 0: Treat CFG type1 TLPs as UR for EP; Supported for RC
- * 1: Treat CFG type1 TLPs as Supported for EP; UR for RC
- */
-#define CX_FLT_MASK_CFG_TYPE1_RE_AS_UR			AL_BIT(19)
-
-/*
- * 0: Enforce requester id match for received CPL TLPs.
- *    A violation results in cpl_abort, and possibly AER of unexp_cpl_err,
- *    cpl_rcvd_ur, cpl_rcvd_ca
- * 1: Mask requester id match for received CPL TLPs
- */
-#define CX_FLT_MASK_CPL_REQID_MATCH			AL_BIT(22)
-
-/*
- * 0: Enforce function match for received CPL TLPs.
- *    A violation results in cpl_abort, and possibly AER of unexp_cpl_err,
- *    cpl_rcvd_ur, cpl_rcvd_ca
- * 1: Mask function match for received CPL TLPs
- */
-#define CX_FLT_MASK_CPL_FUNC_MATCH			AL_BIT(23)
-
-/* vc0_posted_rcv_q_ctrl register */
-#define RADM_PQ_HCRD_VC0_MASK				AL_FIELD_MASK(19, 12)
-#define RADM_PQ_HCRD_VC0_SHIFT				12
-
-/* vc0_non_posted_rcv_q_ctrl register */
-#define RADM_NPQ_HCRD_VC0_MASK				AL_FIELD_MASK(19, 12)
-#define RADM_NPQ_HCRD_VC0_SHIFT				12
-
-/* vc0_comp_rcv_q_ctrl register */
-#define RADM_CPLQ_HCRD_VC0_MASK				AL_FIELD_MASK(19, 12)
-#define RADM_CPLQ_HCRD_VC0_SHIFT			12
-
-/**** iATU, Control Register 1 ****/
-
-/**
- * When the Address and BAR matching logic in the core indicate that a MEM-I/O
- * transaction matches a BAR in the function corresponding to this value, then
- * address translation proceeds. This check is only performed if the "Function
- * Number Match Enable" bit of the "iATU Control 2 Register" is set
- */
-#define PCIE_IATU_CR1_FUNC_NUM_MASK			AL_FIELD_MASK(24, 20)
-#define PCIE_IATU_CR1_FUNC_NUM_SHIFT			20
-
-/**** iATU, Control Register 2 ****/
-/** For outbound regions, the Function Number Translation Bypass mode enables
- *  taking the function number of the translated TLP from the PCIe core
- *  interface and not from the "Function Number" field of CR1.
- *  For inbound regions, this bit should be asserted when physical function
- *  match mode needs to be enabled
- */
-#define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_MASK	AL_BIT(19)
-#define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_SHIFT	19
-
-/* pcie_dev_ctrl_status register */
-#define PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN	AL_BIT(0)
-#define PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN	AL_BIT(1)
-#define PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN	AL_BIT(2)
-#define PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN	AL_BIT(3)
-
-#define PCIE_PORT_DEV_CTRL_STATUS_MPS_MASK		AL_FIELD_MASK(7, 5)
-#define PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT		5
-#define PCIE_PORT_DEV_CTRL_STATUS_MPS_VAL_256		(1 << PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT)
-
-#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_MASK		AL_FIELD_MASK(14, 12)
-#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT		12
-#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_VAL_256		(1 << PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT)
-
-/******************************************************************************
- * AER registers
- ******************************************************************************/
-/* PCI Express Extended Capability ID */
-#define PCIE_AER_CAP_ID_MASK			AL_FIELD_MASK(15, 0)
-#define PCIE_AER_CAP_ID_SHIFT			0
-#define PCIE_AER_CAP_ID_VAL			1
-/* Capability Version */
-#define PCIE_AER_CAP_VER_MASK			AL_FIELD_MASK(19, 16)
-#define PCIE_AER_CAP_VER_SHIFT			16
-#define PCIE_AER_CAP_VER_VAL			2
-
-/* First Error Pointer */
-#define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_MASK		AL_FIELD_MASK(4, 0)
-#define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_SHIFT		0
-/* ECRC Generation Capability */
-#define PCIE_AER_CTRL_STAT_ECRC_GEN_SUPPORTED		AL_BIT(5)
-/* ECRC Generation Enable */
-#define PCIE_AER_CTRL_STAT_ECRC_GEN_EN			AL_BIT(6)
-/* ECRC Check Capable */
-#define PCIE_AER_CTRL_STAT_ECRC_CHK_SUPPORTED		AL_BIT(7)
-/* ECRC Check Enable */
-#define PCIE_AER_CTRL_STAT_ECRC_CHK_EN			AL_BIT(8)
-
-/* Correctable Error Reporting Enable */
-#define PCIE_AER_ROOT_ERR_CMD_CORR_ERR_RPRT_EN		AL_BIT(0)
-/* Non-Fatal Error Reporting Enable */
-#define PCIE_AER_ROOT_ERR_CMD_NON_FTL_ERR_RPRT_EN	AL_BIT(1)
-/* Fatal Error Reporting Enable */
-#define PCIE_AER_ROOT_ERR_CMD_FTL_ERR_RPRT_EN		AL_BIT(2)
-
-/* ERR_COR Received */
-#define PCIE_AER_ROOT_ERR_STAT_CORR_ERR			AL_BIT(0)
-/* Multiple ERR_COR Received */
-#define PCIE_AER_ROOT_ERR_STAT_CORR_ERR_MULTI		AL_BIT(1)
-/* ERR_FATAL/NONFATAL Received */
-#define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR		AL_BIT(2)
-/* Multiple ERR_FATAL/NONFATAL Received */
-#define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR_MULTI	AL_BIT(3)
-/* First Uncorrectable Fatal */
-#define PCIE_AER_ROOT_ERR_STAT_FIRST_UNCORR_FTL		AL_BIT(4)
-/* Non-Fatal Error Messages Received */
-#define PCIE_AER_ROOT_ERR_STAT_NON_FTL_RCVD		AL_BIT(5)
-/* Fatal Error Messages Received */
-#define PCIE_AER_ROOT_ERR_STAT_FTL_RCVD			AL_BIT(6)
-/* Advanced Error Interrupt Message Number */
-#define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_MASK	AL_FIELD_MASK(31, 27)
-#define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_SHIFT	27
-
-/* ERR_COR Source Identification */
-#define PCIE_AER_SRC_ID_CORR_ERR_MASK			AL_FIELD_MASK(15, 0)
-#define PCIE_AER_SRC_ID_CORR_ERR_SHIFT			0
-/* ERR_FATAL/NONFATAL Source Identification */
-#define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_MASK	AL_FIELD_MASK(31, 16)
-#define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_SHIFT	16
-
-/* AER message */
-#define PCIE_AER_MSG_REQID_MASK				AL_FIELD_MASK(31, 16)
-#define PCIE_AER_MSG_REQID_SHIFT			16
-#define PCIE_AER_MSG_TYPE_MASK				AL_FIELD_MASK(15, 8)
-#define PCIE_AER_MSG_TYPE_SHIFT				8
-#define PCIE_AER_MSG_RESERVED				AL_FIELD_MASK(7, 1)
-#define PCIE_AER_MSG_VALID				AL_BIT(0)
-/* AER message ack */
-#define PCIE_AER_MSG_ACK				AL_BIT(0)
-/* AER errors definitions */
-#define AL_PCIE_AER_TYPE_CORR				(0x30)
-#define AL_PCIE_AER_TYPE_NON_FATAL			(0x31)
-#define AL_PCIE_AER_TYPE_FATAL				(0x33)
-/* Requester ID Bus */
-#define AL_PCIE_REQID_BUS_NUM_SHIFT			(8)
-
-/******************************************************************************
- * TPH registers
- ******************************************************************************/
-#define PCIE_TPH_NEXT_POINTER				AL_FIELD_MASK(31, 20)
-
-/******************************************************************************
- * Config Header registers
- ******************************************************************************/
-/**
- * see BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG in core spec
- * Note: valid only for EP mode
- */
-#define PCIE_BIST_HEADER_TYPE_BASE		0xc
-#define PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK	AL_BIT(23)
-
-/******************************************************************************
- * SRIS KP counters default values
- ******************************************************************************/
-#define PCIE_SRIS_KP_COUNTER_GEN3_DEFAULT_VAL	(0x24)
-#define PCIE_SRIS_KP_COUNTER_GEN21_DEFAULT_VAL	(0x4B)
-
-#endif
diff --git a/sys/contrib/alpine-hal/eth/al_hal_pcie_w_reg.h b/sys/contrib/alpine-hal/eth/al_hal_pcie_w_reg.h
deleted file mode 100644
index 44e9d952655d..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_pcie_w_reg.h
+++ /dev/null
@@ -1,1505 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-
-#ifndef __AL_HAL_PCIE_W_REG_H__
-#define __AL_HAL_PCIE_W_REG_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-
-
-struct al_pcie_rev1_w_global_ctrl {
-	/* [0x0]  */
-	uint32_t port_init;
-	/* [0x4]  */
-	uint32_t port_status;
-	/* [0x8]  */
-	uint32_t pm_control;
-	uint32_t rsrvd_0;
-	/* [0x10]  */
-	uint32_t events_gen;
-	uint32_t rsrvd[3];
-};
-struct al_pcie_rev2_w_global_ctrl {
-	/* [0x0]  */
-	uint32_t port_init;
-	/* [0x4]  */
-	uint32_t port_status;
-	/* [0x8]  */
-	uint32_t pm_control;
-	uint32_t rsrvd_0;
-	/* [0x10]  */
-	uint32_t events_gen;
-	/* [0x14]  */
-	uint32_t pended_corr_err_sts_int;
-	/* [0x18]  */
-	uint32_t pended_uncorr_err_sts_int;
-	/* [0x1c]  */
-	uint32_t sris_kp_counter_value;
-};
-struct al_pcie_rev3_w_global_ctrl {
-	/* [0x0]  */
-	uint32_t port_init;
-	/* [0x4]  */
-	uint32_t port_status;
-	/* [0x8]  */
-	uint32_t pm_control;
-	/* [0xc]  */
-	uint32_t pended_corr_err_sts_int;
-	/* [0x10]  */
-	uint32_t pended_uncorr_err_sts_int;
-	/* [0x14]  */
-	uint32_t sris_kp_counter_value;
-	uint32_t rsrvd[2];
-};
-
-struct al_pcie_rev3_w_events_gen_per_func {
-	/* [0x0]  */
-	uint32_t events_gen;
-};
-struct al_pcie_rev3_w_pm_state_per_func {
-	/* [0x0]  */
-	uint32_t pm_state_per_func;
-};
-struct al_pcie_rev3_w_cfg_bars_ovrd {
-	/* [0x0]  */
-	uint32_t bar0_mask_lsb;
-	/* [0x4]  */
-	uint32_t bar0_mask_msb;
-	/* [0x8]  */
-	uint32_t bar0_limit_lsb;
-	/* [0xc]  */
-	uint32_t bar0_limit_msb;
-	/* [0x10]  */
-	uint32_t bar0_start_lsb;
-	/* [0x14]  */
-	uint32_t bar0_start_msb;
-	/* [0x18]  */
-	uint32_t bar0_ctrl;
-	/* [0x1c]  */
-	uint32_t bar1_mask_lsb;
-	/* [0x20]  */
-	uint32_t bar1_mask_msb;
-	/* [0x24]  */
-	uint32_t bar1_limit_lsb;
-	/* [0x28]  */
-	uint32_t bar1_limit_msb;
-	/* [0x2c]  */
-	uint32_t bar1_start_lsb;
-	/* [0x30]  */
-	uint32_t bar1_start_msb;
-	/* [0x34]  */
-	uint32_t bar1_ctrl;
-	/* [0x38]  */
-	uint32_t bar2_mask_lsb;
-	/* [0x3c]  */
-	uint32_t bar2_mask_msb;
-	/* [0x40]  */
-	uint32_t bar2_limit_lsb;
-	/* [0x44]  */
-	uint32_t bar2_limit_msb;
-	/* [0x48]  */
-	uint32_t bar2_start_lsb;
-	/* [0x4c]  */
-	uint32_t bar2_start_msb;
-	/* [0x50]  */
-	uint32_t bar2_ctrl;
-	/* [0x54]  */
-	uint32_t bar3_mask_lsb;
-	/* [0x58]  */
-	uint32_t bar3_mask_msb;
-	/* [0x5c]  */
-	uint32_t bar3_limit_lsb;
-	/* [0x60]  */
-	uint32_t bar3_limit_msb;
-	/* [0x64]  */
-	uint32_t bar3_start_lsb;
-	/* [0x68]  */
-	uint32_t bar3_start_msb;
-	/* [0x6c]  */
-	uint32_t bar3_ctrl;
-	/* [0x70]  */
-	uint32_t bar4_mask_lsb;
-	/* [0x74]  */
-	uint32_t bar4_mask_msb;
-	/* [0x78]  */
-	uint32_t bar4_limit_lsb;
-	/* [0x7c]  */
-	uint32_t bar4_limit_msb;
-	/* [0x80]  */
-	uint32_t bar4_start_lsb;
-	/* [0x84]  */
-	uint32_t bar4_start_msb;
-	/* [0x88]  */
-	uint32_t bar4_ctrl;
-	/* [0x8c]  */
-	uint32_t bar5_mask_lsb;
-	/* [0x90]  */
-	uint32_t bar5_mask_msb;
-	/* [0x94]  */
-	uint32_t bar5_limit_lsb;
-	/* [0x98]  */
-	uint32_t bar5_limit_msb;
-	/* [0x9c]  */
-	uint32_t bar5_start_lsb;
-	/* [0xa0]  */
-	uint32_t bar5_start_msb;
-	/* [0xa4]  */
-	uint32_t bar5_ctrl;
-	uint32_t rsrvd[2];
-};
-
-struct al_pcie_revx_w_debug {
-	/* [0x0]  */
-	uint32_t info_0;
-	/* [0x4]  */
-	uint32_t info_1;
-	/* [0x8]  */
-	uint32_t info_2;
-	/* [0xc]  */
-	uint32_t info_3;
-};
-struct al_pcie_revx_w_ob_ven_msg {
-	/* [0x0]  */
-	uint32_t control;
-	/* [0x4]  */
-	uint32_t param_1;
-	/* [0x8]  */
-	uint32_t param_2;
-	/* [0xc]  */
-	uint32_t data_high;
-	uint32_t rsrvd_0;
-	/* [0x14]  */
-	uint32_t data_low;
-};
-struct al_pcie_revx_w_ap_user_send_msg {
-	/* [0x0]  */
-	uint32_t req_info;
-	/* [0x4]  */
-	uint32_t ack_info;
-};
-struct al_pcie_revx_w_link_down {
-	/* [0x0]  */
-	uint32_t reset_delay;
-	/* [0x4]  */
-	uint32_t reset_extend_rsrvd;
-};
-struct al_pcie_revx_w_cntl_gen {
-	/* [0x0]  */
-	uint32_t features;
-};
-struct al_pcie_revx_w_parity {
-	/* [0x0]  */
-	uint32_t en_core;
-	/* [0x4]  */
-	uint32_t status_core;
-};
-struct al_pcie_revx_w_last_wr {
-	/* [0x0]  */
-	uint32_t cfg_addr;
-};
-struct al_pcie_rev1_2_w_atu {
-	/* [0x0]  */
-	uint32_t in_mask_pair[6];
-	/* [0x18]  */
-	uint32_t out_mask_pair[6];
-};
-struct al_pcie_rev3_w_atu {
-	/* [0x0]  */
-	uint32_t in_mask_pair[12];
-	/* [0x30]  */
-	uint32_t out_mask_pair[8];
-	/* [0x50] */
-	uint32_t reg_out_mask;
-	uint32_t rsrvd[11];
-};
-struct al_pcie_rev3_w_cfg_func_ext {
-	/* [0x0]  */
-	uint32_t cfg;
-};
-struct al_pcie_rev3_w_app_hdr_interface_send {
-	/* [0x0]  */
-	uint32_t app_hdr_31_0;
-	/* [0x4]  */
-	uint32_t app_hdr_63_32;
-	/* [0x8]  */
-	uint32_t app_hdr_95_64;
-	/* [0xc]  */
-	uint32_t app_hdr_127_96;
-	/* [0x10]  */
-	uint32_t app_err_bus;
-	/* [0x14]  */
-	uint32_t app_func_num_advisory;
-	/* [0x18]  */
-	uint32_t app_hdr_cmd;
-};
-struct al_pcie_rev3_w_diag_command {
-	/* [0x0]  */
-	uint32_t diag_ctrl;
-};
-struct al_pcie_rev1_w_soc_int {
-	/* [0x0]  */
-	uint32_t status_0;
-	/* [0x4]  */
-	uint32_t status_1;
-	/* [0x8]  */
-	uint32_t status_2;
-	/* [0xc]  */
-	uint32_t mask_inta_leg_0;
-	/* [0x10]  */
-	uint32_t mask_inta_leg_1;
-	/* [0x14]  */
-	uint32_t mask_inta_leg_2;
-	/* [0x18]  */
-	uint32_t mask_msi_leg_0;
-	/* [0x1c]  */
-	uint32_t mask_msi_leg_1;
-	/* [0x20]  */
-	uint32_t mask_msi_leg_2;
-	/* [0x24]  */
-	uint32_t msi_leg_cntl;
-};
-struct al_pcie_rev2_w_soc_int {
-	/* [0x0]  */
-	uint32_t status_0;
-	/* [0x4]  */
-	uint32_t status_1;
-	/* [0x8]  */
-	uint32_t status_2;
-	/* [0xc]  */
-	uint32_t status_3;
-	/* [0x10]  */
-	uint32_t mask_inta_leg_0;
-	/* [0x14]  */
-	uint32_t mask_inta_leg_1;
-	/* [0x18]  */
-	uint32_t mask_inta_leg_2;
-	/* [0x1c]  */
-	uint32_t mask_inta_leg_3;
-	/* [0x20]  */
-	uint32_t mask_msi_leg_0;
-	/* [0x24]  */
-	uint32_t mask_msi_leg_1;
-	/* [0x28]  */
-	uint32_t mask_msi_leg_2;
-	/* [0x2c]  */
-	uint32_t mask_msi_leg_3;
-	/* [0x30]  */
-	uint32_t msi_leg_cntl;
-};
-struct al_pcie_rev3_w_soc_int_per_func {
-	/* [0x0]  */
-	uint32_t status_0;
-	/* [0x4]  */
-	uint32_t status_1;
-	/* [0x8]  */
-	uint32_t status_2;
-	/* [0xc]  */
-	uint32_t status_3;
-	/* [0x10]  */
-	uint32_t mask_inta_leg_0;
-	/* [0x14]  */
-	uint32_t mask_inta_leg_1;
-	/* [0x18]  */
-	uint32_t mask_inta_leg_2;
-	/* [0x1c]  */
-	uint32_t mask_inta_leg_3;
-	/* [0x20]  */
-	uint32_t mask_msi_leg_0;
-	/* [0x24]  */
-	uint32_t mask_msi_leg_1;
-	/* [0x28]  */
-	uint32_t mask_msi_leg_2;
-	/* [0x2c]  */
-	uint32_t mask_msi_leg_3;
-	/* [0x30]  */
-	uint32_t msi_leg_cntl;
-};
-
-struct al_pcie_revx_w_ap_err {
-	/*
-	 * [0x0] latch the header in case of any error occur in the core, read
-	 * on clear of the last register in the bind.
-	 */
-	uint32_t hdr_log;
-};
-struct al_pcie_revx_w_status_per_func {
-	/*
-	 * [0x0] latch the header in case of any error occure in the core, read
-	 * on clear of the last register in the bind.
-	 */
-	uint32_t status_per_func;
-};
-struct al_pcie_revx_w_int_grp {
-	/*
-	 * [0x0] Interrupt Cause Register
-	 * Set by hardware
-	 * - If MSI-X is enabled and auto_clear control bit =TRUE, automatically
-	 * cleared after MSI-X message associated with this specific interrupt
-	 * bit is sent (MSI-X acknowledge is received).
-	 * - Software can set a bit in this register by writing 1 to the
-	 * associated bit in the Interrupt Cause Set register
-	 * Write-0 clears a bit. Write-1 has no effect.
-	 * - On CPU Read - If clear_on_read control bit =TRUE, automatically
-	 * cleared (all bits are cleared).
-	 * When there is a conflict and on the same clock cycle, hardware tries
-	 * to set a bit in the Interrupt Cause register, the specific bit is set
-	 * to ensure the interrupt indication is not lost.
-	 */
-	uint32_t cause;
-	uint32_t rsrvd_0;
-	/*
-	 * [0x8] Interrupt Cause Set Register
-	 * Writing 1 to a bit in this register sets its corresponding cause bit,
-	 * enabling software to generate a hardware interrupt. Write 0 has no
-	 * effect.
-	 */
-	uint32_t cause_set;
-	uint32_t rsrvd_1;
-	/*
-	 * [0x10] Interrupt Mask Register
-	 * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X
-	 * message associatd with the associated interrupt bit is sent (AXI
-	 * write acknowledge is received).
-	 */
-	uint32_t mask;
-	uint32_t rsrvd_2;
-	/*
-	 * [0x18] Interrupt Mask Clear Register
-	 * Used when auto-mask control bit=True. Enables CPU to clear a specific
-	 * bit. It prevents a scenario in which the CPU overrides another bit
-	 * with 1 (old value) that hardware has just cleared to 0.
-	 * Write 0 to this register clears its corresponding mask bit. Write 1
-	 * has no effect.
-	 */
-	uint32_t mask_clear;
-	uint32_t rsrvd_3;
-	/*
-	 * [0x20] Interrupt Status Register
-	 * This register latches the status of the interrupt source.
-	 */
-	uint32_t status;
-	uint32_t rsrvd_4;
-	/* [0x28] Interrupt Control Register */
-	uint32_t control;
-	uint32_t rsrvd_5;
-	/*
-	 * [0x30] Interrupt Mask Register
-	 * Each bit in this register masks the corresponding cause bit for
-	 * generating an Abort signal. Its default value is determined by unit
-	 * instantiation.
-	 * (Abort = Wire-OR of Cause & !Interrupt_Abort_Mask)
-	 * This register provides error handling configuration for error
-	 * interrupts
-	 */
-	uint32_t abort_mask;
-	uint32_t rsrvd_6;
-	/*
-	 * [0x38] Interrupt Log Register
-	 * Each bit in this register masks the corresponding cause bit for
-	 * capturing the log registers. Its default value is determined by unit
-	 * instantiation.
-	 * (Log_capture = Wire-OR of Cause & !Interrupt_Log_Mask)
-	 * This register provides error handling configuration for error
-	 * interrupts.
-	 */
-	uint32_t log_mask;
-	uint32_t rsrvd;
-};
-
-struct al_pcie_rev1_w_regs {
-	struct al_pcie_rev1_w_global_ctrl global_ctrl;     /* [0x0] */
-	uint32_t rsrvd_0[24];
-	struct al_pcie_revx_w_debug debug;                     /* [0x80] */
-	struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */
-	uint32_t rsrvd_1[86];
-	struct al_pcie_rev1_w_soc_int soc_int;                 /* [0x200] */
-	struct al_pcie_revx_w_link_down link_down;             /* [0x228] */
-	struct al_pcie_revx_w_cntl_gen ctrl_gen;               /* [0x230] */
-	struct al_pcie_revx_w_parity parity;                   /* [0x234] */
-	struct al_pcie_revx_w_last_wr last_wr;                 /* [0x23c] */
-	struct al_pcie_rev1_2_w_atu atu;                         /* [0x240] */
-	uint32_t rsrvd_2[36];
-	struct al_pcie_revx_w_int_grp int_grp_a_m0; /* [0x300] */
-	struct al_pcie_revx_w_int_grp int_grp_b_m0; /* [0x340] */
-	uint32_t rsrvd_3[32];
-	struct al_pcie_revx_w_int_grp int_grp_a; /* [0x400] */
-	struct al_pcie_revx_w_int_grp int_grp_b; /* [0x440] */
-};
-
-struct al_pcie_rev2_w_regs {
-	struct al_pcie_rev2_w_global_ctrl global_ctrl;     /* [0x0] */
-	uint32_t rsrvd_0[24];
-	struct al_pcie_revx_w_debug debug;                     /* [0x80] */
-	struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */
-	struct al_pcie_revx_w_ap_user_send_msg ap_user_send_msg; /* [0xa8] */
-	uint32_t rsrvd_1[20];
-	struct al_pcie_rev2_w_soc_int soc_int;                 /* [0x100] */
-	uint32_t rsrvd_2[61];
-	struct al_pcie_revx_w_link_down link_down;             /* [0x228] */
-	struct al_pcie_revx_w_cntl_gen ctrl_gen;               /* [0x230] */
-	struct al_pcie_revx_w_parity parity;                   /* [0x234] */
-	struct al_pcie_revx_w_last_wr last_wr;                 /* [0x23c] */
-	struct al_pcie_rev1_2_w_atu atu;                         /* [0x240] */
-	uint32_t rsrvd_3[6];
-	struct al_pcie_revx_w_ap_err ap_err[4];             /* [0x288] */
-	uint32_t rsrvd_4[26];
-	struct al_pcie_revx_w_status_per_func status_per_func; /* [0x300] */
-	uint32_t rsrvd_5[63];
-	struct al_pcie_revx_w_int_grp int_grp_a; /* [0x400] */
-	struct al_pcie_revx_w_int_grp int_grp_b; /* [0x440] */
-};
-
-struct al_pcie_rev3_w_regs {
-	struct al_pcie_rev3_w_global_ctrl global_ctrl;     /* [0x0] */
-	uint32_t rsrvd_0[24];
-	struct al_pcie_revx_w_debug debug;                     /* [0x80] */
-	struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */
-	struct al_pcie_revx_w_ap_user_send_msg ap_user_send_msg; /* [0xa8] */
-	uint32_t rsrvd_1[94];
-	struct al_pcie_revx_w_link_down link_down;             /* [0x228] */
-	struct al_pcie_revx_w_cntl_gen ctrl_gen;               /* [0x230] */
-	struct al_pcie_revx_w_parity parity;                   /* [0x234] */
-	struct al_pcie_revx_w_last_wr last_wr;                 /* [0x23c] */
-	struct al_pcie_rev3_w_atu atu;                         /* [0x240] */
-	uint32_t rsrvd_2[8];
-	struct al_pcie_rev3_w_cfg_func_ext cfg_func_ext;    /* [0x2e0] */
-	struct al_pcie_rev3_w_app_hdr_interface_send app_hdr_interface_send;/* [0x2e4] */
-	struct al_pcie_rev3_w_diag_command diag_command;    /* [0x300] */
-	uint32_t rsrvd_3[3];
-	struct al_pcie_rev3_w_soc_int_per_func soc_int_per_func[REV3_MAX_NUM_OF_PFS]; /* [0x310] */
-	uint32_t rsrvd_4[44];
-	struct al_pcie_rev3_w_events_gen_per_func events_gen_per_func[REV3_MAX_NUM_OF_PFS]; /* [0x490] */
-	uint32_t rsrvd_5[4];
-	struct al_pcie_rev3_w_pm_state_per_func pm_state_per_func[REV3_MAX_NUM_OF_PFS];/* [0x4b0] */
-	uint32_t rsrvd_6[16];
-	struct al_pcie_rev3_w_cfg_bars_ovrd cfg_bars_ovrd[REV3_MAX_NUM_OF_PFS]; /* [0x500] */
-	uint32_t rsrvd_7[176];
-	uint32_t rsrvd_8[16];
-	struct al_pcie_revx_w_ap_err ap_err[5]; /* [0xac0] */
-	uint32_t rsrvd_9[11];
-	struct al_pcie_revx_w_status_per_func status_per_func[4]; /* [0xb00] */
-	uint32_t rsrvd_10[316];
-	struct al_pcie_revx_w_int_grp int_grp_a; /* [0x1000] */
-	struct al_pcie_revx_w_int_grp int_grp_b; /* [0x1040] */
-	struct al_pcie_revx_w_int_grp int_grp_c; /* [0x1080] */
-	struct al_pcie_revx_w_int_grp int_grp_d; /* [0x10c0] */
-};
-
-/*
-* Registers Fields
-*/
-
-
-/**** Port_Init register ****/
-/* Enable port to start LTSSM Link Training */
-#define PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK (1 << 0)
-#define PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_SHIFT (0)
-/*
- * Device Type
- * Indicates the specific type of this PCIe Function. It is also used to set the
- * Device/Port Type field.
- * 4'b0000: PCIe Endpoint
- * 4'b0001: Legacy PCIe Endpoint
- * 4'b0100: Root Port of PCIe Root Complex
- * Must be programmed before link training sequence. According to the reset
- * strap
- */
-#define PCIE_W_GLOBAL_CTRL_PORT_INIT_DEVICE_TYPE_MASK 0x000000F0
-#define PCIE_W_GLOBAL_CTRL_PORT_INIT_DEVICE_TYPE_SHIFT 4
-/*
- * Performs Manual Lane reversal for transmit Lanes.
- * Must be programmed before link training sequence.
- */
-#define PCIE_W_GLOBAL_CTRL_PORT_INIT_TX_LANE_FLIP_EN (1 << 8)
-/*
- * Performs Manual Lane reversal for receive Lanes.
- * Must be programmed before link training sequence.
- */
-#define PCIE_W_GLOBAL_CTRL_PORT_INIT_RX_LANE_FLIP_EN (1 << 9)
-/*
- * Auxiliary Power Detected
- * Indicates that auxiliary power (Vaux) is present. This one move to reset
- * strap from
- */
-#define PCIE_W_GLOBAL_CTRL_PORT_INIT_SYS_AUX_PWR_DET_NOT_USE (1 << 10)
-
-/**** Port_Status register ****/
-/* PHY Link up/down indicator */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_PHY_LINK_UP (1 << 0)
-/*
- * Data Link Layer up/down indicator
- * This status from the Flow Control Initialization State Machine indicates that
- * Flow Control has been initiated and the Data Link Layer is ready to transmit
- * and receive packets.
- */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_DL_LINK_UP (1 << 1)
-/* Reset request due to link down status. */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_LINK_REQ_RST (1 << 2)
-/* Power management is in L0s state.. */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_IN_L0S (1 << 3)
-/* Power management is in L1 state. */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_IN_L1 (1 << 4)
-/* Power management is in L2 state. */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_IN_L2 (1 << 5)
-/* Power management is exiting L2 state. */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_L2_EXIT (1 << 6)
-/* Power state of the device. */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_DSTATE_MASK 0x00000380
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_DSTATE_SHIFT 7
-/* tie to zero. */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_XMLH_IN_RL0S (1 << 10)
-/* Timeout count before flush */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_LINK_TOUT_FLUSH_NOT (1 << 11)
-/* Segmentation buffer not empty  */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_RADM_Q_NOT_EMPTY (1 << 12)
-/*
- * Clock Turnoff Request
- * Allows clock generation module to turn off core_clk based on the current
- * power management state:
- * 0: core_clk is required to be active for the current power state.
- * 1: The current power state allows core_clk to be shut down.
- * This does not indicate the clock requirement for the PHY.
- */
-#define PCIE_W_GLOBAL_CTRL_PORT_STS_CORE_CLK_REQ_N (1 << 31)
-
-/**** PM_Control register ****/
-/*
- * Wake Up. Used by application logic to wake up the PMC state machine from a
- * D1, D2, or D3 power state. EP mode only. Change the value from 0 to 1 to send
- * the message. Per function the upper bits are not use for ocie core less than
- * 8 functions
- */
-#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME (1 << 0)
-#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME_FUNC_MASK 0x000000FF
-#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME_FUNC_SHIFT 0
-/*
- * Request to Enter ASPM L1.
- * The core ignores the L1 entry request on app_req_entr_l1 when it is busy
- * processing a transaction.
- */
-#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_REQ_ENTR_L1 (1 << 3)
-#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_REQ_ENTR_L1 (1 << 8)
-/*
- * Request to exit ASPM L1.
- * Only effective if L1 is enabled.
- */
-#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_REQ_EXIT_L1 (1 << 4)
-#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_REQ_EXIT_L1 (1 << 9)
-/*
- * Indication that component is ready to enter the L23 state. The core delays
- * sending PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes
- * active.
- * EP mode
- */
-#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_READY_ENTR_L23 (1 << 5)
-#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_READY_ENTR_L23 (1 << 10)
-/*
- * Request to generate a PM_Turn_Off Message to communicate transition to L2/L3
- * Ready state to downstream components. Host must wait PM_Turn_Off_Ack messages
- * acceptance RC mode.
- */
-#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_PM_XMT_TURNOFF (1 << 6)
-#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_TURNOFF (1 << 11)
-/*
- * Provides a capability to defer incoming Configuration Requests until
- * initialization is complete. When app_req_retry_en is asserted, the core
- * completes incoming Configuration Requests with a Configuration Request Retry
- * Status. Other incoming Requests complete with Unsupported Request status.
- */
-#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN (1 << 7)
-#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN (1 << 12)
-/*
- * Core core gate enable
- * If set, core_clk is gated off whenever a clock turnoff request allows the
- * clock generation module to turn off core_clk (Port_Status.core_clk_req_n
- * field), and the PHY supports a request to disable clock gating. If not, the
- * core clock turns off in P2 mode in any case (PIPE).
- */
-#define PCIE_W_GLOBAL_CTRL_PM_CONTROL_CORE_CLK_GATE (1 << 31)
-
-/**** sris_kp_counter_value register ****/
-/* skp counter when SRIS disable */
-#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_NO_SRIS_MASK 0x000001FF
-#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_NO_SRIS_SHIFT 0
-/* skp counter when SRIS enable */
-#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_MASK 0x0003FE00
-#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_SHIFT 9
-/* skp counter when SRIS enable for gen3 */
-#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_MASK 0x1FFC0000
-#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_SHIFT 18
-/* mask the interrupt to the soc in case correctable error occur in the ARI.  */
-#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_RSRVD_MASK 0x60000000
-#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_RSRVD_SHIFT 29
-/* not in use in the pcie_x8 core. */
-#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_PCIE_X4_SRIS_EN (1 << 31)
-
-/**** Events_Gen register ****/
-/* INT_D. Not supported  */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTD (1 << 0)
-/* INT_C. Not supported  */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTC (1 << 1)
-/* INT_B. Not supported  */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTB (1 << 2)
-/* Transmit INT_A Interrupt ControlEvery transition from 0 to 1  ... */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTA (1 << 3)
-/* A request to generate an outbound MSI interrupt when MSI is e ... */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_TRNS_REQ (1 << 4)
-/* Set the MSI vector before issuing msi_trans_req. */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK 0x000003E0
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_SHIFT 5
-/* The application requests hot reset to a downstream device */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT (1 << 10)
-/* The application request unlock message to be sent */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_UNLOCK_GEN (1 << 30)
-/* Indicates that FLR on a Physical Function has been completed */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_FLR_PF_DONE (1 << 31)
-
-/**** Cpl_TO_Info register ****/
-/* The Traffic Class of the timed out CPL */
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_TC_MASK 0x00000003
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_TC_SHIFT 0
-/* Indicates which Virtual Function (VF) had a CPL timeout */
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_FUN_NUM_MASK 0x000000FC
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_FUN_NUM_SHIFT 2
-/* The Tag field of the timed out CPL */
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_TAG_MASK 0x0000FF00
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_TAG_SHIFT 8
-/* The Attributes field of the timed out CPL */
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_ATTR_MASK 0x00030000
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_ATTR_SHIFT 16
-/* The Len field of the timed out CPL */
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_LEN_MASK 0x3FFC0000
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_LEN_SHIFT 18
-/*
- * Write 1 to this field to clear the information logged in the register. New
- * logged information will only be valid when the interrupt is cleared .
- */
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_VALID (1 << 31)
-#define PCIE_W_LCL_LOG_CPL_TO_INFO_VALID_SHIFT (31)
-
-/**** Rcv_Msg0_0 register ****/
-/* The Requester ID of the received message */
-#define PCIE_W_LCL_LOG_RCV_MSG0_0_REQ_ID_MASK 0x0000FFFF
-#define PCIE_W_LCL_LOG_RCV_MSG0_0_REQ_ID_SHIFT 0
-/*
- * Valid logged message
- * Writing 1 to this bit enables new message capturing. Write one to clear
- */
-#define PCIE_W_LCL_LOG_RCV_MSG0_0_VALID (1 << 31)
-
-/**** Rcv_Msg1_0 register ****/
-/* The Requester ID of the received message */
-#define PCIE_W_LCL_LOG_RCV_MSG1_0_REQ_ID_MASK 0x0000FFFF
-#define PCIE_W_LCL_LOG_RCV_MSG1_0_REQ_ID_SHIFT 0
-/*
- * Valid logged message
- * Writing 1 to this bit enables new message capturing. Write one to clear
- */
-#define PCIE_W_LCL_LOG_RCV_MSG1_0_VALID (1 << 31)
-
-/**** Core_Queues_Status register ****/
-/*
- * Indicates which entries in the CPL lookup table
- * have valid entries stored. NOT supported.
- */
-#define PCIE_W_LCL_LOG_CORE_Q_STATUS_CPL_LUT_VALID_MASK 0x0000FFFF
-#define PCIE_W_LCL_LOG_CORE_Q_STATUS_CPL_LUT_VALID_SHIFT 0
-
-/**** Cpl_to register ****/
-#define PCIE_W_LCL_LOG_CPL_TO_REQID_MASK 0x0000FFFF
-#define PCIE_W_LCL_LOG_CPL_TO_REQID_SHIFT 0
-
-/**** Debug_Info_0 register ****/
-/* Indicates the current power state */
-#define PCIE_W_DEBUG_INFO_0_PM_CURRENT_STATE_MASK 0x00000007
-#define PCIE_W_DEBUG_INFO_0_PM_CURRENT_STATE_SHIFT 0
-/* Current state of the LTSSM */
-#define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_MASK 0x000001F8
-#define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_SHIFT 3
-/* Decode of the Recovery. Equalization LTSSM state */
-#define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_RCVRY_EQ (1 << 9)
-/* State of selected internal signals, for debug purposes only */
-#define PCIE_W_DEBUG_INFO_0_CXPL_DEBUG_INFO_EI_MASK 0x03FFFC00
-#define PCIE_W_DEBUG_INFO_0_CXPL_DEBUG_INFO_EI_SHIFT 10
-
-/**** control register ****/
-/* Indication to send vendor message; when clear the message was sent. */
-#define PCIE_W_OB_VEN_MSG_CONTROL_REQ (1 << 0)
-
-/**** param_1 register ****/
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_1_FMT_MASK 0x00000003
-#define PCIE_W_OB_VEN_MSG_PARAM_1_FMT_SHIFT 0
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_1_TYPE_MASK 0x0000007C
-#define PCIE_W_OB_VEN_MSG_PARAM_1_TYPE_SHIFT 2
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_1_TC_MASK 0x00000380
-#define PCIE_W_OB_VEN_MSG_PARAM_1_TC_SHIFT 7
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_1_TD (1 << 10)
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_1_EP (1 << 11)
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_1_ATTR_MASK 0x00003000
-#define PCIE_W_OB_VEN_MSG_PARAM_1_ATTR_SHIFT 12
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_1_LEN_MASK 0x00FFC000
-#define PCIE_W_OB_VEN_MSG_PARAM_1_LEN_SHIFT 14
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_1_TAG_MASK 0xFF000000
-#define PCIE_W_OB_VEN_MSG_PARAM_1_TAG_SHIFT 24
-
-/**** param_2 register ****/
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_2_REQ_ID_MASK 0x0000FFFF
-#define PCIE_W_OB_VEN_MSG_PARAM_2_REQ_ID_SHIFT 0
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_2_CODE_MASK 0x00FF0000
-#define PCIE_W_OB_VEN_MSG_PARAM_2_CODE_SHIFT 16
-/* Vendor message parameters */
-#define PCIE_W_OB_VEN_MSG_PARAM_2_RSVD_31_24_MASK 0xFF000000
-#define PCIE_W_OB_VEN_MSG_PARAM_2_RSVD_31_24_SHIFT 24
-
-/**** ack_info register ****/
-/* Vendor message parameters */
-#define PCIE_W_AP_USER_SEND_MSG_ACK_INFO_ACK (1 << 0)
-
-/**** features register ****/
-/* Enable MSI fix from the SATA to the PCIe EP - Only valid for port zero */
-#define PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX	AL_BIT(16)
-
-/**** in/out_mask_x_y register ****/
-/* When bit [i] set to 1 it maks the compare in the atu_in/out wind ... */
-#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_MASK 0x0000FFFF
-#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_SHIFT 0
-/* When bit [i] set to 1 it maks the compare in the atu_in/out wind ... */
-#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_MASK 0xFFFF0000
-#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_SHIFT 16
-
-/**** cfg register ****/
-/*
- * The 2-bit TPH Requester Enabled field of each TPH
- * Requester Control register.
- */
-#define PCIE_W_CFG_FUNC_EXT_CFG_CFG_TPH_REQ_EN_MASK 0x000000FF
-#define PCIE_W_CFG_FUNC_EXT_CFG_CFG_TPH_REQ_EN_SHIFT 0
-/* SRIS mode enable. */
-#define PCIE_W_CFG_FUNC_EXT_CFG_APP_SRIS_MODE (1 << 8)
-/*
- *
- */
-#define PCIE_W_CFG_FUNC_EXT_CFG_RSRVD_MASK 0xFFFFFE00
-#define PCIE_W_CFG_FUNC_EXT_CFG_RSRVD_SHIFT 9
-
-/**** app_func_num_advisory register ****/
-/*
- * The number of the function that is reporting the error
- * indicated app_err_bus, valid when app_hdr_valid is asserted.
- * Correctable and Uncorrected Internal errors (app_err_bus[10:9]) are
- * not function specific, and are recorded for all physical functions,
- * regardless of the value this bus. Function numbering starts at '0'.
- */
-#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_FUNC_NUM_MASK 0x0000FFFF
-#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_FUNC_NUM_SHIFT 0
-/*
- * Description: Indicates that your application error is an advisory
- * error. Your application should assert app_err_advisory under either
- * of the following conditions:
- * - The core is configured to mask completion timeout errors, your
- * application is reporting a completion timeout error app_err_bus,
- * and your application intends to resend the request. In such cases
- * the error is an advisory error, as described in PCI Express 3.0
- * Specification. When your application does not intend to resend
- * the request, then your application must keep app_err_advisory
- * de-asserted when reporting a completion timeout error.
- * - The core is configured to forward poisoned TLPs to your
- * application and your application is going to treat the poisoned
- * TLP as a normal TLP, as described in PCI Express 3.0
- * Specification. Upon receipt of a poisoned TLP, your application
- * must report the error app_err_bus, and either assert
- * app_err_advisory (to indicate an advisory error) or de-assert
- * app_err_advisory (to indicate that your application is dropping the
- * TLP).
- * For more details, see the PCI Express 3.0 Specification to determine
- * when an application error is an advisory error.
- */
-#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_ADVISORY (1 << 16)
-/*
- * Rsrvd.
- */
-#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_RSRVD_MASK 0xFFFE0000
-#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_RSRVD_SHIFT 17
-
-/**** app_hdr_cmd register ****/
-/*
- * When set the header is send (need to clear before sending the next message).
- */
-#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_APP_HDR_VALID (1 << 0)
-/*
- * Rsrvd.
- */
-#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_RSRVD_MASK 0xFFFFFFFE
-#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_RSRVD_SHIFT 1
-
-/**** diag_ctrl register ****/
-/*
- * The 2-bit TPH Requester Enabled field of each TPH
- * Requester Control register.
- */
-#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_DIAG_CTRL_BUS_MASK 0x00000007
-#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_DIAG_CTRL_BUS_SHIFT 0
-/*
- *
- */
-#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_RSRVD_MASK 0xFFFFFFF8
-#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_RSRVD_SHIFT 3
-
-
-/**** Events_Gen register ****/
-/* INT_D. Not supported  */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTD (1 << 0)
-/* INT_C. Not supported  */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTC (1 << 1)
-/* INT_B. Not supported  */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTB (1 << 2)
-/*
- * Transmit INT_A Interrupt Control
- * Every transition from 0 to 1 schedules an Assert_ INT interrupt message for
- * transmit.
- * Every transition from 1 to 0, schedules a Deassert_INT interrupt message for
- * transmit. Which interrupt, the PCIe only use INTA message.
- */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTA (1 << 3)
-/*
- * A request to generate an outbound MSI interrupt when MSI is enabled. Change
- * from 1'b0 to 1'b1 to create an MSI write to be sent.
- */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_TRNS_REQ (1 << 4)
-/* Set the MSI vector before issuing msi_trans_req. */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK 0x000003E0
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_SHIFT 5
-/*
- * The application requests hot reset to a downstream device. Change the value
- * from 0 to 1 to send hot reset. Only func 0 is supported.
- */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT (1 << 10)
-/*
- * The application request unlock message to be sent. Change the value from 0 to
- * 1 to send the message. Only func 0 is supported.
- */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_UNLOCK_GEN (1 << 30)
-/* Indicates that FLR on a Physical Function has been completed. */
-#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_FLR_PF_DONE (1 << 31)
-
-/**** pm_state_per_func register ****/
-/*
- * Description: The current power management D-state of the
- * function:
- * \u25a0 000b: D0
- * \u25a0 001b: D1
- * \u25a0 010b: D2
- * \u25a0 011b: D3
- * \u25a0 100b: Uninitialized
- * \u25a0 Other values: Not applicable
- * There are 3 bits of pm_dstate for each configured function.
- */
-#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_DSTATE_MASK 0x0000000F
-#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_DSTATE_SHIFT 0
-/*
- * PME Status bit from the PMCSR. There is 1 bit of
- * pm_status for each configured function
- */
-#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_STATUS (1 << 4)
-/*
- * PME Enable bit in the PMCSR. There is 1 bit of
- * pm_pme_en for each configured function.
- */
-#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_PME_EN (1 << 5)
-/*
- * Auxiliary Power Enable bit in the Device Control
- * register. There is 1 bit of aux_pm_en for each configured function.
- */
-#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_AUX_PME_EN (1 << 6)
-/*
- * This field should be set according to the MAX_FUNC_NUM set in the PCIe core,
- * it uses as mask (bit per function) to the dsate when set to zero.
- */
-#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_ASPM_PF_ENABLE_MAX_FUNC_NUMBER (1 << 7)
-/*
- * This field should be set according to the MAX_FUNC_NUM set in the PCIe core,
- * it uses as mask (bit per function) to the ASPM contrl bit, when set to zero.
- */
-#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_DSATE_PF_ENABLE_MAX_FUNC_NUMBER (1 << 8)
-
-/**** bar0_ctrl register ****/
-/* bar is en and override the internal PF bar. */
-#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_EN_MASK 0x00000003
-#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_EN_SHIFT 0
-/* bar is io */
-#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_IO_MASK 0x0000000C
-#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_IO_SHIFT 2
-/* Reserved. */
-#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_RSRVS_MASK 0xFFFFFFF0
-#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_RSRVS_SHIFT 4
-
-/**** bar1_ctrl register ****/
-/* bar is en and override the internal PF bar. */
-#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_EN_MASK 0x00000003
-#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_EN_SHIFT 0
-/* bar is io */
-#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_IO_MASK 0x0000000C
-#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_IO_SHIFT 2
-/* Reserved. */
-#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_RSRVS_MASK 0xFFFFFFF0
-#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_RSRVS_SHIFT 4
-
-/**** bar2_ctrl register ****/
-/* bar is en and override the internal PF bar. */
-#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_EN_MASK 0x00000003
-#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_EN_SHIFT 0
-/* bar is io */
-#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_IO_MASK 0x0000000C
-#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_IO_SHIFT 2
-/* Reserved. */
-#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_RSRVS_MASK 0xFFFFFFF0
-#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_RSRVS_SHIFT 4
-
-/**** bar3_ctrl register ****/
-/* bar is en and override the internal PF bar. */
-#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_EN_MASK 0x00000003
-#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_EN_SHIFT 0
-/* bar is io */
-#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_IO_MASK 0x0000000C
-#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_IO_SHIFT 2
-/* Reserved. */
-#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_RSRVS_MASK 0xFFFFFFF0
-#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_RSRVS_SHIFT 4
-
-/**** bar4_ctrl register ****/
-/* bar is en and override the internal PF bar. */
-#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_EN_MASK 0x00000003
-#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_EN_SHIFT 0
-/* bar is io */
-#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_IO_MASK 0x0000000C
-#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_IO_SHIFT 2
-/* Reserved. */
-#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_RSRVS_MASK 0xFFFFFFF0
-#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_RSRVS_SHIFT 4
-
-/**** bar5_ctrl register ****/
-/* bar is en and override the internal PF bar. */
-#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_EN_MASK 0x00000003
-#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_EN_SHIFT 0
-/* bar is io */
-#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_IO_MASK 0x0000000C
-#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_IO_SHIFT 2
-/* Reserved. */
-#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_RSRVS_MASK 0xFFFFFFF0
-#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_RSRVS_SHIFT 4
-
-/**** cause_A register ****/
-/* Deassert_INTD received. Write zero to clear this bit. */
-#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTD (1 << 0)
-/* Deassert_INTC received. Write zero to clear this bit. */
-#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTC (1 << 1)
-/* Deassert_INTB received. Write zero to clear this bit. */
-#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTB (1 << 2)
-/* Deassert_INTA received. Write zero to clear this bit. */
-#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTA (1 << 3)
-/* Assert_INTD received. Write zero to clear this bit. */
-#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTD (1 << 4)
-/* Assert_INTC received. Write zero to clear this bit. */
-#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTC (1 << 5)
-/* Assert_INTC received. Write zero to clear this bit. */
-#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTB (1 << 6)
-/* Assert_INTA received. Write zero to clear this bit. */
-#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTA (1 << 7)
-/*
- * MSI Controller Interrupt
- * MSI interrupt is being received. Write zero to clear this bit
- */
-#define PCIE_W_INT_GRP_A_CAUSE_A_MSI_CNTR_RCV_INT (1 << 8)
-/*
- * MSI sent grant. Write zero to clear this bit.
- */
-#define PCIE_W_INT_GRP_A_CAUSE_A_MSI_TRNS_GNT (1 << 9)
-/*
- * System error detected
- * Indicates if any device in the hierarchy reports any of the following errors
- * and the associated enable bit is set in the Root Control register:
- * ERR_COR
- * ERR_FATAL
- * ERR_NONFATAL
- * Also asserted when an internal error is detected. Write zero to clear this
- * bit.
- */
-#define PCIE_W_INT_GRP_A_CAUSE_A_SYS_ERR_RC (1 << 10)
-/*
- * Set when software initiates FLR on a Physical Function by writing to the
- * Initiate FLR register bit of that function Write zero to clear this bit.
- */
-#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_FLR_PF_ACTIVE (1 << 11)
-#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_11 (1 << 11)
-/*
- * Reported error condition causes a bit to be set in the Root Error Status
- * register and the associated error message reporting enable bit is set in the
- * Root Error Command Register. Write zero to clear this bit.
- */
-#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_AER_RC_ERR (1 << 12)
-#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_12 (1 << 12)
-/*
- * The core asserts aer_rc_err_msi when all of the following conditions are
- * true:
- * - MSI or MSI-X is enabled.
- * - A reported error condition causes a bit to be set in the Root Error Status
- * register.
- * - The associated error message reporting enable bit is set in the Root Error
- * Command register Write zero to clear this bit
- */
-#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_AER_RC_ERR_MSI (1 << 13)
-#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_13 (1 << 13)
-/*
- * Wake Up. Wake up from power management unit.
- * The core generates wake to request the system to restore power and clock when
- * a beacon has been detected. wake is an active high signal and its rising edge
- * should be detected to drive the WAKE# on the connector Write zero to clear
- * this bit
- */
-#define PCIE_W_INT_GRP_A_CAUSE_A_WAKE (1 << 14)
-/*
- * The core asserts cfg_pme_int when all of the following conditions are true:
- * - INTx Assertion Disable bit in the Command register is 0.
- * - PME Interrupt Enable bit in the Root Control register is set to 1.
- * - PME Status bit in the Root Status register is set to 1. Write zero to clear
- * this bit
- */
-#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_PME_INT (1 << 15)
-#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_15 (1 << 15)
-/*
- * The core asserts cfg_pme_msi when all of the following conditions are true:
- * - MSI or MSI-X is enabled.
- * - PME Interrupt Enable bit in the Root Control register is set to 1.
- * - PME Status bit in the Root Status register is set to 1. Write zero to clear
- * this bit
- */
-#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_PME_MSI (1 << 16)
-#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_16 (1 << 16)
-/*
- * The core asserts hp_pme when all of the following conditions are true:
- * - The PME Enable bit in the Power Management Control and Status register is
- * set to 1.
- * - Any bit in the Slot Status register transitions from 0 to 1 and the
- * associated event notification is enabled in the Slot Control register. Write
- * zero to clear this bit
- */
-#define PCIE_W_INT_GRP_A_CAUSE_A_HP_PME (1 << 17)
-/*
- * The core asserts hp_int when all of the following conditions are true:
- * - INTx Assertion Disable bit in the Command register is 0.
- * - Hot-Plug interrupts are enabled in the Slot Control register.
- * - Any bit in the Slot Status register is equal to 1, and the associated event
- * notification is enabled in the Slot Control register. Write zero to clear
- * this bit
- */
-#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_HP_INT (1 << 18)
-/* The outstanding write counter become  full should never happen */
-#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_WRITE_COUNTER_FULL_ERR (1 << 18)
-
-
-/*
- * The core asserts hp_msi when the logical AND of the following conditions
- * transitions from false to true:
- * - MSI or MSI-X is enabled.
- * - Hot-Plug interrupts are enabled in the Slot Control register.
- * - Any bit in the Slot Status register transitions from 0 to 1 and the
- * associated event notification is enabled in the Slot Control register.
- */
-#define PCIE_W_INT_GRP_A_CAUSE_A_HP_MSI (1 << 19)
-/* Read VPD registers notification */
-#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_VPD_INT (1 << 20)
-/* not use */
-#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_NOT_USE (1 << 20)
-
-/*
- * The core assert link down event, whenever the link is going down. Write zero
- * to clear this bit, pulse signal
- */
-#define PCIE_W_INT_GRP_A_CAUSE_A_LINK_DOWN_EVENT (1 << 21)
-/*
- * When the EP gets a command to shut down, signal the software to block any new
- * TLP.
- */
-#define PCIE_W_INT_GRP_A_CAUSE_A_PM_XTLH_BLOCK_TLP (1 << 22)
-/* PHY/MAC link up */
-#define PCIE_W_INT_GRP_A_CAUSE_A_XMLH_LINK_UP (1 << 23)
-/* Data link up */
-#define PCIE_W_INT_GRP_A_CAUSE_A_RDLH_LINK_UP (1 << 24)
-/* The ltssm is in RCVRY_LOCK state. */
-#define PCIE_W_INT_GRP_A_CAUSE_A_LTSSM_RCVRY_STATE (1 << 25)
-/*
- * Config write transaction to the config space by the RC peer, enable this
- * interrupt only for EP mode.
- */
-#define PCIE_W_INT_GRP_A_CAUSE_A_CFG_WR_EVENT (1 << 26)
-/* AER error */
-#define PCIE_W_INT_GRP_A_CAUSE_A_AP_PENDED_CORR_ERR_STS_INT (1 << 28)
-/* AER error */
-#define PCIE_W_INT_GRP_A_CAUSE_A_AP_PENDED_UNCORR_ERR_STS_INT (1 << 29)
-
-/**** control_A register ****/
-/* When Clear_on_Read =1, all bits of  Cause register are cleared on read. */
-#define PCIE_W_INT_GRP_A_CONTROL_A_CLEAR_ON_READ (1 << 0)
-/*
- * (Must be set only when MSIX is enabled.)
- * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
- * corresponding bit in the Mask register is set, masking future interrupts.
- */
-#define PCIE_W_INT_GRP_A_CONTROL_A_AUTO_MASK (1 << 1)
-/*
- * Auto_Clear (RW)
- * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
- * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
- */
-#define PCIE_W_INT_GRP_A_CONTROL_A_AUTO_CLEAR (1 << 2)
-/*
- * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on
- * the posedge of the interrupt source, i.e., when interrupt source =1 and
- * Interrupt Status = 0.
- * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
- * interrupt source =1.
- */
-#define PCIE_W_INT_GRP_A_CONTROL_A_SET_ON_POSEDGE (1 << 3)
-/*
- * When Moderation_Reset =1, all Moderation timers associated with the interrupt
- * cause bits are cleared to 0, enabling immediate interrupt assertion if any
- * unmasked cause bit is set to 1. This bit is self-negated.
- */
-#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RST (1 << 4)
-/*
- * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to
- * 1 when the associated summary bit in this group is used to generate a single
- * MSI-X for this group.
- */
-#define PCIE_W_INT_GRP_A_CONTROL_A_MASK_MSI_X (1 << 5)
-/* MSI-X AWID value. Same ID for all cause bits. */
-#define PCIE_W_INT_GRP_A_CONTROL_A_AWID_MASK 0x00000F00
-#define PCIE_W_INT_GRP_A_CONTROL_A_AWID_SHIFT 8
-/*
- * This value determines the interval between interrupts; writing ZERO disables
- * Moderation.
- */
-#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_INTV_MASK 0x00FF0000
-#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_INTV_SHIFT 16
-/*
- * This value determines the Moderation_Timer_Clock speed.
- * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
- * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
- * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
- */
-#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RES_MASK 0x0F000000
-#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RES_SHIFT 24
-
-/**** cause_B register ****/
-/* Indicates that the core received a PM_PME Message. Write Zero to clear. */
-#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_PME (1 << 0)
-/*
- * Indicates that the core received a PME_TO_Ack Message. Write Zero to clear.
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_TO_ACK (1 << 1)
-/*
- * Indicates that the core received an PME_Turn_Off Message. Write Zero to
- * clear.
- * EP mode only
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_TURNOFF (1 << 2)
-/* Indicates that the core received an ERR_CORR Message. Write Zero to clear. */
-#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_CORRECTABLE_ERR (1 << 3)
-/*
- * Indicates that the core received an ERR_NONFATAL Message. Write Zero to
- * clear.
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_NONFATAL_ERR (1 << 4)
-/*
- * Indicates that the core received an ERR_FATAL Message. Write Zero to clear.
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_FATAL_ERR (1 << 5)
-/*
- * Indicates that the core received a Vendor Defined Message. Write Zero to
- * clear.
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_VENDOR_0 (1 << 6)
-/*
- * Indicates that the core received a Vendor Defined Message. Write Zero to
- * clear.
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_VENDOR_1 (1 << 7)
-/* Indicates that the core received an Unlock Message. Write Zero to clear. */
-#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_UNLOCK (1 << 8)
-/*
- * Notification when the Link Autonomous Bandwidth Status register (Link Status
- * register bit 15) is updated and the Link Autonomous Bandwidth Interrupt
- * Enable (Link Control register bit 11) is set. This bit is not applicable to,
- * and is reserved, for Endpoint device. Write Zero to clear
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_LINK_AUTO_BW_INT (1 << 12)
-/*
- * Notification that the Link Equalization Request bit in the Link Status 2
- * Register has been set. Write Zero to clear.
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_LINK_EQ_REQ_INT (1 << 13)
-/*
- * OB Vendor message request is granted by the PCIe core Write Zero to clear.
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_VENDOR_MSG_GRANT (1 << 14)
-/* CPL timeout from the PCIe core inidication. Write Zero to clear */
-#define PCIE_W_INT_GRP_B_CAUSE_B_CMP_TIME_OUT (1 << 15)
-/*
- * Slave Response Composer Lookup Error
- * Indicates that an overflow occurred in a lookup table of the Inbound
- * responses. This indicates that there was a violation of the number of
- * outstanding NP requests issued for the Outbound direction. Write zero to
- * clear
- */
-#define PCIE_W_INT_GRP_B_CAUSE_B_RADMX_CMPOSER_LOOKUP_ERR (1 << 16)
-/* Parity Error */
-#define PCIE_W_INT_GRP_B_CAUSE_B_PARITY_ERROR_CORE (1 << 17)
-
-/**** control_B register ****/
-/* When Clear_on_Read =1, all bits of the Cause register are cleared on read. */
-#define PCIE_W_INT_GRP_B_CONTROL_B_CLEAR_ON_READ (1 << 0)
-/*
- * (Must be set only when MSIX is enabled.)
- * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
- * corresponding bit in the Mask register is set, masking future interrupts.
- */
-#define PCIE_W_INT_GRP_B_CONTROL_B_AUTO_MASK (1 << 1)
-/*
- * Auto_Clear (RW)
- * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
- * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
- */
-#define PCIE_W_INT_GRP_B_CONTROL_B_AUTO_CLEAR (1 << 2)
-/*
- * When Set_on_Posedge =1, the bits in the interrupt Cause register are set on
- * the posedge of the interrupt source, i.e., when Interrupt Source =1 and
- * Interrupt Status = 0.
- * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
- * Interrupt Source =1.
- */
-#define PCIE_W_INT_GRP_B_CONTROL_B_SET_ON_POSEDGE (1 << 3)
-/*
- * When Moderation_Reset =1, all Moderation timers associated with the interrupt
- * cause bits are cleared to 0, enabling an immediate interrupt assertion if any
- * unmasked cause bit is set to 1. This bit is self-negated.
- */
-#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RST (1 << 4)
-/*
- * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to
- * 1 when the associated summary bit in this group is used to generate a single
- * MSI-X for this group.
- */
-#define PCIE_W_INT_GRP_B_CONTROL_B_MASK_MSI_X (1 << 5)
-/* MSI-X AWID value. Same ID for all cause bits. */
-#define PCIE_W_INT_GRP_B_CONTROL_B_AWID_MASK 0x00000F00
-#define PCIE_W_INT_GRP_B_CONTROL_B_AWID_SHIFT 8
-/*
- * This value determines the interval between interrupts. Writing ZERO disables
- * Moderation.
- */
-#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_INTV_MASK 0x00FF0000
-#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_INTV_SHIFT 16
-/*
- * This value determines the Moderation_Timer_Clock speed.
- * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
- * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
- * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
- */
-#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RES_MASK 0x0F000000
-#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RES_SHIFT 24
-
-/**** cause_C register ****/
-/* VPD interrupt, ot read/write frpm EEPROM */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_VPD_INT_FUNC_MASK 0x0000000F
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_VPD_INT_FUNC_SHIFT 0
-/* flr PF active */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_FLR_PF_ACTIVE_MASK 0x000000F0
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_FLR_PF_ACTIVE_SHIFT 4
-/* System ERR RC. */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_SYS_ERR_RC_MASK 0x00000F00
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_SYS_ERR_RC_SHIFT 8
-/* AER RC INT */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_INT_MASK 0x0000F000
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_INT_SHIFT 12
-/* AER RC MSI */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_MSI_MASK 0x000F0000
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_MSI_SHIFT 16
-/* PME MSI */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_MSI_MASK 0x00F00000
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_MSI_SHIFT 20
-/* PME int */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_INT_MASK 0x0F000000
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_INT_SHIFT 24
-/* SB overflow */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_RADM_QOVERFLOW (1 << 28)
-/* ecrc was injected through the diag_ctrl bus */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_ECRC_INJECTED (1 << 29)
-/* lcrc was injected through the diag_ctrl bus */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_LCRC_INJECTED (1 << 30)
-/* lcrc was injected through the diag_ctrl bus */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_RSRVD (1 << 31)
-
-/**** control_C register ****/
-/* When Clear_on_Read =1, all bits of  Cause register are cleared on read. */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_CLEAR_ON_READ (1 << 0)
-/*
- * (Must be set only when MSIX is enabled.)
- * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
- * corresponding bit in the Mask register is set, masking future interrupts.
- */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AUTO_MASK (1 << 1)
-/*
- * Auto_Clear (RW)
- * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
- * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
- */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AUTO_CLEAR (1 << 2)
-/*
- * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on
- * the posedge of the interrupt source, i.e., when interrupt source =1 and
- * Interrupt Status = 0.
- * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
- * interrupt source =1.
- */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_SET_ON_POSEDGE (1 << 3)
-/*
- * When Moderation_Reset =1, all Moderation timers associated with the interrupt
- * cause bits are cleared to 0, enabling immediate interrupt assertion if any
- * unmasked cause bit is set to 1. This bit is self-negated.
- */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RST (1 << 4)
-/*
- * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to
- * 1 when the associated summary bit in this group is used to generate a single
- * MSI-X for this group.
- */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MASK_MSI_X (1 << 5)
-/* MSI-X AWID value. Same ID for all cause bits. */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AWID_MASK 0x00000F00
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AWID_SHIFT 8
-/*
- * This value determines the interval between interrupts; writing ZERO disables
- * Moderation.
- */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_INTV_MASK 0x00FF0000
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_INTV_SHIFT 16
-/*
- * This value determines the Moderation_Timer_Clock speed.
- * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
- * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
- * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
- */
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RES_MASK 0x0F000000
-#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RES_SHIFT 24
-
-/**** control_D register ****/
-/* When Clear_on_Read =1, all bits of  Cause register are cleared on read. */
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_CLEAR_ON_READ (1 << 0)
-/*
- * (Must be set only when MSIX is enabled.)
- * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
- * corresponding bit in the Mask register is set, masking future interrupts.
- */
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AUTO_MASK (1 << 1)
-/*
- * Auto_Clear (RW)
- * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
- * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
- */
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AUTO_CLEAR (1 << 2)
-/*
- * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on
- * the posedge of the interrupt source, i.e., when interrupt source =1 and
- * Interrupt Status = 0.
- * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
- * interrupt source =1.
- */
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_SET_ON_POSEDGE (1 << 3)
-/*
- * When Moderation_Reset =1, all Moderation timers associated with the interrupt
- * cause bits are cleared to 0, enabling immediate interrupt assertion if any
- * unmasked cause bit is set to 1. This bit is self-negated.
- */
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RST (1 << 4)
-/*
- * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to
- * 1 when the associated summary bit in this group is used to generate a single
- * MSI-X for this group.
- */
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MASK_MSI_X (1 << 5)
-/* MSI-X AWID value. Same ID for all cause bits. */
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AWID_MASK 0x00000F00
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AWID_SHIFT 8
-/*
- * This value determines the interval between interrupts; writing ZERO disables
- * Moderation.
- */
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_INTV_MASK 0x00FF0000
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_INTV_SHIFT 16
-/*
- * This value determines the Moderation_Timer_Clock speed.
- * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
- * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
- * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
- */
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RES_MASK 0x0F000000
-#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RES_SHIFT 24
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_PCIE_W_REG_H */
-
-/** @} end of ... group */
-
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_plat_services.h b/sys/contrib/alpine-hal/eth/al_hal_plat_services.h
deleted file mode 100644
index 217bb927f69f..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_plat_services.h
+++ /dev/null
@@ -1,419 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_services Platform Services API
- *  @{
- * The Platform Services API provides miscellaneous system services to HAL
- * drivers, such as:
- * - Registers read/write
- * - Assertions
- * - Memory barriers
- * - Endianness conversions
- *
- * And more.
- * @file   plat_api/sample/al_hal_plat_services.h
- *
- * @brief  API for Platform services provided for to HAL drivers
- *
- *
- */
-
-#ifndef __PLAT_SERVICES_H__
-#define __PLAT_SERVICES_H__
-
-#include <machine/atomic.h>
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/endian.h>
-#include <sys/errno.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-
-/* Prototypes for all the bus_space structure functions */
-bs_protos(generic);
-bs_protos(generic_armv4);
-
-#define __UNUSED __attribute__((unused))
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/*
- * WMA: This is a hack which allows not modifying the __iomem accessing HAL code.
- * On ARMv7, bus_handle holds the information about VA of accessed memory. It
- * is possible to use direct load/store instruction instead of bus_dma machinery.
- * WARNING: This is not guaranteed to stay that way forever, nor that
- * on other architectures these variables behave similarly. Keep that
- * in mind during porting to other systems.
- */
-/**
- * Read MMIO 8 bits register
- * @param  offset	register offset
- *
- * @return register value
- */
-static uint8_t al_reg_read8(uint8_t * offset);
-
-/**
- * Read MMIO 16 bits register
- * @param  offset	register offset
- *
- * @return register value
- */
-static uint16_t al_reg_read16(uint16_t * offset);
-
-/**
- * Read MMIO 32 bits register
- * @param  offset	register offset
- *
- * @return register value
- */
-static uint32_t al_reg_read32(uint32_t * offset);
-
-/**
- * Read MMIO 64 bits register
- * @param  offset	register offset
- *
- * @return register value
- */
-uint64_t al_reg_read64(uint64_t * offset);
-
-/**
- * Relaxed read MMIO 32 bits register
- *
- * Relaxed register read/write functions don't involve cpu instructions that
- * force syncronization, nor ordering between the register access and memory
- * data access.
- * These instructions are used in performance critical code to avoid the
- * overhead of the synchronization instructions.
- *
- * @param  offset	register offset
- *
- * @return register value
- */
-#define al_bus_dma_to_va(bus_tag, bus_handle)	((void*)bus_handle)
-
-/**
- * Relaxed read MMIO 32 bits register
- *
- * Relaxed register read/write functions don't involve cpu instructions that
- * force syncronization, nor ordering between the register access and memory
- * data access.
- * These instructions are used in performance critical code to avoid the
- * overhead of the synchronization instructions.
- *
- * @param  offset	register offset
- *
- * @return register value
- */
-#define al_reg_read32_relaxed(l)	generic_bs_r_4(NULL, (bus_space_handle_t)l, 0)
-
-/**
- * Relaxed write to MMIO 32 bits register
- *
- * Relaxed register read/write functions don't involve cpu instructions that
- * force syncronization, nor ordering between the register access and memory
- * data access.
- * These instructions are used in performance critical code to avoid the
- * overhead of the synchronization instructions.
- *
- * @param  offset	register offset
- * @param  val		value to write to the register
- */
-#define al_reg_write32_relaxed(l,v)	generic_bs_w_4(NULL, (bus_space_handle_t)l, 0, v)
-
-/**
- * Write to MMIO 8 bits register
- * @param  offset	register offset
- * @param  val		value to write to the register
- */
-#define al_reg_write8(l,v)	do { dsb(); generic_bs_w_1(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
-
-/**
- * Write to MMIO 16 bits register
- * @param  offset	register offset
- * @param  val		value to write to the register
- */
-#define al_reg_write16(l,v)	do { dsb(); generic_bs_w_2(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
-
-/**
- * Write to MMIO 32 bits register
- * @param  offset	register offset
- * @param  val		value to write to the register
- */
-#define al_reg_write32(l,v)	do { dsb(); generic_bs_w_4(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
-
-/**
- * Write to MMIO 64 bits register
- * @param  offset	register offset
- * @param  val		value to write to the register
- */
-#define al_reg_write64(l,v)	do { dsb(); generic_bs_w_8(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
-
-static inline uint8_t
-al_reg_read8(uint8_t *l)
-{
-	dsb();
-
-	return (generic_bs_r_1(NULL, (bus_space_handle_t)l, 0));
-}
-
-static inline uint16_t
-al_reg_read16(uint16_t *l)
-{
-	dsb();
-
-	return (generic_bs_r_2(NULL, (bus_space_handle_t)l, 0));
-}
-
-static inline uint32_t
-al_reg_read32(uint32_t *l)
-{
-	dsb();
-
-	return (generic_bs_r_4(NULL, (bus_space_handle_t)l, 0));
-}
-
-#define AL_DBG_LEVEL_NONE 0
-#define AL_DBG_LEVEL_ERR 1
-#define AL_DBG_LEVEL_WARN 2
-#define AL_DBG_LEVEL_INFO 3
-#define AL_DBG_LEVEL_DBG 4
-
-#define AL_DBG_LEVEL AL_DBG_LEVEL_ERR
-
-extern struct mtx al_dbg_lock;
-
-#define AL_DBG_LOCK()	mtx_lock_spin(&al_dbg_lock)
-#define AL_DBG_UNLOCK()	mtx_unlock_spin(&al_dbg_lock)
-
-/**
- * print message
- *
- * @param format The format string
- * @param ... Additional arguments
- */
-#define al_print(type, fmt, ...) 		do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_NONE) { AL_DBG_LOCK(); printf(fmt, ##__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
-
-/**
- * print error message
- *
- * @param format
- */
-#define al_err(...)			do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_ERR) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
-
-/**
- * print warning message
- *
- * @param format
- */
-#define al_warn(...)			do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_WARN) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
-
-/**
- * print info message
- *
- * @param format
- */
-#define al_info(...)			do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_INFO) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
-
-/**
- * print debug message
- *
- * @param format
- */
-#define al_dbg(...)			do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_DBG) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
-
-/**
- * Assertion
- *
- * @param condition
- */
-#define al_assert(COND)		\
-	do {			\
-		if (!(COND))	\
-			al_err(	\
-			"%s:%d:%s: Assertion failed! (%s)\n",	\
-			__FILE__, __LINE__, __func__, #COND);	\
-	} while(AL_FALSE)
-
-/**
-  * Make sure data will be visible by other masters (other CPUS and DMA).
-  * usually this is achieved by the ARM DMB instruction.
-  */
-static void al_data_memory_barrier(void);
-
-/**
-  * Make sure data will be visible by DMA masters, no restriction for other cpus
-  */
-static inline void
-al_data_memory_barrier(void)
-{
-	dsb();
-}
-
-/**
-  * Make sure data will be visible in order by other cpus masters.
-  */
-static inline void
-al_smp_data_memory_barrier(void)
-{
-	dsb();
-}
-
-/**
-  * Make sure write data will be visible in order by other cpus masters.
-  */
-static inline void
-al_local_data_memory_barrier(void)
-{
-	dsb();
-}
-
-/**
- * al_udelay - micro sec delay
- */
-#define al_udelay(u)		DELAY(u)
-
-/**
- * al_msleep - mili sec delay
- */
-#define al_msleep(m)		DELAY((m) * 1000)
-
-/**
- * swap half word to little endian
- *
- * @param x 16 bit value
- *
- * @return the value in little endian
- */
-#define swap16_to_le(x)		htole16(x)
-/**
- * swap word to little endian
- *
- * @param x 32 bit value
- *
- * @return the value in little endian
- */
-#define swap32_to_le(x)		htole32(x)
-
-/**
- * swap 8 bytes to little endian
- *
- * @param x 64 bit value
- *
- * @return the value in little endian
- */
-#define swap64_to_le(x)		htole64(x)
-
-/**
- * swap half word from little endian
- *
- * @param x 16 bit value
- *
- * @return the value in the cpu endianess
- */
-#define swap16_from_le(x)	le16toh(x)
-
-/**
- * swap word from little endian
- *
- * @param x 32 bit value
- *
- * @return the value in the cpu endianess
- */
-#define swap32_from_le(x)	le32toh(x)
-
-/**
- * swap 8 bytes from little endian
- *
- * @param x 64 bit value
- *
- * @return the value in the cpu endianess
- */
-#define swap64_from_le(x)	le64toh(x)
-
-/**
- * Memory set
- *
- * @param p memory pointer
- * @param val value for setting
- * @param cnt number of bytes to set
- */
-#define al_memset(p, val, cnt)	memset(p, val, cnt)
-
-/**
- * Memory copy
- *
- * @param p1 memory pointer
- * @param p2 memory pointer
- * @param cnt number of bytes to copy
- */
-#define al_memcpy(p1, p2, cnt)	memcpy(p1, p2, cnt)
-
-/**
- * Memory compare
- *
- * @param p1 memory pointer
- * @param p2 memory pointer
- * @param cnt number of bytes to compare
- */
-#define al_memcmp(p1, p2, cnt)	memcmp(p1, p2, cnt)
-
-/**
- * String compare
- *
- * @param s1 string pointer
- * @param s2 string pointer
- */
-#define al_strcmp(s1, s2)	strcmp(s1, s2)
-
-#define al_get_cpu_id()		0
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-/** @} end of Platform Services API group */
-#endif				/* __PLAT_SERVICES_H__ */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_plat_types.h b/sys/contrib/alpine-hal/eth/al_hal_plat_types.h
deleted file mode 100644
index 43896ae08f71..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_plat_types.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_services Platform Services API
- *  @{
- * @file   plat_api/sample/al_hal_plat_types.h
- *
- */
-
-#ifndef __PLAT_TYPES_H__
-#define __PLAT_TYPES_H__
-
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <machine/bus.h>
-#include <sys/bus.h>
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/* Basic data types */
-typedef int al_bool;		/** boolean */
-#define AL_TRUE			1
-#define AL_FALSE		0
-
-
-/* define types */
-#ifndef AL_HAVE_TYPES
-typedef unsigned char uint8_t;	/** unsigned 8 bits */
-typedef unsigned short uint16_t;	/** unsigned 16 bits */
-typedef unsigned int uint32_t;	/** unsigned 32 bits */
-typedef unsigned long long uint64_t;	/** unsigned 64 bits */
-
-typedef signed char int8_t;	/** signed 8 bits */
-typedef short int int16_t;	/** signed 16 bits */
-typedef signed int int32_t;	/** signed 32 bits */
-
-/** An unsigned int that is guaranteed to be the same size as a pointer */
-/** C99 standard */
-typedef unsigned long uintptr_t;
-#endif
-
-
-/** in LPAE mode, the address address is 40 bit, we extend it to 64 bit */
-typedef uint64_t al_phys_addr_t;
-
-/** this defines the cpu endiancess. */
-#define PLAT_ARCH_IS_LITTLE()	AL_TRUE
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-/** @} end of Platform Services API group */
-
-#endif				/* __PLAT_TYPES_H__ */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_reg_utils.h b/sys/contrib/alpine-hal/eth/al_hal_reg_utils.h
deleted file mode 100644
index f29c3c5247b5..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_reg_utils.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_common HAL Common Layer
- *  @{
- * @file   al_hal_reg_utils.h
- *
- * @brief  Register utilities used by HALs and platform layer
- *
- *
- */
-
-#ifndef __AL_HAL_REG_UTILS_H__
-#define __AL_HAL_REG_UTILS_H__
-
-#include "al_hal_plat_types.h"
-#include "al_hal_plat_services.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#define AL_BIT(b)	(1UL << (b))
-
-#define AL_ADDR_LOW(x)	((uint32_t)((al_phys_addr_t)(x)))
-#define AL_ADDR_HIGH(x)	((uint32_t)((((al_phys_addr_t)(x)) >> 16) >> 16))
-
-/** get field out of 32 bit register */
-#define AL_REG_FIELD_GET(reg, mask, shift)  (((reg) & (mask)) >> (shift))
-
-/** set field of 32 bit register */
-#define AL_REG_FIELD_SET(reg, mask, shift, val)			\
-	(reg) =							\
-		(((reg) & (~(mask))) |				\
-		((((unsigned)(val)) << (shift)) & (mask)))
-
-/** set field of 64 bit register */
-#define AL_REG_FIELD_SET_64(reg, mask, shift, val)		\
-	((reg) =						\
-		(((reg) & (~(mask))) |				\
-		((((uint64_t)(val)) << (shift)) & (mask))))
-
-/** get single bit out of 32 bit register */
-#define AL_REG_BIT_GET(reg, shift)				\
-	AL_REG_FIELD_GET(reg, AL_BIT(shift), shift)
-
-#define AL_REG_BITS_FIELD(shift, val)				\
-		(((unsigned)(val)) << (shift))
-
-/** set single bit field of 32 bit register to a given value */
-#define AL_REG_BIT_VAL_SET(reg, shift, val)				\
-	AL_REG_FIELD_SET(reg, AL_BIT(shift), shift, val)
-
-/** set single bit of 32 bit register to 1 */
-#define AL_REG_BIT_SET(reg, shift)				\
-	AL_REG_BIT_VAL_SET(reg, shift, 1)
-
-/** clear single bit of 32 bit register */
-#define AL_REG_BIT_CLEAR(reg, shift)				\
-	AL_REG_BIT_VAL_SET(reg, shift, 0)
-
-
-#define AL_BIT_MASK(n)						\
-	(AL_BIT(n) - 1)
-
-#define AL_FIELD_MASK(msb, lsb)					\
-	(AL_BIT(msb) + AL_BIT_MASK(msb) - AL_BIT_MASK(lsb))
-
-/** clear bits specified by clear_mask */
-#define AL_REG_MASK_CLEAR(reg, clear_mask)			\
-	((reg) = (((reg) & (~(clear_mask)))))
-
-/** set bits specified by clear_mask */
-#define AL_REG_MASK_SET(reg, clear_mask)			\
-	((reg) = (((reg) | (clear_mask))))
-
-
-/** clear bits specified by clear_mask, and set bits specified by set_mask */
-#define AL_REG_CLEAR_AND_SET(reg, clear_mask, set_mask)			\
-	(reg) =	(((reg) & (~(clear_mask))) | (set_mask))
-
-#define AL_ALIGN_UP(val, size)					\
-	((size) * (((val) + (size) - 1) / (size)))
-
-/** take bits selected by mask from one data, the rest from background */
-#define AL_MASK_VAL(mask, data, background)		\
-	(((mask) & (data)) | ((~mask) & (background)))
-
-/**
- * 8 bits register masked write
- *
- * @param	reg
- *	register address
- * @param	mask
- *	bits not selected (1) by mask will be left unchanged
- * @param	data
- *	data to write. bits not selected by mask ignored.
- */
-static inline void
-al_reg_write8_masked(uint8_t __iomem *reg, uint8_t mask, uint8_t data)
-{
-	uint8_t temp;
-	temp = al_reg_read8(reg);
-	al_reg_write8(reg, AL_MASK_VAL(mask, data, temp));
-}
-
-
-/**
- * 16 bits register masked write
- *
- * @param	reg
- *	register address
- * @param	mask
- *	bits not selected (1) by mask will be left unchanged
- * @param	data
- *	data to write. bits not selected by mask ignored.
- */
-static inline void
-al_reg_write16_masked(uint16_t __iomem *reg, uint16_t mask, uint16_t data)
-{
-	uint16_t temp;
-	temp = al_reg_read16(reg);
-	al_reg_write16(reg, AL_MASK_VAL(mask, data, temp));
-}
-
-
-/**
- * 32 bits register masked write
- *
- * @param	reg
- *	register address
- * @param	mask
- *	bits not selected (1) by mask will be left unchanged
- * @param	data
- *	data to write. bits not selected by mask ignored.
- */
-static inline void
-al_reg_write32_masked(uint32_t __iomem *reg, uint32_t mask, uint32_t data)
-{
-	uint32_t temp;
-	temp = al_reg_read32(reg);
-	al_reg_write32(reg, AL_MASK_VAL(mask, data, temp));
-}
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-/** @} end of Common group */
-#endif
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes.c b/sys/contrib/alpine-hal/eth/al_hal_serdes.c
deleted file mode 100644
index bb34d13c765f..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes.c
+++ /dev/null
@@ -1,3228 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#include "al_hal_serdes.h"
-#include "al_hal_serdes_regs.h"
-#include "al_hal_serdes_internal_regs.h"
-
-#define SRDS_CORE_REG_ADDR(page, type, offset)\
-	(((page) << 13) | ((type) << 12) | (offset))
-
-/* Link Training configuration */
-#define AL_SERDES_TX_DEEMPH_SUM_MAX		0x1b
-
-/* c configurations */
-#define AL_SERDES_TX_DEEMPH_C_ZERO_MAX_VAL	0x1b
-#define AL_SERDES_TX_DEEMPH_C_ZERO_MIN_VAL	0
-#define AL_SERDES_TX_DEEMPH_C_ZERO_PRESET	AL_SERDES_TX_DEEMPH_C_ZERO_MAX_VAL
-
-/* c(+1) configurations */
-#define AL_SERDES_TX_DEEMPH_C_PLUS_MAX_VAL	0x9
-#define AL_SERDES_TX_DEEMPH_C_PLUS_MIN_VAL	0
-#define AL_SERDES_TX_DEEMPH_C_PLUS_PRESET	AL_SERDES_TX_DEEMPH_C_PLUS_MIN_VAL
-
-/* c(-1) configurations */
-#define AL_SERDES_TX_DEEMPH_C_MINUS_MAX_VAL	0x6
-#define AL_SERDES_TX_DEEMPH_C_MINUS_MIN_VAL	0
-#define AL_SERDES_TX_DEEMPH_C_MINUS_PRESET	AL_SERDES_TX_DEEMPH_C_MINUS_MIN_VAL
-
-/* Rx equal total delay = MDELAY * TRIES */
-#define AL_SERDES_RX_EQUAL_MDELAY		10
-#define AL_SERDES_RX_EQUAL_TRIES		50
-
-/* Rx eye calculation delay = MDELAY * TRIES */
-#define AL_SERDES_RX_EYE_CAL_MDELAY		50
-#define AL_SERDES_RX_EYE_CAL_TRIES		70
-
-
-/**
- * Prototypes for _lane_ compatibility
- */
-int al_serdes_lane_read(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	enum al_serdes_reg_type	type,
-	uint16_t		offset,
-	uint8_t			*data);
-
-int al_serdes_lane_write(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	enum al_serdes_reg_type	type,
-	uint16_t		offset,
-	uint8_t			data);
-
-
-/**
- * SERDES core reg/lane read
- */
-static inline uint8_t al_serdes_grp_reg_read(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_reg_page		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset);
-
-static inline uint8_t al_serdes_grp_lane_read(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset);
-
-/**
- * SERDES core reg/lane write
- */
-static inline void al_serdes_grp_reg_write(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_reg_page		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				data);
-
-static inline void al_serdes_grp_lane_write(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		lane,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				data);
-
-/**
- * SERDES core masked reg/lane write
- */
-static inline void al_serdes_grp_reg_masked_write(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_reg_page		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				mask,
-	uint8_t				data);
-
-/**
- * Lane Rx rate change software flow disable
- */
-static void _al_serdes_lane_rx_rate_change_sw_flow_dis(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		lane);
-
-/**
- * Group Rx rate change software flow enable if all conditions met
- */
-static void al_serdes_group_rx_rate_change_sw_flow_dis(
-	struct al_serdes_group_info	*grp_info);
-
-/**
- * Lane Rx rate change software flow enable if all conditions met
- */
-static void _al_serdes_lane_rx_rate_change_sw_flow_en_cond(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		lane);
-
-/**
- * Group Rx rate change software flow enable if all conditions met
- */
-static void al_serdes_group_rx_rate_change_sw_flow_en_cond(
-	struct al_serdes_group_info	*grp_info);
-
-
-static inline void al_serdes_grp_lane_masked_write(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		lane,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				mask,
-	uint8_t				data);
-
-/******************************************************************************/
-/******************************************************************************/
-int al_serdes_handle_init(
-	void __iomem			*serdes_regs_base,
-	struct al_serdes_obj		*obj)
-{
-	int i;
-
-	al_dbg(
-		"%s(%p, %p)\n",
-		__func__,
-		serdes_regs_base,
-		obj);
-
-	al_assert(serdes_regs_base);
-
-	for (i = 0; i < AL_SRDS_NUM_GROUPS; i++) {
-		obj->grp_info[i].pobj = obj;
-
-		obj->grp_info[i].regs_base =
-			&((struct al_serdes_regs *)serdes_regs_base)[i];
-	}
-
-	return 0;
-}
-
-/******************************************************************************/
-/******************************************************************************/
-int al_serdes_reg_read(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_reg_page	page,
-	enum al_serdes_reg_type	type,
-	uint16_t		offset,
-	uint8_t			*data)
-{
-	int status = 0;
-
-	al_dbg(
-		"%s(%p, %d, %d, %d, %u)\n",
-		__func__,
-		obj,
-		grp,
-		page,
-		type,
-		offset);
-
-	al_assert(obj);
-	al_assert(data);
-	al_assert(((int)grp) >= AL_SRDS_GRP_A);
-	al_assert(((int)grp) <= AL_SRDS_GRP_D);
-	al_assert(((int)page) >= AL_SRDS_REG_PAGE_0_LANE_0);
-	al_assert(((int)page) <= AL_SRDS_REG_PAGE_4_COMMON);
-	al_assert(((int)type) >= AL_SRDS_REG_TYPE_PMA);
-	al_assert(((int)type) <= AL_SRDS_REG_TYPE_PCS);
-
-	*data = al_serdes_grp_reg_read(
-		&obj->grp_info[grp],
-		page,
-		type,
-		offset);
-
-	al_dbg(
-		"%s: return(%u)\n",
-		__func__,
-		*data);
-
-	return status;
-}
-
-int al_serdes_lane_read(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	enum al_serdes_reg_type	type,
-	uint16_t		offset,
-	uint8_t			*data)
-{
-	return al_serdes_reg_read(obj, grp, (enum al_serdes_reg_page)lane, type,
-				  offset, data);
-}
-/******************************************************************************/
-/******************************************************************************/
-int al_serdes_reg_write(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_reg_page	page,
-	enum al_serdes_reg_type	type,
-	uint16_t		offset,
-	uint8_t			data)
-{
-	int status = 0;
-
-	al_dbg(
-		"%s(%p, %d, %d, %d, %u, %u)\n",
-		__func__,
-		obj,
-		grp,
-		page,
-		type,
-		offset,
-		data);
-
-	al_assert(obj);
-	al_assert(((int)grp) >= AL_SRDS_GRP_A);
-	al_assert(((int)grp) <= AL_SRDS_GRP_D);
-	al_assert(((int)page) >= AL_SRDS_REG_PAGE_0_LANE_0);
-	al_assert(((int)page) <= AL_SRDS_REG_PAGE_0123_LANES_0123);
-	al_assert(((int)type) >= AL_SRDS_REG_TYPE_PMA);
-	al_assert(((int)type) <= AL_SRDS_REG_TYPE_PCS);
-
-	al_serdes_grp_reg_write(
-		&obj->grp_info[grp],
-		page,
-		type,
-		offset,
-		data);
-
-	return status;
-}
-
-int al_serdes_lane_write(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	enum al_serdes_reg_type	type,
-	uint16_t		offset,
-	uint8_t			data)
-{
-	return al_serdes_reg_write(obj, grp, (enum al_serdes_reg_page)lane,
-				   type, offset, data);
-}
-/******************************************************************************/
-/******************************************************************************/
-#if (SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM != SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM)
-#error "Wrong assumption!"
-#endif
-#if (SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM != SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM)
-#error "Wrong assumption!"
-#endif
-#if (SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM != SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM)
-#error "Wrong assumption!"
-#endif
-#if (SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM != SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM)
-#error "Wrong assumption!"
-#endif
-#if (SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM != SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM)
-#error "Wrong assumption!"
-#endif
-#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_LB_LOCWREN_REG_NUM)
-#error "Wrong assumption!"
-#endif
-#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM)
-#error "Wrong assumption!"
-#endif
-#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM)
-#error "Wrong assumption!"
-#endif
-#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM)
-#error "Wrong assumption!"
-#endif
-#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM)
-#error "Wrong assumption!"
-#endif
-void al_serdes_bist_overrides_enable(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_rate	rate)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-	int i;
-
-	uint8_t rx_rate_val;
-	uint8_t tx_rate_val;
-
-	switch (rate) {
-	case AL_SRDS_RATE_1_8:
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8;
-		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8;
-		break;
-	case AL_SRDS_RATE_1_4:
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4;
-		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4;
-		break;
-	case AL_SRDS_RATE_1_2:
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2;
-		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2;
-		break;
-	case AL_SRDS_RATE_FULL:
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1;
-		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1;
-		break;
-	default:
-		al_err("%s: invalid rate (%d)\n",  __func__, rate);
-		al_assert(0);
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1;
-		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1;
-	}
-
-	for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
-		al_serdes_grp_reg_masked_write(
-			grp_info,
-			(enum al_serdes_reg_page)i,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM,
-			SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK |
-			SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK,
-			SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20 |
-			SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20);
-
-		al_serdes_grp_reg_masked_write(
-			grp_info,
-			(enum al_serdes_reg_page)i,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM,
-			SERDES_IREG_FLD_PCSRX_DIVRATE_MASK |
-			SERDES_IREG_FLD_PCSTX_DIVRATE_MASK,
-			rx_rate_val | tx_rate_val);
-	}
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN |
-		SERDES_IREG_FLD_CMNPCS_LOCWREN |
-		SERDES_IREG_FLD_CMNPCSBIST_LOCWREN |
-		SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN,
-		0);
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN |
-		SERDES_IREG_FLD_CMNPCS_LOCWREN |
-		SERDES_IREG_FLD_CMNPCSBIST_LOCWREN |
-		SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN,
-		0);
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_PCS_LOCWREN,
-		0);
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM,
-		SERDES_IREG_FLD_CMNPCS_TXENABLE,
-		SERDES_IREG_FLD_CMNPCS_TXENABLE);
-
-	for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
-		al_serdes_grp_reg_masked_write(
-			grp_info,
-			(enum al_serdes_reg_page)i,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM,
-			SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN |
-			SERDES_IREG_FLD_LB_LOCWREN |
-			SERDES_IREG_FLD_PCSRX_LOCWREN |
-			SERDES_IREG_FLD_PCSRXBIST_LOCWREN |
-			SERDES_IREG_FLD_PCSRXEQ_LOCWREN |
-			SERDES_IREG_FLD_PCSTX_LOCWREN,
-			0);
-
-		al_serdes_grp_reg_masked_write(
-			grp_info,
-			(enum al_serdes_reg_page)i,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM,
-			SERDES_IREG_FLD_PCSTXBIST_LOCWREN,
-			0);
-
-		al_serdes_grp_reg_masked_write(
-			grp_info,
-			(enum al_serdes_reg_page)i,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
-			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN,
-			0);
-
-		al_serdes_grp_reg_masked_write(
-			grp_info,
-			(enum al_serdes_reg_page)i,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM,
-			SERDES_IREG_FLD_RXLOCK2REF_OVREN,
-			SERDES_IREG_FLD_RXLOCK2REF_OVREN);
-	}
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_bist_overrides_disable(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-	int i;
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_CMNPCSBIST_LOCWREN,
-		SERDES_IREG_FLD_CMNPCSBIST_LOCWREN);
-
-	for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
-		al_serdes_grp_reg_masked_write(
-			grp_info,
-			(enum al_serdes_reg_page)i,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM,
-			SERDES_IREG_FLD_LB_LOCWREN |
-			SERDES_IREG_FLD_PCSRXBIST_LOCWREN,
-			SERDES_IREG_FLD_LB_LOCWREN |
-			SERDES_IREG_FLD_PCSRXBIST_LOCWREN);
-
-		al_serdes_grp_reg_masked_write(
-			grp_info,
-			(enum al_serdes_reg_page)i,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM,
-			SERDES_IREG_FLD_PCSTXBIST_LOCWREN,
-			SERDES_IREG_FLD_PCSTXBIST_LOCWREN);
-	}
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_rx_rate_change(
-	struct al_serdes_obj *obj,
-	enum al_serdes_group grp,
-	enum al_serdes_rate rate)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-	int i;
-
-	uint8_t rx_rate_val;
-
-	switch (rate) {
-	case AL_SRDS_RATE_1_8:
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8;
-		break;
-	case AL_SRDS_RATE_1_4:
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4;
-		break;
-	case AL_SRDS_RATE_1_2:
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2;
-		break;
-	case AL_SRDS_RATE_FULL:
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1;
-		break;
-	default:
-		al_err("%s: invalid rate (%d)\n",  __func__, rate);
-		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1;
-		break;
-	}
-
-	for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
-		al_serdes_grp_reg_masked_write(
-				   grp_info,
-				   (enum al_serdes_reg_page)i,
-				   AL_SRDS_REG_TYPE_PMA,
-				   SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM,
-				   SERDES_IREG_FLD_PCSRX_DIVRATE_MASK,
-				   rx_rate_val);
-	}
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_group_pm_set(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_pm	pm)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	uint8_t pm_val;
-
-	switch (pm) {
-	case AL_SRDS_PM_PD:
-		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD;
-		break;
-	case AL_SRDS_PM_P2:
-		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2;
-		break;
-	case AL_SRDS_PM_P1:
-		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1;
-		break;
-	case AL_SRDS_PM_P0S:
-		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S;
-		break;
-	case AL_SRDS_PM_P0:
-		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0;
-		break;
-	default:
-		al_err("%s: invalid power mode (%d)\n",  __func__, pm);
-		al_assert(0);
-		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0;
-	}
-
-	if (pm == AL_SRDS_PM_PD)
-		al_serdes_group_rx_rate_change_sw_flow_dis(grp_info);
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM,
-		SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK,
-		pm_val);
-
-	if (pm != AL_SRDS_PM_PD)
-		al_serdes_group_rx_rate_change_sw_flow_en_cond(grp_info);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_lane_rx_rate_change_sw_flow_en(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane)
-{
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 201, 0xfc);
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 202, 0xff);
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 203, 0xff);
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 204, 0xff);
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f);
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 205, 0xff);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_lane_rx_rate_change_sw_flow_dis(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane)
-{
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_lane_pcie_rate_override_enable_set(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	enum al_serdes_lane		lane,
-	al_bool				en)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PCS,
-		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM,
-		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA,
-		en ? SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA : 0);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-al_bool al_serdes_lane_pcie_rate_override_is_enabled(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	enum al_serdes_lane		lane)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	return (al_serdes_grp_lane_read(
-		grp_info,
-		lane,
-		AL_SRDS_REG_TYPE_PCS,
-		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM) &
-		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA) ? AL_TRUE : AL_FALSE;
-}
-
-/******************************************************************************/
-/******************************************************************************/
-enum al_serdes_pcie_rate al_serdes_lane_pcie_rate_get(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	return (al_serdes_grp_reg_read(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PCS,
-		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM) &
-		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK) >>
-		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT;
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_lane_pcie_rate_set(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	enum al_serdes_lane		lane,
-	enum al_serdes_pcie_rate	rate)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PCS,
-		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM,
-		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK,
-		rate << SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_lane_pm_set(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	enum al_serdes_pm	rx_pm,
-	enum al_serdes_pm	tx_pm)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	uint8_t rx_pm_val;
-	uint8_t tx_pm_val;
-
-	switch (rx_pm) {
-	case AL_SRDS_PM_PD:
-		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD;
-		break;
-	case AL_SRDS_PM_P2:
-		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2;
-		break;
-	case AL_SRDS_PM_P1:
-		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1;
-		break;
-	case AL_SRDS_PM_P0S:
-		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S;
-		break;
-	case AL_SRDS_PM_P0:
-		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0;
-		break;
-	default:
-		al_err("%s: invalid rx power mode (%d)\n",  __func__, rx_pm);
-		al_assert(0);
-		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0;
-	}
-
-	switch (tx_pm) {
-	case AL_SRDS_PM_PD:
-		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD;
-		break;
-	case AL_SRDS_PM_P2:
-		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2;
-		break;
-	case AL_SRDS_PM_P1:
-		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1;
-		break;
-	case AL_SRDS_PM_P0S:
-		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S;
-		break;
-	case AL_SRDS_PM_P0:
-		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0;
-		break;
-	default:
-		al_err("%s: invalid tx power mode (%d)\n",  __func__, tx_pm);
-		al_assert(0);
-		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0;
-	}
-
-	if (rx_pm == AL_SRDS_PM_PD)
-		_al_serdes_lane_rx_rate_change_sw_flow_dis(grp_info, lane);
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM,
-		SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK,
-		rx_pm_val);
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM,
-		SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK,
-		tx_pm_val);
-
-	if (rx_pm != AL_SRDS_PM_PD)
-		_al_serdes_lane_rx_rate_change_sw_flow_en_cond(grp_info, lane);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_pma_hard_reset_group(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	al_bool			enable)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	if (enable)
-		al_serdes_group_rx_rate_change_sw_flow_dis(grp_info);
-
-	/* Enable Hard Reset Override */
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS);
-
-	/* Assert/Deassert Hard Reset Override */
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK,
-		enable ?
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT :
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT);
-
-	if (!enable)
-		al_serdes_group_rx_rate_change_sw_flow_en_cond(grp_info);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_pma_hard_reset_lane(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	al_bool			enable)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	if (enable)
-		_al_serdes_lane_rx_rate_change_sw_flow_dis(grp_info, lane);
-
-	/* Enable Hard Reset Override */
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS);
-
-	/* Assert/Deassert Hard Reset Override */
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM,
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK,
-		enable ?
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT :
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT);
-
-	if (!enable)
-		_al_serdes_lane_rx_rate_change_sw_flow_en_cond(grp_info, lane);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-#if	(SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM !=\
-	SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM) ||\
-	(SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM !=\
-	SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM) ||\
-	(SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM !=\
-	 SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM) ||\
-	(SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM !=\
-	 SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM)
-#error Wrong assumption
-#endif
-
-void al_serdes_loopback_control(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	enum al_serdes_lb_mode	mode)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-	uint8_t val = 0;
-
-	switch (mode) {
-	case AL_SRDS_LB_MODE_OFF:
-		break;
-	case AL_SRDS_LB_MODE_PMA_IO_UN_TIMED_RX_TO_TX:
-		val = SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN;
-		break;
-	case AL_SRDS_LB_MODE_PMA_INTERNALLY_BUFFERED_SERIAL_TX_TO_RX:
-		val = SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN;
-		break;
-	case AL_SRDS_LB_MODE_PMA_SERIAL_TX_IO_TO_RX_IO:
-		val = SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN;
-		break;
-	case AL_SRDS_LB_MODE_PMA_PARALLEL_RX_TO_TX:
-		val = SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN |
-			SERDES_IREG_FLD_LB_CDRCLK2TXEN;
-		break;
-	default:
-		al_err("%s: invalid mode (%d)\n",  __func__, mode);
-		al_assert(0);
-	}
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM,
-		SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN |
-		SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN |
-		SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN |
-		SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN |
-		SERDES_IREG_FLD_LB_CDRCLK2TXEN,
-		val);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_bist_pattern_select(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	enum al_serdes_bist_pattern	pattern,
-	uint8_t				*user_data)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-	uint8_t val = 0;
-
-	switch (pattern) {
-	case AL_SRDS_BIST_PATTERN_USER:
-		al_assert(user_data);
-		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER;
-		break;
-	case AL_SRDS_BIST_PATTERN_PRBS7:
-		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7;
-		break;
-	case AL_SRDS_BIST_PATTERN_PRBS23:
-		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23;
-		break;
-	case AL_SRDS_BIST_PATTERN_PRBS31:
-		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31;
-		break;
-	case AL_SRDS_BIST_PATTERN_CLK1010:
-		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010;
-		break;
-	default:
-		al_err("%s: invalid pattern (%d)\n", __func__, pattern);
-		al_assert(0);
-	}
-
-	if (pattern == AL_SRDS_BIST_PATTERN_USER) {
-		int i;
-
-		for (i = 0; i < SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES; i++)
-			al_serdes_grp_reg_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(i),
-				user_data[i]);
-	}
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM,
-		SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK,
-		val);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_bist_tx_enable(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	al_bool			enable)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM,
-		SERDES_IREG_FLD_PCSTXBIST_EN,
-		enable ? SERDES_IREG_FLD_PCSTXBIST_EN : 0);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_bist_tx_err_inject(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM,
-		SERDES_IREG_FLD_TXBIST_BITERROR_EN,
-		SERDES_IREG_FLD_TXBIST_BITERROR_EN);
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM,
-		SERDES_IREG_FLD_TXBIST_BITERROR_EN,
-		0);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-void al_serdes_bist_rx_enable(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	al_bool			enable)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	al_serdes_grp_reg_masked_write(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM,
-		SERDES_IREG_FLD_PCSRXBIST_EN,
-		enable ? SERDES_IREG_FLD_PCSRXBIST_EN : 0);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-#if	(SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM !=\
-	SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM)
-#error Wrong assumption
-#endif
-
-void al_serdes_bist_rx_status(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	al_bool			*is_locked,
-	al_bool			*err_cnt_overflow,
-	uint16_t		*err_cnt)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-	uint8_t status_reg_val;
-	uint16_t err_cnt_msb_reg_val;
-	uint16_t err_cnt_lsb_reg_val;
-
-	status_reg_val = al_serdes_grp_reg_read(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM);
-
-	err_cnt_msb_reg_val = al_serdes_grp_reg_read(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM);
-
-	err_cnt_lsb_reg_val = al_serdes_grp_reg_read(
-		grp_info,
-		(enum al_serdes_reg_page)lane,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM);
-
-	*is_locked =
-		(status_reg_val & SERDES_IREG_FLD_RXBIST_RXLOCKED) ?
-		AL_TRUE : AL_FALSE;
-
-	*err_cnt_overflow =
-		(status_reg_val & SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW) ?
-		AL_TRUE : AL_FALSE;
-
-	*err_cnt = (err_cnt_msb_reg_val << 8) + err_cnt_lsb_reg_val;
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static inline uint8_t al_serdes_grp_reg_read(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_reg_page		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset)
-{
-	al_reg_write32(
-		&grp_info->regs_base->gen.reg_addr,
-		SRDS_CORE_REG_ADDR(page, type, offset));
-
-	return al_reg_read32(&grp_info->regs_base->gen.reg_data);
-}
-
-static inline uint8_t al_serdes_grp_lane_read(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset)
-{
-	return al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)page,
-				      type, offset);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static inline void al_serdes_grp_reg_write(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_reg_page		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				data)
-{
-	al_reg_write32(
-		&grp_info->regs_base->gen.reg_addr,
-		SRDS_CORE_REG_ADDR(page, type, offset));
-
-	al_reg_write32(&grp_info->regs_base->gen.reg_data, data);
-}
-
-
-static inline void al_serdes_grp_lane_write(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		lane,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				data)
-{
-	al_serdes_grp_reg_write(grp_info, (enum al_serdes_reg_page)lane,
-				type, offset, data);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static inline void al_serdes_ns_delay(int cnt)
-{
-	al_udelay((cnt + 999) / 1000);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static inline void al_serdes_grp_reg_masked_write(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_reg_page		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				mask,
-	uint8_t				data)
-{
-	uint8_t val;
-	enum al_serdes_reg_page	start_page = page;
-	enum al_serdes_reg_page	end_page   = page;
-	enum al_serdes_reg_page	iter_page;
-
-	if (page == AL_SRDS_REG_PAGE_0123_LANES_0123) {
-		start_page = AL_SRDS_REG_PAGE_0_LANE_0;
-		end_page   = AL_SRDS_REG_PAGE_3_LANE_3;
-	}
-
-	for(iter_page = start_page; iter_page <= end_page; ++iter_page) {
-		val = al_serdes_grp_reg_read(grp_info, iter_page, type, offset);
-		val &= ~mask;
-		val |= data;
-		al_serdes_grp_reg_write(grp_info, iter_page, type, offset, val);
-	}
-}
-
-static inline void al_serdes_grp_lane_masked_write(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		lane,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				mask,
-	uint8_t				data)
-{
-	al_serdes_grp_reg_masked_write(grp_info, (enum al_serdes_reg_page)lane,
-				       type, offset, mask, data);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static void _al_serdes_lane_rx_rate_change_sw_flow_dis(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		lane)
-{
-	al_bool lane_sw_flow_enabled;
-
-	al_assert(lane != AL_SRDS_LANES_0123);
-
-	lane_sw_flow_enabled =
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 201) == 0xfc) &&
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 202) == 0xff) &&
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 203) == 0xff) &&
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 204) == 0xff) &&
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 205) == 0xff);
-
-	/**
-	 * Disable the Rx rate change software flow by clearing bit 7 of lane PMA register 205
-	 * (RSTPDOVR_RX_OVREN)
-	 */
-	if (lane_sw_flow_enabled) {
-		al_dbg("%s(%d): actually disabling\n", __func__, lane);
-		al_serdes_grp_reg_masked_write(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 205, 0x80, 0x00);
-	}
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static void al_serdes_group_rx_rate_change_sw_flow_dis(
-	struct al_serdes_group_info	*grp_info)
-{
-	int lane;
-
-	for (lane = AL_SRDS_LANE_0; lane < AL_SRDS_NUM_LANES; lane++)
-		_al_serdes_lane_rx_rate_change_sw_flow_dis(grp_info, lane);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static void _al_serdes_lane_rx_rate_change_sw_flow_en_cond(
-	struct al_serdes_group_info	*grp_info,
-	enum al_serdes_lane		lane)
-{
-	al_bool lane_sw_flow_almost_enabled;
-	al_bool group_reset_enabled;
-	al_bool lane_reset_enabled;
-	al_bool group_pd_enabled;
-	al_bool lane_pd_enabled;
-
-	al_assert(lane != AL_SRDS_LANES_0123);
-
-	lane_sw_flow_almost_enabled =
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 201) == 0xfc) &&
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 202) == 0xff) &&
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 203) == 0xff) &&
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 204) == 0xff) &&
-		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 205) == 0x7f);
-
-	group_reset_enabled =
-		((al_serdes_grp_reg_read(
-			grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM) &
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK) ==
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS) &&
-		((al_serdes_grp_reg_read(
-			grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM) &
-			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK) ==
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT);
-
-	lane_reset_enabled =
-		((al_serdes_grp_reg_read(
-			grp_info, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM) &
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK) ==
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS) &&
-		((al_serdes_grp_reg_read(
-			grp_info, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM) &
-			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK) ==
-		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT);
-
-	group_pd_enabled =
-		(al_serdes_grp_reg_read(
-			grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM) &
-		SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK) ==
-		SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD;
-
-	lane_pd_enabled =
-		(al_serdes_grp_reg_read(
-			grp_info, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM) &
-		SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK) ==
-		SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD;
-
-	/**
-	 * Enable the Rx rate change software flow by setting bit 7 of lane PMA register 205
-	 * (RSTPDOVR_RX_OVREN)
-	 */
-	if (lane_sw_flow_almost_enabled && !group_reset_enabled && !lane_reset_enabled &&
-		!group_pd_enabled && !lane_pd_enabled) {
-		al_dbg("%s(%d): actually enabling\n", __func__, lane);
-
-		al_serdes_ns_delay(500);
-		al_serdes_grp_reg_masked_write(grp_info, (enum al_serdes_reg_page)lane,
-			AL_SRDS_REG_TYPE_PMA, 205, 0x80, 0x80);
-	}
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static void al_serdes_group_rx_rate_change_sw_flow_en_cond(
-	struct al_serdes_group_info	*grp_info)
-{
-	int lane;
-
-	for (lane = AL_SRDS_LANE_0; lane < AL_SRDS_NUM_LANES; lane++)
-		_al_serdes_lane_rx_rate_change_sw_flow_en_cond(grp_info, lane);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-int al_serdes_eye_measure_run(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		uint32_t		timeout,
-		unsigned int		*value)
-{
-	uint32_t reg = 0;
-	uint32_t i;
-	struct serdes_lane *lane_regs;
-
-	lane_regs = &obj->grp_info[grp].regs_base->lane[lane];
-
-	al_reg_write32(&lane_regs->ictl_multi_rxeq,
-		       SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A);
-
-	for (i = 0 ; i < timeout ; i++) {
-		reg = al_reg_read32(&lane_regs->octl_multi);
-
-		if (reg & SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A)
-			break;
-
-		al_msleep(10);
-	}
-
-	if (i == timeout) {
-		al_err("%s: measure eye failed on timeout\n", __func__);
-		return -ETIMEDOUT;
-	}
-
-	*value = al_reg_read32(&lane_regs->odat_multi_rxeq);
-
-	al_reg_write32(&lane_regs->ictl_multi_rxeq, 0);
-
-	return 0;
-}
-
-/******************************************************************************/
-/******************************************************************************/
-int al_serdes_eye_diag_sample(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		unsigned int		x,
-		int			y,
-		unsigned int		timeout,
-		unsigned int		*value)
-{
-	enum al_serdes_reg_page	page = (enum al_serdes_reg_page)lane;
-	struct al_serdes_group_info *grp_info;
-	uint32_t i;
-	uint8_t sample_count_orig_msb;
-	uint8_t sample_count_orig_lsb;
-
-	al_assert(obj);
-	al_assert(((int)grp) >= AL_SRDS_GRP_A);
-	al_assert(((int)grp) <= AL_SRDS_GRP_D);
-	al_assert(((int)page) >= AL_SRDS_REG_PAGE_0_LANE_0);
-	al_assert(((int)page) <= AL_SRDS_REG_PAGE_0123_LANES_0123);
-
-	grp_info = &obj->grp_info[grp];
-
-	/* Obtain sample count by reading RXCALROAMEYEMEAS_COUNT */
-	sample_count_orig_msb = al_serdes_grp_reg_read(grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM);
-	sample_count_orig_lsb = al_serdes_grp_reg_read(grp_info,
-		AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM);
-
-	/* Set sample count to ~100000 samples */
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM, 0x13);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM, 0x88);
-
-	/* BER Contour Overwrite */
-	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
-		0);
-	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN,
-		0);
-	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN,
-		0);
-
-	/* RXROAM_XORBITSEL = 0x1 or 0x0 */
-	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
-		SERDES_IREG_FLD_RXROAM_XORBITSEL,
-		SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND);
-
-	/* Set X */
-	al_serdes_grp_reg_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM, x);
-
-	/* Set Y */
-	al_serdes_grp_reg_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM,
-		y < 32 ? 31 - y : y + 1);
-
-	/* Start Measurement by setting RXCALROAMEYEMEASIN_CYCLEEN = 0x1 */
-	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START);
-
-	/* Check RXCALROAMEYEMEASDONE Signal (Polling Until 0x1) */
-	for (i = 0 ; i < timeout ; i++) {
-		if (al_serdes_grp_reg_read(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM) &
-			SERDES_IREG_FLD_RXCALROAMEYEMEASDONE)
-			break;
-		al_udelay(1);
-	}
-	if (i == timeout) {
-		al_err("%s: eye diagram sampling timed out!\n", __func__);
-		return -ETIMEDOUT;
-	}
-
-	/* Stop Measurement by setting RXCALROAMEYEMEASIN_CYCLEEN = 0x0 */
-	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START,
-		0);
-
-	/* Obtain Error Counts by reading RXCALROAMEYEMEAS_ACC */
-	*value = ((unsigned int)al_serdes_grp_reg_read(grp_info, page,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM)) << 8 |
-		al_serdes_grp_reg_read(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM);
-
-	/* BER Contour Overwrite */
-	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN);
-	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN,
-		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN);
-	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
-		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN,
-		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN);
-
-	/* Restore sample count */
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM,
-		sample_count_orig_msb);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM,
-		sample_count_orig_lsb);
-
-	return 0;
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static void al_serdes_tx_deemph_set(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		uint32_t		c_zero,
-		uint32_t		c_plus_1,
-		uint32_t		c_minus_1)
-{
-	al_serdes_grp_lane_masked_write(
-			&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_TX_DRV_1_REG_NUM,
-			SERDES_IREG_TX_DRV_1_LEVN_MASK,
-			((c_zero + c_plus_1 + c_minus_1)
-				<< SERDES_IREG_TX_DRV_1_LEVN_SHIFT));
-
-	al_serdes_grp_lane_masked_write(
-			&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_TX_DRV_2_REG_NUM,
-			SERDES_IREG_TX_DRV_2_LEVNM1_MASK,
-			(c_plus_1 << SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT));
-
-	al_serdes_grp_lane_masked_write(
-			&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_TX_DRV_3_REG_NUM,
-			SERDES_IREG_TX_DRV_3_LEVNP1_MASK,
-			(c_minus_1 << SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT));
-}
-
-static void al_serdes_tx_deemph_get(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		uint32_t		*c_zero,
-		uint32_t		*c_plus_1,
-		uint32_t		*c_minus_1)
-{
-	uint32_t reg = 0;
-
-	reg = al_serdes_grp_lane_read(
-			&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_TX_DRV_2_REG_NUM);
-
-	*c_plus_1 = ((reg & SERDES_IREG_TX_DRV_2_LEVNM1_MASK) >>
-					SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT);
-
-	reg = al_serdes_grp_lane_read(
-			&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_TX_DRV_3_REG_NUM);
-
-	*c_minus_1 = ((reg & SERDES_IREG_TX_DRV_3_LEVNP1_MASK) >>
-					SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT);
-
-	reg = al_serdes_grp_lane_read(
-			&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_TX_DRV_1_REG_NUM);
-
-	*c_zero = (((reg & SERDES_IREG_TX_DRV_1_LEVN_MASK) >>
-		SERDES_IREG_TX_DRV_1_LEVN_SHIFT) - *c_plus_1 - *c_minus_1);
-}
-
-al_bool al_serdes_tx_deemph_inc(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		enum al_serdes_tx_deemph_param param)
-{
-	al_bool ret = AL_TRUE;
-	uint32_t c0;
-	uint32_t c1;
-	uint32_t c_1;
-
-	al_serdes_tx_deemph_get(obj, grp, lane, &c0, &c1, &c_1);
-
-	al_dbg("%s: current txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
-		__func__, c0, c1, c_1);
-
-	switch (param) {
-	case AL_SERDES_TX_DEEMP_C_ZERO:
-
-		if (c0 == AL_SERDES_TX_DEEMPH_C_ZERO_MAX_VAL)
-			return AL_FALSE;
-
-		c0++;
-
-		break;
-	case AL_SERDES_TX_DEEMP_C_PLUS:
-
-		if (c1 == AL_SERDES_TX_DEEMPH_C_PLUS_MAX_VAL)
-			return AL_FALSE;
-
-		c1++;
-
-		break;
-	case AL_SERDES_TX_DEEMP_C_MINUS:
-
-		if (c_1 == AL_SERDES_TX_DEEMPH_C_MINUS_MAX_VAL)
-			return AL_FALSE;
-
-		c_1++;
-
-		break;
-	}
-
-	if ((c0 + c1 + c_1) > AL_SERDES_TX_DEEMPH_SUM_MAX) {
-		al_dbg("%s: sum of all tx de-emphasis over the max limit\n",
-			__func__);
-
-		return AL_FALSE;
-	}
-
-	al_dbg("%s: new txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
-		__func__, c0, c1, c_1);
-
-	al_serdes_tx_deemph_set(obj, grp, lane, c0, c1, c_1);
-
-	return ret;
-}
-
-al_bool al_serdes_tx_deemph_dec(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		enum al_serdes_tx_deemph_param param)
-{
-	al_bool ret = AL_TRUE;
-	uint32_t c0;
-	uint32_t c1;
-	uint32_t c_1;
-
-	al_serdes_tx_deemph_get(obj, grp, lane, &c0, &c1, &c_1);
-
-	al_dbg("%s: current txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
-		__func__, c0, c1, c_1);
-
-	switch (param) {
-	case AL_SERDES_TX_DEEMP_C_ZERO:
-
-		if (c0 == AL_SERDES_TX_DEEMPH_C_ZERO_MIN_VAL)
-			return AL_FALSE;
-
-		c0--;
-
-		break;
-	case AL_SERDES_TX_DEEMP_C_PLUS:
-
-		if (c1 == AL_SERDES_TX_DEEMPH_C_PLUS_MIN_VAL)
-			return AL_FALSE;
-
-		c1--;
-
-		break;
-	case AL_SERDES_TX_DEEMP_C_MINUS:
-
-		if (c_1 == AL_SERDES_TX_DEEMPH_C_MINUS_MIN_VAL)
-			return AL_FALSE;
-
-		c_1--;
-
-		break;
-	}
-
-	al_dbg("%s: new txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
-		__func__, c0, c1, c_1);
-
-	al_serdes_tx_deemph_set(obj, grp, lane, c0, c1, c_1);
-
-	return ret;
-}
-
-void al_serdes_tx_deemph_preset(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane)
-{
-	uint32_t c0;
-	uint32_t c1;
-	uint32_t c_1;
-
-	c0 = AL_SERDES_TX_DEEMPH_C_ZERO_PRESET;
-
-	c1 = AL_SERDES_TX_DEEMPH_C_PLUS_PRESET;
-
-	c_1 = AL_SERDES_TX_DEEMPH_C_MINUS_PRESET;
-
-	al_dbg("preset: new txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
-		c0, c1, c_1);
-
-	al_serdes_tx_deemph_set(obj, grp, lane, c0, c1, c_1);
-}
-
-al_bool al_serdes_signal_is_detected(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane)
-{
-	uint32_t reg = 0;
-
-	reg = al_serdes_grp_lane_read(
-			&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXRANDET_REG_NUM);
-
-	return ((reg & SERDES_IREG_FLD_RXRANDET_STAT) ? AL_TRUE : AL_FALSE);
-}
-
-void al_serdes_tx_advanced_params_set(struct al_serdes_obj		*obj,
-				      enum al_serdes_group		grp,
-				      enum al_serdes_lane		lane,
-				      struct al_serdes_adv_tx_params	*params)
-{
-	uint8_t reg = 0;
-
-	if(!params->override) {
-		al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
-			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN,
-			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN);
-
-		return;
-	}
-
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
-			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN,
-			0);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_TX_DRV_1_HLEV_MASK,
-			 SERDES_IREG_TX_DRV_1_HLEV_SHIFT,
-			 params->amp);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_TX_DRV_1_LEVN_MASK,
-			 SERDES_IREG_TX_DRV_1_LEVN_SHIFT,
-			 params->total_driver_units);
-
-	al_serdes_grp_lane_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_TX_DRV_1_REG_NUM,
-				reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_TX_DRV_2_LEVNM1_MASK,
-			 SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT,
-			 params->c_plus_1);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_TX_DRV_2_LEVNM2_MASK,
-			 SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT,
-			 params->c_plus_2);
-
-	al_serdes_grp_lane_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_TX_DRV_2_REG_NUM,
-				reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_TX_DRV_3_LEVNP1_MASK,
-			 SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT,
-			 params->c_minus_1);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_TX_DRV_3_SLEW_MASK,
-			 SERDES_IREG_TX_DRV_3_SLEW_SHIFT,
-			 params->slew_rate);
-
-	al_serdes_grp_lane_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_TX_DRV_3_REG_NUM,
-				reg);
-
-}
-
-void al_serdes_tx_advanced_params_get(struct al_serdes_obj	     	*obj,
-				      enum al_serdes_group	      	grp,
-				      enum al_serdes_lane		lane,
-				      struct al_serdes_adv_tx_params *tx_params)
-{
-	uint8_t reg_val = 0;
-
-	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_TX_DRV_1_REG_NUM,
-			&reg_val);
-	tx_params->amp = (reg_val & SERDES_IREG_TX_DRV_1_HLEV_MASK) >>
-				SERDES_IREG_TX_DRV_1_HLEV_SHIFT;
-	tx_params->total_driver_units = (reg_val &
-					SERDES_IREG_TX_DRV_1_LEVN_MASK) >>
-					SERDES_IREG_TX_DRV_1_LEVN_SHIFT;
-
-	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_TX_DRV_2_REG_NUM,
-			&reg_val);
-	tx_params->c_plus_1 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM1_MASK) >>
-				SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT;
-	tx_params->c_plus_2 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM2_MASK) >>
-				SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT;
-
-	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_TX_DRV_3_REG_NUM,
-			&reg_val);
-	tx_params->c_minus_1 = (reg_val & SERDES_IREG_TX_DRV_3_LEVNP1_MASK) >>
-				SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT;
-	tx_params->slew_rate = (reg_val & SERDES_IREG_TX_DRV_3_SLEW_MASK) >>
-				SERDES_IREG_TX_DRV_3_SLEW_SHIFT;
-
-	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
-			&reg_val);
-	tx_params->override = ((reg_val & SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN) == 0);
-}
-
-
-void al_serdes_rx_advanced_params_set(struct al_serdes_obj	      *obj,
-				      enum al_serdes_group	      grp,
-				      enum al_serdes_lane	      lane,
-				      struct al_serdes_adv_rx_params  *params)
-{
-	uint8_t reg = 0;
-
-	if(!params->override) {
-		al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM,
-			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN,
-			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN);
-
-		return;
-	}
-
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM,
-			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN,
-			0);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK,
-			 SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT,
-			 params->dcgain);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK,
-			 SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT,
-			 params->dfe_3db_freq);
-
-	al_serdes_grp_lane_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_RX_CALEQ_1_REG_NUM,
-				reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK,
-			 SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT,
-			 params->dfe_gain);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK,
-			 SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT,
-			 params->dfe_first_tap_ctrl);
-
-	al_serdes_grp_lane_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_RX_CALEQ_2_REG_NUM,
-				reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK,
-			 SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT,
-			 params->dfe_secound_tap_ctrl);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK,
-			 SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT,
-			 params->dfe_third_tap_ctrl);
-
-	al_serdes_grp_lane_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_RX_CALEQ_3_REG_NUM,
-				reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK,
-			 SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT,
-			 params->dfe_fourth_tap_ctrl);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK,
-			 SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT,
-			 params->low_freq_agc_gain);
-
-	al_serdes_grp_lane_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_RX_CALEQ_4_REG_NUM,
-				reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK,
-			 SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT,
-			 params->precal_code_sel);
-
-	AL_REG_FIELD_SET(reg,
-			 SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK,
-			 SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT,
-			 params->high_freq_agc_boost);
-
-	al_serdes_grp_lane_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_RX_CALEQ_5_REG_NUM,
-				reg);
-}
-
-static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_info)
-{
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK,
-				(0x1 << SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK,
-				(0 << SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK,
-				(0x2 << SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK,
-				(0 << SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK,
-				(0x1 << SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK,
-				(0x1 << SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK,
-				(0xf0 << SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK,
-				(0 << SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK,
-				(1 << SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM,
-				SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK,
-				(0x8 << SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK,
-				(0 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK,
-				(0x64 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK,
-				(0x3 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK,
-				(0x1 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK,
-				(3 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK,
-				(1 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM,
-				SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK,
-				(0xc << SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT));
-
-	al_serdes_grp_reg_masked_write(
-				grp_info,
-				AL_SRDS_REG_PAGE_4_COMMON,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM,
-				SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK,
-				(0xcc << SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT));
-}
-
-struct al_serdes_mode_rx_tx_inv_state {
-	al_bool		restore;
-	uint32_t	pipe_rst;
-	uint32_t	ipd_multi[AL_SRDS_NUM_LANES];
-	uint8_t		inv_value[AL_SRDS_NUM_LANES];
-};
-
-static void al_serdes_mode_rx_tx_inv_state_save(
-	struct al_serdes_group_info		*grp_info,
-	struct al_serdes_mode_rx_tx_inv_state	*state)
-{
-	if (al_reg_read32(&grp_info->regs_base->gen.irst) & SERDES_GEN_IRST_POR_B_A) {
-		int i;
-
-		state->restore = AL_TRUE;
-		state->pipe_rst = al_reg_read32(&grp_info->regs_base->gen.irst);
-
-		for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
-			state->inv_value[i] = al_serdes_grp_reg_read(
-				grp_info,
-				i,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_POLARITY_RX_REG_NUM);
-			state->ipd_multi[i] =
-				al_reg_read32(&grp_info->regs_base->lane[i].ipd_multi);
-		}
-	} else {
-		state->restore = AL_FALSE;
-	}
-}
-
-static void al_serdes_mode_rx_tx_inv_state_restore(
-	struct al_serdes_group_info		*grp_info,
-	struct al_serdes_mode_rx_tx_inv_state	*state)
-{
-	if (state->restore) {
-		int i;
-
-		for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
-			al_serdes_grp_reg_write(
-				grp_info,
-				i,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_POLARITY_RX_REG_NUM,
-				state->inv_value[i]);
-			al_reg_write32(
-				&grp_info->regs_base->lane[i].ipd_multi, state->ipd_multi[i]);
-			al_reg_write32_masked(
-				&grp_info->regs_base->gen.irst,
-				(SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL >> i) |
-				(SERDES_GEN_IRST_PIPE_RST_L0_B_A >> i),
-				state->pipe_rst);
-		}
-	}
-}
-
-void al_serdes_mode_set_sgmii(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp)
-{
-	struct al_serdes_group_info *grp_info;
-	struct al_serdes_mode_rx_tx_inv_state rx_tx_inv_state;
-
-	al_assert(obj);
-	al_assert(((int)grp) >= AL_SRDS_GRP_A);
-	al_assert(((int)grp) <= AL_SRDS_GRP_D);
-
-	grp_info = &obj->grp_info[grp];
-
-	al_serdes_mode_rx_tx_inv_state_save(grp_info, &rx_tx_inv_state);
-
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
-	al_reg_write32(&grp_info->regs_base->lane[0].ictl_multi, 0x10110010);
-	al_reg_write32(&grp_info->regs_base->lane[1].ictl_multi, 0x10110010);
-	al_reg_write32(&grp_info->regs_base->lane[2].ictl_multi, 0x10110010);
-	al_reg_write32(&grp_info->regs_base->lane[3].ictl_multi, 0x10110010);
-	al_reg_write32(&grp_info->regs_base->gen.ipd_multi_synth , 0x0001);
-	al_reg_write32(&grp_info->regs_base->lane[0].ipd_multi, 0x0003);
-	al_reg_write32(&grp_info->regs_base->lane[1].ipd_multi, 0x0003);
-	al_reg_write32(&grp_info->regs_base->lane[2].ipd_multi, 0x0003);
-	al_reg_write32(&grp_info->regs_base->lane[3].ipd_multi, 0x0003);
-	al_reg_write32(&grp_info->regs_base->gen.ictl_pcs , 0);
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
-	al_serdes_ns_delay(800);
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
-	al_serdes_ns_delay(500);
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
-	al_serdes_ns_delay(500);
-
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 101, 183);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 102, 183);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 103, 12);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 104, 12);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 105, 26);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 106, 26);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 107, 2);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 108, 2);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 109, 17);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 110, 13);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 101, 153);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 102, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 103, 108);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 104, 183);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 105, 183);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 106, 12);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 107, 12);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 108, 26);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 109, 26);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 110, 7);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 111, 12);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 112, 8);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 113, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 114, 8);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 115, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 116, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 117, 179);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 118, 246);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 119, 208);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 120, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 121, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 122, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 123, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 124, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 125, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 126, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 127, 211);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 128, 211);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 129, 226);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 130, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 131, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 132, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 133, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 134, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 135, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 136, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 137, 211);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 138, 211);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 139, 226);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 140, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 141, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 142, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 143, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 144, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 145, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 146, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 147, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 148, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 149, 63);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 150, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 151, 100);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 152, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 153, 4);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 154, 2);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 155, 5);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 156, 5);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 157, 4);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 158, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 159, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 160, 8);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 161, 4);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 162, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 163, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 164, 4);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0_LANE_0,
-		AL_SRDS_REG_TYPE_PMA, 7, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_1_LANE_1,
-		AL_SRDS_REG_TYPE_PMA, 7, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_2_LANE_2,
-		AL_SRDS_REG_TYPE_PMA, 7, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_3_LANE_3,
-		AL_SRDS_REG_TYPE_PMA, 7, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 13, 16);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 48, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 49, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 54, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 55, 180);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 93, 2);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 165, 3);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 41, 6);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 354, 3);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 355, 58);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 356, 9);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 357, 3);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 358, 62);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 359, 12);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 701, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 87, 0x1f);
-
-	al_serdes_common_cfg_eth(grp_info);
-
-	al_serdes_mode_rx_tx_inv_state_restore(grp_info, &rx_tx_inv_state);
-
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x0011F0);
-	al_serdes_ns_delay(500);
-}
-
-void al_serdes_mode_set_kr(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp)
-{
-	struct al_serdes_group_info *grp_info;
-	struct al_serdes_mode_rx_tx_inv_state rx_tx_inv_state;
-
-	al_assert(obj);
-	al_assert(((int)grp) >= AL_SRDS_GRP_A);
-	al_assert(((int)grp) <= AL_SRDS_GRP_D);
-
-	grp_info = &obj->grp_info[grp];
-
-	al_serdes_mode_rx_tx_inv_state_save(grp_info, &rx_tx_inv_state);
-
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
-	al_reg_write32(&grp_info->regs_base->lane[0].ictl_multi, 0x30330030);
-	al_reg_write32(&grp_info->regs_base->lane[1].ictl_multi, 0x30330030);
-	al_reg_write32(&grp_info->regs_base->lane[2].ictl_multi, 0x30330030);
-	al_reg_write32(&grp_info->regs_base->lane[3].ictl_multi, 0x30330030);
-	al_reg_write32(&grp_info->regs_base->gen.ipd_multi_synth , 0x0001);
-	al_reg_write32(&grp_info->regs_base->lane[0].ipd_multi, 0x0003);
-	al_reg_write32(&grp_info->regs_base->lane[1].ipd_multi, 0x0003);
-	al_reg_write32(&grp_info->regs_base->lane[2].ipd_multi, 0x0003);
-	al_reg_write32(&grp_info->regs_base->lane[3].ipd_multi, 0x0003);
-	al_reg_write32(&grp_info->regs_base->gen.ictl_pcs , 0);
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
-	al_serdes_ns_delay(800);
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
-	al_serdes_ns_delay(500);
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
-	al_serdes_ns_delay(500);
-
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 101, 189);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 102, 189);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 103, 6);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 104, 6);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 105, 27);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 106, 27);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 107, 1);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 108, 1);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 109, 119);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 110, 5);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 101, 170);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 102, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 103, 108);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 104, 189);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 105, 189);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 106, 6);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 107, 6);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 108, 27);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 109, 27);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 110, 7);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 111, 12);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 112, 16);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 113, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 114, 16);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 115, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 116, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 117, 179);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 118, 246);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 119, 208);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 120, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 121, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 122, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 123, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 124, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 125, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 126, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 127, 211);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 128, 211);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 129, 226);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 130, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 131, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 132, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 133, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 134, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 135, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 136, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 137, 211);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 138, 211);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 139, 226);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 140, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 141, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 142, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 143, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 144, 239);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 145, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 146, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 147, 251);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 148, 255);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 149, 63);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 150, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 151, 50);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 152, 17);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 153, 2);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 154, 1);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 155, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 156, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 157, 4);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 158, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 159, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 160, 8);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 161, 4);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 162, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 163, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 164, 4);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0_LANE_0,
-		AL_SRDS_REG_TYPE_PMA, 7, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_1_LANE_1,
-		AL_SRDS_REG_TYPE_PMA, 7, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_2_LANE_2,
-		AL_SRDS_REG_TYPE_PMA, 7, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_3_LANE_3,
-		AL_SRDS_REG_TYPE_PMA, 7, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 13, 16);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 48, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 49, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 54, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 55, 149); /*Was 182*/
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 93, 2);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 165, 3);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 41, 6);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 354, 3);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 355, 58);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 356, 9);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 357, 3);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 358, 62);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
-		AL_SRDS_REG_TYPE_PMA, 359, 12);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 701, 0);
-	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
-		AL_SRDS_REG_TYPE_PMA, 87, 0x1f);
-
-	al_serdes_common_cfg_eth(grp_info);
-
-	al_serdes_mode_rx_tx_inv_state_restore(grp_info, &rx_tx_inv_state);
-
-	al_reg_write32(&grp_info->regs_base->gen.irst, 0x0011F0);
-	al_serdes_ns_delay(500);
-}
-
-void al_serdes_rx_advanced_params_get(struct al_serdes_obj           *obj,
-				      enum al_serdes_group	      grp,
-				      enum al_serdes_lane	      lane,
-				      struct al_serdes_adv_rx_params* rx_params)
-{
-	uint8_t temp_val;
-
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_RX_CALEQ_1_REG_NUM,
-			&temp_val);
-	rx_params->dcgain = (temp_val & SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK) >>
-				SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT;
-	rx_params->dfe_3db_freq = (temp_val &
-				SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK) >>
-				SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT;
-
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_RX_CALEQ_2_REG_NUM,
-			&temp_val);
-	rx_params->dfe_gain = (temp_val &
-				SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK) >>
-				SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT;
-	rx_params->dfe_first_tap_ctrl = (temp_val &
-			SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK) >>
-			SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT;
-
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_RX_CALEQ_3_REG_NUM,
-			&temp_val);
-	rx_params->dfe_secound_tap_ctrl = (temp_val &
-			SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK) >>
-			SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT;
-	rx_params->dfe_third_tap_ctrl = (temp_val &
-			SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK) >>
-			SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT;
-
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_RX_CALEQ_4_REG_NUM,
-			&temp_val);
-	rx_params->dfe_fourth_tap_ctrl = (temp_val &
-			SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK) >>
-			SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT;
-	rx_params->low_freq_agc_gain = (temp_val &
-			SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK) >>
-			SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT;
-
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_RX_CALEQ_5_REG_NUM,
-			&temp_val);
-	rx_params->precal_code_sel = (temp_val &
-			SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK) >>
-			SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT;
-	rx_params->high_freq_agc_boost = (temp_val &
-			SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK) >>
-			SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT;
-
-	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM,
-			&temp_val);
-	rx_params->override = ((temp_val & SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN) == 0);
-}
-
-#if (	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM != \
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM || \
-	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM != \
-		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM)
-#error Wrong assumption
-#endif
-int al_serdes_rx_equalization(
-		struct al_serdes_obj *obj,
-		enum al_serdes_group grp,
-		enum al_serdes_lane  lane)
-{
-	uint8_t serdes_ireg_fld_rxcalroamyadjust_locwren_val;
-	uint8_t serdes_ireg_fld_rxroam_xorbitsel_val;
-	uint8_t serdes_ireg_fld_pcsrxeq_locwren_val;
-	uint8_t serdes_ireg_fld_rxcal_locwren_val;
-	uint8_t temp_val;
-	uint8_t done;
-
-	int test_score;
-	int i;
-
-	/*
-	 * Make sure Roam Eye mechanism is not overridden
-	 * Lane SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN = 1,
-	 * 	so Rx 4-Point Eye process is not overridden
-	 * Lane SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN = 1,
-	 * 	so Eye Roam latch is not overridden
-	 * Lane SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN = 1,
-	 * 	so Eye Roam latch 'X adjust' is not overridden
-	 * Lane SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN = 1,
-	 * 	so Eye Roam latch 'Y adjust' is not overridden
-	 * Lane SERDES_IREG_FLD_RXROAM_XORBITSEL = 0/1,
-	 * 	so Eye Roamlatch works on the right Eye position (XORBITSEL)
-	 * 	For most cases 0 is needed, but sometimes 1 is needed.
-	 * 	I couldn't sort out why is this so the code uses a global
-	 *      XORBITSELmode variable, set by the user (GUI). Default is 0.
-	 * control must be internal. At the end we restore original setting
-	 */
-
-	/* save current values for restoring them later in the end */
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
-			&serdes_ireg_fld_rxcal_locwren_val);
-
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
-			&serdes_ireg_fld_rxcalroamyadjust_locwren_val );
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
-			&serdes_ireg_fld_rxroam_xorbitsel_val );
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM,
-			&serdes_ireg_fld_pcsrxeq_locwren_val );
-
-	/*
-	 * Set Bits:
-	 * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN
-	 * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN
-	 * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
-	 * to return 4pt-RxEye and EyeRoam Latch to internal logic
-	 *
-	 * clear bit SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN
-	 * AGC/DFE controlled via PMA registers
-	 */
-	temp_val  = serdes_ireg_fld_rxcal_locwren_val;
-	temp_val |= SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN;
-	temp_val |= SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN;
-	temp_val |= SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN;
-	temp_val |= SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN;
-
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
-			temp_val );
-
-	/*
-	 * Set bit SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN
-	 * to return EyeRoam Latch Y to internal logic
-	 */
-	temp_val = serdes_ireg_fld_rxcalroamyadjust_locwren_val |
-			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN;
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
-			temp_val );
-
-	/*
-	 * Clear Bit: SERDES_IREG_FLD_RXROAM_XORBITSEL
-	 * so XORBITSEL=0, needed for the Eye mapping.
-	 */
-	temp_val = serdes_ireg_fld_rxroam_xorbitsel_val &
-			~SERDES_IREG_FLD_RXROAM_XORBITSEL;
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
-			temp_val );
-
-	/*
-	 * Take Control from int.pin over RxEQ process.
-	 * Clear Bit SERDES_IREG_FLD_PCSRXEQ_LOCWREN
-	 * to override RxEQ via PMA
-	 */
-	temp_val = serdes_ireg_fld_pcsrxeq_locwren_val &
-			~SERDES_IREG_FLD_PCSRXEQ_LOCWREN;
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM,
-			temp_val );
-
-
-	/*
-	 * Start/Stop RxEQ Cal is via PCSRXEQ_START: 1=START. 0=STOP.
-	 * Clear Bit SERDES_IREG_FLD_PCSRXEQ_START
-	 * to start fresh from Stop
-	 */
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
-			&temp_val );
-	temp_val &= ~SERDES_IREG_FLD_PCSRXEQ_START;
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
-			temp_val );
-
-	/* Set Bit SERDES_IREG_FLD_PCSRXEQ_START
-	 * to begin Rx Eq Cal */
-	temp_val |= SERDES_IREG_FLD_PCSRXEQ_START;
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
-			temp_val );
-
-	/* Poll on RxEq Cal completion. SERDES_IREG_FLD_RXEQ_DONE. 1=Done. */
-	for( i = 0; i < AL_SERDES_RX_EQUAL_TRIES; ++i ) {
-		al_serdes_lane_read(
-				obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM,
-				&done );
-		done &= SERDES_IREG_FLD_RXEQ_DONE;
-
-		/* Check if RxEQ Cal is done */
-		if (done)
-			break;
-		al_msleep(AL_SERDES_RX_EQUAL_MDELAY);
-	}
-
-	if (!done) {
-		al_err("%s: Timeout!\n", __func__);
-		return -1;
-	}
-
-	/* Stop the RxEQ process. */
-	temp_val &= ~SERDES_IREG_FLD_PCSRXEQ_START;
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
-			temp_val );
-	/* Get score */
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM,
-			&temp_val );
-	test_score = (int)( (temp_val & 0xFF) << 6 );
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM,
-			&temp_val );
-	test_score += (int)(temp_val & SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK);
-
-	/* Restore start values */
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
-			serdes_ireg_fld_rxcal_locwren_val);
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
-			serdes_ireg_fld_rxcalroamyadjust_locwren_val );
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
-			serdes_ireg_fld_rxroam_xorbitsel_val );
-	al_serdes_lane_write(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM,
-			serdes_ireg_fld_pcsrxeq_locwren_val );
-
-	return test_score;
-}
-
-#if (	SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM != \
-		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM || \
-	SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM != \
-		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM || \
-	SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM != \
-		SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM)
-#error Wrong assumption
-#endif
-int al_serdes_calc_eye_size(
-		struct al_serdes_obj *obj,
-		enum al_serdes_group grp,
-		enum al_serdes_lane  lane,
-		int*                 width,
-		int*                 height)
-{
-	uint8_t rxcaleyediagfsm_x_y_valweight_val;
-	uint8_t rxcaleyediagfsm_xvalcoarse_val;
-	uint8_t rxcaleyediagfsm_xvalfine_val;
-	uint8_t rxcaleyediagfsm_yvalcoarse_val;
-	uint8_t rxcaleyediagfsm_yvalfine_val;
-	uint8_t rxlock2ref_locwren_val;
-	uint8_t rxcal_locwren_val;
-	uint8_t rxcalroamyadjust_locwren_val;
-	uint8_t rxlock2ref_ovren_val;
-
-	int i;
-	uint8_t status;
-	uint8_t reg_value;
-
-	/* Save Registers */
-	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM,
-			&rxlock2ref_locwren_val);
-	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
-			&rxcal_locwren_val);
-	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
-			&rxcalroamyadjust_locwren_val);
-	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM,
-			&rxlock2ref_ovren_val);
-
-	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
-			&rxcaleyediagfsm_x_y_valweight_val);
-	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
-			&rxcaleyediagfsm_xvalcoarse_val);
-	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
-			&rxcaleyediagfsm_xvalfine_val);
-	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
-			&rxcaleyediagfsm_yvalcoarse_val);
-	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
-			&rxcaleyediagfsm_yvalfine_val);
-
-	/*
-	 * Clear Bit:
-	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN
-	 * 	to override RxEQ via PMA
-	 * Set Bits:
-	 * 	SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
-	 * 	SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
-	 * 	to keep Eye Diag Roam controlled internally
-	 */
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN  |
-			SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN |
-			SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN,
-			SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN |
-			SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN);
-	/*
-	 * Set Bit:
-	 * 	 SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN
-	 * 	 to keep Eye Diag Roam controlled internally
-	 */
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
-			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN,
-			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN);
-
-	/*
-	 * Clear Bit:
-	 * 	SERDES_IREG_FLD_RXROAM_XORBITSEL,
-	 * 	so XORBITSEL=0, needed for the Eye mapping
-	 *  Set Bit:
-	 *  SERDES_IREG_FLD_RXLOCK2REF_OVREN,
-	 *  so RXLOCK2REF_OVREN=1, keeping lock to data, preventing data hit
-	 */
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-			lane,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
-			SERDES_IREG_FLD_RXLOCK2REF_OVREN |
-			SERDES_IREG_FLD_RXROAM_XORBITSEL,
-			SERDES_IREG_FLD_RXLOCK2REF_OVREN);
-
-
-	/*
-	 * Clear Bit:
-	 * 	SERDES_IREG_FLD_RXLOCK2REF_LOCWREN,
-	 * 	so RXLOCK2REF_LOCWREN=0, to override control
-	 */
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM,
-				SERDES_IREG_FLD_RXLOCK2REF_LOCWREN,
-				0);
-
-	/* Width Calculation */
-
-	/* Return Value = 0*Y + 1*X */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
-			0x01);
-	/* X coarse scan step = 3 */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
-			0x03);
-	/* X fine scan step = 1   */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
-			0x01);
-	/* Y coarse scan step = 0 */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
-			0x00);
-	/* Y fine scan step = 0   */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
-			0x00);
-
-	/*
-	 * Set Bit:
-	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
-	 * 	to start Eye measurement
-	 */
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START);
-
-	for( i = 0; i < AL_SERDES_RX_EYE_CAL_TRIES; ++i ) {
-		/* Check if RxEQ Cal is done */
-		al_serdes_lane_read(
-				obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM,
-				&status );
-		if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)
-			break;
-		al_msleep(AL_SERDES_RX_EYE_CAL_MDELAY);
-	}
-
-	if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR) {
-		al_err("%s: eye measure error!\n", __func__);
-		return -1;
-	}
-
-	if (!(status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)) {
-		al_err("%s: eye measure timeout!\n", __func__);
-		return -1;
-	}
-
-	/*  Read Eye Opening Metrics, Bits:
-	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB,
-	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB
-	 */
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM,
-			&reg_value );
-	*width = reg_value << 6;
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM,
-			&reg_value );
-	*width =+ reg_value & SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE;
-
-	/*
-	 * Clear Bit:
-	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
-	 * 	to stop Eye measurement
-	 */
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
-				0);
-
-	/* Height Calculation */
-
-	/* Return Value = 1*Y + 0*X */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
-			0x10);
-	/* X coarse scan step = 0 */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
-			0x00);
-	/* X fine scan step = 0   */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
-			0x00);
-	/* Y coarse scan step = 3 */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
-			0x03);
-	/* Y fine scan step = 1   */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
-			0x01);
-
-	/*
-	 * Set Bit:
-	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
-	 * 	to start Eye measurement
-	 */
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START);
-
-	for( i = 0; i < AL_SERDES_RX_EYE_CAL_TRIES; ++i ) {
-		/* Check if RxEQ Cal is done */
-		al_serdes_lane_read(
-				obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM,
-				&status );
-		if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)
-			break;
-		al_msleep(AL_SERDES_RX_EYE_CAL_MDELAY);
-	}
-
-	if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR) {
-		al_err("%s: eye measure error!\n", __func__);
-		return -1;
-	}
-
-	if (!(status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)) {
-		al_err("%s: eye measure timeout!\n", __func__);
-		return -1;
-	}
-
-	/*  Read Eye Opening Metrics, Bits:
-	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB,
-	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB
-	 */
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM,
-			&reg_value );
-	*height = reg_value << 6;
-	al_serdes_lane_read(
-			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM,
-			&reg_value );
-	*height =+ reg_value & SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE;
-
-	/*
-	 * Clear Bit:
-	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
-	 * 	to stop Eye measurement
-	 */
-	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
-				lane,
-				AL_SRDS_REG_TYPE_PMA,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
-				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
-				0);
-
-	/* Restore Registers */
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
-			rxcaleyediagfsm_x_y_valweight_val);
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
-			rxcaleyediagfsm_xvalcoarse_val);
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
-			rxcaleyediagfsm_xvalfine_val);
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
-			rxcaleyediagfsm_yvalcoarse_val);
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
-			AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
-			rxcaleyediagfsm_yvalfine_val);
-
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM,
-			rxlock2ref_locwren_val);
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
-			rxcal_locwren_val);
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
-			rxcalroamyadjust_locwren_val);
-	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
-			SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM,
-			rxlock2ref_ovren_val);
-	return 0;
-}
-
-void al_serdes_sris_config(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	struct al_serdes_sris_params	*params)
-{
-	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
-
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM,
-		(params->ppm_drift_count & AL_FIELD_MASK(7, 0)) >> 0);
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM,
-		(params->ppm_drift_count & AL_FIELD_MASK(15, 8)) >> 8);
-
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM,
-		(params->ppm_drift_max & AL_FIELD_MASK(7, 0)) >> 0);
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM,
-		(params->ppm_drift_max & AL_FIELD_MASK(15, 8)) >> 8);
-
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM,
-		(params->synth_ppm_drift_max & AL_FIELD_MASK(7, 0)) >> 0);
-	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
-		SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM,
-		(params->synth_ppm_drift_max & AL_FIELD_MASK(15, 8)) >> 8);
-
-	al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
-		SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM,
-		SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK,
-		(params->full_d2r1)
-			<< SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT);
-
-	al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
-		SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM,
-		SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK,
-		(params->full_pcie_g3)
-			<< SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT);
-
-	al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
-		SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM,
-		SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK,
-		(params->rd_threshold_d2r1)
-			<< SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT);
-
-	al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
-		SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM,
-		SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK,
-		(params->rd_threshold_pcie_g3)
-			<< SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT);
-}
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes.h b/sys/contrib/alpine-hal/eth/al_hal_serdes.h
deleted file mode 100644
index 37aec839b2f2..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes.h
+++ /dev/null
@@ -1,1125 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_serdes_api API
- * SerDes HAL driver API
- * @ingroup group_serdes SerDes
- * @{
- *
- * @file   al_hal_serdes.h
- *
- * @brief Header file for the SerDes HAL driver
- *
- */
-
-#ifndef __AL_HAL_SERDES_H__
-#define __AL_HAL_SERDES_H__
-
-#include "al_hal_common.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-struct al_serdes_obj;
-
-enum al_serdes_group {
-	AL_SRDS_GRP_A = 0,
-	AL_SRDS_GRP_B,
-	AL_SRDS_GRP_C,
-	AL_SRDS_GRP_D,
-
-	AL_SRDS_NUM_GROUPS,
-};
-
-struct al_serdes_group_info {
-	/*
-	 * Group parent object - filled automatically by al_serdes_handle_init
-	 */
-	struct al_serdes_obj		*pobj;
-
-	/*
-	 * Group specific register base - filled automatically by
-	 * al_sedres_handle_init
-	 */
-	struct al_serdes_regs __iomem	*regs_base;
-};
-
-struct al_serdes_obj {
-	struct al_serdes_group_info	grp_info[AL_SRDS_NUM_GROUPS];
-};
-
-enum al_serdes_reg_page {
-	AL_SRDS_REG_PAGE_0_LANE_0 = 0,
-	AL_SRDS_REG_PAGE_1_LANE_1,
-	AL_SRDS_REG_PAGE_2_LANE_2,
-	AL_SRDS_REG_PAGE_3_LANE_3,
-	AL_SRDS_REG_PAGE_4_COMMON,
-	AL_SRDS_REG_PAGE_0123_LANES_0123 = 7,
-};
-
-enum al_serdes_reg_type {
-	AL_SRDS_REG_TYPE_PMA = 0,
-	AL_SRDS_REG_TYPE_PCS,
-};
-
-enum al_serdes_lane {
-	AL_SRDS_LANE_0 = AL_SRDS_REG_PAGE_0_LANE_0,
-	AL_SRDS_LANE_1 = AL_SRDS_REG_PAGE_1_LANE_1,
-	AL_SRDS_LANE_2 = AL_SRDS_REG_PAGE_2_LANE_2,
-	AL_SRDS_LANE_3 = AL_SRDS_REG_PAGE_3_LANE_3,
-
-	AL_SRDS_NUM_LANES,
-	AL_SRDS_LANES_0123 = AL_SRDS_REG_PAGE_0123_LANES_0123,
-};
-
-/** Serdes loopback mode */
-enum al_serdes_lb_mode {
-	/** No loopback */
-	AL_SRDS_LB_MODE_OFF,
-
-	/**
-	 * Transmits the untimed, partial equalized RX signal out the transmit
-	 * IO pins.
-	 * No clock used (untimed)
-	 */
-	AL_SRDS_LB_MODE_PMA_IO_UN_TIMED_RX_TO_TX,
-
-	/**
-	 * Loops back the TX serializer output into the CDR.
-	 * CDR recovered bit clock used (without attenuation)
-	 */
-	AL_SRDS_LB_MODE_PMA_INTERNALLY_BUFFERED_SERIAL_TX_TO_RX,
-
-	/**
-	 * Loops back the TX driver IO signal to the RX IO pins
-	 * CDR recovered bit clock used (only through IO)
-	 */
-	AL_SRDS_LB_MODE_PMA_SERIAL_TX_IO_TO_RX_IO,
-
-	/**
-	 * Parallel loopback from the PMA receive lane data ports, to the
-	 * transmit lane data ports
-	 * CDR recovered bit clock used
-	 */
-	AL_SRDS_LB_MODE_PMA_PARALLEL_RX_TO_TX,
-
-	/** Loops received data after elastic buffer to transmit path */
-	AL_SRDS_LB_MODE_PCS_PIPE,
-
-	/** Loops TX data (to PMA) to RX path (instead of PMA data) */
-	AL_SRDS_LB_MODE_PCS_NEAR_END,
-
-	/** Loops receive data prior to interface block to transmit path */
-	AL_SRDS_LB_MODE_PCS_FAR_END,
-};
-
-/** Serdes BIST pattern */
-enum al_serdes_bist_pattern {
-	AL_SRDS_BIST_PATTERN_USER,
-	AL_SRDS_BIST_PATTERN_PRBS7,
-	AL_SRDS_BIST_PATTERN_PRBS23,
-	AL_SRDS_BIST_PATTERN_PRBS31,
-	AL_SRDS_BIST_PATTERN_CLK1010,
-};
-
-/** SerDes group rate */
-enum al_serdes_rate {
-	AL_SRDS_RATE_1_8,
-	AL_SRDS_RATE_1_4,
-	AL_SRDS_RATE_1_2,
-	AL_SRDS_RATE_FULL,
-};
-
-/** SerDes power mode */
-enum al_serdes_pm {
-	AL_SRDS_PM_PD,
-	AL_SRDS_PM_P2,
-	AL_SRDS_PM_P1,
-	AL_SRDS_PM_P0S,
-	AL_SRDS_PM_P0,
-};
-
-/** SerDes PCIe Rate - values are important for proper behavior */
-enum al_serdes_pcie_rate {
-	AL_SRDS_PCIE_RATE_GEN1 = 0,
-	AL_SRDS_PCIE_RATE_GEN2,
-	AL_SRDS_PCIE_RATE_GEN3,
-};
-
-/**
- * Initializes a SERDES object
- *
- * @param  serdes_regs_base
- *             The SERDES register file base pointer
- *
- * @param obj
- *             An allocated, non initialized object context
- *
- *
- * @return 0 if no error found.
- *
- */
-int al_serdes_handle_init(
-	void __iomem		*serdes_regs_base,
-	struct al_serdes_obj	*obj);
-
-/**
- * SERDES register read
- *
- * Reads a SERDES register
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  page
- *             The SERDES register page within the group
- *
- * @param  type
- *             The SERDES register type (PMA /PCS)
- *
- * @param  offset
- *             The SERDES register offset (0 - 4095)
- *
- * @param data
- *             The read data
- *
- *
- * @return 0 if no error found.
- *
- */
-int al_serdes_reg_read(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_reg_page	page,
-	enum al_serdes_reg_type	type,
-	uint16_t		offset,
-	uint8_t			*data);
-
-/**
- * SERDES register write
- *
- * Writes a SERDES register
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  page
- *             The SERDES register page within the group
- *
- * @param  type
- *             The SERDES register type (PMA /PCS)
- *
- * @param  offset
- *             The SERDES register offset (0 - 4095)
- *
- * @param  data
- *             The data to write
- *
- *
- * @return 0 if no error found.
- *
- */
-int al_serdes_reg_write(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_reg_page	page,
-	enum al_serdes_reg_type	type,
-	uint16_t		offset,
-	uint8_t			data);
-
-/**
- * Enable BIST required overrides
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	rate
- *		The required speed rate
- */
-void al_serdes_bist_overrides_enable(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_rate	rate);
-
-/**
- * Disable BIST required overrides
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	rate
- *		The required speed rate
- */
-void al_serdes_bist_overrides_disable(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp);
-
-/**
- * Rx rate change
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	rate
- *		The Rx required rate
- */
-void al_serdes_rx_rate_change(
-	struct al_serdes_obj *obj,
-	enum al_serdes_group grp,
-	enum al_serdes_rate rate);
-
-/**
- * SERDES lane Rx rate change software flow enable
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	lane
- *		The SERDES lane within the group
- */
-void al_serdes_lane_rx_rate_change_sw_flow_en(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane);
-
-/**
- * SERDES lane Rx rate change software flow disable
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	lane
- *		The SERDES lane within the group
- */
-void al_serdes_lane_rx_rate_change_sw_flow_dis(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane);
-
-/**
- * PCIe lane rate override check
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	lane
- *		The SERDES lane within the group
- * @returns	AL_TRUE if the override is enabled
- */
-al_bool al_serdes_lane_pcie_rate_override_is_enabled(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	enum al_serdes_lane		lane);
-
-/**
- * PCIe lane rate override control
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	lane
- *		The SERDES lane within the group
- * @param	en
- *		Enable/disable
- */
-void al_serdes_lane_pcie_rate_override_enable_set(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	enum al_serdes_lane		lane,
-	al_bool				en);
-
-/**
- * PCIe lane rate get
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	lane
- *		The SERDES lane within the group
- */
-enum al_serdes_pcie_rate al_serdes_lane_pcie_rate_get(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane);
-
-/**
- * PCIe lane rate set
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	lane
- *		The SERDES lane within the group
- * @param	rate
- *		The required rate
- */
-void al_serdes_lane_pcie_rate_set(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	enum al_serdes_lane		lane,
-	enum al_serdes_pcie_rate	rate);
-
-/**
- * SERDES group power mode control
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	pm
- *		The required power mode
- */
-void al_serdes_group_pm_set(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_pm	pm);
-
-/**
- * SERDES lane power mode control
- *
- * @param	obj
- *		The object context
- * @param	grp
- *		The SERDES group
- * @param	lane
- *		The SERDES lane within the group
- * @param	rx_pm
- *		The required RX power mode
- * @param	tx_pm
- *		The required TX power mode
- */
-void al_serdes_lane_pm_set(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	enum al_serdes_pm	rx_pm,
-	enum al_serdes_pm	tx_pm);
-
-/**
- * SERDES group PMA hard reset
- *
- * Controls Serdes group PMA hard reset
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  enable
- *             Enable/disable hard reset
- */
-void al_serdes_pma_hard_reset_group(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	al_bool			enable);
-
-/**
- * SERDES lane PMA hard reset
- *
- * Controls Serdes lane PMA hard reset
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  lane
- *             The SERDES lane within the group
- *
- * @param  enable
- *             Enable/disable hard reset
- */
-void al_serdes_pma_hard_reset_lane(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	al_bool			enable);
-
-/**
- * SERDES loopback control
- *
- * Controls the loopback
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  lane
- *             The SERDES lane within the group
- *
- * @param  mode
- *             The requested loopback mode
- *
- */
-void al_serdes_loopback_control(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	enum al_serdes_lb_mode	mode);
-
-/**
- * SERDES BIST pattern selection
- *
- * Selects the BIST pattern to be used
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  pattern
- *             The pattern to set
- *
- * @param  user_data
- *             The pattern user data (when pattern == AL_SRDS_BIST_PATTERN_USER)
- *             80 bits (8 bytes array)
- *
- */
-void al_serdes_bist_pattern_select(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	enum al_serdes_bist_pattern	pattern,
-	uint8_t				*user_data);
-
-/**
- * SERDES BIST TX Enable
- *
- * Enables/disables TX BIST per lane
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  lane
- *             The SERDES lane within the group
- *
- * @param  enable
- *             Enable or disable TX BIST
- */
-void al_serdes_bist_tx_enable(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	al_bool			enable);
-
-/**
- * SERDES BIST TX single bit error injection
- *
- * Injects single bit error during a TX BIST
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- */
-void al_serdes_bist_tx_err_inject(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp);
-
-/**
- * SERDES BIST RX Enable
- *
- * Enables/disables RX BIST per lane
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  lane
- *             The SERDES lane within the group
- *
- * @param  enable
- *             Enable or disable TX BIST
- */
-void al_serdes_bist_rx_enable(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	al_bool			enable);
-
-/**
- * SERDES BIST RX status
- *
- * Checks the RX BIST status for a specific SERDES lane
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  lane
- *             The SERDES lane within the group
- *
- * @param is_locked
- *             An indication whether RX BIST is locked
- *
- * @param err_cnt_overflow
- *             An indication whether error count overflow occured
- *
- * @param err_cnt
- *             Current bit error count
- */
-void al_serdes_bist_rx_status(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	al_bool			*is_locked,
-	al_bool			*err_cnt_overflow,
-	uint16_t		*err_cnt);
-
-/**
- * SERDES Digital Test Bus
- *
- * Samples the digital test bus of a specific SERDES lane
- *
- * @param  obj
- *             The object context
- *
- * @param  grp
- *             The SERDES group
- *
- * @param  lane
- *             The SERDES lane within the group
- *
- * @param  sel
- *             The selected sampling group (0 - 31)
- *
- * @param sampled_data
- *             The sampled data (5 bytes array)
- *
- *
- * @return 0 if no error found.
- *
- */
-int al_serdes_digital_test_bus(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp,
-	enum al_serdes_lane	lane,
-	uint8_t			sel,
-	uint8_t			*sampled_data);
-
-
-/* KR link training */
-/**
- * Set the tx de-emphasis to preset values
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- */
-void al_serdes_tx_deemph_preset(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane);
-
-/**
- * Tx de-emphasis parameters
- */
-enum al_serdes_tx_deemph_param {
-	AL_SERDES_TX_DEEMP_C_ZERO,	/*< c(0) */
-	AL_SERDES_TX_DEEMP_C_PLUS,	/*< c(1) */
-	AL_SERDES_TX_DEEMP_C_MINUS,	/*< c(-1) */
-};
-
-/**
- * Increase tx de-emphasis param.
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param param which tx de-emphasis to change
- *
- * @return false in case max is reached. true otherwise.
- */
-al_bool al_serdes_tx_deemph_inc(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		enum al_serdes_tx_deemph_param param);
-
-/**
- * Decrease tx de-emphasis param.
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param param which tx de-emphasis to change
- *
- * @return false in case min is reached. true otherwise.
- */
-al_bool al_serdes_tx_deemph_dec(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		enum al_serdes_tx_deemph_param param);
-
-/**
- * run Rx eye measurement.
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param timeout timeout in uSec
- *
- * @param value Rx eye measurement value
- *		(0 - completely closed eye, 0xffff - completely open eye).
- *
- * @return 0 if no error found.
- */
-int al_serdes_eye_measure_run(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		uint32_t		timeout,
-		unsigned int		*value);
-
-/**
- * Eye diagram single sampling
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param x Sampling X position (0 - 63 --> -1.00 UI ... 1.00 UI)
- *
- * @param y Sampling Y position (0 - 62 --> 500mV ... -500mV)
- *
- * @param timeout timeout in uSec
- *
- * @param value Eye diagram sample value (BER - 0x0000 - 0xffff)
- *
- * @return 0 if no error found.
- */
-int al_serdes_eye_diag_sample(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane,
-		unsigned int		x,
-		int			y,
-		unsigned int		timeout,
-		unsigned int		*value);
-
-/**
- * Check if signal is detected
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @return true if signal is detected. false otherwise.
- */
-al_bool al_serdes_signal_is_detected(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane);
-
-
-struct al_serdes_adv_tx_params {
-	/*
-	 * select the input values location.
-	 * When set to true the values will be taken from the internal registers
-	 * that will be override with the next following parameters.
-	 * When set to false the values will be taken from external pins (the
-	 * other parameters in this case is not needed)
-	 */
-	al_bool				override;
-	/*
-	 * Transmit Amplitude control signal. Used to define the full-scale
-	 * maximum swing of the driver.
-	 *	000 - Not Supported
-	 *	001 - 952mVdiff-pkpk
-	 *	010 - 1024mVdiff-pkpk
-	 *	011 - 1094mVdiff-pkpk
-	 *	100 - 1163mVdiff-pkpk
-	 *	101 - 1227mVdiff-pkpk
-	 *	110 - 1283mVdiff-pkpk
-	 *	111 - 1331mVdiff-pkpk
-	 */
-	uint8_t				amp;
-	/* Defines the total number of driver units allocated in the driver */
-	uint8_t				total_driver_units;
-	/* Defines the total number of driver units allocated to the
-	 * first post-cursor (C+1) tap. */
-	uint8_t				c_plus_1;
-	/* Defines the total number of driver units allocated to the
-	 * second post-cursor (C+2) tap. */
-	uint8_t				c_plus_2;
-	/* Defines the total number of driver units allocated to the
-	 * first pre-cursor (C-1) tap. */
-	uint8_t				c_minus_1;
-	/* TX driver Slew Rate control:
-	 *	00 - 31ps
-	 *	01 - 33ps
-	 *	10 - 68ps
-	 *	11 - 170ps
-	 */
-	uint8_t				slew_rate;
-};
-
-struct al_serdes_adv_rx_params {
-	/*
-	 * select the input values location.
-	 * When set to true the values will be taken from the internal registers
-	 * that will be override with the next following parameters.
-	 * When set to false the values will be taken based in the equalization
-	 * results (the other parameters in this case is not needed)
-	 */
-	al_bool				override;
-	/* RX agc high frequency dc gain:
-	 *	-3'b000: -3dB
-	 *	-3'b001: -2.5dB
-	 *	-3'b010: -2dB
-	 *	-3'b011: -1.5dB
-	 *	-3'b100: -1dB
-	 *	-3'b101: -0.5dB
-	 *	-3'b110: -0dB
-	 *	-3'b111: 0.5dB
-	 */
-	uint8_t				dcgain;
-	/* DFE post-shaping tap 3dB frequency
-	 *	-3'b000: 684MHz
-	 *	-3'b001: 576MHz
-	 *	-3'b010: 514MHz
-	 *	-3'b011: 435MHz
-	 *	-3'b100: 354MHz
-	 *	-3'b101: 281MHz
-	 *	-3'b110: 199MHz
-	 *	-3'b111: 125MHz
-	 */
-	uint8_t				dfe_3db_freq;
-	/* DFE post-shaping tap gain
-	 *	0: no pulse shaping tap
-	 *	1: -24mVpeak
-	 *	2: -45mVpeak
-	 *	3: -64mVpeak
-	 *	4: -80mVpeak
-	 *	5: -93mVpeak
-	 *	6: -101mVpeak
-	 *	7: -105mVpeak
-	 */
-	uint8_t				dfe_gain;
-	/* DFE first tap gain control
-	 *	-4'b0000: +1mVpeak
-	 *	-4'b0001: +10mVpeak
-	 *	....
-	 *	-4'b0110: +55mVpeak
-	 *	-4'b0111: +64mVpeak
-	 *	-4'b1000: -1mVpeak
-	 *	-4'b1001: -10mVpeak
-	 *	....
-	 *	-4'b1110: -55mVpeak
-	 *	-4'b1111: -64mVpeak
-	 */
-	uint8_t				dfe_first_tap_ctrl;
-	/* DFE second tap gain control
-	 *	-4'b0000: +0mVpeak
-	 *	-4'b0001: +9mVpeak
-	 *	....
-	 *	-4'b0110: +46mVpeak
-	 *	-4'b0111: +53mVpeak
-	 *	-4'b1000: -0mVpeak
-	 *	-4'b1001: -9mVpeak
-	 *	....
-	 *	-4'b1110: -46mVpeak
-	 *	-4'b1111: -53mVpeak
-	 */
-	uint8_t				dfe_secound_tap_ctrl;
-	/* DFE third tap gain control
-	 *	-4'b0000: +0mVpeak
-	 *	-4'b0001: +7mVpeak
-	 *	....
-	 *	-4'b0110: +38mVpeak
-	 *	-4'b0111: +44mVpeak
-	 *	-4'b1000: -0mVpeak
-	 *	-4'b1001: -7mVpeak
-	 *	....
-	 *	-4'b1110: -38mVpeak
-	 *	-4'b1111: -44mVpeak
-	 */
-	uint8_t				dfe_third_tap_ctrl;
-	/* DFE fourth tap gain control
-	 *	-4'b0000: +0mVpeak
-	 *	-4'b0001: +6mVpeak
-	 *	....
-	 *	-4'b0110: +29mVpeak
-	 *	-4'b0111: +33mVpeak
-	 *	-4'b1000: -0mVpeak
-	 *	-4'b1001: -6mVpeak
-	 *	....
-	 *	-4'b1110: -29mVpeak
-	 *	-4'b1111: -33mVpeak
-	 */
-	uint8_t				dfe_fourth_tap_ctrl;
-	/* Low frequency agc gain (att) select
-	 *	-3'b000: Disconnected
-	 *	-3'b001: -18.5dB
-	 *	-3'b010: -12.5dB
-	 *	-3'b011: -9dB
-	 *	-3'b100: -6.5dB
-	 *	-3'b101: -4.5dB
-	 *	-3'b110: -2.9dB
-	 *	-3'b111: -1.6dB
-	 */
-	uint8_t				low_freq_agc_gain;
-	/* Provides a RX Equalizer pre-hint, prior to beginning
-	 * adaptive equalization */
-	uint8_t				precal_code_sel;
-	/* High frequency agc boost control
-	 *	Min d0: Boost ~4dB
-	 *	Max d31: Boost ~20dB
-	 */
-	uint8_t				high_freq_agc_boost;
-};
-
-/**
- * configure tx advanced parameters
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param params pointer to the tx parameters
- */
-void al_serdes_tx_advanced_params_set(struct al_serdes_obj	      	*obj,
-				      enum al_serdes_group		grp,
-				      enum al_serdes_lane		lane,
-				      struct al_serdes_adv_tx_params  *params);
-
-/**
- * read tx advanced parameters
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param params pointer to the tx parameters
- */
-void al_serdes_tx_advanced_params_get(struct al_serdes_obj	     	*obj,
-				      enum al_serdes_group	      	grp,
-				      enum al_serdes_lane		lane,
-				      struct al_serdes_adv_tx_params *params);
-
-/**
- * configure rx advanced parameters
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param params pointer to the rx parameters
- */
-void al_serdes_rx_advanced_params_set(struct al_serdes_obj	      *obj,
-				      enum al_serdes_group	      grp,
-				      enum al_serdes_lane	      lane,
-				      struct al_serdes_adv_rx_params  *params);
-
-/**
- * read rx advanced parameters
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param params pointer to the rx parameters
- */
-void al_serdes_rx_advanced_params_get(struct al_serdes_obj           *obj,
-				      enum al_serdes_group	      grp,
-				      enum al_serdes_lane	      lane,
-				      struct al_serdes_adv_rx_params* params);
-
-/**
- *  Switch entire SerDes group to SGMII mode based on 156.25 Mhz reference clock
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- */
-void al_serdes_mode_set_sgmii(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp);
-
-/**
- *  Switch entire SerDes group to KR mode based on 156.25 Mhz reference clock
- *
- * @param obj The object context
- *
- * @param grp The SERDES group
- */
-void al_serdes_mode_set_kr(
-	struct al_serdes_obj	*obj,
-	enum al_serdes_group	grp);
-
-/**
- * performs SerDes HW equalization test and update equalization parameters
- *
- * @param obj the object context
- *
- * @param grp the SERDES group
- *
- * @param lane The SERDES lane within the group
- */
-int al_serdes_rx_equalization(
-		struct al_serdes_obj	*obj,
-		enum al_serdes_group	grp,
-		enum al_serdes_lane	lane);
-
-/**
- * performs Rx equalization and compute the width and height of the eye
- *
- * @param obj the object context
- *
- * @param grp the SERDES group
- *
- * @param lane The SERDES lane within the group
- *
- * @param width the output width of the eye
- *
- * @param height the output height of the eye
- */
-int al_serdes_calc_eye_size(
-		struct al_serdes_obj *obj,
-		enum al_serdes_group grp,
-		enum al_serdes_lane  lane,
-		int*                 width,
-		int*                 height);
-
-/**
- * SRIS parameters
- */
-struct al_serdes_sris_params {
-	/* Controls the frequency accuracy threshold (ppm) for lock detection CDR */
-	uint16_t	ppm_drift_count;
-	/* Controls the frequency accuracy threshold (ppm) for lock detection in the CDR */
-	uint16_t	ppm_drift_max;
-	/* Controls the frequency accuracy threshold (ppm) for lock detection in PLL */
-	uint16_t	synth_ppm_drift_max;
-	/* Elastic buffer full threshold for PCIE modes: GEN1/GEN2 */
-	uint8_t		full_d2r1;
-	/* Elastic buffer full threshold for PCIE modes: GEN3 */
-	uint8_t		full_pcie_g3;
-	/* Elastic buffer midpoint threshold.
-	 * Sets the depth of the buffer while in PCIE mode, GEN1/GEN2
-	 */
-	uint8_t		rd_threshold_d2r1;
-	/* Elastic buffer midpoint threshold.
-	 * Sets the depth of the buffer while in PCIE mode, GEN3
-	 */
-	uint8_t		rd_threshold_pcie_g3;
-};
-
-/**
- * SRIS: Separate Refclk Independent SSC (Spread Spectrum Clocking)
- * Currently available only for PCIe interfaces.
- * When working with local Refclk, same SRIS configuration in both serdes sides
- * (EP and RC in PCIe interface) is required.
- *
- * performs SRIS configuration according to params
- *
- * @param obj the object context
- *
- * @param grp the SERDES group
- *
- * @param params the SRIS parameters
- */
-void al_serdes_sris_config(
-	struct al_serdes_obj		*obj,
-	enum al_serdes_group		grp,
-	struct al_serdes_sris_params	*params);
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-
-/* *INDENT-ON* */
-#endif		/* __AL_SRDS__ */
-
-/** @} end of SERDES group */
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_25g.c b/sys/contrib/alpine-hal/eth/al_hal_serdes_25g.c
deleted file mode 100644
index 68767e557fd1..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_25g.c
+++ /dev/null
@@ -1,1951 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#include "al_hal_serdes_25g.h"
-#include "al_hal_serdes_25g_regs.h"
-#include "al_hal_serdes_25g_internal_regs.h"
-
-#define AL_SERDES_MB_MAX_DATA_LEN		8
-
-#define AL_SERDES_25G_WAIT_FOR_READY_TO		200
-#define AL_SERDES_25G_RESET_TO			100
-#define AL_SERDES_25G_RESET_NUM_RETRIES		5
-
-#if (!defined(AL_SERDES_BASIC_SERVICES_ONLY)) || (AL_SERDES_BASIC_SERVICES_ONLY == 0)
-#define AL_SRDS_ADV_SRVC(func)			func
-#else
-static void al_serdes_hssp_stub_func(void)
-{
-	al_err("%s: not implemented service called!\n", __func__);
-}
-
-#define AL_SRDS_ADV_SRVC(func)			((typeof(func) *)al_serdes_hssp_stub_func)
-#endif
-
-/******************************************************************************/
-/******************************************************************************/
-static enum al_serdes_type al_serdes_25g_type_get(void)
-{
-	return AL_SRDS_TYPE_25G;
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static int al_serdes_25g_reg_read(
-	struct al_serdes_grp_obj	*obj,
-	enum al_serdes_reg_page		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				*data)
-{
-	struct al_serdes_c_regs __iomem	*regs_base = obj->regs_base;
-	uint32_t addr = 0;
-
-	al_dbg("%s(%p, %d, %d, %u)\n", __func__, obj, page, type, offset);
-
-	al_assert(obj);
-	al_assert(data);
-
-	switch (page) {
-	case AL_SRDS_REG_PAGE_TOP:
-		addr = (SERDES_25G_TOP_BASE + offset);
-		break;
-	case AL_SRDS_REG_PAGE_4_COMMON:
-		addr = (SERDES_25G_CM_BASE + offset);
-		break;
-	case AL_SRDS_REG_PAGE_0_LANE_0:
-	case AL_SRDS_REG_PAGE_1_LANE_1:
-		addr = (SERDES_25G_LANE_BASE + (page * SERDES_25G_LANE_SIZE) + offset);
-		break;
-	default:
-		al_err("%s: wrong serdes type %d\n", __func__, type);
-		return -1;
-	}
-
-	al_reg_write32(&regs_base->gen.reg_addr, addr);
-	*data = al_reg_read32(&regs_base->gen.reg_data);
-
-	al_dbg("%s: return(%u)\n", __func__, *data);
-
-	return 0;
-}
-
-static int al_serdes_25g_reg_write(
-	struct al_serdes_grp_obj	*obj,
-	enum al_serdes_reg_page		page,
-	enum al_serdes_reg_type		type,
-	uint16_t			offset,
-	uint8_t				data)
-{
-	struct al_serdes_c_regs __iomem	*regs_base = obj->regs_base;
-	uint32_t addr = 0;
-
-	al_dbg("%s(%p, %d, %d, %u)\n", __func__, obj, page, type, offset);
-
-	al_assert(obj);
-
-	switch (page) {
-	case AL_SRDS_REG_PAGE_TOP:
-		addr = (SERDES_25G_TOP_BASE + offset);
-		break;
-	case AL_SRDS_REG_PAGE_4_COMMON:
-		addr = (SERDES_25G_CM_BASE + offset);
-		break;
-	case AL_SRDS_REG_PAGE_0_LANE_0:
-	case AL_SRDS_REG_PAGE_1_LANE_1:
-		addr = (SERDES_25G_LANE_BASE + (page * SERDES_25G_LANE_SIZE) + offset);
-		break;
-	default:
-		al_err("%s: wrong serdes type %d\n", __func__, type);
-		return -1;
-	}
-
-	al_reg_write32(&regs_base->gen.reg_addr, addr);
-	al_reg_write32(&regs_base->gen.reg_data, (data | SERDES_C_GEN_REG_DATA_STRB_MASK));
-
-	al_dbg("%s: write(%u)\n", __func__, data);
-
-	return 0;
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static int al_serdes_25g_reg_masked_read(
-	struct al_serdes_grp_obj	*obj,
-	enum al_serdes_reg_page		page,
-	uint16_t			offset,
-	uint8_t				mask,
-	uint8_t				shift,
-	uint8_t				*data)
-{
-	uint8_t val;
-	int status = 0;
-
-	status = al_serdes_25g_reg_read(obj, page, 0, offset, &val);
-	if (status)
-		return status;
-
-	*data = AL_REG_FIELD_GET(val, mask, shift);
-
-	return 0;
-}
-
-static int al_serdes_25g_reg_masked_write(
-	struct al_serdes_grp_obj	*obj,
-	enum al_serdes_reg_page		page,
-	uint16_t			offset,
-	uint8_t				mask,
-	uint8_t				shift,
-	uint8_t				data)
-{
-	uint8_t val;
-	int status = 0;
-
-	status = al_serdes_25g_reg_read(obj, page, 0, offset, &val);
-	if (status)
-		return status;
-
-	val &= (~mask);
-	val |= (data << shift);
-	return al_serdes_25g_reg_write(obj, page, 0, offset, val);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-#define SERDES_25G_MB_RESP_BYTES	16
-#define SERDES_25G_MB_TIMEOUT		5000000 /* uSec */
-
-static int al_serdes_25g_mailbox_send_cmd(
-	struct al_serdes_grp_obj	*obj,
-	uint8_t				cmd,
-	uint8_t				*data,
-	uint8_t				data_len)
-{
-	uint8_t val;
-	int i;
-	uint32_t timeout = SERDES_25G_MB_TIMEOUT;
-
-	if (data_len > AL_SERDES_MB_MAX_DATA_LEN) {
-		al_err("Cannot send command, data too long\n");
-		return -1;
-	}
-
-	/* Wait for CMD_FLAG to clear */
-	while(1) {
-		al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
-				       SERDES_25G_TOP_CMD_FLAG_ADDR, &val);
-		if (val == 0)
-			break;
-
-		if (timeout == 0) {
-			al_err("%s: timeout occurred waiting to CMD_FLAG\n", __func__);
-			return -1;
-		}
-
-		timeout--;
-		al_udelay(1);
-	}
-
-	for (i = 0; i < data_len; i++) {
-		al_serdes_25g_reg_write(obj, AL_SRDS_REG_PAGE_TOP, 0,
-					(SERDES_25G_TOP_CMD_DATA0_ADDR + i), data[i]);
-	}
-
-	/* this write will set CMD_FLAG automatically */
-	al_serdes_25g_reg_write(obj, AL_SRDS_REG_PAGE_TOP, 0, SERDES_25G_TOP_CMD_ADDR, cmd);
-
-	return 0;
-}
-
-static int al_serdes_25g_mailbox_recv_rsp(
-	struct al_serdes_grp_obj	*obj,
-	uint8_t				*rsp_code,
-	uint8_t				*data,
-	uint8_t				*data_len)
-{
-	uint8_t val;
-	int i;
-	uint32_t timeout = SERDES_25G_MB_TIMEOUT;
-
-	/* wait for RSP_FLAG to set */
-	while(1) {
-		al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
-				       SERDES_25G_TOP_RSP_FLAG_ADDR, &val);
-		if (val == 0x1)
-			break;
-
-		if (timeout == 0) {
-			al_err("%s: timeout occurred waiting to RSP_FLAG\n", __func__);
-			*data_len = 0;
-			return -1;
-		}
-
-		timeout--;
-		al_udelay(1);
-	}
-
-	/* Grab the response code and data */
-	al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
-				SERDES_25G_TOP_RSP_ADDR, rsp_code);
-
-	for (i = 0; i < SERDES_25G_MB_RESP_BYTES; i++) {
-		al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
-				(SERDES_25G_TOP_RSP_DATA0_ADDR + i), &data[i]);
-	}
-
-	/* clear the RSP_FLAG (write 1 to clear) */
-	al_serdes_25g_reg_write(obj, AL_SRDS_REG_PAGE_TOP, 0,
-				SERDES_25G_TOP_RSP_FLAG_ADDR, 0x1);
-
-	*data_len = SERDES_25G_MB_RESP_BYTES;
-
-	return 0;
-}
-
-/******************************************************************************/
-/******************************************************************************/
-static void al_serdes_25g_bist_rx_enable(
-	struct al_serdes_grp_obj	*obj,
-	enum al_serdes_lane		lane,
-	al_bool				enable)
-{
-	if (enable) {
-		switch (lane) {
-		case 0:
-			al_serdes_25g_reg_masked_write(
-					obj,
-					AL_SRDS_REG_PAGE_TOP,
-					SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR,
-					SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_MASK,
-					SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_SHIFT,
-					0x1);
-			al_serdes_25g_reg_masked_write(
-					obj,
-					AL_SRDS_REG_PAGE_TOP,
-					SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR,
-					SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_MASK,
-					SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_SHIFT,
-					0x1);
-			break;
-		case 1:
-			al_serdes_25g_reg_masked_write(
-					obj,
-					AL_SRDS_REG_PAGE_TOP,
-					SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR,
-					SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_MASK,
-					SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_SHIFT,
-					0x1);
-
-			al_serdes_25g_reg_masked_write(
-					obj,
-					AL_SRDS_REG_PAGE_TOP,
-					SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR,
-					SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_MASK,
-					SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_SHIFT,
-					0x1);
-			break;
-		default:
-			al_err("%s: Wrong serdes lane %d\n", __func__, lane);
-			return;
-		}
-
-		al_serdes_25g_reg_masked_write(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_ADDR,
-				SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_MASK,
-				SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT,
-				0);
-		al_serdes_25g_reg_masked_write(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
-				SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK,
-				SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT,
-				1);
-		al_serdes_25g_reg_masked_write(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
-				SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_MASK,
-				SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_SHIFT,
-				6);
-	} else {
-		/* clear counters */
-		al_serdes_25g_reg_masked_write(
-					obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
-					SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK,
-					SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT,
-					1);
-
-		al_serdes_25g_reg_masked_write(
-					obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
-					SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK,
-					SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT,
-					0);
-
-		al_msleep(AL_SERDES_25G_WAIT_FOR_READY_TO);
-
-		/* disable */
-		al_serdes_25g_reg_masked_write(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
-				SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK,
-				SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT,
-				0);
-	}
-}
-
-// TODO: [Guy] change API to be per lane.
-static void al_serdes_25g_bist_pattern_select(
-	struct al_serdes_grp_obj	*obj,
-	enum al_serdes_bist_pattern	pattern,
-	uint8_t				*user_data)
-{
-	enum al_serdes_lane lane;
-	uint8_t val = 0;
-
-	switch (pattern) {
-	case AL_SRDS_BIST_PATTERN_USER:
-		al_assert(user_data);
-		val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS_USER;
-		break;
-	case AL_SRDS_BIST_PATTERN_PRBS7:
-		val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS7;
-		break;
-	case AL_SRDS_BIST_PATTERN_PRBS23:
-		val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS23;
-		break;
-	case AL_SRDS_BIST_PATTERN_PRBS31:
-		val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS31;
-		break;
-	case AL_SRDS_BIST_PATTERN_CLK1010:
-	default:
-		al_err("%s: invalid pattern (%d)\n", __func__, pattern);
-		al_assert(0);
-	}
-
-	for (lane = AL_SRDS_LANE_0; lane <= AL_SRDS_LANE_1; lane++) {
-		if (pattern == AL_SRDS_BIST_PATTERN_USER) {
-			int i;
-
-			for (i = 0; i < SERDES_25G_LANE_TX_BIST_UDP_NUM_BYTES; i++)
-				al_serdes_25g_reg_write(
-						obj,
-						(enum al_serdes_reg_page)lane,
-						0,
-						SERDES_25G_LANE_TX_BIST_UDP_ADDR(i),
-						user_data[i]);
-		}
-
-		al_serdes_25g_reg_masked_write(
-					obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_TX_BIST_CTRL_ADDR,
-					SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_MASK,
-					SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_SHIFT,
-					val);
-	}
-}
-
-static void al_serdes_25g_bist_tx_enable(
-	struct al_serdes_grp_obj	*obj,
-	enum al_serdes_lane		lane,
-	al_bool				enable)
-{
-	if (enable) {
-		al_serdes_25g_reg_masked_write(
-					obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_TX_BIST_CTRL_ADDR,
-					SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK,
-					SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT,
-					0x1);
-		al_serdes_25g_reg_masked_write(
-					obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR,
-					SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK,
-					SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT,
-					0x2);
-
-		switch (lane) {
-		case AL_SRDS_LANE_0:
-			al_serdes_25g_reg_masked_write(
-					obj,
-					AL_SRDS_REG_PAGE_TOP,
-					SERDES_25G_TOP_CLOCK_LN0_CLK_TX_ADDR,
-					SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_MASK,
-					SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_SHIFT,
-					0x1);
-			break;
-		case AL_SRDS_LANE_1:
-			al_serdes_25g_reg_masked_write(
-					obj,
-					AL_SRDS_REG_PAGE_TOP,
-					SERDES_25G_TOP_CLOCK_LN1_CLK_TX_ADDR,
-					SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_MASK,
-					SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_SHIFT,
-					0x1);
-			break;
-		default:
-			al_err("%s: Wrong serdes lane %d\n", __func__, lane);
-				return;
-		}
-	} else {
-		al_serdes_25g_reg_masked_write(
-					obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_TX_BIST_CTRL_ADDR,
-					SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK,
-					SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT,
-					0);
-	}
-
-}
-
-static void al_serdes_25g_bist_rx_status(
-	struct al_serdes_grp_obj	*obj,
-	enum al_serdes_lane		lane,
-	al_bool				*is_locked,
-	al_bool				*err_cnt_overflow,
-	uint32_t			*err_cnt)
-{
-	uint8_t status;
-	uint8_t err1;
-	uint8_t err2;
-	uint8_t err3;
-
-	al_serdes_25g_reg_masked_read(
-		obj,
-		(enum al_serdes_reg_page)lane,
-		SERDES_25G_LANE_RX_BIST_STATUS_ADDR,
-		SERDES_25G_LANE_RX_BIST_STATUS_STATE_MASK,
-		SERDES_25G_LANE_RX_BIST_STATUS_STATE_SHIFT,
-		&status);
-
-	if (status != 3) {
-		*is_locked = AL_FALSE;
-		return;
-	}
-
-	*is_locked = AL_TRUE;
-	*err_cnt_overflow = AL_FALSE;
-
-	al_serdes_25g_reg_masked_read(
-		obj,
-		(enum al_serdes_reg_page)lane,
-		SERDES_25G_LANE_RX_BIST_BER_STATUS0_ADDR,
-		SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_MASK,
-		SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_SHIFT,
-		&err1);
-
-	al_serdes_25g_reg_masked_read(
-		obj,
-		(enum al_serdes_reg_page)lane,
-		SERDES_25G_LANE_RX_BIST_BER_STATUS1_ADDR,
-		SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_MASK,
-		SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_SHIFT,
-		&err2);
-
-	al_serdes_25g_reg_masked_read(
-		obj,
-		(enum al_serdes_reg_page)lane,
-		SERDES_25G_LANE_RX_BIST_BER_STATUS2_ADDR,
-		SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_MASK,
-		SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_SHIFT,
-		&err3);
-
-	*err_cnt = (err1 + (err2 << 8) + (err3 << 16));
-}
-
-#define SERDES_MB_CMD_SWING_CFG		0x83
-#define SERDES_MB_CMD_SAMPLES_COUNT	0x84
-#define SERDES_MB_CMD_START_MEASURE	0x82
-
-#define SERDES_MB_RSP_CODE_0		0
-#define SERDES_MB_RSP_CODE_1		1
-#define SERDES_MB_RSP_CODE_2		2
-
-static int al_serdes_25g_eye_diag_run(
-	struct al_serdes_grp_obj	*obj,
-	enum al_serdes_lane		lane,
-	int				x_start,
-	int				x_stop,
-	unsigned int			x_step,
-	int				y_start,
-	int				y_stop,
-	unsigned int			y_step,
-	uint64_t			ber_target,
-	uint64_t			*buf,
-	uint32_t			buf_size)
-{
-	int rc;
-	uint8_t rsp_code;
-	uint8_t data[16];
-	uint8_t data_len;
-	uint32_t total_bits;
-	uint8_t bits_left_curr_sample;
-	uint8_t bits_left_curr_byte;
-	uint32_t byte = 0;
-	uint32_t x = 0;
-	uint32_t x_samples = (((x_stop - x_start) / x_step) + 1);
-	uint32_t y = 0;
-	uint32_t y_samples = (((y_stop - y_start) / y_step) + 1);
-	uint8_t sample_width = (64 - __builtin_clzl(ber_target));
-	uint8_t msb;
-	uint8_t lsb;
-	uint32_t samples_left = ((x_samples * y_samples));
-	uint8_t sign = 0;
-
-	al_assert(buf_size == (samples_left * sizeof(uint64_t)));
-
-	al_memset(buf, 0, buf_size);
-
-	if (y_start < 0) {
-		y_start *= -1;
-		sign |= 0x1;
-	}
-
-	if (y_stop < 0) {
-		y_stop *= -1;
-		sign |= 0x2;
-	}
-
-	data[0] = lane;
-	data[1] = x_start;
-	data[2] = x_stop;
-	data[3] = x_step;
-	data[4] = y_start;
-	data[5] = y_stop;
-	data[6] = sign;
-	data[7] = y_step;
-
-	rc = al_serdes_25g_mailbox_send_cmd(
-				obj,
-				SERDES_MB_CMD_SWING_CFG,
-				data,
-				8);
-
-	if (rc) {
-		al_err("%s: Failed to send command %d to mailbox.\n",
-			__func__, SERDES_MB_CMD_SWING_CFG);
-		return rc;
-	}
-
-	rc = al_serdes_25g_mailbox_recv_rsp(
-				obj,
-				&rsp_code,
-				data,
-				&data_len);
-
-	if ((rc) || (rsp_code != SERDES_MB_RSP_CODE_0)) {
-		al_err("%s: Failed to send command %d to mailbox. rsp_code %d\n",
-			__func__, SERDES_MB_CMD_SWING_CFG, rsp_code);
-
-		return (ETIMEDOUT);
-	}
-
-	al_assert(sample_width <= 40);
-
-	data[0] = lane;
-	data[1] = ((ber_target >> 32) & 0xFF);
-	data[2] = ((ber_target >> 24) & 0xFF);
-	data[3] = ((ber_target >> 16) & 0xFF);
-	data[4] = ((ber_target >> 8) & 0xFF);
-	data[5] = (ber_target & 0xFF);
-
-	rc = al_serdes_25g_mailbox_send_cmd(
-				obj,
-				SERDES_MB_CMD_SAMPLES_COUNT,
-				data,
-				6);
-
-	if (rc) {
-		al_err("%s: Failed to send command %d to mailbox.\n",
-			__func__, SERDES_MB_CMD_SAMPLES_COUNT);
-		return rc;
-	}
-
-	rc = al_serdes_25g_mailbox_recv_rsp(
-				obj,
-				&rsp_code,
-				data,
-				&data_len);
-
-	if ((rc) || (rsp_code != SERDES_MB_RSP_CODE_0)) {
-		al_err("%s: Failed to send command %d to mailbox. rsp_code %d\n",
-			__func__, SERDES_MB_CMD_SAMPLES_COUNT, rsp_code);
-
-		return (ETIMEDOUT);
-	}
-
-	rc = al_serdes_25g_mailbox_send_cmd(
-				obj,
-				SERDES_MB_CMD_START_MEASURE,
-				data,
-				0);
-
-	bits_left_curr_sample = sample_width;
-
-	while (rsp_code != SERDES_MB_RSP_CODE_1) {
-		uint8_t num_bits = 0;
-
-		rc = al_serdes_25g_mailbox_recv_rsp(
-				obj,
-				&rsp_code,
-				data,
-				&data_len);
-
-		if ((rc != 0) || (rsp_code > SERDES_MB_RSP_CODE_2)) {
-			al_err("%s: command %d return failure. rsp_code %d\n",
-			__func__, SERDES_MB_CMD_START_MEASURE, rsp_code);
-
-			return (ETIMEDOUT);
-		}
-		byte = 0;
-		total_bits = data_len * 8;
-		bits_left_curr_byte = 8;
-		while (total_bits > 0) {
-			num_bits = al_min_t(uint8_t, bits_left_curr_sample, bits_left_curr_byte);
-
-			buf[(y * x_samples) + x] <<= num_bits;
-			msb = bits_left_curr_byte - 1;
-			lsb = msb - num_bits + 1;
-			buf[(y * x_samples) + x] |= (data[byte] & AL_FIELD_MASK(msb, lsb) >> lsb);
-
-			total_bits -= num_bits;
-
-			bits_left_curr_byte -= num_bits;
-			if (!bits_left_curr_byte) {
-				bits_left_curr_byte = 8;
-				byte++;
-			}
-
-			bits_left_curr_sample -= num_bits;
-			if (!bits_left_curr_sample) {
-				y++;
-				if (y == y_samples) {
-					y = 0;
-					x++;
-				}
-
-				samples_left--;
-				bits_left_curr_sample = sample_width;
-			}
-
-			if (samples_left == 0)
-				break;
-		}
-
-		if ((samples_left == 0) && (rsp_code != SERDES_MB_RSP_CODE_1)) {
-			rc = al_serdes_25g_mailbox_recv_rsp(
-						obj,
-						&rsp_code,
-						data,
-						&data_len);
-			if ((rc) || (rsp_code == SERDES_MB_RSP_CODE_0)) {
-				al_err("%s: Parsed enough samples but f/w is still sending more\n",
-					__func__);
-
-				return -EIO;
-			}
-			break;
-		}
-	}
-
-	if (samples_left > 0) {
-		al_err("%s: Still need more samples but f/w has stopped sending them!?!?!?\n",
-			__func__);
-
-		return -EIO;
-	}
-
-	return 0;
-}
-
-#define SERDES_25G_EYE_X_MIN		1
-#define SERDES_25G_EYE_X_MAX		127
-#define SERDES_25G_EYE_Y_MIN		-200
-#define SERDES_25G_EYE_Y_MAX		200
-#define SERDES_25G_EYE_SIZE_MAX_SAMPLES	401
-#define SERDES_25G_EYE_SIZE_BER_TARGET	0xffff
-#define SERDES_25G_EYE_SIZE_ERR_TH	10
-
-static int al_serdes_25g_calc_eye_size(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane		lane,
-		int				*width,
-		int				*height)
-{
-	uint64_t samples[SERDES_25G_EYE_SIZE_MAX_SAMPLES];
-	int i;
-	int _width = 0;
-	int _height = 0;
-	int rc;
-	int mid_x = ((SERDES_25G_EYE_X_MIN + SERDES_25G_EYE_X_MAX) / 2);
-	int mid_y = ((SERDES_25G_EYE_Y_MIN + SERDES_25G_EYE_Y_MAX) / 2);
-
-	*height = 0;
-	*width = 0;
-
-	rc = al_serdes_25g_eye_diag_run(obj,
-					lane,
-					mid_x,
-					mid_x,
-					1,
-					SERDES_25G_EYE_Y_MIN,
-					SERDES_25G_EYE_Y_MAX,
-					1,
-					SERDES_25G_EYE_SIZE_BER_TARGET,
-					samples,
-					((SERDES_25G_EYE_Y_MAX - SERDES_25G_EYE_Y_MIN + 1) *
-					  sizeof(uint64_t)));
-
-	if (rc) {
-		al_err("%s: failed to run eye_diag\n", __func__);
-		return rc;
-	}
-
-	for (i = (mid_y - SERDES_25G_EYE_Y_MIN);
-		((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) &&
-			(i < (SERDES_25G_EYE_Y_MAX - SERDES_25G_EYE_Y_MIN + 1)));
-		i++, (_height)++)
-		;
-	for (i = (mid_y - SERDES_25G_EYE_Y_MIN);
-		((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) && (i >= 0));
-		i--, (_height)++)
-		;
-
-	rc = al_serdes_25g_eye_diag_run(obj,
-					lane,
-					SERDES_25G_EYE_X_MIN,
-					SERDES_25G_EYE_X_MAX,
-					1,
-					mid_y,
-					mid_y,
-					1,
-					SERDES_25G_EYE_SIZE_BER_TARGET,
-					samples,
-					((SERDES_25G_EYE_X_MAX - SERDES_25G_EYE_X_MIN + 1) *
-					  sizeof(uint64_t)));
-
-	if (rc) {
-		al_err("%s: failed to run eye_diag\n", __func__);
-		return rc;
-	}
-
-	for (i = (mid_x - SERDES_25G_EYE_X_MIN);
-		((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) &&
-			(i < (SERDES_25G_EYE_X_MAX - SERDES_25G_EYE_X_MIN + 1)));
-		i++, (_width)++)
-		;
-	for (i = (mid_x - SERDES_25G_EYE_X_MIN);
-		((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) && (i >= 0));
-		i--, (_width)++)
-		;
-
-	*height = _height;
-	*width = _width;
-
-	return 0;
-}
-
-
-static void al_serdes_25g_tx_advanced_params_set(struct al_serdes_grp_obj	*obj,
-					enum al_serdes_lane			lane,
-					void					*tx_params)
-{
-	struct al_serdes_adv_tx_params	*params = tx_params;
-	uint32_t timeout = 5000;
-	uint8_t val = 0;
-
-	al_serdes_25g_reg_masked_write(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT,
-					params->c_minus_1);
-
-	al_serdes_25g_reg_masked_write(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT,
-					params->c_plus_1);
-
-	al_serdes_25g_reg_masked_write(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT,
-					params->total_driver_units);
-
-	al_serdes_25g_reg_masked_write(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT,
-					1);
-
-
-	/* wait for acknowledge */
-	while (1) {
-		al_serdes_25g_reg_masked_read(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_DRV_TXEQ_STATUS0_ADDR,
-					SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_MASK,
-					SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_SHIFT,
-					&val);
-		if (val == 1)
-			break;
-
-		if (timeout == 0) {
-			al_err("%s: timeout occurred waiting to FW ack\n", __func__);
-			break;
-		}
-
-		timeout--;
-		al_udelay(1);
-	}
-
-	al_serdes_25g_reg_masked_write(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT,
-					0);
-}
-
-static void al_serdes_25g_tx_advanced_params_get(struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane			lane,
-		void					*tx_params)
-{
-	struct al_serdes_adv_tx_params	*params = tx_params;
-
-	al_serdes_25g_reg_masked_read(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT,
-					&params->c_minus_1);
-
-	al_serdes_25g_reg_masked_read(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT,
-					&params->c_plus_1);
-
-	al_serdes_25g_reg_masked_read(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK,
-					SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT,
-					&params->total_driver_units);
-}
-
-static al_bool al_serdes_25g_cdr_is_locked(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane		lane)
-{
-	uint8_t reg;
-
-	al_serdes_25g_reg_masked_read(obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_ADDR,
-				SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_MASK,
-				SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT,
-				&reg);
-
-	return !!reg;
-
-}
-
-static al_bool al_serdes_25g_rx_valid(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane		lane)
-{
-	uint8_t reg;
-
-	al_serdes_25g_reg_masked_read(obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR,
-				SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK,
-				SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT,
-				&reg);
-
-	return !!reg;
-
-}
-
-static al_bool al_serdes_25g_signal_is_detected(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane		lane)
-{
-	struct al_serdes_c_regs __iomem	*regs_base = obj->regs_base;
-	uint32_t reg;
-	al_bool signal_detect = AL_FALSE;
-
-	reg = al_reg_read32(&regs_base->lane[lane].stat);
-
-	signal_detect = ((reg & (SERDES_C_LANE_STAT_LN_STAT_LOS |
-				 SERDES_C_LANE_STAT_LN_STAT_LOS_DEGLITCH)) ?
-					AL_FALSE : AL_TRUE);
-
-	return signal_detect;
-
-}
-
-static int al_serdes_25g_rx_equalization(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane		lane)
-{
-	struct al_serdes_c_regs __iomem	*regs_base = obj->regs_base;
-	uint32_t ready_mask = (SERDES_C_GEN_STATUS_CM0_RST_PD_READY | SERDES_C_GEN_STATUS_CM0_OK_O);
-	uint32_t reset_mask;
-	uint32_t timeout;
-	uint32_t reg_val;
-	uint32_t retries = AL_SERDES_25G_RESET_NUM_RETRIES;
-	int status = 0;
-
-	if (lane == 0) {
-		ready_mask |= SERDES_C_GEN_STATUS_LN0_RST_PD_READY;
-		reset_mask = SERDES_C_GEN_RST_LN0_RST_N;
-	} else {
-		ready_mask |= SERDES_C_GEN_STATUS_LN1_RST_PD_READY;
-		reset_mask = SERDES_C_GEN_RST_LN1_RST_N;
-	}
-
-	while (retries > 0) {
-		timeout = AL_SERDES_25G_WAIT_FOR_READY_TO;
-		status = 0;
-
-		al_reg_write32_masked(&regs_base->gen.rst, reset_mask, 0);
-
-		al_msleep(AL_SERDES_25G_RESET_TO);
-
-		al_serdes_25g_reg_masked_write(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_ADDR,
-					SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_MASK,
-					SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT,
-					0);
-
-		al_serdes_25g_reg_masked_write(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR,
-					SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_MASK,
-					SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT,
-					7);
-
-		al_serdes_25g_reg_masked_write(obj,
-					(enum al_serdes_reg_page)lane,
-					SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR,
-					SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_MASK,
-					SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT,
-					15);
-
-		al_msleep(AL_SERDES_25G_RESET_TO);
-
-		al_reg_write32_masked(&regs_base->gen.rst, reset_mask, reset_mask);
-
-		while (1) {
-			reg_val = al_reg_read32(&regs_base->gen.status);
-			if ((reg_val & ready_mask) == ready_mask)
-				break;
-
-			al_udelay(1);
-			timeout--;
-
-			if (timeout == 0) {
-				al_err("%s: Timeout waiting for serdes ready\n", __func__);
-				status = ETIMEDOUT;
-				retries--;
-				break;
-			}
-		}
-
-		if (status)
-			continue;
-
-		while (1) {
-			reg_val = al_reg_read32(&regs_base->lane[lane].stat);
-			reg_val &= (SERDES_C_LANE_STAT_LNX_STAT_OK |
-				    SERDES_C_LANE_STAT_LN_STAT_RXVALID);
-			if (reg_val == (SERDES_C_LANE_STAT_LNX_STAT_OK |
-					SERDES_C_LANE_STAT_LN_STAT_RXVALID))
-				break;
-
-			al_udelay(1);
-			timeout--;
-
-			if (timeout == 0) {
-				al_err("%s: TO waiting for lane ready (%x)\n", __func__, reg_val);
-				status = ETIMEDOUT;
-				retries--;
-				break;
-			}
-		}
-
-		if (status)
-			continue;
-
-		break;
-	}
-
-	if (retries == 0) {
-		al_err("%s: Failed to run equalization\n", __func__);
-		status = ETIMEDOUT;
-	}
-
-	return status;
-
-}
-
-#define AL_SERDES_25G_GCFSM2_READ_TIMEOUT		2000000 /* uSec */
-
-static int al_serdes_25g_gcfsm2_read(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane		lane,
-		uint8_t			offset,
-		uint16_t		*data)
-{
-	int status = 0;
-	uint32_t timeout = AL_SERDES_25G_GCFSM2_READ_TIMEOUT;
-	uint8_t ack = 0;
-	uint8_t data_low, data_high;
-
-	al_assert(data);
-
-	/* Make sure GCFSM2 REQuest is off */
-	al_serdes_25g_reg_masked_write(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT,
-			0);
-	/* Write GCFSM2 CMD; CMD=0 for Read Request */
-	al_serdes_25g_reg_masked_write(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL1_ADDR,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_MASK,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_SHIFT,
-			0);
-	/* Write GCFSM2 the Address we wish to read */
-	al_serdes_25g_reg_write(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR,
-			offset);
-	/* Issue a command REQuest */
-	al_serdes_25g_reg_masked_write(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT,
-			1);
-	/* Poll on GCFSM2 ACK */
-	while (1) {
-		al_serdes_25g_reg_masked_read(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_GCFSM2_CMD_STATUS_ADDR,
-				SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_MASK,
-				SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_SHIFT,
-				&ack);
-
-		if (ack || (timeout == 0))
-			break;
-
-		timeout--;
-		al_udelay(1);
-	}
-
-	if (ack) {
-		/* Read 12bit of register value */
-		al_serdes_25g_reg_read(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				0,
-				SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_ADDR,
-				&data_low);
-		al_serdes_25g_reg_masked_read(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_ADDR,
-				SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_MASK,
-				SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_SHIFT,
-				&data_high);
-		*data = (data_high << 8) | data_low;
-	} else {
-		al_err("%s: TO waiting for GCFSM2 req to complete (%x)\n", __func__, offset);
-		status = ETIMEDOUT;
-	}
-
-	/* Deassert the GCFSM2 REQuest */
-	al_serdes_25g_reg_masked_write(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK,
-			SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT,
-			0);
-
-	return status;
-}
-
-enum al_serdes_25g_rx_leq_fsm_opcode {
-	AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ		= 0x1,
-	AL_SERDES_25G_RX_LEQ_FSM_OPCODE_WRITE		= 0x2,
-};
-
-enum al_serdes_25g_rx_leq_fsm_target {
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_AGC_SOURCE		= 0x1,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_PLE_ATT			= 0x2,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_LFG			= 0x3,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_GN_APG			= 0x4,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_GNEQ_CCL_LFG	= 0x5,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_HFG_SQL			= 0x6,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBF			= 0x8,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBG			= 0x9,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_VSCAN			= 0xA,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_HSCAN			= 0xB,
-	AL_SERDES_25G_RX_LEQ_FSM_TARGET_EYE_INTF		= 0xC,
-};
-
-#define AL_SERDES_25G_RX_LEQ_FSM_TIMEOUT		2000000 /* uSec */
-
-static int al_serdes_25g_rx_leq_fsm_op(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane	lane,
-		enum al_serdes_25g_rx_leq_fsm_opcode	opcode,
-		enum al_serdes_25g_rx_leq_fsm_target	target,
-		uint8_t	val,
-		uint8_t	*data,
-		uint8_t	*err)
-{
-	uint32_t reg;
-	uint32_t timeout = AL_SERDES_25G_RX_LEQ_FSM_TIMEOUT;
-	uint8_t ack = 0;
-	int status = 0;
-
-	al_assert(data);
-	al_assert(err);
-
-	/* Write the OpCode & Target to LEQ FSM */
-	reg = (target << 4) | opcode;
-	al_serdes_25g_reg_write(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_ADDR,
-			reg);
-
-	/* Write 0 as MiscOption value to LEQ FSM */
-	al_serdes_25g_reg_write(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_ADDR,
-			0);
-
-	/* Write the ArgumentValue to LEQ FSM if needed*/
-	if (opcode == AL_SERDES_25G_RX_LEQ_FSM_OPCODE_WRITE) {
-		al_serdes_25g_reg_write(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				0,
-				SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_ADDR,
-				val);
-	}
-
-	/* Issue an LEQ FSM Command Request */
-	al_serdes_25g_reg_masked_write(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR,
-			SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK,
-			SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT,
-			1);
-
-	/* Poll on LEQ FSM Command acknowledge */
-	while (1) {
-		al_serdes_25g_reg_masked_read(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_ADDR,
-				SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_MASK,
-				SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_SHIFT,
-				&ack);
-
-		if (ack || (timeout == 0))
-			break;
-
-		timeout--;
-		al_udelay(1);
-	}
-
-	if (ack) {
-		uint8_t err1, err2;
-		al_serdes_25g_reg_read(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				0,
-				SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_ADDR,
-				err);
-
-		err1 = (*err &
-			SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_MASK) >>
-			SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_SHIFT;
-		err2 = (*err &
-			SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_MASK) >>
-			SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_SHIFT;
-
-		if (err1 || err2) {
-			al_err("%s: error in RX LEQ FSM req, err status 1=0x%x, err status 2=0x%x",
-					__func__, err1, err2);
-			status = -EIO;
-		}
-
-		/* Read LEQ FSM Command return Value */
-		al_serdes_25g_reg_read(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				0,
-				SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_ADDR,
-				data);
-
-		/* Clear an LEQ FSM Command Request */
-		al_serdes_25g_reg_masked_write(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR,
-				SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK,
-				SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT,
-				0);
-	} else {
-		al_err("%s: TO waiting for RX LEQ FSM req to complete (opcode %x, target %x, val %x)\n",
-				__func__, opcode, target, val);
-		status = ETIMEDOUT;
-	}
-
-	return status;
-}
-
-/* enum values correspond to HW values, don't change! */
-enum al_serdes_25g_tbus_obj {
-	AL_SERDES_25G_TBUS_OBJ_TOP	= 0,
-	AL_SERDES_25G_TBUS_OBJ_CMU	= 1,
-	AL_SERDES_25G_TBUS_OBJ_LANE	= 2,
-};
-
-#define AL_SERDES_25G_TBUS_DELAY	1000 /* uSec */
-#define AL_SERDES_25G_TBUS_ADDR_HIGH_SHIFT	5
-
-static int al_serdes_25g_tbus_read(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane	lane,
-		enum al_serdes_25g_tbus_obj	tbus_obj,
-		uint8_t	offset,
-		uint16_t	*data)
-{
-	uint8_t addr_high, val_high, val_low;
-
-	al_assert(lane < AL_SRDS_NUM_LANES);
-
-	if (tbus_obj == AL_SERDES_25G_TBUS_OBJ_TOP)
-		addr_high = AL_SERDES_25G_TBUS_OBJ_TOP;
-	else if (tbus_obj == AL_SERDES_25G_TBUS_OBJ_CMU)
-		addr_high = AL_SERDES_25G_TBUS_OBJ_CMU;
-	else
-		addr_high = AL_SERDES_25G_TBUS_OBJ_LANE + lane;
-
-	addr_high <<= AL_SERDES_25G_TBUS_ADDR_HIGH_SHIFT;
-
-	al_serdes_25g_reg_write(
-			obj,
-			AL_SRDS_REG_PAGE_TOP,
-			0,
-			SERDES_25G_TOP_TBUS_ADDR_7_0_ADDR,
-			offset);
-
-	al_serdes_25g_reg_write(
-			obj,
-			AL_SRDS_REG_PAGE_TOP,
-			0,
-			SERDES_25G_TOP_TBUS_ADDR_15_8_ADDR,
-			addr_high);
-
-	al_udelay(AL_SERDES_25G_TBUS_DELAY);
-
-	al_serdes_25g_reg_read(
-			obj,
-			AL_SRDS_REG_PAGE_TOP,
-			0,
-			SERDES_25G_TOP_TBUS_DATA_7_0_ADDR,
-			&val_low);
-
-	al_serdes_25g_reg_masked_read(
-			obj,
-			AL_SRDS_REG_PAGE_TOP,
-			SERDES_25G_TOP_TBUS_DATA_11_8_ADDR,
-			SERDES_25G_TOP_TBUS_DATA_11_8_MASK,
-			SERDES_25G_TOP_TBUS_DATA_11_8_SHIFT,
-			&val_high);
-
-	*data = (val_high << 8) | val_low;
-
-	return 0;
-}
-
-#define AL_SERDES_25G_RX_ADV_PARAMS_ATT_MASK	0x07
-#define AL_SERDES_25G_RX_ADV_PARAMS_APG_MASK	0x03
-#define AL_SERDES_25G_RX_ADV_PARAMS_LFG_MASK	0x1F
-#define AL_SERDES_25G_RX_ADV_PARAMS_HFG_MASK	0x1F
-#define AL_SERDES_25G_RX_ADV_PARAMS_MBG_MASK	0x0F
-#define AL_SERDES_25G_RX_ADV_PARAMS_MBF_MASK	0x0F
-#define AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_CNT			8
-#define AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_MASK		0x1F
-#define AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_SIGN_SHIFT	7
-
-static void al_serdes_25g_rx_advanced_params_get(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane			lane,
-		void					*rx_params)
-{
-	struct al_serdes_25g_adv_rx_params *params = rx_params;
-	uint8_t value, err;
-	int8_t tap_weight;
-	uint8_t tap_sign;
-	int8_t *tap_ptr_arr[AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_CNT];
-	int rc;
-	int i;
-
-	rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
-			AL_SERDES_25G_RX_LEQ_FSM_TARGET_PLE_ATT, 0, &value, &err);
-	if (rc || err) {
-		al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read att, rc %d, err %d\n",
-				__func__, rc, err);
-		return;
-	}
-	params->att = value & AL_SERDES_25G_RX_ADV_PARAMS_ATT_MASK;
-
-	rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
-			AL_SERDES_25G_RX_LEQ_FSM_TARGET_GN_APG, 0, &value, &err);
-	if (rc || err) {
-		al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read apg, rc %d, err %d\n",
-				__func__, rc, err);
-		return;
-	}
-	params->apg = value & AL_SERDES_25G_RX_ADV_PARAMS_APG_MASK;
-
-	rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
-			AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_LFG, 0, &value, &err);
-	if (rc || err) {
-		al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read lfg, rc %d, err %d\n",
-				__func__, rc, err);
-		return;
-	}
-	params->lfg = value & AL_SERDES_25G_RX_ADV_PARAMS_LFG_MASK;
-
-	rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
-			AL_SERDES_25G_RX_LEQ_FSM_TARGET_HFG_SQL, 0, &value, &err);
-	if (rc || err) {
-		al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read hfg, rc %d, err %d\n",
-				__func__, rc, err);
-		return;
-	}
-	params->hfg = value & AL_SERDES_25G_RX_ADV_PARAMS_HFG_MASK;
-
-	rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
-			AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBG, 0, &value, &err);
-	if (rc || err) {
-		al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read mbg, rc %d, err %d\n",
-				__func__, rc, err);
-		return;
-	}
-	params->mbg = value & AL_SERDES_25G_RX_ADV_PARAMS_MBG_MASK;
-
-	rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
-			AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBF, 0, &value, &err);
-	if (rc || err) {
-		al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read mbf, rc %d, err %d\n",
-				__func__, rc, err);
-		return;
-	}
-	params->mbf = value & AL_SERDES_25G_RX_ADV_PARAMS_MBF_MASK;
-
-	tap_ptr_arr[0] = &params->dfe_first_tap_even0_ctrl;
-	tap_ptr_arr[1] = &params->dfe_first_tap_even1_ctrl;
-	tap_ptr_arr[2] = &params->dfe_first_tap_odd0_ctrl;
-	tap_ptr_arr[3] = &params->dfe_first_tap_odd1_ctrl;
-	tap_ptr_arr[4] = &params->dfe_second_tap_ctrl;
-	tap_ptr_arr[5] = &params->dfe_third_tap_ctrl;
-	tap_ptr_arr[6] = &params->dfe_fourth_tap_ctrl;
-	tap_ptr_arr[7] = &params->dfe_fifth_tap_ctrl;
-
-	for (i = 0; i < AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_CNT; i++) {
-		al_serdes_25g_reg_read(
-				obj,
-				(enum al_serdes_reg_page)lane,
-				0,
-				SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_ADDR + i,
-				&value);
-
-		tap_weight = value & AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_MASK;
-		tap_sign = (value & AL_BIT(AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_SIGN_SHIFT)) >>
-				AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_SIGN_SHIFT;
-		if (tap_sign == 0)
-			tap_weight = 0 - tap_weight;
-
-		*tap_ptr_arr[i] = tap_weight;
-	}
-}
-
-#define AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_ADDR		0x0B
-#define AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_MASK		0x3F
-#define AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_SIGN_SHIFT	7
-#define AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_ADDR		0x0C
-#define AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_MASK		0xFFF
-
-static void al_serdes_25g_tx_diag_info_get(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane		lane,
-		void *tx_info)
-{
-	struct al_serdes_25g_tx_diag_info *info = tx_info;
-	uint8_t cal_x1, cal_x1_fixed, cal_x2, cal_xp5_fixed;
-	uint16_t val16, sign;
-	uint8_t val8, abs;
-	int rc;
-
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR,
-			&val8);
-	info->regulated_supply = val8 & SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK;
-
-	rc = al_serdes_25g_gcfsm2_read(
-			obj,
-			lane,
-			AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_ADDR,
-			&val16);
-	if (rc) {
-		al_err("%s: al_serdes_25g_gcfsm2_read failed to read dcd_trim, rc %d\n",
-				__func__, rc);
-		return;
-	}
-
-	abs = val16 & AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_MASK;
-	sign = (val16 & AL_BIT(AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_SIGN_SHIFT)) >>
-			AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_SIGN_SHIFT;
-	if (sign)
-		info->dcd_trim = abs;
-	else
-		info->dcd_trim = 0 - abs;
-
-	rc = al_serdes_25g_gcfsm2_read(
-			obj,
-			lane,
-			AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_ADDR,
-			&val16);
-	if (rc) {
-		al_err("%s: al_serdes_25g_gcfsm2_read failed to read clk_delay, rc %d\n",
-				__func__, rc);
-		return;
-	}
-	info->clk_delay = val16 & AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_MASK;
-
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_CM_TOP_AFE_TXTC_CTRL2_ADDR,
-			&val8);
-	cal_x1 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_MASK) >>
-			SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_SHIFT;
-	cal_x1_fixed = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_MASK) >>
-			SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_SHIFT;
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_CM_TOP_AFE_TXTC_CTRL3_ADDR,
-			&val8);
-	cal_x2 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_MASK) >>
-			SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_SHIFT;
-	cal_xp5_fixed = (val8 &
-			SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_MASK) >>
-					SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_SHIFT;
-	info->calp_multiplied_by_2 = 4 * cal_x2 + 2 * cal_x1 + 2 * cal_x1_fixed + cal_xp5_fixed;
-
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_CM_TOP_AFE_TXTC_CTRL0_ADDR,
-			&val8);
-	cal_x1 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_MASK) >>
-			SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_SHIFT;
-	cal_x1_fixed = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_MASK) >>
-			SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_SHIFT;
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_CM_TOP_AFE_TXTC_CTRL1_ADDR,
-			&val8);
-	cal_x2 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_MASK) >>
-			SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_SHIFT;
-	cal_xp5_fixed = (val8 &
-			SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_MASK) >>
-					SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_SHIFT;
-	info->caln_multiplied_by_2 = 4 * cal_x2 + 2 * cal_x1 + 2 * cal_x1_fixed + cal_xp5_fixed;
-}
-
-#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_ABS_MASK			0x1F
-#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK				0x3F
-#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_SIGN_SHIFT		5
-#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK			0xFC0
-#define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT		6
-#define AL_SERDES_25G_RX_DIAG_LEQ_EQ_COUNT					5
-#define AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_EQ_ADDR			0
-#define AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_GAINSTAGE_ADDR		0x5
-#define AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_EVEN_ADDR		0x6
-#define AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_ODD_ADDR		0x7
-#define AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_EVEN_ADDR		0x8
-#define AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_ODD_ADDR			0x9
-#define AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_ADDR		0xF
-#define AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_MASK		0xFFF
-#define AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_EVEN_ADDR	0x11
-#define AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_ODD_ADDR		0x12
-#define AL_SERDES_25G_RX_DIAG_TBUS_EDGE_SLICER_ADDR			0x13
-#define AL_SERDES_25G_RX_DIAG_TBUS_EYE_SLICER_ADDR			0x23
-#define AL_SERDES_25G_RX_DIAG_TBUS_CDR_CLK_Q_ADDR			0x2
-#define AL_SERDES_25G_RX_DIAG_TBUS_CDR_CLK_I_ADDR			0x1
-#define AL_SERDES_25G_RX_DIAG_CDR_RXCLK_DLPF_L_ADDR			0x26
-#define AL_SERDES_25G_RX_DIAG_CDR_RXCLK_DLPF_H_ADDR			0x27
-
-static inline void al_serdes_25g_rx_diag_5bit_signed_set(uint8_t packed_val, int8_t *ptr)
-{
-	uint8_t abs, sign;
-
-	abs = packed_val & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_ABS_MASK;
-	sign = (packed_val & AL_BIT(AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_SIGN_SHIFT)) >>
-			AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_SIGN_SHIFT;
-	if (sign)
-		*ptr = abs;
-	else
-		*ptr = 0 - abs;
-}
-
-static void al_serdes_25g_rx_diag_info_get(
-		struct al_serdes_grp_obj	*obj,
-		enum al_serdes_lane		lane,
-		void *rx_info)
-{
-	struct al_serdes_25g_rx_diag_info *info = rx_info;
-	uint16_t val16;
-	uint8_t val8, val8_2;
-	int rc;
-	int i;
-
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_ADDR,
-			&val8);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->los_offset);
-
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_ADDR,
-			&val8);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->agc_offset);
-
-	rc = al_serdes_25g_gcfsm2_read(
-			obj,
-			lane,
-			AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_GAINSTAGE_ADDR,
-			&val16);
-	if (rc) {
-		al_err("%s: al_serdes_25g_gcfsm2_read failed to read leq_gainstage, rc %d\n",
-				__func__, rc);
-		return;
-	}
-	val8 = (uint8_t)val16;
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_gainstage_offset);
-
-	for (i = 0; i < AL_SERDES_25G_RX_DIAG_LEQ_EQ_COUNT; i++) {
-		rc = al_serdes_25g_gcfsm2_read(
-				obj,
-				lane,
-				AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_EQ_ADDR + i,
-				&val16);
-		if (rc) {
-			al_err("%s: al_serdes_25g_gcfsm2_read failed to read leq_eq %d, rc %d\n",
-					__func__, i, rc);
-			return;
-		}
-		val8 = (uint8_t)val16;
-
-		switch (i) {
-		case 0:
-			al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq1_offset);
-			break;
-		case 1:
-			al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq2_offset);
-			break;
-		case 2:
-			al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq3_offset);
-			break;
-		case 3:
-			al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq4_offset);
-			break;
-		case 4:
-			al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq5_offset);
-			break;
-		default:
-			break;
-		}
-	}
-
-	rc = al_serdes_25g_gcfsm2_read(
-			obj,
-			lane,
-			AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_EVEN_ADDR,
-			&val16);
-	if (rc) {
-		al_err("%s: al_serdes_25g_gcfsm2_read failed to read summer_even_offset, rc %d\n",
-				__func__, rc);
-		return;
-	}
-	val8 = (uint8_t)val16;
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->summer_even_offset);
-
-	rc = al_serdes_25g_gcfsm2_read(
-			obj,
-			lane,
-			AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_ODD_ADDR,
-			&val16);
-	if (rc) {
-		al_err("%s: al_serdes_25g_gcfsm2_read failed to read summer_odd_offset, rc %d\n",
-				__func__, rc);
-		return;
-	}
-	val8 = (uint8_t)val16;
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->summer_odd_offset);
-
-	rc = al_serdes_25g_gcfsm2_read(
-			obj,
-			lane,
-			AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_EVEN_ADDR,
-			&val16);
-	if (rc) {
-		al_err("%s: al_serdes_25g_gcfsm2_read failed to read vscan_even_offset, rc %d\n",
-				__func__, rc);
-		return;
-	}
-	val8 = (uint8_t)val16;
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->vscan_even_offset);
-
-	rc = al_serdes_25g_gcfsm2_read(
-			obj,
-			lane,
-			AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_ODD_ADDR,
-			&val16);
-	if (rc) {
-		al_err("%s: al_serdes_25g_gcfsm2_read failed to read vscan_odd_offset, rc %d\n",
-				__func__, rc);
-		return;
-	}
-	val8 = (uint8_t)val16;
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->vscan_odd_offset);
-
-	al_serdes_25g_tbus_read(
-			obj,
-			lane,
-			AL_SERDES_25G_TBUS_OBJ_LANE,
-			AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_EVEN_ADDR,
-			&val16);
-	val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_even0_offset);
-	val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
-			AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_even1_offset);
-
-	al_serdes_25g_tbus_read(
-			obj,
-			lane,
-			AL_SERDES_25G_TBUS_OBJ_LANE,
-			AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_ODD_ADDR,
-			&val16);
-	val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_odd0_offset);
-	val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
-			AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_odd1_offset);
-
-	al_serdes_25g_tbus_read(
-			obj,
-			lane,
-			AL_SERDES_25G_TBUS_OBJ_LANE,
-			AL_SERDES_25G_RX_DIAG_TBUS_EDGE_SLICER_ADDR,
-			&val16);
-	val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->edge_slicer_even_offset);
-	val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
-			AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->edge_slicer_odd_offset);
-
-	al_serdes_25g_tbus_read(
-			obj,
-			lane,
-			AL_SERDES_25G_TBUS_OBJ_LANE,
-			AL_SERDES_25G_RX_DIAG_TBUS_EYE_SLICER_ADDR,
-			&val16);
-	val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->eye_slicer_even_offset);
-	val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
-			AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
-	al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->eye_slicer_odd_offset);
-
-	al_serdes_25g_reg_masked_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_ADDR,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_MASK,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_SHIFT,
-			&info->cdr_clk_q);
-
-	al_serdes_25g_reg_masked_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_ADDR,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_MASK,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_SHIFT,
-			&info->cdr_clk_i);
-
-	al_serdes_25g_reg_masked_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_ADDR,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_MASK,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_SHIFT,
-			&info->cdr_dll);
-
-	al_serdes_25g_reg_masked_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_ADDR,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_MASK,
-			SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_SHIFT,
-			&info->cdr_vco_dosc);
-
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_ADDR,
-			&val8_2);
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_ADDR,
-			&val8);
-	val8_2 &= SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_MASK;
-	info->cdr_dlpf = (uint16_t)val8_2 << 8 | val8;
-
-	rc = al_serdes_25g_gcfsm2_read(
-			obj,
-			lane,
-			AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_ADDR,
-			&val16);
-	if (rc) {
-		al_err("%s: al_serdes_25g_gcfsm2_read failed to read cdr_vco_fr, rc %d\n",
-				__func__, rc);
-		return;
-	}
-	info->cdr_vco_fr = val16 & AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_MASK;
-
-	al_serdes_25g_reg_masked_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_ADDR,
-			SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_MASK,
-			SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_SHIFT,
-			&info->ple_resistance);
-
-	al_serdes_25g_reg_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			0,
-			SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR,
-			&val8);
-
-	info->rx_term_mode = (val8 & SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK) >>
-			SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT;
-
-	info->rx_coupling = (val8 & SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK) >>
-			SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT;
-
-	al_serdes_25g_reg_masked_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR,
-			SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK,
-			SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT,
-			&info->rx_term_cal_code);
-
-	al_serdes_25g_reg_masked_read(
-			obj,
-			(enum al_serdes_reg_page)lane,
-			SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_ADDR,
-			SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_MASK,
-			SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_SHIFT,
-			&info->rx_sheet_res_cal_code);
-}
-
-/******************************************************************************/
-/******************************************************************************/
-int al_serdes_25g_handle_init(
-	void __iomem			*serdes_regs_base,
-	struct al_serdes_grp_obj	*obj)
-{
-	al_dbg(
-		"%s(%p, %p)\n",
-		__func__,
-		serdes_regs_base,
-		obj);
-
-	al_memset(obj, 0, sizeof(struct al_serdes_grp_obj));
-
-	obj->regs_base = (struct al_serdes_regs *)serdes_regs_base;
-	obj->type_get = al_serdes_25g_type_get;
-	obj->reg_read = al_serdes_25g_reg_read;
-	obj->reg_write = al_serdes_25g_reg_write;
-	obj->bist_overrides_enable = NULL;
-	obj->bist_overrides_disable = NULL;
-	obj->rx_rate_change = NULL;
-	obj->group_pm_set = NULL;
-	obj->lane_pm_set = NULL;
-	obj->pma_hard_reset_group = NULL;
-	obj->pma_hard_reset_lane = NULL;
-	obj->loopback_control = NULL;
-	obj->bist_pattern_select = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_pattern_select);
-	obj->bist_tx_enable = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_tx_enable);
-	obj->bist_tx_err_inject = NULL;
-	obj->bist_rx_enable = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_rx_enable);
-	obj->bist_rx_status = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_rx_status);
-	obj->tx_deemph_preset = NULL;
-	obj->tx_deemph_inc = NULL;
-	obj->tx_deemph_dec = NULL;
-	obj->eye_measure_run = NULL;
-	obj->eye_diag_sample = NULL;
-	obj->eye_diag_run = AL_SRDS_ADV_SRVC(al_serdes_25g_eye_diag_run);
-	obj->cdr_is_locked = AL_SRDS_ADV_SRVC(al_serdes_25g_cdr_is_locked);
-	obj->rx_valid = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_valid);
-	obj->signal_is_detected = AL_SRDS_ADV_SRVC(al_serdes_25g_signal_is_detected);
-	obj->tx_advanced_params_set = AL_SRDS_ADV_SRVC(al_serdes_25g_tx_advanced_params_set);
-	obj->tx_advanced_params_get = AL_SRDS_ADV_SRVC(al_serdes_25g_tx_advanced_params_get);
-	obj->rx_advanced_params_set = NULL;
-	obj->rx_advanced_params_get = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_advanced_params_get);
-	obj->tx_diag_info_get = AL_SRDS_ADV_SRVC(al_serdes_25g_tx_diag_info_get);
-	obj->rx_diag_info_get = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_diag_info_get);
-	obj->mode_set_sgmii = NULL;
-	obj->mode_set_kr = NULL;
-	obj->rx_equalization = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_equalization);
-	obj->calc_eye_size = AL_SRDS_ADV_SRVC(al_serdes_25g_calc_eye_size);
-	obj->sris_config = NULL;
-
-	return 0;
-}
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_25g.h b/sys/contrib/alpine-hal/eth/al_hal_serdes_25g.h
deleted file mode 100644
index 8865b7da94ff..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_25g.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_serdes_api API
- * SerDes HAL driver API
- * @ingroup group_serdes SerDes
- * @{
- *
- * @file   al_hal_serdes_25g.h
- *
- * @brief Header file for the SerDes HAL driver
- *
- */
-
-#ifndef __AL_HAL_SERDES_25G_H__
-#define __AL_HAL_SERDES_25G_H__
-
-#include "al_hal_common.h"
-#include "al_hal_serdes_interface.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-int al_serdes_25g_handle_init(
-	void __iomem			*serdes_regs_base,
-	struct al_serdes_grp_obj	*obj);
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-
-/* *INDENT-ON* */
-#endif		/* __AL_SRDS__ */
-
-/** @} end of SERDES group */
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_25g_internal_regs.h b/sys/contrib/alpine-hal/eth/al_hal_serdes_25g_internal_regs.h
deleted file mode 100644
index ff48f98a940f..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_25g_internal_regs.h
+++ /dev/null
@@ -1,4205 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-#ifndef _AL_SERDES_25G_INTERNAL_REGS_H_
-#define  _AL_SERDES_25G_INTERNAL_REGS_H_
-
-#ifdef _cplusplus
-extern "C" {
-#endif
-
-/*******************************************************************************
- * TOP Registers
- ******************************************************************************/
-#define SERDES_25G_TOP_BASE						0x00
-#define SERDES_25G_TOP_SIZE						0x200
-
-#define SERDES_25G_TOP_PHY_STAT0_ADDR					0x00
-#define SERDES_25G_TOP_PHY_CTRL0_ADDR					0x08
-#define SERDES_25G_TOP_PHY_CFG0_ADDR					0x09
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ADDR				0x30
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ADDR				0x31
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_ADDR				0x32
-#define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_ADDR				0x33
-#define SERDES_25G_TOP_AFE_ATEST_CTRL0_ADDR				0x38
-#define SERDES_25G_TOP_AFE_ATEST_CTRL1_ADDR				0x39
-#define SERDES_25G_TOP_RESET_CTRL_CM0_ADDR				0x50
-#define SERDES_25G_TOP_RESET_CTRL_LN0_ADDR				0x54
-#define SERDES_25G_TOP_RESET_CTRL_LN1_ADDR				0x55
-#define SERDES_25G_TOP_RESET_CTRL_LN2_ADDR				0x56
-#define SERDES_25G_TOP_RESET_CTRL_LN3_ADDR				0x57
-#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_ADDR			0x100
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_ADDR				0x101
-#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_ADDR				0x102
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_ADDR			0x103
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_ADDR				0x104
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_ADDR			0x105
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_ADDR				0x106
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_ADDR			0x107
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_ADDR			0x108
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_ADDR			0x109
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_ADDR			0x10A
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_ADDR				0x110
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_ADDR			0x111
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR				0x112
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_ADDR		0x113
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_ADDR				0x118
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_ADDR			0x119
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR				0x11A
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RXDIV_CORE_ADDR		0x11B
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_ADDR				0x120
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_ADDR			0x121
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_ADDR				0x122
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RXDIV_CORE_ADDR		0x123
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_ADDR				0x128
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_ADDR			0x129
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_ADDR				0x12A
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RXDIV_CORE_ADDR		0x12B
-#define SERDES_25G_TOP_LOS_INT_EN_CTRL_ADDR				0x130
-#define SERDES_25G_TOP_INT0_STATUS_ADDR					0x131
-#define SERDES_25G_TOP_REGBUS_TIMER_ADDR				0x170
-#define SERDES_25G_TOP_ERR_CTRL0_ADDR					0x180
-#define SERDES_25G_TOP_ERR_CTRL1_ADDR					0x181
-#define SERDES_25G_TOP_ERR_CTRL2_ADDR					0x182
-#define SERDES_25G_TOP_ERR_STATUS0_ADDR					0x185
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_ADDR			0x187
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ADDR			0x188
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_ADDR			0x189
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_ADDR			0x18A
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_ADDR			0x18B
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_ADDR			0x18C
-#define SERDES_25G_TOP_TBUS_ADDR_7_0_ADDR				0x1A0
-#define SERDES_25G_TOP_TBUS_ADDR_15_8_ADDR				0x1A1
-#define SERDES_25G_TOP_TBUS_CTRL0_ADDR					0x1A2
-#define SERDES_25G_TOP_TBUS_CTRL1_ADDR					0x1A3
-#define SERDES_25G_TOP_TBUS_DATA_7_0_ADDR				0x1B0
-#define SERDES_25G_TOP_TBUS_DATA_11_8_ADDR				0x1B1
-#define SERDES_25G_TOP_SIM_CTRL_ADDR					0x1C0
-
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_TOP_PHY_STAT0_PHY_CTRL_CFG_MASK			0x0F
-#define SERDES_25G_TOP_PHY_STAT0_PHY_CTRL_CFG_SHIFT			0
-
-#define SERDES_25G_TOP_PHY_CTRL0_PHY_CTRL_CFG_OVR_VAL_MASK		0x0F
-#define SERDES_25G_TOP_PHY_CTRL0_PHY_CTRL_CFG_OVR_VAL_SHIFT		0
-
-#define SERDES_25G_TOP_PHY_CTRL0_OVR_EN_MASK				0x80
-#define SERDES_25G_TOP_PHY_CTRL0_OVR_EN_SHIFT				7
-
-#define SERDES_25G_TOP_PHY_CFG0_CPU_CLK_FREQ_MASK			0xFF
-#define SERDES_25G_TOP_PHY_CFG0_CPU_CLK_FREQ_SHIFT			0
-
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ACAL_EN_MASK			0x0F
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ACAL_EN_SHIFT			0
-
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ACAL_SEL_MASK			0x1F
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ACAL_SEL_SHIFT			0
-
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_EN_MASK		0x01
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_EN_SHIFT		0
-
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_MUTE_MASK		0x02
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_MUTE_SHIFT		1
-
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SEL_MASK		0x04
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SEL_SHIFT		2
-
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SPARE_MASK		0xF0
-#define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SPARE_SHIFT		4
-
-#define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_CALCOMP_OUT_MASK		0x01
-#define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_CALCOMP_OUT_SHIFT		0
-
-#define SERDES_25G_TOP_AFE_ATEST_CTRL0_ATEST_EN_MASK			0x0F
-#define SERDES_25G_TOP_AFE_ATEST_CTRL0_ATEST_EN_SHIFT			0
-
-#define SERDES_25G_TOP_AFE_ATEST_CTRL1_ATEST_SEL_MASK			0x3F
-#define SERDES_25G_TOP_AFE_ATEST_CTRL1_ATEST_SEL_SHIFT			0
-
-#define SERDES_25G_TOP_RESET_CTRL_CM0_CORE_SW_RESET_MASK		0x01
-#define SERDES_25G_TOP_RESET_CTRL_CM0_CORE_SW_RESET_SHIFT		0
-
-#define SERDES_25G_TOP_RESET_CTRL_CM0_REG_SW_RESET_MASK			0x02
-#define SERDES_25G_TOP_RESET_CTRL_CM0_REG_SW_RESET_SHIFT		1
-
-#define SERDES_25G_TOP_RESET_CTRL_CM0_SUBCORE_SW_RESET_MASK		0x04
-#define SERDES_25G_TOP_RESET_CTRL_CM0_SUBCORE_SW_RESET_SHIFT		2
-
-#define SERDES_25G_TOP_RESET_CTRL_CM0_CAL_SW_RESET_MASK			0x40
-#define SERDES_25G_TOP_RESET_CTRL_CM0_CAL_SW_RESET_SHIFT		6
-
-#define SERDES_25G_TOP_RESET_CTRL_LN0_CORE_SW_RESET_MASK		0x01
-#define SERDES_25G_TOP_RESET_CTRL_LN0_CORE_SW_RESET_SHIFT		0
-
-#define SERDES_25G_TOP_RESET_CTRL_LN0_REG_SW_RESET_MASK			0x02
-#define SERDES_25G_TOP_RESET_CTRL_LN0_REG_SW_RESET_SHIFT		1
-
-#define SERDES_25G_TOP_RESET_CTRL_LN0_SUBCORE_SW_RESET_MASK		0x04
-#define SERDES_25G_TOP_RESET_CTRL_LN0_SUBCORE_SW_RESET_SHIFT		2
-
-#define SERDES_25G_TOP_RESET_CTRL_LN0_TXDP_SW_RESET_MASK		0x08
-#define SERDES_25G_TOP_RESET_CTRL_LN0_TXDP_SW_RESET_SHIFT		3
-
-#define SERDES_25G_TOP_RESET_CTRL_LN0_RXDP_SW_RESET_MASK		0x10
-#define SERDES_25G_TOP_RESET_CTRL_LN0_RXDP_SW_RESET_SHIFT		4
-
-#define SERDES_25G_TOP_RESET_CTRL_LN0_LOS_SW_RESET_MASK			0x20
-#define SERDES_25G_TOP_RESET_CTRL_LN0_LOS_SW_RESET_SHIFT		5
-
-#define SERDES_25G_TOP_RESET_CTRL_LN0_CAL_SW_RESET_MASK			0x40
-#define SERDES_25G_TOP_RESET_CTRL_LN0_CAL_SW_RESET_SHIFT		6
-
-#define SERDES_25G_TOP_RESET_CTRL_LN1_CORE_SW_RESET_MASK		0x01
-#define SERDES_25G_TOP_RESET_CTRL_LN1_CORE_SW_RESET_SHIFT		0
-
-#define SERDES_25G_TOP_RESET_CTRL_LN1_REG_SW_RESET_MASK			0x02
-#define SERDES_25G_TOP_RESET_CTRL_LN1_REG_SW_RESET_SHIFT		1
-
-#define SERDES_25G_TOP_RESET_CTRL_LN1_SUBCORE_SW_RESET_MASK		0x04
-#define SERDES_25G_TOP_RESET_CTRL_LN1_SUBCORE_SW_RESET_SHIFT		2
-
-#define SERDES_25G_TOP_RESET_CTRL_LN1_TXDP_SW_RESET_MASK		0x08
-#define SERDES_25G_TOP_RESET_CTRL_LN1_TXDP_SW_RESET_SHIFT		3
-
-#define SERDES_25G_TOP_RESET_CTRL_LN1_RXDP_SW_RESET_MASK		0x10
-#define SERDES_25G_TOP_RESET_CTRL_LN1_RXDP_SW_RESET_SHIFT		4
-
-#define SERDES_25G_TOP_RESET_CTRL_LN1_LOS_SW_RESET_MASK			0x20
-#define SERDES_25G_TOP_RESET_CTRL_LN1_LOS_SW_RESET_SHIFT		5
-
-#define SERDES_25G_TOP_RESET_CTRL_LN1_CAL_SW_RESET_MASK			0x40
-#define SERDES_25G_TOP_RESET_CTRL_LN1_CAL_SW_RESET_SHIFT		6
-
-#define SERDES_25G_TOP_RESET_CTRL_LN2_CORE_SW_RESET_MASK		0x01
-#define SERDES_25G_TOP_RESET_CTRL_LN2_CORE_SW_RESET_SHIFT		0
-
-#define SERDES_25G_TOP_RESET_CTRL_LN2_REG_SW_RESET_MASK			0x02
-#define SERDES_25G_TOP_RESET_CTRL_LN2_REG_SW_RESET_SHIFT		1
-
-#define SERDES_25G_TOP_RESET_CTRL_LN2_SUBCORE_SW_RESET_MASK		0x04
-#define SERDES_25G_TOP_RESET_CTRL_LN2_SUBCORE_SW_RESET_SHIFT		2
-
-#define SERDES_25G_TOP_RESET_CTRL_LN2_TXDP_SW_RESET_MASK		0x08
-#define SERDES_25G_TOP_RESET_CTRL_LN2_TXDP_SW_RESET_SHIFT		3
-
-#define SERDES_25G_TOP_RESET_CTRL_LN2_RXDP_SW_RESET_MASK		0x10
-#define SERDES_25G_TOP_RESET_CTRL_LN2_RXDP_SW_RESET_SHIFT		4
-
-#define SERDES_25G_TOP_RESET_CTRL_LN2_LOS_SW_RESET_MASK			0x20
-#define SERDES_25G_TOP_RESET_CTRL_LN2_LOS_SW_RESET_SHIFT		5
-
-#define SERDES_25G_TOP_RESET_CTRL_LN2_CAL_SW_RESET_MASK			0x40
-#define SERDES_25G_TOP_RESET_CTRL_LN2_CAL_SW_RESET_SHIFT		6
-
-#define SERDES_25G_TOP_RESET_CTRL_LN3_CORE_SW_RESET_MASK		0x01
-#define SERDES_25G_TOP_RESET_CTRL_LN3_CORE_SW_RESET_SHIFT		0
-
-#define SERDES_25G_TOP_RESET_CTRL_LN3_REG_SW_RESET_MASK			0x02
-#define SERDES_25G_TOP_RESET_CTRL_LN3_REG_SW_RESET_SHIFT		1
-
-#define SERDES_25G_TOP_RESET_CTRL_LN3_SUBCORE_SW_RESET_MASK		0x04
-#define SERDES_25G_TOP_RESET_CTRL_LN3_SUBCORE_SW_RESET_SHIFT		2
-
-#define SERDES_25G_TOP_RESET_CTRL_LN3_TXDP_SW_RESET_MASK		0x08
-#define SERDES_25G_TOP_RESET_CTRL_LN3_TXDP_SW_RESET_SHIFT		3
-
-#define SERDES_25G_TOP_RESET_CTRL_LN3_RXDP_SW_RESET_MASK		0x10
-#define SERDES_25G_TOP_RESET_CTRL_LN3_RXDP_SW_RESET_SHIFT		4
-
-#define SERDES_25G_TOP_RESET_CTRL_LN3_LOS_SW_RESET_MASK			0x20
-#define SERDES_25G_TOP_RESET_CTRL_LN3_LOS_SW_RESET_SHIFT		5
-
-#define SERDES_25G_TOP_RESET_CTRL_LN3_CAL_SW_RESET_MASK			0x40
-#define SERDES_25G_TOP_RESET_CTRL_LN3_CAL_SW_RESET_SHIFT		6
-
-#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_SRC_SEL_MASK		0x01
-#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_DEFAULT_CLK_EN_MASK	0x02
-#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_DEFAULT_CLK_EN_SHIFT	1
-
-#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_REF_CLK_EN_MASK	0x04
-#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_REF_CLK_EN_SHIFT	2
-
-#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_DIV_SEL_MASK		0x01
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_DIV_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_CG_EN_MASK			0x01
-#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_CG_EN_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_DIV_SEL_MASK		0x07
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_DIV_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_DIV_SEL_MASK		0x07
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_DIV_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_DIV_SEL_MASK	0x01
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_DIV_SEL_SHIFT	0
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_CG_EN_MASK		0x02
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_CG_EN_SHIFT		1
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_TBUS_OUT_CG_EN_SHIFT 7
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_SRC_SEL_MASK		0x01
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_DEFAULT_CLK_EN_MASK	0x02
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_DEFAULT_CLK_EN_SHIFT	1
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_CMU_CLK_EN_MASK		0x04
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_CMU_CLK_EN_SHIFT		2
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_DIV_SEL_MASK		0xF8
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_DIV_SEL_SHIFT		3
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_SRC_SEL_MASK           0x01
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_SRC_SEL_SHIFT          0
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_DEFAULT_CLK_EN_MASK    0x02
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_DEFAULT_CLK_EN_SHIFT   1
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_CMUDIV_CLK_EN_MASK     0x04
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_CMUDIV_CLK_EN_SHIFT    2
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_DIV_SEL_MASK           0xF8
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_DIV_SEL_SHIFT          3
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_MASK   0x80
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_SHIFT  7
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_FRCDIV_MODE_EN_MASK	0x01
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_FRCDIV_MODE_EN_SHIFT 0
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_SRC_SEL_MASK	0x06
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_SRC_SEL_SHIFT	1
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_DIV_SEL_MASK	0x08
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_DIV_SEL_SHIFT	3
-
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_TBUS_OUT_CG_EN_SHIFT 7
-
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_MASK		0x03
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_DIV_SEL_MASK		0x04
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_DIV_SEL_SHIFT		2
-
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_MASK		0x10
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_SHIFT		4
-
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_SRC_SEL_MASK		0x01
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_DEFAULT_CLK_EN_MASK	0x02
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT	1
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_RX_CLK_EN_MASK		0x04
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_RX_CLK_EN_SHIFT	2
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_SRC_SEL_MASK		0x03
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_MASK			0x10
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_SHIFT		4
-
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_MASK		0x20
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_SHIFT		5
-
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_SRC_SEL_MASK           0x01
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_SRC_SEL_SHIFT          0
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_DEFAULT_CLK_EN_MASK    0x02
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_DEFAULT_CLK_EN_SHIFT   1
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_RX_CLKDIV_EN_MASK      0x04
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_RX_CLKDIV_EN_SHIFT     2
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_TBUS_OUT_CG_EN_MASK    0x80
-#define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_TBUS_OUT_CG_EN_SHIFT   7
-
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_MASK		0x03
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_DIV_SEL_MASK		0x04
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_DIV_SEL_SHIFT		2
-
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_MASK		0x10
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_SHIFT		4
-
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_SRC_SEL_MASK		0x01
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_DEFAULT_CLK_EN_MASK	0x02
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT	1
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_RX_CLK_EN_MASK		0x04
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_RX_CLK_EN_SHIFT	2
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_SRC_SEL_MASK		0x03
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_MASK			0x10
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_SHIFT		4
-
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_MASK		0x20
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_SHIFT		5
-
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_MASK		0x03
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_DIV_SEL_MASK		0x04
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_DIV_SEL_SHIFT		2
-
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_MASK		0x10
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_SHIFT		4
-
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_SRC_SEL_MASK		0x01
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_DEFAULT_CLK_EN_MASK	0x02
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT	1
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_RX_CLK_EN_MASK		0x04
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_RX_CLK_EN_SHIFT	2
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_SRC_SEL_MASK		0x03
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_MASK			0x10
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_SHIFT		4
-
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_MASK		0x20
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_SHIFT		5
-
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_MASK		0x03
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_DIV_SEL_MASK		0x04
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_DIV_SEL_SHIFT		2
-
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_MASK		0x10
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_SHIFT		4
-
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_SRC_SEL_MASK		0x01
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_DEFAULT_CLK_EN_MASK	0x02
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT	1
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_RX_CLK_EN_MASK		0x04
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_RX_CLK_EN_SHIFT	2
-
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_SRC_SEL_MASK		0x03
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_SRC_SEL_SHIFT		0
-
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_MASK			0x10
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_SHIFT		4
-
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_MASK		0x20
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_SHIFT		5
-
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK	0x80
-#define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT	7
-
-#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN0_MASK				0x01
-#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN0_SHIFT			0
-
-#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN1_MASK				0x02
-#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN1_SHIFT			1
-
-#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN2_MASK				0x04
-#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN2_SHIFT			2
-
-#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN3_MASK				0x08
-#define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN3_SHIFT			3
-
-#define SERDES_25G_TOP_REGBUS_TIMER_LOAD_VAL_MASK			0xFF
-#define SERDES_25G_TOP_REGBUS_TIMER_LOAD_VAL_SHIFT			0
-
-#define SERDES_25G_TOP_ERR_CTRL0_ERR_MASK				0x01
-#define SERDES_25G_TOP_ERR_CTRL0_ERR_SHIFT				0
-
-#define SERDES_25G_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK			0xFF
-#define SERDES_25G_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT			0
-
-#define SERDES_25G_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK			0xFF
-#define SERDES_25G_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT			0
-
-#define SERDES_25G_TOP_ERR_STATUS0_REGBUS_ERR_MASK			0x01
-#define SERDES_25G_TOP_ERR_STATUS0_REGBUS_ERR_SHIFT			0
-
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_CLR_MASK			0x01
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_CLR_SHIFT			0
-
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_MASK		0x03
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_SHIFT		0
-
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_MASK		0x04
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_SHIFT	2
-
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_TRANSFER_ADDR_LSB_MASK	0xFF
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_TRANSFER_ADDR_LSB_SHIFT	0
-
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_MASK	0x7F
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_SHIFT	0
-
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_TRANSFER_WD_MASK		0xFF
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_TRANSFER_WD_SHIFT	0
-
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_TRANSFER_WR_BIT_EN_MASK	0xFF
-#define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_TRANSFER_WR_BIT_EN_SHIFT	0
-
-#define SERDES_25G_TOP_TBUS_ADDR_7_0_MASK				0xFF
-#define SERDES_25G_TOP_TBUS_ADDR_7_0_SHIFT				0
-
-#define SERDES_25G_TOP_TBUS_ADDR_15_8_MASK				0xFF
-#define SERDES_25G_TOP_TBUS_ADDR_15_8_SHIFT				0
-
-#define SERDES_25G_TOP_TBUS_CTRL0_CLOCK_GATE0_MASK			0xFF
-#define SERDES_25G_TOP_TBUS_CTRL0_CLOCK_GATE0_SHIFT			0
-
-#define SERDES_25G_TOP_TBUS_CTRL1_CLOCK_GATE1_MASK			0xFF
-#define SERDES_25G_TOP_TBUS_CTRL1_CLOCK_GATE1_SHIFT			0
-
-#define SERDES_25G_TOP_TBUS_DATA_7_0_MASK				0xFF
-#define SERDES_25G_TOP_TBUS_DATA_7_0_SHIFT				0
-
-#define SERDES_25G_TOP_TBUS_DATA_11_8_MASK				0x0F
-#define SERDES_25G_TOP_TBUS_DATA_11_8_SHIFT				0
-
-/*********************************** Mailbox **********************************/
-#define SERDES_25G_TOP_MB_BASE						0x200
-
-#define SERDES_25G_TOP_CMD_ADDR			(SERDES_25G_TOP_MB_BASE +  0x00)
-#define SERDES_25G_TOP_CMD_FLAG_ADDR		(SERDES_25G_TOP_MB_BASE +  0x02)
-#define SERDES_25G_TOP_CMD_DATA0_ADDR		(SERDES_25G_TOP_MB_BASE +  0x03)
-#define SERDES_25G_TOP_CMD_DATA1_ADDR		(SERDES_25G_TOP_MB_BASE +  0x04)
-#define SERDES_25G_TOP_CMD_DATA2_ADDR		(SERDES_25G_TOP_MB_BASE +  0x05)
-#define SERDES_25G_TOP_CMD_DATA3_ADDR		(SERDES_25G_TOP_MB_BASE +  0x06)
-#define SERDES_25G_TOP_CMD_DATA4_ADDR		(SERDES_25G_TOP_MB_BASE +  0x07)
-#define SERDES_25G_TOP_CMD_DATA5_ADDR		(SERDES_25G_TOP_MB_BASE +  0x08)
-#define SERDES_25G_TOP_CMD_DATA6_ADDR		(SERDES_25G_TOP_MB_BASE +  0x09)
-#define SERDES_25G_TOP_CMD_DATA7_ADDR		(SERDES_25G_TOP_MB_BASE +  0x0A)
-#define SERDES_25G_TOP_RSP_ADDR			(SERDES_25G_TOP_MB_BASE +  0x10)
-#define SERDES_25G_TOP_RSP_FLAG_ADDR		(SERDES_25G_TOP_MB_BASE +  0x12)
-#define SERDES_25G_TOP_RSP_DATA0_ADDR		(SERDES_25G_TOP_MB_BASE +  0x13)
-#define SERDES_25G_TOP_RSP_DATA1_ADDR		(SERDES_25G_TOP_MB_BASE +  0x14)
-#define SERDES_25G_TOP_RSP_DATA2_ADDR		(SERDES_25G_TOP_MB_BASE +  0x15)
-#define SERDES_25G_TOP_RSP_DATA3_ADDR		(SERDES_25G_TOP_MB_BASE +  0x16)
-#define SERDES_25G_TOP_RSP_DATA4_ADDR		(SERDES_25G_TOP_MB_BASE +  0x17)
-#define SERDES_25G_TOP_RSP_DATA5_ADDR		(SERDES_25G_TOP_MB_BASE +  0x18)
-#define SERDES_25G_TOP_RSP_DATA6_ADDR		(SERDES_25G_TOP_MB_BASE +  0x19)
-#define SERDES_25G_TOP_RSP_DATA7_ADDR		(SERDES_25G_TOP_MB_BASE +  0x1A)
-#define SERDES_25G_TOP_RSP_DATA8_ADDR		(SERDES_25G_TOP_MB_BASE +  0x1B)
-#define SERDES_25G_TOP_RSP_DATA9_ADDR		(SERDES_25G_TOP_MB_BASE +  0x1C)
-#define SERDES_25G_TOP_RSP_DATA10_ADDR		(SERDES_25G_TOP_MB_BASE +  0x1D)
-#define SERDES_25G_TOP_RSP_DATA11_ADDR		(SERDES_25G_TOP_MB_BASE +  0x1E)
-#define SERDES_25G_TOP_RSP_DATA12_ADDR		(SERDES_25G_TOP_MB_BASE +  0x1F)
-#define SERDES_25G_TOP_RSP_DATA13_ADDR		(SERDES_25G_TOP_MB_BASE +  0x20)
-#define SERDES_25G_TOP_RSP_DATA14_ADDR		(SERDES_25G_TOP_MB_BASE +  0x21)
-#define SERDES_25G_TOP_RSP_DATA15_ADDR		(SERDES_25G_TOP_MB_BASE +  0x22)
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_TOP_CMD_MASK						0xFF
-#define SERDES_25G_TOP_CMD_SHIFT					0
-
-#define SERDES_25G_TOP_CMD_FLAG_MASK					0x01
-#define SERDES_25G_TOP_CMD_FLAG_SHIFT					0
-
-#define SERDES_25G_TOP_CMD_DATA0_MASK					0xFF
-#define SERDES_25G_TOP_CMD_DATA0_SHIFT					0
-
-#define SERDES_25G_TOP_CMD_DATA1_MASK					0xFF
-#define SERDES_25G_TOP_CMD_DATA1_SHIFT					0
-
-#define SERDES_25G_TOP_CMD_DATA2_MASK					0xFF
-#define SERDES_25G_TOP_CMD_DATA2_SHIFT					0
-
-#define SERDES_25G_TOP_CMD_DATA3_MASK					0xFF
-#define SERDES_25G_TOP_CMD_DATA3_SHIFT					0
-
-#define SERDES_25G_TOP_CMD_DATA4_MASK					0xFF
-#define SERDES_25G_TOP_CMD_DATA4_SHIFT					0
-
-#define SERDES_25G_TOP_CMD_DATA5_MASK					0xFF
-#define SERDES_25G_TOP_CMD_DATA5_SHIFT					0
-
-#define SERDES_25G_TOP_CMD_DATA6_MASK					0xFF
-#define SERDES_25G_TOP_CMD_DATA6_SHIFT					0
-
-#define SERDES_25G_TOP_CMD_DATA7_MASK					0xFF
-#define SERDES_25G_TOP_CMD_DATA7_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_MASK						0xFF
-#define SERDES_25G_TOP_RSP_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_FLAG_MASK					0x01
-#define SERDES_25G_TOP_RSP_FLAG_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA0_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA0_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA1_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA1_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA2_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA2_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA3_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA3_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA4_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA4_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA5_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA5_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA6_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA6_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA7_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA7_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA8_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA8_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA9_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA9_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA10_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA10_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA11_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA11_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA12_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA12_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA13_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA13_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA14_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA14_SHIFT					0
-
-#define SERDES_25G_TOP_RSP_DATA15_MASK					0xFF
-#define SERDES_25G_TOP_RSP_DATA15_SHIFT					0
-
-/*******************************************************************************
- * Common Registers
- ******************************************************************************/
-#define SERDES_25G_CM_BASE						0xC00
-#define SERDES_25G_CM_SIZE						0x400
-
-#define SERDES_25G_CM_TOP_AFE_PD_CTRL0_ADDR				0x00
-#define SERDES_25G_CM_TOP_AFE_PD_CTRL1_ADDR				0x01
-#define SERDES_25G_CM_TOP_AFE_RST_CTRL0_ADDR				0x03
-#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL0_ADDR				0x05
-#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL1_ADDR				0x06
-#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL2_ADDR				0x07
-#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL3_ADDR				0x08
-#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL4_ADDR				0x09
-#define SERDES_25G_CM_TOP_AFE_BIAS_CTRL5_ADDR				0x0A
-#define SERDES_25G_CM_TOP_AFE_REG_CTRL0_ADDR				0x0C
-#define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL0_ADDR				0x1A
-#define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL1_ADDR				0x1B
-#define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL2_ADDR				0x1F
-#define SERDES_25G_CM_TOP_AFE_CMCP_CTRL0_ADDR				0x20
-#define SERDES_25G_CM_TOP_AFE_CMCP_CTRL1_ADDR				0x21
-#define SERDES_25G_CM_TOP_AFE_CMCP_CTRL2_ADDR				0x22
-#define SERDES_25G_CM_TOP_AFE_MISC_CTRL0_ADDR				0x23
-#define SERDES_25G_CM_TOP_AFE_CMCP_STATUS_ADDR				0x24
-#define SERDES_25G_CM_TOP_AFE_TOGGLE_CTRL0_ADDR				0x25
-#define SERDES_25G_CM_TOP_AFE_TSTCLK_CTRL0_ADDR				0x28
-#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL0_ADDR				0x30
-#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL1_ADDR				0x31
-#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL2_ADDR				0x32
-#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL3_ADDR				0x33
-#define SERDES_25G_CM_TOP_AFE_TXTC_CTRL4_ADDR				0x34
-#define SERDES_25G_CM_TOP_PWR_STATE_REQ_STATUS_ADDR			0x50
-#define SERDES_25G_CM_TOP_PWR_STATE_ACK_CTRL_ADDR			0x51
-#define SERDES_25G_CM_TOP_PHY_IF_STATUS_ADDR				0x52
-#define SERDES_25G_CM_TOP_CMU_TOP_SPARE0_ADDR				0x58
-#define SERDES_25G_CM_TOP_CMU_TOP_SPARE1_ADDR				0x59
-#define SERDES_25G_CM_TOP_ERR_CTRL1_ADDR				0x80
-#define SERDES_25G_CM_TOP_ERR_CTRL2_ADDR				0x81
-#define SERDES_25G_CM_TOP_ERR_CTRL3_ADDR				0x82
-#define SERDES_25G_CM_TOP_CMU_IF_OVR_CTRL0_ADDR				0x8A
-#define SERDES_25G_CM_TOP_CMU_IF_OVR_CTRL1_ADDR				0x8B
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_MASK			 0x01
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SHIFT			 0
-
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICV_MASK		 0x02
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICV_SHIFT		 1
-
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICC_MASK		 0x04
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICC_SHIFT		 2
-
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_IPTAT_MASK		 0x08
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_IPTAT_SHIFT		 3
-
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SLAVE_MASK		 0x10
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SLAVE_SHIFT		 4
-
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REG_REF_MASK			 0x20
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REG_REF_SHIFT		 5
-
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REFCLK_MASK			 0x40
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REFCLK_SHIFT			 6
-
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_MASK			 0x01
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_SHIFT			 0
-
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_LEFT_MASK		 0x02
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_LEFT_SHIFT	 1
-
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_RIGHT_MASK	 0x04
-#define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_RIGHT_SHIFT	 2
-
-#define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMU_N_MASK	 0x01
-#define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMU_N_SHIFT	 0
-
-#define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMUDIV_N_MASK	 0x02
-#define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMUDIV_N_SHIFT	 1
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICV_TRIM_MASK		 0x0F
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICV_TRIM_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICC_TRIM_MASK		 0xF0
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICC_TRIM_SHIFT		 4
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL1_BIAS_IPTAT_TRIM_MASK		 0x0F
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL1_BIAS_IPTAT_TRIM_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_BGSTART_BYP_MASK		 0x01
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_BGSTART_BYP_SHIFT	 0
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_IPTATSTART_BYP_MASK	 0x02
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_IPTATSTART_BYP_SHIFT	 1
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_TERMCAL_EN_MASK		 0x04
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_TERMCAL_EN_SHIFT		 2
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_PTRIM_MASK		 0x0F
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_PTRIM_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_NTRIM_MASK		 0xF0
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_NTRIM_SHIFT		 4
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL4_BIAS_SPARE_MASK		 0x0F
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL4_BIAS_SPARE_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL5_BIAS_CALREF_TRIM_MASK		 0x0F
-#define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL5_BIAS_CALREF_TRIM_SHIFT	 0
-
-#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_PASS_EN_MASK		 0x01
-#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_PASS_EN_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRIM_MASK		 0x0E
-#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRIM_SHIFT		 1
-
-#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRICKLE_MASK		 0x30
-#define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRICKLE_SHIFT		 4
-
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DIV_MASK		 0x03
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DIV_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DPL_DIV_MASK		 0x0C
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DPL_DIV_SHIFT	 2
-
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DEGLITCH_OVR_MASK	 0x10
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DEGLITCH_OVR_SHIFT	 4
-
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL1_REFCLK_TERM_MASK		 0x1F
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL1_REFCLK_TERM_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL2_REFCLK_SPARE_MASK		 0x0F
-#define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL2_REFCLK_SPARE_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_QSAMPLE_EN_MASK		 0x01
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_QSAMPLE_EN_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_DCD_RANGE_MASK		 0x02
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_DCD_RANGE_SHIFT		 1
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUCLK_DIV_MASK		 0x1C
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUCLK_DIV_SHIFT		 2
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_MASK	 0xE0
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_SHIFT	 5
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CLKDIV_SWING_MASK	 0x03
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CLKDIV_SWING_SHIFT	 0
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_TXCLK_SWING_MASK		 0x0C
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_TXCLK_SWING_SHIFT	 2
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CMUCLK_DIV2_BYPASS_MASK	 0x10
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CMUCLK_DIV2_BYPASS_SHIFT	 4
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_CLKDIV_OVR_MASK		 0x03
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_CLKDIV_OVR_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_BIASI_MASK		 0x0C
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_BIASI_SHIFT	 2
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_DIV_MASK		 0x70
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_DIV_SHIFT		 4
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_DIV1P5_DUMMY_EN_MASK	 0x80
-#define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_DIV1P5_DUMMY_EN_SHIFT	 7
-
-#define SERDES_25G_CMU_TOP_AFE_MISC_CTRL0_CMCP_SPARE_MASK		 0xFF
-#define SERDES_25G_CMU_TOP_AFE_MISC_CTRL0_CMCP_SPARE_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_CMCP_STATUS_CMCP_DIV1P5_QSAMPLE_MASK	 0x0F
-#define SERDES_25G_CMU_TOP_AFE_CMCP_STATUS_CMCP_DIV1P5_QSAMPLE_SHIFT	 0
-
-#define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CLK_TOGGLE_EN_MASK		 0x01
-#define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CLK_TOGGLE_EN_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CMCP_TOGGLE_EN_MASK		 0x02
-#define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CMCP_TOGGLE_EN_SHIFT	 1
-
-#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_MASK	 0x03
-#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_SHIFT	 0
-
-#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_MASK	 0x1C
-#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_SHIFT	 2
-
-#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_SWING_MASK	 0x60
-#define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_SWING_SHIFT	 5
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_MASK		 0x07
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_MASK	 0x18
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_SHIFT	 3
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_MASK		 0x1F
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_MASK	 0x60
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_SHIFT	 5
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_MASK		 0x07
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_MASK	 0x18
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_SHIFT	 3
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_MASK		 0x1F
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_MASK	 0x60
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_SHIFT	 5
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_NEG_MASK		 0x07
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_NEG_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_POS_MASK		 0x70
-#define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_POS_SHIFT		 4
-
-#define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_STATE_MASK		 0x07
-#define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_REQ_MASK		 0x08
-#define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT		 3
-
-#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_STATE_MASK		 0x07
-#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_ACK_MASK			 0x08
-#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT			 3
-
-#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK		 0x70
-#define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT		 4
-
-#define SERDES_25G_CMU_TOP_PHY_IF_STATUS_CMU_OK_MASK			 0x01
-#define SERDES_25G_CMU_TOP_PHY_IF_STATUS_CMU_OK_SHIFT			 0
-
-#define SERDES_25G_CMU_TOP_CMU_TOP_SPARE0_MASK				 0xFF
-#define SERDES_25G_CMU_TOP_CMU_TOP_SPARE0_SHIFT				 0
-
-#define SERDES_25G_CMU_TOP_CMU_TOP_SPARE1_MASK				 0xFF
-#define SERDES_25G_CMU_TOP_CMU_TOP_SPARE1_SHIFT				 0
-
-#define SERDES_25G_CMU_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK			 0xFF
-#define SERDES_25G_CMU_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT			 0
-
-#define SERDES_25G_CMU_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK			 0xFF
-#define SERDES_25G_CMU_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_ERR_CTRL3_CMU_ERR__MASK			 0x01
-#define SERDES_25G_CMU_TOP_ERR_CTRL3_CMU_ERR__SHIFT			 0
-
-#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_EN_MASK		 0x01
-#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_EN_SHIFT		 0
-
-#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_VAL_MASK		 0x06
-#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_VAL_SHIFT	 1
-
-#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_EN_MASK	 0x01
-#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_EN_SHIFT	 0
-
-#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_VAL_MASK	 0x02
-#define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_VAL_SHIFT	 1
-
-
-/*******************************************************************************
- * Lane Registers
- ******************************************************************************/
-#define SERDES_25G_LANE_BASE						0x1800
-#define SERDES_25G_LANE_SIZE						0x800
-
-/********************************** LANE_TOP **********************************/
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_ADDR			 0x00
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_ADDR				 0x01
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_ADDR				 0x02
-#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_ADDR			 0x03
-#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_ADDR			 0x04
-#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_ADDR			 0x05
-#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_ADDR				 0x06
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR				 0x10
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_ADDR				 0x12
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_ADDR				 0x13
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_ADDR				 0x14
-#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_ADDR				 0x16
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_ADDR				 0x19
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR			 0x1B
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR			 0x1C
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR				 0x22
-#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_ADDR				 0x24
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_ADDR			 0x25
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ADDR			 0x26
-#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_ADDR				 0x27
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_ADDR				 0x30
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_ADDR				 0x31
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR				 0x38
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_ADDR			 0x39
-#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_ADDR			 0x3A
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_ADDR				 0x3B
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_ADDR				 0x3C
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_ADDR			 0x3D
-#define SERDES_25G_LANE_TOP_ERR_CTRL1_ADDR				 0x40
-#define SERDES_25G_LANE_TOP_ERR_CTRL2_ADDR				 0x41
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_MASK     0x01
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT    0
-
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_MASK     0x02
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT    1
-
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_MASK       0x04
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT      2
-
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_MASK       0x08
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT      3
-
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_MASK                0x01
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_SHIFT               0
-
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_MASK                  0x02
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_SHIFT                 1
-
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_MASK              0x01
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_SHIFT             0
-
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_MASK                  0x02
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_SHIFT                 1
-
-#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_MASK           0x01
-#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_SHIFT          0
-
-#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_MASK              0x01
-#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_SHIFT             0
-
-#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_MASK              0x04
-#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_SHIFT             2
-
-#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_MASK                0x0F
-#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_SHIFT               0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK            0x0F
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_SHIFT           0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_MASK         0x30
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_SHIFT        4
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_MASK         0x40
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_SHIFT        6
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_MASK           0x01
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_SHIFT          0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_MASK              0x06
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_SHIFT             1
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_MASK               0x0F
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_SHIFT              0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_MASK        0x03
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_SHIFT       0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_MASK           0x04
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_SHIFT          2
-
-#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_MASK               0xF0
-#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_SHIFT              4
-
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_MASK              0x07
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_SHIFT             0
-
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_MASK               0xF0
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_SHIFT              4
-
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_MASK          0x07
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_SHIFT         0
-
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK             0x08
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT            3
-
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK         0x10
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT        4
-
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK             0x1F
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT            0
-
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK             0x03
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT            0
-
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_MASK               0x04
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT              2
-
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_MASK    0x10
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT   4
-
-#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_MASK              0x01
-#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT             0
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_MASK              0x07
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT             0
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_MASK                0x08
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT               3
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_MASK                0x07
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT               0
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_MASK                  0x08
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT                 3
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK            0x70
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT           4
-
-#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_MASK                     0x01
-#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_SHIFT                    0
-
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_MASK              0x07
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_SHIFT             0
-
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_MASK               0x38
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_SHIFT              3
-
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_MASK              0x07
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_SHIFT             0
-
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_MASK                0x38
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_SHIFT               3
-
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK                   0x01
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT                  0
-
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_MASK                 0x01
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_SHIFT                0
-
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_MASK           0x02
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_SHIFT          1
-
-#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_MASK            0x01
-#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_SHIFT           0
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_MASK                     0x01
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT                    0
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_MASK              0x02
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT             1
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_MASK              0x04
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT             2
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_MASK                 0x08
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_SHIFT                3
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_MASK                      0x10
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_SHIFT                     4
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_MASK                 0x20
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_SHIFT                5
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_MASK              0x40
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_SHIFT             6
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_MASK                     0x01
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_SHIFT                    0
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_MASK                         0x06
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_SHIFT                        1
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_MASK                      0x08
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_SHIFT                     3
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_MASK           0x01
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_SHIFT          0
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_MASK           0x02
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_SHIFT          1
-
-#define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK                  0xFF
-#define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT                 0
-
-#define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK                 0xFF
-#define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT                0
-
-/*********************************  Lane CDR RXCLK ***************************/
-#define SERDES_25G_LANE_CDR_RXCLK_BASE					0x80
-
-#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x10)
-#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x11)
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x21)
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x22)
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x26)
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x27)
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x28)
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x29)
-#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2A)
-#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2B)
-#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2D)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x30)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x31)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x32)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x34)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x36)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x37)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x39)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3A)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3B)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3C)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3D)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3E)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3F)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x40)
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x41)
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x44)
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x45)
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x46)
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x48)
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x49)
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4A)
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4B)
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4C)
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4D)
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4E)
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_ADDR		(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4F)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x60)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x61)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x62)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x63)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x68)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x69)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6A)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6B)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6C)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6D)
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_ADDR	(SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6E)
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_DLPF_SRC_SEL_MASK			0x01
-#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_DLPF_SRC_SEL_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_CFG_DOSC_MIN_MASK			0x07
-#define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_CFG_DOSC_MIN_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DECIMATION_MODE_MASK		0x0F
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DECIMATION_MODE_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DLPF_MODE_MASK			0x30
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DLPF_MODE_SHIFT		4
-
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_PD_OUT_MASK_MASK		0x03
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_PD_OUT_MASK_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_DLPF_VAL_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_DLPF_VAL_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_MASK		0x01
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_DLPF_DITHER_VAL_7_0_MASK	0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_DLPF_DITHER_VAL_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_DLPF_DITHER_VAL_10_8_MASK	0x07
-#define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_DLPF_DITHER_VAL_10_8_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_DLPF_VAL_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_DLPF_VAL_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_DLPF_VAL_8_MASK		0x01
-#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_DLPF_VAL_8_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_EN_MASK			0x01
-#define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_EN_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_NUM_DITHER_BITS_MASK		0x0F
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_NUM_DITHER_BITS_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_HIGH_THRESHOLD_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_HIGH_THRESHOLD_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_HIGH_THRESHOLD_8_MASK		0x01
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_HIGH_THRESHOLD_8_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_HIGH_COUNT_MASK			0x0F
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_HIGH_COUNT_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_LOW_THRESHOLD_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_LOW_THRESHOLD_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_LOW_THRESHOLD_8_MASK		0x01
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_LOW_THRESHOLD_8_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_LOW_COUNT_MASK			0x0F
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_LOW_COUNT_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCK_EN_MASK			0x01
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCK_EN_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCKL_EN_MASK			0x02
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCKL_EN_SHIFT			1
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_HIGH_EN_MASK			0x04
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_HIGH_EN_SHIFT			2
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOW_EN_MASK			0x08
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOW_EN_SHIFT			3
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_OUTPUT_SAMPLE_PERIOD_MASK		0x3F
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_OUTPUT_SAMPLE_PERIOD_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_GREY_VAL_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_GREY_VAL_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_GREY_VAL_8_MASK			0x01
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_GREY_VAL_8_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_BINARY_VAL_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_BINARY_VAL_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_MASK		0x01
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_MASK		0x01
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_MASK		0x02
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_SHIFT		1
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_MASK			0x04
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_SHIFT			2
-
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_MASK			0x01
-#define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ACCUMULATOR_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ACCUMULATOR_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ACCUMULATOR_15_8_MASK	0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ACCUMULATOR_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_MASK	0x0F
-#define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_DITHER_BITS_MASK			0x0F
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_DITHER_BITS_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_SAMPLE_PERIOD_MASK		0xF0
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_SAMPLE_PERIOD_SHIFT		4
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_NUM_SAMPLES_MASK			0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_NUM_SAMPLES_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_SLOPE_THRESHOLD_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_SLOPE_THRESHOLD_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_RANGE_THRESHOLD_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_RANGE_THRESHOLD_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_DITHER_BITS_MASK			0x0F
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_DITHER_BITS_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_SAMPLE_PERIOD_MASK		0xF0
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_SAMPLE_PERIOD_SHIFT		4
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_NUM_SAMPLES_MASK			0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_NUM_SAMPLES_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_SLOPE_THRESHOLD_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_SLOPE_THRESHOLD_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_RANGE_THRESHOLD_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_RANGE_THRESHOLD_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_EN_MASK		0x01
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_EN_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_SAMPLE_DROP_BITS_MASK	0x07
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_SAMPLE_DROP_BITS_SHIFT 0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_NUM_PEAKS_MASK	0xF0
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_NUM_PEAKS_SHIFT	4
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_PEAK2PEAK_PERIOD_MIN_MASK	0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_PEAK2PEAK_PERIOD_MIN_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_PEAK2PEAK_PERIOD_MAX_MASK	0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_PEAK2PEAK_PERIOD_MAX_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_DONE_MASK		0x01
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_DONE_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_NOISY_MASK		0x02
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_NOISY_SHIFT		1
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_SLOW_MASK		0x04
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_SLOW_SHIFT		2
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_VAL_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_VAL_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_VAL_15_8_MASK	0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_VAL_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_VAL_19_16_MASK	0x0F
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_VAL_19_16_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_VAL_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_VAL_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_VAL_15_8_MASK		0xFF
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_VAL_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_VAL_19_16_MASK	0x0F
-#define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_VAL_19_16_SHIFT	0
-
-/*********************************  Lane CDR_REFCLK ***************************/
-#define SERDES_25G_LANE_CDR_REFCLK_BASE					0x180
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x00)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x01)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x06)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0A)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0B)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0C)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x10)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x11)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x18)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x19)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x1A)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x1B)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x20)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x21)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_ADDR	(SERDES_25G_LANE_CDR_REFCLK_BASE + 0x22)
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x24)
-#define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x30)
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_MASK				0x01
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_SHIFT				0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_EYE_MASK			0x02
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_EYE_SHIFT			1
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_RXCDR_TOGGLE_EN_MASK			0x04
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_RXCDR_TOGGLE_EN_SHIFT			2
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_RXCDR_PHD_EN_MASK			0xFF
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_RXCDR_PHD_EN_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_PHD_N_MASK			0x01
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_PHD_N_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_CLKDIV_N_MASK		0x02
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_CLKDIV_N_SHIFT		1
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_RXCDR_VCO_KICK_MASK			0x01
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_RXCDR_VCO_KICK_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REGDAC_BANDWIDTH_MASK		0x01
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REGDAC_BANDWIDTH_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_SHORT_VOSC_PRP_MASK		0x02
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_SHORT_VOSC_PRP_SHIFT		1
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REFDAC_GAIN_MASK			0x0C
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REFDAC_GAIN_SHIFT		2
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_MASK			0x07
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_BBSTEP_MASK				0x1F
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_BBSTEP_SHIFT				0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_CLKDIV_MASK				0x60
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_CLKDIV_SHIFT				5
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_CLKDIV_SWING_MASK			0x03
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_CLKDIV_SWING_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_SPARE_MASK				0x3C
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_SPARE_SHIFT				2
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_MASK			0x7F
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_SRC_SEL_MASK				0x80
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_SRC_SEL_SHIFT				7
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_MASK			0x7F
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_SRC_SEL_MASK				0x80
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_SRC_SEL_SHIFT				7
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_MASK			0x7F
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_CAP_MASK			0x07
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_CAP_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_SWING_MASK			0x18
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_SWING_SHIFT			3
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_CAL_EN_MASK			0x01
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_CAL_EN_SHIFT			0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_VCOCAL_DIV4_MASK			0x02
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_VCOCAL_DIV4_SHIFT		1
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_RXCDR_VCOCAL_LOAD_VAL_11_8_MASK	0x0F
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_RXCDR_VCOCAL_LOAD_VAL_11_8_SHIFT	0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_RXCDR_VCOCAL_LOAD_VAL_7_0_MASK		0xFF
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_RXCDR_VCOCAL_LOAD_VAL_7_0_SHIFT	 0
-
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_RXCDR_VCOCAL_UP_MASK		0x01
-#define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_RXCDR_VCOCAL_UP_SHIFT		0
-
-#define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ZERO_PHASE_MASK			0x7F
-#define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ZERO_PHASE_SHIFT			0
-
-/*********************************  Lane BIST *********************************/
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_ADDR			0x00
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_ADDR				0x01
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_ADDR				0x02
-#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_ADDR			0x03
-#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_ADDR			0x04
-#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_ADDR			0x05
-#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_ADDR				0x06
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR				0x10
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_ADDR				0x12
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_ADDR				0x13
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_ADDR				0x14
-#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_ADDR				0x16
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_ADDR				0x19
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR			0x1B
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR			0x1C
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR				0x22
-#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_ADDR				0x24
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_ADDR			0x25
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ADDR			0x26
-#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_ADDR				0x27
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_ADDR				0x30
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_ADDR				0x31
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR				0x38
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_ADDR			0x39
-#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_ADDR			0x3A
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_ADDR				0x3B
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_ADDR				0x3C
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_ADDR			0x3D
-#define SERDES_25G_LANE_TOP_ERR_CTRL1_ADDR				0x40
-#define SERDES_25G_LANE_TOP_ERR_CTRL2_ADDR				0x41
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_MASK	0x01
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT	0
-
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_MASK	0x02
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT	1
-
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_MASK	0x04
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT	2
-
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_MASK	0x08
-#define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT	3
-
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_MASK		0x01
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_MASK			0x02
-#define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_SHIFT		1
-
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_MASK		0x01
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_MASK			0x02
-#define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_SHIFT		1
-
-#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_MASK		0x01
-#define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_MASK		0x01
-#define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_MASK		0x04
-#define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_SHIFT		2
-
-#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_MASK		0x0F
-#define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK		0x0F
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_MASK	0x30
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_SHIFT	4
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_MASK	0x40
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_SHIFT	6
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_MASK		0x01
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_MASK		0x06
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_SHIFT		1
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_MASK		0x0F
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_MASK	0x03
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_SHIFT	0
-
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_MASK		0x04
-#define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_SHIFT		2
-
-#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_MASK		0xF0
-#define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_SHIFT		4
-
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_MASK		0x07
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_MASK		0xF0
-#define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_SHIFT		4
-
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_MASK		0x07
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_SHIFT	0
-
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK		0x08
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT		3
-
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK	0x10
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT	4
-
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK		0x1F
-#define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK		0x03
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_MASK		0x04
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT		2
-
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_MASK	0x10
-#define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT	4
-
-#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_MASK		0x01
-#define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_MASK		0x07
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_MASK		0x08
-#define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT		3
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_MASK		0x07
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_MASK			0x08
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT		3
-
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK		0x70
-#define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT		4
-
-#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_MASK			0x01
-#define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_SHIFT			0
-
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_MASK		0x07
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_MASK		0x38
-#define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_SHIFT		3
-
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_MASK		0x07
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_MASK		0x38
-#define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_SHIFT		3
-
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK			0x01
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT			0
-
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_MASK		0x01
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_MASK		0x02
-#define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_SHIFT		1
-
-#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_MASK		0x01
-#define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_MASK			0x01
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT			0
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_MASK		0x02
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT		1
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_MASK		0x04
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT		2
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_MASK		0x08
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_SHIFT		3
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_MASK			0x10
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_SHIFT			4
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_MASK		0x20
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_SHIFT		5
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_MASK		0x40
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_SHIFT		6
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_MASK			0x01
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_SHIFT			0
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_MASK			0x06
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_SHIFT			1
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_MASK			0x08
-#define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_SHIFT			3
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_MASK		0x01
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_MASK		0x02
-#define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_SHIFT		1
-
-#define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK			0xFF
-#define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK		0xFF
-#define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT		0
-
-/********************************* LEQ_REFCLK *********************************/
-#define SERDES_25G_LANE_LEQ_REFCLK_BASE					0x200
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x00)
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x02)
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x03)
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x05)
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x07)
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x09)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0A)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0B)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0C)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0E)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0F)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x10)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x11)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x20)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x21)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x22)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x23)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x24)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x25)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x26)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x27)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x28)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x29)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2A)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2B)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2C)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2E)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x30)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x31)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x32)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x33)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x34)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x35)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x36)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x37)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x38)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x39)
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3A)
-#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3D)
-#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3E)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x40)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x41)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x42)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x43)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x44)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x45)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x46)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x50)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x51)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x52)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x53)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x54)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x55)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x56)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x57)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x58)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x59)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5A)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5B)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5C)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5D)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5E)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5F)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x60)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x61)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x62)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x63)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x64)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x65)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x66)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x67)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x68)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x70)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x71)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x72)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x73)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x74)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x75)
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x76)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x80)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x81)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x82)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x83)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x84)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x85)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x86)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x87)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x88)
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x90)
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x91)
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x92)
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x93)
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x94)
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x95)
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x96)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x98)
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x99)
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9A)
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9B)
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9C)
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9D)
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA0)
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA1)
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA2)
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA3)
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA6)
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA7)
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA8)
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA9)
-#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAB)
-#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAC)
-#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAE)
-#define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_ADDR	(SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAF)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xB8)
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xB9)
-
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_MASK			 0x3F
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_SHIFT			 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_BIASGEN_MASK		 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_BIASGEN_SHIFT		 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_RXLEQ_BIAS_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_RXLEQ_BIAS_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_VGSW_SEL_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_VGSW_SEL_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_MASK		 0x18
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_SHIFT	 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_MUTE_MASK		 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_MUTE_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_MASK	 0x06
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_SHIFT	 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_PRECH_MASK		 0x08
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_PRECH_SHIFT		 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_RXLEQ_EQ_SQL_DIR_MASK		 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_RXLEQ_EQ_SQL_DIR_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_RXLEQ_SPARE_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_RXLEQ_SPARE_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START0_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START1_MASK		 0x38
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START1_SHIFT		 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START2_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START2_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START3_MASK		 0x38
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START3_SHIFT		 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE0_MASK			 0x03
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE1_MASK			 0x0C
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE1_SHIFT		 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE2_MASK			 0x30
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE2_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE3_MASK			 0xC0
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE3_SHIFT		 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START0_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START1_MASK		 0x38
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START1_SHIFT		 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START2_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START2_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START3_MASK		 0x38
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START3_SHIFT		 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START0_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START1_MASK		 0x38
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START1_SHIFT		 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START2_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START2_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START3_MASK		 0x38
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START3_SHIFT		 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK		 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_STATE_RESET_MASK	 0x04
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_STATE_RESET_SHIFT	 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_OPCODE_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_OPCODE_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_TARGET_MASK		 0xF0
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_TARGET_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_LEQ_FSM_CMD_SCRATCHPAD_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_LEQ_FSM_CMD_SCRATCHPAD_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_LEQ_FSM_CMD_MISC_OPTION_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_LEQ_FSM_CMD_MISC_OPTION_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_MASK	 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_MASK	 0x38
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_SHIFT	 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MAX_CLAMP_MASK	 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MAX_CLAMP_SHIFT	 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MIN_CLAMP_MASK	 0x80
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MIN_CLAMP_SHIFT	 7
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_STATE_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_STATE_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_LAST_RESULT_MASK	 0xF0
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_LAST_RESULT_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_LEQ_FSM_LAST_STEP_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_LEQ_FSM_LAST_STEP_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_LEQ_FSM_LAST_VALUE_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_LEQ_FSM_LAST_VALUE_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_OPCODE_MASK	 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_OPCODE_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_TARGET_MASK	 0xF0
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_TARGET_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_LEQ_FSM_TIMEOUT_LIMIT_7_0_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_LEQ_FSM_TIMEOUT_LIMIT_7_0_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_LEQ_FSM_TIMEOUT_LIMIT_15_8_MASK 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_LEQ_FSM_TIMEOUT_LIMIT_15_8_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_MASK		 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_SHIFT	 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_LEQ_FSM_2LST_VALUE_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_LEQ_FSM_2LST_VALUE_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_LEQ_OUTINTF_RDY_WAIT_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_LEQ_OUTINTF_RDY_WAIT_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_AGCLOS_VALUE_MAX_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_AGCLOS_VALUE_MAX_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_AGCLOS_VALUE_MIN_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_AGCLOS_VALUE_MIN_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_WRWAIT_TIME_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_WRWAIT_TIME_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_INIT_TIMEOUT_DISABLE_MASK 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_INIT_TIMEOUT_DISABLE_SHIFT 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_MEASURE_TIMEOUT_DISABLE_MASK 0x80
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_MEASURE_TIMEOUT_DISABLE_SHIFT 7
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_BY1_MASK		 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_BY1_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_ERROR_SIGN_MASK		 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_ERROR_SIGN_SHIFT		 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_SIZE_MASK		 0x1C
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_SIZE_SHIFT		 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_BOUNCE_LIMIT_MASK	 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_BOUNCE_LIMIT_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_AVG_MASK		 0x30
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_AVG_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_FLOOR_MASK	 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_FLOOR_SHIFT	 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_AGCLOS_LASTWR_ADJUST_MASK	 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_AGCLOS_LASTWR_ADJUST_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_AGCLOS_PEAK_ACQ_TIME_7_0_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_AGCLOS_PEAK_ACQ_TIME_7_0_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_AGCLOS_PEAK_ACQ_TIME_15_8_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_AGCLOS_PEAK_ACQ_TIME_15_8_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_AGCLOS_PEAK_ACQ_TIME_23_16_MASK	 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_AGCLOS_PEAK_ACQ_TIME_23_16_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_AGCLOS_PEAK_ACQ_TIME_25_24_MASK 0x03
-#define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_AGCLOS_PEAK_ACQ_TIME_25_24_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_WRWAIT_TIME_MASK	 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_WRWAIT_TIME_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_STEP_BY1_MASK		 0x10
-#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_STEP_BY1_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_PLE_LFG_START_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_PLE_LFG_START_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_MASK	 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_EQ_HFG_SQL_VALUE_MAX_MASK	 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_EQ_HFG_SQL_VALUE_MAX_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_EQ_HFG_SQL_VALUE_MIN_MASK	 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_EQ_HFG_SQL_VALUE_MIN_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_WRWAIT_TIME_MASK	 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_WRWAIT_TIME_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_MEASURE_TIMEOUT_DISABLE_MASK 0x80
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_MEASURE_TIMEOUT_DISABLE_SHIFT 7
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_BY1_MASK	 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_BY1_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_ERROR_SIGN_MASK	 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_ERROR_SIGN_SHIFT	 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_SIZE_MASK	 0x1C
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_SIZE_SHIFT	 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_BOUNCE_LIMIT_MASK 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_BOUNCE_LIMIT_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_AVG_MASK	 0x30
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_AVG_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_FLOOR_MASK 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_FLOOR_SHIFT 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_EQ_HFG_SQL_LASTWR_ADJUST_MASK 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_EQ_HFG_SQL_LASTWR_ADJUST_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE0_MASK	 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE0_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE1_MASK	 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE1_SHIFT	 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE2_MASK	 0x04
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE2_SHIFT	 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE3_MASK	 0x08
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE3_SHIFT	 3
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP0_RATE0_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP0_RATE0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP1_RATE0_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP1_RATE0_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP2_RATE0_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP2_RATE0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP3_RATE0_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP3_RATE0_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP4_RATE0_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP4_RATE0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP5_RATE0_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP5_RATE0_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP6_RATE0_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP6_RATE0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP7_RATE0_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP7_RATE0_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP8_RATE0_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP8_RATE0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP9_RATE0_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP9_RATE0_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP10_RATE0_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP10_RATE0_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP11_RATE0_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP11_RATE0_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP0_RATE1_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP0_RATE1_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP1_RATE1_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP1_RATE1_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP2_RATE1_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP2_RATE1_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP3_RATE1_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP3_RATE1_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP4_RATE1_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP4_RATE1_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP5_RATE1_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP5_RATE1_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP6_RATE1_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP6_RATE1_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP7_RATE1_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP7_RATE1_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP8_RATE1_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP8_RATE1_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP9_RATE1_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP9_RATE1_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP10_RATE1_MASK	 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP10_RATE1_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP11_RATE1_MASK	 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP11_RATE1_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP0_RATE2_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP0_RATE2_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP1_RATE2_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP1_RATE2_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP2_RATE2_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP2_RATE2_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP3_RATE2_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP3_RATE2_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP4_RATE2_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP4_RATE2_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP5_RATE2_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP5_RATE2_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP6_RATE2_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP6_RATE2_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP7_RATE2_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP7_RATE2_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP8_RATE2_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP8_RATE2_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP9_RATE2_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP9_RATE2_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP10_RATE2_MASK	 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP10_RATE2_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP11_RATE2_MASK	 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP11_RATE2_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP0_RATE3_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP0_RATE3_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP1_RATE3_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP1_RATE3_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP2_RATE3_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP2_RATE3_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP3_RATE3_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP3_RATE3_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP4_RATE3_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP4_RATE3_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP5_RATE3_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP5_RATE3_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP6_RATE3_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP6_RATE3_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP7_RATE3_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP7_RATE3_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP8_RATE3_MASK		 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP8_RATE3_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP9_RATE3_MASK		 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP9_RATE3_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP10_RATE3_MASK	 0x07
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP10_RATE3_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP11_RATE3_MASK	 0x70
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP11_RATE3_SHIFT	 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_MASK		 0x03
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MAX_MASK		 0x03
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MAX_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MIN_MASK		 0x0C
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MIN_SHIFT		 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_WRWAIT_TIME_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_WRWAIT_TIME_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_MEASURE_TIMEOUT_DISABLE_MASK 0x80
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_MEASURE_TIMEOUT_DISABLE_SHIFT 7
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_BY1_MASK		 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_BY1_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_ERROR_SIGN_MASK		 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_ERROR_SIGN_SHIFT		 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_SIZE_MASK		 0x0C
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_SIZE_SHIFT		 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_BOUNCE_LIMIT_MASK	 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_BOUNCE_LIMIT_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_AVG_MASK		 0x30
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_AVG_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_FLOOR_MASK	 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_FLOOR_SHIFT	 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_GN_APG_LASTWR_ADJUST_MASK	 0x03
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_GN_APG_LASTWR_ADJUST_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_DELTA_MASK		 0x03
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_DELTA_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_MAX_MASK		 0x0C
-#define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_MAX_SHIFT		 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_MASK		 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_MASK		 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_MASK		 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_WRWAIT_TIME_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_WRWAIT_TIME_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_MEASURE_TIMEOUT_DISABLE_MASK 0x80
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_MEASURE_TIMEOUT_DISABLE_SHIFT 7
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_BY1_MASK		 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_BY1_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_ERROR_SIGN_MASK		 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_ERROR_SIGN_SHIFT		 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_SIZE_MASK		 0x1C
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_SIZE_SHIFT		 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_BOUNCE_LIMIT_MASK	 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_BOUNCE_LIMIT_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_AVG_MASK		 0x30
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_AVG_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_FLOOR_MASK	 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_FLOOR_SHIFT	 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_EQ_LFG_LASTWR_ADJUST_MASK	 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_EQ_LFG_LASTWR_ADJUST_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_EQ_LFG_CCL_DELTA_MASK		 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_EQ_LFG_CCL_DELTA_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_EQ_LFG_CCL_MAX_MASK		 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_EQ_LFG_CCL_MAX_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_GNEQ_CCL_LFG_START_MASK	 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_GNEQ_CCL_LFG_START_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_GNEQ_CCL_LFG_VALUE_MAX_MASK 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_GNEQ_CCL_LFG_VALUE_MAX_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_GNEQ_CCL_LFG_VALUE_MIN_MASK 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_GNEQ_CCL_LFG_VALUE_MIN_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_WRWAIT_TIME_MASK 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_WRWAIT_TIME_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_MEASURE_TIMEOUT_DISABLE_MASK	0x80
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_MEASURE_TIMEOUT_DISABLE_SHIFT 7
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_BY1_MASK 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_BY1_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_ERROR_SIGN_MASK 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_ERROR_SIGN_SHIFT 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_SIZE_MASK 0x1C
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_SIZE_SHIFT 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_BOUNCE_LIMIT_MASK 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_BOUNCE_LIMIT_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_AVG_MASK 0x30
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_AVG_SHIFT 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_FLOOR_MASK 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_FLOOR_SHIFT 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_GNEQ_CCL_LFG_LASTWR_ADJUST_MASK 0x1F
-#define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_GNEQ_CCL_LFG_LASTWR_ADJUST_SHIFT 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_WRWAIT_TIME_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_WRWAIT_TIME_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_STEP_BY1_MASK		 0x10
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_STEP_BY1_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_MASK		 0xF0
-#define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_VSCAN_VALUE_MAX_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_VSCAN_VALUE_MAX_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_VSCAN_VALUE_MIN_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_VSCAN_VALUE_MIN_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_BY1_MASK		 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_BY1_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_ERROR_SIGN_MASK		 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_ERROR_SIGN_SHIFT		 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_SIZE_MASK		 0x3C
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_SIZE_SHIFT		 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_BOUNCE_LIMIT_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_BOUNCE_LIMIT_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_AVG_MASK		 0x30
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_AVG_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_FLOOR_MASK		 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_FLOOR_SHIFT		 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_HSCAN_VALUE_MAX_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_HSCAN_VALUE_MAX_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_HSCAN_VALUE_MIN_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_HSCAN_VALUE_MIN_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_BY1_MASK		 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_BY1_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_ERROR_SIGN_MASK		 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_ERROR_SIGN_SHIFT		 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_SIZE_MASK		 0x3C
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_SIZE_SHIFT		 2
-
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_BOUNCE_LIMIT_MASK		 0x0F
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_BOUNCE_LIMIT_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_AVG_MASK		 0x30
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_AVG_SHIFT		 4
-
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_FLOOR_MASK		 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_FLOOR_SHIFT		 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_GN_APG_REF_N_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_GN_APG_REF_N_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_GN_APG_REF_P_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_GN_APG_REF_P_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_EQ_LFG_REF_N_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_EQ_LFG_REF_N_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_EQ_LFG_REF_P_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_EQ_LFG_REF_P_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_EYE_PHASE_7_0_MASK		 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_EYE_PHASE_7_0_SHIFT		 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_8_MASK			 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_8_SHIFT			 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_VALID_MASK		 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_VALID_SHIFT		 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_ODDEYE_MASK		 0x01
-#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_ODDEYE_SHIFT	 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_PATH1_MASK		 0x02
-#define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_PATH1_SHIFT		 1
-
-#define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_EYEINTF_INIT_TIMEOUT_DISABLE_MASK 0x40
-#define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_EYEINTF_INIT_TIMEOUT_DISABLE_SHIFT 6
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_MASK			 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_SHIFT			 0
-
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_MASK			 0xFF
-#define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_SHIFT			 0
-
-/********************************* DRV_REFCLK *********************************/
-#define SERDES_25G_LANE_DRV_REFCLK_BASE					0x380
-
-#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x00)
-#define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x01)
-#define SERDES_25G_LANE_DRV_AFE_CTRL1_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x03)
-#define SERDES_25G_LANE_DRV_AFE_CTRL2_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x04)
-#define SERDES_25G_LANE_DRV_AFE_CTRL3_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x05)
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x06)
-#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x08)
-#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x09)
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0A)
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0B)
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0C)
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0D)
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x10)
-#define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x11)
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x12)
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL2_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x13)
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x14)
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x15)
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR		(SERDES_25G_LANE_DRV_REFCLK_BASE + 0x16)
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_PD_TXDRV_MASK			0x01
-#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_PD_TXDRV_SHIFT			0
-
-#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_TXDRV_LP_IDLE_MASK		0x02
-#define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_TXDRV_LP_IDLE_SHIFT		1
-
-#define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_RST_TXDRV_DIV2_N_MASK		0x01
-#define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_RST_TXDRV_DIV2_N_SHIFT	0
-
-#define SERDES_25G_LANE_DRV_AFE_CTRL1_TXDRV_SPARE_MASK			0xFF
-#define SERDES_25G_LANE_DRV_AFE_CTRL1_TXDRV_SPARE_SHIFT			0
-
-#define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_TOGGLE_EN_MASK		0x01
-#define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_TOGGLE_EN_SHIFT		0
-
-#define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_CLK_DELAY_MASK		0x3E
-#define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_CLK_DELAY_SHIFT		1
-
-#define SERDES_25G_LANE_DRV_AFE_CTRL3_TXDRV_CO_POL_MASK			0x07
-#define SERDES_25G_LANE_DRV_AFE_CTRL3_TXDRV_CO_POL_SHIFT		0
-
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_P5_MASK		0x01
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_P5_SHIFT		0
-
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X1_MASK		0x02
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X1_SHIFT		1
-
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X2_MASK		0x1C
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X2_SHIFT		2
-
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X1_MASK		0x20
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X1_SHIFT	5
-
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X2_MASK		0xC0
-#define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X2_SHIFT	6
-
-#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_P5_MASK		0x01
-#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_P5_SHIFT	0
-
-#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X1_MASK		0x02
-#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X1_SHIFT	1
-
-#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X2_MASK		0x0C
-#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X2_SHIFT	2
-
-#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CXCM1_X2_MASK	0x10
-#define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CXCM1_X2_SHIFT	4
-
-#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X1_MASK		0x07
-#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X1_SHIFT	0
-
-#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X2_MASK		0xF8
-#define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X2_SHIFT	3
-
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_CXN_X1_MASK	0x07
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_CXN_X1_SHIFT	0
-
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_FIXEDCXN_X1_MASK	0x18
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_FIXEDCXN_X1_SHIFT	3
-
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_CXN_X2_MASK	0x1F
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_CXN_X2_SHIFT	0
-
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_FIXEDCXN_XP5_MASK	0x60
-#define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_FIXEDCXN_XP5_SHIFT	5
-
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_CXP_X1_MASK	0x07
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_CXP_X1_SHIFT	0
-
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_FIXEDCXP_X1_MASK	0x18
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_FIXEDCXP_X1_SHIFT	3
-
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_CXP_X2_MASK	0x1F
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_CXP_X2_SHIFT	0
-
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_FIXEDCXP_XP5_MASK	0x60
-#define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_FIXEDCXP_XP5_SHIFT	5
-
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK				0x01
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT			0
-
-#define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_MASK			0x01
-#define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_SHIFT			0
-
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK			0x1F
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT			0
-
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL2_TXEQ_C2_MASK			0x03
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL2_TXEQ_C2_SHIFT			0
-
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK			0x0F
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT			0
-
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_TXEQ_1LSB_MODE_MASK		0x01
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_TXEQ_1LSB_MODE_SHIFT		0
-
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_SWING_1LSB_MODE_MASK		0x02
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL4_SWING_1LSB_MODE_SHIFT		1
-
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK			0x0F
-#define SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT			0
-
-/********************************* DFE REFCLK *********************************/
-#define SERDES_25G_LANE_DFE_REFCLK_BASE					0x400
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_ADDR                   (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x00)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_ADDR                   (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x01)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_ADDR                   (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x02)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_ADDR                  (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x04)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_ADDR               (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x06)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_ADDR                 (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0A)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_ADDR                  (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0C)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_ADDR               (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0E)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_ADDR                  (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x10)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_ADDR                 (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x12)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x14)
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x16)
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x18)
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x19)
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_ADDR                 (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x1B)
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x20)
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x21)
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x22)
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x23)
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x24)
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x25)
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x26)
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x27)
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ADDR                    (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x28)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_ADDR                      (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2A)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2B)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2C)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2D)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2E)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2F)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x30)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x31)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x32)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_ADDR             (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x33)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_ADDR             (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x34)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_ADDR             (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x35)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_ADDR             (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x36)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_ADDR             (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x37)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_ADDR             (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x38)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_ADDR             (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x39)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_ADDR             (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3A)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3B)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3C)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3D)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3E)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3F)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x40)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x41)
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_ADDR                (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x42)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ADDR              (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x50)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_ADDR              (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x51)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_ADDR              (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x52)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_ADDR     (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x53)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_ADDR     (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x54)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ADDR     (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x55)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ADDR     (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x56)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_ADDR     (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x57)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ADDR     (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x58)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_ADDR     (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x59)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ADDR     (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5A)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_ADDR        (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5B)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_ADDR        (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5C)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ADDR        (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5D)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ADDR        (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5E)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_ADDR        (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5F)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ADDR        (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x60)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_ADDR        (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x61)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ADDR        (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x62)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ADDR  (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x63)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x64)
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ADDR            (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x65)
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_MASK                           0x01
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_SHIFT                          0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_TAP_MASK                       0x3E
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_TAP_SHIFT                      1
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_EVEN_PATH_MASK                 0x03
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_EVEN_PATH_SHIFT                0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_ODD_PATH_MASK                  0x0C
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_ODD_PATH_SHIFT                 2
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_EVEN_MASK                  0x07
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_EVEN_SHIFT                 0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_ODD_MASK                   0x38
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_ODD_SHIFT                  3
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_RST_RXDFE_N_MASK                       0x01
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_RST_RXDFE_N_SHIFT                      0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_RXDFE_TOGGLE_EN_MASK                0x01
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_RXDFE_TOGGLE_EN_SHIFT               0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_EVEN_MASK              0x01
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_EVEN_SHIFT             0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_ODD_MASK               0x02
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_ODD_SHIFT              1
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_EDGE_MUTE_MASK                  0x0C
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_EDGE_MUTE_SHIFT                 2
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLK_DELAY_MASK                   0x0F
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLK_DELAY_SHIFT                  0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLKDIV_OVR_MASK                  0x30
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLKDIV_OVR_SHIFT                 4
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYECLK_DELAY_MASK             0x0F
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYECLK_DELAY_SHIFT            0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_CLKDIVEYE_OVR_MASK            0x30
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_CLKDIVEYE_OVR_SHIFT           4
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYERESAMP_ADJ_MASK            0xC0
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYERESAMP_ADJ_SHIFT           6
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLI_MASK                        0x0F
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLI_SHIFT                       0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_MASK                        0x30
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_SHIFT                       4
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_LTCH_MASK                   0x40
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_LTCH_SHIFT                  6
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_SUMGAIN_MASK                    0x01
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_SUMGAIN_SHIFT                   0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_LDR_MASK                        0x06
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_LDR_SHIFT                       1
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_RXDFE_SPARE_MASK                           0xFF
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_RXDFE_SPARE_SHIFT                          0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIV_QSAMPLE_MASK        0x01
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIV_QSAMPLE_SHIFT       0
-
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIVEYE_QSAMPLE_MASK     0x1E
-#define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIVEYE_QSAMPLE_SHIFT    1
-
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_MAG_MASK                             0xFF
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_MAG_SHIFT                            0
-
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_POL_MASK                             0x01
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_POL_SHIFT                            0
-
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_MAG_MASK                              0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_MAG_SHIFT                             0
-
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_POL_MASK                              0x80
-#define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_POL_SHIFT                             7
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_REQ_MASK                                   0x01
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_REQ_SHIFT                                  0
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_CMD_MASK                                   0x3E
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_CMD_SHIFT                                  1
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_FINISH_MASK                                0x40
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_FINISH_SHIFT                               6
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_MASK                     0x80
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_SHIFT                    7
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_NEXT_STATE_MASK                            0x0F
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_NEXT_STATE_SHIFT                           0
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_CTRL_EN_MASK                               0x10
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_CTRL_EN_SHIFT                              4
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_WAIT_1_TIMER7_0_MASK                       0xFF
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_WAIT_1_TIMER7_0_SHIFT                      0
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_WAIT_1_TIMER9_8_MASK                       0x03
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_WAIT_1_TIMER9_8_SHIFT                      0
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_WAIT_2_TIMER7_0_MASK                       0xFF
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_WAIT_2_TIMER7_0_SHIFT                      0
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_WAIT_2_TIMER9_8_MASK                       0x03
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_WAIT_2_TIMER9_8_SHIFT                      0
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_TAP_DELAY_7_0_MASK                         0xFF
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_TAP_DELAY_7_0_SHIFT                        0
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_TAP_DELAY_9_8_MASK                         0x03
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_TAP_DELAY_9_8_SHIFT                        0
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ACK_MASK                                 0x01
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ACK_SHIFT                                0
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_SLICER_OFST_ACK_MASK                     0x02
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_SLICER_OFST_ACK_SHIFT                    1
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ERR_FUNC_ACK_MASK                        0x04
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ERR_FUNC_ACK_SHIFT                       2
-
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_AFE_DRV_ACK_MASK                         0x08
-#define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_AFE_DRV_ACK_SHIFT                        3
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_MASK                         0x01
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_SHIFT                        0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_MASK                         0x02
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_SHIFT                        1
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_MASK                          0x04
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_SHIFT                         2
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_MASK                          0x08
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_SHIFT                         3
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP2_EN_MASK                               0x10
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP2_EN_SHIFT                              4
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP3_EN_MASK                               0x20
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP3_EN_SHIFT                              5
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP4_EN_MASK                               0x40
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP4_EN_SHIFT                              6
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP5_EN_MASK                               0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP5_EN_SHIFT                              7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_MASK                  0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_SHIFT                 0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_MASK         0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT        7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_MASK                  0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_SHIFT                 0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_MASK         0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT        7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_MASK                   0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_SHIFT                  0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_MASK          0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT         7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_MASK                   0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_SHIFT                  0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_MASK          0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT         7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_MASK                        0x0F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_SHIFT                       0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_MASK               0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_SHIFT              7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_MASK                        0x07
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_SHIFT                       0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_MASK               0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_SHIFT              7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_MASK                        0x07
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_SHIFT                       0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_MASK               0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_SHIFT              7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_MASK                        0x07
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_SHIFT                       0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_MASK               0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_SHIFT              7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_MASK                   0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_SHIFT                  0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_MASK          0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT         7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_MASK                   0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_SHIFT                  0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_MASK          0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT         7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_MASK                    0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_SHIFT                   0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_MASK           0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT          7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_MASK                    0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_SHIFT                   0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_MASK           0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT          7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_MASK                         0x0F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_SHIFT                        0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_MASK                0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_SHIFT               7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_MASK                         0x07
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_SHIFT                        0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_MASK                0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_SHIFT               7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_MASK                         0x07
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_SHIFT                        0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_MASK                0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_SHIFT               7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_MASK                         0x07
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_SHIFT                        0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_MASK                0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_SHIFT               7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_MASK                      0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_SHIFT                     0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_MASK             0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_SHIFT            7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_MASK                      0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_SHIFT                     0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_MASK             0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_SHIFT            7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_MASK                       0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_SHIFT                      0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_MASK              0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_SHIFT             7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_MASK                       0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_SHIFT                      0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_MASK              0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_SHIFT             7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_MASK                            0x0F
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_SHIFT                           0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_MASK                   0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_SHIFT                  7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_MASK                            0x07
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_SHIFT                           0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_MASK                   0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_SHIFT                  7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_MASK                            0x07
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_SHIFT                           0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_MASK                   0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_SHIFT                  7
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_MASK                            0x07
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_SHIFT                           0
-
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_MASK                   0x80
-#define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_SHIFT                  7
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN0_DATA_EN_MASK                 0x01
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN0_DATA_EN_SHIFT                0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN1_DATA_EN_MASK                 0x02
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN1_DATA_EN_SHIFT                1
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD0_DATA_EN_MASK                  0x04
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD0_DATA_EN_SHIFT                 2
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD1_DATA_EN_MASK                  0x08
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD1_DATA_EN_SHIFT                 3
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EDGE_EN_MASK                  0x10
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EDGE_EN_SHIFT                 4
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EDGE_EN_MASK                   0x20
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EDGE_EN_SHIFT                  5
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EYE_EN_MASK                   0x40
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EYE_EN_SHIFT                  6
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EYE_EN_MASK                    0x80
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EYE_EN_SHIFT                   7
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_LIMIT_MASK                         0x1F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_LIMIT_SHIFT                        0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_MAX_BOUNCES_MASK                   0x0F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_MAX_BOUNCES_SHIFT                  0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_EVEN0_DATA_MASK           0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_EVEN0_DATA_SHIFT          0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_EVEN1_DATA_MASK           0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_EVEN1_DATA_SHIFT          0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ODD0_DATA_MASK            0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ODD0_DATA_SHIFT           0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ODD1_DATA_MASK            0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ODD1_DATA_SHIFT           0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_EVEN_EDGE_MASK            0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_EVEN_EDGE_SHIFT           0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ODD_EDGE_MASK             0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ODD_EDGE_SHIFT            0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_EVEN_EYE_MASK             0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_EVEN_EYE_SHIFT            0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ODD_EYE_MASK              0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ODD_EYE_SHIFT             0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_EVEN0_DATA_MASK              0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_EVEN0_DATA_SHIFT             0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_EVEN1_DATA_MASK              0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_EVEN1_DATA_SHIFT             0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ODD0_DATA_MASK               0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ODD0_DATA_SHIFT              0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ODD1_DATA_MASK               0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ODD1_DATA_SHIFT              0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_EVEN_EDGE_MASK               0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_EVEN_EDGE_SHIFT              0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ODD_EDGE_MASK                0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ODD_EDGE_SHIFT               0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_EVEN_EYE_MASK                0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_EVEN_EYE_SHIFT               0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ODD_EYE_MASK                 0x3F
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ODD_EYE_SHIFT                0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN0_DATA_MASK        0x01
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN0_DATA_SHIFT       0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN1_DATA_MASK        0x02
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN1_DATA_SHIFT       1
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD0_DATA_MASK         0x04
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD0_DATA_SHIFT        2
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD1_DATA_MASK         0x08
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD1_DATA_SHIFT        3
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EDGE_MASK         0x10
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EDGE_SHIFT        4
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EDGE_MASK          0x20
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EDGE_SHIFT         5
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EYE_MASK          0x40
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EYE_SHIFT         6
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EYE_MASK           0x80
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EYE_SHIFT          7
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ERR_MASK                         0x01
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ERR_SHIFT                        0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_INC_MASK                         0x02
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_INC_SHIFT                        1
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_DEC_MASK                         0x04
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_DEC_SHIFT                        2
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN0_DATA_MASK                  0x01
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN0_DATA_SHIFT                 0
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN1_DATA_MASK                  0x02
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN1_DATA_SHIFT                 1
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD0_DATA_MASK                   0x04
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD0_DATA_SHIFT                  2
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD1_DATA_MASK                   0x08
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD1_DATA_SHIFT                  3
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EDGE_MASK                   0x10
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EDGE_SHIFT                  4
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EDGE_MASK                    0x20
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EDGE_SHIFT                   5
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EYE_MASK                    0x40
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EYE_SHIFT                   6
-
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EYE_MASK                     0x80
-#define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EYE_SHIFT                    7
-
-/********************************** LOS REFCLK **********************************/
-#define SERDES_25G_LANE_LOS_REFCLK_BASE					0x500
-
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x00)
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x01)
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_ADDR  (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x02)
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x10)
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x11)
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x12)
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x13)
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x14)
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x15)
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x16)
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x20)
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x21)
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x22)
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x23)
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x24)
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x30)
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x31)
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x32)
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x33)
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x40)
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x41)
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x42)
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_ADDR    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x43)
-#define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_ADDR            (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x46)
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_ADDR   (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x51)
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x59)
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x60)
-#define SERDES_25G_LANE_LOS_REFCLK_CTRL0_ADDR		    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x70)
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_ADDR		    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x71)
-#define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x72)
-#define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_ADDR	    (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x73)
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_MASK			0x01
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_SHIFT			0
-
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ASSERT_THRESHOLD_MASK	0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ASSERT_THRESHOLD_SHIFT	0
-
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_MASK		0x01
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_MASK	0x02
-#define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_SHIFT	1
-
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ASSERT_THRESHOLD_7_0_MASK	0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ASSERT_THRESHOLD_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ASSERT_THRESHOLD_15_8_MASK	0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ASSERT_THRESHOLD_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_DEASSERT_THRESHOLD_7_0_MASK	0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_DEASSERT_THRESHOLD_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_DEASSERT_THRESHOLD_15_8_MASK	0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_DEASSERT_THRESHOLD_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_DEASSERT_THRESHOLD_23_16_MASK	0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_DEASSERT_THRESHOLD_23_16_SHIFT	0
-
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_MASK	0x03
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_SHIFT	0
-
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_EN_MASK				0x01
-#define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_EN_SHIFT			0
-
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_EN_MASK			0x01
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_EN_SHIFT			0
-
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_PERIOD_7_0_MASK		0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_PERIOD_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_PERIOD_15_8_MASK		0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_PERIOD_15_8_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_PERIOD_23_16_MASK		0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_PERIOD_23_16_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_PERIOD_25_24_MASK		0x03
-#define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_PERIOD_25_24_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_MASK			0x01
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_MASK		0x10
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_SHIFT		4
-
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_EN_MASK			0x01
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_EN_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_VALUE_MASK		0x10
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_VALUE_SHIFT		4
-
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_VALUE_MASK		0x3F
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_VALUE_SHIFT	0
-
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_EN_MASK		0x40
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_EN_SHIFT		6
-
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_VALUE_MASK		0x3F
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_VALUE_SHIFT	0
-
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_EN_MASK		0x40
-#define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_EN_SHIFT		6
-
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_BANDWIDTH_MASK		0x01
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_BANDWIDTH_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_HYSTERESIS_MASK		0x0E
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_HYSTERESIS_SHIFT		1
-
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ENVDET_BYP_MASK		0x10
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ENVDET_BYP_SHIFT		4
-
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_GAIN_MASK			0x01
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_GAIN_SHIFT			0
-
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_LOS_INVERT_MASK		0x02
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_LOS_INVERT_SHIFT		1
-
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_AGC_INVERT_MASK		0x04
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_AGC_INVERT_SHIFT		2
-
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_THRESHOLD_MASK		0x78
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_THRESHOLD_SHIFT		3
-
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_MODE_SWITCH_WAIT_7_0_MASK   0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_MODE_SWITCH_WAIT_7_0_SHIFT  0
-
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_MODE_SWITCH_WAIT_15_8_MASK  0xFF
-#define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_MODE_SWITCH_WAIT_15_8_SHIFT 0
-
-#define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_EYE_DATA_PARITY_MASK                0x01
-#define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_EYE_DATA_PARITY_SHIFT               0
-
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_EN_MASK                    0x01
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_EN_SHIFT                   0
-
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_MODE_MASK                  0x02
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_MODE_SHIFT                 1
-
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_LOS_OFFSET_MASK		0x3F
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_LOS_OFFSET_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_AGC_CALIB_DONE_MASK	0x40
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_AGC_CALIB_DONE_SHIFT	6
-
-#define SERDES_25G_LANE_LOS_REFCLK_CTRL0_EN_MASK				0x01
-#define SERDES_25G_LANE_LOS_REFCLK_CTRL0_EN_SHIFT				0
-
-#define SERDES_25G_LANE_FEATURE_CTRL0_SRC_SELECT_MASK                           0x02
-#define SERDES_25G_LANE_FEATURE_CTRL0_SRC_SELECT_SHIFT                          1
-
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_READY_MASK			0x01
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_READY_SHIFT			0
-
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_READY_MASK			0x02
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_READY_SHIFT			1
-
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_MASK				0x04
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_SHIFT				2
-
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_RAW_MASK				0x08
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_RAW_SHIFT			3
-
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_MASK				0x10
-#define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_SHIFT				4
-
-#define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_RXLOS_SPARE_MASK		0x0F
-#define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_RXLOS_SPARE_SHIFT		0
-
-#define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_PD_RXLOS_MASK			0x01
-#define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_PD_RXLOS_SHIFT			0
-
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL6_REQ_MASK			0x01
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL6_REQ_SHIFT			0
-
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS2_ACK_MASK			0x01
-#define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS2_ACK_SHIFT		0
-
-/********************************** GCFSM2 **********************************/
-#define SERDES_25G_LANE_GCFSM2_BASE					0x580
-
-#define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR                 (SERDES_25G_LANE_GCFSM2_BASE + 0x00)
-#define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_ADDR                 (SERDES_25G_LANE_GCFSM2_BASE + 0x01)
-#define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR                 (SERDES_25G_LANE_GCFSM2_BASE + 0x02)
-#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x03)
-#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_ADDR  (SERDES_25G_LANE_GCFSM2_BASE + 0x10)
-#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_ADDR  (SERDES_25G_LANE_GCFSM2_BASE + 0x11)
-#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_ADDR        (SERDES_25G_LANE_GCFSM2_BASE + 0x12)
-#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_ADDR        (SERDES_25G_LANE_GCFSM2_BASE + 0x13)
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x20)
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x21)
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x22)
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x23)
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x24)
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x25)
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x26)
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_ADDR           (SERDES_25G_LANE_GCFSM2_BASE + 0x30)
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_ADDR           (SERDES_25G_LANE_GCFSM2_BASE + 0x31)
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_ADDR           (SERDES_25G_LANE_GCFSM2_BASE + 0x32)
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x40)
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x41)
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x42)
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x43)
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x44)
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x45)
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x46)
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x47)
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_ADDR                (SERDES_25G_LANE_GCFSM2_BASE + 0x48)
-#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_ADDR            (SERDES_25G_LANE_GCFSM2_BASE + 0x50)
-#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_ADDR            (SERDES_25G_LANE_GCFSM2_BASE + 0x51)
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK                                  0x01
-#define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT                                 0
-
-#define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_MASK                                  0x07
-#define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_SHIFT                                 0
-
-#define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR_MASK                                 0xFF
-#define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR_SHIFT                                0
-
-#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_MASK                                 0x01
-#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_SHIFT                                0
-
-#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_CODE_MASK                                0x1E
-#define SERDES_25G_LANE_GCFSM2_CMD_STATUS_CODE_SHIFT                               1
-
-#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_7_0_MASK                   0xFF
-#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_7_0_SHIFT                  0
-
-#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_MASK                  0x0F
-#define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_SHIFT                 0
-
-#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_7_0_MASK                         0xFF
-#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_7_0_SHIFT                        0
-
-#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_8_8_MASK                         0x01
-#define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_8_8_SHIFT                        0
-
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_TYPE_MASK                                0x03
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_TYPE_SHIFT                               0
-
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_WIDTH_MASK                               0x3C
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_WIDTH_SHIFT                              2
-
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_START_7_0_MASK                           0xFF
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_START_7_0_SHIFT                          0
-
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_START_11_8_MASK                          0x0F
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_START_11_8_SHIFT                         0
-
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_MIN_7_0_MASK                             0xFF
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_MIN_7_0_SHIFT                            0
-
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_MIN_11_8_MASK                            0x0F
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_MIN_11_8_SHIFT                           0
-
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_MAX_7_0_MASK                             0xFF
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_MAX_7_0_SHIFT                            0
-
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_MAX_11_8_MASK                            0x0F
-#define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_MAX_11_8_SHIFT                           0
-
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_STEP_SIZE_MASK                      0x1F
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_STEP_SIZE_SHIFT                     0
-
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_BOUNCE_NUM_MASK                     0x0F
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_BOUNCE_NUM_SHIFT                    0
-
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_COARSE_BOUNCE_NUM_MASK              0xF0
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_COARSE_BOUNCE_NUM_SHIFT             4
-
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_SETTLE_ON_LOWEST_AVG_EN_MASK        0x01
-#define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_SETTLE_ON_LOWEST_AVG_EN_SHIFT       0
-
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_LEN_DELAY_AFE_EN_MASK                    0x03
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_LEN_DELAY_AFE_EN_SHIFT                   0
-
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_LEN_AFE_1ST_LATCH_SETTLE_7_0_MASK        0xFF
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_LEN_AFE_1ST_LATCH_SETTLE_7_0_SHIFT       0
-
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_LEN_AFE_1ST_LATCH_SETTLE_15_8_MASK       0xFF
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_LEN_AFE_1ST_LATCH_SETTLE_15_8_SHIFT      0
-
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_LEN_AFE_LATCH_SETTLE_MASK                0xFF
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_LEN_AFE_LATCH_SETTLE_SHIFT               0
-
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_LEN_AFE_CMP_7_0_MASK                     0xFF
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_LEN_AFE_CMP_7_0_SHIFT                    0
-
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_LEN_AFE_CMP_15_8_MASK                    0xFF
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_LEN_AFE_CMP_15_8_SHIFT                   0
-
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_LEN_COARSE_BOUNCE_AFE_CMP_7_0_MASK       0xFF
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_LEN_COARSE_BOUNCE_AFE_CMP_7_0_SHIFT      0
-
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_LEN_COARSE_BOUNCE_AFE_CMP_15_8_MASK      0xFF
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_LEN_COARSE_BOUNCE_AFE_CMP_15_8_SHIFT     0
-
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_WAIT_MODE_MASK                           0x01
-#define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_WAIT_MODE_SHIFT                          0
-
-#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_INVERT_AFE_UP_MASK                   0x01
-#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_INVERT_AFE_UP_SHIFT                  0
-
-#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_LEN_WAIT_AFE_UP_MASK                 0x1E
-#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_LEN_WAIT_AFE_UP_SHIFT                1
-
-#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_LEN_AVG_AFE_UP_MASK                  0xFF
-#define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_LEN_AVG_AFE_UP_SHIFT                 0
-
-/**********************************  TX BIST **********************************/
-#define SERDES_25G_LANE_TX_BIST_BASE					0x600
-
-#define SERDES_25G_LANE_TX_BIST_CTRL_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x00)
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL0_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x04)
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL1_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x05)
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL2_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x06)
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL3_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x07)
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL4_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x08)
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL5_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x09)
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL6_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x0A)
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL7_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x0B)
-#define SERDES_25G_LANE_TX_BIST_UDP_SHIFT_AMOUNT_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x20)
-#define SERDES_25G_LANE_TX_BIST_UDP_ADDR(byte_num) \
-						((SERDES_25G_LANE_TX_BIST_BASE + 0x24) + byte_num)
-#define SERDES_25G_LANE_TX_BIST_UDP_NUM_BYTES		20
-#define SERDES_25G_LANE_TX_BIST_UDP_7_0_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x24)
-#define SERDES_25G_LANE_TX_BIST_UDP_15_8_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x25)
-#define SERDES_25G_LANE_TX_BIST_UDP_23_16_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x26)
-#define SERDES_25G_LANE_TX_BIST_UDP_31_24_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x27)
-#define SERDES_25G_LANE_TX_BIST_UDP_39_32_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x28)
-#define SERDES_25G_LANE_TX_BIST_UDP_47_40_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x29)
-#define SERDES_25G_LANE_TX_BIST_UDP_55_48_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x2A)
-#define SERDES_25G_LANE_TX_BIST_UDP_63_56_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x2B)
-#define SERDES_25G_LANE_TX_BIST_UDP_71_64_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x2C)
-#define SERDES_25G_LANE_TX_BIST_UDP_79_72_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x2D)
-#define SERDES_25G_LANE_TX_BIST_UDP_87_80_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x2E)
-#define SERDES_25G_LANE_TX_BIST_UDP_95_88_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x2F)
-#define SERDES_25G_LANE_TX_BIST_UDP_103_96_ADDR		(SERDES_25G_LANE_TX_BIST_BASE + 0x30)
-#define SERDES_25G_LANE_TX_BIST_UDP_111_104_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x31)
-#define SERDES_25G_LANE_TX_BIST_UDP_119_112_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x32)
-#define SERDES_25G_LANE_TX_BIST_UDP_127_120_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x33)
-#define SERDES_25G_LANE_TX_BIST_UDP_135_128_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x34)
-#define SERDES_25G_LANE_TX_BIST_UDP_143_136_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x35)
-#define SERDES_25G_LANE_TX_BIST_UDP_151_144_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x36)
-#define SERDES_25G_LANE_TX_BIST_UDP_159_152_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x37)
-#define SERDES_25G_LANE_TX_BIST_UDP_167_160_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x38)
-#define SERDES_25G_LANE_TX_BIST_UDP_175_168_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x39)
-#define SERDES_25G_LANE_TX_BIST_UDP_183_176_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x3A)
-#define SERDES_25G_LANE_TX_BIST_UDP_191_184_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x3B)
-#define SERDES_25G_LANE_TX_BIST_UDP_199_192_ADDR	(SERDES_25G_LANE_TX_BIST_BASE + 0x3C)
-
-#define SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK				0x01
-#define SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_MASK			0x1E
-#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_SHIFT			1
-
-#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS7			1
-#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS9			2
-#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS11			3
-#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS15			4
-#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS23			5
-#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS31			6
-#define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS_USER			7
-
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL0_MODE_MASK			0x03
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL0_MODE_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL1_TIMER_7_0_MASK		0xFF
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL1_TIMER_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL2_TIMER_15_8_MASK		0xFF
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL2_TIMER_15_8_SHIFT		0
-
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL3_BIT_ERROR_FIELD_7_0_MASK	0xFF
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL3_BIT_ERROR_FIELD_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL4_BIT_ERROR_FIELD_15_8_MASK	0xFF
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL4_BIT_ERROR_FIELD_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL5_BIT_ERROR_FIELD_23_16_MASK	0xFF
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL5_BIT_ERROR_FIELD_23_16_SHIFT	0
-
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL6_BIT_ERROR_FIELD_31_24_MASK	0xFF
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL6_BIT_ERROR_FIELD_31_24_SHIFT	0
-
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL7_BIT_ERROR_FIELD_39_32_MASK	0xFF
-#define SERDES_25G_LANE_TX_BIST_BER_CTRL7_BIT_ERROR_FIELD_39_32_SHIFT	0
-
-#define SERDES_25G_LANE_TX_BIST_SHIFT_AMOUNT_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_SHIFT_AMOUNT_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_7_0_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_7_0_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_15_8_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_15_8_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_23_16_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_23_16_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_31_24_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_31_24_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_39_32_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_39_32_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_47_40_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_47_40_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_55_48_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_55_48_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_63_56_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_63_56_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_71_64_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_71_64_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_79_72_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_79_72_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_87_80_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_87_80_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_95_88_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_95_88_SHIFT				0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_103_96_MASK				0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_103_96_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_111_104_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_111_104_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_119_112_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_119_112_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_127_120_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_127_120_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_135_128_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_135_128_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_143_136_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_143_136_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_151_144_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_151_144_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_159_152_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_159_152_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_167_160_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_167_160_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_175_168_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_175_168_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_183_176_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_183_176_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_191_184_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_191_184_SHIFT			0
-
-#define SERDES_25G_LANE_TX_BIST_UDP_199_192_MASK			0xFF
-#define SERDES_25G_LANE_TX_BIST_UDP_199_192_SHIFT			0
-
-/**********************************  RX BIST **********************************/
-#define SERDES_25G_LANE_RX_BIST_BASE					0x680
-
-#define SERDES_25G_LANE_RX_BIST_CTRL_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x00)
-#define SERDES_25G_LANE_RX_BIST_STATUS_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x04)
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS0_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x08)
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS1_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x09)
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS2_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x0A)
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS4_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x0C)
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS5_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x0D)
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS6_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x0E)
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x14)
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x15)
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x16)
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x17)
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x20)
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x21)
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x22)
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x23)
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x24)
-#define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x30)
-#define SERDES_25G_LANE_RX_BIST_UDP_7_0_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x34)
-#define SERDES_25G_LANE_RX_BIST_UDP_15_8_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x35)
-#define SERDES_25G_LANE_RX_BIST_UDP_23_16_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x36)
-#define SERDES_25G_LANE_RX_BIST_UDP_31_24_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x37)
-#define SERDES_25G_LANE_RX_BIST_UDP_39_32_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x38)
-#define SERDES_25G_LANE_RX_BIST_UDP_47_40_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x39)
-#define SERDES_25G_LANE_RX_BIST_UDP_55_48_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x3A)
-#define SERDES_25G_LANE_RX_BIST_UDP_63_56_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x3B)
-#define SERDES_25G_LANE_RX_BIST_UDP_71_64_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x3C)
-#define SERDES_25G_LANE_RX_BIST_UDP_79_72_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x3D)
-#define SERDES_25G_LANE_RX_BIST_UDP_87_80_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x3E)
-#define SERDES_25G_LANE_RX_BIST_UDP_95_88_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x3F)
-#define SERDES_25G_LANE_RX_BIST_UDP_103_96_ADDR		(SERDES_25G_LANE_RX_BIST_BASE + 0x40)
-#define SERDES_25G_LANE_RX_BIST_UDP_111_104_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x41)
-#define SERDES_25G_LANE_RX_BIST_UDP_119_112_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x42)
-#define SERDES_25G_LANE_RX_BIST_UDP_127_120_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x43)
-#define SERDES_25G_LANE_RX_BIST_UDP_135_128_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x44)
-#define SERDES_25G_LANE_RX_BIST_UDP_143_136_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x45)
-#define SERDES_25G_LANE_RX_BIST_UDP_151_144_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x46)
-#define SERDES_25G_LANE_RX_BIST_UDP_159_152_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x47)
-#define SERDES_25G_LANE_RX_BIST_UDP_167_160_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x48)
-#define SERDES_25G_LANE_RX_BIST_UDP_175_168_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x49)
-#define SERDES_25G_LANE_RX_BIST_UDP_183_176_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x4A)
-#define SERDES_25G_LANE_RX_BIST_UDP_191_184_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x4B)
-#define SERDES_25G_LANE_RX_BIST_UDP_199_192_ADDR	(SERDES_25G_LANE_RX_BIST_BASE + 0x4C)
-
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK				0x01
-#define SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_MASK			0x1E
-#define SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_SHIFT			1
-
-#define SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK			0x20
-#define SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT			5
-
-#define SERDES_25G_LANE_RX_BIST_CTRL_STOP_ERROR_COUNT_MASK		0x40
-#define SERDES_25G_LANE_RX_BIST_CTRL_STOP_ERROR_COUNT_SHIFT		6
-
-#define SERDES_25G_LANE_RX_BIST_CTRL_FORCE_LFSR_WITH_RXDATA_MASK	0x80
-#define SERDES_25G_LANE_RX_BIST_CTRL_FORCE_LFSR_WITH_RXDATA_SHIFT	7
-
-#define SERDES_25G_LANE_RX_BIST_STATUS_STATE_MASK			0x07
-#define SERDES_25G_LANE_RX_BIST_STATUS_STATE_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_STATUS_PATTERN_DET_MASK			0x78
-#define SERDES_25G_LANE_RX_BIST_STATUS_PATTERN_DET_SHIFT		3
-
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS4_CYCLE_COUNT_7_0_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS4_CYCLE_COUNT_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS5_CYCLE_COUNT_15_8_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS5_CYCLE_COUNT_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS6_CYCLE_COUNT_23_16_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_BER_STATUS6_CYCLE_COUNT_23_16_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_NUM_CYCLES_7_0_MASK		0xFF
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_NUM_CYCLES_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_NUM_CYCLES_15_8_MASK		0xFF
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_NUM_CYCLES_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_MAX_ERRORS_7_0_MASK		0xFF
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_MAX_ERRORS_7_0_SHIFT		0
-
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_MAX_ERRORS_15_8_MASK		0xFF
-#define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_MAX_ERRORS_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_NUM_CYCLES_7_0_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_NUM_CYCLES_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_NUM_CYCLES_15_8_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_NUM_CYCLES_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_MIN_ERRORS_7_0_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_MIN_ERRORS_7_0_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_MIN_ERRORS_15_8_MASK	0xFF
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_MIN_ERRORS_15_8_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_MASK	0x01
-#define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT	0
-
-#define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_7_0_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_7_0_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_15_8_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_15_8_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_23_16_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_23_16_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_31_24_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_31_24_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_39_32_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_39_32_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_47_40_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_47_40_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_55_48_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_55_48_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_63_56_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_63_56_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_71_64_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_71_64_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_79_72_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_79_72_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_87_80_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_87_80_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_95_88_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_95_88_SHIFT				0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_103_96_MASK				0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_103_96_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_111_104_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_111_104_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_119_112_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_119_112_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_127_120_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_127_120_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_135_128_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_135_128_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_143_136_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_143_136_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_151_144_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_151_144_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_159_152_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_159_152_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_167_160_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_167_160_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_175_168_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_175_168_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_183_176_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_183_176_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_191_184_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_191_184_SHIFT			0
-
-#define SERDES_25G_LANE_RX_BIST_UDP_199_192_MASK			0xFF
-#define SERDES_25G_LANE_RX_BIST_UDP_199_192_SHIFT			0
-
-/*********************************** FEATURE **********************************/
-#define SERDES_25G_LANE_FEATURE_BASE					0x700
-
-#define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x00)
-#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x04)
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x05)
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x06)
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x07)
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x08)
-#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x09)
-#define SERDES_25G_LANE_FEATURE_ADAPT_CFG_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x0C)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x10)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_ADDR    (SERDES_25G_LANE_FEATURE_BASE + 0x11)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_ADDR    (SERDES_25G_LANE_FEATURE_BASE + 0x12)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_ADDR    (SERDES_25G_LANE_FEATURE_BASE + 0x13)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x14)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_ADDR  (SERDES_25G_LANE_FEATURE_BASE + 0x15)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x16)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x17)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x18)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x19)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x1A)
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x1B)
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x1F)
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x20)
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x21)
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x22)
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_ADDR     (SERDES_25G_LANE_FEATURE_BASE + 0x23)
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x24)
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x25)
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x26)
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x27)
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x28)
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x30)
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x31)
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x32)
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x33)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x40)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x41)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x42)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x43)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x44)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x45)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x46)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x47)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x48)
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_ADDR	     (SERDES_25G_LANE_FEATURE_BASE + 0x49)
-#define SERDES_25G_LANE_FEATURE_TEST_CFG0_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x50)
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG0_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x58)
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG1_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x59)
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG2_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x5A)
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG3_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x5B)
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG4_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x5C)
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG5_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x5D)
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG6_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x5E)
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG7_ADDR		     (SERDES_25G_LANE_FEATURE_BASE + 0x5F)
-/*******************************************************************************
- * masks and shifts
- ******************************************************************************/
-#define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_AC_COUPLED_MASK                          0x01
-#define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_AC_COUPLED_SHIFT                         0
-
-#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_LOS_COMP_EN_MASK                        0x01
-#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_LOS_COMP_EN_SHIFT                       0
-
-#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_AGC_COMP_EN_MASK                        0x02
-#define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_AGC_COMP_EN_SHIFT                       1
-
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_GN_EN_MASK                       0x01
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_GN_EN_SHIFT                      0
-
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ1_EN_MASK                      0x02
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ1_EN_SHIFT                     1
-
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ2_EN_MASK                      0x04
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ2_EN_SHIFT                     2
-
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ3_EN_MASK                      0x08
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ3_EN_SHIFT                     3
-
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ4_EN_MASK                      0x10
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ4_EN_SHIFT                     4
-
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ5_EN_MASK                      0x20
-#define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ5_EN_SHIFT                     5
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMODD_EN_MASK                  0x01
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMODD_EN_SHIFT                 0
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMEVEN_EN_MASK                 0x02
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMEVEN_EN_SHIFT                1
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANODD_EN_MASK                 0x04
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANODD_EN_SHIFT                2
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANEVEN_EN_MASK                0x08
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANEVEN_EN_SHIFT               3
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN1_EN_MASK          0x01
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN1_EN_SHIFT         0
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN0_EN_MASK          0x02
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN0_EN_SHIFT         1
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD1_EN_MASK           0x04
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD1_EN_SHIFT          2
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD0_EN_MASK           0x08
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD0_EN_SHIFT          3
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICEREVEN_EN_MASK           0x10
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICEREVEN_EN_SHIFT          4
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICERODD_EN_MASK            0x20
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICERODD_EN_SHIFT           5
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICEREVEN_EN_MASK            0x40
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICEREVEN_EN_SHIFT           6
-
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICERODD_EN_MASK             0x80
-#define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICERODD_EN_SHIFT            7
-
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_VCO_FREQ_EN_MASK                        0x01
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_VCO_FREQ_EN_SHIFT                       0
-
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL1_EN_MASK                     0x02
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL1_EN_SHIFT                    1
-
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL2_EN_MASK                     0x04
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL2_EN_SHIFT                    2
-
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL3_EN_MASK                     0x08
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL3_EN_SHIFT                    3
-
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL_RESULT_SEL_MASK              0x30
-#define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL_RESULT_SEL_SHIFT             4
-
-#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_REG_EN_MASK                           0x01
-#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_REG_EN_SHIFT                          0
-
-#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_DCD_EN_MASK                           0x02
-#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_DCD_EN_SHIFT                          1
-
-#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TXDP_CLOCK_PHASE_EN_MASK                 0x04
-#define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TXDP_CLOCK_PHASE_EN_SHIFT                2
-
-#define SERDES_25G_LANE_FEATURE_ADAPT_CFG_EYE_MON_MASK                               0x01
-#define SERDES_25G_LANE_FEATURE_ADAPT_CFG_EYE_MON_SHIFT                              0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_MASK               0x03
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_SHIFT              0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_MASK               0x0C
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_SHIFT              2
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE0_MASK                0x30
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE0_SHIFT               4
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE1_MASK                0xC0
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE1_SHIFT               6
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_INTERVAL_7_0_MASK               0xFF
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_INTERVAL_7_0_SHIFT              0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_INTERVAL_15_8_MASK              0xFF
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_INTERVAL_15_8_SHIFT             0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_INTERVAL_23_16_MASK             0xFF
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_INTERVAL_23_16_SHIFT            0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_MASK                     0x01
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_SHIFT                    0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_EIE0_EN_MASK                      0x04
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_EIE0_EN_SHIFT                     2
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_MASK                 0x01
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_SHIFT                0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_EIE0_EN_MASK                  0x04
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_EIE0_EN_SHIFT                 2
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_MASK                    0x03
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_SHIFT                   0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_MASK                    0x0C
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_SHIFT                   2
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE0_SEL_MASK                     0x30
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE0_SEL_SHIFT                    4
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE1_SEL_MASK                     0xC0
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE1_SEL_SHIFT                    6
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_MASK               0x01
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_SHIFT              0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_MASK               0x02
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_SHIFT              1
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_MASK               0x04
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_SHIFT              2
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_MASK               0x08
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_SHIFT              3
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_EDGE_EN_MASK                0x10
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_EDGE_EN_SHIFT               4
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_DATA_EN_MASK                0x20
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_DATA_EN_SHIFT               5
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_EDGE_EN_MASK                0x40
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_EDGE_EN_SHIFT               6
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_DATA_EN_MASK                0x80
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_DATA_EN_SHIFT               7
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_MASK            0x03
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_SHIFT           0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_MASK            0x0C
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_SHIFT           2
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE0_RESULT_SEL_MASK             0x30
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE0_RESULT_SEL_SHIFT            4
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE1_RESULT_SEL_MASK             0xC0
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE1_RESULT_SEL_SHIFT            6
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_EDGE_EN_MASK                0x01
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_EDGE_EN_SHIFT               0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_DATA_EN_MASK                0x02
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_DATA_EN_SHIFT               1
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_RESULT_SEL_MASK             0x0C
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_RESULT_SEL_SHIFT            2
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_MASK                     0x01
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT                    0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_MASK                     0x02
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_SHIFT                    1
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE0_EN_MASK                      0x04
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE0_EN_SHIFT                     2
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE1_EN_MASK                      0x08
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE1_EN_SHIFT                     3
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_CONT_EN_MASK                      0x10
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_CONT_EN_SHIFT                     4
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_AGCLOS_START_VAL_SEL_MASK        0x01
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_AGCLOS_START_VAL_SEL_SHIFT       0
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_PLE_ATT_START_VAL_SEL_MASK       0x02
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_PLE_ATT_START_VAL_SEL_SHIFT      1
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GN_APG_START_VAL_SEL_MASK        0x04
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GN_APG_START_VAL_SEL_SHIFT       2
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_LFG_START_VAL_SEL_MASK        0x08
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_LFG_START_VAL_SEL_SHIFT       3
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GNEQ_CCL_LFG_START_VAL_SEL_MASK  0x10
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GNEQ_CCL_LFG_START_VAL_SEL_SHIFT 4
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_HFG_SQL_START_VAL_SEL_MASK    0x20
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_HFG_SQL_START_VAL_SEL_SHIFT   5
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBF_START_VAL_SEL_MASK        0x40
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBF_START_VAL_SEL_SHIFT       6
-
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBG_START_VAL_SEL_MASK        0x80
-#define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBG_START_VAL_SEL_SHIFT       7
-
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP1_EN_MASK                                 0x01
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP1_EN_SHIFT                                0
-
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP2_EN_MASK                                 0x02
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP2_EN_SHIFT                                1
-
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP3_EN_MASK                                 0x04
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP3_EN_SHIFT                                2
-
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP4_EN_MASK                                 0x08
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP4_EN_SHIFT                                3
-
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP5_EN_MASK                                 0x10
-#define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP5_EN_SHIFT                                4
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_MASK                        0x01
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_SHIFT                       0
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_INTERVAL_7_0_MASK                0xFF
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_INTERVAL_7_0_SHIFT               0
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_INTERVAL_15_8_MASK               0xFF
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_INTERVAL_15_8_SHIFT              0
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_INTERVAL_23_16_MASK              0xFF
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_INTERVAL_23_16_SHIFT             0
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_MASK                 0x01
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_SHIFT                0
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_EIE_EN_MASK                  0x02
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_EIE_EN_SHIFT                 1
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_CONT_EN_MASK                 0x04
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_CONT_EN_SHIFT                2
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_START_VAL_SEL_MASK           0x08
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_START_VAL_SEL_SHIFT          3
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_MASK                 0x01
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_SHIFT                0
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_EIE_EN_MASK                  0x02
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_EIE_EN_SHIFT                 1
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_CONT_EN_MASK                 0x04
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_CONT_EN_SHIFT                2
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_START_VAL_SEL_MASK           0x08
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_START_VAL_SEL_SHIFT          3
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_MASK                 0x01
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_SHIFT                0
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_EIE_EN_MASK                  0x02
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_EIE_EN_SHIFT                 1
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_CONT_EN_MASK                 0x04
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_CONT_EN_SHIFT                2
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_START_VAL_SEL_MASK           0x08
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_START_VAL_SEL_SHIFT          3
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_MASK                 0x01
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_SHIFT                0
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_EIE_EN_MASK                  0x02
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_EIE_EN_SHIFT                 1
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_CONT_EN_MASK                 0x04
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_CONT_EN_SHIFT                2
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_START_VAL_SEL_MASK           0x08
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_START_VAL_SEL_SHIFT          3
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_MASK                 0x01
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_SHIFT                0
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_EIE_EN_MASK                  0x02
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_EIE_EN_SHIFT                 1
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_CONT_EN_MASK                 0x04
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_CONT_EN_SHIFT                2
-
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_START_VAL_SEL_MASK           0x08
-#define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_START_VAL_SEL_SHIFT          3
-
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_EN_MASK                       0x01
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_EN_SHIFT                      0
-
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_TIMEOUT_US_MASK               0xFE
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_TIMEOUT_US_SHIFT              1
-
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_CDR_LOCK_WAIT_TIME_US_MASK              0xFF
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_CDR_LOCK_WAIT_TIME_US_SHIFT             0
-
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_CDR_FREQ_MEASURE_EN_MASK                0x01
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_CDR_FREQ_MEASURE_EN_SHIFT               0
-
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_RXCLKDIV_EN_MASK                        0x01
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_RXCLKDIV_EN_SHIFT                       0
-
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_BIST_HANDSHAKE_EN_MASK                  0x02
-#define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_BIST_HANDSHAKE_EN_SHIFT                 1
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_SIG_DET_MODE_MASK                       0x03
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_SIG_DET_MODE_SHIFT                      0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_LOS_DET_MODE_MASK                       0x0C
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_LOS_DET_MODE_SHIFT                      2
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_SIG_DET_THRESHOLD_MASK                  0xFF
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_SIG_DET_THRESHOLD_SHIFT                 0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_LOS_DET_THRESHOLD_MASK                  0xFF
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_LOS_DET_THRESHOLD_SHIFT                 0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_INTERVAL_7_0_MASK                       0xFF
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_INTERVAL_7_0_SHIFT                      0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_INTERVAL_15_8_MASK                      0xFF
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_INTERVAL_15_8_SHIFT                     0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_SAMPLE_LEN_7_0_MASK                     0xFF
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_SAMPLE_LEN_7_0_SHIFT                    0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_SAMPLE_LEN_11_8_MASK                    0x0F
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_SAMPLE_LEN_11_8_SHIFT                   0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_PLE_ATT_MASK                            0x07
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_PLE_ATT_SHIFT                           0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_EQ_LFG_MASK                             0xF8
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_EQ_LFG_SHIFT                            3
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_GN_APG_MASK                             0x03
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_GN_APG_SHIFT                            0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_HFG_SQL_MASK                            0x7C
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_HFG_SQL_SHIFT                           2
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBF_MASK                                0x0F
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBF_SHIFT                               0
-
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBG_MASK                                0xF0
-#define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBG_SHIFT                               4
-
-#define SERDES_25G_LANE_FEATURE_TEST_CFG0_LANE_MSM_DIS_MASK                          0x01
-#define SERDES_25G_LANE_FEATURE_TEST_CFG0_LANE_MSM_DIS_SHIFT                         0
-
-#define SERDES_25G_LANE_FEATURE_TEST_CFG0_RX_CTRL_DIS_MASK                           0x02
-#define SERDES_25G_LANE_FEATURE_TEST_CFG0_RX_CTRL_DIS_SHIFT                          1
-
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG0_MASK                                      0xFF
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG0_SHIFT                                     0
-
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG1_MASK                                      0xFF
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG1_SHIFT                                     0
-
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG2_MASK                                      0xFF
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG2_SHIFT                                     0
-
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG3_MASK                                      0xFF
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG3_SHIFT                                     0
-
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG4_MASK                                      0xFF
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG4_SHIFT                                     0
-
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG5_MASK                                      0xFF
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG5_SHIFT                                     0
-
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG6_MASK                                      0xFF
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG6_SHIFT                                     0
-
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG7_MASK                                      0xFF
-#define SERDES_25G_LANE_FEATURE_SPARE_CFG7_SHIFT                                     0
-
-#ifdef _cplusplus
-}
-#endif
-
-#endif
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_25g_regs.h b/sys/contrib/alpine-hal/eth/al_hal_serdes_25g_regs.h
deleted file mode 100644
index 64422f7e931f..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_25g_regs.h
+++ /dev/null
@@ -1,434 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2013 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 or V3 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-	  this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-	  notice, this list of conditions and the following disclaimer in
-	  the documentation and/or other materials provided with the
-	  distribution.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_serdes_c_regs.h
- *
- * @brief ... registers
- *
- */
-
-#ifndef __AL_HAL_serdes_c_REGS_H__
-#define __AL_HAL_serdes_c_REGS_H__
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-struct al_serdes_c_gen {
-	/* [0x0] SERDES registers Version */
-	uint32_t version;
-	uint32_t rsrvd_0[3];
-	/* [0x10] SERDES register file address */
-	uint32_t reg_addr;
-	/* [0x14] SERDES register file data */
-	uint32_t reg_data;
-	/* [0x18] SERDES control */
-	uint32_t ctrl;
-	/* [0x1c] SERDES cpu mem address */
-	uint32_t cpu_prog_addr;
-	/* [0x20] SERDES cpu mem data */
-	uint32_t cpu_prog_data;
-	/* [0x24] SERDES data mem address */
-	uint32_t cpu_data_mem_addr;
-	/* [0x28] SERDES data mem data */
-	uint32_t cpu_data_mem_data;
-	/* [0x2c] SERDES control */
-	uint32_t rst;
-	/* [0x30] SERDES control */
-	uint32_t status;
-	uint32_t rsrvd[51];
-};
-struct al_serdes_c_lane {
-	uint32_t rsrvd_0[4];
-	/* [0x10] Data configuration */
-	uint32_t cfg;
-	/* [0x14] Lane status */
-	uint32_t stat;
-	/* [0x18] SERDES control */
-	uint32_t reserved;
-	uint32_t rsrvd[25];
-};
-
-struct al_serdes_c_regs {
-	uint32_t rsrvd_0[64];
-	struct al_serdes_c_gen gen;                             /* [0x100] */
-	struct al_serdes_c_lane lane[2];                        /* [0x200] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** version register ****/
-/*  Revision number (Minor) */
-#define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
-#define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
-/*  Revision number (Major) */
-#define SERDES_C_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
-#define SERDES_C_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
-/*  date of release */
-#define SERDES_C_GEN_VERSION_DATE_DAY_MASK 0x001F0000
-#define SERDES_C_GEN_VERSION_DATE_DAY_SHIFT 16
-/*  month of release */
-#define SERDES_C_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
-#define SERDES_C_GEN_VERSION_DATA_MONTH_SHIFT 21
-/*  year of release (starting from 2000) */
-#define SERDES_C_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
-#define SERDES_C_GEN_VERSION_DATE_YEAR_SHIFT 25
-/*  Reserved */
-#define SERDES_C_GEN_VERSION_RESERVED_MASK 0xC0000000
-#define SERDES_C_GEN_VERSION_RESERVED_SHIFT 30
-
-/**** reg_addr register ****/
-/* address value */
-#define SERDES_C_GEN_REG_ADDR_VAL_MASK   0x00007FFF
-#define SERDES_C_GEN_REG_ADDR_VAL_SHIFT  0
-
-/**** reg_data register ****/
-/* data value */
-#define SERDES_C_GEN_REG_DATA_VAL_MASK   0x000000FF
-#define SERDES_C_GEN_REG_DATA_VAL_SHIFT  0
-/* Bit-wise write enable */
-#define SERDES_C_GEN_REG_DATA_STRB_MASK  0x0000FF00
-#define SERDES_C_GEN_REG_DATA_STRB_SHIFT 8
-
-/**** ctrl register ****/
-/*
- * 0x0 – Select reference clock from Bump
- * 0x1 – Select inter-macro reference clock from the left side
- * 0x2 – Same as 0x0
- * 0x3 – Select inter-macro reference clock from the right side
- */
-#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_MASK 0x00000003
-#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT 0
-
-#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_REF \
-	(0 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
-#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_L2R \
-	(1 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
-#define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_R2L \
-	(3 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
-
-/*
- * 0x0 – Tied to 0 to save power
- * 0x1 – Select reference clock from Bump
- * 0x2 – Select inter-macro reference clock input from right side
- * 0x3 – Same as 0x2
- */
-#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_MASK 0x00000030
-#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT 4
-
-#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_0 \
-	(0 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
-#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_REF \
-	(1 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
-#define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_R2L \
-	(2 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
-
-/*
- * 0x0 – Tied to 0 to save power
- * 0x1 – Select reference clock from Bump
- * 0x2 – Select inter-macro reference clock input from left side
- * 0x3 – Same as 0x2
- */
-#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_MASK 0x000000C0
-#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT 6
-
-#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_0 \
-	(0 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
-#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_REF \
-	(1 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
-#define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_L2R \
-	(2 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
-
-/*
- * Program memory acknowledge -  Only when the access
- * to the program memory is not
- * ready for the microcontroller, it
- * is driven to 0
- */
-#define SERDES_C_GEN_CTRL_CPU_MEMPSACK   (1 << 8)
-/*
- * Data memory acknowledge -  Only when the access
- * to the program memory is not
- * ready for the microcontroller, it
- * is driven to 0
- */
-#define SERDES_C_GEN_CTRL_CPU_MEMACK     (1 << 12)
-/*
- * 0 - keep cpu clk as sb clk
- * 1 – cpu_clk is sb_clk divided by 2
- */
-#define SERDES_C_GEN_CTRL_CPU_CLK_DIV    (1 << 16)
-/*
- * 0x0 – OIF CEI-28G-SR
- * 0x1 – OIF CIE-25G-LR
- * 0x8 – XFI
- * Others – Reserved
- *
- * Note that phy_ctrl_cfg_i[3] is used to signify high-speed/low-speed
- */
-#define SERDES_C_GEN_CTRL_PHY_CTRL_CFG_MASK 0x00F00000
-#define SERDES_C_GEN_CTRL_PHY_CTRL_CFG_SHIFT 20
-/*
- * 0 - Internal 8051 micro- controller is allowed to access the internal APB
- * CSR. Internal APB runs at cpu_clk_i, and the accesses from the external APB
- * in apb_clk_i domain to APB CSR are resynchronized to cpu_clk_i. 1 – Bypass
- * CPU. Internal 8051 micro-controller is blocked from accessing the internal
- * APB CSR. Internal APB runs at apb_clk_i.
- */
-#define SERDES_C_GEN_CTRL_CPU_BYPASS     (1 << 24)
-
-/**** cpu_prog_addr register ****/
-/*
- * address value 32 bit,
- * The firmware data will be 1 byte with 64K rows
- */
-#define SERDES_C_GEN_CPU_PROG_ADDR_VAL_MASK 0x00007FFF
-#define SERDES_C_GEN_CPU_PROG_ADDR_VAL_SHIFT 0
-
-/**** cpu_data_mem_addr register ****/
-/* address value – 8K byte memory */
-#define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_MASK 0x00001FFF
-#define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_SHIFT 0
-
-/**** cpu_data_mem_data register ****/
-/* data value */
-#define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_MASK 0x000000FF
-#define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_SHIFT 0
-
-/**** rst register ****/
-/* Power on reset Signal  – active low */
-#define SERDES_C_GEN_RST_POR_N           (1 << 0)
-/* CMU reset   Active low */
-#define SERDES_C_GEN_RST_CM0_RST_N       (1 << 1)
-/*
- * 0x0 – Normal / Active
- * 0x1 – Partial power down
- * 0x2 – Near complete power down (only
- * refclk buffers and portions of analog bias
- * active)
- * 0x3 – complete power down (IDDQ mode)
- * Can be asserted when CMU is in normal
- * mode.  These modes provide an increased
- * power savings compared to reset mode.
- * Signal is overridden by por_n_i so has no
- * effect in power on reset state.
- */
-#define SERDES_C_GEN_RST_CM0_PD_MASK     0x00000030
-#define SERDES_C_GEN_RST_CM0_PD_SHIFT    4
-/* Lane0 reset signal  active low */
-#define SERDES_C_GEN_RST_LN0_RST_N       (1 << 6)
-/* Lane1 reset signal  active low */
-#define SERDES_C_GEN_RST_LN1_RST_N       (1 << 7)
-/*
- * 0x0 – Normal / Active
- * 0x1 – Partial power down
- * 0x2 – Most blocks powered down (only LOS
- * active)
- * 0x3 – complete power down (IDDQ mode)
- * Can be asserted when Lane is in normal
- * mode.  These modes provide an increased
- * power savings compared to reset mode.
- * Signal is overridden by por_n_i so has no
- * affect in power on reset state
- */
-#define SERDES_C_GEN_RST_LN0_PD_MASK     0x00000300
-#define SERDES_C_GEN_RST_LN0_PD_SHIFT    8
-/*
- * 0x0 – Normal / Active
- * 0x1 – Partial power down
- * 0x2 – Most blocks powered down (only LOS
- * active)
- * 0x3 – complete power down (IDDQ mode)
- * Can be asserted when Lane is in normal
- * mode.  These modes provide an increased
- * power savings compared to reset mode.
- * Signal is overridden by por_n_i so has no
- * affect in power on reset state
- */
-#define SERDES_C_GEN_RST_LN1_PD_MASK     0x00000C00
-#define SERDES_C_GEN_RST_LN1_PD_SHIFT    10
-
-#define SERDES_C_GEN_RST_CPU_MEM_RESET   (1 << 12)
-
-#define SERDES_C_GEN_RST_CPU_MEM_SHUTDOWN (1 << 13)
-
-#define SERDES_C_GEN_RST_CAPRI_APB_RESET (1 << 14)
-
-/**** status register ****/
-/*
- * 0x0 – No error
- * 0x1 – PHY has an internal error
- */
-#define SERDES_C_GEN_STATUS_ERR_O        (1 << 0)
-/*
- * 0x0 – PHY is not ready to respond to
- * cm0_rst_n_i and cm0_pd_i[1:0]. The
- * signals should not be changed.
- * 0x1 - PHY is ready to respond to
- * cm0_rst_n_i and cm0_pd_i[1:0]
- */
-#define SERDES_C_GEN_STATUS_CM0_RST_PD_READY (1 << 1)
-/*
- * Indicates CMU PLL has locked to the
- * reference clock and all output clocks are at
- * the correct frequency
- */
-#define SERDES_C_GEN_STATUS_CM0_OK_O     (1 << 2)
-/*
- * 0x0 – PHY is not ready to respond to
- * ln0_rst_n and ln0_pd[1:0]. The signals
- * should not be changed.
- * 0x1 - PHY is ready to respond to lnX_rst_n_i
- * and lnX_pd_i[1:0]
- */
-#define SERDES_C_GEN_STATUS_LN0_RST_PD_READY (1 << 3)
-/*
- * 0x0 – PHY is not ready to respond to
- * ln1_rst_n_i and ln1_pd[1:0]. The signals
- * should not be changed.
- * 0x1 - PHY is ready to respond to lnX_rst_n_i
- * and lnX_pd_i[1:0]
- */
-#define SERDES_C_GEN_STATUS_LN1_RST_PD_READY (1 << 4)
-/*
- * Active low when the CPU performs a wait cycle (internally or externally
- * generated)
- */
-#define SERDES_C_GEN_STATUS_CPU_WAITSTATE (1 << 5)
-
-#define SERDES_C_GEN_STATUS_TBUS_MASK    0x000FFF00
-#define SERDES_C_GEN_STATUS_TBUS_SHIFT   8
-
-/**** cfg register ****/
-/* 1- Swap 32 bit data on RX side */
-#define SERDES_C_LANE_CFG_RX_LANE_SWAP   (1 << 0)
-/* 1- Swap 32 bit data on TX side */
-#define SERDES_C_LANE_CFG_TX_LANE_SWAP   (1 << 1)
-/* 1 – invert rx data polarity */
-#define SERDES_C_LANE_CFG_LN_CTRL_RXPOLARITY (1 << 2)
-/* 1 – invert tx data polarity */
-#define SERDES_C_LANE_CFG_TX_LANE_POLARITY (1 << 3)
-/*
- * 0x0 –Data on lnX_txdata_o will not be
- * transmitted. Transmitter will be placed into
- * electrical idle.
- * 0x1 – Data on the active bits of
- * lnX_txdata_o will be transmitted
- */
-#define SERDES_C_LANE_CFG_LN_CTRL_TX_EN  (1 << 4)
-/*
- * Informs the PHY to bypass the output of the
- * analog LOS detector and instead rely upon
- * a protocol LOS mechanism in the SoC/ASIC
- * 0x0 – LOS operates as normal
- * 0x1 – Bypass analog LOS output and
- * instead rely upon protocol-level LOS
- * detection via input lnX_ctrl_los_eii_value
- */
-#define SERDES_C_LANE_CFG_LN_CTRL_LOS_EII_EN (1 << 5)
-/*
- * If lnX_ctrl_los_eii_en_i = 1 then Informs
- * the PHY that the received signal was lost
- */
-#define SERDES_C_LANE_CFG_LN_CTRL_LOS_EII_VALUE (1 << 6)
-/* One hot mux */
-#define SERDES_C_LANE_CFG_TX_DATA_SRC_SELECT_MASK 0x00000F00
-#define SERDES_C_LANE_CFG_TX_DATA_SRC_SELECT_SHIFT 8
-/* 0x0 - 20-bit 0x1 – 40-bit */
-#define SERDES_C_LANE_CFG_LN_CTRL_DATA_WIDTH (1 << 12)
-
-/**** stat register ****/
-/*
- * x0 – lane is not ready to send and receive data
- * 0x1 – lane is ready to send and receive data
- */
-#define SERDES_C_LANE_STAT_LNX_STAT_OK   (1 << 0)
-/*
- * 0x0 – received data run length has not
- * exceed the programmable run length
- * detector threshold
- * 0x1 – received data run length has
- * exceeded the programmable run length
- * detector threshold
- */
-#define SERDES_C_LANE_STAT_LN_STAT_RUNLEN_ERR (1 << 1)
-/*
- * 0x0 – data on lnX_rxdata_o are invalid
- * 0x1 – data on the active bits of
- * lnX_rxdata_o are valid
- */
-#define SERDES_C_LANE_STAT_LN_STAT_RXVALID (1 << 2)
-/*
- * Loss of Signal (LOS) indicator that includes
- * the combined functions of the digitally
- * assisted analog LOS, digital LOS, and
- * protocol LOS override features
- * 0x0 – Signal detected on  lnX_rxp_i /
- * lnX_rxm_i pins
- * 0x1 – No signal detected on lnX_rxp_i /
- * lnX_rxm_i pins
- */
-#define SERDES_C_LANE_STAT_LN_STAT_LOS   (1 << 3)
-
-#define SERDES_C_LANE_STAT_LN_STAT_LOS_DEGLITCH (1 << 4)
-
-/**** reserved register ****/
-
-#define SERDES_C_LANE_RESERVED_DEF_0_MASK 0x0000FFFF
-#define SERDES_C_LANE_RESERVED_DEF_0_SHIFT 0
-
-#define SERDES_C_LANE_RESERVED_DEF_1_MASK 0xFFFF0000
-#define SERDES_C_LANE_RESERVED_DEF_1_SHIFT 16
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_serdes_c_REGS_H__ */
-
-/** @} end of ... group */
-
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp.h b/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp.h
deleted file mode 100644
index fe530f6a31be..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_serdes_api API
- * SerDes HAL driver API
- * @ingroup group_serdes SerDes
- * @{
- *
- * @file   al_hal_serdes.h
- *
- * @brief Header file for the SerDes HAL driver
- *
- */
-
-#ifndef __AL_HAL_SERDES_H__
-#define __AL_HAL_SERDES_H__
-
-#include "al_hal_common.h"
-#include "al_hal_serdes_interface.h"
-#include "al_hal_serdes_hssp_regs.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/**
- * Initializes a SERDES group object
- *
- * @param  serdes_regs_base
- *             The SERDES register file base pointer
- *
- * @param obj
- *             An allocated, non initialized object context
- *
- * @return 0 if no error found.
- *
- */
-int al_serdes_hssp_handle_init(
-	void __iomem			*serdes_regs_base,
-	struct al_serdes_grp_obj	*obj);
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-
-/* *INDENT-ON* */
-#endif		/* __AL_SRDS__ */
-
-/** @} end of SERDES group */
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp_internal_regs.h b/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp_internal_regs.h
deleted file mode 100644
index d5b021519942..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp_internal_regs.h
+++ /dev/null
@@ -1,749 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-#ifndef __AL_SERDES_INTERNAL_REGS_H__
-#define  __AL_SERDES_INTERNAL_REGS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*******************************************************************************
- * Per lane register fields
- ******************************************************************************/
-/*
- * RX and TX lane hard reset
- * 0 - Hard reset is asserted
- * 1 - Hard reset is de-asserted
- */
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM			2
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK			0x01
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT		0x00
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT		0x01
-
-/*
- * RX and TX lane hard reset control
- * 0 - Hard reset is taken from the interface pins
- * 1 - Hard reset is taken from registers
- */
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM		2
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK			0x02
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_IFACE		0x00
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS		0x02
-
-/* RX lane power state control */
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM			3
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK				0x1f
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD				0x01
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2				0x02
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1				0x04
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S			0x08
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0				0x10
-
-/* TX lane power state control */
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM			4
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK				0x1f
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD				0x01
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2				0x02
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1				0x04
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S			0x08
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0				0x10
-
-/* RX lane word width */
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM				5
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK				0x07
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_8				0x00
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_10				0x01
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_16				0x02
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20				0x03
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_32				0x04
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_40				0x05
-
-/* TX lane word width */
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM				5
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK				0x70
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_8				0x00
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_10				0x10
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_16				0x20
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20				0x30
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_32				0x40
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_40				0x50
-
-/* RX lane rate select */
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM				6
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_MASK				0x07
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8				0x00
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4				0x01
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2				0x02
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1				0x03
-
-/* TX lane rate select */
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM				6
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_MASK				0x70
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8				0x00
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4				0x10
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2				0x20
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1				0x30
-
-/*
- * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
- * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
- * partial equalized RX signal out the transmit IO pins
- */
-#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM			7
-#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN				0x10
-
-/*
- * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
- * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
- * the TX serializer output into the CDR
- */
-#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM			7
-#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN				0x20
-
-/*
- * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
- * RX pads). Serial IO loopback from the transmit lane IO pins to the receive
- * lane IO pins: 0 - Disables loopback 1 - Loops back the driver IO signal to
- * the RX IO pins
- */
-#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM			7
-#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN				0x40
-
-/*
- * PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA
- * receive lane 20-bit data ports, to the transmit lane 20-bit data ports 0 -
- * Disables loopback 1 - Loops back the 20-bit receive data port to the
- * transmitter
- */
-#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM			7
-#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN				0x80
-
-/*
- * PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1.
- * Transmit bit clock select: 0 - Selects synthesizer bit clock for transmit 1
- * - Selects CDR clock for transmit
- */
-#define SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM				7
-#define SERDES_IREG_FLD_LB_CDRCLK2TXEN					0x01
-
-/* Receive lane BIST enable. Active High */
-#define SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM				8
-#define SERDES_IREG_FLD_PCSRXBIST_EN					0x01
-
-/* TX lane BIST enable. Active High */
-#define SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM				8
-#define SERDES_IREG_FLD_PCSTXBIST_EN					0x02
-
-/*
- * RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates
- * the test has completed, and will remain high until a new test is initiated
- */
-#define SERDES_IREG_FLD_RXBIST_DONE_REG_NUM				8
-#define SERDES_IREG_FLD_RXBIST_DONE					0x04
-
-/*
- * RX BIST error count overflow indicator. Indicates an overflow in the number
- * of byte errors identified during the course of the test. This word is stable
- * to sample when *_DONE_* signal has asserted
- */
-#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM		8
-#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW			0x08
-
-/*
- * RX BIST locked indicator 0 - Indicates BIST is not word locked and error
- * comparisons have not begun yet 1 - Indicates BIST is word locked and error
- * comparisons have begun
- */
-#define SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM				8
-#define SERDES_IREG_FLD_RXBIST_RXLOCKED					0x10
-
-/*
- * RX BIST error count word. Indicates the number of byte errors identified
- * during the course of the test. This word is stable to sample when *_DONE_*
- * signal has asserted
- */
-#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM			9
-#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM			10
-
-/* Tx params */
-#define SERDES_IREG_TX_DRV_1_REG_NUM					21
-#define SERDES_IREG_TX_DRV_1_HLEV_MASK					0x7
-#define SERDES_IREG_TX_DRV_1_HLEV_SHIFT					0
-#define SERDES_IREG_TX_DRV_1_LEVN_MASK					0xf8
-#define SERDES_IREG_TX_DRV_1_LEVN_SHIFT					3
-
-#define SERDES_IREG_TX_DRV_2_REG_NUM					22
-#define SERDES_IREG_TX_DRV_2_LEVNM1_MASK				0xf
-#define SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT				0
-#define SERDES_IREG_TX_DRV_2_LEVNM2_MASK				0x30
-#define SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT				4
-
-#define SERDES_IREG_TX_DRV_3_REG_NUM					23
-#define SERDES_IREG_TX_DRV_3_LEVNP1_MASK				0x7
-#define SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT				0
-#define SERDES_IREG_TX_DRV_3_SLEW_MASK					0x18
-#define SERDES_IREG_TX_DRV_3_SLEW_SHIFT					3
-
-/* Rx params */
-#define SERDES_IREG_RX_CALEQ_1_REG_NUM					24
-#define SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK				0x7
-#define SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT				0
-/* DFE post-shaping tap 3dB frequency */
-#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK				0x38
-#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT			3
-
-#define SERDES_IREG_RX_CALEQ_2_REG_NUM					25
-/* DFE post-shaping tap gain */
-#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK			0x7
-#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT			0
-/* DFE first tap gain control */
-#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK				0x78
-#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT			3
-
-#define SERDES_IREG_RX_CALEQ_3_REG_NUM					26
-#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK				0xf
-#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT			0
-#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK				0xf0
-#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT			4
-
-#define SERDES_IREG_RX_CALEQ_4_REG_NUM					27
-#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK				0xf
-#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT			0
-#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK			0x70
-#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT			4
-
-#define SERDES_IREG_RX_CALEQ_5_REG_NUM					28
-#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK			0x7
-#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT			0
-#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK			0xf8
-#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT			3
-
-/* RX lane best eye point measurement result */
-#define SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM			29
-#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM			30
-#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK				0x3F
-
-/*
- * Adaptive RX Equalization enable
- * 0 - Disables adaptive RX equalization.
- * 1 - Enables adaptive RX equalization.
- */
-#define SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM				31
-#define SERDES_IREG_FLD_PCSRXEQ_START					(1 << 0)
-
-/*
- * Enables an eye diagram measurement
- * within the PHY.
- * 0 - Disables eye diagram measurement
- * 1 - Enables eye diagram measurement
- */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM			31
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START				(1 << 1)
-
-
-/*
- * RX lane single roam eye point measurement start signal.
- * If asserted, single measurement at fix XADJUST and YADJUST is started.
- */
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM		31
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START		(1 << 2)
-
-
-/*
- * PHY Eye diagram measurement status
- * signal
- * 0 - Indicates eye diagram results are not
- * valid for sampling
- * 1 - Indicates eye diagram is complete and
- * results are valid for sampling
- */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM			32
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE				(1 << 0)
-
-/*
- * Eye diagram error signal. Indicates if the
- * measurement was invalid because the eye
- * diagram was interrupted by the link entering
- * electrical idle.
- * 0 - Indicates eye diagram is valid
- * 1- Indicates an error occurred, and the eye
- * diagram measurement should be re-run
- */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR_REG_NUM			32
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR				(1 << 1)
-
-/*
- * PHY Adaptive Equalization status
- * 0 - Indicates Adaptive Equalization results are not valid for sampling
- * 1 - Indicates Adaptive Equalization is complete and results are valid for
- *     sampling
- */
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM			32
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE				(1 << 2)
-
-/*
- *
- * PHY Adaptive Equalization Status Signal
- * 0 – Indicates adaptive equalization results
- * are not valid for sampling
- * 1 – Indicates adaptive equalization is
- * complete and results are valid for sampling.
- */
-#define SERDES_IREG_FLD_RXEQ_DONE_REG_NUM				32
-#define SERDES_IREG_FLD_RXEQ_DONE					(1 << 3)
-
-
-/*
- * 7-bit eye diagram time adjust control
- * - 6-bits per UI
- * - spans 2 UI
- */
-#define SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM			33
-
-/* 6-bit eye diagram voltage adjust control - spans +/-300mVdiff */
-#define SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM			34
-
-/*
- * Eye diagram status signal. Safe for
- * sampling when *DONE* signal has
- * asserted
- * 14'h0000 - Completely Closed Eye
- * 14'hFFFF - Completely Open Eye
- */
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM		35
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_MAKE			0xFF
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_SHIFT		0
-
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM		36
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE			0x3F
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_SHIFT		0
-
-/*
- * RX lane single roam eye point measurement result.
- * If 0, eye is open at current XADJUST and YADJUST settings.
- */
-#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM		37
-#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM		38
-
-/*
- * Override enable for CDR lock to reference clock
- * 0 - CDR is always locked to reference
- * 1 - CDR operation mode (Lock2Reference or Lock2data are controlled internally
- *     depending on the incoming signal and ppm status)
- */
-#define SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM			39
-#define SERDES_IREG_FLD_RXLOCK2REF_OVREN				(1 << 1)
-
-/*
- * Selects Eye to capture based on edge
- * 0 - Capture 1st Eye in Eye Diagram
- * 1 - Capture 2nd Eye in Eye Diagram measurement
- */
-#define SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM			39
-#define SERDES_IREG_FLD_RXROAM_XORBITSEL				(1 << 2)
-#define SERDES_IREG_FLD_RXROAM_XORBITSEL_1ST				0
-#define SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND				(1 << 2)
-
-/*
- * RX Signal detect. 0 indicates no signal, 1 indicates signal detected.
- */
-#define SERDES_IREG_FLD_RXRANDET_REG_NUM				41
-#define SERDES_IREG_FLD_RXRANDET_STAT					0x20
-
-/*
- * RX data polarity inversion control:
- * 1'b0: no inversion
- * 1'b1: invert polarity
- */
-#define SERDES_IREG_FLD_POLARITY_RX_REG_NUM				46
-#define SERDES_IREG_FLD_POLARITY_RX_INV					(1 << 0)
-
-/*
- * TX data polarity inversion control:
- * 1'b0: no inversion
- * 1'b1: invert polarity
- */
-#define SERDES_IREG_FLD_POLARITY_TX_REG_NUM				46
-#define SERDES_IREG_FLD_POLARITY_TX_INV					(1 << 1)
-
-/* LANEPCSPSTATE* override enable (Active low) */
-#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM			85
-#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN				(1 << 0)
-
-/* LB* override enable (Active low) */
-#define SERDES_IREG_FLD_LB_LOCWREN_REG_NUM				85
-#define SERDES_IREG_FLD_LB_LOCWREN					(1 << 1)
-
-/* PCSRX* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM				85
-#define SERDES_IREG_FLD_PCSRX_LOCWREN					(1 << 4)
-
-/* PCSRXBIST* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM			85
-#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN				(1 << 5)
-
-/* PCSRXEQ* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM				85
-#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN					(1 << 6)
-
-/* PCSTX* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM				85
-#define SERDES_IREG_FLD_PCSTX_LOCWREN					(1 << 7)
-
-/*
- * group registers:
- * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN,
- * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN
- * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
- */
-#define SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM				86
-
-/* PCSTXBIST* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM			86
-#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN				(1 << 0)
-
-/* Override RX_CALCEQ through the internal registers (Active low) */
-#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM			86
-#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN				(1 << 3)
-
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM		86
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN			(1 << 4)
-
-
-/* RXCALROAMEYEMEASIN* override enable - Active Low */
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM		86
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN			(1 << 6)
-
-/* RXCALROAMXADJUST* override enable - Active Low */
-#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM		86
-#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN			(1 << 7)
-
-/* RXCALROAMYADJUST* override enable - Active Low */
-#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM		87
-#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN			(1 << 0)
-
-/* RXCDRCALFOSC* override enable. Active Low */
-#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN_REG_NUM			87
-#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN				(1 << 1)
-
-/* Over-write enable for RXEYEDIAGFSM_INITXVAL */
-#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN_REG_NUM			87
-#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN				(1 << 2)
-
-/* Over-write enable for CMNCLKGENMUXSEL_TXINTERNAL */
-#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN_REG_NUM			87
-#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN				(1 << 3)
-
-/* TXCALTCLKDUTY* override enable. Active Low */
-#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN_REG_NUM			87
-#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN				(1 << 4)
-
-/* Override TX_DRV through the internal registers (Active low) */
-#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM			87
-#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN				(1 << 5)
-
-/*******************************************************************************
- * Common lane register fields - PMA
- ******************************************************************************/
-/*
- * Common lane hard reset control
- * 0 - Hard reset is taken from the interface pins
- * 1 - Hard reset is taken from registers
- */
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM		2
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK		0x01
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_IFACE	0x00
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS	0x01
-
-/*
- * Common lane hard reset
- * 0 - Hard reset is asserted
- * 1 - Hard reset is de-asserted
- */
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM		2
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK		0x02
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT	0x00
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT	0x02
-
-/* Synth power state control */
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM			3
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK				0x1f
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD			0x01
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2			0x02
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1			0x04
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S			0x08
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0			0x10
-
-/* Transmit datapath FIFO enable (Active High) */
-#define SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM				8
-#define SERDES_IREG_FLD_CMNPCS_TXENABLE					(1 << 2)
-
-/*
- * RX lost of signal detector enable
- * - 0 - disable
- * - 1 - enable
- */
-#define SERDES_IREG_FLD_RXLOSDET_ENABLE_REG_NUM				13
-#define SERDES_IREG_FLD_RXLOSDET_ENABLE					AL_BIT(4)
-
-/* Signal Detect Threshold Level */
-#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_REG_NUM			15
-#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK			AL_FIELD_MASK(2, 0)
-
-/* LOS Detect Threshold Level */
-#define SERDES_IREG_FLD_RXLOSDET_THRESH_REG_NUM				15
-#define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK				AL_FIELD_MASK(4, 3)
-#define SERDES_IREG_FLD_RXLOSDET_THRESH_SHIFT				3
-
-#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM			30
-#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK			0x7f
-#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM			31
-#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK				0x7f
-#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM			32
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK			0xff
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM			33
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK			0x1
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM			33
-#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK				0x3e
-#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT				1
-
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM			34
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK			0xff
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM			35
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK			0x1
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM				35
-#define SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK				0x3e
-#define SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT				1
-
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM			36
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK			0xff
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM			37
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK			0x7
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_REG_NUM			43
-#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_MASK				0x7
-#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_SHIFT				0
-
-#define SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(byte_num)			(56 + (byte_num))
-#define SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES				10
-
-/*
- * Selects the transmit BIST mode:
- * 0 - Uses the 80-bit internal memory pattern (w/ OOB)
- * 1 - Uses a 27 PRBS pattern
- * 2 - Uses a 223 PRBS pattern
- * 3 - Uses a 231 PRBS pattern
- * 4 - Uses a 1010 clock pattern
- * 5 and above - Reserved
- */
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM			80
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK				0x07
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER			0x00
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7			0x01
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23			0x02
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31			0x03
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010			0x04
-
-/* Single-Bit error injection enable (on posedge) */
-#define SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM			80
-#define SERDES_IREG_FLD_TXBIST_BITERROR_EN				0x20
-
-/* CMNPCIEGEN3* override enable (Active Low) */
-#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM			95
-#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN				(1 << 2)
-
-/* CMNPCS* override enable (Active Low) */
-#define SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM				95
-#define SERDES_IREG_FLD_CMNPCS_LOCWREN					(1 << 3)
-
-/* CMNPCSBIST* override enable (Active Low) */
-#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM			95
-#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN				(1 << 4)
-
-/* CMNPCSPSTATE* override enable (Active Low) */
-#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM			95
-#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN				(1 << 5)
-
-/*  PCS_EN* override enable (Active Low) */
-#define SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM				96
-#define SERDES_IREG_FLD_PCS_LOCWREN					(1 << 3)
-
-/* Eye diagram sample count */
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM			150
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK			0xff
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT			0
-
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM			151
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK			0xff
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT			0
-
-/* override control */
-#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM			230
-#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN				1 << 0
-
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM		623
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK		0xff
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT		0
-
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM		624
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK		0xff
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT		0
-
-/* X and Y coefficient return value */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM		626
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_MASK			0x0F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_SHIFT		0
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_MASK			0xF0
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_SHIFT		4
-
-/* X coarse scan step */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM		627
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK			0x7F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT		0
-
-/* X fine scan step */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM		628
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK			0x7F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT			0
-
-/* Y coarse scan step */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM		629
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK			0x0F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT		0
-
-/* Y fine scan step */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM		630
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK			0x0F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT			0
-
-#define SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM				157
-
-#define SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM				158
-
-#define SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM				159
-
-#define SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM				160
-
-#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM			163
-
-#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM			164
-
-/*******************************************************************************
- * Common lane register fields - PCS
- ******************************************************************************/
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM			3
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK			AL_FIELD_MASK(5, 4)
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT			4
-
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM			6
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA				AL_BIT(2)
-
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM			18
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK			0x1F
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM			19
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK			0x7C
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT			2
-
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM		20
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK		0x1F
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT		0
-
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM		21
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK		0x7C
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT		2
-
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_REG_NUM		22
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_MASK			0x7f
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_REG_NUM			34
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_MASK			0x7f
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_REG_NUM		23
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_MASK			0xff
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_REG_NUM		22
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_MASK			0x80
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_SHIFT			7
-
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_REG_NUM			24
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_MASK			0x3e
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_SHIFT			1
-
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_REG_NUM			35
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_MASK			0xff
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_REG_NUM			34
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_MASK			0x80
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_SHIFT			7
-
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_REG_NUM			36
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_MASK				0x1f
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_REG_NUM			37
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_MASK			0xff
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_REG_NUM		36
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_MASK			0xe0
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_SHIFT			5
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_serdes_REG_H */
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp_regs.h b/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp_regs.h
deleted file mode 100644
index 20f6cbfa0206..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_hssp_regs.h
+++ /dev/null
@@ -1,494 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_serdes_regs.h
- *
- * @brief ... registers
- *
- */
-
-#ifndef __AL_HAL_SERDES_REGS_H__
-#define __AL_HAL_SERDES_REGS_H__
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-struct serdes_gen {
-	/* [0x0] SerDes Registers Version */
-	uint32_t version;
-	uint32_t rsrvd_0[3];
-	/* [0x10] SerDes register file address */
-	uint32_t reg_addr;
-	/* [0x14] SerDes register file data */
-	uint32_t reg_data;
-	uint32_t rsrvd_1[2];
-	/* [0x20] SerDes control */
-	uint32_t ictl_multi_bist;
-	/* [0x24] SerDes control */
-	uint32_t ictl_pcs;
-	/* [0x28] SerDes control */
-	uint32_t ictl_pma;
-	uint32_t rsrvd_2;
-	/* [0x30] SerDes control */
-	uint32_t ipd_multi_synth;
-	/* [0x34] SerDes control */
-	uint32_t irst;
-	/* [0x38] SerDes control */
-	uint32_t octl_multi_synthready;
-	/* [0x3c] SerDes control */
-	uint32_t octl_multi_synthstatus;
-	/* [0x40] SerDes control */
-	uint32_t clk_out;
-	uint32_t rsrvd[47];
-};
-struct serdes_lane {
-	uint32_t rsrvd1[4];
-	/* [0x10] SerDes status */
-	uint32_t octl_pma;
-	/* [0x14] SerDes control */
-	uint32_t ictl_multi_andme;
-	/* [0x18] SerDes control */
-	uint32_t ictl_multi_lb;
-	/* [0x1c] SerDes control */
-	uint32_t ictl_multi_rxbist;
-	/* [0x20] SerDes control */
-	uint32_t ictl_multi_txbist;
-	/* [0x24] SerDes control */
-	uint32_t ictl_multi;
-	/* [0x28] SerDes control */
-	uint32_t ictl_multi_rxeq;
-	/* [0x2c] SerDes control */
-	uint32_t ictl_multi_rxeq_l_low;
-	/* [0x30] SerDes control */
-	uint32_t ictl_multi_rxeq_l_high;
-	/* [0x34] SerDes control */
-	uint32_t ictl_multi_rxeyediag;
-	/* [0x38] SerDes control */
-	uint32_t ictl_multi_txdeemph;
-	/* [0x3c] SerDes control */
-	uint32_t ictl_multi_txmargin;
-	/* [0x40] SerDes control */
-	uint32_t ictl_multi_txswing;
-	/* [0x44] SerDes control */
-	uint32_t idat_multi;
-	/* [0x48] SerDes control */
-	uint32_t ipd_multi;
-	/* [0x4c] SerDes control */
-	uint32_t octl_multi_rxbist;
-	/* [0x50] SerDes control */
-	uint32_t octl_multi;
-	/* [0x54] SerDes control */
-	uint32_t octl_multi_rxeyediag;
-	/* [0x58] SerDes control */
-	uint32_t odat_multi_rxbist;
-	/* [0x5c] SerDes control */
-	uint32_t odat_multi_rxeq;
-	/* [0x60] SerDes control */
-	uint32_t multi_rx_dvalid;
-	/* [0x64] SerDes control */
-	uint32_t reserved;
-	uint32_t rsrvd[6];
-};
-
-struct al_serdes_regs {
-	uint32_t rsrvd_0[64];
-	struct serdes_gen gen;                               /* [0x100] */
-	struct serdes_lane lane[4];                          /* [0x200] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** version register ****/
-/*  Revision number (Minor) */
-#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
-#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
-/*  Revision number (Major) */
-#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
-#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
-/*  Date of release */
-#define SERDES_GEN_VERSION_DATE_DAY_MASK 0x001F0000
-#define SERDES_GEN_VERSION_DATE_DAY_SHIFT 16
-/*  Month of release */
-#define SERDES_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
-#define SERDES_GEN_VERSION_DATA_MONTH_SHIFT 21
-/* Year of release (starting from 2000) */
-#define SERDES_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
-#define SERDES_GEN_VERSION_DATE_YEAR_SHIFT 25
-/*  Reserved */
-#define SERDES_GEN_VERSION_RESERVED_MASK 0xC0000000
-#define SERDES_GEN_VERSION_RESERVED_SHIFT 30
-
-/**** reg_addr register ****/
-/* Address value */
-#define SERDES_GEN_REG_ADDR_VAL_MASK     0x0000FFFF
-#define SERDES_GEN_REG_ADDR_VAL_SHIFT    0
-
-/**** reg_data register ****/
-/* Data value */
-#define SERDES_GEN_REG_DATA_VAL_MASK     0x000000FF
-#define SERDES_GEN_REG_DATA_VAL_SHIFT    0
-
-/**** ICTL_MULTI_BIST register ****/
-
-#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_MASK 0x00000007
-#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_SHIFT 0
-
-/**** ICTL_PCS register ****/
-
-#define SERDES_GEN_ICTL_PCS_EN_NT        (1 << 0)
-
-/**** ICTL_PMA register ****/
-
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_MASK 0x00000007
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT 0
-
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_REF \
-	(0 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_R2L \
-	(3 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_L2R \
-	(4 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
-
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_MASK 0x00000070
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT 4
-
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_0 \
-	(0 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_REF \
-	(2 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_R2L \
-	(3 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
-
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_MASK 0x00000700
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT 8
-
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_0 \
-	(0 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_REF \
-	(2 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_L2R \
-	(3 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
-
-#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC		(1 << 11)
-#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_THIS		(0 << 11)
-#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_MASTER	(1 << 11)
-
-#define SERDES_GEN_ICTL_PMA_TXENABLE_A   (1 << 12)
-
-#define SERDES_GEN_ICTL_PMA_SYNTHCKBYPASSEN_NT (1 << 13)
-
-/**** IPD_MULTI_SYNTH register ****/
-
-#define SERDES_GEN_IPD_MULTI_SYNTH_B     (1 << 0)
-
-/**** IRST register ****/
-
-#define SERDES_GEN_IRST_PIPE_RST_L3_B_A  (1 << 0)
-
-#define SERDES_GEN_IRST_PIPE_RST_L2_B_A  (1 << 1)
-
-#define SERDES_GEN_IRST_PIPE_RST_L1_B_A  (1 << 2)
-
-#define SERDES_GEN_IRST_PIPE_RST_L0_B_A  (1 << 3)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A (1 << 4)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A (1 << 5)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A (1 << 6)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A (1 << 7)
-
-#define SERDES_GEN_IRST_MULTI_HARD_SYNTH_B_A (1 << 8)
-
-#define SERDES_GEN_IRST_POR_B_A          (1 << 12)
-
-#define SERDES_GEN_IRST_PIPE_RST_L3_B_A_SEL (1 << 16)
-
-#define SERDES_GEN_IRST_PIPE_RST_L2_B_A_SEL (1 << 17)
-
-#define SERDES_GEN_IRST_PIPE_RST_L1_B_A_SEL (1 << 18)
-
-#define SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL (1 << 19)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A_SEL (1 << 20)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A_SEL (1 << 21)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A_SEL (1 << 22)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A_SEL (1 << 23)
-
-/**** OCTL_MULTI_SYNTHREADY register ****/
-
-#define SERDES_GEN_OCTL_MULTI_SYNTHREADY_A (1 << 0)
-
-/**** OCTL_MULTI_SYNTHSTATUS register ****/
-
-#define SERDES_GEN_OCTL_MULTI_SYNTHSTATUS_A (1 << 0)
-
-/**** clk_out register ****/
-
-#define SERDES_GEN_CLK_OUT_SEL_MASK      0x0000003F
-#define SERDES_GEN_CLK_OUT_SEL_SHIFT     0
-
-/**** OCTL_PMA register ****/
-
-#define SERDES_LANE_OCTL_PMA_TXSTATUS_L_A (1 << 0)
-
-/**** ICTL_MULTI_ANDME register ****/
-
-#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A (1 << 0)
-
-#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A_SEL (1 << 1)
-
-/**** ICTL_MULTI_LB register ****/
-
-#define SERDES_LANE_ICTL_MULTI_LB_TX2RXIOTIMEDEN_L_NT (1 << 0)
-
-#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT (1 << 1)
-
-#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT (1 << 2)
-
-#define SERDES_LANE_ICTL_MULTI_LB_PARRX2TXTIMEDEN_L_NT (1 << 3)
-
-#define SERDES_LANE_ICTL_MULTI_LB_CDRCLK2TXEN_L_NT (1 << 4)
-
-#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT_SEL (1 << 8)
-
-#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT_SEL (1 << 9)
-
-/**** ICTL_MULTI_RXBIST register ****/
-
-#define SERDES_LANE_ICTL_MULTI_RXBIST_EN_L_A (1 << 0)
-
-/**** ICTL_MULTI_TXBIST register ****/
-
-#define SERDES_LANE_ICTL_MULTI_TXBIST_EN_L_A (1 << 0)
-
-/**** ICTL_MULTI register ****/
-
-#define SERDES_LANE_ICTL_MULTI_PSTATE_L_MASK 0x00000003
-#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SHIFT 0
-
-#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SEL (1 << 2)
-
-#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_MASK 0x00000070
-#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_SHIFT 4
-
-#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATAEN_L_A (1 << 8)
-
-#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATA_L_A (1 << 9)
-
-#define SERDES_LANE_ICTL_MULTI_TXBEACON_L_A (1 << 12)
-
-#define SERDES_LANE_ICTL_MULTI_TXDETECTRXREQ_L_A (1 << 13)
-
-#define SERDES_LANE_ICTL_MULTI_RXRATE_L_MASK 0x00070000
-#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SHIFT 16
-
-#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SEL (1 << 19)
-
-#define SERDES_LANE_ICTL_MULTI_TXRATE_L_MASK 0x00700000
-#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SHIFT 20
-
-#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SEL (1 << 23)
-
-#define SERDES_LANE_ICTL_MULTI_TXAMP_L_MASK 0x07000000
-#define SERDES_LANE_ICTL_MULTI_TXAMP_L_SHIFT 24
-
-#define SERDES_LANE_ICTL_MULTI_TXAMP_EN_L (1 << 27)
-
-#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_MASK 0x70000000
-#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_SHIFT 28
-
-/**** ICTL_MULTI_RXEQ register ****/
-
-#define SERDES_LANE_ICTL_MULTI_RXEQ_EN_L (1 << 0)
-
-#define SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A (1 << 1)
-
-#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_MASK 0x00000070
-#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_SHIFT 4
-
-/**** ICTL_MULTI_RXEQ_L_high register ****/
-
-#define SERDES_LANE_ICTL_MULTI_RXEQ_L_HIGH_VAL (1 << 0)
-
-/**** ICTL_MULTI_RXEYEDIAG register ****/
-
-#define SERDES_LANE_ICTL_MULTI_RXEYEDIAG_START_L_A (1 << 0)
-
-/**** ICTL_MULTI_TXDEEMPH register ****/
-
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_MASK 0x0003FFFF
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_SHIFT 0
-
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_MASK	0x7c0
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_SHIFT	6
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_MASK	0xf000
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_SHIFT	12
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_MASK	0x7
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_SHIFT	0
-
-/**** ICTL_MULTI_TXMARGIN register ****/
-
-#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_MASK 0x00000007
-#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_SHIFT 0
-
-/**** ICTL_MULTI_TXSWING register ****/
-
-#define SERDES_LANE_ICTL_MULTI_TXSWING_L (1 << 0)
-
-/**** IDAT_MULTI register ****/
-
-#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_MASK 0x0000000F
-#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SHIFT 0
-
-#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SEL (1 << 4)
-
-/**** IPD_MULTI register ****/
-
-#define SERDES_LANE_IPD_MULTI_TX_L_B     (1 << 0)
-
-#define SERDES_LANE_IPD_MULTI_RX_L_B     (1 << 1)
-
-/**** OCTL_MULTI_RXBIST register ****/
-
-#define SERDES_LANE_OCTL_MULTI_RXBIST_DONE_L_A (1 << 0)
-
-#define SERDES_LANE_OCTL_MULTI_RXBIST_RXLOCKED_L_A (1 << 1)
-
-/**** OCTL_MULTI register ****/
-
-#define SERDES_LANE_OCTL_MULTI_RXCDRLOCK2DATA_L_A (1 << 0)
-
-#define SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A (1 << 1)
-
-#define SERDES_LANE_OCTL_MULTI_RXREADY_L_A (1 << 2)
-
-#define SERDES_LANE_OCTL_MULTI_RXSTATUS_L_A (1 << 3)
-
-#define SERDES_LANE_OCTL_MULTI_TXREADY_L_A (1 << 4)
-
-#define SERDES_LANE_OCTL_MULTI_TXDETECTRXSTAT_L_A (1 << 5)
-
-#define SERDES_LANE_OCTL_MULTI_TXDETECTRXACK_L_A (1 << 6)
-
-#define SERDES_LANE_OCTL_MULTI_RXSIGNALDETECT_L_A (1 << 7)
-
-/**** OCTL_MULTI_RXEYEDIAG register ****/
-
-#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_MASK 0x00003FFF
-#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_SHIFT 0
-
-#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_DONE_L_A (1 << 16)
-
-#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_ERR_L_A (1 << 17)
-
-/**** ODAT_MULTI_RXBIST register ****/
-
-#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_MASK 0x0000FFFF
-#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_SHIFT 0
-
-#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_OVERFLOW_L_A (1 << 16)
-
-/**** ODAT_MULTI_RXEQ register ****/
-
-#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_MASK 0x00003FFF
-#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_SHIFT 0
-
-/**** MULTI_RX_DVALID register ****/
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_CDR_LOCK (1 << 0)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_SIGNALDETECT (1 << 1)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_TX_READY (1 << 2)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_READY (1 << 3)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_SYNT_READY (1 << 4)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_ELECIDLE (1 << 5)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_MASK 0x00FF0000
-#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_SHIFT 16
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_00_SEL (1 << 24)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_00_VAL (1 << 25)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_01_SEL (1 << 26)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_01_VAL (1 << 27)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_10_SEL (1 << 28)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_10_VAL (1 << 29)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_11_SEL (1 << 30)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_11_VAL (1 << 31)
-
-/**** reserved register ****/
-
-#define SERDES_LANE_RESERVED_OUT_MASK    0x000000FF
-#define SERDES_LANE_RESERVED_OUT_SHIFT   0
-
-#define SERDES_LANE_RESERVED_IN_MASK     0x00FF0000
-#define SERDES_LANE_RESERVED_IN_SHIFT    16
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_serdes_REGS_H__ */
-
-/** @} end of ... group */
-
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_interface.h b/sys/contrib/alpine-hal/eth/al_hal_serdes_interface.h
deleted file mode 100644
index c41e6c30b69a..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_interface.h
+++ /dev/null
@@ -1,875 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_serdes_api API
- * SerDes HAL driver API
- * @ingroup group_serdes SerDes
- * @{
- *
- * @file   al_hal_serdes_interface.h
- *
- * @brief Header file for the SerDes HAL driver
- *
- */
-
-#ifndef __AL_HAL_SERDES_INTERFACE_H__
-#define __AL_HAL_SERDES_INTERFACE_H__
-
-#include "al_hal_common.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-enum al_serdes_type {
-	AL_SRDS_TYPE_HSSP,
-	AL_SRDS_TYPE_25G,
-};
-
-enum al_serdes_reg_page {
-	/* Relevant to Serdes hssp and 25g */
-	AL_SRDS_REG_PAGE_0_LANE_0 = 0,
-	AL_SRDS_REG_PAGE_1_LANE_1,
-	/* Relevant to Serdes hssp only */
-	AL_SRDS_REG_PAGE_2_LANE_2,
-	AL_SRDS_REG_PAGE_3_LANE_3,
-	/* Relevant to Serdes hssp and 25g */
-	AL_SRDS_REG_PAGE_4_COMMON,
-	/* Relevant to Serdes hssp only */
-	AL_SRDS_REG_PAGE_0123_LANES_0123 = 7,
-	/* Relevant to Serdes 25g only */
-	AL_SRDS_REG_PAGE_TOP,
-};
-
-/* Relevant to Serdes hssp only */
-enum al_serdes_reg_type {
-	AL_SRDS_REG_TYPE_PMA = 0,
-	AL_SRDS_REG_TYPE_PCS,
-};
-
-enum al_serdes_lane {
-	AL_SRDS_LANE_0 = AL_SRDS_REG_PAGE_0_LANE_0,
-	AL_SRDS_LANE_1 = AL_SRDS_REG_PAGE_1_LANE_1,
-	AL_SRDS_LANE_2 = AL_SRDS_REG_PAGE_2_LANE_2,
-	AL_SRDS_LANE_3 = AL_SRDS_REG_PAGE_3_LANE_3,
-
-	AL_SRDS_NUM_LANES,
-	AL_SRDS_LANES_0123 = AL_SRDS_REG_PAGE_0123_LANES_0123,
-};
-
-/** Serdes loopback mode */
-enum al_serdes_lb_mode {
-	/** No loopback */
-	AL_SRDS_LB_MODE_OFF,
-
-	/**
-	 * Transmits the untimed, partial equalized RX signal out the transmit
-	 * IO pins.
-	 * No clock used (untimed)
-	 */
-	AL_SRDS_LB_MODE_PMA_IO_UN_TIMED_RX_TO_TX,
-
-	/**
-	 * Loops back the TX serializer output into the CDR.
-	 * CDR recovered bit clock used (without attenuation)
-	 */
-	AL_SRDS_LB_MODE_PMA_INTERNALLY_BUFFERED_SERIAL_TX_TO_RX,
-
-	/**
-	 * Loops back the TX driver IO signal to the RX IO pins
-	 * CDR recovered bit clock used (only through IO)
-	 */
-	AL_SRDS_LB_MODE_PMA_SERIAL_TX_IO_TO_RX_IO,
-
-	/**
-	 * Parallel loopback from the PMA receive lane data ports, to the
-	 * transmit lane data ports
-	 * CDR recovered bit clock used
-	 */
-	AL_SRDS_LB_MODE_PMA_PARALLEL_RX_TO_TX,
-
-	/** Loops received data after elastic buffer to transmit path */
-	AL_SRDS_LB_MODE_PCS_PIPE,
-
-	/** Loops TX data (to PMA) to RX path (instead of PMA data) */
-	AL_SRDS_LB_MODE_PCS_NEAR_END,
-
-	/** Loops receive data prior to interface block to transmit path */
-	AL_SRDS_LB_MODE_PCS_FAR_END,
-};
-
-enum al_serdes_clk_freq {
-	AL_SRDS_CLK_FREQ_NA,
-	AL_SRDS_CLK_FREQ_100_MHZ,
-	AL_SRDS_CLK_FREQ_125_MHZ,
-	AL_SRDS_CLK_FREQ_156_MHZ,
-};
-
-enum al_serdes_clk_src {
-	AL_SRDS_CLK_SRC_LOGIC_0,
-	AL_SRDS_CLK_SRC_REF_PINS,
-	AL_SRDS_CLK_SRC_R2L,
-	AL_SRDS_CLK_SRC_R2L_PLL,
-	AL_SRDS_CLK_SRC_L2R,
-};
-
-/** Serdes BIST pattern */
-enum al_serdes_bist_pattern {
-	AL_SRDS_BIST_PATTERN_USER,
-	AL_SRDS_BIST_PATTERN_PRBS7,
-	AL_SRDS_BIST_PATTERN_PRBS23,
-	AL_SRDS_BIST_PATTERN_PRBS31,
-	AL_SRDS_BIST_PATTERN_CLK1010,
-};
-
-/** SerDes group rate */
-enum al_serdes_rate {
-	AL_SRDS_RATE_1_8,
-	AL_SRDS_RATE_1_4,
-	AL_SRDS_RATE_1_2,
-	AL_SRDS_RATE_FULL,
-};
-
-/** SerDes power mode */
-enum al_serdes_pm {
-	AL_SRDS_PM_PD,
-	AL_SRDS_PM_P2,
-	AL_SRDS_PM_P1,
-	AL_SRDS_PM_P0S,
-	AL_SRDS_PM_P0,
-};
-
-/**
- * Tx de-emphasis parameters
- */
-enum al_serdes_tx_deemph_param {
-	AL_SERDES_TX_DEEMP_C_ZERO,	/*< c(0) */
-	AL_SERDES_TX_DEEMP_C_PLUS,	/*< c(1) */
-	AL_SERDES_TX_DEEMP_C_MINUS,	/*< c(-1) */
-};
-
-struct al_serdes_adv_tx_params {
-	/*
-	 * select the input values location.
-	 * When set to true the values will be taken from the internal registers
-	 * that will be override with the next following parameters.
-	 * When set to false the values will be taken from external pins (the
-	 * other parameters in this case is not needed)
-	 */
-	al_bool				override;
-	/*
-	 * Transmit Amplitude control signal. Used to define the full-scale
-	 * maximum swing of the driver.
-	 *	000 - Not Supported
-	 *	001 - 952mVdiff-pkpk
-	 *	010 - 1024mVdiff-pkpk
-	 *	011 - 1094mVdiff-pkpk
-	 *	100 - 1163mVdiff-pkpk
-	 *	101 - 1227mVdiff-pkpk
-	 *	110 - 1283mVdiff-pkpk
-	 *	111 - 1331mVdiff-pkpk
-	 */
-	uint8_t				amp;
-	/* Defines the total number of driver units allocated in the driver */
-	uint8_t				total_driver_units;
-	/* Defines the total number of driver units allocated to the
-	 * first post-cursor (C+1) tap. */
-	uint8_t				c_plus_1;
-	/* Defines the total number of driver units allocated to the
-	 * second post-cursor (C+2) tap. */
-	uint8_t				c_plus_2;
-	/* Defines the total number of driver units allocated to the
-	 * first pre-cursor (C-1) tap. */
-	uint8_t				c_minus_1;
-	/* TX driver Slew Rate control:
-	 *	00 - 31ps
-	 *	01 - 33ps
-	 *	10 - 68ps
-	 *	11 - 170ps
-	 */
-	uint8_t				slew_rate;
-};
-
-struct al_serdes_adv_rx_params {
-	/*
-	 * select the input values location.
-	 * When set to true the values will be taken from the internal registers
-	 * that will be override with the next following parameters.
-	 * When set to false the values will be taken based in the equalization
-	 * results (the other parameters in this case is not needed)
-	 */
-	al_bool				override;
-	/* RX agc high frequency dc gain:
-	 *	-3'b000: -3dB
-	 *	-3'b001: -2.5dB
-	 *	-3'b010: -2dB
-	 *	-3'b011: -1.5dB
-	 *	-3'b100: -1dB
-	 *	-3'b101: -0.5dB
-	 *	-3'b110: -0dB
-	 *	-3'b111: 0.5dB
-	 */
-	uint8_t				dcgain;
-	/* DFE post-shaping tap 3dB frequency
-	 *	-3'b000: 684MHz
-	 *	-3'b001: 576MHz
-	 *	-3'b010: 514MHz
-	 *	-3'b011: 435MHz
-	 *	-3'b100: 354MHz
-	 *	-3'b101: 281MHz
-	 *	-3'b110: 199MHz
-	 *	-3'b111: 125MHz
-	 */
-	uint8_t				dfe_3db_freq;
-	/* DFE post-shaping tap gain
-	 *	0: no pulse shaping tap
-	 *	1: -24mVpeak
-	 *	2: -45mVpeak
-	 *	3: -64mVpeak
-	 *	4: -80mVpeak
-	 *	5: -93mVpeak
-	 *	6: -101mVpeak
-	 *	7: -105mVpeak
-	 */
-	uint8_t				dfe_gain;
-	/* DFE first tap gain control
-	 *	-4'b0000: +1mVpeak
-	 *	-4'b0001: +10mVpeak
-	 *	....
-	 *	-4'b0110: +55mVpeak
-	 *	-4'b0111: +64mVpeak
-	 *	-4'b1000: -1mVpeak
-	 *	-4'b1001: -10mVpeak
-	 *	....
-	 *	-4'b1110: -55mVpeak
-	 *	-4'b1111: -64mVpeak
-	 */
-	uint8_t				dfe_first_tap_ctrl;
-	/* DFE second tap gain control
-	 *	-4'b0000: +0mVpeak
-	 *	-4'b0001: +9mVpeak
-	 *	....
-	 *	-4'b0110: +46mVpeak
-	 *	-4'b0111: +53mVpeak
-	 *	-4'b1000: -0mVpeak
-	 *	-4'b1001: -9mVpeak
-	 *	....
-	 *	-4'b1110: -46mVpeak
-	 *	-4'b1111: -53mVpeak
-	 */
-	uint8_t				dfe_secound_tap_ctrl;
-	/* DFE third tap gain control
-	 *	-4'b0000: +0mVpeak
-	 *	-4'b0001: +7mVpeak
-	 *	....
-	 *	-4'b0110: +38mVpeak
-	 *	-4'b0111: +44mVpeak
-	 *	-4'b1000: -0mVpeak
-	 *	-4'b1001: -7mVpeak
-	 *	....
-	 *	-4'b1110: -38mVpeak
-	 *	-4'b1111: -44mVpeak
-	 */
-	uint8_t				dfe_third_tap_ctrl;
-	/* DFE fourth tap gain control
-	 *	-4'b0000: +0mVpeak
-	 *	-4'b0001: +6mVpeak
-	 *	....
-	 *	-4'b0110: +29mVpeak
-	 *	-4'b0111: +33mVpeak
-	 *	-4'b1000: -0mVpeak
-	 *	-4'b1001: -6mVpeak
-	 *	....
-	 *	-4'b1110: -29mVpeak
-	 *	-4'b1111: -33mVpeak
-	 */
-	uint8_t				dfe_fourth_tap_ctrl;
-	/* Low frequency agc gain (att) select
-	 *	-3'b000: Disconnected
-	 *	-3'b001: -18.5dB
-	 *	-3'b010: -12.5dB
-	 *	-3'b011: -9dB
-	 *	-3'b100: -6.5dB
-	 *	-3'b101: -4.5dB
-	 *	-3'b110: -2.9dB
-	 *	-3'b111: -1.6dB
-	 */
-	uint8_t				low_freq_agc_gain;
-	/* Provides a RX Equalizer pre-hint, prior to beginning
-	 * adaptive equalization */
-	uint8_t				precal_code_sel;
-	/* High frequency agc boost control
-	 *	Min d0: Boost ~4dB
-	 *	Max d31: Boost ~20dB
-	 */
-	uint8_t				high_freq_agc_boost;
-};
-
-struct al_serdes_25g_adv_rx_params {
-	/* ATT (PLE Flat-Band Gain) */
-	uint8_t				att;
-	/* APG (CTLE's Flat-Band Gain) */
-	uint8_t				apg;
-	/* LFG (Low-Freq Gain) */
-	uint8_t				lfg;
-	/* HFG (High-Freq Gain) */
-	uint8_t				hfg;
-	/* MBG (MidBand-Freq-knob Gain) */
-	uint8_t				mbg;
-	/* MBF (MidBand-Freq-knob Frequency position Gain) */
-	uint8_t				mbf;
-	/* DFE Tap1 even#0 Value */
-	int8_t				dfe_first_tap_even0_ctrl;
-	/* DFE Tap1 even#1 Value */
-	int8_t				dfe_first_tap_even1_ctrl;
-	/* DFE Tap1 odd#0 Value */
-	int8_t				dfe_first_tap_odd0_ctrl;
-	/* DFE Tap1 odd#1 Value */
-	int8_t				dfe_first_tap_odd1_ctrl;
-	/* DFE Tap2 Value */
-	int8_t				dfe_second_tap_ctrl;
-	/* DFE Tap3 Value */
-	int8_t				dfe_third_tap_ctrl;
-	/* DFE Tap4 Value */
-	int8_t				dfe_fourth_tap_ctrl;
-	/* DFE Tap5 Value */
-	int8_t				dfe_fifth_tap_ctrl;
-};
-
-struct al_serdes_25g_tx_diag_info {
-	uint8_t regulated_supply;
-	int8_t dcd_trim;
-	uint8_t clk_delay;
-	uint8_t calp_multiplied_by_2;
-	uint8_t caln_multiplied_by_2;
-};
-
-struct al_serdes_25g_rx_diag_info {
-	int8_t los_offset;
-	int8_t agc_offset;
-	int8_t leq_gainstage_offset;
-	int8_t leq_eq1_offset;
-	int8_t leq_eq2_offset;
-	int8_t leq_eq3_offset;
-	int8_t leq_eq4_offset;
-	int8_t leq_eq5_offset;
-	int8_t summer_even_offset;
-	int8_t summer_odd_offset;
-	int8_t vscan_even_offset;
-	int8_t vscan_odd_offset;
-	int8_t data_slicer_even0_offset;
-	int8_t data_slicer_even1_offset;
-	int8_t data_slicer_odd0_offset;
-	int8_t data_slicer_odd1_offset;
-	int8_t edge_slicer_even_offset;
-	int8_t edge_slicer_odd_offset;
-	int8_t eye_slicer_even_offset;
-	int8_t eye_slicer_odd_offset;
-	uint8_t cdr_clk_i;
-	uint8_t cdr_clk_q;
-	uint8_t cdr_dll;
-	uint8_t cdr_vco_dosc;
-	uint8_t cdr_vco_fr;
-	uint16_t cdr_dlpf;
-	uint8_t ple_resistance;
-	uint8_t rx_term_mode;
-	uint8_t rx_coupling;
-	uint8_t rx_term_cal_code;
-	uint8_t rx_sheet_res_cal_code;
-};
-
-/**
- * SRIS parameters
- */
-struct al_serdes_sris_params {
-	/* Controls the frequency accuracy threshold (ppm) for lock detection CDR */
-	uint16_t	ppm_drift_count;
-	/* Controls the frequency accuracy threshold (ppm) for lock detection in the CDR */
-	uint16_t	ppm_drift_max;
-	/* Controls the frequency accuracy threshold (ppm) for lock detection in PLL */
-	uint16_t	synth_ppm_drift_max;
-	/* Elastic buffer full threshold for PCIE modes: GEN1/GEN2 */
-	uint8_t		full_d2r1;
-	/* Elastic buffer full threshold for PCIE modes: GEN3 */
-	uint8_t		full_pcie_g3;
-	/* Elastic buffer midpoint threshold.
-	 * Sets the depth of the buffer while in PCIE mode, GEN1/GEN2
-	 */
-	uint8_t		rd_threshold_d2r1;
-	/* Elastic buffer midpoint threshold.
-	 * Sets the depth of the buffer while in PCIE mode, GEN3
-	 */
-	uint8_t		rd_threshold_pcie_g3;
-};
-
-/** SerDes PCIe Rate - values are important for proper behavior */
-enum al_serdes_pcie_rate {
-	AL_SRDS_PCIE_RATE_GEN1 = 0,
-	AL_SRDS_PCIE_RATE_GEN2,
-	AL_SRDS_PCIE_RATE_GEN3,
-};
-
-struct al_serdes_grp_obj {
-	void __iomem				*regs_base;
-
-	/**
-	 * get the type of the serdes.
-	 * Must be implemented for all SerDes unit.
-	 *
-	 * @return the serdes type.
-	 */
-	enum al_serdes_type (*type_get)(void);
-
-	/**
-	 * Reads a SERDES internal register
-	 *
-	 * @param obj		The object context
-	 * @param page		The SERDES register page within the group
-	 * @param type		The SERDES register type (PMA /PCS)
-	 * @param offset	The SERDES register offset (0 - 4095)
-	 * @param data		The read data
-	 *
-	 * @return 0 if no error found.
-	 */
-	int (*reg_read)(struct al_serdes_grp_obj *, enum al_serdes_reg_page,
-			enum al_serdes_reg_type, uint16_t, uint8_t *);
-
-	/**
-	 * Writes a SERDES internal register
-	 *
-	 * @param obj		The object context
-	 * @param page		The SERDES register page within the group
-	 * @param type		The SERDES register type (PMA /PCS)
-	 * @param offset	The SERDES register offset (0 - 4095)
-	 * @param data		The data to write
-	 *
-	 * @return 0 if no error found.
-	 */
-	int (*reg_write)(struct al_serdes_grp_obj *, enum al_serdes_reg_page,
-			enum al_serdes_reg_type, uint16_t, uint8_t);
-
-	/**
-	 * Enable BIST required overrides
-	 *
-	 * @param obj		The object context
-	 * @param grp		The SERDES group
-	 * @param rate		The required speed rate
-	 */
-	void (*bist_overrides_enable)(struct al_serdes_grp_obj *, enum al_serdes_rate);
-	/**
-	 * Disable BIST required overrides
-	 *
-	 * @param obj		The object context
-	 * @param grp		The SERDES group
-	 * @param rate		The required speed rate
-	 */
-	void (*bist_overrides_disable)(struct al_serdes_grp_obj *);
-	/**
-	 * Rx rate change
-	 *
-	 * @param obj		The object context
-	 * @param grp		The SERDES group
-	 * @param rate		The Rx required rate
-	 */
-	void (*rx_rate_change)(struct al_serdes_grp_obj *, enum al_serdes_rate);
-	/**
-	 * SERDES lane Rx rate change software flow enable
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 */
-	void (*rx_rate_change_sw_flow_en)(struct al_serdes_grp_obj *, enum al_serdes_lane);
-	/**
-	 * SERDES lane Rx rate change software flow disable
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 */
-	void (*rx_rate_change_sw_flow_dis)(struct al_serdes_grp_obj *, enum al_serdes_lane);
-	/**
-	 * PCIe lane rate override check
-	 *
-	 * @param obj		The object context
-	 * @param grp		The SERDES group
-	 * @param lane		The SERDES lane within the group
-	 *
-	 * @returns	AL_TRUE if the override is enabled
-	 */
-	al_bool (*pcie_rate_override_is_enabled)(struct al_serdes_grp_obj *, enum al_serdes_lane);
-	/**
-	 * PCIe lane rate override control
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param en		Enable/disable
-	 */
-	void (*pcie_rate_override_enable_set)(struct al_serdes_grp_obj *, enum al_serdes_lane,
-					      al_bool en);
-	/**
-	 * PCIe lane rate get
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 */
-	enum al_serdes_pcie_rate (*pcie_rate_get)(struct al_serdes_grp_obj *, enum al_serdes_lane);
-	/**
-	 * PCIe lane rate set
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param rate		The required rate
-	 */
-	void (*pcie_rate_set)(struct al_serdes_grp_obj *, enum al_serdes_lane,
-			      enum al_serdes_pcie_rate rate);
-	/**
-	 * SERDES group power mode control
-	 *
-	 * @param obj		The object context
-	 * @param grp		The SERDES group
-	 * @param pm		The required power mode
-	 */
-	void (*group_pm_set)(struct al_serdes_grp_obj *, enum al_serdes_pm);
-	/**
-	 * SERDES lane power mode control
-	 *
-	 * @param obj		The object context
-	 * @param grp		The SERDES group
-	 * @param lane		The SERDES lane within the group
-	 * @param rx_pm		The required RX power mode
-	 * @param tx_pm		The required TX power mode
-	 */
-	void (*lane_pm_set)(struct al_serdes_grp_obj *, enum al_serdes_lane,
-			    enum al_serdes_pm, enum al_serdes_pm);
-
-	/**
-	 * SERDES group PMA hard reset
-	 * Controls Serdes group PMA hard reset
-	 *
-	 * @param obj		The object context
-	 * @param grp		The SERDES group
-	 * @param enable	Enable/disable hard reset
-	 */
-	void (*pma_hard_reset_group)(struct al_serdes_grp_obj *, al_bool);
-	/**
-	 * SERDES lane PMA hard reset
-	 * Controls Serdes lane PMA hard reset
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param enable	Enable/disable hard reset
-	 */
-	void (*pma_hard_reset_lane)(struct al_serdes_grp_obj *, enum al_serdes_lane, al_bool);
-	/**
-	 * Configure SERDES loopback
-	 * Controls the loopback
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param mode		The requested loopback mode
-	 */
-	void (*loopback_control)(struct al_serdes_grp_obj *, enum al_serdes_lane,
-				 enum al_serdes_lb_mode);
-	/**
-	 * SERDES BIST pattern selection
-	 * Selects the BIST pattern to be used
-	 *
-	 * @param obj		The object context
-	 * @param pattern	The pattern to set
-	 * @param user_data	The pattern user data (when pattern == AL_SRDS_BIST_PATTERN_USER)
-	 *			80 bits (8 bytes array)
-	 */
-	void (*bist_pattern_select)(struct al_serdes_grp_obj *,
-				    enum al_serdes_bist_pattern, uint8_t *);
-	/**
-	 * SERDES BIST TX Enable
-	 * Enables/disables TX BIST per lane
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param enable	Enable or disable TX BIST
-	 */
-	void (*bist_tx_enable)(struct al_serdes_grp_obj *, enum al_serdes_lane, al_bool);
-	/**
-	 * SERDES BIST TX single bit error injection
-	 * Injects single bit error during a TX BIST
-	 *
-	 * @param obj		The object context
-	 */
-	void (*bist_tx_err_inject)(struct al_serdes_grp_obj *);
-	/**
-	 * SERDES BIST RX Enable
-	 * Enables/disables RX BIST per lane
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param enable	Enable or disable TX BIST
-	 */
-	void (*bist_rx_enable)(struct al_serdes_grp_obj *, enum al_serdes_lane, al_bool);
-	/**
-	 * SERDES BIST RX status
-	 * Checks the RX BIST status for a specific SERDES lane
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param is_locked	An indication whether RX BIST is locked
-	 * @param err_cnt_overflow	An indication whether error count overflow occured
-	 * @param err_cnt	Current bit error count
-	 */
-	void (*bist_rx_status)(struct al_serdes_grp_obj *, enum al_serdes_lane, al_bool *,
-			       al_bool *, uint32_t *);
-
-	/**
-	 * Set the tx de-emphasis to preset values
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 *
-	 */
-	void (*tx_deemph_preset)(struct al_serdes_grp_obj *, enum al_serdes_lane);
-	/**
-	 * Increase tx de-emphasis param.
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param param		which tx de-emphasis to change
-	 *
-	 * @return false in case max is reached. true otherwise.
-	 */
-	al_bool (*tx_deemph_inc)(struct al_serdes_grp_obj *, enum al_serdes_lane,
-				 enum al_serdes_tx_deemph_param);
-	/**
-	 * Decrease tx de-emphasis param.
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param param		which tx de-emphasis to change
-	 *
-	 * @return false in case min is reached. true otherwise.
-	 */
-	al_bool (*tx_deemph_dec)(struct al_serdes_grp_obj *, enum al_serdes_lane,
-				 enum al_serdes_tx_deemph_param);
-	/**
-	 * run Rx eye measurement.
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param timeout	timeout in uSec
-	 * @param value		Rx eye measurement value
-	 *			(0 - completely closed eye, 0xffff - completely open eye).
-	 *
-	 * @return 0 if no error found.
-	 */
-	int (*eye_measure_run)(struct al_serdes_grp_obj *, enum al_serdes_lane,
-			       uint32_t, unsigned int *);
-	/**
-	 * Eye diagram single sampling
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param x		Sampling X position (0 - 63 --> -1.00 UI ... 1.00 UI)
-	 * @param y		Sampling Y position (0 - 62 --> 500mV ... -500mV)
-	 * @param timeout	timeout in uSec
-	 * @param value		Eye diagram sample value (BER - 0x0000 - 0xffff)
-	 *
-	 * @return 0 if no error found.
-	 */
-	int (*eye_diag_sample)(struct al_serdes_grp_obj *, enum al_serdes_lane,
-			       unsigned int, int, unsigned int, unsigned int *);
-
-	/**
-	 * Eye diagram full run
-	 *
-	 * @param obj			The object context
-	 * @param lane			The SERDES lane within the group
-	 * @param x_start		Sampling from X position
-	 * @param x_stop		Sampling to X position
-	 * @param x_step		jump in x_step
-	 * @param y_start		Sampling from Y position
-	 * @param y_stop		Sampling to Y position
-	 * @param y_step		jump in y_step
-	 * @param num_bits_per_sample	How many bits to check
-	 * @param buf			array of results
-	 * @param buf_size		array size - must be equal to
-	 *				(((y_stop - y_start) / y_step) + 1) *
-	 *				(((x_stop - x_start) / x_step) + 1)
-	 *
-	 * @return 0 if no error found.
-	 */
-	int (*eye_diag_run)(struct al_serdes_grp_obj	*, enum al_serdes_lane,
-			    int, int, unsigned int, int, int, unsigned int, uint64_t, uint64_t *,
-			    uint32_t);
-	/**
-	 * Check if signal is detected
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 *
-	 * @return true if signal is detected. false otherwise.
-	 */
-	al_bool (*signal_is_detected)(struct al_serdes_grp_obj *, enum al_serdes_lane);
-
-	/**
-	 * Check if CDR is locked
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 *
-	 * @return true if cdr is locked. false otherwise.
-	 */
-	al_bool (*cdr_is_locked)(struct al_serdes_grp_obj *, enum al_serdes_lane);
-
-	/**
-	 * Check if rx is valid for this lane
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 *
-	 * @return true if rx is valid. false otherwise.
-	 */
-	al_bool (*rx_valid)(struct al_serdes_grp_obj *, enum al_serdes_lane);
-
-	/**
-	 * configure tx advanced parameters
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param params	pointer to the tx parameters
-	 */
-	void (*tx_advanced_params_set)(struct al_serdes_grp_obj *, enum al_serdes_lane, void *);
-	/**
-	 * read tx advanced parameters
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param params	pointer to the tx parameters
-	 */
-	void (*tx_advanced_params_get)(struct al_serdes_grp_obj *, enum al_serdes_lane, void *);
-	/**
-	 * configure rx advanced parameters
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param params	pointer to the rx parameters
-	 */
-	void (*rx_advanced_params_set)(struct al_serdes_grp_obj *, enum al_serdes_lane, void *);
-	/**
-	 * read rx advanced parameters
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param params	pointer to the rx parameters
-	 */
-	void (*rx_advanced_params_get)(struct al_serdes_grp_obj *, enum al_serdes_lane, void *);
-	/**
-	 *  Switch entire SerDes group to SGMII mode based on 156.25 Mhz reference clock
-	 *
-	 * @param obj		The object context
-	 *
-	 */
-	void (*mode_set_sgmii)(struct al_serdes_grp_obj *);
-	/**
-	 *  Switch entire SerDes group to KR mode based on 156.25 Mhz reference clock
-	 *
-	 * @param obj		The object context
-	 *
-	 */
-	void (*mode_set_kr)(struct al_serdes_grp_obj *);
-	/**
-	 * performs SerDes HW equalization test and update equalization parameters
-	 *
-	 * @param obj		the object context
-	 * @param lane		The SERDES lane within the group
-	 */
-	int (*rx_equalization)(struct al_serdes_grp_obj *, enum al_serdes_lane);
-	/**
-	 * performs Rx equalization and compute the width and height of the eye
-	 *
-	 * @param obj		the object context
-	 * @param lane		The SERDES lane within the group
-	 * @param width		the output width of the eye
-	 * @param height	the output height of the eye
-	 */
-	int (*calc_eye_size)(struct al_serdes_grp_obj *, enum al_serdes_lane, int *, int *);
-	/**
-	 * SRIS: Separate Refclk Independent SSC (Spread Spectrum Clocking)
-	 * Currently available only for PCIe interfaces.
-	 * When working with local Refclk, same SRIS configuration in both serdes sides
-	 * (EP and RC in PCIe interface) is required.
-	 *
-	 * performs SRIS configuration according to params
-	 *
-	 * @param obj		the object context
-	 * @param params	the SRIS parameters
-	 */
-	void (*sris_config)(struct al_serdes_grp_obj *, void *);
-	/**
-	 * set SERDES dcgain parameter
-	 *
-	 * @param obj		the object context
-	 * @param dcgain	dcgain value to set
-	 */
-	void (*dcgain_set)(struct al_serdes_grp_obj *, uint8_t);
-	/**
-	 * read tx diagnostics info
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param params	pointer to the tx diagnostics info structure
-	 */
-	void (*tx_diag_info_get)(struct al_serdes_grp_obj *, enum al_serdes_lane, void*);
-	/**
-	 * read rx diagnostics info
-	 *
-	 * @param obj		The object context
-	 * @param lane		The SERDES lane within the group
-	 * @param params	pointer to the rx diagnostics info structure
-	 */
-	void (*rx_diag_info_get)(struct al_serdes_grp_obj *, enum al_serdes_lane, void*);
-};
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-
-/* *INDENT-ON* */
-#endif		/* __AL_HAL_SERDES_INTERFACE_H__ */
-
-/** @} end of SERDES group */
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_internal_regs.h b/sys/contrib/alpine-hal/eth/al_hal_serdes_internal_regs.h
deleted file mode 100644
index 8f53469bc4cf..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_internal_regs.h
+++ /dev/null
@@ -1,750 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-#ifndef __AL_SERDES_INTERNAL_REGS_H__
-#define  __AL_SERDES_INTERNAL_REGS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*******************************************************************************
- * Per lane register fields
- ******************************************************************************/
-/*
- * RX and TX lane hard reset
- * 0 - Hard reset is asserted
- * 1 - Hard reset is de-asserted
- */
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM			2
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK			0x01
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT		0x00
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT		0x01
-
-/*
- * RX and TX lane hard reset control
- * 0 - Hard reset is taken from the interface pins
- * 1 - Hard reset is taken from registers
- */
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM		2
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK			0x02
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_IFACE		0x00
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS		0x02
-
-/* RX lane power state control */
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM			3
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK				0x1f
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD				0x01
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2				0x02
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1				0x04
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S			0x08
-#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0				0x10
-
-/* TX lane power state control */
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM			4
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK				0x1f
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD				0x01
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2				0x02
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1				0x04
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S			0x08
-#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0				0x10
-
-/* RX lane word width */
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM				5
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK				0x07
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_8				0x00
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_10				0x01
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_16				0x02
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20				0x03
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_32				0x04
-#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_40				0x05
-
-/* TX lane word width */
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM				5
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK				0x70
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_8				0x00
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_10				0x10
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_16				0x20
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20				0x30
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_32				0x40
-#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_40				0x50
-
-/* RX lane rate select */
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM				6
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_MASK				0x07
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8				0x00
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4				0x01
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2				0x02
-#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1				0x03
-
-/* TX lane rate select */
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM				6
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_MASK				0x70
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8				0x00
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4				0x10
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2				0x20
-#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1				0x30
-
-/*
- * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
- * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
- * partial equalized RX signal out the transmit IO pins
- */
-#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM			7
-#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN				0x10
-
-/*
- * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
- * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
- * the TX serializer output into the CDR
- */
-#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM			7
-#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN				0x20
-
-/*
- * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
- * RX pads). Serial IO loopback from the transmit lane IO pins to the receive
- * lane IO pins: 0 - Disables loopback 1 - Loops back the driver IO signal to
- * the RX IO pins
- */
-#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM			7
-#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN				0x40
-
-/*
- * PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA
- * receive lane 20-bit data ports, to the transmit lane 20-bit data ports 0 -
- * Disables loopback 1 - Loops back the 20-bit receive data port to the
- * transmitter
- */
-#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM			7
-#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN				0x80
-
-/*
- * PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1.
- * Transmit bit clock select: 0 - Selects synthesizer bit clock for transmit 1
- * - Selects CDR clock for transmit
- */
-#define SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM				7
-#define SERDES_IREG_FLD_LB_CDRCLK2TXEN					0x01
-
-/* Receive lane BIST enable. Active High */
-#define SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM				8
-#define SERDES_IREG_FLD_PCSRXBIST_EN					0x01
-
-/* TX lane BIST enable. Active High */
-#define SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM				8
-#define SERDES_IREG_FLD_PCSTXBIST_EN					0x02
-
-/*
- * RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates
- * the test has completed, and will remain high until a new test is initiated
- */
-#define SERDES_IREG_FLD_RXBIST_DONE_REG_NUM				8
-#define SERDES_IREG_FLD_RXBIST_DONE					0x04
-
-/*
- * RX BIST error count overflow indicator. Indicates an overflow in the number
- * of byte errors identified during the course of the test. This word is stable
- * to sample when *_DONE_* signal has asserted
- */
-#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM		8
-#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW			0x08
-
-/*
- * RX BIST locked indicator 0 - Indicates BIST is not word locked and error
- * comparisons have not begun yet 1 - Indicates BIST is word locked and error
- * comparisons have begun
- */
-#define SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM				8
-#define SERDES_IREG_FLD_RXBIST_RXLOCKED					0x10
-
-/*
- * RX BIST error count word. Indicates the number of byte errors identified
- * during the course of the test. This word is stable to sample when *_DONE_*
- * signal has asserted
- */
-#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM			9
-#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM			10
-
-/* Tx params */
-#define SERDES_IREG_TX_DRV_1_REG_NUM					21
-#define SERDES_IREG_TX_DRV_1_HLEV_MASK					0x7
-#define SERDES_IREG_TX_DRV_1_HLEV_SHIFT					0
-#define SERDES_IREG_TX_DRV_1_LEVN_MASK					0xf8
-#define SERDES_IREG_TX_DRV_1_LEVN_SHIFT					3
-
-#define SERDES_IREG_TX_DRV_2_REG_NUM					22
-#define SERDES_IREG_TX_DRV_2_LEVNM1_MASK				0xf
-#define SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT				0
-#define SERDES_IREG_TX_DRV_2_LEVNM2_MASK				0x30
-#define SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT				4
-
-#define SERDES_IREG_TX_DRV_3_REG_NUM					23
-#define SERDES_IREG_TX_DRV_3_LEVNP1_MASK				0x7
-#define SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT				0
-#define SERDES_IREG_TX_DRV_3_SLEW_MASK					0x18
-#define SERDES_IREG_TX_DRV_3_SLEW_SHIFT					3
-
-/* Rx params */
-#define SERDES_IREG_RX_CALEQ_1_REG_NUM					24
-#define SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK				0x7
-#define SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT				0
-/* DFE post-shaping tap 3dB frequency */
-#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK				0x38
-#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT			3
-
-#define SERDES_IREG_RX_CALEQ_2_REG_NUM					25
-/* DFE post-shaping tap gain */
-#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK			0x7
-#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT			0
-/* DFE first tap gain control */
-#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK				0x78
-#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT			3
-
-#define SERDES_IREG_RX_CALEQ_3_REG_NUM					26
-#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK				0xf
-#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT			0
-#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK				0xf0
-#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT			4
-
-#define SERDES_IREG_RX_CALEQ_4_REG_NUM					27
-#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK				0xf
-#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT			0
-#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK			0x70
-#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT			4
-
-#define SERDES_IREG_RX_CALEQ_5_REG_NUM					28
-#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK			0x7
-#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT			0
-#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK			0xf8
-#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT			3
-
-/* RX lane best eye point measurement result */
-#define SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM			29
-#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM			30
-#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK				0x3F
-
-/*
- * Adaptive RX Equalization enable
- * 0 - Disables adaptive RX equalization.
- * 1 - Enables adaptive RX equalization.
- */
-#define SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM				31
-#define SERDES_IREG_FLD_PCSRXEQ_START					(1 << 0)
-
-/*
- * Enables an eye diagram measurement
- * within the PHY.
- * 0 - Disables eye diagram measurement
- * 1 - Enables eye diagram measurement
- */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM			31
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START				(1 << 1)
-
-
-/*
- * RX lane single roam eye point measurement start signal.
- * If asserted, single measurement at fix XADJUST and YADJUST is started.
- */
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM		31
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START		(1 << 2)
-
-
-/*
- * PHY Eye diagram measurement status
- * signal
- * 0 - Indicates eye diagram results are not
- * valid for sampling
- * 1 - Indicates eye diagram is complete and
- * results are valid for sampling
- */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM			32
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE				(1 << 0)
-
-/*
- * Eye diagram error signal. Indicates if the
- * measurement was invalid because the eye
- * diagram was interrupted by the link entering
- * electrical idle.
- * 0 - Indicates eye diagram is valid
- * 1- Indicates an error occurred, and the eye
- * diagram measurement should be re-run
- */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR_REG_NUM			32
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR				(1 << 1)
-
-/*
- * PHY Adaptive Equalization status
- * 0 - Indicates Adaptive Equalization results are not valid for sampling
- * 1 - Indicates Adaptive Equalization is complete and results are valid for
- *     sampling
- */
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM			32
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE				(1 << 2)
-
-/*
- *
- * PHY Adaptive Equalization Status Signal
- * 0 – Indicates adaptive equalization results
- * are not valid for sampling
- * 1 – Indicates adaptive equalization is
- * complete and results are valid for sampling.
- */
-#define SERDES_IREG_FLD_RXEQ_DONE_REG_NUM				32
-#define SERDES_IREG_FLD_RXEQ_DONE					(1 << 3)
-
-
-/*
- * 7-bit eye diagram time adjust control
- * - 6-bits per UI
- * - spans 2 UI
- */
-#define SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM			33
-
-/* 6-bit eye diagram voltage adjust control - spans +/-300mVdiff */
-#define SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM			34
-
-/*
- * Eye diagram status signal. Safe for
- * sampling when *DONE* signal has
- * asserted
- * 14'h0000 - Completely Closed Eye
- * 14'hFFFF - Completely Open Eye
- */
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM		35
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_MAKE			0xFF
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_SHIFT		0
-
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM		36
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE			0x3F
-#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_SHIFT		0
-
-/*
- * RX lane single roam eye point measurement result.
- * If 0, eye is open at current XADJUST and YADJUST settings.
- */
-#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM		37
-#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM		38
-
-/*
- * Override enable for CDR lock to reference clock
- * 0 - CDR is always locked to reference
- * 1 - CDR operation mode (Lock2Reference or Lock2data are controlled internally
- *     depending on the incoming signal and ppm status)
- */
-#define SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM			39
-#define SERDES_IREG_FLD_RXLOCK2REF_OVREN				(1 << 1)
-
-/*
- * Selects Eye to capture based on edge
- * 0 - Capture 1st Eye in Eye Diagram
- * 1 - Capture 2nd Eye in Eye Diagram measurement
- */
-#define SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM			39
-#define SERDES_IREG_FLD_RXROAM_XORBITSEL				(1 << 2)
-#define SERDES_IREG_FLD_RXROAM_XORBITSEL_1ST				0
-#define SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND				(1 << 2)
-
-/*
- * RX Signal detect. 0 indicates no signal, 1 indicates signal detected.
- */
-#define SERDES_IREG_FLD_RXRANDET_REG_NUM				41
-#define SERDES_IREG_FLD_RXRANDET_STAT					0x20
-
-/*
- * RX data polarity inversion control:
- * 1'b0: no inversion
- * 1'b1: invert polarity
- */
-#define SERDES_IREG_FLD_POLARITY_RX_REG_NUM				46
-#define SERDES_IREG_FLD_POLARITY_RX_INV					(1 << 0)
-
-/*
- * TX data polarity inversion control:
- * 1'b0: no inversion
- * 1'b1: invert polarity
- */
-#define SERDES_IREG_FLD_POLARITY_TX_REG_NUM				46
-#define SERDES_IREG_FLD_POLARITY_TX_INV					(1 << 1)
-
-/* LANEPCSPSTATE* override enable (Active low) */
-#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM			85
-#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN				(1 << 0)
-
-/* LB* override enable (Active low) */
-#define SERDES_IREG_FLD_LB_LOCWREN_REG_NUM				85
-#define SERDES_IREG_FLD_LB_LOCWREN					(1 << 1)
-
-/* PCSRX* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM				85
-#define SERDES_IREG_FLD_PCSRX_LOCWREN					(1 << 4)
-
-/* PCSRXBIST* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM			85
-#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN				(1 << 5)
-
-/* PCSRXEQ* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM				85
-#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN					(1 << 6)
-
-/* PCSTX* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM				85
-#define SERDES_IREG_FLD_PCSTX_LOCWREN					(1 << 7)
-
-/*
- * group registers:
- * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN,
- * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN
- * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
- */
-#define SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM				86
-
-/* PCSTXBIST* override enable (Active low) */
-#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM			86
-#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN				(1 << 0)
-
-/* Override RX_CALCEQ through the internal registers (Active low) */
-#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM			86
-#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN				(1 << 3)
-
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM		86
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN			(1 << 4)
-
-
-/* RXCALROAMEYEMEASIN* override enable - Active Low */
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM		86
-#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN			(1 << 6)
-
-/* RXCALROAMXADJUST* override enable - Active Low */
-#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM		86
-#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN			(1 << 7)
-
-/* RXCALROAMYADJUST* override enable - Active Low */
-#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM		87
-#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN			(1 << 0)
-
-/* RXCDRCALFOSC* override enable. Active Low */
-#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN_REG_NUM			87
-#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN				(1 << 1)
-
-/* Over-write enable for RXEYEDIAGFSM_INITXVAL */
-#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN_REG_NUM			87
-#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN				(1 << 2)
-
-/* Over-write enable for CMNCLKGENMUXSEL_TXINTERNAL */
-#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN_REG_NUM			87
-#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN				(1 << 3)
-
-/* TXCALTCLKDUTY* override enable. Active Low */
-#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN_REG_NUM			87
-#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN				(1 << 4)
-
-/* Override TX_DRV through the internal registers (Active low) */
-#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM			87
-#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN				(1 << 5)
-
-/*******************************************************************************
- * Common lane register fields - PMA
- ******************************************************************************/
-/*
- * Common lane hard reset control
- * 0 - Hard reset is taken from the interface pins
- * 1 - Hard reset is taken from registers
- */
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM		2
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK		0x01
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_IFACE	0x00
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS	0x01
-
-/*
- * Common lane hard reset
- * 0 - Hard reset is asserted
- * 1 - Hard reset is de-asserted
- */
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM		2
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK		0x02
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT	0x00
-#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT	0x02
-
-/* Synth power state control */
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM			3
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK				0x1f
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD			0x01
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2			0x02
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1			0x04
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S			0x08
-#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0			0x10
-
-/* Transmit datapath FIFO enable (Active High) */
-#define SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM				8
-#define SERDES_IREG_FLD_CMNPCS_TXENABLE					(1 << 2)
-
-/*
- * RX lost of signal detector enable
- * - 0 - disable
- * - 1 - enable
- */
-#define SERDES_IREG_FLD_RXLOSDET_ENABLE_REG_NUM				13
-#define SERDES_IREG_FLD_RXLOSDET_ENABLE					AL_BIT(4)
-
-/* Signal Detect Threshold Level */
-#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_REG_NUM			15
-#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK			AL_FIELD_MASK(2, 0)
-
-/* LOS Detect Threshold Level */
-#define SERDES_IREG_FLD_RXLOSDET_THRESH_REG_NUM				15
-#define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK				AL_FIELD_MASK(4, 3)
-#define SERDES_IREG_FLD_RXLOSDET_THRESH_SHIFT				3
-
-#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM			30
-#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK			0x7f
-#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM			31
-#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK				0x7f
-#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM			32
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK			0xff
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM			33
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK			0x1
-#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM			33
-#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK				0x3e
-#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT				1
-
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM			34
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK			0xff
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM			35
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK			0x1
-#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM				35
-#define SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK				0x3e
-#define SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT				1
-
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM			36
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK			0xff
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM			37
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK			0x7
-#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT			0
-
-#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_REG_NUM			43
-#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_MASK				0x7
-#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_SHIFT				0
-
-#define SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(byte_num)			(56 + (byte_num))
-#define SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES				10
-
-/*
- * Selects the transmit BIST mode:
- * 0 - Uses the 80-bit internal memory pattern (w/ OOB)
- * 1 - Uses a 27 PRBS pattern
- * 2 - Uses a 223 PRBS pattern
- * 3 - Uses a 231 PRBS pattern
- * 4 - Uses a 1010 clock pattern
- * 5 and above - Reserved
- */
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM			80
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK				0x07
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER			0x00
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7			0x01
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23			0x02
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31			0x03
-#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010			0x04
-
-/* Single-Bit error injection enable (on posedge) */
-#define SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM			80
-#define SERDES_IREG_FLD_TXBIST_BITERROR_EN				0x20
-
-/* CMNPCIEGEN3* override enable (Active Low) */
-#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM			95
-#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN				(1 << 2)
-
-/* CMNPCS* override enable (Active Low) */
-#define SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM				95
-#define SERDES_IREG_FLD_CMNPCS_LOCWREN					(1 << 3)
-
-/* CMNPCSBIST* override enable (Active Low) */
-#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM			95
-#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN				(1 << 4)
-
-/* CMNPCSPSTATE* override enable (Active Low) */
-#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM			95
-#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN				(1 << 5)
-
-/*  PCS_EN* override enable (Active Low) */
-#define SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM				96
-#define SERDES_IREG_FLD_PCS_LOCWREN					(1 << 3)
-
-/* Eye diagram sample count */
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM			150
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK			0xff
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT			0
-
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM			151
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK			0xff
-#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT			0
-
-/* override control */
-#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM			230
-#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN				1 << 0
-
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM		623
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK		0xff
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT		0
-
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM		624
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK		0xff
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT		0
-
-/* X and Y coefficient return value */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM		626
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_MASK			0x0F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_SHIFT		0
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_MASK			0xF0
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_SHIFT		4
-
-/* X coarse scan step */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM		627
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK			0x7F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT		0
-
-/* X fine scan step */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM		628
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK			0x7F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT			0
-
-/* Y coarse scan step */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM		629
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK			0x0F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT		0
-
-/* Y fine scan step */
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM		630
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK			0x0F
-#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT			0
-
-#define SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM				157
-
-#define SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM				158
-
-#define SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM				159
-
-#define SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM				160
-
-#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM			163
-
-#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM			164
-
-/*******************************************************************************
- * Common lane register fields - PCS
- ******************************************************************************/
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM			3
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK			AL_FIELD_MASK(5, 4)
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT			4
-
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM			6
-#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA				AL_BIT(2)
-
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM			18
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK			0x1F
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM			19
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK			0x7C
-#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT			2
-
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM		20
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK		0x1F
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT		0
-
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM		21
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK		0x7C
-#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT		2
-
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_REG_NUM		22
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_MASK			0x7f
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_REG_NUM			34
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_MASK			0x7f
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_REG_NUM		23
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_MASK			0xff
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_REG_NUM		22
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_MASK			0x80
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_SHIFT			7
-
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_REG_NUM			24
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_MASK			0x3e
-#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_SHIFT			1
-
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_REG_NUM			35
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_MASK			0xff
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_REG_NUM			34
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_MASK			0x80
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_SHIFT			7
-
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_REG_NUM			36
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_MASK				0x1f
-#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_REG_NUM			37
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_MASK			0xff
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_SHIFT			0
-
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_REG_NUM		36
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_MASK			0xe0
-#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_SHIFT			5
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_serdes_REG_H */
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_serdes_regs.h b/sys/contrib/alpine-hal/eth/al_hal_serdes_regs.h
deleted file mode 100644
index 1af7a918e215..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_serdes_regs.h
+++ /dev/null
@@ -1,495 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_serdes_regs.h
- *
- * @brief ... registers
- *
- */
-
-#ifndef __AL_HAL_SERDES_REGS_H__
-#define __AL_HAL_SERDES_REGS_H__
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-struct serdes_gen {
-	/* [0x0] SerDes Registers Version */
-	uint32_t version;
-	uint32_t rsrvd_0[3];
-	/* [0x10] SerDes register file address */
-	uint32_t reg_addr;
-	/* [0x14] SerDes register file data */
-	uint32_t reg_data;
-	uint32_t rsrvd_1[2];
-	/* [0x20] SerDes control */
-	uint32_t ictl_multi_bist;
-	/* [0x24] SerDes control */
-	uint32_t ictl_pcs;
-	/* [0x28] SerDes control */
-	uint32_t ictl_pma;
-	uint32_t rsrvd_2;
-	/* [0x30] SerDes control */
-	uint32_t ipd_multi_synth;
-	/* [0x34] SerDes control */
-	uint32_t irst;
-	/* [0x38] SerDes control */
-	uint32_t octl_multi_synthready;
-	/* [0x3c] SerDes control */
-	uint32_t octl_multi_synthstatus;
-	/* [0x40] SerDes control */
-	uint32_t clk_out;
-	uint32_t rsrvd[47];
-};
-struct serdes_lane {
-	uint32_t rsrvd1[4];
-	/* [0x10] SerDes status */
-	uint32_t octl_pma;
-	/* [0x14] SerDes control */
-	uint32_t ictl_multi_andme;
-	/* [0x18] SerDes control */
-	uint32_t ictl_multi_lb;
-	/* [0x1c] SerDes control */
-	uint32_t ictl_multi_rxbist;
-	/* [0x20] SerDes control */
-	uint32_t ictl_multi_txbist;
-	/* [0x24] SerDes control */
-	uint32_t ictl_multi;
-	/* [0x28] SerDes control */
-	uint32_t ictl_multi_rxeq;
-	/* [0x2c] SerDes control */
-	uint32_t ictl_multi_rxeq_l_low;
-	/* [0x30] SerDes control */
-	uint32_t ictl_multi_rxeq_l_high;
-	/* [0x34] SerDes control */
-	uint32_t ictl_multi_rxeyediag;
-	/* [0x38] SerDes control */
-	uint32_t ictl_multi_txdeemph;
-	/* [0x3c] SerDes control */
-	uint32_t ictl_multi_txmargin;
-	/* [0x40] SerDes control */
-	uint32_t ictl_multi_txswing;
-	/* [0x44] SerDes control */
-	uint32_t idat_multi;
-	/* [0x48] SerDes control */
-	uint32_t ipd_multi;
-	/* [0x4c] SerDes control */
-	uint32_t octl_multi_rxbist;
-	/* [0x50] SerDes control */
-	uint32_t octl_multi;
-	/* [0x54] SerDes control */
-	uint32_t octl_multi_rxeyediag;
-	/* [0x58] SerDes control */
-	uint32_t odat_multi_rxbist;
-	/* [0x5c] SerDes control */
-	uint32_t odat_multi_rxeq;
-	/* [0x60] SerDes control */
-	uint32_t multi_rx_dvalid;
-	/* [0x64] SerDes control */
-	uint32_t reserved;
-	uint32_t rsrvd[6];
-};
-
-struct al_serdes_regs {
-	uint32_t rsrvd_0[64];
-	struct serdes_gen gen;                               /* [0x100] */
-	struct serdes_lane lane[4];                          /* [0x200] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** version register ****/
-/*  Revision number (Minor) */
-#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
-#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
-/*  Revision number (Major) */
-#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
-#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
-/*  Date of release */
-#define SERDES_GEN_VERSION_DATE_DAY_MASK 0x001F0000
-#define SERDES_GEN_VERSION_DATE_DAY_SHIFT 16
-/*  Month of release */
-#define SERDES_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
-#define SERDES_GEN_VERSION_DATA_MONTH_SHIFT 21
-/* Year of release (starting from 2000) */
-#define SERDES_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
-#define SERDES_GEN_VERSION_DATE_YEAR_SHIFT 25
-/*  Reserved */
-#define SERDES_GEN_VERSION_RESERVED_MASK 0xC0000000
-#define SERDES_GEN_VERSION_RESERVED_SHIFT 30
-
-/**** reg_addr register ****/
-/* Address value */
-#define SERDES_GEN_REG_ADDR_VAL_MASK     0x0000FFFF
-#define SERDES_GEN_REG_ADDR_VAL_SHIFT    0
-
-/**** reg_data register ****/
-/* Data value */
-#define SERDES_GEN_REG_DATA_VAL_MASK     0x000000FF
-#define SERDES_GEN_REG_DATA_VAL_SHIFT    0
-
-/**** ICTL_MULTI_BIST register ****/
-
-#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_MASK 0x00000007
-#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_SHIFT 0
-
-/**** ICTL_PCS register ****/
-
-#define SERDES_GEN_ICTL_PCS_EN_NT        (1 << 0)
-
-/**** ICTL_PMA register ****/
-
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_MASK 0x00000007
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT 0
-
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_REF \
-	(0 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_R2L \
-	(3 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_L2R \
-	(4 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
-
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_MASK 0x00000070
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT 4
-
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_0 \
-	(0 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_REF \
-	(2 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_R2L \
-	(3 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
-
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_MASK 0x00000700
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT 8
-
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_0 \
-	(0 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_REF \
-	(2 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
-#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_L2R \
-	(3 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
-
-#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC		(1 << 11)
-#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_THIS		(0 << 11)
-#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_MASTER	(1 << 11)
-
-#define SERDES_GEN_ICTL_PMA_TXENABLE_A   (1 << 12)
-
-#define SERDES_GEN_ICTL_PMA_SYNTHCKBYPASSEN_NT (1 << 13)
-
-/**** IPD_MULTI_SYNTH register ****/
-
-#define SERDES_GEN_IPD_MULTI_SYNTH_B     (1 << 0)
-
-/**** IRST register ****/
-
-#define SERDES_GEN_IRST_PIPE_RST_L3_B_A  (1 << 0)
-
-#define SERDES_GEN_IRST_PIPE_RST_L2_B_A  (1 << 1)
-
-#define SERDES_GEN_IRST_PIPE_RST_L1_B_A  (1 << 2)
-
-#define SERDES_GEN_IRST_PIPE_RST_L0_B_A  (1 << 3)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A (1 << 4)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A (1 << 5)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A (1 << 6)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A (1 << 7)
-
-#define SERDES_GEN_IRST_MULTI_HARD_SYNTH_B_A (1 << 8)
-
-#define SERDES_GEN_IRST_POR_B_A          (1 << 12)
-
-#define SERDES_GEN_IRST_PIPE_RST_L3_B_A_SEL (1 << 16)
-
-#define SERDES_GEN_IRST_PIPE_RST_L2_B_A_SEL (1 << 17)
-
-#define SERDES_GEN_IRST_PIPE_RST_L1_B_A_SEL (1 << 18)
-
-#define SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL (1 << 19)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A_SEL (1 << 20)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A_SEL (1 << 21)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A_SEL (1 << 22)
-
-#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A_SEL (1 << 23)
-
-/**** OCTL_MULTI_SYNTHREADY register ****/
-
-#define SERDES_GEN_OCTL_MULTI_SYNTHREADY_A (1 << 0)
-
-/**** OCTL_MULTI_SYNTHSTATUS register ****/
-
-#define SERDES_GEN_OCTL_MULTI_SYNTHSTATUS_A (1 << 0)
-
-/**** clk_out register ****/
-
-#define SERDES_GEN_CLK_OUT_SEL_MASK      0x0000003F
-#define SERDES_GEN_CLK_OUT_SEL_SHIFT     0
-
-/**** OCTL_PMA register ****/
-
-#define SERDES_LANE_OCTL_PMA_TXSTATUS_L_A (1 << 0)
-
-/**** ICTL_MULTI_ANDME register ****/
-
-#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A (1 << 0)
-
-#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A_SEL (1 << 1)
-
-/**** ICTL_MULTI_LB register ****/
-
-#define SERDES_LANE_ICTL_MULTI_LB_TX2RXIOTIMEDEN_L_NT (1 << 0)
-
-#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT (1 << 1)
-
-#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT (1 << 2)
-
-#define SERDES_LANE_ICTL_MULTI_LB_PARRX2TXTIMEDEN_L_NT (1 << 3)
-
-#define SERDES_LANE_ICTL_MULTI_LB_CDRCLK2TXEN_L_NT (1 << 4)
-
-#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT_SEL (1 << 8)
-
-#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT_SEL (1 << 9)
-
-/**** ICTL_MULTI_RXBIST register ****/
-
-#define SERDES_LANE_ICTL_MULTI_RXBIST_EN_L_A (1 << 0)
-
-/**** ICTL_MULTI_TXBIST register ****/
-
-#define SERDES_LANE_ICTL_MULTI_TXBIST_EN_L_A (1 << 0)
-
-/**** ICTL_MULTI register ****/
-
-#define SERDES_LANE_ICTL_MULTI_PSTATE_L_MASK 0x00000003
-#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SHIFT 0
-
-#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SEL (1 << 2)
-
-#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_MASK 0x00000070
-#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_SHIFT 4
-
-#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATAEN_L_A (1 << 8)
-
-#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATA_L_A (1 << 9)
-
-#define SERDES_LANE_ICTL_MULTI_TXBEACON_L_A (1 << 12)
-
-#define SERDES_LANE_ICTL_MULTI_TXDETECTRXREQ_L_A (1 << 13)
-
-#define SERDES_LANE_ICTL_MULTI_RXRATE_L_MASK 0x00070000
-#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SHIFT 16
-
-#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SEL (1 << 19)
-
-#define SERDES_LANE_ICTL_MULTI_TXRATE_L_MASK 0x00700000
-#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SHIFT 20
-
-#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SEL (1 << 23)
-
-#define SERDES_LANE_ICTL_MULTI_TXAMP_L_MASK 0x07000000
-#define SERDES_LANE_ICTL_MULTI_TXAMP_L_SHIFT 24
-
-#define SERDES_LANE_ICTL_MULTI_TXAMP_EN_L (1 << 27)
-
-#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_MASK 0x70000000
-#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_SHIFT 28
-
-/**** ICTL_MULTI_RXEQ register ****/
-
-#define SERDES_LANE_ICTL_MULTI_RXEQ_EN_L (1 << 0)
-
-#define SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A (1 << 1)
-
-#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_MASK 0x00000070
-#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_SHIFT 4
-
-/**** ICTL_MULTI_RXEQ_L_high register ****/
-
-#define SERDES_LANE_ICTL_MULTI_RXEQ_L_HIGH_VAL (1 << 0)
-
-/**** ICTL_MULTI_RXEYEDIAG register ****/
-
-#define SERDES_LANE_ICTL_MULTI_RXEYEDIAG_START_L_A (1 << 0)
-
-/**** ICTL_MULTI_TXDEEMPH register ****/
-
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_MASK 0x0003FFFF
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_SHIFT 0
-
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_MASK	0x7c0
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_SHIFT	6
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_MASK	0xf000
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_SHIFT	12
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_MASK	0x7
-#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_SHIFT	0
-
-/**** ICTL_MULTI_TXMARGIN register ****/
-
-#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_MASK 0x00000007
-#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_SHIFT 0
-
-/**** ICTL_MULTI_TXSWING register ****/
-
-#define SERDES_LANE_ICTL_MULTI_TXSWING_L (1 << 0)
-
-/**** IDAT_MULTI register ****/
-
-#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_MASK 0x0000000F
-#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SHIFT 0
-
-#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SEL (1 << 4)
-
-/**** IPD_MULTI register ****/
-
-#define SERDES_LANE_IPD_MULTI_TX_L_B     (1 << 0)
-
-#define SERDES_LANE_IPD_MULTI_RX_L_B     (1 << 1)
-
-/**** OCTL_MULTI_RXBIST register ****/
-
-#define SERDES_LANE_OCTL_MULTI_RXBIST_DONE_L_A (1 << 0)
-
-#define SERDES_LANE_OCTL_MULTI_RXBIST_RXLOCKED_L_A (1 << 1)
-
-/**** OCTL_MULTI register ****/
-
-#define SERDES_LANE_OCTL_MULTI_RXCDRLOCK2DATA_L_A (1 << 0)
-
-#define SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A (1 << 1)
-
-#define SERDES_LANE_OCTL_MULTI_RXREADY_L_A (1 << 2)
-
-#define SERDES_LANE_OCTL_MULTI_RXSTATUS_L_A (1 << 3)
-
-#define SERDES_LANE_OCTL_MULTI_TXREADY_L_A (1 << 4)
-
-#define SERDES_LANE_OCTL_MULTI_TXDETECTRXSTAT_L_A (1 << 5)
-
-#define SERDES_LANE_OCTL_MULTI_TXDETECTRXACK_L_A (1 << 6)
-
-#define SERDES_LANE_OCTL_MULTI_RXSIGNALDETECT_L_A (1 << 7)
-
-/**** OCTL_MULTI_RXEYEDIAG register ****/
-
-#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_MASK 0x00003FFF
-#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_SHIFT 0
-
-#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_DONE_L_A (1 << 16)
-
-#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_ERR_L_A (1 << 17)
-
-/**** ODAT_MULTI_RXBIST register ****/
-
-#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_MASK 0x0000FFFF
-#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_SHIFT 0
-
-#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_OVERFLOW_L_A (1 << 16)
-
-/**** ODAT_MULTI_RXEQ register ****/
-
-#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_MASK 0x00003FFF
-#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_SHIFT 0
-
-/**** MULTI_RX_DVALID register ****/
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_CDR_LOCK (1 << 0)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_SIGNALDETECT (1 << 1)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_TX_READY (1 << 2)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_READY (1 << 3)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_SYNT_READY (1 << 4)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_ELECIDLE (1 << 5)
-
-#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_MASK 0x00FF0000
-#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_SHIFT 16
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_00_SEL (1 << 24)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_00_VAL (1 << 25)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_01_SEL (1 << 26)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_01_VAL (1 << 27)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_10_SEL (1 << 28)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_10_VAL (1 << 29)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_11_SEL (1 << 30)
-
-#define SERDES_LANE_MULTI_RX_DVALID_PS_11_VAL (1 << 31)
-
-/**** reserved register ****/
-
-#define SERDES_LANE_RESERVED_OUT_MASK    0x000000FF
-#define SERDES_LANE_RESERVED_OUT_SHIFT   0
-
-#define SERDES_LANE_RESERVED_IN_MASK     0x00FF0000
-#define SERDES_LANE_RESERVED_IN_SHIFT    16
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_serdes_REGS_H__ */
-
-/** @} end of ... group */
-
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_types.h b/sys/contrib/alpine-hal/eth/al_hal_types.h
deleted file mode 100644
index cea839dcfdcc..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_types.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_common HAL Common Layer
- *  @{
- * @file   al_hal_types.h
- *
- * @brief  macros used by HALs and platform layer
- *
- */
-
-#ifndef __AL_HAL_TYPES_H__
-#define __AL_HAL_TYPES_H__
-
-#include "al_hal_plat_types.h"
-#include "al_hal_plat_services.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/* Common defines */
-
-#if (!AL_TRUE) || (AL_FALSE)
-#error "AL_TRUE must be non zero and AL_FALSE must be zero"
-#endif
-
-typedef int AL_RETURN;
-
-#if !defined(NULL)
-#define NULL		(void *)0
-#endif
-
-#if !defined(likely)
-#define likely(x)	(__builtin_expect(!!(x), 1))
-#define unlikely(x)	(__builtin_expect(!!(x), 0))
-#endif
-
-
-#ifdef __GNUC__
-#if !defined(__packed)
-#define __packed __attribute__ ((packed))
-#endif
-  /* packed and alinged types */
-#define __packed_a4 __attribute__ ((packed, aligned(4)))
-#define __packed_a8 __attribute__ ((packed, aligned(8)))
-#define __packed_a16 __attribute__ ((packed, aligned(16)))
-
-#else
-#if !defined(__packed)
-#error "__packed is not defined!!"
-#endif
-#endif
-
-#if !defined(__iomem)
-#define __iomem
-#endif
-
-#if !defined(__cache_aligned)
-#ifdef __GNUC__
-#define __cache_aligned __attribute__ ((__aligned__(64)))
-#else
-#define __cache_aligned
-#endif
-#endif
-
-#if !defined(INLINE)
-#ifdef __GNUC__
-#define INLINE inline
-#else
-#define INLINE
-#endif
-#endif
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-/** @} end of Common group */
-#endif				/* __TYPES_H__ */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma.h b/sys/contrib/alpine-hal/eth/al_hal_udma.h
deleted file mode 100644
index a1bdb4fe8dbb..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma.h
+++ /dev/null
@@ -1,672 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_udma_api API
- * @ingroup group_udma
- * UDMA API
- * @{
- * @}
- *
- * @defgroup group_udma_main UDMA Main
- * @ingroup group_udma_api
- * UDMA main API
- * @{
- * @file   al_hal_udma.h
- *
- * @brief C Header file for the Universal DMA HAL driver
- *
- */
-
-#ifndef __AL_HAL_UDMA_H__
-#define __AL_HAL_UDMA_H__
-
-#include "al_hal_common.h"
-#include "al_hal_udma_regs.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#define DMA_MAX_Q 	4
-#define AL_UDMA_MIN_Q_SIZE 	4
-#define AL_UDMA_MAX_Q_SIZE 	(1 << 16) /* hw can do more, but we limit it */
-
-/* Default Max number of descriptors supported per action */
-#define AL_UDMA_DEFAULT_MAX_ACTN_DESCS	16
-
-#define AL_UDMA_REV_ID_0	0
-#define AL_UDMA_REV_ID_1	1
-#define AL_UDMA_REV_ID_2	2
-
-#define DMA_RING_ID_MASK	0x3
-/* New registers ?? */
-/* Statistics - TBD */
-
-/** UDMA submission descriptor */
-union al_udma_desc {
-	/* TX */
-	struct {
-		uint32_t len_ctrl;
-		uint32_t meta_ctrl;
-		uint64_t buf_ptr;
-	} tx;
-	/* TX Meta, used by upper layer */
-	struct {
-		uint32_t len_ctrl;
-		uint32_t meta_ctrl;
-		uint32_t meta1;
-		uint32_t meta2;
-	} tx_meta;
-	/* RX */
-	struct {
-		uint32_t len_ctrl;
-		uint32_t buf2_ptr_lo;
-		uint64_t buf1_ptr;
-	} rx;
-} __packed_a16;
-
-/* TX desc length and control fields */
-
-#define AL_M2S_DESC_CONCAT			AL_BIT(31)	/* concatenate */
-#define AL_M2S_DESC_DMB				AL_BIT(30)
-						/** Data Memory Barrier */
-#define AL_M2S_DESC_NO_SNOOP_H			AL_BIT(29)
-#define AL_M2S_DESC_INT_EN			AL_BIT(28)	/** enable interrupt */
-#define AL_M2S_DESC_LAST			AL_BIT(27)
-#define AL_M2S_DESC_FIRST			AL_BIT(26)
-#define AL_M2S_DESC_RING_ID_SHIFT		24
-#define AL_M2S_DESC_RING_ID_MASK		(0x3 << AL_M2S_DESC_RING_ID_SHIFT)
-#define AL_M2S_DESC_META_DATA			AL_BIT(23)
-#define AL_M2S_DESC_DUMMY			AL_BIT(22) /* for Metdata only */
-#define AL_M2S_DESC_LEN_ADJ_SHIFT		20
-#define AL_M2S_DESC_LEN_ADJ_MASK		(0x7 << AL_M2S_DESC_LEN_ADJ_SHIFT)
-#define AL_M2S_DESC_LEN_SHIFT			0
-#define AL_M2S_DESC_LEN_MASK			(0xfffff << AL_M2S_DESC_LEN_SHIFT)
-
-#define AL_S2M_DESC_DUAL_BUF			AL_BIT(31)
-#define AL_S2M_DESC_NO_SNOOP_H			AL_BIT(29)
-#define AL_S2M_DESC_INT_EN			AL_BIT(28)	/** enable interrupt */
-#define AL_S2M_DESC_RING_ID_SHIFT		24
-#define AL_S2M_DESC_RING_ID_MASK		(0x3 << AL_S2M_DESC_RING_ID_SHIFT)
-#define AL_S2M_DESC_LEN_SHIFT			0
-#define AL_S2M_DESC_LEN_MASK			(0xffff << AL_S2M_DESC_LEN_SHIFT)
-#define AL_S2M_DESC_LEN2_SHIFT			16
-#define AL_S2M_DESC_LEN2_MASK			(0x3fff << AL_S2M_DESC_LEN2_SHIFT)
-#define AL_S2M_DESC_LEN2_GRANULARITY_SHIFT	6
-
-/* TX/RX descriptor VMID field (in the buffer address 64 bit field) */
-#define AL_UDMA_DESC_VMID_SHIFT		48
-
-/** UDMA completion descriptor */
-union al_udma_cdesc {
-	/* TX completion */
-	struct {
-		uint32_t ctrl_meta;
-	} al_desc_comp_tx;
-	/* RX completion */
-	struct {
-		/* TBD */
-		uint32_t ctrl_meta;
-	} al_desc_comp_rx;
-} __packed_a4;
-
-/* TX/RX common completion desc ctrl_meta feilds */
-#define AL_UDMA_CDESC_ERROR		AL_BIT(31)
-#define AL_UDMA_CDESC_BUF1_USED		AL_BIT(30)
-#define AL_UDMA_CDESC_DDP		AL_BIT(29)
-#define AL_UDMA_CDESC_LAST		AL_BIT(27)
-#define AL_UDMA_CDESC_FIRST		AL_BIT(26)
-/* word 2 */
-#define AL_UDMA_CDESC_BUF2_USED			AL_BIT(31)
-#define AL_UDMA_CDESC_BUF2_LEN_SHIFT	16
-#define AL_UDMA_CDESC_BUF2_LEN_MASK		AL_FIELD_MASK(29, 16)
-/** Basic Buffer structure */
-struct al_buf {
-	al_phys_addr_t addr; /**< Buffer physical address */
-	uint32_t len; /**< Buffer lenght in bytes */
-};
-
-/** Block is a set of buffers that belong to same source or destination */
-struct al_block {
-	struct al_buf *bufs; /**< The buffers of the block */
-	uint32_t num; /**< Number of buffers of the block */
-
-	/**<
-	 * VMID to be assigned to the block descriptors
-	 * Requires VMID in descriptor to be enabled for the specific UDMA
-	 * queue.
-	 */
-	uint16_t vmid;
-};
-
-/** UDMA type */
-enum al_udma_type {
-	UDMA_TX,
-	UDMA_RX
-};
-
-/** UDMA state */
-enum al_udma_state {
-	UDMA_DISABLE = 0,
-	UDMA_IDLE,
-	UDMA_NORMAL,
-	UDMA_ABORT,
-	UDMA_RESET
-};
-
-extern const char *const al_udma_states_name[];
-
-/** UDMA Q specific parameters from upper layer */
-struct al_udma_q_params {
-	uint32_t size;		/**< ring size (in descriptors), submission and
-				 * completion rings must have same size
-				 */
-	union al_udma_desc *desc_base; /**< cpu address for submission ring
-					 * descriptors
-					 */
-	al_phys_addr_t desc_phy_base;	/**< submission ring descriptors
-					 * physical base address
-					 */
-#ifdef __FreeBSD__
-	bus_dma_tag_t desc_phy_base_tag;
-	bus_dmamap_t desc_phy_base_map;
-#endif
-	uint8_t *cdesc_base;	/**< completion descriptors pointer, NULL */
-				/* means no completion update */
-	al_phys_addr_t cdesc_phy_base;	/**< completion descriptors ring
-					 * physical base address
-					 */
-#ifdef __FreeBSD__
-	bus_dma_tag_t cdesc_phy_base_tag;
-	bus_dmamap_t cdesc_phy_base_map;
-#endif
-	uint32_t cdesc_size;	/**< size (in bytes) of a single dma completion
-					* descriptor
-					*/
-
-	uint8_t adapter_rev_id; /**<PCI adapter revision ID */
-};
-
-/** UDMA parameters from upper layer */
-struct al_udma_params {
-	struct unit_regs __iomem *udma_regs_base;
-	enum al_udma_type type;	/**< Tx or Rx */
-	uint8_t num_of_queues; /**< number of queues supported by the UDMA */
-	const char *name; /**< the upper layer must keep the string area */
-};
-
-/* Fordward decleration */
-struct al_udma;
-
-/** SW status of a queue */
-enum al_udma_queue_status {
-	AL_QUEUE_NOT_INITIALIZED = 0,
-	AL_QUEUE_DISABLED,
-	AL_QUEUE_ENABLED,
-	AL_QUEUE_ABORTED
-};
-
-/** UDMA Queue private data structure */
-struct __cache_aligned al_udma_q {
-	uint16_t size_mask;		/**< mask used for pointers wrap around
-					 * equals to size - 1
-					 */
-	union udma_q_regs __iomem *q_regs; /**< pointer to the per queue UDMA
-					   * registers
-					   */
-	union al_udma_desc *desc_base_ptr; /**< base address submission ring
-						* descriptors
-						*/
-	uint16_t next_desc_idx; /**< index to the next available submission
-				      * descriptor
-				      */
-
-	uint32_t desc_ring_id;	/**< current submission ring id */
-
-	uint8_t *cdesc_base_ptr;/**< completion descriptors pointer, NULL */
-				/* means no completion */
-	uint32_t cdesc_size;	/**< size (in bytes) of the udma completion ring
-				 * descriptor
-				 */
-	uint16_t next_cdesc_idx; /**< index in descriptors for next completing
-			      * ring descriptor
-			      */
-	uint8_t *end_cdesc_ptr;	/**< used for wrap around detection */
-	uint16_t comp_head_idx; /**< completion ring head pointer register
-				 *shadow
-				 */
-	volatile union al_udma_cdesc *comp_head_ptr; /**< when working in get_packet mode
-				       * we maintain pointer instead of the
-				       * above idx
-				       */
-
-	uint32_t pkt_crnt_descs; /**< holds the number of processed descriptors
-				  * of the current packet
-				  */
-	uint32_t comp_ring_id;	/**< current completion Ring Id */
-
-
-	al_phys_addr_t desc_phy_base; /**< submission desc. physical base */
-	al_phys_addr_t cdesc_phy_base; /**< completion desc. physical base */
-
-	uint32_t flags; /**< flags used for completion modes */
-	uint32_t size;		/**< ring size in descriptors  */
-	enum al_udma_queue_status status;
-	struct al_udma *udma;	/**< pointer to parent UDMA */
-	uint32_t qid;		/**< the index number of the queue */
-
-	/*
-	 * The following fields are duplicated from the UDMA parent adapter
-	 * due to performance considerations.
-	 */
-	uint8_t adapter_rev_id; /**<PCI adapter revision ID */
-};
-
-/* UDMA */
-struct al_udma {
-	const char *name;
-	enum al_udma_type type;	/* Tx or Rx */
-	enum al_udma_state state;
-	uint8_t num_of_queues; /* number of queues supported by the UDMA */
-	union udma_regs __iomem *udma_regs; /* pointer to the UDMA registers */
-	struct udma_gen_regs *gen_regs;		/* pointer to the Gen registers*/
-	struct al_udma_q udma_q[DMA_MAX_Q];	/* Array of UDMA Qs pointers */
-	unsigned int rev_id; /* UDMA revision ID */
-};
-
-
-/*
- * Configurations
- */
-
-/* Initializations functions */
-/**
- * Initialize the udma engine
- *
- * @param udma udma data structure
- * @param udma_params udma parameters from upper layer
- *
- * @return 0 on success. -EINVAL otherwise.
- */
-int al_udma_init(struct al_udma *udma, struct al_udma_params *udma_params);
-
-/**
- * Initialize the udma queue data structure
- *
- * @param udma
- * @param qid
- * @param q_params
- *
- * @return 0 if no error found.
- *	   -EINVAL if the qid is out of range
- *	   -EIO if queue was already initialized
- */
-
-int al_udma_q_init(struct al_udma *udma, uint32_t qid,
-		   struct al_udma_q_params *q_params);
-
-/**
- * Reset a udma queue
- *
- * Prior to calling this function make sure:
- * 1. Queue interrupts are masked
- * 2. No additional descriptors are written to the descriptor ring of the queue
- * 3. No completed descriptors are being fetched
- *
- * The queue can be initialized again using 'al_udma_q_init'
- *
- * @param udma_q
- *
- * @return 0 if no error found.
- */
-
-int al_udma_q_reset(struct al_udma_q *udma_q);
-
-/**
- * return (by reference) a pointer to a specific queue date structure.
- * this pointer needed for calling functions (i.e. al_udma_desc_action_add) that
- * require this pointer as input argument.
- *
- * @param udma udma data structure
- * @param qid queue index
- * @param q_handle pointer to the location where the queue structure pointer
- * written to.
- *
- * @return  0 on success. -EINVAL otherwise.
- */
-int al_udma_q_handle_get(struct al_udma *udma, uint32_t qid,
-		      struct al_udma_q **q_handle);
-
-/**
- * Change the UDMA's state
- *
- * @param udma udma data structure
- * @param state the target state
- *
- * @return 0
- */
-int al_udma_state_set(struct al_udma *udma, enum al_udma_state state);
-
-/**
- * return the current UDMA hardware state
- *
- * @param udma udma handle
- *
- * @return the UDMA state as reported by the hardware.
- */
-enum al_udma_state al_udma_state_get(struct al_udma *udma);
-
-/*
- * Action handling
- */
-
-/**
- * get number of descriptors that can be submitted to the udma.
- * keep one free descriptor to simplify full/empty management
- * @param udma_q queue handle
- *
- * @return num of free descriptors.
- */
-static INLINE uint32_t al_udma_available_get(struct al_udma_q *udma_q)
-{
-	uint16_t tmp = udma_q->next_cdesc_idx - (udma_q->next_desc_idx + 1);
-	tmp &= udma_q->size_mask;
-
-	return (uint32_t) tmp;
-}
-
-/**
- * check if queue has pending descriptors
- *
- * @param udma_q queue handle
- *
- * @return AL_TRUE if descriptors are submitted to completion ring and still
- * not completed (with ack). AL_FALSE otherwise.
- */
-static INLINE al_bool al_udma_is_empty(struct al_udma_q *udma_q)
-{
-	if (((udma_q->next_cdesc_idx - udma_q->next_desc_idx) &
-	     udma_q->size_mask) == 0)
-		return AL_TRUE;
-
-	return AL_FALSE;
-}
-
-/**
- * get next available descriptor
- * @param udma_q queue handle
- *
- * @return pointer to the next available descriptor
- */
-static INLINE union al_udma_desc *al_udma_desc_get(struct al_udma_q *udma_q)
-{
-	union al_udma_desc *desc;
-	uint16_t next_desc_idx;
-
-	al_assert(udma_q);
-
-	next_desc_idx = udma_q->next_desc_idx;
-	desc = udma_q->desc_base_ptr + next_desc_idx;
-
-	next_desc_idx++;
-
-	/* if reached end of queue, wrap around */
-	udma_q->next_desc_idx = next_desc_idx & udma_q->size_mask;
-
-	return desc;
-}
-
-/**
- * get ring id for the last allocated descriptor
- * @param udma_q
- *
- * @return ring id for the last allocated descriptor
- * this function must be called each time a new descriptor is allocated
- * by the al_udma_desc_get(), unless ring id is ignored.
- */
-static INLINE uint32_t al_udma_ring_id_get(struct al_udma_q *udma_q)
-{
-	uint32_t ring_id;
-
-	al_assert(udma_q);
-
-	ring_id = udma_q->desc_ring_id;
-
-	/* calculate the ring id of the next desc */
-	/* if next_desc points to first desc, then queue wrapped around */
-	if (unlikely(udma_q->next_desc_idx) == 0)
-		udma_q->desc_ring_id = (udma_q->desc_ring_id + 1) &
-			DMA_RING_ID_MASK;
-	return ring_id;
-}
-
-/* add DMA action - trigger the engine */
-/**
- * add num descriptors to the submission queue.
- *
- * @param udma_q queue handle
- * @param num number of descriptors to add to the queues ring.
- *
- * @return 0;
- */
-static INLINE int al_udma_desc_action_add(struct al_udma_q *udma_q,
-					  uint32_t num)
-{
-	uint32_t *addr;
-
-	al_assert(udma_q);
-	al_assert((num > 0) && (num <= udma_q->size));
-
-	addr = &udma_q->q_regs->rings.drtp_inc;
-	/* make sure data written to the descriptors will be visible by the */
-	/* DMA */
-	al_local_data_memory_barrier();
-
-	/*
-	 * As we explicitly invoke the synchronization function
-	 * (al_data_memory_barrier()), then we can use the relaxed version.
-	 */
-	al_reg_write32_relaxed(addr, num);
-
-	return 0;
-}
-
-#define cdesc_is_first(flags) ((flags) & AL_UDMA_CDESC_FIRST)
-#define cdesc_is_last(flags) ((flags) & AL_UDMA_CDESC_LAST)
-
-/**
- * return pointer to the cdesc + offset desciptors. wrap around when needed.
- *
- * @param udma_q queue handle
- * @param cdesc pointer that set by this function
- * @param offset offset desciptors
- *
- */
-static INLINE volatile union al_udma_cdesc *al_cdesc_next(
-	struct al_udma_q		*udma_q,
-	volatile union al_udma_cdesc	*cdesc,
-	uint32_t			offset)
-{
-	volatile uint8_t *tmp = (volatile uint8_t *) cdesc + offset * udma_q->cdesc_size;
-	al_assert(udma_q);
-	al_assert(cdesc);
-
-	/* if wrap around */
-	if (unlikely((tmp > udma_q->end_cdesc_ptr)))
-		return (union al_udma_cdesc *)
-			(udma_q->cdesc_base_ptr +
-			(tmp - udma_q->end_cdesc_ptr - udma_q->cdesc_size));
-
-	return (volatile union al_udma_cdesc *) tmp;
-}
-
-/**
- * check if the flags of the descriptor indicates that is new one
- * the function uses the ring id from the descriptor flags to know whether it
- * new one by comparing it with the curring ring id of the queue
- *
- * @param udma_q queue handle
- * @param flags the flags of the completion descriptor
- *
- * @return AL_TRUE if the completion descriptor is new one.
- * 	AL_FALSE if it old one.
- */
-static INLINE al_bool al_udma_new_cdesc(struct al_udma_q *udma_q,
-								uint32_t flags)
-{
-	if (((flags & AL_M2S_DESC_RING_ID_MASK) >> AL_M2S_DESC_RING_ID_SHIFT)
-	    == udma_q->comp_ring_id)
-		return AL_TRUE;
-	return AL_FALSE;
-}
-
-/**
- * get next completion descriptor
- * this function will also increment the completion ring id when the ring wraps
- * around
- *
- * @param udma_q queue handle
- * @param cdesc current completion descriptor
- *
- * @return pointer to the completion descriptor that follows the one pointed by
- * cdesc
- */
-static INLINE volatile union al_udma_cdesc *al_cdesc_next_update(
-	struct al_udma_q		*udma_q,
-	volatile union al_udma_cdesc	*cdesc)
-{
-	/* if last desc, wrap around */
-	if (unlikely(((volatile uint8_t *) cdesc == udma_q->end_cdesc_ptr))) {
-		udma_q->comp_ring_id =
-		    (udma_q->comp_ring_id + 1) & DMA_RING_ID_MASK;
-		return (union al_udma_cdesc *) udma_q->cdesc_base_ptr;
-	}
-	return (volatile union al_udma_cdesc *) ((volatile uint8_t *) cdesc + udma_q->cdesc_size);
-}
-
-/**
- * get next completed packet from completion ring of the queue
- *
- * @param udma_q udma queue handle
- * @param desc pointer that set by this function to the first descriptor
- * note: desc is valid only when return value is not zero
- * @return number of descriptors that belong to the packet. 0 means no completed
- * full packet was found.
- * If the descriptors found in the completion queue don't form full packet (no
- * desc with LAST flag), then this function will do the following:
- * (1) save the number of processed descriptors.
- * (2) save last processed descriptor, so next time it called, it will resume
- *     from there.
- * (3) return 0.
- * note: the descriptors that belong to the completed packet will still be
- * considered as used, that means the upper layer is safe to access those
- * descriptors when this function returns. the al_udma_cdesc_ack() should be
- * called to inform the udma driver that those descriptors are freed.
- */
-uint32_t al_udma_cdesc_packet_get(
-	struct al_udma_q		*udma_q,
-	volatile union al_udma_cdesc	**desc);
-
-/** get completion descriptor pointer from its index */
-#define al_udma_cdesc_idx_to_ptr(udma_q, idx)				\
-	((volatile union al_udma_cdesc *) ((udma_q)->cdesc_base_ptr +	\
-				(idx) * (udma_q)->cdesc_size))
-
-
-/**
- * return number of all completed descriptors in the completion ring
- *
- * @param udma_q udma queue handle
- * @param cdesc pointer that set by this function to the first descriptor
- * note: desc is valid only when return value is not zero
- * note: pass NULL if not interested
- * @return number of descriptors. 0 means no completed descriptors were found.
- * note: the descriptors that belong to the completed packet will still be
- * considered as used, that means the upper layer is safe to access those
- * descriptors when this function returns. the al_udma_cdesc_ack() should be
- * called to inform the udma driver that those descriptors are freed.
- */
-static INLINE uint32_t al_udma_cdesc_get_all(
-	struct al_udma_q		*udma_q,
-	volatile union al_udma_cdesc	**cdesc)
-{
-	uint16_t count = 0;
-
-	al_assert(udma_q);
-
-	udma_q->comp_head_idx = (uint16_t)
-				(al_reg_read32(&udma_q->q_regs->rings.crhp) &
-						0xFFFF);
-
-	count = (udma_q->comp_head_idx - udma_q->next_cdesc_idx) &
-		udma_q->size_mask;
-
-	if (cdesc)
-		*cdesc = al_udma_cdesc_idx_to_ptr(udma_q, udma_q->next_cdesc_idx);
-
-	return (uint32_t)count;
-}
-
-/**
- * acknowledge the driver that the upper layer completed processing completion
- * descriptors
- *
- * @param udma_q udma queue handle
- * @param num number of descriptors to acknowledge
- *
- * @return 0
- */
-static INLINE int al_udma_cdesc_ack(struct al_udma_q *udma_q, uint32_t num)
-{
-	al_assert(udma_q);
-
-	udma_q->next_cdesc_idx += num;
-	udma_q->next_cdesc_idx &= udma_q->size_mask;
-
-	return 0;
-}
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-
-#endif /* __AL_HAL_UDMA_H__ */
-/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_config.c b/sys/contrib/alpine-hal/eth/al_hal_udma_config.c
deleted file mode 100644
index a06f78983080..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_config.c
+++ /dev/null
@@ -1,1373 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @file   al_hal_udma_config.c
- *
- * @brief  Universal DMA HAL driver for configurations
- *
- */
-
-#include <al_hal_common.h>
-#include <al_hal_udma_regs.h>
-#include <al_hal_udma_config.h>
-
-/**************** Misc configurations *********************/
-/** Configure AXI generic configuration */
-int al_udma_axi_set(struct udma_gen_axi *axi_regs,
-					struct al_udma_axi_conf *axi)
-{
-        uint32_t reg;
-
-        al_reg_write32(&axi_regs->cfg_1, axi->axi_timeout);
-
-        reg = al_reg_read32(&axi_regs->cfg_2);
-        reg &= ~UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK;
-        reg |= axi->arb_promotion;
-        al_reg_write32(&axi_regs->cfg_2, reg);
-
-        reg = al_reg_read32(&axi_regs->endian_cfg);
-        if (axi->swap_8_bytes == AL_TRUE)
-                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN;
-        else
-                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN;
-
-        if (axi->swap_s2m_data == AL_TRUE)
-                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA;
-        else
-                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA;
-
-        if (axi->swap_s2m_desc == AL_TRUE)
-                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC;
-        else
-                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC;
-
-        if (axi->swap_m2s_data == AL_TRUE)
-                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA;
-        else
-                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA;
-
-        if (axi->swap_m2s_desc == AL_TRUE)
-                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC;
-        else
-                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC;
-
-        al_reg_write32(&axi_regs->endian_cfg, reg);
-        return 0;
-}
-
-/* Configure UDMA AXI M2S configuration */
-/** Configure AXI M2S submaster */
-static int al_udma_m2s_axi_sm_set(struct al_udma_axi_submaster *m2s_sm,
-				      uint32_t *cfg_1, uint32_t *cfg_2,
-				      uint32_t *cfg_max_beats)
-{
-	uint32_t reg;
-	reg = al_reg_read32(cfg_1);
-	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK;
-	reg |= m2s_sm->id & UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK;
-	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK;
-	reg |= (m2s_sm->cache_type <<
-			UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_SHIFT) &
-		UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK;
-	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK;
-	reg |= (m2s_sm->burst << UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_SHIFT) &
-		UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK;
-	al_reg_write32(cfg_1, reg);
-
-	reg = al_reg_read32(cfg_2);
-	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK;
-	reg |= m2s_sm->used_ext & UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK;
-	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK;
-	reg |= (m2s_sm->bus_size <<
-			UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_SHIFT) &
-		UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK;
-	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK;
-	reg |= (m2s_sm->qos << UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_SHIFT) &
-		UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK;
-	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK;
-	reg |= (m2s_sm->prot << UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_SHIFT) &
-		UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK;
-	al_reg_write32(cfg_2, reg);
-
-	reg = al_reg_read32(cfg_max_beats);
-	reg &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
-	reg |= m2s_sm->max_beats &
-			UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
-	al_reg_write32(cfg_max_beats, reg);
-
-	return 0;
-}
-
-/** Configure UDMA AXI M2S configuration */
-int al_udma_m2s_axi_set(struct al_udma *udma,
-					struct al_udma_m2s_axi_conf *axi_m2s)
-{
-	uint32_t reg;
-
-	al_udma_m2s_axi_sm_set(&axi_m2s->comp_write,
-			       &udma->udma_regs->m2s.axi_m2s.comp_wr_cfg_1,
-			       &udma->udma_regs->m2s.axi_m2s.comp_wr_cfg_2,
-			       &udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1);
-
-	al_udma_m2s_axi_sm_set(&axi_m2s->data_read,
-			       &udma->udma_regs->m2s.axi_m2s.data_rd_cfg_1,
-			       &udma->udma_regs->m2s.axi_m2s.data_rd_cfg_2,
-			       &udma->udma_regs->m2s.axi_m2s.data_rd_cfg);
-
-	al_udma_m2s_axi_sm_set(&axi_m2s->desc_read,
-			       &udma->udma_regs->m2s.axi_m2s.desc_rd_cfg_1,
-			       &udma->udma_regs->m2s.axi_m2s.desc_rd_cfg_2,
-			       &udma->udma_regs->m2s.axi_m2s.desc_rd_cfg_3);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg);
-	if (axi_m2s->break_on_max_boundary == AL_TRUE)
-		reg |= UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY;
-	else
-		reg &= ~UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY;
-	al_reg_write32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1);
-	reg &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
-	reg |= (axi_m2s->min_axi_beats <<
-			UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT) &
-		UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
-	al_reg_write32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg);
-	reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK;
-	reg |= axi_m2s->ostand_max_data_read &
-			UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK;
-	reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK;
-	reg |= (axi_m2s->ostand_max_desc_read <<
-			UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_SHIFT) &
-		UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK;
-	reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK;
-	reg |= (axi_m2s->ostand_max_comp_req <<
-			UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_SHIFT) &
-		UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK;
-	reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK;
-	reg |= (axi_m2s->ostand_max_comp_write <<
-			UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_SHIFT) &
-		UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK;
-	al_reg_write32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg, reg);
-	return 0;
-}
-
-/** Configure AXI S2M submaster */
-static int al_udma_s2m_axi_sm_set(struct al_udma_axi_submaster *s2m_sm,
-				      uint32_t *cfg_1, uint32_t *cfg_2,
-				      uint32_t *cfg_max_beats)
-{
-	uint32_t reg;
-	reg = al_reg_read32(cfg_1);
-	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK;
-	reg |= s2m_sm->id & UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK;
-	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_MASK;
-	reg |= (s2m_sm->cache_type <<
-			UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_SHIFT) &
-		UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_MASK;
-	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_MASK;
-	reg |= (s2m_sm->burst << UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_SHIFT) &
-		UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_MASK;
-	al_reg_write32(cfg_1, reg);
-
-	reg = al_reg_read32(cfg_2);
-	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK;
-	reg |= s2m_sm->used_ext & UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK;
-	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_MASK;
-	reg |= (s2m_sm->bus_size << UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_SHIFT) &
-		UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_MASK;
-	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_MASK;
-	reg |= (s2m_sm->qos << UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_SHIFT) &
-		UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_MASK;
-	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_MASK;
-	reg |= (s2m_sm->prot << UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_SHIFT) &
-		UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_MASK;
-	al_reg_write32(cfg_2, reg);
-
-	reg = al_reg_read32(cfg_max_beats);
-	reg &= ~UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
-	reg |= s2m_sm->max_beats &
-			UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
-	al_reg_write32(cfg_max_beats, reg);
-
-	return 0;
-}
-
-/** Configure UDMA AXI S2M configuration */
-int al_udma_s2m_axi_set(struct al_udma *udma,
-				struct al_udma_s2m_axi_conf *axi_s2m)
-{
-
-	uint32_t reg;
-
-	al_udma_s2m_axi_sm_set(&axi_s2m->data_write,
-			       &udma->udma_regs->s2m.axi_s2m.data_wr_cfg_1,
-			       &udma->udma_regs->s2m.axi_s2m.data_wr_cfg_2,
-			       &udma->udma_regs->s2m.axi_s2m.data_wr_cfg);
-
-	al_udma_s2m_axi_sm_set(&axi_s2m->desc_read,
-			       &udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_4,
-			       &udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_5,
-			       &udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3);
-
-	al_udma_s2m_axi_sm_set(&axi_s2m->comp_write,
-			       &udma->udma_regs->s2m.axi_s2m.comp_wr_cfg_1,
-			       &udma->udma_regs->s2m.axi_s2m.comp_wr_cfg_2,
-			       &udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1);
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3);
-	if (axi_s2m->break_on_max_boundary == AL_TRUE)
-		reg |= UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY;
-	else
-		reg &= ~UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY;
-	al_reg_write32(&udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1);
-	reg &= ~UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
-	reg |= (axi_s2m->min_axi_beats <<
-			UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT) &
-		UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
-	al_reg_write32(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_rd);
-	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_MASK;
-	reg |= axi_s2m->ostand_max_desc_read &
-			UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_MASK;
-
-	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_MASK;
-	reg |= (axi_s2m->ack_fifo_depth <<
-			UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_SHIFT) &
-		UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_MASK;
-
-	al_reg_write32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_rd, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_wr);
-	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_MASK;
-	reg |= axi_s2m->ostand_max_data_req &
-			UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_MASK;
-	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_MASK;
-	reg |= (axi_s2m->ostand_max_data_write <<
-		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_SHIFT) &
-		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_MASK;
-	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_MASK;
-	reg |= (axi_s2m->ostand_max_comp_req <<
-			UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_SHIFT) &
-		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_MASK;
-	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_MASK;
-	reg |= (axi_s2m->ostand_max_comp_write <<
-		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_SHIFT) &
-		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_MASK;
-	al_reg_write32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_wr, reg);
-	return 0;
-}
-
-/** M2S packet len configuration */
-int al_udma_m2s_packet_size_cfg_set(struct al_udma *udma,
-				struct al_udma_m2s_pkt_len_conf *conf)
-{
-	uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s.cfg_len);
-	uint32_t max_supported_size = UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK;
-
-	al_assert(udma->type == UDMA_TX);
-
-	if (conf->encode_64k_as_zero == AL_TRUE)
-		max_supported_size += 1;	/* 64K */
-
-	if (conf->max_pkt_size > max_supported_size) {
-		al_err("udma [%s]: requested max_pkt_size (0x%x) exceeds the"
-			"supported limit (0x%x)\n", udma->name,
-			 conf->max_pkt_size, max_supported_size);
-		return -EINVAL;
-	}
-
-	reg &= ~UDMA_M2S_CFG_LEN_ENCODE_64K;
-	if (conf->encode_64k_as_zero == AL_TRUE)
-		reg |= UDMA_M2S_CFG_LEN_ENCODE_64K;
-	else
-		reg &= ~UDMA_M2S_CFG_LEN_ENCODE_64K;
-
-	reg &= ~UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK;
-	reg |= conf->max_pkt_size;
-
-	al_reg_write32(&udma->udma_regs->m2s.m2s.cfg_len, reg);
-	return 0;
-}
-
-/** Report Error - to be used for abort */
-void al_udma_err_report(struct al_udma *udma __attribute__((__unused__)))
-{
-	return;
-}
-
-/** Statistics - TBD */
-void al_udma_stats_get(struct al_udma *udma __attribute__((__unused__)))
-{
-	return;
-}
-
-/** Configure UDMA M2S descriptor prefetch */
-int al_udma_m2s_pref_set(struct al_udma *udma,
-				struct al_udma_m2s_desc_pref_conf *conf)
-{
-	uint32_t reg;
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1);
-	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK;
-	reg |= conf->desc_fifo_depth;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2);
-
-	if (conf->sch_mode == SRR)
-		reg |= UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
-	else if (conf->sch_mode == STRICT)
-		reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
-	else {
-		al_err("udma [%s]: requested descriptor preferch arbiter "
-			"mode (%d) is invalid\n", udma->name, conf->sch_mode);
-		return -EINVAL;
-	}
-	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK;
-	reg |= conf->max_desc_per_packet &
-		UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3);
-	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
-	reg |= conf->min_burst_below_thr &
-		UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
-
-	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK;
-	reg |=(conf->min_burst_above_thr <<
-	       UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT) &
-		UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK;
-
-	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
-	reg |= (conf->pref_thr <<
-			UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) &
-		UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
-
-	al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.data_cfg);
-	reg &= ~UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK;
-	reg |= conf->data_fifo_depth &
-			UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK;
-
-	reg &= ~UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK;
-	reg |= (conf->max_pkt_limit
-			<< UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_SHIFT) &
-		UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_rd.data_cfg, reg);
-
-	return 0;
-}
-
-/** Ger the M2S UDMA descriptor prefetch */
-int al_udma_m2s_pref_get(struct al_udma *udma,
-				struct al_udma_m2s_desc_pref_conf *conf)
-{
-	uint32_t reg;
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1);
-	conf->desc_fifo_depth =
-	    AL_REG_FIELD_GET(reg, UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK,
-			UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_SHIFT);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2);
-	if (reg & UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK)
-		conf->sch_mode = SRR;
-	else
-		conf->sch_mode = STRICT;
-	conf->max_desc_per_packet =
-	    AL_REG_FIELD_GET(reg,
-			UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK,
-			UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_SHIFT);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3);
-
-	conf->min_burst_below_thr =
-	    AL_REG_FIELD_GET(reg,
-			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK,
-			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_SHIFT);
-
-	conf->min_burst_above_thr =
-	    AL_REG_FIELD_GET(reg,
-			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK,
-			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT);
-
-	conf->pref_thr = AL_REG_FIELD_GET(reg,
-				UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK,
-				UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT);
-	return 0;
-}
-
-/* set max descriptors */
-int al_udma_m2s_max_descs_set(struct al_udma *udma, uint8_t max_descs)
-{
-	uint32_t pref_thr = max_descs;
-	uint32_t min_burst_above_thr = 4;
-	al_assert(max_descs <= AL_UDMA_M2S_MAX_ALLOWED_DESCS_PER_PACKET);
-	al_assert(max_descs > 0);
-
-	/* increase min_burst_above_thr so larger burst can be used to fetch
-	 * descriptors */
-	if (pref_thr >= 8)
-		min_burst_above_thr = 8;
-	else {
-	/* don't set prefetch threshold too low so we can have the
-	 * min_burst_above_thr >= 4 */
-		pref_thr = 4;
-	}
-
-	al_reg_write32_masked(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2,
-			      UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK,
-			      max_descs << UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_SHIFT);
-
-	al_reg_write32_masked(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3,
-			      UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK |
-			      UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK,
-			      (pref_thr << UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) |
-			      (min_burst_above_thr << UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT));
-
-	return 0;
-}
-
-/* set s2m max descriptors */
-int al_udma_s2m_max_descs_set(struct al_udma *udma, uint8_t max_descs)
-{
-	uint32_t pref_thr = max_descs;
-	uint32_t min_burst_above_thr = 4;
-	al_assert(max_descs <= AL_UDMA_S2M_MAX_ALLOWED_DESCS_PER_PACKET);
-	al_assert(max_descs > 0);
-
-	/* increase min_burst_above_thr so larger burst can be used to fetch
-	 * descriptors */
-	if (pref_thr >= 8)
-		min_burst_above_thr = 8;
-	else
-	/* don't set prefetch threshold too low so we can have the
-	 * min_burst_above_thr >= 4 */
-		pref_thr = 4;
-
-	al_reg_write32_masked(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3,
-			      UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK |
-			      UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK,
-			      (pref_thr << UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) |
-			      (min_burst_above_thr << UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT));
-
-	return 0;
-}
-
-int al_udma_s2m_full_line_write_set(struct al_udma *udma, al_bool enable)
-{
-	uint32_t	val = 0;
-
-	if (enable == AL_TRUE) {
-		val = UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE;
-		al_info("udma [%s]: full line write enabled\n", udma->name);
-	}
-
-	al_reg_write32_masked(&udma->udma_regs->s2m.s2m_wr.data_cfg_2,
-			UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE,
-			val);
-	return 0;
-}
-
-/** Configure S2M UDMA descriptor prefetch */
-int al_udma_s2m_pref_set(struct al_udma *udma,
-				struct al_udma_s2m_desc_pref_conf *conf)
-{
-	uint32_t reg;
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_1);
-	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK;
-	reg |= conf->desc_fifo_depth;
-	al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_1, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_2);
-
-	if (conf->sch_mode == SRR)
-		reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
-	else if (conf->sch_mode == STRICT)
-		reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
-	else {
-		al_err("udma [%s]: requested descriptor preferch arbiter "
-			"mode (%d) is invalid\n", udma->name, conf->sch_mode);
-		return -EINVAL;
-	}
-	if (conf->q_promotion == AL_TRUE)
-		reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION;
-	else
-		reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION;
-
-	if (conf->force_promotion == AL_TRUE)
-		reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION;
-	else
-		reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION;
-
-	if (conf->en_pref_prediction == AL_TRUE)
-		reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION;
-	else
-		reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION;
-
-	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_MASK;
-	reg |= (conf->promotion_th
-			<< UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_SHIFT) &
-		UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_MASK;
-
-	al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_2, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3);
-	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
-	reg |= (conf->pref_thr << UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) &
-		UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
-
-	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
-	reg |= conf->min_burst_below_thr &
-		UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
-
-	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK;
-	reg |=(conf->min_burst_above_thr <<
-	       UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT) &
-		UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
-
-	al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_4);
-	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK;
-	reg |= conf->a_full_thr & UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK;
-	al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_4, reg);
-
-
-	return 0;
-}
-
-/* Configure S2M UDMA data write */
-int al_udma_s2m_data_write_set(struct al_udma *udma,
-				struct al_udma_s2m_data_write_conf *conf)
-{
-	uint32_t reg;
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_1);
-	reg &= ~UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_MASK;
-	reg |= conf->data_fifo_depth &
-			UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_MASK;
-	reg &= ~UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_MASK;
-	reg |= (conf->max_pkt_limit <<
-				UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_SHIFT) &
-			UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_MASK;
-	reg &= ~UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_MASK;
-	reg |= (conf->fifo_margin <<
-				UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_SHIFT) &
-			UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_MASK;
-	al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_1, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2);
-	reg &= ~UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK;
-	reg |= conf->desc_wait_timer &
-			UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK;
-	reg &= ~(UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC |
-		 UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC |
-		 UDMA_S2M_WR_DATA_CFG_2_WAIT_FOR_PREF |
-		 UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE |
-		 UDMA_S2M_WR_DATA_CFG_2_DIRECT_HDR_USE_BUF1);
-	reg |= conf->flags &
-		(UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC |
-		 UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC |
-		 UDMA_S2M_WR_DATA_CFG_2_WAIT_FOR_PREF |
-		 UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE |
-		 UDMA_S2M_WR_DATA_CFG_2_DIRECT_HDR_USE_BUF1);
-	al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2, reg);
-
-	return 0;
-}
-
-/* Configure S2M UDMA completion */
-int al_udma_s2m_completion_set(struct al_udma *udma,
-				struct al_udma_s2m_completion_conf *conf)
-{
-	uint32_t reg = al_reg_read32(&udma->udma_regs->s2m.s2m_comp.cfg_1c);
-	reg &= ~UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
-	reg |= conf->desc_size & UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
-	if (conf->cnt_words == AL_TRUE)
-		reg |= UDMA_S2M_COMP_CFG_1C_CNT_WORDS;
-	else
-		reg &= ~UDMA_S2M_COMP_CFG_1C_CNT_WORDS;
-	if (conf->q_promotion == AL_TRUE)
-		reg |= UDMA_S2M_COMP_CFG_1C_Q_PROMOTION;
-	else
-		reg &= ~UDMA_S2M_COMP_CFG_1C_Q_PROMOTION;
-	if (conf->force_rr == AL_TRUE)
-		reg |= UDMA_S2M_COMP_CFG_1C_FORCE_RR;
-	else
-		reg &= ~UDMA_S2M_COMP_CFG_1C_FORCE_RR;
-	reg &= ~UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_MASK;
-	reg |= (conf->q_free_min << UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_SHIFT) &
-		UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_MASK;
-	al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_1c, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_comp.cfg_2c);
-	reg &= ~UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_MASK;
-	reg |= conf->comp_fifo_depth
-				& UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_MASK;
-	reg &= ~UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_MASK;
-	reg |= (conf->unack_fifo_depth
-			<< UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_SHIFT) &
-			UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_MASK;
-	al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_2c, reg);
-
-	al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_application_ack,
-		       conf->timeout);
-	return 0;
-}
-
-/** Configure the M2S UDMA scheduling mode */
-int al_udma_m2s_sc_set(struct al_udma *udma,
-					struct al_udma_m2s_dwrr_conf *sched)
-{
-	uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched);
-
-	if (sched->enable_dwrr == AL_TRUE)
-		reg |= UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR;
-	else
-		reg &= ~UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR;
-
-	if (sched->pkt_mode == AL_TRUE)
-		reg |= UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN;
-	else
-		reg &= ~UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN;
-
-	reg &= ~UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_MASK;
-	reg |= sched->weight << UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_SHIFT;
-	reg &= ~UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_MASK;
-	reg |= sched->inc_factor << UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_SHIFT;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt);
-	reg &= ~UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_MASK;
-	reg |= sched->deficit_init_val;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt, reg);
-
-	return 0;
-}
-
-/** Configure the M2S UDMA rate limitation */
-int al_udma_m2s_rlimit_set(struct al_udma *udma,
-					struct al_udma_m2s_rlimit_mode *mode)
-{
-	uint32_t reg = al_reg_read32(
-				&udma->udma_regs->m2s.m2s_rate_limiter.gen_cfg);
-
-	if (mode->pkt_mode_en == AL_TRUE)
-		reg |= UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN;
-	else
-		reg &= ~UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN;
-	reg &= ~UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK;
-	reg |= mode->short_cycle_sz &
-	    UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.gen_cfg, reg);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token);
-	reg &= ~UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK;
-	reg |= mode->token_init_val &
-			UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token, reg);
-
-	return 0;
-}
-
-int al_udma_m2s_rlimit_reset(struct al_udma *udma)
-{
-	uint32_t reg = al_reg_read32(
-			&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_cycle_cnt);
-	reg |= UDMA_M2S_RATE_LIMITER_CTRL_CYCLE_CNT_RST;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_cycle_cnt,
-						reg);
-	return 0;
-}
-
-/** Configure the Stream/Q rate limitation */
-static int al_udma_common_rlimit_set(struct udma_rlimit_common *regs,
-					  struct al_udma_m2s_rlimit_cfg *conf)
-{
-	uint32_t reg = al_reg_read32(&regs->cfg_1s);
-	/* mask max burst size, and enable/pause control bits */
-	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK;
-	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN;
-	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE;
-	reg |= conf->max_burst_sz &
-		UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK;
-	al_reg_write32(&regs->cfg_1s, reg);
-
-	reg = al_reg_read32(&regs->cfg_cycle);
-	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK;
-	reg |= conf->long_cycle_sz &
-		UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK;
-	al_reg_write32(&regs->cfg_cycle, reg);
-
-	reg = al_reg_read32(&regs->cfg_token_size_1);
-	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK;
-	reg |= conf->long_cycle &
-		UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK;
-	al_reg_write32(&regs->cfg_token_size_1, reg);
-
-	reg = al_reg_read32(&regs->cfg_token_size_2);
-	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK;
-	reg |= conf->short_cycle &
-		UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK;
-	al_reg_write32(&regs->cfg_token_size_2, reg);
-
-	reg = al_reg_read32(&regs->mask);
-	reg &= ~0xf;		/* only bits 0-3 defined */
-	reg |= conf->mask & 0xf;
-	al_reg_write32(&regs->mask, reg);
-
-	return 0;
-}
-
-static int al_udma_common_rlimit_act(struct udma_rlimit_common *regs,
-					  enum al_udma_m2s_rlimit_action act)
-{
-	uint32_t reg;
-
-	switch (act) {
-	case AL_UDMA_STRM_RLIMIT_ENABLE:
-		reg = al_reg_read32(&regs->cfg_1s);
-		reg |= UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN;
-		al_reg_write32(&regs->cfg_1s, reg);
-		break;
-	case AL_UDMA_STRM_RLIMIT_PAUSE:
-		reg = al_reg_read32(&regs->cfg_1s);
-		reg |= UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE;
-		al_reg_write32(&regs->cfg_1s, reg);
-		break;
-	case AL_UDMA_STRM_RLIMIT_RESET:
-		reg = al_reg_read32(&regs->sw_ctrl);
-		reg |= UDMA_M2S_STREAM_RATE_LIMITER_SW_CTRL_RST_TOKEN_CNT;
-		al_reg_write32(&regs->sw_ctrl, reg);
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-/** Configure the M2S Stream rate limitation */
-int al_udma_m2s_strm_rlimit_set(struct al_udma *udma,
-				struct al_udma_m2s_rlimit_cfg *conf)
-{
-	struct udma_rlimit_common *rlimit_regs =
-	    &udma->udma_regs->m2s.m2s_stream_rate_limiter.rlimit;
-
-	return al_udma_common_rlimit_set(rlimit_regs, conf);
-}
-
-int al_udma_m2s_strm_rlimit_act(struct al_udma *udma,
-				enum al_udma_m2s_rlimit_action act)
-{
-	struct udma_rlimit_common *rlimit_regs =
-	    &udma->udma_regs->m2s.m2s_stream_rate_limiter.rlimit;
-
-	if (al_udma_common_rlimit_act(rlimit_regs, act) == -EINVAL) {
-		al_err("udma [%s]: udma stream rate limit invalid action "
-			"(%d)\n", udma->name, act);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-/** Configure the M2S UDMA Q rate limitation */
-int al_udma_m2s_q_rlimit_set(struct al_udma_q *udma_q,
-				struct al_udma_m2s_rlimit_cfg *conf)
-{
-	struct udma_rlimit_common *rlimit_regs = &udma_q->q_regs->m2s_q.rlimit;
-
-	return al_udma_common_rlimit_set(rlimit_regs, conf);
-}
-
-int al_udma_m2s_q_rlimit_act(struct al_udma_q *udma_q,
-				enum al_udma_m2s_rlimit_action act)
-{
-	struct udma_rlimit_common *rlimit_regs = &udma_q->q_regs->m2s_q.rlimit;
-
-	if (al_udma_common_rlimit_act(rlimit_regs, act) == -EINVAL) {
-		al_err("udma [%s %d]: udma stream rate limit invalid action "
-				"(%d)\n",
-				udma_q->udma->name, udma_q->qid, act);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-/** Configure the M2S UDMA Q scheduling mode */
-int al_udma_m2s_q_sc_set(struct al_udma_q *udma_q,
-					struct al_udma_m2s_q_dwrr_conf *conf)
-{
-	uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1);
-
-	reg &= ~UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK;
-	reg |= conf->max_deficit_cnt_sz &
-		UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK;
-	if (conf->strict == AL_TRUE)
-		reg |= UDMA_M2S_Q_DWRR_CFG_1_STRICT;
-	else
-		reg &= ~UDMA_M2S_Q_DWRR_CFG_1_STRICT;
-	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg);
-
-	reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_2);
-	reg &= ~UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
-	reg |= (conf->axi_qos << UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_SHIFT) &
-	    UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
-	reg &= ~UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
-	reg |= conf->q_qos & UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
-	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_2, reg);
-
-	reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_3);
-	reg &= ~UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK;
-	reg |= conf->weight & UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK;
-	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_3, reg);
-
-	return 0;
-}
-
-int al_udma_m2s_q_sc_pause(struct al_udma_q *udma_q, al_bool set)
-{
-	uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1);
-
-	if (set == AL_TRUE)
-		reg |= UDMA_M2S_Q_DWRR_CFG_1_PAUSE;
-	else
-		reg &= ~UDMA_M2S_Q_DWRR_CFG_1_PAUSE;
-	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg);
-
-	return 0;
-}
-
-int al_udma_m2s_q_sc_reset(struct al_udma_q *udma_q)
-{
-	uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl);
-
-	reg |= UDMA_M2S_Q_DWRR_SW_CTRL_RST_CNT;
-	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl, reg);
-
-	return 0;
-}
-
-/** M2S UDMA completion and application timeouts */
-int al_udma_m2s_comp_timeouts_set(struct al_udma *udma,
-				struct al_udma_m2s_comp_timeouts *conf)
-{
-	uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c);
-
-	if (conf->sch_mode == SRR)
-		reg |= UDMA_M2S_COMP_CFG_1C_FORCE_RR;
-	else if (conf->sch_mode == STRICT)
-		reg &= ~UDMA_M2S_COMP_CFG_1C_FORCE_RR;
-	else {
-		al_err("udma [%s]: requested completion descriptor preferch "
-				"arbiter mode (%d) is invalid\n",
-				udma->name, conf->sch_mode);
-		return -EINVAL;
-	}
-	if (conf->enable_q_promotion == AL_TRUE)
-		reg |= UDMA_M2S_COMP_CFG_1C_Q_PROMOTION;
-	else
-		reg &= ~UDMA_M2S_COMP_CFG_1C_Q_PROMOTION;
-	reg &= ~UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK;
-	reg |=
-	    conf->comp_fifo_depth << UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_SHIFT;
-
-	reg &= ~UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK;
-	reg |= conf->unack_fifo_depth
-				<< UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_SHIFT;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_1c, reg);
-
-	al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_coal
-							, conf->coal_timeout);
-
-	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack);
-	reg &= ~UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK;
-	reg |= conf->app_timeout << UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT;
-	al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack, reg);
-	return 0;
-}
-
-int al_udma_m2s_comp_timeouts_get(struct al_udma *udma,
-					struct al_udma_m2s_comp_timeouts *conf)
-{
-	uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c);
-
-	if (reg & UDMA_M2S_COMP_CFG_1C_FORCE_RR)
-		conf->sch_mode = SRR;
-	else
-		conf->sch_mode = STRICT;
-
-	if (reg & UDMA_M2S_COMP_CFG_1C_Q_PROMOTION)
-		conf->enable_q_promotion = AL_TRUE;
-	else
-		conf->enable_q_promotion = AL_FALSE;
-
-	conf->comp_fifo_depth =
-	    AL_REG_FIELD_GET(reg,
-			     UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK,
-			     UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_SHIFT);
-	conf->unack_fifo_depth =
-	    AL_REG_FIELD_GET(reg,
-			     UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK,
-			     UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_SHIFT);
-
-	conf->coal_timeout = al_reg_read32(
-				&udma->udma_regs->m2s.m2s_comp.cfg_coal);
-
-	reg = al_reg_read32(
-			&udma->udma_regs->m2s.m2s_comp.cfg_application_ack);
-
-	conf->app_timeout =
-	    AL_REG_FIELD_GET(reg,
-			     UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK,
-			     UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT);
-
-	return 0;
-}
-
-/**
- * S2M UDMA configure no descriptors behaviour
- */
-int al_udma_s2m_no_desc_cfg_set(struct al_udma *udma, al_bool drop_packet, al_bool gen_interrupt, uint32_t wait_for_desc_timeout)
-{
-	uint32_t reg;
-
-	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2);
-
-	if ((drop_packet == AL_TRUE) && (wait_for_desc_timeout == 0)) {
-		al_err("udam [%s]: setting timeout to 0 will cause the udma to wait forever instead of dropping the packet", udma->name);
-		return -EINVAL;
-	}
-
-	if (drop_packet == AL_TRUE)
-		reg |= UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC;
-	else
-		reg &= ~UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC;
-
-	if (gen_interrupt == AL_TRUE)
-		reg |= UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC;
-	else
-		reg &= ~UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC;
-
-	AL_REG_FIELD_SET(reg, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_SHIFT, wait_for_desc_timeout);
-
-	al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2, reg);
-
-	return 0;
-}
-
-/* S2M UDMA configure a queue's completion update */
-int al_udma_s2m_q_compl_updade_config(struct al_udma_q *udma_q, al_bool enable)
-{
-	uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
-
-	if (enable == AL_TRUE)
-		reg |= UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
-	else
-		reg &= ~UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
-
-	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
-
-	return 0;
-}
-
-/* S2M UDMA configure a queue's completion descriptors coalescing */
-int al_udma_s2m_q_compl_coal_config(struct al_udma_q *udma_q, al_bool enable, uint32_t
-		coal_timeout)
-{
-	uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
-
-	if (enable == AL_TRUE)
-		reg &= ~UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
-	else
-		reg |= UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
-
-	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
-
-	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg_2, coal_timeout);
-	return 0;
-}
-
-/* S2M UDMA configure completion descriptors write burst parameters */
-int al_udma_s2m_compl_desc_burst_config(struct al_udma *udma, uint16_t
-		burst_size)
-{
-	if ((burst_size != 64) && (burst_size != 128) && (burst_size != 256)) {
-		al_err("%s: invalid burst_size value (%d)\n", __func__,
-				burst_size);
-		return -EINVAL;
-	}
-
-	/* convert burst size from bytes to beats (16 byte) */
-	burst_size = burst_size / 16;
-	al_reg_write32_masked(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1,
-			UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK |
-			UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK,
-			burst_size << UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT |
-			burst_size << UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT);
-	return 0;
-}
-
-/* S2M UDMA configure a queue's completion descriptors header split */
-int al_udma_s2m_q_compl_hdr_split_config(struct al_udma_q *udma_q, al_bool enable,
-					 al_bool force_hdr_split, uint32_t hdr_len)
-{
-	uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg);
-
-	reg &= ~UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
-	reg &= ~UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
-	reg &= ~UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
-
-	if (enable == AL_TRUE) {
-		reg |= hdr_len & UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
-		reg |= UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
-
-		if (force_hdr_split == AL_TRUE)
-			reg |= UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
-	}
-
-	al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg);
-
-	return 0;
-}
-
-/* S2M UDMA per queue completion configuration */
-int al_udma_s2m_q_comp_set(struct al_udma_q *udma_q,
-					struct al_udma_s2m_q_comp_conf *conf)
-{
-	uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
-	if (conf->en_comp_ring_update == AL_TRUE)
-		reg |= UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
-	else
-		reg &= ~UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
-
-	if (conf->dis_comp_coal == AL_TRUE)
-		reg |= UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
-	else
-		reg &= ~UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
-
-	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
-
-	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg_2, conf->comp_timer);
-
-	reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg);
-
-	reg &= ~UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
-	reg |= conf->hdr_split_size & UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
-	if (conf->force_hdr_split == AL_TRUE)
-		reg |= UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
-	else
-		reg &= ~UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
-	if (conf->en_hdr_split == AL_TRUE)
-		reg |= UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
-	else
-		reg &= ~UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
-
-	al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg);
-
-	reg = al_reg_read32(&udma_q->q_regs->s2m_q.qos_cfg);
-	reg &= ~UDMA_S2M_QOS_CFG_Q_QOS_MASK;
-	reg |= conf->q_qos & UDMA_S2M_QOS_CFG_Q_QOS_MASK;
-	al_reg_write32(&udma_q->q_regs->s2m_q.qos_cfg, reg);
-
-	return 0;
-}
-
-/* UDMA VMID control configuration */
-void al_udma_gen_vmid_conf_set(
-	struct unit_regs		*unit_regs,
-	struct al_udma_gen_vmid_conf	*conf)
-{
-	unsigned int rev_id;
-
-	al_reg_write32_masked(
-		&unit_regs->gen.vmid.cfg_vmid_0,
-		UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_MASK |
-		UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_MASK |
-		UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_MASK |
-		UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_MASK,
-		(((conf->tx_q_conf[0].desc_en << 0) |
-		(conf->tx_q_conf[1].desc_en << 1) |
-		(conf->tx_q_conf[2].desc_en << 2) |
-		(conf->tx_q_conf[3].desc_en << 3)) <<
-		UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_SHIFT) |
-		(((conf->tx_q_conf[0].queue_en << 0) |
-		(conf->tx_q_conf[1].queue_en << 1) |
-		(conf->tx_q_conf[2].queue_en << 2) |
-		(conf->tx_q_conf[3].queue_en << 3)) <<
-		UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_SHIFT) |
-		(((conf->rx_q_conf[0].desc_en << 0) |
-		(conf->rx_q_conf[1].desc_en << 1) |
-		(conf->rx_q_conf[2].desc_en << 2) |
-		(conf->rx_q_conf[3].desc_en << 3)) <<
-		UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_SHIFT) |
-		(((conf->rx_q_conf[0].queue_en << 0) |
-		(conf->rx_q_conf[1].queue_en << 1) |
-		(conf->rx_q_conf[2].queue_en << 2) |
-		(conf->rx_q_conf[3].queue_en << 3)) <<
-		UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_SHIFT));
-
-	/* VMID per queue */
-	al_reg_write32(
-		&unit_regs->gen.vmid.cfg_vmid_1,
-		(conf->tx_q_conf[0].vmid <<
-		UDMA_GEN_VMID_CFG_VMID_1_TX_Q_0_VMID_SHIFT) |
-		(conf->tx_q_conf[1].vmid <<
-		UDMA_GEN_VMID_CFG_VMID_1_TX_Q_1_VMID_SHIFT));
-
-	al_reg_write32(
-		&unit_regs->gen.vmid.cfg_vmid_2,
-		(conf->tx_q_conf[2].vmid <<
-		UDMA_GEN_VMID_CFG_VMID_2_TX_Q_2_VMID_SHIFT) |
-		(conf->tx_q_conf[3].vmid <<
-		UDMA_GEN_VMID_CFG_VMID_2_TX_Q_3_VMID_SHIFT));
-
-	al_reg_write32(
-		&unit_regs->gen.vmid.cfg_vmid_3,
-		(conf->rx_q_conf[0].vmid <<
-		UDMA_GEN_VMID_CFG_VMID_3_RX_Q_0_VMID_SHIFT) |
-		(conf->rx_q_conf[1].vmid <<
-		UDMA_GEN_VMID_CFG_VMID_3_RX_Q_1_VMID_SHIFT));
-
-	al_reg_write32(
-		&unit_regs->gen.vmid.cfg_vmid_4,
-		(conf->rx_q_conf[2].vmid <<
-		UDMA_GEN_VMID_CFG_VMID_4_RX_Q_2_VMID_SHIFT) |
-		(conf->rx_q_conf[3].vmid <<
-		UDMA_GEN_VMID_CFG_VMID_4_RX_Q_3_VMID_SHIFT));
-
-	/* VMADDR per queue */
-	rev_id = al_udma_get_revision(unit_regs);
-	if (rev_id >= AL_UDMA_REV_ID_REV2) {
-		al_reg_write32(
-			&unit_regs->gen.vmaddr.cfg_vmaddr_0,
-			(conf->tx_q_conf[0].vmaddr <<
-			UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_0_VMADDR_SHIFT) |
-			(conf->tx_q_conf[1].vmaddr <<
-			UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_1_VMADDR_SHIFT));
-
-		al_reg_write32(
-			&unit_regs->gen.vmaddr.cfg_vmaddr_1,
-			(conf->tx_q_conf[2].vmaddr <<
-			UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_2_VMADDR_SHIFT) |
-			(conf->tx_q_conf[3].vmaddr <<
-			UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_3_VMADDR_SHIFT));
-
-		al_reg_write32(
-			&unit_regs->gen.vmaddr.cfg_vmaddr_2,
-			(conf->rx_q_conf[0].vmaddr <<
-			UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_0_VMADDR_SHIFT) |
-			(conf->rx_q_conf[1].vmaddr <<
-			UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_1_VMADDR_SHIFT));
-
-		al_reg_write32(
-			&unit_regs->gen.vmaddr.cfg_vmaddr_3,
-			(conf->rx_q_conf[2].vmaddr <<
-			UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_2_VMADDR_SHIFT) |
-			(conf->rx_q_conf[3].vmaddr <<
-			UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_3_VMADDR_SHIFT));
-	}
-}
-
-/* UDMA VMID MSIX control configuration */
-void al_udma_gen_vmid_msix_conf_set(
-	struct unit_regs			*unit_regs,
-	struct al_udma_gen_vmid_msix_conf	*conf)
-{
-	al_reg_write32_masked(
-		&unit_regs->gen.vmid.cfg_vmid_0,
-		UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_ACCESS_EN |
-		UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_SEL,
-		(conf->access_en ? UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_ACCESS_EN : 0) |
-		(conf->sel ? UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_SEL : 0));
-}
-
-/* UDMA VMID control advanced Tx queue configuration */
-void al_udma_gen_vmid_advanced_tx_q_conf(
-	struct al_udma_q				*q,
-	struct al_udma_gen_vmid_advanced_tx_q_conf	*conf)
-{
-	struct udma_gen_regs *gen_regs = q->udma->gen_regs;
-	struct udma_gen_vmpr *vmpr = &gen_regs->vmpr[q->qid];
-
-	al_reg_write32_masked(
-		&vmpr->cfg_vmpr_0,
-		UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_DATA_VMID_EN |
-		UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_PREF_VMID_EN |
-		UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_CMPL_VMID_EN,
-		conf->tx_q_addr_hi_sel |
-		((conf->tx_q_data_vmid_en == AL_TRUE) ?
-		 UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_DATA_VMID_EN : 0) |
-		((conf->tx_q_prefetch_vmid_en == AL_TRUE) ?
-		 UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_PREF_VMID_EN : 0) |
-		((conf->tx_q_compl_vmid_en == AL_TRUE) ?
-		 UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_CMPL_VMID_EN : 0));
-
-	al_reg_write32(
-		&vmpr->cfg_vmpr_1,
-		conf->tx_q_addr_hi);
-
-	al_reg_write32_masked(
-		&vmpr->cfg_vmpr_2,
-		UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_MASK,
-		(conf->tx_q_prefetch_vmid <<
-		 UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_SHIFT) |
-		(conf->tx_q_compl_vmid <<
-		 UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_SHIFT));
-
-	al_reg_write32_masked(
-		&vmpr->cfg_vmpr_3,
-		UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_MASK,
-		(conf->tx_q_data_vmid <<
-		 UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SHIFT) |
-		(conf->tx_q_data_vmid_mask <<
-		 UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_SHIFT));
-}
-
-/** UDMA VMID control advanced Rx queue configuration */
-void al_udma_gen_vmid_advanced_rx_q_conf(
-	struct al_udma_q				*q,
-	struct al_udma_gen_vmid_advanced_rx_q_conf	*conf)
-{
-	struct udma_gen_regs *gen_regs = q->udma->gen_regs;
-	struct udma_gen_vmpr *vmpr = &gen_regs->vmpr[q->qid];
-
-	al_reg_write32_masked(
-		&vmpr->cfg_vmpr_4,
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_VMID_EN |
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_VMID_EN |
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_VMID_EN |
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_PREF_VMID_EN |
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_CMPL_VMID_EN,
-		(conf->rx_q_addr_hi_sel <<
-		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_SHIFT) |
-		((conf->rx_q_data_vmid_en == AL_TRUE) ?
-		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_VMID_EN : 0) |
-		(conf->rx_q_data_buff2_addr_hi_sel <<
-		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_SHIFT) |
-		((conf->rx_q_data_buff2_vmid_en == AL_TRUE) ?
-		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_VMID_EN : 0) |
-		(conf->rx_q_ddp_addr_hi_sel <<
-		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_SHIFT) |
-		((conf->rx_q_ddp_vmid_en == AL_TRUE) ?
-		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_VMID_EN : 0) |
-		((conf->rx_q_prefetch_vmid_en == AL_TRUE) ?
-		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_PREF_VMID_EN : 0) |
-		((conf->rx_q_compl_vmid_en == AL_TRUE) ?
-		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_CMPL_VMID_EN : 0));
-
-	al_reg_write32_masked(
-		&vmpr->cfg_vmpr_6,
-		UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_MASK,
-		(conf->rx_q_prefetch_vmid <<
-		 UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_SHIFT) |
-		(conf->rx_q_compl_vmid <<
-		 UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_SHIFT));
-
-	al_reg_write32_masked(
-		&vmpr->cfg_vmpr_7,
-		UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_MASK,
-		(conf->rx_q_data_vmid <<
-		 UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SHIFT) |
-		(conf->rx_q_data_vmid_mask <<
-		 UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_SHIFT));
-
-	al_reg_write32_masked(
-		&vmpr->cfg_vmpr_8,
-		UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_MASK,
-		(conf->rx_q_data_buff2_vmid <<
-		 UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SHIFT) |
-		(conf->rx_q_data_buff2_mask <<
-		 UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_SHIFT));
-
-	al_reg_write32_masked(
-		&vmpr->cfg_vmpr_9,
-		UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_MASK |
-		UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_MASK,
-		(conf->rx_q_ddp_vmid <<
-		 UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SHIFT) |
-		(conf->rx_q_ddp_mask <<
-		 UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_SHIFT));
-
-	al_reg_write32(
-		&vmpr->cfg_vmpr_10,
-		conf->rx_q_addr_hi);
-
-	al_reg_write32(
-		&vmpr->cfg_vmpr_11,
-		conf->rx_q_data_buff2_addr_hi);
-
-	al_reg_write32(
-		&vmpr->cfg_vmpr_12,
-		conf->rx_q_ddp_addr_hi);
-}
-
-/* UDMA header split buffer 2 Rx queue configuration */
-void al_udma_gen_hdr_split_buff2_rx_q_conf(
-	struct al_udma_q				*q,
-	struct al_udma_gen_hdr_split_buff2_q_conf	*conf)
-{
-	struct udma_gen_regs *gen_regs = q->udma->gen_regs;
-	struct udma_gen_vmpr *vmpr = &gen_regs->vmpr[q->qid];
-
-	al_reg_write32_masked(
-		&vmpr->cfg_vmpr_4,
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_MASK,
-		conf->add_msb_sel <<
-		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_SHIFT);
-
-	al_reg_write32(
-		&vmpr->cfg_vmpr_5,
-		conf->addr_msb);
-}
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_config.h b/sys/contrib/alpine-hal/eth/al_hal_udma_config.h
deleted file mode 100644
index b742e1824c92..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_config.h
+++ /dev/null
@@ -1,755 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_udma_config UDMA Config
- * @ingroup group_udma_api
- *  UDMA Config API
- *  @{
- * @file   al_hal_udma_config.h
- *
- * @brief C Header file for the Universal DMA HAL driver for configuration APIs
- *
- */
-
-#ifndef __AL_HAL_UDMA_CONFIG_H__
-#define __AL_HAL_UDMA_CONFIG_H__
-
-#include <al_hal_udma.h>
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/** Scheduling mode */
-enum al_udma_sch_mode {
-	STRICT,			/* Strict */
-	SRR,			/* Simple Sound Rubin */
-	DWRR			/* Deficit Weighted Round Rubin */
-};
-
-/** AXI configuration */
-struct al_udma_axi_conf {
-	uint32_t axi_timeout;	/* Timeout for AXI transactions  */
-	uint8_t arb_promotion;	/* arbitration promotion */
-	al_bool swap_8_bytes;	/* enable 8 bytes swap instead of 4 bytes */
-	al_bool swap_s2m_data;
-	al_bool swap_s2m_desc;
-	al_bool swap_m2s_data;
-	al_bool swap_m2s_desc;
-};
-
-/** UDMA AXI M2S configuration */
-struct al_udma_axi_submaster {
-	uint8_t id; /* AXI ID */
-	uint8_t cache_type;
-	uint8_t burst;
-	uint16_t used_ext;
-	uint8_t bus_size;
-	uint8_t qos;
-	uint8_t prot;
-	uint8_t max_beats;
-};
-
-/** UDMA AXI M2S configuration */
-struct al_udma_m2s_axi_conf {
-	struct al_udma_axi_submaster comp_write;
-	struct al_udma_axi_submaster data_read;
-	struct al_udma_axi_submaster desc_read;
-	al_bool break_on_max_boundary; /* Data read break on max boundary */
-	uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
-	uint8_t ostand_max_data_read;
-	uint8_t ostand_max_desc_read;
-	uint8_t ostand_max_comp_req;
-	uint8_t ostand_max_comp_write;
-};
-
-/** UDMA AXI S2M configuration */
-struct al_udma_s2m_axi_conf {
-	struct al_udma_axi_submaster data_write;
-	struct al_udma_axi_submaster desc_read;
-	struct al_udma_axi_submaster comp_write;
-	al_bool break_on_max_boundary; /* Data read break on max boundary */
-	uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
-	uint8_t ostand_max_data_req;
-	uint8_t ostand_max_data_write;
-	uint8_t ostand_max_comp_req;
-	uint8_t ostand_max_comp_write;
-	uint8_t ostand_max_desc_read;
-	uint8_t ack_fifo_depth;	/* size of the stream application ack fifo */
-};
-
-/** M2S error logging */
-struct al_udma_err_log {
-	uint32_t error_status;
-	uint32_t header[4];
-};
-
-/** M2S max packet size configuration */
-struct al_udma_m2s_pkt_len_conf {
-	uint32_t max_pkt_size;
-	al_bool encode_64k_as_zero;
-};
-
-/** M2S Descriptor Prefetch configuration */
-struct al_udma_m2s_desc_pref_conf {
-	uint8_t desc_fifo_depth;
-	enum al_udma_sch_mode sch_mode;	/* Scheduling mode
-					* (either strict or RR) */
-
-	uint8_t max_desc_per_packet;	/* max number of descriptors to
-					 * prefetch */
-	/* in one burst (5b) */
-	uint8_t pref_thr;
-	uint8_t min_burst_above_thr;	/* min burst size when fifo above
-					* pref_thr (4b)
-					*/
-	uint8_t min_burst_below_thr;	/* min burst size when fifo below
-					* pref_thr (4b)
-					*/
-	uint8_t max_pkt_limit;		/* maximum number of packets in the data
-					* read FIFO, defined based on header
-					* FIFO size
-					*/
-	uint16_t data_fifo_depth;	/* maximum number of data beats in the
-					* data read FIFO,
-					* defined based on header FIFO size
-					*/
-};
-
-/** S2M Descriptor Prefetch configuration */
-struct al_udma_s2m_desc_pref_conf {
-	uint8_t desc_fifo_depth;
-	enum al_udma_sch_mode sch_mode;	/* Scheduling mode *
-					* (either strict or RR)
-					*/
-
-	al_bool q_promotion;		/* enable promotion */
-	al_bool force_promotion;	/* force promotion  */
-	al_bool en_pref_prediction;	/* enable prefetch prediction */
-	uint8_t promotion_th;		/* Threshold for queue promotion */
-
-	uint8_t pref_thr;
-	uint8_t min_burst_above_thr;	/* min burst size when fifo above
-	 	 	 	 	 * pref_thr (4b)
-	 	 	 	 	 */
-	uint8_t min_burst_below_thr;	/* min burst size when fifo below
-	 	 	 	 	 * pref_thr (4b)
-	 	 	 	 	 */
-	uint8_t a_full_thr;		/* almost full threshold */
-};
-
-/** S2M Data write configuration */
-struct al_udma_s2m_data_write_conf {
-	uint16_t data_fifo_depth;	/* maximum number of data beats in the
-					 * data write FIFO, defined based on
-					 * header FIFO size
-					 */
-	uint8_t max_pkt_limit;		/* maximum number of packets in the
-					* data write FIFO,defined based on
-					* header FIFO size
-					*/
-	uint8_t fifo_margin;
-	uint32_t desc_wait_timer;	/* waiting time for the host to write
-					* new descriptor to the queue
-					* (for the current packet in process)
-					*/
-	uint32_t flags;			/* bitwise of flags of s2m
-					 * data_cfg_2 register
-					 */
-};
-
-/** S2M Completion configuration */
-struct al_udma_s2m_completion_conf {
-	uint8_t desc_size;		/* Size of completion descriptor
-					 * in words
-					 */
-	al_bool cnt_words;		/* Completion fifo in use counter:
-	 	 	 	 	 * AL_TRUE words, AL_FALS descriptors
-	 	 	 	 	 */
-	al_bool q_promotion;		/* Enable promotion of the current
-					 * unack in progress */
-					/* in the completion write scheduler */
-	al_bool force_rr;		/* force RR arbitration in the
-					*  scheduler
-					*/
-  //	uint8_t ack_fifo_depth;		/* size of the stream application ack fifo */
-	uint8_t q_free_min;		/* minimum number of free completion
-					 * entries
-					 */
-					/* to qualify for promotion */
-
-	uint16_t comp_fifo_depth;	/* Size of completion fifo in words */
-	uint16_t unack_fifo_depth;	/* Size of unacked fifo in descs */
-	uint32_t timeout;		/* Ack timout from stream interface */
-};
-
-/** M2S UDMA DWRR configuration */
-struct al_udma_m2s_dwrr_conf {
-	al_bool enable_dwrr;
-	uint8_t inc_factor;
-	uint8_t weight;
-	al_bool pkt_mode;
-	uint32_t deficit_init_val;
-};
-
-/** M2S DMA Rate Limitation mode */
-struct al_udma_m2s_rlimit_mode {
-	al_bool pkt_mode_en;
-	uint16_t short_cycle_sz;
-	uint32_t token_init_val;
-};
-
-/** M2S Stream/Q Rate Limitation */
-struct al_udma_m2s_rlimit_cfg {
-	uint32_t max_burst_sz;	/* maximum number of accumulated bytes in the
-				 * token counter
-				 */
-	uint16_t long_cycle_sz;	/* number of short cycles between token fill */
-	uint32_t long_cycle;	/* number of bits to add in each long cycle */
-	uint32_t short_cycle;	/* number of bits to add in each cycle */
-	uint32_t mask;		/* mask the different types of rate limiters */
-};
-
-enum al_udma_m2s_rlimit_action {
-	AL_UDMA_STRM_RLIMIT_ENABLE,
-	AL_UDMA_STRM_RLIMIT_PAUSE,
-	AL_UDMA_STRM_RLIMIT_RESET
-};
-
-/** M2S UDMA Q scheduling configuration */
-struct al_udma_m2s_q_dwrr_conf {
-	uint32_t max_deficit_cnt_sz;	/*maximum number of accumulated bytes
-					* in the deficit counter
-					*/
-	al_bool strict;		/* bypass DWRR */
-	uint8_t axi_qos;
-	uint16_t q_qos;
-	uint8_t weight;
-};
-
-/** M2S UDMA / UDMA Q scheduling configuration */
-struct al_udma_m2s_sc {
-	enum al_udma_sch_mode sch_mode;	/* Scheduling Mode */
-	struct al_udma_m2s_dwrr_conf dwrr;	/* DWRR configuration */
-};
-
-/** UDMA / UDMA Q rate limitation configuration */
-struct al_udma_m2s_rlimit {
-	struct al_udma_m2s_rlimit_mode rlimit_mode;
-						/* rate limitation enablers */
-#if 0
-	struct al_udma_tkn_bkt_conf token_bkt;        /* Token Bucket configuration */
-#endif
-};
-
-/** UDMA Data read configuration */
-struct al_udma_m2s_data_rd_conf {
-	uint8_t max_rd_d_beats;		/* max burst size for reading data
-					 * (in AXI beats-128b) (5b)
-					 */
-	uint8_t max_rd_d_out_req;	/* max number of outstanding data
-					 * read requests (6b)
-					 */
-	uint16_t max_rd_d_out_beats;	/* max num. of data read beats (10b) */
-};
-
-/** M2S UDMA completion and application timeouts */
-struct al_udma_m2s_comp_timeouts {
-	enum al_udma_sch_mode sch_mode;	/* Scheduling mode
-					 * (either strict or RR)
-					 */
-	al_bool enable_q_promotion;
-	uint8_t unack_fifo_depth;	/* unacked desc fifo size */
-	uint8_t comp_fifo_depth;	/* desc fifo size */
-	uint32_t coal_timeout;	/* (24b) */
-	uint32_t app_timeout;	/* (24b) */
-};
-
-/** S2M UDMA per queue completion configuration */
-struct al_udma_s2m_q_comp_conf {
-	al_bool dis_comp_coal;		/* disable completion coalescing */
-	al_bool en_comp_ring_update;	/* enable writing completion descs */
-	uint32_t comp_timer;		/* completion coalescing timer */
-	al_bool en_hdr_split;		/* enable header split */
-	al_bool force_hdr_split;	/* force header split */
-	uint16_t hdr_split_size;	/* size used for the header split */
-	uint8_t q_qos;			/* queue QoS */
-};
-
-/** UDMA per queue VMID control configuration */
-struct al_udma_gen_vmid_q_conf {
-	/* Enable usage of the VMID per queue according to 'vmid' */
-	al_bool queue_en;
-
-	/* Enable usage of the VMID from the descriptor buffer address 63:48 */
-	al_bool desc_en;
-
-	/* VMID to be applied when 'queue_en' is asserted */
-	uint16_t vmid;
-
-	/* VMADDR to be applied to msbs when 'desc_en' is asserted.
-	 * Relevant for revisions >= AL_UDMA_REV_ID_REV2 */
-	uint16_t vmaddr;
-};
-
-/** UDMA VMID control configuration */
-struct al_udma_gen_vmid_conf {
-	/* TX queue configuration */
-	struct al_udma_gen_vmid_q_conf tx_q_conf[DMA_MAX_Q];
-
-	/* RX queue configuration */
-	struct al_udma_gen_vmid_q_conf rx_q_conf[DMA_MAX_Q];
-};
-
-/** UDMA VMID MSIX control configuration */
-struct al_udma_gen_vmid_msix_conf {
-	/* Enable write to all VMID_n registers in the MSI-X Controller */
-	al_bool access_en;
-
-	/* use VMID_n [7:0] from MSI-X Controller for MSI-X message */
-	al_bool sel;
-};
-
-/** UDMA per Tx queue advanced VMID control configuration */
-struct al_udma_gen_vmid_advanced_tx_q_conf {
-	/**********************************************************************
-	 * Tx Data VMID
-	 **********************************************************************/
-	/* Tx data VMID enable */
-	al_bool tx_q_data_vmid_en;
-
-	/*
-	 * For Tx data reads, replacement bits for the original address.
-	 * The number of bits replaced is determined according to
-	 * 'tx_q_addr_hi_sel'
-	 */
-	unsigned int tx_q_addr_hi;
-
-	/*
-	 * For Tx data reads, 6 bits serving the number of bits taken from the
-	 * extra register on account of bits coming from the original address
-	 * field.
-	 * When 'tx_q_addr_hi_sel'=32 all of 'tx_q_addr_hi' will be taken.
-	 * When 'tx_q_addr_hi_sel'=0 none of it will be taken, and when any
-	 * value in between, it will start from the MSB bit and sweep down as
-	 * many bits as needed. For example if 'tx_q_addr_hi_sel'=8, the final
-	 * address [63:56] will carry 'tx_q_addr_hi'[31:24] while [55:32] will
-	 * carry the original buffer address[55:32].
-	 */
-	unsigned int tx_q_addr_hi_sel;
-
-	/*
-	 * Tx data read VMID
-	 * Masked per bit with 'tx_q_data_vmid_mask'
-	 */
-	unsigned int tx_q_data_vmid;
-
-	/*
-	 * Tx data read VMID mask
-	 * Each '1' selects from the buffer address, each '0' selects from
-	 * 'tx_q_data_vmid'
-	 */
-	unsigned int tx_q_data_vmid_mask;
-
-	/**********************************************************************
-	 * Tx prefetch VMID
-	 **********************************************************************/
-	/* Tx prefetch VMID enable */
-	al_bool tx_q_prefetch_vmid_en;
-
-	/* Tx prefetch VMID */
-	unsigned int tx_q_prefetch_vmid;
-
-	/**********************************************************************
-	 * Tx completion VMID
-	 **********************************************************************/
-	/* Tx completion VMID enable */
-	al_bool tx_q_compl_vmid_en;
-
-	/* Tx completion VMID */
-	unsigned int tx_q_compl_vmid;
-};
-
-/** UDMA per Rx queue advanced VMID control configuration */
-struct al_udma_gen_vmid_advanced_rx_q_conf {
-	/**********************************************************************
-	 * Rx Data VMID
-	 **********************************************************************/
-	/* Rx data VMID enable */
-	al_bool rx_q_data_vmid_en;
-
-	/*
-	 * For Rx data writes, replacement bits for the original address.
-	 * The number of bits replaced is determined according to
-	 * 'rx_q_addr_hi_sel'
-	 */
-	unsigned int rx_q_addr_hi;
-
-	/*
-	 * For Rx data writes, 6 bits serving the number of bits taken from the
-	 * extra register on account of bits coming from the original address
-	 * field.
-	 */
-	unsigned int rx_q_addr_hi_sel;
-
-	/*
-	 * Rx data write VMID
-	 * Masked per bit with 'rx_q_data_vmid_mask'
-	 */
-	unsigned int rx_q_data_vmid;
-
-	/* Rx data write VMID mask */
-	unsigned int rx_q_data_vmid_mask;
-
-	/**********************************************************************
-	 * Rx Data Buffer 2 VMID
-	 **********************************************************************/
-	/* Rx data buff2 VMID enable */
-	al_bool rx_q_data_buff2_vmid_en;
-
-	/*
-	 * For Rx data buff2 writes, replacement bits for the original address.
-	 * The number of bits replaced is determined according to
-	 * 'rx_q_data_buff2_addr_hi_sel'
-	 */
-	unsigned int rx_q_data_buff2_addr_hi;
-
-	/*
-	 * For Rx data buff2 writes, 6 bits serving the number of bits taken
-	 * from the extra register on account of bits coming from the original
-	 * address field.
-	 */
-	unsigned int rx_q_data_buff2_addr_hi_sel;
-
-	/*
-	 * Rx data buff2 write VMID
-	 * Masked per bit with 'rx_q_data_buff2_mask'
-	 */
-	unsigned int rx_q_data_buff2_vmid;
-
-	/* Rx data buff2 write VMID mask */
-	unsigned int rx_q_data_buff2_mask;
-
-	/**********************************************************************
-	 * Rx DDP VMID
-	 **********************************************************************/
-	/* Rx DDP write VMID enable */
-	al_bool rx_q_ddp_vmid_en;
-
-	/*
-	 * For Rx DDP writes, replacement bits for the original address.
-	 * The number of bits replaced is determined according to
-	 * 'rx_q_ddp_addr_hi_sel'
-	 */
-	unsigned int rx_q_ddp_addr_hi;
-
-	/*
-	 * For Rx DDP writes, 6 bits serving the number of bits taken from the
-	 * extra register on account of bits coming from the original address
-	 * field.
-	 */
-	unsigned int rx_q_ddp_addr_hi_sel;
-
-	/*
-	 * Rx DDP write VMID
-	 * Masked per bit with 'rx_q_ddp_mask'
-	 */
-	unsigned int rx_q_ddp_vmid;
-
-	/* Rx DDP write VMID mask */
-	unsigned int rx_q_ddp_mask;
-
-	/**********************************************************************
-	 * Rx prefetch VMID
-	 **********************************************************************/
-	/* Rx prefetch VMID enable */
-	al_bool rx_q_prefetch_vmid_en;
-
-	/* Rx prefetch VMID */
-	unsigned int rx_q_prefetch_vmid;
-
-	/**********************************************************************
-	 * Rx completion VMID
-	 **********************************************************************/
-	/* Rx completion VMID enable */
-	al_bool rx_q_compl_vmid_en;
-
-	/* Rx completion VMID */
-	unsigned int rx_q_compl_vmid;
-};
-
-/**
- * Header split, buffer 2 per queue configuration
- * When header split is enabled, Buffer_2 is used as an address for the header
- * data. Buffer_2 is defined as 32-bits in the RX descriptor and it is defined
- * that the MSB ([63:32]) of Buffer_1 is used as address [63:32] for the header
- * address.
- */
-struct al_udma_gen_hdr_split_buff2_q_conf {
-	/*
-	 * MSB of the 64-bit address (bits [63:32]) that can be used for header
-	 * split for this queue
-	 */
-	unsigned int addr_msb;
-
-	/*
-	 * Determine how to select the MSB (bits [63:32]) of the address when
-	 * header split is enabled (4 bits, one per byte)
-	 * - Bits [3:0]:
-	 *	[0] – selector for bits [39:32]
-	 *	[1] – selector for bits [47:40]
-	 *	[2] – selector for bits [55:48]
-	 *	[3] – selector for bits [63:55]
-	 * - Bit value:
-	 *	0 – Use Buffer_1 (legacy operation)
-	 *	1 – Use the queue configuration 'addr_msb'
-	 */
-	unsigned int add_msb_sel;
-};
-
-/* Report Error - to be used for abort */
-void al_udma_err_report(struct al_udma *udma);
-
-/* Statistics - TBD */
-void al_udma_stats_get(struct al_udma *udma);
-
-/* Misc configurations */
-/* Configure AXI configuration */
-int al_udma_axi_set(struct udma_gen_axi *axi_regs,
-		    struct al_udma_axi_conf *axi);
-
-/* Configure UDMA AXI M2S configuration */
-int al_udma_m2s_axi_set(struct al_udma *udma,
-			struct al_udma_m2s_axi_conf *axi_m2s);
-
-/* Configure UDMA AXI S2M configuration */
-int al_udma_s2m_axi_set(struct al_udma *udma,
-			struct al_udma_s2m_axi_conf *axi_s2m);
-
-/* Configure M2S packet len */
-int al_udma_m2s_packet_size_cfg_set(struct al_udma *udma,
-				    struct al_udma_m2s_pkt_len_conf *conf);
-
-/* Configure M2S UDMA descriptor prefetch */
-int al_udma_m2s_pref_set(struct al_udma *udma,
-			 struct al_udma_m2s_desc_pref_conf *conf);
-int al_udma_m2s_pref_get(struct al_udma *udma,
-			 struct al_udma_m2s_desc_pref_conf *conf);
-
-/* set m2s packet's max descriptors (including meta descriptors) */
-#define AL_UDMA_M2S_MAX_ALLOWED_DESCS_PER_PACKET	31
-int al_udma_m2s_max_descs_set(struct al_udma *udma, uint8_t max_descs);
-
-/* set s2m packets' max descriptors */
-#define AL_UDMA_S2M_MAX_ALLOWED_DESCS_PER_PACKET	31
-int al_udma_s2m_max_descs_set(struct al_udma *udma, uint8_t max_descs);
-
-
-/* Configure S2M UDMA descriptor prefetch */
-int al_udma_s2m_pref_set(struct al_udma *udma,
-			 struct al_udma_s2m_desc_pref_conf *conf);
-int al_udma_m2s_pref_get(struct al_udma *udma,
-			 struct al_udma_m2s_desc_pref_conf *conf);
-
-/* Configure S2M UDMA data write */
-int al_udma_s2m_data_write_set(struct al_udma *udma,
-			       struct al_udma_s2m_data_write_conf *conf);
-
-/* Configure the s2m full line write feature */
-int al_udma_s2m_full_line_write_set(struct al_udma *umda, al_bool enable);
-
-/* Configure S2M UDMA completion */
-int al_udma_s2m_completion_set(struct al_udma *udma,
-			       struct al_udma_s2m_completion_conf *conf);
-
-/* Configure the M2S UDMA scheduling mode */
-int al_udma_m2s_sc_set(struct al_udma *udma,
-		       struct al_udma_m2s_dwrr_conf *sched);
-
-/* Configure the M2S UDMA rate limitation */
-int al_udma_m2s_rlimit_set(struct al_udma *udma,
-			   struct al_udma_m2s_rlimit_mode *mode);
-int al_udma_m2s_rlimit_reset(struct al_udma *udma);
-
-/* Configure the M2S Stream rate limitation */
-int al_udma_m2s_strm_rlimit_set(struct al_udma *udma,
-				struct al_udma_m2s_rlimit_cfg *conf);
-int al_udma_m2s_strm_rlimit_act(struct al_udma *udma,
-				enum al_udma_m2s_rlimit_action act);
-
-/* Configure the M2S UDMA Q rate limitation */
-int al_udma_m2s_q_rlimit_set(struct al_udma_q *udma_q,
-			     struct al_udma_m2s_rlimit_cfg *conf);
-int al_udma_m2s_q_rlimit_act(struct al_udma_q *udma_q,
-			     enum al_udma_m2s_rlimit_action act);
-
-/* Configure the M2S UDMA Q scheduling mode */
-int al_udma_m2s_q_sc_set(struct al_udma_q *udma_q,
-			 struct al_udma_m2s_q_dwrr_conf *conf);
-int al_udma_m2s_q_sc_pause(struct al_udma_q *udma_q, al_bool set);
-int al_udma_m2s_q_sc_reset(struct al_udma_q *udma_q);
-
-/* M2S UDMA completion and application timeouts */
-int al_udma_m2s_comp_timeouts_set(struct al_udma *udma,
-				  struct al_udma_m2s_comp_timeouts *conf);
-int al_udma_m2s_comp_timeouts_get(struct al_udma *udma,
-				  struct al_udma_m2s_comp_timeouts *conf);
-
-/* UDMA get revision */
-static INLINE unsigned int al_udma_get_revision(struct unit_regs __iomem *unit_regs)
-{
-	return (al_reg_read32(&unit_regs->gen.dma_misc.revision)
-			& UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK) >>
-			UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT;
-}
-
-/**
- * S2M UDMA Configure the expected behavior of Rx/S2M UDMA when there are no Rx Descriptors.
- *
- * @param udma
- * @param drop_packet when set to true, the UDMA will drop packet.
- * @param gen_interrupt when set to true, the UDMA will generate
- *        no_desc_hint interrupt when a packet received and the UDMA
- *	  doesn't find enough free descriptors for it.
- * @param wait_for_desc_timeout timeout in SB cycles to wait for new
- *	  descriptors before dropping the packets.
- *	  Notes:
- *		- The hint interrupt is raised immediately without waiting
- *		for new descs.
- *		- value 0 means wait for ever.
- *
- * Notes:
- * - When get_interrupt is set, the API won't program the iofic to unmask this
- * interrupt, in this case the callee should take care for doing that unmask
- * using the al_udma_iofic_config() API.
- *
- * - The hardware's default configuration is: no drop packet, generate hint
- * interrupt.
- * - This API must be called once and before enabling the UDMA
- *
- * @return 0 if no error found.
- */
-int al_udma_s2m_no_desc_cfg_set(struct al_udma *udma, al_bool drop_packet, al_bool gen_interrupt, uint32_t wait_for_desc_timeout);
-
-/**
- * S2M UDMA configure a queue's completion update
- *
- * @param q_udma
- * @param enable set to true to enable completion update
- *
- * completion update better be disabled for tx queues as those descriptors
- * doesn't carry useful information, thus disabling it saves DMA accesses.
- *
- * @return 0 if no error found.
- */
-int al_udma_s2m_q_compl_updade_config(struct al_udma_q *udma_q, al_bool enable);
-
-/**
- * S2M UDMA configure a queue's completion descriptors coalescing
- *
- * @param q_udma
- * @param enable set to true to enable completion coalescing
- * @param coal_timeout in South Bridge cycles.
- *
- * @return 0 if no error found.
- */
-int al_udma_s2m_q_compl_coal_config(struct al_udma_q *udma_q, al_bool enable, uint32_t coal_timeout);
-
-/**
- * S2M UDMA configure completion descriptors write burst parameters
- *
- * @param udma
- * @param burst_size completion descriptors write burst size in bytes.
- *
- * @return 0 if no error found.
- */int al_udma_s2m_compl_desc_burst_config(struct al_udma *udma, uint16_t
-		 burst_size);
-
-/**
- * S2M UDMA configure a queue's completion header split
- *
- * @param q_udma
- * @param enable set to true to enable completion header split
- * @param force_hdr_split the header split length will be taken from the queue configuration
- * @param hdr_len header split length.
- *
- * @return 0 if no error found.
- */
-int al_udma_s2m_q_compl_hdr_split_config(struct al_udma_q *udma_q,
-					 al_bool enable,
-					 al_bool force_hdr_split,
-					 uint32_t hdr_len);
-
-/* S2M UDMA per queue completion configuration */
-int al_udma_s2m_q_comp_set(struct al_udma_q *udma_q,
-			   struct al_udma_s2m_q_comp_conf *conf);
-
-/** UDMA VMID control configuration */
-void al_udma_gen_vmid_conf_set(
-	struct unit_regs __iomem	*unit_regs,
-	struct al_udma_gen_vmid_conf	*conf);
-
-/** UDMA VMID MSIX control configuration */
-void al_udma_gen_vmid_msix_conf_set(
-	struct unit_regs __iomem		*unit_regs,
-	struct al_udma_gen_vmid_msix_conf	*conf);
-
-/** UDMA VMID control advanced Tx queue configuration */
-void al_udma_gen_vmid_advanced_tx_q_conf(
-	struct al_udma_q				*q,
-	struct al_udma_gen_vmid_advanced_tx_q_conf	*conf);
-
-/** UDMA VMID control advanced Rx queue configuration */
-void al_udma_gen_vmid_advanced_rx_q_conf(
-	struct al_udma_q				*q,
-	struct al_udma_gen_vmid_advanced_rx_q_conf	*conf);
-
-/** UDMA header split buffer 2 Rx queue configuration */
-void al_udma_gen_hdr_split_buff2_rx_q_conf(
-	struct al_udma_q				*q,
-	struct al_udma_gen_hdr_split_buff2_q_conf	*conf);
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-/** @} end of UDMA config group */
-#endif /* __AL_HAL_UDMA_CONFIG_H__ */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_debug.c b/sys/contrib/alpine-hal/eth/al_hal_udma_debug.c
deleted file mode 100644
index c6b9bf4b9bf0..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_debug.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @file   al_hal_udma_debug.c
- *
- * @brief  Universal DMA HAL driver for debug
- *
- */
-
-#define DEBUG
-
-#include <al_hal_common.h>
-#include <al_hal_udma_regs.h>
-#include <al_hal_udma_debug.h>
-
-static void al_udma_regs_m2s_axi_print(struct al_udma *udma)
-{
-	al_dbg("M2S AXI regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, comp_wr_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, comp_wr_cfg_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, data_rd_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, data_rd_cfg_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_rd_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_rd_cfg_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, data_rd_cfg);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_rd_cfg_3);
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_wr_cfg_1);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, axi_m2s,
-			desc_wr_cfg_1,
-			max_axi_beats,
-			UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, axi_m2s,
-			desc_wr_cfg_1,
-			min_axi_beats,
-			UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS);
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, ostand_cfg);
-}
-
-static void al_udma_regs_m2s_general_print(struct al_udma *udma)
-{
-	al_dbg("M2S general regs:\n");
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, state);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s, state,
-			comp_ctrl,
-			UDMA_M2S_STATE_COMP_CTRL);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s, state,
-			stream_if,
-			UDMA_M2S_STATE_STREAM_IF);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s, state,
-			rd_ctrl,
-			UDMA_M2S_STATE_DATA_RD_CTRL);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s, state,
-			desc_pref,
-			UDMA_M2S_STATE_DESC_PREF);
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, err_log_mask);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_0);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_3);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, data_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, header_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, unack_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, check_en);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, fifo_en);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, cfg_len);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, stream_cfg);
-}
-
-static void al_udma_regs_m2s_rd_print(struct al_udma *udma)
-{
-	al_dbg("M2S read regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, desc_pref_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, desc_pref_cfg_2);
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, desc_pref_cfg_3);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_rd,
-			desc_pref_cfg_3,
-			min_burst_below_thr,
-			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_rd,
-			desc_pref_cfg_3,
-			min_burst_above_thr,
-			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_rd,
-			desc_pref_cfg_3,
-			pref_thr,
-			UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR);
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, data_cfg);
-}
-
-static void al_udma_regs_m2s_dwrr_print(struct al_udma *udma)
-{
-	al_dbg("M2S DWRR regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_dwrr, cfg_sched);
-}
-
-static void al_udma_regs_m2s_rate_limiter_print(struct al_udma *udma)
-{
-	al_dbg("M2S rate limiter regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rate_limiter, gen_cfg);
-}
-
-static void al_udma_regs_m2s_stream_rate_limiter_print(struct al_udma *udma)
-{
-	al_dbg("M2S stream rate limiter regs:\n");
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
-			rlimit.cfg_1s);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
-			rlimit.cfg_cycle);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
-			rlimit.cfg_token_size_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
-			rlimit.cfg_token_size_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
-			rlimit.mask);
-}
-
-static void al_udma_regs_m2s_comp_print(struct al_udma *udma)
-{
-	al_dbg("M2S completion regs:\n");
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_comp, cfg_1c);
-
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_comp, cfg_1c,
-			comp_fifo_depth,
-			UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_comp, cfg_1c,
-			unack_fifo_depth,
-			UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH);
-	AL_UDMA_PRINT_REG_BIT(udma, "  ", "\n", m2s, m2s_comp, cfg_1c,
-			q_promotion,
-			UDMA_M2S_COMP_CFG_1C_Q_PROMOTION);
-	AL_UDMA_PRINT_REG_BIT(udma, "  ", "\n", m2s, m2s_comp, cfg_1c,
-			force_rr,
-			UDMA_M2S_COMP_CFG_1C_FORCE_RR);
-	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_comp, cfg_1c,
-			q_free_min,
-			UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN);
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_comp, cfg_coal);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_comp, cfg_application_ack);
-}
-
-static void al_udma_regs_m2s_stat_print(struct al_udma *udma)
-{
-	al_dbg("M2S statistics regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, cfg_st);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, tx_pkt);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, tx_bytes_low);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, tx_bytes_high);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, prefed_desc);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, comp_pkt);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, comp_desc);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, ack_pkts);
-}
-
-static void al_udma_regs_m2s_feature_print(struct al_udma *udma)
-{
-	al_dbg("M2S feature regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_3);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_4);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_5);
-}
-
-static void al_udma_regs_m2s_q_print(struct al_udma *udma, uint32_t qid)
-{
-	al_dbg("M2S Q[%d] status regs:\n", qid);
-	al_reg_write32(&udma->udma_regs->m2s.m2s.indirect_ctrl, qid);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_pref_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_comp_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_rate_limit_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_dwrr_status);
-
-	al_dbg("M2S Q[%d] regs:\n", qid);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], cfg);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrbp_low);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrbp_high);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrl);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrhp);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrtp);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdcp);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tcrbp_low);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tcrbp_high);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tcrhp);
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], rlimit.cfg_1s);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], rlimit.cfg_cycle);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid],
-			rlimit.cfg_token_size_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid],
-			rlimit.cfg_token_size_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], rlimit.mask);
-
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], dwrr_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], dwrr_cfg_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], dwrr_cfg_3);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], comp_cfg);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], q_tx_pkt);
-}
-
-static void al_udma_regs_s2m_axi_print(struct al_udma *udma)
-{
-	al_dbg("S2M AXI regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, data_wr_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, data_wr_cfg_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_rd_cfg_4);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_rd_cfg_5);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, comp_wr_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, comp_wr_cfg_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, data_wr_cfg);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_rd_cfg_3);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_wr_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, ostand_cfg_rd);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, ostand_cfg_wr);
-}
-
-static void al_udma_regs_s2m_general_print(struct al_udma *udma)
-{
-	al_dbg("S2M general regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, state);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, err_log_mask);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_0);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_3);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, s_data_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, s_header_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, axi_data_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, unack_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, check_en);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, fifo_en);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, stream_cfg);
-}
-
-static void al_udma_regs_s2m_rd_print(struct al_udma *udma)
-{
-	al_dbg("S2M read regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_3);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_4);
-}
-
-static void al_udma_regs_s2m_wr_print(struct al_udma *udma)
-{
-	al_dbg("S2M write regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_wr, data_cfg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_wr, data_cfg_1);
-}
-
-static void al_udma_regs_s2m_comp_print(struct al_udma *udma)
-{
-	al_dbg("S2M completion regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_comp, cfg_1c);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_comp, cfg_2c);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_comp, cfg_application_ack);
-}
-
-static void al_udma_regs_s2m_stat_print(struct al_udma *udma)
-{
-	al_dbg("S2M statistics regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, drop_pkt);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, rx_bytes_low);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, rx_bytes_high);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, prefed_desc);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, comp_pkt);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, comp_desc);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, ack_pkts);
-}
-
-static void al_udma_regs_s2m_feature_print(struct al_udma *udma)
-{
-	al_dbg("S2M feature regs:\n");
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_1);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_3);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_4);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_5);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_6);
-}
-
-static void al_udma_regs_s2m_q_print(struct al_udma *udma, uint32_t qid)
-{
-	al_dbg("S2M Q[%d] status regs:\n", qid);
-	al_reg_write32(&udma->udma_regs->m2s.m2s.indirect_ctrl, qid);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, sel_pref_fifo_status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, sel_comp_fifo_status);
-
-	al_dbg("S2M Q[%d] regs:\n", qid);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], cfg);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], status);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrbp_low);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrbp_high);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrl);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrhp);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrtp);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdcp);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrbp_low);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrbp_high);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrhp);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrhp_internal);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], comp_cfg);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], comp_cfg_2);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], pkt_cfg);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], qos_cfg);
-	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], q_rx_pkt);
-}
-
-void al_udma_regs_print(struct al_udma *udma, unsigned int mask)
-{
-	uint32_t i;
-
-	if (!udma)
-		return;
-
-	if (udma->type == UDMA_TX) {
-		if (mask & AL_UDMA_DEBUG_AXI)
-			al_udma_regs_m2s_axi_print(udma);
-		if (mask & AL_UDMA_DEBUG_GENERAL)
-			al_udma_regs_m2s_general_print(udma);
-		if (mask & AL_UDMA_DEBUG_READ)
-			al_udma_regs_m2s_rd_print(udma);
-		if (mask & AL_UDMA_DEBUG_DWRR)
-			al_udma_regs_m2s_dwrr_print(udma);
-		if (mask & AL_UDMA_DEBUG_RATE_LIMITER)
-			al_udma_regs_m2s_rate_limiter_print(udma);
-		if (mask & AL_UDMA_DEBUG_STREAM_RATE_LIMITER)
-			al_udma_regs_m2s_stream_rate_limiter_print(udma);
-		if (mask & AL_UDMA_DEBUG_COMP)
-			al_udma_regs_m2s_comp_print(udma);
-		if (mask & AL_UDMA_DEBUG_STAT)
-			al_udma_regs_m2s_stat_print(udma);
-		if (mask & AL_UDMA_DEBUG_FEATURE)
-			al_udma_regs_m2s_feature_print(udma);
-		for (i = 0; i < DMA_MAX_Q; i++) {
-			if (mask & AL_UDMA_DEBUG_QUEUE(i))
-				al_udma_regs_m2s_q_print(udma, i);
-		}
-	} else {
-		if (mask & AL_UDMA_DEBUG_AXI)
-			al_udma_regs_s2m_axi_print(udma);
-		if (mask & AL_UDMA_DEBUG_GENERAL)
-			al_udma_regs_s2m_general_print(udma);
-		if (mask & AL_UDMA_DEBUG_READ)
-			al_udma_regs_s2m_rd_print(udma);
-		if (mask & AL_UDMA_DEBUG_WRITE)
-			al_udma_regs_s2m_wr_print(udma);
-		if (mask & AL_UDMA_DEBUG_COMP)
-			al_udma_regs_s2m_comp_print(udma);
-		if (mask & AL_UDMA_DEBUG_STAT)
-			al_udma_regs_s2m_stat_print(udma);
-		if (mask & AL_UDMA_DEBUG_FEATURE)
-			al_udma_regs_s2m_feature_print(udma);
-		for (i = 0; i < DMA_MAX_Q; i++) {
-			if (mask & AL_UDMA_DEBUG_QUEUE(i))
-				al_udma_regs_s2m_q_print(udma, i);
-		}
-	}
-}
-
-void al_udma_q_struct_print(struct al_udma *udma, uint32_t qid)
-{
-	struct al_udma_q *queue;
-
-	if (!udma)
-		return;
-
-	if (qid >= DMA_MAX_Q)
-		return;
-
-	queue = &udma->udma_q[qid];
-
-	al_dbg("Q[%d] struct:\n", qid);
-	al_dbg(" size_mask = 0x%08x\n", (uint32_t)queue->size_mask);
-	al_dbg(" q_regs = %p\n", queue->q_regs);
-	al_dbg(" desc_base_ptr = %p\n", queue->desc_base_ptr);
-	al_dbg(" next_desc_idx = %d\n", (uint16_t)queue->next_desc_idx);
-	al_dbg(" desc_ring_id = %d\n", (uint32_t)queue->desc_ring_id);
-	al_dbg(" cdesc_base_ptr = %p\n", queue->cdesc_base_ptr);
-	al_dbg(" cdesc_size = %d\n", (uint32_t)queue->cdesc_size);
-	al_dbg(" next_cdesc_idx = %d\n", (uint16_t)queue->next_cdesc_idx);
-	al_dbg(" end_cdesc_ptr = %p\n", queue->end_cdesc_ptr);
-	al_dbg(" comp_head_idx = %d\n", (uint16_t)queue->comp_head_idx);
-	al_dbg(" comp_head_ptr = %p\n", queue->comp_head_ptr);
-	al_dbg(" pkt_crnt_descs = %d\n", (uint32_t)queue->pkt_crnt_descs);
-	al_dbg(" comp_ring_id = %d\n", (uint32_t)queue->comp_ring_id);
-	al_dbg(" desc_phy_base = 0x%016llx\n", (uint64_t)queue->desc_phy_base);
-	al_dbg(" cdesc_phy_base = 0x%016llx\n",
-			(uint64_t)queue->cdesc_phy_base);
-	al_dbg(" flags = 0x%08x\n", (uint32_t)queue->flags);
-	al_dbg(" size = %d\n", (uint32_t)queue->size);
-	al_dbg(" status = %d\n", (uint32_t)queue->status);
-	al_dbg(" udma = %p\n", queue->udma);
-	al_dbg(" qid = %d\n", (uint32_t)queue->qid);
-}
-
-void al_udma_ring_print(struct al_udma *udma, uint32_t qid,
-		enum al_udma_ring_type rtype)
-{
-	struct al_udma_q *queue;
-	uint32_t desc_size;
-	void *base_ptr;
-	uint32_t i;
-
-	if (!udma)
-		return;
-
-	if (qid >= DMA_MAX_Q)
-		return;
-
-	queue = &udma->udma_q[qid];
-	if (rtype == AL_RING_SUBMISSION) {
-		base_ptr = queue->desc_base_ptr;
-		desc_size = sizeof(union al_udma_desc);
-		if (base_ptr)
-			al_dbg("Q[%d] submission ring pointers:\n", qid);
-		else {
-			al_dbg("Q[%d] submission ring is not allocated\n", qid);
-			return;
-		}
-	} else {
-		base_ptr = queue->cdesc_base_ptr;
-		desc_size = queue->cdesc_size;
-		if (base_ptr)
-			al_dbg("Q[%d] completion ring pointers:\n", qid);
-		else {
-			al_dbg("Q[%d] completion ring is not allocated\n", qid);
-			return;
-		}
-	}
-
-	for (i = 0; i < queue->size; i++) {
-		uint32_t *curr_addr = (void*)((uint32_t)base_ptr + i * desc_size);
-		if (desc_size == 16)
-			al_dbg("[%04d](%p): %08x %08x %08x %08x\n",
-					i,
-					curr_addr,
-					(uint32_t)*curr_addr,
-					(uint32_t)*(curr_addr+1),
-					(uint32_t)*(curr_addr+2),
-					(uint32_t)*(curr_addr+3));
-		else if (desc_size == 8)
-			al_dbg("[%04d](%p): %08x %08x\n",
-					i,
-					curr_addr,
-					(uint32_t)*curr_addr,
-					(uint32_t)*(curr_addr+1));
-		else if (desc_size == 4)
-			al_dbg("[%04d](%p): %08x\n",
-					i,
-					curr_addr,
-					(uint32_t)*curr_addr);
-		else
-			break;
-	}
-}
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_debug.h b/sys/contrib/alpine-hal/eth/al_hal_udma_debug.h
deleted file mode 100644
index 7bd1d972917a..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_debug.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_udma_debug UDMA Debug
- * @ingroup group_udma_api
- *  UDMA Debug
- *  @{
- * @file   al_hal_udma_debug.h
- *
- * @brief C Header file for the Universal DMA HAL driver for debug APIs
- *
- */
-
-#ifndef __AL_HAL_UDMA_DEBUG_H__
-#define __AL_HAL_UDMA_DEBUG_H__
-
-#include <al_hal_udma.h>
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/* UDMA register print helper macros */
-#define AL_UDMA_PRINT_REG(UDMA, PREFIX, POSTFIX, TYPE, GROUP, REG) \
-	al_dbg(PREFIX #REG " = 0x%08x" POSTFIX, al_reg_read32( \
-		&(UDMA->udma_regs->TYPE.GROUP.REG)))
-
-#define AL_UDMA_PRINT_REG_FIELD( \
-		UDMA, PREFIX, POSTFIX, FMT, TYPE, GROUP, REG, LBL, FIELD) \
-	al_dbg(PREFIX #LBL " = " FMT POSTFIX, al_reg_read32( \
-			&(UDMA->udma_regs->TYPE.GROUP.REG)) \
-			& FIELD ## _MASK >> FIELD ## _SHIFT)
-
-#define AL_UDMA_PRINT_REG_BIT( \
-		UDMA, PREFIX, POSTFIX, TYPE, GROUP, REG, LBL, FIELD) \
-	al_dbg(PREFIX #LBL " = %d" POSTFIX, ((al_reg_read32( \
-			&(UDMA->udma_regs->TYPE.GROUP.REG)) \
-			& FIELD) != 0))
-
-/* UDMA register print mask definitions */
-#define AL_UDMA_DEBUG_QUEUE(n)			AL_BIT(n)
-#define AL_UDMA_DEBUG_AXI			AL_BIT(DMA_MAX_Q)
-#define AL_UDMA_DEBUG_GENERAL			AL_BIT(DMA_MAX_Q + 1)
-#define AL_UDMA_DEBUG_READ			AL_BIT(DMA_MAX_Q + 2)
-#define AL_UDMA_DEBUG_WRITE			AL_BIT(DMA_MAX_Q + 3)
-#define AL_UDMA_DEBUG_DWRR			AL_BIT(DMA_MAX_Q + 4)
-#define AL_UDMA_DEBUG_RATE_LIMITER		AL_BIT(DMA_MAX_Q + 5)
-#define AL_UDMA_DEBUG_STREAM_RATE_LIMITER	AL_BIT(DMA_MAX_Q + 6)
-#define AL_UDMA_DEBUG_COMP			AL_BIT(DMA_MAX_Q + 7)
-#define AL_UDMA_DEBUG_STAT			AL_BIT(DMA_MAX_Q + 8)
-#define AL_UDMA_DEBUG_FEATURE			AL_BIT(DMA_MAX_Q + 9)
-#define AL_UDMA_DEBUG_ALL			0xFFFFFFFF
-
-/* Debug functions */
-
-/**
- * Print udma registers according to the provided mask
- *
- * @param udma udma data structure
- * @param mask mask that specifies which registers groups to print
- * e.g. AL_UDMA_DEBUG_AXI prints AXI registers, AL_UDMA_DEBUG_ALL prints all
- * registers
- */
-void al_udma_regs_print(struct al_udma *udma, unsigned int mask);
-
-/**
- * Print udma queue software structure
- *
- * @param udma udma data structure
- * @param qid queue index
- */
-void al_udma_q_struct_print(struct al_udma *udma, uint32_t qid);
-
-/** UDMA ring type */
-enum al_udma_ring_type {
-	AL_RING_SUBMISSION,
-	AL_RING_COMPLETION
-};
-
-/**
- * Print the ring entries for the specified queue index and ring type
- * (submission/completion)
- *
- * @param udma udma data structure
- * @param qid queue index
- * @param rtype udma ring type
- */
-void al_udma_ring_print(struct al_udma *udma, uint32_t qid,
-		enum al_udma_ring_type rtype);
-
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-#endif /* __AL_HAL_UDMA_DEBUG_H__ */
-/** @} end of UDMA debug group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_iofic.c b/sys/contrib/alpine-hal/eth/al_hal_udma_iofic.c
deleted file mode 100644
index d6ba485296c3..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_iofic.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_udma_iofic.c
- *
- * @brief  unit interrupts configurations
- *
- */
-
-#include "al_hal_udma_iofic.h"
-#include "al_hal_udma_regs.h"
-
-/*
- * configure the interrupt registers, interrupts will are kept masked
- */
-static int al_udma_main_iofic_config(struct al_iofic_regs __iomem *base,
-				    enum al_iofic_mode mode)
-{
-	switch (mode) {
-	case AL_IOFIC_MODE_LEGACY:
-		al_iofic_config(base, AL_INT_GROUP_A,
-				INT_CONTROL_GRP_SET_ON_POSEDGE |
-				INT_CONTROL_GRP_MASK_MSI_X |
-				INT_CONTROL_GRP_CLEAR_ON_READ);
-		al_iofic_config(base, AL_INT_GROUP_B,
-				INT_CONTROL_GRP_CLEAR_ON_READ |
-				INT_CONTROL_GRP_MASK_MSI_X);
-		al_iofic_config(base, AL_INT_GROUP_C,
-				INT_CONTROL_GRP_CLEAR_ON_READ |
-				INT_CONTROL_GRP_MASK_MSI_X);
-		al_iofic_config(base, AL_INT_GROUP_D,
-				INT_CONTROL_GRP_SET_ON_POSEDGE |
-				INT_CONTROL_GRP_MASK_MSI_X |
-				INT_CONTROL_GRP_CLEAR_ON_READ);
-		break;
-	case AL_IOFIC_MODE_MSIX_PER_Q:
-		al_iofic_config(base, AL_INT_GROUP_A,
-				INT_CONTROL_GRP_SET_ON_POSEDGE |
-				INT_CONTROL_GRP_AUTO_MASK |
-				INT_CONTROL_GRP_AUTO_CLEAR);
-		al_iofic_config(base, AL_INT_GROUP_B,
-				INT_CONTROL_GRP_AUTO_CLEAR |
-				INT_CONTROL_GRP_AUTO_MASK |
-				INT_CONTROL_GRP_CLEAR_ON_READ);
-		al_iofic_config(base, AL_INT_GROUP_C,
-				INT_CONTROL_GRP_AUTO_CLEAR |
-				INT_CONTROL_GRP_AUTO_MASK |
-				INT_CONTROL_GRP_CLEAR_ON_READ);
-		al_iofic_config(base, AL_INT_GROUP_D,
-				INT_CONTROL_GRP_SET_ON_POSEDGE |
-				INT_CONTROL_GRP_CLEAR_ON_READ |
-				INT_CONTROL_GRP_MASK_MSI_X);
-		break;
-	case AL_IOFIC_MODE_MSIX_PER_GROUP:
-		al_iofic_config(base, AL_INT_GROUP_A,
-				INT_CONTROL_GRP_SET_ON_POSEDGE |
-				INT_CONTROL_GRP_AUTO_CLEAR |
-				INT_CONTROL_GRP_AUTO_MASK);
-		al_iofic_config(base, AL_INT_GROUP_B,
-				INT_CONTROL_GRP_CLEAR_ON_READ |
-				INT_CONTROL_GRP_MASK_MSI_X);
-		al_iofic_config(base, AL_INT_GROUP_C,
-				INT_CONTROL_GRP_CLEAR_ON_READ |
-				INT_CONTROL_GRP_MASK_MSI_X);
-		al_iofic_config(base, AL_INT_GROUP_D,
-				INT_CONTROL_GRP_SET_ON_POSEDGE |
-				INT_CONTROL_GRP_CLEAR_ON_READ |
-				INT_CONTROL_GRP_MASK_MSI_X);
-		break;
-	default:
-		al_err("%s: invalid mode (%d)\n", __func__, mode);
-		return -EINVAL;
-	}
-
-	al_dbg("%s: base.%p mode %d\n", __func__, base, mode);
-	return 0;
-}
-
-/*
- * configure the UDMA interrupt registers, interrupts are kept masked
- */
-int al_udma_iofic_config(struct unit_regs __iomem *regs, enum al_iofic_mode mode,
-			uint32_t	m2s_errors_disable,
-			uint32_t	m2s_aborts_disable,
-			uint32_t	s2m_errors_disable,
-			uint32_t	s2m_aborts_disable)
-{
-	int rc;
-
-	rc = al_udma_main_iofic_config(&regs->gen.interrupt_regs.main_iofic, mode);
-	if (rc != 0)
-		return rc;
-
-	al_iofic_unmask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_A, ~m2s_errors_disable);
-	al_iofic_abort_mask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_A, m2s_aborts_disable);
-
-	al_iofic_unmask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_B, ~s2m_errors_disable);
-	al_iofic_abort_mask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_B, s2m_aborts_disable);
-
-	al_dbg("%s base.%p mode %d\n", __func__, regs, mode);
-	return 0;
-}
-
-/*
- * return the offset of the unmask register for a given group
- */
-uint32_t __iomem * al_udma_iofic_unmask_offset_get(
-	struct unit_regs __iomem	*regs,
-	enum al_udma_iofic_level	level,
-	int				group)
-{
-	al_assert(al_udma_iofic_level_and_group_valid(level, group));
-	return al_iofic_unmask_offset_get(al_udma_iofic_reg_base_get(regs, level), group);
-}
-
-/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_iofic.h b/sys/contrib/alpine-hal/eth/al_hal_udma_iofic.h
deleted file mode 100644
index 9e7950048374..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_iofic.h
+++ /dev/null
@@ -1,614 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_udma_interrupts UDMA I/O Fabric Interrupt Controller
- * @ingroup group_udma_api
- *  UDMA IOFIC API
- *  @{
- * @file   al_hal_udma_iofic.h
- *
- * @brief C Header file for programming the interrupt controller that found
- * in UDMA based units. These APIs rely and use some the Interrupt controller
- * API under al_hal_iofic.h
- */
-
-#ifndef __AL_HAL_UDMA_IOFIC_H__
-#define __AL_HAL_UDMA_IOFIC_H__
-
-#include <al_hal_common.h>
-#include <al_hal_iofic.h>
-#include <al_hal_udma_regs.h>
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/**
- * Interrupt Mode
- * This is the interrupt mode for the primary interrupt level The secondary
- * interrupt level does not have mode and it is always a level sensitive
- * interrupt that is reflected in group D of the primary.
- */
-enum al_iofic_mode {
-	AL_IOFIC_MODE_LEGACY, /**< level-sensitive interrupt wire */
-	AL_IOFIC_MODE_MSIX_PER_Q, /**< per UDMA queue MSI-X interrupt */
-	AL_IOFIC_MODE_MSIX_PER_GROUP
-};
-
-/** interrupt controller level (primary/secondary) */
-enum al_udma_iofic_level {
-	AL_UDMA_IOFIC_LEVEL_PRIMARY,
-	AL_UDMA_IOFIC_LEVEL_SECONDARY
-};
-
-/*
- * The next four groups represents the standard 4 groups in the primary
- * interrupt controller of each bus-master unit in the I/O Fabric.
- * The first two groups can be used when accessing the secondary interrupt
- * controller as well.
- */
-#define AL_INT_GROUP_A		0 /**< summary of the below events */
-#define AL_INT_GROUP_B		1 /**< RX completion queues */
-#define AL_INT_GROUP_C		2 /**< TX completion queues */
-#define AL_INT_GROUP_D		3 /**< Misc */
-
-/*******************************************************************************
- * Primary interrupt controller, group A bits
- ******************************************************************************/
-/* Group A bits which are just summary bits of GROUP B, C and D */
-#define AL_INT_GROUP_A_GROUP_B_SUM	AL_BIT(0)
-#define AL_INT_GROUP_A_GROUP_C_SUM	AL_BIT(1)
-#define AL_INT_GROUP_A_GROUP_D_SUM	AL_BIT(2)
-
-/*******************************************************************************
- * MSIX entry indices
- ******************************************************************************/
-/** MSIX entry index for summary of group D in group A */
-#define AL_INT_MSIX_GROUP_A_SUM_D_IDX 	2
-/** MSIX entry index for RX completion queue 0 */
-#define AL_INT_MSIX_RX_COMPLETION_START	3
-
-/*******************************************************************************
- * Primary interrupt controller, group D bits
- ******************************************************************************/
-#define AL_INT_GROUP_D_CROSS_MAIL_BOXES	\
-			(AL_BIT(0) | AL_BIT(1) | AL_BIT(2) | AL_BIT(3))
-/** Summary of secondary interrupt controller, group A) */
-#define AL_INT_GROUP_D_M2S	AL_BIT(8)
-/** Summary of secondary interrupt controller, group B) */
-#define AL_INT_GROUP_D_S2M	AL_BIT(9)
-#define AL_INT_GROUP_D_SW_TIMER_INT	AL_BIT(10)
-#define AL_INT_GROUP_D_APP_EXT_INT	AL_BIT(11)
-#define AL_INT_GROUP_D_ALL			\
-			AL_INT_GROUP_D_CROSS_MAIL_BOXES | \
-			AL_INT_GROUP_D_M2S | \
-			AL_INT_GROUP_D_S2M | \
-			AL_INT_GROUP_D_SW_TIMER_INT | \
-			AL_INT_GROUP_D_APP_EXT_INT
-
-/*
- * Until this point, all description above is for Groups A/B/C/D in the PRIMARY
- * Interrupt controller.
- * Following are definitions related to the secondary interrupt controller with
- * two cause registers (group A and group B) that covers UDMA M2S/S2M errors.
- * Secondary interrupt controller summary bits are not mapped to the Processor
- * GIC directly, rather they are represented in Group D of the primary interrupt
- * controller.
- */
-
-/******************************************************************************
- * Secondary interrupt Controller, Group A, which holds the TX (M2S) error
- * interrupt bits
- ******************************************************************************/
-
-/**
- * MSIx response
- * MSIX Bus generator response error, the Bus response received with error indication
- */
-#define AL_INT_2ND_GROUP_A_M2S_MSIX_RESP		AL_BIT(27)
-/**
- * MSIx timeout	MSIX Bus generator timeout error.
- * The generator didn't receive bus response for the MSIx write transaction.
- */
-#define AL_INT_2ND_GROUP_A_M2S_MSIX_TO			AL_BIT(26)
-/** Prefetch header buffer parity error */
-#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_HDR_PARITY	AL_BIT(25)
-/** Prefetch descriptor buffer parity error */
-#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_DESC_PARITY	AL_BIT(24)
-/** Data buffer parity error */
-#define AL_INT_2ND_GROUP_A_M2S_DATA_PARITY		AL_BIT(23)
-/** Data header buffer parity error */
-#define AL_INT_2ND_GROUP_A_M2S_HDR_PARITY		AL_BIT(22)
-/** Completion coalescing buffer parity error */
-#define AL_INT_2ND_GROUP_A_M2S_COMPL_COAL_PARITY	AL_BIT(21)
-/** UNACK packets buffer parity error */
-#define AL_INT_2ND_GROUP_A_M2S_UNACK_PKT_PARITY		AL_BIT(20)
-/** ACK packets buffer parity error */
-#define AL_INT_2ND_GROUP_A_M2S_ACK_PKT_PARITY		AL_BIT(19)
-/** AXI data buffer parity error */
-#define AL_INT_2ND_GROUP_A_M2S_AX_DATA_PARITY		AL_BIT(18)
-/**
- * Prefetch Ring ID error
- * A wrong RingId was received while prefetching submission descriptor. This
- * could indicate a software bug or hardware failure, unless the UDMA is
- * working in a mode to ignore RingId (the al_udma_iofic_config() API can be
- * used to configure the UDMA to ignore the Ring ID check)
- */
-#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_RING_ID		AL_BIT(17)
-/**
- * Prefetch last
- * Error in last bit indication of the descriptor
- * Descriptor with Last bit asserted is read from the queue to the prefetch
- * FIFO when the prefetch engine is not in a middle of packet processing (a
- * descriptor with First bit asserted should be read first to indicate start of
- * packet)
- */
-#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_LAST		AL_BIT(16)
-/**
- * Prefetch first
- * Error in first bit indication of the descriptor
- * Descriptor with First bit asserted is read from the queue to the prefetch
- * FIFO while the prefetch engine is in a middle of packet processing ( a
- * descriptor with Last bit asserted should be read to indicate end of packet
- * before starting a new one)
- */
-#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_FIRST		AL_BIT(15)
-/**
- * Prefetch max descriptors
- * Number of descriptors per packet exceeds the configurable maximum
- * descriptors per packet. This could indicate a software bug or a hardware
- * failure.  (The al_udma_m2s_max_descs_set() API is used to configure the
- * maximum descriptors per packet)
- */
-#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_MAX_DESC	AL_BIT(14)
-/**
- * Packet length
- * Packet length exceeds the configurable maximum packet size.  The
- * al_udma_m2s_packet_size_cfg_set() API is used to configure the maximum
- * packet size)
- */
-#define AL_INT_2ND_GROUP_A_M2S_PKT_LEN			AL_BIT(13)
-/**
- * Prefetch AXI timeout
- * Bus request to I/O Fabric timeout error
- */
-#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_AXI_TO		AL_BIT(12)
-/**
- * Prefetch AXI response
- * Bus response from I/O Fabric error
- */
-#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_AXI_RESP	AL_BIT(11)
-/**
- * Prefetch AXI parity
- * Bus parity error on descriptor being prefetched
- */
-#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_AXI_PARITY	AL_BIT(10)
-/**
- * Data AXI timeout
- * Bus request to I/O Fabric timeout error
- */
-#define AL_INT_2ND_GROUP_A_M2S_DATA_AXI_TO		AL_BIT(9)
-/**
- * Data AXI response
- * Bus response from I/O Fabric error
- */
-#define AL_INT_2ND_GROUP_A_M2S_DATA_AXI_RESP		AL_BIT(8)
-/**
- * Data AXI parity
- * Bus parity error on data being read
- */
-#define AL_INT_2ND_GROUP_A_M2S_DATA_AXI_PARITY		AL_BIT(7)
-/**
- * Completion AXI timeout
- * Bus request to I/O Fabric timeout error
- */
-#define AL_INT_2ND_GROUP_A_M2S_CONPL_AXI_TO		AL_BIT(6)
-/**
- * Completion AXI response
- * Bus response from I/O Fabric error
- */
-#define AL_INT_2ND_GROUP_A_M2S_COMPL_AXI_RESP		AL_BIT(5)
-/**
- * Completion AXI parity
- * Bus generator internal SRAM parity error
- */
-#define AL_INT_2ND_GROUP_A_M2S_COMP_AXI_PARITY		AL_BIT(4)
-/**
- * Stream timeout
- * Application stream interface timeout indicating a failure at the Application
- * layer (RAID, Ethernet etc)
- */
-#define AL_INT_2ND_GROUP_A_M2S_STRM_TO			AL_BIT(3)
-/**
- * Stream response
- * Application stream interface response error indicating a failure at the
- * Application layer (RAID, Ethernet etc)
- */
-#define AL_INT_2ND_GROUP_A_M2S_STRM_RESP		AL_BIT(2)
-/**
- * Stream parity
- * Application stream interface parity error indicating a failure at the
- * Application layer (RAID, Ethernet etc)
- */
-#define AL_INT_2ND_GROUP_A_M2S_STRM_PARITY		 AL_BIT(1)
-/**
- * Stream completion mismatch
- * Application stream interface, packet serial mismatch error indicating a
- * failure at the Application layer (RAID, Ethernet etc)
- */
-#define AL_INT_2ND_GROUP_A_M2S_STRM_COMPL_MISMATCH	AL_BIT(0)
-
-/*******************************************************************************
- * Secondary interrupt Controller, Group B, which holds the RX (S2M) error
- * interrupt bits
- ******************************************************************************/
-
-/** Prefetch descriptor buffer parity error */
-#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_DESC_PARITY	AL_BIT(30)
-/** Completion coalescing buffer parity error */
-#define AL_INT_2ND_GROUP_B_S2M_COMPL_COAL_PARITY	AL_BIT(29)
-/** PRE-UNACK packets buffer parity error */
-#define AL_INT_2ND_GROUP_B_S2M_PRE_UNACK_PKT_PARITY	AL_BIT(28)
-/** UNACK packets buffer parity error */
-#define AL_INT_2ND_GROUP_B_S2M_UNACK_PKT_PARITY		AL_BIT(27)
-/** Data buffer parity error */
-#define AL_INT_2ND_GROUP_B_S2M_DATA_PARITY		AL_BIT(26)
-/** Data header buffer parity error */
-#define AL_INT_2ND_GROUP_B_S2M_DATA_HDR_PARITY		AL_BIT(25)
-/**
- * Packet length
- * Application stream interface, Data counter length mismatch with metadata
- * packet length indicating a failure at the Application layer (RAID, Ethernet
- * etc)
- */
-#define AL_INT_2ND_GROUP_B_S2M_PKT_LEN			AL_BIT(24)
-/**
- * Stream last
- * Application stream interface, error in Last bit indication, this error is
- * asserted when a 'last' indication is asserted on the stream interface
- * (between the application and the UDMA) when the interface is not in the
- * middle of packet, meaning that there was no 'first' indication before. This
- * indicates a failure at the application layer.
- */
-#define AL_INT_2ND_GROUP_B_S2M_STRM_LAST		AL_BIT(23)
-/**
- * Stream first
- * Application stream interface error in first bit indication, this error is
- * asserted when a 'first' indication is asserted on the stream interface
- * (between the application and the UDMA) when the interface is in the middle
- * of packet, meaning that there was a 'first' indication before and the UDMA
- * is waiting for a 'last' indication to end the packet. This indicates a
- * failure at the application layer.
- */
-#define AL_INT_2ND_GROUP_B_S2M_STRM_FIRST		AL_BIT(22)
-/**
- * Stream data
- * Application stream interface, error indication during data transaction
- */
-#define AL_INT_2ND_GROUP_B_S2M_STRM_DATA		AL_BIT(21)
-/**
- * Stream Data parity
- * Application stream interface, parity error during data transaction
- */
-#define AL_INT_2ND_GROUP_B_S2M_STRM_DATA_PARITY		AL_BIT(20)
-/**
- * Stream Header error
- * Application stream interface, error indication during header transaction
- */
-#define AL_INT_2ND_GROUP_B_S2M_STRM_HDR			AL_BIT(19)
-/**
- * Stream Header parity
- * Application stream interface, parity error during header transaction
- */
-#define AL_INT_2ND_GROUP_B_S2M_STRM_HDR_PARITY		AL_BIT(18)
-/**
- * Completion UNACK
- * Completion write, UNACK timeout due to completion FIFO back pressure
- */
-#define AL_INT_2ND_GROUP_B_S2M_COMPL_UNACK		AL_BIT(17)
-/**
- * Completion stream
- * Completion write, UNACK timeout due to stream ACK FIFO back pressure
- */
-#define AL_INT_2ND_GROUP_B_S2M_COMPL_STRM		AL_BIT(16)
-/**
- * Completion AXI timeout
- * Bus request to I/O Fabric timeout error
- */
-#define AL_INT_2ND_GROUP_B_S2M_COMPL_AXI_TO		AL_BIT(15)
-/**
- * Completion AXI response
- * Bus response from I/O Fabric error
- */
-#define AL_INT_2ND_GROUP_B_S2M_COMPL_AXI_RESP		AL_BIT(14)
-/**
- * Completion AXI parity
- * Completion Bus generator internal SRAM parity error
- */
-#define AL_INT_2ND_GROUP_B_S2M_COMPL_AXI_PARITY		AL_BIT(13)
-/**
- * Prefetch saturate
- * Prefetch engine, packet length counter saturated (32 bit) , this is caused
- * by an error at the application layer which sends packet data without
- * 'last'/'first' indication.
- */
-#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_SAT		AL_BIT(12)
-/**
- * Prefetch ring ID
- * Prefetch engine, Ring ID is not matching the expected RingID. This could
- * indicate a software bug or hardware failure, unless the UDMA is working in a
- * mode to ignore RingId  (the al_udma_iofic_config() API can be used to
- * configure the UDMA to ignore the Ring ID check)
- */
-#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_RING_ID		AL_BIT(11)
-/**
- * Prefetch AXI timeout
- * Bus request to I/O Fabric timeout error
- */
-#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_AXI_TO		AL_BIT(10)
-/**
- * Prefetch AXI response
- * Bus response from I/O Fabric error
- */
-#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_AXI_RESP	AL_BIT(9)
-/**
- * Prefetch AXI parity
- * Bus parity error on descriptor being prefetched
- */
-#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_AXI_PARITY	AL_BIT(8)
-/**
- * No descriptors hint
- * Data write, Hint to the SW that there are not enough descriptors in the
- * queue for the current received packet. This is considered a hint and not an
- * error, as it could be a normal situation in certain application. The S2M
- * UDMA behavior when it runs out of Rx Descriptor is controlled by driver
- * which can use this hint to add more descriptors to the Rx queue.
- */
-#define AL_INT_2ND_GROUP_B_S2M_NO_DESC_HINT		AL_BIT(7)
-/**
- * No descriptors timeout
- * Data write, Timeout indication when there are not enough descriptors for the
- * current packet and the timeout expires. The S2M UDMA behavior when it runs
- * out of Rx Descriptor is controlled by driver which can use this hint to add
- * more descriptors to the Rx queue. The al_udma_s2m_no_desc_cfg_set() is used
- * to configure theUDMA S2M timeout and behavior when there are no Rx
- * descriptors for the received packet.
- */
-#define AL_INT_2ND_GROUP_B_S2M_NO_DESC_TO		AL_BIT(6)
-/**
- * Promotion indication
- * Data write, the data write engine checks the queue number of the two packets
- * at the head of the data FIFO, the data write engine notify the prefetch
- * engine to promote these queue numbers in the prefetch scheduler to make sure
- * that these queue will have RX descriptors for these packets. This error
- * indicates that the prefetch promotion didn't work for the second packet in
- * the FIFO. This is an indication used for system debug and not an error.
- */
-#define AL_INT_2ND_GROUP_B_S2M_PROM_IND			AL_BIT(5)
-/**
- * Header split ignored
- * Data write, The application requested header split but the buffer descriptor
- * doesn't include a second buffer for the header
- */
-#define AL_INT_2ND_GROUP_B_S2M_HDR_SPLT_IGNORED		AL_BIT(4)
-/**
- * Header split length
- * Data write, The application requested header split and the length of the
- * second buffer allocated for the header is not enough for the requested
- * header length. The remaining of the header is written to buffer 1 (data
- * buffer).
- */
-#define AL_INT_2ND_GROUP_B_S2M_HDR_SPLT_LEN		AL_BIT(3)
-/**
- * Data AXI timeout
- * Bus request to I/O Fabric timeout error
- */
-#define AL_INT_2ND_GROUP_B_S2M_DATA_AXI_TO		AL_BIT(2)
-/**
- * Data AXI response
- * Bus response from I/O Fabric error
- */
-#define AL_INT_2ND_GROUP_B_S2M_DATA_AXI_RESP		AL_BIT(1)
-/**
- * Data AXI parity
- * Bus parity error on data being read
- */
-#define AL_INT_2ND_GROUP_B_S2M_DATA_AXI_PARITY		AL_BIT(0)
-
-/*******************************************************************************
- * Configurations
- ******************************************************************************/
-
-/**
- * Configure the UDMA interrupt controller registers, interrupts will are kept
- * masked.
- * This is a static setting that should be called while initialized the
- * interrupt controller within a given UDMA, and should not be modified during
- * runtime unless the UDMA is completely disabled. The first argument sets the
- * interrupt and MSIX modes. The m2s/s2m errors/abort are a set of bit-wise
- * masks to define the behaviour of the UDMA once an error happens: The _abort
- * will put the UDMA in abort state once an error happens The _error bitmask
- * will indicate and error in the secondary cause register but will not abort.
- * The bit-mask that the _errors_disable and _aborts_disable are described in
- * 'AL_INT_2ND_GROUP_A_*' and 'AL_INT_2ND_GROUP_B_*'
- *
- * @param regs pointer to unit registers
- * @param mode interrupt scheme mode (legacy, MSI-X..)
- * @param m2s_errors_disable
- * 	  This is a bit-wise mask, to indicate which one of the error causes in
- * 	  secondary interrupt group_A should generate an interrupt. When a bit is
- * 	  set, the error cause is ignored.
- * 	  Recommended value: 0 (enable all errors).
- * @param m2s_aborts_disable
- * 	  This is a bit-wise mask, to indicate which one of the error causes in
- * 	  secondary interrupt group_A should automatically put the UDMA in
- * 	  abort state. When a bit is set, the error cause does cause an abort.
- * 	  Recommended value: 0 (enable all aborts).
- * @param s2m_errors_disable
- * 	  This is a bit-wise mask, to indicate which one of the error causes in
- * 	  secondary interrupt group_A should generate an interrupt. When a bit is
- * 	  set, the error cause is ignored.
- * 	  Recommended value: 0xE0 (disable hint errors).
- * @param s2m_aborts_disable
- * 	  This is a bit-wise mask, to indicate which one of the error causes in
- * 	  secondary interrupt group_A should automatically put the UDMA in
- * 	  abort state. When a bit is set, the error cause does cause an abort.
- * 	  Recommended value: 0xE0 (disable hint aborts).
- *
- * @return 0 on success. -EINVAL otherwise.
- */
-int al_udma_iofic_config(struct unit_regs __iomem *regs,
-			enum al_iofic_mode mode,
-			uint32_t	m2s_errors_disable,
-			uint32_t	m2s_aborts_disable,
-			uint32_t	s2m_errors_disable,
-			uint32_t	s2m_aborts_disable);
-/**
- * return the offset of the unmask register for a given group.
- * this function can be used when the upper layer wants to directly
- * access the unmask regiter and bypass the al_udma_iofic_unmask() API.
- *
- * @param regs pointer to udma registers
- * @param level the interrupt controller level (primary / secondary)
- * @param group the interrupt group ('AL_INT_GROUP_*')
- * @return the offset of the unmask register.
- */
-uint32_t __iomem * al_udma_iofic_unmask_offset_get(
-	struct unit_regs __iomem	*regs,
-	enum al_udma_iofic_level	level,
-	int				group);
-
-/**
- * Get the interrupt controller base address for either the primary or secondary
- * interrupt controller
- *
- * @param regs pointer to udma unit registers
- * @param level the interrupt controller level (primary / secondary)
- *
- * @returns	The interrupt controller base address
- *
- */
-static INLINE void __iomem *al_udma_iofic_reg_base_get(
-	struct unit_regs __iomem	*regs,
-	enum al_udma_iofic_level	level)
-{
-	void __iomem *iofic_regs = (level == AL_UDMA_IOFIC_LEVEL_PRIMARY) ?
-		(void __iomem *)&regs->gen.interrupt_regs.main_iofic :
-		(void __iomem *)&regs->gen.interrupt_regs.secondary_iofic_ctrl;
-
-	return iofic_regs;
-}
-
-/**
- * Check the interrupt controller level/group validity
- *
- * @param level the interrupt controller level (primary / secondary)
- * @param group the interrupt group ('AL_INT_GROUP_*')
- *
- * @returns	0 - invalid, 1 - valid
- *
- */
-static INLINE int al_udma_iofic_level_and_group_valid(
-	enum al_udma_iofic_level	level,
-	int				group)
-{
-	if (((level == AL_UDMA_IOFIC_LEVEL_PRIMARY) && (group >= 0) && (group < 4)) ||
-		((level == AL_UDMA_IOFIC_LEVEL_SECONDARY) && (group >= 0) && (group < 2)))
-		return 1;
-
-	return 0;
-}
-/**
- * unmask specific interrupts for a given group
- * this functions uses the interrupt mask clear register to guarantee atomicity
- * it's safe to call it while the mask is changed by the HW (auto mask) or another cpu.
- *
- * @param regs pointer to udma unit registers
- * @param level the interrupt controller level (primary / secondary)
- * @param group the interrupt group ('AL_INT_GROUP_*')
- * @param mask bitwise of interrupts to unmask, set bits will be unmasked.
- */
-static INLINE void al_udma_iofic_unmask(
-	struct unit_regs __iomem	*regs,
-	enum al_udma_iofic_level	level,
-	int				group,
-	uint32_t			mask)
-{
-	al_assert(al_udma_iofic_level_and_group_valid(level, group));
-	al_iofic_unmask(al_udma_iofic_reg_base_get(regs, level), group, mask);
-}
-
-/**
- * mask specific interrupts for a given group
- * this functions modifies interrupt mask register, the callee must make sure
- * the mask is not changed by another cpu.
- *
- * @param regs pointer to udma unit registers
- * @param level the interrupt controller level (primary / secondary)
- * @param group the interrupt group ('AL_INT_GROUP_*')
- * @param mask bitwise of interrupts to mask, set bits will be masked.
- */
-static INLINE void al_udma_iofic_mask(
-	struct unit_regs __iomem	*regs,
-	enum al_udma_iofic_level	level,
-	int				group,
-	uint32_t			mask)
-{
-	al_assert(al_udma_iofic_level_and_group_valid(level, group));
-	al_iofic_mask(al_udma_iofic_reg_base_get(regs, level), group, mask);
-}
-
-/**
- * read interrupt cause register for a given group
- * this will clear the set bits if the Clear on Read mode enabled.
- * @param regs pointer to udma unit registers
- * @param level the interrupt controller level (primary / secondary)
- * @param group the interrupt group ('AL_INT_GROUP_*')
- */
-static INLINE uint32_t al_udma_iofic_read_cause(
-	struct unit_regs __iomem	*regs,
-	enum al_udma_iofic_level	level,
-	int				group)
-{
-	al_assert(al_udma_iofic_level_and_group_valid(level, group));
-	return al_iofic_read_cause(al_udma_iofic_reg_base_get(regs, level), group);
-}
-
-#endif
-/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_iofic_regs.h b/sys/contrib/alpine-hal/eth/al_hal_udma_iofic_regs.h
deleted file mode 100644
index 8e53aa673cce..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_iofic_regs.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-
-#ifndef __AL_HAL_UDMA_IOFIC_REG_H
-#define __AL_HAL_UDMA_IOFIC_REG_H
-
-#include "al_hal_iofic_regs.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** This structure covers all interrupt registers of a given UDMA, which is
- * built of an al_iofic_regs, which is the common I/O Fabric Interrupt
- * controller (IOFIC), and additional two interrupts groups dedicated for the
- * application-specific engine attached to the UDMA, the interrupt summary
- * of those two groups routed to gourp D of the main controller.
- */
-struct udma_iofic_regs {
-	struct al_iofic_regs	main_iofic;
-	uint32_t rsrvd1[(0x1c00) >> 2];
-	struct al_iofic_grp_ctrl secondary_iofic_ctrl[2];
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_UDMA_IOFIC_REG_H */
-
-
-
-
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_main.c b/sys/contrib/alpine-hal/eth/al_hal_udma_main.c
deleted file mode 100644
index 6e9919b3596c..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_main.c
+++ /dev/null
@@ -1,618 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_udma_main.c
- *
- * @brief  Universal DMA HAL driver for main functions (initialization, data path)
- *
- */
-
-#include <al_hal_udma.h>
-#include <al_hal_udma_config.h>
-
-#define AL_UDMA_Q_RST_TOUT	10000	/* Queue reset timeout [uSecs] */
-
-#define UDMA_STATE_IDLE		0x0
-#define UDMA_STATE_NORMAL	0x1
-#define UDMA_STATE_ABORT	0x2
-#define UDMA_STATE_RESERVED	0x3
-
-const char *const al_udma_states_name[] = {
-	"Disable",
-	"Idle",
-	"Normal",
-	"Abort",
-	"Reset"
-};
-
-#define AL_UDMA_INITIAL_RING_ID	1
-
-/*  dma_q flags */
-#define AL_UDMA_Q_FLAGS_IGNORE_RING_ID	AL_BIT(0)
-#define AL_UDMA_Q_FLAGS_NO_COMP_UPDATE	AL_BIT(1)
-#define AL_UDMA_Q_FLAGS_EN_COMP_COAL	AL_BIT(2)
-
-
-static void al_udma_set_defaults(struct al_udma *udma)
-{
-	uint32_t tmp;
-	uint8_t rev_id = udma->rev_id;
-
-	if (udma->type == UDMA_TX) {
-		struct unit_regs* tmp_unit_regs =
-			(struct unit_regs*)udma->udma_regs;
-
-		/* Setting the data fifo depth to 4K (256 strips of 16B)
-		 * This allows the UDMA to have 16 outstanding writes */
-		if (rev_id >= AL_UDMA_REV_ID_2) {
-			al_reg_write32_masked(&tmp_unit_regs->m2s.m2s_rd.data_cfg,
-			      UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK,
-			      256 << UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_SHIFT);
-		}
-
-		if (rev_id == AL_UDMA_REV_ID_0)
-			/* disable AXI timeout for M0*/
-			al_reg_write32(&tmp_unit_regs->gen.axi.cfg_1, 0);
-		else
-			/* set AXI timeout to 1M (~2.6 ms) */
-			al_reg_write32(&tmp_unit_regs->gen.axi.cfg_1, 1000000);
-
-		al_reg_write32(&tmp_unit_regs->m2s.m2s_comp.cfg_application_ack
-					, 0); /* Ack time out */
-
-
-		if (rev_id == AL_UDMA_REV_ID_0) {
-			tmp = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1);
-			tmp &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
-			tmp |= 4 << UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT;
-			al_reg_write32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1
-									, tmp);
-		}
-
-	}
-	if (udma->type == UDMA_RX) {
-		al_reg_write32(
-			&udma->udma_regs->s2m.s2m_comp.cfg_application_ack, 0);
-					/* Ack time out */
-
-	}
-}
-/**
- * misc queue configurations
- *
- * @param udma_q udma queue data structure
- *
- * @return 0
- */
-static int al_udma_q_config(struct al_udma_q *udma_q)
-{
-	uint32_t *reg_addr;
-	uint32_t val;
-
-	if (udma_q->udma->type == UDMA_TX) {
-		reg_addr = &udma_q->q_regs->m2s_q.rlimit.mask;
-
-		val = al_reg_read32(reg_addr);
-		// enable DMB
-		val &= ~UDMA_M2S_Q_RATE_LIMIT_MASK_INTERNAL_PAUSE_DMB;
-		al_reg_write32(reg_addr, val);
-	}
-	return 0;
-}
-
-/**
- * set the queue's completion configuration register
- *
- * @param udma_q udma queue data structure
- *
- * @return 0
- */
-static int al_udma_q_config_compl(struct al_udma_q *udma_q)
-{
-	uint32_t *reg_addr;
-	uint32_t val;
-
-	if (udma_q->udma->type == UDMA_TX)
-		reg_addr = &udma_q->q_regs->m2s_q.comp_cfg;
-	else
-		reg_addr = &udma_q->q_regs->s2m_q.comp_cfg;
-
-	val = al_reg_read32(reg_addr);
-
-	if (udma_q->flags & AL_UDMA_Q_FLAGS_NO_COMP_UPDATE)
-		val &= ~UDMA_M2S_Q_COMP_CFG_EN_COMP_RING_UPDATE;
-	else
-		val |= UDMA_M2S_Q_COMP_CFG_EN_COMP_RING_UPDATE;
-
-	if (udma_q->flags & AL_UDMA_Q_FLAGS_EN_COMP_COAL)
-		val &= ~UDMA_M2S_Q_COMP_CFG_DIS_COMP_COAL;
-	else
-		val |= UDMA_M2S_Q_COMP_CFG_DIS_COMP_COAL;
-
-	al_reg_write32(reg_addr, val);
-
-	/* set the completion queue size */
-	if (udma_q->udma->type == UDMA_RX) {
-		val = al_reg_read32(
-				&udma_q->udma->udma_regs->s2m.s2m_comp.cfg_1c);
-		val &= ~UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
-		/* the register expects it to be in words */
-		val |= (udma_q->cdesc_size >> 2)
-				& UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
-		al_reg_write32(&udma_q->udma->udma_regs->s2m.s2m_comp.cfg_1c
-							, val);
-	}
-	return 0;
-}
-
-/**
- * reset the queues pointers (Head, Tail, etc) and set the base addresses
- *
- * @param udma_q udma queue data structure
- */
-static int al_udma_q_set_pointers(struct al_udma_q *udma_q)
-{
-	/* reset the descriptors ring pointers */
-	/* assert descriptor base address aligned. */
-	al_assert((AL_ADDR_LOW(udma_q->desc_phy_base) &
-		   ~UDMA_M2S_Q_TDRBP_LOW_ADDR_MASK) == 0);
-	al_reg_write32(&udma_q->q_regs->rings.drbp_low,
-		       AL_ADDR_LOW(udma_q->desc_phy_base));
-	al_reg_write32(&udma_q->q_regs->rings.drbp_high,
-		       AL_ADDR_HIGH(udma_q->desc_phy_base));
-
-	al_reg_write32(&udma_q->q_regs->rings.drl, udma_q->size);
-
-	/* if completion ring update disabled */
-	if (udma_q->cdesc_base_ptr == NULL) {
-		udma_q->flags |= AL_UDMA_Q_FLAGS_NO_COMP_UPDATE;
-	} else {
-		/* reset the completion descriptors ring pointers */
-		/* assert completion base address aligned. */
-		al_assert((AL_ADDR_LOW(udma_q->cdesc_phy_base) &
-			   ~UDMA_M2S_Q_TCRBP_LOW_ADDR_MASK) == 0);
-		al_reg_write32(&udma_q->q_regs->rings.crbp_low,
-			       AL_ADDR_LOW(udma_q->cdesc_phy_base));
-		al_reg_write32(&udma_q->q_regs->rings.crbp_high,
-			       AL_ADDR_HIGH(udma_q->cdesc_phy_base));
-	}
-	al_udma_q_config_compl(udma_q);
-	return 0;
-}
-
-/**
- * enable/disable udma queue
- *
- * @param udma_q udma queue data structure
- * @param enable none zero value enables the queue, zero means disable
- *
- * @return 0
- */
-static int al_udma_q_enable(struct al_udma_q *udma_q, int enable)
-{
-	uint32_t reg = al_reg_read32(&udma_q->q_regs->rings.cfg);
-
-	if (enable) {
-		reg |= (UDMA_M2S_Q_CFG_EN_PREF | UDMA_M2S_Q_CFG_EN_SCHEDULING);
-		udma_q->status = AL_QUEUE_ENABLED;
-	} else {
-		reg &= ~(UDMA_M2S_Q_CFG_EN_PREF | UDMA_M2S_Q_CFG_EN_SCHEDULING);
-		udma_q->status = AL_QUEUE_DISABLED;
-	}
-	al_reg_write32(&udma_q->q_regs->rings.cfg, reg);
-	return 0;
-}
-
-
-/************************ API functions ***************************************/
-
-/* Initializations functions */
-/*
- * Initialize the udma engine
- */
-int al_udma_init(struct al_udma *udma, struct al_udma_params *udma_params)
-{
-	int i;
-
-	al_assert(udma);
-
-	if (udma_params->num_of_queues > DMA_MAX_Q) {
-		al_err("udma: invalid num_of_queues parameter\n");
-		return -EINVAL;
-	}
-
-	udma->type = udma_params->type;
-	udma->num_of_queues = udma_params->num_of_queues;
-	udma->gen_regs = &udma_params->udma_regs_base->gen;
-
-	if (udma->type == UDMA_TX)
-		udma->udma_regs = (union udma_regs *)&udma_params->udma_regs_base->m2s;
-	else
-		udma->udma_regs = (union udma_regs *)&udma_params->udma_regs_base->s2m;
-
-	udma->rev_id = al_udma_get_revision(udma_params->udma_regs_base);
-
-	if (udma_params->name == NULL)
-		udma->name = "";
-	else
-		udma->name = udma_params->name;
-
-	udma->state = UDMA_DISABLE;
-	for (i = 0; i < DMA_MAX_Q; i++) {
-		udma->udma_q[i].status = AL_QUEUE_NOT_INITIALIZED;
-	}
-	/* initialize configuration registers to correct values */
-	al_udma_set_defaults(udma);
-	al_dbg("udma [%s] initialized. base %p\n", udma->name,
-		udma->udma_regs);
-	return 0;
-}
-
-/*
- * Initialize the udma queue data structure
- */
-int al_udma_q_init(struct al_udma *udma, uint32_t qid,
-					struct al_udma_q_params *q_params)
-{
-	struct al_udma_q *udma_q;
-
-	al_assert(udma);
-	al_assert(q_params);
-
-	if (qid >= udma->num_of_queues) {
-		al_err("udma: invalid queue id (%d)\n", qid);
-		return -EINVAL;
-	}
-
-	if (udma->udma_q[qid].status == AL_QUEUE_ENABLED) {
-		al_err("udma: queue (%d) already enabled!\n", qid);
-		return -EIO;
-	}
-
-	if (q_params->size < AL_UDMA_MIN_Q_SIZE) {
-		al_err("udma: queue (%d) size too small\n", qid);
-		return -EINVAL;
-	}
-
-	if (q_params->size > AL_UDMA_MAX_Q_SIZE) {
-		al_err("udma: queue (%d) size too large\n", qid);
-		return -EINVAL;
-	}
-
-	if (q_params->size & (q_params->size - 1)) {
-		al_err("udma: queue (%d) size (%d) must be power of 2\n",
-			 q_params->size, qid);
-		return -EINVAL;
-	}
-
-	udma_q = &udma->udma_q[qid];
-	/* set the queue's regs base address */
-	if (udma->type == UDMA_TX)
-		udma_q->q_regs = (union udma_q_regs __iomem *)
-					&udma->udma_regs->m2s.m2s_q[qid];
-	else
-		udma_q->q_regs = (union udma_q_regs __iomem *)
-					&udma->udma_regs->s2m.s2m_q[qid];
-
-	udma_q->adapter_rev_id = q_params->adapter_rev_id;
-	udma_q->size = q_params->size;
-	udma_q->size_mask = q_params->size - 1;
-	udma_q->desc_base_ptr = q_params->desc_base;
-	udma_q->desc_phy_base = q_params->desc_phy_base;
-	udma_q->cdesc_base_ptr = q_params->cdesc_base;
-	udma_q->cdesc_phy_base = q_params->cdesc_phy_base;
-	udma_q->cdesc_size = q_params->cdesc_size;
-
-	udma_q->next_desc_idx = 0;
-	udma_q->next_cdesc_idx = 0;
-	udma_q->end_cdesc_ptr = (uint8_t *) udma_q->cdesc_base_ptr +
-	    (udma_q->size - 1) * udma_q->cdesc_size;
-	udma_q->comp_head_idx = 0;
-	udma_q->comp_head_ptr = (union al_udma_cdesc *)udma_q->cdesc_base_ptr;
-	udma_q->desc_ring_id = AL_UDMA_INITIAL_RING_ID;
-	udma_q->comp_ring_id = AL_UDMA_INITIAL_RING_ID;
-#if 0
-	udma_q->desc_ctrl_bits = AL_UDMA_INITIAL_RING_ID <<
-						AL_M2S_DESC_RING_ID_SHIFT;
-#endif
-	udma_q->pkt_crnt_descs = 0;
-	udma_q->flags = 0;
-	udma_q->status = AL_QUEUE_DISABLED;
-	udma_q->udma = udma;
-	udma_q->qid = qid;
-
-	/* start hardware configuration: */
-	al_udma_q_config(udma_q);
-	/* reset the queue pointers */
-	al_udma_q_set_pointers(udma_q);
-
-	/* enable the q */
-	al_udma_q_enable(udma_q, 1);
-
-	al_dbg("udma [%s %d]: %s q init. size 0x%x\n"
-			"  desc ring info: phys base 0x%llx virt base %p\n"
-			"  cdesc ring info: phys base 0x%llx virt base %p "
-				"entry size 0x%x",
-			udma_q->udma->name, udma_q->qid,
-			udma->type == UDMA_TX ? "Tx" : "Rx",
-			q_params->size,
-			(unsigned long long)q_params->desc_phy_base,
-			q_params->desc_base,
-			(unsigned long long)q_params->cdesc_phy_base,
-			q_params->cdesc_base,
-			q_params->cdesc_size);
-
-	return 0;
-}
-
-/*
- * Reset a udma queue
- */
-int al_udma_q_reset(struct al_udma_q *udma_q)
-{
-	unsigned int remaining_time = AL_UDMA_Q_RST_TOUT;
-	uint32_t *status_reg;
-	uint32_t *dcp_reg;
-	uint32_t *crhp_reg;
-	uint32_t *q_sw_ctrl_reg;
-
-	al_assert(udma_q);
-
-	/* De-assert scheduling and prefetch */
-	al_udma_q_enable(udma_q, 0);
-
-	/* Wait for scheduling and prefetch to stop */
-	status_reg = &udma_q->q_regs->rings.status;
-
-	while (remaining_time) {
-		uint32_t status = al_reg_read32(status_reg);
-
-		if (!(status & (UDMA_M2S_Q_STATUS_PREFETCH |
-						UDMA_M2S_Q_STATUS_SCHEDULER)))
-			break;
-
-		remaining_time--;
-		al_udelay(1);
-	}
-
-	if (!remaining_time) {
-		al_err("udma [%s %d]: %s timeout waiting for prefetch and "
-			"scheduler disable\n", udma_q->udma->name, udma_q->qid,
-			__func__);
-		return -ETIMEDOUT;
-	}
-
-	/* Wait for the completion queue to reach to the same pointer as the
-	 * prefetch stopped at ([TR]DCP == [TR]CRHP) */
-	dcp_reg = &udma_q->q_regs->rings.dcp;
-	crhp_reg = &udma_q->q_regs->rings.crhp;
-
-	while (remaining_time) {
-		uint32_t dcp = al_reg_read32(dcp_reg);
-		uint32_t crhp = al_reg_read32(crhp_reg);
-
-		if (dcp == crhp)
-			break;
-
-		remaining_time--;
-		al_udelay(1);
-	};
-
-	if (!remaining_time) {
-		al_err("udma [%s %d]: %s timeout waiting for dcp==crhp\n",
-			udma_q->udma->name, udma_q->qid, __func__);
-		return -ETIMEDOUT;
-	}
-
-	/* Assert the queue reset */
-	if (udma_q->udma->type == UDMA_TX)
-		q_sw_ctrl_reg = &udma_q->q_regs->m2s_q.q_sw_ctrl;
-	else
-		q_sw_ctrl_reg = &udma_q->q_regs->s2m_q.q_sw_ctrl;
-
-	al_reg_write32(q_sw_ctrl_reg, UDMA_M2S_Q_SW_CTRL_RST_Q);
-
-	return 0;
-}
-
-/*
- * return (by reference) a pointer to a specific queue date structure.
- */
-int al_udma_q_handle_get(struct al_udma *udma, uint32_t qid,
-						struct al_udma_q **q_handle)
-{
-
-	al_assert(udma);
-	al_assert(q_handle);
-
-	if (unlikely(qid >= udma->num_of_queues)) {
-		al_err("udma [%s]: invalid queue id (%d)\n", udma->name, qid);
-		return -EINVAL;
-	}
-	*q_handle = &udma->udma_q[qid];
-	return 0;
-}
-
-/*
- * Change the UDMA's state
- */
-int al_udma_state_set(struct al_udma *udma, enum al_udma_state state)
-{
-	uint32_t reg;
-
-	al_assert(udma != NULL);
-	if (state == udma->state)
-		al_dbg("udma [%s]: requested state identical to "
-			"current state (%d)\n", udma->name, state);
-
-	al_dbg("udma [%s]: change state from (%s) to (%s)\n",
-		 udma->name, al_udma_states_name[udma->state],
-		 al_udma_states_name[state]);
-
-	reg = 0;
-	switch (state) {
-	case UDMA_DISABLE:
-		reg |= UDMA_M2S_CHANGE_STATE_DIS;
-		break;
-	case UDMA_NORMAL:
-		reg |= UDMA_M2S_CHANGE_STATE_NORMAL;
-		break;
-	case UDMA_ABORT:
-		reg |= UDMA_M2S_CHANGE_STATE_ABORT;
-		break;
-	default:
-		al_err("udma: invalid state (%d)\n", state);
-		return -EINVAL;
-	}
-
-	if (udma->type == UDMA_TX)
-		al_reg_write32(&udma->udma_regs->m2s.m2s.change_state, reg);
-	else
-		al_reg_write32(&udma->udma_regs->s2m.s2m.change_state, reg);
-
-	udma->state = state;
-	return 0;
-}
-
-/*
- * return the current UDMA hardware state
- */
-enum al_udma_state al_udma_state_get(struct al_udma *udma)
-{
-	uint32_t state_reg;
-	uint32_t comp_ctrl;
-	uint32_t stream_if;
-	uint32_t data_rd;
-	uint32_t desc_pref;
-
-	if (udma->type == UDMA_TX)
-		state_reg = al_reg_read32(&udma->udma_regs->m2s.m2s.state);
-	else
-		state_reg = al_reg_read32(&udma->udma_regs->s2m.s2m.state);
-
-	comp_ctrl = AL_REG_FIELD_GET(state_reg,
-				     UDMA_M2S_STATE_COMP_CTRL_MASK,
-				     UDMA_M2S_STATE_COMP_CTRL_SHIFT);
-	stream_if = AL_REG_FIELD_GET(state_reg,
-				     UDMA_M2S_STATE_STREAM_IF_MASK,
-				     UDMA_M2S_STATE_STREAM_IF_SHIFT);
-	data_rd = AL_REG_FIELD_GET(state_reg,
-				   UDMA_M2S_STATE_DATA_RD_CTRL_MASK,
-				   UDMA_M2S_STATE_DATA_RD_CTRL_SHIFT);
-	desc_pref = AL_REG_FIELD_GET(state_reg,
-				     UDMA_M2S_STATE_DESC_PREF_MASK,
-				     UDMA_M2S_STATE_DESC_PREF_SHIFT);
-
-	al_assert(comp_ctrl != UDMA_STATE_RESERVED);
-	al_assert(stream_if != UDMA_STATE_RESERVED);
-	al_assert(data_rd != UDMA_STATE_RESERVED);
-	al_assert(desc_pref != UDMA_STATE_RESERVED);
-
-	/* if any of the states is abort then return abort */
-	if ((comp_ctrl == UDMA_STATE_ABORT) || (stream_if == UDMA_STATE_ABORT)
-			|| (data_rd == UDMA_STATE_ABORT)
-			|| (desc_pref == UDMA_STATE_ABORT))
-		return UDMA_ABORT;
-
-	/* if any of the states is normal then return normal */
-	if ((comp_ctrl == UDMA_STATE_NORMAL)
-			|| (stream_if == UDMA_STATE_NORMAL)
-			|| (data_rd == UDMA_STATE_NORMAL)
-			|| (desc_pref == UDMA_STATE_NORMAL))
-		return UDMA_NORMAL;
-
-	return UDMA_IDLE;
-}
-
-/*
- * Action handling
- */
-
-/*
- * get next completed packet from completion ring of the queue
- */
-uint32_t al_udma_cdesc_packet_get(
-	struct al_udma_q		*udma_q,
-	volatile union al_udma_cdesc	**cdesc)
-{
-	uint32_t count;
-	volatile union al_udma_cdesc *curr;
-	uint32_t comp_flags;
-
-	/* this function requires the completion ring update */
-	al_assert(!(udma_q->flags & AL_UDMA_Q_FLAGS_NO_COMP_UPDATE));
-
-	/* comp_head points to the last comp desc that was processed */
-	curr = udma_q->comp_head_ptr;
-	comp_flags = swap32_from_le(curr->al_desc_comp_tx.ctrl_meta);
-
-	/* check if the completion descriptor is new */
-	if (unlikely(al_udma_new_cdesc(udma_q, comp_flags) == AL_FALSE))
-		return 0;
-	/* if new desc found, increment the current packets descriptors */
-	count = udma_q->pkt_crnt_descs + 1;
-	while (!cdesc_is_last(comp_flags)) {
-		curr = al_cdesc_next_update(udma_q, curr);
-		comp_flags = swap32_from_le(curr->al_desc_comp_tx.ctrl_meta);
-		if (unlikely(al_udma_new_cdesc(udma_q, comp_flags)
-								== AL_FALSE)) {
-			/* the current packet here doesn't have all  */
-			/* descriptors completed. log the current desc */
-			/* location and number of completed descriptors so */
-			/*  far. then return */
-			udma_q->pkt_crnt_descs = count;
-			udma_q->comp_head_ptr = curr;
-			return 0;
-		}
-		count++;
-		/* check against max descs per packet. */
-		al_assert(count <= udma_q->size);
-	}
-	/* return back the first descriptor of the packet */
-	*cdesc = al_udma_cdesc_idx_to_ptr(udma_q, udma_q->next_cdesc_idx);
-	udma_q->pkt_crnt_descs = 0;
-	udma_q->comp_head_ptr = al_cdesc_next_update(udma_q, curr);
-
-	al_dbg("udma [%s %d]: packet completed. first desc %p (ixd 0x%x)"
-		 " descs %d\n", udma_q->udma->name, udma_q->qid, *cdesc,
-		 udma_q->next_cdesc_idx, count);
-
-	return count;
-}
-
-/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_regs.h b/sys/contrib/alpine-hal/eth/al_hal_udma_regs.h
deleted file mode 100644
index ed37215ae445..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_regs.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_udma_regs.h
- *
- * @brief  udma registers definition
- *
- *
- */
-#ifndef __AL_HAL_UDMA_REG_H
-#define __AL_HAL_UDMA_REG_H
-
-#include "al_hal_udma_regs_m2s.h"
-#include "al_hal_udma_regs_s2m.h"
-#include "al_hal_udma_regs_gen.h"
-
-#define AL_UDMA_REV_ID_REV0   0
-#define AL_UDMA_REV_ID_REV1   1
-#define AL_UDMA_REV_ID_REV2   2
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** UDMA registers, either m2s or s2m */
-union udma_regs {
-	struct udma_m2s_regs m2s;
-	struct udma_s2m_regs s2m;
-};
-
-struct unit_regs {
-	struct udma_m2s_regs m2s;
-	uint32_t rsrvd0[(0x10000 - sizeof(struct udma_m2s_regs)) >> 2];
-	struct udma_s2m_regs s2m;
-	uint32_t rsrvd1[((0x1C000 - 0x10000) - sizeof(struct udma_s2m_regs)) >> 2];
-	struct udma_gen_regs gen;
-};
-
-/** UDMA submission and completion registers, M2S and S2M UDMAs have same stucture */
-struct udma_rings_regs {
-	uint32_t rsrvd0[8];
-	uint32_t cfg;		/* Descriptor ring configuration */
-	uint32_t status;	/* Descriptor ring status and information */
-	uint32_t drbp_low;	/* Descriptor Ring Base Pointer [31:4] */
-	uint32_t drbp_high;	/* Descriptor Ring Base Pointer [63:32] */
-	uint32_t drl;		/* Descriptor Ring Length[23:2] */
-	uint32_t drhp;		/* Descriptor Ring Head Pointer */
-	uint32_t drtp_inc;	/* Descriptor Tail Pointer increment */
-	uint32_t drtp;		/* Descriptor Tail Pointer */
-	uint32_t dcp;		/* Descriptor Current Pointer */
-	uint32_t crbp_low;	/* Completion Ring Base Pointer [31:4] */
-	uint32_t crbp_high;	/* Completion Ring Base Pointer [63:32] */
-	uint32_t crhp;		/* Completion Ring Head Pointer */
-	uint32_t crhp_internal;	/* Completion Ring Head Pointer internal, before AX ... */
-};
-
-/** M2S and S2M generic structure of Q registers */
-union udma_q_regs {
-	struct udma_rings_regs	rings;
-	struct udma_m2s_q	m2s_q;
-	struct udma_s2m_q	s2m_q;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_UDMA_REG_H */
-/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_regs_gen.h b/sys/contrib/alpine-hal/eth/al_hal_udma_regs_gen.h
deleted file mode 100644
index 89f94b85a56b..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_regs_gen.h
+++ /dev/null
@@ -1,414 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @file   al_hal_udma_regs_gen.h
- *
- * @brief C Header file for the UDMA general registers
- *
- */
-
-#ifndef __AL_HAL_UDMA_GEN_REG_H
-#define __AL_HAL_UDMA_GEN_REG_H
-
-#include "al_hal_udma_iofic_regs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-
-
-struct udma_gen_dma_misc {
-	/* [0x0] Reserved register for the interrupt controller */
-	uint32_t int_cfg;
-	/* [0x4] Revision register */
-	uint32_t revision;
-	/* [0x8] Reserved for future use */
-	uint32_t general_cfg_1;
-	/* [0xc] Reserved for future use */
-	uint32_t general_cfg_2;
-	/* [0x10] Reserved for future use */
-	uint32_t general_cfg_3;
-	/* [0x14] Reserved for future use */
-	uint32_t general_cfg_4;
-	/* [0x18] General timer configuration */
-	uint32_t general_cfg_5;
-	uint32_t rsrvd[57];
-};
-struct udma_gen_mailbox {
-	/*
-	 * [0x0] Mailbox interrupt generator.
-	 * Generates interrupt to neighbor DMA
-	 */
-	uint32_t interrupt;
-	/* [0x4] Mailbox message data out */
-	uint32_t msg_out;
-	/* [0x8] Mailbox message data in */
-	uint32_t msg_in;
-	uint32_t rsrvd[13];
-};
-struct udma_gen_axi {
-	/* [0x0] Configuration of the AXI masters */
-	uint32_t cfg_1;
-	/* [0x4] Configuration of the AXI masters */
-	uint32_t cfg_2;
-	/* [0x8] Configuration of the AXI masters. Endianess configuration */
-	uint32_t endian_cfg;
-	uint32_t rsrvd[61];
-};
-struct udma_gen_sram_ctrl {
-	/* [0x0] Timing configuration */
-	uint32_t timing;
-};
-struct udma_gen_vmid {
-	/* [0x0] VMID control */
-	uint32_t cfg_vmid_0;
-	/* [0x4] TX queue 0/1 VMID */
-	uint32_t cfg_vmid_1;
-	/* [0x8] TX queue 2/3 VMID */
-	uint32_t cfg_vmid_2;
-	/* [0xc] RX queue 0/1 VMID */
-	uint32_t cfg_vmid_3;
-	/* [0x10] RX queue 2/3 VMID */
-	uint32_t cfg_vmid_4;
-};
-struct udma_gen_vmaddr {
-	/* [0x0] TX queue 0/1 VMADDR */
-	uint32_t cfg_vmaddr_0;
-	/* [0x4] TX queue 2/3 VMADDR */
-	uint32_t cfg_vmaddr_1;
-	/* [0x8] RX queue 0/1 VMADDR */
-	uint32_t cfg_vmaddr_2;
-	/* [0xc] RX queue 2/3 VMADDR */
-	uint32_t cfg_vmaddr_3;
-};
-struct udma_gen_vmpr {
-	/* [0x0] TX VMPR control */
-	uint32_t cfg_vmpr_0;
-	/* [0x4] TX VMPR Address High Regsiter */
-	uint32_t cfg_vmpr_1;
-	/* [0x8] TX queue VMID values */
-	uint32_t cfg_vmpr_2;
-	/* [0xc] TX queue VMID values */
-	uint32_t cfg_vmpr_3;
-	/* [0x10] RX VMPR control */
-	uint32_t cfg_vmpr_4;
-	/* [0x14] RX VMPR Buffer2 MSB address */
-	uint32_t cfg_vmpr_5;
-	/* [0x18] RX queue VMID values */
-	uint32_t cfg_vmpr_6;
-	/* [0x1c] RX queue BUF1 VMID values */
-	uint32_t cfg_vmpr_7;
-	/* [0x20] RX queue BUF2 VMID values */
-	uint32_t cfg_vmpr_8;
-	/* [0x24] RX queue Direct Data Placement VMID values */
-	uint32_t cfg_vmpr_9;
-	/* [0x28] RX VMPR BUF1 Address High Regsiter */
-	uint32_t cfg_vmpr_10;
-	/* [0x2c] RX VMPR BUF2 Address High Regsiter */
-	uint32_t cfg_vmpr_11;
-	/* [0x30] RX VMPR DDP Address High Regsiter */
-	uint32_t cfg_vmpr_12;
-	uint32_t rsrvd[3];
-};
-
-struct udma_gen_regs {
-	struct udma_iofic_regs interrupt_regs;					/* [0x0000] */
-	struct udma_gen_dma_misc dma_misc;                   /* [0x2080] */
-	struct udma_gen_mailbox mailbox[4];                  /* [0x2180] */
-	struct udma_gen_axi axi;                             /* [0x2280] */
-	struct udma_gen_sram_ctrl sram_ctrl[25];             /* [0x2380] */
-	uint32_t rsrvd_1[2];
-	struct udma_gen_vmid vmid;                           /* [0x23ec] */
-	struct udma_gen_vmaddr vmaddr;                       /* [0x2400] */
-	uint32_t rsrvd_2[252];
-	struct udma_gen_vmpr vmpr[4];                        /* [0x2800] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** int_cfg register ****/
-/*
- * MSIX data width
- * 1 - 64 bit
- * 0 – 32 bit
- */
-#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_64 (1 << 0)
-/* General configuration */
-#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_MASK 0x0000000E
-#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_SHIFT 1
-/* MSIx AXI QoS */
-#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_MASK 0x00000070
-#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_SHIFT 4
-
-#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_MASK 0xFFFFFF80
-#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_SHIFT 7
-
-/**** revision register ****/
-/* Design programming interface  revision ID */
-#define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK 0x00000FFF
-#define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT 0
-/* Design minor revision ID */
-#define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_MASK 0x00FFF000
-#define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_SHIFT 12
-/* Design major revision ID */
-#define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_MASK 0xFF000000
-#define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_SHIFT 24
-
-/**** Interrupt register ****/
-/* Generate interrupt to another DMA */
-#define UDMA_GEN_MAILBOX_INTERRUPT_SET   (1 << 0)
-
-/**** cfg_2 register ****/
-/*
- * Enable arbitration promotion.
- * Increment master priority after configured number of arbitration cycles
- */
-#define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK 0x0000000F
-#define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_SHIFT 0
-
-/**** endian_cfg register ****/
-/* Swap M2S descriptor read and completion descriptor write.  */
-#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC (1 << 0)
-/* Swap M2S data read. */
-#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA (1 << 1)
-/* Swap S2M descriptor read and completion descriptor write.  */
-#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC (1 << 2)
-/* Swap S2M data write. */
-#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA (1 << 3)
-/*
- * Swap 32 or 64 bit mode:
- * 0 - Swap groups of 4 bytes
- * 1 - Swap groups of 8 bytes
- */
-#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN (1 << 4)
-
-/**** timing register ****/
-/* Write margin */
-#define UDMA_GEN_SRAM_CTRL_TIMING_RMA_MASK 0x0000000F
-#define UDMA_GEN_SRAM_CTRL_TIMING_RMA_SHIFT 0
-/* Write margin enable */
-#define UDMA_GEN_SRAM_CTRL_TIMING_RMEA   (1 << 8)
-/* Read margin */
-#define UDMA_GEN_SRAM_CTRL_TIMING_RMB_MASK 0x000F0000
-#define UDMA_GEN_SRAM_CTRL_TIMING_RMB_SHIFT 16
-/* Read margin enable */
-#define UDMA_GEN_SRAM_CTRL_TIMING_RMEB   (1 << 24)
-
-/**** cfg_vmid_0 register ****/
-/* For M2S queues 3:0, enable usage of the VMID from the buffer address 63:56 */
-#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_MASK 0x0000000F
-#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_SHIFT 0
-/*
- * For M2S queues 3:0, enable usage of the VMID from the configuration register
- * (cfg_vmid_1/2 used for M2S queue_x)
- */
-#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_MASK 0x000000F0
-#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_SHIFT 4
-/* use VMID_n [7:0] from MSI-X Controller for MSI-X message  */
-#define UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_SEL (1 << 8)
-/* Enable write to all VMID_n registers in the MSI-X Controller */
-#define UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_ACCESS_EN (1 << 9)
-/* For S2M queues 3:0, enable usage of the VMID from the buffer address 63:56 */
-#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_MASK 0x000F0000
-#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_SHIFT 16
-/*
- * For S2M queues 3:0, enable usage of the VMID from the configuration register
- * (cfg_vmid_3/4 used for M2S queue_x)
- */
-#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_MASK 0x00F00000
-#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_SHIFT 20
-
-/**** cfg_vmid_1 register ****/
-/* TX queue 0 VMID value */
-#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_0_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_0_VMID_SHIFT 0
-/* TX queue 1 VMID value */
-#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_1_VMID_MASK 0xFFFF0000
-#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_1_VMID_SHIFT 16
-
-/**** cfg_vmid_2 register ****/
-/* TX queue 2 VMID value */
-#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_2_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_2_VMID_SHIFT 0
-/* TX queue 3 VMID value */
-#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_3_VMID_MASK 0xFFFF0000
-#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_3_VMID_SHIFT 16
-
-/**** cfg_vmid_3 register ****/
-/* RX queue 0 VMID value */
-#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_0_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_0_VMID_SHIFT 0
-/* RX queue 1 VMID value */
-#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_1_VMID_MASK 0xFFFF0000
-#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_1_VMID_SHIFT 16
-
-/**** cfg_vmid_4 register ****/
-/* RX queue 2 VMID value */
-#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_2_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_2_VMID_SHIFT 0
-/* RX queue 3 VMID value */
-#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_3_VMID_MASK 0xFFFF0000
-#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_3_VMID_SHIFT 16
-
-/**** cfg_vmaddr_0 register ****/
-/* TX queue 0 VMADDR value */
-#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_0_VMADDR_MASK 0x0000FFFF
-#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_0_VMADDR_SHIFT 0
-/* TX queue 1 VMADDR value */
-#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_1_VMADDR_MASK 0xFFFF0000
-#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_1_VMADDR_SHIFT 16
-
-/**** cfg_vmaddr_1 register ****/
-/* TX queue 2 VMADDR value */
-#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_2_VMADDR_MASK 0x0000FFFF
-#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_2_VMADDR_SHIFT 0
-/* TX queue 3 VMADDR value */
-#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_3_VMADDR_MASK 0xFFFF0000
-#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_3_VMADDR_SHIFT 16
-
-/**** cfg_vmaddr_2 register ****/
-/* RX queue 0 VMADDR value */
-#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_0_VMADDR_MASK 0x0000FFFF
-#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_0_VMADDR_SHIFT 0
-/* RX queue 1 VMADDR value */
-#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_1_VMADDR_MASK 0xFFFF0000
-#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_1_VMADDR_SHIFT 16
-
-/**** cfg_vmaddr_3 register ****/
-/* RX queue 2 VMADDR value */
-#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_2_VMADDR_MASK 0x0000FFFF
-#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_2_VMADDR_SHIFT 0
-/* RX queue 3 VMADDR value */
-#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_3_VMADDR_MASK 0xFFFF0000
-#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_3_VMADDR_SHIFT 16
-
-/**** cfg_vmpr_0 register ****/
-/* TX High Address Select Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_MASK 0x0000003F
-#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_SHIFT 0
-/* TX Data VMID Enable Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_DATA_VMID_EN (1 << 7)
-/* TX Prefetch VMID Enable Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_PREF_VMID_EN (1 << 28)
-/* TX Completions VMID Enable Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_CMPL_VMID_EN (1 << 29)
-
-/**** cfg_vmpr_2 register ****/
-/* TX queue Prefetch VMID */
-#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_SHIFT 0
-/* TX queue Completion VMID */
-#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_MASK 0xFFFF0000
-#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_SHIFT 16
-
-/**** cfg_vmpr_3 register ****/
-/* TX queue Data VMID */
-#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SHIFT 0
-/* TX queue Data VMID select */
-#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_MASK 0xFFFF0000
-#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_SHIFT 16
-
-/**** cfg_vmpr_4 register ****/
-/* RX Data Buffer1 - High Address Select Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_MASK 0x0000003F
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_SHIFT 0
-/* RX Data Buffer1 VMID Enable Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_VMID_EN (1 << 7)
-/* RX Data Buffer2 - High Address Select Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_MASK 0x00003F00
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_SHIFT 8
-/* RX Data Buffer2 VMID Enable Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_VMID_EN (1 << 15)
-/* RX Direct Data Placement - High Address Select Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_MASK 0x003F0000
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_SHIFT 16
-/* RX Direct Data Placement VMID Enable Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_VMID_EN (1 << 23)
-/* RX Buffer 2 MSB address word selects per bytes, per queue */
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_MASK 0x0F000000
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_SHIFT 24
-/* RX Prefetch VMID Enable Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_PREF_VMID_EN (1 << 28)
-/* RX Completions VMID Enable Per Q */
-#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_CMPL_VMID_EN (1 << 29)
-
-/**** cfg_vmpr_6 register ****/
-/* RX queue Prefetch VMID */
-#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_SHIFT 0
-/* RX queue Completion VMID */
-#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_MASK 0xFFFF0000
-#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_SHIFT 16
-
-/**** cfg_vmpr_7 register ****/
-/* RX queue Data Buffer 1 VMID */
-#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SHIFT 0
-/* RX queue Data Buffer 1 VMID select */
-#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_MASK 0xFFFF0000
-#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_SHIFT 16
-
-/**** cfg_vmpr_8 register ****/
-/* RX queue Data Buffer 2 VMID */
-#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SHIFT 0
-/* RX queue Data Buffer 2 VMID select */
-#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_MASK 0xFFFF0000
-#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_SHIFT 16
-
-/**** cfg_vmpr_9 register ****/
-/* RX queue DDP VMID */
-#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_MASK 0x0000FFFF
-#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SHIFT 0
-/* RX queue DDP VMID select */
-#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_MASK 0xFFFF0000
-#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_SHIFT 16
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_UDMA_GEN_REG_H */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_regs_m2s.h b/sys/contrib/alpine-hal/eth/al_hal_udma_regs_m2s.h
deleted file mode 100644
index 06cea8db8f6d..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_regs_m2s.h
+++ /dev/null
@@ -1,1159 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @file   al_hal_udma_regs_m2s.h
- *
- * @brief C Header file for the UDMA M2S registers
- *
- */
-
-#ifndef __AL_HAL_UDMA_M2S_REG_H
-#define __AL_HAL_UDMA_M2S_REG_H
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-
-
-struct udma_axi_m2s {
-	/* [0x0] Completion write master configuration */
-	uint32_t comp_wr_cfg_1;
-	/* [0x4] Completion write master configuration */
-	uint32_t comp_wr_cfg_2;
-	/* [0x8] Data read master configuration */
-	uint32_t data_rd_cfg_1;
-	/* [0xc] Data read master configuration */
-	uint32_t data_rd_cfg_2;
-	/* [0x10] Descriptor read master configuration */
-	uint32_t desc_rd_cfg_1;
-	/* [0x14] Descriptor read master configuration */
-	uint32_t desc_rd_cfg_2;
-	/* [0x18] Data read master configuration */
-	uint32_t data_rd_cfg;
-	/* [0x1c] Descriptors read master configuration */
-	uint32_t desc_rd_cfg_3;
-	/* [0x20] Descriptors write master configuration (completion) */
-	uint32_t desc_wr_cfg_1;
-	/* [0x24] AXI outstanding  configuration */
-	uint32_t ostand_cfg;
-	uint32_t rsrvd[54];
-};
-struct udma_m2s {
-	/*
-	 * [0x0] DMA state.
-	 * 00  - No pending tasks
-	 * 01 – Normal (active)
-	 * 10 – Abort (error condition)
-	 * 11 – Reserved
-	 */
-	uint32_t state;
-	/* [0x4] CPU request to change DMA state */
-	uint32_t change_state;
-	uint32_t rsrvd_0;
-	/*
-	 * [0xc] M2S DMA error log mask.
-	 * Each error has an interrupt controller cause bit.
-	 * This register determines if these errors cause the M2S DMA to log the
-	 * error condition.
-	 * 0 - Log is enabled.
-	 * 1 - Log is masked.
-	 */
-	uint32_t err_log_mask;
-	uint32_t rsrvd_1;
-	/*
-	 * [0x14] DMA header log.
-	 * Sample the packet header that caused the error.
-	 */
-	uint32_t log_0;
-	/*
-	 * [0x18] DMA header log.
-	 * Sample the packet header that caused the error.
-	 */
-	uint32_t log_1;
-	/*
-	 * [0x1c] DMA header log.
-	 * Sample the packet header that caused the error.
-	 */
-	uint32_t log_2;
-	/*
-	 * [0x20] DMA header log.
-	 * Sample the packet header that caused the error.
-	 */
-	uint32_t log_3;
-	/* [0x24] DMA clear error log */
-	uint32_t clear_err_log;
-	/* [0x28] M2S data FIFO status */
-	uint32_t data_fifo_status;
-	/* [0x2c] M2S header FIFO status */
-	uint32_t header_fifo_status;
-	/* [0x30] M2S unack FIFO status */
-	uint32_t unack_fifo_status;
-	/* [0x34] Select queue for debug */
-	uint32_t indirect_ctrl;
-	/*
-	 * [0x38] M2S prefetch FIFO status.
-	 * Status of the selected queue in M2S_indirect_ctrl
-	 */
-	uint32_t sel_pref_fifo_status;
-	/*
-	 * [0x3c] M2S completion FIFO status.
-	 * Status of the selected queue in M2S_indirect_ctrl
-	 */
-	uint32_t sel_comp_fifo_status;
-	/*
-	 * [0x40] M2S rate limit status.
-	 * Status of the selected queue in M2S_indirect_ctrl
-	 */
-	uint32_t sel_rate_limit_status;
-	/*
-	 * [0x44] M2S DWRR scheduler status.
-	 * Status of the selected queue in M2S_indirect_ctrl
-	 */
-	uint32_t sel_dwrr_status;
-	/* [0x48] M2S state machine and FIFO clear control */
-	uint32_t clear_ctrl;
-	/* [0x4c] Misc Check enable */
-	uint32_t check_en;
-	/* [0x50] M2S FIFO enable control, internal */
-	uint32_t fifo_en;
-	/* [0x54] M2S packet length configuration */
-	uint32_t cfg_len;
-	/* [0x58] Stream interface configuration */
-	uint32_t stream_cfg;
-	uint32_t rsrvd[41];
-};
-struct udma_m2s_rd {
-	/* [0x0] M2S descriptor prefetch configuration */
-	uint32_t desc_pref_cfg_1;
-	/* [0x4] M2S descriptor prefetch configuration */
-	uint32_t desc_pref_cfg_2;
-	/* [0x8] M2S descriptor prefetch configuration */
-	uint32_t desc_pref_cfg_3;
-	uint32_t rsrvd_0;
-	/* [0x10] Data burst read configuration */
-	uint32_t data_cfg;
-	uint32_t rsrvd[11];
-};
-struct udma_m2s_dwrr {
-	/* [0x0] Tx DMA DWRR scheduler configuration */
-	uint32_t cfg_sched;
-	/* [0x4] Token bucket rate limit control */
-	uint32_t ctrl_deficit_cnt;
-	uint32_t rsrvd[14];
-};
-struct udma_m2s_rate_limiter {
-	/* [0x0] Token bucket rate limit configuration */
-	uint32_t gen_cfg;
-	/*
-	 * [0x4] Token bucket rate limit control.
-	 * Controls the cycle counters.
-	 */
-	uint32_t ctrl_cycle_cnt;
-	/*
-	 * [0x8] Token bucket rate limit control.
-	 * Controls the token bucket counter.
-	 */
-	uint32_t ctrl_token;
-	uint32_t rsrvd[13];
-};
-
-struct udma_rlimit_common {
-	/* [0x0] Token bucket configuration */
-	uint32_t cfg_1s;
-	/* [0x4] Token bucket rate limit configuration */
-	uint32_t cfg_cycle;
-	/* [0x8] Token bucket rate limit configuration */
-	uint32_t cfg_token_size_1;
-	/* [0xc] Token bucket rate limit configuration */
-	uint32_t cfg_token_size_2;
-	/* [0x10] Token bucket rate limit configuration */
-	uint32_t sw_ctrl;
-	/*
-	 * [0x14] Mask the different types of rate limiter.
-	 * 0 - Rate limit is active.
-	 * 1 - Rate limit is masked.
-	 */
-	uint32_t mask;
-};
-
-struct udma_m2s_stream_rate_limiter {
-	struct udma_rlimit_common rlimit;
-	uint32_t rsrvd[10];
-};
-struct udma_m2s_comp {
-	/* [0x0] Completion controller configuration */
-	uint32_t cfg_1c;
-	/* [0x4] Completion controller coalescing configuration */
-	uint32_t cfg_coal;
-	/* [0x8] Completion controller application acknowledge configuration */
-	uint32_t cfg_application_ack;
-	uint32_t rsrvd[61];
-};
-struct udma_m2s_stat {
-	/* [0x0] Statistics counters configuration */
-	uint32_t cfg_st;
-	/* [0x4] Counting number of descriptors with First-bit set. */
-	uint32_t tx_pkt;
-	/*
-	 * [0x8] Counting the net length of the data buffers [64-bit]
-	 * Should be read before tx_bytes_high
-	 */
-	uint32_t tx_bytes_low;
-	/*
-	 * [0xc] Counting the net length of the data buffers [64-bit],
-	 * Should be read after tx_bytes_low (value is sampled when reading
-	 * Should be read before tx_bytes_low
-	 */
-	uint32_t tx_bytes_high;
-	/* [0x10] Total number of descriptors read from the host memory */
-	uint32_t prefed_desc;
-	/* [0x14] Number of packets read from the unack FIFO */
-	uint32_t comp_pkt;
-	/* [0x18] Number of descriptors written into the completion ring */
-	uint32_t comp_desc;
-	/*
-	 * [0x1c] Number of acknowledged packets.
-	 * (acknowledge received from the stream interface)
-	 */
-	uint32_t ack_pkts;
-	uint32_t rsrvd[56];
-};
-struct udma_m2s_feature {
-	/*
-	 * [0x0] M2S Feature register.
-	 * M2S instantiation parameters
-	 */
-	uint32_t reg_1;
-	/* [0x4] Reserved M2S feature register */
-	uint32_t reg_2;
-	/*
-	 * [0x8] M2S Feature register.
-	 * M2S instantiation parameters
-	 */
-	uint32_t reg_3;
-	/*
-	 * [0xc] M2S Feature register.
-	 * M2S instantiation parameters
-	 */
-	uint32_t reg_4;
-	/*
-	 * [0x10] M2S Feature register.
-	 * M2S instantiation parameters
-	 */
-	uint32_t reg_5;
-	uint32_t rsrvd[59];
-};
-struct udma_m2s_q {
-	uint32_t rsrvd_0[8];
-	/* [0x20] M2S descriptor ring configuration */
-	uint32_t cfg;
-	/* [0x24] M2S descriptor ring status and information */
-	uint32_t status;
-	/* [0x28] TX Descriptor Ring Base Pointer [31:4] */
-	uint32_t tdrbp_low;
-	/* [0x2c] TX Descriptor Ring Base Pointer [63:32] */
-	uint32_t tdrbp_high;
-	/*
-	 * [0x30] TX Descriptor Ring Length[23:2]
-	 */
-	uint32_t tdrl;
-	/* [0x34] TX Descriptor Ring Head Pointer */
-	uint32_t tdrhp;
-	/* [0x38] Tx Descriptor Tail Pointer increment */
-	uint32_t tdrtp_inc;
-	/* [0x3c] Tx Descriptor Tail Pointer */
-	uint32_t tdrtp;
-	/* [0x40] TX Descriptor Current Pointer */
-	uint32_t tdcp;
-	/* [0x44] Tx Completion Ring Base Pointer [31:4] */
-	uint32_t tcrbp_low;
-	/* [0x48] TX Completion Ring Base Pointer [63:32] */
-	uint32_t tcrbp_high;
-	/* [0x4c] TX Completion Ring Head Pointer */
-	uint32_t tcrhp;
-	/*
-	 * [0x50] Tx Completion Ring Head Pointer internal (Before the
-	 * coalescing FIFO)
-	 */
-	uint32_t tcrhp_internal;
-	uint32_t rsrvd_1[3];
-	/* [0x60] Rate limit configuration */
-	struct udma_rlimit_common rlimit;
-	uint32_t rsrvd_2[2];
-	/* [0x80] DWRR scheduler configuration */
-	uint32_t dwrr_cfg_1;
-	/* [0x84] DWRR scheduler configuration */
-	uint32_t dwrr_cfg_2;
-	/* [0x88] DWRR scheduler configuration */
-	uint32_t dwrr_cfg_3;
-	/* [0x8c] DWRR scheduler software control */
-	uint32_t dwrr_sw_ctrl;
-	uint32_t rsrvd_3[4];
-	/* [0xa0] Completion controller configuration */
-	uint32_t comp_cfg;
-	uint32_t rsrvd_4[3];
-	/* [0xb0] SW control  */
-	uint32_t q_sw_ctrl;
-	uint32_t rsrvd_5[3];
-	/* [0xc0] Number of M2S Tx packets after the scheduler */
-	uint32_t q_tx_pkt;
-	uint32_t rsrvd[975];
-};
-
-struct udma_m2s_regs {
-	uint32_t rsrvd_0[64];
-	struct udma_axi_m2s axi_m2s;                     /* [0x100] */
-	struct udma_m2s m2s;                             /* [0x200] */
-	struct udma_m2s_rd m2s_rd;                       /* [0x300] */
-	struct udma_m2s_dwrr m2s_dwrr;                   /* [0x340] */
-	struct udma_m2s_rate_limiter m2s_rate_limiter;   /* [0x380] */
-	struct udma_m2s_stream_rate_limiter m2s_stream_rate_limiter; /* [0x3c0] */
-	struct udma_m2s_comp m2s_comp;                   /* [0x400] */
-	struct udma_m2s_stat m2s_stat;                   /* [0x500] */
-	struct udma_m2s_feature m2s_feature;             /* [0x600] */
-	uint32_t rsrvd_1[576];
-	struct udma_m2s_q m2s_q[4];                      /* [0x1000] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** comp_wr_cfg_1 register ****/
-/* AXI write  ID (AWID) */
-#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK 0x000000FF
-#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_SHIFT 0
-/* Cache Type */
-#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK 0x000F0000
-#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_SHIFT 16
-/* Burst type */
-#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK 0x03000000
-#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_SHIFT 24
-
-/**** comp_wr_cfg_2 register ****/
-/* User extension */
-#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK 0x000FFFFF
-#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_SHIFT 0
-/* Bus size, 128-bit */
-#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK 0x00700000
-#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_SHIFT 20
-/*
- * AXI Master QoS.
- * Used for arbitration between AXI masters
- */
-#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK 0x07000000
-#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_SHIFT 24
-/* Protection Type */
-#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK 0x70000000
-#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_SHIFT 28
-
-/**** data_rd_cfg_1 register ****/
-/* AXI read  ID (ARID) */
-#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARID_MASK 0x000000FF
-#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARID_SHIFT 0
-/* Cache Type */
-#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARCACHE_MASK 0x000F0000
-#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARCACHE_SHIFT 16
-/* Burst type */
-#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARBURST_MASK 0x03000000
-#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARBURST_SHIFT 24
-
-/**** data_rd_cfg_2 register ****/
-/* User extension */
-#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARUSER_MASK 0x000FFFFF
-#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARUSER_SHIFT 0
-/* Bus size, 128-bit */
-#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARSIZE_MASK 0x00700000
-#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARSIZE_SHIFT 20
-/*
- * AXI Master QoS.
- * Used for arbitration between AXI masters
- */
-#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARQOS_MASK 0x07000000
-#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARQOS_SHIFT 24
-/* Protection Type */
-#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARPROT_MASK 0x70000000
-#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARPROT_SHIFT 28
-
-/**** desc_rd_cfg_1 register ****/
-/* AXI read  ID (ARID) */
-#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARID_MASK 0x000000FF
-#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARID_SHIFT 0
-/* Cache Type */
-#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARCACHE_MASK 0x000F0000
-#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARCACHE_SHIFT 16
-/* Burst type */
-#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARBURST_MASK 0x03000000
-#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARBURST_SHIFT 24
-
-/**** desc_rd_cfg_2 register ****/
-/* User extension */
-#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARUSER_MASK 0x000FFFFF
-#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARUSER_SHIFT 0
-/* Bus size, 128-bit */
-#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARSIZE_MASK 0x00700000
-#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARSIZE_SHIFT 20
-/*
- * AXI Master QoS
- * Used for arbitration between AXI masters
- */
-#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARQOS_MASK 0x07000000
-#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARQOS_SHIFT 24
-/* Protection Type */
-#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARPROT_MASK 0x70000000
-#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARPROT_SHIFT 28
-
-/**** data_rd_cfg register ****/
-/*
- * Defines the maximum number of AXI beats for a single AXI burst.
- * This value is used for a burst split decision.
- */
-#define UDMA_AXI_M2S_DATA_RD_CFG_MAX_AXI_BEATS_MASK 0x000000FF
-#define UDMA_AXI_M2S_DATA_RD_CFG_MAX_AXI_BEATS_SHIFT 0
-/*
- * Enable breaking data read request.
- * Aligned to max_AXI_beats when the total read size is less than max_AXI_beats
- */
-#define UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY (1 << 16)
-
-/**** desc_rd_cfg_3 register ****/
-/*
- * Defines the maximum number of AXI beats for a single AXI burst.
- * This value is used for a burst split decision.
- * Maximum burst size for reading data( in AXI beats, 128-bits)
- * (default – 16 beats, 256 bytes)
- */
-#define UDMA_AXI_M2S_DESC_RD_CFG_3_MAX_AXI_BEATS_MASK 0x000000FF
-#define UDMA_AXI_M2S_DESC_RD_CFG_3_MAX_AXI_BEATS_SHIFT 0
-/*
- * Enable breaking descriptor read request.
- * Aligned to max_AXI_beats when the total read size is less than max_AXI_beats.
- */
-#define UDMA_AXI_M2S_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY (1 << 16)
-
-/**** desc_wr_cfg_1 register ****/
-/*
- * Defines the maximum number of AXI beats for a single AXI burst.
- * This value is used for a burst split decision.
- */
-#define UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK 0x000000FF
-#define UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT 0
-/*
- * Minimum burst for writing completion descriptors.
- * Defined in AXI beats
- * 4 Descriptors per beat.
- * Value must be aligned to cache lines (64 bytes).
- * Default value is 2 cache lines, 32 descriptors, 8 beats.
- */
-#define UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK 0x00FF0000
-#define UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT 16
-
-/**** ostand_cfg register ****/
-/* Maximum number of outstanding data reads to the AXI (AXI transactions) */
-#define UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK 0x0000003F
-#define UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_SHIFT 0
-/*
- * Maximum number of outstanding descriptor reads to the AXI (AXI transactions)
- */
-#define UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK 0x00003F00
-#define UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_SHIFT 8
-/*
- * Maximum number of outstanding descriptor writes to the AXI (AXI transactions)
- */
-#define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK 0x003F0000
-#define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_SHIFT 16
-/*
- * Maximum number of outstanding data beats for descriptor write to AXI (AXI
- * beats)
- */
-#define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK 0xFF000000
-#define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_SHIFT 24
-
-/**** state register ****/
-/* Completion control */
-#define UDMA_M2S_STATE_COMP_CTRL_MASK 0x00000003
-#define UDMA_M2S_STATE_COMP_CTRL_SHIFT 0
-/* Stream interface */
-#define UDMA_M2S_STATE_STREAM_IF_MASK 0x00000030
-#define UDMA_M2S_STATE_STREAM_IF_SHIFT 4
-/* Data read control */
-#define UDMA_M2S_STATE_DATA_RD_CTRL_MASK 0x00000300
-#define UDMA_M2S_STATE_DATA_RD_CTRL_SHIFT 8
-/* Descriptor prefetch */
-#define UDMA_M2S_STATE_DESC_PREF_MASK 0x00003000
-#define UDMA_M2S_STATE_DESC_PREF_SHIFT 12
-
-/**** change_state register ****/
-/* Start normal operation */
-#define UDMA_M2S_CHANGE_STATE_NORMAL (1 << 0)
-/* Stop normal operation */
-#define UDMA_M2S_CHANGE_STATE_DIS    (1 << 1)
-/*
- * Stop all machines.
- * (Prefetch, scheduling, completion and stream interface)
- */
-#define UDMA_M2S_CHANGE_STATE_ABORT  (1 << 2)
-
-/**** err_log_mask register ****/
-/*
- * Mismatch of packet serial number.
- * (between first packet in the unacknowledged FIFO and received ack from the
- * stream)
- */
-#define UDMA_M2S_ERR_LOG_MASK_COMP_PKT_MISMATCH (1 << 0)
-/* Parity error */
-#define UDMA_M2S_ERR_LOG_MASK_STREAM_AXI_PARITY (1 << 1)
-/* AXI response error */
-#define UDMA_M2S_ERR_LOG_MASK_STREAM_AXI_RESPONSE (1 << 2)
-/* AXI timeout (ack not received) */
-#define UDMA_M2S_ERR_LOG_MASK_STREAM_AXI_TOUT (1 << 3)
-/* Parity error */
-#define UDMA_M2S_ERR_LOG_MASK_COMP_AXI_PARITY (1 << 4)
-/* AXI response error */
-#define UDMA_M2S_ERR_LOG_MASK_COMP_AXI_RESPONSE (1 << 5)
-/* AXI timeout */
-#define UDMA_M2S_ERR_LOG_MASK_COMP_AXI_TOUT (1 << 6)
-/* Parity error */
-#define UDMA_M2S_ERR_LOG_MASK_DATA_AXI_PARITY (1 << 7)
-/* AXI response error */
-#define UDMA_M2S_ERR_LOG_MASK_DATA_AXI_RESPONSE (1 << 8)
-/* AXI timeout */
-#define UDMA_M2S_ERR_LOG_MASK_DATA_AXI_TOUT (1 << 9)
-/* Parity error */
-#define UDMA_M2S_ERR_LOG_MASK_PREF_AXI_PARITY (1 << 10)
-/* AXI response error */
-#define UDMA_M2S_ERR_LOG_MASK_PREF_AXI_RESPONSE (1 << 11)
-/* AXI timeout */
-#define UDMA_M2S_ERR_LOG_MASK_PREF_AXI_TOUT (1 << 12)
-/* Packet length error */
-#define UDMA_M2S_ERR_LOG_MASK_PREF_PKT_LEN_OVERFLOW (1 << 13)
-/* Maximum number of descriptors per packet error */
-#define UDMA_M2S_ERR_LOG_MASK_PREF_MAX_DESC_CNT (1 << 14)
-/* Error in first bit indication of the descriptor */
-#define UDMA_M2S_ERR_LOG_MASK_PREF_FIRST (1 << 15)
-/* Error in last bit indication of the descriptor */
-#define UDMA_M2S_ERR_LOG_MASK_PREF_LAST (1 << 16)
-/* Ring_ID error */
-#define UDMA_M2S_ERR_LOG_MASK_PREF_RING_ID (1 << 17)
-/* Data buffer parity error */
-#define UDMA_M2S_ERR_LOG_MASK_DATA_BUFF_PARITY (1 << 18)
-/* Internal error */
-#define UDMA_M2S_ERR_LOG_MASK_INTERNAL_MASK 0xFFF80000
-#define UDMA_M2S_ERR_LOG_MASK_INTERNAL_SHIFT 19
-
-/**** clear_err_log register ****/
-/* Clear error log */
-#define UDMA_M2S_CLEAR_ERR_LOG_CLEAR (1 << 0)
-
-/**** data_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_M2S_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_M2S_DATA_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_M2S_DATA_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_M2S_DATA_FIFO_STATUS_FULL (1 << 28)
-
-/**** header_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_M2S_HEADER_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_M2S_HEADER_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_M2S_HEADER_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_M2S_HEADER_FIFO_STATUS_FULL (1 << 28)
-
-/**** unack_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_M2S_UNACK_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_M2S_UNACK_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_M2S_UNACK_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_M2S_UNACK_FIFO_STATUS_FULL (1 << 28)
-
-/**** indirect_ctrl register ****/
-/* Selected queue for status read */
-#define UDMA_M2S_INDIRECT_CTRL_Q_NUM_MASK 0x00000FFF
-#define UDMA_M2S_INDIRECT_CTRL_Q_NUM_SHIFT 0
-
-/**** sel_pref_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_M2S_SEL_PREF_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_M2S_SEL_PREF_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_M2S_SEL_PREF_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_M2S_SEL_PREF_FIFO_STATUS_FULL (1 << 28)
-
-/**** sel_comp_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_M2S_SEL_COMP_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_M2S_SEL_COMP_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_M2S_SEL_COMP_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_M2S_SEL_COMP_FIFO_STATUS_FULL (1 << 28)
-
-/**** sel_rate_limit_status register ****/
-/* Token counter */
-#define UDMA_M2S_SEL_RATE_LIMIT_STATUS_TOKEN_CNT_MASK 0x00FFFFFF
-#define UDMA_M2S_SEL_RATE_LIMIT_STATUS_TOKEN_CNT_SHIFT 0
-
-/**** sel_dwrr_status register ****/
-/* Deficit counter */
-#define UDMA_M2S_SEL_DWRR_STATUS_DEFICIT_CNT_MASK 0x00FFFFFF
-#define UDMA_M2S_SEL_DWRR_STATUS_DEFICIT_CNT_SHIFT 0
-
-/**** cfg_len register ****/
-/* Maximum packet size for the M2S */
-#define UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK 0x000FFFFF
-#define UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_SHIFT 0
-/*
- * Length encoding for 64K.
- * 0 - length 0x0000 = 0
- * 1 - length 0x0000 = 64k
- */
-#define UDMA_M2S_CFG_LEN_ENCODE_64K  (1 << 24)
-
-/**** stream_cfg register ****/
-/*
- * Disables the stream interface operation.
- * Changing to 1 stops at the end of packet transmission.
- */
-#define UDMA_M2S_STREAM_CFG_DISABLE  (1 << 0)
-/*
- * Configuration of the stream FIFO read control.
- * 0 - Cut through
- * 1 - Threshold based
- */
-#define UDMA_M2S_STREAM_CFG_RD_MODE  (1 << 1)
-/* Minimum number of beats to start packet transmission. */
-#define UDMA_M2S_STREAM_CFG_RD_TH_MASK 0x0003FF00
-#define UDMA_M2S_STREAM_CFG_RD_TH_SHIFT 8
-
-/**** desc_pref_cfg_1 register ****/
-/* Size of the descriptor prefetch FIFO (in descriptors) */
-#define UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK 0x000000FF
-#define UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_SHIFT 0
-
-/**** desc_pref_cfg_2 register ****/
-/* Maximum number of descriptors per packet */
-#define UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK 0x0000001F
-#define UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_SHIFT 0
-/*
- * Force RR arbitration in the prefetch arbiter.
- * 0 -Standard arbitration based on queue QoS
- * 1 - Force Round Robin arbitration
- */
-#define UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR (1 << 16)
-
-/**** desc_pref_cfg_3 register ****/
-/*
- * Minimum descriptor burst size when prefetch FIFO level is below the
- * descriptor prefetch threshold
- * (must be 1)
- */
-#define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK 0x0000000F
-#define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_SHIFT 0
-/*
- * Minimum descriptor burst size when prefetch FIFO level is above the
- * descriptor prefetch threshold
- */
-#define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK 0x000000F0
-#define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT 4
-/*
- * Descriptor fetch threshold.
- * Used as a threshold to determine the allowed minimum descriptor burst size.
- * (Must be at least max_desc_per_pkt)
- */
-#define UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK 0x0000FF00
-#define UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT 8
-
-/**** data_cfg register ****/
-/*
- * Maximum number of data beats in the data read FIFO.
- * Defined based on data FIFO size
- * (default FIFO size 2KB → 128 beats)
- */
-#define UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK 0x000003FF
-#define UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_SHIFT 0
-/*
- * Maximum number of packets in the data read FIFO.
- * Defined based on header FIFO size
- */
-#define UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK 0x00FF0000
-#define UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_SHIFT 16
-
-/**** cfg_sched register ****/
-/*
- * Enable the DWRR scheduler.
- * If this bit is 0, queues with same QoS will be served with RR scheduler.
- */
-#define UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR (1 << 0)
-/*
- * Scheduler operation mode.
- * 0 - Byte mode
- * 1 - Packet mode
- */
-#define UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN (1 << 4)
-/*
- * Enable incrementing the weight factor between DWRR iterations.
- * 00 - Don't increase the increment factor.
- * 01 - Increment once
- * 10 - Increment exponential
- * 11 - Reserved
- */
-#define UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_MASK 0x00000300
-#define UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_SHIFT 8
-/*
- * Increment factor power of 2.
- * 7 --> 128 bytes
- * This is the factor used to multiply the weight.
- */
-#define UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_MASK 0x000F0000
-#define UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_SHIFT 16
-
-/**** ctrl_deficit_cnt register ****/
-/*
- * Init value for the deficit counter.
- * Initializes the deficit counters of all queues to this value any time this
- * register is written.
- */
-#define UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_MASK 0x00FFFFFF
-#define UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_SHIFT 0
-
-/**** gen_cfg register ****/
-/* Size of the basic token fill cycle, system clock cycles */
-#define UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK 0x0000FFFF
-#define UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_SHIFT 0
-/*
- * Rate limiter operation mode.
- * 0 - Byte mode
- * 1 - Packet mode
- */
-#define UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN (1 << 24)
-
-/**** ctrl_cycle_cnt register ****/
-/* Reset the short and long cycle counters. */
-#define UDMA_M2S_RATE_LIMITER_CTRL_CYCLE_CNT_RST (1 << 0)
-
-/**** ctrl_token register ****/
-/*
- * Init value for the token counter.
- * Initializes the token counters of all queues to this value any time this
- * register is written.
- */
-#define UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK 0x00FFFFFF
-#define UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_SHIFT 0
-
-/**** cfg_1s register ****/
-/* Maximum number of accumulated bytes in the token counter */
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK 0x00FFFFFF
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_SHIFT 0
-/* Enable the rate limiter. */
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN (1 << 24)
-/* Stop token fill. */
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE (1 << 25)
-
-/**** cfg_cycle register ****/
-/* Number of short cycles between token fills */
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK 0x0000FFFF
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_SHIFT 0
-
-/**** cfg_token_size_1 register ****/
-/* Number of bits to add in each long cycle */
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK 0x0007FFFF
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_SHIFT 0
-
-/**** cfg_token_size_2 register ****/
-/* Number of bits to add in each short cycle */
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK 0x0007FFFF
-#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_SHIFT 0
-
-/**** sw_ctrl register ****/
-/* Reset the token bucket counter. */
-#define UDMA_M2S_STREAM_RATE_LIMITER_SW_CTRL_RST_TOKEN_CNT (1 << 0)
-
-/**** mask register ****/
-/* Mask the external rate limiter. */
-#define UDMA_M2S_STREAM_RATE_LIMITER_MASK_EXTERNAL_RATE_LIMITER (1 << 0)
-/* Mask the internal rate limiter. */
-#define UDMA_M2S_STREAM_RATE_LIMITER_MASK_INTERNAL_RATE_LIMITER (1 << 1)
-/* Mask the external application pause interface. */
-#define UDMA_M2S_STREAM_RATE_LIMITER_MASK_EXTERNAL_PAUSE (1 << 3)
-
-/**** cfg_1c register ****/
-/*
- * Completion FIFO size
- *  (descriptors per queue)
- */
-#define UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK 0x000000FF
-#define UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_SHIFT 0
-/*
- * Unacknowledged FIFO size.
- * (descriptors)
- */
-#define UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK 0x0001FF00
-#define UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_SHIFT 8
-/*
- * Enable promotion.
- * Enable the promotion of the current queue in progress for the completion
- * write scheduler.
- */
-#define UDMA_M2S_COMP_CFG_1C_Q_PROMOTION (1 << 24)
-/* Force RR arbitration in the completion arbiter */
-#define UDMA_M2S_COMP_CFG_1C_FORCE_RR (1 << 25)
-/* Minimum number of free completion entries to qualify for promotion */
-#define UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN_MASK 0xF0000000
-#define UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN_SHIFT 28
-
-/**** cfg_application_ack register ****/
-/*
- * Acknowledge timeout timer.
- * ACK from the application through the stream interface)
- */
-#define UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK 0x00FFFFFF
-#define UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT 0
-
-/**** cfg_st register ****/
-/* Use additional length value for all statistics counters. */
-#define UDMA_M2S_STAT_CFG_ST_USE_EXTRA_LEN (1 << 0)
-
-/**** reg_1 register ****/
-/*
- * Read the size of the descriptor prefetch FIFO
- * (descriptors).
- */
-#define UDMA_M2S_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_MASK 0x000000FF
-#define UDMA_M2S_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_SHIFT 0
-
-/**** reg_3 register ****/
-/*
- * Maximum number of data beats in the data read FIFO.
- * Defined based on data FIFO size
- * (default FIFO size 2KB → 128 beats)
- */
-#define UDMA_M2S_FEATURE_REG_3_DATA_FIFO_DEPTH_MASK 0x000003FF
-#define UDMA_M2S_FEATURE_REG_3_DATA_FIFO_DEPTH_SHIFT 0
-/*
- * Maximum number of packets in the data read FIFO.
- * Defined based on header FIFO size
- */
-#define UDMA_M2S_FEATURE_REG_3_DATA_RD_MAX_PKT_LIMIT_MASK 0x00FF0000
-#define UDMA_M2S_FEATURE_REG_3_DATA_RD_MAX_PKT_LIMIT_SHIFT 16
-
-/**** reg_4 register ****/
-/*
- * Size of the completion FIFO of each queue
- * (words)
- */
-#define UDMA_M2S_FEATURE_REG_4_COMP_FIFO_DEPTH_MASK 0x000000FF
-#define UDMA_M2S_FEATURE_REG_4_COMP_FIFO_DEPTH_SHIFT 0
-/* Size of the unacknowledged FIFO (descriptors) */
-#define UDMA_M2S_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_MASK 0x0001FF00
-#define UDMA_M2S_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_SHIFT 8
-
-/**** reg_5 register ****/
-/* Maximum number of outstanding data reads to AXI */
-#define UDMA_M2S_FEATURE_REG_5_MAX_DATA_RD_OSTAND_MASK 0x0000003F
-#define UDMA_M2S_FEATURE_REG_5_MAX_DATA_RD_OSTAND_SHIFT 0
-/* Maximum number of outstanding descriptor reads to AXI */
-#define UDMA_M2S_FEATURE_REG_5_MAX_DESC_RD_OSTAND_MASK 0x00003F00
-#define UDMA_M2S_FEATURE_REG_5_MAX_DESC_RD_OSTAND_SHIFT 8
-/*
- * Maximum number of outstanding descriptor writes to AXI.
- * (AXI transactions)
- */
-#define UDMA_M2S_FEATURE_REG_5_MAX_COMP_REQ_MASK 0x003F0000
-#define UDMA_M2S_FEATURE_REG_5_MAX_COMP_REQ_SHIFT 16
-/*
- * Maximum number of outstanding data beats for descriptor write to AXI.
- * (AXI beats)
- */
-#define UDMA_M2S_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000
-#define UDMA_M2S_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_SHIFT 24
-
-/**** cfg register ****/
-/*
- * Length offset to be used for each packet from this queue.
- * (length offset is used for the scheduler and rate limiter).
- */
-#define UDMA_M2S_Q_CFG_PKT_LEN_OFFSET_MASK 0x0000FFFF
-#define UDMA_M2S_Q_CFG_PKT_LEN_OFFSET_SHIFT 0
-/*
- * Enable operation of this queue.
- * Start prefetch.
- */
-#define UDMA_M2S_Q_CFG_EN_PREF       (1 << 16)
-/*
- * Enable operation of this queue.
- * Start scheduling.
- */
-#define UDMA_M2S_Q_CFG_EN_SCHEDULING (1 << 17)
-/* Allow prefetch of less than minimum prefetch burst size. */
-#define UDMA_M2S_Q_CFG_ALLOW_LT_MIN_PREF (1 << 20)
-/* Configure the AXI AWCACHE for completion write.  */
-#define UDMA_M2S_Q_CFG_AXI_AWCACHE_COMP_MASK 0x0F000000
-#define UDMA_M2S_Q_CFG_AXI_AWCACHE_COMP_SHIFT 24
-/*
- * AXI QoS for the selected queue.
- * This value is used in AXI transactions associated with this queue and the
- * prefetch and completion arbiters.
- */
-#define UDMA_M2S_Q_CFG_AXI_QOS_MASK  0x70000000
-#define UDMA_M2S_Q_CFG_AXI_QOS_SHIFT 28
-
-/**** status register ****/
-/* Indicates how many entries are used in the queue */
-#define UDMA_M2S_Q_STATUS_Q_USED_MASK 0x01FFFFFF
-#define UDMA_M2S_Q_STATUS_Q_USED_SHIFT 0
-/*
- * prefetch status
- * 0 – prefetch operation is stopped
- * 1 – prefetch is operational
- */
-#define UDMA_M2S_Q_STATUS_PREFETCH   (1 << 28)
-/*
- * Queue scheduler status
- * 0 – queue is not active and not participating in scheduling
- * 1 – queue is active and participating in the scheduling process
- */
-#define UDMA_M2S_Q_STATUS_SCHEDULER  (1 << 29)
-/* Queue is suspended due to DMB */
-#define UDMA_M2S_Q_STATUS_Q_DMB      (1 << 30)
-/*
- * Queue full indication.
- * (used by the host when head pointer equals tail pointer).
- */
-#define UDMA_M2S_Q_STATUS_Q_FULL     (1 << 31)
-/*
- * M2S Descriptor Ring Base address [31:4].
- * Value of the base address of the M2S descriptor ring
- * [3:0] - 0 - 16B alignment is enforced
- * ([11:4] should be 0 for 4KB alignment)
- */
-#define UDMA_M2S_Q_TDRBP_LOW_ADDR_MASK 0xFFFFFFF0
-#define UDMA_M2S_Q_TDRBP_LOW_ADDR_SHIFT 4
-
-/**** TDRL register ****/
-/*
- * Length of the descriptor ring.
- * (descriptors)
- * Associated with the ring base address, ends at maximum burst size alignment.
- */
-#define UDMA_M2S_Q_TDRL_OFFSET_MASK  0x00FFFFFF
-#define UDMA_M2S_Q_TDRL_OFFSET_SHIFT 0
-
-/**** TDRHP register ****/
-/*
- * Relative offset of the next descriptor that needs to be read into the
- * prefetch FIFO.
- * Incremented when the DMA reads valid descriptors from the host memory to the
- * prefetch FIFO.
- * Note that this is the offset in # of descriptors and not in byte address.
- */
-#define UDMA_M2S_Q_TDRHP_OFFSET_MASK 0x00FFFFFF
-#define UDMA_M2S_Q_TDRHP_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_M2S_Q_TDRHP_RING_ID_MASK 0xC0000000
-#define UDMA_M2S_Q_TDRHP_RING_ID_SHIFT 30
-
-/**** TDRTP_inc register ****/
-/* Increments the value in Q_TDRTP (descriptors) */
-#define UDMA_M2S_Q_TDRTP_INC_VAL_MASK 0x00FFFFFF
-#define UDMA_M2S_Q_TDRTP_INC_VAL_SHIFT 0
-
-/**** TDRTP register ****/
-/*
- * Relative offset of the next free descriptor in the host memory.
- * Note that this is the offset in # of descriptors and not in byte address.
- */
-#define UDMA_M2S_Q_TDRTP_OFFSET_MASK 0x00FFFFFF
-#define UDMA_M2S_Q_TDRTP_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_M2S_Q_TDRTP_RING_ID_MASK 0xC0000000
-#define UDMA_M2S_Q_TDRTP_RING_ID_SHIFT 30
-
-/**** TDCP register ****/
-/*
- * Relative offset of the first descriptor in the prefetch FIFO.
- * This is the next descriptor that will be read by the scheduler.
- */
-#define UDMA_M2S_Q_TDCP_OFFSET_MASK  0x00FFFFFF
-#define UDMA_M2S_Q_TDCP_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_M2S_Q_TDCP_RING_ID_MASK 0xC0000000
-#define UDMA_M2S_Q_TDCP_RING_ID_SHIFT 30
-/*
- * M2S Descriptor Ring Base address [31:4].
- * Value of the base address of the M2S descriptor ring
- * [3:0] - 0 - 16B alignment is enforced
- * ([11:4] should be 0 for 4KB alignment)
- * NOTE:
- * Length of the descriptor ring (in descriptors) associated with the ring base
- * address. Ends at maximum burst size alignment.
- */
-#define UDMA_M2S_Q_TCRBP_LOW_ADDR_MASK 0xFFFFFFF0
-#define UDMA_M2S_Q_TCRBP_LOW_ADDR_SHIFT 4
-
-/**** TCRHP register ****/
-/*
- * Relative offset of the next descriptor that needs to be updated by the
- * completion controller.
- * Note: This is in descriptors and not in byte address.
- */
-#define UDMA_M2S_Q_TCRHP_OFFSET_MASK 0x00FFFFFF
-#define UDMA_M2S_Q_TCRHP_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_M2S_Q_TCRHP_RING_ID_MASK 0xC0000000
-#define UDMA_M2S_Q_TCRHP_RING_ID_SHIFT 30
-
-/**** TCRHP_internal register ****/
-/*
- * Relative offset of the next descriptor that needs to be updated by the
- * completion controller.
- * Note: This is in descriptors and not in byte address.
- */
-#define UDMA_M2S_Q_TCRHP_INTERNAL_OFFSET_MASK 0x00FFFFFF
-#define UDMA_M2S_Q_TCRHP_INTERNAL_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_M2S_Q_TCRHP_INTERNAL_RING_ID_MASK 0xC0000000
-#define UDMA_M2S_Q_TCRHP_INTERNAL_RING_ID_SHIFT 30
-
-/**** rate_limit_cfg_1 register ****/
-/* Maximum number of accumulated bytes in the token counter. */
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_1_MAX_BURST_SIZE_MASK 0x00FFFFFF
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_1_MAX_BURST_SIZE_SHIFT 0
-/* Enable the rate limiter. */
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_1_EN (1 << 24)
-/* Stop token fill. */
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_1_PAUSE (1 << 25)
-
-/**** rate_limit_cfg_cycle register ****/
-/* Number of short cycles between token fills */
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_CYCLE_LONG_CYCLE_SIZE_MASK 0x0000FFFF
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_CYCLE_LONG_CYCLE_SIZE_SHIFT 0
-
-/**** rate_limit_cfg_token_size_1 register ****/
-/* Number of bits to add in each long cycle */
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK 0x0007FFFF
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_1_LONG_CYCLE_SHIFT 0
-
-/**** rate_limit_cfg_token_size_2 register ****/
-/* Number of bits to add in each cycle */
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK 0x0007FFFF
-#define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_2_SHORT_CYCLE_SHIFT 0
-
-/**** rate_limit_sw_ctrl register ****/
-/* Reset the token bucket counter. */
-#define UDMA_M2S_Q_RATE_LIMIT_SW_CTRL_RST_TOKEN_CNT (1 << 0)
-
-/**** rate_limit_mask register ****/
-/* Mask the external rate limiter. */
-#define UDMA_M2S_Q_RATE_LIMIT_MASK_EXTERNAL_RATE_LIMITER (1 << 0)
-/* Mask the internal rate limiter. */
-#define UDMA_M2S_Q_RATE_LIMIT_MASK_INTERNAL_RATE_LIMITER (1 << 1)
-/*
- * Mask the internal pause mechanism for DMB.
- * (Data Memory Barrier).
- */
-#define UDMA_M2S_Q_RATE_LIMIT_MASK_INTERNAL_PAUSE_DMB (1 << 2)
-/* Mask the external application pause interface. */
-#define UDMA_M2S_Q_RATE_LIMIT_MASK_EXTERNAL_PAUSE (1 << 3)
-
-/**** dwrr_cfg_1 register ****/
-/* Maximum number of accumulated bytes in the deficit counter */
-#define UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK 0x00FFFFFF
-#define UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_SHIFT 0
-/* Bypass the DWRR.  */
-#define UDMA_M2S_Q_DWRR_CFG_1_STRICT (1 << 24)
-/* Stop deficit counter increment. */
-#define UDMA_M2S_Q_DWRR_CFG_1_PAUSE  (1 << 25)
-
-/**** dwrr_cfg_2 register ****/
-/*
- * Value for the queue QoS.
- * Queues with the same QoS value are scheduled with RR/DWRR.
- * Only LOG(number of queues) is used.
- */
-#define UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK 0x000000FF
-#define UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_SHIFT 0
-
-/**** dwrr_cfg_3 register ****/
-/* Queue weight */
-#define UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK 0x000000FF
-#define UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_SHIFT 0
-
-/**** dwrr_sw_ctrl register ****/
-/* Reset the DWRR deficit counter. */
-#define UDMA_M2S_Q_DWRR_SW_CTRL_RST_CNT (1 << 0)
-
-/**** comp_cfg register ****/
-/* Enable writing to the completion ring */
-#define UDMA_M2S_Q_COMP_CFG_EN_COMP_RING_UPDATE (1 << 0)
-/* Disable the completion coalescing function. */
-#define UDMA_M2S_Q_COMP_CFG_DIS_COMP_COAL (1 << 1)
-
-/**** q_sw_ctrl register ****/
-/*
- * Reset the DMB hardware barrier
- * (enable queue operation).
- */
-#define UDMA_M2S_Q_SW_CTRL_RST_DMB (1 << 0)
-/* Reset the tail pointer hardware. */
-#define UDMA_M2S_Q_SW_CTRL_RST_TAIL_PTR (1 << 1)
-/* Reset the head pointer hardware. */
-#define UDMA_M2S_Q_SW_CTRL_RST_HEAD_PTR (1 << 2)
-/* Reset the current pointer hardware. */
-#define UDMA_M2S_Q_SW_CTRL_RST_CURRENT_PTR (1 << 3)
-/* Reset the queue */
-#define UDMA_M2S_Q_SW_CTRL_RST_Q   (1 << 8)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_UDMA_M2S_REG_H */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_udma_regs_s2m.h b/sys/contrib/alpine-hal/eth/al_hal_udma_regs_s2m.h
deleted file mode 100644
index 4b3149b97ae6..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_udma_regs_s2m.h
+++ /dev/null
@@ -1,998 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @file   al_hal_udma_regs_s2m.h
- *
- * @brief C Header file for the UDMA S2M registers
- *
- */
-
-#ifndef __AL_HAL_UDMA_S2M_REG_H
-#define __AL_HAL_UDMA_S2M_REG_H
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-
-
-struct udma_axi_s2m {
-	/* [0x0] Data write master configuration */
-	uint32_t data_wr_cfg_1;
-	/* [0x4] Data write master configuration */
-	uint32_t data_wr_cfg_2;
-	/* [0x8] Descriptor read master configuration */
-	uint32_t desc_rd_cfg_4;
-	/* [0xc] Descriptor read master configuration */
-	uint32_t desc_rd_cfg_5;
-	/* [0x10] Completion  write master configuration */
-	uint32_t comp_wr_cfg_1;
-	/* [0x14] Completion  write master configuration */
-	uint32_t comp_wr_cfg_2;
-	/* [0x18] Data write master configuration */
-	uint32_t data_wr_cfg;
-	/* [0x1c] Descriptors read master configuration */
-	uint32_t desc_rd_cfg_3;
-	/* [0x20] Completion descriptors write master configuration */
-	uint32_t desc_wr_cfg_1;
-	/* [0x24] AXI outstanding read configuration */
-	uint32_t ostand_cfg_rd;
-	/* [0x28] AXI outstanding write configuration */
-	uint32_t ostand_cfg_wr;
-	uint32_t rsrvd[53];
-};
-struct udma_s2m {
-	/*
-	 * [0x0] DMA state
-	 * 00  - No pending tasks
-	 * 01 – Normal (active)
-	 * 10 – Abort (error condition)
-	 * 11 – Reserved
-	 */
-	uint32_t state;
-	/* [0x4] CPU request to change DMA state */
-	uint32_t change_state;
-	uint32_t rsrvd_0;
-	/*
-	 * [0xc] S2M DMA error log mask.
-	 * Each error has an interrupt controller cause bit.
-	 * This register determines if these errors cause the S2M DMA to log the
-	 * error condition.
-	 * 0 - Log is enable
-	 * 1 - Log is masked.
-	 */
-	uint32_t err_log_mask;
-	uint32_t rsrvd_1;
-	/*
-	 * [0x14] DMA header log
-	 * Sample the packet header that caused the error
-	 */
-	uint32_t log_0;
-	/*
-	 * [0x18] DMA header log
-	 * Sample the packet header that caused the error.
-	 */
-	uint32_t log_1;
-	/*
-	 * [0x1c] DMA header log
-	 * Sample the packet header that caused the error.
-	 */
-	uint32_t log_2;
-	/*
-	 * [0x20] DMA header log
-	 * Sample the packet header that caused the error
-	 */
-	uint32_t log_3;
-	/* [0x24] DMA clear error log */
-	uint32_t clear_err_log;
-	/* [0x28] S2M stream data FIFO status */
-	uint32_t s_data_fifo_status;
-	/* [0x2c] S2M stream header FIFO status */
-	uint32_t s_header_fifo_status;
-	/* [0x30] S2M AXI data FIFO status */
-	uint32_t axi_data_fifo_status;
-	/* [0x34] S2M unack FIFO status */
-	uint32_t unack_fifo_status;
-	/* [0x38] Select queue for debug */
-	uint32_t indirect_ctrl;
-	/*
-	 * [0x3c] S2M prefetch FIFO status.
-	 * Status of the selected queue in S2M_indirect_ctrl
-	 */
-	uint32_t sel_pref_fifo_status;
-	/*
-	 * [0x40] S2M completion FIFO status.
-	 * Status of the selected queue in S2M_indirect_ctrl
-	 */
-	uint32_t sel_comp_fifo_status;
-	/* [0x44] S2M state machine and FIFO clear control */
-	uint32_t clear_ctrl;
-	/* [0x48] S2M Misc Check enable */
-	uint32_t check_en;
-	/* [0x4c] S2M FIFO enable control, internal */
-	uint32_t fifo_en;
-	/* [0x50] Stream interface configuration */
-	uint32_t stream_cfg;
-	uint32_t rsrvd[43];
-};
-struct udma_s2m_rd {
-	/* [0x0] S2M descriptor prefetch configuration */
-	uint32_t desc_pref_cfg_1;
-	/* [0x4] S2M descriptor prefetch configuration */
-	uint32_t desc_pref_cfg_2;
-	/* [0x8] S2M descriptor prefetch configuration */
-	uint32_t desc_pref_cfg_3;
-	/* [0xc] S2M descriptor prefetch configuration */
-	uint32_t desc_pref_cfg_4;
-	uint32_t rsrvd[12];
-};
-struct udma_s2m_wr {
-	/* [0x0] Stream data FIFO configuration */
-	uint32_t data_cfg_1;
-	/* [0x4] Data write configuration */
-	uint32_t data_cfg_2;
-	uint32_t rsrvd[14];
-};
-struct udma_s2m_comp {
-	/* [0x0] Completion controller configuration */
-	uint32_t cfg_1c;
-	/* [0x4] Completion controller configuration */
-	uint32_t cfg_2c;
-	uint32_t rsrvd_0;
-	/* [0xc] Completion controller application acknowledge configuration */
-	uint32_t cfg_application_ack;
-	uint32_t rsrvd[12];
-};
-struct udma_s2m_stat {
-	uint32_t rsrvd_0;
-	/* [0x4] Number of dropped packets */
-	uint32_t drop_pkt;
-	/*
-	 * [0x8] Counting the net length of the data buffers [64-bit]
-	 * Should be read before rx_bytes_high
-	 */
-	uint32_t rx_bytes_low;
-	/*
-	 * [0xc] Counting the net length of the data buffers [64-bit]
-	 * Should be read after tx_bytes_low (value is sampled when reading
-	 * Should be read before rx_bytes_low
-	 */
-	uint32_t rx_bytes_high;
-	/* [0x10] Total number of descriptors read from the host memory */
-	uint32_t prefed_desc;
-	/* [0x14] Number of packets written into the completion ring */
-	uint32_t comp_pkt;
-	/* [0x18] Number of descriptors written into the completion ring */
-	uint32_t comp_desc;
-	/*
-	 * [0x1c] Number of acknowledged packets.
-	 * (acknowledge sent to the stream interface)
-	 */
-	uint32_t ack_pkts;
-	uint32_t rsrvd[56];
-};
-struct udma_s2m_feature {
-	/*
-	 * [0x0] S2M Feature register
-	 * S2M instantiation parameters
-	 */
-	uint32_t reg_1;
-	/* [0x4] Reserved S2M feature register */
-	uint32_t reg_2;
-	/*
-	 * [0x8] S2M Feature register
-	 * S2M instantiation parameters
-	 */
-	uint32_t reg_3;
-	/*
-	 * [0xc] S2M Feature register.
-	 * S2M instantiation parameters.
-	 */
-	uint32_t reg_4;
-	/*
-	 * [0x10] S2M Feature register.
-	 * S2M instantiation parameters.
-	 */
-	uint32_t reg_5;
-	/* [0x14] S2M Feature register. S2M instantiation parameters. */
-	uint32_t reg_6;
-	uint32_t rsrvd[58];
-};
-struct udma_s2m_q {
-	uint32_t rsrvd_0[8];
-	/* [0x20] S2M Descriptor ring configuration */
-	uint32_t cfg;
-	/* [0x24] S2M Descriptor ring status and information */
-	uint32_t status;
-	/* [0x28] Rx Descriptor Ring Base Pointer [31:4] */
-	uint32_t rdrbp_low;
-	/* [0x2c] Rx Descriptor Ring Base Pointer [63:32] */
-	uint32_t rdrbp_high;
-	/*
-	 * [0x30] Rx Descriptor Ring Length[23:2]
-	 */
-	uint32_t rdrl;
-	/* [0x34] RX Descriptor Ring Head Pointer */
-	uint32_t rdrhp;
-	/* [0x38] Rx Descriptor Tail Pointer increment */
-	uint32_t rdrtp_inc;
-	/* [0x3c] Rx Descriptor Tail Pointer */
-	uint32_t rdrtp;
-	/* [0x40] RX Descriptor Current Pointer */
-	uint32_t rdcp;
-	/* [0x44] Rx Completion Ring Base Pointer [31:4] */
-	uint32_t rcrbp_low;
-	/* [0x48] Rx Completion Ring Base Pointer [63:32] */
-	uint32_t rcrbp_high;
-	/* [0x4c] Rx Completion Ring Head Pointer */
-	uint32_t rcrhp;
-	/*
-	 * [0x50] RX Completion Ring Head Pointer internal.
-	 * (Before the coalescing FIFO)
-	 */
-	uint32_t rcrhp_internal;
-	/* [0x54] Completion controller configuration for the queue */
-	uint32_t comp_cfg;
-	/* [0x58] Completion controller configuration for the queue */
-	uint32_t comp_cfg_2;
-	/* [0x5c] Packet handler configuration */
-	uint32_t pkt_cfg;
-	/* [0x60] Queue QoS configuration */
-	uint32_t qos_cfg;
-	/* [0x64] DMB software control */
-	uint32_t q_sw_ctrl;
-	/* [0x68] Number of S2M Rx packets after completion  */
-	uint32_t q_rx_pkt;
-	uint32_t rsrvd[997];
-};
-
-struct udma_s2m_regs {
-	uint32_t rsrvd_0[64];
-	struct udma_axi_s2m axi_s2m;                     /* [0x100] */
-	struct udma_s2m s2m;                             /* [0x200] */
-	struct udma_s2m_rd s2m_rd;                       /* [0x300] */
-	struct udma_s2m_wr s2m_wr;                       /* [0x340] */
-	struct udma_s2m_comp s2m_comp;                   /* [0x380] */
-	uint32_t rsrvd_1[80];
-	struct udma_s2m_stat s2m_stat;                   /* [0x500] */
-	struct udma_s2m_feature s2m_feature;             /* [0x600] */
-	uint32_t rsrvd_2[576];
-	struct udma_s2m_q s2m_q[4];                      /* [0x1000] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** data_wr_cfg_1 register ****/
-/* AXI write  ID (AWID) */
-#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWID_MASK 0x000000FF
-#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWID_SHIFT 0
-/* Cache Type */
-#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWCACHE_MASK 0x000F0000
-#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWCACHE_SHIFT 16
-/* Burst type */
-#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWBURST_MASK 0x03000000
-#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWBURST_SHIFT 24
-
-/**** data_wr_cfg_2 register ****/
-/* User extension */
-#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWUSER_MASK 0x000FFFFF
-#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWUSER_SHIFT 0
-/* Bus size, 128-bit */
-#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWSIZE_MASK 0x00700000
-#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWSIZE_SHIFT 20
-/*
- * AXI Master QoS.
- * Used for arbitration between AXI masters
- */
-#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWQOS_MASK 0x07000000
-#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWQOS_SHIFT 24
-/* Protection Type */
-#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWPROT_MASK 0x70000000
-#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWPROT_SHIFT 28
-
-/**** desc_rd_cfg_4 register ****/
-/* AXI read  ID (ARID) */
-#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARID_MASK 0x000000FF
-#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARID_SHIFT 0
-/* Cache Type */
-#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARCACHE_MASK 0x000F0000
-#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARCACHE_SHIFT 16
-/* Burst type */
-#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARBURST_MASK 0x03000000
-#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARBURST_SHIFT 24
-
-/**** desc_rd_cfg_5 register ****/
-/* User extension */
-#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARUSER_MASK 0x000FFFFF
-#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARUSER_SHIFT 0
-/* Bus size, 128-bit */
-#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARSIZE_MASK 0x00700000
-#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARSIZE_SHIFT 20
-/*
- * AXI Master QoS.
- * Used for arbitration between AXI masters
- */
-#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARQOS_MASK 0x07000000
-#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARQOS_SHIFT 24
-/* Protection Type */
-#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARPROT_MASK 0x70000000
-#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARPROT_SHIFT 28
-
-/**** comp_wr_cfg_1 register ****/
-/* AXI write  ID (AWID) */
-#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK 0x000000FF
-#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_SHIFT 0
-/* Cache Type */
-#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_MASK 0x000F0000
-#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_SHIFT 16
-/* Burst type */
-#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_MASK 0x03000000
-#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_SHIFT 24
-
-/**** comp_wr_cfg_2 register ****/
-/* User extension */
-#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK 0x000FFFFF
-#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_SHIFT 0
-/* Bus size, 128-bit */
-#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_MASK 0x00700000
-#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_SHIFT 20
-/*
- * AXI Master QoS.
- * Used for arbitration between AXI masters
- */
-#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_MASK 0x07000000
-#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_SHIFT 24
-/* Protection Type */
-#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_MASK 0x70000000
-#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_SHIFT 28
-
-/**** data_wr_cfg register ****/
-/*
- * Defines the maximum number of AXI beats for a single AXI burst. This value is
- * used for the burst split decision.
- */
-#define UDMA_AXI_S2M_DATA_WR_CFG_MAX_AXI_BEATS_MASK 0x000000FF
-#define UDMA_AXI_S2M_DATA_WR_CFG_MAX_AXI_BEATS_SHIFT 0
-
-/**** desc_rd_cfg_3 register ****/
-/*
- * Defines the maximum number of AXI beats for a single AXI burst. This value is
- * used for the burst split decision.
- */
-#define UDMA_AXI_S2M_DESC_RD_CFG_3_MAX_AXI_BEATS_MASK 0x000000FF
-#define UDMA_AXI_S2M_DESC_RD_CFG_3_MAX_AXI_BEATS_SHIFT 0
-/*
- * Enables breaking descriptor read request.
- * Aligned to max_AXI_beats when the total read size is less than max_AXI_beats.
- */
-#define UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY (1 << 16)
-
-/**** desc_wr_cfg_1 register ****/
-/*
- * Defines the maximum number of AXI beats for a single AXI burst. This value is
- * used for the burst split decision.
- */
-#define UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK 0x000000FF
-#define UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT 0
-/*
- * Minimum burst for writing completion descriptors.
- * (AXI beats).
- * Value must be aligned to cache lines (64 bytes).
- * Default value is 2 cache lines, 8 beats.
- */
-#define UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK 0x00FF0000
-#define UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT 16
-
-/**** ostand_cfg_rd register ****/
-/*
- * Maximum number of outstanding descriptor reads to the AXI.
- * (AXI transactions).
- */
-#define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_MASK 0x0000003F
-#define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_SHIFT 0
-/* Maximum number of outstanding stream acknowledges. */
-#define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_MASK 0x001F0000
-#define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_SHIFT 16
-
-/**** ostand_cfg_wr register ****/
-/*
- * Maximum number of outstanding data writes to the AXI.
- * (AXI transactions).
- */
-#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_MASK 0x0000003F
-#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_SHIFT 0
-/*
- * Maximum number of outstanding data beats for data write to AXI.
- * (AXI beats).
- */
-#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_MASK 0x0000FF00
-#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_SHIFT 8
-/*
- * Maximum number of outstanding descriptor writes to the AXI.
- * (AXI transactions).
- */
-#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_MASK 0x003F0000
-#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_SHIFT 16
-/*
- * Maximum number of outstanding data beats for descriptor write to AXI.
- * (AXI beats).
- */
-#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000
-#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_SHIFT 24
-
-/**** state register ****/
-
-#define UDMA_S2M_STATE_COMP_CTRL_MASK 0x00000003
-#define UDMA_S2M_STATE_COMP_CTRL_SHIFT 0
-
-#define UDMA_S2M_STATE_STREAM_IF_MASK 0x00000030
-#define UDMA_S2M_STATE_STREAM_IF_SHIFT 4
-
-#define UDMA_S2M_STATE_DATA_WR_CTRL_MASK 0x00000300
-#define UDMA_S2M_STATE_DATA_WR_CTRL_SHIFT 8
-
-#define UDMA_S2M_STATE_DESC_PREF_MASK 0x00003000
-#define UDMA_S2M_STATE_DESC_PREF_SHIFT 12
-
-#define UDMA_S2M_STATE_AXI_WR_DATA_MASK 0x00030000
-#define UDMA_S2M_STATE_AXI_WR_DATA_SHIFT 16
-
-/**** change_state register ****/
-/* Start normal operation */
-#define UDMA_S2M_CHANGE_STATE_NORMAL (1 << 0)
-/* Stop normal operation */
-#define UDMA_S2M_CHANGE_STATE_DIS    (1 << 1)
-/*
- * Stop all machines.
- * (Prefetch, scheduling, completion and stream interface)
- */
-#define UDMA_S2M_CHANGE_STATE_ABORT  (1 << 2)
-
-/**** clear_err_log register ****/
-/* Clear error log */
-#define UDMA_S2M_CLEAR_ERR_LOG_CLEAR (1 << 0)
-
-/**** s_data_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_S2M_S_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_S2M_S_DATA_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_S2M_S_DATA_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_S2M_S_DATA_FIFO_STATUS_FULL (1 << 28)
-
-/**** s_header_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_S2M_S_HEADER_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_S2M_S_HEADER_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_S2M_S_HEADER_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_S2M_S_HEADER_FIFO_STATUS_FULL (1 << 28)
-
-/**** axi_data_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_S2M_AXI_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_S2M_AXI_DATA_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_S2M_AXI_DATA_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_S2M_AXI_DATA_FIFO_STATUS_FULL (1 << 28)
-
-/**** unack_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_S2M_UNACK_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_S2M_UNACK_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_S2M_UNACK_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_S2M_UNACK_FIFO_STATUS_FULL (1 << 28)
-
-/**** indirect_ctrl register ****/
-/* Selected queue for status read */
-#define UDMA_S2M_INDIRECT_CTRL_Q_NUM_MASK 0x00000FFF
-#define UDMA_S2M_INDIRECT_CTRL_Q_NUM_SHIFT 0
-
-/**** sel_pref_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_S2M_SEL_PREF_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_S2M_SEL_PREF_FIFO_STATUS_USED_SHIFT 0
-/* FIFO empty indication */
-#define UDMA_S2M_SEL_PREF_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_S2M_SEL_PREF_FIFO_STATUS_FULL (1 << 28)
-
-/**** sel_comp_fifo_status register ****/
-/* FIFO used indication */
-#define UDMA_S2M_SEL_COMP_FIFO_STATUS_USED_MASK 0x0000FFFF
-#define UDMA_S2M_SEL_COMP_FIFO_STATUS_USED_SHIFT 0
-/* Coalescing ACTIVE FSM state indication. */
-#define UDMA_S2M_SEL_COMP_FIFO_STATUS_COAL_ACTIVE_STATE_MASK 0x00300000
-#define UDMA_S2M_SEL_COMP_FIFO_STATUS_COAL_ACTIVE_STATE_SHIFT 20
-/* FIFO empty indication */
-#define UDMA_S2M_SEL_COMP_FIFO_STATUS_EMPTY (1 << 24)
-/* FIFO full indication */
-#define UDMA_S2M_SEL_COMP_FIFO_STATUS_FULL (1 << 28)
-
-/**** stream_cfg register ****/
-/*
- * Disables the stream interface operation.
- * Changing to 1 stops at the end of packet reception.
- */
-#define UDMA_S2M_STREAM_CFG_DISABLE  (1 << 0)
-/*
- * Flush the stream interface operation.
- * Changing to 1 stops at the end of packet reception and assert ready to the
- * stream I/F.
- */
-#define UDMA_S2M_STREAM_CFG_FLUSH    (1 << 4)
-/* Stop descriptor prefetch when the stream is disabled and the S2M is idle. */
-#define UDMA_S2M_STREAM_CFG_STOP_PREFETCH (1 << 8)
-
-/**** desc_pref_cfg_1 register ****/
-/*
- * Size of the descriptor prefetch FIFO.
- * (descriptors)
- */
-#define UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK 0x000000FF
-#define UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_SHIFT 0
-
-/**** desc_pref_cfg_2 register ****/
-/* Enable promotion of the current queue in progress */
-#define UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION (1 << 0)
-/* Force promotion of the current queue in progress */
-#define UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION (1 << 1)
-/* Enable prefetch prediction of next packet in line. */
-#define UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION (1 << 2)
-/*
- * Threshold for queue promotion.
- * Queue is promoted for prefetch if there are less descriptors in the prefetch
- * FIFO than the threshold
- */
-#define UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_MASK 0x0000FF00
-#define UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_SHIFT 8
-/*
- * Force RR arbitration in the prefetch arbiter.
- * 0 - Standard arbitration based on queue QoS
- * 1 - Force round robin arbitration
- */
-#define UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR (1 << 16)
-
-/**** desc_pref_cfg_3 register ****/
-/*
- * Minimum descriptor burst size when prefetch FIFO level is below the
- * descriptor prefetch threshold
- * (must be 1)
- */
-#define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK 0x0000000F
-#define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_SHIFT 0
-/*
- * Minimum descriptor burst size when prefetch FIFO level is above the
- * descriptor prefetch threshold
- */
-#define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK 0x000000F0
-#define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT 4
-/*
- * Descriptor fetch threshold.
- * Used as a threshold to determine the allowed minimum descriptor burst size.
- * (Must be at least "max_desc_per_pkt")
- */
-#define UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK 0x0000FF00
-#define UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT 8
-
-/**** desc_pref_cfg_4 register ****/
-/*
- * Used as a threshold for generating almost FULL indication to the application
- */
-#define UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK 0x000000FF
-#define UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_SHIFT 0
-
-/**** data_cfg_1 register ****/
-/*
- * Maximum number of data beats in the data write FIFO.
- * Defined based on data FIFO size
- * (default FIFO size 512B → 32 beats)
- */
-#define UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_MASK 0x000003FF
-#define UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_SHIFT 0
-/*
- * Maximum number of packets in the data write FIFO.
- * Defined based on header FIFO size
- */
-#define UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_MASK 0x00FF0000
-#define UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_SHIFT 16
-/*
- * Internal use
- * Data FIFO margin
- */
-#define UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_MASK 0xFF000000
-#define UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_SHIFT 24
-
-/**** data_cfg_2 register ****/
-/*
- * Drop timer.
- * Waiting time for the host to write new descriptor to the queue
- * (for the current packet in process)
- */
-#define UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK 0x00FFFFFF
-#define UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_SHIFT 0
-/*
- * Drop enable.
- * Enable packet drop if there are no available descriptors in the system for
- * this queue
- */
-#define UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC (1 << 27)
-/*
- * Lack of descriptors hint.
- * Generate interrupt when a packet is waiting but there are no available
- * descriptors in the queue
- */
-#define UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC (1 << 28)
-/*
- * Drop conditions
- * Wait until a descriptor is available in the prefetch FIFO or the host before
- * dropping packet.
- * 1 - Drop if a descriptor is not available in the prefetch.
- * 0 - Drop if a descriptor is not available in the system
- */
-#define UDMA_S2M_WR_DATA_CFG_2_WAIT_FOR_PREF (1 << 29)
-/*
- * DRAM write optimization
- * 0 - Data write with byte enable
- * 1 - Data write is always in Full AXI bus width (128 bit)
- */
-#define UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE (1 << 30)
-/*
- * Direct data write address
- * 1 - Use buffer 1 instead of buffer 2 when direct data placement is used with
- * header split.
- * 0 - Use buffer 2 for the header.
- */
-#define UDMA_S2M_WR_DATA_CFG_2_DIRECT_HDR_USE_BUF1 (1 << 31)
-
-/**** cfg_1c register ****/
-/*
- * Completion descriptor size.
- * (words)
- */
-#define UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK 0x0000000F
-#define UDMA_S2M_COMP_CFG_1C_DESC_SIZE_SHIFT 0
-/*
- * Completion queue counter configuration.
- * Completion FIFO in use counter measured in words or descriptors
- * 1 - Words
- * 0 - Descriptors
- */
-#define UDMA_S2M_COMP_CFG_1C_CNT_WORDS (1 << 8)
-/*
- * Enable promotion of the current queue in progress in the completion write
- * scheduler.
- */
-#define UDMA_S2M_COMP_CFG_1C_Q_PROMOTION (1 << 12)
-/* Force RR arbitration in the completion arbiter */
-#define UDMA_S2M_COMP_CFG_1C_FORCE_RR (1 << 16)
-/* Minimum number of free completion entries to qualify for promotion */
-#define UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_MASK 0xF0000000
-#define UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_SHIFT 28
-
-/**** cfg_2c register ****/
-/*
- * Completion FIFO size.
- * (words per queue)
- */
-#define UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_MASK 0x00000FFF
-#define UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_SHIFT 0
-/*
- * Unacknowledged FIFO size.
- * (descriptors)
- */
-#define UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_MASK 0x0FFF0000
-#define UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_SHIFT 16
-
-/**** reg_1 register ****/
-/*
- * Descriptor prefetch FIFO size
- * (descriptors)
- */
-#define UDMA_S2M_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_MASK 0x000000FF
-#define UDMA_S2M_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_SHIFT 0
-
-/**** reg_3 register ****/
-/*
- * Maximum number of data beats in the data write FIFO.
- * Defined based on data FIFO size
- * (default FIFO size 512B →32 beats)
- */
-#define UDMA_S2M_FEATURE_REG_3_DATA_FIFO_DEPTH_MASK 0x000003FF
-#define UDMA_S2M_FEATURE_REG_3_DATA_FIFO_DEPTH_SHIFT 0
-/*
- * Maximum number of packets in the data write FIFO.
- * Defined based on header FIFO size
- */
-#define UDMA_S2M_FEATURE_REG_3_DATA_WR_MAX_PKT_LIMIT_MASK 0x00FF0000
-#define UDMA_S2M_FEATURE_REG_3_DATA_WR_MAX_PKT_LIMIT_SHIFT 16
-
-/**** reg_4 register ****/
-/*
- * Completion FIFO size.
- * (words per queue)
- */
-#define UDMA_S2M_FEATURE_REG_4_COMP_FIFO_DEPTH_MASK 0x00000FFF
-#define UDMA_S2M_FEATURE_REG_4_COMP_FIFO_DEPTH_SHIFT 0
-/*
- * Unacknowledged FIFO size.
- * (descriptors)
- */
-#define UDMA_S2M_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_MASK 0x0FFF0000
-#define UDMA_S2M_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_SHIFT 16
-
-/**** reg_5 register ****/
-/* Maximum number of outstanding data writes to the AXI */
-#define UDMA_S2M_FEATURE_REG_5_MAX_DATA_WR_OSTAND_MASK 0x0000003F
-#define UDMA_S2M_FEATURE_REG_5_MAX_DATA_WR_OSTAND_SHIFT 0
-/*
- * Maximum number of outstanding data beats for data write to AXI.
- * (AXI beats)
- */
-#define UDMA_S2M_FEATURE_REG_5_MAX_DATA_BEATS_WR_OSTAND_MASK 0x0000FF00
-#define UDMA_S2M_FEATURE_REG_5_MAX_DATA_BEATS_WR_OSTAND_SHIFT 8
-/*
- * Maximum number of outstanding descriptor reads to the AXI.
- * (AXI transactions)
- */
-#define UDMA_S2M_FEATURE_REG_5_MAX_COMP_REQ_MASK 0x003F0000
-#define UDMA_S2M_FEATURE_REG_5_MAX_COMP_REQ_SHIFT 16
-/*
- * Maximum number of outstanding data beats for descriptor write to AXI.
- * (AXI beats)
- */
-#define UDMA_S2M_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000
-#define UDMA_S2M_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_SHIFT 24
-
-/**** reg_6 register ****/
-/* Maximum number of outstanding descriptor reads to the AXI */
-#define UDMA_S2M_FEATURE_REG_6_MAX_DESC_RD_OSTAND_MASK 0x0000003F
-#define UDMA_S2M_FEATURE_REG_6_MAX_DESC_RD_OSTAND_SHIFT 0
-/* Maximum number of outstanding stream acknowledges */
-#define UDMA_S2M_FEATURE_REG_6_MAX_STREAM_ACK_MASK 0x001F0000
-#define UDMA_S2M_FEATURE_REG_6_MAX_STREAM_ACK_SHIFT 16
-
-/**** cfg register ****/
-/*
- * Configure the AXI AWCACHE
- * for header write.
- */
-#define UDMA_S2M_Q_CFG_AXI_AWCACHE_HDR_MASK 0x0000000F
-#define UDMA_S2M_Q_CFG_AXI_AWCACHE_HDR_SHIFT 0
-/*
- * Configure the AXI AWCACHE
- * for data write.
- */
-#define UDMA_S2M_Q_CFG_AXI_AWCACHE_DATA_MASK 0x000000F0
-#define UDMA_S2M_Q_CFG_AXI_AWCACHE_DATA_SHIFT 4
-/*
- * Enable operation of this queue.
- * Start prefetch.
- */
-#define UDMA_S2M_Q_CFG_EN_PREF       (1 << 16)
-/* Enables the reception of packets from the stream to this queue */
-#define UDMA_S2M_Q_CFG_EN_STREAM     (1 << 17)
-/* Allow prefetch of less than minimum prefetch burst size. */
-#define UDMA_S2M_Q_CFG_ALLOW_LT_MIN_PREF (1 << 20)
-/*
- * Configure the AXI AWCACHE
- * for completion descriptor write
- */
-#define UDMA_S2M_Q_CFG_AXI_AWCACHE_COMP_MASK 0x0F000000
-#define UDMA_S2M_Q_CFG_AXI_AWCACHE_COMP_SHIFT 24
-/*
- * AXI QoS
- * This value is used in AXI transactions associated with this queue and the
- * prefetch and completion arbiters.
- */
-#define UDMA_S2M_Q_CFG_AXI_QOS_MASK  0x70000000
-#define UDMA_S2M_Q_CFG_AXI_QOS_SHIFT 28
-
-/**** status register ****/
-/* Indicates how many entries are used in the Queue */
-#define UDMA_S2M_Q_STATUS_Q_USED_MASK 0x01FFFFFF
-#define UDMA_S2M_Q_STATUS_Q_USED_SHIFT 0
-/*
- * prefetch status
- * 0 – prefetch operation is stopped
- * 1 – prefetch is operational
- */
-#define UDMA_S2M_Q_STATUS_PREFETCH   (1 << 28)
-/*
- * Queue receive status
- * 0 -queue RX operation is stopped
- * 1 – RX queue is active and processing packets
- */
-#define UDMA_S2M_Q_STATUS_RX         (1 << 29)
-/*
- * Indicates if the queue is full.
- * (Used by the host when head pointer equals tail pointer)
- */
-#define UDMA_S2M_Q_STATUS_Q_FULL     (1 << 31)
-/*
- * S2M Descriptor Ring Base address [31:4].
- * Value of the base address of the S2M descriptor ring
- * [3:0] - 0 - 16B alignment is enforced
- * ([11:4] should be 0 for 4KB alignment)
- */
-#define UDMA_S2M_Q_RDRBP_LOW_ADDR_MASK 0xFFFFFFF0
-#define UDMA_S2M_Q_RDRBP_LOW_ADDR_SHIFT 4
-
-/**** RDRL register ****/
-/*
- * Length of the descriptor ring.
- * (descriptors)
- * Associated with the ring base address ends at maximum burst size alignment
- */
-#define UDMA_S2M_Q_RDRL_OFFSET_MASK  0x00FFFFFF
-#define UDMA_S2M_Q_RDRL_OFFSET_SHIFT 0
-
-/**** RDRHP register ****/
-/*
- * Relative offset of the next descriptor that needs to be read into the
- * prefetch FIFO.
- * Incremented when the DMA reads valid descriptors from the host memory to the
- * prefetch FIFO.
- * Note that this is the offset in # of descriptors and not in byte address.
- */
-#define UDMA_S2M_Q_RDRHP_OFFSET_MASK 0x00FFFFFF
-#define UDMA_S2M_Q_RDRHP_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_S2M_Q_RDRHP_RING_ID_MASK 0xC0000000
-#define UDMA_S2M_Q_RDRHP_RING_ID_SHIFT 30
-
-/**** RDRTP_inc register ****/
-/*
- * Increments the value in Q_RDRTP with the value written to this field in
- * number of descriptors.
- */
-#define UDMA_S2M_Q_RDRTP_INC_VAL_MASK 0x00FFFFFF
-#define UDMA_S2M_Q_RDRTP_INC_VAL_SHIFT 0
-
-/**** RDRTP register ****/
-/*
- * Relative offset of the next free descriptor in the host memory.
- * Note that this is the offset in # of descriptors and not in byte address.
- */
-#define UDMA_S2M_Q_RDRTP_OFFSET_MASK 0x00FFFFFF
-#define UDMA_S2M_Q_RDRTP_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_S2M_Q_RDRTP_RING_ID_MASK 0xC0000000
-#define UDMA_S2M_Q_RDRTP_RING_ID_SHIFT 30
-
-/**** RDCP register ****/
-/* Relative offset of the first descriptor in the prefetch FIFO.  */
-#define UDMA_S2M_Q_RDCP_OFFSET_MASK  0x00FFFFFF
-#define UDMA_S2M_Q_RDCP_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_S2M_Q_RDCP_RING_ID_MASK 0xC0000000
-#define UDMA_S2M_Q_RDCP_RING_ID_SHIFT 30
-/*
- * S2M Descriptor Ring Base address [31:4].
- * Value of the base address of the S2M descriptor ring
- * [3:0] - 0 - 16B alignment is enforced
- * ([11:4] Must be 0 for 4KB alignment)
- * NOTE:
- * Length of the descriptor ring (in descriptors) associated with the ring base
- * address ends at maximum burst size alignment
- */
-#define UDMA_S2M_Q_RCRBP_LOW_ADDR_MASK 0xFFFFFFF0
-#define UDMA_S2M_Q_RCRBP_LOW_ADDR_SHIFT 4
-
-/**** RCRHP register ****/
-/*
- * Relative offset of the next descriptor that needs to be updated by the
- * completion controller.
- * Note: This is in descriptors and not in byte address.
- */
-#define UDMA_S2M_Q_RCRHP_OFFSET_MASK 0x00FFFFFF
-#define UDMA_S2M_Q_RCRHP_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_S2M_Q_RCRHP_RING_ID_MASK 0xC0000000
-#define UDMA_S2M_Q_RCRHP_RING_ID_SHIFT 30
-
-/**** RCRHP_internal register ****/
-/*
- * Relative offset of the next descriptor that needs to be updated by the
- * completion controller.
- * Note: This is in descriptors and not in byte address.
- */
-#define UDMA_S2M_Q_RCRHP_INTERNAL_OFFSET_MASK 0x00FFFFFF
-#define UDMA_S2M_Q_RCRHP_INTERNAL_OFFSET_SHIFT 0
-/* Ring ID */
-#define UDMA_S2M_Q_RCRHP_INTERNAL_RING_ID_MASK 0xC0000000
-#define UDMA_S2M_Q_RCRHP_INTERNAL_RING_ID_SHIFT 30
-
-/**** comp_cfg register ****/
-/* Enables writing to the completion ring. */
-#define UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE (1 << 0)
-/* Disables the completion coalescing function. */
-#define UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL (1 << 1)
-/* Reserved */
-#define UDMA_S2M_Q_COMP_CFG_FIRST_PKT_PROMOTION (1 << 2)
-/*
- * Buffer 2 location.
- * Determines the position of the buffer 2 length in the S2M completion
- * descriptor.
- * 0 - WORD 1 [31:16]
- * 1 - WORD 2 [31:16]
- */
-#define UDMA_S2M_Q_COMP_CFG_BUF2_LEN_LOCATION (1 << 3)
-
-/**** pkt_cfg register ****/
-/* Header size. (bytes) */
-#define UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK 0x0000FFFF
-#define UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_SHIFT 0
-/* Force header split */
-#define UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT (1 << 16)
-/* Enable header split. */
-#define UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT (1 << 17)
-
-/**** qos_cfg register ****/
-/* Queue QoS */
-#define UDMA_S2M_QOS_CFG_Q_QOS_MASK 0x000000FF
-#define UDMA_S2M_QOS_CFG_Q_QOS_SHIFT 0
-/* Reset the tail pointer hardware. */
-#define UDMA_S2M_Q_SW_CTRL_RST_TAIL_PTR (1 << 1)
-/* Reset the head pointer hardware. */
-#define UDMA_S2M_Q_SW_CTRL_RST_HEAD_PTR (1 << 2)
-/* Reset the current pointer hardware. */
-#define UDMA_S2M_Q_SW_CTRL_RST_CURRENT_PTR (1 << 3)
-/* Reset the prefetch FIFO */
-#define UDMA_S2M_Q_SW_CTRL_RST_PREFETCH (1 << 4)
-/* Reset the queue */
-#define UDMA_S2M_Q_SW_CTRL_RST_Q   (1 << 8)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_UDMA_S2M_REG_H */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_unit_adapter_regs.h b/sys/contrib/alpine-hal/eth/al_hal_unit_adapter_regs.h
deleted file mode 100644
index 740b959ab43e..000000000000
--- a/sys/contrib/alpine-hal/eth/al_hal_unit_adapter_regs.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/*-
-********************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#ifndef __AL_HAL_UNIT_ADAPTER_REGS_H__
-#define __AL_HAL_UNIT_ADAPTER_REGS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define AL_PCI_COMMAND		0x04	/* 16 bits */
-#define  AL_PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
-#define  AL_PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
-#define  AL_PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
-
-#define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8 revision */
-
-#define  AL_PCI_BASE_ADDRESS_SPACE_IO        0x01
-#define  AL_PCI_BASE_ADDRESS_MEM_TYPE_64     0x04    /* 64 bit address */
-#define  AL_PCI_BASE_ADDRESS_MEM_PREFETCH    0x08    /* prefetchable? */
-#define  AL_PCI_BASE_ADDRESS_DEVICE_ID	     0x0c
-
-#define  AL_PCI_BASE_ADDRESS_0			0x10
-#define  AL_PCI_BASE_ADDRESS_0_HI		0x14
-#define  AL_PCI_BASE_ADDRESS_2			0x18
-#define  AL_PCI_BASE_ADDRESS_2_HI		0x1c
-#define  AL_PCI_BASE_ADDRESS_4			0x20
-#define  AL_PCI_BASE_ADDRESS_4_HI		0x24
-
-#define	AL_PCI_EXP_ROM_BASE_ADDRESS		0x30
-
-#define  AL_PCI_AXI_CFG_AND_CTR_0           0x110
-#define  AL_PCI_AXI_CFG_AND_CTR_1           0x130
-#define  AL_PCI_AXI_CFG_AND_CTR_2           0x150
-#define  AL_PCI_AXI_CFG_AND_CTR_3           0x170
-
-#define  AL_PCI_APP_CONTROL                 0x220
-
-#define  AL_PCI_SRIOV_TOTAL_AND_INITIAL_VFS 0x30c
-
-#define  AL_PCI_VF_BASE_ADDRESS_0           0x324
-
-
-#define AL_PCI_EXP_CAP_BASE	0x40
-#define AL_PCI_EXP_DEVCAP          4       /* Device capabilities */
-#define  AL_PCI_EXP_DEVCAP_PAYLOAD 0x07    /* Max_Payload_Size */
-#define  AL_PCI_EXP_DEVCAP_PHANTOM 0x18    /* Phantom functions */
-#define  AL_PCI_EXP_DEVCAP_EXT_TAG 0x20    /* Extended tags */
-#define  AL_PCI_EXP_DEVCAP_L0S     0x1c0   /* L0s Acceptable Latency */
-#define  AL_PCI_EXP_DEVCAP_L1      0xe00   /* L1 Acceptable Latency */
-#define  AL_PCI_EXP_DEVCAP_ATN_BUT 0x1000  /* Attention Button Present */
-#define  AL_PCI_EXP_DEVCAP_ATN_IND 0x2000  /* Attention Indicator Present */
-#define  AL_PCI_EXP_DEVCAP_PWR_IND 0x4000  /* Power Indicator Present */
-#define  AL_PCI_EXP_DEVCAP_RBER    0x8000  /* Role-Based Error Reporting */
-#define  AL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
-#define  AL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
-#define  AL_PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
-#define AL_PCI_EXP_DEVCTL          8       /* Device Control */
-#define  AL_PCI_EXP_DEVCTL_CERE    0x0001  /* Correctable Error Reporting En. */
-#define  AL_PCI_EXP_DEVCTL_NFERE   0x0002  /* Non-Fatal Error Reporting Enable */
-#define  AL_PCI_EXP_DEVCTL_FERE    0x0004  /* Fatal Error Reporting Enable */
-#define  AL_PCI_EXP_DEVCTL_URRE    0x0008  /* Unsupported Request Reporting En. */
-#define  AL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
-#define  AL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0  /* Max_Payload_Size */
-#define  AL_PCI_EXP_DEVCTL_EXT_TAG 0x0100  /* Extended Tag Field Enable */
-#define  AL_PCI_EXP_DEVCTL_PHANTOM 0x0200  /* Phantom Functions Enable */
-#define  AL_PCI_EXP_DEVCTL_AUX_PME 0x0400  /* Auxiliary Power PM Enable */
-#define  AL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
-#define  AL_PCI_EXP_DEVCTL_READRQ  0x7000  /* Max_Read_Request_Size */
-#define  AL_PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
-#define AL_PCI_EXP_DEVSTA          0xA      /* Device Status */
-#define  AL_PCI_EXP_DEVSTA_CED     0x01    /* Correctable Error Detected */
-#define  AL_PCI_EXP_DEVSTA_NFED    0x02    /* Non-Fatal Error Detected */
-#define  AL_PCI_EXP_DEVSTA_FED     0x04    /* Fatal Error Detected */
-#define  AL_PCI_EXP_DEVSTA_URD     0x08    /* Unsupported Request Detected */
-#define  AL_PCI_EXP_DEVSTA_AUXPD   0x10    /* AUX Power Detected */
-#define  AL_PCI_EXP_DEVSTA_TRPND   0x20    /* Transactions Pending */
-#define AL_PCI_EXP_LNKCAP	   0xC	   /* Link Capabilities */
-#define  AL_PCI_EXP_LNKCAP_SLS	   0xf	   /* Supported Link Speeds */
-#define  AL_PCI_EXP_LNKCAP_SLS_2_5GB 0x1   /* LNKCAP2 SLS Vector bit 0 (2.5GT/s) */
-#define  AL_PCI_EXP_LNKCAP_SLS_5_0GB 0x2   /* LNKCAP2 SLS Vector bit 1 (5.0GT/s) */
-#define  AL_PCI_EXP_LNKCAP_MLW	   0x3f0   /* Maximum Link Width */
-#define  AL_PCI_EXP_LNKCAP_ASPMS   0xc00   /* ASPM Support */
-#define  AL_PCI_EXP_LNKCAP_L0SEL   0x7000  /* L0s Exit Latency */
-#define  AL_PCI_EXP_LNKCAP_L1EL	   0x38000 /* L1 Exit Latency */
-#define  AL_PCI_EXP_LNKCAP_CLKPM   0x40000 /* L1 Clock Power Management */
-#define  AL_PCI_EXP_LNKCAP_SDERC   0x80000 /* Surprise Down Error Reporting Capable */
-#define  AL_PCI_EXP_LNKCAP_DLLLARC 0x100000 /* Data Link Layer Link Active Reporting Capable */
-#define  AL_PCI_EXP_LNKCAP_LBNC	   0x200000 /* Link Bandwidth Notification Capability */
-#define  AL_PCI_EXP_LNKCAP_PN	   0xff000000 /* Port Number */
-
-#define AL_PCI_EXP_LNKCTL          0x10      /* Link Control */
-#define AL_PCI_EXP_LNKCTL_LNK_DIS  0x4       /* Link Disable Status */
-#define AL_PCI_EXP_LNKCTL_LNK_RTRN 0x5       /* Link Retrain Status */
-
-#define AL_PCI_EXP_LNKSTA            0x12      /* Link Status */
-#define  AL_PCI_EXP_LNKSTA_CLS       0x000f  /* Current Link Speed */
-#define  AL_PCI_EXP_LNKSTA_CLS_2_5GB 0x01    /* Current Link Speed 2.5GT/s */
-#define  AL_PCI_EXP_LNKSTA_CLS_5_0GB 0x02    /* Current Link Speed 5.0GT/s */
-#define  AL_PCI_EXP_LNKSTA_CLS_8_0GB 0x03    /* Current Link Speed 8.0GT/s */
-#define  AL_PCI_EXP_LNKSTA_NLW       0x03f0  /* Nogotiated Link Width */
-#define  AL_PCI_EXP_LNKSTA_NLW_SHIFT 4       /* start of NLW mask in link status */
-#define  AL_PCI_EXP_LNKSTA_LT        0x0800  /* Link Training */
-#define  AL_PCI_EXP_LNKSTA_SLC       0x1000  /* Slot Clock Configuration */
-#define  AL_PCI_EXP_LNKSTA_DLLLA     0x2000  /* Data Link Layer Link Active */
-#define  AL_PCI_EXP_LNKSTA_LBMS      0x4000  /* Link Bandwidth Management Status */
-#define  AL_PCI_EXP_LNKSTA_LABS      0x8000  /* Link Autonomous Bandwidth Status */
-
-#define AL_PCI_EXP_LNKCTL2           0x30      /* Link Control 2 */
-
-#define AL_PCI_MSIX_MSGCTRL                 0            /* MSIX message control reg */
-#define AL_PCI_MSIX_MSGCTRL_TBL_SIZE        0x7ff        /* MSIX table size */
-#define AL_PCI_MSIX_MSGCTRL_TBL_SIZE_SHIFT  16           /* MSIX table size shift */
-#define AL_PCI_MSIX_MSGCTRL_EN              0x80000000   /* MSIX enable */
-#define AL_PCI_MSIX_MSGCTRL_MASK            0x40000000   /* MSIX mask */
-
-#define AL_PCI_MSIX_TABLE            0x4          /* MSIX table offset and bar reg */
-#define AL_PCI_MSIX_TABLE_OFFSET     0xfffffff8   /* MSIX table offset */
-#define AL_PCI_MSIX_TABLE_BAR        0x7          /* MSIX table BAR */
-
-#define AL_PCI_MSIX_PBA              0x8          /* MSIX pba offset and bar reg */
-#define AL_PCI_MSIX_PBA_OFFSET       0xfffffff8   /* MSIX pba offset */
-#define AL_PCI_MSIX_PBA_BAR          0x7          /* MSIX pba BAR */
-
-
-/* Adapter power management register 0 */
-#define AL_ADAPTER_PM_0				0x80
-#define  AL_ADAPTER_PM_0_PM_NEXT_CAP_MASK	0xff00
-#define  AL_ADAPTER_PM_0_PM_NEXT_CAP_SHIFT	8
-#define  AL_ADAPTER_PM_0_PM_NEXT_CAP_VAL_MSIX	0x90
-
-/* Adapter power management register 1 */
-#define AL_ADAPTER_PM_1			0x84
-#define  AL_ADAPTER_PM_1_PME_EN		0x100	/* PM enable */
-#define  AL_ADAPTER_PM_1_PWR_STATE_MASK	0x3	/* PM state mask */
-#define  AL_ADAPTER_PM_1_PWR_STATE_D3	0x3	/* PM D3 state */
-
-/* Sub Master Configuration & Control */
-#define AL_ADAPTER_SMCC				0x110
-#define AL_ADAPTER_SMCC_CONF_2		0x114
-
-/* Interrupt_Cause register */
-#define AL_ADAPTER_INT_CAUSE			0x1B0
-#define AL_ADAPTER_INT_CAUSE_WR_ERR		AL_BIT(1)
-#define AL_ADAPTER_INT_CAUSE_RD_ERR		AL_BIT(0)
-
-/* AXI_Master_Write_Error_Attribute_Latch register */
-/* AXI_Master_Read_Error_Attribute_Latch register */
-#define AL_ADAPTER_AXI_MSTR_WR_ERR_ATTR			0x1B4
-#define AL_ADAPTER_AXI_MSTR_RD_ERR_ATTR			0x1B8
-
-#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_MASK	AL_FIELD_MASK(1, 0)
-#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_SHIFT	0
-#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_MSTR_ID_MASK		AL_FIELD_MASK(4, 2)
-#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_MSTR_ID_SHIFT	2
-#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_ADDR_TO		AL_BIT(8)
-#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_ERR		AL_BIT(9)
-#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_TO		AL_BIT(10)
-#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_ERR_BLK		AL_BIT(11)
-#define AL_ADAPTER_AXI_MSTR_RD_ERR_ATTR_RD_PARITY_ERR		AL_BIT(12)
-
-/* Interrupt_Cause_mask register */
-#define AL_ADAPTER_INT_CAUSE_MASK		0x1BC
-#define AL_ADAPTER_INT_CAUSE_MASK_WR_ERR	AL_BIT(1)
-#define AL_ADAPTER_INT_CAUSE_MASK_RD_ERR	AL_BIT(0)
-
-/* AXI_Master_write_error_address_Latch register */
-#define AL_ADAPTER_AXI_MSTR_WR_ERR_LO_LATCH	0x1C0
-
-/* AXI_Master_write_error_address_high_Latch register */
-#define AL_ADAPTER_AXI_MSTR_WR_ERR_HI_LATCH	0x1C4
-
-/* AXI_Master_read_error_address_Latch register */
-#define AL_ADAPTER_AXI_MSTR_RD_ERR_LO_LATCH	0x1C8
-
-/* AXI_Master_read_error_address_high_Latch register */
-#define AL_ADAPTER_AXI_MSTR_RD_ERR_HI_LATCH	0x1CC
-
-/* AXI_Master_Timeout register */
-#define AL_ADAPTER_AXI_MSTR_TO			0x1D0
-#define AL_ADAPTER_AXI_MSTR_TO_WR_MASK		AL_FIELD_MASK(31, 16)
-#define AL_ADAPTER_AXI_MSTR_TO_WR_SHIFT		16
-#define AL_ADAPTER_AXI_MSTR_TO_RD_MASK		AL_FIELD_MASK(15, 0)
-#define AL_ADAPTER_AXI_MSTR_TO_RD_SHIFT		0
-
-/*
- * Generic control registers
- */
-
-/* Control 0 */
-#define AL_ADAPTER_GENERIC_CONTROL_0			0x1E0
-/* Control 2 */
-#define AL_ADAPTER_GENERIC_CONTROL_2			0x1E8
-/* Control 3 */
-#define AL_ADAPTER_GENERIC_CONTROL_3			0x1EC
-/* Control 9 */
-#define AL_ADAPTER_GENERIC_CONTROL_9			0x218
-/* Control 10 */
-#define AL_ADAPTER_GENERIC_CONTROL_10			0x21C
-/* Control 11 */
-#define AL_ADAPTER_GENERIC_CONTROL_11			0x220
-/* Control 12 */
-#define AL_ADAPTER_GENERIC_CONTROL_12			0x224
-/* Control 13 */
-#define AL_ADAPTER_GENERIC_CONTROL_13			0x228
-/* Control 14 */
-#define AL_ADAPTER_GENERIC_CONTROL_14			0x22C
-/* Control 15 */
-#define AL_ADAPTER_GENERIC_CONTROL_15			0x230
-/* Control 16 */
-#define AL_ADAPTER_GENERIC_CONTROL_16			0x234
-/* Control 17 */
-#define AL_ADAPTER_GENERIC_CONTROL_17			0x238
-/* Control 18 */
-#define AL_ADAPTER_GENERIC_CONTROL_18			0x23C
-/* Control 19 */
-#define AL_ADAPTER_GENERIC_CONTROL_19			0x240
-
-/* Enable clock gating */
-#define AL_ADAPTER_GENERIC_CONTROL_0_CLK_GATE_EN	0x01
-/* When set, all transactions through the PCI conf & mem BARs get timeout */
-#define AL_ADAPTER_GENERIC_CONTROL_0_ADAPTER_DIS	0x40
-#define AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC	AL_BIT(18)
-#define AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC_ON_FLR	AL_BIT(26)
-
-/*
- * SATA registers only
- */
-/* Select 125MHz free running clock from IOFAB main PLL as SATA OOB clock
- * instead of using power management ref clock
- */
-#define AL_ADAPTER_GENERIC_CONTROL_10_SATA_OOB_CLK_SEL	AL_BIT(26)
-/* AXUSER selection and value per bit (1 = address, 0 = register) */
-/* Rx */
-#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_MASK	AL_FIELD_MASK(15, 0)
-#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_SHIFT	0
-#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_SEL_MASK	AL_FIELD_MASK(31, 16)
-#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_SEL_SHIFT	16
-/* Tx */
-#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_MASK	AL_FIELD_MASK(15, 0)
-#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_SHIFT	0
-#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_SEL_MASK	AL_FIELD_MASK(31, 16)
-#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_SEL_SHIFT	16
-/* Central VMID enabler. If set, then each entry will be used as programmed */
-#define AL_ADPTR_GEN_CTL_14_SATA_MSIX_VMID_SEL		AL_BIT(0)
-/* Allow access to store VMID values per entry */
-#define AL_ADPTR_GEN_CTL_14_SATA_MSIX_VMID_ACCESS_EN	AL_BIT(1)
-/* VMID Address select */
-/* Tx */
-#define AL_ADPTR_GEN_CTL_14_SATA_VM_ARADDR_SEL_MASK	AL_FIELD_MASK(13, 8)
-#define AL_ADPTR_GEN_CTL_14_SATA_VM_ARADDR_SEL_SHIFT	8
-/* Rx */
-#define AL_ADPTR_GEN_CTL_14_SATA_VM_AWADDR_SEL_MASK	AL_FIELD_MASK(21, 16)
-#define AL_ADPTR_GEN_CTL_14_SATA_VM_AWADDR_SEL_SHIFT	16
-/* Address Value */
-/* Rx */
-#define AL_ADPTR_GEN_CTL_15_SATA_VM_AWDDR_HI	AL_FIELD_MASK(31, 0)
-/* Tx */
-#define AL_ADPTR_GEN_CTL_16_SATA_VM_ARDDR_HI	AL_FIELD_MASK(31, 0)
-
-/*
- * ROB registers
- */
-/* Read ROB_Enable, when disabled the read ROB is bypassed */
-#define AL_ADPTR_GEN_CTL_19_READ_ROB_EN			AL_BIT(0)
-/* Read force in-order of every read transaction */
-#define AL_ADPTR_GEN_CTL_19_READ_ROB_FORCE_INORDER	AL_BIT(1)
-/* Read software reset */
-#define AL_ADPTR_GEN_CTL_19_READ_ROB_SW_RESET		AL_BIT(15)
-/* Write ROB_Enable, when disabled_the_Write ROB is bypassed */
-#define AL_ADPTR_GEN_CTL_19_WRITE_ROB_EN		AL_BIT(16)
-/* Write force in-order of every write transaction */
-#define AL_ADPTR_GEN_CTL_19_WRITE_ROB_FORCE_INORDER	AL_BIT(17)
-/* Write software reset */
-#define AL_ADPTR_GEN_CTL_19_WRITE_ROB_SW_RESET		AL_BIT(31)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/sys/contrib/alpine-hal/eth/al_serdes.c b/sys/contrib/alpine-hal/eth/al_serdes.c
deleted file mode 100644
index 6f9782327568..000000000000
--- a/sys/contrib/alpine-hal/eth/al_serdes.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#include "al_serdes.h"
-#include "al_hal_serdes_hssp.h"
-#include "al_hal_serdes_25g.h"
-
-static int(*handle_init[AL_SRDS_NUM_GROUPS])(void __iomem *, struct al_serdes_grp_obj *) = {
-	al_serdes_hssp_handle_init,
-	al_serdes_hssp_handle_init,
-	al_serdes_hssp_handle_init,
-	al_serdes_hssp_handle_init,
-#if CHECK_ALPINE_V2
-	al_serdes_25g_handle_init,
-#endif
-};
-
-int al_serdes_handle_grp_init(
-	void __iomem			*serdes_regs_base,
-	enum al_serdes_group		grp,
-	struct al_serdes_grp_obj	*obj)
-{
-	handle_init[grp](serdes_regs_base, obj);
-
-	return 0;
-}
-
diff --git a/sys/contrib/alpine-hal/eth/al_serdes.h b/sys/contrib/alpine-hal/eth/al_serdes.h
deleted file mode 100644
index 44e217e7887d..000000000000
--- a/sys/contrib/alpine-hal/eth/al_serdes.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2013 Annapurna Labs Ltd.
-
-This file is licensed under the terms of the Annapurna Labs' Commercial License
-Agreement distributed with the file or available on the software download site.
-Recipient shall use the content of this file only on semiconductor devices or
-systems developed by or for Annapurna Labs.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_serdes_init SerDes Initialization
- * @ingroup group_serdes SerDes
- * @{
- *
- * @file   al_serdes.h
- *
- */
-
-#ifndef __AL_SERDES_H__
-#define __AL_SERDES_H__
-
-#include "al_hal_serdes_interface.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#ifdef AL_DEV_ID
-#define CHECK_ALPINE_V1	(AL_DEV_ID == AL_DEV_ID_ALPINE_V1)
-#define CHECK_ALPINE_V2	(AL_DEV_ID == AL_DEV_ID_ALPINE_V2)
-#else
-#define CHECK_ALPINE_V1	1
-#define CHECK_ALPINE_V2	1
-#endif
-
-enum al_serdes_group {
-	AL_SRDS_GRP_A = 0,
-	AL_SRDS_GRP_B,
-	AL_SRDS_GRP_C,
-	AL_SRDS_GRP_D,
-	AL_SRDS_NUM_HSSP_GROUPS,
-#if CHECK_ALPINE_V2
-	AL_SRDS_GRP_E = AL_SRDS_NUM_HSSP_GROUPS,
-	AL_SRDS_NUM_GROUPS,
-#else
-	AL_SRDS_NUM_GROUPS = AL_SRDS_NUM_HSSP_GROUPS,
-#endif
-};
-
-int al_serdes_handle_grp_init(
-	void __iomem			*serdes_regs_base,
-	enum al_serdes_group		grp,
-	struct al_serdes_grp_obj	*obj);
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-}
-#endif
-
-/* *INDENT-ON* */
-#endif
-
-/** @} end of SERDES group */
-
diff --git a/sys/contrib/alpine-hal/eth/eth/al_hal_an_lt_wrapper_regs.h b/sys/contrib/alpine-hal/eth/eth/al_hal_an_lt_wrapper_regs.h
deleted file mode 100644
index 72b5cc66fb44..000000000000
--- a/sys/contrib/alpine-hal/eth/eth/al_hal_an_lt_wrapper_regs.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-	  this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-	  notice, this list of conditions and the following disclaimer in
-	  the documentation and/or other materials provided with the
-	  distribution.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_an_lt_wrapper_regs.h
- *
- * @brief ... registers
- *
- */
-
-#ifndef __AL_HAL_AN_LT_wrapper_REGS_H__
-#define __AL_HAL_AN_LT_wrapper_REGS_H__
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-
-
-struct al_an_lt_wrapper_gen {
-	/* [0x0] AN LT wrapper Version */
-	uint32_t version;
-	/* [0x4] AN LT general configuration */
-	uint32_t cfg;
-	uint32_t rsrvd[14];
-};
-struct al_an_lt_wrapper_an_lt {
-	/* [0x0] AN LT register file address */
-	uint32_t addr;
-	/* [0x4] PCS register file data */
-	uint32_t data;
-	/* [0x8] AN LT control signals */
-	uint32_t ctrl;
-	/* [0xc] AN LT status signals */
-	uint32_t status;
-	uint32_t rsrvd[4];
-};
-
-enum al_eth_an_lt_unit {
-	AL_ETH_AN_LT_UNIT_32_BIT	= 0,
-	AL_ETH_AN_LT_UNIT_20_BIT	= 1,
-	AL_ETH_AN_LT_UNIT_16_BIT	= 2,
-};
-
-struct al_an_lt_wrapper_regs {
-	uint32_t rsrvd_0[64];
-	struct al_an_lt_wrapper_gen gen;                        /* [0x100] */
-	struct al_an_lt_wrapper_an_lt an_lt[3];                 /* [0x140] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** version register ****/
-/*  Revision number (Minor) */
-#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
-#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
-/*  Revision number (Major) */
-#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
-#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
-/*  Date of release */
-#define AN_LT_WRAPPER_GEN_VERSION_DATE_DAY_MASK 0x001F0000
-#define AN_LT_WRAPPER_GEN_VERSION_DATE_DAY_SHIFT 16
-/*  Month of release */
-#define AN_LT_WRAPPER_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
-#define AN_LT_WRAPPER_GEN_VERSION_DATA_MONTH_SHIFT 21
-/*  Year of release (starting from 2000) */
-#define AN_LT_WRAPPER_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
-#define AN_LT_WRAPPER_GEN_VERSION_DATE_YEAR_SHIFT 25
-/*  Reserved */
-#define AN_LT_WRAPPER_GEN_VERSION_RESERVED_MASK 0xC0000000
-#define AN_LT_WRAPPER_GEN_VERSION_RESERVED_SHIFT 30
-
-/**** cfg register ****/
-/*
- * selection between different bus widths:
- * 0 – 16
- * 1 – 20
- * 2 – 32
- * 3 – N/A
- */
-#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK 0x00000003
-#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT 0
-/*
- * selection between different bus widths:
- * 0 – 16
- * 1 – 20
- * 2 – 32
- * 3 – N/A
- */
-#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK 0x0000000C
-#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT 2
-/* bypass the AN/LT block */
-#define AN_LT_WRAPPER_GEN_CFG_BYPASS_RX  (1 << 4)
-/* bypass the AN/LT block */
-#define AN_LT_WRAPPER_GEN_CFG_BYPASS_TX  (1 << 5)
-
-/**** addr register ****/
-/* Address value */
-#define AN_LT_WRAPPER_AN_LT_ADDR_VAL_MASK 0x000007FF
-#define AN_LT_WRAPPER_AN_LT_ADDR_VAL_SHIFT 0
-
-/**** data register ****/
-/* Data value */
-#define AN_LT_WRAPPER_AN_LT_DATA_VAL_MASK 0x0000FFFF
-#define AN_LT_WRAPPER_AN_LT_DATA_VAL_SHIFT 0
-
-/**** ctrl register ****/
-/*
- * Default Auto-Negotiation Enable. If ‘1’, the auto-negotiation process will
- * start after reset de-assertion. The application can also start the
- * auto-negotiation process by writing the KXAN_CONTROL.an_enable bit with ‘1’.
- * Important: This signal is OR'ed with the KXAN_CONTROL.an_enable bit. Hence,
- * when asserted (1) the application is unable to disable autonegotiation and
- * writing the an_enable bit has no effect.
- * Note: Even if enabled by this pin, the application must write the correct
- * abilities in the KXAN_ABILITY_1/2/3 registers within 60ms from reset
- * deassertion (break_link_timer).
- */
-#define AN_LT_WRAPPER_AN_LT_CTRL_AN_ENA  (1 << 0)
-/*
- * If set to 1, the Arbitration State Machine reached the TRANSMIT_DISABLE
- * state.
- */
-#define AN_LT_WRAPPER_AN_LT_CTRL_AN_DIS_TIMER (1 << 1)
-
-#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS_KX (1 << 4)
-
-#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS_KX4 (1 << 5)
-
-#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS (1 << 6)
-/*
- * PHY LOS indication selection
- * 0 - Select input from the SerDes
- * 1 - Select register value from phy_los_in_def
- */
-#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_SEL (1 << 8)
-/* PHY LOS default value */
-#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_DEF (1 << 9)
-/* PHY LOS polarity */
-#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_POL (1 << 10)
-/*
- * PHY LOS indication selection
- * 0 – select AN output
- * 1 - Select register value from phy_los_out_def
- * 2 - Select input from the SerDes
- * 3 – 0
- */
-#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_SEL_MASK 0x00003000
-#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_SEL_SHIFT 12
-/* PHY LOS default value */
-#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_DEF (1 << 14)
-/* PHY LOS polarity */
-#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_POL (1 << 15)
-
-/**** status register ****/
-/* Auto-Negotiation Done. If ‘1’, the auto-negotiation process has completed. */
-#define AN_LT_WRAPPER_AN_LT_STATUS_AN_DONE (1 << 0)
-/*
- * If set to 1, auto-negotiation is enabled on the link. It represents the
- * enable control bit KXAN_CONTROL.an_enable. When set to 1, the signals
- * an_status/an_select are valid.
- */
-#define AN_LT_WRAPPER_AN_LT_STATUS_AN_VAL (1 << 1)
-/*
- * If set to 0, auto-negotiation is in progress, if set to 1, the Arbitration
- * State Machine reached the AN_GOOD_CHECK state (i.e. before autonegotiation is
- * done, but the link no longer is used to transfer DME pages). Stays asserted
- * also during AN_GOOD (autoneg done).
- */
-#define AN_LT_WRAPPER_AN_LT_STATUS_AN_STATUS (1 << 2)
-/*
- * Selected Technology. Becomes valid when an_status is 1.
- * The selection mode number (from 0 to 24) corresponds to the Technology
- * Ability (A0-A24) from the ability pages (see 4.3.2.3 page 13). The mode
- * selection is based on the matching technology abilities and priority.
- * A value of 31 is an invalid setting that indicates that no common technology
- * could be resolved. The application should then inspect the base page results
- * to determine if the link is operable or not.
- */
-#define AN_LT_WRAPPER_AN_LT_STATUS_AN_SELECT_MASK 0x000001F0
-#define AN_LT_WRAPPER_AN_LT_STATUS_AN_SELECT_SHIFT 4
-/*
- * If set to 1, the Arbitration State Machine reached the TRANSMIT_DISABLE state
- */
-#define AN_LT_WRAPPER_AN_LT_STATUS_AN_TR_DIS_STATUS (1 << 16)
-/*
- * FEC Enable. Asserts when autonegotiation base page exchange identified both
- * link partners advertising FEC capability and at least one is requesting FEC.
- * The signal stays constant following base page exchange until autonegotiation
- * is disabled or restarted.
- * Note: the information can also be extracted from the base page exchange or
- * the BP_ETH_STATUS register.
- */
-#define AN_LT_WRAPPER_AN_LT_STATUS_FEC_ENA (1 << 17)
-/*
- * Link Training Frame Lock. If set to 1 the training frame delineation has been
- * acquired.
- */
-#define AN_LT_WRAPPER_AN_LT_STATUS_LT_LOCK (1 << 20)
-/*
- * If set to 0, link-training is in progress, if set to 1, the training is
- * completed and the PCS datapath has been enabled (phy_los_out no longer
- * gated).
- */
-#define AN_LT_WRAPPER_AN_LT_STATUS_LT_STATUS (1 << 21)
-/*
- * If set to 1, link-training is enabled on the link. It represents the enable
- * control bit PMD Control.taining enable. When set to 1, the signal lt_status
- * is valid
- */
-#define AN_LT_WRAPPER_AN_LT_STATUS_LT_VAL (1 << 22)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_AN_LT_wrapper_REGS_H__ */
-
-/** @} end of ... group */
-
-
diff --git a/sys/contrib/alpine-hal/eth/eth/al_hal_eth.h b/sys/contrib/alpine-hal/eth/eth/al_hal_eth.h
deleted file mode 100644
index 12944d307726..000000000000
--- a/sys/contrib/alpine-hal/eth/eth/al_hal_eth.h
+++ /dev/null
@@ -1,2441 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_eth_api API
- * Ethernet Controller HAL driver API
- * @ingroup group_eth
- * @{
- * @file   al_hal_eth.h
- *
- * @brief Header file for Unified GbE and 10GbE Ethernet Controllers This is a
- * common header file that covers both Standard and Advanced Controller
- *
- *
- */
-
-#ifndef __AL_HAL_ETH_H__
-#define __AL_HAL_ETH_H__
-
-#include "al_hal_common.h"
-#include "al_hal_udma.h"
-#include "al_hal_eth_alu.h"
-#ifdef AL_ETH_EX
-#include "al_hal_eth_ex.h"
-#include "al_hal_eth_ex_internal.h"
-#endif
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-#ifndef AL_ETH_PKT_MAX_BUFS
-#ifndef AL_ETH_EX
-#define AL_ETH_PKT_MAX_BUFS 19
-#else
-#define AL_ETH_PKT_MAX_BUFS 30
-#endif
-#endif
-
-#define AL_ETH_UDMA_TX_QUEUES		4
-#define AL_ETH_UDMA_RX_QUEUES		4
-
-/* PCI Adapter Device/Revision ID */
-#define AL_ETH_DEV_ID_STANDARD		0x0001
-#define AL_ETH_DEV_ID_ADVANCED		0x0002
-#define AL_ETH_REV_ID_0			0 /* Alpine V1 Rev 0 */
-#define AL_ETH_REV_ID_1			1 /* Alpine V1 Rev 1 */
-#define AL_ETH_REV_ID_2			2 /* Alpine V2 basic */
-#define AL_ETH_REV_ID_3			3 /* Alpine V2 advanced */
-
-/* PCI BARs */
-#define AL_ETH_UDMA_BAR			0
-#define AL_ETH_EC_BAR			4
-#define AL_ETH_MAC_BAR			2
-
-#define AL_ETH_MAX_FRAME_LEN		10000
-#define AL_ETH_MIN_FRAME_LEN		60
-
-#define AL_ETH_TSO_MSS_MAX_IDX		8
-#define AL_ETH_TSO_MSS_MIN_VAL		1
-/*TODO: update with correct value*/
-#define AL_ETH_TSO_MSS_MAX_VAL		(AL_ETH_MAX_FRAME_LEN - 200)
-
-enum AL_ETH_PROTO_ID {
-	AL_ETH_PROTO_ID_UNKNOWN = 0,
-	AL_ETH_PROTO_ID_IPv4	= 8,
-	AL_ETH_PROTO_ID_IPv6	= 11,
-	AL_ETH_PROTO_ID_TCP	= 12,
-	AL_ETH_PROTO_ID_UDP	= 13,
-	AL_ETH_PROTO_ID_FCOE    = 21,
-	AL_ETH_PROTO_ID_GRH     = 22, /** RoCE l3 header */
-	AL_ETH_PROTO_ID_BTH     = 23, /** RoCE l4 header */
-	AL_ETH_PROTO_ID_ANY	= 32, /**< for sw usage only */
-};
-#define AL_ETH_PROTOCOLS_NUM		(AL_ETH_PROTO_ID_ANY)
-
-enum AL_ETH_TX_TUNNEL_MODE {
-	AL_ETH_NO_TUNNELING	= 0,
-	AL_ETH_TUNNEL_NO_UDP	= 1, /* NVGRE / IP over IP */
-	AL_ETH_TUNNEL_WITH_UDP	= 3,	/* VXLAN */
-};
-
-#define AL_ETH_RX_THASH_TABLE_SIZE	(1 << 8)
-#define AL_ETH_RX_FSM_TABLE_SIZE	(1 << 7)
-#define AL_ETH_RX_CTRL_TABLE_SIZE	(1 << 11)
-#define AL_ETH_RX_HASH_KEY_NUM		10
-#define AL_ETH_FWD_MAC_NUM			32
-#define AL_ETH_FWD_MAC_HASH_NUM			256
-#define AL_ETH_FWD_PBITS_TABLE_NUM	(1 << 3)
-#define AL_ETH_FWD_PRIO_TABLE_NUM	(1 << 3)
-#define AL_ETH_FWD_VID_TABLE_NUM	(1 << 12)
-#define AL_ETH_FWD_DSCP_TABLE_NUM	(1 << 8)
-#define AL_ETH_FWD_TC_TABLE_NUM	(1 << 8)
-
-/** MAC media mode */
-enum al_eth_mac_mode {
-	AL_ETH_MAC_MODE_RGMII,
-	AL_ETH_MAC_MODE_SGMII,
-	AL_ETH_MAC_MODE_SGMII_2_5G,
-	AL_ETH_MAC_MODE_10GbE_Serial,	/**< Applies to XFI and KR modes */
-	AL_ETH_MAC_MODE_10G_SGMII,	/**< SGMII using the 10G MAC, don't use*/
-	AL_ETH_MAC_MODE_XLG_LL_40G,	/**< applies to 40G mode using the 40G low latency (LL) MAC */
-	AL_ETH_MAC_MODE_KR_LL_25G,	/**< applies to 25G mode using the 10/25G low latency (LL) MAC */
-	AL_ETH_MAC_MODE_XLG_LL_50G,	/**< applies to 50G mode using the 40/50G low latency (LL) MAC */
-	AL_ETH_MAC_MODE_XLG_LL_25G	/**< applies to 25G mode using the 40/50G low latency (LL) MAC */
-};
-
-struct al_eth_capabilities {
-	al_bool	speed_10_HD;
-	al_bool	speed_10_FD;
-	al_bool speed_100_HD;
-	al_bool speed_100_FD;
-	al_bool speed_1000_HD;
-	al_bool speed_1000_FD;
-	al_bool speed_10000_HD;
-	al_bool speed_10000_FD;
-	al_bool pfc; /**< priority flow control */
-	al_bool eee; /**< Energy Efficient Ethernet */
-};
-
-/** interface type used for MDIO */
-enum al_eth_mdio_if {
-	AL_ETH_MDIO_IF_1G_MAC = 0,
-	AL_ETH_MDIO_IF_10G_MAC = 1
-};
-
-/** MDIO protocol type */
-enum al_eth_mdio_type {
-	AL_ETH_MDIO_TYPE_CLAUSE_22 = 0,
-	AL_ETH_MDIO_TYPE_CLAUSE_45 = 1
-};
-
-/** flow control mode */
-enum al_eth_flow_control_type {
-	AL_ETH_FLOW_CONTROL_TYPE_LINK_PAUSE,
-	AL_ETH_FLOW_CONTROL_TYPE_PFC
-};
-
-/** Tx to Rx switching decision type */
-enum al_eth_tx_switch_dec_type {
-	AL_ETH_TX_SWITCH_TYPE_MAC = 0,
-	AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE = 1,
-	AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE_AND_MAC = 2,
-	AL_ETH_TX_SWITCH_TYPE_BITMAP = 3
-};
-
-/** Tx to Rx VLAN ID selection type */
-enum al_eth_tx_switch_vid_sel_type {
-	AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN1 = 0,
-	AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN2 = 1,
-	AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN1 = 2,
-	AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN2 = 3,
-	AL_ETH_TX_SWITCH_VID_SEL_TYPE_DEFAULT_VLAN1 = 4,
-	AL_ETH_TX_SWITCH_VID_SEL_TYPE_FINAL_VLAN1 = 5
-};
-
-/** Rx descriptor configurations */
-/* Note: when selecting rx descriptor field to inner packet, then that field
-* will be set according to inner packet when packet is tunneled, for non-tunneled
-* packets, the field will be set according to the packets header */
-
-/** selection of the LRO_context_value result in the Metadata */
-enum al_eth_rx_desc_lro_context_val_res {
-	AL_ETH_LRO_CONTEXT_VALUE = 0, /**< LRO_context_value */
-	AL_ETH_L4_OFFSET = 1, /**< L4_offset */
-};
-
-/** selection of the L4 offset in the Metadata */
-enum al_eth_rx_desc_l4_offset_sel {
-	AL_ETH_L4_OFFSET_OUTER = 0, /**< set L4 offset of the outer packet */
-	AL_ETH_L4_OFFSET_INNER = 1, /**< set L4 offset of the inner packet */
-};
-
-/** selection of the L4 checksum result in the Metadata */
-enum al_eth_rx_desc_l4_chk_res_sel {
-	AL_ETH_L4_INNER_CHK = 0, /**< L4 checksum */
-	AL_ETH_L4_INNER_OUTER_CHK = 1, /**< Logic AND between outer and inner
-					    L4 checksum result */
-};
-
-/** selection of the L3 checksum result in the Metadata */
-enum al_eth_rx_desc_l3_chk_res_sel {
-	AL_ETH_L3_CHK_TYPE_0 = 0, /**< L3 checksum */
-	AL_ETH_L3_CHK_TYPE_1 = 1, /**< L3 checksum or RoCE/FCoE CRC,
-				       based on outer header */
-	AL_ETH_L3_CHK_TYPE_2 = 2, /**< If tunnel exist = 0,
-					  L3 checksum or RoCE/FCoE CRC,
-					  based on outer header.
-				       Else,
-					  logic AND between outer L3 checksum
-					  (Ipv4) and inner CRC (RoCE or FcoE) */
-	AL_ETH_L3_CHK_TYPE_3 = 3, /**< combination of the L3 checksum result and
-				       CRC result,based on the checksum and
-				       RoCE/FCoE CRC input selections. */
-};
-
-/** selection of the L3 protocol index in the Metadata */
-enum al_eth_rx_desc_l3_proto_idx_sel {
-	AL_ETH_L3_PROTO_IDX_OUTER = 0, /**< set L3 proto index of the outer packet */
-	AL_ETH_L3_PROTO_IDX_INNER = 1, /**< set L3 proto index of the inner packet */
-};
-
-/** selection of the L3 offset in the Metadata */
-enum al_eth_rx_desc_l3_offset_sel {
-	AL_ETH_L3_OFFSET_OUTER = 0, /**< set L3 offset of the outer packet */
-	AL_ETH_L3_OFFSET_INNER = 1, /**< set L3 offset of the inner packet */
-};
-
-
-/** selection of the L4 protocol index in the Metadata */
-enum al_eth_rx_desc_l4_proto_idx_sel {
-	AL_ETH_L4_PROTO_IDX_OUTER = 0, /**< set L4 proto index of the outer packet */
-	AL_ETH_L4_PROTO_IDX_INNER = 1, /**< set L4 proto index of the inner packet */
-};
-
-/** selection of the frag indication in the Metadata */
-enum al_eth_rx_desc_frag_sel {
-	AL_ETH_FRAG_OUTER = 0, /**< set frag of the outer packet */
-	AL_ETH_FRAG_INNER = 1, /**< set frag of the inner packet */
-};
-
-/** Ethernet Rx completion descriptor */
-typedef struct {
-	uint32_t ctrl_meta;
-	uint32_t len;
-	uint32_t word2;
-	uint32_t word3;
-} al_eth_rx_cdesc;
-
-/** Flow Contol parameters */
-struct al_eth_flow_control_params{
-	enum al_eth_flow_control_type type; /**< flow control type */
-	al_bool		obay_enable; /**< stop tx when pause received */
-	al_bool		gen_enable; /**< generate pause frames */
-	uint16_t	rx_fifo_th_high;
-	uint16_t	rx_fifo_th_low;
-	uint16_t	quanta;
-	uint16_t	quanta_th;
-	uint8_t		prio_q_map[4][8]; /**< for each UDMA, defines the mapping between
-					   * PFC priority and queues(in bit mask).
-					   * same mapping used for obay and generation.
-					   * for example:
-					   * if prio_q_map[1][7] = 0xC, then TX queues 2
-					   * and 3 of UDMA 1 will be stopped when pause
-					   * received with priority 7, also, when RX queues
-					   * 2 and 3 of UDMA 1 become almost full, then
-					   * pause frame with priority 7 will be sent.
-					   *
-					   *note:
-					   * 1) if specific a queue is not used, the caller must
-					   * make set the prio_q_map to 0 otherwise that queue
-					   * will make the controller keep sending PAUSE packets.
-					   * 2) queues of unused UDMA must be treated as above.
-					   * 3) when working in LINK PAUSE mode, only entries at
-					   * priority 0 will be considered.
-					   */
-};
-
-/* Packet Tx flags */
-#define AL_ETH_TX_FLAGS_TSO		AL_BIT(7)  /**< Enable TCP/UDP segmentation offloading */
-#define AL_ETH_TX_FLAGS_IPV4_L3_CSUM	AL_BIT(13) /**< Enable IPv4 header checksum calculation */
-#define AL_ETH_TX_FLAGS_L4_CSUM		AL_BIT(14) /**< Enable TCP/UDP checksum calculation */
-#define AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM	AL_BIT(17) /**< L4 partial checksum calculation */
-#define AL_ETH_TX_FLAGS_L2_MACSEC_PKT	AL_BIT(16) /**< L2 Packet type 802_3 or 802_3_MACSEC, V2 */
-#define AL_ETH_TX_FLAGS_ENCRYPT		AL_BIT(16) /**< Enable TX packet encryption, V3 */
-#define AL_ETH_TX_FLAGS_L2_DIS_FCS	AL_BIT(15) /**< Disable CRC calculation*/
-#define AL_ETH_TX_FLAGS_TS		AL_BIT(21) /**< Timestamp the packet */
-
-#define AL_ETH_TX_FLAGS_INT		AL_M2S_DESC_INT_EN
-#define AL_ETH_TX_FLAGS_NO_SNOOP	AL_M2S_DESC_NO_SNOOP_H
-
-/** this structure used for tx packet meta data */
-struct al_eth_meta_data{
-	uint8_t store :1; /**< store the meta into the queues cache */
-	uint8_t words_valid :4; /**< valid bit per word */
-
-	uint8_t vlan1_cfi_sel:2;
-	uint8_t vlan2_vid_sel:2;
-	uint8_t vlan2_cfi_sel:2;
-	uint8_t vlan2_pbits_sel:2;
-	uint8_t vlan2_ether_sel:2;
-
-	uint16_t vlan1_new_vid:12;
-	uint8_t vlan1_new_cfi :1;
-	uint8_t vlan1_new_pbits :3;
-	uint16_t vlan2_new_vid:12;
-	uint8_t vlan2_new_cfi :1;
-	uint8_t vlan2_new_pbits :3;
-
-	uint8_t l3_header_len; /**< in bytes */
-	uint8_t l3_header_offset;
-	uint8_t l4_header_len; /**< in words(32-bits) */
-
-	/* rev 0 specific */
-	uint8_t mss_idx_sel:3; /**< for TSO, select the register that holds the MSS */
-
-	/* rev 1 specific */
-	uint8_t	ts_index:4; /**< index of regiser where to store the tx timestamp */
-	uint16_t mss_val :14; /**< for TSO, set the mss value */
-	uint8_t outer_l3_offset; /**< for tunneling mode. up to 64 bytes */
-	uint8_t outer_l3_len; /**< for tunneling mode. up to 128 bytes */
-};
-
-/* Packet Rx flags when adding buffer to receive queue */
-
-/**<
- * Target-ID to be assigned to the packet descriptors
- * Requires Target-ID in descriptor to be enabled for the specific UDMA
- * queue.
- */
-#define AL_ETH_RX_FLAGS_TGTID_MASK	AL_FIELD_MASK(15, 0)
-#define AL_ETH_RX_FLAGS_NO_SNOOP	AL_M2S_DESC_NO_SNOOP_H
-#define AL_ETH_RX_FLAGS_INT		AL_M2S_DESC_INT_EN
-#define AL_ETH_RX_FLAGS_DUAL_BUF	AL_BIT(31)
-
-/* Packet Rx flags set by HW when receiving packet */
-#define AL_ETH_RX_ERROR			AL_BIT(16) /**< layer 2 errors (FCS, bad len, etc) */
-#define AL_ETH_RX_FLAGS_L4_CSUM_ERR	AL_BIT(14)
-#define AL_ETH_RX_FLAGS_L3_CSUM_ERR	AL_BIT(13)
-
-/* Packet Rx flags - word 3 in Rx completion descriptor */
-#define AL_ETH_RX_FLAGS_CRC						AL_BIT(31)
-#define AL_ETH_RX_FLAGS_L3_CSUM_2				AL_BIT(30)
-#define AL_ETH_RX_FLAGS_L4_CSUM_2				AL_BIT(29)
-#define AL_ETH_RX_FLAGS_SW_SRC_PORT_SHIFT		13
-#define AL_ETH_RX_FLAGS_SW_SRC_PORT_MASK		AL_FIELD_MASK(15, 13)
-#define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_SHIFT	3
-#define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_MASK	AL_FIELD_MASK(10, 3)
-#define AL_ETH_RX_FLAGS_L4_OFFSET_SHIFT			3
-#define AL_ETH_RX_FLAGS_L4_OFFSET_MASK			AL_FIELD_MASK(10, 3)
-#define AL_ETH_RX_FLAGS_PRIORITY_SHIFT			0
-#define AL_ETH_RX_FLAGS_PRIORITY_MASK			AL_FIELD_MASK(2, 0)
-
-/** packet structure. used for packet transmission and reception */
-struct al_eth_pkt{
-	uint32_t flags; /**< see flags above, depends on context(tx or rx) */
-	enum AL_ETH_PROTO_ID l3_proto_idx;
-	enum AL_ETH_PROTO_ID l4_proto_idx;
-	uint8_t source_vlan_count:2;
-	uint8_t vlan_mod_add_count:2;
-	uint8_t vlan_mod_del_count:2;
-	uint8_t vlan_mod_v1_ether_sel:2;
-	uint8_t vlan_mod_v1_vid_sel:2;
-	uint8_t vlan_mod_v1_pbits_sel:2;
-
-	/* rev 1 specific */
-	enum AL_ETH_TX_TUNNEL_MODE tunnel_mode;
-	enum AL_ETH_PROTO_ID outer_l3_proto_idx; /**< for tunneling mode */
-
-	/**<
-	 * Target-ID to be assigned to the packet descriptors
-	 * Requires Target-ID in descriptor to be enabled for the specific UDMA
-	 * queue.
-	 */
-	uint16_t tgtid;
-
-	uint32_t rx_header_len; /**< header buffer length of rx packet, not used */
-	struct al_eth_meta_data *meta; /**< if null, then no meta added */
-#ifdef AL_ETH_RX_DESC_RAW_GET
-	uint32_t rx_desc_raw[4];
-#endif
-	uint16_t rxhash;
-	uint16_t l3_offset;
-
-#ifdef AL_ETH_EX
-	struct al_eth_ext_metadata *ext_meta_data;
-#endif
-
-	uint8_t num_of_bufs;
-	struct al_buf	bufs[AL_ETH_PKT_MAX_BUFS];
-};
-
-struct al_ec_regs;
-
-
-/** Ethernet Adapter private data structure used by this driver */
-struct al_hal_eth_adapter{
-	uint8_t rev_id; /**<PCI adapter revision ID */
-	uint8_t udma_id; /**< the id of the UDMA used by this adapter */
-	struct unit_regs __iomem * unit_regs;
-	void __iomem *udma_regs_base;
-	struct al_ec_regs __iomem *ec_regs_base;
-	void __iomem *ec_ints_base;
-	struct al_eth_mac_regs __iomem *mac_regs_base;
-	struct interrupt_controller_ctrl __iomem *mac_ints_base;
-
-	char *name; /**< the upper layer must keep the string area */
-
-	struct al_udma tx_udma;
-	/*	uint8_t tx_queues;*//* number of tx queues */
-	struct al_udma rx_udma;
-	/*	uint8_t rx_queues;*//* number of tx queues */
-
-	uint8_t		enable_rx_parser; /**< config and enable rx parsing */
-
-	enum al_eth_flow_control_type fc_type; /**< flow control*/
-
-	enum al_eth_mac_mode mac_mode;
-	enum al_eth_mdio_if	mdio_if; /**< which mac mdio interface to use */
-	enum al_eth_mdio_type mdio_type; /**< mdio protocol type */
-	al_bool	shared_mdio_if; /**< when AL_TRUE, the mdio interface is shared with other controllers.*/
-	uint8_t curr_lt_unit;
-	uint8_t serdes_lane;
-#ifdef AL_ETH_EX
-	struct al_eth_ex_state ex_state;
-#endif
-};
-
-/** parameters from upper layer */
-struct al_eth_adapter_params{
-	uint8_t rev_id; /**<PCI adapter revision ID */
-	uint8_t udma_id; /**< the id of the UDMA used by this adapter */
-	uint8_t	enable_rx_parser; /**< when true, the rx epe parser will be enabled */
-	void __iomem *udma_regs_base; /**< UDMA register base address */
-	void __iomem *ec_regs_base; /**< Ethernet controller registers base address
-				     * can be null if the function is virtual
-				     */
-	void __iomem *mac_regs_base; /**< Ethernet MAC registers base address
-				      * can be null if the function is virtual
-				      */
-	char *name; /**< the upper layer must keep the string area */
-
-	uint8_t serdes_lane; /**< serdes lane (relevant to 25G macs only) */
-};
-
-/* adapter management */
-/**
- * initialize the ethernet adapter's DMA
- * - initialize the adapter data structure
- * - initialize the Tx and Rx UDMA
- * - enable the Tx and Rx UDMA, the rings will be still disabled at this point.
- *
- * @param adapter pointer to the private structure
- * @param params the parameters passed from upper layer
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_adapter_init(struct al_hal_eth_adapter *adapter, struct al_eth_adapter_params *params);
-
-/**
- * stop the DMA of the ethernet adapter
- *
- * @param adapter pointer to the private structure
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_adapter_stop(struct al_hal_eth_adapter *adapter);
-
-int al_eth_adapter_reset(struct al_hal_eth_adapter *adapter);
-
-/**
- * enable the ec and mac interrupts
- *
- * @param adapter pointer to the private structure
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_ec_mac_ints_config(struct al_hal_eth_adapter *adapter);
-
-/**
- * ec and mac interrupt service routine
- * read and print asserted interrupts
- *
- * @param adapter pointer to the private structure
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_ec_mac_isr(struct al_hal_eth_adapter *adapter);
-
-/* Q management */
-/**
- * Configure and enable a queue ring
- *
- * @param adapter pointer to the private structure
- * @param type tx or rx
- * @param qid queue index
- * @param q_params queue parameters
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_queue_config(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid,
-			struct al_udma_q_params *q_params);
-
-
-/**
- * enable a queue if it was previously disabled
- *
- * @param adapter pointer to the private structure
- * @param type tx or rx
- * @param qid queue index
- *
- * @return -EPERM (not implemented yet).
- */
-int al_eth_queue_enable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid);
-
-/**
- * disable a queue
- * @param adapter pointer to the private structure
- * @param type tx or rx
- * @param qid queue index
- *
- * @return -EPERM (not implemented yet).
- */
-int al_eth_queue_disable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid);
-
-/* MAC layer */
-
-/**
- * configure the mac media type.
- * this function only sets the mode, but not the speed as certain mac modes
- * support multiple speeds as will be negotiated by the link layer.
- * @param adapter pointer to the private structure.
- * @param mode media mode
- *
- * @return 0 on success. negative errno on failure.
- */
-int al_eth_mac_config(struct al_hal_eth_adapter *adapter, enum al_eth_mac_mode mode);
-
-/**
- * stop the mac tx and rx paths.
- * @param adapter pointer to the private structure.
- *
- * @return 0 on success. negative error on failure.
- */
-int al_eth_mac_stop(struct al_hal_eth_adapter *adapter);
-
-/**
- * start the mac tx and rx paths.
- * @param adapter pointer to the private structure.
- *
- * @return 0 on success. negative error on failure.
- */
-int al_eth_mac_start(struct al_hal_eth_adapter *adapter);
-
-/**
- * Perform gearbox reset for tx lanes And/Or Rx lanes.
- * applicable only when the controller is connected to srds25G.
- * This reset should be performed after each operation that changes the clocks
- * (such as serdes reset, mac stop, etc.)
- *
- * @param adapter pointer to the private structure.
- * @param tx_reset assert and de-assert reset for tx lanes
- * @param rx_reset assert and de-assert reset for rx lanes
- */
-void al_eth_gearbox_reset(struct al_hal_eth_adapter *adapter, al_bool tx_reset, al_bool rx_reset);
-
-/**
- * Enable / Disable forward error correction (FEC)
- *
- * @param adapter pointer to the private structure.
- * @param enable true to enable FEC. false to disable FEC.
- *
- * @return 0 on success. negative error on failure.
- */
-int al_eth_fec_enable(struct al_hal_eth_adapter *adapter, al_bool enable);
-
-/**
- * Get forward error correction (FEC) statistics
- *
- * @param adapter pointer to the private structure.
- * @param corrected number of bits been corrected by the FEC
- * @param uncorrectable number of bits that FEC couldn't correct.
- *
- * @return 0 on success. negative error on failure.
- */
-int al_eth_fec_stats_get(struct al_hal_eth_adapter *adapter,
-			uint32_t *corrected, uint32_t *uncorrectable);
-
-/**
- * get the adapter capabilities (speed, duplex,..)
- * this function must not be called before configuring the mac mode using al_eth_mac_config()
- * @param adapter pointer to the private structure.
- * @param caps pointer to structure that will be updated by this function
- *
- * @return 0 on success. negative errno on failure.
- */
-int al_eth_capabilities_get(struct al_hal_eth_adapter *adapter, struct al_eth_capabilities *caps);
-
-/**
- * update link auto negotiation speed and duplex mode
- * this function assumes the mac mode already set using the al_eth_mac_config()
- * function.
- *
- * @param adapter pointer to the private structure
- * @param force_1000_base_x set to AL_TRUE to force the mac to work on 1000baseX
- *	  (not relevant to RGMII)
- * @param an_enable set to AL_TRUE to enable auto negotiation
- *	  (not relevant to RGMII)
- * @param speed in mega bits, e.g 1000 stands for 1Gbps (relevant only in case
- *	  an_enable is AL_FALSE)
- * @param full_duplex set to AL_TRUE to enable full duplex mode (relevant only
- *	  in case an_enable is AL_FALSE)
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_mac_link_config(struct al_hal_eth_adapter *adapter,
-			   al_bool force_1000_base_x,
-			   al_bool an_enable,
-			   uint32_t speed,
-			   al_bool full_duplex);
-/**
- * Enable/Disable Loopback mode
- *
- * @param adapter pointer to the private structure
- * @param enable set to AL_TRUE to enable full duplex mode
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_mac_loopback_config(struct al_hal_eth_adapter *adapter, int enable);
-
-/**
- * configure minimum and maximum rx packet length
- *
- * @param adapter pointer to the private structure
- * @param min_rx_len minimum rx packet length
- * @param max_rx_len maximum rx packet length
- * both length limits in bytes and it includes the MAC Layer header and FCS.
- * @return 0 on success, otherwise on failure.
- */
-int al_eth_rx_pkt_limit_config(struct al_hal_eth_adapter *adapter, uint32_t min_rx_len, uint32_t max_rx_len);
-
-
-/* MDIO */
-
-/* Reference clock frequency (platform specific) */
-enum al_eth_ref_clk_freq {
-	AL_ETH_REF_FREQ_375_MHZ		= 0,
-	AL_ETH_REF_FREQ_187_5_MHZ	= 1,
-	AL_ETH_REF_FREQ_250_MHZ		= 2,
-	AL_ETH_REF_FREQ_500_MHZ		= 3,
-	AL_ETH_REF_FREQ_428_MHZ         = 4,
-};
-
-/**
- * configure the MDIO hardware interface
- * @param adapter pointer to the private structure
- * @param mdio_type clause type
- * @param shared_mdio_if set to AL_TRUE if multiple controllers using the same
- * @param ref_clk_freq reference clock frequency
- * @param mdio_clk_freq_khz the required MDC/MDIO clock frequency [Khz]
- * MDIO pins of the chip.
- *
- * @return 0 on success, otherwise on failure.
- */
-int al_eth_mdio_config(struct al_hal_eth_adapter *adapter,
-		       enum al_eth_mdio_type mdio_type,
-		       al_bool shared_mdio_if,
-		       enum al_eth_ref_clk_freq ref_clk_freq,
-		       unsigned int mdio_clk_freq_khz);
-
-/**
- * read mdio register
- * this function uses polling mode, and as the mdio is slow interface, it might
- * block the cpu for long time (milliseconds).
- * @param adapter pointer to the private structure
- * @param phy_addr address of mdio phy
- * @param device address of mdio device (used only in CLAUSE 45)
- * @param reg index of the register
- * @param val pointer for read value of the register
- *
- * @return 0 on success, negative errno on failure
- */
-int al_eth_mdio_read(struct al_hal_eth_adapter *adapter, uint32_t phy_addr,
-		     uint32_t device, uint32_t reg, uint16_t *val);
-
-/**
- * write mdio register
- * this function uses polling mode, and as the mdio is slow interface, it might
- * block the cpu for long time (milliseconds).
- * @param adapter pointer to the private structure
- * @param phy_addr address of mdio phy
- * @param device address of mdio device (used only in CLAUSE 45)
- * @param reg index of the register
- * @param val value to write
- *
- * @return 0 on success, negative errno on failure
- */
-int al_eth_mdio_write(struct al_hal_eth_adapter *adapter, uint32_t phy_addr,
-		      uint32_t device, uint32_t reg, uint16_t val);
-
-/* TX */
-/**
- * get number of free tx descriptors
- *
- * @param adapter adapter handle
- * @param qid queue index
- *
- * @return num of free descriptors.
- */
-static INLINE uint32_t al_eth_tx_available_get(struct al_hal_eth_adapter *adapter,
-					       uint32_t qid)
-{
-	struct al_udma_q *udma_q;
-
-	al_udma_q_handle_get(&adapter->tx_udma, qid, &udma_q);
-
-	return al_udma_available_get(udma_q);
-}
-
-/**
- * prepare packet descriptors in tx queue.
- *
- * This functions prepares the descriptors for the given packet in the tx
- * submission ring. the caller must call al_eth_tx_pkt_action() below
- * in order to notify the hardware about the new descriptors.
- *
- * @param tx_dma_q pointer to UDMA tx queue
- * @param pkt the packet to transmit
- *
- * @return number of descriptors used for this packet, 0 if no free
- * room in the descriptors ring
- */
-int al_eth_tx_pkt_prepare(struct al_udma_q *tx_dma_q, struct al_eth_pkt *pkt);
-
-
-/**
- * Trigger the DMA about previously added tx descriptors.
- *
- * @param tx_dma_q pointer to UDMA tx queue
- * @param tx_descs number of descriptors to notify the DMA about.
- * the tx_descs can be sum of descriptor numbers of multiple prepared packets,
- * this way the caller can use this function to notify the DMA about multiple
- * packets.
- */
-void al_eth_tx_dma_action(struct al_udma_q *tx_dma_q, uint32_t tx_descs);
-
-/**
- * get number of completed tx descriptors, upper layer should derive from
- * this information which packets were completed.
- *
- * @param tx_dma_q pointer to UDMA tx queue
- *
- * @return number of completed tx descriptors.
- */
-int al_eth_comp_tx_get(struct al_udma_q *tx_dma_q);
-
-/**
- * configure a TSO MSS val
- *
- * the TSO MSS vals are preconfigured values for MSS stored in hardware and the
- * packet could use them when not working in MSS explicit mode.
- * @param adapter pointer to the private structure
- * @param idx the mss index
- * @param mss_val the MSS value
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_tso_mss_config(struct al_hal_eth_adapter *adapter, uint8_t idx, uint32_t mss_val);
-
-/* RX */
-/**
- * Config the RX descriptor fields
- *
- * @param adapter pointer to the private structure
- * @param lro_sel select LRO context or l4 offset
- * @param l4_offset_sel select l4 offset source
- * @param l4_sel  select the l4 checksum result
- * @param l3_sel  select the l3 checksum result
- * @param l3_proto_sel select the l3 protocol index source
- * @param l4_proto_sel select the l4 protocol index source
- * @param frag_sel select the frag indication source
- */
-void al_eth_rx_desc_config(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_rx_desc_lro_context_val_res lro_sel,
-			enum al_eth_rx_desc_l4_offset_sel l4_offset_sel,
-			enum al_eth_rx_desc_l3_offset_sel l3_offset_sel,
-			enum al_eth_rx_desc_l4_chk_res_sel l4_sel,
-			enum al_eth_rx_desc_l3_chk_res_sel l3_sel,
-			enum al_eth_rx_desc_l3_proto_idx_sel l3_proto_sel,
-			enum al_eth_rx_desc_l4_proto_idx_sel l4_proto_sel,
-			enum al_eth_rx_desc_frag_sel frag_sel);
-
-/**
- * Configure RX header split
- *
- * @param adapter pointer to the private structure
- * @param enable header split when AL_TRUE
- * @param header_split_len length in bytes of the header split, this value used when
- * CTRL TABLE header split len select is set to
- * AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG, in this case the controller will
- * store the first header_split_len bytes into buf2, then the rest (if any) into buf1.
- * when CTRL_TABLE header split len select set to other value, then the header_len
- * determined according to the parser, and the header_split_len parameter is not
- * used.
- *
- * return 0 on success. otherwise on failure.
- */
-int al_eth_rx_header_split_config(struct al_hal_eth_adapter *adapter, al_bool enable, uint32_t header_len);
-
-/**
- * enable / disable header split in the udma queue.
- * length will be taken from the udma configuration to enable different length per queue.
- *
- * @param adapter pointer to the private structure
- * @param enable header split when AL_TRUE
- * @param qid the queue id to enable/disable header split
- * @param header_len in what len the udma will cut the header
- *
- * return 0 on success.
- */
-int al_eth_rx_header_split_force_len_config(struct al_hal_eth_adapter *adapter,
-					al_bool enable,
-					uint32_t qid,
-					uint32_t header_len);
-
-/**
- * add buffer to receive queue
- *
- * @param rx_dma_q pointer to UDMA rx queue
- * @param buf pointer to data buffer
- * @param flags bitwise of AL_ETH_RX_FLAGS
- * @param header_buf this is not used for far and header_buf should be set to
- * NULL.
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_rx_buffer_add(struct al_udma_q *rx_dma_q,
-			      struct al_buf *buf, uint32_t flags,
-			      struct al_buf *header_buf);
-
-/**
- * notify the hw engine about rx descriptors that were added to the receive queue
- *
- * @param rx_dma_q pointer to UDMA rx queue
- * @param descs_num number of rx descriptors
- */
-void al_eth_rx_buffer_action(struct al_udma_q *rx_dma_q,
-				uint32_t descs_num);
-
-/**
- * get packet from RX completion ring
- *
- * @param rx_dma_q pointer to UDMA rx queue
- * @param pkt pointer to a packet data structure, this function fills this
- * structure with the information about the received packet. the buffers
- * structures filled only with the length of the data written into the buffer,
- * the address fields are not updated as the upper layer can retrieve this
- * information by itself because the hardware uses the buffers in the same order
- * were those buffers inserted into the ring of the receive queue.
- * this structure should be allocated by the caller function.
- *
- * @return return number of descriptors or 0 if no completed packet found.
- */
- uint32_t al_eth_pkt_rx(struct al_udma_q *rx_dma_q, struct al_eth_pkt *pkt);
-
-
-/* RX parser table */
-struct al_eth_epe_p_reg_entry {
-	uint32_t data;
-	uint32_t mask;
-	uint32_t ctrl;
-};
-
-struct al_eth_epe_control_entry {
-	uint32_t data[6];
-};
-
-/**
- * update rx parser entry
- *
- * @param adapter pointer to the private structure
- * @param idx the protocol index to update
- * @param reg_entry contents of parser register entry
- * @param control entry contents of control table entry
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_rx_parser_entry_update(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_epe_p_reg_entry *reg_entry,
-		struct al_eth_epe_control_entry *control_entry);
-
-/* Flow Steering and filtering */
-int al_eth_thash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma, uint32_t queue);
-
-/* FSM table bits */
-/** FSM table has 7 bits input address:
- *  bits[2:0] are the outer packet's type (IPv4, TCP...)
- *  bits[5:3] are the inner packet's type
- *  bit[6] is set when packet is tunneled.
- *
- * The output of each entry:
- *  bits[1:0] - input selection: selects the input for the thash (2/4 tuple, inner/outer)
- *  bit[2] - selects whether to use thash output, or default values for the queue and udma
- *  bits[6:3] default UDMA mask: the UDMAs to select when bit 2 above was unset
- *  bits[9:5] defualt queue: the queue index to select when bit 2 above was unset
- */
-
-#define AL_ETH_FSM_ENTRY_IPV4_TCP	   0
-#define AL_ETH_FSM_ENTRY_IPV4_UDP	   1
-#define AL_ETH_FSM_ENTRY_IPV6_TCP	   2
-#define AL_ETH_FSM_ENTRY_IPV6_UDP	   3
-#define AL_ETH_FSM_ENTRY_IPV6_NO_UDP_TCP   4
-#define AL_ETH_FSM_ENTRY_IPV4_NO_UDP_TCP   5
-#define AL_ETH_FSM_ENTRY_IPV4_FRAGMENTED   6
-#define AL_ETH_FSM_ENTRY_NOT_IP		   7
-
-#define AL_ETH_FSM_ENTRY_OUTER(idx)	   ((idx) & 7)
-#define AL_ETH_FSM_ENTRY_INNER(idx)	   (((idx) >> 3) & 7)
-#define AL_ETH_FSM_ENTRY_TUNNELED(idx)	   (((idx) >> 6) & 1)
-
-/* FSM DATA format */
-#define AL_ETH_FSM_DATA_OUTER_2_TUPLE	0
-#define AL_ETH_FSM_DATA_OUTER_4_TUPLE	1
-#define AL_ETH_FSM_DATA_INNER_2_TUPLE	2
-#define AL_ETH_FSM_DATA_INNER_4_TUPLE	3
-
-#define AL_ETH_FSM_DATA_HASH_SEL	(1 << 2)
-
-#define AL_ETH_FSM_DATA_DEFAULT_Q_SHIFT		5
-#define AL_ETH_FSM_DATA_DEFAULT_UDMA_SHIFT	3
-
-/* set fsm table entry */
-int al_eth_fsm_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry);
-
-enum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT {
-	AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_0 = 0,
-	AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_1 = 1,
-	AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_ANY = 2,
-};
-
-enum AL_ETH_FWD_CTRL_IDX_TUNNEL {
-	AL_ETH_FWD_CTRL_IDX_TUNNEL_NOT_EXIST = 0,
-	AL_ETH_FWD_CTRL_IDX_TUNNEL_EXIST = 1,
-	AL_ETH_FWD_CTRL_IDX_TUNNEL_ANY = 2,
-};
-
-enum AL_ETH_FWD_CTRL_IDX_VLAN {
-	AL_ETH_FWD_CTRL_IDX_VLAN_NOT_EXIST = 0,
-	AL_ETH_FWD_CTRL_IDX_VLAN_EXIST = 1,
-	AL_ETH_FWD_CTRL_IDX_VLAN_ANY = 2,
-};
-
-enum AL_ETH_FWD_CTRL_IDX_MAC_TABLE {
-	AL_ETH_FWD_CTRL_IDX_MAC_TABLE_NO_MATCH = 0,
-	AL_ETH_FWD_CTRL_IDX_MAC_TABLE_MATCH = 1,
-	AL_ETH_FWD_CTRL_IDX_MAC_TABLE_ANY = 2,
-};
-
-enum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE {
-	AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_UC = 0, /**< unicast */
-	AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_MC = 1, /**< multicast */
-	AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_BC = 2, /**< broadcast */
-	AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_ANY = 4, /**< for sw usage */
-};
-
-/**
- * This structure defines the index or group of indeces within the control table.
- * each field has special enum value (with _ANY postfix) that indicates all
- * possible values of that field.
- */
-struct al_eth_fwd_ctrl_table_index {
-	enum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT	vlan_table_out;
-	enum AL_ETH_FWD_CTRL_IDX_TUNNEL tunnel_exist;
-	enum AL_ETH_FWD_CTRL_IDX_VLAN vlan_exist;
-	enum AL_ETH_FWD_CTRL_IDX_MAC_TABLE mac_table_match;
-	enum AL_ETH_PROTO_ID		protocol_id;
-	enum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE mac_type;
-};
-
-enum AL_ETH_CTRL_TABLE_PRIO_SEL {
-	AL_ETH_CTRL_TABLE_PRIO_SEL_PBITS_TABLE	= 0,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_DSCP_TABLE	= 1,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_TC_TABLE	= 2,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_REG1		= 3,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_REG2		= 4,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_REG3		= 5,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_REG4		= 6,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_REG5		= 7,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_REG6		= 7,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_REG7		= 9,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_REG8		= 10,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_3	= 11,
-	AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_0	= 12,
-};
-/** where to select the initial queue from */
-enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1 {
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_PRIO_TABLE	= 0,
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_THASH_TABLE	= 1,
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MAC_TABLE		= 2,
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MHASH_TABLE	= 3,
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG1		= 4,
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG2		= 5,
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG3		= 6,
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG4		= 7,
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_3		= 12,
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_0		= 13,
-};
-
-/** target queue will be built up from the priority and initial queue */
-enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2 {
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_TABLE	= 0, /**< target queue is the output of priority table */
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO		= 1, /**< target queue is the priority */
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_QUEUE	= 2, /**< target queue is initial queue[0], priority[1] */
-	AL_ETH_CTRL_TABLE_QUEUE_SEL_2_NO_PRIO		= 3, /**< target queue is the initial */
-};
-
-enum AL_ETH_CTRL_TABLE_UDMA_SEL {
-	AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_TABLE		= 0,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_AND_VLAN	= 1,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_TABLE		= 2,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_AND_MAC		= 3,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_TABLE		= 4,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_AND_MHASH	= 5,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_MHASH_TABLE		= 6,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_REG1			= 7,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_REG2			= 8,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_REG3			= 9,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_REG4			= 10,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_REG5			= 11,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_REG6			= 12,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_REG7			= 13,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_REG8			= 14,
-	AL_ETH_CTRL_TABLE_UDMA_SEL_VAL_0		= 15,
-};
-
-enum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL {
-	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_0		= 0,
-	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG		= 1, /**< select header len from the hdr_split register (set by al_eth_rx_header_split_config())*/
-	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L3_OFFSET = 2,
-	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L4_OFFSET = 3,
-	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_TUNNEL_START_OFFSET = 4,
-	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L3_OFFSET = 5,
-	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L4_OFFSET = 6,
-};
-
-struct al_eth_fwd_ctrl_table_entry {
-	enum AL_ETH_CTRL_TABLE_PRIO_SEL		prio_sel;
-	enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1	queue_sel_1; /**< queue id source */
-	enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2	queue_sel_2; /**< mix queue id with priority */
-	enum AL_ETH_CTRL_TABLE_UDMA_SEL		udma_sel;
-	enum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL hdr_split_len_sel;
-	al_bool 	filter; /**< set to AL_TRUE to enable filtering */
-};
-/**
- * Configure default control table entry
- *
- * @param adapter pointer to the private structure
- * @param use_table set to AL_TRUE if control table is used, when set to AL_FALSE
- * then control table will be bypassed and the entry value will be used.
- * @param entry defines the value to be used when bypassing control table.
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_ctrl_table_def_set(struct al_hal_eth_adapter *adapter,
-			      al_bool use_table,
-			      struct al_eth_fwd_ctrl_table_entry *entry);
-
-/**
- * Configure control table entry
- *
- * @param adapter pointer to the private structure
- * @param index the entry index within the control table.
- * @param entry the value to write to the control table entry
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_ctrl_table_set(struct al_hal_eth_adapter *adapter,
-			  struct al_eth_fwd_ctrl_table_index *index,
-			  struct al_eth_fwd_ctrl_table_entry *entry);
-
-int al_eth_ctrl_table_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry);
-int al_eth_ctrl_table_def_raw_set(struct al_hal_eth_adapter *adapter, uint32_t val);
-
-/**
- * Configure hash key initial registers
- * Those registers define the initial key values, those values used for
- * the THASH and MHASH hash functions.
- *
- * @param adapter pointer to the private structure
- * @param idx the register index
- * @param val the register value
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_hash_key_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t val);
-
-struct al_eth_fwd_mac_table_entry {
-	uint8_t		addr[6]; /**< byte 0 is the first byte seen on the wire */
-	uint8_t		mask[6];
-	al_bool		tx_valid;
-	uint8_t		tx_target;
-	al_bool		rx_valid;
-	uint8_t		udma_mask; /**< target udma */
-	uint8_t		qid; /**< target queue */
-	al_bool		filter; /**< set to AL_TRUE to enable filtering */
-};
-
-/**
- * Configure mac table entry
- * The HW traverse this table and looks for match from lowest index,
- * when the packets MAC DA & mask == addr, and the valid bit is set, then match occurs.
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index within the mac table.
- * @param entry the contents of the MAC table entry
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_mac_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-				struct al_eth_fwd_mac_table_entry *entry);
-
-int al_eth_fwd_mac_addr_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-				uint32_t addr_lo, uint32_t addr_hi, uint32_t mask_lo, uint32_t mask_hi);
-int al_eth_fwd_mac_ctrl_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t ctrl);
-
-int al_eth_mac_addr_store(void * __iomem ec_base, uint32_t idx, uint8_t *addr);
-int al_eth_mac_addr_read(void * __iomem ec_base, uint32_t idx, uint8_t *addr);
-
-/**
- * Configure pbits table entry
- * The HW uses this table to translate between vlan pbits field to priority.
- * The vlan pbits is used as the index of this table.
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index within the table.
- * @param prio the priority to set for this entry
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_pbits_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio);
-
-/**
- * Configure priority table entry
- * The HW uses this table to translate between priority to queue index.
- * The priority is used as the index of this table.
- *
- * @param adapter pointer to the private structure
- * @param prio the entry index within the table.
- * @param qid the queue index to set for this entry (priority).
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_priority_table_set(struct al_hal_eth_adapter *adapter, uint8_t prio, uint8_t qid);
-
-/**
- * Configure DSCP table entry
- * The HW uses this table to translate between IPv4 DSCP field to priority.
- * The IPv4 byte 1 (DSCP+ECN) used as index to this table.
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index within the table.
- * @param prio the queue index to set for this entry (priority).
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_dscp_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio);
-
-/**
- * Configure TC table entry
- * The HW uses this table to translate between IPv6 TC field to priority.
- * The IPv6 TC used as index to this table.
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index within the table.
- * @param prio the queue index to set for this entry (priority).
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_tc_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio);
-
-/**
- * Configure MAC HASH table entry
- * The HW uses 8 bits from the hash result on the MAC DA as index to this table.
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index within the table.
- * @param udma_mask the target udma to set for this entry.
- * @param qid the target queue index to set for this entry.
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_mhash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, uint8_t qid);
-
-struct al_eth_fwd_vid_table_entry {
-	uint8_t	control:1; /**< used as input for the control table */
-	uint8_t filter:1; /**< set to 1 to enable filtering */
-	uint8_t udma_mask:4; /**< target udmas */
-};
-
-/**
- * Configure default vlan table entry
- *
- * @param adapter pointer to the private structure
- * @param use_table set to AL_TRUE if vlan table is used, when set to AL_FALSE
- * then vid table will be bypassed and the default_entry value will be used.
- * @param default_entry defines the value to be used when bypassing vid table.
- * @param default_vlan defines the value will be used when untagget packet
- * received. this value will be used only for steering and filtering control,
- * the packet's data will not be changed.
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_vid_config_set(struct al_hal_eth_adapter *adapter, al_bool use_table,
-			      struct al_eth_fwd_vid_table_entry *default_entry,
-			      uint32_t default_vlan);
-/**
- * Configure vlan table entry
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index within the vlan table. The HW uses the vlan id
- * field of the packet when accessing this table.
- * @param entry the value to write to the vlan table entry
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-			     struct al_eth_fwd_vid_table_entry *entry);
-
-
-/**
- * Configure default UDMA register
- * When the control table entry udma selection set to AL_ETH_CTRL_TABLE_UDMA_SEL_REG<n>,
- * then the target UDMA will be set according to the register n of the default
- * UDMA registers.
- *
- * @param adapter pointer to the private structure
- * @param idx the index of the default register.
- * @param udma_mask the value of the register.
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_default_udma_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
-				   uint8_t udma_mask);
-
-/**
- * Configure default queue register
- * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG<n>,
- * then the target queue will be set according to the register n of the default
- * queue registers.
- *
- * @param adapter pointer to the private structure
- * @param idx the index of the default register.
- * @param qid the value of the register.
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_default_queue_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
-				   uint8_t qid);
-
-/**
- * Configure default priority register
- * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_PRIO_SEL_1_REG<n>,
- * then the target priority will be set according to the register n of the default
- * priority registers.
- *
- * @param adapter pointer to the private structure
- * @param idx the index of the default register.
- * @param prio the value of the register.
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_fwd_default_priority_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
-				   uint8_t prio);
-
-
-
-/* filter undetected MAC DA */
-#define AL_ETH_RFW_FILTER_UNDET_MAC          (1 << 0)
-/* filter specific MAC DA based on MAC table output */
-#define AL_ETH_RFW_FILTER_DET_MAC            (1 << 1)
-/* filter all tagged */
-#define AL_ETH_RFW_FILTER_TAGGED             (1 << 2)
-/* filter all untagged */
-#define AL_ETH_RFW_FILTER_UNTAGGED           (1 << 3)
-/* filter all broadcast */
-#define AL_ETH_RFW_FILTER_BC                 (1 << 4)
-/* filter all multicast */
-#define AL_ETH_RFW_FILTER_MC                 (1 << 5)
-/* filter packet based on parser drop */
-#define AL_ETH_RFW_FILTER_PARSE              (1 << 6)
-/* filter packet based on VLAN table output */
-#define AL_ETH_RFW_FILTER_VLAN_VID           (1 << 7)
-/* filter packet based on control table output */
-#define AL_ETH_RFW_FILTER_CTRL_TABLE         (1 << 8)
-/* filter packet based on protocol index */
-#define AL_ETH_RFW_FILTER_PROT_INDEX         (1 << 9)
-/* filter packet based on WoL decision */
-#define AL_ETH_RFW_FILTER_WOL		     (1 << 10)
-
-
-struct al_eth_filter_params {
-	al_bool		enable;
-	uint32_t	filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to enable */
-	al_bool		filter_proto[AL_ETH_PROTOCOLS_NUM]; /**< set AL_TRUE for protocols to filter */
-};
-
-struct al_eth_filter_override_params {
-	uint32_t	filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to override */
-	uint8_t		udma; /**< target udma id */
-	uint8_t		qid; /**< target queue id */
-};
-
-/**
- * Configure the receive filters
- * this function enables/disables filtering packets and which filtering
- * types to apply.
- * filters that indicated in tables (MAC table, VLAN and Control tables)
- * are not configured by this function. This functions only enables/disables
- * respecting the filter indication from those tables.
- *
- * @param adapter pointer to the private structure
- * @param params the parameters passed from upper layer
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_filter_config(struct al_hal_eth_adapter *adapter, struct al_eth_filter_params *params);
-
-/**
- * Configure the receive override filters
- * This function controls whither to force forwarding filtered packets
- * to a specific UDMA/queue. The override filters apply only for
- * filters that enabled by al_eth_filter_config().
- *
- * @param adapter pointer to the private structure
- * @param params override config parameters
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_filter_override_config(struct al_hal_eth_adapter *adapter,
-				  struct al_eth_filter_override_params *params);
-
-
-int al_eth_switching_config_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t forward_all_to_mac, uint8_t enable_int_switching,
-					enum al_eth_tx_switch_vid_sel_type vid_sel_type,
-					enum al_eth_tx_switch_dec_type uc_dec,
-					enum al_eth_tx_switch_dec_type mc_dec,
-					enum al_eth_tx_switch_dec_type bc_dec);
-int al_eth_switching_default_bitmap_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t udma_uc_bitmask,
-						uint8_t udma_mc_bitmask,uint8_t udma_bc_bitmask);
-int al_eth_flow_control_config(struct al_hal_eth_adapter *adapter, struct al_eth_flow_control_params *params);
-
-struct al_eth_eee_params{
-	uint8_t enable;
-	uint32_t tx_eee_timer; /**< time in cycles the interface delays prior to entering eee state */
-	uint32_t min_interval; /**< minimum interval in cycles between two eee states */
-	uint32_t stop_cnt; /**< time in cycles to stop Tx mac i/f after getting out of eee state */
-	al_bool fast_wake; /**< fast_wake is only applicable to 40/50G, otherwise the mode is deep_sleep */
-};
-
-/**
- * configure EEE mode
- * @param adapter pointer to the private structure.
- * @param params pointer to the eee input parameters.
- *
- * @return return 0 on success. otherwise on failure.
- */
-int al_eth_eee_config(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params);
-
-/**
- * get EEE configuration
- * @param adapter pointer to the private structure.
- * @param params pointer to the eee output parameters.
- *
- * @return return 0 on success. otherwise on failure.
- */
-int al_eth_eee_get(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params);
-
-int al_eth_vlan_mod_config(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint16_t udma_etype, uint16_t vlan1_data, uint16_t vlan2_data);
-
-/* Timestamp
- * This is a generic time-stamp mechanism that can be used as generic to
- * time-stamp every received or transmit packet it can also support IEEE 1588v2
- * PTP time synchronization protocol.
- * In addition to time-stamp, an internal system time is maintained. For
- * further accuracy, the chip support transmit/receive clock synchronization
- * including recovery of master clock from one of the ports and distributing it
- * to the rest of the ports - that is outside the scope of the Ethernet
- * Controller - please refer to Annapurna Labs Alpine Hardware Wiki
- */
-
-/* Timestamp management APIs */
-
-/**
- * prepare the adapter for timestamping packets.
- * Rx timestamps requires using 8 words (8x4 bytes) rx completion descriptor
- * size as the timestamp value added into word 4.
- *
- * This function should be called after al_eth_mac_config() and before
- * enabling the queues.
- * @param adapter pointer to the private structure.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_ts_init(struct al_hal_eth_adapter *adapter);
-
-/* Timestamp data path APIs */
-
-/*
- * This is the size of the on-chip array that keeps the time-stamp of the
- * latest transmitted packets
- */
-#define AL_ETH_PTH_TX_SAMPLES_NUM	16
-
-/**
- * read Timestamp sample value of previously transmitted packet.
- *
- * The adapter includes AL_ETH_PTH_TX_SAMPLES_NUM timestamp samples for tx
- * packets, those samples shared for all the UDMAs and queues. the al_eth_pkt
- * data structure includes the index of which sample to use for the packet
- * to transmit. It's the caller's responsibility to manage those samples,
- * for example, when using an index, the caller must make sure the packet
- * is completed and the tx time is sampled before using that index for
- * another packet.
- *
- * This function should be called after the completion indication of the
- * tx packet. however, there is a little chance that the timestamp sample
- * won't be updated yet, thus this function must be called again when it
- * returns -EAGAIN.
- * @param adapter pointer to the private structure.
- * @param ts_index the index (out of 16) of the timestamp register
- * @param timestamp the timestamp value in 2^18 femtoseconds resolution.
- * @return -EAGAIN if the sample was not updated yet. 0 when the sample
- * was updated and no errors found.
- */
-int al_eth_tx_ts_val_get(struct al_hal_eth_adapter *adapter, uint8_t ts_index,
-			 uint32_t *timestamp);
-
-/* Timestamp PTH (PTP Timestamp Handler) control and times management */
-/** structure for describing PTH epoch time */
-struct al_eth_pth_time {
-	uint32_t	seconds; /**< seconds */
-	uint64_t	femto; /**< femto seconds */
-};
-
-/**
- * Read the systime value
- * This API should not be used to get the timestamp of packets.
- * The HW maintains 50 bits for the sub-seconds portion in femto resolution,
- * but this function reads only the 32 MSB bits since the LSB provides
- * sub-nanoseconds accuracy, which is not needed.
- * @param adapter pointer to the private structure.
- * @param systime pointer to structure where the time will be stored.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_systime_read(struct al_hal_eth_adapter *adapter,
-			    struct al_eth_pth_time *systime);
-
-/**
- * Set the clock period to a given value.
- * The systime will be incremented by this value on each posedge of the
- * adapters internal clock which driven by the SouthBridge clock.
- * @param adapter pointer to the private structure.
- * @param clk_period the clock period in femto seconds.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_clk_period_write(struct al_hal_eth_adapter *adapter,
-				uint64_t clk_period);
-
-/**< enum for methods when updating systime using triggers */
-enum al_eth_pth_update_method {
-	AL_ETH_PTH_UPDATE_METHOD_SET = 0, /**< Set the time in int/ext update time */
-	AL_ETH_PTH_UPDATE_METHOD_INC = 1, /**< increment */
-	AL_ETH_PTH_UPDATE_METHOD_DEC = 2, /**< decrement */
-	AL_ETH_PTH_UPDATE_METHOD_ADD_TO_LAST = 3, /**< Set to last time + int/ext update time.*/
-};
-
-/**< systime internal update trigger types */
-enum al_eth_pth_int_trig {
-	AL_ETH_PTH_INT_TRIG_OUT_PULSE_0 = 0, /**< use output pulse as trigger */
-	AL_ETH_PTH_INT_TRIG_REG_WRITE = 1, /**< use the int update register
-					    * write as a trigger
-					    */
-};
-
-/**< parameters for internal trigger update */
-struct al_eth_pth_int_update_params {
-	al_bool		enable; /**< enable internal trigger update */
-	enum al_eth_pth_update_method	method; /**< internal trigger update
-						 * method
-						 */
-	enum al_eth_pth_int_trig	trigger; /**< which internal trigger to
-						  * use
-						  */
-};
-
-/**
- * Configure the systime internal update
- *
- * @param adapter pointer to the private structure.
- * @param params the configuration of the internal update.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_int_update_config(struct al_hal_eth_adapter *adapter,
-				 struct al_eth_pth_int_update_params *params);
-
-/**
- * set internal update time
- *
- * The update time used when updating the systime with
- * internal update method.
- *
- * @param adapter pointer to the private structure.
- * @param time the internal update time value
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_int_update_time_set(struct al_hal_eth_adapter *adapter,
-				   struct al_eth_pth_time *time);
-
-/**< parameters for external trigger update */
-struct al_eth_pth_ext_update_params {
-	uint8_t		triggers; /**< bitmask of external triggers to enable */
-	enum al_eth_pth_update_method	method; /**< external trigger update
-						 * method
-						 */
-};
-
-/**
- * Configure the systime external update.
- * external update triggered by external signals such as GPIO or pulses
- * from other eth controllers on the SoC.
- *
- * @param adapter pointer to the private structure.
- * @param params the configuration of the external update.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_ext_update_config(struct al_hal_eth_adapter *adapter,
-				 struct al_eth_pth_ext_update_params *params);
-
-/**
- * set external update time
- *
- * The update time used when updating the systime with
- * external update method.
- * @param adapter pointer to the private structure.
- * @param time the external update time value
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_ext_update_time_set(struct al_hal_eth_adapter *adapter,
-				   struct al_eth_pth_time *time);
-/**
- * set the read compensation delay
- *
- * When reading the systime, the HW adds this value to compensate
- * read latency.
- *
- * @param adapter pointer to the private structure.
- * @param subseconds the read latency delay in femto seconds.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_read_compensation_set(struct al_hal_eth_adapter *adapter,
-				     uint64_t subseconds);
-/**
- * set the internal write compensation delay
- *
- * When updating the systime due to an internal trigger's event, the HW adds
- * this value to compensate latency.
- *
- * @param adapter pointer to the private structure.
- * @param subseconds the write latency delay in femto seconds.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_int_write_compensation_set(struct al_hal_eth_adapter *adapter,
-					  uint64_t subseconds);
-
-/**
- * set the external write compensation delay
- *
- * When updating the systime due to an external trigger's event, the HW adds
- * this value to compensate pulse propagation latency.
- *
- * @param adapter pointer to the private structure.
- * @param subseconds the write latency delay in femto seconds.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_ext_write_compensation_set(struct al_hal_eth_adapter *adapter,
-					  uint64_t subseconds);
-
-/**
- * set the sync compensation delay
- *
- * When the adapter passes systime from PTH to MAC to do the packets
- * timestamping, the sync compensation delay is added to systime value to
- * compensate the latency between the PTH and the MAC.
- *
- * @param adapter pointer to the private structure.
- * @param subseconds the sync latency delay in femto seconds.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_sync_compensation_set(struct al_hal_eth_adapter *adapter,
-				     uint64_t subseconds);
-
-#define AL_ETH_PTH_PULSE_OUT_NUM	8
-struct al_eth_pth_pulse_out_params {
-	uint8_t		index; /**< id of the pulse (0..7) */
-	al_bool		enable;
-	al_bool		periodic; /**< when true, generate periodic pulse (PPS) */
-	uint8_t		period_sec; /**< for periodic pulse, this is seconds
-				     * portion of the period time
-				     */
-	uint32_t	period_us; /**< this is microseconds portion of the
-				      * period
-				      */
-	struct al_eth_pth_time	start_time; /**< when to start pulse triggering */
-	uint64_t	pulse_width; /**< pulse width in femto seconds */
-};
-
-/**
- * Configure an output pulse
- * This function configures an output pulse coming from the internal System
- * Time. This is typically a 1Hhz pulse that is used to synchronize the
- * rest of the components of the system. This API configure the Ethernet
- * Controller pulse. An additional set up is required to configure the chip
- * General Purpose I/O (GPIO) to enable the chip output pin.
- *
- * @param adapter pointer to the private structure.
- * @param params output pulse configuration.
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_pth_pulse_out_config(struct al_hal_eth_adapter *adapter,
-				struct al_eth_pth_pulse_out_params *params);
-
-/* link */
-struct al_eth_link_status {
-	al_bool		link_up;
-	al_bool		local_fault;
-	al_bool		remote_fault;
-};
-
-/**
- * get link status
- *
- * this function should be used when no external phy is used to get
- * information about the link
- *
- * @param adapter pointer to the private structure.
- * @param status pointer to struct where to set link information
- *
- * @return return 0 on success. otherwise on failure.
- */
-int al_eth_link_status_get(struct al_hal_eth_adapter *adapter,
-			   struct al_eth_link_status *status);
-
-/**
- * clear link status
- *
- * this function clear latched status of the link.
- *
- * @param adapter pointer to the private structure.
- *
- * @return return 0 if supported.
- */
-int al_eth_link_status_clear(struct al_hal_eth_adapter *adapter);
-
-/**
- * Set LEDs to represent link status.
- *
- * @param adapter pointer to the private structure.
- * @param link_is_up boolean indicating current link status.
- *	  In case link is down the leds will be turned off.
- *	  In case link is up the leds will be turned on, that means
- *	  leds will be blinking on traffic and will be constantly lighting
- *	  on inactive link
- * @return return 0 on success. otherwise on failure.
- */
-int al_eth_led_set(struct al_hal_eth_adapter *adapter, al_bool link_is_up);
-
-/* get statistics */
-
-struct al_eth_mac_stats{
-	/* sum the data and padding octets (i.e. without header and FCS) received with a valid frame. */
-	uint64_t aOctetsReceivedOK;
-	/* sum of Payload and padding octets of frames transmitted without error*/
-	uint64_t aOctetsTransmittedOK;
-	/* total number of packets received. Good and bad packets */
-	uint32_t etherStatsPkts;
-	/* number of received unicast packets */
-	uint32_t ifInUcastPkts;
-	/* number of received multicast packets */
-	uint32_t ifInMulticastPkts;
-	/* number of received broadcast packets */
-	uint32_t ifInBroadcastPkts;
-	/* Number of frames received with FIFO Overflow, CRC, Payload Length, Jabber and Oversized, Alignment or PHY/PCS error indication */
-	uint32_t ifInErrors;
-
-	/* number of transmitted unicast packets */
-	uint32_t ifOutUcastPkts;
-	/* number of transmitted multicast packets */
-	uint32_t ifOutMulticastPkts;
-	/* number of transmitted broadcast packets */
-	uint32_t ifOutBroadcastPkts;
-	/* number of frames transmitted with FIFO Overflow, FIFO Underflow or Controller indicated error */
-	uint32_t ifOutErrors;
-
-	/* number of Frame received without error (Including Pause Frames). */
-	uint32_t aFramesReceivedOK;
-	/* number of Frames transmitter without error (Including Pause Frames) */
-	uint32_t aFramesTransmittedOK;
-	/* number of packets received with less than 64 octets */
-	uint32_t etherStatsUndersizePkts;
-	/* Too short frames with CRC error, available only for RGMII and 1G Serial modes */
-	uint32_t etherStatsFragments;
-	/* Too long frames with CRC error */
-	uint32_t etherStatsJabbers;
-	/* packet that exceeds the valid maximum programmed frame length */
-	uint32_t etherStatsOversizePkts;
-	/* number of frames received with a CRC error */
-	uint32_t aFrameCheckSequenceErrors;
-	/* number of frames received with alignment error */
-	uint32_t aAlignmentErrors;
-	/* number of dropped packets due to FIFO overflow */
-	uint32_t etherStatsDropEvents;
-	/* number of transmitted pause frames. */
-	uint32_t aPAUSEMACCtrlFramesTransmitted;
-	/* number of received pause frames. */
-	uint32_t aPAUSEMACCtrlFramesReceived;
-	/* frame received exceeded the maximum length programmed with register FRM_LGTH, available only for 10G modes */
-	uint32_t aFrameTooLongErrors;
-	/* received frame with bad length/type (between 46 and 0x600 or less
-	 * than 46 for packets longer than 64), available only for 10G modes */
-	uint32_t aInRangeLengthErrors;
-	/* Valid VLAN tagged frames transmitted */
-	uint32_t VLANTransmittedOK;
-	/* Valid VLAN tagged frames received */
-	uint32_t VLANReceivedOK;
-	/* Total number of octets received. Good and bad packets */
-	uint32_t etherStatsOctets;
-
-	/* packets of 64 octets length is received (good and bad frames are counted) */
-	uint32_t etherStatsPkts64Octets;
-	/* Frames (good and bad) with 65 to 127 octets */
-	uint32_t etherStatsPkts65to127Octets;
-	/* Frames (good and bad) with 128 to 255 octets */
-	uint32_t etherStatsPkts128to255Octets;
-	/* Frames (good and bad) with 256 to 511 octets */
-	uint32_t etherStatsPkts256to511Octets;
-	/* Frames (good and bad) with 512 to 1023 octets */
-	uint32_t etherStatsPkts512to1023Octets;
-	/* Frames (good and bad) with 1024 to 1518 octets */
-	uint32_t etherStatsPkts1024to1518Octets;
-	/* frames with 1519 bytes to the maximum length programmed in the register FRAME_LENGTH. */
-	uint32_t etherStatsPkts1519toX;
-
-	uint32_t eee_in;
-	uint32_t eee_out;
-};
-
-/**
- * get mac statistics
- * @param adapter pointer to the private structure.
- * @param stats pointer to structure that will be filled with statistics.
- *
- * @return return 0 on success. otherwise on failure.
- */
-int al_eth_mac_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_mac_stats *stats);
-
-struct al_eth_ec_stats{
-	/* Rx Frequency adjust FIFO input  packets */
-	uint32_t faf_in_rx_pkt;
-	/* Rx Frequency adjust FIFO input  short error packets */
-	uint32_t faf_in_rx_short;
-	/* Rx Frequency adjust FIFO input  long error packets */
-	uint32_t faf_in_rx_long;
-	/* Rx Frequency adjust FIFO output  packets */
-	uint32_t faf_out_rx_pkt;
-	/* Rx Frequency adjust FIFO output  short error packets */
-	uint32_t faf_out_rx_short;
-	/* Rx Frequency adjust FIFO output  long error packets */
-	uint32_t faf_out_rx_long;
-	/* Rx Frequency adjust FIFO output  drop packets */
-	uint32_t faf_out_drop;
-	/* Number of packets written into the Rx FIFO (without FIFO error indication) */
-	uint32_t rxf_in_rx_pkt;
-	/* Number of error packets written into the Rx FIFO (with FIFO error indication, */
-	/* FIFO full indication during packet reception) */
-	uint32_t rxf_in_fifo_err;
-	/* Number of packets read from Rx FIFO 1 */
-	uint32_t lbf_in_rx_pkt;
-	/* Number of packets read from Rx FIFO 2 (loopback FIFO) */
-	uint32_t lbf_in_fifo_err;
-	/* Rx FIFO output drop packets from FIFO 1 */
-	uint32_t rxf_out_rx_1_pkt;
-	/* Rx FIFO output drop packets from FIFO 2 (loop back) */
-	uint32_t rxf_out_rx_2_pkt;
-	/* Rx FIFO output drop packets from FIFO 1 */
-	uint32_t rxf_out_drop_1_pkt;
-	/* Rx FIFO output drop packets from FIFO 2 (loop back) */
-	uint32_t rxf_out_drop_2_pkt;
-	/* Rx Parser 1, input packet counter */
-	uint32_t rpe_1_in_rx_pkt;
-	/* Rx Parser 1, output packet counter */
-	uint32_t rpe_1_out_rx_pkt;
-	/* Rx Parser 2, input packet counter */
-	uint32_t rpe_2_in_rx_pkt;
-	/* Rx Parser 2, output packet counter */
-	uint32_t rpe_2_out_rx_pkt;
-	/* Rx Parser 3 (MACsec), input packet counter */
-	uint32_t rpe_3_in_rx_pkt;
-	/* Rx Parser 3 (MACsec), output packet counter */
-	uint32_t rpe_3_out_rx_pkt;
-	/* Tx parser, input packet counter */
-	uint32_t tpe_in_tx_pkt;
-	/* Tx parser, output packet counter */
-	uint32_t tpe_out_tx_pkt;
-	/* Tx packet modification, input packet counter */
-	uint32_t tpm_tx_pkt;
-	/* Tx forwarding input packet counter */
-	uint32_t tfw_in_tx_pkt;
-	/* Tx forwarding input packet counter */
-	uint32_t tfw_out_tx_pkt;
-	/* Rx forwarding input packet counter */
-	uint32_t rfw_in_rx_pkt;
-	/* Rx Forwarding, packet with VLAN command drop indication */
-	uint32_t rfw_in_vlan_drop;
-	/* Rx Forwarding, packets with parse drop indication */
-	uint32_t rfw_in_parse_drop;
-	/* Rx Forwarding, multicast packets */
-	uint32_t rfw_in_mc;
-	/* Rx Forwarding, broadcast packets */
-	uint32_t rfw_in_bc;
-	/* Rx Forwarding, tagged packets */
-	uint32_t rfw_in_vlan_exist;
-	/* Rx Forwarding, untagged packets */
-	uint32_t rfw_in_vlan_nexist;
-	/* Rx Forwarding, packets with MAC address drop indication (from the MAC address table) */
-	uint32_t rfw_in_mac_drop;
-	/* Rx Forwarding, packets with undetected MAC address */
-	uint32_t rfw_in_mac_ndet_drop;
-	/* Rx Forwarding, packets with drop indication from the control table */
-	uint32_t rfw_in_ctrl_drop;
-	/* Rx Forwarding, packets with L3_protocol_index drop indication */
-	uint32_t rfw_in_prot_i_drop;
-	/* EEE, number of times the system went into EEE state */
-	uint32_t eee_in;
-};
-
-/**
- * get ec statistics
- * @param adapter pointer to the private structure.
- * @param stats pointer to structure that will be filled with statistics.
- *
- * @return return 0 on success. otherwise on failure.
- */
-int al_eth_ec_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_ec_stats *stats);
-
-struct al_eth_ec_stat_udma{
-	/* Rx forwarding output packet counter */
-	uint32_t rfw_out_rx_pkt;
-	/* Rx forwarding output drop packet counter */
-	uint32_t rfw_out_drop;
-	/* Multi-stream write, number of Rx packets */
-	uint32_t msw_in_rx_pkt;
-	/* Multi-stream write, number of dropped packets at SOP,  Q full indication */
-	uint32_t msw_drop_q_full;
-	/* Multi-stream write, number of dropped packets at SOP */
-	uint32_t msw_drop_sop;
-	/* Multi-stream write, number of dropped packets at EOP, */
-	/*EOP was written with error indication (not all packet data was written) */
-	uint32_t msw_drop_eop;
-	/* Multi-stream write, number of packets written to the stream FIFO with EOP and without packet loss */
-	uint32_t msw_wr_eop;
-	/* Multi-stream write, number of packets read from the FIFO into the stream */
-	uint32_t msw_out_rx_pkt;
-	/* Number of transmitted packets without TSO enabled */
-	uint32_t tso_no_tso_pkt;
-	/* Number of transmitted packets with TSO enabled */
-	uint32_t tso_tso_pkt;
-	/* Number of TSO segments that were generated */
-	uint32_t tso_seg_pkt;
-	/* Number of TSO segments that required padding */
-	uint32_t tso_pad_pkt;
-	/* Tx Packet modification, MAC SA spoof error */
-	uint32_t tpm_tx_spoof;
-	/* Tx MAC interface, input packet counter */
-	uint32_t tmi_in_tx_pkt;
-	/* Tx MAC interface, number of packets forwarded to the MAC */
-	uint32_t tmi_out_to_mac;
-	/* Tx MAC interface, number of packets forwarded to the Rx data path */
-	uint32_t tmi_out_to_rx;
-	/* Tx MAC interface, number of transmitted bytes */
-	uint32_t tx_q0_bytes;
-	/* Tx MAC interface, number of transmitted bytes */
-	uint32_t tx_q1_bytes;
-	/* Tx MAC interface, number of transmitted bytes */
-	uint32_t tx_q2_bytes;
-	/* Tx MAC interface, number of transmitted bytes */
-	uint32_t tx_q3_bytes;
-	/* Tx MAC interface, number of transmitted packets */
-	uint32_t tx_q0_pkts;
-	/* Tx MAC interface, number of transmitted packets */
-	uint32_t tx_q1_pkts;
-	/* Tx MAC interface, number of transmitted packets */
-	uint32_t tx_q2_pkts;
-	/* Tx MAC interface, number of transmitted packets */
-	uint32_t tx_q3_pkts;
-};
-
-/**
- * get per_udma statistics
- * @param adapter pointer to the private structure.
- * @param idx udma_id value
- * @param stats pointer to structure that will be filled with statistics.
- *
- * @return return 0 on success. otherwise on failure.
- */
-int al_eth_ec_stat_udma_get(struct al_hal_eth_adapter *adapter, uint8_t idx, struct al_eth_ec_stat_udma *stats);
-
-/* trafic control */
-
-/**
- * perform Function Level Reset RMN
- *
- * Addressing RMN: 714
- *
- * @param pci_read_config_u32 pointer to function that reads register from pci header
- * @param pci_write_config_u32 pointer to function that writes register from pci header
- * @param handle pointer passes to the above functions as first parameter
- * @param mac_base base address of the MAC registers
- *
- * @return 0.
- */
-int al_eth_flr_rmn(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val),
-		   int (* pci_write_config_u32)(void *handle, int where, uint32_t val),
-		   void *handle,
-		   void __iomem	*mac_base);
-
-/**
- * perform Function Level Reset RMN but restore registers that contain board specific data
- *
- * the data that save and restored is the board params and mac addresses
- *
- * @param pci_read_config_u32 pointer to function that reads register from pci header
- * @param pci_write_config_u32 pointer to function that writes register from pci header
- * @param handle pointer passes to the above functions as first parameter
- * @param mac_base base address of the MAC registers
- * @param ec_base base address of the Ethernet Controller registers
- * @param mac_addresses_num number of mac addresses to restore
- *
- * @return 0.
- */
-int al_eth_flr_rmn_restore_params(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val),
-		int (* pci_write_config_u32)(void *handle, int where, uint32_t val),
-		void *handle,
-		void __iomem	*mac_base,
-		void __iomem	*ec_base,
-		int	mac_addresses_num);
-
-/* board specific information (media type, phy address, etc.. */
-
-
-enum al_eth_board_media_type {
-	AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT		= 0,
-	AL_ETH_BOARD_MEDIA_TYPE_RGMII			= 1,
-	AL_ETH_BOARD_MEDIA_TYPE_10GBASE_SR		= 2,
-	AL_ETH_BOARD_MEDIA_TYPE_SGMII			= 3,
-	AL_ETH_BOARD_MEDIA_TYPE_1000BASE_X		= 4,
-	AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT_AUTO_SPEED	= 5,
-	AL_ETH_BOARD_MEDIA_TYPE_SGMII_2_5G		= 6,
-	AL_ETH_BOARD_MEDIA_TYPE_NBASE_T			= 7,
-	AL_ETH_BOARD_MEDIA_TYPE_25G			= 8,
-};
-
-enum al_eth_board_mdio_freq {
-	AL_ETH_BOARD_MDIO_FREQ_2_5_MHZ	= 0,
-	AL_ETH_BOARD_MDIO_FREQ_1_MHZ	= 1,
-};
-
-enum al_eth_board_ext_phy_if {
-	AL_ETH_BOARD_PHY_IF_MDIO	= 0,
-	AL_ETH_BOARD_PHY_IF_XMDIO	= 1,
-	AL_ETH_BOARD_PHY_IF_I2C		= 2,
-
-};
-
-enum al_eth_board_auto_neg_mode {
-	AL_ETH_BOARD_AUTONEG_OUT_OF_BAND	= 0,
-	AL_ETH_BOARD_AUTONEG_IN_BAND		= 1,
-
-};
-
-/* declare the 1G mac active speed when auto negotiation disabled */
-enum al_eth_board_1g_speed {
-	AL_ETH_BOARD_1G_SPEED_1000M		= 0,
-	AL_ETH_BOARD_1G_SPEED_100M		= 1,
-	AL_ETH_BOARD_1G_SPEED_10M		= 2,
-};
-
-enum al_eth_retimer_channel {
-	AL_ETH_RETIMER_CHANNEL_A		= 0,
-	AL_ETH_RETIMER_CHANNEL_B		= 1,
-	AL_ETH_RETIMER_CHANNEL_C		= 2,
-	AL_ETH_RETIMER_CHANNEL_D		= 3,
-	AL_ETH_RETIMER_CHANNEL_E		= 4,
-	AL_ETH_RETIMER_CHANNEL_F		= 5,
-	AL_ETH_RETIMER_CHANNEL_G		= 6,
-	AL_ETH_RETIMER_CHANNEL_H		= 7,
-	AL_ETH_RETIMER_CHANNEL_MAX		= 8
-};
-
-/* list of supported retimers */
-enum al_eth_retimer_type {
-	AL_ETH_RETIMER_BR_210			= 0,
-	AL_ETH_RETIMER_BR_410			= 1,
-	AL_ETH_RETIMER_DS_25			= 2,
-
-	AL_ETH_RETIMER_TYPE_MAX			= 4,
-};
-
-/** structure represents the board information. this info set by boot loader
- * and read by OS driver.
- */
-struct al_eth_board_params {
-	enum al_eth_board_media_type	media_type;
-	al_bool		phy_exist; /**< external phy exist */
-	uint8_t		phy_mdio_addr; /**< mdio address of external phy */
-	al_bool		sfp_plus_module_exist; /**< SFP+ module connected */
-	al_bool		autoneg_enable; /**< enable Auto-Negotiation */
-	al_bool		kr_lt_enable; /**< enable KR Link-Training */
-	al_bool		kr_fec_enable; /**< enable KR FEC */
-	enum al_eth_board_mdio_freq	mdio_freq; /**< MDIO frequency */
-	uint8_t		i2c_adapter_id; /**< identifier for the i2c adapter to use to access SFP+ module */
-	enum al_eth_board_ext_phy_if	phy_if; /**< phy interface */
-	enum al_eth_board_auto_neg_mode	an_mode; /**< auto-negotiation mode (in-band / out-of-band) */
-	uint8_t		serdes_grp; /**< serdes's group id */
-	uint8_t		serdes_lane; /**< serdes's lane id */
-	enum al_eth_ref_clk_freq	ref_clk_freq; /**< reference clock frequency */
-	al_bool		dont_override_serdes; /**< prevent override serdes parameters */
-	al_bool		force_1000_base_x; /**< set mac to 1000 base-x mode (instead sgmii) */
-	al_bool		an_disable; /**< disable auto negotiation */
-	enum al_eth_board_1g_speed	speed; /**< port speed if AN disabled */
-	al_bool		half_duplex; /**< force half duplex if AN disabled */
-	al_bool		fc_disable; /**< disable flow control */
-	al_bool		retimer_exist; /**< retimer is exist on the board */
-	uint8_t		retimer_bus_id; /**< in what i2c bus the retimer is on */
-	uint8_t		retimer_i2c_addr; /**< i2c address of the retimer */
-	enum al_eth_retimer_channel retimer_channel; /**< what channel connected to this port (Rx) */
-	al_bool		dac; /**< assume direct attached cable is connected if auto detect is off or failed */
-	uint8_t		dac_len; /**< assume this cable length if auto detect is off or failed  */
-	enum al_eth_retimer_type retimer_type; /**< the type of the specific retimer */
-	enum al_eth_retimer_channel retimer_tx_channel; /**< what channel connected to this port (Tx) */
-	uint8_t		gpio_sfp_present; /**< gpio number of sfp present for this port. 0 if not exist */
-};
-
-/**
- * set board parameter of the eth port
- * this function used to set the board parameters into scratchpad
- * registers. those paramters can be read later by OS driver.
- *
- * @param mac_base the virtual address of the mac registers (PCI BAR 2)
- * @param params pointer to structure the includes the paramters
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_board_params_set(void * __iomem mac_base, struct al_eth_board_params *params);
-
-/**
- * get board parameter of the eth port
- * this function used to get the board parameters from scratchpad
- * registers.
- *
- * @param mac_base the virtual address of the mac registers (PCI BAR 2)
- * @param params pointer to structure where the parameters will be stored.
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_board_params_get(void * __iomem mac_base, struct al_eth_board_params *params);
-
-/*
- * Wake-On-Lan (WoL)
- *
- * The following few functions configure the Wake-On-Lan packet detection
- * inside the Integrated Ethernet MAC.
- *
- * There are other alternative ways to set WoL, such using the
- * external 1000Base-T transceiver to set WoL mode.
- *
- * These APIs do not set the system-wide power-state, nor responsible on the
- * transition from Sleep to Normal power state.
- *
- * For system level considerations, please refer to Annapurna Labs Alpine Wiki.
- */
-/* Interrupt enable WoL MAC DA Unicast detected  packet */
-#define AL_ETH_WOL_INT_UNICAST		AL_BIT(0)
-/* Interrupt enable WoL L2 Multicast detected  packet */
-#define AL_ETH_WOL_INT_MULTICAST	AL_BIT(1)
-/* Interrupt enable WoL L2 Broadcast detected  packet */
-#define AL_ETH_WOL_INT_BROADCAST	AL_BIT(2)
-/* Interrupt enable WoL IPv4 detected  packet */
-#define AL_ETH_WOL_INT_IPV4		AL_BIT(3)
-/* Interrupt enable WoL IPv6 detected  packet */
-#define AL_ETH_WOL_INT_IPV6		AL_BIT(4)
-/* Interrupt enable WoL EtherType+MAC DA detected  packet */
-#define AL_ETH_WOL_INT_ETHERTYPE_DA	AL_BIT(5)
-/* Interrupt enable WoL EtherType+L2 Broadcast detected  packet */
-#define AL_ETH_WOL_INT_ETHERTYPE_BC	AL_BIT(6)
-/* Interrupt enable WoL parser detected  packet */
-#define AL_ETH_WOL_INT_PARSER		AL_BIT(7)
-/* Interrupt enable WoL magic detected  packet */
-#define AL_ETH_WOL_INT_MAGIC		AL_BIT(8)
-/* Interrupt enable WoL magic+password detected  packet */
-#define AL_ETH_WOL_INT_MAGIC_PSWD	AL_BIT(9)
-
-/* Forward enable WoL MAC DA Unicast detected  packet */
-#define AL_ETH_WOL_FWRD_UNICAST		AL_BIT(0)
-/* Forward enable WoL L2 Multicast detected  packet */
-#define AL_ETH_WOL_FWRD_MULTICAST	AL_BIT(1)
-/* Forward enable WoL L2 Broadcast detected  packet */
-#define AL_ETH_WOL_FWRD_BROADCAST	AL_BIT(2)
-/* Forward enable WoL IPv4 detected  packet */
-#define AL_ETH_WOL_FWRD_IPV4		AL_BIT(3)
-/* Forward enable WoL IPv6 detected  packet */
-#define AL_ETH_WOL_FWRD_IPV6		AL_BIT(4)
-/* Forward enable WoL EtherType+MAC DA detected  packet */
-#define AL_ETH_WOL_FWRD_ETHERTYPE_DA	AL_BIT(5)
-/* Forward enable WoL EtherType+L2 Broadcast detected  packet */
-#define AL_ETH_WOL_FWRD_ETHERTYPE_BC	AL_BIT(6)
-/* Forward enable WoL parser detected  packet */
-#define AL_ETH_WOL_FWRD_PARSER		AL_BIT(7)
-
-struct al_eth_wol_params {
-	uint8_t *dest_addr; /**< 6 bytes array of destanation address for
-				 magic packet detection */
-	uint8_t *pswd; /**< 6 bytes array of the password to use */
-	uint8_t *ipv4; /**< 4 bytes array of the ipv4 to use.
-			    example: for ip = 192.168.1.2
-			       ipv4[0]=2, ipv4[1]=1, ipv4[2]=168, ipv4[3]=192 */
-	uint8_t *ipv6; /** 16 bytes array of the ipv6 to use.
-			   example: ip = 2607:f0d0:1002:0051:0000:0000:5231:1234
-			       ipv6[0]=34, ipv6[1]=12, ipv6[2]=31 .. */
-	uint16_t ethr_type1; /**< first ethertype to use */
-	uint16_t ethr_type2; /**< secound ethertype to use */
-	uint16_t forward_mask; /**< bitmask of AL_ETH_WOL_FWRD_* of the packet
-				    types needed to be forward. */
-	uint16_t int_mask; /**< bitmask of AL_ETH_WOL_INT_* of the packet types
-				that will send interrupt to wake the system. */
-};
-
-/**
- * enable the wol mechanism
- * set what type of packets will wake up the system and what type of packets
- * neet to forward after the system is up
- *
- * beside this function wol filter also need to be set by
- * calling al_eth_filter_config with AL_ETH_RFW_FILTER_WOL
- *
- * @param adapter pointer to the private structure
- * @param wol the parameters needed to configure the wol
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_wol_enable(
-		struct al_hal_eth_adapter *adapter,
-		struct al_eth_wol_params *wol);
-
-/**
- * Disable the WoL mechnism.
- *
- * @param adapter pointer to the private structure
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_wol_disable(
-		struct al_hal_eth_adapter *adapter);
-
-/**
- * Configure tx fwd vlan table entry
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index within the vlan table. The HW uses the vlan id
- * field of the packet when accessing this table.
- * @param udma_mask vlan table value that indicates that the packet should be forward back to
- * the udmas, through the Rx path (udma_mask is one-hot representation)
- * @param fwd_to_mac vlan table value that indicates that the packet should be forward to mac
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_tx_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, al_bool fwd_to_mac);
-
-/** Tx Generic protocol detect Cam compare table entry  */
-struct al_eth_tx_gpd_cam_entry {
-	enum AL_ETH_PROTO_ID l3_proto_idx;
-	enum AL_ETH_PROTO_ID l4_proto_idx;
-	enum AL_ETH_TX_TUNNEL_MODE tunnel_control;
-	uint8_t source_vlan_count:2;
-	uint8_t tx_gpd_cam_ctrl:1;
-	uint8_t l3_proto_idx_mask:5;
-	uint8_t l4_proto_idx_mask:5;
-	uint8_t tunnel_control_mask:3;
-	uint8_t source_vlan_count_mask:2;
-};
-
-/** Rx Generic protocol detect Cam compare table entry  */
-struct al_eth_rx_gpd_cam_entry {
-	enum AL_ETH_PROTO_ID outer_l3_proto_idx;
-	enum AL_ETH_PROTO_ID outer_l4_proto_idx;
-	enum AL_ETH_PROTO_ID inner_l3_proto_idx;
-	enum AL_ETH_PROTO_ID inner_l4_proto_idx;
-	uint8_t parse_ctrl;
-	uint8_t outer_l3_len;
-	uint8_t l3_priority;
-	uint8_t l4_dst_port_lsb;
-	uint8_t rx_gpd_cam_ctrl:1;
-	uint8_t outer_l3_proto_idx_mask:5;
-	uint8_t outer_l4_proto_idx_mask:5;
-	uint8_t inner_l3_proto_idx_mask:5;
-	uint8_t inner_l4_proto_idx_mask:5;
-	uint8_t parse_ctrl_mask;
-	uint8_t outer_l3_len_mask;
-	uint8_t l3_priority_mask;
-	uint8_t l4_dst_port_lsb_mask;
-};
-
-enum AL_ETH_TX_GCP_ALU_OPSEL {
-	AL_ETH_TX_GCP_ALU_L3_OFFSET			= 0,
-	AL_ETH_TX_GCP_ALU_OUTER_L3_OFFSET		= 1,
-	AL_ETH_TX_GCP_ALU_L3_LEN			= 2,
-	AL_ETH_TX_GCP_ALU_OUTER_L3_LEN			= 3,
-	AL_ETH_TX_GCP_ALU_L4_OFFSET			= 4,
-	AL_ETH_TX_GCP_ALU_L4_LEN			= 5,
-	AL_ETH_TX_GCP_ALU_TABLE_VAL			= 10
-};
-
-enum AL_ETH_RX_GCP_ALU_OPSEL {
-	AL_ETH_RX_GCP_ALU_OUTER_L3_OFFSET		= 0,
-	AL_ETH_RX_GCP_ALU_INNER_L3_OFFSET		= 1,
-	AL_ETH_RX_GCP_ALU_OUTER_L4_OFFSET		= 2,
-	AL_ETH_RX_GCP_ALU_INNER_L4_OFFSET		= 3,
-	AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_LAT		= 4,
-	AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_LAT		= 5,
-	AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_SEL		= 6,
-	AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_SEL		= 7,
-	AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_1	= 8,
-	AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_2	= 9,
-	AL_ETH_RX_GCP_ALU_TABLE_VAL			= 10
-};
-
-/** Tx Generic crc prameters table entry  */
-
-struct al_eth_tx_gcp_table_entry {
-	uint8_t poly_sel:1;
-	uint8_t crc32_bit_comp:1;
-	uint8_t crc32_bit_swap:1;
-	uint8_t crc32_byte_swap:1;
-	uint8_t data_bit_swap:1;
-	uint8_t data_byte_swap:1;
-	uint8_t trail_size:4;
-	uint8_t head_size:8;
-	uint8_t head_calc:1;
-	uint8_t mask_polarity:1;
-	enum AL_ETH_ALU_OPCODE tx_alu_opcode_1;
-	enum AL_ETH_ALU_OPCODE tx_alu_opcode_2;
-	enum AL_ETH_ALU_OPCODE tx_alu_opcode_3;
-	enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_1;
-	enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_2;
-	enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_3;
-	enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_4;
-	uint32_t gcp_mask[6];
-	uint32_t crc_init;
-	uint8_t gcp_table_res:7;
-	uint16_t alu_val:9;
-};
-
-/** Rx Generic crc prameters table entry  */
-
-struct al_eth_rx_gcp_table_entry {
-	uint8_t poly_sel:1;
-	uint8_t crc32_bit_comp:1;
-	uint8_t crc32_bit_swap:1;
-	uint8_t crc32_byte_swap:1;
-	uint8_t data_bit_swap:1;
-	uint8_t data_byte_swap:1;
-	uint8_t trail_size:4;
-	uint8_t head_size:8;
-	uint8_t head_calc:1;
-	uint8_t mask_polarity:1;
-	enum AL_ETH_ALU_OPCODE rx_alu_opcode_1;
-	enum AL_ETH_ALU_OPCODE rx_alu_opcode_2;
-	enum AL_ETH_ALU_OPCODE rx_alu_opcode_3;
-	enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_1;
-	enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_2;
-	enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_3;
-	enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_4;
-	uint32_t gcp_mask[6];
-	uint32_t crc_init;
-	uint32_t gcp_table_res:27;
-	uint16_t alu_val:9;
-};
-
-/** Tx per_protocol_number crc & l3_checksum & l4_checksum command table entry  */
-
-struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry {
-        al_bool crc_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */
-        al_bool crc_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */
-        al_bool crc_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */
-        al_bool crc_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */
-        al_bool l4_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */
-        al_bool l4_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */
-        al_bool l4_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */
-        al_bool l4_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */
-        al_bool l3_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */
-        al_bool l3_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */
-        al_bool l3_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */
-        al_bool l3_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */
-};
-
-/**
- * Configure tx_gpd_entry
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index
- * @param tx_gpd_entry entry data for the Tx protocol detect Cam compare table
- *
- * @return 0 on success. otherwise on failure.
- *
- */
-int al_eth_tx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_tx_gpd_cam_entry *tx_gpd_entry);
-
-/**
- * Configure tx_gcp_entry
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index
- * @param tx_gcp_entry entry data for the Tx Generic crc prameters table
- *
- * @return 0 on success. otherwise on failure.
- *
- */
-int al_eth_tx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_tx_gcp_table_entry *tx_gcp_entry);
-
-/**
- * Configure tx_crc_chksum_replace_cmd_entry
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index
- * @param tx_replace_entry entry data for the Tx crc_&_l3_checksum_&_l4_checksum replace command table
- *
- * @return 0 on success. otherwise on failure.
- *
- */
-int al_eth_tx_crc_chksum_replace_cmd_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry *tx_replace_entry);
-
-/**
- * Configure rx_gpd_entry
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index
- * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table
- *
- * @return 0 on success. otherwise on failure.
- *
- */
-int al_eth_rx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_rx_gpd_cam_entry *rx_gpd_entry);
-
-/**
- * Configure rx_gcp_entry
- *
- * @param adapter pointer to the private structure
- * @param idx the entry index
- * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table
- * @param rx_gcp_entry entry data for the Tx Generic crc prameters table
- *
- * @return 0 on success. otherwise on failure.
- *
- */
-int al_eth_rx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_rx_gcp_table_entry *rx_gcp_entry);
-
-/**
- * Configure tx_gpd_table and regs
- *
- * @param adapter pointer to the private structure
- *
- */
-int al_eth_tx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter);
-
-/**
- * Configure crc_chksum_replace_cmd_table
- *
- * @param adapter pointer to the private structure
- *
- */
-int al_eth_tx_crc_chksum_replace_cmd_init(struct al_hal_eth_adapter *adapter);
-
-/**
- * Configure tx_gcp_table and regs
- *
- * @param adapter pointer to the private structure
- *
- */
-int al_eth_tx_generic_crc_table_init(struct al_hal_eth_adapter *adapter);
-
-/**
- * Configure rx_gpd_table and regs
- *
- * @param adapter pointer to the private structure
- *
- */
-int al_eth_rx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter);
-
-/**
- * Configure rx_gcp_table and regs
- *
- * @param adapter pointer to the private structure
- *
- */
-int al_eth_rx_generic_crc_table_init(struct al_hal_eth_adapter *adapter);
-
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-#endif		/* __AL_HAL_ETH_H__ */
-/** @} end of Ethernet group */
diff --git a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_alu.h b/sys/contrib/alpine-hal/eth/eth/al_hal_eth_alu.h
deleted file mode 100644
index 2f5f1fa2301e..000000000000
--- a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_alu.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-*     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-*     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- * @defgroup group_eth_alu_api API
- * Ethernet Controller generic ALU API
- * @ingroup group_eth
- * @{
- * @file   al_hal_eth_alu.h
- *
- * @brief Header file for control parameters for the generic ALU unit in the Ethernet Datapath for Advanced Ethernet port.
- *
- */
-
-#ifndef __AL_HAL_ETH_ALU_H__
-#define __AL_HAL_ETH_ALU_H__
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-enum AL_ETH_ALU_OPCODE
-{
-	AL_ALU_FWD_A                            = 0,
-	AL_ALU_ARITHMETIC_ADD                   = 1,
-	AL_ALU_ARITHMETIC_SUBTRACT              = 2,
-	AL_ALU_BITWISE_AND                      = 3,
-	AL_ALU_BITWISE_OR                       = 4,
-	AL_ALU_SHIFT_RIGHT_A_BY_B               = 5,
-	AL_ALU_SHIFT_LEFT_A_BY_B                = 6,
-	AL_ALU_BITWISE_XOR                      = 7,
-	AL_ALU_FWD_INV_A                        = 16,
-	AL_ALU_ARITHMETIC_ADD_INV_A_AND_B       = 17,
-	AL_ALU_ARITHMETIC_SUBTRACT_INV_A_AND_B  = 18,
-	AL_ALU_BITWISE_AND_INV_A_AND_B          = 19,
-	AL_ALU_BITWISE_OR_INV_A_AND_B           = 20,
-	AL_ALU_SHIFT_RIGHT_INV_A_BY_B           = 21,
-	AL_ALU_SHIFT_LEFT_INV_A_BY_B            = 22,
-	AL_ALU_BITWISE_XOR_INV_A_AND_B          = 23,
-	AL_ALU_ARITHMETIC_ADD_A_AND_INV_B       = 33,
-	AL_ALU_ARITHMETIC_SUBTRACT_A_AND_INV_B  = 34,
-	AL_ALU_BITWISE_AND_A_AND_INV_B          = 35,
-	AL_ALU_BITWISE_OR_A_AND_INV_B           = 36,
-	AL_ALU_SHIFT_RIGHT_A_BY_INV_B           = 37,
-	AL_ALU_SHIFT_LEFT_A_BY_INV_B            = 38,
-	AL_ALU_BITWISE_XOR_A_AND_INV_B          = 39,
-	AL_ALU_ARITHMETIC_ADD_INV_A_AND_INV_B   = 49,
-	AL_ALU_ARITHMETIC_SUBTRACT_INV_A_AND    = 50,
-	AL_ALU_BITWISE_AND_INV_A_AND_INV_B      = 51,
-	AL_ALU_BITWISE_OR_INV_A_AND_INV_B       = 52,
-	AL_ALU_SHIFT_RIGHT_INV_A_BY_INV_B       = 53,
-	AL_ALU_SHIFT_LEFT_INV_A_BY_INV_B        = 54,
-	AL_ALU_BITWISE_XOR_INV_A_AND_INV_B      = 55
-};
-
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-#endif /* __AL_HAL_ETH_ALU_H__ */
-/** @} end of Ethernet group */
diff --git a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_ec_regs.h b/sys/contrib/alpine-hal/eth/eth/al_hal_eth_ec_regs.h
deleted file mode 100644
index 153e0d57a452..000000000000
--- a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_ec_regs.h
+++ /dev/null
@@ -1,3362 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_eth_ec_regs.h
- *
- * @brief Ethernet controller registers
- *
- */
-
-#ifndef __AL_HAL_EC_REG_H
-#define __AL_HAL_EC_REG_H
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-
-
-struct al_ec_gen {
-	/* [0x0] Ethernet controller Version */
-	uint32_t version;
-	/* [0x4] Enable modules operation. */
-	uint32_t en;
-	/* [0x8] Enable FIFO operation on the EC side. */
-	uint32_t fifo_en;
-	/* [0xc] General L2 configuration for the Ethernet controlle ... */
-	uint32_t l2;
-	/* [0x10] Configure protocol index values */
-	uint32_t cfg_i;
-	/* [0x14] Configure protocol index values (extended protocols ... */
-	uint32_t cfg_i_ext;
-	/* [0x18] Enable modules operation (extended operations). */
-	uint32_t en_ext;
-	uint32_t rsrvd[9];
-};
-struct al_ec_mac {
-	/* [0x0] General configuration of the MAC side of the Ethern ... */
-	uint32_t gen;
-	/* [0x4] Minimum packet size  */
-	uint32_t min_pkt;
-	/* [0x8] Maximum packet size  */
-	uint32_t max_pkt;
-	uint32_t rsrvd[13];
-};
-struct al_ec_rxf {
-	/* [0x0] Rx FIFO input controller configuration 1 */
-	uint32_t cfg_1;
-	/* [0x4] Rx FIFO input controller configuration 2 */
-	uint32_t cfg_2;
-	/* [0x8] Threshold to start reading packet from the Rx FIFO */
-	uint32_t rd_fifo;
-	/* [0xc] Threshold to stop writing packet to the Rx FIFO */
-	uint32_t wr_fifo;
-	/* [0x10] Threshold to stop writing packet to the loopback FI ... */
-	uint32_t lb_fifo;
-	/* [0x14] Rx FIFO input controller loopback FIFO configuratio ... */
-	uint32_t cfg_lb;
-	/* [0x18] Configuration for dropping packet at the FIFO outpu ... */
-	uint32_t out_drop;
-	uint32_t rsrvd[25];
-};
-struct al_ec_epe {
-	/* [0x0] Ethernet parsing engine configuration 1 */
-	uint32_t parse_cfg;
-	/* [0x4] Protocol index action table address */
-	uint32_t act_table_addr;
-	/* [0x8] Protocol index action table data */
-	uint32_t act_table_data_1;
-	/* [0xc] Protocol index action table data */
-	uint32_t act_table_data_2;
-	/* [0x10] Protocol index action table data */
-	uint32_t act_table_data_3;
-	/* [0x14] Protocol index action table data */
-	uint32_t act_table_data_4;
-	/* [0x18] Protocol index action table data */
-	uint32_t act_table_data_5;
-	/* [0x1c] Protocol index action table data */
-	uint32_t act_table_data_6;
-	/* [0x20] Input result vector, default values for parser inpu ... */
-	uint32_t res_def;
-	/* [0x24] Result input vector selection */
-	uint32_t res_in;
-	uint32_t rsrvd[6];
-};
-struct al_ec_epe_res {
-	/* [0x0] Parser result vector pointer */
-	uint32_t p1;
-	/* [0x4] Parser result vector pointer */
-	uint32_t p2;
-	/* [0x8] Parser result vector pointer */
-	uint32_t p3;
-	/* [0xc] Parser result vector pointer */
-	uint32_t p4;
-	/* [0x10] Parser result vector pointer */
-	uint32_t p5;
-	/* [0x14] Parser result vector pointer */
-	uint32_t p6;
-	/* [0x18] Parser result vector pointer */
-	uint32_t p7;
-	/* [0x1c] Parser result vector pointer */
-	uint32_t p8;
-	/* [0x20] Parser result vector pointer */
-	uint32_t p9;
-	/* [0x24] Parser result vector pointer */
-	uint32_t p10;
-	/* [0x28] Parser result vector pointer */
-	uint32_t p11;
-	/* [0x2c] Parser result vector pointer */
-	uint32_t p12;
-	/* [0x30] Parser result vector pointer */
-	uint32_t p13;
-	/* [0x34] Parser result vector pointer */
-	uint32_t p14;
-	/* [0x38] Parser result vector pointer */
-	uint32_t p15;
-	/* [0x3c] Parser result vector pointer */
-	uint32_t p16;
-	/* [0x40] Parser result vector pointer */
-	uint32_t p17;
-	/* [0x44] Parser result vector pointer */
-	uint32_t p18;
-	/* [0x48] Parser result vector pointer */
-	uint32_t p19;
-	/* [0x4c] Parser result vector pointer */
-	uint32_t p20;
-	uint32_t rsrvd[12];
-};
-struct al_ec_epe_h {
-	/* [0x0] Header length, support for header length table for  ... */
-	uint32_t hdr_len;
-};
-struct al_ec_epe_p {
-	/* [0x0] Data  for comparison */
-	uint32_t comp_data;
-	/* [0x4] Mask for comparison */
-	uint32_t comp_mask;
-	/* [0x8] Compare control */
-	uint32_t comp_ctrl;
-	uint32_t rsrvd[4];
-};
-struct al_ec_epe_a {
-	/* [0x0] Protocol index action register */
-	uint32_t prot_act;
-};
-struct al_ec_rfw {
-	/* [0x0] Tuple (4/2) Hash configuration */
-	uint32_t thash_cfg_1;
-	/* [0x4] Tuple (4/2) Hash configuration */
-	uint32_t thash_cfg_2;
-	/* [0x8] MAC Hash configuration */
-	uint32_t mhash_cfg_1;
-	/* [0xc] MAC Hash configuration */
-	uint32_t mhash_cfg_2;
-	/* [0x10] MAC Hash configuration */
-	uint32_t hdr_split;
-	/* [0x14] Masking the errors described in  register rxf_drop  ... */
-	uint32_t meta_err;
-	/* [0x18] Configuration for generating the MetaData for the R ... */
-	uint32_t meta;
-	/* [0x1c] Configuration for generating the MetaData for the R ... */
-	uint32_t filter;
-	/* [0x20] 4 tupple hash table address */
-	uint32_t thash_table_addr;
-	/* [0x24] 4 tupple hash table data */
-	uint32_t thash_table_data;
-	/* [0x28] MAC hash table address */
-	uint32_t mhash_table_addr;
-	/* [0x2c] MAC hash table data */
-	uint32_t mhash_table_data;
-	/* [0x30] VLAN table address */
-	uint32_t vid_table_addr;
-	/* [0x34] VLAN table data */
-	uint32_t vid_table_data;
-	/* [0x38] VLAN p-bits table address */
-	uint32_t pbits_table_addr;
-	/* [0x3c] VLAN p-bits table data */
-	uint32_t pbits_table_data;
-	/* [0x40] DSCP table address */
-	uint32_t dscp_table_addr;
-	/* [0x44] DSCP table data */
-	uint32_t dscp_table_data;
-	/* [0x48] TC table address */
-	uint32_t tc_table_addr;
-	/* [0x4c] TC table data */
-	uint32_t tc_table_data;
-	/* [0x50] Control table address */
-	uint32_t ctrl_table_addr;
-	/* [0x54] Control table data */
-	uint32_t ctrl_table_data;
-	/* [0x58] Forwarding output configuration */
-	uint32_t out_cfg;
-	/* [0x5c] Flow steering mechanism,
-Table address */
-	uint32_t fsm_table_addr;
-	/* [0x60] Flow steering mechanism,
-Table data */
-	uint32_t fsm_table_data;
-	/* [0x64] Selection of data to be used in packet forwarding0  ... */
-	uint32_t ctrl_sel;
-	/* [0x68] Default VLAN data, used for untagged packets */
-	uint32_t default_vlan;
-	/* [0x6c] Default HASH output values */
-	uint32_t default_hash;
-	/* [0x70] Default override values, if a packet was filtered b ... */
-	uint32_t default_or;
-	/* [0x74] Latched information when a drop condition occurred */
-	uint32_t drop_latch;
-	/* [0x78] Check sum calculation configuration */
-	uint32_t checksum;
-	/* [0x7c] LRO offload engine configuration register */
-	uint32_t lro_cfg_1;
-	/* [0x80] LRO offload engine Check rules configurations for I ... */
-	uint32_t lro_check_ipv4;
-	/* [0x84] LRO offload engine IPv4 values configuration */
-	uint32_t lro_ipv4;
-	/* [0x88] LRO offload engine Check rules configurations for I ... */
-	uint32_t lro_check_ipv6;
-	/* [0x8c] LRO offload engine IPv6 values configuration */
-	uint32_t lro_ipv6;
-	/* [0x90] LRO offload engine Check rules configurations for T ... */
-	uint32_t lro_check_tcp;
-	/* [0x94] LRO offload engine IPv6 values configuration */
-	uint32_t lro_tcp;
-	/* [0x98] LRO offload engine Check rules configurations for U ... */
-	uint32_t lro_check_udp;
-	/* [0x9c] LRO offload engine Check rules configurations for U ... */
-	uint32_t lro_check_l2;
-	/* [0xa0] LRO offload engine Check rules configurations for U ... */
-	uint32_t lro_check_gen;
-	/* [0xa4] Rules for storing packet information into the cache ... */
-	uint32_t lro_store;
-	/* [0xa8] VLAN table default */
-	uint32_t vid_table_def;
-	/* [0xac] Control table default */
-	uint32_t ctrl_table_def;
-	/* [0xb0] Additional configuration 0 */
-	uint32_t cfg_a_0;
-	/* [0xb4] Tuple (4/2) Hash configuration (extended for RoCE a ... */
-	uint32_t thash_cfg_3;
-	/* [0xb8] Tuple (4/2) Hash configuration , mask for the input ... */
-	uint32_t thash_mask_outer_ipv6;
-	/* [0xbc] Tuple (4/2) Hash configuration , mask for the input ... */
-	uint32_t thash_mask_outer;
-	/* [0xc0] Tuple (4/2) Hash configuration , mask for the input ... */
-	uint32_t thash_mask_inner_ipv6;
-	/* [0xc4] Tuple (4/2) Hash configuration , mask for the input ... */
-	uint32_t thash_mask_inner;
-	uint32_t rsrvd[10];
-};
-struct al_ec_rfw_udma {
-	/* [0x0] Per UDMA default configuration */
-	uint32_t def_cfg;
-};
-struct al_ec_rfw_hash {
-	/* [0x0] key configuration (320 bits) */
-	uint32_t key;
-};
-struct al_ec_rfw_priority {
-	/* [0x0] Priority to queue mapping configuration */
-	uint32_t queue;
-};
-struct al_ec_rfw_default {
-	/* [0x0] Default forwarding configuration options */
-	uint32_t opt_1;
-};
-struct al_ec_fwd_mac {
-	/* [0x0] MAC address data [31:0] */
-	uint32_t data_l;
-	/* [0x4] MAC address data [15:0] */
-	uint32_t data_h;
-	/* [0x8] MAC address mask [31:0] */
-	uint32_t mask_l;
-	/* [0xc] MAC address mask [15:0] */
-	uint32_t mask_h;
-	/* [0x10] MAC compare control */
-	uint32_t ctrl;
-};
-struct al_ec_msw {
-	/* [0x0] Configuration for unicast packets */
-	uint32_t uc;
-	/* [0x4] Configuration for multicast packets */
-	uint32_t mc;
-	/* [0x8] Configuration for broadcast packets */
-	uint32_t bc;
-	uint32_t rsrvd[3];
-};
-struct al_ec_tso {
-	/* [0x0] Input configuration */
-	uint32_t in_cfg;
-	/* [0x4] MetaData default cache table address */
-	uint32_t cache_table_addr;
-	/* [0x8] MetaData default cache table data */
-	uint32_t cache_table_data_1;
-	/* [0xc] MetaData default cache table data */
-	uint32_t cache_table_data_2;
-	/* [0x10] MetaData default cache table data */
-	uint32_t cache_table_data_3;
-	/* [0x14] MetaData default cache table data */
-	uint32_t cache_table_data_4;
-	/* [0x18] TCP control bit operation for first segment */
-	uint32_t ctrl_first;
-	/* [0x1c] TCP control bit operation for middle segments  */
-	uint32_t ctrl_middle;
-	/* [0x20] TCP control bit operation for last segment */
-	uint32_t ctrl_last;
-	/* [0x24] Additional TSO configurations */
-	uint32_t cfg_add_0;
-	/* [0x28] TSO configuration for tunnelled packets */
-	uint32_t cfg_tunnel;
-	uint32_t rsrvd[13];
-};
-struct al_ec_tso_sel {
-	/* [0x0] MSS value */
-	uint32_t mss;
-};
-struct al_ec_tpe {
-	/* [0x0] Parsing configuration */
-	uint32_t parse;
-	uint32_t rsrvd[15];
-};
-struct al_ec_tpm_udma {
-	/* [0x0] Default VLAN data */
-	uint32_t vlan_data;
-	/* [0x4] UDMA MAC SA information for spoofing */
-	uint32_t mac_sa_1;
-	/* [0x8] UDMA MAC SA information for spoofing */
-	uint32_t mac_sa_2;
-};
-struct al_ec_tpm_sel {
-	/* [0x0] Ethertype values for VLAN modification */
-	uint32_t etype;
-};
-struct al_ec_tfw {
-	/* [0x0] Tx FIFO Wr configuration */
-	uint32_t tx_wr_fifo;
-	/* [0x4] VLAN table address */
-	uint32_t tx_vid_table_addr;
-	/* [0x8] VLAN table data */
-	uint32_t tx_vid_table_data;
-	/* [0xc] Tx FIFO Rd configuration */
-	uint32_t tx_rd_fifo;
-	/* [0x10] Tx FIFO Rd configuration, checksum insertion */
-	uint32_t tx_checksum;
-	/* [0x14] Tx forwarding general configuration register */
-	uint32_t tx_gen;
-	/* [0x18] Tx spoofing configuration */
-	uint32_t tx_spf;
-	/* [0x1c] TX data FIFO status */
-	uint32_t data_fifo;
-	/* [0x20] Tx control FIFO status */
-	uint32_t ctrl_fifo;
-	/* [0x24] Tx header FIFO status */
-	uint32_t hdr_fifo;
-	uint32_t rsrvd[14];
-};
-struct al_ec_tfw_udma {
-	/* [0x0] Default GMDA output bitmap for unicast packet */
-	uint32_t uc_udma;
-	/* [0x4] Default GMDA output bitmap for multicast packet */
-	uint32_t mc_udma;
-	/* [0x8] Default GMDA output bitmap for broadcast packet */
-	uint32_t bc_udma;
-	/* [0xc] Tx spoofing configuration */
-	uint32_t spf_cmd;
-	/* [0x10] Forwarding decision control */
-	uint32_t fwd_dec;
-	uint32_t rsrvd;
-};
-struct al_ec_tmi {
-	/* [0x0] Forward packets back to the Rx data path for local  ... */
-	uint32_t tx_cfg;
-	uint32_t rsrvd[3];
-};
-struct al_ec_efc {
-	/* [0x0] Mask of pause_on  [7:0] for the Ethernet controller ... */
-	uint32_t ec_pause;
-	/* [0x4] Mask of Ethernet controller Almost Full indication  ... */
-	uint32_t ec_xoff;
-	/* [0x8] Mask for generating XON indication pulse */
-	uint32_t xon;
-	/* [0xc] Mask for generating GPIO output XOFF indication fro ... */
-	uint32_t gpio;
-	/* [0x10] Rx FIFO threshold for generating the Almost Full in ... */
-	uint32_t rx_fifo_af;
-	/* [0x14] Rx FIFO threshold for generating the Almost Full in ... */
-	uint32_t rx_fifo_hyst;
-	/* [0x18] Rx FIFO threshold for generating the Almost Full in ... */
-	uint32_t stat;
-	/* [0x1c] XOFF timer for the 1G MACSets the interval (in SB_C ... */
-	uint32_t xoff_timer_1g;
-	/* [0x20] PFC force flow control generation */
-	uint32_t ec_pfc;
-	uint32_t rsrvd[3];
-};
-struct al_ec_fc_udma {
-	/* [0x0] Mask of "pause_on"  [0] for all queues */
-	uint32_t q_pause_0;
-	/* [0x4] Mask of "pause_on"  [1] for all queues */
-	uint32_t q_pause_1;
-	/* [0x8] Mask of "pause_on"  [2] for all queues */
-	uint32_t q_pause_2;
-	/* [0xc] Mask of "pause_on"  [3] for all queues */
-	uint32_t q_pause_3;
-	/* [0x10] Mask of "pause_on"  [4] for all queues */
-	uint32_t q_pause_4;
-	/* [0x14] Mask of "pause_on"  [5] for all queues */
-	uint32_t q_pause_5;
-	/* [0x18] Mask of "pause_on"  [6] for all queues */
-	uint32_t q_pause_6;
-	/* [0x1c] Mask of "pause_on"  [7] for all queues */
-	uint32_t q_pause_7;
-	/* [0x20] Mask of external GPIO input pause [0] for all queue ... */
-	uint32_t q_gpio_0;
-	/* [0x24] Mask of external GPIO input pause [1] for all queue ... */
-	uint32_t q_gpio_1;
-	/* [0x28] Mask of external GPIO input pause [2] for all queue ... */
-	uint32_t q_gpio_2;
-	/* [0x2c] Mask of external GPIO input pause [3] for all queue ... */
-	uint32_t q_gpio_3;
-	/* [0x30] Mask of external GPIO input [4] for all queues */
-	uint32_t q_gpio_4;
-	/* [0x34] Mask of external GPIO input [5] for all queues */
-	uint32_t q_gpio_5;
-	/* [0x38] Mask of external GPIO input [6] for all queues */
-	uint32_t q_gpio_6;
-	/* [0x3c] Mask of external GPIO input [7] for all queues */
-	uint32_t q_gpio_7;
-	/* [0x40] Mask of "pause_on"  [7:0] for the UDMA stream inter ... */
-	uint32_t s_pause;
-	/* [0x44] Mask of Rx Almost Full indication for generating XO ... */
-	uint32_t q_xoff_0;
-	/* [0x48] Mask of Rx Almost Full indication for generating XO ... */
-	uint32_t q_xoff_1;
-	/* [0x4c] Mask of Rx Almost Full indication for generating XO ... */
-	uint32_t q_xoff_2;
-	/* [0x50] Mask of Rx Almost Full indication for generating XO ... */
-	uint32_t q_xoff_3;
-	/* [0x54] Mask of Rx Almost Full indication for generating XO ... */
-	uint32_t q_xoff_4;
-	/* [0x58] Mask of Rx Almost Full indication for generating XO ... */
-	uint32_t q_xoff_5;
-	/* [0x5c] Mask of Rx Almost Full indication for generating XO ... */
-	uint32_t q_xoff_6;
-	/* [0x60] Mask of Rx Almost Full indication for generating XO ... */
-	uint32_t q_xoff_7;
-	uint32_t rsrvd[7];
-};
-struct al_ec_tpg_rpa_res {
-	/* [0x0] NOT used */
-	uint32_t not_used;
-	uint32_t rsrvd[63];
-};
-struct al_ec_eee {
-	/* [0x0] EEE configuration */
-	uint32_t cfg_e;
-	/* [0x4] Number of clocks to get into EEE mode. */
-	uint32_t pre_cnt;
-	/* [0x8] Number of clocks to stop MAC EEE mode after getting ... */
-	uint32_t post_cnt;
-	/* [0xc] Number of clocks to stop the Tx MAC interface after ... */
-	uint32_t stop_cnt;
-	/* [0x10] EEE status */
-	uint32_t stat_eee;
-	uint32_t rsrvd[59];
-};
-struct al_ec_stat {
-	/* [0x0] Rx Frequency adjust FIFO input  packets */
-	uint32_t faf_in_rx_pkt;
-	/* [0x4] Rx Frequency adjust FIFO input short error packets */
-	uint32_t faf_in_rx_short;
-	/* [0x8] Rx Frequency adjust FIFO input  long error packets */
-	uint32_t faf_in_rx_long;
-	/* [0xc] Rx Frequency adjust FIFO output  packets */
-	uint32_t faf_out_rx_pkt;
-	/* [0x10] Rx Frequency adjust FIFO output short error packets ... */
-	uint32_t faf_out_rx_short;
-	/* [0x14] Rx Frequency adjust FIFO output long error packets */
-	uint32_t faf_out_rx_long;
-	/* [0x18] Rx Frequency adjust FIFO output  drop packets */
-	uint32_t faf_out_drop;
-	/* [0x1c] Number of packets written into the Rx FIFO (without ... */
-	uint32_t rxf_in_rx_pkt;
-	/* [0x20] Number of error packets written into the Rx FIFO (w ... */
-	uint32_t rxf_in_fifo_err;
-	/* [0x24] Number of packets written into the loopback FIFO (w ... */
-	uint32_t lbf_in_rx_pkt;
-	/* [0x28] Number of error packets written into the loopback F ... */
-	uint32_t lbf_in_fifo_err;
-	/* [0x2c] Number of packets read from Rx FIFO 1 */
-	uint32_t rxf_out_rx_1_pkt;
-	/* [0x30] Number of packets read from Rx FIFO 2 (loopback FIF ... */
-	uint32_t rxf_out_rx_2_pkt;
-	/* [0x34] Rx FIFO output drop packets from FIFO 1 */
-	uint32_t rxf_out_drop_1_pkt;
-	/* [0x38] Rx FIFO output drop packets from FIFO 2 (loopback) */
-	uint32_t rxf_out_drop_2_pkt;
-	/* [0x3c] Rx Parser 1, input packet counter */
-	uint32_t rpe_1_in_rx_pkt;
-	/* [0x40] Rx Parser 1, output packet counter */
-	uint32_t rpe_1_out_rx_pkt;
-	/* [0x44] Rx Parser 2, input packet counter */
-	uint32_t rpe_2_in_rx_pkt;
-	/* [0x48] Rx Parser 2, output packet counter */
-	uint32_t rpe_2_out_rx_pkt;
-	/* [0x4c] Rx Parser 3 (MACsec), input packet counter */
-	uint32_t rpe_3_in_rx_pkt;
-	/* [0x50] Rx Parser 3 (MACsec), output packet counter */
-	uint32_t rpe_3_out_rx_pkt;
-	/* [0x54] Tx parser, input packet counter */
-	uint32_t tpe_in_tx_pkt;
-	/* [0x58] Tx parser, output packet counter */
-	uint32_t tpe_out_tx_pkt;
-	/* [0x5c] Tx packet modification, input packet counter */
-	uint32_t tpm_tx_pkt;
-	/* [0x60] Tx forwarding input packet counter */
-	uint32_t tfw_in_tx_pkt;
-	/* [0x64] Tx forwarding input packet counter */
-	uint32_t tfw_out_tx_pkt;
-	/* [0x68] Rx forwarding input packet counter */
-	uint32_t rfw_in_rx_pkt;
-	/* [0x6c] Rx Forwarding, packet with VLAN command drop indica ... */
-	uint32_t rfw_in_vlan_drop;
-	/* [0x70] Rx Forwarding, packets with parse drop indication */
-	uint32_t rfw_in_parse_drop;
-	/* [0x74] Rx Forwarding, multicast packets */
-	uint32_t rfw_in_mc;
-	/* [0x78] Rx Forwarding, broadcast packets */
-	uint32_t rfw_in_bc;
-	/* [0x7c] Rx Forwarding, tagged packets */
-	uint32_t rfw_in_vlan_exist;
-	/* [0x80] Rx Forwarding, untagged packets */
-	uint32_t rfw_in_vlan_nexist;
-	/* [0x84] Rx Forwarding, packets with MAC address drop indica ... */
-	uint32_t rfw_in_mac_drop;
-	/* [0x88] Rx Forwarding, packets with undetected MAC address */
-	uint32_t rfw_in_mac_ndet_drop;
-	/* [0x8c] Rx Forwarding, packets with drop indication from th ... */
-	uint32_t rfw_in_ctrl_drop;
-	/* [0x90] Rx Forwarding, packets with L3_protocol_index drop  ... */
-	uint32_t rfw_in_prot_i_drop;
-	/* [0x94] EEE, number of times the system went into EEE state ... */
-	uint32_t eee_in;
-	uint32_t rsrvd[90];
-};
-struct al_ec_stat_udma {
-	/* [0x0] Rx forwarding output packet counter */
-	uint32_t rfw_out_rx_pkt;
-	/* [0x4] Rx forwarding output drop packet counter */
-	uint32_t rfw_out_drop;
-	/* [0x8] Multi-stream write, number of Rx packets */
-	uint32_t msw_in_rx_pkt;
-	/* [0xc] Multi-stream write, number of dropped packets at SO ... */
-	uint32_t msw_drop_q_full;
-	/* [0x10] Multi-stream write, number of dropped packets at SO ... */
-	uint32_t msw_drop_sop;
-	/* [0x14] Multi-stream write, number of dropped packets at EO ... */
-	uint32_t msw_drop_eop;
-	/* [0x18] Multi-stream write, number of packets written to th ... */
-	uint32_t msw_wr_eop;
-	/* [0x1c] Multi-stream write, number of packets read from the ... */
-	uint32_t msw_out_rx_pkt;
-	/* [0x20] Number of transmitted packets without TSO enabled */
-	uint32_t tso_no_tso_pkt;
-	/* [0x24] Number of transmitted packets with TSO enabled */
-	uint32_t tso_tso_pkt;
-	/* [0x28] Number of TSO segments that were generated */
-	uint32_t tso_seg_pkt;
-	/* [0x2c] Number of TSO segments that required padding */
-	uint32_t tso_pad_pkt;
-	/* [0x30] Tx Packet modification, MAC SA spoof error  */
-	uint32_t tpm_tx_spoof;
-	/* [0x34] Tx MAC interface, input packet counter */
-	uint32_t tmi_in_tx_pkt;
-	/* [0x38] Tx MAC interface, number of packets forwarded to th ... */
-	uint32_t tmi_out_to_mac;
-	/* [0x3c] Tx MAC interface, number of packets forwarded to th ... */
-	uint32_t tmi_out_to_rx;
-	/* [0x40] Tx MAC interface, number of transmitted bytes */
-	uint32_t tx_q0_bytes;
-	/* [0x44] Tx MAC interface, number of transmitted bytes */
-	uint32_t tx_q1_bytes;
-	/* [0x48] Tx MAC interface, number of transmitted bytes */
-	uint32_t tx_q2_bytes;
-	/* [0x4c] Tx MAC interface, number of transmitted bytes */
-	uint32_t tx_q3_bytes;
-	/* [0x50] Tx MAC interface, number of transmitted packets */
-	uint32_t tx_q0_pkts;
-	/* [0x54] Tx MAC interface, number of transmitted packets */
-	uint32_t tx_q1_pkts;
-	/* [0x58] Tx MAC interface, number of transmitted packets */
-	uint32_t tx_q2_pkts;
-	/* [0x5c] Tx MAC interface, number of transmitted packets */
-	uint32_t tx_q3_pkts;
-	uint32_t rsrvd[40];
-};
-struct al_ec_msp {
-	/* [0x0] Ethernet parsing engine configuration 1 */
-	uint32_t p_parse_cfg;
-	/* [0x4] Protocol index action table address */
-	uint32_t p_act_table_addr;
-	/* [0x8] Protocol index action table data */
-	uint32_t p_act_table_data_1;
-	/* [0xc] Protocol index action table data */
-	uint32_t p_act_table_data_2;
-	/* [0x10] Protocol index action table data */
-	uint32_t p_act_table_data_3;
-	/* [0x14] Protocol index action table data */
-	uint32_t p_act_table_data_4;
-	/* [0x18] Protocol index action table data */
-	uint32_t p_act_table_data_5;
-	/* [0x1c] Protocol index action table data */
-	uint32_t p_act_table_data_6;
-	/* [0x20] Input result vector, default values for parser inpu ... */
-	uint32_t p_res_def;
-	/* [0x24] Result input vector selection */
-	uint32_t p_res_in;
-	uint32_t rsrvd[6];
-};
-struct al_ec_msp_p {
-	/* [0x0] Header length, support for header length table for  ... */
-	uint32_t h_hdr_len;
-};
-struct al_ec_msp_c {
-	/* [0x0] Data  for comparison */
-	uint32_t p_comp_data;
-	/* [0x4] Mask for comparison */
-	uint32_t p_comp_mask;
-	/* [0x8] Compare control */
-	uint32_t p_comp_ctrl;
-	uint32_t rsrvd[4];
-};
-struct al_ec_wol {
-	/* [0x0] WoL enable configuration,Packet forwarding and inte ... */
-	uint32_t wol_en;
-	/* [0x4] Password for magic_password packet detection - bits ... */
-	uint32_t magic_pswd_l;
-	/* [0x8] Password for magic+password packet detection -  47: ... */
-	uint32_t magic_pswd_h;
-	/* [0xc] Configured L3 Destination IP address for WoL IPv6 p ... */
-	uint32_t ipv6_dip_word0;
-	/* [0x10] Configured L3 Destination IP address for WoL IPv6 p ... */
-	uint32_t ipv6_dip_word1;
-	/* [0x14] Configured L3 Destination IP address for WoL IPv6 p ... */
-	uint32_t ipv6_dip_word2;
-	/* [0x18] Configured L3 Destination IP address for WoL IPv6 p ... */
-	uint32_t ipv6_dip_word3;
-	/* [0x1c] Configured L3 Destination IP address for WoL IPv4 p ... */
-	uint32_t ipv4_dip;
-	/* [0x20] Configured EtherType for WoL EtherType_da/EtherType ... */
-	uint32_t ethertype;
-	uint32_t rsrvd[7];
-};
-struct al_ec_pth {
-	/* [0x0] System time counter (Time of Day) */
-	uint32_t system_time_seconds;
-	/* [0x4] System time subseconds in a second (MSBs) */
-	uint32_t system_time_subseconds_msb;
-	/* [0x8] System time subseconds in a second (LSBs) */
-	uint32_t system_time_subseconds_lsb;
-	/* [0xc] Clock period in femtoseconds (MSB) */
-	uint32_t clock_period_msb;
-	/* [0x10] Clock period in femtoseconds (LSB) */
-	uint32_t clock_period_lsb;
-	/* [0x14] Control register for internal updates to the system ... */
-	uint32_t int_update_ctrl;
-	/* [0x18] Value to update system_time_seconds with */
-	uint32_t int_update_seconds;
-	/* [0x1c] Value to update system_time_subseconds_msb with */
-	uint32_t int_update_subseconds_msb;
-	/* [0x20] Value to update system_time_subseconds_lsb with */
-	uint32_t int_update_subseconds_lsb;
-	/* [0x24] Control register for external updates to the system ... */
-	uint32_t ext_update_ctrl;
-	/* [0x28] Value to update system_time_seconds with */
-	uint32_t ext_update_seconds;
-	/* [0x2c] Value to update system_time_subseconds_msb with */
-	uint32_t ext_update_subseconds_msb;
-	/* [0x30] Value to update system_time_subseconds_lsb with */
-	uint32_t ext_update_subseconds_lsb;
-	/* [0x34] This value represents the APB transaction delay fro ... */
-	uint32_t read_compensation_subseconds_msb;
-	/* [0x38] This value represents the APB transaction delay fro ... */
-	uint32_t read_compensation_subseconds_lsb;
-	/* [0x3c] This value is used for two purposes:1 */
-	uint32_t int_write_compensation_subseconds_msb;
-	/* [0x40] This value is used for two purposes:1 */
-	uint32_t int_write_compensation_subseconds_lsb;
-	/* [0x44] This value represents the number of cycles it for a ... */
-	uint32_t ext_write_compensation_subseconds_msb;
-	/* [0x48] This value represents the number of cycles it for a ... */
-	uint32_t ext_write_compensation_subseconds_lsb;
-	/* [0x4c] Value to be added to system_time before transferrin ... */
-	uint32_t sync_compensation_subseconds_msb;
-	/* [0x50] Value to be added to system_time before transferrin ... */
-	uint32_t sync_compensation_subseconds_lsb;
-	uint32_t rsrvd[11];
-};
-struct al_ec_pth_egress {
-	/* [0x0] Control register for egress trigger #k */
-	uint32_t trigger_ctrl;
-	/* [0x4] threshold for next egress trigger (#k) - secondsWri ... */
-	uint32_t trigger_seconds;
-	/* [0x8] Threshold for next egress trigger (#k) - subseconds ... */
-	uint32_t trigger_subseconds_msb;
-	/* [0xc] threshold for next egress trigger (#k) - subseconds ... */
-	uint32_t trigger_subseconds_lsb;
-	/* [0x10] External output pulse width (subseconds_msb)(Atomic ... */
-	uint32_t pulse_width_subseconds_msb;
-	/* [0x14] External output pulse width (subseconds_lsb)(Atomic ... */
-	uint32_t pulse_width_subseconds_lsb;
-	uint32_t rsrvd[2];
-};
-struct al_ec_pth_db {
-	/* [0x0] timestamp[k], in resolution of 2^18 femtosec =~ 0 */
-	uint32_t ts;
-	/* [0x4] Timestamp entry is valid */
-	uint32_t qual;
-	uint32_t rsrvd[4];
-};
-struct al_ec_gen_v3 {
-	/* [0x0] Bypass enable */
-	uint32_t bypass;
-	/* [0x4] Rx Completion descriptor */
-	uint32_t rx_comp_desc;
-	/* [0x8] general configuration */
-	uint32_t conf;
-	uint32_t rsrvd[13];
-};
-struct al_ec_tfw_v3 {
-	/* [0x0] Generic protocol detect Cam compare table address */
-	uint32_t tx_gpd_cam_addr;
-	/* [0x4] Tx Generic protocol detect Cam compare data_1 (low) ... */
-	uint32_t tx_gpd_cam_data_1;
-	/* [0x8] Tx Generic protocol detect Cam compare data_2 (high ... */
-	uint32_t tx_gpd_cam_data_2;
-	/* [0xc] Tx Generic protocol detect Cam compare mask_1 (low) ... */
-	uint32_t tx_gpd_cam_mask_1;
-	/* [0x10] Tx Generic protocol detect Cam compare mask_1 (high ... */
-	uint32_t tx_gpd_cam_mask_2;
-	/* [0x14] Tx Generic protocol detect Cam compare control */
-	uint32_t tx_gpd_cam_ctrl;
-	/* [0x18] Tx Generic crc parameters legacy */
-	uint32_t tx_gcp_legacy;
-	/* [0x1c] Tx Generic crc prameters table address */
-	uint32_t tx_gcp_table_addr;
-	/* [0x20] Tx Generic crc prameters table general */
-	uint32_t tx_gcp_table_gen;
-	/* [0x24] Tx Generic crc parametrs tabel mask word 1 */
-	uint32_t tx_gcp_table_mask_1;
-	/* [0x28] Tx Generic crc parametrs tabel mask word 2 */
-	uint32_t tx_gcp_table_mask_2;
-	/* [0x2c] Tx Generic crc parametrs tabel mask word 3 */
-	uint32_t tx_gcp_table_mask_3;
-	/* [0x30] Tx Generic crc parametrs tabel mask word 4 */
-	uint32_t tx_gcp_table_mask_4;
-	/* [0x34] Tx Generic crc parametrs tabel mask word 5 */
-	uint32_t tx_gcp_table_mask_5;
-	/* [0x38] Tx Generic crc parametrs tabel mask word 6 */
-	uint32_t tx_gcp_table_mask_6;
-	/* [0x3c] Tx Generic crc parametrs tabel crc init */
-	uint32_t tx_gcp_table_crc_init;
-	/* [0x40] Tx Generic crc parametrs tabel result configuration ... */
-	uint32_t tx_gcp_table_res;
-	/* [0x44] Tx Generic crc parameters table alu opcode */
-	uint32_t tx_gcp_table_alu_opcode;
-	/* [0x48] Tx Generic crc parameters table alu opsel */
-	uint32_t tx_gcp_table_alu_opsel;
-	/* [0x4c] Tx Generic crc parameters table alu constant value */
-	uint32_t tx_gcp_table_alu_val;
-	/* [0x50] Tx CRC/Checksum replace */
-	uint32_t crc_csum_replace;
-	/* [0x54] CRC/Checksum replace table address */
-	uint32_t crc_csum_replace_table_addr;
-	/* [0x58] CRC/Checksum replace table */
-	uint32_t crc_csum_replace_table;
-	uint32_t rsrvd[9];
-};
-
-struct al_ec_rfw_v3 {
-	/* [0x0] Rx Generic protocol detect Cam compare table addres ... */
-	uint32_t rx_gpd_cam_addr;
-	/* [0x4] Rx Generic protocol detect Cam compare data_1 (low) ... */
-	uint32_t rx_gpd_cam_data_1;
-	/* [0x8] Rx Generic protocol detect Cam compare data_2 (high ... */
-	uint32_t rx_gpd_cam_data_2;
-	/* [0xc] Rx Generic protocol detect Cam compare mask_1 (low) ... */
-	uint32_t rx_gpd_cam_mask_1;
-	/* [0x10] Rx Generic protocol detect Cam compare mask_1 (high ... */
-	uint32_t rx_gpd_cam_mask_2;
-	/* [0x14] Rx Generic protocol detect Cam compare control */
-	uint32_t rx_gpd_cam_ctrl;
-	/* [0x18] Generic protocol detect Parser result vector pointe ... */
-	uint32_t gpd_p1;
-	/* [0x1c] Generic protocol detect Parser result vector pointe ... */
-	uint32_t gpd_p2;
-	/* [0x20] Generic protocol detect Parser result vector pointe ... */
-	uint32_t gpd_p3;
-	/* [0x24] Generic protocol detect Parser result vector pointe ... */
-	uint32_t gpd_p4;
-	/* [0x28] Generic protocol detect Parser result vector pointe ... */
-	uint32_t gpd_p5;
-	/* [0x2c] Generic protocol detect Parser result vector pointe ... */
-	uint32_t gpd_p6;
-	/* [0x30] Generic protocol detect Parser result vector pointe ... */
-	uint32_t gpd_p7;
-	/* [0x34] Generic protocol detect Parser result vector pointe ... */
-	uint32_t gpd_p8;
-	/* [0x38] Rx Generic crc parameters legacy */
-	uint32_t rx_gcp_legacy;
-	/* [0x3c] Rx Generic crc prameters table address */
-	uint32_t rx_gcp_table_addr;
-	/* [0x40] Rx Generic crc prameters table general */
-	uint32_t rx_gcp_table_gen;
-	/* [0x44] Rx Generic crc parametrs tabel mask word 1 */
-	uint32_t rx_gcp_table_mask_1;
-	/* [0x48] Rx Generic crc parametrs tabel mask word 2 */
-	uint32_t rx_gcp_table_mask_2;
-	/* [0x4c] Rx Generic crc parametrs tabel mask word 3 */
-	uint32_t rx_gcp_table_mask_3;
-	/* [0x50] Rx Generic crc parametrs tabel mask word 4 */
-	uint32_t rx_gcp_table_mask_4;
-	/* [0x54] Rx Generic crc parametrs tabel mask word 5 */
-	uint32_t rx_gcp_table_mask_5;
-	/* [0x58] Rx Generic crc parametrs tabel mask word 6 */
-	uint32_t rx_gcp_table_mask_6;
-	/* [0x5c] Rx Generic crc parametrs tabel crc init */
-	uint32_t rx_gcp_table_crc_init;
-	/* [0x60] Rx Generic crc parametrs tabel result configuration ... */
-	uint32_t rx_gcp_table_res;
-	/* [0x64] Rx Generic crc  parameters table alu opcode */
-	uint32_t rx_gcp_table_alu_opcode;
-	/* [0x68] Rx Generic crc  parameters table alu opsel */
-	uint32_t rx_gcp_table_alu_opsel;
-	/* [0x6c] Rx Generic crc  parameters table alu constant value ... */
-	uint32_t rx_gcp_table_alu_val;
-	/* [0x70] Generic crc engin parameters alu Parser result vect ... */
-	uint32_t rx_gcp_alu_p1;
-	/* [0x74] Generic crc engine parameters alu Parser result vec ... */
-	uint32_t rx_gcp_alu_p2;
-	/* [0x78] Header split control table address */
-	uint32_t hs_ctrl_table_addr;
-	/* [0x7c] Header split control table */
-	uint32_t hs_ctrl_table;
-	/* [0x80] Header split control alu opcode */
-	uint32_t hs_ctrl_table_alu_opcode;
-	/* [0x84] Header split control alu opsel */
-	uint32_t hs_ctrl_table_alu_opsel;
-	/* [0x88] Header split control alu constant value */
-	uint32_t hs_ctrl_table_alu_val;
-	/* [0x8c] Header split control configuration */
-	uint32_t hs_ctrl_cfg;
-	/* [0x90] Header split control alu Parser result vector point ... */
-	uint32_t hs_ctrl_alu_p1;
-	/* [0x94] Header split control alu Parser result vector point ... */
-	uint32_t hs_ctrl_alu_p2;
-	uint32_t rsrvd[26];
-};
-struct al_ec_crypto {
-	/* [0x0] Tx inline crypto configuration */
-	uint32_t tx_config;
-	/* [0x4] Rx inline crypto configuration */
-	uint32_t rx_config;
-	/* [0x8] reserved FFU */
-	uint32_t tx_override;
-	/* [0xc] reserved FFU */
-	uint32_t rx_override;
-	/* [0x10] inline XTS alpha [31:0] */
-	uint32_t xts_alpha_1;
-	/* [0x14] inline XTS alpha [63:32] */
-	uint32_t xts_alpha_2;
-	/* [0x18] inline XTS alpha [95:64] */
-	uint32_t xts_alpha_3;
-	/* [0x1c] inline XTS alpha [127:96] */
-	uint32_t xts_alpha_4;
-	/* [0x20] inline XTS sector ID increment [31:0] */
-	uint32_t xts_sector_id_1;
-	/* [0x24] inline XTS sector ID increment [63:32] */
-	uint32_t xts_sector_id_2;
-	/* [0x28] inline XTS sector ID increment [95:64] */
-	uint32_t xts_sector_id_3;
-	/* [0x2c] inline XTS sector ID increment [127:96] */
-	uint32_t xts_sector_id_4;
-	/* [0x30] IV formation configuration */
-	uint32_t tx_enc_iv_construction;
-	/* [0x34] IV formation configuration */
-	uint32_t rx_enc_iv_construction;
-	/* [0x38] IV formation configuration */
-	uint32_t rx_enc_iv_map;
-	/*
-	[0x3c] effectively shorten shift-registers used for
-	eop-pkt-trim, in order to improve performance.
-	Each value must be built of consecutive 1's (bypassed regs),
-	and then consecutive 0's (non-bypassed regs)
-	*/
-	uint32_t tx_pkt_trim_len;
-	/*
-	[0x40] effectively shorten shift-registers used for
-	eop-pkt-trim, in order to improve performance.
-	Each value must be built of consecutive 1's (bypassed regs),
-	and then consecutive 0's (non-bypassed regs)
-	*/
-	uint32_t rx_pkt_trim_len;
-	/* [0x44] reserved FFU */
-	uint32_t tx_reserved;
-	/* [0x48] reserved FFU */
-	uint32_t rx_reserved;
-	uint32_t rsrvd[13];
-};
-struct al_ec_crypto_perf_cntr {
-	/* [0x0]  */
-	uint32_t total_tx_pkts;
-	/* [0x4]  */
-	uint32_t total_rx_pkts;
-	/* [0x8]  */
-	uint32_t total_tx_secured_pkts;
-	/* [0xc]  */
-	uint32_t total_rx_secured_pkts;
-	/* [0x10]  */
-	uint32_t total_tx_secured_pkts_cipher_mode;
-	/* [0x14]  */
-	uint32_t total_tx_secured_pkts_cipher_mode_cmpr;
-	/* [0x18]  */
-	uint32_t total_rx_secured_pkts_cipher_mode;
-	/* [0x1c]  */
-	uint32_t total_rx_secured_pkts_cipher_mode_cmpr;
-	/* [0x20]  */
-	uint32_t total_tx_secured_bytes_low;
-	/* [0x24]  */
-	uint32_t total_tx_secured_bytes_high;
-	/* [0x28]  */
-	uint32_t total_rx_secured_bytes_low;
-	/* [0x2c]  */
-	uint32_t total_rx_secured_bytes_high;
-	/* [0x30]  */
-	uint32_t total_tx_sign_calcs;
-	/* [0x34]  */
-	uint32_t total_rx_sign_calcs;
-	/* [0x38]  */
-	uint32_t total_tx_sign_errs;
-	/* [0x3c]  */
-	uint32_t total_rx_sign_errs;
-};
-struct al_ec_crypto_tx_tid {
-	/* [0x0] tid_default_entry */
-	uint32_t def_val;
-};
-
-struct al_ec_regs {
-	uint32_t rsrvd_0[32];
-	struct al_ec_gen gen;                                /* [0x80] */
-	struct al_ec_mac mac;                                /* [0xc0] */
-	struct al_ec_rxf rxf;                                /* [0x100] */
-	struct al_ec_epe epe[2];                             /* [0x180] */
-	struct al_ec_epe_res epe_res;                        /* [0x200] */
-	struct al_ec_epe_h epe_h[32];                        /* [0x280] */
-	struct al_ec_epe_p epe_p[32];                        /* [0x300] */
-	struct al_ec_epe_a epe_a[32];                        /* [0x680] */
-	struct al_ec_rfw rfw;                                /* [0x700] */
-	struct al_ec_rfw_udma rfw_udma[4];                   /* [0x7f0] */
-	struct al_ec_rfw_hash rfw_hash[10];                  /* [0x800] */
-	struct al_ec_rfw_priority rfw_priority[8];           /* [0x828] */
-	struct al_ec_rfw_default rfw_default[8];             /* [0x848] */
-	struct al_ec_fwd_mac fwd_mac[32];                    /* [0x868] */
-	struct al_ec_msw msw;                                /* [0xae8] */
-	struct al_ec_tso tso;                                /* [0xb00] */
-	struct al_ec_tso_sel tso_sel[8];                     /* [0xb60] */
-	struct al_ec_tpe tpe;                                /* [0xb80] */
-	struct al_ec_tpm_udma tpm_udma[4];                   /* [0xbc0] */
-	struct al_ec_tpm_sel tpm_sel[4];                     /* [0xbf0] */
-	struct al_ec_tfw tfw;                                /* [0xc00] */
-	struct al_ec_tfw_udma tfw_udma[4];                   /* [0xc60] */
-	struct al_ec_tmi tmi;                                /* [0xcc0] */
-	struct al_ec_efc efc;                                /* [0xcd0] */
-	struct al_ec_fc_udma fc_udma[4];                     /* [0xd00] */
-	struct al_ec_tpg_rpa_res tpg_rpa_res;                /* [0xf00] */
-	struct al_ec_eee eee;                                /* [0x1000] */
-	struct al_ec_stat stat;                              /* [0x1100] */
-	struct al_ec_stat_udma stat_udma[4];                 /* [0x1300] */
-	struct al_ec_msp msp;                                /* [0x1700] */
-	struct al_ec_msp_p msp_p[32];                        /* [0x1740] */
-	struct al_ec_msp_c msp_c[32];                        /* [0x17c0] */
-	uint32_t rsrvd_1[16];
-	struct al_ec_wol wol;                                /* [0x1b80] */
-	uint32_t rsrvd_2[80];
-	struct al_ec_pth pth;                                /* [0x1d00] */
-	struct al_ec_pth_egress pth_egress[8];               /* [0x1d80] */
-	struct al_ec_pth_db pth_db[16];                      /* [0x1e80] */
-	uint32_t rsrvd_3[416];
-	struct al_ec_gen_v3 gen_v3;                             /* [0x2680] */
-	struct al_ec_tfw_v3 tfw_v3;                             /* [0x26c0] */
-	struct al_ec_rfw_v3 rfw_v3;                             /* [0x2740] */
-	struct al_ec_crypto crypto;                             /* [0x2840] */
-	struct al_ec_crypto_perf_cntr crypto_perf_cntr[2];      /* [0x28c0] */
-	uint32_t rsrvd_4[48];
-	struct al_ec_crypto_tx_tid crypto_tx_tid[8];            /* [0x2a00] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-
-/**** version register ****/
-/* Revision number (Minor) */
-#define EC_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
-#define EC_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
-/* Revision number (Major) */
-#define EC_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
-#define EC_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
-/* Day of release */
-#define EC_GEN_VERSION_DATE_DAY_MASK     0x001F0000
-#define EC_GEN_VERSION_DATE_DAY_SHIFT    16
-/* Month of release */
-#define EC_GEN_VERSION_DATA_MONTH_MASK   0x01E00000
-#define EC_GEN_VERSION_DATA_MONTH_SHIFT  21
-/* Year of release (starting from 2000) */
-#define EC_GEN_VERSION_DATE_YEAR_MASK    0x3E000000
-#define EC_GEN_VERSION_DATE_YEAR_SHIFT   25
-/* Reserved */
-#define EC_GEN_VERSION_RESERVED_MASK     0xC0000000
-#define EC_GEN_VERSION_RESERVED_SHIFT    30
-
-/**** en register ****/
-/* Enable Frequency adjust FIFO input controller operation. */
-#define EC_GEN_EN_FAF_IN                 (1 << 0)
-/* Enable Frequency adjust FIFO output controller operation. */
-#define EC_GEN_EN_FAF_OUT                (1 << 1)
-/* Enable Rx FIFO input controller 1 operation. */
-#define EC_GEN_EN_RXF_IN                 (1 << 2)
-/* Enable Rx FIFO output controller  operation. */
-#define EC_GEN_EN_RXF_OUT                (1 << 3)
-/* Enable Rx forwarding input controller operation. */
-#define EC_GEN_EN_RFW_IN                 (1 << 4)
-/* Enable Rx forwarding output controller operation. */
-#define EC_GEN_EN_RFW_OUT                (1 << 5)
-/* Enable Rx multi-stream write controller operation. */
-#define EC_GEN_EN_MSW_IN                 (1 << 6)
-/* Enable Rx first parsing engine output operation. */
-#define EC_GEN_EN_RPE_1_OUT              (1 << 7)
-/* Enable Rx first parsing engine input operation. */
-#define EC_GEN_EN_RPE_1_IN               (1 << 8)
-/* Enable Rx second parsing engine output operation. */
-#define EC_GEN_EN_RPE_2_OUT              (1 << 9)
-/* Enable Rx second parsing engine input operation. */
-#define EC_GEN_EN_RPE_2_IN               (1 << 10)
-/* Enable Rx MACsec parsing engine output operation. */
-#define EC_GEN_EN_RPE_3_OUT              (1 << 11)
-/* Enable Rx MACsec parsing engine input operation. */
-#define EC_GEN_EN_RPE_3_IN               (1 << 12)
-/* Enable Loopback FIFO input controller 1 operation. */
-#define EC_GEN_EN_LBF_IN                 (1 << 13)
-/* Enable Rx packet analyzer operation. */
-#define EC_GEN_EN_RPA                    (1 << 14)
-
-#define EC_GEN_EN_RESERVED_15            (1 << 15)
-/* Enable Tx stream interface operation. */
-#define EC_GEN_EN_TSO                    (1 << 16)
-/* Enable Tx parser input controller operation. */
-#define EC_GEN_EN_TPE_IN                 (1 << 17)
-/* Enable Tx parser output controller operation. */
-#define EC_GEN_EN_TPE_OUT                (1 << 18)
-/* Enable Tx packet modification operation. */
-#define EC_GEN_EN_TPM                    (1 << 19)
-/* Enable Tx forwarding input controller operation. */
-#define EC_GEN_EN_TFW_IN                 (1 << 20)
-/* Enable Tx forwarding output controller operation. */
-#define EC_GEN_EN_TFW_OUT                (1 << 21)
-/* Enable Tx MAC interface controller operation. */
-#define EC_GEN_EN_TMI                    (1 << 22)
-/* Enable Tx packet generator operation. */
-#define EC_GEN_EN_TPG                    (1 << 23)
-
-#define EC_GEN_EN_RESERVED_31_MASK       0xFF000000
-#define EC_GEN_EN_RESERVED_31_SHIFT      24
-
-/**** fifo_en register ****/
-/* Enable Frequency adjust FIFO operation (input). */
-#define EC_GEN_FIFO_EN_FAF_IN            (1 << 0)
-/* Enable Frequency adjust FIFO operation (output). */
-#define EC_GEN_FIFO_EN_FAF_OUT           (1 << 1)
-/* Enable Rx FIFO operation. */
-#define EC_GEN_FIFO_EN_RX_FIFO           (1 << 2)
-/* Enable Rx forwarding FIFO operation. */
-#define EC_GEN_FIFO_EN_RFW_FIFO          (1 << 3)
-/* Enable Rx multi-stream write FIFO operation */
-#define EC_GEN_FIFO_EN_MSW_FIFO          (1 << 4)
-/* Enable Rx first parser FIFO operation. */
-#define EC_GEN_FIFO_EN_RPE_1_FIFO        (1 << 5)
-/* Enable Rx second parser FIFO operation. */
-#define EC_GEN_FIFO_EN_RPE_2_FIFO        (1 << 6)
-/* Enable Rx MACsec parser FIFO operation. */
-#define EC_GEN_FIFO_EN_RPE_3_FIFO        (1 << 7)
-/* Enable Loopback FIFO operation. */
-#define EC_GEN_FIFO_EN_LB_FIFO           (1 << 8)
-
-#define EC_GEN_FIFO_EN_RESERVED_15_9_MASK 0x0000FE00
-#define EC_GEN_FIFO_EN_RESERVED_15_9_SHIFT 9
-/* Enable Tx parser FIFO operation. */
-#define EC_GEN_FIFO_EN_TPE_FIFO          (1 << 16)
-/* Enable Tx forwarding FIFO operation. */
-#define EC_GEN_FIFO_EN_TFW_FIFO          (1 << 17)
-
-#define EC_GEN_FIFO_EN_RESERVED_31_18_MASK 0xFFFC0000
-#define EC_GEN_FIFO_EN_RESERVED_31_18_SHIFT 18
-
-/**** l2 register ****/
-/* Size of a 802.3 Ethernet header (DA+SA) */
-#define EC_GEN_L2_SIZE_802_3_MASK        0x0000003F
-#define EC_GEN_L2_SIZE_802_3_SHIFT       0
-/* Size of a 802.3 + MACsec 8 byte header */
-#define EC_GEN_L2_SIZE_802_3_MS_8_MASK   0x00003F00
-#define EC_GEN_L2_SIZE_802_3_MS_8_SHIFT  8
-/* Offset of the L2 header from the beginning of the packet. */
-#define EC_GEN_L2_OFFSET_MASK            0x7F000000
-#define EC_GEN_L2_OFFSET_SHIFT           24
-
-/**** cfg_i register ****/
-/* IPv4 protocol index */
-#define EC_GEN_CFG_I_IPV4_INDEX_MASK     0x0000001F
-#define EC_GEN_CFG_I_IPV4_INDEX_SHIFT    0
-/* IPv6 protocol index */
-#define EC_GEN_CFG_I_IPV6_INDEX_MASK     0x000003E0
-#define EC_GEN_CFG_I_IPV6_INDEX_SHIFT    5
-/* TCP protocol index */
-#define EC_GEN_CFG_I_TCP_INDEX_MASK      0x00007C00
-#define EC_GEN_CFG_I_TCP_INDEX_SHIFT     10
-/* UDP protocol index */
-#define EC_GEN_CFG_I_UDP_INDEX_MASK      0x000F8000
-#define EC_GEN_CFG_I_UDP_INDEX_SHIFT     15
-/* MACsec with 8 bytes SecTAG */
-#define EC_GEN_CFG_I_MACSEC_8_INDEX_MASK 0x01F00000
-#define EC_GEN_CFG_I_MACSEC_8_INDEX_SHIFT 20
-/* MACsec with 16 bytes SecTAG */
-#define EC_GEN_CFG_I_MACSEC_16_INDEX_MASK 0x3E000000
-#define EC_GEN_CFG_I_MACSEC_16_INDEX_SHIFT 25
-
-/**** cfg_i_ext register ****/
-/* FcoE protocol index */
-#define EC_GEN_CFG_I_EXT_FCOE_INDEX_MASK 0x0000001F
-#define EC_GEN_CFG_I_EXT_FCOE_INDEX_SHIFT 0
-/* RoCE protocol index */
-#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_1_MASK 0x000003E0
-#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_1_SHIFT 5
-/* RoCE protocol index */
-#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_2_MASK 0x00007C00
-#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_2_SHIFT 10
-/* RoCE protocol index */
-#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L4_MASK 0x000F8000
-#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L4_SHIFT 15
-
-/**** en_ext register ****/
-/* Enable Usage of Ethernet port memories for testing */
-#define EC_GEN_EN_EXT_MEM_FOR_TEST_MASK  0x0000000F
-#define EC_GEN_EN_EXT_MEM_FOR_TEST_SHIFT 0
-#define EC_GEN_EN_EXT_MEM_FOR_TEST_VAL_EN	\
-	(0xa << EC_GEN_EN_EXT_MEM_FOR_TEST_SHIFT)
-#define EC_GEN_EN_EXT_MEM_FOR_TEST_VAL_DIS	\
-	(0x0 << EC_GEN_EN_EXT_MEM_FOR_TEST_SHIFT)
-/* Enable MAC loop back (Rx --> Tx, after MAC layer) for 802 */
-#define EC_GEN_EN_EXT_MAC_LB             (1 << 4)
-/* CRC forward value for the MAC Tx when working in loopback mod ... */
-#define EC_GEN_EN_EXT_MAC_LB_CRC_FWD     (1 << 5)
-/* Ready signal configuration when in loopback mode:00 - Ready f ... */
-#define EC_GEN_EN_EXT_MAC_LB_READY_CFG_MASK 0x000000C0
-#define EC_GEN_EN_EXT_MAC_LB_READY_CFG_SHIFT 6
-/* Bypass the PTH completion update. */
-#define EC_GEN_EN_EXT_PTH_COMPLETION_BYPASS (1 << 16)
-/* Selection between the 1G and 10G MAC:
-0 - 1G
-1 - 10G */
-#define EC_GEN_EN_EXT_PTH_1_10_SEL       (1 << 17)
-/* avoid timestamping every pkt in 1G */
-#define EC_GEN_EN_EXT_PTH_CFG_1G_TIMESTAMP_OPT (1 << 18)
-/* Selection between descriptor caching options (WORD selection) ... */
-#define EC_GEN_EN_EXT_CACHE_WORD_SPLIT   (1 << 20)
-
-/**** gen register ****/
-/* Enable swap of input byte order */
-#define EC_MAC_GEN_SWAP_IN_BYTE          (1 << 0)
-
-/**** min_pkt register ****/
-/* Minimum packet size  */
-#define EC_MAC_MIN_PKT_SIZE_MASK         0x000FFFFF
-#define EC_MAC_MIN_PKT_SIZE_SHIFT        0
-
-/**** max_pkt register ****/
-/* Maximum packet size  */
-#define EC_MAC_MAX_PKT_SIZE_MASK         0x000FFFFF
-#define EC_MAC_MAX_PKT_SIZE_SHIFT        0
-
-/**** cfg_1 register ****/
-/* Drop packet at the ingress0 - Packets are not dropped at the  ... */
-#define EC_RXF_CFG_1_DROP_AT_INGRESS     (1 << 0)
-/* Accept packet criteria at start of packet indication */
-#define EC_RXF_CFG_1_SOP_ACCEPT          (1 << 1)
-/* Select the arbiter between Rx packets and Tx packets (packets ... */
-#define EC_RXF_CFG_1_ARB_SEL             (1 << 2)
-/* Arbiter priority when strict priority is selected in arb_sel0 ... */
-#define EC_RXF_CFG_1_ARB_P               (1 << 3)
-/* Force loopback operation */
-#define EC_RXF_CFG_1_FORCE_LB            (1 << 4)
-/* Forwarding selection between Rx path and/or packet analyzer */
-#define EC_RXF_CFG_1_FWD_SEL_MASK        0x00000300
-#define EC_RXF_CFG_1_FWD_SEL_SHIFT       8
-
-/**** cfg_2 register ****/
-/* FIFO USED threshold for accepting new packets, low threshold  ... */
-#define EC_RXF_CFG_2_FIFO_USED_TH_L_MASK 0x0000FFFF
-#define EC_RXF_CFG_2_FIFO_USED_TH_L_SHIFT 0
-/* FIFO USED threshold for accepting new packets, high threshold ... */
-#define EC_RXF_CFG_2_FIFO_USED_TH_H_MASK 0xFFFF0000
-#define EC_RXF_CFG_2_FIFO_USED_TH_H_SHIFT 16
-
-/**** rd_fifo register ****/
-/* Minimum number of entries in the data FIFO to start reading p ... */
-#define EC_RXF_RD_FIFO_TH_DATA_MASK      0x0000FFFF
-#define EC_RXF_RD_FIFO_TH_DATA_SHIFT     0
-/* Enable cut through operation */
-#define EC_RXF_RD_FIFO_EN_CUT_TH         (1 << 16)
-
-/**** wr_fifo register ****/
-
-#define EC_RXF_WR_FIFO_TH_DATA_MASK      0x0000FFFF
-#define EC_RXF_WR_FIFO_TH_DATA_SHIFT     0
-
-#define EC_RXF_WR_FIFO_TH_INFO_MASK      0xFFFF0000
-#define EC_RXF_WR_FIFO_TH_INFO_SHIFT     16
-
-/**** lb_fifo register ****/
-
-#define EC_RXF_LB_FIFO_TH_DATA_MASK      0x0000FFFF
-#define EC_RXF_LB_FIFO_TH_DATA_SHIFT     0
-
-#define EC_RXF_LB_FIFO_TH_INFO_MASK      0xFFFF0000
-#define EC_RXF_LB_FIFO_TH_INFO_SHIFT     16
-
-/**** cfg_lb register ****/
-/* FIFO USED threshold for accepting new packets */
-#define EC_RXF_CFG_LB_FIFO_USED_TH_INT_MASK 0x0000FFFF
-#define EC_RXF_CFG_LB_FIFO_USED_TH_INT_SHIFT 0
-/* FIFO USED threshold for generating ready for the Tx path */
-#define EC_RXF_CFG_LB_FIFO_USED_TH_EXT_MASK 0xFFFF0000
-#define EC_RXF_CFG_LB_FIFO_USED_TH_EXT_SHIFT 16
-
-/**** out_drop register ****/
-
-#define EC_RXF_OUT_DROP_MAC_ERR          (1 << 0)
-
-#define EC_RXF_OUT_DROP_MAC_COL          (1 << 1)
-
-#define EC_RXF_OUT_DROP_MAC_DEC          (1 << 2)
-
-#define EC_RXF_OUT_DROP_MAC_LEN          (1 << 3)
-
-#define EC_RXF_OUT_DROP_MAC_PHY          (1 << 4)
-
-#define EC_RXF_OUT_DROP_MAC_FIFO         (1 << 5)
-
-#define EC_RXF_OUT_DROP_MAC_FCS          (1 << 6)
-
-#define EC_RXF_OUT_DROP_MAC_ETYPE        (1 << 7)
-
-#define EC_RXF_OUT_DROP_EC_LEN           (1 << 8)
-
-#define EC_RXF_OUT_DROP_EC_FIFO          (1 << 9)
-
-/**** parse_cfg register ****/
-/* MAX number of beats for packet parsing */
-#define EC_EPE_PARSE_CFG_MAX_BEATS_MASK  0x000000FF
-#define EC_EPE_PARSE_CFG_MAX_BEATS_SHIFT 0
-/* MAX number of parsing iterations for packet parsing */
-#define EC_EPE_PARSE_CFG_MAX_ITER_MASK   0x0000FF00
-#define EC_EPE_PARSE_CFG_MAX_ITER_SHIFT  8
-
-/**** act_table_addr register ****/
-/* Address for accessing the table */
-#define EC_EPE_ACT_TABLE_ADDR_VAL_MASK   0x0000001F
-#define EC_EPE_ACT_TABLE_ADDR_VAL_SHIFT  0
-
-/**** act_table_data_1 register ****/
-/* Table data[5:0] - Offset to next protocol [bytes][6] - Next p ... */
-#define EC_EPE_ACT_TABLE_DATA_1_VAL_MASK 0x03FFFFFF
-#define EC_EPE_ACT_TABLE_DATA_1_VAL_SHIFT 0
-
-/**** act_table_data_2 register ****/
-/* Table Data [8:0] - Offset to data in the packet [bits][17:9]  ... */
-#define EC_EPE_ACT_TABLE_DATA_2_VAL_MASK 0x1FFFFFFF
-#define EC_EPE_ACT_TABLE_DATA_2_VAL_SHIFT 0
-
-/**** act_table_data_3 register ****/
-/* Table Data  [8:0] - Offset to data in the packet [bits] [17:9 ... */
-#define EC_EPE_ACT_TABLE_DATA_3_VAL_MASK 0x1FFFFFFF
-#define EC_EPE_ACT_TABLE_DATA_3_VAL_SHIFT 0
-
-/**** act_table_data_4 register ****/
-/* Table data[7:0] - Offset to header length location in the pac ... */
-#define EC_EPE_ACT_TABLE_DATA_4_VAL_MASK 0x0FFFFFFF
-#define EC_EPE_ACT_TABLE_DATA_4_VAL_SHIFT 0
-
-/**** act_table_data_6 register ****/
-/* Table data[0] - WR header length[10:1] - Write header length  ... */
-#define EC_EPE_ACT_TABLE_DATA_6_VAL_MASK 0x007FFFFF
-#define EC_EPE_ACT_TABLE_DATA_6_VAL_SHIFT 0
-
-/**** res_in register ****/
-/* Selector for input parse_en0 - Input vector1 - Default value  ... */
-#define EC_EPE_RES_IN_SEL_PARSE_EN       (1 << 0)
-/* Selector for input protocol_index 0 - Input vector 1 - Defaul ... */
-#define EC_EPE_RES_IN_SEL_PROT_INDEX     (1 << 1)
-/* Selector for input hdr_offset 0 - Input vector 1 - Default va ... */
-#define EC_EPE_RES_IN_SEL_HDR_OFFSET     (1 << 2)
-
-/**** p1 register ****/
-/* Location of the input protocol index in the parser result vec ... */
-#define EC_EPE_RES_P1_IN_PROT_INDEX_MASK 0x000003FF
-#define EC_EPE_RES_P1_IN_PROT_INDEX_SHIFT 0
-
-/**** p2 register ****/
-/* Location of the input offset in the parser result vector */
-#define EC_EPE_RES_P2_IN_OFFSET_MASK     0x000003FF
-#define EC_EPE_RES_P2_IN_OFFSET_SHIFT    0
-
-/**** p3 register ****/
-/* Location of the input parse enable in the parser result vecto ... */
-#define EC_EPE_RES_P3_IN_PARSE_EN_MASK   0x000003FF
-#define EC_EPE_RES_P3_IN_PARSE_EN_SHIFT  0
-
-/**** p4 register ****/
-/* Location of the control bits in the parser result vector */
-#define EC_EPE_RES_P4_CTRL_BITS_MASK     0x000003FF
-#define EC_EPE_RES_P4_CTRL_BITS_SHIFT    0
-
-/**** p5 register ****/
-/* Location of the MAC DA in the parser result vector */
-#define EC_EPE_RES_P5_DA_MASK            0x000003FF
-#define EC_EPE_RES_P5_DA_SHIFT           0
-
-/**** p6 register ****/
-/* Location of the MAC SA in the parser result vector */
-#define EC_EPE_RES_P6_SA_MASK            0x000003FF
-#define EC_EPE_RES_P6_SA_SHIFT           0
-
-/**** p7 register ****/
-/* Location of the first VLAN in the parser result vector */
-#define EC_EPE_RES_P7_VLAN_1_MASK        0x000003FF
-#define EC_EPE_RES_P7_VLAN_1_SHIFT       0
-
-/**** p8 register ****/
-/* Location of the second VLAN in the parser result vector */
-#define EC_EPE_RES_P8_VLAN_2_MASK        0x000003FF
-#define EC_EPE_RES_P8_VLAN_2_SHIFT       0
-
-/**** p9 register ****/
-/* Location of the L3 protocol index in the parser result vector ... */
-#define EC_EPE_RES_P9_L3_PROT_INDEX_MASK 0x000003FF
-#define EC_EPE_RES_P9_L3_PROT_INDEX_SHIFT 0
-
-/**** p10 register ****/
-/* Location of the L3 offset in the parser result vector */
-#define EC_EPE_RES_P10_L3_OFFSET_MASK    0x000003FF
-#define EC_EPE_RES_P10_L3_OFFSET_SHIFT   0
-
-/**** p11 register ****/
-/* Location of the L3 SIP in the parser result vector */
-#define EC_EPE_RES_P11_L3_SIP_MASK       0x000003FF
-#define EC_EPE_RES_P11_L3_SIP_SHIFT      0
-
-/**** p12 register ****/
-/* Location of the L3 DIP in the parser result vector */
-#define EC_EPE_RES_P12_L3_DIP_MASK       0x000003FF
-#define EC_EPE_RES_P12_L3_DIP_SHIFT      0
-
-/**** p13 register ****/
-/* Location of the L3 priority in the parser result vector */
-#define EC_EPE_RES_P13_L3_PRIORITY_MASK  0x000003FF
-#define EC_EPE_RES_P13_L3_PRIORITY_SHIFT 0
-
-/**** p14 register ****/
-/* Location of the L3 header length in the parser result vector */
-#define EC_EPE_RES_P14_L3_HDR_LEN_MASK   0x000003FF
-#define EC_EPE_RES_P14_L3_HDR_LEN_SHIFT  0
-
-/**** p15 register ****/
-/* Location of the L4 protocol index in the parser result vector ... */
-#define EC_EPE_RES_P15_L4_PROT_INDEX_MASK 0x000003FF
-#define EC_EPE_RES_P15_L4_PROT_INDEX_SHIFT 0
-
-/**** p16 register ****/
-/* Location of the L4 source port in the parser result vector */
-#define EC_EPE_RES_P16_L4_SRC_PORT_MASK  0x000003FF
-#define EC_EPE_RES_P16_L4_SRC_PORT_SHIFT 0
-
-/**** p17 register ****/
-/* Location of the L4 destination port in the parser result vect ... */
-#define EC_EPE_RES_P17_L4_DST_PORT_MASK  0x000003FF
-#define EC_EPE_RES_P17_L4_DST_PORT_SHIFT 0
-
-/**** p18 register ****/
-/* Location of the L4 offset in the parser result vector */
-#define EC_EPE_RES_P18_L4_OFFSET_MASK    0x000003FF
-#define EC_EPE_RES_P18_L4_OFFSET_SHIFT   0
-
-/**** p19 register ****/
-/* Location of the Ether type in the parser result vector when w ... */
-#define EC_EPE_RES_P19_WOL_ETYPE_MASK    0x000003FF
-#define EC_EPE_RES_P19_WOL_ETYPE_SHIFT   0
-
-/**** p20 register ****/
-/* Location of the RoCE QP number field in the parser result vec ... */
-#define EC_EPE_RES_P20_ROCE_QPN_MASK     0x000003FF
-#define EC_EPE_RES_P20_ROCE_QPN_SHIFT    0
-
-/**** hdr_len register ****/
-/* Value for selecting table 1 */
-#define EC_EPE_H_HDR_LEN_TABLE_1_MASK    0x000000FF
-#define EC_EPE_H_HDR_LEN_TABLE_1_SHIFT   0
-/* Value for selecting table 2 */
-#define EC_EPE_H_HDR_LEN_TABLE_2_MASK    0x00FF0000
-#define EC_EPE_H_HDR_LEN_TABLE_2_SHIFT   16
-
-/**** comp_data register ****/
-/* Data 1 for comparison */
-#define EC_EPE_P_COMP_DATA_DATA_1_MASK   0x0000FFFF
-#define EC_EPE_P_COMP_DATA_DATA_1_SHIFT  0
-/* Data 2 for comparison
-[18:16] - Stage
-[24:19] - Branch ID */
-#define EC_EPE_P_COMP_DATA_DATA_2_MASK   0x01FF0000
-#define EC_EPE_P_COMP_DATA_DATA_2_SHIFT  16
-
-/**** comp_mask register ****/
-/* Data 1 for comparison */
-#define EC_EPE_P_COMP_MASK_DATA_1_MASK   0x0000FFFF
-#define EC_EPE_P_COMP_MASK_DATA_1_SHIFT  0
-/* Data 2 for comparison
-[18:16] - Stage
-[24:19] - Branch ID */
-#define EC_EPE_P_COMP_MASK_DATA_2_MASK   0x01FF0000
-#define EC_EPE_P_COMP_MASK_DATA_2_SHIFT  16
-
-/**** comp_ctrl register ****/
-/* Output result value */
-#define EC_EPE_P_COMP_CTRL_RES_MASK      0x0000001F
-#define EC_EPE_P_COMP_CTRL_RES_SHIFT     0
-/* Compare command for the data_1 field00 - Compare01 - <=10 - > ... */
-#define EC_EPE_P_COMP_CTRL_CMD_1_MASK    0x00030000
-#define EC_EPE_P_COMP_CTRL_CMD_1_SHIFT   16
-/* Compare command for the data_2 field 00 - Compare 01 - <= 10  ... */
-#define EC_EPE_P_COMP_CTRL_CMD_2_MASK    0x000C0000
-#define EC_EPE_P_COMP_CTRL_CMD_2_SHIFT   18
-/* Entry is valid */
-#define EC_EPE_P_COMP_CTRL_VALID         (1 << 31)
-
-/**** prot_act register ****/
-/* Drop indication for the selected protocol index */
-#define EC_EPE_A_PROT_ACT_DROP           (1 << 0)
-/* Mapping value Used when mapping the entire protocol index ran ... */
-#define EC_EPE_A_PROT_ACT_MAP_MASK       0x00000F00
-#define EC_EPE_A_PROT_ACT_MAP_SHIFT      8
-
-/**** thash_cfg_1 register ****/
-/* Hash function output selection:000 - [7:0]001 - [15:8]010 - [ ... */
-#define EC_RFW_THASH_CFG_1_OUT_SEL_MASK  0x00000007
-#define EC_RFW_THASH_CFG_1_OUT_SEL_SHIFT 0
-/* Selects between hash functions00 - toeplitz01 - CRC-3210 - 0x ... */
-#define EC_RFW_THASH_CFG_1_FUNC_SEL_MASK 0x00000300
-#define EC_RFW_THASH_CFG_1_FUNC_SEL_SHIFT 8
-/* Enable SIP/DIP swap if SIP<DIP */
-#define EC_RFW_THASH_CFG_1_ENABLE_IP_SWAP (1 << 16)
-/* Enable PORT swap if SPORT<DPORT */
-#define EC_RFW_THASH_CFG_1_ENABLE_PORT_SWAP (1 << 17)
-
-/**** mhash_cfg_1 register ****/
-/* Hash function output selection:000 - [7:0]001 - [15:8]010 - [ ... */
-#define EC_RFW_MHASH_CFG_1_OUT_SEL_MASK  0x00000007
-#define EC_RFW_MHASH_CFG_1_OUT_SEL_SHIFT 0
-/* Selects the input to the MAC hash function0 - DA1 - DA + SA ... */
-#define EC_RFW_MHASH_CFG_1_INPUT_SEL     (1 << 4)
-/* Selects between hash functions00 - toeplitz01 - CRC-3210 - 0x ... */
-#define EC_RFW_MHASH_CFG_1_FUNC_SEL_MASK 0x00000300
-#define EC_RFW_MHASH_CFG_1_FUNC_SEL_SHIFT 8
-
-/**** hdr_split register ****/
-/* Default header length for header split */
-#define EC_RFW_HDR_SPLIT_DEF_LEN_MASK    0x0000FFFF
-#define EC_RFW_HDR_SPLIT_DEF_LEN_SHIFT   0
-/* Enable header split operation */
-#define EC_RFW_HDR_SPLIT_EN              (1 << 16)
-
-/**** meta_err register ****/
-/* Mask for error 1 in the Rx descriptor */
-#define EC_RFW_META_ERR_MASK_1_MASK      0x000003FF
-#define EC_RFW_META_ERR_MASK_1_SHIFT     0
-/* Mask for error 2 in the Rx descriptor */
-#define EC_RFW_META_ERR_MASK_2_MASK      0x03FF0000
-#define EC_RFW_META_ERR_MASK_2_SHIFT     16
-
-/**** meta register ****/
-/* Selection of the L3 offset source: 1 - Inner packet 0 - Outer ... */
-#define EC_RFW_META_L3_LEN_SEL           (1 << 0)
-/* Selection of the L3 offset source:1 - Inner packet0 - Outer p ... */
-#define EC_RFW_META_L3_OFFSET_SEL        (1 << 1)
-/* Selection of the l3 protocol index source: 1 - Inner packet 0 ... */
-#define EC_RFW_META_L3_PROT_SEL          (1 << 2)
-/* Selection of the l4 protocol index source:  1 - Inner packet  ... */
-#define EC_RFW_META_L4_PROT_SEL          (1 << 3)
-/* Selects how to calculate the L3 header length when L3 is IpPv ... */
-#define EC_RFW_META_L3_LEN_CALC          (1 << 4)
-/* Selection of the IPv4 fragment indication source:  1 - Inner  ... */
-#define EC_RFW_META_FRAG_SEL             (1 << 5)
-/* Selection of the L4 offset source:1 - Inner packet0 - Outer p ... */
-#define EC_RFW_META_L4_OFFSET_SEL        (1 << 6)
-
-/**** filter register ****/
-/* Filter undetected MAC DA */
-#define EC_RFW_FILTER_UNDET_MAC          (1 << 0)
-/* Filter specific MAC DA based on MAC table output. */
-#define EC_RFW_FILTER_DET_MAC            (1 << 1)
-/* Filter all tagged. */
-#define EC_RFW_FILTER_TAGGED             (1 << 2)
-/* Filter all untagged. */
-#define EC_RFW_FILTER_UNTAGGED           (1 << 3)
-/* Filter all broadcast. */
-#define EC_RFW_FILTER_BC                 (1 << 4)
-/* Filter all multicast. */
-#define EC_RFW_FILTER_MC                 (1 << 5)
-/* Filter based on parsing output (used to drop selected protoco ... */
-#define EC_RFW_FILTER_PARSE              (1 << 6)
-/* Filter packet based on VLAN table output. */
-#define EC_RFW_FILTER_VLAN_VID           (1 << 7)
-/* Filter packet based on control table output. */
-#define EC_RFW_FILTER_CTRL_TABLE         (1 << 8)
-/* Filter packet based on protocol index action register. */
-#define EC_RFW_FILTER_PROT_INDEX         (1 << 9)
-/* Filter packet based on WoL decision */
-#define EC_RFW_FILTER_WOL                (1 << 10)
-/* Override filter decision and forward to default UDMA/queue;dr ... */
-#define EC_RFW_FILTER_OR_UNDET_MAC       (1 << 16)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_DET_MAC         (1 << 17)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_TAGGED          (1 << 18)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_UNTAGGED        (1 << 19)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_BC              (1 << 20)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_MC              (1 << 21)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_PARSE           (1 << 22)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_VLAN_VID        (1 << 23)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_CTRL_TABLE      (1 << 24)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_PROT_INDEX      (1 << 25)
-/* Override filter decision and forward to default UDMA/queue;Dr ... */
-#define EC_RFW_FILTER_OR_WOL             (1 << 26)
-
-/**** thash_table_addr register ****/
-/* Address for accessing the table */
-#define EC_RFW_THASH_TABLE_ADDR_VAL_MASK 0x000000FF
-#define EC_RFW_THASH_TABLE_ADDR_VAL_SHIFT 0
-
-/**** thash_table_data register ****/
-/* Table data (valid only after configuring the table address re ... */
-#define EC_RFW_THASH_TABLE_DATA_VAL_MASK 0x00003FFF
-#define EC_RFW_THASH_TABLE_DATA_VAL_SHIFT 0
-
-/**** mhash_table_addr register ****/
-/* Address for accessing the table */
-#define EC_RFW_MHASH_TABLE_ADDR_VAL_MASK 0x000000FF
-#define EC_RFW_MHASH_TABLE_ADDR_VAL_SHIFT 0
-
-/**** mhash_table_data register ****/
-/* Table data (valid only after configuring the table address re ... */
-#define EC_RFW_MHASH_TABLE_DATA_VAL_MASK 0x0000003F
-#define EC_RFW_MHASH_TABLE_DATA_VAL_SHIFT 0
-
-/**** vid_table_addr register ****/
-/* Address for accessing the table */
-#define EC_RFW_VID_TABLE_ADDR_VAL_MASK   0x00000FFF
-#define EC_RFW_VID_TABLE_ADDR_VAL_SHIFT  0
-
-/**** vid_table_data register ****/
-/* Table data (valid only after configuring the table address re ... */
-#define EC_RFW_VID_TABLE_DATA_VAL_MASK   0x0000003F
-#define EC_RFW_VID_TABLE_DATA_VAL_SHIFT  0
-
-/**** pbits_table_addr register ****/
-/* Address for accessing the table */
-#define EC_RFW_PBITS_TABLE_ADDR_VAL_MASK 0x00000007
-#define EC_RFW_PBITS_TABLE_ADDR_VAL_SHIFT 0
-
-/**** pbits_table_data register ****/
-/* VLAN P-bits to internal priority mapping */
-#define EC_RFW_PBITS_TABLE_DATA_VAL_MASK 0x00000007
-#define EC_RFW_PBITS_TABLE_DATA_VAL_SHIFT 0
-
-/**** dscp_table_addr register ****/
-/* Address for accessing the table */
-#define EC_RFW_DSCP_TABLE_ADDR_VAL_MASK  0x000000FF
-#define EC_RFW_DSCP_TABLE_ADDR_VAL_SHIFT 0
-
-/**** dscp_table_data register ****/
-/* IPv4 DSCP to internal priority mapping */
-#define EC_RFW_DSCP_TABLE_DATA_VAL_MASK  0x00000007
-#define EC_RFW_DSCP_TABLE_DATA_VAL_SHIFT 0
-
-/**** tc_table_addr register ****/
-/* Address for accessing the table */
-#define EC_RFW_TC_TABLE_ADDR_VAL_MASK    0x000000FF
-#define EC_RFW_TC_TABLE_ADDR_VAL_SHIFT   0
-
-/**** tc_table_data register ****/
-/* IPv6 TC to internal priority mapping */
-#define EC_RFW_TC_TABLE_DATA_VAL_MASK    0x00000007
-#define EC_RFW_TC_TABLE_DATA_VAL_SHIFT   0
-
-/**** ctrl_table_addr register ****/
-/* Address for accessing the table[0] - VLAN table control out[1 ... */
-#define EC_RFW_CTRL_TABLE_ADDR_VAL_MASK  0x000007FF
-#define EC_RFW_CTRL_TABLE_ADDR_VAL_SHIFT 0
-
-/**** ctrl_table_data register ****/
-/* Control table output for selecting the forwarding MUXs[3:0] - ... */
-#define EC_RFW_CTRL_TABLE_DATA_VAL_MASK  0x000FFFFF
-#define EC_RFW_CTRL_TABLE_DATA_VAL_SHIFT 0
-
-/**** out_cfg register ****/
-/* Number of MetaData at the end of the packet1 - One MetaData b ... */
-#define EC_RFW_OUT_CFG_META_CNT_MASK     0x00000003
-#define EC_RFW_OUT_CFG_META_CNT_SHIFT    0
-/* Enable packet drop */
-#define EC_RFW_OUT_CFG_DROP_EN           (1 << 2)
-/* Swap output byte order */
-#define EC_RFW_OUT_CFG_SWAP_OUT_BYTE     (1 << 3)
-/* Enable the insertion of the MACsec decoding result into the M ... */
-#define EC_RFW_OUT_CFG_EN_MACSEC_DEC     (1 << 4)
-/* Sample time of the time stamp:0 - SOP (for 10G MAC)1 - EOP (f ... */
-#define EC_RFW_OUT_CFG_TIMESTAMP_SAMPLE  (1 << 5)
-/* Determines which queue to write into the packet header0 - Ori ... */
-#define EC_RFW_OUT_CFG_QUEUE_OR_SEL   (1 << 6)
-/* Determines the logic of the drop indication:0 - Sample the dr ... */
-#define EC_RFW_OUT_CFG_DROP_LOGIC_SEL (1 << 7)
-/* Determines the logic of the drop indication:0 - Sample the dr ... */
-#define EC_RFW_OUT_CFG_PKT_TYPE_DEF   (1 << 8)
-
-/**** fsm_table_addr register ****/
-/* Address for accessing the table :[2:0] - Outer header control ... */
-#define EC_RFW_FSM_TABLE_ADDR_VAL_MASK   0x0000007F
-#define EC_RFW_FSM_TABLE_ADDR_VAL_SHIFT  0
-
-/**** fsm_table_data register ****/
-/* Flow steering mechanism output selectors:[1:0] - Input select ... */
-#define EC_RFW_FSM_TABLE_DATA_VAL_MASK   0x00000007
-#define EC_RFW_FSM_TABLE_DATA_VAL_SHIFT  0
-
-/**** ctrl_sel register ****/
-/* Packet type (UC/MC/BC) for the control table */
-#define EC_RFW_CTRL_SEL_PKT_TYPE         (1 << 0)
-/* L3 protocol index for the control table */
-#define EC_RFW_CTRL_SEL_L3_PROTOCOL      (1 << 1)
-/* Selects the content and structure of the control table addres ... */
-#define EC_RFW_CTRL_SEL_ADDR_MASK        0x0000000C
-#define EC_RFW_CTRL_SEL_ADDR_SHIFT       2
-
-/**** default_vlan register ****/
-/* Default VLAN data, used for untagged packets */
-#define EC_RFW_DEFAULT_VLAN_DATA_MASK    0x0000FFFF
-#define EC_RFW_DEFAULT_VLAN_DATA_SHIFT   0
-
-/**** default_hash register ****/
-/* Default UDMA */
-#define EC_RFW_DEFAULT_HASH_UDMA_MASK    0x0000000F
-#define EC_RFW_DEFAULT_HASH_UDMA_SHIFT   0
-/* Default queue */
-#define EC_RFW_DEFAULT_HASH_QUEUE_MASK   0x00030000
-#define EC_RFW_DEFAULT_HASH_QUEUE_SHIFT  16
-
-/**** default_or register ****/
-/* Default UDMA */
-#define EC_RFW_DEFAULT_OR_UDMA_MASK      0x0000000F
-#define EC_RFW_DEFAULT_OR_UDMA_SHIFT     0
-/* Default queue */
-#define EC_RFW_DEFAULT_OR_QUEUE_MASK     0x00030000
-#define EC_RFW_DEFAULT_OR_QUEUE_SHIFT    16
-
-/**** checksum register ****/
-/* Check that the length in the UDP header matches the length in ... */
-#define EC_RFW_CHECKSUM_UDP_LEN          (1 << 0)
-/* Select the header that will be used for the checksum when a t ... */
-#define EC_RFW_CHECKSUM_HDR_SEL          (1 << 1)
-/* Enable L4 checksum when L3 fragmentation is detected */
-#define EC_RFW_CHECKSUM_L4_FRAG_EN       (1 << 2)
-/* L3 Checksum result selection for the Metadata descriptor0 - O ... */
-#define EC_RFW_CHECKSUM_L3_CKS_SEL       (1 << 4)
-/* L4 Checksum result selection for the Metadata descriptor0 - O ... */
-#define EC_RFW_CHECKSUM_L4_CKS_SEL       (1 << 5)
-
-/**** lro_cfg_1 register ****/
-/* Select the header that will be used for the LRO offload engin ... */
-#define EC_RFW_LRO_CFG_1_HDR_SEL         (1 << 0)
-/* Select the L2 header that will be used for the LRO offload en ... */
-#define EC_RFW_LRO_CFG_1_HDR_L2_SEL      (1 << 1)
-
-/**** lro_check_ipv4 register ****/
-/* Check version field. */
-#define EC_RFW_LRO_CHECK_IPV4_VER        (1 << 0)
-/* Check IHL field == 5. */
-#define EC_RFW_LRO_CHECK_IPV4_IHL_0      (1 << 1)
-/* Check IHL field >= 5. */
-#define EC_RFW_LRO_CHECK_IPV4_IHL_1      (1 << 2)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV4_IHL_2      (1 << 3)
-/* Compare DSCP to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV4_DSCP       (1 << 4)
-/* Check that Total length >= lro_ipv4_tlen_val. */
-#define EC_RFW_LRO_CHECK_IPV4_TLEN       (1 << 5)
-/* Compare to previous packet value +1. */
-#define EC_RFW_LRO_CHECK_IPV4_ID         (1 << 6)
-/* Compare to lro_ipv4_flags_val with lro_ipv4_flags_mask_0. */
-#define EC_RFW_LRO_CHECK_IPV4_FLAGS_0    (1 << 7)
-/* Compare to previous packet flags with lro_ipv4_flags_mask_1. */
-#define EC_RFW_LRO_CHECK_IPV4_FLAGS_1    (1 << 8)
-/* Verify that the fragment offset field is 0. */
-#define EC_RFW_LRO_CHECK_IPV4_FRAG       (1 << 9)
-/* Verify that the TTL value >0. */
-#define EC_RFW_LRO_CHECK_IPV4_TTL_0      (1 << 10)
-/* Compare TTL value to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV4_TTL_1      (1 << 11)
-/* Compare to previous packet protocol field. */
-#define EC_RFW_LRO_CHECK_IPV4_PROT_0     (1 << 12)
-/* Verify that the protocol is TCP or UDP. */
-#define EC_RFW_LRO_CHECK_IPV4_PROT_1     (1 << 13)
-/* Verify that the check sum is correct. */
-#define EC_RFW_LRO_CHECK_IPV4_CHECKSUM   (1 << 14)
-/* Compare SIP to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV4_SIP        (1 << 15)
-/* Compare DIP to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV4_DIP        (1 << 16)
-
-/**** lro_ipv4 register ****/
-/* Total length minimum value */
-#define EC_RFW_LRO_IPV4_TLEN_VAL_MASK    0x0000FFFF
-#define EC_RFW_LRO_IPV4_TLEN_VAL_SHIFT   0
-/* Flags value  */
-#define EC_RFW_LRO_IPV4_FLAGS_VAL_MASK   0x00070000
-#define EC_RFW_LRO_IPV4_FLAGS_VAL_SHIFT  16
-/* Flags mask */
-#define EC_RFW_LRO_IPV4_FLAGS_MASK_0_MASK 0x00380000
-#define EC_RFW_LRO_IPV4_FLAGS_MASK_0_SHIFT 19
-/* Flags mask */
-#define EC_RFW_LRO_IPV4_FLAGS_MASK_1_MASK 0x01C00000
-#define EC_RFW_LRO_IPV4_FLAGS_MASK_1_SHIFT 22
-/* Version value */
-#define EC_RFW_LRO_IPV4_VER_MASK         0xF0000000
-#define EC_RFW_LRO_IPV4_VER_SHIFT        28
-
-/**** lro_check_ipv6 register ****/
-/* Check version field */
-#define EC_RFW_LRO_CHECK_IPV6_VER        (1 << 0)
-/* Compare TC to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV6_TC         (1 << 1)
-/* Compare flow label field to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV6_FLOW       (1 << 2)
-/* Check that Total length >= lro_ipv6_pen_val. */
-#define EC_RFW_LRO_CHECK_IPV6_PLEN       (1 << 3)
-/* Compare to previous packet next header field. */
-#define EC_RFW_LRO_CHECK_IPV6_NEXT_0     (1 << 4)
-/* Verify that the next header is TCP or UDP. */
-#define EC_RFW_LRO_CHECK_IPV6_NEXT_1     (1 << 5)
-/* Verify that hop limit is >0. */
-#define EC_RFW_LRO_CHECK_IPV6_HOP_0      (1 << 6)
-/* Compare hop limit to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV6_HOP_1      (1 << 7)
-/* Compare SIP to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV6_SIP        (1 << 8)
-/* Compare DIP to previous packet. */
-#define EC_RFW_LRO_CHECK_IPV6_DIP        (1 << 9)
-
-/**** lro_ipv6 register ****/
-/* Payload length minimum value */
-#define EC_RFW_LRO_IPV6_PLEN_VAL_MASK    0x0000FFFF
-#define EC_RFW_LRO_IPV6_PLEN_VAL_SHIFT   0
-/* Version value */
-#define EC_RFW_LRO_IPV6_VER_MASK         0x0F000000
-#define EC_RFW_LRO_IPV6_VER_SHIFT        24
-
-/**** lro_check_tcp register ****/
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_TCP_SRC_PORT    (1 << 0)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_TCP_DST_PORT    (1 << 1)
-/* If (SYN == 1), don't check  */
-#define EC_RFW_LRO_CHECK_TCP_SN          (1 << 2)
-/* Check data offset field == 5. */
-#define EC_RFW_LRO_CHECK_TCP_OFFSET_0    (1 << 3)
-/* Check data offset field >= 5. */
-#define EC_RFW_LRO_CHECK_TCP_OFFSET_1    (1 << 4)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_TCP_OFFSET_2    (1 << 5)
-/* Compare reserved field to lro_tcp_res. */
-#define EC_RFW_LRO_CHECK_TCP_RES         (1 << 6)
-/* Compare to lro_tcp_ecn_val and lro_tcp_ecn_mask_0. */
-#define EC_RFW_LRO_CHECK_TCP_ECN_0       (1 << 7)
-/* Compare to previous packet ECN field with lro_tcp_ecn_mask_1 */
-#define EC_RFW_LRO_CHECK_TCP_ECN_1       (1 << 8)
-/* Compare to lro_tcp_ctrl_val and lro_tcp_ctrl_mask_0. */
-#define EC_RFW_LRO_CHECK_TCP_CTRL_0      (1 << 9)
-/* Compare to previous packet ECN field with lro_tcp_ctrl_mask_1 */
-#define EC_RFW_LRO_CHECK_TCP_CTRL_1      (1 << 10)
-/* Verify that check sum is correct. */
-#define EC_RFW_LRO_CHECK_TCP_CHECKSUM    (1 << 11)
-
-/**** lro_tcp register ****/
-/* Reserved field default value */
-#define EC_RFW_LRO_TCP_RES_MASK          0x00000007
-#define EC_RFW_LRO_TCP_RES_SHIFT         0
-/* ECN field value */
-#define EC_RFW_LRO_TCP_ECN_VAL_MASK      0x00000038
-#define EC_RFW_LRO_TCP_ECN_VAL_SHIFT     3
-/* ECN field mask */
-#define EC_RFW_LRO_TCP_ECN_MASK_0_MASK   0x000001C0
-#define EC_RFW_LRO_TCP_ECN_MASK_0_SHIFT  6
-/* ECN field mask */
-#define EC_RFW_LRO_TCP_ECN_MASK_1_MASK   0x00000E00
-#define EC_RFW_LRO_TCP_ECN_MASK_1_SHIFT  9
-/* Control field value */
-#define EC_RFW_LRO_TCP_CTRL_VAL_MASK     0x0003F000
-#define EC_RFW_LRO_TCP_CTRL_VAL_SHIFT    12
-/* Control field mask */
-#define EC_RFW_LRO_TCP_CTRL_MASK_0_MASK  0x00FC0000
-#define EC_RFW_LRO_TCP_CTRL_MASK_0_SHIFT 18
-/* Control field mask */
-#define EC_RFW_LRO_TCP_CTRL_MASK_1_MASK  0x3F000000
-#define EC_RFW_LRO_TCP_CTRL_MASK_1_SHIFT 24
-
-/**** lro_check_udp register ****/
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_UDP_SRC_PORT    (1 << 0)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_UDP_DST_PORT    (1 << 1)
-/* Verify that check sum is correct. */
-#define EC_RFW_LRO_CHECK_UDP_CHECKSUM    (1 << 2)
-
-/**** lro_check_l2 register ****/
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_MAC_DA       (1 << 0)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_MAC_SA       (1 << 1)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_VLAN_1_EXIST (1 << 2)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_VLAN_1_VID   (1 << 3)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_VLAN_1_CFI   (1 << 4)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_VLAN_1_PBITS (1 << 5)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_VLAN_2_EXIST (1 << 6)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_VLAN_2_VID   (1 << 7)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_VLAN_2_CFI   (1 << 8)
-/* Compare to previous packet. */
-#define EC_RFW_LRO_CHECK_L2_VLAN_2_PBITS (1 << 9)
-/* Verify that the FCS is correct. */
-#define EC_RFW_LRO_CHECK_L2_FCS          (1 << 10)
-
-/**** lro_check_gen register ****/
-/* Compare to previous packet */
-#define EC_RFW_LRO_CHECK_GEN_UDMA        (1 << 0)
-/* Compare to previous packet */
-#define EC_RFW_LRO_CHECK_GEN_QUEUE       (1 << 1)
-
-/**** lro_store register ****/
-/* Store packet information if protocol match. */
-#define EC_RFW_LRO_STORE_IPV4            (1 << 0)
-/* Store packet information if protocol match. */
-#define EC_RFW_LRO_STORE_IPV6            (1 << 1)
-/* Store packet information if protocol match. */
-#define EC_RFW_LRO_STORE_TCP             (1 << 2)
-/* Store packet information if protocol match. */
-#define EC_RFW_LRO_STORE_UDP             (1 << 3)
-/* Store packet if IPv4 flags match the register value with mask */
-#define EC_RFW_LRO_STORE_IPV4_FLAGS_VAL_MASK 0x00000070
-#define EC_RFW_LRO_STORE_IPV4_FLAGS_VAL_SHIFT 4
-/* Mask for IPv4 flags */
-#define EC_RFW_LRO_STORE_IPV4_FLAGS_MASK_MASK 0x00000380
-#define EC_RFW_LRO_STORE_IPV4_FLAGS_MASK_SHIFT 7
-/* Store packet if TCP control and ECN match the register value  ... */
-#define EC_RFW_LRO_STORE_TCP_CTRL_VAL_MASK 0x0007FC00
-#define EC_RFW_LRO_STORE_TCP_CTRL_VAL_SHIFT 10
-/* Mask for TCP control */
-#define EC_RFW_LRO_STORE_TCP_CTRL_MASK_MASK 0x0FF80000
-#define EC_RFW_LRO_STORE_TCP_CTRL_MASK_SHIFT 19
-
-/**** vid_table_def register ****/
-/* Table default data (valid only after configuring the table ad ... */
-#define EC_RFW_VID_TABLE_DEF_VAL_MASK    0x0000003F
-#define EC_RFW_VID_TABLE_DEF_VAL_SHIFT   0
-/* Default data selection
-0 - Default value
-1 - Table data out */
-#define EC_RFW_VID_TABLE_DEF_SEL         (1 << 6)
-
-/**** ctrl_table_def register ****/
-/* Control table output for selecting the forwarding MUXs [3:0]  ... */
-#define EC_RFW_CTRL_TABLE_DEF_VAL_MASK   0x000FFFFF
-#define EC_RFW_CTRL_TABLE_DEF_VAL_SHIFT  0
-/* Default data selection 0 - Default value 1 - Table data out ... */
-#define EC_RFW_CTRL_TABLE_DEF_SEL        (1 << 20)
-
-/**** cfg_a_0 register ****/
-/* Selection of the L3 checksum result in the Metadata00 - L3 ch ... */
-#define EC_RFW_CFG_A_0_META_L3_CHK_RES_SEL_MASK 0x00000003
-#define EC_RFW_CFG_A_0_META_L3_CHK_RES_SEL_SHIFT 0
-/* Selection of the L4 checksum result in the Metadata0 - L4 che ... */
-#define EC_RFW_CFG_A_0_META_L4_CHK_RES_SEL (1 << 2)
-/* Selection of the LRO_context_value result in the Metadata0 -  ... */
-#define EC_RFW_CFG_A_0_LRO_CONTEXT_SEL   (1 << 4)
-
-/**** thash_cfg_3 register ****/
-/* Enable Hash value for RoCE packets in outer packet. */
-#define EC_RFW_THASH_CFG_3_ENABLE_OUTER_ROCE (1 << 0)
-/* Enable Hash value for RoCE packets in inner packet. */
-#define EC_RFW_THASH_CFG_3_ENABLE_INNER_ROCE (1 << 1)
-/* Enable Hash value for FcoE packets in outer packet. */
-#define EC_RFW_THASH_CFG_3_ENABLE_OUTER_FCOE (1 << 2)
-/* Enable Hash value for FcoE packets in inner packet. */
-#define EC_RFW_THASH_CFG_3_ENABLE_INNER_FCOE (1 << 3)
-
-/**** thash_mask_outer_ipv6 register ****/
-/* IPv6 source IP address */
-#define EC_RFW_THASH_MASK_OUTER_IPV6_SRC_MASK 0x0000FFFF
-#define EC_RFW_THASH_MASK_OUTER_IPV6_SRC_SHIFT 0
-/* IPv6 destination IP address */
-#define EC_RFW_THASH_MASK_OUTER_IPV6_DST_MASK 0xFFFF0000
-#define EC_RFW_THASH_MASK_OUTER_IPV6_DST_SHIFT 16
-
-/**** thash_mask_outer register ****/
-/* IPv4 source IP address */
-#define EC_RFW_THASH_MASK_OUTER_IPV4_SRC_MASK 0x0000000F
-#define EC_RFW_THASH_MASK_OUTER_IPV4_SRC_SHIFT 0
-/* IPv4 destination IP address */
-#define EC_RFW_THASH_MASK_OUTER_IPV4_DST_MASK 0x000000F0
-#define EC_RFW_THASH_MASK_OUTER_IPV4_DST_SHIFT 4
-/* TCP source port */
-#define EC_RFW_THASH_MASK_OUTER_TCP_SRC_PORT_MASK 0x00000300
-#define EC_RFW_THASH_MASK_OUTER_TCP_SRC_PORT_SHIFT 8
-/* TCP destination port */
-#define EC_RFW_THASH_MASK_OUTER_TCP_DST_PORT_MASK 0x00000C00
-#define EC_RFW_THASH_MASK_OUTER_TCP_DST_PORT_SHIFT 10
-/* UDP source port */
-#define EC_RFW_THASH_MASK_OUTER_UDP_SRC_PORT_MASK 0x00003000
-#define EC_RFW_THASH_MASK_OUTER_UDP_SRC_PORT_SHIFT 12
-/* UDP destination port */
-#define EC_RFW_THASH_MASK_OUTER_UDP_DST_PORT_MASK 0x0000C000
-#define EC_RFW_THASH_MASK_OUTER_UDP_DST_PORT_SHIFT 14
-
-/**** thash_mask_inner_ipv6 register ****/
-/* IPv6 source IP address */
-#define EC_RFW_THASH_MASK_INNER_IPV6_SRC_MASK 0x0000FFFF
-#define EC_RFW_THASH_MASK_INNER_IPV6_SRC_SHIFT 0
-/* IPv6 destination IP address */
-#define EC_RFW_THASH_MASK_INNER_IPV6_DST_MASK 0xFFFF0000
-#define EC_RFW_THASH_MASK_INNER_IPV6_DST_SHIFT 16
-
-/**** thash_mask_inner register ****/
-/* IPv4 source IP address */
-#define EC_RFW_THASH_MASK_INNER_IPV4_SRC_MASK 0x0000000F
-#define EC_RFW_THASH_MASK_INNER_IPV4_SRC_SHIFT 0
-/* IPv4 destination IP address */
-#define EC_RFW_THASH_MASK_INNER_IPV4_DST_MASK 0x000000F0
-#define EC_RFW_THASH_MASK_INNER_IPV4_DST_SHIFT 4
-/* TCP source port */
-#define EC_RFW_THASH_MASK_INNER_TCP_SRC_PORT_MASK 0x00000300
-#define EC_RFW_THASH_MASK_INNER_TCP_SRC_PORT_SHIFT 8
-/* TCP destination port */
-#define EC_RFW_THASH_MASK_INNER_TCP_DST_PORT_MASK 0x00000C00
-#define EC_RFW_THASH_MASK_INNER_TCP_DST_PORT_SHIFT 10
-/* UDP source port */
-#define EC_RFW_THASH_MASK_INNER_UDP_SRC_PORT_MASK 0x00003000
-#define EC_RFW_THASH_MASK_INNER_UDP_SRC_PORT_SHIFT 12
-/* UDP destination port */
-#define EC_RFW_THASH_MASK_INNER_UDP_DST_PORT_MASK 0x0000C000
-#define EC_RFW_THASH_MASK_INNER_UDP_DST_PORT_SHIFT 14
-
-/**** def_cfg register ****/
-/* Number of padding bytes to add at the beginning of each Ether ... */
-#define EC_RFW_UDMA_DEF_CFG_RX_PAD_MASK  0x0000003F
-#define EC_RFW_UDMA_DEF_CFG_RX_PAD_SHIFT 0
-
-/**** queue register ****/
-/* Mapping between priority and queue number */
-#define EC_RFW_PRIORITY_QUEUE_MAP_MASK   0x00000003
-#define EC_RFW_PRIORITY_QUEUE_MAP_SHIFT  0
-
-/**** opt_1 register ****/
-/* Default UDMA for forwarding  */
-#define EC_RFW_DEFAULT_OPT_1_UDMA_MASK   0x0000000F
-#define EC_RFW_DEFAULT_OPT_1_UDMA_SHIFT  0
-/* Default priority for forwarding */
-#define EC_RFW_DEFAULT_OPT_1_PRIORITY_MASK 0x00000700
-#define EC_RFW_DEFAULT_OPT_1_PRIORITY_SHIFT 8
-/* Default queue for forwarding */
-#define EC_RFW_DEFAULT_OPT_1_QUEUE_MASK  0x00030000
-#define EC_RFW_DEFAULT_OPT_1_QUEUE_SHIFT 16
-
-/**** data_h register ****/
-/* MAC address data  */
-#define EC_FWD_MAC_DATA_H_VAL_MASK       0x0000FFFF
-#define EC_FWD_MAC_DATA_H_VAL_SHIFT      0
-
-/**** mask_h register ****/
-/* MAC address mask  */
-#define EC_FWD_MAC_MASK_H_VAL_MASK       0x0000FFFF
-#define EC_FWD_MAC_MASK_H_VAL_SHIFT      0
-
-/**** ctrl register ****/
-/* Control value for Rx forwarding engine[0] - Drop indication[2 ... */
-#define EC_FWD_MAC_CTRL_RX_VAL_MASK      0x000001FF
-#define EC_FWD_MAC_CTRL_RX_VAL_SHIFT     0
-
-/* Drop indication */
-#define EC_FWD_MAC_CTRL_RX_VAL_DROP		(1 << 0)
-
-/* control table command input */
-#define EC_FWD_MAC_CTRL_RX_VAL_CTRL_CMD_MASK	0x00000006
-#define EC_FWD_MAC_CTRL_RX_VAL_CTRL_CMD_SHIFT	1
-
-/* UDMA selection */
-#define EC_FWD_MAC_CTRL_RX_VAL_UDMA_MASK	0x000000078
-#define EC_FWD_MAC_CTRL_RX_VAL_UDMA_SHIFT	3
-
-/* queue number */
-#define EC_FWD_MAC_CTRL_RX_VAL_QID_MASK		0x00000180
-#define EC_FWD_MAC_CTRL_RX_VAL_QID_SHIFT	7
-
-/* Entry is valid for Rx forwarding engine. */
-#define EC_FWD_MAC_CTRL_RX_VALID         (1 << 15)
-/* Control value for Tx forwarding engine */
-#define EC_FWD_MAC_CTRL_TX_VAL_MASK      0x001F0000
-#define EC_FWD_MAC_CTRL_TX_VAL_SHIFT     16
-/* Entry is valid for Tx forwarding engine. */
-#define EC_FWD_MAC_CTRL_TX_VALID         (1 << 31)
-
-/**** uc register ****/
-/* timer max value for waiting for a stream to be ready to accep ... */
-#define EC_MSW_UC_TIMER_MASK             0x0000FFFF
-#define EC_MSW_UC_TIMER_SHIFT            0
-/* Drop packet if target queue in the UDMA is full */
-#define EC_MSW_UC_Q_FULL_DROP_MASK       0x000F0000
-#define EC_MSW_UC_Q_FULL_DROP_SHIFT      16
-/* Drop packet if timer expires. */
-#define EC_MSW_UC_TIMER_DROP_MASK        0x0F000000
-#define EC_MSW_UC_TIMER_DROP_SHIFT       24
-
-/**** mc register ****/
-/* Timer max value for waiting for a stream to be ready to accep ... */
-#define EC_MSW_MC_TIMER_MASK             0x0000FFFF
-#define EC_MSW_MC_TIMER_SHIFT            0
-/* Drop packet if target queue in UDMA is full. */
-#define EC_MSW_MC_Q_FULL_DROP_MASK       0x000F0000
-#define EC_MSW_MC_Q_FULL_DROP_SHIFT      16
-/* Drop packet if timer expires. */
-#define EC_MSW_MC_TIMER_DROP_MASK        0x0F000000
-#define EC_MSW_MC_TIMER_DROP_SHIFT       24
-
-/**** bc register ****/
-/* Timer max value for waiting for a stream to be ready to accep ... */
-#define EC_MSW_BC_TIMER_MASK             0x0000FFFF
-#define EC_MSW_BC_TIMER_SHIFT            0
-/* Drop packet if target queue in UDMA is full. */
-#define EC_MSW_BC_Q_FULL_DROP_MASK       0x000F0000
-#define EC_MSW_BC_Q_FULL_DROP_SHIFT      16
-/* Drop packet if timer expires. */
-#define EC_MSW_BC_TIMER_DROP_MASK        0x0F000000
-#define EC_MSW_BC_TIMER_DROP_SHIFT       24
-
-/**** in_cfg register ****/
-/* Swap input bytes order */
-#define EC_TSO_IN_CFG_SWAP_BYTES         (1 << 0)
-/* Selects strict priority or round robin scheduling between GDM ... */
-#define EC_TSO_IN_CFG_SEL_SP_RR          (1 << 1)
-/* Selects scheduler numbering direction */
-#define EC_TSO_IN_CFG_SEL_SCH_DIR        (1 << 2)
-/* Minimum L2 packet size (not including FCS) */
-#define EC_TSO_IN_CFG_L2_MIN_SIZE_MASK   0x00007F00
-#define EC_TSO_IN_CFG_L2_MIN_SIZE_SHIFT  8
-/* Swap input bytes order */
-#define EC_TSO_IN_CFG_SP_INIT_VAL_MASK   0x000F0000
-#define EC_TSO_IN_CFG_SP_INIT_VAL_SHIFT  16
-
-/**** cache_table_addr register ****/
-/* Address for accessing the table */
-#define EC_TSO_CACHE_TABLE_ADDR_VAL_MASK 0x0000000F
-#define EC_TSO_CACHE_TABLE_ADDR_VAL_SHIFT 0
-
-/**** ctrl_first register ****/
-/* Data to be written into the control BIS. */
-#define EC_TSO_CTRL_FIRST_DATA_MASK      0x000001FF
-#define EC_TSO_CTRL_FIRST_DATA_SHIFT     0
-/* Mask for control bits */
-#define EC_TSO_CTRL_FIRST_MASK_MASK      0x01FF0000
-#define EC_TSO_CTRL_FIRST_MASK_SHIFT     16
-
-/**** ctrl_middle register ****/
-/* Data to be written into the control BIS. */
-#define EC_TSO_CTRL_MIDDLE_DATA_MASK     0x000001FF
-#define EC_TSO_CTRL_MIDDLE_DATA_SHIFT    0
-/* Mask for the control bits */
-#define EC_TSO_CTRL_MIDDLE_MASK_MASK     0x01FF0000
-#define EC_TSO_CTRL_MIDDLE_MASK_SHIFT    16
-
-/**** ctrl_last register ****/
-/* Data to be written into the control BIS. */
-#define EC_TSO_CTRL_LAST_DATA_MASK       0x000001FF
-#define EC_TSO_CTRL_LAST_DATA_SHIFT      0
-/* Mask for the control bits */
-#define EC_TSO_CTRL_LAST_MASK_MASK       0x01FF0000
-#define EC_TSO_CTRL_LAST_MASK_SHIFT      16
-
-/**** cfg_add_0 register ****/
-/* MSS selection option:0 - MSS value is selected using MSS_sel  ... */
-#define EC_TSO_CFG_ADD_0_MSS_SEL         (1 << 0)
-
-/**** cfg_tunnel register ****/
-/* Enable TSO with tunnelling */
-#define EC_TSO_CFG_TUNNEL_EN_TUNNEL_TSO  (1 << 0)
-/* Enable outer UDP checksum update */
-#define EC_TSO_CFG_TUNNEL_EN_UDP_CHKSUM  (1 << 8)
-/* Enable outer UDP length update */
-#define EC_TSO_CFG_TUNNEL_EN_UDP_LEN     (1 << 9)
-/* Enable outer Ip6  length update */
-#define EC_TSO_CFG_TUNNEL_EN_IPV6_PLEN   (1 << 10)
-/* Enable outer IPv4 checksum update */
-#define EC_TSO_CFG_TUNNEL_EN_IPV4_CHKSUM (1 << 11)
-/* Enable outer IPv4 Identification update */
-#define EC_TSO_CFG_TUNNEL_EN_IPV4_IDEN   (1 << 12)
-/* Enable outer IPv4 length update */
-#define EC_TSO_CFG_TUNNEL_EN_IPV4_TLEN   (1 << 13)
-
-/**** mss register ****/
-/* MSS value */
-#define EC_TSO_SEL_MSS_VAL_MASK          0x000FFFFF
-#define EC_TSO_SEL_MSS_VAL_SHIFT         0
-
-/**** parse register ****/
-/* Max number of bus beats for parsing */
-#define EC_TPE_PARSE_MAX_BEATS_MASK      0x0000FFFF
-#define EC_TPE_PARSE_MAX_BEATS_SHIFT     0
-
-/**** vlan_data register ****/
-/* UDMA default VLAN 1 data */
-#define EC_TPM_UDMA_VLAN_DATA_DEF_1_MASK 0x0000FFFF
-#define EC_TPM_UDMA_VLAN_DATA_DEF_1_SHIFT 0
-/* UDMA default VLAN 2 data */
-#define EC_TPM_UDMA_VLAN_DATA_DEF_2_MASK 0xFFFF0000
-#define EC_TPM_UDMA_VLAN_DATA_DEF_2_SHIFT 16
-
-/**** mac_sa_2 register ****/
-/* MAC source address data [47:32] */
-#define EC_TPM_UDMA_MAC_SA_2_H_VAL_MASK  0x0000FFFF
-#define EC_TPM_UDMA_MAC_SA_2_H_VAL_SHIFT 0
-/* Drop indication for MAC SA spoofing0 – Don't drop */
-#define EC_TPM_UDMA_MAC_SA_2_DROP        (1 << 16)
-/* Replace indication for MAC SA spoofing 0 - Don't replace */
-#define EC_TPM_UDMA_MAC_SA_2_REPLACE     (1 << 17)
-
-/**** etype register ****/
-/* Ether type value  */
-#define EC_TPM_SEL_ETYPE_VAL_MASK        0x0000FFFF
-#define EC_TPM_SEL_ETYPE_VAL_SHIFT       0
-
-/**** tx_wr_fifo register ****/
-/* Max data beats that can be used in the Tx FIFO */
-#define EC_TFW_TX_WR_FIFO_DATA_TH_MASK   0x0000FFFF
-#define EC_TFW_TX_WR_FIFO_DATA_TH_SHIFT  0
-/* Max packets that can be stored in the Tx FIFO */
-#define EC_TFW_TX_WR_FIFO_INFO_TH_MASK   0xFFFF0000
-#define EC_TFW_TX_WR_FIFO_INFO_TH_SHIFT  16
-
-/**** tx_vid_table_addr register ****/
-/* Address for accessing the table */
-#define EC_TFW_TX_VID_TABLE_ADDR_VAL_MASK 0x00000FFF
-#define EC_TFW_TX_VID_TABLE_ADDR_VAL_SHIFT 0
-
-/**** tx_vid_table_data register ****/
-/* Table data (valid only after configuring the table address re ... */
-#define EC_TFW_TX_VID_TABLE_DATA_VAL_MASK 0x0000001F
-#define EC_TFW_TX_VID_TABLE_DATA_VAL_SHIFT 0
-
-/**** tx_rd_fifo register ****/
-/* Read data threshold when cut through mode is enabled. */
-#define EC_TFW_TX_RD_FIFO_READ_TH_MASK   0x0000FFFF
-#define EC_TFW_TX_RD_FIFO_READ_TH_SHIFT  0
-/* Enable cut through operation of the Tx FIFO. */
-#define EC_TFW_TX_RD_FIFO_EN_CUT_THROUGH (1 << 16)
-
-/**** tx_checksum register ****/
-/* Enable L3 checksum insertion. */
-#define EC_TFW_TX_CHECKSUM_L3_EN         (1 << 0)
-/* Enable L4 checksum insertion. */
-#define EC_TFW_TX_CHECKSUM_L4_EN         (1 << 1)
-/* Enable L4 checksum when L3 fragmentation is detected. */
-#define EC_TFW_TX_CHECKSUM_L4_FRAG_EN    (1 << 2)
-
-/**** tx_gen register ****/
-/* Force forward of all Tx packets to MAC. */
-#define EC_TFW_TX_GEN_FWD_ALL_TO_MAC     (1 << 0)
-/* Select the Packet generator as the source of Tx packets0 - Tx ... */
-#define EC_TFW_TX_GEN_SELECT_PKT_GEN     (1 << 1)
-
-/**** tx_spf register ****/
-/* Select the VID for spoofing check:[0] - Packet VID[1] - Forwa ... */
-#define EC_TFW_TX_SPF_VID_SEL            (1 << 0)
-
-/**** data_fifo register ****/
-/* FIFO used value (number of entries) */
-#define EC_TFW_DATA_FIFO_USED_MASK       0x0000FFFF
-#define EC_TFW_DATA_FIFO_USED_SHIFT      0
-/* FIFO FULL status */
-#define EC_TFW_DATA_FIFO_FULL            (1 << 16)
-/* FIFO EMPTY status */
-#define EC_TFW_DATA_FIFO_EMPTY           (1 << 17)
-
-/**** ctrl_fifo register ****/
-/* FIFO used value (number of entries) */
-#define EC_TFW_CTRL_FIFO_USED_MASK       0x0000FFFF
-#define EC_TFW_CTRL_FIFO_USED_SHIFT      0
-/* FIFO FULL status */
-#define EC_TFW_CTRL_FIFO_FULL            (1 << 16)
-/* FIFO EMPTY status */
-#define EC_TFW_CTRL_FIFO_EMPTY           (1 << 17)
-
-/**** hdr_fifo register ****/
-/* FIFO used value (number of entries) */
-#define EC_TFW_HDR_FIFO_USED_MASK        0x0000FFFF
-#define EC_TFW_HDR_FIFO_USED_SHIFT       0
-/* FIFO FULL status */
-#define EC_TFW_HDR_FIFO_FULL             (1 << 16)
-/* FIFO EMPTY status */
-#define EC_TFW_HDR_FIFO_EMPTY            (1 << 17)
-
-/**** uc_udma register ****/
-/* Default UDMA bitmap
-(MSB represents physical port) */
-#define EC_TFW_UDMA_UC_UDMA_DEF_MASK     0x0000001F
-#define EC_TFW_UDMA_UC_UDMA_DEF_SHIFT    0
-
-/**** mc_udma register ****/
-/* Default UDMA bitmap (MSB represents physical port.) */
-#define EC_TFW_UDMA_MC_UDMA_DEF_MASK     0x0000001F
-#define EC_TFW_UDMA_MC_UDMA_DEF_SHIFT    0
-
-/**** bc_udma register ****/
-/* Default UDMA bitmap (MSB represents physical port.) */
-#define EC_TFW_UDMA_BC_UDMA_DEF_MASK     0x0000001F
-#define EC_TFW_UDMA_BC_UDMA_DEF_SHIFT    0
-
-/**** spf_cmd register ****/
-/* Command for the VLAN spoofing00 – Ignore  mismatch */
-#define EC_TFW_UDMA_SPF_CMD_VID_MASK     0x00000003
-#define EC_TFW_UDMA_SPF_CMD_VID_SHIFT    0
-/* Command for VLAN spoofing 00 - Ignore  mismatch */
-#define EC_TFW_UDMA_SPF_CMD_MAC_MASK     0x0000000C
-#define EC_TFW_UDMA_SPF_CMD_MAC_SHIFT    2
-
-/**** fwd_dec register ****/
-/* Forwarding decision control:[0] – Enable internal switch */
-#define EC_TFW_UDMA_FWD_DEC_CTRL_MASK    0x000003FF
-#define EC_TFW_UDMA_FWD_DEC_CTRL_SHIFT   0
-
-/**** tx_cfg register ****/
-/* Swap output byte order */
-#define EC_TMI_TX_CFG_SWAP_BYTES         (1 << 0)
-/* Enable forwarding to the Rx data path. */
-#define EC_TMI_TX_CFG_EN_FWD_TO_RX       (1 << 1)
-/* Force forwarding all packets to the MAC. */
-#define EC_TMI_TX_CFG_FORCE_FWD_MAC      (1 << 2)
-/* Force forwarding all packets to the MAC. */
-#define EC_TMI_TX_CFG_FORCE_FWD_RX       (1 << 3)
-/* Force loop back operation */
-#define EC_TMI_TX_CFG_FORCE_LB           (1 << 4)
-
-/**** ec_pause register ****/
-/* Mask of pause_on [7:0] */
-#define EC_EFC_EC_PAUSE_MASK_MAC_MASK    0x000000FF
-#define EC_EFC_EC_PAUSE_MASK_MAC_SHIFT   0
-/* Mask of GPIO input [7:0] */
-#define EC_EFC_EC_PAUSE_MASK_GPIO_MASK   0x0000FF00
-#define EC_EFC_EC_PAUSE_MASK_GPIO_SHIFT  8
-
-/**** ec_xoff register ****/
-/* Mask 1 for XOFF [7:0]
-Mask 1 for Almost Full indication, */
-#define EC_EFC_EC_XOFF_MASK_1_MASK       0x000000FF
-#define EC_EFC_EC_XOFF_MASK_1_SHIFT      0
-/* Mask 2 for XOFF [7:0] Mask 2 for sampled Almost Full indicati ... */
-#define EC_EFC_EC_XOFF_MASK_2_MASK       0x0000FF00
-#define EC_EFC_EC_XOFF_MASK_2_SHIFT      8
-
-/**** xon register ****/
-/* Mask 1 for generating XON pulse, masking XOFF [0] */
-#define EC_EFC_XON_MASK_1                (1 << 0)
-/* Mask 2 for generating XON pulse, masking Almost Full indicati ... */
-#define EC_EFC_XON_MASK_2                (1 << 1)
-
-/**** gpio register ****/
-/* Mask for generating GPIO output XOFF indication from XOFF[0] */
-#define EC_EFC_GPIO_MASK_1               (1 << 0)
-
-/**** rx_fifo_af register ****/
-/* Threshold */
-#define EC_EFC_RX_FIFO_AF_TH_MASK        0x0000FFFF
-#define EC_EFC_RX_FIFO_AF_TH_SHIFT       0
-
-/**** rx_fifo_hyst register ****/
-/* Threshold low */
-#define EC_EFC_RX_FIFO_HYST_TH_LOW_MASK  0x0000FFFF
-#define EC_EFC_RX_FIFO_HYST_TH_LOW_SHIFT 0
-/* Threshold high */
-#define EC_EFC_RX_FIFO_HYST_TH_HIGH_MASK 0xFFFF0000
-#define EC_EFC_RX_FIFO_HYST_TH_HIGH_SHIFT 16
-
-/**** stat register ****/
-/* 10G MAC PFC mode, input from the 10 MAC */
-#define EC_EFC_STAT_PFC_MODE             (1 << 0)
-
-/**** ec_pfc register ****/
-/* Force PFC flow control */
-#define EC_EFC_EC_PFC_FORCE_MASK         0x000000FF
-#define EC_EFC_EC_PFC_FORCE_SHIFT        0
-
-/**** q_pause_0 register ****/
-/* [i] – Mask for Q[i] */
-#define EC_FC_UDMA_Q_PAUSE_0_MASK_MASK   0x0000000F
-#define EC_FC_UDMA_Q_PAUSE_0_MASK_SHIFT  0
-
-/**** q_pause_1 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_PAUSE_1_MASK_MASK   0x0000000F
-#define EC_FC_UDMA_Q_PAUSE_1_MASK_SHIFT  0
-
-/**** q_pause_2 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_PAUSE_2_MASK_MASK   0x0000000F
-#define EC_FC_UDMA_Q_PAUSE_2_MASK_SHIFT  0
-
-/**** q_pause_3 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_PAUSE_3_MASK_MASK   0x0000000F
-#define EC_FC_UDMA_Q_PAUSE_3_MASK_SHIFT  0
-
-/**** q_pause_4 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_PAUSE_4_MASK_MASK   0x0000000F
-#define EC_FC_UDMA_Q_PAUSE_4_MASK_SHIFT  0
-
-/**** q_pause_5 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_PAUSE_5_MASK_MASK   0x0000000F
-#define EC_FC_UDMA_Q_PAUSE_5_MASK_SHIFT  0
-
-/**** q_pause_6 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_PAUSE_6_MASK_MASK   0x0000000F
-#define EC_FC_UDMA_Q_PAUSE_6_MASK_SHIFT  0
-
-/**** q_pause_7 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_PAUSE_7_MASK_MASK   0x0000000F
-#define EC_FC_UDMA_Q_PAUSE_7_MASK_SHIFT  0
-
-/**** q_gpio_0 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_GPIO_0_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_GPIO_0_MASK_SHIFT   0
-
-/**** q_gpio_1 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_GPIO_1_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_GPIO_1_MASK_SHIFT   0
-
-/**** q_gpio_2 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_GPIO_2_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_GPIO_2_MASK_SHIFT   0
-
-/**** q_gpio_3 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_GPIO_3_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_GPIO_3_MASK_SHIFT   0
-
-/**** q_gpio_4 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_GPIO_4_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_GPIO_4_MASK_SHIFT   0
-
-/**** q_gpio_5 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_GPIO_5_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_GPIO_5_MASK_SHIFT   0
-
-/**** q_gpio_6 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_GPIO_6_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_GPIO_6_MASK_SHIFT   0
-
-/**** q_gpio_7 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_GPIO_7_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_GPIO_7_MASK_SHIFT   0
-
-/**** s_pause register ****/
-/* Mask of pause_on [7:0] */
-#define EC_FC_UDMA_S_PAUSE_MASK_MAC_MASK 0x000000FF
-#define EC_FC_UDMA_S_PAUSE_MASK_MAC_SHIFT 0
-/* Mask of GPIO input  [7:0] */
-#define EC_FC_UDMA_S_PAUSE_MASK_GPIO_MASK 0x0000FF00
-#define EC_FC_UDMA_S_PAUSE_MASK_GPIO_SHIFT 8
-
-/**** q_xoff_0 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_XOFF_0_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_XOFF_0_MASK_SHIFT   0
-
-/**** q_xoff_1 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_XOFF_1_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_XOFF_1_MASK_SHIFT   0
-
-/**** q_xoff_2 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_XOFF_2_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_XOFF_2_MASK_SHIFT   0
-
-/**** q_xoff_3 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_XOFF_3_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_XOFF_3_MASK_SHIFT   0
-
-/**** q_xoff_4 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_XOFF_4_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_XOFF_4_MASK_SHIFT   0
-
-/**** q_xoff_5 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_XOFF_5_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_XOFF_5_MASK_SHIFT   0
-
-/**** q_xoff_6 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_XOFF_6_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_XOFF_6_MASK_SHIFT   0
-
-/**** q_xoff_7 register ****/
-/* [i] - Mask for Q[i] */
-#define EC_FC_UDMA_Q_XOFF_7_MASK_MASK    0x0000000F
-#define EC_FC_UDMA_Q_XOFF_7_MASK_SHIFT   0
-
-/**** cfg_e register ****/
-/* Use MAC Tx FIFO empty status for EEE control. */
-#define EC_EEE_CFG_E_USE_MAC_TX_FIFO     (1 << 0)
-/* Use MAC Rx FIFO empty status for EEE control. */
-#define EC_EEE_CFG_E_USE_MAC_RX_FIFO     (1 << 1)
-/* Use Ethernet controller Tx FIFO empty status for EEE control */
-#define EC_EEE_CFG_E_USE_EC_TX_FIFO      (1 << 2)
-/* Use Ethernet controller Rx FIFO empty status for EEE control */
-#define EC_EEE_CFG_E_USE_EC_RX_FIFO      (1 << 3)
-/* Enable Low power signalling. */
-#define EC_EEE_CFG_E_ENABLE              (1 << 4)
-/* Mask output to MAC.  */
-#define EC_EEE_CFG_E_MASK_MAC_EEE        (1 << 8)
-/* Mask output to stop MAC interface. */
-#define EC_EEE_CFG_E_MASK_EC_TMI_STOP    (1 << 9)
-
-/**** stat_eee register ****/
-/* EEE state */
-#define EC_EEE_STAT_EEE_STATE_MASK       0x0000000F
-#define EC_EEE_STAT_EEE_STATE_SHIFT      0
-/* EEE detected */
-#define EC_EEE_STAT_EEE_DET              (1 << 4)
-
-/**** p_parse_cfg register ****/
-/* MAX number of beats for packet parsing */
-#define EC_MSP_P_PARSE_CFG_MAX_BEATS_MASK 0x000000FF
-#define EC_MSP_P_PARSE_CFG_MAX_BEATS_SHIFT 0
-/* MAX number of parsing iterations for packet parsing */
-#define EC_MSP_P_PARSE_CFG_MAX_ITER_MASK 0x0000FF00
-#define EC_MSP_P_PARSE_CFG_MAX_ITER_SHIFT 8
-
-/**** p_act_table_addr register ****/
-/* Address for accessing the table */
-#define EC_MSP_P_ACT_TABLE_ADDR_VAL_MASK 0x0000001F
-#define EC_MSP_P_ACT_TABLE_ADDR_VAL_SHIFT 0
-
-/**** p_act_table_data_1 register ****/
-/* Table data[5:0] - Offset to next protocol [bytes] [6] - Next  ... */
-#define EC_MSP_P_ACT_TABLE_DATA_1_VAL_MASK 0x03FFFFFF
-#define EC_MSP_P_ACT_TABLE_DATA_1_VAL_SHIFT 0
-
-/**** p_act_table_data_2 register ****/
-/* Table data  [8:0] - Offset to data in the packet [bits][17:9] ... */
-#define EC_MSP_P_ACT_TABLE_DATA_2_VAL_MASK 0x1FFFFFFF
-#define EC_MSP_P_ACT_TABLE_DATA_2_VAL_SHIFT 0
-
-/**** p_act_table_data_3 register ****/
-/* Table data   [8:0] - Offset to data in the packet [bits]  [17 ... */
-#define EC_MSP_P_ACT_TABLE_DATA_3_VAL_MASK 0x1FFFFFFF
-#define EC_MSP_P_ACT_TABLE_DATA_3_VAL_SHIFT 0
-
-/**** p_act_table_data_4 register ****/
-/* Table data [7:0] - Offset to the header length location in th ... */
-#define EC_MSP_P_ACT_TABLE_DATA_4_VAL_MASK 0x0FFFFFFF
-#define EC_MSP_P_ACT_TABLE_DATA_4_VAL_SHIFT 0
-
-/**** p_act_table_data_6 register ****/
-/* Table data [0] - Wr header length [10:1] - Write header lengt ... */
-#define EC_MSP_P_ACT_TABLE_DATA_6_VAL_MASK 0x007FFFFF
-#define EC_MSP_P_ACT_TABLE_DATA_6_VAL_SHIFT 0
-
-/**** p_res_in register ****/
-/* Selector for input parse_en 0 - Input vector 1 - Default valu ... */
-#define EC_MSP_P_RES_IN_SEL_PARSE_EN     (1 << 0)
-/* Selector for input protocol_index  0 - Input vector  1 - Defa ... */
-#define EC_MSP_P_RES_IN_SEL_PROT_INDEX   (1 << 1)
-/* Selector for input hdr_offset  0 - Input vector 1 - Default v ... */
-#define EC_MSP_P_RES_IN_SEL_HDR_OFFSET   (1 << 2)
-
-/**** h_hdr_len register ****/
-/* Value for selecting table 1 */
-#define EC_MSP_P_H_HDR_LEN_TABLE_1_MASK  0x000000FF
-#define EC_MSP_P_H_HDR_LEN_TABLE_1_SHIFT 0
-/* Value for selecting table 2 */
-#define EC_MSP_P_H_HDR_LEN_TABLE_2_MASK  0x00FF0000
-#define EC_MSP_P_H_HDR_LEN_TABLE_2_SHIFT 16
-
-/**** p_comp_data register ****/
-/* Data 1 for comparison */
-#define EC_MSP_C_P_COMP_DATA_DATA_1_MASK 0x0000FFFF
-#define EC_MSP_C_P_COMP_DATA_DATA_1_SHIFT 0
-/* Data 2 for comparison
-[18:16] - Stage
-[24:19] - Branch ID */
-#define EC_MSP_C_P_COMP_DATA_DATA_2_MASK 0x01FF0000
-#define EC_MSP_C_P_COMP_DATA_DATA_2_SHIFT 16
-
-/**** p_comp_mask register ****/
-/* Data 1 for comparison */
-#define EC_MSP_C_P_COMP_MASK_DATA_1_MASK 0x0000FFFF
-#define EC_MSP_C_P_COMP_MASK_DATA_1_SHIFT 0
-/* Data 2 for comparison
-[18:16] - Stage
-[24:19] - Branch ID */
-#define EC_MSP_C_P_COMP_MASK_DATA_2_MASK 0x01FF0000
-#define EC_MSP_C_P_COMP_MASK_DATA_2_SHIFT 16
-
-/**** p_comp_ctrl register ****/
-/* Output result value */
-#define EC_MSP_C_P_COMP_CTRL_RES_MASK    0x0000001F
-#define EC_MSP_C_P_COMP_CTRL_RES_SHIFT   0
-/* Compare command for the data_1 field 00 - Compare 01 - <= 10  ... */
-#define EC_MSP_C_P_COMP_CTRL_CMD_1_MASK  0x00030000
-#define EC_MSP_C_P_COMP_CTRL_CMD_1_SHIFT 16
-/* Compare command for the data_2 field 00 - Compare 01 - <= 10  ... */
-#define EC_MSP_C_P_COMP_CTRL_CMD_2_MASK  0x000C0000
-#define EC_MSP_C_P_COMP_CTRL_CMD_2_SHIFT 18
-/* Entry is valid */
-#define EC_MSP_C_P_COMP_CTRL_VALID       (1 << 31)
-
-/**** wol_en register ****/
-/* Interrupt enable WoL MAC DA Unicast detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_UNICAST  (1 << 0)
-/* Interrupt enable WoL L2 Multicast detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_MULTICAST (1 << 1)
-/* Interrupt enable WoL L2 Broadcast detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_BROADCAST (1 << 2)
-/* Interrupt enable WoL IPv4 detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_IPV4     (1 << 3)
-/* Interrupt enable WoL IPv6 detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_IPV6     (1 << 4)
-/* Interrupt enable WoL EtherType+MAC DA detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_ETHERTYPE_DA (1 << 5)
-/* Interrupt enable WoL EtherType+L2 Broadcast detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_ETHERTYPE_BC (1 << 6)
-/* Interrupt enable WoL parser detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_PARSER   (1 << 7)
-/* Interrupt enable WoL magic detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_MAGIC    (1 << 8)
-/* Interrupt enable WoL magic+password detected  packet */
-#define EC_WOL_WOL_EN_INTRPT_EN_MAGIC_PSWD (1 << 9)
-/* Forward enable WoL MAC DA Unicast detected  packet */
-#define EC_WOL_WOL_EN_FWRD_EN_UNICAST    (1 << 16)
-/* Forward enable WoL L2 Multicast detected  packet */
-#define EC_WOL_WOL_EN_FWRD_EN_MULTICAST  (1 << 17)
-/* Forward enable WoL L2 Broadcast detected  packet */
-#define EC_WOL_WOL_EN_FWRD_EN_BROADCAST  (1 << 18)
-/* Forward enable WoL IPv4 detected  packet */
-#define EC_WOL_WOL_EN_FWRD_EN_IPV4       (1 << 19)
-/* Forward enable WoL IPv6 detected  packet */
-#define EC_WOL_WOL_EN_FWRD_EN_IPV6       (1 << 20)
-/* Forward enable WoL EtherType+MAC DA detected  packet */
-#define EC_WOL_WOL_EN_FWRD_EN_ETHERTYPE_DA (1 << 21)
-/* Forward enable WoL EtherType+L2 Broadcast detected  packet */
-#define EC_WOL_WOL_EN_FWRD_EN_ETHERTYPE_BC (1 << 22)
-/* Forward enable WoL parser detected  packet */
-#define EC_WOL_WOL_EN_FWRD_EN_PARSER     (1 << 23)
-
-/**** magic_pswd_h register ****/
-/* Password for magic_password packet detection - bits 47:32 */
-#define EC_WOL_MAGIC_PSWD_H_VAL_MASK     0x0000FFFF
-#define EC_WOL_MAGIC_PSWD_H_VAL_SHIFT    0
-
-/**** ethertype register ****/
-/* Configured EtherType 1 for WoL EtherType_da/EtherType_bc pack ... */
-#define EC_WOL_ETHERTYPE_VAL_1_MASK      0x0000FFFF
-#define EC_WOL_ETHERTYPE_VAL_1_SHIFT     0
-/* Configured EtherType 2 for WoL EtherType_da/EtherType_bc pack ... */
-#define EC_WOL_ETHERTYPE_VAL_2_MASK      0xFFFF0000
-#define EC_WOL_ETHERTYPE_VAL_2_SHIFT     16
-
-#define EC_PTH_SYSTEM_TIME_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_SYSTEM_TIME_SUBSECONDS_LSB_VAL_SHIFT 14
-
-#define EC_PTH_CLOCK_PERIOD_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_CLOCK_PERIOD_LSB_VAL_SHIFT 14
-
-/**** int_update_ctrl register ****/
-/* This field chooses between two methods for SW to update the s ... */
-#define EC_PTH_INT_UPDATE_CTRL_UPDATE_TRIG (1 << 0)
-/* 3'b000 - Set system time according to the value in {int_updat ... */
-#define EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_MASK 0x0000000E
-#define EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_SHIFT 1
-/* 1'b1 - Next update writes to system_time_subseconds1'b0 - Nex ... */
-#define EC_PTH_INT_UPDATE_CTRL_SUBSECOND_MASK (1 << 4)
-/* 1'b1 - Next update writes to system_time_seconds1'b0 - Next u ... */
-#define EC_PTH_INT_UPDATE_CTRL_SECOND_MASK (1 << 5)
-/* Enabling / disabling the internal ingress trigger (ingress_tr ... */
-#define EC_PTH_INT_UPDATE_CTRL_INT_TRIG_EN (1 << 16)
-/* Determines if internal ingress trigger (ingress_trigger #0) s ... */
-#define EC_PTH_INT_UPDATE_CTRL_PULSE_LEVEL_N (1 << 17)
-/* Internal ingress trigger polarity (ingress_trigger #0)1'b0 -  ... */
-#define EC_PTH_INT_UPDATE_CTRL_POLARITY  (1 << 18)
-
-/**** int_update_subseconds_lsb register ****/
-
-#define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF
-#define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0
-
-#define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT 14
-/* 3'b000 - Set system time according to the value in {int_updat ... */
-#define EC_PTH_EXT_UPDATE_CTRL_UPDATE_METHOD_MASK 0x0000000E
-#define EC_PTH_EXT_UPDATE_CTRL_UPDATE_METHOD_SHIFT 1
-/* 1'b1 - next update writes to system_time_subseconds1'b0 - nex ... */
-#define EC_PTH_EXT_UPDATE_CTRL_SUBSECOND_MASK (1 << 4)
-/* 1'b1 - Next update writes to system_time_seconds1'b0 - Next u ... */
-#define EC_PTH_EXT_UPDATE_CTRL_SECOND_MASK (1 << 5)
-/* Enabling / disabling the external ingress triggers (ingress_t ... */
-#define EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_MASK 0x00001F00
-#define EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_SHIFT 8
-/* Determines if external ingress triggers (ingress_triggers #1- ... */
-#define EC_PTH_EXT_UPDATE_CTRL_PULSE_LEVEL_N_MASK 0x001F0000
-#define EC_PTH_EXT_UPDATE_CTRL_PULSE_LEVEL_N_SHIFT 16
-/* bit-field configurations of external ingress trigger polarity ... */
-#define EC_PTH_EXT_UPDATE_CTRL_POLARITY_MASK 0x1F000000
-#define EC_PTH_EXT_UPDATE_CTRL_POLARITY_SHIFT 24
-
-/**** ext_update_subseconds_lsb register ****/
-
-#define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF
-#define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0
-
-#define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT 14
-
-#define EC_PTH_READ_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_READ_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14
-
-#define EC_PTH_INT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_INT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14
-
-#define EC_PTH_EXT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_EXT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14
-
-#define EC_PTH_SYNC_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_SYNC_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14
-
-/**** trigger_ctrl register ****/
-/* Enabling / disabling the egress trigger1'b1 - Enabled1'b0 - D ... */
-#define EC_PTH_EGRESS_TRIGGER_CTRL_EN    (1 << 0)
-/* Configuration that determines if the egress trigger is a peri ... */
-#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIODIC (1 << 1)
-/* Configuration of egress trigger polarity */
-#define EC_PTH_EGRESS_TRIGGER_CTRL_POLARITY (1 << 2)
-/* If the pulse is marked as periodic (see periodic field), this ... */
-#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_MASK 0x00FFFFF0
-#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_SHIFT 4
-/* If the pulse is marked as periodic (see periodic field), this ... */
-#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_MASK 0xFF000000
-#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_SHIFT 24
-
-/**** trigger_subseconds_lsb register ****/
-
-#define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF
-#define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0
-
-#define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_VAL_SHIFT 14
-
-/**** pulse_width_subseconds_lsb register ****/
-
-#define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF
-#define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0
-
-#define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
-#define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_VAL_SHIFT 14
-
-/**** qual register ****/
-
-#define EC_PTH_DB_QUAL_TS_VALID       (1 << 0)
-
-#define EC_PTH_DB_QUAL_RESERVED_31_1_MASK 0xFFFFFFFE
-#define EC_PTH_DB_QUAL_RESERVED_31_1_SHIFT 1
-
-/**** rx_comp_desc register ****/
-/* Selection for word0[13]:0- legacy SR-A01- per generic protoco ... */
-#define EC_GEN_V3_RX_COMP_DESC_W0_L3_CKS_RES_SEL (1 << 0)
-/* Selection for word0[14]:0- legacy SR-A01- per generic protoco ... */
-#define EC_GEN_V3_RX_COMP_DESC_W0_L4_CKS_RES_SEL (1 << 1)
-/* Selection for word3[29]:0-macsec decryption status[13] (legac ... */
-#define EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_13_L4_CKS_RES_SEL (1 << 8)
-/* Selection for word3[30]:0-macsec decryption status[14] (legac ... */
-#define EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_14_L3_CKS_RES_SEL (1 << 9)
-/* Selection for word3[31]:0-macsec decryption status[15] (legac ... */
-#define EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_15_CRC_RES_SEL (1 << 10)
-/* Selection for word 0 [6:5], source VLAN count0- source vlan c ... */
-#define EC_GEN_V3_RX_COMP_DESC_W0_SRC_VLAN_CNT (1 << 12)
-/* Selection for word 0 [4:0], l3 protocol index0-  l3 protocol  ... */
-#define EC_GEN_V3_RX_COMP_DESC_W0_L3_PROT_INDEX (1 << 13)
-/* Selection for word 1 [31:16], lP fragment checksum0-  IP frag ... */
-#define EC_GEN_V3_RX_COMP_DESC_W1_IP_FRAG_CHECKSUM (1 << 14)
-/* Selection for word 2 [15:9], L3 offset0-  LL3 offset1- CRC re ... */
-#define EC_GEN_V3_RX_COMP_DESC_W2_L3_OFFSET (1 << 15)
-/* Selection for word 2 [8:0], tunnel offset0-  tunnel offset1-  ... */
-#define EC_GEN_V3_RX_COMP_DESC_W2_TUNNEL_OFFSET (1 << 16)
-
-/**** conf register ****/
-/* Valid signal configuration when in loopback mode:00 - valid f ... */
-#define EC_GEN_V3_CONF_MAC_LB_EC_OUT_S_VALID_CFG_MASK 0x00000003
-#define EC_GEN_V3_CONF_MAC_LB_EC_OUT_S_VALID_CFG_SHIFT 0
-/* Valid signal configuration when in loopback mode:00 – valid f ... */
-#define EC_GEN_V3_CONF_MAC_LB_EC_IN_S_VALID_CFG_MASK 0x0000000C
-#define EC_GEN_V3_CONF_MAC_LB_EC_IN_S_VALID_CFG_SHIFT 2
-
-/**** tx_gpd_cam_addr register ****/
-/* Cam compare table address */
-#define EC_TFW_V3_TX_GPD_CAM_ADDR_VAL_MASK 0x0000001F
-#define EC_TFW_V3_TX_GPD_CAM_ADDR_VAL_SHIFT 0
-/* cam entry is valid */
-#define EC_TFW_V3_TX_GPD_CAM_CTRL_VALID  (1 << 31)
-
-/**** tx_gcp_legacy register ****/
-/* 0-choose parameters from table1- choose legacy crce roce para ... */
-#define EC_TFW_V3_TX_GCP_LEGACY_PARAM_SEL (1 << 0)
-
-/**** tx_gcp_table_addr register ****/
-/* parametrs table address */
-#define EC_TFW_V3_TX_GCP_TABLE_ADDR_VAL_MASK 0x0000001F
-#define EC_TFW_V3_TX_GCP_TABLE_ADDR_VAL_SHIFT 0
-
-/**** tx_gcp_table_gen register ****/
-/* polynomial selcet
-0-crc32(0x104C11DB7)
-1-crc32c(0x11EDC6F41) */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_POLY_SEL (1 << 0)
-/* Enable bit complement on crc result */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_CRC32_BIT_COMP (1 << 1)
-/* Enable bit swap on crc result */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_CRC32_BIT_SWAP (1 << 2)
-/* Enable byte swap on crc result */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_CRC32_BYTE_SWAP (1 << 3)
-/* Enable bit swap on input data */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_DATA_BIT_SWAP (1 << 4)
-/* Enable byte swap on input data */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_DATA_BYTE_SWAP (1 << 5)
-/* Number of bytes in trailer which are not part of crc calculat ... */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_TRAIL_SIZE_MASK 0x000003C0
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_TRAIL_SIZE_SHIFT 6
-/* Number of bytes in header which are not part of crc calculati ... */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_HEAD_SIZE_MASK 0x00FF0000
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_HEAD_SIZE_SHIFT 16
-/* corrected offset calculation0- subtract head_size (roce)1- ad ... */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_HEAD_CALC (1 << 24)
-/* 0-replace masked bits with 01-replace masked bits with 1 (roc ... */
-#define EC_TFW_V3_TX_GCP_TABLE_GEN_MASK_POLARITY (1 << 25)
-
-/**** tx_gcp_table_res register ****/
-/* Not in use */
-#define EC_TFW_V3_TX_GCP_TABLE_RES_SEL_MASK 0x0000001F
-#define EC_TFW_V3_TX_GCP_TABLE_RES_SEL_SHIFT 0
-/* Not in use */
-#define EC_TFW_V3_TX_GCP_TABLE_RES_EN    (1 << 5)
-/* Not in use */
-#define EC_TFW_V3_TX_GCP_TABLE_RES_DEF   (1 << 6)
-
-/**** tx_gcp_table_alu_opcode register ****/
-/* first opcode
-e.g. (A op1 B) op3 (C op2 D) */
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_1_MASK 0x0000003F
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_1_SHIFT 0
-/* second opcode
-e.g. (A op1 B) op3 (C op2 D) */
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_2_MASK 0x00000FC0
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_2_SHIFT 6
-/* third opcode
-e.g. (A op1 B) op3 (C op2 D) */
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_3_MASK 0x0003F000
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_3_SHIFT 12
-
-/**** tx_gcp_table_alu_opsel register ****/
-/* frst opsel, input selection */
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_1_MASK 0x0000000F
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_1_SHIFT 0
-/* second opsel, input selection */
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_2_MASK 0x000000F0
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_2_SHIFT 4
-/* third opsel, input selction */
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_3_MASK 0x00000F00
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_3_SHIFT 8
-/* fourth opsel, input selction */
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_4_MASK 0x0000F000
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_4_SHIFT 12
-
-/**** tx_gcp_table_alu_val register ****/
-/* value for alu input */
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_VAL_VAL_MASK 0x000001FF
-#define EC_TFW_V3_TX_GCP_TABLE_ALU_VAL_VAL_SHIFT 0
-
-/**** crc_csum_replace register ****/
-/* 0- use table
-1- legacy SR-A0 */
-#define EC_TFW_V3_CRC_CSUM_REPLACE_L3_CSUM_LEGACY_SEL (1 << 0)
-/* 0- use table
-1- legacy SR-A0 */
-#define EC_TFW_V3_CRC_CSUM_REPLACE_L4_CSUM_LEGACY_SEL (1 << 1)
-/* 0- use table
-1- legacy SR-A0 */
-#define EC_TFW_V3_CRC_CSUM_REPLACE_CRC_LEGACY_SEL (1 << 2)
-
-/**** crc_csum_replace_table_addr register ****/
-/* parametrs table address */
-#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_ADDR_VAL_MASK 0x0000007F
-#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_ADDR_VAL_SHIFT 0
-
-/**** crc_csum_replace_table register ****/
-/* L3 Checksum replace enable */
-#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_L3_CSUM_EN (1 << 0)
-/* L4 Checksum replace enable */
-#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_L4_CSUM_EN (1 << 1)
-/* CRC replace enable */
-#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_CRC_EN (1 << 2)
-
-/**** rx_gpd_cam_addr register ****/
-/* Cam compare table address */
-#define EC_RFW_V3_RX_GPD_CAM_ADDR_VAL_MASK 0x0000001F
-#define EC_RFW_V3_RX_GPD_CAM_ADDR_VAL_SHIFT 0
-/* cam entry is valid */
-#define EC_RFW_V3_RX_GPD_CAM_CTRL_VALID  (1 << 31)
-
-/**** gpd_p1 register ****/
-/* Location in bytes of the gpd cam data1 in the parser result v ... */
-#define EC_RFW_V3_GPD_P1_OFFSET_MASK     0x000003FF
-#define EC_RFW_V3_GPD_P1_OFFSET_SHIFT    0
-
-/**** gpd_p2 register ****/
-/* Location in bytes of the gpd cam data2 in the parser result v ... */
-#define EC_RFW_V3_GPD_P2_OFFSET_MASK     0x000003FF
-#define EC_RFW_V3_GPD_P2_OFFSET_SHIFT    0
-
-/**** gpd_p3 register ****/
-/* Location in bytes of the gpd cam data3 in the parser result v ... */
-#define EC_RFW_V3_GPD_P3_OFFSET_MASK     0x000003FF
-#define EC_RFW_V3_GPD_P3_OFFSET_SHIFT    0
-
-/**** gpd_p4 register ****/
-/* Location in bytes of the gpd cam data4 in the parser result v ... */
-#define EC_RFW_V3_GPD_P4_OFFSET_MASK     0x000003FF
-#define EC_RFW_V3_GPD_P4_OFFSET_SHIFT    0
-
-/**** gpd_p5 register ****/
-/* Location in bytes of the gpd cam data5 in the parser result v ... */
-#define EC_RFW_V3_GPD_P5_OFFSET_MASK     0x000003FF
-#define EC_RFW_V3_GPD_P5_OFFSET_SHIFT    0
-
-/**** gpd_p6 register ****/
-/* Location in bytes of the gpd cam data6 in the parser result v ... */
-#define EC_RFW_V3_GPD_P6_OFFSET_MASK     0x000003FF
-#define EC_RFW_V3_GPD_P6_OFFSET_SHIFT    0
-
-/**** gpd_p7 register ****/
-/* Location in bytes of the gpd cam data7 in the parser result v ... */
-#define EC_RFW_V3_GPD_P7_OFFSET_MASK     0x000003FF
-#define EC_RFW_V3_GPD_P7_OFFSET_SHIFT    0
-
-/**** gpd_p8 register ****/
-/* Location in bytes of the gpd cam data8 in the parser result v ... */
-#define EC_RFW_V3_GPD_P8_OFFSET_MASK     0x000003FF
-#define EC_RFW_V3_GPD_P8_OFFSET_SHIFT    0
-
-/**** rx_gcp_legacy register ****/
-/* 0-choose parameters from table1- choose legacy crce roce para ... */
-#define EC_RFW_V3_RX_GCP_LEGACY_PARAM_SEL (1 << 0)
-
-/**** rx_gcp_table_addr register ****/
-/* parametrs table address */
-#define EC_RFW_V3_RX_GCP_TABLE_ADDR_VAL_MASK 0x0000001F
-#define EC_RFW_V3_RX_GCP_TABLE_ADDR_VAL_SHIFT 0
-
-/**** rx_gcp_table_gen register ****/
-/* polynomial selcet
-0-crc32(0x104C11DB7)
-1-crc32c(0x11EDC6F41) */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_POLY_SEL (1 << 0)
-/* Enable bit complement on crc result */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_CRC32_BIT_COMP (1 << 1)
-/* Enable bit swap on crc result */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_CRC32_BIT_SWAP (1 << 2)
-/* Enable byte swap on crc result */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_CRC32_BYTE_SWAP (1 << 3)
-/* Enable bit swap on input data */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_DATA_BIT_SWAP (1 << 4)
-/* Enable byte swap on input data */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_DATA_BYTE_SWAP (1 << 5)
-/* Number of bytes in trailer which are not part of crc calculat ... */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_TRAIL_SIZE_MASK 0x000003C0
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_TRAIL_SIZE_SHIFT 6
-/* Number of bytes in header which are not part of crc calculati ... */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_HEAD_SIZE_MASK 0x00FF0000
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_HEAD_SIZE_SHIFT 16
-/* corrected offset calculation0- subtract head_size (roce)1- ad ... */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_HEAD_CALC (1 << 24)
-/* 0-replace masked bits with 01-replace masked bits with 1 (roc ... */
-#define EC_RFW_V3_RX_GCP_TABLE_GEN_MASK_POLARITY (1 << 25)
-
-/**** rx_gcp_table_res register ****/
-/* Bit mask for crc/checksum result options for metadata W0[13][ ... */
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_0_MASK 0x0000001F
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_0_SHIFT 0
-/* Bit mask for crc/checksum result options for metadata W0[14][ ... */
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_1_MASK 0x000003E0
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_1_SHIFT 5
-/* Bit mask for crc/checksum result options for metadata W3[29][ ... */
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_2_MASK 0x00007C00
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_2_SHIFT 10
-/* Bit mask for crc/checksum result options for metadata W3[30][ ... */
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_3_MASK 0x000F8000
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_3_SHIFT 15
-/* Bit mask for crc/checksum result options for metadata W3[31][ ... */
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_4_MASK 0x01F00000
-#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_4_SHIFT 20
-/* enable crc result check */
-#define EC_RFW_V3_RX_GCP_TABLE_RES_EN    (1 << 25)
-/* default value for crc check for non-crc protocol */
-#define EC_RFW_V3_RX_GCP_TABLE_RES_DEF   (1 << 26)
-
-/**** rx_gcp_table_alu_opcode register ****/
-/* first opcode
-e.g. (A op1 B) op3 (C op2 D) */
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_1_MASK 0x0000003F
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_1_SHIFT 0
-/* second opcode
-e.g. (A op1 B) op3 (C op2 D) */
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_2_MASK 0x00000FC0
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_2_SHIFT 6
-/* third opcode
-e.g. (A op1 B) op3 (C op2 D) */
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_3_MASK 0x0003F000
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_3_SHIFT 12
-
-/**** rx_gcp_table_alu_opsel register ****/
-/* frst opsel, input selection */
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_1_MASK 0x0000000F
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_1_SHIFT 0
-/* second opsel, input selection */
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_2_MASK 0x000000F0
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_2_SHIFT 4
-/* third opsel, input selction */
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_3_MASK 0x00000F00
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_3_SHIFT 8
-/* fourth opsel, input selction */
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_4_MASK 0x0000F000
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_4_SHIFT 12
-
-/**** rx_gcp_table_alu_val register ****/
-/* value for alu input */
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_VAL_VAL_MASK 0x000001FF
-#define EC_RFW_V3_RX_GCP_TABLE_ALU_VAL_VAL_SHIFT 0
-
-/**** rx_gcp_alu_p1 register ****/
-/* Location in bytes of field 1 in the parser result vector */
-#define EC_RFW_V3_RX_GCP_ALU_P1_OFFSET_MASK 0x000003FF
-#define EC_RFW_V3_RX_GCP_ALU_P1_OFFSET_SHIFT 0
-/* Right shift for field 1 in the parser result vector */
-#define EC_RFW_V3_RX_GCP_ALU_P1_SHIFT_MASK 0x000F0000
-#define EC_RFW_V3_RX_GCP_ALU_P1_SHIFT_SHIFT 16
-
-/**** rx_gcp_alu_p2 register ****/
-/* Location in bytes of field 2 in the parser result vector */
-#define EC_RFW_V3_RX_GCP_ALU_P2_OFFSET_MASK 0x000003FF
-#define EC_RFW_V3_RX_GCP_ALU_P2_OFFSET_SHIFT 0
-/* Right shift for field 2 in the parser result vector */
-#define EC_RFW_V3_RX_GCP_ALU_P2_SHIFT_MASK 0x000F0000
-#define EC_RFW_V3_RX_GCP_ALU_P2_SHIFT_SHIFT 16
-
-/**** hs_ctrl_table_addr register ****/
-/* Header split control table address */
-#define EC_RFW_V3_HS_CTRL_TABLE_ADDR_VAL_MASK 0x000000FF
-#define EC_RFW_V3_HS_CTRL_TABLE_ADDR_VAL_SHIFT 0
-
-/**** hs_ctrl_table register ****/
-/* Header split length select */
-#define EC_RFW_V3_HS_CTRL_TABLE_SEL_MASK 0x00000003
-#define EC_RFW_V3_HS_CTRL_TABLE_SEL_SHIFT 0
-/* enable header split */
-#define EC_RFW_V3_HS_CTRL_TABLE_ENABLE   (1 << 2)
-
-/**** hs_ctrl_table_alu_opcode register ****/
-/* first opcode
-e.g. (A op1 B) op3 (C op2 D) */
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_1_MASK 0x0000003F
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_1_SHIFT 0
-/* second opcode
-e.g. (A op1 B) op3 (C op2 D) */
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_2_MASK 0x00000FC0
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_2_SHIFT 6
-/* third opcode
-e.g. (A op1 B) op3 (C op2 D) */
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_3_MASK 0x0003F000
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_3_SHIFT 12
-
-/**** hs_ctrl_table_alu_opsel register ****/
-/* frst opsel, input selection */
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_1_MASK 0x0000000F
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_1_SHIFT 0
-/* second opsel, input selection */
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_2_MASK 0x000000F0
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_2_SHIFT 4
-/* third opsel, input selction */
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_3_MASK 0x00000F00
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_3_SHIFT 8
-/* fourth opsel, input selction */
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_4_MASK 0x0000F000
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_4_SHIFT 12
-
-/**** hs_ctrl_table_alu_val register ****/
-/* value for alu input */
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_VAL_VAL_MASK 0x0000FFFF
-#define EC_RFW_V3_HS_CTRL_TABLE_ALU_VAL_VAL_SHIFT 0
-
-/**** hs_ctrl_cfg register ****/
-/* Header split enable static selction0 – legacy1 – header split ... */
-#define EC_RFW_V3_HS_CTRL_CFG_ENABLE_SEL (1 << 0)
-/* Header split length static selction0 – legacy1 – header split ... */
-#define EC_RFW_V3_HS_CTRL_CFG_LENGTH_SEL (1 << 1)
-
-/**** hs_ctrl_alu_p1 register ****/
-/* Location in bytes of field 1 in the parser result vector */
-#define EC_RFW_V3_HS_CTRL_ALU_P1_OFFSET_MASK 0x000003FF
-#define EC_RFW_V3_HS_CTRL_ALU_P1_OFFSET_SHIFT 0
-/* Right shift for field 1 in the parser result vector */
-#define EC_RFW_V3_HS_CTRL_ALU_P1_SHIFT_MASK 0x000F0000
-#define EC_RFW_V3_HS_CTRL_ALU_P1_SHIFT_SHIFT 16
-
-/**** hs_ctrl_alu_p2 register ****/
-/* Location in bytes of field 2 in the parser result vector */
-#define EC_RFW_V3_HS_CTRL_ALU_P2_OFFSET_MASK 0x000003FF
-#define EC_RFW_V3_HS_CTRL_ALU_P2_OFFSET_SHIFT 0
-/* Right shift for field 2 in the parser result vector */
-#define EC_RFW_V3_HS_CTRL_ALU_P2_SHIFT_MASK 0x000F0000
-#define EC_RFW_V3_HS_CTRL_ALU_P2_SHIFT_SHIFT 16
-
-/**** tx_config register ****/
-/* [0] pre increment word swap[1] pre increment byte swap[2] pre ... */
-#define EC_CRYPTO_TX_CONFIG_TWEAK_ENDIANITY_SWAP_MASK 0x0000003F
-#define EC_CRYPTO_TX_CONFIG_TWEAK_ENDIANITY_SWAP_SHIFT 0
-/* [0] pre encryption word swap[1] pre encryption byte swap[2] p ... */
-#define EC_CRYPTO_TX_CONFIG_DATA_ENDIANITY_SWAP_MASK 0x00003F00
-#define EC_CRYPTO_TX_CONFIG_DATA_ENDIANITY_SWAP_SHIFT 8
-/* direction flip, used in order to use same TID entry for both TX & RX traffic */
-#define EC_CRYPTO_TX_CONFIG_CRYPTO_DIR_FLIP (1 << 14)
-/* Enabling pipe line optimization */
-#define EC_CRYPTO_TX_CONFIG_PIPE_CALC_EN (1 << 16)
-/* enable performance counters */
-#define EC_CRYPTO_TX_CONFIG_PERF_CNT_EN  (1 << 17)
-/* [0] pre aes word swap[1] pre aes byte swap[2] pre aes bit swa ... */
-#define EC_CRYPTO_TX_CONFIG_AES_ENDIANITY_SWAP_MASK 0x03F00000
-#define EC_CRYPTO_TX_CONFIG_AES_ENDIANITY_SWAP_SHIFT 20
-/* [0] pre aes key word swap[1] pre aes key byte swap[2] pre aes ... */
-#define EC_CRYPTO_TX_CONFIG_AES_KEY_ENDIANITY_SWAP_MASK 0xFC000000
-#define EC_CRYPTO_TX_CONFIG_AES_KEY_ENDIANITY_SWAP_SHIFT 26
-
-/**** rx_config register ****/
-/* [0] pre increment word swap[1] pre increment byte swap[2] pre ... */
-#define EC_CRYPTO_RX_CONFIG_TWEAK_ENDIANITY_SWAP_MASK 0x0000003F
-#define EC_CRYPTO_RX_CONFIG_TWEAK_ENDIANITY_SWAP_SHIFT 0
-/* [0] pre encryption word swap[1] pre encryption byte swap[2] p ... */
-#define EC_CRYPTO_RX_CONFIG_DATA_ENDIANITY_SWAP_MASK 0x00003F00
-#define EC_CRYPTO_RX_CONFIG_DATA_ENDIANITY_SWAP_SHIFT 8
-/* direction flip, used in order to use same TID entry for both TX & RX traffic */
-#define EC_CRYPTO_RX_CONFIG_CRYPTO_DIR_FLIP (1 << 14)
-/* Enabling pipe line optimization */
-#define EC_CRYPTO_RX_CONFIG_PIPE_CALC_EN (1 << 16)
-/* enable performance counters */
-#define EC_CRYPTO_RX_CONFIG_PERF_CNT_EN  (1 << 17)
-/* [0] pre aes word swap[1] pre aes byte swap[2] pre aes bit swa ... */
-#define EC_CRYPTO_RX_CONFIG_AES_ENDIANITY_SWAP_MASK 0x03F00000
-#define EC_CRYPTO_RX_CONFIG_AES_ENDIANITY_SWAP_SHIFT 20
-/* [0] data aes key word swap[1] data aes key byte swap[2] data  ... */
-#define EC_CRYPTO_RX_CONFIG_AES_KEY_ENDIANITY_SWAP_MASK 0xFC000000
-#define EC_CRYPTO_RX_CONFIG_AES_KEY_ENDIANITY_SWAP_SHIFT 26
-
-/**** tx_override register ****/
-/* all transactions are encrypted */
-#define EC_CRYPTO_TX_OVERRIDE_ENCRYPT_ONLY (1 << 0)
-/* all transactions are decrypted */
-#define EC_CRYPTO_TX_OVERRIDE_DECRYPT_ONLY (1 << 1)
-/* all pkts use IV */
-#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_DRIVE_IV (1 << 2)
-/* no pkt uses IV */
-#define EC_CRYPTO_TX_OVERRIDE_NEVER_DRIVE_IV (1 << 3)
-/* all pkts perform authentication calculation */
-#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_PERFORM_SIGN (1 << 4)
-/* no pkt performs authentication calculation */
-#define EC_CRYPTO_TX_OVERRIDE_NEVER_PERFORM_SIGN (1 << 5)
-/* all pkts perform encryption calculation */
-#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_PERFORM_ENC (1 << 6)
-/* no pkt performs encryption calculation */
-#define EC_CRYPTO_TX_OVERRIDE_NEVER_PERFORM_ENC (1 << 7)
-/* Enforce pkt trimming
-bit[0] relates to metadata_pkt_trim
-bit[1] relates to trailer_pkt_trime
-bit[2] relates to sign_trim
-bit[3] relates to aes_padding_trim */
-#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_MASK 0x00000F00
-#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_SHIFT 8
-/* Enforce no pkt trimming
-bit[0] relates to metadata_pkt_trim
-bit[1] relates to trailer_pkt_trime
-bit[2] relates to sign_trim
-bit[3] relates to aes_padding_trim */
-#define EC_CRYPTO_TX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_MASK 0x0000F000
-#define EC_CRYPTO_TX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_SHIFT 12
-/* chicken bit to disable metadata handling optimization */
-#define EC_CRYPTO_TX_OVERRIDE_EXPLICIT_METADATA_STAGE (1 << 16)
-
-/**** rx_override register ****/
-/* all transactions are encrypted */
-#define EC_CRYPTO_RX_OVERRIDE_ENCRYPT_ONLY (1 << 0)
-/* all transactions are decrypted */
-#define EC_CRYPTO_RX_OVERRIDE_DECRYPT_ONLY (1 << 1)
-/* all pkts use IV */
-#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_DRIVE_IV (1 << 2)
-/* no pkt uses IV */
-#define EC_CRYPTO_RX_OVERRIDE_NEVER_DRIVE_IV (1 << 3)
-/* all pkts perform authentication calculation */
-#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_PERFORM_SIGN (1 << 4)
-/* no pkt performs authentication calculation */
-#define EC_CRYPTO_RX_OVERRIDE_NEVER_PERFORM_SIGN (1 << 5)
-/* all pkts perform encryption calculation */
-#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_PERFORM_ENC (1 << 6)
-/* no pkt performs encryption calculation */
-#define EC_CRYPTO_RX_OVERRIDE_NEVER_PERFORM_ENC (1 << 7)
-/* Enforce pkt trimming
-bit[0] relates to metadata_pkt_trim
-bit[1] relates to trailer_pkt_trime
-bit[2] relates to sign_trim
-bit[3] relates to aes_padding_trim */
-#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_MASK 0x00000F00
-#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_SHIFT 8
-/* Enforce no pkt trimming
-bit[0] relates to metadata_pkt_trim
-bit[1] relates to trailer_pkt_trime
-bit[2] relates to sign_trim
-bit[3] relates to aes_padding_trim */
-#define EC_CRYPTO_RX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_MASK 0x0000F000
-#define EC_CRYPTO_RX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_SHIFT 12
-/* bit enable for writing to rx_cmpl metadata info */
-#define EC_CRYPTO_RX_OVERRIDE_META_DATA_WRITE_EN_MASK 0x00070000
-#define EC_CRYPTO_RX_OVERRIDE_META_DATA_WRITE_EN_SHIFT 16
-/* chicken bit to disable metadata handling optimization */
-#define EC_CRYPTO_RX_OVERRIDE_EXPLICIT_METADATA_STAGE (1 << 19)
-/* crypto metadata offset in the rx cmpl_desc */
-#define EC_CRYPTO_RX_OVERRIDE_META_DATA_BASE_MASK 0x07F00000
-#define EC_CRYPTO_RX_OVERRIDE_META_DATA_BASE_SHIFT 20
-
-/**** tx_enc_iv_construction register ****/
-/* for each IV byte, select between src1 & src2. Src1 & src2 ... */
-#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MUX_SEL_MASK 0x0000FFFF
-#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MUX_SEL_SHIFT 0
-/* configure meaning of mux_sel=1'b0 (2'b00 – zeros, 2'b01 f...  */
-#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_0_MASK 0x00030000
-#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_0_SHIFT 16
-/* configure meaning of mux_sel=1'b1 (2'b00 – zeros, 2'b01 ...  */
-#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_1_MASK 0x000C0000
-#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_1_SHIFT 18
-/* Per-byte mux select taken from Crypto table (otherwise ...  */
-#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_SEL_FROM_TABLE (1 << 20)
-/* [0] word swap en
-[1] byte swap en
-[2] bit swap en */
-#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_MASK 0x00E00000
-#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_SHIFT 21
-
-/**** rx_enc_iv_construction register ****/
-/* for each IV byte, select between src1 & src2. Src1 & src2 ...  */
-#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MUX_SEL_MASK 0x0000FFFF
-#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MUX_SEL_SHIFT 0
-/* configure meaning of mux_sel=1'b0 (2'b00 – zeros, 2'b01 – ...  */
-#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_0_MASK 0x00030000
-#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_0_SHIFT 16
-/* configure meaning of mux_sel=1'b1 (2'b00 – zeros, 2'b01 – ...  */
-#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_1_MASK 0x000C0000
-#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_1_SHIFT 18
-/* Per-byte mux select taken from Crypto table (otherwise from ...  */
-#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_SEL_FROM_TABLE (1 << 20)
-/* [0] word swap en
-[1] byte swap en
-[2] bit swap en */
-#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_MASK 0x00E00000
-#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_SHIFT 21
-
-/**** rx_enc_iv_map register ****/
-/* [0] word swap en
-[1] byte swap en
-[2] bit swap en */
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_OFFSET_MASK 0x0000001F
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_OFFSET_SHIFT 0
-/* number of valid bytes in word, as generated by field extract ... */
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_LENGTH_MASK 0x000000E0
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_LENGTH_SHIFT 5
-/* [0] word swap en
-[1] byte swap en
-[2] bit swap en */
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_OFFSET_MASK 0x00001F00
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_OFFSET_SHIFT 8
-/* number of valid bytes in word, as generated by field extract ... */
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_LENGTH_MASK 0x0000E000
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_LENGTH_SHIFT 13
-/* [0] word swap en
-[1] byte swap en
-[2] bit swap en */
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_OFFSET_MASK 0x001F0000
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_OFFSET_SHIFT 16
-/* number of valid bytes in word, as generated by field extract ... */
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_LENGTH_MASK 0x00E00000
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_LENGTH_SHIFT 21
-/* [0] word swap en
-[1] byte swap en
-[2] bit swap en */
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_OFFSET_MASK 0x1F000000
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_OFFSET_SHIFT 24
-/* number of valid bytes in word, as generated by field extract ... */
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_LENGTH_MASK 0xE0000000
-#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_LENGTH_SHIFT 29
-
-/**** tx_pkt_trim_len register ****/
-/* metadata shift-reg length */
-#define EC_CRYPTO_TX_PKT_TRIM_LEN_META_MASK 0x00000007
-#define EC_CRYPTO_TX_PKT_TRIM_LEN_META_SHIFT 0
-/* pkt trailer shift-reg length */
-#define EC_CRYPTO_TX_PKT_TRIM_LEN_TRAIL_MASK 0x000000F0
-#define EC_CRYPTO_TX_PKT_TRIM_LEN_TRAIL_SHIFT 4
-/* sign shift-reg length */
-#define EC_CRYPTO_TX_PKT_TRIM_LEN_SIGN_MASK 0x00000300
-#define EC_CRYPTO_TX_PKT_TRIM_LEN_SIGN_SHIFT 8
-/* crypto padding shift-reg length */
-#define EC_CRYPTO_TX_PKT_TRIM_LEN_CRYPTO_PADDING_MASK 0x00003000
-#define EC_CRYPTO_TX_PKT_TRIM_LEN_CRYPTO_PADDING_SHIFT 12
-/* hardware chooses shift-registers configurations automatically – no need for sw configuration */
-#define EC_CRYPTO_TX_PKT_TRIM_LEN_AUTO_MODE (1 << 16)
-
-/**** rx_pkt_trim_len register ****/
-/* metadata shift-reg length */
-#define EC_CRYPTO_RX_PKT_TRIM_LEN_META_MASK 0x00000007
-#define EC_CRYPTO_RX_PKT_TRIM_LEN_META_SHIFT 0
-/* pkt trailer shift-reg length */
-#define EC_CRYPTO_RX_PKT_TRIM_LEN_TRAIL_MASK 0x000000F0
-#define EC_CRYPTO_RX_PKT_TRIM_LEN_TRAIL_SHIFT 4
-/* sign shift-reg length */
-#define EC_CRYPTO_RX_PKT_TRIM_LEN_SIGN_MASK 0x00000300
-#define EC_CRYPTO_RX_PKT_TRIM_LEN_SIGN_SHIFT 8
-/* crypto padding shift-reg length */
-#define EC_CRYPTO_RX_PKT_TRIM_LEN_CRYPTO_PADDING_MASK 0x00003000
-#define EC_CRYPTO_RX_PKT_TRIM_LEN_CRYPTO_PADDING_SHIFT 12
-/* hardware chooses shift-registers configurations automatically – no need for sw configuration */
-#define EC_CRYPTO_RX_PKT_TRIM_LEN_AUTO_MODE (1 << 16)
-
-/**** total_tx_secured_pkts_cipher_mode_cmpr register ****/
-
-#define EC_CRYPTO_PERF_CNTR_TOTAL_TX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_MASK 0x0000000F
-#define EC_CRYPTO_PERF_CNTR_TOTAL_TX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_SHIFT 0
-
-/**** total_rx_secured_pkts_cipher_mode_cmpr register ****/
-
-#define EC_CRYPTO_PERF_CNTR_TOTAL_RX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_MASK 0x0000000F
-#define EC_CRYPTO_PERF_CNTR_TOTAL_RX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_SHIFT 0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_EC_REG_H */
-
-/** @} end of ... group */
-
-
diff --git a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_kr.c b/sys/contrib/alpine-hal/eth/eth/al_hal_eth_kr.c
deleted file mode 100644
index 14ef797eb00c..000000000000
--- a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_kr.c
+++ /dev/null
@@ -1,1030 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-/**
- *  Ethernet
- *  @{
- * @file   al_hal_eth_kr.c
- *
- * @brief  KR HAL driver for main functions (auto-neg, Link Training)
- *
- */
-
-#include "al_hal_eth_kr.h"
-#include "al_hal_eth_mac_regs.h"
-#include "al_hal_an_lt_wrapper_regs.h"
-
-enum al_eth_lt_unit_rev {
-	AL_ETH_LT_UNIT_REV_1 = 0,
-	AL_ETH_LT_UNIT_REV_2,
-
-	AL_ETH_LT_UNIT_REV_MAX
-};
-
-enum al_eth_an_lt_regs_ids {
-	AL_ETH_KR_AN_CONTROL = 0,
-	AL_ETH_KR_AN_STATUS,
-	AL_ETH_KR_AN_ADV0,
-	AL_ETH_KR_AN_ADV1,
-	AL_ETH_KR_AN_ADV2,
-	AL_ETH_KR_AN_REM_ADV0,
-	AL_ETH_KR_AN_REM_ADV1,
-	AL_ETH_KR_AN_REM_ADV2,
-	AL_ETH_KR_PMD_CONTROL,
-	AL_ETH_KR_PMD_STATUS,
-	AL_ETH_KR_PMD_LP_COEF_UP,
-	AL_ETH_KR_PMD_LP_STATUS_REPORT,
-	AL_ETH_KR_PMD_LD_COEF_UP,
-	AL_ETH_KR_PMD_LD_STATUS_REPORT,
-	AL_ETH_KR_AN_XNP_ADV0,
-	AL_ETH_KR_AN_XNP_ADV1,
-	AL_ETH_KR_AN_XNP_ADV2,
-	AL_ETH_KR_AN_REM_XNP_ADV0,
-	AL_ETH_KR_AN_REM_XNP_ADV1,
-	AL_ETH_KR_AN_REM_XNP_ADV2,
-};
-
-static uint32_t al_eth_an_lt_regs_addr[][AL_ETH_LT_UNIT_REV_MAX] = {
-	[AL_ETH_KR_AN_CONTROL]			=	{0  ,	0x0},
-	[AL_ETH_KR_AN_STATUS]			=	{1  ,	0x4},
-	[AL_ETH_KR_AN_ADV0]			=	{16 ,	0x8},
-	[AL_ETH_KR_AN_ADV1]			=	{17 ,	0xc},
-	[AL_ETH_KR_AN_ADV2]			=	{18 ,	0x10},
-	[AL_ETH_KR_AN_REM_ADV0]			=	{19 ,	0x14},
-	[AL_ETH_KR_AN_REM_ADV1]			=	{20 ,	0x18},
-	[AL_ETH_KR_AN_REM_ADV2]			=	{21 ,	0x1c},
-	[AL_ETH_KR_PMD_CONTROL]			=	{150,	0x400},
-	[AL_ETH_KR_PMD_STATUS]			=	{151,	0x404},
-	[AL_ETH_KR_PMD_LP_COEF_UP]		=	{152,	0x408},
-	[AL_ETH_KR_PMD_LP_STATUS_REPORT]	=	{153,	0x40c},
-	[AL_ETH_KR_PMD_LD_COEF_UP]		=	{154,	0x410},
-	[AL_ETH_KR_PMD_LD_STATUS_REPORT]	=	{155,	0x414},
-	[AL_ETH_KR_AN_XNP_ADV0]			=	{22 ,   0x24},
-	[AL_ETH_KR_AN_XNP_ADV1]			=	{23 ,   0x28},
-	[AL_ETH_KR_AN_XNP_ADV2]			=	{24 ,   0x2c},
-	[AL_ETH_KR_AN_REM_XNP_ADV0]		=	{25 ,   0x30},
-	[AL_ETH_KR_AN_REM_XNP_ADV1]		=	{26 ,   0x34},
-	[AL_ETH_KR_AN_REM_XNP_ADV2]		=	{27 ,   0x38},
-};
-
-
-/*
- * AN(Auto Negotiation) registers
- * (read / write indirect with al_eth_an_reg_read/write)
- */
-#define AL_ETH_KR_AN_CONTROL_RESTART				AL_BIT(9)
-#define AL_ETH_KR_AN_CONTROL_ENABLE				AL_BIT(12)
-#define AL_ETH_KR_AN_CONTROL_NP_ENABLE				AL_BIT(13)
-
-#define AL_ETH_KR_AN_STATUS_COMPLETED				AL_BIT(5)
-#define AL_ETH_KR_AN_STATUS_BASE_PAGE_RECEIVED			AL_BIT(6)
-#define AL_ETH_KR_AN_STATUS_CHECK_MASK				0xFF0A
-#define AL_ETH_KR_AN_STATUS_CHECK_NO_ERROR			0x0008
-
-/* AN advertising registers parsing */
-/* register 1 */
-#define AL_ETH_KR_AN_ADV1_SEL_FIELD_MASK			0x001f
-#define AL_ETH_KR_AN_ADV1_SEL_FIELD_SHIFT			0
-#define AL_ETH_KR_AN_ADV1_ECHOED_NONCE_MASK			0x03e0
-#define AL_ETH_KR_AN_ADV1_ECHOED_NONCE_SHIFT			5
-#define AL_ETH_KR_AN_ADV1_CAPABILITY_MASK			0x1c00
-#define AL_ETH_KR_AN_ADV1_CAPABILITY_SHIFT			10
-#define AL_ETH_KR_AN_ADV1_REM_FAULT_MASK			0x2000
-#define AL_ETH_KR_AN_ADV1_REM_FAULT_SHIFT			13
-#define AL_ETH_KR_AN_ADV1_ACK_MASK				0x4000
-#define AL_ETH_KR_AN_ADV1_ACK_SHIFT				14
-#define AL_ETH_KR_AN_ADV1_NEXT_PAGE_MASK			0x8000
-#define AL_ETH_KR_AN_ADV1_NEXT_PAGE_SHIFT			15
-/* register 2 */
-#define AL_ETH_KR_AN_ADV2_TX_NONCE_MASK				0x001f
-#define AL_ETH_KR_AN_ADV2_TX_NONCE_SHIFT			0
-#define AL_ETH_KR_AN_ADV2_TECH_MASK				0xffe0
-#define AL_ETH_KR_AN_ADV2_TECH_SHIFT				5
-/* register 3 */
-/* TECH field in the third register is extended to the field in the second
- * register and it is currently reserved (should be always 0) */
-#define AL_ETH_KR_AN_ADV3_TECH_MASK				0x1fff
-#define AL_ETH_KR_AN_ADV3_TECH_SHIFT				0
-#define AL_ETH_KR_AN_ADV3_FEC_MASK				0xc000
-#define AL_ETH_KR_AN_ADV3_FEC_SHIFT				14
-
-/* Next Page Fields */
-/* register 1 */
-#define AL_ETH_KR_AN_NP_ADV1_DATA1_MASK				0x07ff
-#define AL_ETH_KR_AN_NP_ADV1_DATA1_SHIFT			0
-#define AL_ETH_KR_AN_NP_ADV1_TOGGLE_MASK			0x0800
-#define AL_ETH_KR_AN_NP_ADV1_TOGGLE_SHIFT			11
-#define AL_ETH_KR_AN_NP_ADV1_ACK2_MASK				0x1000
-#define AL_ETH_KR_AN_NP_ADV1_ACK2_SHIFT				12
-#define AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_MASK			0x2000
-#define AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_SHIFT			13
-#define AL_ETH_KR_AN_NP_ADV1_NP_MASK				0x8000
-#define AL_ETH_KR_AN_NP_ADV1_NP_SHIFT				15
-
-/*
- * LT(Link Training) registers
- * (read / write indirect with al_eth_pma_reg_read/write)
- */
-#define AL_ETH_KR_PMD_CONTROL_RESTART				0
-#define AL_ETH_KR_PMD_CONTROL_ENABLE				1
-
-#define AL_ETH_KR_PMD_STATUS_RECEIVER_COMPLETED_SHIFT		0
-#define AL_ETH_KR_PMD_STATUS_RECEIVER_FRAME_LOCK_SHIFT		1
-#define AL_ETH_KR_PMD_STATUS_RECEIVER_START_UP_PROTO_PROG_SHIFT	2
-#define AL_ETH_KR_PMD_STATUS_FAILURE_SHIFT			3
-
-#define AL_ETH_KR_PMD_LP_COEF_UP_MINUS_MASK			0x0003
-#define AL_ETH_KR_PMD_LP_COEF_UP_MINUS_SHIFT			0
-#define AL_ETH_KR_PMD_LP_COEF_UP_ZERO_MASK			0x000C
-#define AL_ETH_KR_PMD_LP_COEF_UP_ZERO_SHIFT			2
-#define AL_ETH_KR_PMD_LP_COEF_UP_PLUS_MASK			0x0030
-#define AL_ETH_KR_PMD_LP_COEF_UP_PLUS_SHIFT			4
-#define AL_ETH_KR_PMD_LP_COEF_UP_INITIALIZE_SHIFT		12
-#define AL_ETH_KR_PMD_LP_COEF_UP_PRESET_SHIFT			13
-
-#define AL_ETH_KR_PMD_LP_STATUS_REPORT_MINUS_MASK		0x0003
-#define AL_ETH_KR_PMD_LP_STATUS_REPORT_MINUS_SHIFT		0
-#define AL_ETH_KR_PMD_LP_STATUS_REPORT_ZERO_MASK		0x000C
-#define AL_ETH_KR_PMD_LP_STATUS_REPORT_ZERO_SHIFT		2
-#define AL_ETH_KR_PMD_LP_STATUS_REPORT_PLUS_MASK		0x0030
-#define AL_ETH_KR_PMD_LP_STATUS_REPORT_PLUS_SHIFT		4
-#define AL_ETH_KR_PMD_LP_STATUS_RECEIVER_READY_SHIFT		15
-
-#define AL_ETH_KR_PMD_LD_COEF_UP_MINUS_MASK			0x0003
-#define AL_ETH_KR_PMD_LD_COEF_UP_MINUS_SHIFT			0
-#define AL_ETH_KR_PMD_LD_COEF_UP_ZERO_MASK			0x000C
-#define AL_ETH_KR_PMD_LD_COEF_UP_ZERO_SHIFT			2
-#define AL_ETH_KR_PMD_LD_COEF_UP_PLUS_MASK			0x0030
-#define AL_ETH_KR_PMD_LD_COEF_UP_PLUS_SHIFT			4
-#define AL_ETH_KR_PMD_LD_COEF_UP_INITIALIZE_SHIFT		12
-#define AL_ETH_KR_PMD_LD_COEF_UP_PRESET_SHIFT			13
-
-#define AL_ETH_KR_PMD_LD_STATUS_REPORT_MINUS_MASK		0x0003
-#define AL_ETH_KR_PMD_LD_STATUS_REPORT_MINUS_SHIFT		0
-#define AL_ETH_KR_PMD_LD_STATUS_REPORT_ZERO_MASK		0x000C
-#define AL_ETH_KR_PMD_LD_STATUS_REPORT_ZERO_SHIFT		2
-#define AL_ETH_KR_PMD_LD_STATUS_REPORT_PLUS_MASK		0x0030
-#define AL_ETH_KR_PMD_LD_STATUS_REPORT_PLUS_SHIFT		4
-#define AL_ETH_KR_PMD_LD_STATUS_REPORT_RECEIVER_READY_SHIFT	15
-
-
-enum al_eth_an_lt_regs {
-	AL_ETH_AN_REGS,
-	AL_ETH_LT_REGS,
-};
-
-static uint16_t al_eth_an_lt_reg_read(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_regs_ids reg_id,
-			enum al_eth_an_lt_regs an_lt,
-			enum al_eth_an_lt_lane lane)
-{
-	uint32_t val;
-	uint16_t reg_addr;
-
-	if (adapter->rev_id < AL_ETH_REV_ID_3) {
-		al_assert(lane == AL_ETH_AN__LT_LANE_0);
-
-		reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_1];
-		if (an_lt == AL_ETH_AN_REGS) {
-			al_reg_write32(&adapter->mac_regs_base->kr.an_addr, reg_addr);
-			val = al_reg_read32(&adapter->mac_regs_base->kr.an_data);
-		} else {
-			al_reg_write32(&adapter->mac_regs_base->kr.pma_addr, reg_addr);
-			val = al_reg_read32(&adapter->mac_regs_base->kr.pma_data);
-		}
-	} else {
-		struct al_an_lt_wrapper_regs *regs = NULL;
-
-		reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_2];
-
-		switch (lane) {
-		case AL_ETH_AN__LT_LANE_0:
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_data,
-				       reg_addr);
-
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
-			val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_0_data);
-			break;
-		case AL_ETH_AN__LT_LANE_1:
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_data,
-				       reg_addr);
-
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
-			val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_1_data);
-			break;
-		case AL_ETH_AN__LT_LANE_2:
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_data,
-				       reg_addr);
-
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
-			val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_2_data);
-			break;
-		case AL_ETH_AN__LT_LANE_3:
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_data,
-				       reg_addr);
-
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
-			val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_3_data);
-			break;
-		default:
-			al_err("%s: Unknown Lane %d\n", __func__, lane);
-			return 0;
-		}
-	}
-
-
-	al_dbg("[%s]: %s - (%s) lane %d, reg %d, val 0x%x", adapter->name, __func__,
-	       (an_lt == AL_ETH_AN_REGS) ? "AN" : "LT", lane, reg_addr, val);
-
-	return (uint16_t)val;
-}
-
-static void al_eth_an_lt_reg_write(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_regs_ids reg_id,
-			enum al_eth_an_lt_regs an_lt,
-			enum al_eth_an_lt_lane lane,
-			uint16_t val)
-{
-	uint16_t reg_addr;
-
-	if (adapter->rev_id < AL_ETH_REV_ID_3) {
-		reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_1];
-		if (an_lt == AL_ETH_AN_REGS) {
-			al_reg_write32(&adapter->mac_regs_base->kr.an_addr, reg_addr);
-			al_reg_write32(&adapter->mac_regs_base->kr.an_data, val);
-		} else {
-			al_reg_write32(&adapter->mac_regs_base->kr.pma_addr, reg_addr);
-			al_reg_write32(&adapter->mac_regs_base->kr.pma_data, val);
-		}
-	} else {
-		struct al_an_lt_wrapper_regs *regs = NULL;
-
-		reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_2];
-
-		switch (lane) {
-		case AL_ETH_AN__LT_LANE_0:
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_data,
-				       reg_addr);
-
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_data,
-				       val);
-			break;
-		case AL_ETH_AN__LT_LANE_1:
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_data,
-				       reg_addr);
-
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_data,
-				       val);
-			break;
-		case AL_ETH_AN__LT_LANE_2:
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_data,
-				       reg_addr);
-
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_data,
-				       val);
-			break;
-		case AL_ETH_AN__LT_LANE_3:
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_data,
-				       reg_addr);
-
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
-				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_data,
-				       val);
-			break;
-		default:
-			al_err("%s: Unknown Lane %d\n", __func__, lane);
-			return;
-		}
-	}
-
-
-	al_dbg("[%s]: %s - (%s) lane %d, reg %d, val 0x%x", adapter->name, __func__,
-	       (an_lt == AL_ETH_AN_REGS) ? "AN" : "LT", lane, reg_addr, val);
-}
-
-static void al_eth_an_lt_unit_config(struct al_hal_eth_adapter *adapter)
-{
-	struct al_an_lt_wrapper_regs *regs = NULL;
-	uint32_t cfg_lane_0 = (AN_LT_WRAPPER_GEN_CFG_BYPASS_RX | AN_LT_WRAPPER_GEN_CFG_BYPASS_TX);
-	uint32_t cfg_lane_1 = (AN_LT_WRAPPER_GEN_CFG_BYPASS_RX | AN_LT_WRAPPER_GEN_CFG_BYPASS_TX);
-	uint32_t cfg_lane_2 = (AN_LT_WRAPPER_GEN_CFG_BYPASS_RX | AN_LT_WRAPPER_GEN_CFG_BYPASS_TX);
-	uint32_t cfg_lane_3 = (AN_LT_WRAPPER_GEN_CFG_BYPASS_RX | AN_LT_WRAPPER_GEN_CFG_BYPASS_TX);
-
-	switch (adapter->mac_mode) {
-	case AL_ETH_MAC_MODE_10GbE_Serial:
-		cfg_lane_0 = 0;
-		AL_REG_FIELD_SET(cfg_lane_0,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_20_BIT);
-		AL_REG_FIELD_SET(cfg_lane_0,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_20_BIT);
-
-		adapter->curr_lt_unit = AL_ETH_AN_LT_UNIT_20_BIT;
-
-		break;
-	case AL_ETH_MAC_MODE_KR_LL_25G:
-		cfg_lane_0 = 0;
-		AL_REG_FIELD_SET(cfg_lane_0,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_32_BIT);
-		AL_REG_FIELD_SET(cfg_lane_0,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_32_BIT);
-
-		adapter->curr_lt_unit = AL_ETH_AN_LT_UNIT_32_BIT;
-
-		break;
-	case AL_ETH_MAC_MODE_XLG_LL_40G:
-		cfg_lane_0 = 0;
-		AL_REG_FIELD_SET(cfg_lane_0,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_16_BIT);
-		AL_REG_FIELD_SET(cfg_lane_0,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_16_BIT);
-
-		cfg_lane_1 = 0;
-		AL_REG_FIELD_SET(cfg_lane_1,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_16_BIT);
-		AL_REG_FIELD_SET(cfg_lane_1,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_16_BIT);
-
-		cfg_lane_2 = 0;
-		AL_REG_FIELD_SET(cfg_lane_2,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_16_BIT);
-		AL_REG_FIELD_SET(cfg_lane_2,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_16_BIT);
-
-		cfg_lane_3 = 0;
-		AL_REG_FIELD_SET(cfg_lane_3,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_16_BIT);
-		AL_REG_FIELD_SET(cfg_lane_3,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_16_BIT);
-
-		adapter->curr_lt_unit = AL_ETH_AN_LT_UNIT_16_BIT;
-
-		break;
-	case AL_ETH_MAC_MODE_XLG_LL_50G:
-		cfg_lane_0 = 0;
-		AL_REG_FIELD_SET(cfg_lane_0,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_32_BIT);
-		AL_REG_FIELD_SET(cfg_lane_0,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_32_BIT);
-
-		cfg_lane_1 = 0;
-		AL_REG_FIELD_SET(cfg_lane_1,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_32_BIT);
-		AL_REG_FIELD_SET(cfg_lane_1,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
-				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
-				 AL_ETH_AN_LT_UNIT_32_BIT);
-
-		adapter->curr_lt_unit = AL_ETH_AN_LT_UNIT_32_BIT;
-
-		break;
-	default:
-		al_err("%s: Unknown mac_mode\n", __func__);
-		return;
-	}
-
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
-		       (uintptr_t)&regs->gen.cfg);
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_data,
-		       cfg_lane_0);
-
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
-		       (uintptr_t)&regs->gen.cfg);
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_data,
-		       cfg_lane_1);
-
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
-		       (uintptr_t)&regs->gen.cfg);
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_data,
-		       cfg_lane_2);
-
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
-		       (uintptr_t)&regs->gen.cfg);
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_data,
-		       cfg_lane_3);
-}
-
-void al_eth_lp_coeff_up_get(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_lane lane,
-			struct al_eth_kr_coef_up_data *lpcoeff)
-{
-	uint16_t reg;
-
-	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_LP_COEF_UP, AL_ETH_LT_REGS, lane);
-
-	lpcoeff->preset =
-		(AL_REG_BIT_GET(
-			reg, AL_ETH_KR_PMD_LP_COEF_UP_PRESET_SHIFT) != 0);
-
-	lpcoeff->initialize =
-		(AL_REG_BIT_GET(
-			reg, AL_ETH_KR_PMD_LP_COEF_UP_INITIALIZE_SHIFT) != 0);
-
-	lpcoeff->c_minus = AL_REG_FIELD_GET(reg,
-					AL_ETH_KR_PMD_LP_COEF_UP_MINUS_MASK,
-					AL_ETH_KR_PMD_LP_COEF_UP_MINUS_SHIFT);
-
-	lpcoeff->c_zero = AL_REG_FIELD_GET(reg,
-					AL_ETH_KR_PMD_LP_COEF_UP_ZERO_MASK,
-					AL_ETH_KR_PMD_LP_COEF_UP_ZERO_SHIFT);
-
-	lpcoeff->c_plus = AL_REG_FIELD_GET(reg,
-					AL_ETH_KR_PMD_LP_COEF_UP_PLUS_MASK,
-					AL_ETH_KR_PMD_LP_COEF_UP_PLUS_SHIFT);
-}
-
-void al_eth_lp_status_report_get(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_lane lane,
-			struct al_eth_kr_status_report_data *status)
-{
-	uint16_t reg;
-
-	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_LP_STATUS_REPORT, AL_ETH_LT_REGS, lane);
-
-	status->c_minus = AL_REG_FIELD_GET(reg,
-				    AL_ETH_KR_PMD_LP_STATUS_REPORT_MINUS_MASK,
-				    AL_ETH_KR_PMD_LP_STATUS_REPORT_MINUS_SHIFT);
-
-	status->c_zero = AL_REG_FIELD_GET(reg,
-				   AL_ETH_KR_PMD_LP_STATUS_REPORT_ZERO_MASK,
-				   AL_ETH_KR_PMD_LP_STATUS_REPORT_ZERO_SHIFT);
-
-	status->c_plus = AL_REG_FIELD_GET(reg,
-				   AL_ETH_KR_PMD_LP_STATUS_REPORT_PLUS_MASK,
-				   AL_ETH_KR_PMD_LP_STATUS_REPORT_PLUS_SHIFT);
-
-	status->receiver_ready =
-		(AL_REG_BIT_GET(
-			reg, AL_ETH_KR_PMD_LP_STATUS_RECEIVER_READY_SHIFT) != 0);
-
-}
-
-void al_eth_ld_coeff_up_set(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_lane lane,
-			struct al_eth_kr_coef_up_data *ldcoeff)
-{
-	uint16_t reg = 0;
-
-	if (ldcoeff->preset)
-		AL_REG_BIT_SET(reg, AL_ETH_KR_PMD_LD_COEF_UP_PRESET_SHIFT);
-
-	if (ldcoeff->initialize)
-		AL_REG_BIT_SET(reg, AL_ETH_KR_PMD_LD_COEF_UP_INITIALIZE_SHIFT);
-
-	AL_REG_FIELD_SET(reg,
-			 AL_ETH_KR_PMD_LD_COEF_UP_MINUS_MASK,
-			 AL_ETH_KR_PMD_LD_COEF_UP_MINUS_SHIFT,
-			 ldcoeff->c_minus);
-
-	AL_REG_FIELD_SET(reg,
-			 AL_ETH_KR_PMD_LD_COEF_UP_ZERO_MASK,
-			 AL_ETH_KR_PMD_LD_COEF_UP_ZERO_SHIFT,
-			 ldcoeff->c_zero);
-
-	AL_REG_FIELD_SET(reg,
-			 AL_ETH_KR_PMD_LD_COEF_UP_PLUS_MASK,
-			 AL_ETH_KR_PMD_LD_COEF_UP_PLUS_SHIFT,
-			 ldcoeff->c_plus);
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_LD_COEF_UP, AL_ETH_LT_REGS, lane, reg);
-}
-
-void al_eth_ld_status_report_set(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_lane lane,
-			struct al_eth_kr_status_report_data *status)
-{
-	uint16_t reg = 0;
-
-	AL_REG_FIELD_SET(reg,
-			 AL_ETH_KR_PMD_LD_STATUS_REPORT_MINUS_MASK,
-			 AL_ETH_KR_PMD_LD_STATUS_REPORT_MINUS_SHIFT,
-			 status->c_minus);
-
-	AL_REG_FIELD_SET(reg,
-			 AL_ETH_KR_PMD_LD_STATUS_REPORT_ZERO_MASK,
-			 AL_ETH_KR_PMD_LD_STATUS_REPORT_ZERO_SHIFT,
-			 status->c_zero);
-
-	AL_REG_FIELD_SET(reg,
-			 AL_ETH_KR_PMD_LD_STATUS_REPORT_PLUS_MASK,
-			 AL_ETH_KR_PMD_LD_STATUS_REPORT_PLUS_SHIFT,
-			 status->c_plus);
-
-	if (status->receiver_ready)
-		AL_REG_BIT_SET(reg,
-			AL_ETH_KR_PMD_LD_STATUS_REPORT_RECEIVER_READY_SHIFT);
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_LD_STATUS_REPORT, AL_ETH_LT_REGS, lane, reg);
-}
-
-al_bool al_eth_kr_receiver_frame_lock_get(struct al_hal_eth_adapter *adapter,
-					  enum al_eth_an_lt_lane lane)
-{
-	uint16_t reg;
-
-	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane);
-
-	return (AL_REG_BIT_GET(reg,
-			AL_ETH_KR_PMD_STATUS_RECEIVER_FRAME_LOCK_SHIFT) != 0);
-}
-
-al_bool al_eth_kr_startup_proto_prog_get(struct al_hal_eth_adapter *adapter,
-					 enum al_eth_an_lt_lane lane)
-{
-	uint16_t reg;
-
-	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane);
-
-	return (AL_REG_BIT_GET(
-		reg, AL_ETH_KR_PMD_STATUS_RECEIVER_START_UP_PROTO_PROG_SHIFT) != 0);
-}
-
-al_bool al_eth_kr_training_status_fail_get(struct al_hal_eth_adapter *adapter,
-					   enum al_eth_an_lt_lane lane)
-{
-	uint16_t reg;
-
-	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane);
-
-	return (AL_REG_BIT_GET(reg, AL_ETH_KR_PMD_STATUS_FAILURE_SHIFT) != 0);
-}
-
-void al_eth_receiver_ready_set(struct al_hal_eth_adapter *adapter,
-			       enum al_eth_an_lt_lane lane)
-{
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane, 1);
-}
-
-/*************************** auto negotiation *********************************/
-static int al_eth_kr_an_validate_adv(struct al_hal_eth_adapter *adapter,
-				     struct al_eth_an_adv *an_adv)
-{
-	al_assert(adapter);
-
-	if (an_adv == NULL)
-		return 0;
-
-	if (an_adv->selector_field != 1) {
-		al_err("[%s]: %s failed on selector_field (%d)\n",
-			adapter->name, __func__, an_adv->selector_field);
-		return -EINVAL;
-	}
-
-	if (an_adv->capability & AL_BIT(2)) {
-		al_err("[%s]: %s failed on capability bit 2 (%d)\n",
-			adapter->name, __func__, an_adv->capability);
-		return -EINVAL;
-	}
-
-	if (an_adv->remote_fault) {
-		al_err("[%s]: %s failed on remote_fault (%d)\n",
-			adapter->name, __func__, an_adv->remote_fault);
-		return -EINVAL;
-	}
-
-	if (an_adv->acknowledge) {
-		al_err("[%s]: %s failed on acknowledge (%d)\n",
-			adapter->name, __func__, an_adv->acknowledge);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int al_eth_kr_an_write_adv(struct al_hal_eth_adapter *adapter,
-			       struct al_eth_an_adv *an_adv)
-{
-	uint16_t	reg;
-
-	if(an_adv == NULL)
-		return 0;
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV1_SEL_FIELD_MASK,
-			 AL_ETH_KR_AN_ADV1_SEL_FIELD_SHIFT,
-			 an_adv->selector_field);
-
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV1_ECHOED_NONCE_MASK,
-			 AL_ETH_KR_AN_ADV1_ECHOED_NONCE_SHIFT,
-			 an_adv->echoed_nonce);
-
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV1_CAPABILITY_MASK,
-			 AL_ETH_KR_AN_ADV1_CAPABILITY_SHIFT,
-			 an_adv->capability);
-
-	AL_REG_BIT_VAL_SET(reg, AL_ETH_KR_AN_ADV1_REM_FAULT_SHIFT,
-			   an_adv->remote_fault);
-
-	AL_REG_BIT_VAL_SET(reg, AL_ETH_KR_AN_ADV1_ACK_SHIFT,
-			   an_adv->acknowledge);
-
-	AL_REG_BIT_VAL_SET(reg, AL_ETH_KR_AN_ADV1_NEXT_PAGE_SHIFT,
-			   an_adv->next_page);
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_ADV0, AL_ETH_AN_REGS,
-			       AL_ETH_AN__LT_LANE_0, reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV2_TX_NONCE_MASK,
-			 AL_ETH_KR_AN_ADV2_TX_NONCE_SHIFT,
-			 an_adv->transmitted_nonce);
-
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV2_TECH_MASK,
-			 AL_ETH_KR_AN_ADV2_TECH_SHIFT,
-			 an_adv->technology);
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_ADV1, AL_ETH_AN_REGS,
-			       AL_ETH_AN__LT_LANE_0, reg);
-
-	reg = 0;
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV3_TECH_MASK,
-			 AL_ETH_KR_AN_ADV3_TECH_SHIFT,
-			 an_adv->technology >> 11);
-
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV3_FEC_MASK,
-			 AL_ETH_KR_AN_ADV3_FEC_SHIFT,
-			 an_adv->fec_capability);
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_ADV2, AL_ETH_AN_REGS,
-			       AL_ETH_AN__LT_LANE_0, reg);
-
-	return 0;
-}
-
-void al_eth_kr_an_read_adv(struct al_hal_eth_adapter *adapter,
-			   struct al_eth_an_adv *an_adv)
-{
-	int16_t	reg;
-
-	al_assert(an_adv != NULL);
-
-
-	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_REM_ADV0,
-				    AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
-
-	an_adv->selector_field = AL_REG_FIELD_GET(reg,
-					AL_ETH_KR_AN_ADV1_SEL_FIELD_MASK,
-					AL_ETH_KR_AN_ADV1_SEL_FIELD_SHIFT);
-
-	an_adv->echoed_nonce = AL_REG_FIELD_GET(reg,
-					AL_ETH_KR_AN_ADV1_ECHOED_NONCE_MASK,
-					AL_ETH_KR_AN_ADV1_ECHOED_NONCE_SHIFT);
-
-	an_adv->capability = AL_REG_FIELD_GET(reg,
-					AL_ETH_KR_AN_ADV1_CAPABILITY_MASK,
-					AL_ETH_KR_AN_ADV1_CAPABILITY_SHIFT);
-
-	an_adv->remote_fault = AL_REG_BIT_GET(reg,
-					AL_ETH_KR_AN_ADV1_REM_FAULT_SHIFT);
-
-	an_adv->acknowledge = AL_REG_BIT_GET(reg,
-					AL_ETH_KR_AN_ADV1_ACK_SHIFT);
-
-	an_adv->next_page = AL_REG_BIT_GET(reg,
-					AL_ETH_KR_AN_ADV1_NEXT_PAGE_SHIFT);
-
-
-	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_REM_ADV1,
-				    AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
-
-	an_adv->transmitted_nonce = AL_REG_FIELD_GET(reg,
-					 AL_ETH_KR_AN_ADV2_TX_NONCE_MASK,
-					 AL_ETH_KR_AN_ADV2_TX_NONCE_SHIFT);
-
-	an_adv->technology = AL_REG_FIELD_GET(reg,
-					 AL_ETH_KR_AN_ADV2_TECH_MASK,
-					 AL_ETH_KR_AN_ADV2_TECH_SHIFT);
-
-
-	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_REM_ADV2,
-				    AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
-
-	an_adv->technology |= (AL_REG_FIELD_GET(reg,
-					AL_ETH_KR_AN_ADV3_TECH_MASK,
-					AL_ETH_KR_AN_ADV3_TECH_SHIFT)  << 11);
-
-	an_adv->fec_capability = AL_REG_FIELD_GET(reg,
-					 AL_ETH_KR_AN_ADV3_FEC_MASK,
-					 AL_ETH_KR_AN_ADV3_FEC_SHIFT);
-}
-
-int al_eth_kr_next_page_read(struct al_hal_eth_adapter *adapter,
-			     struct al_eth_an_np *np)
-{
-	uint16_t reg;
-
-	reg = al_eth_an_lt_reg_read(adapter,
-				    AL_ETH_KR_AN_REM_XNP_ADV0,
-				    AL_ETH_AN_REGS,
-				    AL_ETH_AN__LT_LANE_0);
-
-	np->unformatted_code_field = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_DATA1_MASK,
-					 AL_ETH_KR_AN_NP_ADV1_DATA1_SHIFT);
-
-	np->toggle = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_TOGGLE_MASK,
-					 AL_ETH_KR_AN_NP_ADV1_TOGGLE_SHIFT);
-
-	np->ack2 = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_ACK2_MASK,
-					 AL_ETH_KR_AN_NP_ADV1_ACK2_SHIFT);
-
-	np->msg_page = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_MASK,
-					 AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_SHIFT);
-
-	np->next_page = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_NP_MASK,
-					 AL_ETH_KR_AN_NP_ADV1_NP_SHIFT);
-
-	np->unformatted_code_field1 = al_eth_an_lt_reg_read(adapter,
-							    AL_ETH_KR_AN_REM_XNP_ADV1,
-							    AL_ETH_AN_REGS,
-							    AL_ETH_AN__LT_LANE_0);
-	np->unformatted_code_field2 = al_eth_an_lt_reg_read(adapter,
-							    AL_ETH_KR_AN_REM_XNP_ADV2,
-							    AL_ETH_AN_REGS,
-							    AL_ETH_AN__LT_LANE_0);
-
-	return 0;
-}
-
-int al_eth_kr_next_page_write(struct al_hal_eth_adapter *adapter,
-			      struct al_eth_an_np *np)
-{
-	uint16_t reg = 0;
-
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_DATA1_MASK,
-			 AL_ETH_KR_AN_NP_ADV1_DATA1_SHIFT,
-			 np->unformatted_code_field);
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_TOGGLE_MASK,
-			 AL_ETH_KR_AN_NP_ADV1_TOGGLE_SHIFT,
-			 np->toggle);
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_ACK2_MASK,
-			 AL_ETH_KR_AN_NP_ADV1_ACK2_SHIFT,
-			 np->ack2);
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_MASK,
-			 AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_SHIFT,
-			 np->msg_page);
-	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_NP_MASK,
-			 AL_ETH_KR_AN_NP_ADV1_NP_SHIFT,
-			 np->next_page);
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_XNP_ADV0, AL_ETH_AN_REGS,
-			       AL_ETH_AN__LT_LANE_0, reg);
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_XNP_ADV1, AL_ETH_AN_REGS,
-			       AL_ETH_AN__LT_LANE_0, np->unformatted_code_field1);
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_XNP_ADV2, AL_ETH_AN_REGS,
-			       AL_ETH_AN__LT_LANE_0, np->unformatted_code_field2);
-
-	return 0;
-}
-
-int al_eth_kr_an_init(struct al_hal_eth_adapter *adapter,
-		      struct al_eth_an_adv *an_adv)
-{
-	int		rc;
-
-	if (adapter->rev_id > AL_ETH_REV_ID_2)
-		al_eth_an_lt_unit_config(adapter);
-
-	rc = al_eth_kr_an_validate_adv(adapter, an_adv);
-	if (rc)
-		return rc;
-
-	rc = al_eth_kr_an_write_adv(adapter, an_adv);
-	if (rc)
-		return rc;
-
-	/* clear status */
-	al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_STATUS, AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
-
-	al_dbg("[%s]: autonegotiation initialized successfully", adapter->name);
-	return 0;
-}
-
-int al_eth_kr_an_start(struct al_hal_eth_adapter *adapter,
-		       enum al_eth_an_lt_lane lane,
-		       al_bool next_page_enable,
-		       al_bool lt_enable)
-{
-	uint16_t control = AL_ETH_KR_AN_CONTROL_ENABLE | AL_ETH_KR_AN_CONTROL_RESTART;
-
-	al_dbg("Eth [%s]: enable autonegotiation. lt_en %s",
-		adapter->name, (lt_enable == AL_TRUE) ? "yes" : "no");
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_CONTROL, AL_ETH_LT_REGS,
-			       lane, AL_BIT(AL_ETH_KR_PMD_CONTROL_RESTART));
-
-	if (next_page_enable == AL_TRUE)
-		control |= AL_ETH_KR_AN_CONTROL_NP_ENABLE;
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_CONTROL, AL_ETH_AN_REGS,
-			       lane, control);
-
-	if (lt_enable == AL_TRUE) {
-		al_eth_kr_lt_initialize(adapter, lane);
-	}
-
-	return 0;
-}
-
-void al_eth_kr_an_stop(struct al_hal_eth_adapter *adapter)
-{
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_CONTROL, AL_ETH_AN_REGS,
-			       AL_ETH_AN__LT_LANE_0, 0);
-}
-
-void al_eth_kr_an_status_check(struct al_hal_eth_adapter *adapter,
-			      al_bool *page_received,
-			      al_bool *an_completed,
-			      al_bool *error)
-{
-	uint16_t	reg;
-
-	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_STATUS,
-				    AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
-
-	if ((reg & AL_ETH_KR_AN_STATUS_CHECK_MASK) !=
-				AL_ETH_KR_AN_STATUS_CHECK_NO_ERROR) {
-		al_err("[%s]: %s AN_STATUS (0x%x) indicated error\n",
-			adapter->name, __func__, reg);
-
-		*error = AL_TRUE;
-	}
-
-	if (reg & AL_ETH_KR_AN_STATUS_BASE_PAGE_RECEIVED)
-		*page_received = AL_TRUE;
-	else
-		*page_received = AL_FALSE;
-
-	if (reg & AL_ETH_KR_AN_STATUS_COMPLETED)
-		*an_completed = AL_TRUE;
-	else
-		*an_completed = AL_FALSE;
-}
-
-
-/****************************** KR Link Training *****************************/
-void al_eth_kr_lt_restart(struct al_hal_eth_adapter *adapter,
-			  enum al_eth_an_lt_lane lane)
-{
-	al_dbg("[%s]: KR LT Restart Link Training.\n", adapter->name);
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_CONTROL, AL_ETH_LT_REGS,
-			       lane, (AL_BIT(AL_ETH_KR_PMD_CONTROL_ENABLE) |
-				      AL_BIT(AL_ETH_KR_PMD_CONTROL_RESTART)));
-}
-
-void al_eth_kr_lt_stop(struct al_hal_eth_adapter *adapter,
-		       enum al_eth_an_lt_lane lane)
-{
-	al_dbg("[%s]: KR LT Stop Link Training.\n", adapter->name);
-
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_CONTROL, AL_ETH_LT_REGS,
-			       lane, AL_BIT(AL_ETH_KR_PMD_CONTROL_RESTART));
-}
-
-void al_eth_kr_lt_initialize(struct al_hal_eth_adapter *adapter,
-			     enum al_eth_an_lt_lane lane)
-{
-	al_dbg("[%s]: KR LT Initialize.\n", adapter->name);
-
-	/* Reset LT state machine */
-	al_eth_kr_lt_stop(adapter, lane);
-
-	/* clear receiver status */
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane, 0);
-
-	/* Coefficient Update to all zero (no command, hold) */
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_LD_COEF_UP, AL_ETH_LT_REGS, lane, 0);
-	/* Coefficient Status to all zero (not_updated) */
-	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_LD_STATUS_REPORT, AL_ETH_LT_REGS, lane, 0);
-
-	/* start */
-	al_eth_kr_lt_restart(adapter, lane);
-}
-
-al_bool al_eth_kr_lt_frame_lock_wait(struct al_hal_eth_adapter *adapter,
-				     enum al_eth_an_lt_lane lane,
-				     uint32_t timeout)
-{
-	uint32_t loop;
-	uint16_t reg = 0;
-
-	for (loop = 0; loop < timeout; loop++) {
-		reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane);
-
-		if (AL_REG_BIT_GET(reg, AL_ETH_KR_PMD_STATUS_FAILURE_SHIFT)) {
-			al_info("[%s]: Failed on Training Failure."
-			       " loops %d PMD STATUS 0x%04x\n",
-			       adapter->name, loop, reg);
-
-			return AL_FALSE;
-		}
-		if (AL_REG_BIT_GET(reg,
-			AL_ETH_KR_PMD_STATUS_RECEIVER_FRAME_LOCK_SHIFT)) {
-			al_dbg("[%s]: Frame lock received."
-			       " loops %d PMD STATUS 0x%04x\n",
-			       adapter->name, loop, reg);
-
-			return AL_TRUE;
-		}
-		al_udelay(1);
-	}
-	al_info("[%s]: Failed on timeout. PMD STATUS 0x%04x\n",
-			adapter->name, reg);
-
-	return AL_FALSE;
-}
diff --git a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_kr.h b/sys/contrib/alpine-hal/eth/eth/al_hal_eth_kr.h
deleted file mode 100644
index c8b69460aaa7..000000000000
--- a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_kr.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-/**
- * @defgroup group_eth_kr_api API
- * Ethernet KR auto-neg and link-training driver API
- * @ingroup group_eth
- * @{
- * @file   al_hal_eth_kr.h
- *
- * @brief Header file for KR driver
- *
- *
- */
-
-#ifndef __AL_HAL_ETH_KR_H__
-#define __AL_HAL_ETH_KR_H__
-
-#include "al_hal_eth.h"
-
-/* *INDENT-OFF* */
-#ifdef __cplusplus
-extern "C" {
-#endif
-/* *INDENT-ON* */
-
-/* AN (Auto-negotiation) Advertisement Registers */
-struct al_eth_an_adv {
-	/* constant value defining 802.3ap support.
-	 * The suggested value is 0x01.*/
-	uint8_t   selector_field;
-	/* Contains arbitrary data. */
-	uint8_t   echoed_nonce;
-	/* pause capability. */
-	uint8_t   capability;
-	/* Set to 1 to indicate a Remote Fault condition.
-	 * Set to 0 to indicate normal operation.*/
-	uint8_t   remote_fault;
-	/* Should always be set to 0. */
-	uint8_t   acknowledge;
-	/* Set to 1 to indicate that the device has next pages to send.
-	 * Set to 0 to indicate that that device has no next pages to send. */
-	uint8_t   next_page;
-	/* Must be set to an arbitrary value.
-	 * Two devices must have a different nonce for autonegotiation to
-	 * operate (a loopback will not allow autonegotiation to complete). */
-	uint8_t   transmitted_nonce;
-	uint32_t  technology;
-#define AL_ETH_AN_TECH_1000BASE_KX  AL_BIT(0)
-#define AL_ETH_AN_TECH_10GBASE_KX4  AL_BIT(1)
-#define AL_ETH_AN_TECH_10GBASE_KR   AL_BIT(2)
-#define AL_ETH_AN_TECH_40GBASE_KR4  AL_BIT(3)
-#define AL_ETH_AN_TECH_40GBASE_CR4  AL_BIT(4)
-#define AL_ETH_AN_TECH_100GBASE_CR  AL_BIT(5)
-	uint8_t   fec_capability;
-};
-
-/* AN next page fields */
-struct al_eth_an_np {
-	/* These bits can be used as message code field or unformatted code field.
-	 * When msg_page is true, these bits represent message code field.
-	 * Predefined message code field Code Field should be used as specified in the standard
-	 * 802.3ap.
-	 * For the null message code the value is 0x01.
-	 */
-	uint16_t	unformatted_code_field;
-	/* Flag to keep track of the state of the local device's Toggle bit.
-	 * Initial value is taken from base page. Set to 0.
-	 */
-	al_bool		toggle;
-	/* Acknowledge 2 is used to indicate that the receiver is able to act on the information
-	 * (or perform the task) defined in the message.
-	 */
-	al_bool		ack2;
-	al_bool		msg_page;
-	/* If the device does not have any more Next Pages to send, set to AL_FALSE */
-	al_bool		next_page;
-	uint16_t	unformatted_code_field1;
-	uint16_t	unformatted_code_field2;
-};
-
-enum al_eth_kr_cl72_cstate {
-	C72_CSTATE_NOT_UPDATED = 0,
-	C72_CSTATE_UPDATED = 1,
-	C72_CSTATE_MIN = 2,
-	C72_CSTATE_MAX = 3,
-};
-
-enum al_eth_kr_cl72_coef_op {
-	AL_PHY_KR_COEF_UP_HOLD = 0,
-	AL_PHY_KR_COEF_UP_INC = 1,
-	AL_PHY_KR_COEF_UP_DEC = 2,
-	AL_PHY_KR_COEF_UP_RESERVED = 3
-};
-
-struct al_eth_kr_coef_up_data {
-	enum al_eth_kr_cl72_coef_op c_zero;
-	enum al_eth_kr_cl72_coef_op c_plus;
-	enum al_eth_kr_cl72_coef_op c_minus;
-	al_bool preset;
-	al_bool initialize;
-};
-
-struct al_eth_kr_status_report_data {
-	enum al_eth_kr_cl72_cstate c_zero;
-	enum al_eth_kr_cl72_cstate c_plus;
-	enum al_eth_kr_cl72_cstate c_minus;
-	al_bool receiver_ready;
-};
-
-enum al_eth_an_lt_lane {
-	AL_ETH_AN__LT_LANE_0,
-	AL_ETH_AN__LT_LANE_1,
-	AL_ETH_AN__LT_LANE_2,
-	AL_ETH_AN__LT_LANE_3,
-};
-
-/**
- * get the last received coefficient update message from the link partner
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- * @param lpcoeff coeff update received
- *
- */
-void al_eth_lp_coeff_up_get(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_lane lane,
-			struct al_eth_kr_coef_up_data *lpcoeff);
-
-/**
- * get the last received status report message from the link partner
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- * @param status status report received
- *
- */
-void al_eth_lp_status_report_get(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_lane lane,
-			struct al_eth_kr_status_report_data *status);
-
-/**
- * set the coefficient data for the next message that will be sent to lp
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- * @param ldcoeff coeff update to send
- *
- */
-void al_eth_ld_coeff_up_set(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_lane lane,
-			struct al_eth_kr_coef_up_data *ldcoeff);
-
-/**
- * set the status report message for the next message that will be sent to lp
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- * @param status status report to send
- *
- */
-void al_eth_ld_status_report_set(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_an_lt_lane lane,
-			struct al_eth_kr_status_report_data *status);
-
-/**
- * get the receiver frame lock status
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- *
- * @return true if Training frame delineation is detected, otherwise false.
- */
-al_bool al_eth_kr_receiver_frame_lock_get(struct al_hal_eth_adapter *adapter,
-					  enum al_eth_an_lt_lane lane);
-
-/**
- * get the start up protocol progress status
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- *
- * @return true if the startup protocol is in progress.
- */
-al_bool al_eth_kr_startup_proto_prog_get(struct al_hal_eth_adapter *adapter,
-					 enum al_eth_an_lt_lane lane);
-
-/**
- * indicate the receiver is ready (the link training is completed)
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- *
- */
-void al_eth_receiver_ready_set(struct al_hal_eth_adapter *adapter,
-			       enum al_eth_an_lt_lane lane);
-
-/**
- * read Training failure status.
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- *
- *@return true if Training failure has been detected.
- */
-al_bool al_eth_kr_training_status_fail_get(struct al_hal_eth_adapter *adapter,
-					   enum al_eth_an_lt_lane lane);
-
-/****************************** auto negotiation *******************************/
-/**
- * Initialize Auto-negotiation
- * - Program Ability Registers (Advertisement Registers)
- * - Clear Status latches
- * @param adapter pointer to the private structure
- * @param an_adv pointer to the AN Advertisement Registers structure
- *        when NULL, the registers will not be updated.
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_kr_an_init(struct al_hal_eth_adapter *adapter,
-		      struct al_eth_an_adv *an_adv);
-
-/**
- * Enable/Restart Auto-negotiation
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- * @param lt_enable initialize link training as well
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_kr_an_start(struct al_hal_eth_adapter *adapter,
-		       enum al_eth_an_lt_lane lane,
-		       al_bool next_page_enable,
-		       al_bool lt_enable);
-
-
-int al_eth_kr_next_page_write(struct al_hal_eth_adapter *adapter,
-			      struct al_eth_an_np *np);
-
-int al_eth_kr_next_page_read(struct al_hal_eth_adapter *adapter,
-			     struct al_eth_an_np *np);
-
-/**
- * Stop Auto-negotiation
- *
- * Stopping the auto-negotiation will prevent the mac from sending the last page
- * to the link partner in case it start the AN again. It must be called after
- * link training is completed or the software will lose sync with the HW state
- * machine
- *
- * @param adapter pointer to the private structure
- *
- */
-void al_eth_kr_an_stop(struct al_hal_eth_adapter *adapter);
-
-/**
- *  Check Auto-negotiation event done
- *
- * @param adapter pointer to the private structure
- * @param page_received	Set to true if the AN page received indication is set.
- *			Set to false otherwise.
- * @param an_completed	Set to true of the AN completed indication is set.
- *			Set to false otherwise.
- * @param error	Set to true if any error encountered
- *
- */
-void al_eth_kr_an_status_check(struct al_hal_eth_adapter *adapter,
-			      al_bool *page_received,
-			      al_bool *an_completed,
-			      al_bool *error);
-
-/**
- *  Read the remote auto-negotiation advertising.
- *  This function is safe to called after al_eth_kr_an_status_check returned
- *  with page_received set.
- *
- * @param adapter pointer to the private structure
- * @param an_adv pointer to the AN Advertisement Registers structure
- *
- */
-void al_eth_kr_an_read_adv(struct al_hal_eth_adapter *adapter,
-			   struct al_eth_an_adv *an_adv);
-
-/****************************** link training **********************************/
-/**
- *  Initialize Link-training.
- *  Clear the status register and set the local coefficient update and status
- *  to zero.
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- *
- */
-void al_eth_kr_lt_initialize(struct al_hal_eth_adapter *adapter,
-			     enum al_eth_an_lt_lane lane);
-
-/**
- * Wait for frame lock.
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- * @param timeout timeout in usec.
- *
- * @return true if frame lock received. false otherwise.
- */
-al_bool al_eth_kr_lt_frame_lock_wait(struct al_hal_eth_adapter *adapter,
-				     enum al_eth_an_lt_lane lane,
-				     uint32_t timeout);
-
-/**
- * reset the 10GBase- KR startup protocol and begin its operation
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- *
- */
-void al_eth_kr_lt_restart(struct al_hal_eth_adapter *adapter,
-			  enum al_eth_an_lt_lane lane);
-
-/**
- * reset the 10GBase- KR startup protocol and end its operation
- *
- * @param adapter pointer to the private structure
- * @param lane lane number
- *
- */
-void al_eth_kr_lt_stop(struct al_hal_eth_adapter *adapter,
-		       enum al_eth_an_lt_lane lane);
-
-#ifdef __cplusplus
-}
-#endif
-/* *INDENT-ON* */
-#endif /*__AL_HAL_ETH_KR_H__*/
-/** @} end of Ethernet kr group */
diff --git a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_mac_regs.h b/sys/contrib/alpine-hal/eth/eth/al_hal_eth_mac_regs.h
deleted file mode 100644
index 3218e5c4cacc..000000000000
--- a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_mac_regs.h
+++ /dev/null
@@ -1,2088 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_eth_mac_regs.h
- *
- * @brief Ethernet MAC registers
- *
- */
-
-#ifndef __AL_HAL_ETH_MAC_REGS_H__
-#define __AL_HAL_ETH_MAC_REGS_H__
-
-#include "al_hal_plat_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
-* Unit Registers
-*/
-
-struct al_eth_mac_1g_stats {
-	uint32_t reserved1[2];
-	uint32_t aFramesTransmittedOK;			/* 0x68 */
-	uint32_t aFramesReceivedOK;			/* 0x6c */
-	uint32_t aFrameCheckSequenceErrors;		/* 0x70 */
-	uint32_t aAlignmentErrors;			/* 0x74 */
-	uint32_t aOctetsTransmittedOK;			/* 0x78 */
-	uint32_t aOctetsReceivedOK;			/* 0x7c */
-	uint32_t aPAUSEMACCtrlFramesTransmitted;	/* 0x80 */
-	uint32_t aPAUSEMACCtrlFramesReceived;		/* 0x84 */
-	uint32_t ifInErrors	;			/* 0x88 */
-	uint32_t ifOutErrors;				/* 0x8c */
-	uint32_t ifInUcastPkts;				/* 0x90 */
-	uint32_t ifInMulticastPkts;			/* 0x94 */
-	uint32_t ifInBroadcastPkts;			/* 0x98 */
-	uint32_t reserved2;
-	uint32_t ifOutUcastPkts;			/* 0xa0 */
-	uint32_t ifOutMulticastPkts;			/* 0xa4 */
-	uint32_t ifOutBroadcastPkts;			/* 0xa8 */
-	uint32_t etherStatsDropEvents;			/* 0xac */
-	uint32_t etherStatsOctets;			/* 0xb0 */
-	uint32_t etherStatsPkts;			/* 0xb4 */
-	uint32_t etherStatsUndersizePkts;		/* 0xb8 */
-	uint32_t etherStatsOversizePkts;		/* 0xbc */
-	uint32_t etherStatsPkts64Octets;		/* 0xc0 */
-	uint32_t etherStatsPkts65to127Octets;		/* 0xc4 */
-	uint32_t etherStatsPkts128to255Octets;		/* 0xc8 */
-	uint32_t etherStatsPkts256to511Octets;		/* 0xcc */
-	uint32_t etherStatsPkts512to1023Octets;		/* 0xd0 */
-	uint32_t etherStatsPkts1024to1518Octets;	/* 0xd4 */
-	uint32_t etherStatsPkts1519toX;			/* 0xd8 */
-	uint32_t etherStatsJabbers;			/* 0xdc */
-	uint32_t etherStatsFragments;			/* 0xe0 */
-	uint32_t reserved3[71];
-};
-
-struct al_eth_mac_1g {
-	/* [0x0] */
-	uint32_t rev;
-	uint32_t scratch;
-	uint32_t cmd_cfg;
-	uint32_t mac_0;
-	/* [0x10] */
-	uint32_t mac_1;
-	uint32_t frm_len;
-	uint32_t pause_quant;
-	uint32_t rx_section_empty;
-	/* [0x20] */
-	uint32_t rx_section_full;
-	uint32_t tx_section_empty;
-	uint32_t tx_section_full;
-	uint32_t rx_almost_empty;
-	/* [0x30] */
-	uint32_t rx_almost_full;
-	uint32_t tx_almost_empty;
-	uint32_t tx_almost_full;
-	uint32_t mdio_addr0;
-	/* [0x40] */
-	uint32_t mdio_addr1;
-	uint32_t Reserved[5];
-	/* [0x58] */
-	uint32_t reg_stat;
-	uint32_t tx_ipg_len;
-	/* [0x60] */
-	struct al_eth_mac_1g_stats stats;
-	/* [0x200] */
-	uint32_t phy_regs_base;
-	uint32_t Reserved2[127];
-};
-
-struct al_eth_mac_10g_stats_v2 {
-	uint32_t aFramesTransmittedOK;			/* 0x80 */
-	uint32_t reserved1;
-	uint32_t aFramesReceivedOK;			/* 0x88 */
-	uint32_t reserved2;
-	uint32_t aFrameCheckSequenceErrors;		/* 0x90 */
-	uint32_t reserved3;
-	uint32_t aAlignmentErrors;			/* 0x98 */
-	uint32_t reserved4;
-	uint32_t aPAUSEMACCtrlFramesTransmitted;	/* 0xa0 */
-	uint32_t reserved5;
-	uint32_t aPAUSEMACCtrlFramesReceived;		/* 0xa8 */
-	uint32_t reserved6;
-	uint32_t aFrameTooLongErrors;			/* 0xb0 */
-	uint32_t reserved7;
-	uint32_t aInRangeLengthErrors;			/* 0xb8 */
-	uint32_t reserved8;
-	uint32_t VLANTransmittedOK;			/* 0xc0 */
-	uint32_t reserved9;
-	uint32_t VLANReceivedOK;			/* 0xc8 */
-	uint32_t reserved10;
-	uint32_t ifOutOctetsL;				/* 0xd0 */
-	uint32_t ifOutOctetsH;				/* 0xd4 */
-	uint32_t ifInOctetsL;				/* 0xd8 */
-	uint32_t ifInOctetsH;				/* 0xdc */
-	uint32_t ifInUcastPkts;				/* 0xe0 */
-	uint32_t reserved11;
-	uint32_t ifInMulticastPkts;			/* 0xe8 */
-	uint32_t reserved12;
-	uint32_t ifInBroadcastPkts;			/* 0xf0 */
-	uint32_t reserved13;
-	uint32_t ifOutErrors;				/* 0xf8 */
-	uint32_t reserved14[3];
-	uint32_t ifOutUcastPkts;			/* 0x108 */
-	uint32_t reserved15;
-	uint32_t ifOutMulticastPkts;			/* 0x110 */
-	uint32_t reserved16;
-	uint32_t ifOutBroadcastPkts;			/* 0x118 */
-	uint32_t reserved17;
-	uint32_t etherStatsDropEvents;			/* 0x120 */
-	uint32_t reserved18;
-	uint32_t etherStatsOctets;			/* 0x128 */
-	uint32_t reserved19;
-	uint32_t etherStatsPkts;			/* 0x130 */
-	uint32_t reserved20;
-	uint32_t etherStatsUndersizePkts;		/* 0x138 */
-	uint32_t reserved21;
-	uint32_t etherStatsPkts64Octets;		/* 0x140 */
-	uint32_t reserved22;
-	uint32_t etherStatsPkts65to127Octets;		/* 0x148 */
-	uint32_t reserved23;
-	uint32_t etherStatsPkts128to255Octets;		/* 0x150 */
-	uint32_t reserved24;
-	uint32_t etherStatsPkts256to511Octets;		/* 0x158 */
-	uint32_t reserved25;
-	uint32_t etherStatsPkts512to1023Octets;		/* 0x160 */
-	uint32_t reserved26;
-	uint32_t etherStatsPkts1024to1518Octets;	/* 0x168 */
-	uint32_t reserved27;
-	uint32_t etherStatsPkts1519toX;			/* 0x170 */
-	uint32_t reserved28;
-	uint32_t etherStatsOversizePkts;		/* 0x178 */
-	uint32_t reserved29;
-	uint32_t etherStatsJabbers;			/* 0x180 */
-	uint32_t reserved30;
-	uint32_t etherStatsFragments;			/* 0x188 */
-	uint32_t reserved31;
-	uint32_t ifInErrors;				/* 0x190 */
-	uint32_t reserved32[91];
-};
-
-struct al_eth_mac_10g_stats_v3_rx {
-	uint32_t etherStatsOctets;			/* 0x00 */
-	uint32_t reserved2;
-	uint32_t ifOctetsL;				/* 0x08 */
-	uint32_t ifOctetsH;				/* 0x0c */
-	uint32_t aAlignmentErrors;			/* 0x10 */
-	uint32_t reserved4;
-	uint32_t aPAUSEMACCtrlFrames;			/* 0x18 */
-	uint32_t reserved5;
-	uint32_t FramesOK;				/* 0x20 */
-	uint32_t reserved6;
-	uint32_t CRCErrors;				/* 0x28 */
-	uint32_t reserved7;
-	uint32_t VLANOK;				/* 0x30 */
-	uint32_t reserved8;
-	uint32_t ifInErrors;				/* 0x38 */
-	uint32_t reserved9;
-	uint32_t ifInUcastPkts;				/* 0x40 */
-	uint32_t reserved10;
-	uint32_t ifInMulticastPkts;			/* 0x48 */
-	uint32_t reserved11;
-	uint32_t ifInBroadcastPkts;			/* 0x50 */
-	uint32_t reserved12;
-	uint32_t etherStatsDropEvents;			/* 0x58 */
-	uint32_t reserved13;
-	uint32_t etherStatsPkts;			/* 0x60 */
-	uint32_t reserved14;
-	uint32_t etherStatsUndersizePkts;		/* 0x68 */
-	uint32_t reserved15;
-	uint32_t etherStatsPkts64Octets;		/* 0x70 */
-	uint32_t reserved16;
-	uint32_t etherStatsPkts65to127Octets;		/* 0x78 */
-	uint32_t reserved17;
-	uint32_t etherStatsPkts128to255Octets;		/* 0x80 */
-	uint32_t reserved18;
-	uint32_t etherStatsPkts256to511Octets;		/* 0x88 */
-	uint32_t reserved19;
-	uint32_t etherStatsPkts512to1023Octets;		/* 0x90 */
-	uint32_t reserved20;
-	uint32_t etherStatsPkts1024to1518Octets;	/* 0x98 */
-	uint32_t reserved21;
-	uint32_t etherStatsPkts1519toMax;		/* 0xa0 */
-	uint32_t reserved22;
-	uint32_t etherStatsOversizePkts;		/* 0xa8 */
-	uint32_t reserved23;
-	uint32_t etherStatsJabbers;			/* 0xb0 */
-	uint32_t reserved24;
-	uint32_t etherStatsFragments;			/* 0xb8 */
-	uint32_t reserved25;
-	uint32_t aMACControlFramesReceived;		/* 0xc0 */
-	uint32_t reserved26;
-	uint32_t aFrameTooLong;				/* 0xc8 */
-	uint32_t reserved27;
-	uint32_t aInRangeLengthErrors;			/* 0xd0 */
-	uint32_t reserved28;
-	uint32_t reserved29[10];
-};
-
-struct al_eth_mac_10g_stats_v3_tx {
-	uint32_t etherStatsOctets;			/* 0x00 */
-	uint32_t reserved30;
-	uint32_t ifOctetsL;				/* 0x08 */
-	uint32_t ifOctetsH;				/* 0x0c */
-	uint32_t aAlignmentErrors;			/* 0x10 */
-	uint32_t reserved32;
-	uint32_t aPAUSEMACCtrlFrames;			/* 0x18 */
-	uint32_t reserved33;
-	uint32_t FramesOK;				/* 0x20 */
-	uint32_t reserved34;
-	uint32_t CRCErrors;				/* 0x28 */
-	uint32_t reserved35;
-	uint32_t VLANOK;				/* 0x30 */
-	uint32_t reserved36;
-	uint32_t ifOutErrors;				/* 0x38 */
-	uint32_t reserved37;
-	uint32_t ifUcastPkts;				/* 0x40 */
-	uint32_t reserved38;
-	uint32_t ifMulticastPkts;			/* 0x48 */
-	uint32_t reserved39;
-	uint32_t ifBroadcastPkts;			/* 0x50 */
-	uint32_t reserved40;
-	uint32_t etherStatsDropEvents;			/* 0x58 */
-	uint32_t reserved41;
-	uint32_t etherStatsPkts;			/* 0x60 */
-	uint32_t reserved42;
-	uint32_t etherStatsUndersizePkts;		/* 0x68 */
-	uint32_t reserved43;
-	uint32_t etherStatsPkts64Octets;		/* 0x70 */
-	uint32_t reserved44;
-	uint32_t etherStatsPkts65to127Octets;		/* 0x78 */
-	uint32_t reserved45;
-	uint32_t etherStatsPkts128to255Octets;		/* 0x80 */
-	uint32_t reserved46;
-	uint32_t etherStatsPkts256to511Octets;		/* 0x88 */
-	uint32_t reserved47;
-	uint32_t etherStatsPkts512to1023Octets;		/* 0x90 */
-	uint32_t reserved48;
-	uint32_t etherStatsPkts1024to1518Octets;	/* 0x98 */
-	uint32_t reserved49;
-	uint32_t etherStatsPkts1519toTX_MTU;		/* 0xa0 */
-	uint32_t reserved50;
-	uint32_t reserved51[4];
-	uint32_t aMACControlFrames;			/* 0xc0 */
-	uint32_t reserved52[15];
-};
-
-struct al_eth_mac_10g_stats_v3 {
-	uint32_t reserved1[32];
-	/* 0x100 */
-	struct al_eth_mac_10g_stats_v3_rx	rx;
-	/* 0x200 */
-	struct al_eth_mac_10g_stats_v3_tx	tx;
-};
-
-union al_eth_mac_10g_stats {
-	struct al_eth_mac_10g_stats_v2	v2;
-	struct al_eth_mac_10g_stats_v3	v3;
-};
-
-struct al_eth_mac_10g {
-	/* [0x0] */
-	uint32_t rev;
-	uint32_t scratch;
-	uint32_t cmd_cfg;
-	uint32_t mac_0;
-	/* [0x10] */
-	uint32_t mac_1;
-	uint32_t frm_len;
-	uint32_t Reserved;
-	uint32_t rx_fifo_sections;
-	/* [0x20] */
-	uint32_t tx_fifo_sections;
-	uint32_t rx_fifo_almost_f_e;
-	uint32_t tx_fifo_almost_f_e;
-	uint32_t hashtable_load;
-	/* [0x30] */
-	uint32_t mdio_cfg_status;
-	uint16_t mdio_cmd;
-	uint16_t reserved1;
-	uint16_t mdio_data;
-	uint16_t reserved2;
-	uint16_t mdio_regaddr;
-	uint16_t reserved3;
-	/* [0x40] */
-	uint32_t status;
-	uint32_t tx_ipg_len;
-	uint32_t Reserved1[3];
-	/* [0x54] */
-	uint32_t cl01_pause_quanta;
-	uint32_t cl23_pause_quanta;
-	uint32_t cl45_pause_quanta;
-	/* [0x60] */
-	uint32_t cl67_pause_quanta;
-	uint32_t cl01_quanta_thresh;
-	uint32_t cl23_quanta_thresh;
-	uint32_t cl45_quanta_thresh;
-	/* [0x70] */
-	uint32_t cl67_quanta_thresh;
-	uint32_t rx_pause_status;
-	uint32_t Reserved2;
-	uint32_t ts_timestamp;
-	/* [0x80] */
-	union al_eth_mac_10g_stats stats;
-
-	/* [0x300] */
-	uint32_t control;
-	uint32_t status_reg;
-	uint32_t phy_id[2];
-	/* [0x310] */
-	uint32_t dev_ability;
-	uint32_t partner_ability;
-	uint32_t an_expansion;
-	uint32_t device_np;
-	/* [0x320] */
-	uint32_t partner_np;
-	uint32_t Reserved4[9];
-
-	/* [0x348] */
-	uint32_t link_timer_lo;
-	uint32_t link_timer_hi;
-	/* [0x350] */
-	uint32_t if_mode;
-
-	uint32_t Reserved5[43];
-};
-
-struct al_eth_mac_gen {
-	/* [0x0]  Ethernet Controller Version */
-	uint32_t version;
-	uint32_t rsrvd_0[2];
-	/* [0xc] MAC selection configuration */
-	uint32_t cfg;
-	/* [0x10] 10/100/1000 MAC external configuration */
-	uint32_t mac_1g_cfg;
-	/* [0x14] 10/100/1000 MAC status */
-	uint32_t mac_1g_stat;
-	/* [0x18] RGMII external configuration */
-	uint32_t rgmii_cfg;
-	/* [0x1c] RGMII status */
-	uint32_t rgmii_stat;
-	/* [0x20] 1/2.5/10G MAC external configuration */
-	uint32_t mac_10g_cfg;
-	/* [0x24] 1/2.5/10G MAC status */
-	uint32_t mac_10g_stat;
-	/* [0x28] XAUI PCS configuration */
-	uint32_t xaui_cfg;
-	/* [0x2c] XAUI PCS status */
-	uint32_t xaui_stat;
-	/* [0x30] RXAUI PCS configuration */
-	uint32_t rxaui_cfg;
-	/* [0x34] RXAUI PCS status */
-	uint32_t rxaui_stat;
-	/* [0x38] Signal detect configuration */
-	uint32_t sd_cfg;
-	/* [0x3c] MDIO control register for MDIO interface 1 */
-	uint32_t mdio_ctrl_1;
-	/* [0x40] MDIO information register for MDIO interface 1 */
-	uint32_t mdio_1;
-	/* [0x44] MDIO control register for MDIO interface 2 */
-	uint32_t mdio_ctrl_2;
-	/* [0x48] MDIO information register for MDIO interface 2 */
-	uint32_t mdio_2;
-	/* [0x4c] XGMII 32 to 64 data FIFO control */
-	uint32_t xgmii_dfifo_32_64;
-	/* [0x50] Reserved 1 out */
-	uint32_t mac_res_1_out;
-	/* [0x54] XGMII 64 to 32 data FIFO control */
-	uint32_t xgmii_dfifo_64_32;
-	/* [0x58] Reserved 1 in */
-	uint32_t mac_res_1_in;
-	/* [0x5c] SerDes TX FIFO control */
-	uint32_t sd_fifo_ctrl;
-	/* [0x60] SerDes TX FIFO status */
-	uint32_t sd_fifo_stat;
-	/* [0x64] SerDes in/out selection */
-	uint32_t mux_sel;
-	/* [0x68] Clock configuration */
-	uint32_t clk_cfg;
-	uint32_t rsrvd_1;
-	/* [0x70] LOS and SD selection */
-	uint32_t los_sel;
-	/* [0x74] RGMII selection configuration */
-	uint32_t rgmii_sel;
-	/* [0x78] Ethernet LED configuration */
-	uint32_t led_cfg;
-	uint32_t rsrvd[33];
-};
-struct al_eth_mac_kr {
-	/* [0x0] PCS register file address */
-	uint32_t pcs_addr;
-	/* [0x4] PCS register file data */
-	uint32_t pcs_data;
-	/* [0x8] AN register file address */
-	uint32_t an_addr;
-	/* [0xc] AN register file data */
-	uint32_t an_data;
-	/* [0x10] PMA register file address */
-	uint32_t pma_addr;
-	/* [0x14] PMA register file data */
-	uint32_t pma_data;
-	/* [0x18] MTIP register file address */
-	uint32_t mtip_addr;
-	/* [0x1c] MTIP register file data */
-	uint32_t mtip_data;
-	/* [0x20] KR PCS config  */
-	uint32_t pcs_cfg;
-	/* [0x24] KR PCS status  */
-	uint32_t pcs_stat;
-	uint32_t rsrvd[54];
-};
-struct al_eth_mac_sgmii {
-	/* [0x0] PCS register file address */
-	uint32_t reg_addr;
-	/* [0x4] PCS register file data */
-	uint32_t reg_data;
-	/* [0x8] PCS clock divider configuration */
-	uint32_t clk_div;
-	/* [0xc] PCS Status */
-	uint32_t link_stat;
-	uint32_t rsrvd[60];
-};
-struct al_eth_mac_stat {
-	/* [0x0] Receive rate matching error */
-	uint32_t match_fault;
-	/* [0x4] EEE, number of times the MAC went into low power mode */
-	uint32_t eee_in;
-	/* [0x8] EEE, number of times the MAC went out of low power mode */
-	uint32_t eee_out;
-	/*
-	 * [0xc] 40G PCS,
-	 * FEC corrected error indication
-	 */
-	uint32_t v3_pcs_40g_ll_cerr_0;
-	/*
-	 * [0x10] 40G PCS,
-	 * FEC corrected error indication
-	 */
-	uint32_t v3_pcs_40g_ll_cerr_1;
-	/*
-	 * [0x14] 40G PCS,
-	 * FEC corrected error indication
-	 */
-	uint32_t v3_pcs_40g_ll_cerr_2;
-	/*
-	 * [0x18] 40G PCS,
-	 * FEC corrected error indication
-	 */
-	uint32_t v3_pcs_40g_ll_cerr_3;
-	/*
-	 * [0x1c] 40G PCS,
-	 * FEC uncorrectable error indication
-	 */
-	uint32_t v3_pcs_40g_ll_ncerr_0;
-	/*
-	 * [0x20] 40G PCS,
-	 * FEC uncorrectable error indication
-	 */
-	uint32_t v3_pcs_40g_ll_ncerr_1;
-	/*
-	 * [0x24] 40G PCS,
-	 * FEC uncorrectable error indication
-	 */
-	uint32_t v3_pcs_40g_ll_ncerr_2;
-	/*
-	 * [0x28] 40G PCS,
-	 * FEC uncorrectable error indication
-	 */
-	uint32_t v3_pcs_40g_ll_ncerr_3;
-	/*
-	 * [0x2c] 10G_LL PCS,
-	 * FEC corrected error indication
-	 */
-	uint32_t v3_pcs_10g_ll_cerr;
-	/*
-	 * [0x30] 10G_LL PCS,
-	 * FEC uncorrectable error indication
-	 */
-	uint32_t v3_pcs_10g_ll_ncerr;
-	uint32_t rsrvd[51];
-};
-struct al_eth_mac_stat_lane {
-	/* [0x0] Character error */
-	uint32_t char_err;
-	/* [0x4] Disparity error */
-	uint32_t disp_err;
-	/* [0x8] Comma detection */
-	uint32_t pat;
-	uint32_t rsrvd[13];
-};
-struct al_eth_mac_gen_v3 {
-	/* [0x0] ASYNC FIFOs control */
-	uint32_t afifo_ctrl;
-	/* [0x4] TX ASYNC FIFO configuration */
-	uint32_t tx_afifo_cfg_1;
-	/* [0x8] TX ASYNC FIFO configuration */
-	uint32_t tx_afifo_cfg_2;
-	/* [0xc] TX ASYNC FIFO configuration */
-	uint32_t tx_afifo_cfg_3;
-	/* [0x10] TX ASYNC FIFO configuration */
-	uint32_t tx_afifo_cfg_4;
-	/* [0x14] TX ASYNC FIFO configuration */
-	uint32_t tx_afifo_cfg_5;
-	/* [0x18] RX ASYNC FIFO configuration */
-	uint32_t rx_afifo_cfg_1;
-	/* [0x1c] RX ASYNC FIFO configuration */
-	uint32_t rx_afifo_cfg_2;
-	/* [0x20] RX ASYNC FIFO configuration */
-	uint32_t rx_afifo_cfg_3;
-	/* [0x24] RX ASYNC FIFO configuration */
-	uint32_t rx_afifo_cfg_4;
-	/* [0x28] RX ASYNC FIFO configuration */
-	uint32_t rx_afifo_cfg_5;
-	/* [0x2c] MAC selection configuration */
-	uint32_t mac_sel;
-	/* [0x30] 10G LL MAC configuration */
-	uint32_t mac_10g_ll_cfg;
-	/* [0x34] 10G LL MAC control */
-	uint32_t mac_10g_ll_ctrl;
-	/* [0x38] 10G LL PCS configuration */
-	uint32_t pcs_10g_ll_cfg;
-	/* [0x3c] 10G LL PCS status */
-	uint32_t pcs_10g_ll_status;
-	/* [0x40] 40G LL PCS configuration */
-	uint32_t pcs_40g_ll_cfg;
-	/* [0x44] 40G LL PCS status */
-	uint32_t pcs_40g_ll_status;
-	/* [0x48] PCS 40G  register file address */
-	uint32_t pcs_40g_ll_addr;
-	/* [0x4c] PCS 40G register file data */
-	uint32_t pcs_40g_ll_data;
-	/* [0x50] 40G LL MAC configuration */
-	uint32_t mac_40g_ll_cfg;
-	/* [0x54] 40G LL MAC status */
-	uint32_t mac_40g_ll_status;
-	/* [0x58] Preamble configuration (high [55:32]) */
-	uint32_t preamble_cfg_high;
-	/* [0x5c] Preamble configuration (low [31:0]) */
-	uint32_t preamble_cfg_low;
-	/* [0x60] MAC 40G register file address */
-	uint32_t mac_40g_ll_addr;
-	/* [0x64] MAC 40G register file data */
-	uint32_t mac_40g_ll_data;
-	/* [0x68] 40G LL MAC control */
-	uint32_t mac_40g_ll_ctrl;
-	/* [0x6c] PCS 40G  register file address */
-	uint32_t pcs_40g_fec_91_ll_addr;
-	/* [0x70] PCS 40G register file data */
-	uint32_t pcs_40g_fec_91_ll_data;
-	/* [0x74] 40G LL PCS EEE configuration */
-	uint32_t pcs_40g_ll_eee_cfg;
-	/* [0x78] 40G LL PCS EEE status */
-	uint32_t pcs_40g_ll_eee_status;
-	/*
-	 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
-	 * enabled)
-	 */
-	uint32_t serdes_32_tx_shift;
-	/*
-	 * [0x80] SERDES 32-bit interface shift configuration (when swap is
-	 * enabled)
-	 */
-	uint32_t serdes_32_rx_shift;
-	/*
-	 * [0x84] SERDES 32-bit interface bit selection
-	 */
-	uint32_t serdes_32_tx_sel;
-	/*
-	 * [0x88] SERDES 32-bit interface bit selection
-	 */
-	uint32_t serdes_32_rx_sel;
-	/* [0x8c] AN/LT wrapper  control */
-	uint32_t an_lt_ctrl;
-	/* [0x90] AN/LT wrapper  register file address */
-	uint32_t an_lt_0_addr;
-	/* [0x94] AN/LT wrapper register file data */
-	uint32_t an_lt_0_data;
-	/* [0x98] AN/LT wrapper  register file address */
-	uint32_t an_lt_1_addr;
-	/* [0x9c] AN/LT wrapper register file data */
-	uint32_t an_lt_1_data;
-	/* [0xa0] AN/LT wrapper  register file address */
-	uint32_t an_lt_2_addr;
-	/* [0xa4] AN/LT wrapper register file data */
-	uint32_t an_lt_2_data;
-	/* [0xa8] AN/LT wrapper  register file address */
-	uint32_t an_lt_3_addr;
-	/* [0xac] AN/LT wrapper register file data */
-	uint32_t an_lt_3_data;
-	/* [0xb0] External SERDES control */
-	uint32_t ext_serdes_ctrl;
-	/* [0xb4] spare bits */
-	uint32_t spare;
-	uint32_t rsrvd[18];
-};
-
-struct al_eth_mac_regs {
-	struct al_eth_mac_1g mac_1g;				/* [0x000] */
-	struct al_eth_mac_10g mac_10g;				/* [0x400] */
-	uint32_t rsrvd_0[64];					/* [0x800] */
-	struct al_eth_mac_gen gen;                              /* [0x900] */
-	struct al_eth_mac_kr kr;                                /* [0xa00] */
-	struct al_eth_mac_sgmii sgmii;                          /* [0xb00] */
-	struct al_eth_mac_stat stat;                            /* [0xc00] */
-	struct al_eth_mac_stat_lane stat_lane[4];               /* [0xd00] */
-	struct al_eth_mac_gen_v3 gen_v3;                        /* [0xe00] */
-};
-
-
-/*
-* Registers Fields
-*/
-
-/**** 1G MAC registers ****/
-/* cmd_cfg */
-#define ETH_1G_MAC_CMD_CFG_TX_ENA	(1 << 0)
-#define ETH_1G_MAC_CMD_CFG_RX_ENA	(1 << 1)
-/* enable Half Duplex */
-#define ETH_1G_MAC_CMD_CFG_HD_EN	(1 << 10)
-/* enable 1G speed */
-#define ETH_1G_MAC_CMD_CFG_1G_SPD	(1 << 3)
-/* enable 10M speed */
-#define ETH_1G_MAC_CMD_CFG_10M_SPD	(1 << 25)
-
-/**** 10G MAC registers ****/
-/* cmd_cfg */
-#define ETH_10G_MAC_CMD_CFG_TX_ENA				(1 << 0)
-#define ETH_10G_MAC_CMD_CFG_RX_ENA				(1 << 1)
-#define ETH_10G_MAC_CMD_CFG_WAN_MODE			(1 << 3)
-#define ETH_10G_MAC_CMD_CFG_PROMIS_EN			(1 << 4)
-#define ETH_10G_MAC_CMD_CFG_PAD_EN				(1 << 5)
-#define ETH_10G_MAC_CMD_CFG_CRC_FWD				(1 << 6)
-#define ETH_10G_MAC_CMD_CFG_PAUSE_FWD			(1 << 7)
-#define ETH_10G_MAC_CMD_CFG_PAUSE_IGNORE		(1 << 8)
-#define ETH_10G_MAC_CMD_CFG_TX_ADDR_INS			(1 << 9)
-#define ETH_10G_MAC_CMD_CFG_LOOP_ENA			(1 << 10)
-#define ETH_10G_MAC_CMD_CFG_TX_PAD_EN			(1 << 11)
-#define ETH_10G_MAC_CMD_CFG_SW_RESET			(1 << 12)
-#define ETH_10G_MAC_CMD_CFG_CNTL_FRM_ENA		(1 << 13)
-#define ETH_10G_MAC_CMD_CFG_RX_ERR_DISC			(1 << 14)
-#define ETH_10G_MAC_CMD_CFG_PHY_TXENA			(1 << 15)
-#define ETH_10G_MAC_CMD_CFG_FORCE_SEND_IDLE		(1 << 16)
-#define ETH_10G_MAC_CMD_CFG_NO_LGTH_CHECK		(1 << 17)
-#define ETH_10G_MAC_CMD_CFG_COL_CNT_EXT			(1 << 18)
-#define ETH_10G_MAC_CMD_CFG_PFC_MODE			(1 << 19)
-#define ETH_10G_MAC_CMD_CFG_PAUSE_PFC_COMP		(1 << 20)
-#define ETH_10G_MAC_CMD_CFG_SFD_ANY				(1 << 21)
-#define ETH_10G_MAC_CMD_CFG_TX_FLUSH			(1 << 22)
-#define ETH_10G_MAC_CMD_CFG_TX_LOWP_ENA			(1 << 23)
-#define ETH_10G_MAC_CMD_CFG_REG_LOWP_RXEMPTY	(1 << 24)
-#define ETH_10G_MAC_CMD_CFG_SHORT_DISCARD		(1 << 25)
-
-/* mdio_cfg_status */
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK	0x0000001c
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_SHIFT	2
-
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_1_CLK	0
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_3_CLK	1
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_5_CLK	2
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_7_CLK	3
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_9_CLK	4
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_11_CLK	5
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_13_CLK	6
-#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_15_CLK	7
-
-/* control */
-#define ETH_10G_MAC_CONTROL_AN_EN_MASK	0x00001000
-#define ETH_10G_MAC_CONTROL_AN_EN_SHIFT	12
-
-/* if_mode */
-#define ETH_10G_MAC_IF_MODE_SGMII_EN_MASK	0x00000001
-#define ETH_10G_MAC_IF_MODE_SGMII_EN_SHIFT	0
-#define ETH_10G_MAC_IF_MODE_SGMII_AN_MASK	0x00000002
-#define ETH_10G_MAC_IF_MODE_SGMII_AN_SHIFT	1
-#define ETH_10G_MAC_IF_MODE_SGMII_SPEED_MASK	0x0000000c
-#define ETH_10G_MAC_IF_MODE_SGMII_SPEED_SHIFT	2
-#define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_MASK	0x00000010
-#define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_SHIFT	4
-
-#define ETH_10G_MAC_IF_MODE_SGMII_SPEED_10M	0
-#define ETH_10G_MAC_IF_MODE_SGMII_SPEED_100M	1
-#define ETH_10G_MAC_IF_MODE_SGMII_SPEED_1G	2
-
-#define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_FULL	0
-#define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_HALF	1
-
-/**** version register ****/
-/*  Revision number (Minor) */
-#define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
-#define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
-/*  Revision number (Major) */
-#define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
-#define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
-/*  Date of release */
-#define ETH_MAC_GEN_VERSION_DATE_DAY_MASK 0x001F0000
-#define ETH_MAC_GEN_VERSION_DATE_DAY_SHIFT 16
-/*  Month of release */
-#define ETH_MAC_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
-#define ETH_MAC_GEN_VERSION_DATA_MONTH_SHIFT 21
-/*  Year of release (starting from 2000) */
-#define ETH_MAC_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
-#define ETH_MAC_GEN_VERSION_DATE_YEAR_SHIFT 25
-/*  Reserved */
-#define ETH_MAC_GEN_VERSION_RESERVED_MASK 0xC0000000
-#define ETH_MAC_GEN_VERSION_RESERVED_SHIFT 30
-
-/**** cfg register ****/
-/*
- * Selects between the 10/100/1000 MAC and the 1/2.5/10G MAC:
- * 0 - 10/100/1000
- * 1 - 1/2.5/10G
- */
-#define ETH_MAC_GEN_CFG_MAC_1_10         (1 << 0)
-/*
- * Selects the operation mode of the 1/2.5/10G MAC:
- * 00 - 1/2.5G SGMII
- * 01 - 10G XAUI/RXAUI
- * 10 – 10G KR
- * 11 – Reserved
- */
-#define ETH_MAC_GEN_CFG_XGMII_SGMII_MASK 0x00000006
-#define ETH_MAC_GEN_CFG_XGMII_SGMII_SHIFT 1
-/*
- * Selects the operation mode of the PCS:
- * 0 - XAUI
- * 1 - RXAUI
- */
-#define ETH_MAC_GEN_CFG_XAUI_RXAUI       (1 << 3)
-/* Swap bits of TBI (SGMII mode) interface */
-#define ETH_MAC_GEN_CFG_SWAP_TBI_RX      (1 << 4)
-/*
- * Determines the offset of the TBI bus on the SerDes interface:
- * 0 - LSB
- * 1 - MSB
- */
-#define ETH_MAC_GEN_CFG_TBI_MSB_RX       (1 << 5)
-/*
- * Selects the SGMII PCS/MAC:
- * 0 – 10G MAC with SGMII
- * 1 – 1G MAC with SGMII
- */
-#define ETH_MAC_GEN_CFG_SGMII_SEL        (1 << 6)
-/*
- * Selects between RGMII and SGMII for the 1G MAC:
- * 0 – RGMII
- * 1 – SGMII
- */
-#define ETH_MAC_GEN_CFG_RGMII_SGMII_SEL  (1 << 7)
-/* Swap bits of TBI (SGMII mode) interface */
-#define ETH_MAC_GEN_CFG_SWAP_TBI_TX      (1 << 8)
-/*
- * Determines the offset of the TBI bus on the SerDes interface:
- *  0 - LSB
- * 1 - MSB
- */
-#define ETH_MAC_GEN_CFG_TBI_MSB_TX       (1 << 9)
-/*
- * Selection between the MDIO from 10/100/1000 MAC or the 1/2.5/10G MAC
- * 0 - 10/100/1000
- * 1 - 1/2.5/10G
- */
-#define ETH_MAC_GEN_CFG_MDIO_1_10        (1 << 10)
-/*
- * Swap MDC output
- * 0 – Normal
- * 1 – Flipped
- */
-#define ETH_MAC_GEN_CFG_MDIO_POL         (1 << 11)
-/* Swap bits on SerDes interface */
-#define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_MASK 0x000F0000
-#define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_SHIFT 16
-/* Swap bits on SerDes interface */
-#define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_MASK 0x0F000000
-#define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_SHIFT 24
-
-/**** mac_1g_cfg register ****/
-/*
- * Selection of the input for the "set_1000" input of the Ethernet 10/100/1000
- * MAC:
- * 0 - From RGMII converter (automatic speed selection)
- * 1 - From register set_1000_def
- */
-#define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_SEL (1 << 0)
-/* Default value for the 10/100/1000 MAC "set_1000" input */
-#define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_DEF (1 << 1)
-/*
- * Selection of the input for the "set_10" input of the Ethernet 10/100/1000
- * MAC:
- * 0 - From RGMII converter (automatic speed selection)
- * 1 - From register set_10_def
- */
-#define ETH_MAC_GEN_MAC_1G_CFG_SET_10_SEL (1 << 4)
-/* Default value for the 10/100/1000 MAC "set_10" input */
-#define ETH_MAC_GEN_MAC_1G_CFG_SET_10_DEF (1 << 5)
-/* Transmit low power enable */
-#define ETH_MAC_GEN_MAC_1G_CFG_LOWP_ENA  (1 << 8)
-/*
- * Enable magic packet mode:
- * 0 - Sleep mode
- * 1 - Normal operation
- */
-#define ETH_MAC_GEN_MAC_1G_CFG_SLEEPN    (1 << 9)
-/* Swap ff_tx_crc input */
-#define ETH_MAC_GEN_MAC_1G_CFG_SWAP_FF_TX_CRC (1 << 12)
-
-/**** mac_1g_stat register ****/
-/* Status of the en_10 output form the 10/100/1000 MAC */
-#define ETH_MAC_GEN_MAC_1G_STAT_EN_10    (1 << 0)
-/* Status of the eth_mode output from th 10/100/1000 MAC */
-#define ETH_MAC_GEN_MAC_1G_STAT_ETH_MODE (1 << 1)
-/* Status of the lowp output from the 10/100/1000 MAC */
-#define ETH_MAC_GEN_MAC_1G_STAT_LOWP     (1 << 4)
-/* Status of the wakeup output from the 10/100/1000 MAC */
-#define ETH_MAC_GEN_MAC_1G_STAT_WAKEUP   (1 << 5)
-
-/**** rgmii_cfg register ****/
-/*
- * Selection of the input for the "set_1000" input of the RGMII converter
- * 0 - From MAC
- * 1 - From register set_1000_def (automatic speed selection)
- */
-#define ETH_MAC_GEN_RGMII_CFG_SET_1000_SEL (1 << 0)
-/* Default value for the RGMII converter "set_1000" input */
-#define ETH_MAC_GEN_RGMII_CFG_SET_1000_DEF (1 << 1)
-/*
- * Selection of the input for the "set_10" input of the RGMII converter:
- * 0 - From MAC
- * 1 - From register set_10_def (automatic speed selection)
- */
-#define ETH_MAC_GEN_RGMII_CFG_SET_10_SEL (1 << 4)
-/* Default value for the 10/100/1000 MAC "set_10" input  */
-#define ETH_MAC_GEN_RGMII_CFG_SET_10_DEF (1 << 5)
-/* Enable automatic speed selection (based on PHY in-band status information) */
-#define ETH_MAC_GEN_RGMII_CFG_ENA_AUTO   (1 << 8)
-/* Force full duplex, only valid when ena_auto is '1'. */
-#define ETH_MAC_GEN_RGMII_CFG_SET_FD     (1 << 9)
-
-/**** rgmii_stat register ****/
-/*
- * Status of the speed output form the RGMII converter
- * 00 - 10 Mbps
- * 01 - 100 Mbps
- * 10 - 1000 Mbps
- * 11 - Reserved
- */
-#define ETH_MAC_GEN_RGMII_STAT_SPEED_MASK 0x00000003
-#define ETH_MAC_GEN_RGMII_STAT_SPEED_SHIFT 0
-/*
- * Link indication from the RGMII converter (valid only if the external PHY
- * supports in-band status signaling)
- */
-#define ETH_MAC_GEN_RGMII_STAT_LINK      (1 << 4)
-/*
- * Full duplex indication from the RGMII converter (valid only if the external
- * PHY supports in-band status signaling)
- */
-#define ETH_MAC_GEN_RGMII_STAT_DUP       (1 << 5)
-
-/**** mac_10g_cfg register ****/
-/* Instruct the XGMII to transmit local fault. */
-#define ETH_MAC_GEN_MAC_10G_CFG_TX_LOC_FAULT (1 << 0)
-/* Instruct the XGMII to transmit remote fault. */
-#define ETH_MAC_GEN_MAC_10G_CFG_TX_REM_FAULT (1 << 1)
-/* Instruct the XGMII to transmit link fault. */
-#define ETH_MAC_GEN_MAC_10G_CFG_TX_LI_FAULT (1 << 2)
-/*
- * Synchronous reset for the PCS layer. Can be used after SerDes lock assertion
- * to reset the PCS state machine.
- */
-#define ETH_MAC_GEN_MAC_10G_CFG_SG_SRESET (1 << 3)
-/*
- * PHY LOS indication selection
- * 00 - Select register value from phy_los_def
- * 01 - Select input from the SerDes
- * 10 - Select input from GPIO
- * 11 - Select inverted input from GPIO
- */
-#define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_MASK 0x00000030
-#define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_SHIFT 4
-/*
- * Default value for PHY LOS indication. Reflects the LOS indication from the
- * SerDes. ('0' if not used)
- */
-#define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_DEF (1 << 6)
-/* Reverse polarity of the LOS signal from the SerDes */
-#define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_POL (1 << 7)
-/* Transmit low power enable */
-#define ETH_MAC_GEN_MAC_10G_CFG_LOWP_ENA (1 << 8)
-/* Swap ff_tx_crc input */
-#define ETH_MAC_GEN_MAC_10G_CFG_SWAP_FF_TX_CRC (1 << 12)
-
-/**** mac_10g_stat register ****/
-/* XGMII RS detects local fault */
-#define ETH_MAC_GEN_MAC_10G_STAT_LOC_FAULT (1 << 0)
-/* XGMII RS detects remote fault */
-#define ETH_MAC_GEN_MAC_10G_STAT_REM_FAULT (1 << 1)
-/* XGMII RS detects link fault */
-#define ETH_MAC_GEN_MAC_10G_STAT_LI_FAULT (1 << 2)
-/* PFC mode */
-#define ETH_MAC_GEN_MAC_10G_STAT_PFC_MODE (1 << 3)
-
-#define ETH_MAC_GEN_MAC_10G_STAT_SG_ENA  (1 << 4)
-
-#define ETH_MAC_GEN_MAC_10G_STAT_SG_ANDONE (1 << 5)
-
-#define ETH_MAC_GEN_MAC_10G_STAT_SG_SYNC (1 << 6)
-
-#define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_MASK 0x00000180
-#define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_SHIFT 7
-/* Status of the lowp output form the 1/2.5/10G MAC */
-#define ETH_MAC_GEN_MAC_10G_STAT_LOWP    (1 << 9)
-/* Status of the ts_avail output from th 1/2.5/10G MAC */
-#define ETH_MAC_GEN_MAC_10G_STAT_TS_AVAIL (1 << 10)
-/* Transmit pause indication */
-#define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_MASK 0xFF000000
-#define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_SHIFT 24
-
-/**** xaui_cfg register ****/
-/* Increase rate matching FIFO threshold */
-#define ETH_MAC_GEN_XAUI_CFG_JUMBO_EN    (1 << 0)
-
-/**** xaui_stat register ****/
-/* Lane alignment status */
-#define ETH_MAC_GEN_XAUI_STAT_ALIGN_DONE (1 << 0)
-/* Lane synchronization */
-#define ETH_MAC_GEN_XAUI_STAT_SYNC_MASK  0x000000F0
-#define ETH_MAC_GEN_XAUI_STAT_SYNC_SHIFT 4
-/* Code group alignment indication */
-#define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_MASK 0x00000F00
-#define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_SHIFT 8
-
-/**** rxaui_cfg register ****/
-/* Increase rate matching FIFO threshold */
-#define ETH_MAC_GEN_RXAUI_CFG_JUMBO_EN   (1 << 0)
-/* Scrambler enable */
-#define ETH_MAC_GEN_RXAUI_CFG_SRBL_EN    (1 << 1)
-/* Disparity calculation across lanes enabled */
-#define ETH_MAC_GEN_RXAUI_CFG_DISP_ACROSS_LANE (1 << 2)
-
-/**** rxaui_stat register ****/
-/* Lane alignment status */
-#define ETH_MAC_GEN_RXAUI_STAT_ALIGN_DONE (1 << 0)
-/* Lane synchronization */
-#define ETH_MAC_GEN_RXAUI_STAT_SYNC_MASK 0x000000F0
-#define ETH_MAC_GEN_RXAUI_STAT_SYNC_SHIFT 4
-/* Code group alignment indication */
-#define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_MASK 0x00000F00
-#define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_SHIFT 8
-
-/**** sd_cfg register ****/
-/*
- * Signal detect selection
- * 0 - from register
- * 1 - from SerDes
- */
-#define ETH_MAC_GEN_SD_CFG_SEL_MASK      0x0000000F
-#define ETH_MAC_GEN_SD_CFG_SEL_SHIFT     0
-/* Signal detect value */
-#define ETH_MAC_GEN_SD_CFG_VAL_MASK      0x000000F0
-#define ETH_MAC_GEN_SD_CFG_VAL_SHIFT     4
-/* Signal detect revers polarity (reverse polarity of signal from the SerDes */
-#define ETH_MAC_GEN_SD_CFG_POL_MASK      0x00000F00
-#define ETH_MAC_GEN_SD_CFG_POL_SHIFT     8
-
-/**** mdio_ctrl_1 register ****/
-/*
- * Available indication
- * 0 - The port was available and it is captured by this Ethernet controller.
- * 1 - The port is used by another Ethernet controller.
- */
-#define ETH_MAC_GEN_MDIO_CTRL_1_AVAIL    (1 << 0)
-
-/**** mdio_1 register ****/
-/* Current Ethernet interface number that controls the MDIO port */
-#define ETH_MAC_GEN_MDIO_1_INFO_MASK     0x000000FF
-#define ETH_MAC_GEN_MDIO_1_INFO_SHIFT    0
-
-/**** mdio_ctrl_2 register ****/
-/*
- * Available indication
- * 0 - The port was available and it is captured by this Ethernet controller.
- * 1 - The port is used by another Ethernet controller.
- */
-#define ETH_MAC_GEN_MDIO_CTRL_2_AVAIL    (1 << 0)
-
-/**** mdio_2 register ****/
-/* Current Ethernet interface number that controls the MDIO port */
-#define ETH_MAC_GEN_MDIO_2_INFO_MASK     0x000000FF
-#define ETH_MAC_GEN_MDIO_2_INFO_SHIFT    0
-
-/**** xgmii_dfifo_32_64 register ****/
-/* FIFO enable */
-#define ETH_MAC_GEN_XGMII_DFIFO_32_64_ENABLE (1 << 0)
-/* Read Write command every 2 cycles */
-#define ETH_MAC_GEN_XGMII_DFIFO_32_64_RW_2_CYCLES (1 << 1)
-/* Swap LSB MSB when creating wider bus */
-#define ETH_MAC_GEN_XGMII_DFIFO_32_64_SWAP_LSB_MSB (1 << 2)
-/* Software reset */
-#define ETH_MAC_GEN_XGMII_DFIFO_32_64_SW_RESET (1 << 4)
-/* Read threshold */
-#define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_MASK 0x0000FF00
-#define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_SHIFT 8
-/* FIFO used */
-#define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_MASK 0x00FF0000
-#define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_SHIFT 16
-
-/**** xgmii_dfifo_64_32 register ****/
-/* FIFO enable */
-#define ETH_MAC_GEN_XGMII_DFIFO_64_32_ENABLE (1 << 0)
-/* Read Write command every 2 cycles */
-#define ETH_MAC_GEN_XGMII_DFIFO_64_32_RW_2_CYCLES (1 << 1)
-/* Swap LSB MSB when creating wider bus */
-#define ETH_MAC_GEN_XGMII_DFIFO_64_32_SWAP_LSB_MSB (1 << 2)
-/* Software reset */
-#define ETH_MAC_GEN_XGMII_DFIFO_64_32_SW_RESET (1 << 4)
-/* Read threshold */
-#define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_MASK 0x0000FF00
-#define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_SHIFT 8
-/* FIFO used */
-#define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_MASK 0x00FF0000
-#define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_SHIFT 16
-
-/**** sd_fifo_ctrl register ****/
-/* FIFO enable */
-#define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_MASK 0x0000000F
-#define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_SHIFT 0
-/* Software reset */
-#define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_MASK 0x000000F0
-#define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_SHIFT 4
-/* Read threshold */
-#define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_MASK 0x0000FF00
-#define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_SHIFT 8
-
-/**** sd_fifo_stat register ****/
-/* FIFO 0 used */
-#define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_MASK 0x000000FF
-#define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_SHIFT 0
-/* FIFO 1 used */
-#define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_MASK 0x0000FF00
-#define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_SHIFT 8
-/* FIFO 2 used */
-#define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_MASK 0x00FF0000
-#define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_SHIFT 16
-/* FIFO 3 used */
-#define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_MASK 0xFF000000
-#define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_SHIFT 24
-
-/**** mux_sel register ****/
-/*
- * SGMII input selection selector
- * 00 – SerDes 0
- * 01 – SerDes 1
- * 10 – SerDes 2
- * 11 – SerDes 3
- */
-#define ETH_MAC_GEN_MUX_SEL_SGMII_IN_MASK 0x00000003
-#define ETH_MAC_GEN_MUX_SEL_SGMII_IN_SHIFT 0
-/*
- * RXAUI Lane 0 Input
- * 00 – SerDes 0
- * 01 – SerDes 1
- * 10 – SerDes 2
- * 11 – SerDes 3
- */
-#define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_MASK 0x0000000C
-#define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_SHIFT 2
-/*
- * RXAUI Lane 1 Input
- * 00 – SERDES 0
- * 01 – SERDES 1
- * 10 – SERDES 2
- * 11 – SERDES 3
- */
-#define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_MASK 0x00000030
-#define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_SHIFT 4
-/*
- * XAUI Lane 0 Input
- * 00 – SERDES 0
- * 01 – SERDES 1
- * 10 – SERDES 2
- * 11 – SERDES 3
- */
-#define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_MASK 0x000000C0
-#define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_SHIFT 6
-/*
- * XAUI Lane 1 Input
- * 00 – SERDES 0
- * 01 – SERDES 1
- * 10 – SERDES 2
- * 11 – SERDES 3
- */
-#define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_MASK 0x00000300
-#define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_SHIFT 8
-/*
- * XAUI Lane 2 Input
- * 00 – SERDES 0
- * 01 – SERDES 1
- * 10 – SERDES 2
- * 11 – SERDES 3
- */
-#define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_MASK 0x00000C00
-#define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_SHIFT 10
-/*
- * XAUI Lane 3 Input
- * 00 – SERDES 0
- * 01 – SERDES 1
- * 10 – SERDES 2
- * 11 – SERDES 3
- */
-#define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_MASK 0x00003000
-#define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_SHIFT 12
-/*
- * KR PCS Input
- * 00 - SERDES 0
- * 01 - SERDES 1
- * 10 - SERDES 2
- * 11 - SERDES 3
- */
-#define ETH_MAC_GEN_MUX_SEL_KR_IN_MASK   0x0000C000
-#define ETH_MAC_GEN_MUX_SEL_KR_IN_SHIFT  14
-/*
- * SerDes 0 input selection (TX)
- * 000 – XAUI lane 0
- * 001 – XAUI lane 1
- * 010 – XAUI lane 2
- * 011 – XAUI lane 3
- * 100 – RXAUI lane 0
- * 101 – RXAUI lane 1
- * 110 – SGMII
- * 111 – KR
- */
-#define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_MASK 0x00070000
-#define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_SHIFT 16
-/*
- * SERDES 1 input selection (Tx)
- * 000 – XAUI lane 0
- * 001 – XAUI lane 1
- * 010 – XAUI lane 2
- * 011 – XAUI lane 3
- * 100 – RXAUI lane 0
- * 101 – RXAUI lane 1
- * 110 – SGMII
- * 111 – KR
- */
-#define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_MASK 0x00380000
-#define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_SHIFT 19
-/*
- * SerDes 2 input selection (Tx)
- * 000 – XAUI lane 0
- * 001 – XAUI lane 1
- * 010 – XAUI lane 2
- * 011 – XAUI lane 3
- * 100 – RXAUI lane 0
- * 101 – RXAUI lane 1
- * 110 – SGMII
- * 111 – KR
- */
-#define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_MASK 0x01C00000
-#define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_SHIFT 22
-/*
- * SerDes 3 input selection (Tx)
- * 000 – XAUI lane 0
- * 001 – XAUI lane 1
- * 010 – XAUI lane 2
- * 011 – XAUI lane 3
- * 100 – RXAUI lane 0
- * 101 – RXAUI lane 1
- * 110 – SGMII
- * 111 – KR
- */
-#define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_MASK 0x0E000000
-#define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_SHIFT 25
-
-/**** clk_cfg register ****/
-/*
- * Rx/Tx lane 0 clock MUX select
- * must be aligned with data selector MUXs)
- * 0 – SerDes 0 clock
- * 0 – SerDes 1 clock
- * 2 – SerDes 2 clock
- * 3 – SerDes 3 clock
- */
-#define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_MASK 0x00000003
-#define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_SHIFT 0
-/*
- * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs)
- * 0 - SerDes 0 clock
- * 1 - SerDes 1 clock
- * 2 - SerDes 2 clock
- * 3 - SerDes 3 clock
- */
-#define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_MASK 0x00000030
-#define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_SHIFT 4
-/*
- * RX/TX lane 0 clock MUX select (should be aligned with data selector MUXs)
- * 0 - SERDES 0 clock
- * 1 - SERDES 1 clock
- * 2 - SERDES 2 clock
- * 3 - SERDES 3 clock
- */
-#define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_MASK 0x00000300
-#define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_SHIFT 8
-/*
- * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs)
- * 0 - SerDes 0 clock
- * 1 - SerDes 1 clock
- * 2 - SerDes 2 clock
- * 3 - SerDes 3 clock
- */
-#define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_MASK 0x00003000
-#define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_SHIFT 12
-/*
- * MAC GMII Rx clock MUX select must be aligned with data selector MUXs)
- * 0 – RGMII
- * 1 – SGMII
- */
-#define ETH_MAC_GEN_CLK_CFG_GMII_RX_CLK_SEL (1 << 16)
-/*
- * MAC GMII Tx clock MUX select (should be aligned with data selector MUXs)
- * 0 - RGMII
- * 1 - SGMII
- */
-#define ETH_MAC_GEN_CLK_CFG_GMII_TX_CLK_SEL (1 << 18)
-/*
- * Tx clock MUX select,
- * Selects the internal clock for the Tx data path
- * 0 – SerDes[0] TX DWORD CLK REF (for RXAUI and SGMII)
- * 1 – SerDes[0] TX WORD CLK REF (for XAUI and KR)
- */
-#define ETH_MAC_GEN_CLK_CFG_TX_CLK_SEL   (1 << 28)
-/*
- * Rxclock MUX select
- * Selects the internal clock for the Rx data path
- * 0 – XGMII TX CLK 32 LOCAL (for XAUI and RXAUI and KR)
- * 1 – SerDes[0] RX DWORD CLK GENERATED (125M)
- * (for SGMII)
- */
-#define ETH_MAC_GEN_CLK_CFG_RX_CLK_SEL   (1 << 30)
-
-/**** los_sel register ****/
-/*
- * Selected LOS/SD select
- * 00 – SerDes 0
- * 01 – SerDes 1
- * 10 – SerDes 2
- * 11 – SerDes 3
- */
-#define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_MASK 0x00000003
-#define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_SHIFT 0
-/*
- * Selected LOS/SD select
- * 00 - SerDes 0
- * 01 - SerDes 1
- * 10 - SerDes 2
- * 11 - SerDes 3
- */
-#define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_MASK 0x00000030
-#define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_SHIFT 4
-/*
- * Selected LOS/SD select
- * 00 - SerDes 0
- * 01 - SerDes 1
- * 10 - SerDes 2
- * 11 - SerDes 3
- */
-#define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_MASK 0x00000300
-#define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_SHIFT 8
-/*
- * Selected LOS/SD select
- * 00 - SerDes 0
- * 01 - SerDes 1
- * 10 - SerDes 2
- * 11 - SerDes 3
- */
-#define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_MASK 0x00003000
-#define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_SHIFT 12
-
-/**** rgmii_sel register ****/
-/* Swap [3:0] input with [7:4] */
-#define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_3_0 (1 << 0)
-/* Swap [4] input with [9] */
-#define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_4  (1 << 1)
-/* Swap [7:4] input with [3:0] */
-#define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_7_3 (1 << 2)
-/* Swap [9] input with [4] */
-#define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_9  (1 << 3)
-/* Swap [3:0] input with [7:4] */
-#define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_3_0 (1 << 4)
-/* Swap [4] input with [9] */
-#define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_4  (1 << 5)
-/* Swap [7:4] input with [3:0] */
-#define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_7_3 (1 << 6)
-/* Swap [9] input with [4] */
-#define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_9  (1 << 7)
-
-/**** led_cfg register ****/
-/*
- * LED source selection:
- * 0 – Default reg
- * 1 – Rx activity
- * 2 – Tx activity
- * 3 – Rx | Tx activity
- * 4-9 – SGMII LEDs
- */
-#define ETH_MAC_GEN_LED_CFG_SEL_MASK     0x0000000F
-#define ETH_MAC_GEN_LED_CFG_SEL_SHIFT    0
-
-/* turn the led on/off based on default value field (ETH_MAC_GEN_LED_CFG_DEF) */
-#define ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG	0
-#define ETH_MAC_GEN_LED_CFG_SEL_RX_ACTIVITY_DEPRECIATED	1
-#define ETH_MAC_GEN_LED_CFG_SEL_TX_ACTIVITY_DEPRECIATED	2
-#define ETH_MAC_GEN_LED_CFG_SEL_RX_TX_ACTIVITY_DEPRECIATED 3
-#define ETH_MAC_GEN_LED_CFG_SEL_LINK_ACTIVITY 10
-
-/* LED default value */
-#define ETH_MAC_GEN_LED_CFG_DEF          (1 << 4)
-/* LED signal polarity */
-#define ETH_MAC_GEN_LED_CFG_POL          (1 << 5)
-/*
- * activity timer (MSB)
- * 32 bit timer @SB clock
- */
-#define ETH_MAC_GEN_LED_CFG_ACT_TIMER_MASK 0x00FF0000
-#define ETH_MAC_GEN_LED_CFG_ACT_TIMER_SHIFT 16
-/*
- * activity timer (MSB)
- * 32 bit timer @SB clock
- */
-#define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_MASK 0xFF000000
-#define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_SHIFT 24
-
-/**** pcs_addr register ****/
-/* Address value */
-#define ETH_MAC_KR_PCS_ADDR_VAL_MASK     0x0000FFFF
-#define ETH_MAC_KR_PCS_ADDR_VAL_SHIFT    0
-
-/**** pcs_data register ****/
-/* Data value */
-#define ETH_MAC_KR_PCS_DATA_VAL_MASK     0x0000FFFF
-#define ETH_MAC_KR_PCS_DATA_VAL_SHIFT    0
-
-/**** an_addr register ****/
-/* Address value */
-#define ETH_MAC_KR_AN_ADDR_VAL_MASK      0x0000FFFF
-#define ETH_MAC_KR_AN_ADDR_VAL_SHIFT     0
-
-/**** an_data register ****/
-/* Data value */
-#define ETH_MAC_KR_AN_DATA_VAL_MASK      0x0000FFFF
-#define ETH_MAC_KR_AN_DATA_VAL_SHIFT     0
-
-/**** pma_addr register ****/
-/* Dddress value */
-#define ETH_MAC_KR_PMA_ADDR_VAL_MASK     0x0000FFFF
-#define ETH_MAC_KR_PMA_ADDR_VAL_SHIFT    0
-
-/**** pma_data register ****/
-/* Data value */
-#define ETH_MAC_KR_PMA_DATA_VAL_MASK     0x0000FFFF
-#define ETH_MAC_KR_PMA_DATA_VAL_SHIFT    0
-
-/**** mtip_addr register ****/
-/* Address value */
-#define ETH_MAC_KR_MTIP_ADDR_VAL_MASK    0x0000FFFF
-#define ETH_MAC_KR_MTIP_ADDR_VAL_SHIFT   0
-
-/**** mtip_data register ****/
-/* Data value */
-#define ETH_MAC_KR_MTIP_DATA_VAL_MASK    0x0000FFFF
-#define ETH_MAC_KR_MTIP_DATA_VAL_SHIFT   0
-
-/**** pcs_cfg register ****/
-/* Enable Auto-Negotiation after Reset */
-#define ETH_MAC_KR_PCS_CFG_STRAP_AN_ENA  (1 << 0)
-/*
- * Signal detect selector for the EEE
- * 0 – Register default value
- * 1 – SerDes value
- */
-#define ETH_MAC_KR_PCS_CFG_EEE_SD_SEL    (1 << 4)
-/* Signal detect default value for the EEE */
-#define ETH_MAC_KR_PCS_CFG_EEE_DEF_VAL   (1 << 5)
-/* Signal detect polarity reversal for the EEE */
-#define ETH_MAC_KR_PCS_CFG_EEE_SD_POL    (1 << 6)
-/* EEE timer value  */
-#define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK 0x0000FF00
-#define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT 8
-/*
- * Selects source for the enable SerDes DME signal
- * 0 – Register value
- * 1 – PCS output
- */
-#define ETH_MAC_KR_PCS_CFG_DME_SEL       (1 << 16)
-/* DME default value */
-#define ETH_MAC_KR_PCS_CFG_DME_VAL       (1 << 17)
-/* DME default polarity reversal when selecting PCS output */
-#define ETH_MAC_KR_PCS_CFG_DME_POL       (1 << 18)
-
-/**** pcs_stat register ****/
-/* Link enable by the Auto-Negotiation */
-#define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_MASK 0x0000003F
-#define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_SHIFT 0
-/* Block lock */
-#define ETH_MAC_KR_PCS_STAT_BLOCK_LOCK   (1 << 8)
-/* hi BER */
-#define ETH_MAC_KR_PCS_STAT_HI_BER       (1 << 9)
-
-#define ETH_MAC_KR_PCS_STAT_RX_WAKE_ERR  (1 << 16)
-
-#define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_ALERT (1 << 17)
-
-#define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_QUIET (1 << 18)
-
-#define ETH_MAC_KR_PCS_STAT_PMA_RXMODE_QUIET (1 << 19)
-
-#define ETH_MAC_KR_PCS_STAT_RX_LPI_ACTIVE (1 << 20)
-
-#define ETH_MAC_KR_PCS_STAT_TX_LPI_ACTIVE (1 << 21)
-
-/**** reg_addr register ****/
-/* Address value */
-#define ETH_MAC_SGMII_REG_ADDR_VAL_MASK  0x0000001F
-#define ETH_MAC_SGMII_REG_ADDR_VAL_SHIFT 0
-
-#define ETH_MAC_SGMII_REG_ADDR_CTRL_REG	0x0
-#define ETH_MAC_SGMII_REG_ADDR_IF_MODE_REG 0x14
-
-/**** reg_data register ****/
-/* Data value */
-#define ETH_MAC_SGMII_REG_DATA_VAL_MASK  0x0000FFFF
-#define ETH_MAC_SGMII_REG_DATA_VAL_SHIFT 0
-
-#define ETH_MAC_SGMII_REG_DATA_CTRL_AN_ENABLE			(1 << 12)
-#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_EN			(1 << 0)
-#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_AN			(1 << 1)
-#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_MASK		0xC
-#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_SHIFT	2
-#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_10		0x0
-#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_100		0x1
-#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_1000		0x2
-#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_DUPLEX		(1 << 4)
-
-/**** clk_div register ****/
-/* Value for 1000M selection */
-#define ETH_MAC_SGMII_CLK_DIV_VAL_1000_MASK 0x000000FF
-#define ETH_MAC_SGMII_CLK_DIV_VAL_1000_SHIFT 0
-/* Value for 100M selection */
-#define ETH_MAC_SGMII_CLK_DIV_VAL_100_MASK 0x0000FF00
-#define ETH_MAC_SGMII_CLK_DIV_VAL_100_SHIFT 8
-/* Value for 10M selection */
-#define ETH_MAC_SGMII_CLK_DIV_VAL_10_MASK 0x00FF0000
-#define ETH_MAC_SGMII_CLK_DIV_VAL_10_SHIFT 16
-/* Bypass PCS selection */
-#define ETH_MAC_SGMII_CLK_DIV_BYPASS     (1 << 24)
-/*
- * Divider selection when bypass field is '1', one hot
- * 001 – 1000M
- * 010 – 100M
- * 100 – 10M
- */
-#define ETH_MAC_SGMII_CLK_DIV_SEL_MASK   0x0E000000
-#define ETH_MAC_SGMII_CLK_DIV_SEL_SHIFT  25
-
-/**** link_stat register ****/
-
-#define ETH_MAC_SGMII_LINK_STAT_SET_1000 (1 << 0)
-
-#define ETH_MAC_SGMII_LINK_STAT_SET_100  (1 << 1)
-
-#define ETH_MAC_SGMII_LINK_STAT_SET_10   (1 << 2)
-
-#define ETH_MAC_SGMII_LINK_STAT_LED_AN   (1 << 3)
-
-#define ETH_MAC_SGMII_LINK_STAT_HD_ENA   (1 << 4)
-
-#define ETH_MAC_SGMII_LINK_STAT_LED_LINK (1 << 5)
-
-/**** afifo_ctrl register ****/
-/* enable tx input operation */
-#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_IN (1 << 0)
-/* enable tx output operation */
-#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_OUT (1 << 1)
-/* enable rx input operation */
-#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_IN (1 << 4)
-/* enable rx output operation */
-#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_OUT (1 << 5)
-/* enable tx FIFO input operation */
-#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_IN (1 << 8)
-/* enable tx FIFO output operation */
-#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_OUT (1 << 9)
-/* enable rx FIFO input operation */
-#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_IN (1 << 12)
-/* enable rx FIFO output operation */
-#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_OUT (1 << 13)
-
-/**** tx_afifo_cfg_1 register ****/
-/* minimum packet size configuration */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0
-
-/**** tx_afifo_cfg_2 register ****/
-/* maximum packet size configuration */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0
-
-/**** tx_afifo_cfg_3 register ****/
-/* input bus width */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0
-/* input bus width divide factor */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16
-
-/**** tx_afifo_cfg_4 register ****/
-/* output bus width */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0
-/* output bus width divide factor */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16
-
-/**** tx_afifo_cfg_5 register ****/
-/*
- * determines if the input bus is valid/read or “write enable”.
- * 0 – write enable
- * 1 – valid/ready
- */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0)
-/*
- * determines if the output bus is valid/read or “write enable”.
- * 0 – write enable
- * 1 – valid/ready
- */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1)
-/* Swap input bus bytes */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4)
-/* Swap output bus bytes */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5)
-/*
- * output clock select
- * 0 – mac_ll_tx_clk
- * 1 – clk_mac_sys_clk
- */
-#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_CLK_SEL (1 << 8)
-
-/**** rx_afifo_cfg_1 register ****/
-/* minimum packet size configuration */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0
-
-/**** rx_afifo_cfg_2 register ****/
-/* maximum packet size configuration */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0
-
-/**** rx_afifo_cfg_3 register ****/
-/* input bus width */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0
-/* input bus width divide factor */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16
-
-/**** rx_afifo_cfg_4 register ****/
-/* output bus width */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0
-/* output bus width divide factor */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16
-
-/**** rx_afifo_cfg_5 register ****/
-/*
- * determines if the input bus is valid/read or “write enable”.
- * 0 – write enable
- * 1 – valid/ready
- */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0)
-/*
- * determines if the output bus is valid/read or “write enable”.
- * 0 – write enable
- * 1 – valid/ready
- */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1)
-/* Swap input bus bytes */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4)
-/* Swap output bus bytes */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5)
-/*
- * input clock select
- * 0 – mac_ll_rx_clk
- * 1 – clk_serdes_int_0_tx_dword_ref
- * 2 – clk_mac_sys_clk
- * 3 – mac_ll_tx_clk
- */
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_MASK 0x00000300
-#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_SHIFT 8
-
-/**** mac_sel register ****/
-/*
- * Select the MAC that is connected to the SGMII PCS.
- * 0 – 1G MAC
- * 1 – 10G MAC
- */
-#define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_SGMII (1 << 0)
-/*
- * Select between the 10G and 40G MAC
- * 0 – 10G MAC
- * 1 – 40G MAC
- */
-#define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_40G (1 << 4)
-
-/**** mac_10g_ll_cfg register ****/
-/*
- * select between 10G (KR PCS) and 1G (SGMII) mode.
- * 0 – 10G
- * 1 – 1G
- */
-#define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MODE_1G (1 << 0)
-/* enable Magic packet detection in the MAC (all other packets are dropped) */
-#define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MAGIC_ENA (1 << 5)
-
-/**** mac_10g_ll_ctrl register ****/
-/* Force the MAC to stop TX transmission after low power mode. */
-#define ETH_MAC_GEN_V3_MAC_10G_LL_CTRL_LPI_TXHOLD (1 << 0)
-
-/**** pcs_10g_ll_cfg register ****/
-/* RX FEC Enable */
-#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_RX (1 << 0)
-/* TX FEC enable */
-#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_TX (1 << 1)
-/*
- * RX FEC error propagation enable,
- * (debug, always 0)
- */
-#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_ERR_ENA (1 << 2)
-/*
- * Gearbox configuration:
- * 00 -16
- * 01 – 20
- * 10 – 32
- * 11 – reserved
- */
-#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_MASK 0x00000030
-#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_SHIFT 4
-/*
- * Gearbox configuration:
- * 00 -16
- * 01 – 20
- * 10 – 32
- * 11 – reserved
- */
-#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_MASK 0x000000C0
-#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_SHIFT 6
-
-/**** pcs_10g_ll_status register ****/
-/* FEC locked indication */
-#define ETH_MAC_GEN_V3_PCS_10G_LL_STATUS_FEC_LOCKED (1 << 0)
-
-/**** pcs_40g_ll_cfg register ****/
-/* RX FEC Enable */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_MASK 0x0000000F
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_SHIFT 0
-/* TX FEC enable */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_MASK 0x000000F0
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_SHIFT 4
-/*
- * RX FEC error propagation enable,
- * (debug, always 0)
- */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_MASK 0x00000F00
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_SHIFT 8
-/*
- * SERDES width, 16 bit enable
- * 1 – 16
- * 2 – 32
- */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_SD_16B (1 << 12)
-/* FEC 91 enable */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC91_ENA (1 << 13)
-/*
- * PHY LOS indication selection
- * 00 - Select register value from phy_los_def
- * 01 - Select input from the SerDes
- * 10 - Select input from GPIO
- * 11 - Select inverted input from GPIO
- */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00030000
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_SHIFT 16
-/* PHY LOS default value */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_DEF (1 << 18)
-/* PHY LOS polarity */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_POL (1 << 19)
-/*
- * Energy detect  indication selection
- * 00 - Select register value from phy_los_def
- * 01 - Select input from the SerDes
- * 10 - Select input from GPIO
- * 11 - Select inverted input from GPIO
- */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_MASK 0x00300000
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_SHIFT 20
-/* Energy detect default value */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_DEF (1 << 22)
-/* Energy detect polarity */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_POL (1 << 23)
-
-/**** pcs_40g_ll_status register ****/
-/* Block lock */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_MASK 0x0000000F
-#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_SHIFT 0
-/* align done */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_ALIGN_DONE (1 << 4)
-/* high BER */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_HIGH_BER (1 << 8)
-/* FEC locked indication */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_MASK 0x0000F000
-#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_SHIFT 12
-
-/**** pcs_40g_ll_addr register ****/
-/* Address value */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_MASK 0x0001FFFF
-#define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_SHIFT 0
-
-/**** pcs_40g_ll_data register ****/
-/* Data value */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_SHIFT 0
-
-/**** mac_40g_ll_cfg register ****/
-/* change TX CRC polarity */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_SWAP_FF_TX_CRC (1 << 0)
-/* force TX remote fault */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_REM_FAULT (1 << 4)
-/* force TX local fault */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LOC_FAULT (1 << 5)
-/* force TX Link fault */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LI_FAULT (1 << 6)
-/*
- * PHY LOS indication selection
- * 00 - Select register value from phy_los_def
- * 01 - Select input from the SerDes
- * 10 - Select input from GPIO
- * 11 - Select inverted input from GPIO
- */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00000300
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_SHIFT 8
-/* PHY LOS default value */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_DEF (1 << 10)
-/* PHY LOS polarity */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_POL (1 << 11)
-
-/**** mac_40g_ll_status register ****/
-/* pause on indication */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_MASK 0x000000FF
-#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_SHIFT 0
-/* local fault indication received */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LOC_FAULT (1 << 8)
-/* remote fault indication received */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_REM_FAULT (1 << 9)
-/* Link fault indication */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LI_FAULT (1 << 10)
-
-/**** preamble_cfg_high register ****/
-/* preamble value */
-#define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_MASK 0x00FFFFFF
-#define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_SHIFT 0
-
-/**** mac_40g_ll_addr register ****/
-/* Address value */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_MASK 0x000003FF
-#define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_SHIFT 0
-
-/**** mac_40g_ll_ctrl register ****/
-/* Force the MAC to stop TX transmission after low power mode. */
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_LPI_TXHOLD (1 << 0)
-
-#define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_REG_LOWP_ENA (1 << 1)
-
-/**** pcs_40g_fec_91_ll_addr register ****/
-/* Address value */
-#define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_MASK 0x000001FF
-#define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_SHIFT 0
-
-/**** pcs_40g_fec_91_ll_data register ****/
-/* Data value */
-#define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_SHIFT 0
-
-/**** pcs_40g_ll_eee_cfg register ****/
-/* Low power timer configuration */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK 0x000000FF
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT 0
-/* Low power Fast wake */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_LPI_FW (1 << 8)
-
-/**** pcs_40g_ll_eee_status register ****/
-/* TX LPI mode */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_MASK 0x00000003
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_SHIFT 0
-/* TX LPI state */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_MASK 0x00000070
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_SHIFT 4
-/* TX LPI mode */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_MODE (1 << 8)
-/* TX LPI state */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_MASK 0x00007000
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_SHIFT 12
-/* TX LPI active */
-#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_ACTIVE (1 << 15)
-
-/**** serdes_32_tx_shift register ****/
-/* bit shift */
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_MASK 0x0000001F
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_SHIFT 0
-/* bit shift */
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_MASK 0x000003E0
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_SHIFT 5
-/* bit shift */
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_MASK 0x00007C00
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_SHIFT 10
-/* bit shift */
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_MASK 0x000F8000
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_SHIFT 15
-
-/**** serdes_32_rx_shift register ****/
-/* bit shift */
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_MASK 0x0000001F
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_SHIFT 0
-/* bit shift */
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_MASK 0x000003E0
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_SHIFT 5
-/* bit shift */
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_MASK 0x00007C00
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_SHIFT 10
-/* bit shift */
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_MASK 0x000F8000
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_SHIFT 15
-
-/**** serdes_32_tx_sel register ****/
-/*
- * 0 – directly from serdes
- * 1 – swapped
- * 2 – swapped with shift
- * 3 - legacy (based on gen cfg register)
- */
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_MASK 0x00000003
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_SHIFT 0
-/*
- * 0 – directly from serdes
- * 1 – swapped
- * 2 – swapped with shift
- * 3 - legacy (based on gen cfg register)
- */
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_MASK 0x00000030
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_SHIFT 4
-/*
- * 0 – directly from serdes
- * 1 – swapped
- * 2 – swapped with shift
- * 3 - legacy (based on gen cfg register)
- */
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_MASK 0x00000300
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_SHIFT 8
-/*
- * 0 – directly from serdes
- * 1 – swapped
- * 2 – swapped with shift
- * 3 - legacy (based on gen cfg register)
- */
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_MASK 0x00003000
-#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_SHIFT 12
-
-/**** serdes_32_rx_sel register ****/
-/*
- * 0 – directly from serdes
- * 1 – swapped
- * 2 – swapped with shift
- * 3 - legacy (based on gen cfg register)
- */
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_MASK 0x00000003
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_SHIFT 0
-/*
- * 0 – directly from serdes
- * 1 – swapped
- * 2 – swapped with shift
- * 3 - legacy (based on gen cfg register)
- */
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_MASK 0x00000030
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_SHIFT 4
-/*
- * 0 – directly from serdes
- * 1 – swapped
- * 2 – swapped with shift
- * 3 - legacy (based on gen cfg register)
- */
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_MASK 0x00000300
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_SHIFT 8
-/*
- * 0 – directly from serdes
- * 1 – swapped
- * 2 – swapped with shift
- * 3 - legacy (based on gen cfg register)
- */
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_MASK 0x00003000
-#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_SHIFT 12
-
-/**** an_lt_ctrl register ****/
-/* reset lane [3:0] */
-#define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_MASK 0x0000000F
-#define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_SHIFT 0
-
-/* PHY LOS indication input selection
- * 0 - from serdes
- * 1 - from an_lt
- */
-#define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_0 (1 << 8)
-/* PHY LOS indication input selection
- * 0 - from serdes
- * 1 - from an_lt
- */
-#define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_1 (1 << 9)
-/* PHY LOS indication input selection
- * 0 - from serdes
- * 1 - from an_lt
- */
-#define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_2 (1 << 10)
-/* PHY LOS indication input selection
- * 0 - from serdes
- * 1 - from an_lt
- */
-#define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_3 (1 << 11)
-
-/**** an_lt_0_addr register ****/
-/* Address value */
-#define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_SHIFT 0
-
-/**** an_lt_1_addr register ****/
-/* Address value */
-#define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_SHIFT 0
-
-/**** an_lt_2_addr register ****/
-/* Address value */
-#define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_SHIFT 0
-
-/**** an_lt_3_addr register ****/
-/* Address value */
-#define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_MASK 0x0000FFFF
-#define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_SHIFT 0
-
-/**** ext_serdes_ctrl register ****/
-/*
- * Lane 0, SERDES selection:
- * 0 – 10G SERDES, lane 0
- * 1 – 25G SERDES, lane 0
- */
-#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_SEL_25_10 (1 << 0)
-/*
- * Lane 1, SERDES selection:
- * 0 – 10G SERDES, lane 1
- * 1 – 25G SERDES, lane 1
- */
-#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_SEL_25_10 (1 << 1)
-/*
- * Lane 2, SERDES selection:
- * 0 – 10G SERDES, lane 2
- * 1 – 25G SERDES, lane 0
- */
-#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_2_SEL_25_10 (1 << 2)
-/*
- * Lane 3, SERDES selection:
- * 0 – 10G SERDES, lane 3
- * 1 – 25G SERDES, lane 1
- */
-#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_3_SEL_25_10 (1 << 3)
-
-/* Lane 0 Rx, 25G 40bit-32bit gearshitf sw reset */
-#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_RX_25_GS_SW_RESET (1 << 4)
-/* Lane 0 Tx, 25G 40bit-32bit gearshitf sw reset */
-#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_TX_25_GS_SW_RESET (1 << 5)
-/* Lane 1 Rx, 25G 40bit-32bit gearshitf sw reset */
-#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_RX_25_GS_SW_RESET (1 << 6)
-/* Lane 1 Tx, 25G 40bit-32bit gearshitf sw reset */
-#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_TX_25_GS_SW_RESET (1 << 7)
-/* SerDes 25G gear shift Tx lane selector */
-#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_SRDS25_GS_TX_LANE_CLK_SEL (1 << 8)
-
-/*** MAC Core registers addresses ***/
-/* command config */
-#define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR	0x00000008
-#define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_TX_ENA	(1 << 0)
-#define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_RX_ENA	(1 << 1)
-#define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_PFC_MODE	(1 << 19)
-
-/* frame length */
-#define ETH_MAC_GEN_V3_MAC_40G_FRM_LENGTH_ADDR		0x00000014
-
-#define ETH_MAC_GEN_V3_MAC_40G_CL01_PAUSE_QUANTA_ADDR	0x00000054
-#define ETH_MAC_GEN_V3_MAC_40G_CL23_PAUSE_QUANTA_ADDR	0x00000058
-#define ETH_MAC_GEN_V3_MAC_40G_CL45_PAUSE_QUANTA_ADDR	0x0000005C
-#define ETH_MAC_GEN_V3_MAC_40G_CL67_PAUSE_QUANTA_ADDR	0x00000060
-#define ETH_MAC_GEN_V3_MAC_40G_CL01_QUANTA_THRESH_ADDR	0x00000064
-#define ETH_MAC_GEN_V3_MAC_40G_CL23_QUANTA_THRESH_ADDR	0x00000068
-#define ETH_MAC_GEN_V3_MAC_40G_CL45_QUANTA_THRESH_ADDR	0x0000006C
-#define ETH_MAC_GEN_V3_MAC_40G_CL67_QUANTA_THRESH_ADDR	0x00000070
-
-/* spare */
-#define ETH_MAC_GEN_V3_SPARE_CHICKEN_DISABLE_TIMESTAMP_STRETCH (1 << 0)
-
-/*** PCS Core registers addresses ***/
-/* 40g control/status */
-#define ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR      0x00000000
-/* 40g EEE control and capability */
-#define ETH_MAC_GEN_V3_PCS_40G_EEE_CONTROL_ADDR         0x00000028
-/* 10g control_1 */
-#define ETH_MAC_KR_PCS_CONTROL_1_ADDR                   0x00000000
-
-#define ETH_MAC_KR_PCS_BASE_R_STATUS2			0x00000021
-
-#define ETH_MAC_KR_AN_MILLISECONDS_COUNTER_ADDR         0x00008000
-#define ETH_MAC_AN_LT_MILLISECONDS_COUNTER_ADDR         0x00000020
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __AL_HAL_ETH_MAC_REGS_H__ */
-
-/** @} end of Ethernet group */
diff --git a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_main.c b/sys/contrib/alpine-hal/eth/eth/al_hal_eth_main.c
deleted file mode 100644
index d7913af2c935..000000000000
--- a/sys/contrib/alpine-hal/eth/eth/al_hal_eth_main.c
+++ /dev/null
@@ -1,5668 +0,0 @@
-/*-
-*******************************************************************************
-Copyright (C) 2015 Annapurna Labs Ltd.
-
-This file may be licensed under the terms of the Annapurna Labs Commercial
-License Agreement.
-
-Alternatively, this file can be distributed under the terms of the GNU General
-Public License V2 as published by the Free Software Foundation and can be
-found at http://www.gnu.org/licenses/gpl-2.0.html
-
-Alternatively, redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following conditions are
-met:
-
-    *     Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-
-    *     Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-/**
- *  @{
- * @file   al_hal_eth_main.c
- *
- * @brief  XG Ethernet unit HAL driver for main functions (initialization, data path)
- *
- */
-
-#include "al_hal_eth.h"
-#include "al_hal_udma_iofic.h"
-#include "al_hal_udma_config.h"
-#include "al_hal_eth_ec_regs.h"
-#include "al_hal_eth_mac_regs.h"
-#include "al_hal_unit_adapter_regs.h"
-#ifdef AL_ETH_EX
-#include "al_hal_eth_ex_internal.h"
-#endif
-
-/* Number of xfi_txclk cycles that accumulate into 100ns */
-#define ETH_MAC_KR_10_PCS_CFG_EEE_TIMER_VAL 52
-#define ETH_MAC_KR_25_PCS_CFG_EEE_TIMER_VAL 80
-#define ETH_MAC_XLG_40_PCS_CFG_EEE_TIMER_VAL 63
-#define ETH_MAC_XLG_50_PCS_CFG_EEE_TIMER_VAL 85
-
-#define AL_ETH_TX_PKT_UDMA_FLAGS	(AL_ETH_TX_FLAGS_NO_SNOOP | \
-					 AL_ETH_TX_FLAGS_INT)
-
-#define AL_ETH_TX_PKT_META_FLAGS	(AL_ETH_TX_FLAGS_IPV4_L3_CSUM | \
-					 AL_ETH_TX_FLAGS_L4_CSUM |	\
-					 AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM |	\
-					 AL_ETH_TX_FLAGS_L2_MACSEC_PKT | \
-					 AL_ETH_TX_FLAGS_L2_DIS_FCS |\
-					 AL_ETH_TX_FLAGS_TSO |\
-					 AL_ETH_TX_FLAGS_TS)
-
-#define AL_ETH_TX_SRC_VLAN_CNT_MASK	3
-#define AL_ETH_TX_SRC_VLAN_CNT_SHIFT	5
-#define AL_ETH_TX_L4_PROTO_IDX_MASK	0x1F
-#define AL_ETH_TX_L4_PROTO_IDX_SHIFT	8
-#define AL_ETH_TX_TUNNEL_MODE_SHIFT		18
-#define AL_ETH_TX_OUTER_L3_PROTO_SHIFT		20
-#define AL_ETH_TX_VLAN_MOD_ADD_SHIFT		22
-#define AL_ETH_TX_VLAN_MOD_DEL_SHIFT		24
-#define AL_ETH_TX_VLAN_MOD_E_SEL_SHIFT		26
-#define AL_ETH_TX_VLAN_MOD_VID_SEL_SHIFT	28
-#define AL_ETH_TX_VLAN_MOD_PBIT_SEL_SHIFT	30
-
-/* tx Meta Descriptor defines */
-#define AL_ETH_TX_META_STORE			(1 << 21)
-#define AL_ETH_TX_META_L3_LEN_MASK		0xff
-#define AL_ETH_TX_META_L3_OFF_MASK		0xff
-#define AL_ETH_TX_META_L3_OFF_SHIFT		8
-#define AL_ETH_TX_META_MSS_LSB_VAL_SHIFT	22
-#define AL_ETH_TX_META_MSS_MSB_TS_VAL_SHIFT	16
-#define AL_ETH_TX_META_OUTER_L3_LEN_MASK	0x1f
-#define AL_ETH_TX_META_OUTER_L3_LEN_SHIFT	24
-#define AL_ETH_TX_META_OUTER_L3_OFF_HIGH_MASK	0x18
-#define AL_ETH_TX_META_OUTER_L3_OFF_HIGH_SHIFT	10
-#define AL_ETH_TX_META_OUTER_L3_OFF_LOW_MASK	0x07
-#define AL_ETH_TX_META_OUTER_L3_OFF_LOW_SHIFT	29
-
-/* tx Meta Descriptor defines - MacSec */
-#define AL_ETH_TX_MACSEC_SIGN_SHIFT			  0		/* Sign TX pkt */
-#define AL_ETH_TX_MACSEC_ENCRYPT_SHIFT			  1		/* Encrypt TX pkt */
-#define AL_ETH_TX_MACSEC_AN_LSB_SHIFT			  2		/* Association Number */
-#define AL_ETH_TX_MACSEC_AN_MSB_SHIFT			  3
-#define AL_ETH_TX_MACSEC_SC_LSB_SHIFT			  4		/* Secured Channel */
-#define AL_ETH_TX_MACSEC_SC_MSB_SHIFT			  9
-#define AL_ETH_TX_MACSEC_SECURED_PYLD_LEN_LSB_SHIFT	 10		/* Secure Payload Length (0x3FFF for non-SL packets) */
-#define AL_ETH_TX_MACSEC_SECURED_PYLD_LEN_MSB_SHIFT	 23
-
-/* Rx Descriptor defines */
-#define AL_ETH_RX_L3_PROTO_IDX_MASK	0x1F
-#define AL_ETH_RX_SRC_VLAN_CNT_MASK	3
-#define AL_ETH_RX_SRC_VLAN_CNT_SHIFT	5
-#define AL_ETH_RX_L4_PROTO_IDX_MASK	0x1F
-#define AL_ETH_RX_L4_PROTO_IDX_SHIFT	8
-
-#define AL_ETH_RX_L3_OFFSET_SHIFT	9
-#define AL_ETH_RX_L3_OFFSET_MASK	(0x7f << AL_ETH_RX_L3_OFFSET_SHIFT)
-#define AL_ETH_RX_HASH_SHIFT		16
-#define AL_ETH_RX_HASH_MASK		(0xffff 	<< AL_ETH_RX_HASH_SHIFT)
-
-#define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_VAL 5
-#define ETH_MAC_GEN_LED_CFG_ACT_TIMER_VAL 7
-
-/* Tx VID Table*/
-#define AL_ETH_TX_VLAN_TABLE_UDMA_MASK		0xF
-#define AL_ETH_TX_VLAN_TABLE_FWD_TO_MAC		(1 << 4)
-
-/* tx gpd defines */
-#define AL_ETH_TX_GPD_L3_PROTO_MASK		0x1f
-#define AL_ETH_TX_GPD_L3_PROTO_SHIFT		0
-#define AL_ETH_TX_GPD_L4_PROTO_MASK		0x1f
-#define AL_ETH_TX_GPD_L4_PROTO_SHIFT		5
-#define AL_ETH_TX_GPD_TUNNEL_CTRL_MASK		0x7
-#define AL_ETH_TX_GPD_TUNNEL_CTRL_SHIFT		10
-#define AL_ETH_TX_GPD_SRC_VLAN_CNT_MASK		0x3
-#define AL_ETH_TX_GPD_SRC_VLAN_CNT_SHIFT	13
-#define AL_ETH_TX_GPD_CAM_DATA_2_SHIFT		32
-#define AL_ETH_TX_GPD_CAM_MASK_2_SHIFT		32
-#define AL_ETH_TX_GPD_CAM_CTRL_VALID_SHIFT	31
-
-/* tx gcp defines */
-#define AL_ETH_TX_GCP_POLY_SEL_MASK		0x1
-#define AL_ETH_TX_GCP_POLY_SEL_SHIFT		0
-#define AL_ETH_TX_GCP_CRC32_BIT_COMP_MASK	0x1
-#define AL_ETH_TX_GCP_CRC32_BIT_COMP_SHIFT	1
-#define AL_ETH_TX_GCP_CRC32_BIT_SWAP_MASK	0x1
-#define AL_ETH_TX_GCP_CRC32_BIT_SWAP_SHIFT	2
-#define AL_ETH_TX_GCP_CRC32_BYTE_SWAP_MASK	0x1
-#define AL_ETH_TX_GCP_CRC32_BYTE_SWAP_SHIFT	3
-#define AL_ETH_TX_GCP_DATA_BIT_SWAP_MASK	0x1
-#define AL_ETH_TX_GCP_DATA_BIT_SWAP_SHIFT	4
-#define AL_ETH_TX_GCP_DATA_BYTE_SWAP_MASK	0x1
-#define AL_ETH_TX_GCP_DATA_BYTE_SWAP_SHIFT	5
-#define AL_ETH_TX_GCP_TRAIL_SIZE_MASK		0xF
-#define AL_ETH_TX_GCP_TRAIL_SIZE_SHIFT		6
-#define AL_ETH_TX_GCP_HEAD_SIZE_MASK		0xFF
-#define AL_ETH_TX_GCP_HEAD_SIZE_SHIFT		16
-#define AL_ETH_TX_GCP_HEAD_CALC_MASK		0x1
-#define AL_ETH_TX_GCP_HEAD_CALC_SHIFT		24
-#define AL_ETH_TX_GCP_MASK_POLARITY_MASK	0x1
-#define AL_ETH_TX_GCP_MASK_POLARITY_SHIFT	25
-
-#define AL_ETH_TX_GCP_OPCODE_1_MASK		0x3F
-#define AL_ETH_TX_GCP_OPCODE_1_SHIFT		0
-#define AL_ETH_TX_GCP_OPCODE_2_MASK		0x3F
-#define AL_ETH_TX_GCP_OPCODE_2_SHIFT		6
-#define AL_ETH_TX_GCP_OPCODE_3_MASK		0x3F
-#define AL_ETH_TX_GCP_OPCODE_3_SHIFT		12
-#define AL_ETH_TX_GCP_OPSEL_1_MASK		0xF
-#define AL_ETH_TX_GCP_OPSEL_1_SHIFT		0
-#define AL_ETH_TX_GCP_OPSEL_2_MASK		0xF
-#define AL_ETH_TX_GCP_OPSEL_2_SHIFT		4
-#define AL_ETH_TX_GCP_OPSEL_3_MASK		0xF
-#define AL_ETH_TX_GCP_OPSEL_3_SHIFT		8
-#define AL_ETH_TX_GCP_OPSEL_4_MASK		0xF
-#define AL_ETH_TX_GCP_OPSEL_4_SHIFT		12
-
-/*  Tx crc_chksum_replace defines */
-#define L4_CHECKSUM_DIS_AND_L3_CHECKSUM_DIS     0x00
-#define L4_CHECKSUM_DIS_AND_L3_CHECKSUM_EN      0x20
-#define L4_CHECKSUM_EN_AND_L3_CHECKSUM_DIS      0x40
-#define L4_CHECKSUM_EN_AND_L3_CHECKSUM_EN       0x60
-
-/* rx gpd defines */
-#define AL_ETH_RX_GPD_OUTER_L3_PROTO_MASK		0x1f
-#define AL_ETH_RX_GPD_OUTER_L3_PROTO_SHIFT		(3 + 0)
-#define AL_ETH_RX_GPD_OUTER_L4_PROTO_MASK		0x1f
-#define AL_ETH_RX_GPD_OUTER_L4_PROTO_SHIFT		(3 + 8)
-#define AL_ETH_RX_GPD_INNER_L3_PROTO_MASK		0x1f
-#define AL_ETH_RX_GPD_INNER_L3_PROTO_SHIFT		(3 + 16)
-#define AL_ETH_RX_GPD_INNER_L4_PROTO_MASK		0x1f
-#define AL_ETH_RX_GPD_INNER_L4_PROTO_SHIFT		(3 + 24)
-#define AL_ETH_RX_GPD_OUTER_PARSE_CTRL_MASK		0xFF
-#define AL_ETH_RX_GPD_OUTER_PARSE_CTRL_SHIFT	32
-#define AL_ETH_RX_GPD_INNER_PARSE_CTRL_MASK		0xFF
-#define AL_ETH_RX_GPD_INNER_PARSE_CTRL_SHIFT	40
-#define AL_ETH_RX_GPD_L3_PRIORITY_MASK			0xFF
-#define AL_ETH_RX_GPD_L3_PRIORITY_SHIFT			48
-#define AL_ETH_RX_GPD_L4_DST_PORT_LSB_MASK		0xFF
-#define AL_ETH_RX_GPD_L4_DST_PORT_LSB_SHIFT		56
-#define AL_ETH_RX_GPD_CAM_DATA_2_SHIFT			32
-#define AL_ETH_RX_GPD_CAM_MASK_2_SHIFT			32
-#define AL_ETH_RX_GPD_CAM_CTRL_VALID_SHIFT		31
-
-#define AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L3_PROTO_IDX_OFFSET	(106 + 5)
-#define AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L4_PROTO_IDX_OFFSET	(106 + 10)
-#define AL_ETH_RX_GPD_PARSE_RESULT_INNER_L3_PROTO_IDX_OFFSET	(0 + 5)
-#define AL_ETH_RX_GPD_PARSE_RESULT_INNER_L4_PROTO_IDX_OFFSET	(0 + 10)
-#define AL_ETH_RX_GPD_PARSE_RESULT_OUTER_PARSE_CTRL			(106 + 4)
-#define AL_ETH_RX_GPD_PARSE_RESULT_INNER_PARSE_CTRL			4
-#define AL_ETH_RX_GPD_PARSE_RESULT_L3_PRIORITY			(106 + 13)
-#define AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L4_DST_PORT_LSB	(106 + 65)
-
-/* rx gcp defines */
-#define AL_ETH_RX_GCP_POLY_SEL_MASK		0x1
-#define AL_ETH_RX_GCP_POLY_SEL_SHIFT		0
-#define AL_ETH_RX_GCP_CRC32_BIT_COMP_MASK	0x1
-#define AL_ETH_RX_GCP_CRC32_BIT_COMP_SHIFT	1
-#define AL_ETH_RX_GCP_CRC32_BIT_SWAP_MASK	0x1
-#define AL_ETH_RX_GCP_CRC32_BIT_SWAP_SHIFT	2
-#define AL_ETH_RX_GCP_CRC32_BYTE_SWAP_MASK      0x1
-#define AL_ETH_RX_GCP_CRC32_BYTE_SWAP_SHIFT	3
-#define AL_ETH_RX_GCP_DATA_BIT_SWAP_MASK	0x1
-#define AL_ETH_RX_GCP_DATA_BIT_SWAP_SHIFT	4
-#define AL_ETH_RX_GCP_DATA_BYTE_SWAP_MASK       0x1
-#define AL_ETH_RX_GCP_DATA_BYTE_SWAP_SHIFT	5
-#define AL_ETH_RX_GCP_TRAIL_SIZE_MASK		0xF
-#define AL_ETH_RX_GCP_TRAIL_SIZE_SHIFT		6
-#define AL_ETH_RX_GCP_HEAD_SIZE_MASK		0xFF
-#define AL_ETH_RX_GCP_HEAD_SIZE_SHIFT		16
-#define AL_ETH_RX_GCP_HEAD_CALC_MASK		0x1
-#define AL_ETH_RX_GCP_HEAD_CALC_SHIFT		24
-#define AL_ETH_RX_GCP_MASK_POLARITY_MASK	0x1
-#define AL_ETH_RX_GCP_MASK_POLARITY_SHIFT	25
-
-#define AL_ETH_RX_GCP_OPCODE_1_MASK		0x3F
-#define AL_ETH_RX_GCP_OPCODE_1_SHIFT		0
-#define AL_ETH_RX_GCP_OPCODE_2_MASK		0x3F
-#define AL_ETH_RX_GCP_OPCODE_2_SHIFT		6
-#define AL_ETH_RX_GCP_OPCODE_3_MASK		0x3F
-#define AL_ETH_RX_GCP_OPCODE_3_SHIFT		12
-#define AL_ETH_RX_GCP_OPSEL_1_MASK		0xF
-#define AL_ETH_RX_GCP_OPSEL_1_SHIFT		0
-#define AL_ETH_RX_GCP_OPSEL_2_MASK		0xF
-#define AL_ETH_RX_GCP_OPSEL_2_SHIFT		4
-#define AL_ETH_RX_GCP_OPSEL_3_MASK		0xF
-#define AL_ETH_RX_GCP_OPSEL_3_SHIFT		8
-#define AL_ETH_RX_GCP_OPSEL_4_MASK		0xF
-#define AL_ETH_RX_GCP_OPSEL_4_SHIFT		12
-
-#define AL_ETH_MDIO_DELAY_PERIOD	1 /* micro seconds to wait when polling mdio status */
-#define AL_ETH_MDIO_DELAY_COUNT		150 /* number of times to poll */
-#define AL_ETH_S2M_UDMA_COMP_COAL_TIMEOUT	200 /* Rx descriptors coalescing timeout in SB clocks */
-
-#define AL_ETH_EPE_ENTRIES_NUM 26
-static struct al_eth_epe_p_reg_entry al_eth_epe_p_regs[AL_ETH_EPE_ENTRIES_NUM] = {
-	{ 0x0, 0x0, 0x0 },
-	{ 0x0, 0x0, 0x1 },
-	{ 0x0, 0x0, 0x2 },
-	{ 0x0, 0x0, 0x3 },
-	{ 0x18100, 0xFFFFF, 0x80000004 },
-	{ 0x188A8, 0xFFFFF, 0x80000005 },
-	{ 0x99100, 0xFFFFF, 0x80000006 },
-	{ 0x98100, 0xFFFFF, 0x80000007 },
-	{ 0x10800, 0x7FFFF, 0x80000008 },
-	{ 0x20000, 0x73FFF, 0x80000009 },
-	{ 0x20000, 0x70000, 0x8000000A },
-	{ 0x186DD, 0x7FFFF, 0x8000000B },
-	{ 0x30600, 0x7FF00, 0x8000000C },
-	{ 0x31100, 0x7FF00, 0x8000000D },
-	{ 0x32F00, 0x7FF00, 0x8000000E },
-	{ 0x32900, 0x7FF00, 0x8000000F },
-	{ 0x105DC, 0x7FFFF, 0x80010010 },
-	{ 0x188E5, 0x7FFFF, 0x80000011 },
-	{ 0x72000, 0x72000, 0x80000012 },
-	{ 0x70000, 0x72000, 0x80000013 },
-	{ 0x46558, 0x7FFFF, 0x80000001 },
-	{ 0x18906, 0x7FFFF, 0x80000015 },
-	{ 0x18915, 0x7FFFF, 0x80000016 },
-	{ 0x31B00, 0x7FF00, 0x80000017 },
-	{ 0x30400, 0x7FF00, 0x80000018 },
-	{ 0x0, 0x0, 0x8000001F }
-};
-
-
-static struct al_eth_epe_control_entry al_eth_epe_control_table[AL_ETH_EPE_ENTRIES_NUM] = {
-	{{ 0x2800000, 0x0, 0x0, 0x0, 0x1, 0x400000 }},
-	{{ 0x280004C, 0x746000, 0xA46030, 0xE00000, 0x2, 0x400000 }},
-	{{ 0x2800054, 0x746000, 0xA46030, 0x1600000, 0x2, 0x400000 }},
-	{{ 0x280005C, 0x746000, 0xA46030, 0x1E00000, 0x2, 0x400000 }},
-	{{ 0x2800042, 0xD42000, 0x0, 0x400000, 0x1010412, 0x400000 }},
-	{{ 0x2800042, 0xD42000, 0x0, 0x400000, 0x1010412, 0x400000 }},
-	{{ 0x2800042, 0xE42000, 0x0, 0x400000, 0x2020002, 0x400000 }},
-	{{ 0x2800042, 0xE42000, 0x0, 0x400000, 0x2020002, 0x400000 }},
-	{{ 0x280B046, 0x0, 0x6C1008, 0x0, 0x4, 0x406800 }},
-	{{ 0x2800049, 0xF44060, 0x1744080, 0x14404, 0x6, 0x400011 }},
-	{{ 0x2015049, 0xF44060, 0x1744080, 0x14404, 0x8080007, 0x400011 }},
-	{{ 0x280B046, 0xF60040, 0x6C1004, 0x2800000, 0x6, 0x406811 }},
-	{{ 0x2815042, 0x1F42000, 0x2042010, 0x1414460, 0x10100009, 0x40B800 }},
-	{{ 0x2815042, 0x1F42000, 0x2042010, 0x800000, 0x10100009, 0x40B800 }},
-	{{ 0x280B042, 0x0, 0x0, 0x430400, 0x4040009, 0x0 }},
-	{{ 0x2815580, 0x0, 0x0, 0x0, 0x4040005, 0x0 }},
-	{{ 0x280B000, 0x0, 0x0, 0x0, 0x1, 0x400000 }},
-	{{ 0x2800040, 0x174E000, 0x0, 0x0, 0xE, 0x406800 }},
-	{{ 0x280B000, 0x0, 0x0, 0x600000, 0x1, 0x406800 }},
-	{{ 0x280B000, 0x0, 0x0, 0xE00000, 0x1, 0x406800 }},
-	{{ 0x2800000, 0x0, 0x0, 0x0, 0x1, 0x400000 }},
-	{{ 0x280B046, 0x0, 0x0, 0x2800000, 0x7, 0x400000 }},
-	{{ 0x280B046, 0xF60040, 0x6C1004, 0x2800000, 0x6, 0x406811 }},
-	{{ 0x2815042, 0x1F43028, 0x2000000, 0xC00000, 0x10100009, 0x40B800 }},
-	{{ 0x2815400, 0x0, 0x0, 0x0, 0x4040005, 0x0 }},
-	{{ 0x2800000, 0x0, 0x0, 0x0, 0x1, 0x400000 }}
-};
-
-
-#define AL_ETH_IS_1G_MAC(mac_mode) (((mac_mode) == AL_ETH_MAC_MODE_RGMII) || ((mac_mode) == AL_ETH_MAC_MODE_SGMII))
-#define AL_ETH_IS_10G_MAC(mac_mode)	(((mac_mode) == AL_ETH_MAC_MODE_10GbE_Serial) ||	\
-					((mac_mode) == AL_ETH_MAC_MODE_10G_SGMII) ||		\
-					((mac_mode) == AL_ETH_MAC_MODE_SGMII_2_5G))
-#define AL_ETH_IS_25G_MAC(mac_mode) ((mac_mode) == AL_ETH_MAC_MODE_KR_LL_25G)
-
-static const char *al_eth_mac_mode_str(enum al_eth_mac_mode mode)
-{
-	switch(mode) {
-	case AL_ETH_MAC_MODE_RGMII:
-		return "RGMII";
-	case AL_ETH_MAC_MODE_SGMII:
-		return "SGMII";
-	case AL_ETH_MAC_MODE_SGMII_2_5G:
-		return "SGMII_2_5G";
-	case AL_ETH_MAC_MODE_10GbE_Serial:
-		return "KR";
-        case AL_ETH_MAC_MODE_KR_LL_25G:
-		return "KR_LL_25G";
-	case AL_ETH_MAC_MODE_10G_SGMII:
-		return "10G_SGMII";
-	case AL_ETH_MAC_MODE_XLG_LL_40G:
-		return "40G_LL";
-	case AL_ETH_MAC_MODE_XLG_LL_50G:
-		return "50G_LL";
-	case AL_ETH_MAC_MODE_XLG_LL_25G:
-		return "25G_LL";
-	default:
-		return "N/A";
-	}
-}
-
-/**
- * change and wait udma state
- *
- * @param dma the udma to change its state
- * @param new_state
- *
- * @return 0 on success. otherwise on failure.
- */
-static int al_udma_state_set_wait(struct al_udma *dma, enum al_udma_state new_state)
-{
-	enum al_udma_state state;
-	enum al_udma_state expected_state = new_state;
-	int count = 1000;
-	int rc;
-
-	rc = al_udma_state_set(dma, new_state);
-	if (rc != 0) {
-		al_warn("[%s] warn: failed to change state, error %d\n", dma->name, rc);
-		return rc;
-	}
-
-	if ((new_state == UDMA_NORMAL) || (new_state == UDMA_DISABLE))
-		expected_state = UDMA_IDLE;
-
-	do {
-		state = al_udma_state_get(dma);
-		if (state == expected_state)
-			break;
-		al_udelay(1);
-		if (count-- == 0) {
-			al_warn("[%s] warn: dma state didn't change to %s\n",
-				 dma->name, al_udma_states_name[new_state]);
-			return -ETIMEDOUT;
-		}
-	} while (1);
-	return 0;
-}
-
-static void al_eth_epe_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_epe_p_reg_entry *reg_entry,
-		struct al_eth_epe_control_entry *control_entry)
-{
-	al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_data, reg_entry->data);
-	al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_mask, reg_entry->mask);
-	al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_ctrl, reg_entry->ctrl);
-
-	al_reg_write32(&adapter->ec_regs_base->msp_c[idx].p_comp_data, reg_entry->data);
-	al_reg_write32(&adapter->ec_regs_base->msp_c[idx].p_comp_mask, reg_entry->mask);
-	al_reg_write32(&adapter->ec_regs_base->msp_c[idx].p_comp_ctrl, reg_entry->ctrl);
-
-	/*control table  0*/
-	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_6,
-			control_entry->data[5]);
-	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_2,
-			control_entry->data[1]);
-	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_3,
-			control_entry->data[2]);
-	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_4,
-			control_entry->data[3]);
-	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_5,
-			control_entry->data[4]);
-	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_1,
-			control_entry->data[0]);
-
-	/*control table 1*/
-	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_6,
-			control_entry->data[5]);
-	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_2,
-			control_entry->data[1]);
-	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_3,
-			control_entry->data[2]);
-	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_4,
-			control_entry->data[3]);
-	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_5,
-			control_entry->data[4]);
-	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_1,
-			control_entry->data[0]);
-}
-
-static void al_eth_epe_init(struct al_hal_eth_adapter *adapter)
-{
-	int idx;
-
-	if (adapter->enable_rx_parser == 0) {
-		al_dbg("eth [%s]: disable rx parser\n", adapter->name);
-
-		al_reg_write32(&adapter->ec_regs_base->epe[0].res_def, 0x08000000);
-		al_reg_write32(&adapter->ec_regs_base->epe[0].res_in, 0x7);
-
-		al_reg_write32(&adapter->ec_regs_base->epe[1].res_def, 0x08000000);
-		al_reg_write32(&adapter->ec_regs_base->epe[1].res_in, 0x7);
-
-		return;
-	}
-	al_dbg("eth [%s]: enable rx parser\n", adapter->name);
-	for (idx = 0; idx < AL_ETH_EPE_ENTRIES_NUM; idx++)
-		al_eth_epe_entry_set(adapter, idx, &al_eth_epe_p_regs[idx], &al_eth_epe_control_table[idx]);
-
-	al_reg_write32(&adapter->ec_regs_base->epe[0].res_def, 0x08000080);
-	al_reg_write32(&adapter->ec_regs_base->epe[0].res_in, 0x7);
-
-	al_reg_write32(&adapter->ec_regs_base->epe[1].res_def, 0x08000080);
-	al_reg_write32(&adapter->ec_regs_base->epe[1].res_in, 0);
-
-	/* header length as function of 4 bits value, for GRE, when C bit is set, the header len should be increase by 4*/
-	al_reg_write32(&adapter->ec_regs_base->epe_h[8].hdr_len, (4 << 16) | 4);
-
-	/* select the outer information when writing the rx descriptor (l3 protocol index etc) */
-	al_reg_write32(&adapter->ec_regs_base->rfw.meta, EC_RFW_META_L3_LEN_CALC);
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.checksum, EC_RFW_CHECKSUM_HDR_SEL);
-}
-
-/**
- * read 40G MAC registers (indirect access)
- *
- * @param adapter pointer to the private structure
- * @param reg_addr address in the an registers
- *
- * @return the register value
- */
-static uint32_t al_eth_40g_mac_reg_read(
-			struct al_hal_eth_adapter *adapter,
-			uint32_t reg_addr)
-{
-	uint32_t val;
-
-	/* indirect access */
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, reg_addr);
-	val = al_reg_read32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data);
-
-	al_dbg("[%s]: %s - reg %d. val 0x%x",
-	       adapter->name, __func__, reg_addr, val);
-
-	return val;
-}
-
-/**
- * write 40G MAC registers (indirect access)
- *
- * @param adapter pointer to the private structure
- * @param reg_addr address in the an registers
- * @param reg_data value to write to the register
- *
- */
-static void al_eth_40g_mac_reg_write(
-			struct al_hal_eth_adapter *adapter,
-			uint32_t reg_addr,
-			uint32_t reg_data)
-{
-	/* indirect access */
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, reg_addr);
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, reg_data);
-
-	al_dbg("[%s]: %s - reg %d. val 0x%x",
-	       adapter->name, __func__, reg_addr, reg_data);
-}
-
-/**
- * read 40G PCS registers (indirect access)
- *
- * @param adapter pointer to the private structure
- * @param reg_addr address in the an registers
- *
- * @return the register value
- */
-static uint32_t al_eth_40g_pcs_reg_read(
-			struct al_hal_eth_adapter *adapter,
-			uint32_t reg_addr)
-{
-	uint32_t val;
-
-	/* indirect access */
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, reg_addr);
-	val = al_reg_read32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data);
-
-	al_dbg("[%s]: %s - reg %d. val 0x%x",
-	       adapter->name, __func__, reg_addr, val);
-
-	return val;
-}
-
-/**
- * write 40G PCS registers (indirect access)
- *
- * @param adapter pointer to the private structure
- * @param reg_addr address in the an registers
- * @param reg_data value to write to the register
- *
- */
-static void al_eth_40g_pcs_reg_write(
-			struct al_hal_eth_adapter *adapter,
-			uint32_t reg_addr,
-			uint32_t reg_data)
-{
-	/* indirect access */
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, reg_addr);
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, reg_data);
-
-	al_dbg("[%s]: %s - reg %d. val 0x%x",
-	       adapter->name, __func__, reg_addr, reg_data);
-}
-
-/*****************************API Functions  **********************************/
-/*adapter management */
-/**
- * initialize the ethernet adapter's DMA
- */
-int al_eth_adapter_init(struct al_hal_eth_adapter *adapter, struct al_eth_adapter_params *params)
-{
-	struct al_udma_params udma_params;
-	struct al_udma_m2s_pkt_len_conf conf;
-	int i;
-	uint32_t reg;
-	int rc;
-
-	al_dbg("eth [%s]: initialize controller's UDMA. id = %d\n", params->name, params->udma_id);
-	al_dbg("eth [%s]: UDMA base regs: %p\n", params->name, params->udma_regs_base);
-	al_dbg("eth [%s]: EC base regs: %p\n", params->name, params->ec_regs_base);
-	al_dbg("eth [%s]: MAC base regs: %p\n", params->name, params->mac_regs_base);
-	al_dbg("eth [%s]: enable_rx_parser: %x\n", params->name, params->enable_rx_parser);
-
-	adapter->name = params->name;
-	adapter->rev_id = params->rev_id;
-	adapter->udma_id = params->udma_id;
-	adapter->udma_regs_base = params->udma_regs_base;
-	adapter->ec_regs_base = (struct al_ec_regs __iomem*)params->ec_regs_base;
-	adapter->mac_regs_base = (struct al_eth_mac_regs __iomem*)params->mac_regs_base;
-	adapter->unit_regs = (struct unit_regs __iomem *)params->udma_regs_base;
-	adapter->enable_rx_parser = params->enable_rx_parser;
-	adapter->serdes_lane = params->serdes_lane;
-	adapter->ec_ints_base = (uint8_t __iomem *)adapter->ec_regs_base + 0x1c00;
-	adapter->mac_ints_base = (struct interrupt_controller_ctrl __iomem *)
-			((uint8_t __iomem *)adapter->mac_regs_base + 0x800);
-
-	/* initialize Tx udma */
-	udma_params.udma_regs_base = adapter->unit_regs;
-	udma_params.type = UDMA_TX;
-	udma_params.num_of_queues = AL_ETH_UDMA_TX_QUEUES;
-	udma_params.name = "eth tx";
-	rc = al_udma_init(&adapter->tx_udma, &udma_params);
-
-	if (rc != 0) {
-		al_err("failed to initialize %s, error %d\n",
-			 udma_params.name, rc);
-		return rc;
-	}
-	rc = al_udma_state_set_wait(&adapter->tx_udma, UDMA_NORMAL);
-	if (rc != 0) {
-		al_err("[%s]: failed to change state, error %d\n",
-			 udma_params.name, rc);
-		return rc;
-	}
-	/* initialize Rx udma */
-	udma_params.udma_regs_base = adapter->unit_regs;
-	udma_params.type = UDMA_RX;
-	udma_params.num_of_queues = AL_ETH_UDMA_RX_QUEUES;
-	udma_params.name = "eth rx";
-	rc = al_udma_init(&adapter->rx_udma, &udma_params);
-
-	if (rc != 0) {
-		al_err("failed to initialize %s, error %d\n",
-			 udma_params.name, rc);
-		return rc;
-	}
-
-	rc = al_udma_state_set_wait(&adapter->rx_udma, UDMA_NORMAL);
-	if (rc != 0) {
-		al_err("[%s]: failed to change state, error %d\n",
-			 udma_params.name, rc);
-		return rc;
-	}
-	al_dbg("eth [%s]: controller's UDMA successfully initialized\n",
-		 params->name);
-
-	/* set max packet size to 1M (for TSO) */
-	conf.encode_64k_as_zero = AL_TRUE;
-	conf.max_pkt_size = 0xfffff;
-	al_udma_m2s_packet_size_cfg_set(&adapter->tx_udma, &conf);
-
-	/* set m2s (tx) max descriptors to max data buffers number and one for
-	 * meta descriptor
-	 */
-	al_udma_m2s_max_descs_set(&adapter->tx_udma, AL_ETH_PKT_MAX_BUFS + 1);
-
-	/* set s2m (rx) max descriptors to max data buffers */
-	al_udma_s2m_max_descs_set(&adapter->rx_udma, AL_ETH_PKT_MAX_BUFS);
-
-	/* set s2m burst lenght when writing completion descriptors to 64 bytes
-	 */
-	al_udma_s2m_compl_desc_burst_config(&adapter->rx_udma, 64);
-
-	/* if pointer to ec regs provided, then init the tx meta cache of this udma*/
-	if (adapter->ec_regs_base != NULL) {
-		// INIT TX CACHE TABLE:
-		for (i = 0; i < 4; i++) {
-			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_addr, i + (adapter->udma_id * 4));
-			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_1, 0x00000000);
-			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_2, 0x00000000);
-			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_3, 0x00000000);
-			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_4, 0x00000000);
-		}
-	}
-	// only udma 0 allowed to init ec
-	if (adapter->udma_id != 0) {
-		return 0;
-	}
-	/* enable Ethernet controller: */
-	/* enable internal machines*/
-	al_reg_write32(&adapter->ec_regs_base->gen.en, 0xffffffff);
-	al_reg_write32(&adapter->ec_regs_base->gen.fifo_en, 0xffffffff);
-
-	if (adapter->rev_id > AL_ETH_REV_ID_0) {
-		/* enable A0 descriptor structure */
-		al_reg_write32_masked(&adapter->ec_regs_base->gen.en_ext,
-				      EC_GEN_EN_EXT_CACHE_WORD_SPLIT,
-				      EC_GEN_EN_EXT_CACHE_WORD_SPLIT);
-
-		/* use mss value in the descriptor */
-		al_reg_write32(&adapter->ec_regs_base->tso.cfg_add_0,
-						EC_TSO_CFG_ADD_0_MSS_SEL);
-
-		/* enable tunnel TSO */
-		al_reg_write32(&adapter->ec_regs_base->tso.cfg_tunnel,
-						(EC_TSO_CFG_TUNNEL_EN_TUNNEL_TSO |
-						 EC_TSO_CFG_TUNNEL_EN_UDP_CHKSUM |
-						 EC_TSO_CFG_TUNNEL_EN_UDP_LEN |
-						 EC_TSO_CFG_TUNNEL_EN_IPV6_PLEN |
-						 EC_TSO_CFG_TUNNEL_EN_IPV4_CHKSUM |
-						 EC_TSO_CFG_TUNNEL_EN_IPV4_IDEN |
-						 EC_TSO_CFG_TUNNEL_EN_IPV4_TLEN));
-	}
-
-	/* swap input byts from MAC RX */
-	al_reg_write32(&adapter->ec_regs_base->mac.gen, 0x00000001);
-	/* swap output bytes to MAC TX*/
-	al_reg_write32(&adapter->ec_regs_base->tmi.tx_cfg, EC_TMI_TX_CFG_EN_FWD_TO_RX|EC_TMI_TX_CFG_SWAP_BYTES);
-
-	/* TODO: check if we need this line*/
-	al_reg_write32(&adapter->ec_regs_base->tfw_udma[0].fwd_dec, 0x000003fb);
-
-	/* RFW configuration: default 0 */
-	al_reg_write32(&adapter->ec_regs_base->rfw_default[0].opt_1, 0x00000001);
-
-	/* VLAN table address*/
-	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_addr, 0x00000000);
-	/* VLAN table data*/
-	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_data, 0x00000000);
-	/* HASH config (select toeplitz and bits 7:0 of the thash result, enable
-	 * symmetric hash) */
-	al_reg_write32(&adapter->ec_regs_base->rfw.thash_cfg_1,
-			EC_RFW_THASH_CFG_1_ENABLE_IP_SWAP |
-			EC_RFW_THASH_CFG_1_ENABLE_PORT_SWAP);
-
-	al_eth_epe_init(adapter);
-
-	/* disable TSO padding and use mac padding instead */
-	reg = al_reg_read32(&adapter->ec_regs_base->tso.in_cfg);
-	reg &= ~0x7F00; /*clear bits 14:8 */
-	al_reg_write32(&adapter->ec_regs_base->tso.in_cfg, reg);
-
-	return 0;
-}
-
-/*****************************API Functions  **********************************/
-/*adapter management */
-/**
- * enable the ec and mac interrupts
- */
-int al_eth_ec_mac_ints_config(struct al_hal_eth_adapter *adapter)
-{
-
-	al_dbg("eth [%s]: enable ethernet and mac interrupts\n", adapter->name);
-
-	// only udma 0 allowed to init ec
-	if (adapter->udma_id != 0)
-		return -EPERM;
-
-	/* enable mac ints */
-	al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_A,
-		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
-	al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_B,
-		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
-	al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_C,
-		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
-	al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_D,
-		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
-
-	/* unmask MAC int */
-	al_iofic_unmask(adapter->ec_ints_base, AL_INT_GROUP_A, 8);
-
-	/* enable ec interrupts */
-	al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_A,
-		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
-	al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_B,
-		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
-	al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_C,
-		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
-	al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_D,
-		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
-
-	/* eee active */
-	al_iofic_unmask(adapter->mac_ints_base, AL_INT_GROUP_B, AL_BIT(14));
-
-	al_iofic_unmask(adapter->unit_regs, AL_INT_GROUP_D, AL_BIT(11));
-	return 0;
-}
-
-/**
- * ec and mac interrupt service routine
- * read and print asserted interrupts
- *
- * @param adapter pointer to the private structure
- *
- * @return 0 on success. otherwise on failure.
- */
-int al_eth_ec_mac_isr(struct al_hal_eth_adapter *adapter)
-{
-	uint32_t cause;
-	al_dbg("[%s]: ethernet interrupts handler\n", adapter->name);
-
-	// only udma 0 allowed to init ec
-	if (adapter->udma_id != 0)
-		return -EPERM;
-
-	/* read ec cause */
-	cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_A);
-	al_dbg("[%s]: ethernet group A cause 0x%08x\n", adapter->name, cause);
-	if (cause & 1)
-	{
-		cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_A);
-		al_dbg("[%s]: mac group A cause 0x%08x\n", adapter->name, cause);
-
-		cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_B);
-		al_dbg("[%s]: mac group B cause 0x%08x\n", adapter->name, cause);
-
-		cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_C);
-		al_dbg("[%s]: mac group C cause 0x%08x\n", adapter->name, cause);
-
-		cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_D);
-		al_dbg("[%s]: mac group D cause 0x%08x\n", adapter->name, cause);
-	}
-	cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_B);
-	al_dbg("[%s]: ethernet group B cause 0x%08x\n", adapter->name, cause);
-	cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_C);
-	al_dbg("[%s]: ethernet group C cause 0x%08x\n", adapter->name, cause);
-	cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_D);
-	al_dbg("[%s]: ethernet group D cause 0x%08x\n", adapter->name, cause);
-
-	return 0;
-}
-
-/**
- * stop the DMA of the ethernet adapter
- */
-int al_eth_adapter_stop(struct al_hal_eth_adapter *adapter)
-{
-	int rc;
-
-	al_dbg("eth [%s]: stop controller's UDMA\n", adapter->name);
-
-	/* disable Tx dma*/
-	rc = al_udma_state_set_wait(&adapter->tx_udma, UDMA_DISABLE);
-	if (rc != 0) {
-		al_warn("[%s] warn: failed to change state, error %d\n",
-			 adapter->tx_udma.name, rc);
-		return rc;
-	}
-
-	al_dbg("eth [%s]: controller's TX UDMA stopped\n",
-		 adapter->name);
-	/* disable Rx dma*/
-	rc = al_udma_state_set_wait(&adapter->rx_udma, UDMA_DISABLE);
-	if (rc != 0) {
-		al_warn("[%s] warn: failed to change state, error %d\n",
-			 adapter->rx_udma.name, rc);
-		return rc;
-	}
-
-	al_dbg("eth [%s]: controller's RX UDMA stopped\n",
-		 adapter->name);
-	return 0;
-}
-
-int al_eth_adapter_reset(struct al_hal_eth_adapter *adapter)
-{
-	al_dbg("eth [%s]: reset controller's UDMA\n", adapter->name);
-
-	return -EPERM;
-}
-
-/* Q management */
-/**
- * Configure and enable a queue ring
- */
-int al_eth_queue_config(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid,
-			     struct al_udma_q_params *q_params)
-{
-	struct al_udma *udma;
-	int rc;
-
-	al_dbg("eth [%s]: config UDMA %s queue %d\n", adapter->name,
-		 type == UDMA_TX ? "Tx" : "Rx", qid);
-
-	if (type == UDMA_TX) {
-		udma = &adapter->tx_udma;
-	} else {
-		udma = &adapter->rx_udma;
-	}
-
-	q_params->adapter_rev_id = adapter->rev_id;
-
-	rc = al_udma_q_init(udma, qid, q_params);
-
-	if (rc)
-		return rc;
-
-	if (type == UDMA_RX) {
-		rc = al_udma_s2m_q_compl_coal_config(&udma->udma_q[qid],
-				AL_TRUE, AL_ETH_S2M_UDMA_COMP_COAL_TIMEOUT);
-
-		al_assert(q_params->cdesc_size <= 32);
-
-		if (q_params->cdesc_size > 16)
-			al_reg_write32_masked(&adapter->ec_regs_base->rfw.out_cfg,
-					EC_RFW_OUT_CFG_META_CNT_MASK, 2);
-	}
-	return rc;
-}
-
-int al_eth_queue_enable(struct al_hal_eth_adapter *adapter __attribute__((__unused__)),
-			enum al_udma_type type __attribute__((__unused__)),
-			uint32_t qid __attribute__((__unused__)))
-{
-	return -EPERM;
-}
-int al_eth_queue_disable(struct al_hal_eth_adapter *adapter __attribute__((__unused__)),
-			 enum al_udma_type type __attribute__((__unused__)),
-			 uint32_t qid __attribute__((__unused__)))
-{
-	return -EPERM;
-}
-
-/* MAC layer */
-int al_eth_rx_pkt_limit_config(struct al_hal_eth_adapter *adapter, uint32_t min_rx_len, uint32_t max_rx_len)
-{
-	al_assert(max_rx_len <= AL_ETH_MAX_FRAME_LEN);
-
-	/* EC minimum packet length [bytes] in RX */
-	al_reg_write32(&adapter->ec_regs_base->mac.min_pkt, min_rx_len);
-	/* EC maximum packet length [bytes] in RX */
-	al_reg_write32(&adapter->ec_regs_base->mac.max_pkt, max_rx_len);
-
-	if (adapter->rev_id > AL_ETH_REV_ID_2) {
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, min_rx_len);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, max_rx_len);
-	}
-
-	/* configure the MAC's max rx length, add 16 bytes so the packet get
-	 * trimmed by the EC/Async_fifo rather by the MAC
-	*/
-	if (AL_ETH_IS_1G_MAC(adapter->mac_mode))
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.frm_len, max_rx_len + 16);
-	else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode))
-		/* 10G MAC control register  */
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.frm_len, (max_rx_len + 16));
-	else
-		al_eth_40g_mac_reg_write(adapter, ETH_MAC_GEN_V3_MAC_40G_FRM_LENGTH_ADDR, (max_rx_len + 16));
-
-	return 0;
-}
-
-/* configure the mac media type. */
-int al_eth_mac_config(struct al_hal_eth_adapter *adapter, enum al_eth_mac_mode mode)
-{
-	switch(mode) {
-	case AL_ETH_MAC_MODE_RGMII:
-		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210);
-
-		/* 1G MAC control register */
-		/* bit[0]  - TX_ENA - zeroed by default. Should be asserted by al_eth_mac_start
-		 * bit[1]  - RX_ENA - zeroed by default. Should be asserted by al_eth_mac_start
-		 * bit[3]  - ETH_SPEED - zeroed to enable 10/100 Mbps Ethernet
-		 * bit[4]  - PROMIS_EN - asserted to enable MAC promiscuous mode
-		 * bit[23] - CNTL_FRM-ENA - asserted to enable control frames
-		 * bit[24] - NO_LGTH_CHECK - asserted to disable length checks, which is done in the controller
-		 */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x01800010);
-
-		/* RX_SECTION_EMPTY,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_empty, 0x00000000);
-		/* RX_SECTION_FULL,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_full, 0x0000000c); /* must be larger than almost empty */
-		/* RX_ALMOST_EMPTY,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_empty, 0x00000008);
-		/* RX_ALMOST_FULL,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_full, 0x00000008);
-
-
-		/* TX_SECTION_EMPTY,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_empty, 0x00000008); /* 8 ? */
-		/* TX_SECTION_FULL, 0 - store and forward, */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_full, 0x0000000c);
-		/* TX_ALMOST_EMPTY,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_empty, 0x00000008);
-		/* TX_ALMOST_FULL,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_full, 0x00000008);
-
-		/* XAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000000);
-
-		/* 1G MACSET 1G */
-		/* taking sel_1000/sel_10 inputs from rgmii PHY, and not from register.
-		 * disabling magic_packets detection in mac */
-		al_reg_write32(&adapter->mac_regs_base->gen.mac_1g_cfg, 0x00000002);
-		/* RGMII set 1G */
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910);
-		al_reg_write32(&adapter->mac_regs_base->gen.rgmii_sel, 0xF);
-		break;
-	case AL_ETH_MAC_MODE_SGMII:
-		if (adapter->rev_id > AL_ETH_REV_ID_2) {
-			/* configure and enable the ASYNC FIFO between the MACs and the EC */
-			/* TX min packet size */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010);
-			/* TX max packet size */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
-			/* TX input bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
-			/* TX output bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020);
-			/* TX Valid/ready configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000121);
-			/* RX min packet size */
-			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
-			/* RX max packet size */
-			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
-			/* RX input bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020);
-			/* RX output bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
-			/* RX Valid/ready configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000212);
-			/* V3 additional MAC selection */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000001);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000);
-			/* ASYNC FIFO ENABLE */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
-			/* Timestamp_configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.spare,
-					ETH_MAC_GEN_V3_SPARE_CHICKEN_DISABLE_TIMESTAMP_STRETCH);
-		}
-
-		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40053210);
-
-		/* 1G MAC control register */
-		/* bit[0]  - TX_ENA - zeroed by default. Should be asserted by al_eth_mac_start
-		 * bit[1]  - RX_ENA - zeroed by default. Should be asserted by al_eth_mac_start
-		 * bit[3]  - ETH_SPEED - zeroed to enable 10/100 Mbps Ethernet
-		 * bit[4]  - PROMIS_EN - asserted to enable MAC promiscuous mode
-		 * bit[23] - CNTL_FRM-ENA - asserted to enable control frames
-		 * bit[24] - NO_LGTH_CHECK - asserted to disable length checks, which is done in the controller
-		 */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x01800010);
-
-		/* RX_SECTION_EMPTY,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_empty, 0x00000000);
-		/* RX_SECTION_FULL,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_full, 0x0000000c); /* must be larger than almost empty */
-		/* RX_ALMOST_EMPTY,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_empty, 0x00000008);
-		/* RX_ALMOST_FULL,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_full, 0x00000008);
-
-
-		/* TX_SECTION_EMPTY,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_empty, 0x00000008); /* 8 ? */
-		/* TX_SECTION_FULL, 0 - store and forward, */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_full, 0x0000000c);
-		/* TX_ALMOST_EMPTY,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_empty, 0x00000008);
-		/* TX_ALMOST_FULL,  */
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_full, 0x00000008);
-
-		/* XAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x000000c0);
-
-		/* 1G MACSET 1G */
-		/* taking sel_1000/sel_10 inputs from rgmii_converter, and not from register.
-		 * disabling magic_packets detection in mac */
-		al_reg_write32(&adapter->mac_regs_base->gen.mac_1g_cfg, 0x00000002);
-		/* SerDes configuration */
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
-
-		// FAST AN -- Testing only
-#ifdef AL_HAL_ETH_FAST_AN
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000012);
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x00000040);
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000013);
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x00000000);
-#endif
-
-		/* Setting PCS i/f mode to SGMII (instead of default 1000Base-X) */
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000014);
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x0000000b);
-		/* setting dev_ability to have speed of 1000Mb, [11:10] = 2'b10 */
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000004);
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x000009A0);
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
-				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
-				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
-		break;
-
-	case AL_ETH_MAC_MODE_SGMII_2_5G:
-		if (adapter->rev_id > AL_ETH_REV_ID_2) {
-			/* configure and enable the ASYNC FIFO between the MACs and the EC */
-			/* TX min packet size */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010);
-			/* TX max packet size */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
-			/* TX input bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
-			/* TX output bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020);
-			/* TX Valid/ready configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
-			/* RX input bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020);
-			/* RX output bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
-			/* RX Valid/ready configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012);
-			/* V3 additional MAC selection */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000050);
-			/* ASYNC FIFO ENABLE */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
-		}
-
-		/* MAC register file */
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022830);
-		/* XAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000001);
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, 0x00000028);
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.control, 0x00001140);
-		/* RXAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
-				      ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910);
-		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
-
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
-				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
-				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
-		break;
-
-	case AL_ETH_MAC_MODE_10GbE_Serial:
-		if (adapter->rev_id > AL_ETH_REV_ID_2) {
-			/* configure and enable the ASYNC FIFO between the MACs and the EC */
-			/* TX min packet size */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010);
-			/* TX max packet size */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
-			/* TX input bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
-			/* TX output bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020);
-			/* TX Valid/ready configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
-			/* RX min packet size */
-			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
-			/* RX max packet size */
-			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
-			/* RX input bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020);
-			/* RX output bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
-			/* RX Valid/ready configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012);
-			/* V3 additional MAC selection */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000050);
-			/* ASYNC FIFO ENABLE */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
-		}
-
-		/* MAC register file */
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810);
-		/* XAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005);
-		/* RXAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1);
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
-					~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910);
-		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
-
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
-				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
-				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
-		break;
-
-	case AL_ETH_MAC_MODE_KR_LL_25G:
-			/* select 25G SERDES lane 0 and lane 1 */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0002110f);
-
-		if (adapter->rev_id > AL_ETH_REV_ID_2) {
-			/* configure and enable the ASYNC FIFO between the MACs and the EC */
-			/* TX min packet size */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010);
-			/* TX max packet size */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
-			/* TX input bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
-			/* TX output bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020);
-			/* TX Valid/ready configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
-			/* RX min packet size */
-			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
-			/* RX max packet size */
-			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
-			/* RX input bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020);
-			/* RX output bus configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
-			/* RX Valid/ready configuration */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012);
-			/* V3 additional MAC selection */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x000000a0);
-			/* ASYNC FIFO ENABLE */
-			al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
-		}
-
-		/* MAC register file */
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810);
-		/* XAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005);
-		/* RXAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1);
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
-
-		if (adapter->serdes_lane == 0)
-			al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
-					~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910);
-		else
-			al_reg_write32(&adapter->mac_regs_base->gen.mux_sel, 0x00077910);
-
-		if (adapter->serdes_lane == 0)
-			al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210);
-		else
-			al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10000101);
-
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
-
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
-				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
-				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
-
-		if (adapter->serdes_lane == 1)
-			al_reg_write32(&adapter->mac_regs_base->gen.los_sel, 0x101);
-
-
-		break;
-
-	case AL_ETH_MAC_MODE_10G_SGMII:
-		/* MAC register file */
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810);
-
-		/* XAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000001);
-
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, 0x0000002b);
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.control, 0x00009140);
-		// FAST AN -- Testing only
-#ifdef AL_HAL_ETH_FAST_AN
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.link_timer_lo, 0x00000040);
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.link_timer_hi, 0x00000000);
-#endif
-
-		/* RXAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
-					~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910);
-		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
-
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
-				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
-				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
-		break;
-
-	case AL_ETH_MAC_MODE_XLG_LL_40G:
-		/* configure and enable the ASYNC FIFO between the MACs and the EC */
-		/* TX min packet size */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010);
-		/* TX max packet size */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
-		/* TX input bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
-		/* TX output bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040);
-		/* TX Valid/ready configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
-		/* RX min packet size */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
-		/* RX max packet size */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
-		/* RX input bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040);
-		/* RX output bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
-		/* RX Valid/ready configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112);
-		/* V3 additional MAC selection */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000);
-		/* ASYNC FIFO ENABLE */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
-
-		/* cmd_cfg */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810);
-		/* speed_ability //Read-Only */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */
-		/* 40G capable */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */
-
-#ifdef AL_HAL_ETH_FAST_AN
-		al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023);
-		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c);
-		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c);
-
-#endif
-
-		/* XAUI MAC control register */
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
-					~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x06883910);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f);
-
-		/* MAC register file */
-/*		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); */
-		/* XAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005);
-		/* RXAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1);
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
-/*		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910); *//* XLG_LL_40G change */
-		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); *//* XLG_LL_40G change */
-/*		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); *//* XLG_LL_40G change */
-
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
-				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
-				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
-		break;
-
-	case AL_ETH_MAC_MODE_XLG_LL_25G:
-		/* xgmii_mode: 0=xlgmii, 1=xgmii */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x0080);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x00000001);
-
-		/* configure and enable the ASYNC FIFO between the MACs and the EC */
-		/* TX min packet size */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010);
-		/* TX max packet size */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
-		/* TX input bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
-		/* TX output bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040);
-		/* TX Valid/ready configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
-		/* RX min packet size */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
-		/* RX max packet size */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
-		/* RX input bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040);
-		/* RX output bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
-		/* RX Valid/ready configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112);
-		/* V3 additional MAC selection */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000);
-		/* ASYNC FIFO ENABLE */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
-
-		/* cmd_cfg */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810);
-		/* speed_ability //Read-Only */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */
-		/* 40G capable */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */
-
-		/* select the 25G serdes for lanes 0/1 */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0002110f);
-		/* configure the PCS to work with 2 lanes */
-		/* configure which two of the 4 PCS Lanes (VL) are combined to one RXLAUI lane */
-		/* use VL 0-2 for RXLAUI lane 0, use VL 1-3 for RXLAUI lane 1 */
-		al_eth_40g_pcs_reg_write(adapter, 0x00010008, 0x0d80);
-		/* configure the PCS to work 32 bit interface */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_cfg, 0x00440000);
-
-		/* disable MLD and move to clause 49 PCS: */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0xE);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0);
-
-#ifdef AL_HAL_ETH_FAST_AN
-		al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023);
-		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c);
-		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c);
-#endif
-
-		/* XAUI MAC control register */
-		if (adapter->serdes_lane == 0)
-			al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
-					      ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x06883910);
-		else
-			al_reg_write32(&adapter->mac_regs_base->gen.mux_sel, 0x06803950);
-
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f);
-
-		/* XAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005);
-		/* RXAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1);
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
-		if (adapter->serdes_lane == 0)
-			al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210);
-		else
-			al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10000101);
-
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
-					ETH_MAC_GEN_LED_CFG_SEL_MASK,
-					ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
-
-		if (adapter->serdes_lane == 1)
-			al_reg_write32(&adapter->mac_regs_base->gen.los_sel, 0x101);
-
-		break;
-
-	case AL_ETH_MAC_MODE_XLG_LL_50G:
-
-		/* configure and enable the ASYNC FIFO between the MACs and the EC */
-		/* TX min packet size */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000010);
-		/* TX max packet size */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
-		/* TX input bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
-		/* TX output bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040);
-		/* TX Valid/ready configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
-		/* RX min packet size */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
-		/* RX max packet size */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
-		/* RX input bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040);
-		/* RX output bus configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
-		/* RX Valid/ready configuration */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112);
-		/* V3 additional MAC selection */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000);
-		/* ASYNC FIFO ENABLE */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
-
-		/* cmd_cfg */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008);
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810);
-		/* speed_ability //Read-Only */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */
-		/* 40G capable */
-		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */
-
-		/* select the 25G serdes for lanes 0/1 */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0382110F);
-		/* configure the PCS to work with 2 lanes */
-		/* configure which two of the 4 PCS Lanes (VL) are combined to one RXLAUI lane */
-		/* use VL 0-2 for RXLAUI lane 0, use VL 1-3 for RXLAUI lane 1 */
-		al_eth_40g_pcs_reg_write(adapter, 0x00010008, 0x0d81);
-		/* configure the PCS to work 32 bit interface */
-		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_cfg, 0x00440000);
-
-
-#ifdef AL_HAL_ETH_FAST_AN
-		al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023);
-		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c);
-		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c);
-#endif
-
-		/* XAUI MAC control register */
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x06883910);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f);
-
-		/* MAC register file */
-/*		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); */
-		/* XAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005);
-		/* RXAUI MAC control register */
-		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
-		al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1);
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
-		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
-/*		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910); *//* XLG_LL_40G change */
-		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210);
-/*		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); *//* XLG_LL_40G change */
-/*		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); *//* XLG_LL_40G change */
-
-		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
-				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
-				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
-		break;
-
-
-	default:
-		al_err("Eth: unsupported MAC mode %d", mode);
-		return -EPERM;
-	}
-	adapter->mac_mode = mode;
-	al_info("configured MAC to %s mode:\n", al_eth_mac_mode_str(mode));
-
-	return 0;
-}
-
-/* start the mac */
-int al_eth_mac_start(struct al_hal_eth_adapter *adapter)
-{
-	if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
-		/* 1G MAC control register */
-		al_reg_write32_masked(&adapter->mac_regs_base->mac_1g.cmd_cfg,
-				ETH_1G_MAC_CMD_CFG_TX_ENA | ETH_1G_MAC_CMD_CFG_RX_ENA,
-				ETH_1G_MAC_CMD_CFG_TX_ENA | ETH_1G_MAC_CMD_CFG_RX_ENA);
-	} else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
-		/* 10G MAC control register  */
-		al_reg_write32_masked(&adapter->mac_regs_base->mac_10g.cmd_cfg,
-				ETH_10G_MAC_CMD_CFG_TX_ENA | ETH_10G_MAC_CMD_CFG_RX_ENA,
-				ETH_10G_MAC_CMD_CFG_TX_ENA | ETH_10G_MAC_CMD_CFG_RX_ENA);
-	} else {
-		uint32_t cmd_cfg;
-
-		cmd_cfg = al_eth_40g_mac_reg_read(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR);
-
-		cmd_cfg |= (ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_TX_ENA |
-			    ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_RX_ENA);
-
-		al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR,
-				cmd_cfg);
-	}
-
-	return 0;
-}
-
-/* stop the mac */
-int al_eth_mac_stop(struct al_hal_eth_adapter *adapter)
-{
-	if (AL_ETH_IS_1G_MAC(adapter->mac_mode))
-		/* 1G MAC control register */
-		al_reg_write32_masked(&adapter->mac_regs_base->mac_1g.cmd_cfg,
-				ETH_1G_MAC_CMD_CFG_TX_ENA | ETH_1G_MAC_CMD_CFG_RX_ENA,
-				0);
-	else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode))
-		/* 10G MAC control register  */
-		al_reg_write32_masked(&adapter->mac_regs_base->mac_10g.cmd_cfg,
-				ETH_10G_MAC_CMD_CFG_TX_ENA | ETH_10G_MAC_CMD_CFG_RX_ENA,
-				0);
-	else {
-		uint32_t cmd_cfg;
-
-		cmd_cfg = al_eth_40g_mac_reg_read(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR);
-
-		cmd_cfg &= ~(ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_TX_ENA |
-			    ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_RX_ENA);
-
-		al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR,
-				cmd_cfg);
-	}
-
-	return 0;
-}
-
-void al_eth_gearbox_reset(struct al_hal_eth_adapter *adapter, al_bool tx_reset, al_bool rx_reset)
-{
-	uint32_t reg, orig_val;
-
-	/* Gearbox is exist only from revision 3 */
-	al_assert(adapter->rev_id > AL_ETH_REV_ID_2);
-
-	orig_val = al_reg_read32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl);
-	reg = orig_val;
-
-	if (tx_reset) {
-		reg |= (ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_TX_25_GS_SW_RESET |
-			ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_TX_25_GS_SW_RESET);
-	}
-
-	if (rx_reset) {
-		reg |= (ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_RX_25_GS_SW_RESET |
-			ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_RX_25_GS_SW_RESET);
-	}
-
-	al_dbg("%s: perform gearbox reset (Tx %d, Rx %d) \n", __func__, tx_reset, rx_reset);
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, reg);
-
-	al_udelay(10);
-
-	al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, orig_val);
-}
-
-int al_eth_fec_enable(struct al_hal_eth_adapter *adapter, al_bool enable)
-{
-	if (adapter->rev_id <= AL_ETH_REV_ID_2)
-		return -1;
-
-	if (enable)
-		al_reg_write32_masked(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg,
-					(ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_RX |
-					 ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_TX),
-					(ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_RX |
-					 ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_TX));
-	else
-		al_reg_write32_masked(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg,
-					(ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_RX |
-					 ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_TX),
-					0);
-	return 0;
-}
-
-int al_eth_fec_stats_get(struct al_hal_eth_adapter *adapter,
-			uint32_t *corrected, uint32_t *uncorrectable)
-{
-	if (adapter->rev_id <= AL_ETH_REV_ID_2)
-		return -1;
-
-	*corrected = al_reg_read32(&adapter->mac_regs_base->stat.v3_pcs_10g_ll_cerr);
-	*uncorrectable = al_reg_read32(&adapter->mac_regs_base->stat.v3_pcs_10g_ll_ncerr);
-
-	return 0;
-}
-
-
-int al_eth_capabilities_get(struct al_hal_eth_adapter *adapter, struct al_eth_capabilities *caps)
-{
-	al_assert(caps);
-
-	caps->speed_10_HD = AL_FALSE;
-	caps->speed_10_FD = AL_FALSE;
-	caps->speed_100_HD = AL_FALSE;
-	caps->speed_100_FD = AL_FALSE;
-	caps->speed_1000_HD = AL_FALSE;
-	caps->speed_1000_FD = AL_FALSE;
-	caps->speed_10000_HD = AL_FALSE;
-	caps->speed_10000_FD = AL_FALSE;
-	caps->pfc = AL_FALSE;
-	caps->eee = AL_FALSE;
-
-	switch (adapter->mac_mode) {
-		case AL_ETH_MAC_MODE_RGMII:
-		case AL_ETH_MAC_MODE_SGMII:
-			caps->speed_10_HD = AL_TRUE;
-			caps->speed_10_FD = AL_TRUE;
-			caps->speed_100_HD = AL_TRUE;
-			caps->speed_100_FD = AL_TRUE;
-			caps->speed_1000_FD = AL_TRUE;
-			caps->eee = AL_TRUE;
-			break;
-		case AL_ETH_MAC_MODE_10GbE_Serial:
-			caps->speed_10000_FD = AL_TRUE;
-			caps->pfc = AL_TRUE;
-			break;
-		default:
-		al_err("Eth: unsupported MAC mode %d", adapter->mac_mode);
-		return -EPERM;
-	}
-	return 0;
-}
-
-static void al_eth_mac_link_config_1g_mac(
-				struct al_hal_eth_adapter *adapter,
-				al_bool force_1000_base_x,
-				al_bool an_enable,
-				uint32_t speed,
-				al_bool full_duplex)
-{
-	uint32_t mac_ctrl;
-	uint32_t sgmii_ctrl = 0;
-	uint32_t sgmii_if_mode = 0;
-	uint32_t rgmii_ctrl = 0;
-
-	mac_ctrl = al_reg_read32(&adapter->mac_regs_base->mac_1g.cmd_cfg);
-
-	if (adapter->mac_mode == AL_ETH_MAC_MODE_SGMII) {
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr,
-			       ETH_MAC_SGMII_REG_ADDR_CTRL_REG);
-		sgmii_ctrl = al_reg_read32(&adapter->mac_regs_base->sgmii.reg_data);
-		/*
-		 * in case bit 0 is off in sgmii_if_mode register all the other
-		 * bits are ignored.
-		 */
-		if (force_1000_base_x == AL_FALSE)
-			sgmii_if_mode = ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_EN;
-
-		if (an_enable == AL_TRUE) {
-			sgmii_if_mode |= ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_AN;
-			sgmii_ctrl |= ETH_MAC_SGMII_REG_DATA_CTRL_AN_ENABLE;
-		} else {
-			sgmii_ctrl &= ~(ETH_MAC_SGMII_REG_DATA_CTRL_AN_ENABLE);
-		}
-	}
-
-	if (adapter->mac_mode == AL_ETH_MAC_MODE_RGMII) {
-		/*
-		 * Use the speed provided by the MAC instead of the PHY
-		 */
-		rgmii_ctrl = al_reg_read32(&adapter->mac_regs_base->gen.rgmii_cfg);
-
-		AL_REG_MASK_CLEAR(rgmii_ctrl, ETH_MAC_GEN_RGMII_CFG_ENA_AUTO);
-		AL_REG_MASK_CLEAR(rgmii_ctrl, ETH_MAC_GEN_RGMII_CFG_SET_1000_SEL);
-		AL_REG_MASK_CLEAR(rgmii_ctrl, ETH_MAC_GEN_RGMII_CFG_SET_10_SEL);
-
-		al_reg_write32(&adapter->mac_regs_base->gen.rgmii_cfg, rgmii_ctrl);
-	}
-
-	if (full_duplex == AL_TRUE) {
-		AL_REG_MASK_CLEAR(mac_ctrl, ETH_1G_MAC_CMD_CFG_HD_EN);
-	} else {
-		AL_REG_MASK_SET(mac_ctrl, ETH_1G_MAC_CMD_CFG_HD_EN);
-		sgmii_if_mode |= ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_DUPLEX;
-	}
-
-	if (speed == 1000) {
-		AL_REG_MASK_SET(mac_ctrl, ETH_1G_MAC_CMD_CFG_1G_SPD);
-		sgmii_if_mode |= ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_1000;
-	} else {
-		AL_REG_MASK_CLEAR(mac_ctrl, ETH_1G_MAC_CMD_CFG_1G_SPD);
-		if (speed == 10) {
-			AL_REG_MASK_SET(mac_ctrl, ETH_1G_MAC_CMD_CFG_10M_SPD);
-		} else {
-			sgmii_if_mode |= ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_100;
-			AL_REG_MASK_CLEAR(mac_ctrl, ETH_1G_MAC_CMD_CFG_10M_SPD);
-		}
-	}
-
-	if (adapter->mac_mode == AL_ETH_MAC_MODE_SGMII) {
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr,
-			       ETH_MAC_SGMII_REG_ADDR_IF_MODE_REG);
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data,
-			       sgmii_if_mode);
-
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr,
-			       ETH_MAC_SGMII_REG_ADDR_CTRL_REG);
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data,
-			       sgmii_ctrl);
-	}
-
-	al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, mac_ctrl);
-}
-
-static void al_eth_mac_link_config_10g_mac(
-				struct al_hal_eth_adapter *adapter,
-				al_bool force_1000_base_x,
-				al_bool an_enable,
-				uint32_t speed,
-				al_bool full_duplex)
-{
-	uint32_t if_mode;
-	uint32_t val;
-
-	if_mode = al_reg_read32(&adapter->mac_regs_base->mac_10g.if_mode);
-
-	if (force_1000_base_x) {
-		uint32_t control;
-
-		AL_REG_MASK_CLEAR(if_mode, ETH_10G_MAC_IF_MODE_SGMII_EN_MASK);
-
-		control = al_reg_read32(&adapter->mac_regs_base->mac_10g.control);
-
-		if (an_enable)
-			AL_REG_MASK_SET(control, ETH_10G_MAC_CONTROL_AN_EN_MASK);
-		else
-			AL_REG_MASK_CLEAR(control, ETH_10G_MAC_CONTROL_AN_EN_MASK);
-
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.control, control);
-
-	} else {
-		AL_REG_MASK_SET(if_mode, ETH_10G_MAC_IF_MODE_SGMII_EN_MASK);
-		if (an_enable) {
-			AL_REG_MASK_SET(if_mode, ETH_10G_MAC_IF_MODE_SGMII_AN_MASK);
-		} else {
-			AL_REG_MASK_CLEAR(if_mode, ETH_10G_MAC_IF_MODE_SGMII_AN_MASK);
-
-			if (speed == 1000)
-				val = ETH_10G_MAC_IF_MODE_SGMII_SPEED_1G;
-			else if (speed == 100)
-				val = ETH_10G_MAC_IF_MODE_SGMII_SPEED_100M;
-			else
-				val = ETH_10G_MAC_IF_MODE_SGMII_SPEED_10M;
-
-			AL_REG_FIELD_SET(if_mode,
-					 ETH_10G_MAC_IF_MODE_SGMII_SPEED_MASK,
-					 ETH_10G_MAC_IF_MODE_SGMII_SPEED_SHIFT,
-					 val);
-
-			AL_REG_FIELD_SET(if_mode,
-					 ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_MASK,
-					 ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_SHIFT,
-					 ((full_duplex) ?
-						ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_FULL :
-						ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_HALF));
-		}
-	}
-
-	al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, if_mode);
-}
-
-/* update link speed and duplex mode */
-int al_eth_mac_link_config(struct al_hal_eth_adapter *adapter,
-			   al_bool force_1000_base_x,
-			   al_bool an_enable,
-			   uint32_t speed,
-			   al_bool full_duplex)
-{
-	if ((!AL_ETH_IS_1G_MAC(adapter->mac_mode)) &&
-		(adapter->mac_mode != AL_ETH_MAC_MODE_SGMII_2_5G)) {
-		al_err("eth [%s]: this function not supported in this mac mode.\n",
-			       adapter->name);
-		return -EINVAL;
-	}
-
-	if ((adapter->mac_mode != AL_ETH_MAC_MODE_RGMII) && (an_enable)) {
-		/*
-		 * an_enable is not relevant to RGMII mode.
-		 * in AN mode speed and duplex aren't relevant.
-		 */
-		al_info("eth [%s]: set auto negotiation to enable\n", adapter->name);
-	} else {
-		al_info("eth [%s]: set link speed to %dMbps. %s duplex.\n", adapter->name,
-			speed, full_duplex == AL_TRUE ? "full" : "half");
-
-		if ((speed != 10) && (speed != 100) && (speed != 1000)) {
-			al_err("eth [%s]: bad speed parameter (%d).\n",
-				       adapter->name, speed);
-			return -EINVAL;
-		}
-		if ((speed == 1000) && (full_duplex == AL_FALSE)) {
-			al_err("eth [%s]: half duplex in 1Gbps is not supported.\n",
-				       adapter->name);
-			return -EINVAL;
-		}
-	}
-
-	if (AL_ETH_IS_1G_MAC(adapter->mac_mode))
-		al_eth_mac_link_config_1g_mac(adapter,
-					      force_1000_base_x,
-					      an_enable,
-					      speed,
-					      full_duplex);
-	else
-		al_eth_mac_link_config_10g_mac(adapter,
-					       force_1000_base_x,
-					       an_enable,
-					       speed,
-					       full_duplex);
-
-	return 0;
-}
-
-int al_eth_mac_loopback_config(struct al_hal_eth_adapter *adapter, int enable)
-{
-	const char *state = (enable) ? "enable" : "disable";
-
-	al_dbg("eth [%s]: loopback %s\n", adapter->name, state);
-	if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
-		uint32_t reg;
-		reg = al_reg_read32(&adapter->mac_regs_base->mac_1g.cmd_cfg);
-		if (enable)
-			reg |= AL_BIT(15);
-		else
-			reg &= ~AL_BIT(15);
-		al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, reg);
-	} else if ((AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode))
-			&& (adapter->rev_id == AL_ETH_REV_ID_3)) {
-		uint32_t reg;
-		al_reg_write16(
-			(uint16_t *)&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_CONTROL_1_ADDR);
-		reg = al_reg_read16(
-			(uint16_t *)&adapter->mac_regs_base->kr.pcs_data);
-		if (enable)
-			reg |= AL_BIT(14);
-		else
-			reg &= ~AL_BIT(14);
-		al_reg_write16(
-			(uint16_t *)&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_CONTROL_1_ADDR);
-		al_reg_write16(
-			(uint16_t *)&adapter->mac_regs_base->kr.pcs_data, reg);
-	} else if (adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G ||
-			(adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_50G)) {
-		uint32_t reg;
-		reg = al_eth_40g_pcs_reg_read(adapter, ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR);
-		if (enable)
-			reg |= AL_BIT(14);
-		else
-			reg &= ~AL_BIT(14);
-		al_eth_40g_pcs_reg_write(adapter, ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR, reg);
-	} else {
-		al_err("Eth: mac loopback not supported in this mode %d", adapter->mac_mode);
-		return -EPERM;
-	}
-	return 0;
-}
-
-/* MDIO */
-int al_eth_mdio_config(
-	struct al_hal_eth_adapter	*adapter,
-	enum al_eth_mdio_type		mdio_type,
-	al_bool				shared_mdio_if,
-	enum al_eth_ref_clk_freq	ref_clk_freq,
-	unsigned int			mdio_clk_freq_khz)
-{
-	enum al_eth_mdio_if mdio_if = AL_ETH_MDIO_IF_10G_MAC;
-	const char *if_name = (mdio_if == AL_ETH_MDIO_IF_1G_MAC) ? "10/100/1G MAC" : "10G MAC";
-	const char *type_name = (mdio_type == AL_ETH_MDIO_TYPE_CLAUSE_22) ? "Clause 22" : "Clause 45";
-	const char *shared_name = (shared_mdio_if == AL_TRUE) ? "Yes" : "No";
-
-	unsigned int ref_clk_freq_khz;
-	uint32_t val;
-
-	al_dbg("eth [%s]: mdio config: interface %s. type %s. shared: %s\n", adapter->name, if_name, type_name, shared_name);
-	adapter->shared_mdio_if = shared_mdio_if;
-
-	val = al_reg_read32(&adapter->mac_regs_base->gen.cfg);
-	al_dbg("eth [%s]: mdio config: 10G mac \n", adapter->name);
-
-	switch(mdio_if)
-	{
-		case AL_ETH_MDIO_IF_1G_MAC:
-			val &= ~AL_BIT(10);
-			break;
-		case AL_ETH_MDIO_IF_10G_MAC:
-			val |= AL_BIT(10);
-			break;
-	}
-	al_reg_write32(&adapter->mac_regs_base->gen.cfg, val);
-	adapter->mdio_if = mdio_if;
-
-
-	if (mdio_if == AL_ETH_MDIO_IF_10G_MAC)
-	{
-		val = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status);
-		switch(mdio_type)
-		{
-			case AL_ETH_MDIO_TYPE_CLAUSE_22:
-				val &= ~AL_BIT(6);
-				break;
-			case AL_ETH_MDIO_TYPE_CLAUSE_45:
-				val |= AL_BIT(6);
-				break;
-		}
-
-		/* set clock div to get 'mdio_clk_freq_khz' */
-		switch (ref_clk_freq) {
-		default:
-			al_err("eth [%s]: %s: invalid reference clock frequency"
-				" (%d)\n",
-				adapter->name, __func__, ref_clk_freq);
-		case AL_ETH_REF_FREQ_375_MHZ:
-			ref_clk_freq_khz = 375000;
-			break;
-		case AL_ETH_REF_FREQ_187_5_MHZ:
-			ref_clk_freq_khz = 187500;
-			break;
-		case AL_ETH_REF_FREQ_250_MHZ:
-			ref_clk_freq_khz = 250000;
-			break;
-		case AL_ETH_REF_FREQ_500_MHZ:
-			ref_clk_freq_khz = 500000;
-			break;
-                case AL_ETH_REF_FREQ_428_MHZ:
-                        ref_clk_freq_khz = 428000;
-                        break;
-		};
-
-		val &= ~(0x1FF << 7);
-		val |= (ref_clk_freq_khz / (2 * mdio_clk_freq_khz)) << 7;
-		AL_REG_FIELD_SET(val, ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK,
-				 ETH_10G_MAC_MDIO_CFG_HOLD_TIME_SHIFT,
-				 ETH_10G_MAC_MDIO_CFG_HOLD_TIME_7_CLK);
-		al_reg_write32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status, val);
-	}else{
-		if(mdio_type != AL_ETH_MDIO_TYPE_CLAUSE_22) {
-			al_err("eth [%s] mdio type not supported for this interface\n",
-				 adapter->name);
-			return -EINVAL;
-		}
-	}
-	adapter->mdio_type = mdio_type;
-
-	return 0;
-}
-
-static int al_eth_mdio_1g_mac_read(struct al_hal_eth_adapter *adapter,
-			    uint32_t phy_addr __attribute__((__unused__)),
-			    uint32_t reg, uint16_t *val)
-{
-	*val = al_reg_read32(
-		&adapter->mac_regs_base->mac_1g.phy_regs_base + reg);
-	return 0;
-}
-
-static int al_eth_mdio_1g_mac_write(struct al_hal_eth_adapter *adapter,
-			     uint32_t phy_addr __attribute__((__unused__)),
-			     uint32_t reg, uint16_t val)
-{
-	al_reg_write32(
-		&adapter->mac_regs_base->mac_1g.phy_regs_base + reg, val);
-	return 0;
-}
-
-static int al_eth_mdio_10g_mac_wait_busy(struct al_hal_eth_adapter *adapter)
-{
-	int	count = 0;
-	uint32_t mdio_cfg_status;
-
-	do {
-		mdio_cfg_status = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status);
-/*
-		if (mdio_cfg_status & AL_BIT(1)){ //error
-			al_err(" %s mdio read failed on error. phy_addr 0x%x reg 0x%x\n",
-				udma_params.name, phy_addr, reg);
-			return -EIO;
-		}*/
-		if (mdio_cfg_status & AL_BIT(0)){
-			if (count > 0)
-				al_dbg("eth [%s] mdio: still busy!\n", adapter->name);
-		}else{
-			return 0;
-		}
-		al_udelay(AL_ETH_MDIO_DELAY_PERIOD);
-	}while(count++ < AL_ETH_MDIO_DELAY_COUNT);
-
-	return -ETIMEDOUT;
-}
-
-static int al_eth_mdio_10g_mac_type22(
-	struct al_hal_eth_adapter *adapter,
-	int read, uint32_t phy_addr, uint32_t reg, uint16_t *val)
-{
-	int rc;
-	const char *op = (read == 1) ? "read":"write";
-	uint32_t mdio_cfg_status;
-	uint16_t mdio_cmd;
-
-	//wait if the HW is busy
-	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
-	if (rc) {
-		al_err(" eth [%s] mdio %s failed. HW is busy\n", adapter->name, op);
-		return rc;
-	}
-
-	mdio_cmd = (uint16_t)(0x1F & reg);
-	mdio_cmd |= (0x1F & phy_addr) << 5;
-
-	if (read)
-		mdio_cmd |= AL_BIT(15); //READ command
-
-	al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_cmd,
-			mdio_cmd);
-	if (!read)
-		al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_data,
-				*val);
-
-	//wait for the busy to clear
-	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
-	if (rc != 0) {
-		al_err(" %s mdio %s failed on timeout\n", adapter->name, op);
-		return -ETIMEDOUT;
-	}
-
-	mdio_cfg_status = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status);
-
-	if (mdio_cfg_status & AL_BIT(1)){ //error
-		al_err(" %s mdio %s failed on error. phy_addr 0x%x reg 0x%x\n",
-			adapter->name, op, phy_addr, reg);
-			return -EIO;
-	}
-	if (read)
-		*val = al_reg_read16(
-			(uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_data);
-	return 0;
-}
-
-static int al_eth_mdio_10g_mac_type45(
-	struct al_hal_eth_adapter *adapter,
-	int read, uint32_t port_addr, uint32_t device, uint32_t reg, uint16_t *val)
-{
-	int rc;
-	const char *op = (read == 1) ? "read":"write";
-	uint32_t mdio_cfg_status;
-	uint16_t mdio_cmd;
-
-	//wait if the HW is busy
-	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
-	if (rc) {
-		al_err(" %s mdio %s failed. HW is busy\n", adapter->name, op);
-		return rc;
-	}
-	// set command register
-	mdio_cmd = (uint16_t)(0x1F & device);
-	mdio_cmd |= (0x1F & port_addr) << 5;
-	al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_cmd,
-			mdio_cmd);
-
-	// send address frame
-	al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_regaddr, reg);
-	//wait for the busy to clear
-	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
-	if (rc) {
-		al_err(" %s mdio %s (address frame) failed on timeout\n", adapter->name, op);
-		return rc;
-	}
-
-	// if read, write again to the command register with READ bit set
-	if (read) {
-		mdio_cmd |= AL_BIT(15); //READ command
-		al_reg_write16(
-			(uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_cmd,
-			mdio_cmd);
-	} else {
-		al_reg_write16(
-			(uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_data,
-			*val);
-	}
-	//wait for the busy to clear
-	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
-	if (rc) {
-		al_err(" %s mdio %s failed on timeout\n", adapter->name, op);
-		return rc;
-	}
-
-	mdio_cfg_status = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status);
-
-	if (mdio_cfg_status & AL_BIT(1)){ //error
-		al_err(" %s mdio %s failed on error. port 0x%x, device 0x%x reg 0x%x\n",
-			adapter->name, op, port_addr, device, reg);
-			return -EIO;
-	}
-	if (read)
-		*val = al_reg_read16(
-			(uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_data);
-	return 0;
-}
-
-/**
- * acquire mdio interface ownership
- * when mdio interface shared between multiple eth controllers, this function waits until the ownership granted for this controller.
- * this function does nothing when the mdio interface is used only by this controller.
- *
- * @param adapter
- * @return 0 on success, -ETIMEDOUT  on timeout.
- */
-static int al_eth_mdio_lock(struct al_hal_eth_adapter *adapter)
-{
-	int	count = 0;
-	uint32_t mdio_ctrl_1;
-
-	if (adapter->shared_mdio_if == AL_FALSE)
-		return 0; /* nothing to do when interface is not shared */
-
-	do {
-		mdio_ctrl_1 = al_reg_read32(&adapter->mac_regs_base->gen.mdio_ctrl_1);
-/*
-		if (mdio_cfg_status & AL_BIT(1)){ //error
-			al_err(" %s mdio read failed on error. phy_addr 0x%x reg 0x%x\n",
-				udma_params.name, phy_addr, reg);
-			return -EIO;
-		}*/
-		if (mdio_ctrl_1 & AL_BIT(0)){
-			if (count > 0)
-				al_dbg("eth %s mdio interface still busy!\n", adapter->name);
-		}else{
-			return 0;
-		}
-		al_udelay(AL_ETH_MDIO_DELAY_PERIOD);
-	}while(count++ < (AL_ETH_MDIO_DELAY_COUNT * 4));
-	al_err(" %s mdio failed to take ownership. MDIO info reg: 0x%08x\n",
-		adapter->name, al_reg_read32(&adapter->mac_regs_base->gen.mdio_1));
-
-	return -ETIMEDOUT;
-}
-
-/**
- * free mdio interface ownership
- * when mdio interface shared between multiple eth controllers, this function releases the ownership granted for this controller.
- * this function does nothing when the mdio interface is used only by this controller.
- *
- * @param adapter
- * @return 0.
- */
-static int al_eth_mdio_free(struct al_hal_eth_adapter *adapter)
-{
-	if (adapter->shared_mdio_if == AL_FALSE)
-		return 0; /* nothing to do when interface is not shared */
-
-	al_reg_write32(&adapter->mac_regs_base->gen.mdio_ctrl_1, 0);
-
-	/*
-	 * Addressing RMN: 2917
-	 *
-	 * RMN description:
-	 * The HW spin-lock is stateless and doesn't maintain any scheduling
-	 * policy.
-	 *
-	 * Software flow:
-	 * After getting the lock wait 2 times the delay period in order to give
-	 * the other port chance to take the lock and prevent starvation.
-	 * This is not scalable to more than two ports.
-	 */
-	al_udelay(2 * AL_ETH_MDIO_DELAY_PERIOD);
-
-	return 0;
-}
-
-int al_eth_mdio_read(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, uint32_t device, uint32_t reg, uint16_t *val)
-{
-	int rc;
-	rc = al_eth_mdio_lock(adapter);
-
-	/*"interface ownership taken"*/
-	if (rc)
-		return rc;
-
-	if (adapter->mdio_if == AL_ETH_MDIO_IF_1G_MAC)
-		rc = al_eth_mdio_1g_mac_read(adapter, phy_addr, reg, val);
-	else
-		if (adapter->mdio_type == AL_ETH_MDIO_TYPE_CLAUSE_22)
-			rc = al_eth_mdio_10g_mac_type22(adapter, 1, phy_addr, reg, val);
-		else
-			rc = al_eth_mdio_10g_mac_type45(adapter, 1, phy_addr, device, reg, val);
-
-	al_eth_mdio_free(adapter);
-	al_dbg("eth mdio read: phy_addr %x, device %x, reg %x val %x\n", phy_addr, device, reg, *val);
-	return rc;
-}
-
-int al_eth_mdio_write(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, uint32_t device, uint32_t reg, uint16_t val)
-{
-	int rc;
-	al_dbg("eth mdio write: phy_addr %x, device %x, reg %x, val %x\n", phy_addr, device, reg, val);
-	rc = al_eth_mdio_lock(adapter);
-	/* interface ownership taken */
-	if (rc)
-		return rc;
-
-	if (adapter->mdio_if == AL_ETH_MDIO_IF_1G_MAC)
-		rc = al_eth_mdio_1g_mac_write(adapter, phy_addr, reg, val);
-	else
-		if (adapter->mdio_type == AL_ETH_MDIO_TYPE_CLAUSE_22)
-			rc = al_eth_mdio_10g_mac_type22(adapter, 0, phy_addr, reg, &val);
-		else
-			rc = al_eth_mdio_10g_mac_type45(adapter, 0, phy_addr, device, reg, &val);
-
-	al_eth_mdio_free(adapter);
-	return rc;
-}
-
-static void al_dump_tx_desc(union al_udma_desc *tx_desc)
-{
-	uint32_t *ptr = (uint32_t *)tx_desc;
-	al_dbg("eth tx desc:\n");
-	al_dbg("0x%08x\n", *(ptr++));
-	al_dbg("0x%08x\n", *(ptr++));
-	al_dbg("0x%08x\n", *(ptr++));
-	al_dbg("0x%08x\n", *(ptr++));
-}
-
-static void
-al_dump_tx_pkt(struct al_udma_q *tx_dma_q, struct al_eth_pkt *pkt)
-{
-	const char *tso = (pkt->flags & AL_ETH_TX_FLAGS_TSO) ? "TSO" : "";
-	const char *l3_csum = (pkt->flags & AL_ETH_TX_FLAGS_IPV4_L3_CSUM) ? "L3 CSUM" : "";
-	const char *l4_csum = (pkt->flags & AL_ETH_TX_FLAGS_L4_CSUM) ?
-	  ((pkt->flags & AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM) ? "L4 PARTIAL CSUM" : "L4 FULL CSUM") : "";
-	const char *fcs = (pkt->flags & AL_ETH_TX_FLAGS_L2_DIS_FCS) ? "Disable FCS" : "";
-	const char *ptp = (pkt->flags & AL_ETH_TX_FLAGS_TS) ? "TX_PTP" : "";
-	const char *l3_proto_name = "unknown";
-	const char *l4_proto_name = "unknown";
-	const char *outer_l3_proto_name = "N/A";
-	const char *tunnel_mode = (((pkt->tunnel_mode &
-				AL_ETH_TUNNEL_WITH_UDP) == AL_ETH_TUNNEL_WITH_UDP) ?
-				"TUNNEL_WITH_UDP" :
-				(((pkt->tunnel_mode &
-				AL_ETH_TUNNEL_NO_UDP) == AL_ETH_TUNNEL_NO_UDP) ?
-				"TUNNEL_NO_UDP" : ""));
-	uint32_t total_len = 0;
-	int i;
-
-	al_dbg("[%s %d]: flags: %s %s %s %s %s %s\n", tx_dma_q->udma->name, tx_dma_q->qid,
-		 tso, l3_csum, l4_csum, fcs, ptp, tunnel_mode);
-
-	switch (pkt->l3_proto_idx) {
-	case AL_ETH_PROTO_ID_IPv4:
-		l3_proto_name = "IPv4";
-		break;
-	case AL_ETH_PROTO_ID_IPv6:
-		l3_proto_name = "IPv6";
-		break;
-	default:
-		l3_proto_name = "unknown";
-		break;
-	}
-
-	switch (pkt->l4_proto_idx) {
-	case AL_ETH_PROTO_ID_TCP:
-		l4_proto_name = "TCP";
-		break;
-	case AL_ETH_PROTO_ID_UDP:
-		l4_proto_name = "UDP";
-		break;
-	default:
-		l4_proto_name = "unknown";
-		break;
-	}
-
-	switch (pkt->outer_l3_proto_idx) {
-	case AL_ETH_PROTO_ID_IPv4:
-		outer_l3_proto_name = "IPv4";
-		break;
-	case AL_ETH_PROTO_ID_IPv6:
-		outer_l3_proto_name = "IPv6";
-		break;
-	default:
-		outer_l3_proto_name = "N/A";
-		break;
-	}
-
-	al_dbg("[%s %d]: L3 proto: %d (%s). L4 proto: %d (%s). Outer_L3 proto: %d (%s). vlan source count %d. mod add %d. mod del %d\n",
-			tx_dma_q->udma->name, tx_dma_q->qid, pkt->l3_proto_idx,
-			l3_proto_name, pkt->l4_proto_idx, l4_proto_name,
-			pkt->outer_l3_proto_idx, outer_l3_proto_name,
-			pkt->source_vlan_count, pkt->vlan_mod_add_count,
-			pkt->vlan_mod_del_count);
-
-	if (pkt->meta) {
-		const char * store = pkt->meta->store ? "Yes" : "No";
-		const char *ptp_val = (pkt->flags & AL_ETH_TX_FLAGS_TS) ? "Yes" : "No";
-
-		al_dbg("[%s %d]: tx pkt with meta data. words valid %x\n",
-			tx_dma_q->udma->name, tx_dma_q->qid,
-			pkt->meta->words_valid);
-		al_dbg("[%s %d]: meta: store to cache %s. l3 hdr len %d. l3 hdr offset %d. "
-			"l4 hdr len %d. mss val %d ts_index %d ts_val:%s\n"
-			, tx_dma_q->udma->name, tx_dma_q->qid, store,
-			pkt->meta->l3_header_len, pkt->meta->l3_header_offset,
-			pkt->meta->l4_header_len, pkt->meta->mss_val,
-			pkt->meta->ts_index, ptp_val);
-		al_dbg("outer_l3_hdr_offset %d. outer_l3_len %d.\n",
-			pkt->meta->outer_l3_offset, pkt->meta->outer_l3_len);
-	}
-
-	al_dbg("[%s %d]: num of bufs: %d\n", tx_dma_q->udma->name, tx_dma_q->qid,
-		pkt->num_of_bufs);
-	for (i = 0; i < pkt->num_of_bufs; i++) {
-		al_dbg("eth [%s %d]: buf[%d]: len 0x%08x. address 0x%016llx\n", tx_dma_q->udma->name, tx_dma_q->qid,
-			i, pkt->bufs[i].len, (unsigned long long)pkt->bufs[i].addr);
-		total_len += pkt->bufs[i].len;
-	}
-	al_dbg("[%s %d]: total len: 0x%08x\n", tx_dma_q->udma->name, tx_dma_q->qid, total_len);
-
-}
-
-/* TX */
-/**
- * add packet to transmission queue
- */
-int al_eth_tx_pkt_prepare(struct al_udma_q *tx_dma_q, struct al_eth_pkt *pkt)
-{
-	union al_udma_desc *tx_desc;
-	uint32_t tx_descs;
-	uint32_t flags = AL_M2S_DESC_FIRST |
-			AL_M2S_DESC_CONCAT |
-			(pkt->flags & AL_ETH_TX_FLAGS_INT);
-	uint64_t tgtid = ((uint64_t)pkt->tgtid) << AL_UDMA_DESC_TGTID_SHIFT;
-	uint32_t meta_ctrl;
-	uint32_t ring_id;
-	int buf_idx;
-
-	al_dbg("[%s %d]: new tx pkt\n", tx_dma_q->udma->name, tx_dma_q->qid);
-
-	al_dump_tx_pkt(tx_dma_q, pkt);
-
-	tx_descs = pkt->num_of_bufs;
-	if (pkt->meta) {
-		tx_descs += 1;
-	}
-#ifdef AL_ETH_EX
-	al_assert((pkt->ext_meta_data == NULL) || (tx_dma_q->adapter_rev_id > AL_ETH_REV_ID_2));
-
-	tx_descs += al_eth_ext_metadata_needed_descs(pkt->ext_meta_data);
-	al_dbg("[%s %d]: %d Descriptors: ext_meta (%d). meta (%d). buffer (%d) ",
-			tx_dma_q->udma->name, tx_dma_q->qid, tx_descs,
-			al_eth_ext_metadata_needed_descs(pkt->ext_meta_data),
-			(pkt->meta != NULL), pkt->num_of_bufs);
-#endif
-
-	if (unlikely(al_udma_available_get(tx_dma_q) < tx_descs)) {
-		al_dbg("[%s %d]: failed to allocate (%d) descriptors",
-			 tx_dma_q->udma->name, tx_dma_q->qid, tx_descs);
-		return 0;
-	}
-
-#ifdef AL_ETH_EX
-	if (pkt->ext_meta_data != NULL) {
-		al_eth_ext_metadata_create(tx_dma_q, &flags, pkt->ext_meta_data);
-		flags &= ~(AL_M2S_DESC_FIRST | AL_ETH_TX_FLAGS_INT);
-	}
-#endif
-
-	if (pkt->meta) {
-		uint32_t meta_word_0 = 0;
-		uint32_t meta_word_1 = 0;
-		uint32_t meta_word_2 = 0;
-		uint32_t meta_word_3 = 0;
-
-		meta_word_0 |= flags | AL_M2S_DESC_META_DATA;
-		meta_word_0 &=  ~AL_M2S_DESC_CONCAT;
-		flags &= ~(AL_M2S_DESC_FIRST | AL_ETH_TX_FLAGS_INT);
-
-		tx_desc = al_udma_desc_get(tx_dma_q);
-		/* get ring id, and clear FIRST and Int flags */
-		ring_id = al_udma_ring_id_get(tx_dma_q) <<
-			AL_M2S_DESC_RING_ID_SHIFT;
-
-		meta_word_0 |= ring_id;
-		meta_word_0 |= pkt->meta->words_valid << 12;
-
-		if (pkt->meta->store)
-			meta_word_0 |= AL_ETH_TX_META_STORE;
-
-		if (pkt->meta->words_valid & 1) {
-			meta_word_0 |= pkt->meta->vlan1_cfi_sel;
-			meta_word_0 |= pkt->meta->vlan2_vid_sel << 2;
-			meta_word_0 |= pkt->meta->vlan2_cfi_sel << 4;
-			meta_word_0 |= pkt->meta->vlan2_pbits_sel << 6;
-			meta_word_0 |= pkt->meta->vlan2_ether_sel << 8;
-		}
-
-		if (pkt->meta->words_valid & 2) {
-			meta_word_1 = pkt->meta->vlan1_new_vid;
-			meta_word_1 |= pkt->meta->vlan1_new_cfi << 12;
-			meta_word_1 |= pkt->meta->vlan1_new_pbits << 13;
-			meta_word_1 |= pkt->meta->vlan2_new_vid << 16;
-			meta_word_1 |= pkt->meta->vlan2_new_cfi << 28;
-			meta_word_1 |= pkt->meta->vlan2_new_pbits << 29;
-		}
-
-		if (pkt->meta->words_valid & 4) {
-			uint32_t l3_offset;
-
-			meta_word_2 = pkt->meta->l3_header_len & AL_ETH_TX_META_L3_LEN_MASK;
-			meta_word_2 |= (pkt->meta->l3_header_offset & AL_ETH_TX_META_L3_OFF_MASK) <<
-				AL_ETH_TX_META_L3_OFF_SHIFT;
-			meta_word_2 |= (pkt->meta->l4_header_len & 0x3f) << 16;
-
-			if (unlikely(pkt->flags & AL_ETH_TX_FLAGS_TS))
-				meta_word_0 |= pkt->meta->ts_index <<
-					AL_ETH_TX_META_MSS_MSB_TS_VAL_SHIFT;
-			else
-				meta_word_0 |= (((pkt->meta->mss_val & 0x3c00) >> 10)
-						<< AL_ETH_TX_META_MSS_MSB_TS_VAL_SHIFT);
-			meta_word_2 |= ((pkt->meta->mss_val & 0x03ff)
-					<< AL_ETH_TX_META_MSS_LSB_VAL_SHIFT);
-
-			/*
-			 * move from bytes to multiplication of 2 as the HW
-			 * expect to get it
-			 */
-			l3_offset = (pkt->meta->outer_l3_offset >> 1);
-
-			meta_word_0 |=
-				(((l3_offset &
-				   AL_ETH_TX_META_OUTER_L3_OFF_HIGH_MASK) >> 3)
-				   << AL_ETH_TX_META_OUTER_L3_OFF_HIGH_SHIFT);
-
-			meta_word_3 |=
-				((l3_offset &
-				   AL_ETH_TX_META_OUTER_L3_OFF_LOW_MASK)
-				   << AL_ETH_TX_META_OUTER_L3_OFF_LOW_SHIFT);
-
-			/*
-			 * shift right 2 bits to work in multiplication of 4
-			 * as the HW expect to get it
-			 */
-			meta_word_3 |=
-				(((pkt->meta->outer_l3_len >> 2) &
-				   AL_ETH_TX_META_OUTER_L3_LEN_MASK)
-				   << AL_ETH_TX_META_OUTER_L3_LEN_SHIFT);
-		}
-
-		tx_desc->tx_meta.len_ctrl = swap32_to_le(meta_word_0);
-		tx_desc->tx_meta.meta_ctrl = swap32_to_le(meta_word_1);
-		tx_desc->tx_meta.meta1 = swap32_to_le(meta_word_2);
-		tx_desc->tx_meta.meta2 = swap32_to_le(meta_word_3);
-		al_dump_tx_desc(tx_desc);
-	}
-
-	meta_ctrl = pkt->flags & AL_ETH_TX_PKT_META_FLAGS;
-
-	/* L4_PARTIAL_CSUM without L4_CSUM is invalid option  */
-	al_assert((pkt->flags & (AL_ETH_TX_FLAGS_L4_CSUM|AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM)) !=
-		  AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM);
-
-	/* TSO packets can't have Timestamp enabled */
-	al_assert((pkt->flags & (AL_ETH_TX_FLAGS_TSO|AL_ETH_TX_FLAGS_TS)) !=
-		  (AL_ETH_TX_FLAGS_TSO|AL_ETH_TX_FLAGS_TS));
-
-	meta_ctrl |= pkt->l3_proto_idx;
-	meta_ctrl |= pkt->l4_proto_idx << AL_ETH_TX_L4_PROTO_IDX_SHIFT;
-	meta_ctrl |= pkt->source_vlan_count << AL_ETH_TX_SRC_VLAN_CNT_SHIFT;
-	meta_ctrl |= pkt->vlan_mod_add_count << AL_ETH_TX_VLAN_MOD_ADD_SHIFT;
-	meta_ctrl |= pkt->vlan_mod_del_count << AL_ETH_TX_VLAN_MOD_DEL_SHIFT;
-	meta_ctrl |= pkt->vlan_mod_v1_ether_sel << AL_ETH_TX_VLAN_MOD_E_SEL_SHIFT;
-	meta_ctrl |= pkt->vlan_mod_v1_vid_sel << AL_ETH_TX_VLAN_MOD_VID_SEL_SHIFT;
-	meta_ctrl |= pkt->vlan_mod_v1_pbits_sel << AL_ETH_TX_VLAN_MOD_PBIT_SEL_SHIFT;
-
-#ifdef AL_ETH_EX
-	if ((pkt->ext_meta_data != NULL) && (pkt->ext_meta_data->tx_crypto_data != NULL))
-		meta_ctrl |= AL_ETH_TX_FLAGS_ENCRYPT;
-#endif
-
-	meta_ctrl |= pkt->tunnel_mode << AL_ETH_TX_TUNNEL_MODE_SHIFT;
-	if (pkt->outer_l3_proto_idx == AL_ETH_PROTO_ID_IPv4)
-		meta_ctrl |= 1 << AL_ETH_TX_OUTER_L3_PROTO_SHIFT;
-
-	flags |= pkt->flags & AL_ETH_TX_PKT_UDMA_FLAGS;
-	for(buf_idx = 0; buf_idx < pkt->num_of_bufs; buf_idx++ ) {
-		uint32_t flags_len = flags;
-
-		tx_desc = al_udma_desc_get(tx_dma_q);
-		/* get ring id, and clear FIRST and Int flags */
-		ring_id = al_udma_ring_id_get(tx_dma_q) <<
-			AL_M2S_DESC_RING_ID_SHIFT;
-
-		flags_len |= ring_id;
-
-		if (buf_idx == (pkt->num_of_bufs - 1))
-			flags_len |= AL_M2S_DESC_LAST;
-
-		/* clear First and Int flags */
-		flags &= AL_ETH_TX_FLAGS_NO_SNOOP;
-		flags |= AL_M2S_DESC_CONCAT;
-
-		flags_len |= pkt->bufs[buf_idx].len & AL_M2S_DESC_LEN_MASK;
-		tx_desc->tx.len_ctrl = swap32_to_le(flags_len);
-		if (buf_idx == 0)
-			tx_desc->tx.meta_ctrl = swap32_to_le(meta_ctrl);
-		tx_desc->tx.buf_ptr = swap64_to_le(
-			pkt->bufs[buf_idx].addr | tgtid);
-		al_dump_tx_desc(tx_desc);
-	}
-
-	al_dbg("[%s %d]: pkt descriptors written into the tx queue. descs num (%d)\n",
-		tx_dma_q->udma->name, tx_dma_q->qid, tx_descs);
-
-	return tx_descs;
-}
-
-
-void al_eth_tx_dma_action(struct al_udma_q *tx_dma_q, uint32_t tx_descs)
-{
-	/* add tx descriptors */
-	al_udma_desc_action_add(tx_dma_q, tx_descs);
-}
-
-/**
- * get number of completed tx descriptors, upper layer should derive from
- */
-int al_eth_comp_tx_get(struct al_udma_q *tx_dma_q)
-{
-	int rc;
-
-	rc = al_udma_cdesc_get_all(tx_dma_q, NULL);
-	if (rc != 0) {
-		al_udma_cdesc_ack(tx_dma_q, rc);
-		al_dbg("[%s %d]: tx completion: descs (%d)\n",
-			 tx_dma_q->udma->name, tx_dma_q->qid, rc);
-	}
-
-	return rc;
-}
-
-/**
- * configure the TSO MSS val
- */
-int al_eth_tso_mss_config(struct al_hal_eth_adapter *adapter, uint8_t idx, uint32_t mss_val)
-{
-
-	al_assert(idx <= 8); /*valid MSS index*/
-	al_assert(mss_val <= AL_ETH_TSO_MSS_MAX_VAL); /*valid MSS val*/
-	al_assert(mss_val >= AL_ETH_TSO_MSS_MIN_VAL); /*valid MSS val*/
-
-	al_reg_write32(&adapter->ec_regs_base->tso_sel[idx].mss, mss_val);
-	return 0;
-}
-
-
-/* RX */
-/**
- * config the rx descriptor fields
- */
-void al_eth_rx_desc_config(
-			struct al_hal_eth_adapter *adapter,
-			enum al_eth_rx_desc_lro_context_val_res lro_sel,
-			enum al_eth_rx_desc_l4_offset_sel l4_offset_sel,
-			enum al_eth_rx_desc_l3_offset_sel l3_offset_sel,
-			enum al_eth_rx_desc_l4_chk_res_sel l4_sel,
-			enum al_eth_rx_desc_l3_chk_res_sel l3_sel,
-			enum al_eth_rx_desc_l3_proto_idx_sel l3_proto_sel,
-			enum al_eth_rx_desc_l4_proto_idx_sel l4_proto_sel,
-			enum al_eth_rx_desc_frag_sel frag_sel)
-{
-	uint32_t reg_val = 0;
-
-	reg_val |= (lro_sel == AL_ETH_L4_OFFSET) ?
-			EC_RFW_CFG_A_0_LRO_CONTEXT_SEL : 0;
-
-	reg_val |= (l4_sel == AL_ETH_L4_INNER_OUTER_CHK) ?
-			EC_RFW_CFG_A_0_META_L4_CHK_RES_SEL : 0;
-
-	reg_val |= l3_sel << EC_RFW_CFG_A_0_META_L3_CHK_RES_SEL_SHIFT;
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.cfg_a_0, reg_val);
-
-	reg_val = al_reg_read32(&adapter->ec_regs_base->rfw.meta);
-	if (l3_proto_sel == AL_ETH_L3_PROTO_IDX_INNER)
-		reg_val |= EC_RFW_META_L3_PROT_SEL;
-	else
-		reg_val &= ~EC_RFW_META_L3_PROT_SEL;
-
-	if (l4_proto_sel == AL_ETH_L4_PROTO_IDX_INNER)
-		reg_val |= EC_RFW_META_L4_PROT_SEL;
-	else
-		reg_val &= ~EC_RFW_META_L4_PROT_SEL;
-
-	if (l4_offset_sel == AL_ETH_L4_OFFSET_INNER)
-		reg_val |= EC_RFW_META_L4_OFFSET_SEL;
-	else
-		reg_val &= ~EC_RFW_META_L4_OFFSET_SEL;
-
-	if (l3_offset_sel == AL_ETH_L3_OFFSET_INNER)
-		reg_val |= EC_RFW_META_L3_OFFSET_SEL;
-	else
-		reg_val &= ~EC_RFW_META_L3_OFFSET_SEL;
-
-	if (frag_sel == AL_ETH_FRAG_INNER)
-		reg_val |= EC_RFW_META_FRAG_SEL;
-	else
-		reg_val &= ~EC_RFW_META_FRAG_SEL;
-
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.meta, reg_val);
-}
-
-/**
- * Configure RX header split
- */
-int al_eth_rx_header_split_config(struct al_hal_eth_adapter *adapter, al_bool enable, uint32_t header_len)
-{
-	uint32_t	reg;
-
-	reg = al_reg_read32(&adapter->ec_regs_base->rfw.hdr_split);
-	if (enable == AL_TRUE)
-		reg |= EC_RFW_HDR_SPLIT_EN;
-	else
-		reg &= ~EC_RFW_HDR_SPLIT_EN;
-
-	AL_REG_FIELD_SET(reg, EC_RFW_HDR_SPLIT_DEF_LEN_MASK, EC_RFW_HDR_SPLIT_DEF_LEN_SHIFT, header_len);
-	al_reg_write32(&adapter->ec_regs_base->rfw.hdr_split, reg);
-	return 0;
-}
-
-
-/**
- * enable / disable header split in the udma queue.
- * length will be taken from the udma configuration to enable different length per queue.
- */
-int al_eth_rx_header_split_force_len_config(struct al_hal_eth_adapter *adapter,
-					al_bool enable,
-					uint32_t qid,
-					uint32_t header_len)
-{
-	al_udma_s2m_q_compl_hdr_split_config(&(adapter->rx_udma.udma_q[qid]), enable,
-					     AL_TRUE, header_len);
-
-	return 0;
-}
-
-
-/**
- * add buffer to receive queue
- */
-int al_eth_rx_buffer_add(struct al_udma_q *rx_dma_q,
-			      struct al_buf *buf, uint32_t flags,
-			      struct al_buf *header_buf)
-{
-	uint64_t tgtid = ((uint64_t)flags & AL_ETH_RX_FLAGS_TGTID_MASK) <<
-		AL_UDMA_DESC_TGTID_SHIFT;
-	uint32_t flags_len = flags & ~AL_ETH_RX_FLAGS_TGTID_MASK;
-	union al_udma_desc *rx_desc;
-
-	al_dbg("[%s %d]: add rx buffer.\n", rx_dma_q->udma->name, rx_dma_q->qid);
-
-#if 1
-	if (unlikely(al_udma_available_get(rx_dma_q) < 1)) {
-		al_dbg("[%s]: rx q (%d) has no enough free descriptor",
-			 rx_dma_q->udma->name, rx_dma_q->qid);
-		return -ENOSPC;
-	}
-#endif
-	rx_desc = al_udma_desc_get(rx_dma_q);
-
-	flags_len |= al_udma_ring_id_get(rx_dma_q) << AL_S2M_DESC_RING_ID_SHIFT;
-	flags_len |= buf->len & AL_S2M_DESC_LEN_MASK;
-
-	if (flags & AL_S2M_DESC_DUAL_BUF) {
-		al_assert(header_buf != NULL); /*header valid in dual buf */
-		al_assert((rx_dma_q->udma->rev_id >= AL_UDMA_REV_ID_2) ||
-			(AL_ADDR_HIGH(buf->addr) == AL_ADDR_HIGH(header_buf->addr)));
-
-		flags_len |= ((header_buf->len >> AL_S2M_DESC_LEN2_GRANULARITY_SHIFT)
-			<< AL_S2M_DESC_LEN2_SHIFT) & AL_S2M_DESC_LEN2_MASK;
-		rx_desc->rx.buf2_ptr_lo = swap32_to_le(AL_ADDR_LOW(header_buf->addr));
-	}
-	rx_desc->rx.len_ctrl = swap32_to_le(flags_len);
-	rx_desc->rx.buf1_ptr = swap64_to_le(buf->addr | tgtid);
-
-	return 0;
-}
-
-/**
- * notify the hw engine about rx descriptors that were added to the receive queue
- */
-void al_eth_rx_buffer_action(struct al_udma_q *rx_dma_q, uint32_t descs_num)
-{
-	al_dbg("[%s]: update the rx engine tail pointer: queue %d. descs %d\n",
-		 rx_dma_q->udma->name, rx_dma_q->qid, descs_num);
-
-	/* add rx descriptor */
-	al_udma_desc_action_add(rx_dma_q, descs_num);
-}
-
-/**
- * get packet from RX completion ring
- */
-uint32_t al_eth_pkt_rx(struct al_udma_q *rx_dma_q,
-			      struct al_eth_pkt *pkt)
-{
-	volatile union al_udma_cdesc *cdesc;
-	volatile al_eth_rx_cdesc *rx_desc;
-	uint32_t i;
-	uint32_t rc;
-
-	rc = al_udma_cdesc_packet_get(rx_dma_q, &cdesc);
-	if (rc == 0)
-		return 0;
-
-	al_assert(rc <= AL_ETH_PKT_MAX_BUFS);
-
-	al_dbg("[%s]: fetch rx packet: queue %d.\n",
-		 rx_dma_q->udma->name, rx_dma_q->qid);
-
-	pkt->rx_header_len = 0;
-	for (i = 0; i < rc; i++) {
-		uint32_t buf1_len, buf2_len;
-
-		/* get next descriptor */
-		rx_desc = (volatile al_eth_rx_cdesc *)al_cdesc_next(rx_dma_q, cdesc, i);
-
-		buf1_len = swap32_from_le(rx_desc->len);
-
-		if ((i == 0) && (swap32_from_le(rx_desc->word2) &
-			AL_UDMA_CDESC_BUF2_USED)) {
-			buf2_len = swap32_from_le(rx_desc->word2);
-			pkt->rx_header_len = (buf2_len & AL_S2M_DESC_LEN2_MASK) >>
-			AL_S2M_DESC_LEN2_SHIFT;
-			}
-		if ((swap32_from_le(rx_desc->ctrl_meta) & AL_UDMA_CDESC_BUF1_USED) &&
-			((swap32_from_le(rx_desc->ctrl_meta) & AL_UDMA_CDESC_DDP) == 0))
-			pkt->bufs[i].len = buf1_len & AL_S2M_DESC_LEN_MASK;
-		else
-			pkt->bufs[i].len = 0;
-	}
-	/* get flags from last desc */
-	pkt->flags = swap32_from_le(rx_desc->ctrl_meta);
-#ifdef AL_ETH_RX_DESC_RAW_GET
-	pkt->rx_desc_raw[0] = pkt->flags;
-	pkt->rx_desc_raw[1] = swap32_from_le(rx_desc->len);
-	pkt->rx_desc_raw[2] = swap32_from_le(rx_desc->word2);
-	pkt->rx_desc_raw[3] = swap32_from_le(rx_desc->word3);
-#endif
-	/* update L3/L4 proto index */
-	pkt->l3_proto_idx = pkt->flags & AL_ETH_RX_L3_PROTO_IDX_MASK;
-	pkt->l4_proto_idx = (pkt->flags >> AL_ETH_RX_L4_PROTO_IDX_SHIFT) &
-				AL_ETH_RX_L4_PROTO_IDX_MASK;
-	pkt->rxhash = (swap32_from_le(rx_desc->len) & AL_ETH_RX_HASH_MASK) >>
-			AL_ETH_RX_HASH_SHIFT;
-	pkt->l3_offset = (swap32_from_le(rx_desc->word2) & AL_ETH_RX_L3_OFFSET_MASK) >> AL_ETH_RX_L3_OFFSET_SHIFT;
-
-	al_udma_cdesc_ack(rx_dma_q, rc);
-	return rc;
-}
-
-
-int al_eth_rx_parser_entry_update(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_epe_p_reg_entry *reg_entry,
-		struct al_eth_epe_control_entry *control_entry)
-{
-	al_eth_epe_entry_set(adapter, idx, reg_entry, control_entry);
-	return 0;
-}
-
-#define AL_ETH_THASH_UDMA_SHIFT		0
-#define AL_ETH_THASH_UDMA_MASK		(0xF << AL_ETH_THASH_UDMA_SHIFT)
-
-#define AL_ETH_THASH_Q_SHIFT		4
-#define AL_ETH_THASH_Q_MASK		(0x3 << AL_ETH_THASH_Q_SHIFT)
-
-int al_eth_thash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma, uint32_t queue)
-{
-	uint32_t entry;
-	al_assert(idx < AL_ETH_RX_THASH_TABLE_SIZE); /*valid THASH index*/
-
-	entry = (udma << AL_ETH_THASH_UDMA_SHIFT) & AL_ETH_THASH_UDMA_MASK;
-	entry |= (queue << AL_ETH_THASH_Q_SHIFT) & AL_ETH_THASH_Q_MASK;
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.thash_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw.thash_table_data, entry);
-	return 0;
-}
-
-int al_eth_fsm_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry)
-{
-
-	al_assert(idx < AL_ETH_RX_FSM_TABLE_SIZE); /*valid FSM index*/
-
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.fsm_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw.fsm_table_data, entry);
-	return 0;
-}
-
-static uint32_t	al_eth_fwd_ctrl_entry_to_val(struct al_eth_fwd_ctrl_table_entry *entry)
-{
-	uint32_t val = 0;
-	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(3,0), 0, entry->prio_sel);
-	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(7,4), 4, entry->queue_sel_1);
-	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(9,8), 8, entry->queue_sel_2);
-	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(13,10), 10, entry->udma_sel);
-	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(17,15), 15, entry->hdr_split_len_sel);
-	if (entry->hdr_split_len_sel != AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_0)
-		val |= AL_BIT(18);
-	AL_REG_BIT_VAL_SET(val, 19, !!(entry->filter == AL_TRUE));
-
-	return val;
-}
-
-static int al_eth_ctrl_index_match(struct al_eth_fwd_ctrl_table_index *index, uint32_t i) {
-	if ((index->vlan_table_out != AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_ANY)
-		&& (index->vlan_table_out != AL_REG_BIT_GET(i, 0)))
-		return 0;
-	if ((index->tunnel_exist != AL_ETH_FWD_CTRL_IDX_TUNNEL_ANY)
-		&& (index->tunnel_exist != AL_REG_BIT_GET(i, 1)))
-		return 0;
-	if ((index->vlan_exist != AL_ETH_FWD_CTRL_IDX_VLAN_ANY)
-		&& (index->vlan_exist != AL_REG_BIT_GET(i, 2)))
-		return 0;
-	if ((index->mac_table_match != AL_ETH_FWD_CTRL_IDX_MAC_TABLE_ANY)
-		&& (index->mac_table_match != AL_REG_BIT_GET(i, 3)))
-		return 0;
-	if ((index->protocol_id != AL_ETH_PROTO_ID_ANY)
-		&& (index->protocol_id != AL_REG_FIELD_GET(i, AL_FIELD_MASK(8,4),4)))
-		return 0;
-	if ((index->mac_type != AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_ANY)
-		&& (index->mac_type != AL_REG_FIELD_GET(i, AL_FIELD_MASK(10,9),9)))
-		return 0;
-	return 1;
-}
-
-int al_eth_ctrl_table_set(struct al_hal_eth_adapter *adapter,
-			  struct al_eth_fwd_ctrl_table_index *index,
-			  struct al_eth_fwd_ctrl_table_entry *entry)
-{
-	uint32_t val = al_eth_fwd_ctrl_entry_to_val(entry);
-	uint32_t i;
-
-	for (i = 0; i < AL_ETH_RX_CTRL_TABLE_SIZE; i++) {
-		if (al_eth_ctrl_index_match(index, i)) {
-			al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_addr, i);
-			al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_data, val);
-		}
-	}
-	return 0;
-}
-
-int al_eth_ctrl_table_def_set(struct al_hal_eth_adapter *adapter,
-			      al_bool use_table,
-			      struct al_eth_fwd_ctrl_table_entry *entry)
-{
-	uint32_t val = al_eth_fwd_ctrl_entry_to_val(entry);
-
-	if (use_table)
-		val |= EC_RFW_CTRL_TABLE_DEF_SEL;
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_def, val);
-
-	return 0;
-}
-
-int al_eth_ctrl_table_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry)
-{
-
-	al_assert(idx < AL_ETH_RX_CTRL_TABLE_SIZE); /* valid CTRL index */
-
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_data, entry);
-	return 0;
-}
-
-int al_eth_ctrl_table_def_raw_set(struct al_hal_eth_adapter *adapter, uint32_t val)
-{
-	al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_def, val);
-
-	return 0;
-}
-
-int al_eth_hash_key_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t val)
-{
-
-	al_assert(idx < AL_ETH_RX_HASH_KEY_NUM); /*valid CTRL index*/
-
-	al_reg_write32(&adapter->ec_regs_base->rfw_hash[idx].key, val);
-
-	return 0;
-}
-
-static uint32_t	al_eth_fwd_mac_table_entry_to_val(struct al_eth_fwd_mac_table_entry *entry)
-{
-	uint32_t val = 0;
-
-	val |= (entry->filter == AL_TRUE) ? EC_FWD_MAC_CTRL_RX_VAL_DROP : 0;
-	val |= ((entry->udma_mask << EC_FWD_MAC_CTRL_RX_VAL_UDMA_SHIFT) &
-					EC_FWD_MAC_CTRL_RX_VAL_UDMA_MASK);
-
-	val |= ((entry->qid << EC_FWD_MAC_CTRL_RX_VAL_QID_SHIFT) &
-					EC_FWD_MAC_CTRL_RX_VAL_QID_MASK);
-
-	val |= (entry->rx_valid == AL_TRUE) ? EC_FWD_MAC_CTRL_RX_VALID : 0;
-
-	val |= ((entry->tx_target << EC_FWD_MAC_CTRL_TX_VAL_SHIFT) &
-					EC_FWD_MAC_CTRL_TX_VAL_MASK);
-
-	val |= (entry->tx_valid == AL_TRUE) ? EC_FWD_MAC_CTRL_TX_VALID : 0;
-
-	return val;
-}
-
-int al_eth_fwd_mac_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-			     struct al_eth_fwd_mac_table_entry *entry)
-{
-	uint32_t val;
-
-	al_assert(idx < AL_ETH_FWD_MAC_NUM); /*valid FWD MAC index */
-
-	val = (entry->addr[2] << 24) | (entry->addr[3] << 16) |
-	      (entry->addr[4] << 8) | entry->addr[5];
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_l, val);
-	val = (entry->addr[0] << 8) | entry->addr[1];
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_h, val);
-	val = (entry->mask[2] << 24) | (entry->mask[3] << 16) |
-	      (entry->mask[4] << 8) | entry->mask[5];
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_l, val);
-	val = (entry->mask[0] << 8) | entry->mask[1];
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_h, val);
-
-	val = al_eth_fwd_mac_table_entry_to_val(entry);
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].ctrl, val);
-	return 0;
-}
-
-
-
-int al_eth_fwd_mac_addr_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t addr_lo, uint32_t addr_hi, uint32_t mask_lo, uint32_t mask_hi)
-{
-	al_assert(idx < AL_ETH_FWD_MAC_NUM); /*valid FWD MAC index */
-
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_l, addr_lo);
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_h, addr_hi);
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_l, mask_lo);
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_h, mask_hi);
-
-	return 0;
-}
-
-int al_eth_fwd_mac_ctrl_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t ctrl)
-{
-	al_assert(idx < AL_ETH_FWD_MAC_NUM); /*valid FWD MAC index */
-
-	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].ctrl, ctrl);
-
-	return 0;
-}
-
-int al_eth_mac_addr_store(void * __iomem ec_base, uint32_t idx, uint8_t *addr)
-{
-	struct al_ec_regs __iomem *ec_regs_base = (struct al_ec_regs __iomem*)ec_base;
-	uint32_t val;
-
-	al_assert(idx < AL_ETH_FWD_MAC_NUM); /*valid FWD MAC index */
-
-	val = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
-	al_reg_write32(&ec_regs_base->fwd_mac[idx].data_l, val);
-	val = (addr[0] << 8) | addr[1];
-	al_reg_write32(&ec_regs_base->fwd_mac[idx].data_h, val);
-	return 0;
-}
-
-int al_eth_mac_addr_read(void * __iomem ec_base, uint32_t idx, uint8_t *addr)
-{
-	struct al_ec_regs __iomem *ec_regs_base = (struct al_ec_regs __iomem*)ec_base;
-	uint32_t addr_lo = al_reg_read32(&ec_regs_base->fwd_mac[idx].data_l);
-	uint16_t addr_hi = al_reg_read32(&ec_regs_base->fwd_mac[idx].data_h);
-
-	addr[5] = addr_lo & 0xff;
-	addr[4] = (addr_lo >> 8) & 0xff;
-	addr[3] = (addr_lo >> 16) & 0xff;
-	addr[2] = (addr_lo >> 24) & 0xff;
-	addr[1] = addr_hi & 0xff;
-	addr[0] = (addr_hi >> 8) & 0xff;
-	return 0;
-}
-
-int al_eth_fwd_mhash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, uint8_t qid)
-{
-	uint32_t val = 0;
-	al_assert(idx < AL_ETH_FWD_MAC_HASH_NUM); /* valid MHASH index */
-
-	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(3,0), 0, udma_mask);
-	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(5,4), 4, qid);
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.mhash_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw.mhash_table_data, val);
-	return 0;
-}
-static uint32_t	al_eth_fwd_vid_entry_to_val(struct al_eth_fwd_vid_table_entry *entry)
-{
-	uint32_t val = 0;
-	AL_REG_BIT_VAL_SET(val, 0, entry->control);
-	AL_REG_BIT_VAL_SET(val, 1, entry->filter);
-	AL_REG_FIELD_SET(val, AL_FIELD_MASK(5,2), 2, entry->udma_mask);
-
-	return val;
-}
-
-int al_eth_fwd_vid_config_set(struct al_hal_eth_adapter *adapter, al_bool use_table,
-			      struct al_eth_fwd_vid_table_entry *default_entry,
-			      uint32_t default_vlan)
-{
-	uint32_t reg;
-
-	reg = al_eth_fwd_vid_entry_to_val(default_entry);
-	if (use_table)
-		reg |= EC_RFW_VID_TABLE_DEF_SEL;
-	else
-		reg &= ~EC_RFW_VID_TABLE_DEF_SEL;
-	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_def, reg);
-	al_reg_write32(&adapter->ec_regs_base->rfw.default_vlan, default_vlan);
-
-	return 0;
-}
-
-int al_eth_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-			     struct al_eth_fwd_vid_table_entry *entry)
-{
-	uint32_t val;
-	al_assert(idx < AL_ETH_FWD_VID_TABLE_NUM); /* valid VID index */
-
-	val = al_eth_fwd_vid_entry_to_val(entry);
-	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_data, val);
-	return 0;
-}
-
-int al_eth_fwd_pbits_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio)
-{
-
-	al_assert(idx < AL_ETH_FWD_PBITS_TABLE_NUM); /* valid PBIT index */
-	al_assert(prio < AL_ETH_FWD_PRIO_TABLE_NUM); /* valid PRIO index */
-	al_reg_write32(&adapter->ec_regs_base->rfw.pbits_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw.pbits_table_data, prio);
-	return 0;
-}
-
-int al_eth_fwd_priority_table_set(struct al_hal_eth_adapter *adapter, uint8_t prio, uint8_t qid)
-{
-	al_assert(prio < AL_ETH_FWD_PRIO_TABLE_NUM); /* valid PRIO index */
-
-	al_reg_write32(&adapter->ec_regs_base->rfw_priority[prio].queue, qid);
-	return 0;
-}
-
-
-int al_eth_fwd_dscp_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio)
-{
-
-	al_assert(idx < AL_ETH_FWD_DSCP_TABLE_NUM); /* valid DSCP index */
-
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.dscp_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw.dscp_table_data, prio);
-	return 0;
-}
-
-int al_eth_fwd_tc_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio)
-{
-
-	al_assert(idx < AL_ETH_FWD_TC_TABLE_NUM); /* valid TC index */
-
-
-	al_reg_write32(&adapter->ec_regs_base->rfw.tc_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw.tc_table_data, prio);
-	return 0;
-}
-
-/** Configure default UDMA register */
-int al_eth_fwd_default_udma_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
-				   uint8_t udma_mask)
-{
-	al_reg_write32_masked(&adapter->ec_regs_base->rfw_default[idx].opt_1,
-			       EC_RFW_DEFAULT_OPT_1_UDMA_MASK,
-			       udma_mask << EC_RFW_DEFAULT_OPT_1_UDMA_SHIFT);
-	return 0;
-}
-
-/** Configure default queue register */
-int al_eth_fwd_default_queue_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
-				   uint8_t qid)
-{
-	al_reg_write32_masked(&adapter->ec_regs_base->rfw_default[idx].opt_1,
-			       EC_RFW_DEFAULT_OPT_1_QUEUE_MASK,
-			       qid << EC_RFW_DEFAULT_OPT_1_QUEUE_SHIFT);
-	return 0;
-}
-
-/** Configure default priority register */
-int al_eth_fwd_default_priority_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
-				   uint8_t prio)
-{
-	al_reg_write32_masked(&adapter->ec_regs_base->rfw_default[idx].opt_1,
-			       EC_RFW_DEFAULT_OPT_1_PRIORITY_MASK,
-			       prio << EC_RFW_DEFAULT_OPT_1_PRIORITY_SHIFT);
-	return 0;
-}
-
-int al_eth_switching_config_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t forward_all_to_mac, uint8_t enable_int_switching,
-					enum al_eth_tx_switch_vid_sel_type vid_sel_type,
-					enum al_eth_tx_switch_dec_type uc_dec,
-					enum al_eth_tx_switch_dec_type mc_dec,
-					enum al_eth_tx_switch_dec_type bc_dec)
-{
-	uint32_t reg;
-
-	if (udma_id == 0) {
-		reg = al_reg_read32(&adapter->ec_regs_base->tfw.tx_gen);
-		if (forward_all_to_mac)
-			reg |= EC_TFW_TX_GEN_FWD_ALL_TO_MAC;
-		else
-			reg &= ~EC_TFW_TX_GEN_FWD_ALL_TO_MAC;
-		al_reg_write32(&adapter->ec_regs_base->tfw.tx_gen, reg);
-	}
-
-	reg = enable_int_switching;
-	reg |= (vid_sel_type & 7) << 1;
-	reg |= (bc_dec & 3) << 4;
-	reg |= (mc_dec & 3) << 6;
-	reg |= (uc_dec & 3) << 8;
-	al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].fwd_dec, reg);
-
-	return 0;
-}
-
-#define AL_ETH_RFW_FILTER_SUPPORTED(rev_id)	\
-	(AL_ETH_RFW_FILTER_UNDET_MAC | \
-	AL_ETH_RFW_FILTER_DET_MAC | \
-	AL_ETH_RFW_FILTER_TAGGED | \
-	AL_ETH_RFW_FILTER_UNTAGGED | \
-	AL_ETH_RFW_FILTER_BC | \
-	AL_ETH_RFW_FILTER_MC | \
-	AL_ETH_RFW_FILTER_VLAN_VID | \
-	AL_ETH_RFW_FILTER_CTRL_TABLE | \
-	AL_ETH_RFW_FILTER_PROT_INDEX | \
-	AL_ETH_RFW_FILTER_WOL | \
-	AL_ETH_RFW_FILTER_PARSE)
-
-/* Configure the receive filters */
-int al_eth_filter_config(struct al_hal_eth_adapter *adapter, struct al_eth_filter_params *params)
-{
-	uint32_t reg;
-
-	al_assert(params); /* valid params pointer */
-
-	if (params->filters & ~(AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id))) {
-		al_err("[%s]: unsupported filter options (0x%08x)\n", adapter->name, params->filters);
-		return -EINVAL;
-	}
-
-	reg = al_reg_read32(&adapter->ec_regs_base->rfw.out_cfg);
-	if (params->enable == AL_TRUE)
-		AL_REG_MASK_SET(reg, EC_RFW_OUT_CFG_DROP_EN);
-	else
-		AL_REG_MASK_CLEAR(reg, EC_RFW_OUT_CFG_DROP_EN);
-	al_reg_write32(&adapter->ec_regs_base->rfw.out_cfg, reg);
-
-	al_reg_write32_masked(
-		&adapter->ec_regs_base->rfw.filter,
-		AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id),
-		params->filters);
-	if (params->filters & AL_ETH_RFW_FILTER_PROT_INDEX) {
-		int i;
-		for (i = 0; i < AL_ETH_PROTOCOLS_NUM; i++) {
-			reg = al_reg_read32(&adapter->ec_regs_base->epe_a[i].prot_act);
-			if (params->filter_proto[i] == AL_TRUE)
-				AL_REG_MASK_SET(reg, EC_EPE_A_PROT_ACT_DROP);
-			else
-				AL_REG_MASK_CLEAR(reg, EC_EPE_A_PROT_ACT_DROP);
-			al_reg_write32(&adapter->ec_regs_base->epe_a[i].prot_act, reg);
-		}
-	}
-	return 0;
-}
-
-/* Configure the receive override filters */
-int al_eth_filter_override_config(struct al_hal_eth_adapter *adapter,
-				  struct al_eth_filter_override_params *params)
-{
-	uint32_t reg;
-
-	al_assert(params); /* valid params pointer */
-
-	if (params->filters & ~(AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id))) {
-		al_err("[%s]: unsupported override filter options (0x%08x)\n", adapter->name, params->filters);
-		return -EINVAL;
-	}
-
-	al_reg_write32_masked(
-		&adapter->ec_regs_base->rfw.filter,
-		AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id) << 16,
-		params->filters << 16);
-
-	reg = al_reg_read32(&adapter->ec_regs_base->rfw.default_or);
-	AL_REG_FIELD_SET(reg, EC_RFW_DEFAULT_OR_UDMA_MASK, EC_RFW_DEFAULT_OR_UDMA_SHIFT, params->udma);
-	AL_REG_FIELD_SET(reg, EC_RFW_DEFAULT_OR_QUEUE_MASK, EC_RFW_DEFAULT_OR_QUEUE_SHIFT, params->qid);
-	al_reg_write32(&adapter->ec_regs_base->rfw.default_or, reg);
-	return 0;
-}
-
-
-
-int al_eth_switching_default_bitmap_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t udma_uc_bitmask,
-						uint8_t udma_mc_bitmask,uint8_t udma_bc_bitmask)
-{
-	al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].uc_udma, udma_uc_bitmask);
-	al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].mc_udma, udma_mc_bitmask);
-	al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].bc_udma, udma_bc_bitmask);
-
-	return 0;
-}
-
-int al_eth_flow_control_config(struct al_hal_eth_adapter *adapter, struct al_eth_flow_control_params *params)
-{
-	uint32_t reg;
-	int i;
-	al_assert(params); /* valid params pointer */
-
-	switch(params->type){
-	case AL_ETH_FLOW_CONTROL_TYPE_LINK_PAUSE:
-		al_dbg("[%s]: config flow control to link pause mode.\n", adapter->name);
-
-		/* config the mac */
-		if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
-			/* set quanta value */
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_1g.pause_quant,
-				params->quanta);
-			al_reg_write32(
-				&adapter->ec_regs_base->efc.xoff_timer_1g,
-				params->quanta_th);
-
-		} else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
-			/* set quanta value */
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl01_pause_quanta,
-				params->quanta);
-			/* set quanta threshold value */
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl01_quanta_thresh,
-				params->quanta_th);
-		} else {
-			/* set quanta value */
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL01_PAUSE_QUANTA_ADDR,
-				params->quanta);
-			/* set quanta threshold value */
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL01_QUANTA_THRESH_ADDR,
-				params->quanta_th);
-		}
-
-		if (params->obay_enable == AL_TRUE)
-			/* Tx path FIFO, unmask pause_on from MAC when PAUSE packet received */
-			al_reg_write32(&adapter->ec_regs_base->efc.ec_pause, 1);
-		else
-			al_reg_write32(&adapter->ec_regs_base->efc.ec_pause, 0);
-
-
-		/* Rx path */
-		if (params->gen_enable == AL_TRUE)
-			/* enable generating xoff from ec fifo almost full indication in hysteresis mode */
-			al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 1 << EC_EFC_EC_XOFF_MASK_2_SHIFT);
-		else
-			al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0);
-
-		if (AL_ETH_IS_1G_MAC(adapter->mac_mode))
-			/* in 1G mode, enable generating xon from ec fifo in hysteresis mode*/
-			al_reg_write32(&adapter->ec_regs_base->efc.xon, EC_EFC_XON_MASK_2 | EC_EFC_XON_MASK_1);
-
-		/* set hysteresis mode thresholds */
-		al_reg_write32(&adapter->ec_regs_base->efc.rx_fifo_hyst, params->rx_fifo_th_low | (params->rx_fifo_th_high << EC_EFC_RX_FIFO_HYST_TH_HIGH_SHIFT));
-
-		for (i = 0; i < 4; i++) {
-			if (params->obay_enable == AL_TRUE)
-				/* Tx path UDMA, unmask pause_on for all queues */
-				al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0,
-						params->prio_q_map[i][0]);
-			else
-				al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0, 0);
-
-			if (params->gen_enable == AL_TRUE)
-				/* Rx path UDMA, enable generating xoff from UDMA queue almost full indication */
-				al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0, params->prio_q_map[i][0]);
-			else
-				al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0, 0);
-		}
-	break;
-	case AL_ETH_FLOW_CONTROL_TYPE_PFC:
-		al_dbg("[%s]: config flow control to PFC mode.\n", adapter->name);
-		al_assert(!AL_ETH_IS_1G_MAC(adapter->mac_mode)); /* pfc not available for RGMII mode */;
-
-		for (i = 0; i < 4; i++) {
-			int prio;
-			for (prio = 0; prio < 8; prio++) {
-				if (params->obay_enable == AL_TRUE)
-					/* Tx path UDMA, unmask pause_on for all queues */
-					al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0 + prio,
-							params->prio_q_map[i][prio]);
-				else
-					al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0 + prio,
-							0);
-
-				if (params->gen_enable == AL_TRUE)
-					al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0 + prio,
-							params->prio_q_map[i][prio]);
-				else
-					al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0 + prio,
-							0);
-			}
-		}
-
-		/* Rx path */
-		/* enable generating xoff from ec fifo almost full indication in hysteresis mode */
-		if (params->gen_enable == AL_TRUE)
-			al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0xFF << EC_EFC_EC_XOFF_MASK_2_SHIFT);
-		else
-			al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0);
-
-		/* set hysteresis mode thresholds */
-		al_reg_write32(&adapter->ec_regs_base->efc.rx_fifo_hyst, params->rx_fifo_th_low | (params->rx_fifo_th_high << EC_EFC_RX_FIFO_HYST_TH_HIGH_SHIFT));
-
-		if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
-			/* config the 10g_mac */
-			/* set quanta value (same value for all prios) */
-			reg = params->quanta | (params->quanta << 16);
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl01_pause_quanta, reg);
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl23_pause_quanta, reg);
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl45_pause_quanta, reg);
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl67_pause_quanta, reg);
-			/* set quanta threshold value (same value for all prios) */
-			reg = params->quanta_th | (params->quanta_th << 16);
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl01_quanta_thresh, reg);
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl23_quanta_thresh, reg);
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl45_quanta_thresh, reg);
-			al_reg_write32(
-				&adapter->mac_regs_base->mac_10g.cl67_quanta_thresh, reg);
-
-			/* enable PFC in the 10g_MAC */
-			reg = al_reg_read32(&adapter->mac_regs_base->mac_10g.cmd_cfg);
-			reg |= 1 << 19;
-			al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, reg);
-		} else {
-			/* config the 40g_mac */
-			/* set quanta value (same value for all prios) */
-			reg = params->quanta | (params->quanta << 16);
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL01_PAUSE_QUANTA_ADDR, reg);
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL23_PAUSE_QUANTA_ADDR, reg);
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL45_PAUSE_QUANTA_ADDR, reg);
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL67_PAUSE_QUANTA_ADDR, reg);
-			/* set quanta threshold value (same value for all prios) */
-			reg = params->quanta_th | (params->quanta_th << 16);
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL01_QUANTA_THRESH_ADDR, reg);
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL23_QUANTA_THRESH_ADDR, reg);
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL45_QUANTA_THRESH_ADDR, reg);
-			al_eth_40g_mac_reg_write(adapter,
-				ETH_MAC_GEN_V3_MAC_40G_CL67_QUANTA_THRESH_ADDR, reg);
-
-			/* enable PFC in the 40g_MAC */
-			reg = al_reg_read32(&adapter->mac_regs_base->mac_10g.cmd_cfg);
-			reg |= 1 << 19;
-			al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, reg);
-			reg = al_eth_40g_mac_reg_read(adapter, ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR);
-
-			reg |= ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_PFC_MODE;
-
-			al_eth_40g_mac_reg_write(adapter, ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR, reg);
-		}
-
-	break;
-	default:
-		al_err("[%s]: unsupported flow control type %d\n", adapter->name, params->type);
-		return -EINVAL;
-
-	}
-	return 0;
-}
-
-int al_eth_vlan_mod_config(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint16_t udma_etype, uint16_t vlan1_data, uint16_t vlan2_data)
-{
-	al_dbg("[%s]: config vlan modification registers. udma id %d.\n", adapter->name, udma_id);
-
-	al_reg_write32(&adapter->ec_regs_base->tpm_sel[udma_id].etype, udma_etype);
-	al_reg_write32(&adapter->ec_regs_base->tpm_udma[udma_id].vlan_data, vlan1_data | (vlan2_data << 16));
-
-	return 0;
-}
-
-int al_eth_eee_get(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params)
-{
-	uint32_t reg;
-
-	al_dbg("[%s]: getting eee.\n", adapter->name);
-
-	reg = al_reg_read32(&adapter->ec_regs_base->eee.cfg_e);
-	params->enable = (reg & EC_EEE_CFG_E_ENABLE) ? AL_TRUE : AL_FALSE;
-
-	params->tx_eee_timer = al_reg_read32(&adapter->ec_regs_base->eee.pre_cnt);
-	params->min_interval = al_reg_read32(&adapter->ec_regs_base->eee.post_cnt);
-	params->stop_cnt = al_reg_read32(&adapter->ec_regs_base->eee.stop_cnt);
-
-	return 0;
-}
-
-
-int al_eth_eee_config(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params)
-{
-	uint32_t reg;
-	al_dbg("[%s]: config eee.\n", adapter->name);
-
-	if (params->enable == 0) {
-		al_dbg("[%s]: disable eee.\n", adapter->name);
-		al_reg_write32(&adapter->ec_regs_base->eee.cfg_e, 0);
-		return 0;
-	}
-	if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
-		al_reg_write32_masked(
-			&adapter->mac_regs_base->kr.pcs_cfg,
-			ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK,
-			((AL_ETH_IS_10G_MAC(adapter->mac_mode)) ?
-			ETH_MAC_KR_10_PCS_CFG_EEE_TIMER_VAL :
-			ETH_MAC_KR_25_PCS_CFG_EEE_TIMER_VAL) <<
-			ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT);
-	}
-	if ((adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G) ||
-		(adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_50G)) {
-		al_reg_write32_masked(
-			&adapter->mac_regs_base->gen_v3.pcs_40g_ll_eee_cfg,
-			ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK,
-			((adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G) ?
-			ETH_MAC_XLG_40_PCS_CFG_EEE_TIMER_VAL :
-			ETH_MAC_XLG_50_PCS_CFG_EEE_TIMER_VAL) <<
-			ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT);
-		/* set Deep sleep mode as the LPI function (instead of Fast wake mode) */
-		al_eth_40g_pcs_reg_write(adapter, ETH_MAC_GEN_V3_PCS_40G_EEE_CONTROL_ADDR,
-			params->fast_wake ? 1 : 0);
-	}
-
-	al_reg_write32(&adapter->ec_regs_base->eee.pre_cnt, params->tx_eee_timer);
-	al_reg_write32(&adapter->ec_regs_base->eee.post_cnt, params->min_interval);
-	al_reg_write32(&adapter->ec_regs_base->eee.stop_cnt, params->stop_cnt);
-
-	reg = EC_EEE_CFG_E_MASK_EC_TMI_STOP | EC_EEE_CFG_E_MASK_MAC_EEE |
-	       EC_EEE_CFG_E_ENABLE |
-	       EC_EEE_CFG_E_USE_EC_TX_FIFO | EC_EEE_CFG_E_USE_EC_RX_FIFO;
-
-	/*
-	 * Addressing RMN: 3732
-	 *
-	 * RMN description:
-	 * When the HW get into eee mode, it can't transmit any pause packet
-	 * (when flow control policy is enabled).
-	 * In such case, the HW has no way to handle extreme pushback from
-	 * the Rx_path fifos.
-	 *
-	 * Software flow:
-	 * Configure RX_FIFO empty as eee mode term.
-	 * That way, nothing will prevent pause packet transmittion in
-	 * case of extreme pushback from the Rx_path fifos.
-	 *
-	 */
-
-	al_reg_write32(&adapter->ec_regs_base->eee.cfg_e, reg);
-
-	return 0;
-}
-
-/* Timestamp */
-/* prepare the adapter for doing Timestamps for Rx packets. */
-int al_eth_ts_init(struct al_hal_eth_adapter *adapter)
-{
-	uint32_t reg;
-
-	/*TODO:
-	 * return error when:
-	 * - working in 1G mode and MACSEC enabled
-	 * - RX completion descriptor is not 8 words
-	 */
-	reg = al_reg_read32(&adapter->ec_regs_base->gen.en_ext);
-	if (AL_ETH_IS_1G_MAC(adapter->mac_mode))
-		reg &= ~EC_GEN_EN_EXT_PTH_1_10_SEL;
-	else
-		reg |= EC_GEN_EN_EXT_PTH_1_10_SEL;
-	/*
-	 * set completion bypass so tx timestamps won't be inserted to tx cmpl
-	 * (in order to disable unverified flow)
-	 */
-	reg |= EC_GEN_EN_EXT_PTH_COMPLETION_BYPASS;
-	al_reg_write32(&adapter->ec_regs_base->gen.en_ext, reg);
-
-	/*TODO: add the following when we have updated regs file:
-	 * reg_rfw_out_cfg_timestamp_sample_out
-		0 (default) – use the timestamp from the SOP info (10G MAC)
-		1 – use the timestamp from the EOP (1G MAC) (noly when MACSEC is disabled)
-	 */
-	return 0;
-}
-
-/* read Timestamp sample value of previously transmitted packet. */
-int al_eth_tx_ts_val_get(struct al_hal_eth_adapter *adapter, uint8_t ts_index,
-			 uint32_t *timestamp)
-{
-	al_assert(ts_index < AL_ETH_PTH_TX_SAMPLES_NUM);
-
-	/* in 1G mode, only indexes 1-7 are allowed*/
-	if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
-		al_assert(ts_index <= 7);
-		al_assert(ts_index >= 1);
-	}
-
-	/*TODO: check if sample is valid */
-	*timestamp = al_reg_read32(&adapter->ec_regs_base->pth_db[ts_index].ts);
-	return 0;
-}
-
-/* Read the systime value */
-int al_eth_pth_systime_read(struct al_hal_eth_adapter *adapter,
-			    struct al_eth_pth_time *systime)
-{
-	uint32_t reg;
-
-	/* first we must read the subseconds MSB so the seconds register will be
-	 * shadowed
-	 */
-	reg = al_reg_read32(&adapter->ec_regs_base->pth.system_time_subseconds_msb);
-	systime->femto = (uint64_t)reg << 18;
-	reg = al_reg_read32(&adapter->ec_regs_base->pth.system_time_seconds);
-	systime->seconds = reg;
-
-	return 0;
-}
-
-/* Set the clock period to a given value. */
-int al_eth_pth_clk_period_write(struct al_hal_eth_adapter *adapter,
-				uint64_t clk_period)
-{
-	uint32_t reg;
-	/* first write the LSB so it will be shadowed */
-	/* bits 31:14 of the clock period lsb register contains bits 17:0 of the
-	 * period.
-	 */
-	reg = (clk_period & AL_BIT_MASK(18)) << EC_PTH_CLOCK_PERIOD_LSB_VAL_SHIFT;
-	al_reg_write32(&adapter->ec_regs_base->pth.clock_period_lsb, reg);
-	reg = clk_period >> 18;
-	al_reg_write32(&adapter->ec_regs_base->pth.clock_period_msb, reg);
-
-	return 0;
-}
-
-/* Configure the systime internal update */
-int al_eth_pth_int_update_config(struct al_hal_eth_adapter *adapter,
-				 struct al_eth_pth_int_update_params *params)
-{
-	uint32_t reg;
-
-	reg = al_reg_read32(&adapter->ec_regs_base->pth.int_update_ctrl);
-	if (params->enable == AL_FALSE) {
-		reg &= ~EC_PTH_INT_UPDATE_CTRL_INT_TRIG_EN;
-	} else {
-		reg |= EC_PTH_INT_UPDATE_CTRL_INT_TRIG_EN;
-		AL_REG_FIELD_SET(reg, EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_MASK,
-				 EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_SHIFT,
-				 params->method);
-		if (params->trigger == AL_ETH_PTH_INT_TRIG_REG_WRITE)
-			reg |= EC_PTH_INT_UPDATE_CTRL_UPDATE_TRIG;
-		else
-			reg &= ~EC_PTH_INT_UPDATE_CTRL_UPDATE_TRIG;
-	}
-	al_reg_write32(&adapter->ec_regs_base->pth.int_update_ctrl, reg);
-	return 0;
-}
-/* set internal update time */
-int al_eth_pth_int_update_time_set(struct al_hal_eth_adapter *adapter,
-				   struct al_eth_pth_time *time)
-{
-	uint32_t reg;
-
-	al_reg_write32(&adapter->ec_regs_base->pth.int_update_seconds,
-		       time->seconds);
-	reg = time->femto & AL_BIT_MASK(18);
-	reg = reg << EC_PTH_INT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT;
-	al_reg_write32(&adapter->ec_regs_base->pth.int_update_subseconds_lsb,
-		       reg);
-	reg = time->femto >> 18;
-	al_reg_write32(&adapter->ec_regs_base->pth.int_update_subseconds_msb,
-		       reg);
-
-	return 0;
-}
-
-/* Configure the systime external update */
-int al_eth_pth_ext_update_config(struct al_hal_eth_adapter *adapter,
-				 struct al_eth_pth_ext_update_params * params)
-{
-	uint32_t reg;
-
-	reg = al_reg_read32(&adapter->ec_regs_base->pth.int_update_ctrl);
-	AL_REG_FIELD_SET(reg, EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_MASK,
-			 EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_SHIFT,
-			 params->method);
-
-	AL_REG_FIELD_SET(reg, EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_MASK,
-			 EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_SHIFT,
-			 params->triggers);
-	al_reg_write32(&adapter->ec_regs_base->pth.int_update_ctrl, reg);
-	return 0;
-}
-
-/* set external update time */
-int al_eth_pth_ext_update_time_set(struct al_hal_eth_adapter *adapter,
-				   struct al_eth_pth_time *time)
-{
-	uint32_t reg;
-
-	al_reg_write32(&adapter->ec_regs_base->pth.ext_update_seconds,
-		       time->seconds);
-	reg = time->femto & AL_BIT_MASK(18);
-	reg = reg << EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT;
-	al_reg_write32(&adapter->ec_regs_base->pth.ext_update_subseconds_lsb,
-		       reg);
-	reg = time->femto >> 18;
-	al_reg_write32(&adapter->ec_regs_base->pth.ext_update_subseconds_msb,
-		       reg);
-
-	return 0;
-};
-
-/* set the read compensation delay */
-int al_eth_pth_read_compensation_set(struct al_hal_eth_adapter *adapter,
-				     uint64_t subseconds)
-{
-	uint32_t reg;
-
-	/* first write to lsb to ensure atomicity */
-	reg = (subseconds & AL_BIT_MASK(18)) << EC_PTH_READ_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT;
-	al_reg_write32(&adapter->ec_regs_base->pth.read_compensation_subseconds_lsb, reg);
-
-	reg = subseconds >> 18;
-	al_reg_write32(&adapter->ec_regs_base->pth.read_compensation_subseconds_msb, reg);
-	return 0;
-}
-
-/* set the internal write compensation delay */
-int al_eth_pth_int_write_compensation_set(struct al_hal_eth_adapter *adapter,
-					  uint64_t subseconds)
-{
-	uint32_t reg;
-
-	/* first write to lsb to ensure atomicity */
-	reg = (subseconds & AL_BIT_MASK(18)) << EC_PTH_INT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT;
-	al_reg_write32(&adapter->ec_regs_base->pth.int_write_compensation_subseconds_lsb, reg);
-
-	reg = subseconds >> 18;
-	al_reg_write32(&adapter->ec_regs_base->pth.int_write_compensation_subseconds_msb, reg);
-	return 0;
-}
-
-/* set the external write compensation delay */
-int al_eth_pth_ext_write_compensation_set(struct al_hal_eth_adapter *adapter,
-					  uint64_t subseconds)
-{
-	uint32_t reg;
-
-	/* first write to lsb to ensure atomicity */
-	reg = (subseconds & AL_BIT_MASK(18)) << EC_PTH_EXT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT;
-	al_reg_write32(&adapter->ec_regs_base->pth.ext_write_compensation_subseconds_lsb, reg);
-
-	reg = subseconds >> 18;
-	al_reg_write32(&adapter->ec_regs_base->pth.ext_write_compensation_subseconds_msb, reg);
-	return 0;
-}
-
-/* set the sync compensation delay */
-int al_eth_pth_sync_compensation_set(struct al_hal_eth_adapter *adapter,
-				     uint64_t subseconds)
-{
-	uint32_t reg;
-
-	/* first write to lsb to ensure atomicity */
-	reg = (subseconds & AL_BIT_MASK(18)) << EC_PTH_SYNC_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT;
-	al_reg_write32(&adapter->ec_regs_base->pth.sync_compensation_subseconds_lsb, reg);
-
-	reg = subseconds >> 18;
-	al_reg_write32(&adapter->ec_regs_base->pth.sync_compensation_subseconds_msb, reg);
-	return 0;
-}
-
-/* Configure an output pulse */
-int al_eth_pth_pulse_out_config(struct al_hal_eth_adapter *adapter,
-				struct al_eth_pth_pulse_out_params *params)
-{
-	uint32_t reg;
-
-	if (params->index >= AL_ETH_PTH_PULSE_OUT_NUM) {
-		al_err("eth [%s] PTH out pulse index out of range\n",
-				 adapter->name);
-		return -EINVAL;
-	}
-	reg = al_reg_read32(&adapter->ec_regs_base->pth_egress[params->index].trigger_ctrl);
-	if (params->enable == AL_FALSE) {
-		reg &= ~EC_PTH_EGRESS_TRIGGER_CTRL_EN;
-	} else {
-		reg |= EC_PTH_EGRESS_TRIGGER_CTRL_EN;
-		if (params->periodic == AL_FALSE)
-			reg &= ~EC_PTH_EGRESS_TRIGGER_CTRL_PERIODIC;
-		else
-			reg |= EC_PTH_EGRESS_TRIGGER_CTRL_PERIODIC;
-
-		AL_REG_FIELD_SET(reg, EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_MASK,
-				 EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_SHIFT,
-				 params->period_us);
-		AL_REG_FIELD_SET(reg, EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_MASK,
-				 EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_SHIFT,
-				 params->period_sec);
-	}
-	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_ctrl, reg);
-
-	/* set trigger time */
-	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_seconds,
-		       params->start_time.seconds);
-	reg = params->start_time.femto & AL_BIT_MASK(18);
-	reg = reg << EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_VAL_SHIFT;
-	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_subseconds_lsb,
-		       reg);
-	reg = params->start_time.femto >> 18;
-	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_subseconds_msb,
-		       reg);
-
-	/* set pulse width */
-	reg = params->pulse_width & AL_BIT_MASK(18);
-	reg = reg << EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_VAL_SHIFT;
-	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].pulse_width_subseconds_lsb, reg);
-
-	reg = params->pulse_width  >> 18;
-	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].pulse_width_subseconds_msb, reg);
-
-	return 0;
-}
-
-/** get link status */
-int al_eth_link_status_get(struct al_hal_eth_adapter *adapter,
-			   struct al_eth_link_status *status)
-{
-	uint32_t reg;
-
-	if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
-		status->link_up = AL_FALSE;
-		status->local_fault = AL_TRUE;
-		status->remote_fault = AL_TRUE;
-
-		al_reg_write32(&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_BASE_R_STATUS2);
-		reg = al_reg_read32(&adapter->mac_regs_base->kr.pcs_data);
-
-		if (reg & AL_BIT(15)) {
-			reg = al_reg_read32(&adapter->mac_regs_base->mac_10g.status);
-
-			status->remote_fault = ((reg & ETH_MAC_GEN_MAC_10G_STAT_REM_FAULT) ?
-							AL_TRUE : AL_FALSE);
-			status->local_fault = ((reg & ETH_MAC_GEN_MAC_10G_STAT_LOC_FAULT) ?
-							AL_TRUE : AL_FALSE);
-
-			status->link_up = ((status->remote_fault == AL_FALSE) &&
-					   (status->local_fault == AL_FALSE));
-		}
-
-	} else if (adapter->mac_mode == AL_ETH_MAC_MODE_SGMII) {
-		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 1);
-		/*
-		 * This register is latched low so need to read twice to get
-		 * the current link status
-		 */
-		reg = al_reg_read32(&adapter->mac_regs_base->sgmii.reg_data);
-		reg = al_reg_read32(&adapter->mac_regs_base->sgmii.reg_data);
-
-		status->link_up = AL_FALSE;
-
-		if (reg & AL_BIT(2))
-			status->link_up = AL_TRUE;
-
-		reg = al_reg_read32(&adapter->mac_regs_base->sgmii.link_stat);
-
-		if ((reg & AL_BIT(3)) == 0)
-			status->link_up = AL_FALSE;
-
-	} else if (adapter->mac_mode == AL_ETH_MAC_MODE_RGMII) {
-		reg = al_reg_read32(&adapter->mac_regs_base->gen.rgmii_stat);
-
-		status->link_up = AL_FALSE;
-
-		if (reg & AL_BIT(4))
-			status->link_up = AL_TRUE;
-
-	} else if (adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_25G) {
-		status->link_up = AL_FALSE;
-		status->local_fault = AL_TRUE;
-		status->remote_fault = AL_TRUE;
-
-		reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_status);
-
-		status->link_up = AL_FALSE;
-
-		if ((reg & 0xF) == 0xF) {
-			reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_status);
-
-			status->remote_fault = ((reg & ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_REM_FAULT) ?
-							AL_TRUE : AL_FALSE);
-			status->local_fault = ((reg & ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LOC_FAULT) ?
-							AL_TRUE : AL_FALSE);
-
-			status->link_up = ((status->remote_fault == AL_FALSE) &&
-					   (status->local_fault == AL_FALSE));
-		}
-
-	} else if ((adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G) ||
-			(adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_50G)) {
-		reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_status);
-
-		status->link_up = AL_FALSE;
-
-		if ((reg & 0x1F) == 0x1F) {
-			reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_status);
-			if ((reg & (ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_REM_FAULT |
-					ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LOC_FAULT)) == 0)
-				status->link_up = AL_TRUE;
-		}
-
-	} else {
-		/* not implemented yet */
-		return -EPERM;
-	}
-
-	al_dbg("[%s]: mac %s port. link_status: %s.\n", adapter->name,
-		al_eth_mac_mode_str(adapter->mac_mode),
-		(status->link_up == AL_TRUE) ? "LINK_UP" : "LINK_DOWN");
-
-	return 0;
-}
-
-int al_eth_link_status_clear(struct al_hal_eth_adapter *adapter)
-{
-	int status = 0;
-
-	if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
-		al_reg_write32(&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_BASE_R_STATUS2);
-		al_reg_read32(&adapter->mac_regs_base->kr.pcs_data);
-
-		al_reg_read32(&adapter->mac_regs_base->mac_10g.status);
-	} else {
-		status = -1;
-	}
-
-	return status;
-}
-
-/** set LED mode and value */
-int al_eth_led_set(struct al_hal_eth_adapter *adapter, al_bool link_is_up)
-{
-	uint32_t reg = 0;
-	uint32_t mode  = ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG;
-
-	if (link_is_up)
-		mode = ETH_MAC_GEN_LED_CFG_SEL_LINK_ACTIVITY;
-
-	AL_REG_FIELD_SET(reg,  ETH_MAC_GEN_LED_CFG_SEL_MASK,
-			 ETH_MAC_GEN_LED_CFG_SEL_SHIFT, mode);
-
-	AL_REG_FIELD_SET(reg, ETH_MAC_GEN_LED_CFG_BLINK_TIMER_MASK,
-			 ETH_MAC_GEN_LED_CFG_BLINK_TIMER_SHIFT,
-			 ETH_MAC_GEN_LED_CFG_BLINK_TIMER_VAL);
-
-	AL_REG_FIELD_SET(reg, ETH_MAC_GEN_LED_CFG_ACT_TIMER_MASK,
-			 ETH_MAC_GEN_LED_CFG_ACT_TIMER_SHIFT,
-			 ETH_MAC_GEN_LED_CFG_ACT_TIMER_VAL);
-
-	al_reg_write32(&adapter->mac_regs_base->gen.led_cfg, reg);
-
-	return 0;
-}
-
-/* get statistics */
-int al_eth_mac_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_mac_stats *stats)
-{
-	al_assert(stats);
-
-	al_memset(stats, 0, sizeof(struct al_eth_mac_stats));
-
-	if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
-		struct al_eth_mac_1g_stats __iomem *reg_stats =
-			&adapter->mac_regs_base->mac_1g.stats;
-
-		stats->ifInUcastPkts = al_reg_read32(&reg_stats->ifInUcastPkts);
-		stats->ifInMulticastPkts = al_reg_read32(&reg_stats->ifInMulticastPkts);
-		stats->ifInBroadcastPkts = al_reg_read32(&reg_stats->ifInBroadcastPkts);
-		stats->etherStatsPkts = al_reg_read32(&reg_stats->etherStatsPkts);
-		stats->ifOutUcastPkts = al_reg_read32(&reg_stats->ifOutUcastPkts);
-		stats->ifOutMulticastPkts = al_reg_read32(&reg_stats->ifOutMulticastPkts);
-		stats->ifOutBroadcastPkts = al_reg_read32(&reg_stats->ifOutBroadcastPkts);
-		stats->ifInErrors = al_reg_read32(&reg_stats->ifInErrors);
-		stats->ifOutErrors = al_reg_read32(&reg_stats->ifOutErrors);
-		stats->aFramesReceivedOK = al_reg_read32(&reg_stats->aFramesReceivedOK);
-		stats->aFramesTransmittedOK = al_reg_read32(&reg_stats->aFramesTransmittedOK);
-		stats->aOctetsReceivedOK = al_reg_read32(&reg_stats->aOctetsReceivedOK);
-		stats->aOctetsTransmittedOK = al_reg_read32(&reg_stats->aOctetsTransmittedOK);
-		stats->etherStatsUndersizePkts = al_reg_read32(&reg_stats->etherStatsUndersizePkts);
-		stats->etherStatsFragments = al_reg_read32(&reg_stats->etherStatsFragments);
-		stats->etherStatsJabbers = al_reg_read32(&reg_stats->etherStatsJabbers);
-		stats->etherStatsOversizePkts = al_reg_read32(&reg_stats->etherStatsOversizePkts);
-		stats->aFrameCheckSequenceErrors =
-			al_reg_read32(&reg_stats->aFrameCheckSequenceErrors);
-		stats->aAlignmentErrors = al_reg_read32(&reg_stats->aAlignmentErrors);
-		stats->etherStatsDropEvents = al_reg_read32(&reg_stats->etherStatsDropEvents);
-		stats->aPAUSEMACCtrlFramesTransmitted =
-			al_reg_read32(&reg_stats->aPAUSEMACCtrlFramesTransmitted);
-		stats->aPAUSEMACCtrlFramesReceived =
-			al_reg_read32(&reg_stats->aPAUSEMACCtrlFramesReceived);
-		stats->aFrameTooLongErrors = 0; /* N/A */
-		stats->aInRangeLengthErrors = 0; /* N/A */
-		stats->VLANTransmittedOK = 0; /* N/A */
-		stats->VLANReceivedOK = 0; /* N/A */
-		stats->etherStatsOctets = al_reg_read32(&reg_stats->etherStatsOctets);
-		stats->etherStatsPkts64Octets = al_reg_read32(&reg_stats->etherStatsPkts64Octets);
-		stats->etherStatsPkts65to127Octets =
-			al_reg_read32(&reg_stats->etherStatsPkts65to127Octets);
-		stats->etherStatsPkts128to255Octets =
-			al_reg_read32(&reg_stats->etherStatsPkts128to255Octets);
-		stats->etherStatsPkts256to511Octets =
-			al_reg_read32(&reg_stats->etherStatsPkts256to511Octets);
-		stats->etherStatsPkts512to1023Octets =
-			al_reg_read32(&reg_stats->etherStatsPkts512to1023Octets);
-		stats->etherStatsPkts1024to1518Octets =
-			al_reg_read32(&reg_stats->etherStatsPkts1024to1518Octets);
-		stats->etherStatsPkts1519toX = al_reg_read32(&reg_stats->etherStatsPkts1519toX);
-	} else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
-		if (adapter->rev_id < AL_ETH_REV_ID_3) {
-			struct al_eth_mac_10g_stats_v2 __iomem *reg_stats =
-				&adapter->mac_regs_base->mac_10g.stats.v2;
-			uint64_t octets;
-
-			stats->ifInUcastPkts = al_reg_read32(&reg_stats->ifInUcastPkts);
-			stats->ifInMulticastPkts = al_reg_read32(&reg_stats->ifInMulticastPkts);
-			stats->ifInBroadcastPkts = al_reg_read32(&reg_stats->ifInBroadcastPkts);
-			stats->etherStatsPkts = al_reg_read32(&reg_stats->etherStatsPkts);
-			stats->ifOutUcastPkts = al_reg_read32(&reg_stats->ifOutUcastPkts);
-			stats->ifOutMulticastPkts = al_reg_read32(&reg_stats->ifOutMulticastPkts);
-			stats->ifOutBroadcastPkts = al_reg_read32(&reg_stats->ifOutBroadcastPkts);
-			stats->ifInErrors = al_reg_read32(&reg_stats->ifInErrors);
-			stats->ifOutErrors = al_reg_read32(&reg_stats->ifOutErrors);
-			stats->aFramesReceivedOK = al_reg_read32(&reg_stats->aFramesReceivedOK);
-			stats->aFramesTransmittedOK = al_reg_read32(&reg_stats->aFramesTransmittedOK);
-
-			/* aOctetsReceivedOK = ifInOctets - 18 * aFramesReceivedOK - 4 * VLANReceivedOK */
-			octets = al_reg_read32(&reg_stats->ifInOctetsL);
-			octets |= (uint64_t)(al_reg_read32(&reg_stats->ifInOctetsH)) << 32;
-			octets -= 18 * stats->aFramesReceivedOK;
-			octets -= 4 * al_reg_read32(&reg_stats->VLANReceivedOK);
-			stats->aOctetsReceivedOK = octets;
-
-			/* aOctetsTransmittedOK = ifOutOctets - 18 * aFramesTransmittedOK - 4 * VLANTransmittedOK */
-			octets = al_reg_read32(&reg_stats->ifOutOctetsL);
-			octets |= (uint64_t)(al_reg_read32(&reg_stats->ifOutOctetsH)) << 32;
-			octets -= 18 * stats->aFramesTransmittedOK;
-			octets -= 4 * al_reg_read32(&reg_stats->VLANTransmittedOK);
-			stats->aOctetsTransmittedOK = octets;
-
-			stats->etherStatsUndersizePkts = al_reg_read32(&reg_stats->etherStatsUndersizePkts);
-			stats->etherStatsFragments = al_reg_read32(&reg_stats->etherStatsFragments);
-			stats->etherStatsJabbers = al_reg_read32(&reg_stats->etherStatsJabbers);
-			stats->etherStatsOversizePkts = al_reg_read32(&reg_stats->etherStatsOversizePkts);
-			stats->aFrameCheckSequenceErrors = al_reg_read32(&reg_stats->aFrameCheckSequenceErrors);
-			stats->aAlignmentErrors = al_reg_read32(&reg_stats->aAlignmentErrors);
-			stats->etherStatsDropEvents = al_reg_read32(&reg_stats->etherStatsDropEvents);
-			stats->aPAUSEMACCtrlFramesTransmitted = al_reg_read32(&reg_stats->aPAUSEMACCtrlFramesTransmitted);
-			stats->aPAUSEMACCtrlFramesReceived = al_reg_read32(&reg_stats->aPAUSEMACCtrlFramesReceived);
-			stats->aFrameTooLongErrors = al_reg_read32(&reg_stats->aFrameTooLongErrors);
-			stats->aInRangeLengthErrors = al_reg_read32(&reg_stats->aInRangeLengthErrors);
-			stats->VLANTransmittedOK = al_reg_read32(&reg_stats->VLANTransmittedOK);
-			stats->VLANReceivedOK = al_reg_read32(&reg_stats->VLANReceivedOK);
-			stats->etherStatsOctets = al_reg_read32(&reg_stats->etherStatsOctets);
-			stats->etherStatsPkts64Octets = al_reg_read32(&reg_stats->etherStatsPkts64Octets);
-			stats->etherStatsPkts65to127Octets = al_reg_read32(&reg_stats->etherStatsPkts65to127Octets);
-			stats->etherStatsPkts128to255Octets = al_reg_read32(&reg_stats->etherStatsPkts128to255Octets);
-			stats->etherStatsPkts256to511Octets = al_reg_read32(&reg_stats->etherStatsPkts256to511Octets);
-			stats->etherStatsPkts512to1023Octets = al_reg_read32(&reg_stats->etherStatsPkts512to1023Octets);
-			stats->etherStatsPkts1024to1518Octets = al_reg_read32(&reg_stats->etherStatsPkts1024to1518Octets);
-			stats->etherStatsPkts1519toX = al_reg_read32(&reg_stats->etherStatsPkts1519toX);
-		} else {
-			struct al_eth_mac_10g_stats_v3_rx __iomem *reg_rx_stats =
-				&adapter->mac_regs_base->mac_10g.stats.v3.rx;
-			struct al_eth_mac_10g_stats_v3_tx __iomem *reg_tx_stats =
-				&adapter->mac_regs_base->mac_10g.stats.v3.tx;
-			uint64_t octets;
-
-			stats->ifInUcastPkts = al_reg_read32(&reg_rx_stats->ifInUcastPkts);
-			stats->ifInMulticastPkts = al_reg_read32(&reg_rx_stats->ifInMulticastPkts);
-			stats->ifInBroadcastPkts = al_reg_read32(&reg_rx_stats->ifInBroadcastPkts);
-			stats->etherStatsPkts = al_reg_read32(&reg_rx_stats->etherStatsPkts);
-			stats->ifOutUcastPkts = al_reg_read32(&reg_tx_stats->ifUcastPkts);
-			stats->ifOutMulticastPkts = al_reg_read32(&reg_tx_stats->ifMulticastPkts);
-			stats->ifOutBroadcastPkts = al_reg_read32(&reg_tx_stats->ifBroadcastPkts);
-			stats->ifInErrors = al_reg_read32(&reg_rx_stats->ifInErrors);
-			stats->ifOutErrors = al_reg_read32(&reg_tx_stats->ifOutErrors);
-			stats->aFramesReceivedOK = al_reg_read32(&reg_rx_stats->FramesOK);
-			stats->aFramesTransmittedOK = al_reg_read32(&reg_tx_stats->FramesOK);
-
-			/* aOctetsReceivedOK = ifInOctets - 18 * aFramesReceivedOK - 4 * VLANReceivedOK */
-			octets = al_reg_read32(&reg_rx_stats->ifOctetsL);
-			octets |= (uint64_t)(al_reg_read32(&reg_rx_stats->ifOctetsH)) << 32;
-			octets -= 18 * stats->aFramesReceivedOK;
-			octets -= 4 * al_reg_read32(&reg_rx_stats->VLANOK);
-			stats->aOctetsReceivedOK = octets;
-
-			/* aOctetsTransmittedOK = ifOutOctets - 18 * aFramesTransmittedOK - 4 * VLANTransmittedOK */
-			octets = al_reg_read32(&reg_tx_stats->ifOctetsL);
-			octets |= (uint64_t)(al_reg_read32(&reg_tx_stats->ifOctetsH)) << 32;
-			octets -= 18 * stats->aFramesTransmittedOK;
-			octets -= 4 * al_reg_read32(&reg_tx_stats->VLANOK);
-			stats->aOctetsTransmittedOK = octets;
-
-			stats->etherStatsUndersizePkts = al_reg_read32(&reg_rx_stats->etherStatsUndersizePkts);
-			stats->etherStatsFragments = al_reg_read32(&reg_rx_stats->etherStatsFragments);
-			stats->etherStatsJabbers = al_reg_read32(&reg_rx_stats->etherStatsJabbers);
-			stats->etherStatsOversizePkts = al_reg_read32(&reg_rx_stats->etherStatsOversizePkts);
-			stats->aFrameCheckSequenceErrors = al_reg_read32(&reg_rx_stats->CRCErrors);
-			stats->aAlignmentErrors = al_reg_read32(&reg_rx_stats->aAlignmentErrors);
-			stats->etherStatsDropEvents = al_reg_read32(&reg_rx_stats->etherStatsDropEvents);
-			stats->aPAUSEMACCtrlFramesTransmitted = al_reg_read32(&reg_tx_stats->aPAUSEMACCtrlFrames);
-			stats->aPAUSEMACCtrlFramesReceived = al_reg_read32(&reg_rx_stats->aPAUSEMACCtrlFrames);
-			stats->aFrameTooLongErrors = al_reg_read32(&reg_rx_stats->aFrameTooLong);
-			stats->aInRangeLengthErrors = al_reg_read32(&reg_rx_stats->aInRangeLengthErrors);
-			stats->VLANTransmittedOK = al_reg_read32(&reg_tx_stats->VLANOK);
-			stats->VLANReceivedOK = al_reg_read32(&reg_rx_stats->VLANOK);
-			stats->etherStatsOctets = al_reg_read32(&reg_rx_stats->etherStatsOctets);
-			stats->etherStatsPkts64Octets = al_reg_read32(&reg_rx_stats->etherStatsPkts64Octets);
-			stats->etherStatsPkts65to127Octets = al_reg_read32(&reg_rx_stats->etherStatsPkts65to127Octets);
-			stats->etherStatsPkts128to255Octets = al_reg_read32(&reg_rx_stats->etherStatsPkts128to255Octets);
-			stats->etherStatsPkts256to511Octets = al_reg_read32(&reg_rx_stats->etherStatsPkts256to511Octets);
-			stats->etherStatsPkts512to1023Octets = al_reg_read32(&reg_rx_stats->etherStatsPkts512to1023Octets);
-			stats->etherStatsPkts1024to1518Octets = al_reg_read32(&reg_rx_stats->etherStatsPkts1024to1518Octets);
-			stats->etherStatsPkts1519toX = al_reg_read32(&reg_rx_stats->etherStatsPkts1519toMax);
-		}
-	} else {
-		struct al_eth_mac_10g_stats_v3_rx __iomem *reg_rx_stats =
-			&adapter->mac_regs_base->mac_10g.stats.v3.rx;
-		struct al_eth_mac_10g_stats_v3_tx __iomem *reg_tx_stats =
-			&adapter->mac_regs_base->mac_10g.stats.v3.tx;
-		uint64_t octets;
-
-		/* 40G MAC statistics registers are the same, only read indirectly */
-		#define _40g_mac_reg_read32(field)	al_eth_40g_mac_reg_read(adapter,	\
-			((uint8_t *)(field)) - ((uint8_t *)&adapter->mac_regs_base->mac_10g))
-
-		stats->ifInUcastPkts = _40g_mac_reg_read32(&reg_rx_stats->ifInUcastPkts);
-		stats->ifInMulticastPkts = _40g_mac_reg_read32(&reg_rx_stats->ifInMulticastPkts);
-		stats->ifInBroadcastPkts = _40g_mac_reg_read32(&reg_rx_stats->ifInBroadcastPkts);
-		stats->etherStatsPkts = _40g_mac_reg_read32(&reg_rx_stats->etherStatsPkts);
-		stats->ifOutUcastPkts = _40g_mac_reg_read32(&reg_tx_stats->ifUcastPkts);
-		stats->ifOutMulticastPkts = _40g_mac_reg_read32(&reg_tx_stats->ifMulticastPkts);
-		stats->ifOutBroadcastPkts = _40g_mac_reg_read32(&reg_tx_stats->ifBroadcastPkts);
-		stats->ifInErrors = _40g_mac_reg_read32(&reg_rx_stats->ifInErrors);
-		stats->ifOutErrors = _40g_mac_reg_read32(&reg_tx_stats->ifOutErrors);
-		stats->aFramesReceivedOK = _40g_mac_reg_read32(&reg_rx_stats->FramesOK);
-		stats->aFramesTransmittedOK = _40g_mac_reg_read32(&reg_tx_stats->FramesOK);
-
-		/* aOctetsReceivedOK = ifInOctets - 18 * aFramesReceivedOK - 4 * VLANReceivedOK */
-		octets = _40g_mac_reg_read32(&reg_rx_stats->ifOctetsL);
-		octets |= (uint64_t)(_40g_mac_reg_read32(&reg_rx_stats->ifOctetsH)) << 32;
-		octets -= 18 * stats->aFramesReceivedOK;
-		octets -= 4 * _40g_mac_reg_read32(&reg_rx_stats->VLANOK);
-		stats->aOctetsReceivedOK = octets;
-
-		/* aOctetsTransmittedOK = ifOutOctets - 18 * aFramesTransmittedOK - 4 * VLANTransmittedOK */
-		octets = _40g_mac_reg_read32(&reg_tx_stats->ifOctetsL);
-		octets |= (uint64_t)(_40g_mac_reg_read32(&reg_tx_stats->ifOctetsH)) << 32;
-		octets -= 18 * stats->aFramesTransmittedOK;
-		octets -= 4 * _40g_mac_reg_read32(&reg_tx_stats->VLANOK);
-		stats->aOctetsTransmittedOK = octets;
-
-		stats->etherStatsUndersizePkts = _40g_mac_reg_read32(&reg_rx_stats->etherStatsUndersizePkts);
-		stats->etherStatsFragments = _40g_mac_reg_read32(&reg_rx_stats->etherStatsFragments);
-		stats->etherStatsJabbers = _40g_mac_reg_read32(&reg_rx_stats->etherStatsJabbers);
-		stats->etherStatsOversizePkts = _40g_mac_reg_read32(&reg_rx_stats->etherStatsOversizePkts);
-		stats->aFrameCheckSequenceErrors = _40g_mac_reg_read32(&reg_rx_stats->CRCErrors);
-		stats->aAlignmentErrors = _40g_mac_reg_read32(&reg_rx_stats->aAlignmentErrors);
-		stats->etherStatsDropEvents = _40g_mac_reg_read32(&reg_rx_stats->etherStatsDropEvents);
-		stats->aPAUSEMACCtrlFramesTransmitted = _40g_mac_reg_read32(&reg_tx_stats->aPAUSEMACCtrlFrames);
-		stats->aPAUSEMACCtrlFramesReceived = _40g_mac_reg_read32(&reg_rx_stats->aPAUSEMACCtrlFrames);
-		stats->aFrameTooLongErrors = _40g_mac_reg_read32(&reg_rx_stats->aFrameTooLong);
-		stats->aInRangeLengthErrors = _40g_mac_reg_read32(&reg_rx_stats->aInRangeLengthErrors);
-		stats->VLANTransmittedOK = _40g_mac_reg_read32(&reg_tx_stats->VLANOK);
-		stats->VLANReceivedOK = _40g_mac_reg_read32(&reg_rx_stats->VLANOK);
-		stats->etherStatsOctets = _40g_mac_reg_read32(&reg_rx_stats->etherStatsOctets);
-		stats->etherStatsPkts64Octets = _40g_mac_reg_read32(&reg_rx_stats->etherStatsPkts64Octets);
-		stats->etherStatsPkts65to127Octets = _40g_mac_reg_read32(&reg_rx_stats->etherStatsPkts65to127Octets);
-		stats->etherStatsPkts128to255Octets = _40g_mac_reg_read32(&reg_rx_stats->etherStatsPkts128to255Octets);
-		stats->etherStatsPkts256to511Octets = _40g_mac_reg_read32(&reg_rx_stats->etherStatsPkts256to511Octets);
-		stats->etherStatsPkts512to1023Octets = _40g_mac_reg_read32(&reg_rx_stats->etherStatsPkts512to1023Octets);
-		stats->etherStatsPkts1024to1518Octets = _40g_mac_reg_read32(&reg_rx_stats->etherStatsPkts1024to1518Octets);
-		stats->etherStatsPkts1519toX = _40g_mac_reg_read32(&reg_rx_stats->etherStatsPkts1519toMax);
-	}
-
-	stats->eee_in = al_reg_read32(&adapter->mac_regs_base->stat.eee_in);
-	stats->eee_out = al_reg_read32(&adapter->mac_regs_base->stat.eee_out);
-
-/*	stats->etherStatsPkts = 1; */
-	return 0;
-}
-
-/**
-* read ec_stat_counters
-*/
-int al_eth_ec_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_ec_stats *stats)
-{
-	al_assert(stats);
-	stats->faf_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.faf_in_rx_pkt);
-	stats->faf_in_rx_short = al_reg_read32(&adapter->ec_regs_base->stat.faf_in_rx_short);
-	stats->faf_in_rx_long = al_reg_read32(&adapter->ec_regs_base->stat.faf_in_rx_long);
-	stats->faf_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_rx_pkt);
-	stats->faf_out_rx_short = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_rx_short);
-	stats->faf_out_rx_long = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_rx_long);
-	stats->faf_out_drop = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_drop);
-	stats->rxf_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_in_rx_pkt);
-	stats->rxf_in_fifo_err = al_reg_read32(&adapter->ec_regs_base->stat.rxf_in_fifo_err);
-	stats->lbf_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.lbf_in_rx_pkt);
-	stats->lbf_in_fifo_err = al_reg_read32(&adapter->ec_regs_base->stat.lbf_in_fifo_err);
-	stats->rxf_out_rx_1_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_rx_1_pkt);
-	stats->rxf_out_rx_2_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_rx_2_pkt);
-	stats->rxf_out_drop_1_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_drop_1_pkt);
-	stats->rxf_out_drop_2_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_drop_2_pkt);
-	stats->rpe_1_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_1_in_rx_pkt);
-	stats->rpe_1_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_1_out_rx_pkt);
-	stats->rpe_2_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_2_in_rx_pkt);
-	stats->rpe_2_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_2_out_rx_pkt);
-	stats->rpe_3_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_3_in_rx_pkt);
-	stats->rpe_3_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_3_out_rx_pkt);
-	stats->tpe_in_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tpe_in_tx_pkt);
-	stats->tpe_out_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tpe_out_tx_pkt);
-	stats->tpm_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tpm_tx_pkt);
-	stats->tfw_in_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tfw_in_tx_pkt);
-	stats->tfw_out_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tfw_out_tx_pkt);
-	stats->rfw_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_rx_pkt);
-	stats->rfw_in_vlan_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_vlan_drop);
-	stats->rfw_in_parse_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_parse_drop);
-	stats->rfw_in_mc = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_mc);
-	stats->rfw_in_bc = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_bc);
-	stats->rfw_in_vlan_exist = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_vlan_exist);
-	stats->rfw_in_vlan_nexist = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_vlan_nexist);
-	stats->rfw_in_mac_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_mac_drop);
-	stats->rfw_in_mac_ndet_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_mac_ndet_drop);
-	stats->rfw_in_ctrl_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_ctrl_drop);
-	stats->rfw_in_prot_i_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_prot_i_drop);
-	stats->eee_in = al_reg_read32(&adapter->ec_regs_base->stat.eee_in);
-	return 0;
-}
-
-/**
- * read per_udma_counters
- */
-int al_eth_ec_stat_udma_get(struct al_hal_eth_adapter *adapter, uint8_t idx, struct al_eth_ec_stat_udma *stats)
-{
-
-	al_assert(idx <= 3); /*valid udma_id*/
-	al_assert(stats);
-	stats->rfw_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].rfw_out_rx_pkt);
-	stats->rfw_out_drop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].rfw_out_drop);
-	stats->msw_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_in_rx_pkt);
-	stats->msw_drop_q_full = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_drop_q_full);
-	stats->msw_drop_sop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_drop_sop);
-	stats->msw_drop_eop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_drop_eop);
-	stats->msw_wr_eop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_wr_eop);
-	stats->msw_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_out_rx_pkt);
-	stats->tso_no_tso_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_no_tso_pkt);
-	stats->tso_tso_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_tso_pkt);
-	stats->tso_seg_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_seg_pkt);
-	stats->tso_pad_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_pad_pkt);
-	stats->tpm_tx_spoof = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tpm_tx_spoof);
-	stats->tmi_in_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tmi_in_tx_pkt);
-	stats->tmi_out_to_mac = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tmi_out_to_mac);
-	stats->tmi_out_to_rx = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tmi_out_to_rx);
-	stats->tx_q0_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q0_bytes);
-	stats->tx_q1_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q1_bytes);
-	stats->tx_q2_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q2_bytes);
-	stats->tx_q3_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q3_bytes);
-	stats->tx_q0_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q0_pkts);
-	stats->tx_q1_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q1_pkts);
-	stats->tx_q2_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q2_pkts);
-	stats->tx_q3_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q3_pkts);
-	return 0;
-}
-
-/* Traffic control */
-
-
-int al_eth_flr_rmn(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val),
-		   int (* pci_write_config_u32)(void *handle, int where, uint32_t val),
-		   void *handle,
-		   void __iomem	*mac_base)
-{
-	struct al_eth_mac_regs __iomem *mac_regs_base =
-		(struct	al_eth_mac_regs __iomem *)mac_base;
-	uint32_t cfg_reg_store[6];
-	uint32_t reg;
-	uint32_t mux_sel;
-	int i = 0;
-
-	(*pci_read_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, &reg);
-
-	/* reset 1G mac */
-	AL_REG_MASK_SET(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC);
-	(*pci_write_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, reg);
-	al_udelay(1000);
-	/* don't reset 1G mac */
-	AL_REG_MASK_CLEAR(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC);
-	/* prevent 1G mac reset on FLR */
-	AL_REG_MASK_CLEAR(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC_ON_FLR);
-	/* prevent adapter reset */
-	(*pci_write_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, reg);
-
-	mux_sel = al_reg_read32(&mac_regs_base->gen.mux_sel);
-
-	/* save pci register that get reset due to flr*/
-	(*pci_read_config_u32)(handle, AL_PCI_COMMAND, &cfg_reg_store[i++]);
-	(*pci_read_config_u32)(handle, 0xC, &cfg_reg_store[i++]);
-	(*pci_read_config_u32)(handle, 0x10, &cfg_reg_store[i++]);
-	(*pci_read_config_u32)(handle, 0x18, &cfg_reg_store[i++]);
-	(*pci_read_config_u32)(handle, 0x20, &cfg_reg_store[i++]);
-	(*pci_read_config_u32)(handle, 0x110, &cfg_reg_store[i++]);
-
-	/* do flr */
-	(*pci_write_config_u32)(handle, AL_PCI_EXP_CAP_BASE + AL_PCI_EXP_DEVCTL, AL_PCI_EXP_DEVCTL_BCR_FLR);
-	al_udelay(1000);
-	/* restore command */
-	i = 0;
-	(*pci_write_config_u32)(handle, AL_PCI_COMMAND, cfg_reg_store[i++]);
-	(*pci_write_config_u32)(handle, 0xC, cfg_reg_store[i++]);
-	(*pci_write_config_u32)(handle, 0x10, cfg_reg_store[i++]);
-	(*pci_write_config_u32)(handle, 0x18, cfg_reg_store[i++]);
-	(*pci_write_config_u32)(handle, 0x20, cfg_reg_store[i++]);
-	(*pci_write_config_u32)(handle, 0x110, cfg_reg_store[i++]);
-
-	al_reg_write32_masked(&mac_regs_base->gen.mux_sel, ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, mux_sel);
-
-	/* set SGMII clock to 125MHz */
-	al_reg_write32(&mac_regs_base->sgmii.clk_div, 0x03320501);
-
-	/* reset 1G mac */
-	AL_REG_MASK_SET(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC);
-	(*pci_write_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, reg);
-
-	al_udelay(1000);
-
-	/* clear 1G mac reset */
-	AL_REG_MASK_CLEAR(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC);
-	(*pci_write_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, reg);
-
-	/* reset SGMII mac clock to default */
-	al_reg_write32(&mac_regs_base->sgmii.clk_div, 0x00320501);
-	al_udelay(1000);
-	/* reset async fifo */
-	reg = al_reg_read32(&mac_regs_base->gen.sd_fifo_ctrl);
-	AL_REG_MASK_SET(reg, 0xF0);
-	al_reg_write32(&mac_regs_base->gen.sd_fifo_ctrl, reg);
-	reg = al_reg_read32(&mac_regs_base->gen.sd_fifo_ctrl);
-	AL_REG_MASK_CLEAR(reg, 0xF0);
-	al_reg_write32(&mac_regs_base->gen.sd_fifo_ctrl, reg);
-
-	return 0;
-}
-
-int al_eth_flr_rmn_restore_params(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val),
-		int (* pci_write_config_u32)(void *handle, int where, uint32_t val),
-		void *handle,
-		void __iomem    *mac_base,
-		void __iomem    *ec_base,
-		int     mac_addresses_num
-		)
-{
-	struct al_eth_board_params params = { .media_type = 0 };
-	uint8_t mac_addr[6];
-	int rc;
-
-	/* not implemented yet */
-	if (mac_addresses_num > 1)
-		return -EPERM;
-
-	/* save board params so we restore it after reset */
-	al_eth_board_params_get(mac_base, &params);
-	al_eth_mac_addr_read(ec_base, 0, mac_addr);
-
-	rc = al_eth_flr_rmn(pci_read_config_u32, pci_write_config_u32, handle, mac_base);
-	al_eth_board_params_set(mac_base, &params);
-	al_eth_mac_addr_store(ec_base, 0, mac_addr);
-
-	return rc;
-}
-
-/* board params register 1 */
-#define AL_HAL_ETH_MEDIA_TYPE_MASK	(AL_FIELD_MASK(3, 0))
-#define AL_HAL_ETH_MEDIA_TYPE_SHIFT	0
-#define AL_HAL_ETH_EXT_PHY_SHIFT	4
-#define AL_HAL_ETH_PHY_ADDR_MASK	(AL_FIELD_MASK(9, 5))
-#define AL_HAL_ETH_PHY_ADDR_SHIFT	5
-#define AL_HAL_ETH_SFP_EXIST_SHIFT	10
-#define AL_HAL_ETH_AN_ENABLE_SHIFT	11
-#define AL_HAL_ETH_KR_LT_ENABLE_SHIFT	12
-#define AL_HAL_ETH_KR_FEC_ENABLE_SHIFT	13
-#define AL_HAL_ETH_MDIO_FREQ_MASK	(AL_FIELD_MASK(15, 14))
-#define AL_HAL_ETH_MDIO_FREQ_SHIFT	14
-#define AL_HAL_ETH_I2C_ADAPTER_ID_MASK	(AL_FIELD_MASK(19, 16))
-#define AL_HAL_ETH_I2C_ADAPTER_ID_SHIFT	16
-#define AL_HAL_ETH_EXT_PHY_IF_MASK	(AL_FIELD_MASK(21, 20))
-#define AL_HAL_ETH_EXT_PHY_IF_SHIFT	20
-#define AL_HAL_ETH_AUTO_NEG_MODE_SHIFT	22
-#define AL_HAL_ETH_SERDES_GRP_2_SHIFT	23
-#define AL_HAL_ETH_SERDES_GRP_MASK	(AL_FIELD_MASK(26, 25))
-#define AL_HAL_ETH_SERDES_GRP_SHIFT	25
-#define AL_HAL_ETH_SERDES_LANE_MASK	(AL_FIELD_MASK(28, 27))
-#define AL_HAL_ETH_SERDES_LANE_SHIFT	27
-#define AL_HAL_ETH_REF_CLK_FREQ_MASK	(AL_FIELD_MASK(31, 29))
-#define AL_HAL_ETH_REF_CLK_FREQ_SHIFT	29
-
-/* board params register 2 */
-#define AL_HAL_ETH_DONT_OVERRIDE_SERDES_SHIFT	0
-#define AL_HAL_ETH_1000_BASE_X_SHIFT		1
-#define AL_HAL_ETH_1G_AN_DISABLE_SHIFT		2
-#define AL_HAL_ETH_1G_SPEED_MASK		(AL_FIELD_MASK(4, 3))
-#define AL_HAL_ETH_1G_SPEED_SHIFT		3
-#define AL_HAL_ETH_1G_HALF_DUPLEX_SHIFT		5
-#define AL_HAL_ETH_1G_FC_DISABLE_SHIFT		6
-#define AL_HAL_ETH_RETIMER_EXIST_SHIFT		7
-#define AL_HAL_ETH_RETIMER_BUS_ID_MASK		(AL_FIELD_MASK(11, 8))
-#define AL_HAL_ETH_RETIMER_BUS_ID_SHIFT		8
-#define AL_HAL_ETH_RETIMER_I2C_ADDR_MASK	(AL_FIELD_MASK(18, 12))
-#define AL_HAL_ETH_RETIMER_I2C_ADDR_SHIFT	12
-#define AL_HAL_ETH_RETIMER_CHANNEL_SHIFT	19
-#define AL_HAL_ETH_DAC_LENGTH_MASK		(AL_FIELD_MASK(23, 20))
-#define AL_HAL_ETH_DAC_LENGTH_SHIFT		20
-#define AL_HAL_ETH_DAC_SHIFT			24
-#define AL_HAL_ETH_RETIMER_TYPE_MASK		(AL_FIELD_MASK(26, 25))
-#define AL_HAL_ETH_RETIMER_TYPE_SHIFT		25
-#define AL_HAL_ETH_RETIMER_CHANNEL_2_MASK	(AL_FIELD_MASK(28, 27))
-#define AL_HAL_ETH_RETIMER_CHANNEL_2_SHIFT	27
-#define AL_HAL_ETH_RETIMER_TX_CHANNEL_MASK	(AL_FIELD_MASK(31, 29))
-#define AL_HAL_ETH_RETIMER_TX_CHANNEL_SHIFT	29
-
-/* board params register 3 */
-#define AL_HAL_ETH_GPIO_SFP_PRESENT_MASK	(AL_FIELD_MASK(5, 0))
-#define AL_HAL_ETH_GPIO_SFP_PRESENT_SHIFT	0
-
-int al_eth_board_params_set(void * __iomem mac_base, struct al_eth_board_params *params)
-{
-	struct al_eth_mac_regs __iomem *mac_regs_base =
-		(struct	al_eth_mac_regs __iomem *)mac_base;
-	uint32_t	reg = 0;
-
-	/* ************* Setting Board params register 1 **************** */
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_MEDIA_TYPE_MASK,
-			 AL_HAL_ETH_MEDIA_TYPE_SHIFT, params->media_type);
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_EXT_PHY_SHIFT, params->phy_exist == AL_TRUE);
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_PHY_ADDR_MASK,
-			 AL_HAL_ETH_PHY_ADDR_SHIFT, params->phy_mdio_addr);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_SFP_EXIST_SHIFT, params->sfp_plus_module_exist == AL_TRUE);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_AN_ENABLE_SHIFT, params->autoneg_enable == AL_TRUE);
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_KR_LT_ENABLE_SHIFT, params->kr_lt_enable == AL_TRUE);
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_KR_FEC_ENABLE_SHIFT, params->kr_fec_enable == AL_TRUE);
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_MDIO_FREQ_MASK,
-			 AL_HAL_ETH_MDIO_FREQ_SHIFT, params->mdio_freq);
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_I2C_ADAPTER_ID_MASK,
-			 AL_HAL_ETH_I2C_ADAPTER_ID_SHIFT, params->i2c_adapter_id);
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_EXT_PHY_IF_MASK,
-			 AL_HAL_ETH_EXT_PHY_IF_SHIFT, params->phy_if);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_AUTO_NEG_MODE_SHIFT,
-			   params->an_mode == AL_ETH_BOARD_AUTONEG_IN_BAND);
-
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_SERDES_GRP_MASK,
-			 AL_HAL_ETH_SERDES_GRP_SHIFT, params->serdes_grp);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_SERDES_GRP_2_SHIFT,
-			(params->serdes_grp & AL_BIT(2)) ? 1 : 0);
-
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_SERDES_LANE_MASK,
-			 AL_HAL_ETH_SERDES_LANE_SHIFT, params->serdes_lane);
-
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_REF_CLK_FREQ_MASK,
-			 AL_HAL_ETH_REF_CLK_FREQ_SHIFT, params->ref_clk_freq);
-
-	al_assert(reg != 0);
-
-	al_reg_write32(&mac_regs_base->mac_1g.scratch, reg);
-
-	/* ************* Setting Board params register 2 **************** */
-	reg = 0;
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_DONT_OVERRIDE_SERDES_SHIFT,
-			   params->dont_override_serdes == AL_TRUE);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_1000_BASE_X_SHIFT,
-			   params->force_1000_base_x == AL_TRUE);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_1G_AN_DISABLE_SHIFT,
-			   params->an_disable == AL_TRUE);
-
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_1G_SPEED_MASK,
-			 AL_HAL_ETH_1G_SPEED_SHIFT, params->speed);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_1G_HALF_DUPLEX_SHIFT,
-			   params->half_duplex == AL_TRUE);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_1G_FC_DISABLE_SHIFT,
-			   params->fc_disable == AL_TRUE);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_RETIMER_EXIST_SHIFT, params->retimer_exist == AL_TRUE);
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_BUS_ID_MASK,
-			 AL_HAL_ETH_RETIMER_BUS_ID_SHIFT, params->retimer_bus_id);
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_I2C_ADDR_MASK,
-			 AL_HAL_ETH_RETIMER_I2C_ADDR_SHIFT, params->retimer_i2c_addr);
-
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_RETIMER_CHANNEL_SHIFT,
-				(params->retimer_channel & AL_BIT(0)));
-
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_CHANNEL_2_MASK,
-			 AL_HAL_ETH_RETIMER_CHANNEL_2_SHIFT,
-			 (AL_REG_FIELD_GET(params->retimer_channel, 0x6, 1)));
-
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_DAC_LENGTH_MASK,
-			 AL_HAL_ETH_DAC_LENGTH_SHIFT, params->dac_len);
-	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_DAC_SHIFT, params->dac);
-
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_TYPE_MASK,
-			 AL_HAL_ETH_RETIMER_TYPE_SHIFT, params->retimer_type);
-
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_TX_CHANNEL_MASK,
-			 AL_HAL_ETH_RETIMER_TX_CHANNEL_SHIFT,
-			 params->retimer_tx_channel);
-
-	al_reg_write32(&mac_regs_base->mac_10g.scratch, reg);
-
-	/* ************* Setting Board params register 3 **************** */
-	reg = 0;
-
-	AL_REG_FIELD_SET(reg, AL_HAL_ETH_GPIO_SFP_PRESENT_MASK,
-			 AL_HAL_ETH_GPIO_SFP_PRESENT_SHIFT,
-			 params->gpio_sfp_present);
-
-	al_reg_write32(&mac_regs_base->mac_1g.mac_0, reg);
-
-	return 0;
-}
-
-int al_eth_board_params_get(void * __iomem mac_base, struct al_eth_board_params *params)
-{
-	struct al_eth_mac_regs __iomem *mac_regs_base =
-		(struct	al_eth_mac_regs __iomem *)mac_base;
-	uint32_t	reg = al_reg_read32(&mac_regs_base->mac_1g.scratch);
-
-	/* check if the register was initialized, 0 is not a valid value */
-	if (reg == 0)
-		return -ENOENT;
-
-	/* ************* Getting Board params register 1 **************** */
-	params->media_type = AL_REG_FIELD_GET(reg, AL_HAL_ETH_MEDIA_TYPE_MASK,
-					      AL_HAL_ETH_MEDIA_TYPE_SHIFT);
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_EXT_PHY_SHIFT))
-		params->phy_exist = AL_TRUE;
-	else
-		params->phy_exist = AL_FALSE;
-
-	params->phy_mdio_addr = AL_REG_FIELD_GET(reg, AL_HAL_ETH_PHY_ADDR_MASK,
-						 AL_HAL_ETH_PHY_ADDR_SHIFT);
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_SFP_EXIST_SHIFT))
-		params->sfp_plus_module_exist = AL_TRUE;
-	else
-		params->sfp_plus_module_exist = AL_FALSE;
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_AN_ENABLE_SHIFT))
-		params->autoneg_enable = AL_TRUE;
-	else
-		params->autoneg_enable = AL_FALSE;
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_KR_LT_ENABLE_SHIFT))
-		params->kr_lt_enable = AL_TRUE;
-	else
-		params->kr_lt_enable = AL_FALSE;
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_KR_FEC_ENABLE_SHIFT))
-		params->kr_fec_enable = AL_TRUE;
-	else
-		params->kr_fec_enable = AL_FALSE;
-
-	params->mdio_freq = AL_REG_FIELD_GET(reg,
-					     AL_HAL_ETH_MDIO_FREQ_MASK,
-					     AL_HAL_ETH_MDIO_FREQ_SHIFT);
-
-	params->i2c_adapter_id = AL_REG_FIELD_GET(reg,
-						  AL_HAL_ETH_I2C_ADAPTER_ID_MASK,
-						  AL_HAL_ETH_I2C_ADAPTER_ID_SHIFT);
-
-	params->phy_if = AL_REG_FIELD_GET(reg,
-					  AL_HAL_ETH_EXT_PHY_IF_MASK,
-					  AL_HAL_ETH_EXT_PHY_IF_SHIFT);
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_AUTO_NEG_MODE_SHIFT))
-		params->an_mode = AL_TRUE;
-	else
-		params->an_mode = AL_FALSE;
-
-	params->serdes_grp = AL_REG_FIELD_GET(reg,
-					      AL_HAL_ETH_SERDES_GRP_MASK,
-					      AL_HAL_ETH_SERDES_GRP_SHIFT);
-
-	params->serdes_grp |= (AL_REG_BIT_GET(reg, AL_HAL_ETH_SERDES_GRP_2_SHIFT) ? AL_BIT(2) : 0);
-
-	params->serdes_lane = AL_REG_FIELD_GET(reg,
-					       AL_HAL_ETH_SERDES_LANE_MASK,
-					       AL_HAL_ETH_SERDES_LANE_SHIFT);
-
-	params->ref_clk_freq = AL_REG_FIELD_GET(reg,
-						AL_HAL_ETH_REF_CLK_FREQ_MASK,
-						AL_HAL_ETH_REF_CLK_FREQ_SHIFT);
-
-	/* ************* Getting Board params register 2 **************** */
-	reg = al_reg_read32(&mac_regs_base->mac_10g.scratch);
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_DONT_OVERRIDE_SERDES_SHIFT))
-		params->dont_override_serdes = AL_TRUE;
-	else
-		params->dont_override_serdes = AL_FALSE;
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_1000_BASE_X_SHIFT))
-		params->force_1000_base_x = AL_TRUE;
-	else
-		params->force_1000_base_x = AL_FALSE;
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_1G_AN_DISABLE_SHIFT))
-		params->an_disable = AL_TRUE;
-	else
-		params->an_disable = AL_FALSE;
-
-	params->speed = AL_REG_FIELD_GET(reg,
-					 AL_HAL_ETH_1G_SPEED_MASK,
-					 AL_HAL_ETH_1G_SPEED_SHIFT);
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_1G_HALF_DUPLEX_SHIFT))
-		params->half_duplex = AL_TRUE;
-	else
-		params->half_duplex = AL_FALSE;
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_1G_FC_DISABLE_SHIFT))
-		params->fc_disable = AL_TRUE;
-	else
-		params->fc_disable = AL_FALSE;
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_RETIMER_EXIST_SHIFT))
-		params->retimer_exist = AL_TRUE;
-	else
-		params->retimer_exist = AL_FALSE;
-
-	params->retimer_bus_id = AL_REG_FIELD_GET(reg,
-					       AL_HAL_ETH_RETIMER_BUS_ID_MASK,
-					       AL_HAL_ETH_RETIMER_BUS_ID_SHIFT);
-	params->retimer_i2c_addr = AL_REG_FIELD_GET(reg,
-					       AL_HAL_ETH_RETIMER_I2C_ADDR_MASK,
-					       AL_HAL_ETH_RETIMER_I2C_ADDR_SHIFT);
-
-	params->retimer_channel =
-		((AL_REG_BIT_GET(reg, AL_HAL_ETH_RETIMER_CHANNEL_SHIFT)) |
-		 (AL_REG_FIELD_GET(reg, AL_HAL_ETH_RETIMER_CHANNEL_2_MASK,
-				   AL_HAL_ETH_RETIMER_CHANNEL_2_SHIFT) << 1));
-
-	params->dac_len = AL_REG_FIELD_GET(reg,
-					   AL_HAL_ETH_DAC_LENGTH_MASK,
-					   AL_HAL_ETH_DAC_LENGTH_SHIFT);
-
-	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_DAC_SHIFT))
-		params->dac = AL_TRUE;
-	else
-		params->dac = AL_FALSE;
-
-	params->retimer_type = AL_REG_FIELD_GET(reg,
-					   AL_HAL_ETH_RETIMER_TYPE_MASK,
-					   AL_HAL_ETH_RETIMER_TYPE_SHIFT);
-
-	params->retimer_tx_channel = AL_REG_FIELD_GET(reg,
-					   AL_HAL_ETH_RETIMER_TX_CHANNEL_MASK,
-					   AL_HAL_ETH_RETIMER_TX_CHANNEL_SHIFT);
-
-	/* ************* Getting Board params register 3 **************** */
-	reg = al_reg_read32(&mac_regs_base->mac_1g.mac_0);
-
-	params->gpio_sfp_present = AL_REG_FIELD_GET(reg,
-					AL_HAL_ETH_GPIO_SFP_PRESENT_MASK,
-					AL_HAL_ETH_GPIO_SFP_PRESENT_SHIFT);
-
-	return 0;
-}
-
-/* Wake-On-Lan (WoL) */
-static inline void al_eth_byte_arr_to_reg(
-		uint32_t *reg, uint8_t *arr, unsigned int num_bytes)
-{
-	uint32_t mask = 0xff;
-	unsigned int i;
-
-	al_assert(num_bytes <= 4);
-
-	*reg = 0;
-
-	for (i = 0 ; i < num_bytes ; i++) {
-		AL_REG_FIELD_SET(*reg, mask, (sizeof(uint8_t) * i), arr[i]);
-		mask = mask << sizeof(uint8_t);
-	}
-}
-
-int al_eth_wol_enable(
-		struct al_hal_eth_adapter *adapter,
-		struct al_eth_wol_params *wol)
-{
-	uint32_t reg = 0;
-
-	if (wol->int_mask & AL_ETH_WOL_INT_MAGIC_PSWD) {
-		al_assert(wol->pswd != NULL);
-
-		al_eth_byte_arr_to_reg(&reg, &wol->pswd[0], 4);
-		al_reg_write32(&adapter->ec_regs_base->wol.magic_pswd_l, reg);
-
-		al_eth_byte_arr_to_reg(&reg, &wol->pswd[4], 2);
-		al_reg_write32(&adapter->ec_regs_base->wol.magic_pswd_h, reg);
-	}
-
-	if (wol->int_mask & AL_ETH_WOL_INT_IPV4) {
-		al_assert(wol->ipv4 != NULL);
-
-		al_eth_byte_arr_to_reg(&reg, &wol->ipv4[0], 4);
-		al_reg_write32(&adapter->ec_regs_base->wol.ipv4_dip, reg);
-	}
-
-	if (wol->int_mask & AL_ETH_WOL_INT_IPV6) {
-		al_assert(wol->ipv6 != NULL);
-
-		al_eth_byte_arr_to_reg(&reg, &wol->ipv6[0], 4);
-		al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word0, reg);
-
-		al_eth_byte_arr_to_reg(&reg, &wol->ipv6[4], 4);
-		al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word1, reg);
-
-		al_eth_byte_arr_to_reg(&reg, &wol->ipv6[8], 4);
-		al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word2, reg);
-
-		al_eth_byte_arr_to_reg(&reg, &wol->ipv6[12], 4);
-		al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word3, reg);
-	}
-
-	if (wol->int_mask &
-		(AL_ETH_WOL_INT_ETHERTYPE_BC | AL_ETH_WOL_INT_ETHERTYPE_DA)) {
-
-		reg = ((uint32_t)wol->ethr_type2 << 16);
-		reg |= wol->ethr_type1;
-
-		al_reg_write32(&adapter->ec_regs_base->wol.ethertype, reg);
-	}
-
-	/* make sure we dont forwarding packets without interrupt */
-	al_assert((wol->forward_mask | wol->int_mask) == wol->int_mask);
-
-	reg = ((uint32_t)wol->forward_mask << 16);
-	reg |= wol->int_mask;
-	al_reg_write32(&adapter->ec_regs_base->wol.wol_en, reg);
-
-	return 0;
-}
-
-int al_eth_wol_disable(
-		struct al_hal_eth_adapter *adapter)
-{
-	al_reg_write32(&adapter->ec_regs_base->wol.wol_en, 0);
-
-	return 0;
-}
-
-int al_eth_tx_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-				uint8_t udma_mask, al_bool fwd_to_mac)
-{
-	uint32_t	val = 0;
-	al_assert(idx < AL_ETH_FWD_VID_TABLE_NUM); /* valid VID index */
-	AL_REG_FIELD_SET(val,  AL_ETH_TX_VLAN_TABLE_UDMA_MASK, 0, udma_mask);
-	AL_REG_FIELD_SET(val,  AL_ETH_TX_VLAN_TABLE_FWD_TO_MAC, 4, fwd_to_mac);
-
-	al_reg_write32(&adapter->ec_regs_base->tfw.tx_vid_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->tfw.tx_vid_table_data, val);
-	return 0;
-}
-
-int al_eth_tx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_tx_gpd_cam_entry *tx_gpd_entry)
-{
-	uint64_t gpd_data;
-	uint64_t gpd_mask;
-
-	gpd_data = ((uint64_t)tx_gpd_entry->l3_proto_idx & AL_ETH_TX_GPD_L3_PROTO_MASK) <<
-		AL_ETH_TX_GPD_L3_PROTO_SHIFT;
-	gpd_data |= ((uint64_t)tx_gpd_entry->l4_proto_idx & AL_ETH_TX_GPD_L4_PROTO_MASK) <<
-		AL_ETH_TX_GPD_L4_PROTO_SHIFT;
-	gpd_data |= ((uint64_t)tx_gpd_entry->tunnel_control & AL_ETH_TX_GPD_TUNNEL_CTRL_MASK) <<
-		AL_ETH_TX_GPD_TUNNEL_CTRL_SHIFT;
-	gpd_data |= ((uint64_t)tx_gpd_entry->source_vlan_count & AL_ETH_TX_GPD_SRC_VLAN_CNT_MASK) <<
-		AL_ETH_TX_GPD_SRC_VLAN_CNT_SHIFT;
-	gpd_mask  = ((uint64_t)tx_gpd_entry->l3_proto_idx_mask & AL_ETH_TX_GPD_L3_PROTO_MASK) <<
-		AL_ETH_TX_GPD_L3_PROTO_SHIFT;
-	gpd_mask |= ((uint64_t)tx_gpd_entry->l4_proto_idx_mask & AL_ETH_TX_GPD_L4_PROTO_MASK) <<
-		AL_ETH_TX_GPD_L4_PROTO_SHIFT;
-	gpd_mask |= ((uint64_t)tx_gpd_entry->tunnel_control_mask & AL_ETH_TX_GPD_TUNNEL_CTRL_MASK) <<
-		AL_ETH_TX_GPD_TUNNEL_CTRL_SHIFT;
-	gpd_mask |= ((uint64_t)tx_gpd_entry->source_vlan_count_mask & AL_ETH_TX_GPD_SRC_VLAN_CNT_MASK) <<
-		AL_ETH_TX_GPD_SRC_VLAN_CNT_SHIFT;
-
-	/* Tx Generic protocol detect Cam compare table */
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_ctrl,
-			(uint32_t)((tx_gpd_entry->tx_gpd_cam_ctrl) << AL_ETH_TX_GPD_CAM_CTRL_VALID_SHIFT));
-	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_ctrl: %#x", idx, tx_gpd_entry->tx_gpd_cam_ctrl);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_mask_2,
-			(uint32_t)(gpd_mask >> AL_ETH_TX_GPD_CAM_MASK_2_SHIFT));
-	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_mask_2: %#x", idx, (uint32_t)(gpd_mask >> AL_ETH_TX_GPD_CAM_MASK_2_SHIFT));
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_mask_1,
-			(uint32_t)(gpd_mask));
-	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_mask_1: %#x", idx, (uint32_t)(gpd_mask));
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_data_2,
-			(uint32_t)(gpd_data >> AL_ETH_TX_GPD_CAM_DATA_2_SHIFT));
-	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_data_2: %#x", idx, (uint32_t)(gpd_data >> AL_ETH_TX_GPD_CAM_DATA_2_SHIFT));
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_data_1,
-			(uint32_t)(gpd_data));
-	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_data_1: %#x", idx, (uint32_t)(gpd_data));
-	return 0;
-}
-
-int al_eth_tx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_tx_gcp_table_entry *tx_gcp_entry)
-{
-	uint32_t gcp_table_gen;
-	uint32_t tx_alu_opcode;
-	uint32_t tx_alu_opsel;
-
-	gcp_table_gen  = (tx_gcp_entry->poly_sel & AL_ETH_TX_GCP_POLY_SEL_MASK) <<
-		AL_ETH_TX_GCP_POLY_SEL_SHIFT;
-	gcp_table_gen |= (tx_gcp_entry->crc32_bit_comp & AL_ETH_TX_GCP_CRC32_BIT_COMP_MASK) <<
-		AL_ETH_TX_GCP_CRC32_BIT_COMP_SHIFT;
-	gcp_table_gen |= (tx_gcp_entry->crc32_bit_swap & AL_ETH_TX_GCP_CRC32_BIT_SWAP_MASK) <<
-		AL_ETH_TX_GCP_CRC32_BIT_SWAP_SHIFT;
-	gcp_table_gen |= (tx_gcp_entry->crc32_byte_swap & AL_ETH_TX_GCP_CRC32_BYTE_SWAP_MASK) <<
-		AL_ETH_TX_GCP_CRC32_BYTE_SWAP_SHIFT;
-	gcp_table_gen |= (tx_gcp_entry->data_bit_swap & AL_ETH_TX_GCP_DATA_BIT_SWAP_MASK) <<
-		AL_ETH_TX_GCP_DATA_BIT_SWAP_SHIFT;
-	gcp_table_gen |= (tx_gcp_entry->data_byte_swap & AL_ETH_TX_GCP_DATA_BYTE_SWAP_MASK) <<
-		AL_ETH_TX_GCP_DATA_BYTE_SWAP_SHIFT;
-	gcp_table_gen |= (tx_gcp_entry->trail_size & AL_ETH_TX_GCP_TRAIL_SIZE_MASK) <<
-		AL_ETH_TX_GCP_TRAIL_SIZE_SHIFT;
-	gcp_table_gen |= (tx_gcp_entry->head_size & AL_ETH_TX_GCP_HEAD_SIZE_MASK) <<
-		AL_ETH_TX_GCP_HEAD_SIZE_SHIFT;
-	gcp_table_gen |= (tx_gcp_entry->head_calc & AL_ETH_TX_GCP_HEAD_CALC_MASK) <<
-		AL_ETH_TX_GCP_HEAD_CALC_SHIFT;
-	gcp_table_gen |= (tx_gcp_entry->mask_polarity & AL_ETH_TX_GCP_MASK_POLARITY_MASK) <<
-		AL_ETH_TX_GCP_MASK_POLARITY_SHIFT;
-	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], gcp_table_gen: %#x", idx, gcp_table_gen);
-
-	tx_alu_opcode  = (tx_gcp_entry->tx_alu_opcode_1 & AL_ETH_TX_GCP_OPCODE_1_MASK) <<
-		AL_ETH_TX_GCP_OPCODE_1_SHIFT;
-	tx_alu_opcode |= (tx_gcp_entry->tx_alu_opcode_2 & AL_ETH_TX_GCP_OPCODE_2_MASK) <<
-		AL_ETH_TX_GCP_OPCODE_2_SHIFT;
-	tx_alu_opcode |= (tx_gcp_entry->tx_alu_opcode_3 & AL_ETH_TX_GCP_OPCODE_3_MASK) <<
-		AL_ETH_TX_GCP_OPCODE_3_SHIFT;
-	tx_alu_opsel  = (tx_gcp_entry->tx_alu_opsel_1 & AL_ETH_TX_GCP_OPSEL_1_MASK) <<
-		AL_ETH_TX_GCP_OPSEL_1_SHIFT;
-	tx_alu_opsel |= (tx_gcp_entry->tx_alu_opsel_2 & AL_ETH_TX_GCP_OPSEL_2_MASK) <<
-		AL_ETH_TX_GCP_OPSEL_2_SHIFT;
-	tx_alu_opsel |= (tx_gcp_entry->tx_alu_opsel_3 & AL_ETH_TX_GCP_OPSEL_3_MASK) <<
-		AL_ETH_TX_GCP_OPSEL_3_SHIFT;
-	tx_alu_opsel |= (tx_gcp_entry->tx_alu_opsel_4 & AL_ETH_TX_GCP_OPSEL_4_MASK) <<
-		AL_ETH_TX_GCP_OPSEL_4_SHIFT;
-
-	/*  Tx Generic crc prameters table general */
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_gen,
-			gcp_table_gen);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_1,
-			tx_gcp_entry->gcp_mask[0]);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_2,
-			tx_gcp_entry->gcp_mask[1]);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_3,
-			tx_gcp_entry->gcp_mask[2]);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_4,
-			tx_gcp_entry->gcp_mask[3]);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_5,
-			tx_gcp_entry->gcp_mask[4]);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_6,
-			tx_gcp_entry->gcp_mask[5]);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_crc_init,
-			tx_gcp_entry->crc_init);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_res,
-			tx_gcp_entry->gcp_table_res);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_alu_opcode,
-			tx_alu_opcode);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_alu_opsel,
-			tx_alu_opsel);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_alu_val,
-			tx_gcp_entry->alu_val);
-	return 0;
-}
-
-int al_eth_tx_crc_chksum_replace_cmd_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry *tx_replace_entry)
-{
-	uint32_t replace_table_address;
-	uint32_t tx_replace_cmd;
-
-	/*  Tx crc_chksum_replace_cmd */
-	replace_table_address = L4_CHECKSUM_DIS_AND_L3_CHECKSUM_DIS | idx;
-	tx_replace_cmd  = (uint32_t)(tx_replace_entry->l3_csum_en_00) << 0;
-	tx_replace_cmd |= (uint32_t)(tx_replace_entry->l4_csum_en_00) << 1;
-	tx_replace_cmd |= (uint32_t)(tx_replace_entry->crc_en_00)     << 2;
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table,
-			tx_replace_cmd);
-	replace_table_address = L4_CHECKSUM_DIS_AND_L3_CHECKSUM_EN | idx;
-	tx_replace_cmd  = (uint32_t)(tx_replace_entry->l3_csum_en_01) << 0;
-	tx_replace_cmd |= (uint32_t)(tx_replace_entry->l4_csum_en_01) << 1;
-	tx_replace_cmd |= (uint32_t)(tx_replace_entry->crc_en_01)     << 2;
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table,
-			tx_replace_cmd);
-	replace_table_address = L4_CHECKSUM_EN_AND_L3_CHECKSUM_DIS | idx;
-	tx_replace_cmd  = (uint32_t)(tx_replace_entry->l3_csum_en_10) << 0;
-	tx_replace_cmd |= (uint32_t)(tx_replace_entry->l4_csum_en_10) << 1;
-	tx_replace_cmd |= (uint32_t)(tx_replace_entry->crc_en_10)     << 2;
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table,
-			tx_replace_cmd);
-	replace_table_address = L4_CHECKSUM_EN_AND_L3_CHECKSUM_EN | idx;
-	tx_replace_cmd  = (uint32_t)(tx_replace_entry->l3_csum_en_11) << 0;
-	tx_replace_cmd |= (uint32_t)(tx_replace_entry->l4_csum_en_11) << 1;
-	tx_replace_cmd |= (uint32_t)(tx_replace_entry->crc_en_11)     << 2;
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table,
-			tx_replace_cmd);
-
-	return 0;
-}
-
-int al_eth_rx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_rx_gpd_cam_entry *rx_gpd_entry)
-{
-	uint64_t gpd_data;
-	uint64_t gpd_mask;
-
-	gpd_data  = ((uint64_t)rx_gpd_entry->outer_l3_proto_idx & AL_ETH_RX_GPD_OUTER_L3_PROTO_MASK) <<
-		AL_ETH_RX_GPD_OUTER_L3_PROTO_SHIFT;
-	gpd_data |= ((uint64_t)rx_gpd_entry->outer_l4_proto_idx & AL_ETH_RX_GPD_OUTER_L4_PROTO_MASK) <<
-		AL_ETH_RX_GPD_OUTER_L4_PROTO_SHIFT;
-	gpd_data |= ((uint64_t)rx_gpd_entry->inner_l3_proto_idx & AL_ETH_RX_GPD_INNER_L3_PROTO_MASK) <<
-		AL_ETH_RX_GPD_INNER_L3_PROTO_SHIFT;
-	gpd_data |= ((uint64_t)rx_gpd_entry->inner_l4_proto_idx & AL_ETH_RX_GPD_INNER_L4_PROTO_MASK) <<
-		AL_ETH_RX_GPD_INNER_L4_PROTO_SHIFT;
-	gpd_data |= ((uint64_t)rx_gpd_entry->parse_ctrl & AL_ETH_RX_GPD_OUTER_PARSE_CTRL_MASK) <<
-		AL_ETH_RX_GPD_OUTER_PARSE_CTRL_SHIFT;
-	gpd_data |= ((uint64_t)rx_gpd_entry->outer_l3_len & AL_ETH_RX_GPD_INNER_PARSE_CTRL_MASK) <<
-		AL_ETH_RX_GPD_INNER_PARSE_CTRL_SHIFT;
-	gpd_data |= ((uint64_t)rx_gpd_entry->l3_priority & AL_ETH_RX_GPD_L3_PRIORITY_MASK) <<
-		AL_ETH_RX_GPD_L3_PRIORITY_SHIFT;
-	gpd_data |= ((uint64_t)rx_gpd_entry->l4_dst_port_lsb & AL_ETH_RX_GPD_L4_DST_PORT_LSB_MASK) <<
-		AL_ETH_RX_GPD_L4_DST_PORT_LSB_SHIFT;
-
-	gpd_mask  = ((uint64_t)rx_gpd_entry->outer_l3_proto_idx_mask & AL_ETH_RX_GPD_OUTER_L3_PROTO_MASK) <<
-		AL_ETH_RX_GPD_OUTER_L3_PROTO_SHIFT;
-	gpd_mask |= ((uint64_t)rx_gpd_entry->outer_l4_proto_idx_mask & AL_ETH_RX_GPD_OUTER_L4_PROTO_MASK) <<
-		AL_ETH_RX_GPD_OUTER_L4_PROTO_SHIFT;
-	gpd_mask |= ((uint64_t)rx_gpd_entry->inner_l3_proto_idx_mask & AL_ETH_RX_GPD_INNER_L3_PROTO_MASK) <<
-		AL_ETH_RX_GPD_INNER_L3_PROTO_SHIFT;
-	gpd_mask |= ((uint64_t)rx_gpd_entry->inner_l4_proto_idx_mask & AL_ETH_RX_GPD_INNER_L4_PROTO_MASK) <<
-		AL_ETH_RX_GPD_INNER_L4_PROTO_SHIFT;
-	gpd_mask |= ((uint64_t)rx_gpd_entry->parse_ctrl_mask & AL_ETH_RX_GPD_OUTER_PARSE_CTRL_MASK) <<
-		AL_ETH_RX_GPD_OUTER_PARSE_CTRL_SHIFT;
-	gpd_mask |= ((uint64_t)rx_gpd_entry->outer_l3_len_mask & AL_ETH_RX_GPD_INNER_PARSE_CTRL_MASK) <<
-		AL_ETH_RX_GPD_INNER_PARSE_CTRL_SHIFT;
-	gpd_mask |= ((uint64_t)rx_gpd_entry->l3_priority_mask & AL_ETH_RX_GPD_L3_PRIORITY_MASK) <<
-		AL_ETH_RX_GPD_L3_PRIORITY_SHIFT;
-	gpd_mask |= ((uint64_t)rx_gpd_entry->l4_dst_port_lsb_mask & AL_ETH_RX_GPD_L4_DST_PORT_LSB_MASK) <<
-		AL_ETH_RX_GPD_L4_DST_PORT_LSB_SHIFT;
-
-	/* Rx Generic protocol detect Cam compare table */
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_ctrl,
-			(uint32_t)((rx_gpd_entry->rx_gpd_cam_ctrl) << AL_ETH_RX_GPD_CAM_CTRL_VALID_SHIFT));
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_mask_2,
-			(uint32_t)(gpd_mask >> AL_ETH_RX_GPD_CAM_MASK_2_SHIFT));
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_mask_1,
-			(uint32_t)(gpd_mask));
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_data_2,
-			(uint32_t)(gpd_data >> AL_ETH_RX_GPD_CAM_DATA_2_SHIFT));
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_data_1,
-			(uint32_t)(gpd_data));
-	return 0;
-}
-
-int al_eth_rx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
-		struct al_eth_rx_gcp_table_entry *rx_gcp_entry)
-{
-	uint32_t gcp_table_gen;
-	uint32_t rx_alu_opcode;
-	uint32_t rx_alu_opsel;
-
-	gcp_table_gen  = (rx_gcp_entry->poly_sel & AL_ETH_RX_GCP_POLY_SEL_MASK) <<
-		AL_ETH_RX_GCP_POLY_SEL_SHIFT;
-	gcp_table_gen |= (rx_gcp_entry->crc32_bit_comp & AL_ETH_RX_GCP_CRC32_BIT_COMP_MASK) <<
-		AL_ETH_RX_GCP_CRC32_BIT_COMP_SHIFT;
-	gcp_table_gen |= (rx_gcp_entry->crc32_bit_swap & AL_ETH_RX_GCP_CRC32_BIT_SWAP_MASK) <<
-		AL_ETH_RX_GCP_CRC32_BIT_SWAP_SHIFT;
-	gcp_table_gen |= (rx_gcp_entry->crc32_byte_swap & AL_ETH_RX_GCP_CRC32_BYTE_SWAP_MASK) <<
-		AL_ETH_RX_GCP_CRC32_BYTE_SWAP_SHIFT;
-	gcp_table_gen |= (rx_gcp_entry->data_bit_swap & AL_ETH_RX_GCP_DATA_BIT_SWAP_MASK) <<
-		AL_ETH_RX_GCP_DATA_BIT_SWAP_SHIFT;
-	gcp_table_gen |= (rx_gcp_entry->data_byte_swap & AL_ETH_RX_GCP_DATA_BYTE_SWAP_MASK) <<
-		AL_ETH_RX_GCP_DATA_BYTE_SWAP_SHIFT;
-	gcp_table_gen |= (rx_gcp_entry->trail_size & AL_ETH_RX_GCP_TRAIL_SIZE_MASK) <<
-		AL_ETH_RX_GCP_TRAIL_SIZE_SHIFT;
-	gcp_table_gen |= (rx_gcp_entry->head_size & AL_ETH_RX_GCP_HEAD_SIZE_MASK) <<
-		AL_ETH_RX_GCP_HEAD_SIZE_SHIFT;
-	gcp_table_gen |= (rx_gcp_entry->head_calc & AL_ETH_RX_GCP_HEAD_CALC_MASK) <<
-		AL_ETH_RX_GCP_HEAD_CALC_SHIFT;
-	gcp_table_gen |= (rx_gcp_entry->mask_polarity & AL_ETH_RX_GCP_MASK_POLARITY_MASK) <<
-		AL_ETH_RX_GCP_MASK_POLARITY_SHIFT;
-
-	rx_alu_opcode  = (rx_gcp_entry->rx_alu_opcode_1 & AL_ETH_RX_GCP_OPCODE_1_MASK) <<
-		AL_ETH_RX_GCP_OPCODE_1_SHIFT;
-	rx_alu_opcode |= (rx_gcp_entry->rx_alu_opcode_2 & AL_ETH_RX_GCP_OPCODE_2_MASK) <<
-		AL_ETH_RX_GCP_OPCODE_2_SHIFT;
-	rx_alu_opcode |= (rx_gcp_entry->rx_alu_opcode_3 & AL_ETH_RX_GCP_OPCODE_3_MASK) <<
-		AL_ETH_RX_GCP_OPCODE_3_SHIFT;
-	rx_alu_opsel  = (rx_gcp_entry->rx_alu_opsel_1 & AL_ETH_RX_GCP_OPSEL_1_MASK) <<
-		AL_ETH_RX_GCP_OPSEL_1_SHIFT;
-	rx_alu_opsel |= (rx_gcp_entry->rx_alu_opsel_2 & AL_ETH_RX_GCP_OPSEL_2_MASK) <<
-		AL_ETH_RX_GCP_OPSEL_2_SHIFT;
-	rx_alu_opsel |= (rx_gcp_entry->rx_alu_opsel_3 & AL_ETH_RX_GCP_OPSEL_3_MASK) <<
-		AL_ETH_RX_GCP_OPSEL_3_SHIFT;
-	rx_alu_opsel |= (rx_gcp_entry->rx_alu_opsel_4 & AL_ETH_RX_GCP_OPSEL_4_MASK) <<
-		AL_ETH_RX_GCP_OPSEL_4_SHIFT;
-
-	/*  Rx Generic crc prameters table general */
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_addr, idx);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_gen,
-			gcp_table_gen);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_1,
-			rx_gcp_entry->gcp_mask[0]);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_2,
-			rx_gcp_entry->gcp_mask[1]);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_3,
-			rx_gcp_entry->gcp_mask[2]);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_4,
-			rx_gcp_entry->gcp_mask[3]);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_5,
-			rx_gcp_entry->gcp_mask[4]);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_6,
-			rx_gcp_entry->gcp_mask[5]);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_crc_init,
-			rx_gcp_entry->crc_init);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_res,
-			rx_gcp_entry->gcp_table_res);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_alu_opcode,
-			rx_alu_opcode);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_alu_opsel,
-			rx_alu_opsel);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_alu_val,
-			rx_gcp_entry->alu_val);
-	return 0;
-}
-
-
-#define AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM 9
-#define AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM 32
-
-static struct al_eth_tx_gpd_cam_entry
-al_eth_generic_tx_crc_gpd[AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM] = {
-
-	/* [0] roce (with grh, bth) */
-	{22,		0,		0,		0,		1,
-	 0x1f,		0x0,		0x0,		0x0,		},
-	/* [1] fcoe */
-	{21,		0,		0,		0,		1,
-	 0x1f,		0x0,		0x0,		0x0,		},
-	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
-	{8,		23,		0,		0,		1,
-	 0x1f,		0x1f,		0x0,		0x0,		},
-	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
-	{11,		23,		0,		0,		1,
-	 0x1f,		0x1f,		0x0,		0x0,		},
-	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
-	{23,		0,		5,		0,		1,
-	 0x1f,		0x0,		0x5,		0x0,		},
-	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
-	{23,		0,		3,		0,		1,
-	 0x1f,		0x0,		0x5,		0x0		},
-	/* [6] GENERIC_STORAGE_READ over IPV4 (and udp) */
-	{8,		2,		0,		0,		1,
-	 0x1f,		0x1f,		0x0,		0x0,		},
-	/* [7] GENERIC_STORAGE_READ over IPV6 (and udp) */
-	{11,		2,		0,		0,		1,
-	 0x1f,		0x1f,		0x0,		0x0,		},
-	/* [8] default match */
-	{0,		0,		0,		0,		1,
-	 0x0,		0x0,		0x0,		0x0		}
-};
-
-static struct al_eth_tx_gcp_table_entry
-al_eth_generic_tx_crc_gcp[AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM] = {
-
-	/* [0] roce (with grh, bth) */
-	{0,		1,		1,		0,		1,
-	 0,		4,		8,		0,		1,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0xffff7f03,	0x00000000,	0x00000000,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
-	 0},
-	/* [1] fcoe */
-	{0,		1,		0,		0,		1,
-	 0,		8,		14,		1,		1,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
-	 0},
-	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
-	 0},
-	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
-	 0},
-	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 2,		0,		0,		0,		10,
-	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
-	 28},
-	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 2,		0,		0,		0,		10,
-	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
-	 48},
-	/* [6] GENERIC_STORAGE_READ over IPV4 (and udp) */
-	{1,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 1,		0,		1,		0,		2,
-	 10,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
-	 8},
-	/* [7] GENERIC_STORAGE_READ over IPV6 (and udp) */
-	{1,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 1,		0,		1,		0,		2,
-	 10,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
-	 8},
-	/* [8] default match */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	  0x00000000},	0x00000000,	0x0,
-	 0}
-};
-
-static struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry
-al_eth_tx_crc_chksum_replace_cmd[AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM] = {
-
-	/* [0] roce (with grh, bth) */
-	{0,1,0,1,		0,0,0,0,		0,0,0,0},
-	/* [1] fcoe */
-	{0,1,0,1,		0,0,0,0,		0,0,0,0},
-	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
-	{0,0,1,1,		0,0,0,0,		0,1,0,1},
-	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
-	{0,0,1,1,		0,0,0,0,		0,0,0,0},
-	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
-	{0,1,0,1,		0,0,0,0,		0,0,0,0},
-	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
-	{0,1,0,1,		0,0,0,0,		0,0,0,0},
-	/* [6] GENERIC_STORAGE_READ over IPV4 (and udp) */
-	{0,0,1,1,		0,0,0,0,		0,1,0,1},
-	/* [7] GENERIC_STORAGE_READ over IPV6 (and udp) */
-	{0,0,1,1,		0,0,0,0,		0,0,0,0},
-	/* [8] default match */
-	{0,0,0,0,		0,0,1,1,		0,1,0,1}
-};
-
-static struct al_eth_rx_gpd_cam_entry
-al_eth_generic_rx_crc_gpd[AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM] = {
-
-	/* [0] roce (with grh, bth) */
-	{22,		0,		0,		0,
-	 0,		0,		0,		0,		1,
-	 0x1f,		0x0,		0x0,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [1] fcoe */
-	{21,		0,		0,		0,
-	 0,		0,		0,		0,		1,
-	 0x1f,		0x0,		0x0,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
-	{8,		23,		0,		0,
-	 0,		0,		0,		0,		1,
-	 0x1f,		0x1f,		0x0,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
-	{11,		23,		0,		0,
-	 0,		0,		0,		0,		1,
-	 0x1f,		0x1f,		0x0,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
-	{8,		13,		23,		0,
-	 0,		0,		0,		0,		1,
-	 0x1f,		0x1f,		0x1f,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
-	{11,		13,		23,		0,
-	 0,		0,		0,		0,		1,
-	 0x1f,		0x1f,		0x1f,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [6] tunneled roce (with grh, bth) over GRE over IPV4 */
-	{8,		0,		22,		0,
-	 4,		0,		0,		0,		1,
-	 0x1f,		0x0,		0x1f,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [7] tunneled roce (with grh, bth) over GRE over IPV6 */
-	{11,		0,		22,		0,
-	 4,		0,		0,		0,		1,
-	 0x1f,		0x0,		0x1f,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [8] tunneled fcoe over IPV4 */
-	{8,		0,		21,		0,
-	 4,		0,		0,		0,		1,
-	 0x1f,		0x0,		0x1f,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-        /* [9] tunneled fcoe over IPV6 */
-        {11,		0,		21,		0,
-	 4,		0,		0,		0,		1,
-         0x1f,		0x0,		0x1f,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [10] tunneled routable_roce that is refered as l4_protocol, over IPV4 (and udp) over IPV4 */
-	{8,             0,              8,              23,
-	 4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1f,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [11] tunneled routable_roce that is refered as l4_protocol, over IPV4 (and udp) over IPV6 */
-	{11,		0,		8,		23,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1f,
-	0x4,		0x0,		0x0,		0x0},
-	/* [12] tunneled routable_roce that is refered as l4_protocol, over IPV6 (and udp) over IPV4 */
-	{8,		0,		11,		23,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1f,
-	0x4,		0x0,		0x0,		0x0},
-	/* [13] tunneled routable_roce that is refered as l4_protocol, over IPV6 (and udp) over IPV6 */
-	{11,		0,		11,		23,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1f,
-	0x4,		0x0,		0x0,		0x0},
-	/* [14] l3_pkt - IPV4 */
-	{8,		0,		0,		0,
-	0,		0,		0,		0,		1,
-	0x1f,		0x1f,		0x0,		0x0,
-	0x4,		0x0,		0x0,		0x0},
-	/* [15] l4_hdr over IPV4 */
-	{8,		12,		0,		0,
-	0,		0,		0,		0,		1,
-	0x1f,		0x1e,		0x0,		0x0,
-	0x4,		0x0,		0x0,		0x0},
-	/* [16] l3_pkt - IPV6 */
-	{11,		0,		0,		0,
-	0,		0,		0,		0,		1,
-	0x1f,		0x1f,		0x0,		0x0,
-	0x4,		0x0,		0x0,		0x0},
-	/* [17] l4_hdr over IPV6 */
-	{11,		12,		0,		0,
-	0,		0,		0,		0,		1,
-	0x1f,		0x1e,		0x0,		0x0,
-	0x4,		0x0,		0x0,		0x0},
-	/* [18] IPV4 over IPV4 */
-	{8,		0,		8,		0,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1f,
-	0x4,		0x0,		0x0,		0x0},
-	/* [19] l4_hdr over IPV4 over IPV4 */
-	{8,		0,		8,		12,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1e,
-	0x4,		0x0,		0x0,		0x0},
-	/* [20] IPV4 over IPV6 */
-	{11,		0,		8,		0,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1f,
-	0x4,		0x0,		0x0,		0x0},
-	/* [21] l4_hdr over IPV4 over IPV6 */
-	{11,		0,		8,		12,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1e,
-	0x4,		0x0,		0x0,		0x0},
-	/* [22] IPV6 over IPV4 */
-	{8,		0,		11,		0,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1f,
-	0x4,		0x0,		0x0,		0x0},
-	/* [23] l4_hdr over IPV6 over IPV4 */
-	{8,		0,		11,		12,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1e,
-	0x4,		0x0,		0x0,		0x0},
-	/* [24] IPV6 over IPV6 */
-	{11,		0,		11,		0,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1f,
-	0x4,		0x0,		0x0,		0x0},
-	/* [25] l4_hdr over IPV6 over IPV6 */
-	{11,		0,		11,		12,
-	4,		0,		0,		0,		1,
-	0x1f,		0x0,		0x1f,		0x1e,
-	0x4,		0x0,		0x0,		0x0},
-	/* [26] GENERIC_STORAGE_READ, over IPV4 (and udp) */
-	{8,		2,		0,		0,
-	0,		0,		0,		0,		1,
-	0x1f,		0x1f,		0x0,		0x0,
-	0x4,		0x0,		0x0,		0x0},
-	/* [27] GENERIC_STORAGE_READ, over IPV6 (and udp) */
-	{11,		2,		0,		0,
-	0,		0,		0,		0,		1,
-	0x1f,		0x1f,		0x0,		0x0,
-	0x4,		0x0,		0x0,		0x0},
-	/* [28] tunneled GENERIC_STORAGE_READ over IPV4 (and udp) over IPV4/IPV6 */
-	{8,		0,		8,		2,
-	4,		0,		0,		0,		1,
-	0x18,		0x0,		0x1f,		0x1f,
-	0x4,		0x0,		0x0,		0x0},
-	/* [29] tunneled GENERIC_STORAGE_READ over IPV6 (and udp)  over IPV4/IPV6 */
-	{8,		0,		11,		2,
-	4,		0,		0,		0,		1,
-	0x18,		0x0,		0x1f,		0x1f,
-	0x4,		0x0,		0x0,		0x0},
-	/* [30] tunneled L2 over GRE over IPV4 */
-	{8,		0,		0,		0,
-	 4,		0,		0,		0,		1,
-	 0x1f,		0x0,		0x1f,		0x0,
-	 0x4,		0x0,		0x0,		0x0},
-	/* [31] default match */
-	{0,		0,		0,		0,
-	 0,		0,		0,		0,		1,
-	 0x0,		0x0,		0x0,		0x0,
-	 0x0,		0x0,		0x0,		0x0}
-};
-
-static struct al_eth_rx_gcp_table_entry
-al_eth_generic_rx_crc_gcp[AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM] = {
-
-	/* [0] roce (with grh, bth) */
-	{0,		 1,		1,		0,		1,
-	 0,		4,		8,		0,		1,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0xffff7f03,	0x00000000,	0x00000000,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
-	 0},
-	/* [1] fcoe */
-	{0,		1,		0,		0,		1,
-	 0,		8,		14,		1,		1,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
-	 0},
-	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000011,
-	 0},
-	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
-	 0},
-	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 2,		0,		0,		0,		10,
-	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0302201c,
-	 28},
-	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 2,		0,		0,		0,		10,
-	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03002018,
-	 48},
-	/* [6] tunneled roce (with grh, bth) over IPV4 */
-	{0,		1,		1,		0,		1,
-	 0,		4,		8,		0,		1,
-	 0,		0,		0,		1,		0,
-	 0,		0,		{0xffff7f03,	0x00000000,	0x00000000,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03020014,
-	 0},
-	/* [7] tunneled roce (with grh, bth) over IPV6 */
-	{0,		1,		1,		0,		1,
-	 0,		4,		8,		0,		1,
-	 0,		0,		0,		1,		0,
-	 0,		0,		{0xffff7f03,	0x00000000,	0x00000000,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
-	 0},
-	/* [8] tunneled fcoe over IPV4 */
-	{0,		1,		0,		0,		1,
-	 0,		8,		14,		1,		1,
-	 0,		0,		0,		1,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03020014,
-	 0},
-	/* [9] tunneled fcoe over IPV6 */
-	{0,		1,		0,		0,		1,
-	 0,		8,		14,		1,		1,
-	 0,		0,		0,		1,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
-	 0},
-	/* [10] tunneled routable_roce that is refered as l4_protocol, over IPV4 (and udp) over IPV4 */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		1,		0,
-	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03020015,
-	 0},
-	/* [11] tunneled routable_roce that is refered as l4_protocol, over IPV4 (and udp) over IPV6 */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		1,		0,
-	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000011,
-	 0},
-	/* [12] tunneled routable_roce that is refered as l4_protocol, over IPV6 (and udp) over IPV4 */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		1,		0,
-	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03020014,
-	 0},
-	/* [13] tunneled routable_roce that is refered as l4_protocol, over IPV6 (and udp) over IPV6 */
-	{0,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		1,		0,
-	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
-	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
-	 0},
-	/* [14] l3_pkt - IPV4 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000001,
-	 0},
-	/* [15] l4_hdr over IPV4 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000003,
-	 0},
-	/* [16] l3_pkt - IPV6 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000000,
-	 0},
-	/* [17] l4_hdr over IPV6 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000002,
-	 0},
-	/* [18] IPV4 over IPV4 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020005,
-	 0},
-	/* [19] l4_hdr over IPV4 over IPV4 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020007,
-	 0},
-	/* [20] IPV4 over IPV6 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000001,
-	 0},
-	/* [21] l4_hdr over IPV4 over IPV6 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000003,
-	 0},
-	/* [22] IPV6 over IPV4 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020004,
-	 0},
-	/* [23] l4_hdr over IPV6 over IPV4 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020006,
-	 0},
-	/* [24] IPV6 over IPV6 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000000,
-	 0},
-	/* [25] l4_hdr over IPV6 over IPV6 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000002,
-	 0},
-	/* [26] GENERIC_STORAGE_READ, over IPV4 (and udp) */
-	{1,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		2,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000011,
-	 0},
-	/* [27] GENERIC_STORAGE_READ, over IPV6 (and udp) */
-	{1,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		2,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
-	 0},
-	/* [28] tunneled GENERIC_STORAGE_READ over IPV4 (and udp) over IPV4/IPV6 */
-	{1,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		3,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000011,
-	 0},
-	/* [29] tunneled GENERIC_STORAGE_READ over IPV6 (and udp)  over IPV4/IPV6 */
-	{1,		1,		1,		0,		1,
-	 0,		4,		0,		0,		1,
-	 0,		0,		0,		3,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
-	 0},
-	/* [30] tunneled L2 over GRE over IPV4 */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020004,
-	 0},
-	/* [31] default match */
-	{0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		0,		0,		0,
-	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
-	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x0,
-	 0}
-};
-
-int al_eth_tx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter)
-{
-	int idx;
-	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
-
-	for (idx = 0; idx < AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM; idx++)
-		al_eth_tx_protocol_detect_table_entry_set(adapter, idx,
-				&al_eth_generic_tx_crc_gpd[idx]);
-
-	return 0;
-}
-
-int al_eth_tx_generic_crc_table_init(struct al_hal_eth_adapter *adapter)
-{
-	int idx;
-	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
-
-	al_dbg("eth [%s]: enable tx_generic_crc\n", adapter->name);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_legacy, 0x0);
-	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace, 0x0);
-	for (idx = 0; idx < AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM; idx++)
-		al_eth_tx_generic_crc_table_entry_set(adapter, idx,
-				&al_eth_generic_tx_crc_gcp[idx]);
-
-	return 0;
-}
-
-int al_eth_tx_crc_chksum_replace_cmd_init(struct al_hal_eth_adapter *adapter)
-{
-	int idx;
-	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
-
-	for (idx = 0; idx < AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM; idx++)
-		al_eth_tx_crc_chksum_replace_cmd_entry_set(adapter, idx,
-				&al_eth_tx_crc_chksum_replace_cmd[idx]);
-
-	return 0;
-}
-
-int al_eth_rx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter)
-{
-	int idx;
-	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p1,
-			AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L3_PROTO_IDX_OFFSET);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p2,
-			AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L4_PROTO_IDX_OFFSET);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p3,
-			AL_ETH_RX_GPD_PARSE_RESULT_INNER_L3_PROTO_IDX_OFFSET);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p4,
-			AL_ETH_RX_GPD_PARSE_RESULT_INNER_L4_PROTO_IDX_OFFSET);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p5,
-			AL_ETH_RX_GPD_PARSE_RESULT_OUTER_PARSE_CTRL);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p6,
-			AL_ETH_RX_GPD_PARSE_RESULT_INNER_PARSE_CTRL);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p7,
-			AL_ETH_RX_GPD_PARSE_RESULT_L3_PRIORITY);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p8,
-			AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L4_DST_PORT_LSB);
-
-	for (idx = 0; idx < AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM; idx++)
-		al_eth_rx_protocol_detect_table_entry_set(adapter, idx,
-				&al_eth_generic_rx_crc_gpd[idx]);
-	return 0;
-}
-
-int al_eth_rx_generic_crc_table_init(struct al_hal_eth_adapter *adapter)
-	{
-	int idx;
-	uint32_t val;
-
-	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
-
-	al_dbg("eth [%s]: enable rx_generic_crc\n", adapter->name);
-	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_legacy, 0x0);
-
-	for (idx = 0; idx < AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM; idx++)
-		al_eth_rx_generic_crc_table_entry_set(adapter, idx,
-				&al_eth_generic_rx_crc_gcp[idx]);
-
-	val = EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_15_CRC_RES_SEL |
-			EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_14_L3_CKS_RES_SEL |
-			EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_13_L4_CKS_RES_SEL |
-			EC_GEN_V3_RX_COMP_DESC_W0_L3_CKS_RES_SEL;
-	al_reg_write32_masked(&adapter->ec_regs_base->gen_v3.rx_comp_desc,
-			val, val);
-	return 0;
-}
-
-/** @} end of Ethernet group */
-
diff --git a/sys/contrib/cloudabi/cloudabi_vdso_armv6.S b/sys/contrib/cloudabi/cloudabi_vdso_armv6.S
new file mode 100644
index 000000000000..b4d68cc9b658
--- /dev/null
+++ b/sys/contrib/cloudabi/cloudabi_vdso_armv6.S
@@ -0,0 +1,451 @@
+// Copyright (c) 2016 Nuxi (https://nuxi.nl/) and contributors.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+// OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+// SUCH DAMAGE.
+//
+// This file is automatically generated. Do not edit.
+//
+// Source: https://github.com/NuxiNL/cloudabi
+
+#define ENTRY(name)      \
+  .text;                 \
+  .p2align 2;            \
+  .global name;          \
+  .type name, %function; \
+name:
+
+#define END(name) .size name, . - name
+
+ENTRY(cloudabi_sys_clock_res_get)
+  str r1, [sp, #-4]
+  mov ip, #0
+  swi 0
+  ldrcc r2, [sp, #-4]
+  strcc r0, [r2, 0]
+  strcc r1, [r2, 4]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_clock_res_get)
+
+ENTRY(cloudabi_sys_clock_time_get)
+  mov ip, #1
+  swi 0
+  ldrcc r2, [sp, #0]
+  strcc r0, [r2, 0]
+  strcc r1, [r2, 4]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_clock_time_get)
+
+ENTRY(cloudabi_sys_condvar_signal)
+  mov ip, #2
+  swi 0
+  bx lr
+END(cloudabi_sys_condvar_signal)
+
+ENTRY(cloudabi_sys_fd_close)
+  mov ip, #3
+  swi 0
+  bx lr
+END(cloudabi_sys_fd_close)
+
+ENTRY(cloudabi_sys_fd_create1)
+  str r1, [sp, #-4]
+  mov ip, #4
+  swi 0
+  ldrcc r2, [sp, #-4]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_fd_create1)
+
+ENTRY(cloudabi_sys_fd_create2)
+  str r1, [sp, #-4]
+  str r2, [sp, #-8]
+  mov ip, #5
+  swi 0
+  ldrcc r2, [sp, #-4]
+  ldrcc r3, [sp, #-8]
+  strcc r0, [r2]
+  strcc r1, [r3]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_fd_create2)
+
+ENTRY(cloudabi_sys_fd_datasync)
+  mov ip, #6
+  swi 0
+  bx lr
+END(cloudabi_sys_fd_datasync)
+
+ENTRY(cloudabi_sys_fd_dup)
+  str r1, [sp, #-4]
+  mov ip, #7
+  swi 0
+  ldrcc r2, [sp, #-4]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_fd_dup)
+
+ENTRY(cloudabi_sys_fd_pread)
+  mov ip, #8
+  swi 0
+  ldrcc r2, [sp, #8]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_fd_pread)
+
+ENTRY(cloudabi_sys_fd_pwrite)
+  mov ip, #9
+  swi 0
+  ldrcc r2, [sp, #8]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_fd_pwrite)
+
+ENTRY(cloudabi_sys_fd_read)
+  str r3, [sp, #-4]
+  mov ip, #10
+  swi 0
+  ldrcc r2, [sp, #-4]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_fd_read)
+
+ENTRY(cloudabi_sys_fd_replace)
+  mov ip, #11
+  swi 0
+  bx lr
+END(cloudabi_sys_fd_replace)
+
+ENTRY(cloudabi_sys_fd_seek)
+  mov ip, #12
+  swi 0
+  ldrcc r2, [sp, #4]
+  strcc r0, [r2, 0]
+  strcc r1, [r2, 4]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_fd_seek)
+
+ENTRY(cloudabi_sys_fd_stat_get)
+  mov ip, #13
+  swi 0
+  bx lr
+END(cloudabi_sys_fd_stat_get)
+
+ENTRY(cloudabi_sys_fd_stat_put)
+  mov ip, #14
+  swi 0
+  bx lr
+END(cloudabi_sys_fd_stat_put)
+
+ENTRY(cloudabi_sys_fd_sync)
+  mov ip, #15
+  swi 0
+  bx lr
+END(cloudabi_sys_fd_sync)
+
+ENTRY(cloudabi_sys_fd_write)
+  str r3, [sp, #-4]
+  mov ip, #16
+  swi 0
+  ldrcc r2, [sp, #-4]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_fd_write)
+
+ENTRY(cloudabi_sys_file_advise)
+  mov ip, #17
+  swi 0
+  bx lr
+END(cloudabi_sys_file_advise)
+
+ENTRY(cloudabi_sys_file_allocate)
+  mov ip, #18
+  swi 0
+  bx lr
+END(cloudabi_sys_file_allocate)
+
+ENTRY(cloudabi_sys_file_create)
+  mov ip, #19
+  swi 0
+  bx lr
+END(cloudabi_sys_file_create)
+
+ENTRY(cloudabi_sys_file_link)
+  mov ip, #20
+  swi 0
+  bx lr
+END(cloudabi_sys_file_link)
+
+ENTRY(cloudabi_sys_file_open)
+  mov ip, #21
+  swi 0
+  ldrcc r2, [sp, #8]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_file_open)
+
+ENTRY(cloudabi_sys_file_readdir)
+  mov ip, #22
+  swi 0
+  ldrcc r2, [sp, #8]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_file_readdir)
+
+ENTRY(cloudabi_sys_file_readlink)
+  mov ip, #23
+  swi 0
+  ldrcc r2, [sp, #4]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_file_readlink)
+
+ENTRY(cloudabi_sys_file_rename)
+  mov ip, #24
+  swi 0
+  bx lr
+END(cloudabi_sys_file_rename)
+
+ENTRY(cloudabi_sys_file_stat_fget)
+  mov ip, #25
+  swi 0
+  bx lr
+END(cloudabi_sys_file_stat_fget)
+
+ENTRY(cloudabi_sys_file_stat_fput)
+  mov ip, #26
+  swi 0
+  bx lr
+END(cloudabi_sys_file_stat_fput)
+
+ENTRY(cloudabi_sys_file_stat_get)
+  mov ip, #27
+  swi 0
+  bx lr
+END(cloudabi_sys_file_stat_get)
+
+ENTRY(cloudabi_sys_file_stat_put)
+  mov ip, #28
+  swi 0
+  bx lr
+END(cloudabi_sys_file_stat_put)
+
+ENTRY(cloudabi_sys_file_symlink)
+  mov ip, #29
+  swi 0
+  bx lr
+END(cloudabi_sys_file_symlink)
+
+ENTRY(cloudabi_sys_file_unlink)
+  mov ip, #30
+  swi 0
+  bx lr
+END(cloudabi_sys_file_unlink)
+
+ENTRY(cloudabi_sys_lock_unlock)
+  mov ip, #31
+  swi 0
+  bx lr
+END(cloudabi_sys_lock_unlock)
+
+ENTRY(cloudabi_sys_mem_advise)
+  mov ip, #32
+  swi 0
+  bx lr
+END(cloudabi_sys_mem_advise)
+
+ENTRY(cloudabi_sys_mem_lock)
+  mov ip, #33
+  swi 0
+  bx lr
+END(cloudabi_sys_mem_lock)
+
+ENTRY(cloudabi_sys_mem_map)
+  mov ip, #34
+  swi 0
+  ldrcc r2, [sp, #16]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_mem_map)
+
+ENTRY(cloudabi_sys_mem_protect)
+  mov ip, #35
+  swi 0
+  bx lr
+END(cloudabi_sys_mem_protect)
+
+ENTRY(cloudabi_sys_mem_sync)
+  mov ip, #36
+  swi 0
+  bx lr
+END(cloudabi_sys_mem_sync)
+
+ENTRY(cloudabi_sys_mem_unlock)
+  mov ip, #37
+  swi 0
+  bx lr
+END(cloudabi_sys_mem_unlock)
+
+ENTRY(cloudabi_sys_mem_unmap)
+  mov ip, #38
+  swi 0
+  bx lr
+END(cloudabi_sys_mem_unmap)
+
+ENTRY(cloudabi_sys_poll)
+  str r3, [sp, #-4]
+  mov ip, #39
+  swi 0
+  ldrcc r2, [sp, #-4]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_poll)
+
+ENTRY(cloudabi_sys_poll_fd)
+  mov ip, #40
+  swi 0
+  ldrcc r2, [sp, #8]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_poll_fd)
+
+ENTRY(cloudabi_sys_proc_exec)
+  mov ip, #41
+  swi 0
+  bx lr
+END(cloudabi_sys_proc_exec)
+
+ENTRY(cloudabi_sys_proc_exit)
+  mov ip, #42
+  swi 0
+END(cloudabi_sys_proc_exit)
+
+ENTRY(cloudabi_sys_proc_fork)
+  str r0, [sp, #-4]
+  str r1, [sp, #-8]
+  mov ip, #43
+  swi 0
+  ldrcc r2, [sp, #-4]
+  ldrcc r3, [sp, #-8]
+  strcc r0, [r2]
+  strcc r1, [r3]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_proc_fork)
+
+ENTRY(cloudabi_sys_proc_raise)
+  mov ip, #44
+  swi 0
+  bx lr
+END(cloudabi_sys_proc_raise)
+
+ENTRY(cloudabi_sys_random_get)
+  mov ip, #45
+  swi 0
+  bx lr
+END(cloudabi_sys_random_get)
+
+ENTRY(cloudabi_sys_sock_accept)
+  str r2, [sp, #-4]
+  mov ip, #46
+  swi 0
+  ldrcc r2, [sp, #-4]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_sock_accept)
+
+ENTRY(cloudabi_sys_sock_bind)
+  mov ip, #47
+  swi 0
+  bx lr
+END(cloudabi_sys_sock_bind)
+
+ENTRY(cloudabi_sys_sock_connect)
+  mov ip, #48
+  swi 0
+  bx lr
+END(cloudabi_sys_sock_connect)
+
+ENTRY(cloudabi_sys_sock_listen)
+  mov ip, #49
+  swi 0
+  bx lr
+END(cloudabi_sys_sock_listen)
+
+ENTRY(cloudabi_sys_sock_recv)
+  mov ip, #50
+  swi 0
+  bx lr
+END(cloudabi_sys_sock_recv)
+
+ENTRY(cloudabi_sys_sock_send)
+  mov ip, #51
+  swi 0
+  bx lr
+END(cloudabi_sys_sock_send)
+
+ENTRY(cloudabi_sys_sock_shutdown)
+  mov ip, #52
+  swi 0
+  bx lr
+END(cloudabi_sys_sock_shutdown)
+
+ENTRY(cloudabi_sys_sock_stat_get)
+  mov ip, #53
+  swi 0
+  bx lr
+END(cloudabi_sys_sock_stat_get)
+
+ENTRY(cloudabi_sys_thread_create)
+  str r1, [sp, #-4]
+  mov ip, #54
+  swi 0
+  ldrcc r2, [sp, #-4]
+  strcc r0, [r2]
+  movcc r0, $0
+  bx lr
+END(cloudabi_sys_thread_create)
+
+ENTRY(cloudabi_sys_thread_exit)
+  mov ip, #55
+  swi 0
+END(cloudabi_sys_thread_exit)
+
+ENTRY(cloudabi_sys_thread_yield)
+  mov ip, #56
+  swi 0
+  bx lr
+END(cloudabi_sys_thread_yield)
diff --git a/sys/contrib/cloudabi/cloudabi_vdso_i686.S b/sys/contrib/cloudabi/cloudabi_vdso_i686.S
index 96e4074451b7..d02c6e18dcde 100644
--- a/sys/contrib/cloudabi/cloudabi_vdso_i686.S
+++ b/sys/contrib/cloudabi/cloudabi_vdso_i686.S
@@ -30,7 +30,7 @@
   .p2align 2, 0x90;      \
   .global name;          \
   .type name, @function; \
-  name:
+name:
 
 #define END(name) .size name, . - name
 
@@ -38,7 +38,7 @@ ENTRY(cloudabi_sys_clock_res_get)
   mov $0, %eax
   int $0x80
   jc 1f
-  mov 0x8(%esp), %ecx
+  mov 8(%esp), %ecx
   mov %eax, 0(%ecx)
   mov %edx, 4(%ecx)
   xor %eax, %eax
@@ -50,7 +50,7 @@ ENTRY(cloudabi_sys_clock_time_get)
   mov $1, %eax
   int $0x80
   jc 1f
-  mov 0x10(%esp), %ecx
+  mov 16(%esp), %ecx
   mov %eax, 0(%ecx)
   mov %edx, 4(%ecx)
   xor %eax, %eax
@@ -74,7 +74,7 @@ ENTRY(cloudabi_sys_fd_create1)
   mov $4, %eax
   int $0x80
   jc 1f
-  mov 0x8(%esp), %ecx
+  mov 8(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -85,9 +85,9 @@ ENTRY(cloudabi_sys_fd_create2)
   mov $5, %eax
   int $0x80
   jc 1f
-  mov 0x8(%esp), %ecx
+  mov 8(%esp), %ecx
   mov %eax, (%ecx)
-  mov 0xc(%esp), %ecx
+  mov 12(%esp), %ecx
   mov %edx, (%ecx)
   xor %eax, %eax
 1:
@@ -104,7 +104,7 @@ ENTRY(cloudabi_sys_fd_dup)
   mov $7, %eax
   int $0x80
   jc 1f
-  mov 0x8(%esp), %ecx
+  mov 8(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -115,7 +115,7 @@ ENTRY(cloudabi_sys_fd_pread)
   mov $8, %eax
   int $0x80
   jc 1f
-  mov 0x18(%esp), %ecx
+  mov 24(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -126,7 +126,7 @@ ENTRY(cloudabi_sys_fd_pwrite)
   mov $9, %eax
   int $0x80
   jc 1f
-  mov 0x18(%esp), %ecx
+  mov 24(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -137,7 +137,7 @@ ENTRY(cloudabi_sys_fd_read)
   mov $10, %eax
   int $0x80
   jc 1f
-  mov 0x10(%esp), %ecx
+  mov 16(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -154,7 +154,7 @@ ENTRY(cloudabi_sys_fd_seek)
   mov $12, %eax
   int $0x80
   jc 1f
-  mov 0x14(%esp), %ecx
+  mov 20(%esp), %ecx
   mov %eax, 0(%ecx)
   mov %edx, 4(%ecx)
   xor %eax, %eax
@@ -184,7 +184,7 @@ ENTRY(cloudabi_sys_fd_write)
   mov $16, %eax
   int $0x80
   jc 1f
-  mov 0x10(%esp), %ecx
+  mov 16(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -219,7 +219,7 @@ ENTRY(cloudabi_sys_file_open)
   mov $21, %eax
   int $0x80
   jc 1f
-  mov 0x1c(%esp), %ecx
+  mov 28(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -230,7 +230,7 @@ ENTRY(cloudabi_sys_file_readdir)
   mov $22, %eax
   int $0x80
   jc 1f
-  mov 0x18(%esp), %ecx
+  mov 24(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -241,7 +241,7 @@ ENTRY(cloudabi_sys_file_readlink)
   mov $23, %eax
   int $0x80
   jc 1f
-  mov 0x18(%esp), %ecx
+  mov 24(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -312,7 +312,7 @@ ENTRY(cloudabi_sys_mem_map)
   mov $34, %eax
   int $0x80
   jc 1f
-  mov 0x20(%esp), %ecx
+  mov 32(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -347,7 +347,7 @@ ENTRY(cloudabi_sys_poll)
   mov $39, %eax
   int $0x80
   jc 1f
-  mov 0x10(%esp), %ecx
+  mov 16(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -358,7 +358,7 @@ ENTRY(cloudabi_sys_poll_fd)
   mov $40, %eax
   int $0x80
   jc 1f
-  mov 0x1c(%esp), %ecx
+  mov 28(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -380,9 +380,9 @@ ENTRY(cloudabi_sys_proc_fork)
   mov $43, %eax
   int $0x80
   jc 1f
-  mov 0x4(%esp), %ecx
+  mov 4(%esp), %ecx
   mov %eax, (%ecx)
-  mov 0x8(%esp), %ecx
+  mov 8(%esp), %ecx
   mov %edx, (%ecx)
   xor %eax, %eax
 1:
@@ -405,7 +405,7 @@ ENTRY(cloudabi_sys_sock_accept)
   mov $46, %eax
   int $0x80
   jc 1f
-  mov 0xc(%esp), %ecx
+  mov 12(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
@@ -458,7 +458,7 @@ ENTRY(cloudabi_sys_thread_create)
   mov $54, %eax
   int $0x80
   jc 1f
-  mov 0x8(%esp), %ecx
+  mov 8(%esp), %ecx
   mov %eax, (%ecx)
   xor %eax, %eax
 1:
diff --git a/sys/ddb/db_run.c b/sys/ddb/db_run.c
index 8cfcfc7fdfcd..4ffba48583b8 100644
--- a/sys/ddb/db_run.c
+++ b/sys/ddb/db_run.c
@@ -136,21 +136,29 @@ db_stop_at_pc(int type, int code, bool *is_breakpoint, bool *is_watchpoint)
 	*is_breakpoint = false;	/* might be a breakpoint, but not ours */
 
 	/*
+	 * If not stepping, then silently ignore single-step traps
+	 * (except for clearing the single-step-flag above).
+	 *
 	 * If stepping, then abort if the trap type is unexpected.
 	 * Breakpoints owned by us are expected and were handled above.
 	 * Single-steps are expected and are handled below.  All others
 	 * are unexpected.
 	 *
-	 * If the MD layer doesn't tell us when it is stepping, use the
-	 * bad historical default that all unexepected traps.
+	 * Only do either of these if the MD layer claims to classify
+	 * single-step traps unambiguously (by defining IS_SSTEP_TRAP).
+	 * Otherwise, fall through to the bad historical behaviour
+	 * given by turning unexpected traps into expected traps: if not
+	 * stepping, then expect only breakpoints and stop, and if
+	 * stepping, then expect only single-steps and step.
 	 */
-#ifndef IS_SSTEP_TRAP
-#define	IS_SSTEP_TRAP(type, code)	true
-#endif
+#ifdef IS_SSTEP_TRAP
+	if (db_run_mode == STEP_CONTINUE && IS_SSTEP_TRAP(type, code))
+	    return (false);
 	if (db_run_mode != STEP_CONTINUE && !IS_SSTEP_TRAP(type, code)) {
 	    printf("Stepping aborted\n");
 	    return (true);
 	}
+#endif
 
 	if (db_run_mode == STEP_INVISIBLE) {
 	    db_run_mode = STEP_CONTINUE;
diff --git a/sys/dev/amdsbwd/amd_chipset.h b/sys/dev/amdsbwd/amd_chipset.h
new file mode 100644
index 000000000000..51ef8840661a
--- /dev/null
+++ b/sys/dev/amdsbwd/amd_chipset.h
@@ -0,0 +1,147 @@
+/*-
+ * Copyright (c) 2016 Andriy Gapon <avg@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * The following registers, bits and magic values are defined in Register
+ * Reference Guide documents for SB600, SB7x0, SB8x0, SB9x0 southbridges and
+ * various versions of Fusion Controller Hubs (FCHs).  FCHs integrated into
+ * CPUs are documented in BIOS and Kernel Development Guide documents for
+ * the corresponding processor families.
+ *
+ * At present there are three classes of supported chipsets:
+ * - SB600 and S7x0 southbridges where the SMBus controller device has
+ *   a PCI Device ID of 0x43851002 and a revision less than 0x40
+ * - several types of southbridges and FCHs:
+ *   o SB8x0, SB9x0 southbridges where the SMBus controller device has a PCI
+ *     Device ID of 0x43851002 and a revision greater than or equal to 0x40
+ *   o FCHs where the controller has an ID of 0x780b1022 and a revision less
+ *     than 0x41 (various variants of "Hudson" and "Bolton" as well as FCHs
+ *     integrated into processors, e.g. "Kabini")
+ *   o FCHs where the controller has an ID of 0x790b1022 and a revision less
+ *     than 0x49
+ * - several types of FCHs:
+ *   o FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022
+ *     and a revision greater than or equal to 0x41 (integrated into "Mullins"
+ *     processors, code named "ML")
+ *   o FCHs where the controller has an ID of 0x790b1022 and a revision greater
+ *     than or equal to 0x49 (integrated into "Carrizo" processors, code named
+ *     "KERNCZ" or "CZ")
+ *
+ * The register definitions are compatible within the classes and may be
+ * incompatible accross them.
+ */
+
+/*
+ * IO registers for accessing the PMIO space.
+ * See SB7xx RRG 2.3.3.1.1, for instance.
+ */
+#define	AMDSB_PMIO_INDEX		0xcd6
+#define	AMDSB_PMIO_DATA			(PMIO_INDEX + 1)
+#define	AMDSB_PMIO_WIDTH		2
+
+/*
+ * SB7x0 and compatible registers in the PMIO space.
+ * See SB7xx RRG 2.3.3.2.
+ */
+#define	AMDSB_PM_RESET_STATUS0		0x44
+#define	AMDSB_PM_RESET_STATUS1		0x45
+#define		AMDSB_WD_RST_STS	0x02
+#define	AMDSB_PM_WDT_CTRL		0x69
+#define		AMDSB_WDT_DISABLE	0x01
+#define		AMDSB_WDT_RES_MASK	(0x02 | 0x04)
+#define		AMDSB_WDT_RES_32US	0x00
+#define		AMDSB_WDT_RES_10MS	0x02
+#define		AMDSB_WDT_RES_100MS	0x04
+#define		AMDSB_WDT_RES_1S	0x06
+#define	AMDSB_PM_WDT_BASE_LSB		0x6c
+#define	AMDSB_PM_WDT_BASE_MSB		0x6f
+
+/*
+ * SB8x0 and compatible registers in the PMIO space.
+ * See SB8xx RRG 2.3.3, for instance.
+ */
+#define	AMDSB8_PM_SMBUS_EN		0x2c
+#define		AMDSB8_SMBUS_EN		0x01
+#define		AMDSB8_SMBUS_ADDR_MASK	0xffe0u
+#define	AMDSB8_PM_WDT_EN		0x48
+#define		AMDSB8_WDT_DEC_EN	0x01
+#define		AMDSB8_WDT_DISABLE	0x02
+#define	AMDSB8_PM_WDT_CTRL		0x4c
+#define		AMDSB8_WDT_32KHZ	0x00
+#define		AMDSB8_WDT_1HZ		0x03
+#define		AMDSB8_WDT_RES_MASK	0x03
+#define	AMDSB8_PM_RESET_STATUS0		0xc0
+#define	AMDSB8_PM_RESET_STATUS1		0xc1
+#define		AMDSB8_WD_RST_STS	0x20
+
+/*
+ * Newer FCH registers in the PMIO space.
+ * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04.
+ */
+#define AMDFCH41_PM_DECODE_EN0		0x00
+#define		AMDFCH41_SMBUS_EN	0x10
+#define		AMDFCH41_WDT_EN		0x80
+#define AMDFCH41_PM_DECODE_EN1		0x01
+#define	AMDFCH41_PM_DECODE_EN3		0x03
+#define		AMDFCH41_WDT_RES_MASK	0x03
+#define		AMDFCH41_WDT_RES_32US	0x00
+#define		AMDFCH41_WDT_RES_10MS	0x01
+#define		AMDFCH41_WDT_RES_100MS	0x02
+#define		AMDFCH41_WDT_RES_1S	0x03
+#define		AMDFCH41_WDT_EN_MASK	0x0c
+#define		AMDFCH41_WDT_ENABLE	0x00
+#define	AMDFCH41_PM_ISA_CTRL		0x04
+#define		AMDFCH41_MMIO_EN	0x02
+
+/*
+ * Fixed MMIO addresses for accessing Watchdog and SMBus registers.
+ * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04.
+ */
+#define	AMDFCH41_WDT_FIXED_ADDR		0xfeb00000u
+#define	AMDFCH41_MMIO_ADDR		0xfed80000u
+#define AMDFCH41_MMIO_SMBUS_OFF		0x0a00
+#define AMDFCH41_MMIO_WDT_OFF		0x0b00
+
+/*
+ * PCI Device IDs and revisions.
+ * SB600 RRG 2.3.1.1,
+ * SB7xx RRG 2.3.1.1,
+ * SB8xx RRG 2.3.1,
+ * BKDG for Family 15h Models 60h-6Fh 3.26.6.1,
+ * BKDG for Family 15h Models 70h-7Fh 3.26.6.1,
+ * BKDG for Family 16h Models 00h-0Fh 3.26.7.1,
+ * BKDG for Family 16h Models 30h-3Fh 3.26.7.1.
+ * Also, see i2c-piix4 aka piix4_smbus Linux driver.
+ */
+#define	AMDSB_SMBUS_DEVID		0x43851002
+#define	AMDSB8_SMBUS_REVID		0x40
+#define	AMDFCH_SMBUS_DEVID		0x780b1022
+#define	AMDFCH41_SMBUS_REVID		0x41
+#define	AMDCZ_SMBUS_DEVID		0x790b1022
+#define	AMDCZ49_SMBUS_REVID		0x49
+
diff --git a/sys/dev/amdsbwd/amdsbwd.c b/sys/dev/amdsbwd/amdsbwd.c
index bc6e256bdc75..628aef2554d4 100644
--- a/sys/dev/amdsbwd/amdsbwd.c
+++ b/sys/dev/amdsbwd/amdsbwd.c
@@ -59,38 +59,13 @@ __FBSDID("$FreeBSD$");
 #include <sys/watchdog.h>
 
 #include <dev/pci/pcivar.h>
+#include <dev/amdsbwd/amd_chipset.h>
 #include <isa/isavar.h>
 
-/* SB7xx RRG 2.3.3.1.1. */
-#define	AMDSB_PMIO_INDEX		0xcd6
-#define	AMDSB_PMIO_DATA			(PMIO_INDEX + 1)
-#define	AMDSB_PMIO_WIDTH		2
-/* SB7xx RRG 2.3.3.2. */
-#define	AMDSB_PM_RESET_STATUS0		0x44
-#define	AMDSB_PM_RESET_STATUS1		0x45
-#define		AMDSB_WD_RST_STS	0x02
-/* SB7xx RRG 2.3.3.2, RPR 2.36. */
-#define	AMDSB_PM_WDT_CTRL		0x69
-#define		AMDSB_WDT_DISABLE	0x01
-#define		AMDSB_WDT_RES_MASK	(0x02 | 0x04)
-#define		AMDSB_WDT_RES_32US	0x00
-#define		AMDSB_WDT_RES_10MS	0x02
-#define		AMDSB_WDT_RES_100MS	0x04
-#define		AMDSB_WDT_RES_1S	0x06
-#define	AMDSB_PM_WDT_BASE_LSB		0x6c
-#define	AMDSB_PM_WDT_BASE_MSB		0x6f
-/* SB8xx RRG 2.3.3. */
-#define	AMDSB8_PM_WDT_EN		0x48
-#define		AMDSB8_WDT_DEC_EN	0x01
-#define		AMDSB8_WDT_DISABLE	0x02
-#define	AMDSB8_PM_WDT_CTRL		0x4c
-#define		AMDSB8_WDT_32KHZ	0x00
-#define		AMDSB8_WDT_1HZ		0x03
-#define		AMDSB8_WDT_RES_MASK	0x03
-#define	AMDSB8_PM_RESET_STATUS0		0xC0
-#define	AMDSB8_PM_RESET_STATUS1		0xC1
-#define		AMDSB8_WD_RST_STS	0x20
-/* SB7xx RRG 2.3.4, WDRT. */
+/*
+ * Registers in the Watchdog IO space.
+ * See SB7xx RRG 2.3.4, WDRT.
+ */
 #define	AMDSB_WD_CTRL			0x00
 #define		AMDSB_WD_RUN		0x01
 #define		AMDSB_WD_FIRED		0x02
@@ -101,28 +76,6 @@ __FBSDID("$FreeBSD$");
 #define	AMDSB_WD_COUNT			0x04
 #define		AMDSB_WD_COUNT_MASK	0xffff
 #define	AMDSB_WDIO_REG_WIDTH		4
-/* WDRT */
-#define	MAXCOUNT_MIN_VALUE		511
-/* SB7xx RRG 2.3.1.1, SB600 RRG 2.3.1.1, SB8xx RRG 2.3.1.  */
-#define	AMDSB_SMBUS_DEVID		0x43851002
-#define	AMDSB8_SMBUS_REVID		0x40
-#define	AMDHUDSON_SMBUS_DEVID		0x780b1022
-#define	AMDKERNCZ_SMBUS_DEVID		0x790b1022
-/* BKDG Family 16h Models 30h - 3Fh */
-#define AMDFCH16H3XH_PM_WDT_EN		0x00
-#define		AMDFCH_WDT_DEC_EN	0x80
-#define	AMDFCH16H3XH_PM_WDT_CTRL	0x03
-#define		AMDFCH_WDT_RES_MASK	0x03
-#define		AMDFCH_WDT_RES_32US	0x00
-#define		AMDFCH_WDT_RES_10MS	0x01
-#define		AMDFCH_WDT_RES_100MS	0x02
-#define		AMDFCH_WDT_RES_1S	0x03
-#define		AMDFCH_WDT_ENABLE_MASK	0x0c
-#define		AMDFCH_WDT_ENABLE	0x00
-#define	AMDFCH16H3XH_PM_MMIO_CTRL	0x04
-#define		AMDFCH_WDT_MMIO_EN	0x02
-#define	AMDFCH16H3XH_WDT_ADDR1		0xfed80b00u
-#define	AMDFCH16H3XH_WDT_ADDR2		0xfeb00000u
 
 #define	amdsbwd_verbose_printf(dev, ...)	\
 	do {						\
@@ -297,8 +250,8 @@ amdsbwd_identify(driver_t *driver, device_t parent)
 	if (smb_dev == NULL)
 		return;
 	if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID &&
-	    pci_get_devid(smb_dev) != AMDHUDSON_SMBUS_DEVID &&
-	    pci_get_devid(smb_dev) != AMDKERNCZ_SMBUS_DEVID)
+	    pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID &&
+	    pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID)
 		return;
 
 	child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1);
@@ -397,48 +350,48 @@ amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
 }
 
 static void
-amdsbwd_probe_fch_16h_3xh(device_t dev, struct resource *pmres, uint32_t *addr)
+amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr)
 {
 	uint8_t	val;
 
-	val = pmio_read(pmres, AMDFCH16H3XH_PM_MMIO_CTRL);
-	if ((val & AMDFCH_WDT_MMIO_EN) != 0) {
+	val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
+	if ((val & AMDFCH41_MMIO_EN) != 0) {
 		/* Fixed offset for the watchdog within ACPI MMIO range. */
 		amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n");
-		*addr = AMDFCH16H3XH_WDT_ADDR1;
+		*addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF;
 	} else {
 		/*
 		 * Enable decoding of watchdog MMIO address.
 		 */
-		val = pmio_read(pmres, AMDFCH16H3XH_PM_WDT_EN);
-		val |= AMDFCH_WDT_DEC_EN;
-		pmio_write(pmres, AMDFCH16H3XH_PM_WDT_EN, val);
+		val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
+		val |= AMDFCH41_WDT_EN;
+		pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
 #ifdef AMDSBWD_DEBUG
-		val = pmio_read(pmres, AMDFCH16H3XH_PM_WDT_EN);
-		device_printf(dev, "AMDFCH16H3XH_PM_WDT_EN value = %#04x\n",
+		val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
+		device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n",
 		    val);
 #endif
 
 		/* Special fixed MMIO range for the watchdog. */
-		*addr = AMDFCH16H3XH_WDT_ADDR2;
+		*addr = AMDFCH41_WDT_FIXED_ADDR;
 	}
 
 	/*
 	 * Set watchdog timer tick to 1s and
 	 * enable the watchdog device (in stopped state).
 	 */
-	val = pmio_read(pmres, AMDFCH16H3XH_PM_WDT_CTRL);
-	val &= ~AMDFCH_WDT_RES_MASK;
-	val |= AMDFCH_WDT_RES_1S;
-	val &= ~AMDFCH_WDT_ENABLE_MASK;
-	val |= AMDFCH_WDT_ENABLE;
-	pmio_write(pmres, AMDFCH16H3XH_PM_WDT_CTRL, val);
+	val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
+	val &= ~AMDFCH41_WDT_RES_MASK;
+	val |= AMDFCH41_WDT_RES_1S;
+	val &= ~AMDFCH41_WDT_EN_MASK;
+	val |= AMDFCH41_WDT_ENABLE;
+	pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val);
 #ifdef AMDSBWD_DEBUG
-	val = pmio_read(pmres, AMDFCH16H3XH_PM_WDT_CTRL);
-	amdsbwd_verbose_printf(dev, "AMDFCH16H3XH_PM_WDT_CTRL value = %#04x\n",
+	val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
+	amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n",
 	    val);
 #endif
-	device_set_desc(dev, "AMD FCH Rev 42h+ Watchdog Timer");
+	device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer");
 }
 
 static int
@@ -476,11 +429,12 @@ amdsbwd_probe(device_t dev)
 	revid = pci_get_revid(smb_dev);
 	if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID)
 		amdsbwd_probe_sb7xx(dev, res, &addr);
-	else if (devid == AMDSB_SMBUS_DEVID || devid == AMDKERNCZ_SMBUS_DEVID ||
-	    (devid == AMDHUDSON_SMBUS_DEVID && revid < 0x42))
+	else if (devid == AMDSB_SMBUS_DEVID ||
+	    (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
+	    (devid == AMDCZ_SMBUS_DEVID  && revid < AMDCZ49_SMBUS_REVID))
 		amdsbwd_probe_sb8xx(dev, res, &addr);
 	else
-		amdsbwd_probe_fch_16h_3xh(dev, res, &addr);
+		amdsbwd_probe_fch41(dev, res, &addr);
 
 	bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
 	bus_delete_resource(dev, SYS_RES_IOPORT, rid);
diff --git a/sys/dev/ath/if_ath_tx.c b/sys/dev/ath/if_ath_tx.c
index 6c4e4ca1e294..e6a31e5d62dd 100644
--- a/sys/dev/ath/if_ath_tx.c
+++ b/sys/dev/ath/if_ath_tx.c
@@ -1538,7 +1538,6 @@ ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni,
     struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq)
 {
 	struct ieee80211vap *vap = ni->ni_vap;
-	struct ath_hal *ah = sc->sc_ah;
 	struct ieee80211com *ic = &sc->sc_ic;
 	const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
 	int error, iswep, ismcast, isfrag, ismrr;
@@ -1822,9 +1821,6 @@ ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni,
 		    sc->sc_hwmap[rix].ieeerate, -1);
 
 	if (ieee80211_radiotap_active_vap(vap)) {
-		u_int64_t tsf = ath_hal_gettsf64(ah);
-
-		sc->sc_tx_th.wt_tsf = htole64(tsf);
 		sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
 		if (iswep)
 			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
@@ -2105,7 +2101,6 @@ ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
 	const struct ieee80211_bpf_params *params)
 {
 	struct ieee80211com *ic = &sc->sc_ic;
-	struct ath_hal *ah = sc->sc_ah;
 	struct ieee80211vap *vap = ni->ni_vap;
 	int error, ismcast, ismrr;
 	int keyix, hdrlen, pktlen, try0, txantenna;
@@ -2252,9 +2247,6 @@ ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
 		    sc->sc_hwmap[rix].ieeerate, -1);
 
 	if (ieee80211_radiotap_active_vap(vap)) {
-		u_int64_t tsf = ath_hal_gettsf64(ah);
-
-		sc->sc_tx_th.wt_tsf = htole64(tsf);
 		sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
 		if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
 			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
diff --git a/sys/dev/ath/if_athioctl.h b/sys/dev/ath/if_athioctl.h
index 73905d3fa0a4..9f879893356f 100644
--- a/sys/dev/ath/if_athioctl.h
+++ b/sys/dev/ath/if_athioctl.h
@@ -374,7 +374,6 @@ struct ath_rx_radiotap_header {
 } __packed;
 
 #define ATH_TX_RADIOTAP_PRESENT (		\
-	(1 << IEEE80211_RADIOTAP_TSFT)		| \
 	(1 << IEEE80211_RADIOTAP_FLAGS)		| \
 	(1 << IEEE80211_RADIOTAP_RATE)		| \
 	(1 << IEEE80211_RADIOTAP_DBM_TX_POWER)	| \
@@ -384,7 +383,6 @@ struct ath_rx_radiotap_header {
 
 struct ath_tx_radiotap_header {
 	struct ieee80211_radiotap_header wt_ihdr;
-	u_int64_t	wt_tsf;
 	u_int8_t	wt_flags;
 	u_int8_t	wt_rate;
 	u_int8_t	wt_txpower;
diff --git a/sys/dev/bhnd/bcma/bcma.c b/sys/dev/bhnd/bcma/bcma.c
index 434bbfc57c6d..08808955ba0e 100644
--- a/sys/dev/bhnd/bcma/bcma.c
+++ b/sys/dev/bhnd/bcma/bcma.c
@@ -39,14 +39,14 @@ __FBSDID("$FreeBSD$");
 
 #include <machine/bus.h>
 
-#include "bcmavar.h"
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
 
 #include "bcma_dmp.h"
 
 #include "bcma_eromreg.h"
 #include "bcma_eromvar.h"
 
-#include <dev/bhnd/bhnd_core.h>
+#include "bcmavar.h"
 
 /* RID used when allocating EROM table */
 #define	BCMA_EROM_RID	0
@@ -91,6 +91,44 @@ bcma_detach(device_t dev)
 	return (bhnd_generic_detach(dev));
 }
 
+static device_t
+bcma_add_child(device_t dev, u_int order, const char *name, int unit)
+{
+	struct bcma_devinfo	*dinfo;
+	device_t		 child;
+
+	child = device_add_child_ordered(dev, order, name, unit);
+	if (child == NULL)
+		return (NULL);
+
+	if ((dinfo = bcma_alloc_dinfo(dev)) == NULL) {
+		device_delete_child(dev, child);
+		return (NULL);
+	}
+
+	device_set_ivars(child, dinfo);
+
+	return (child);
+}
+
+static void
+bcma_child_deleted(device_t dev, device_t child)
+{
+	struct bhnd_softc	*sc;
+	struct bcma_devinfo	*dinfo;
+
+	sc = device_get_softc(dev);
+
+	/* Call required bhnd(4) implementation */
+	bhnd_generic_child_deleted(dev, child);
+
+	/* Free bcma device info */
+	if ((dinfo = device_get_ivars(child)) != NULL)
+		bcma_free_dinfo(dev, dinfo);
+
+	device_set_ivars(child, NULL);
+}
+
 static int
 bcma_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
 {
@@ -125,6 +163,9 @@ bcma_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
 	case BHND_IVAR_CORE_UNIT:
 		*result = ci->unit;
 		return (0);
+	case BHND_IVAR_PMU_INFO:
+		*result = (uintptr_t) dinfo->pmu_info;
+		return (0);
 	default:
 		return (ENOENT);
 	}
@@ -133,6 +174,10 @@ bcma_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
 static int
 bcma_write_ivar(device_t dev, device_t child, int index, uintptr_t value)
 {
+	struct bcma_devinfo *dinfo;
+
+	dinfo = device_get_ivars(child);
+
 	switch (index) {
 	case BHND_IVAR_VENDOR:
 	case BHND_IVAR_DEVICE:
@@ -143,6 +188,9 @@ bcma_write_ivar(device_t dev, device_t child, int index, uintptr_t value)
 	case BHND_IVAR_CORE_INDEX:
 	case BHND_IVAR_CORE_UNIT:
 		return (EINVAL);
+	case BHND_IVAR_PMU_INFO:
+		dinfo->pmu_info = (struct bhnd_core_pmu_info *) value;
+		return (0);
 	default:
 		return (ENOENT);
 	}
@@ -156,136 +204,262 @@ bcma_get_resource_list(device_t dev, device_t child)
 }
 
 static int
-bcma_reset_core(device_t dev, device_t child, uint16_t flags)
+bcma_read_iost(device_t dev, device_t child, uint16_t *iost)
 {
-	struct bcma_devinfo *dinfo;
+	uint32_t	value;
+	int		error;
+
+	if ((error = bhnd_read_config(child, BCMA_DMP_IOSTATUS, &value, 4)))
+		return (error);
+
+	/* Return only the bottom 16 bits */
+	*iost = (value & BCMA_DMP_IOST_MASK);
+	return (0);
+}
+
+static int
+bcma_read_ioctl(device_t dev, device_t child, uint16_t *ioctl)
+{
+	uint32_t	value;
+	int		error;
+
+	if ((error = bhnd_read_config(child, BCMA_DMP_IOCTRL, &value, 4)))
+		return (error);
+
+	/* Return only the bottom 16 bits */
+	*ioctl = (value & BCMA_DMP_IOCTRL_MASK);
+	return (0);
+}
+
+static int
+bcma_write_ioctl(device_t dev, device_t child, uint16_t value, uint16_t mask)
+{
+	struct bcma_devinfo	*dinfo;
+	struct bhnd_resource	*r;
+	uint32_t		 ioctl;
 
 	if (device_get_parent(child) != dev)
-		BHND_BUS_RESET_CORE(device_get_parent(dev), child, flags);
+		return (EINVAL);
 
 	dinfo = device_get_ivars(child);
-
-	/* Can't reset the core without access to the agent registers */
-	if (dinfo->res_agent == NULL)
+	if ((r = dinfo->res_agent) == NULL)
 		return (ENODEV);
 
-	/* Start reset */
-	bhnd_bus_write_4(dinfo->res_agent, BHND_RESET_CF, BHND_RESET_CF_ENABLE);
-	bhnd_bus_read_4(dinfo->res_agent, BHND_RESET_CF);
-	DELAY(10);
+	/* Write new value */
+	ioctl = bhnd_bus_read_4(r, BCMA_DMP_IOCTRL);
+	ioctl &= ~(BCMA_DMP_IOCTRL_MASK & mask);
+	ioctl |= (value & mask);
 
-	/* Disable clock */
-	bhnd_bus_write_4(dinfo->res_agent, BHND_CF, flags);
-	bhnd_bus_read_4(dinfo->res_agent, BHND_CF);
-	DELAY(10);
+	bhnd_bus_write_4(r, BCMA_DMP_IOCTRL, ioctl);
 
-	/* Enable clocks & force clock gating */
-	bhnd_bus_write_4(dinfo->res_agent, BHND_CF, BHND_CF_CLOCK_EN |
-	    BHND_CF_FGC | flags);
-	bhnd_bus_read_4(dinfo->res_agent, BHND_CF);
+	/* Perform read-back and wait for completion */
+	bhnd_bus_read_4(r, BCMA_DMP_IOCTRL);
 	DELAY(10);
 
-	/* Complete reset */
-	bhnd_bus_write_4(dinfo->res_agent, BHND_RESET_CF, 0);
-	bhnd_bus_read_4(dinfo->res_agent, BHND_RESET_CF);
-	DELAY(10);
+	return (0);
+}
 
-	/* Release force clock gating */
-	bhnd_bus_write_4(dinfo->res_agent, BHND_CF, BHND_CF_CLOCK_EN | flags);
-	bhnd_bus_read_4(dinfo->res_agent, BHND_CF);
-	DELAY(10);
+static bool
+bcma_is_hw_suspended(device_t dev, device_t child)
+{
+	uint32_t	rst;
+	uint16_t	ioctl;
+	int		error;
+
+	/* Is core held in RESET? */
+	error = bhnd_read_config(child, BCMA_DMP_RESETCTRL, &rst, 4);
+	if (error) {
+		device_printf(child, "error reading HW reset state: %d\n",
+		    error);
+		return (true);
+	}
+
+	if (rst & BMCA_DMP_RC_RESET)
+		return (true);
+
+	/* Is core clocked? */
+	error = bhnd_read_ioctl(child, &ioctl);
+	if (error) {
+		device_printf(child, "error reading HW ioctl register: %d\n",
+		    error);
+		return (true);
+	}
+
+	if (!(ioctl & BHND_IOCTL_CLK_EN))
+		return (true);
+
+	return (false);
+}
+
+static int
+bcma_reset_hw(device_t dev, device_t child, uint16_t ioctl)
+{
+	struct bcma_devinfo		*dinfo;
+	struct bhnd_core_pmu_info	*pm;
+	struct bhnd_resource		*r;
+	int				 error;
+
+	if (device_get_parent(child) != dev)
+		return (EINVAL);
+
+	dinfo = device_get_ivars(child);
+	pm = dinfo->pmu_info;
+
+	/* We require exclusive control over BHND_IOCTL_CLK_EN and
+	 * BHND_IOCTL_CLK_FORCE. */
+	if (ioctl & (BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE))
+		return (EINVAL);
+
+	/* Can't suspend the core without access to the agent registers */
+	if ((r = dinfo->res_agent) == NULL)
+		return (ENODEV);
+
+	/* Place core into known RESET state */
+	if ((error = BHND_BUS_SUSPEND_HW(dev, child)))
+		return (error);
+
+	/*
+	 * Leaving the core in reset:
+	 * - Set the caller's IOCTL flags
+	 * - Enable clocks
+	 * - Force clock distribution to ensure propagation throughout the
+	 *   core.
+	 */
+	error = bhnd_write_ioctl(child, 
+	    ioctl | BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE, UINT16_MAX);
+	if (error)
+		return (error);
+
+	/* Bring the core out of reset */
+	if ((error = bcma_dmp_write_reset(child, dinfo, 0x0)))
+		return (error);
+
+	/* Disable forced clock gating (leaving clock enabled) */
+	error = bhnd_write_ioctl(child, 0x0, BHND_IOCTL_CLK_FORCE);
+	if (error)
+		return (error);
 
 	return (0);
 }
 
 static int
-bcma_suspend_core(device_t dev, device_t child)
+bcma_suspend_hw(device_t dev, device_t child)
 {
-	struct bcma_devinfo *dinfo;
+	struct bcma_devinfo		*dinfo;
+	struct bhnd_core_pmu_info	*pm;
+	struct bhnd_resource		*r;
+	uint32_t			 rst;
+	int				 error;
 
 	if (device_get_parent(child) != dev)
-		BHND_BUS_SUSPEND_CORE(device_get_parent(dev), child);
+		return (EINVAL);
 
 	dinfo = device_get_ivars(child);
+	pm = dinfo->pmu_info;
 
 	/* Can't suspend the core without access to the agent registers */
-	if (dinfo->res_agent == NULL)
+	if ((r = dinfo->res_agent) == NULL)
 		return (ENODEV);
 
-	// TODO - perform suspend
+	/* Wait for any pending reset operations to clear */
+	if ((error = bcma_dmp_wait_reset(child, dinfo)))
+		return (error);
+
+	/* Already in reset? */
+	rst = bhnd_bus_read_4(r, BCMA_DMP_RESETCTRL);
+	if (rst & BMCA_DMP_RC_RESET)
+		return (0);
+
+	/* Put core into reset */
+	if ((error = bcma_dmp_write_reset(child, dinfo, BMCA_DMP_RC_RESET)))
+		return (error);
+
+	/* Clear core flags */
+	if ((error = bhnd_write_ioctl(child, 0x0, UINT16_MAX)))
+		return (error);
+
+	/* Inform PMU that all outstanding request state should be discarded */
+	if (pm != NULL) {
+		if ((error = BHND_PMU_CORE_RELEASE(pm->pm_pmu, pm)))
+			return (error);
+	}
 
-	return (ENXIO);
+	return (0);
 }
 
-static uint32_t
-bcma_read_config(device_t dev, device_t child, bus_size_t offset, u_int width)
+static int
+bcma_read_config(device_t dev, device_t child, bus_size_t offset, void *value,
+    u_int width)
 {
 	struct bcma_devinfo	*dinfo;
 	struct bhnd_resource	*r;
 
 	/* Must be a directly attached child core */
 	if (device_get_parent(child) != dev)
-		return (UINT32_MAX);
+		return (EINVAL);
 
 	/* Fetch the agent registers */
 	dinfo = device_get_ivars(child);
 	if ((r = dinfo->res_agent) == NULL)
-		return (UINT32_MAX);
+		return (ENODEV);
 
 	/* Verify bounds */
 	if (offset > rman_get_size(r->res))
-		return (UINT32_MAX);
+		return (EFAULT);
 
 	if (rman_get_size(r->res) - offset < width)
-		return (UINT32_MAX);
+		return (EFAULT);
 
 	switch (width) {
 	case 1:
-		return (bhnd_bus_read_1(r, offset));
+		*((uint8_t *)value) = bhnd_bus_read_1(r, offset);
+		return (0);
 	case 2:
-		return (bhnd_bus_read_2(r, offset));
+		*((uint16_t *)value) = bhnd_bus_read_2(r, offset);
+		return (0);
 	case 4:
-		return (bhnd_bus_read_4(r, offset));
+		*((uint32_t *)value) = bhnd_bus_read_4(r, offset);
+		return (0);
 	default:
-		return (UINT32_MAX);
+		return (EINVAL);
 	}
 }
 
-static void
-bcma_write_config(device_t dev, device_t child, bus_size_t offset, uint32_t val,
-    u_int width)
+static int
+bcma_write_config(device_t dev, device_t child, bus_size_t offset,
+    const void *value, u_int width)
 {
 	struct bcma_devinfo	*dinfo;
 	struct bhnd_resource	*r;
 
 	/* Must be a directly attached child core */
 	if (device_get_parent(child) != dev)
-		return;
+		return (EINVAL);
 
 	/* Fetch the agent registers */
 	dinfo = device_get_ivars(child);
 	if ((r = dinfo->res_agent) == NULL)
-		return;
+		return (ENODEV);
 
 	/* Verify bounds */
 	if (offset > rman_get_size(r->res))
-		return;
+		return (EFAULT);
 
 	if (rman_get_size(r->res) - offset < width)
-		return;
+		return (EFAULT);
 
 	switch (width) {
 	case 1:
-		bhnd_bus_write_1(r, offset, val);
-		break;
+		bhnd_bus_write_1(r, offset, *(const uint8_t *)value);
+		return (0);
 	case 2:
-		bhnd_bus_write_2(r, offset, val);
-		break;
+		bhnd_bus_write_2(r, offset, *(const uint16_t *)value);
+		return (0);
 	case 4:
-		bhnd_bus_write_4(r, offset, val);
-		break;
+		bhnd_bus_write_4(r, offset, *(const uint32_t *)value);
+		return (0);
 	default:
-		break;
+		return (EINVAL);
 	}
 }
 
@@ -501,19 +675,6 @@ bcma_get_core_ivec(device_t dev, device_t child, u_int intr, uint32_t *ivec)
 	return (0);
 }
 
-static struct bhnd_devinfo *
-bcma_alloc_bhnd_dinfo(device_t dev)
-{
-	struct bcma_devinfo *dinfo = bcma_alloc_dinfo(dev);
-	return ((struct bhnd_devinfo *)dinfo);
-}
-
-static void
-bcma_free_bhnd_dinfo(device_t dev, struct bhnd_devinfo *dinfo)
-{
-	bcma_free_dinfo(dev, (struct bcma_devinfo *)dinfo);
-}
-
 /**
  * Scan the device enumeration ROM table, adding all valid discovered cores to
  * the bus.
@@ -607,16 +768,20 @@ static device_method_t bcma_methods[] = {
 	DEVMETHOD(device_detach,		bcma_detach),
 	
 	/* Bus interface */
+	DEVMETHOD(bus_add_child,		bcma_add_child),
+	DEVMETHOD(bus_child_deleted,		bcma_child_deleted),
 	DEVMETHOD(bus_read_ivar,		bcma_read_ivar),
 	DEVMETHOD(bus_write_ivar,		bcma_write_ivar),
 	DEVMETHOD(bus_get_resource_list,	bcma_get_resource_list),
 
 	/* BHND interface */
 	DEVMETHOD(bhnd_bus_get_erom_class,	bcma_get_erom_class),
-	DEVMETHOD(bhnd_bus_alloc_devinfo,	bcma_alloc_bhnd_dinfo),
-	DEVMETHOD(bhnd_bus_free_devinfo,	bcma_free_bhnd_dinfo),
-	DEVMETHOD(bhnd_bus_reset_core,		bcma_reset_core),
-	DEVMETHOD(bhnd_bus_suspend_core,	bcma_suspend_core),
+	DEVMETHOD(bhnd_bus_read_ioctl,		bcma_read_ioctl),
+	DEVMETHOD(bhnd_bus_write_ioctl,		bcma_write_ioctl),
+	DEVMETHOD(bhnd_bus_read_iost,		bcma_read_iost),
+	DEVMETHOD(bhnd_bus_is_hw_suspended,	bcma_is_hw_suspended),
+	DEVMETHOD(bhnd_bus_reset_hw,		bcma_reset_hw),
+	DEVMETHOD(bhnd_bus_suspend_hw,		bcma_suspend_hw),
 	DEVMETHOD(bhnd_bus_read_config,		bcma_read_config),
 	DEVMETHOD(bhnd_bus_write_config,	bcma_write_config),
 	DEVMETHOD(bhnd_bus_get_port_count,	bcma_get_port_count),
diff --git a/sys/dev/bhnd/bcma/bcma_dmp.h b/sys/dev/bhnd/bcma/bcma_dmp.h
index ae5f8dcb5499..0fd41a7a4f24 100644
--- a/sys/dev/bhnd/bcma/bcma_dmp.h
+++ b/sys/dev/bhnd/bcma/bcma_dmp.h
@@ -245,8 +245,14 @@
 #define	BCMA_DMP_OOBSEL_6_SHIFT	BCMA_DMP_OOBSEL_2_SHIFT
 #define	BCMA_DMP_OOBSEL_7_SHIFT	BCMA_DMP_OOBSEL_3_SHIFT
 
+/* ioctrl */
+#define	BCMA_DMP_IOCTRL_MASK	0x0000FFFF
+
+/* iostatus */
+#define	BCMA_DMP_IOST_MASK	0x0000FFFF
+
 /* resetctrl */
-#define	BMCA_DMP_RC_RESET	1
+#define	BMCA_DMP_RC_RESET	0x00000001
 
 /* config */
 #define	BCMA_DMP_CFG_OOB	0x00000020
diff --git a/sys/dev/bhnd/bcma/bcma_subr.c b/sys/dev/bhnd/bcma/bcma_subr.c
index e6d544cf8485..ff69e5f7e147 100644
--- a/sys/dev/bhnd/bcma/bcma_subr.c
+++ b/sys/dev/bhnd/bcma/bcma_subr.c
@@ -41,6 +41,8 @@ __FBSDID("$FreeBSD$");
 
 #include <dev/bhnd/bhndvar.h>
 
+#include "bcma_dmp.h"
+
 #include "bcmavar.h"
 
 /* Return the resource ID for a device's agent register allocation */
@@ -368,3 +370,62 @@ bcma_free_sport(struct bcma_sport *sport) {
 	free(sport, M_BHND);
 }
 
+
+/**
+ * Given a bcma(4) child's device info, spin waiting for the device's DMP
+ * resetstatus register to clear.
+ * 
+ * @param child The bcma(4) child device.
+ * @param dinfo The @p child device info.
+ * 
+ * @retval 0 success
+ * @retval ENODEV if @p dinfo does not map an agent register resource.
+ * @retval ETIMEDOUT if timeout occurs
+ */
+int
+bcma_dmp_wait_reset(device_t child, struct bcma_devinfo *dinfo)
+{
+	uint32_t rst;
+
+	if (dinfo->res_agent == NULL)
+		return (ENODEV);
+
+	/* 300us should be long enough, but there are references to this
+	 * requiring up to 10ms when performing reset of an 80211 core
+	 * after a MAC PSM microcode watchdog event. */
+	for (int i = 0; i < 10000; i += 10) {
+		rst = bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_RESETSTATUS);
+		if (rst == 0)
+			return (0);
+
+		DELAY(10);
+	}
+
+	device_printf(child, "BCMA_DMP_RESETSTATUS timeout\n");
+	return (ETIMEDOUT);
+}
+
+/**
+ * Set the bcma(4) child's DMP resetctrl register value, and then wait
+ * for all backplane operations to complete.
+ * 
+ * @param child The bcma(4) child device.
+ * @param dinfo The @p child device info.
+ * @param value The new ioctrl value to set.
+ * 
+ * @retval 0 success
+ * @retval ENODEV if @p dinfo does not map an agent register resource.
+ * @retval ETIMEDOUT if timeout occurs waiting for reset completion
+ */
+int
+bcma_dmp_write_reset(device_t child, struct bcma_devinfo *dinfo, uint32_t value)
+{
+	if (dinfo->res_agent == NULL)
+		return (ENODEV);
+
+	bhnd_bus_write_4(dinfo->res_agent, BCMA_DMP_RESETCTRL, value);
+	bhnd_bus_read_4(dinfo->res_agent, BCMA_DMP_RESETCTRL); /* read-back */
+	DELAY(10);
+
+	return (bcma_dmp_wait_reset(child, dinfo));
+}
diff --git a/sys/dev/bhnd/bcma/bcmavar.h b/sys/dev/bhnd/bcma/bcmavar.h
index 8d1c08e5d4f2..1cdabcd6a81d 100644
--- a/sys/dev/bhnd/bcma/bcmavar.h
+++ b/sys/dev/bhnd/bcma/bcmavar.h
@@ -99,6 +99,11 @@ void			 bcma_free_corecfg(struct bcma_corecfg *corecfg);
 struct bcma_sport	*bcma_alloc_sport(bcma_pid_t port_num, bhnd_port_type port_type);
 void			 bcma_free_sport(struct bcma_sport *sport);
 
+int			 bcma_dmp_wait_reset(device_t child,
+			     struct bcma_devinfo *dinfo);
+int			 bcma_dmp_write_reset(device_t child,
+			     struct bcma_devinfo *dinfo, uint32_t value);
+
 /** BCMA master port descriptor */
 struct bcma_mport {
 	bcma_pid_t	mp_num;		/**< AXI port identifier (bus-unique) */
@@ -150,14 +155,14 @@ struct bcma_corecfg {
  * BCMA per-device info
  */
 struct bcma_devinfo {
-	struct bhnd_devinfo	 bhnd_dinfo;	/**< superclass device info. */
+	struct resource_list		 resources;	/**< Slave port memory regions. */
+	struct bcma_corecfg		*corecfg;	/**< IP core/block config */
 
-	struct resource_list	 resources;	/**< Slave port memory regions. */
-	struct bcma_corecfg	*corecfg;	/**< IP core/block config */
+	struct bhnd_resource		*res_agent;	/**< Agent (wrapper) resource, or NULL. Not
+							  *  all bcma(4) cores have or require an agent. */
+	int				 rid_agent;	/**< Agent resource ID, or -1 */
 
-	struct bhnd_resource	*res_agent;	/**< Agent (wrapper) resource, or NULL. Not
-						  *  all bcma(4) cores have or require an agent. */
-	int			 rid_agent;	/**< Agent resource ID, or -1 */
+	struct bhnd_core_pmu_info	*pmu_info;	/**< Bus-managed PMU state, or NULL */
 };
 
 
diff --git a/sys/dev/bhnd/bhnd.c b/sys/dev/bhnd/bhnd.c
index 63acead4875f..104ca8ecb44a 100644
--- a/sys/dev/bhnd/bhnd.c
+++ b/sys/dev/bhnd/bhnd.c
@@ -631,7 +631,6 @@ bhnd_generic_alloc_pmu(device_t dev, device_t child)
 	struct bhnd_softc		*sc;
 	struct bhnd_resource		*br;
 	struct chipc_caps		*ccaps;
-	struct bhnd_devinfo		*dinfo;	
 	struct bhnd_core_pmu_info	*pm;
 	struct resource_list		*rl;
 	struct resource_list_entry	*rle;
@@ -644,7 +643,7 @@ bhnd_generic_alloc_pmu(device_t dev, device_t child)
 	GIANT_REQUIRED;	/* for newbus */
 	
 	sc = device_get_softc(dev);
-	dinfo = device_get_ivars(child);
+	pm = bhnd_get_pmu_info(child);
 	pmu_regs = BHND_CLK_CTL_ST;
 
 	if ((ccaps = bhnd_find_chipc_caps(sc)) == NULL) {
@@ -660,7 +659,7 @@ bhnd_generic_alloc_pmu(device_t dev, device_t child)
 	}
 
 	/* already allocated? */
-	if (dinfo->pmu_info != NULL) {
+	if (pm != NULL) {
 		panic("duplicate PMU allocation for %s",
 		    device_get_nameunit(child));
 	}
@@ -728,7 +727,7 @@ bhnd_generic_alloc_pmu(device_t dev, device_t child)
 	br->res = rle->res;
 	br->direct = ((rman_get_flags(rle->res) & RF_ACTIVE) != 0);
 
-	pm = malloc(sizeof(*dinfo->pmu_info), M_BHND, M_NOWAIT);
+	pm = malloc(sizeof(*pm), M_BHND, M_NOWAIT);
 	if (pm == NULL) {
 		free(br, M_BHND);
 		return (ENOMEM);
@@ -738,7 +737,7 @@ bhnd_generic_alloc_pmu(device_t dev, device_t child)
 	pm->pm_res = br;
 	pm->pm_regs = pmu_regs;
 
-	dinfo->pmu_info = pm;
+	bhnd_set_pmu_info(child, pm);
 	return (0);
 }
 
@@ -749,14 +748,13 @@ int
 bhnd_generic_release_pmu(device_t dev, device_t child)
 {
 	struct bhnd_softc		*sc;
-	struct bhnd_devinfo		*dinfo;
+	struct bhnd_core_pmu_info	*pm;
 	device_t			 pmu;
 	int				 error;
 
 	GIANT_REQUIRED;	/* for newbus */
 	
 	sc = device_get_softc(dev);
-	dinfo = device_get_ivars(child);
 
 	if ((pmu = bhnd_find_pmu(sc)) == NULL) {
 		device_printf(sc->dev, 
@@ -765,16 +763,17 @@ bhnd_generic_release_pmu(device_t dev, device_t child)
 	}
 
 	/* dispatch release request */
-	if (dinfo->pmu_info == NULL)
+	pm = bhnd_get_pmu_info(child);
+	if (pm == NULL)
 		panic("pmu over-release for %s", device_get_nameunit(child));
 
-	if ((error = BHND_PMU_CORE_RELEASE(pmu, dinfo->pmu_info)))
+	if ((error = BHND_PMU_CORE_RELEASE(pmu, pm)))
 		return (error);
 
 	/* free PMU info */
-	free(dinfo->pmu_info->pm_res, M_BHND);
-	free(dinfo->pmu_info, M_BHND);
-	dinfo->pmu_info = NULL;
+	bhnd_set_pmu_info(child, NULL);
+	free(pm->pm_res, M_BHND);
+	free(pm, M_BHND);
 
 	return (0);
 }
@@ -786,13 +785,11 @@ int
 bhnd_generic_request_clock(device_t dev, device_t child, bhnd_clock clock)
 {
 	struct bhnd_softc		*sc;
-	struct bhnd_devinfo		*dinfo;
 	struct bhnd_core_pmu_info	*pm;
 
 	sc = device_get_softc(dev);
-	dinfo = device_get_ivars(child);
 
-	if ((pm = dinfo->pmu_info) == NULL)
+	if ((pm = bhnd_get_pmu_info(child)) == NULL)
 		panic("no active PMU request state");
 
 	/* dispatch request to PMU */
@@ -806,13 +803,11 @@ int
 bhnd_generic_enable_clocks(device_t dev, device_t child, uint32_t clocks)
 {
 	struct bhnd_softc		*sc;
-	struct bhnd_devinfo		*dinfo;
 	struct bhnd_core_pmu_info	*pm;
 
 	sc = device_get_softc(dev);
-	dinfo = device_get_ivars(child);
 
-	if ((pm = dinfo->pmu_info) == NULL)
+	if ((pm = bhnd_get_pmu_info(child)) == NULL)
 		panic("no active PMU request state");
 
 	/* dispatch request to PMU */
@@ -826,13 +821,11 @@ int
 bhnd_generic_request_ext_rsrc(device_t dev, device_t child, u_int rsrc)
 {
 	struct bhnd_softc		*sc;
-	struct bhnd_devinfo		*dinfo;
 	struct bhnd_core_pmu_info	*pm;
 
 	sc = device_get_softc(dev);
-	dinfo = device_get_ivars(child);
 
-	if ((pm = dinfo->pmu_info) == NULL)
+	if ((pm = bhnd_get_pmu_info(child)) == NULL)
 		panic("no active PMU request state");
 
 	/* dispatch request to PMU */
@@ -846,13 +839,11 @@ int
 bhnd_generic_release_ext_rsrc(device_t dev, device_t child, u_int rsrc)
 {
 	struct bhnd_softc		*sc;
-	struct bhnd_devinfo		*dinfo;
 	struct bhnd_core_pmu_info	*pm;
 
 	sc = device_get_softc(dev);
-	dinfo = device_get_ivars(child);
 
-	if ((pm = dinfo->pmu_info) == NULL)
+	if ((pm = bhnd_get_pmu_info(child)) == NULL)
 		panic("no active PMU request state");
 
 	/* dispatch request to PMU */
@@ -1035,43 +1026,6 @@ bhnd_child_location_str(device_t dev, device_t child, char *buf,
 }
 
 /**
- * Default bhnd(4) bus driver implementation of BUS_ADD_CHILD().
- * 
- * This implementation manages internal bhnd(4) state, and must be called
- * by subclassing drivers.
- */
-device_t
-bhnd_generic_add_child(device_t dev, u_int order, const char *name, int unit)
-{
-	struct bhnd_devinfo	*dinfo;
-	device_t		 child;
-
-	child = device_add_child_ordered(dev, order, name, unit);
-	if (child == NULL)
-		return (NULL);
-
-	if ((dinfo = BHND_BUS_ALLOC_DEVINFO(dev)) == NULL) {
-		device_delete_child(dev, child);
-		return (NULL);
-	}
-
-	device_set_ivars(child, dinfo);
-
-	return (child);
-}
-
-/**
- * Default bhnd(4) bus driver implementation of BHND_BUS_CHILD_ADDED().
- * 
- * This implementation manages internal bhnd(4) state, and must be called
- * by subclassing drivers.
- */
-void
-bhnd_generic_child_added(device_t dev, device_t child)
-{
-}
-
-/**
  * Default bhnd(4) bus driver implementation of BUS_CHILD_DELETED().
  * 
  * This implementation manages internal bhnd(4) state, and must be called
@@ -1081,21 +1035,16 @@ void
 bhnd_generic_child_deleted(device_t dev, device_t child)
 {
 	struct bhnd_softc	*sc;
-	struct bhnd_devinfo	*dinfo;
 
 	sc = device_get_softc(dev);
 
 	/* Free device info */
-	if ((dinfo = device_get_ivars(child)) != NULL) {
-		if (dinfo->pmu_info != NULL) {
-			/* Releasing PMU requests automatically would be nice,
-			 * but we can't reference per-core PMU register
-			 * resource after driver detach */
-			panic("%s leaked device pmu state\n",
-			    device_get_nameunit(child));
-		}
-
-		BHND_BUS_FREE_DEVINFO(dev, dinfo);
+	if (bhnd_get_pmu_info(child) != NULL) {
+		/* Releasing PMU requests automatically would be nice,
+		 * but we can't reference per-core PMU register
+		 * resource after driver detach */
+		panic("%s leaked device pmu state\n",
+		    device_get_nameunit(child));
 	}
 
 	/* Clean up platform device references */
@@ -1228,7 +1177,6 @@ static device_method_t bhnd_methods[] = {
 
 	/* Bus interface */
 	DEVMETHOD(bus_new_pass,			bhnd_new_pass),
-	DEVMETHOD(bus_add_child,		bhnd_generic_add_child),
 	DEVMETHOD(bus_child_deleted,		bhnd_generic_child_deleted),
 	DEVMETHOD(bus_probe_nomatch,		bhnd_generic_probe_nomatch),
 	DEVMETHOD(bus_print_child,		bhnd_generic_print_child),
@@ -1269,7 +1217,6 @@ static device_method_t bhnd_methods[] = {
 	DEVMETHOD(bhnd_bus_request_ext_rsrc,	bhnd_generic_request_ext_rsrc),
 	DEVMETHOD(bhnd_bus_release_ext_rsrc,	bhnd_generic_release_ext_rsrc),
 
-	DEVMETHOD(bhnd_bus_child_added,		bhnd_generic_child_added),
 	DEVMETHOD(bhnd_bus_is_region_valid,	bhnd_generic_is_region_valid),
 	DEVMETHOD(bhnd_bus_get_nvram_var,	bhnd_generic_get_nvram_var),
 
diff --git a/sys/dev/bhnd/bhnd.h b/sys/dev/bhnd/bhnd.h
index ea4d55d19b53..0e4e03a42fc8 100644
--- a/sys/dev/bhnd/bhnd.h
+++ b/sys/dev/bhnd/bhnd.h
@@ -46,6 +46,8 @@
 
 #include "nvram/bhnd_nvram.h"
 
+struct bhnd_core_pmu_info;
+
 extern devclass_t bhnd_devclass;
 extern devclass_t bhnd_hostb_devclass;
 extern devclass_t bhnd_nvram_devclass;
@@ -67,6 +69,7 @@ enum bhnd_device_vars {
 	BHND_IVAR_CORE_UNIT,	/**< Bus-assigned core unit number,
 				     assigned sequentially (starting at 0) for
 				     each vendor/device pair. */
+	BHND_IVAR_PMU_INFO,	/**< Internal bus-managed PMU state */
 };
 
 /**
@@ -99,6 +102,39 @@ enum {
 
 };
 
+
+/**
+ * Per-core IOCTL flags common to all bhnd(4) cores.
+ */
+enum {
+	BHND_IOCTL_BIST		= 0x8000,	/**< Initiate a built-in self-test (BIST). Must be cleared
+						     after BIST results are read via BHND_IOST_BIST_* */
+	BHND_IOCTL_PME		= 0x4000,	/**< Enable posting of power management events by the core. */
+	BHND_IOCTL_CFLAGS	= 0x3FFC,	/**< Reserved for core-specific ioctl flags. */
+	BHND_IOCTL_CLK_FORCE	= 0x0002,	/**< Force disable of clock gating, resulting in all clocks
+						     being distributed within the core. Should be set when
+						     asserting/deasserting reset to ensure the reset signal
+						     fully propagates to the entire core. */
+	BHND_IOCTL_CLK_EN	= 0x0001,	/**< If cleared, the core clock will be disabled. Should be
+						     set during normal operation, and cleared when the core is
+						     held in reset. */
+};
+
+/**
+ * Per-core IOST flags common to all bhnd(4) cores.
+ */
+enum {
+	BHND_IOST_BIST_DONE	= 0x8000,	/**< Set upon BIST completion (see BHND_IOCTL_BIST), and cleared
+						     if 0 is written to BHND_IOCTL_BIST. */ 
+	BHND_IOST_BIST_FAIL	= 0x4000,	/**< Set upon detection of a BIST error; the value is unspecified
+						     if BIST has not completed and BHND_IOST_BIST_DONE is not set. */
+	BHND_IOST_CLK		= 0x2000,	/**< Set if the core has requested that gated clocks be enabled, or
+						     cleared otherwise. The value is undefined if a core does not
+						     support clock gating. */
+	BHND_IOST_DMA64		= 0x1000,	/**< Set if this core supports 64-bit DMA */
+	BHND_IOST_CFLAGS	= 0x0FFC,	/**< Reserved for core-specific status flags. */
+};
+
 /*
  * Simplified accessors for bhnd device ivars
  */
@@ -113,6 +149,7 @@ BHND_ACCESSOR(vendor_name,	VENDOR_NAME,	const char *);
 BHND_ACCESSOR(device_name,	DEVICE_NAME,	const char *);
 BHND_ACCESSOR(core_index,	CORE_INDEX,	u_int);
 BHND_ACCESSOR(core_unit,	CORE_UNIT,	int);
+BHND_ACCESSOR(pmu_info,		PMU_INFO,	struct bhnd_core_pmu_info *);
 
 #undef	BHND_ACCESSOR
 
@@ -451,6 +488,119 @@ bhnd_get_chipid(device_t dev) {
 	return (BHND_BUS_GET_CHIPID(device_get_parent(dev), dev));
 };
 
+
+/**
+ * Read the current value of a bhnd(4) device's per-core I/O control register.
+ *
+ * @param dev The bhnd bus child device to be queried.
+ * @param[out] ioctl On success, the I/O control register value.
+ *
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval ENODEV If agent/config space for @p child is unavailable.
+ * @retval non-zero If reading the IOCTL register otherwise fails, a regular
+ * unix error code will be returned.
+ */
+static inline int
+bhnd_read_ioctl(device_t dev, uint16_t *ioctl)
+{
+	return (BHND_BUS_READ_IOCTL(device_get_parent(dev), dev, ioctl));
+}
+
+/**
+ * Write @p value and @p mask to a bhnd(4) device's per-core I/O control
+ * register.
+ * 
+ * @param dev The bhnd bus child device for which the IOCTL register will be
+ * written.
+ * @param value The value to be written (see BHND_IOCTL_*).
+ * @param mask Only the bits defined by @p mask will be updated from @p value.
+ *
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval ENODEV If agent/config space for @p child is unavailable.
+ * @retval non-zero If writing the IOCTL register otherwise fails, a regular
+ * unix error code will be returned.
+ */
+static inline int
+bhnd_write_ioctl(device_t dev, uint16_t value, uint16_t mask)
+{
+	return (BHND_BUS_WRITE_IOCTL(device_get_parent(dev), dev, value, mask));
+}
+
+/**
+ * Read the current value of a bhnd(4) device's per-core I/O status register.
+ *
+ * @param dev The bhnd bus child device to be queried.
+ * @param[out] iost On success, the I/O status register value.
+ *
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval ENODEV If agent/config space for @p child is unavailable.
+ * @retval non-zero If reading the IOST register otherwise fails, a regular
+ * unix error code will be returned.
+ */
+static inline int
+bhnd_read_iost(device_t dev, uint16_t *iost)
+{
+	return (BHND_BUS_READ_IOST(device_get_parent(dev), dev, iost));
+}
+
+/**
+ * Return true if the given bhnd device's hardware is currently held
+ * in a RESET state or otherwise not clocked (BHND_IOCTL_CLK_EN).
+ * 
+ * @param dev The device to query.
+ *
+ * @retval true If @p dev is held in RESET or not clocked (BHND_IOCTL_CLK_EN),
+ * or an error occured determining @p dev's hardware state.
+ * @retval false If @p dev is clocked and is not held in RESET.
+ */
+static inline bool
+bhnd_is_hw_suspended(device_t dev)
+{
+	return (BHND_BUS_IS_HW_SUSPENDED(device_get_parent(dev), dev));
+}
+
+/**
+ * Place the bhnd(4) device's hardware into a reset state, and then bring the
+ * hardware out of reset with BHND_IOCTL_CLK_EN and @p ioctl flags set.
+ * 
+ * Any clock or resource PMU requests previously made by @p dev will be
+ * invalidated.
+ *
+ * @param dev The device to be reset.
+ * @param ioctl Device-specific core ioctl flags to be supplied on reset
+ * (see BHND_IOCTL_*).
+ *
+ * @retval 0 success
+ * @retval non-zero error
+ */
+static inline int
+bhnd_reset_hw(device_t dev, uint16_t ioctl)
+{
+	return (BHND_BUS_RESET_HW(device_get_parent(dev), dev, ioctl));
+}
+
+/**
+ * Suspend @p child's hardware in a low-power reset state.
+ *
+ * Any clock or resource PMU requests previously made by @p dev will be
+ * invalidated.
+ *
+ * The hardware may be brought out of reset via bhnd_reset_hw().
+ *
+ * @param dev The device to be suspended.
+ *
+ * @retval 0 success
+ * @retval non-zero error
+ */
+static inline int
+bhnd_suspend_hw(device_t dev)
+{
+	return (BHND_BUS_SUSPEND_HW(device_get_parent(dev), dev));
+}
+
 /**
  * If supported by the chipset, return the clock source for the given clock.
  *
@@ -630,17 +780,18 @@ bhnd_release_pmu(device_t dev)
 /** 
  * Request that @p clock (or faster) be routed to @p dev.
  * 
- * A driver must ask the bhnd bus to allocate clock request state
+ * @note A driver must ask the bhnd bus to allocate clock request state
  * via bhnd_alloc_pmu() before it can request clock resources.
  * 
- * Request multiplexing is managed by the bus.
+ * @note Any outstanding PMU clock requests will be discarded upon calling
+ * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW().
  *
  * @param dev The bhnd(4) device to which @p clock should be routed.
  * @param clock The requested clock source. 
  *
  * @retval 0 success
  * @retval ENODEV If an unsupported clock was requested.
- * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable.
+ * @retval ENXIO If the PMU has not been initialized or is otherwise unvailable,
  */
 static inline int
 bhnd_request_clock(device_t dev, bhnd_clock clock)
@@ -654,12 +805,13 @@ bhnd_request_clock(device_t dev, bhnd_clock clock)
  * This will power any clock sources (e.g. XTAL, PLL, etc) required for
  * @p clocks and wait until they are ready, discarding any previous
  * requests by @p dev.
- *
- * Request multiplexing is managed by the bus.
  * 
- * A driver must ask the bhnd bus to allocate clock request state
+ * @note A driver must ask the bhnd bus to allocate clock request state
  * via bhnd_alloc_pmu() before it can request clock resources.
- *
+ * 
+ * @note Any outstanding PMU clock requests will be discarded upon calling
+ * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW().
+ * 
  * @param dev The requesting bhnd(4) device.
  * @param clocks The clock(s) to be enabled.
  *
@@ -676,9 +828,12 @@ bhnd_enable_clocks(device_t dev, uint32_t clocks)
 /**
  * Power up an external PMU-managed resource assigned to @p dev.
  * 
- * A driver must ask the bhnd bus to allocate PMU request state
+ * @note A driver must ask the bhnd bus to allocate PMU request state
  * via bhnd_alloc_pmu() before it can request PMU resources.
  *
+ * @note Any outstanding PMU resource requests will be released upon calling
+ * bhnd_reset_hw() or bhnd_suspend_hw().
+ *
  * @param dev The requesting bhnd(4) device.
  * @param rsrc The core-specific external resource identifier.
  *
@@ -711,13 +866,14 @@ bhnd_release_ext_rsrc(device_t dev, u_int rsrc)
 	return (BHND_BUS_RELEASE_EXT_RSRC(device_get_parent(dev), dev, rsrc));
 }
 
-
 /**
  * Read @p width bytes at @p offset from the bus-specific agent/config
  * space of @p dev.
  *
  * @param dev The bhnd device for which @p offset should be read.
  * @param offset The offset to be read.
+ * @param[out] value On success, the will be set to the @p width value read
+ * at @p offset.
  * @param width The size of the access. Must be 1, 2 or 4 bytes.
  *
  * The exact behavior of this method is bus-specific. In the case of
@@ -725,32 +881,49 @@ bhnd_release_ext_rsrc(device_t dev, u_int rsrc)
  *
  * @note Device drivers should only use this API for functionality
  * that is not available via another bhnd(4) function.
+ * 
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval EINVAL If @p width is not one of 1, 2, or 4 bytes.
+ * @retval ENODEV If accessing agent/config space for @p child is unsupported.
+ * @retval EFAULT If reading @p width at @p offset exceeds the bounds of
+ * the mapped agent/config space  for @p child.
  */
 static inline uint32_t
-bhnd_read_config(device_t dev, bus_size_t offset, u_int width)
+bhnd_read_config(device_t dev, bus_size_t offset, void *value, u_int width)
 {
 	return (BHND_BUS_READ_CONFIG(device_get_parent(dev), dev, offset,
-	    width));
+	    value, width));
 }
 
 /**
- * Read @p width bytes at @p offset from the bus-specific agent/config
+ * Write @p width bytes at @p offset to the bus-specific agent/config
  * space of @p dev.
  *
  * @param dev The bhnd device for which @p offset should be read.
  * @param offset The offset to be written.
- * @param width The size of the access. Must be 1, 2 or 4 bytes.
+ * @param value A pointer to the value to be written.
+ * @param width The size of @p value. Must be 1, 2 or 4 bytes.
  *
  * The exact behavior of this method is bus-specific. In the case of
  * bcma(4), this method provides access to the first agent port of @p child.
  *
  * @note Device drivers should only use this API for functionality
  * that is not available via another bhnd(4) function.
+ * 
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval EINVAL If @p width is not one of 1, 2, or 4 bytes.
+ * @retval ENODEV If accessing agent/config space for @p child is unsupported.
+ * @retval EFAULT If reading @p width at @p offset exceeds the bounds of
+ * the mapped agent/config space  for @p child.
  */
-static inline void
-bhnd_write_config(device_t dev, bus_size_t offset, uint32_t val, u_int width)
+static inline int
+bhnd_write_config(device_t dev, bus_size_t offset, const void *value,
+    u_int width)
 {
-	BHND_BUS_WRITE_CONFIG(device_get_parent(dev), dev, offset, val, width);
+	return (BHND_BUS_WRITE_CONFIG(device_get_parent(dev), dev, offset,
+	    value, width));
 }
 
 /**
diff --git a/sys/dev/bhnd/bhnd_bus_if.m b/sys/dev/bhnd/bhnd_bus_if.m
index b6a75c415311..1b2bff6d4159 100644
--- a/sys/dev/bhnd/bhnd_bus_if.m
+++ b/sys/dev/bhnd/bhnd_bus_if.m
@@ -63,6 +63,46 @@ CODE {
 		panic("bhnd_bus_get_chipid unimplemented");
 	}
 
+	static int
+	bhnd_bus_null_read_ioctl(device_t dev, device_t child, uint16_t *ioctl)
+	{
+		panic("bhnd_bus_read_ioctl unimplemented");
+	}
+
+
+	static int
+	bhnd_bus_null_write_ioctl(device_t dev, device_t child, uint16_t value,
+	    uint16_t mask)
+	{
+		panic("bhnd_bus_write_ioctl unimplemented");
+	}
+
+
+	static int
+	bhnd_bus_null_read_iost(device_t dev, device_t child, uint16_t *iost)
+	{
+		panic("bhnd_bus_read_iost unimplemented");
+	}
+
+	static bool
+	bhnd_bus_null_is_hw_suspended(device_t dev, device_t child)
+	{
+		panic("bhnd_bus_is_hw_suspended unimplemented");
+	}
+
+	static int
+	bhnd_bus_null_reset_hw(device_t dev, device_t child, uint16_t ioctl)
+	{
+		panic("bhnd_bus_reset_hw unimplemented");
+	}
+
+
+	static int
+	bhnd_bus_null_suspend_hw(device_t dev, device_t child)
+	{
+		panic("bhnd_bus_suspend_hw unimplemented");
+	}
+
 	static bhnd_attach_type
 	bhnd_bus_null_get_attach_type(device_t dev, device_t child)
 	{
@@ -161,16 +201,16 @@ CODE {
 		panic("bhnd_bus_release_ext_rsrc unimplemented");
 	}
 
-	static uint32_t
+	static int
 	bhnd_bus_null_read_config(device_t dev, device_t child,
-	    bus_size_t offset, u_int width)
+	    bus_size_t offset, void *value, u_int width)
 	{
 		panic("bhnd_bus_null_read_config unimplemented");
 	}
 
 	static void
 	bhnd_bus_null_write_config(device_t dev, device_t child,
-	    bus_size_t offset, uint32_t val, u_int width)
+	    bus_size_t offset, void *value, u_int width)
 	{
 		panic("bhnd_bus_null_write_config unimplemented");
 	}
@@ -344,32 +384,6 @@ METHOD int read_board_info {
 } DEFAULT bhnd_bus_null_read_board_info;
 
 /**
- * Allocate and zero-initialize a buffer suitably sized and aligned for a
- * bhnd_devinfo structure.
- *
- * @param dev The bhnd bus device.
- *
- * @retval non-NULL	success
- * @retval NULL		allocation failed
- */
-METHOD struct bhnd_devinfo * alloc_devinfo {
-	device_t dev;
-};
-
-/**
- * Release memory previously allocated for @p devinfo.
- *
- * @param dev The bhnd bus device.
- * @param dinfo A devinfo buffer previously allocated via
- * BHND_BUS_ALLOC_DEVINFO().
- */
-METHOD void free_devinfo {
-	device_t dev;
-	struct bhnd_devinfo *dinfo;
-};
-
-
-/**
  * Return the number of interrupts to be assigned to @p child via
  * BHND_BUS_ASSIGN_INTR().
  * 
@@ -455,34 +469,123 @@ METHOD void child_added {
 } DEFAULT bhnd_bus_null_child_added;
 
 /**
- * Reset the device's hardware core.
+ * Read the current value of @p child's I/O control register.
  *
- * @param dev The parent of @p child.
+ * @param dev The bhnd bus parent of @p child.
+ * @param child The bhnd device for which the I/O control register should be
+ * read.
+ * @param[out] ioctl On success, the I/O control register value.
+ *
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval ENODEV If agent/config space for @p child is unavailable.
+ * @retval non-zero If reading the IOCTL register otherwise fails, a regular
+ * unix error code will be returned.
+ */
+METHOD int read_ioctl {
+	device_t dev;
+	device_t child;
+	uint16_t *ioctl;
+} DEFAULT bhnd_bus_null_read_ioctl;
+
+/**
+ * Write @p value with @p mask to @p child's I/O control register.
+ * 
+ * @param dev The bhnd bus parent of @p child.
+ * @param child The bhnd device for which the I/O control register should
+ * be updated.
+ * @param value The value to be written (see also BHND_IOCTL_*).
+ * @param mask Only the bits defined by @p mask will be updated from @p value.
+ * 
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval ENODEV If agent/config space for @p child is unavailable.
+ * @retval non-zero If writing the IOCTL register otherwise fails, a regular
+ * unix error code will be returned.
+ */
+METHOD int write_ioctl {
+	device_t dev;
+	device_t child;
+	uint16_t value;
+	uint16_t mask;
+} DEFAULT bhnd_bus_null_write_ioctl;
+
+/**
+ * Read the current value of @p child's I/O status register.
+ *
+ * @param dev The bhnd bus parent of @p child.
+ * @param child The bhnd device for which the I/O status register should be
+ * read.
+ * @param[out] iost On success, the I/O status register value.
+ * 
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval ENODEV If agent/config space for @p child is unavailable.
+ * @retval non-zero If reading the IOST register otherwise fails, a regular
+ * unix error code will be returned.
+ */
+METHOD int read_iost {
+	device_t dev;
+	device_t child;
+	uint16_t *iost;
+} DEFAULT bhnd_bus_null_read_iost;
+
+
+/**
+ * Return true if the given bhnd device's hardware is currently held
+ * in a RESET state or otherwise not clocked (BHND_IOCTL_CLK_EN).
+ * 
+ * @param dev The bhnd bus parent of @p child.
+ * @param child The device to query.
+ *
+ * @retval true If @p child is held in RESET or not clocked (BHND_IOCTL_CLK_EN),
+ * or an error occured determining @p child's hardware state.
+ * @retval false If @p child is clocked and is not held in RESET.
+ */
+METHOD bool is_hw_suspended {
+	device_t dev;
+	device_t child;
+} DEFAULT bhnd_bus_null_is_hw_suspended;
+
+/**
+ * Place the bhnd(4) device's hardware into a reset state, and then bring the
+ * hardware out of reset with BHND_IOCTL_CLK_EN and @p ioctl flags set.
+ * 
+ * Any clock or resource PMU requests previously made by @p child will be
+ * invalidated.
+ *
+ * @param dev The bhnd bus parent of @p child.
  * @param child The device to be reset.
- * @param flags Device-specific core flags to be supplied on reset.
+ * @param ioctl Device-specific core ioctl flags to be supplied on reset
+ * (see BHND_IOCTL_*).
  *
  * @retval 0 success
  * @retval non-zero error
  */
-METHOD int reset_core {
+METHOD int reset_hw {
 	device_t dev;
 	device_t child;
-	uint16_t flags;
-}
+	uint16_t ioctl;
+} DEFAULT bhnd_bus_null_reset_hw;
 
 /**
- * Suspend a device hardware core.
+ * Suspend @p child's hardware in a low-power reset state.
  *
- * @param dev The parent of @p child.
- * @param child The device to be reset.
+ * Any clock or resource PMU requests previously made by @p dev will be
+ * invalidated.
+ *
+ * The hardware may be brought out of reset via bhnd_reset_hw().
+ *
+ * @param dev The bhnd bus parent of @P child.
+ * @param dev The device to be suspended.
  *
  * @retval 0 success
  * @retval non-zero error
  */
-METHOD int suspend_core {
+METHOD int suspend_hw {
 	device_t dev;
 	device_t child;
-}
+} DEFAULT bhnd_bus_null_suspend_hw;
 
 /**
  * If supported by the chipset, return the clock source for the given clock.
@@ -578,10 +681,11 @@ METHOD int release_pmu {
 /** 
  * Request that @p clock (or faster) be routed to @p child.
  * 
- * A driver must ask the bhnd bus to allocate PMU request state
+ * @note A driver must ask the bhnd bus to allocate PMU request state
  * via BHND_BUS_ALLOC_PMU() before it can request clock resources.
- * 
- * Request multiplexing is managed by the bus.
+ *
+ * @note Any outstanding PMU clock requests will be discarded upon calling
+ * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW().
  *
  * @param dev The parent of @p child.
  * @param child The bhnd device requesting @p clock.
@@ -604,11 +708,12 @@ METHOD int request_clock {
  * @p clocks and wait until they are ready, discarding any previous
  * requests by @p child.
  *
- * Request multiplexing is managed by the bus.
- * 
- * A driver must ask the bhnd bus to allocate PMU request state
+ * @note A driver must ask the bhnd bus to allocate PMU request state
  * via BHND_BUS_ALLOC_PMU() before it can request clock resources.
  *
+ * @note Any outstanding PMU clock requests will be discarded upon calling
+ * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW().
+ *
  * @param dev The parent of @p child.
  * @param child The bhnd device requesting @p clock.
  * @param clock The requested clock source.
@@ -626,9 +731,12 @@ METHOD int enable_clocks {
 /**
  * Power up an external PMU-managed resource assigned to @p child.
  * 
- * A driver must ask the bhnd bus to allocate PMU request state
+ * @note A driver must ask the bhnd bus to allocate PMU request state
  * via BHND_BUS_ALLOC_PMU() before it can request PMU resources.
  *
+ * @note Any outstanding PMU resource requests will be released upon calling
+ * BHND_BUS_RESET_HW() or BHND_BUS_SUSPEND_HW().
+ *
  * @param dev The parent of @p child.
  * @param child The bhnd device requesting @p rsrc.
  * @param rsrc The core-specific external resource identifier.
@@ -646,7 +754,7 @@ METHOD int request_ext_rsrc {
 /**
  * Power down an external PMU-managed resource assigned to @p child.
  * 
- * A driver must ask the bhnd bus to allocate PMU request state
+ * @note A driver must ask the bhnd bus to allocate PMU request state
  * via BHND_BUS_ALLOC_PMU() before it can request PMU resources.
  *
  * @param dev The parent of @p child.
@@ -670,6 +778,7 @@ METHOD int release_ext_rsrc {
  * @param dev The parent of @p child.
  * @param child The bhnd device for which @p offset should be read.
  * @param offset The offset to be read.
+ * @param[out] value On success, the bytes read at @p offset.
  * @param width The size of the access. Must be 1, 2 or 4 bytes.
  *
  * The exact behavior of this method is bus-specific. On a bcma(4) bus, this
@@ -678,11 +787,19 @@ METHOD int release_ext_rsrc {
  *
  * @note Device drivers should only use this API for functionality
  * that is not available via another bhnd(4) function.
+ *
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval EINVAL If @p width is not one of 1, 2, or 4 bytes.
+ * @retval ENODEV If accessing agent/config space for @p child is unsupported.
+ * @retval EFAULT If reading @p width at @p offset exceeds the bounds of
+ * the mapped agent/config space  for @p child.
  */
-METHOD uint32_t read_config {
+METHOD int read_config {
 	device_t dev;
 	device_t child;
 	bus_size_t offset;
+	void *value;
 	u_int width;
 } DEFAULT bhnd_bus_null_read_config;
 
@@ -693,19 +810,27 @@ METHOD uint32_t read_config {
  * @param dev The parent of @p child.
  * @param child The bhnd device for which @p offset should be read.
  * @param offset The offset to be written.
- * @param width The size of the access. Must be 1, 2 or 4 bytes.
+ * @param value A pointer to the value to be written.
+ * @param width The size of @p value. Must be 1, 2 or 4 bytes.
  *
  * The exact behavior of this method is bus-specific. In the case of
  * bcma(4), this method provides access to the first agent port of @p child.
  *
  * @note Device drivers should only use this API for functionality
  * that is not available via another bhnd(4) function.
+ *
+ * @retval 0 success
+ * @retval EINVAL If @p child is not a direct child of @p dev.
+ * @retval EINVAL If @p width is not one of 1, 2, or 4 bytes.
+ * @retval ENODEV If accessing agent/config space for @p child is unsupported.
+ * @retval EFAULT If reading @p width at @p offset exceeds the bounds of
+ * the mapped agent/config space  for @p child.
  */
-METHOD void write_config {
+METHOD int write_config {
 	device_t dev;
 	device_t child;
 	bus_size_t offset;
-	uint32_t val;
+	const void *value;
 	u_int width;
 } DEFAULT bhnd_bus_null_write_config;
 
diff --git a/sys/dev/bhnd/bhnd_core.h b/sys/dev/bhnd/bhnd_core.h
deleted file mode 100644
index 26506969429a..000000000000
--- a/sys/dev/bhnd/bhnd_core.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*-
- * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
- * Copyright (c) 2010 Broadcom Corporation
- *
- * This file is derived from the hndsoc.h header distributed with
- * Broadcom's initial brcm80211 Linux driver release, as
- * contributed to the Linux staging repository.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- * 
- * $FreeBSD$
- */
-
-#ifndef _BHND_BHND_CORE_H_
-#define _BHND_BHND_CORE_H_
-
-/* Common core control flags */
-#define	BHND_CF 		0x0408
-#define	BHND_CF_BIST_EN		0x8000		/**< built-in self test */
-#define	BHND_CF_PME_EN		0x4000		/**< ??? */
-#define	BHND_CF_CORE_BITS	0x3ffc		/**< core specific flag mask */
-#define	BHND_CF_FGC		0x0002		/**< force clock gating */
-#define	BHND_CF_CLOCK_EN	0x0001		/**< enable clock */
-
-/* Common core status flags */
-#define	BHND_SF			0x0500
-#define	BHND_SF_BIST_DONE	0x8000		/**< ??? */
-#define	BHND_SF_BIST_ERROR	0x4000		/**< ??? */
-#define	BHND_SF_GATED_CLK	0x2000		/**< clock gated */
-#define	BHND_SF_DMA64		0x1000		/**< supports 64-bit DMA */
-#define	BHND_SF_CORE_BITS	0x0fff		/**< core-specific status mask */
-
-/*Reset core control flags */
-#define	BHND_RESET_CF		0x0800
-#define	BHND_RESET_CF_ENABLE	0x0001
-
-#define	BHND_RESET_SF		0x0804
-
-#endif /* _BHND_BHND_CORE_H_ */
diff --git a/sys/dev/bhnd/bhnd_subr.c b/sys/dev/bhnd/bhnd_subr.c
index 31007695a36f..8b70e24376e3 100644
--- a/sys/dev/bhnd/bhnd_subr.c
+++ b/sys/dev/bhnd/bhnd_subr.c
@@ -68,7 +68,7 @@ static const struct bhnd_core_desc {
 	BHND_CDESC(BCM, SRAM,		RAM,		"SRAM"),
 	BHND_CDESC(BCM, SDRAM,		RAM,		"SDRAM"),
 	BHND_CDESC(BCM, PCI,		PCI,		"PCI Bridge"),
-	BHND_CDESC(BCM, MIPS,		CPU,		"MIPS Core"),
+	BHND_CDESC(BCM, MIPS,		CPU,		"BMIPS CPU"),
 	BHND_CDESC(BCM, ENET,		ENET_MAC,	"Fast Ethernet MAC"),
 	BHND_CDESC(BCM, CODEC,		OTHER,		"V.90 Modem Codec"),
 	BHND_CDESC(BCM, USB,		USB_DUAL,	"USB 1.1 Device/Host Controller"),
@@ -85,7 +85,7 @@ static const struct bhnd_core_desc {
 	BHND_CDESC(BCM, APHY,		WLAN_PHY,	"802.11a PHY"),
 	BHND_CDESC(BCM, BPHY,		WLAN_PHY,	"802.11b PHY"),
 	BHND_CDESC(BCM, GPHY,		WLAN_PHY,	"802.11g PHY"),
-	BHND_CDESC(BCM, MIPS33,		CPU,		"MIPS3302 Core"),
+	BHND_CDESC(BCM, MIPS33,		CPU,		"BMIPS33 CPU"),
 	BHND_CDESC(BCM, USB11H,		USB_HOST,	"USB 1.1 Host Controller"),
 	BHND_CDESC(BCM, USB11D,		USB_DEV,	"USB 1.1 Device Controller"),
 	BHND_CDESC(BCM, USB20H,		USB_HOST,	"USB 2.0 Host Controller"),
diff --git a/sys/dev/bhnd/bhndvar.h b/sys/dev/bhnd/bhndvar.h
index c5317a04b5b9..2602302a1861 100644
--- a/sys/dev/bhnd/bhndvar.h
+++ b/sys/dev/bhnd/bhndvar.h
@@ -45,8 +45,6 @@
 MALLOC_DECLARE(M_BHND);
 DECLARE_CLASS(bhnd_driver);
 
-struct bhnd_core_pmu_info;
-
 int			 bhnd_generic_attach(device_t dev);
 int			 bhnd_generic_detach(device_t dev);
 int			 bhnd_generic_shutdown(device_t dev);
@@ -74,9 +72,6 @@ int			 bhnd_generic_print_child(device_t dev,
 void			 bhnd_generic_probe_nomatch(device_t dev,
 			     device_t child);
 
-device_t		 bhnd_generic_add_child(device_t dev, u_int order,
-			     const char *name, int unit);
-void			 bhnd_generic_child_added(device_t dev, device_t child);
 void			 bhnd_generic_child_deleted(device_t dev,
 			     device_t child);
 int			 bhnd_generic_suspend_child(device_t dev,
@@ -88,15 +83,6 @@ int			 bhnd_generic_get_nvram_var(device_t dev,
 			     device_t child, const char *name, void *buf,
 			     size_t *size, bhnd_nvram_type type);
 
-
-/**
- * bhnd per-device info.  Must be first member of all subclass
- * devinfo structures.
- */
-struct bhnd_devinfo {
-	struct bhnd_core_pmu_info *pmu_info;	/**< PMU info, or NULL */
-};
-
 /**
  * bhnd driver instance state. Must be first member of all subclass
  * softc structures.
diff --git a/sys/dev/bhnd/cores/chipc/chipc.c b/sys/dev/bhnd/cores/chipc/chipc.c
index b57ceb4d6779..b5fe97eb7971 100644
--- a/sys/dev/bhnd/cores/chipc/chipc.c
+++ b/sys/dev/bhnd/cores/chipc/chipc.c
@@ -1261,8 +1261,7 @@ chipc_disable_sprom_pins(struct chipc_softc *sc)
 		return;
 
 	CHIPC_LOCK_ASSERT(sc, MA_OWNED);
-	KASSERT(sc->sprom_refcnt != 0, ("sprom pins already disabled"));
-	KASSERT(sc->sprom_refcnt == 1, ("sprom pins in use"));
+	KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use"));
 
 	cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
 
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmu.c b/sys/dev/bhnd/cores/pmu/bhnd_pmu.c
index 0d24392f0da8..6d7e907da4cb 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmu.c
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmu.c
@@ -80,6 +80,10 @@ static const struct bhnd_pmu_io bhnd_pmu_res_io = {
 	.rd_chipst	= bhnd_pmu_read_chipst
 };
 
+#define	BPMU_ASSERT_CLKCTL_AVAIL(_pinfo)			\
+	KASSERT(!bhnd_is_hw_suspended((_pinfo)->pm_dev),	\
+	    ("reading clkctl on suspended core will trigger system livelock"))
+
 #define	BPMU_CLKCTL_READ_4(_pinfo)		\
 	bhnd_bus_read_4((_pinfo)->pm_res, (_pinfo)->pm_regs)
 
@@ -304,6 +308,8 @@ bhnd_pmu_core_req_clock(device_t dev, struct bhnd_core_pmu_info *pinfo,
 	uint32_t		 avail;
 	uint32_t		 req;
 
+	BPMU_ASSERT_CLKCTL_AVAIL(pinfo);
+
 	sc = device_get_softc(dev);
 
 	avail = 0x0;
@@ -351,6 +357,8 @@ bhnd_pmu_core_en_clocks(device_t dev, struct bhnd_core_pmu_info *pinfo,
 	uint32_t		 avail;
 	uint32_t		 req;
 
+	BPMU_ASSERT_CLKCTL_AVAIL(pinfo);
+
 	sc = device_get_softc(dev);
 
 	avail = 0x0;
@@ -404,6 +412,8 @@ bhnd_pmu_core_req_ext_rsrc(device_t dev, struct bhnd_core_pmu_info *pinfo,
 	uint32_t		 req;
 	uint32_t		 avail;
 
+	BPMU_ASSERT_CLKCTL_AVAIL(pinfo);
+
 	sc = device_get_softc(dev);
 
 	if (rsrc > BHND_CCS_ERSRC_MAX)
@@ -433,6 +443,8 @@ bhnd_pmu_core_release_ext_rsrc(device_t dev, struct bhnd_core_pmu_info *pinfo,
 	struct bhnd_pmu_softc	*sc;
 	uint32_t		 mask;
 
+	BPMU_ASSERT_CLKCTL_AVAIL(pinfo);
+
 	sc = device_get_softc(dev);
 
 	if (rsrc > BHND_CCS_ERSRC_MAX)
@@ -455,6 +467,11 @@ bhnd_pmu_core_release(device_t dev, struct bhnd_core_pmu_info *pinfo)
 
 	sc = device_get_softc(dev);
 
+	/* On PMU-equipped hardware, clkctl is cleared on RESET (and
+	 * attempting to access it will trigger a system livelock). */
+	if (bhnd_is_hw_suspended(pinfo->pm_dev))
+		return (0);
+
 	BPMU_LOCK(sc);
 
 	/* Clear all FORCE, AREQ, and ERSRC flags */
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmu.h b/sys/dev/bhnd/cores/pmu/bhnd_pmu.h
index 64f4c8e5c645..01c3ea127e67 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmu.h
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmu.h
@@ -34,6 +34,8 @@
 
 #include <sys/types.h>
 
+#include <dev/bhnd/bhnd.h>
+
 #include "bhnd_pmu_if.h"
 
 /**
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h b/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h
index 786c0b871937..e20f65fe7787 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmu_private.h
@@ -122,7 +122,7 @@ void		bhnd_pmu_spuravoid(struct bhnd_pmu_softc *sc,
 bool		bhnd_pmu_is_otp_powered(struct bhnd_pmu_softc *sc);
 uint32_t	bhnd_pmu_measure_alpclk(struct bhnd_pmu_softc *sc);
 
-void		bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc,
+int		bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc,
 		    device_t d11core, bool enable);
 
 uint32_t	bhnd_pmu_waitforclk_on_backplane(struct bhnd_pmu_softc *sc,
diff --git a/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c b/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
index bd10febff274..7744da60222e 100644
--- a/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
+++ b/sys/dev/bhnd/cores/pmu/bhnd_pmu_subr.c
@@ -3363,14 +3363,18 @@ bhnd_pmu_swreg_init(struct bhnd_pmu_softc *sc)
 	}
 }
 
-void
+int
 bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc, device_t d11core, bool enable)
 {
-	uint32_t oobsel;
-	uint32_t rsrcs;
+	uint32_t	oobsel;
+	uint32_t	rsrcs;
+	int		error;
 
-	if (bhnd_get_device(d11core) != BHND_COREID_D11)
-		panic("bhnd_pmu_radio_enable() called on non-D11 core");
+	if (bhnd_get_device(d11core) != BHND_COREID_D11) {
+		device_printf(sc->dev,
+		    "bhnd_pmu_radio_enable() called on non-D11 core");
+		return (EINVAL);
+	}
 
 	switch (sc->cid.chip_id) {
 	case BHND_CHIPID_BCM4325:
@@ -3389,9 +3393,13 @@ bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc, device_t d11core, bool enable)
 			BHND_PMU_AND_4(sc, BHND_PMU_MIN_RES_MASK, ~rsrcs);
 		}
 
-		break;
+		return (0);
+
 	case BHND_CHIPID_BCM4319:
-		oobsel = bhnd_read_config(d11core, BCMA_DMP_OOBSELOUTB74, 4);
+		error = bhnd_read_config(d11core, BCMA_DMP_OOBSELOUTB74,
+		    &oobsel, 4);
+		if (error)
+			return (error);
 
 		if (enable) {
 			oobsel |= BHND_PMU_SET_BITS(BCMA_DMP_OOBSEL_EN,
@@ -3405,9 +3413,11 @@ bhnd_pmu_radio_enable(struct bhnd_pmu_softc *sc, device_t d11core, bool enable)
 			    BCMA_DMP_OOBSEL_6);
 		}
 
-		bhnd_write_config(d11core, BCMA_DMP_OOBSELOUTB74, oobsel, 4);
-		break;
+		return (bhnd_write_config(d11core, BCMA_DMP_OOBSELOUTB74,
+		    &oobsel, 4));
 	}
+
+	return (0);
 }
 
 /* Wait for a particular clock level to be on the backplane */
diff --git a/sys/dev/bhnd/cores/usb/bhnd_usb.c b/sys/dev/bhnd/cores/usb/bhnd_usb.c
index 263c0cad9b5c..f753e5b0d6cd 100644
--- a/sys/dev/bhnd/cores/usb/bhnd_usb.c
+++ b/sys/dev/bhnd/cores/usb/bhnd_usb.c
@@ -44,7 +44,6 @@ __FBSDID("$FreeBSD$");
 #include <machine/resource.h>
 
 #include <dev/bhnd/bhnd.h>
-#include <dev/bhnd/bhnd_core.h>
 
 #include <dev/bhnd/cores/pmu/bhnd_pmureg.h>
 
@@ -103,7 +102,7 @@ bhnd_usb_attach(device_t dev)
 
 	sc = device_get_softc(dev);
 
-	BHND_BUS_RESET_CORE(device_get_parent(dev), dev, 0);
+	bhnd_reset_hw(dev, 0);
 
 	/*
 	 * Allocate the resources which the parent bus has already
diff --git a/sys/dev/bhnd/siba/siba.c b/sys/dev/bhnd/siba/siba.c
index 678940ba872e..7f85a1d8ec89 100644
--- a/sys/dev/bhnd/siba/siba.c
+++ b/sys/dev/bhnd/siba/siba.c
@@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/bus.h>
 
 #include <dev/bhnd/cores/chipc/chipcreg.h>
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
 
 #include "sibareg.h"
 #include "sibavar.h"
@@ -134,6 +135,9 @@ siba_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
 	case BHND_IVAR_CORE_UNIT:
 		*result = cfg->unit;
 		return (0);
+	case BHND_IVAR_PMU_INFO:
+		*result = (uintptr_t) dinfo->pmu_info;
+		return (0);
 	default:
 		return (ENOENT);
 	}
@@ -142,6 +146,10 @@ siba_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
 static int
 siba_write_ivar(device_t dev, device_t child, int index, uintptr_t value)
 {
+	struct siba_devinfo *dinfo;
+
+	dinfo = device_get_ivars(child);
+
 	switch (index) {
 	case BHND_IVAR_VENDOR:
 	case BHND_IVAR_DEVICE:
@@ -152,6 +160,9 @@ siba_write_ivar(device_t dev, device_t child, int index, uintptr_t value)
 	case BHND_IVAR_CORE_INDEX:
 	case BHND_IVAR_CORE_UNIT:
 		return (EINVAL);
+	case BHND_IVAR_PMU_INFO:
+		dinfo->pmu_info = (struct bhnd_core_pmu_info *) value;
+		return (0);
 	default:
 		return (ENOENT);
 	}
@@ -165,104 +176,320 @@ siba_get_resource_list(device_t dev, device_t child)
 }
 
 static int
-siba_reset_core(device_t dev, device_t child, uint16_t flags)
+siba_read_iost(device_t dev, device_t child, uint16_t *iost)
 {
-	struct siba_devinfo *dinfo;
+	uint32_t	tmhigh;
+	int		error;
+
+	error = bhnd_read_config(child, SIBA_CFG0_TMSTATEHIGH, &tmhigh, 4);
+	if (error)
+		return (error);
+
+	*iost = (SIBA_REG_GET(tmhigh, TMH_SISF));
+	return (0);
+}
+
+static int
+siba_read_ioctl(device_t dev, device_t child, uint16_t *ioctl)
+{
+	uint32_t	ts_low;
+	int		error;
+
+	if ((error = bhnd_read_config(child, SIBA_CFG0_TMSTATELOW, &ts_low, 4)))
+		return (error);
+
+	*ioctl = (SIBA_REG_GET(ts_low, TML_SICF));
+	return (0);
+}
+
+static int
+siba_write_ioctl(device_t dev, device_t child, uint16_t value, uint16_t mask)
+{
+	struct siba_devinfo	*dinfo;
+	struct bhnd_resource	*r;
+	uint32_t		 ts_low, ts_mask;
 
 	if (device_get_parent(child) != dev)
-		BHND_BUS_RESET_CORE(device_get_parent(dev), child, flags);
+		return (EINVAL);
 
+	/* Fetch CFG0 mapping */
 	dinfo = device_get_ivars(child);
+	if ((r = dinfo->cfg[0]) == NULL)
+		return (ENODEV);
 
-	/* Can't reset the core without access to the CFG0 registers */
-	if (dinfo->cfg[0] == NULL)
+	/* Mask and set TMSTATELOW core flag bits */
+	ts_mask = (mask << SIBA_TML_SICF_SHIFT) & SIBA_TML_SICF_MASK;
+	ts_low = (value << SIBA_TML_SICF_SHIFT) & ts_mask;
+
+	return (siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
+	    ts_low, ts_mask));
+}
+
+static bool
+siba_is_hw_suspended(device_t dev, device_t child)
+{
+	uint32_t		ts_low;
+	uint16_t		ioctl;
+	int			error;
+
+	/* Fetch target state */
+	error = bhnd_read_config(child, SIBA_CFG0_TMSTATELOW, &ts_low, 4);
+	if (error) {
+		device_printf(child, "error reading HW reset state: %d\n",
+		    error);
+		return (true);
+	}
+
+	/* Is core held in RESET? */
+	if (ts_low & SIBA_TML_RESET)
+		return (true);
+
+	/* Is core clocked? */
+	ioctl = SIBA_REG_GET(ts_low, TML_SICF);
+	if (!(ioctl & BHND_IOCTL_CLK_EN))
+		return (true);
+
+	return (false);
+}
+
+static int
+siba_reset_hw(device_t dev, device_t child, uint16_t ioctl)
+{
+	struct siba_devinfo		*dinfo;
+	struct bhnd_resource		*r;
+	uint32_t			 ts_low, imstate;
+	int				 error;
+
+	if (device_get_parent(child) != dev)
+		return (EINVAL);
+
+	dinfo = device_get_ivars(child);
+
+	/* Can't suspend the core without access to the CFG0 registers */
+	if ((r = dinfo->cfg[0]) == NULL)
 		return (ENODEV);
 
-	// TODO - perform reset
+	/* We require exclusive control over BHND_IOCTL_CLK_EN and
+	 * BHND_IOCTL_CLK_FORCE. */
+	if (ioctl & (BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE))
+		return (EINVAL);
 
-	return (ENXIO);
+	/* Place core into known RESET state */
+	if ((error = BHND_BUS_SUSPEND_HW(dev, child)))
+		return (error);
+
+	/* Leaving the core in reset, set the caller's IOCTL flags and
+	 * enable the core's clocks. */
+	ts_low = (ioctl | BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE) <<
+	    SIBA_TML_SICF_SHIFT;
+	error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
+	    ts_low, SIBA_TML_SICF_MASK);
+	if (error)
+		return (error);
+
+	/* Clear any target errors */
+	if (bhnd_bus_read_4(r, SIBA_CFG0_TMSTATEHIGH) & SIBA_TMH_SERR) {
+		error = siba_write_target_state(child, dinfo,
+		    SIBA_CFG0_TMSTATEHIGH, 0, SIBA_TMH_SERR);
+		if (error)
+			return (error);
+	}
+
+	/* Clear any initiator errors */
+	imstate = bhnd_bus_read_4(r, SIBA_CFG0_IMSTATE);
+	if (imstate & (SIBA_IM_IBE|SIBA_IM_TO)) {
+		error = siba_write_target_state(child, dinfo, SIBA_CFG0_IMSTATE,
+		    0, SIBA_IM_IBE|SIBA_IM_TO);
+		if (error)
+			return (error);
+	}
+
+	/* Release from RESET while leaving clocks forced, ensuring the
+	 * signal propagates throughout the core */
+	error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
+	    0x0, SIBA_TML_RESET);
+	if (error)
+		return (error);
+
+	/* The core should now be active; we can clear the BHND_IOCTL_CLK_FORCE
+	 * bit and allow the core to manage clock gating. */
+	error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
+	    0x0, (BHND_IOCTL_CLK_FORCE << SIBA_TML_SICF_SHIFT));
+	if (error)
+		return (error);
+
+	return (0);
 }
 
 static int
-siba_suspend_core(device_t dev, device_t child)
+siba_suspend_hw(device_t dev, device_t child)
 {
-	struct siba_devinfo *dinfo;
+	struct siba_devinfo		*dinfo;
+	struct bhnd_core_pmu_info	*pm;
+	struct bhnd_resource		*r;
+	uint32_t			 idl, ts_low;
+	uint16_t			 ioctl;
+	int				 error;
 
 	if (device_get_parent(child) != dev)
-		BHND_BUS_SUSPEND_CORE(device_get_parent(dev), child);
+		return (EINVAL);
 
 	dinfo = device_get_ivars(child);
+	pm = dinfo->pmu_info;
 
 	/* Can't suspend the core without access to the CFG0 registers */
-	if (dinfo->cfg[0] == NULL)
+	if ((r = dinfo->cfg[0]) == NULL)
 		return (ENODEV);
 
-	// TODO - perform suspend
+	/* Already in RESET? */
+	ts_low = bhnd_bus_read_4(r, SIBA_CFG0_TMSTATELOW);
+	if (ts_low & SIBA_TML_RESET) {
+		/* Clear IOCTL flags, ensuring the clock is disabled */
+		return (siba_write_target_state(child, dinfo,
+		    SIBA_CFG0_TMSTATELOW, 0x0, SIBA_TML_SICF_MASK));
+
+		return (0);
+	}
+
+	/* If clocks are already disabled, we can put the core directly
+	 * into RESET */
+	ioctl = SIBA_REG_GET(ts_low, TML_SICF);
+	if (!(ioctl & BHND_IOCTL_CLK_EN)) {
+		/* Set RESET and clear IOCTL flags */
+		return (siba_write_target_state(child, dinfo, 
+		    SIBA_CFG0_TMSTATELOW,
+		    SIBA_TML_RESET,
+		    SIBA_TML_RESET | SIBA_TML_SICF_MASK));
+	}
+
+	/* Reject any further target backplane transactions */
+	error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
+	    SIBA_TML_REJ, SIBA_TML_REJ);
+	if (error)
+		return (error);
+
+	/* If this is an initiator core, we need to reject initiator
+	 * transactions too. */
+	idl = bhnd_bus_read_4(r, SIBA_CFG0_IDLOW);
+	if (idl & SIBA_IDL_INIT) {
+		error = siba_write_target_state(child, dinfo, SIBA_CFG0_IMSTATE,
+		    SIBA_IM_RJ, SIBA_IM_RJ);
+		if (error)
+			return (error);
+	}
 
-	return (ENXIO);
+	/* Put the core into RESET|REJECT, forcing clocks to ensure the RESET
+	 * signal propagates throughout the core, leaving REJECT asserted. */
+	ts_low = SIBA_TML_RESET;
+	ts_low |= (BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE) <<
+	    SIBA_TML_SICF_SHIFT;
+
+	error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
+		ts_low, ts_low);
+	if (error)
+		return (error);
+
+	/* Give RESET ample time */
+	DELAY(10);
+
+	/* Leaving core in reset, disable all clocks, clear REJ flags and
+	 * IOCTL state */
+	error = siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
+		SIBA_TML_RESET,
+		SIBA_TML_RESET | SIBA_TML_REJ | SIBA_TML_SICF_MASK);
+	if (error)
+		return (error);
+
+	/* Clear previously asserted initiator reject */
+	if (idl & SIBA_IDL_INIT) {
+		error = siba_write_target_state(child, dinfo, SIBA_CFG0_IMSTATE,
+		    0, SIBA_IM_RJ);
+		if (error)
+			return (error);
+	}
+
+	/* Core is now in RESET, with clocks disabled and REJ not asserted.
+	 * 
+	 * We lastly need to inform the PMU, releasing any outstanding per-core
+	 * PMU requests */	
+	if (pm != NULL) {
+		if ((error = BHND_PMU_CORE_RELEASE(pm->pm_pmu, pm)))
+			return (error);
+	}
+
+	return (0);
 }
 
-static uint32_t
-siba_read_config(device_t dev, device_t child, bus_size_t offset, u_int width)
+static int
+siba_read_config(device_t dev, device_t child, bus_size_t offset, void *value,
+    u_int width)
 {
 	struct siba_devinfo	*dinfo;
 	rman_res_t		 r_size;
 
 	/* Must be directly attached */
 	if (device_get_parent(child) != dev)
-		return (UINT32_MAX);
+		return (EINVAL);
 
 	/* CFG0 registers must be available */
 	dinfo = device_get_ivars(child);
 	if (dinfo->cfg[0] == NULL)
-		return (UINT32_MAX);
+		return (ENODEV);
 
 	/* Offset must fall within CFG0 */
 	r_size = rman_get_size(dinfo->cfg[0]->res);
 	if (r_size < offset || r_size - offset < width)
-		return (UINT32_MAX);
+		return (EFAULT);
 
 	switch (width) {
 	case 1:
-		return (bhnd_bus_read_1(dinfo->cfg[0], offset));
+		*((uint8_t *)value) = bhnd_bus_read_1(dinfo->cfg[0], offset);
+		return (0);
 	case 2:
-		return (bhnd_bus_read_2(dinfo->cfg[0], offset));
+		*((uint16_t *)value) = bhnd_bus_read_2(dinfo->cfg[0], offset);
+		return (0);
 	case 4:
-		return (bhnd_bus_read_4(dinfo->cfg[0], offset));
+		*((uint32_t *)value) = bhnd_bus_read_4(dinfo->cfg[0], offset);
+		return (0);
+	default:
+		return (EINVAL);
 	}
-	
-	/* Unsuported */
-	return (UINT32_MAX);
 }
 
-static void
-siba_write_config(device_t dev, device_t child, bus_size_t offset, uint32_t val,
-    u_int width)
+static int
+siba_write_config(device_t dev, device_t child, bus_size_t offset,
+    const void *value, u_int width)
 {
 	struct siba_devinfo	*dinfo;
+	struct bhnd_resource	*r;
 	rman_res_t		 r_size;
 
 	/* Must be directly attached */
 	if (device_get_parent(child) != dev)
-		return;
+		return (EINVAL);
 
 	/* CFG0 registers must be available */
 	dinfo = device_get_ivars(child);
-	if (dinfo->cfg[0] == NULL)
-		return;
+	if ((r = dinfo->cfg[0]) == NULL)
+		return (ENODEV);
 
 	/* Offset must fall within CFG0 */
-	r_size = rman_get_size(dinfo->cfg[0]->res);
+	r_size = rman_get_size(r->res);
 	if (r_size < offset || r_size - offset < width)
-		return;
+		return (EFAULT);
 
 	switch (width) {
 	case 1:
-		bhnd_bus_write_1(dinfo->cfg[0], offset, val);
+		bhnd_bus_write_1(r, offset, *(const uint8_t *)value);
+		return (0);
 	case 2:
-		bhnd_bus_write_2(dinfo->cfg[0], offset, val);
+		bhnd_bus_write_2(r, offset, *(const uint8_t *)value);
+		return (0);
 	case 4:
-		bhnd_bus_write_4(dinfo->cfg[0], offset, val);
+		bhnd_bus_write_4(r, offset, *(const uint8_t *)value);
+		return (0);
+	default:
+		return (EINVAL);
 	}
 }
 
@@ -545,18 +772,42 @@ siba_map_cfg_resources(device_t dev, struct siba_devinfo *dinfo)
 	return (0);
 }
 
-
-static struct bhnd_devinfo *
-siba_alloc_bhnd_dinfo(device_t dev)
+static device_t
+siba_add_child(device_t dev, u_int order, const char *name, int unit)
 {
-	struct siba_devinfo *dinfo = siba_alloc_dinfo(dev);
-	return ((struct bhnd_devinfo *)dinfo);
+	struct siba_devinfo	*dinfo;
+	device_t		 child;
+
+	child = device_add_child_ordered(dev, order, name, unit);
+	if (child == NULL)
+		return (NULL);
+
+	if ((dinfo = siba_alloc_dinfo(dev)) == NULL) {
+		device_delete_child(dev, child);
+		return (NULL);
+	}
+
+	device_set_ivars(child, dinfo);
+
+	return (child);
 }
 
 static void
-siba_free_bhnd_dinfo(device_t dev, struct bhnd_devinfo *dinfo)
+siba_child_deleted(device_t dev, device_t child)
 {
-	siba_free_dinfo(dev, (struct siba_devinfo *)dinfo);
+	struct bhnd_softc	*sc;
+	struct siba_devinfo	*dinfo;
+
+	sc = device_get_softc(dev);
+
+	/* Call required bhnd(4) implementation */
+	bhnd_generic_child_deleted(dev, child);
+
+	/* Free siba device info */
+	if ((dinfo = device_get_ivars(child)) != NULL)
+		siba_free_dinfo(dev, dinfo);
+
+	device_set_ivars(child, NULL);
 }
 
 /**
@@ -687,16 +938,20 @@ static device_method_t siba_methods[] = {
 	DEVMETHOD(device_suspend,		siba_suspend),
 	
 	/* Bus interface */
+	DEVMETHOD(bus_add_child,		siba_add_child),
+	DEVMETHOD(bus_child_deleted,		siba_child_deleted),
 	DEVMETHOD(bus_read_ivar,		siba_read_ivar),
 	DEVMETHOD(bus_write_ivar,		siba_write_ivar),
 	DEVMETHOD(bus_get_resource_list,	siba_get_resource_list),
 
 	/* BHND interface */
 	DEVMETHOD(bhnd_bus_get_erom_class,	siba_get_erom_class),
-	DEVMETHOD(bhnd_bus_alloc_devinfo,	siba_alloc_bhnd_dinfo),
-	DEVMETHOD(bhnd_bus_free_devinfo,	siba_free_bhnd_dinfo),
-	DEVMETHOD(bhnd_bus_reset_core,		siba_reset_core),
-	DEVMETHOD(bhnd_bus_suspend_core,	siba_suspend_core),
+	DEVMETHOD(bhnd_bus_read_ioctl,		siba_read_ioctl),
+	DEVMETHOD(bhnd_bus_write_ioctl,		siba_write_ioctl),
+	DEVMETHOD(bhnd_bus_read_iost,		siba_read_iost),
+	DEVMETHOD(bhnd_bus_is_hw_suspended,	siba_is_hw_suspended),
+	DEVMETHOD(bhnd_bus_reset_hw,		siba_reset_hw),
+	DEVMETHOD(bhnd_bus_suspend_hw,		siba_suspend_hw),
 	DEVMETHOD(bhnd_bus_read_config,		siba_read_config),
 	DEVMETHOD(bhnd_bus_write_config,	siba_write_config),
 	DEVMETHOD(bhnd_bus_get_port_count,	siba_get_port_count),
diff --git a/sys/dev/bhnd/siba/siba_subr.c b/sys/dev/bhnd/siba/siba_subr.c
index 86a0bbf89607..52a5e019cc38 100644
--- a/sys/dev/bhnd/siba/siba_subr.c
+++ b/sys/dev/bhnd/siba/siba_subr.c
@@ -467,3 +467,85 @@ siba_parse_admatch(uint32_t am, uint32_t *addr, uint32_t *size)
 
 	return (0);
 }
+
+/**
+ * Write @p value to @p dev's CFG0 target/initiator state register and
+ * wait for completion.
+ * 
+ * @param dev The siba(4) child device.
+ * @param reg The state register to write (e.g. SIBA_CFG0_TMSTATELOW,
+ *    SIBA_CFG0_IMSTATE)
+ * @param value The value to write to @p reg.
+ * @param mask The mask of bits to be included from @p value.
+ * 
+ * @retval 0 success.
+ * @retval ENODEV if SIBA_CFG0 is not mapped by @p dinfo.
+ * @retval ETIMEDOUT if a timeout occurs prior to SIBA_TMH_BUSY clearing.
+ */
+int
+siba_write_target_state(device_t dev, struct siba_devinfo *dinfo,
+    bus_size_t reg, uint32_t value, uint32_t mask)
+{
+	struct bhnd_resource	*r;
+	uint32_t		 rval;
+
+	/* Must have a CFG0 block */
+	if ((r = dinfo->cfg[0]) == NULL)
+		return (ENODEV);
+
+	/* Verify the register offset falls within CFG register block */
+	if (reg > SIBA_CFG_SIZE-4)
+		return (EFAULT);
+
+	for (int i = 0; i < 300; i += 10) {
+		rval = bhnd_bus_read_4(r, reg);
+		rval &= ~mask;
+		rval |= (value & mask);
+
+		bhnd_bus_write_4(r, reg, rval);
+		bhnd_bus_read_4(r, reg); /* read-back */
+		DELAY(1);
+
+		/* If the write has completed, wait for target busy state
+		 * to clear */
+		rval = bhnd_bus_read_4(r, reg);
+		if ((rval & mask) == (value & mask))
+			return (siba_wait_target_busy(dev, dinfo, 100000));
+
+		DELAY(10);
+	}
+
+	return (ETIMEDOUT);
+}
+
+/**
+ * Spin for up to @p usec waiting for SIBA_TMH_BUSY to clear in
+ * @p dev's SIBA_CFG0_TMSTATEHIGH register.
+ * 
+ * @param dev The siba(4) child device to wait on.
+ * @param dinfo The @p dev's device info
+ * 
+ * @retval 0 if SIBA_TMH_BUSY is cleared prior to the @p usec timeout.
+ * @retval ENODEV if SIBA_CFG0 is not mapped by @p dinfo.
+ * @retval ETIMEDOUT if a timeout occurs prior to SIBA_TMH_BUSY clearing.
+ */
+int
+siba_wait_target_busy(device_t dev, struct siba_devinfo *dinfo, int usec)
+{
+	struct bhnd_resource	*r;
+	uint32_t		 ts_high;
+
+	if ((r = dinfo->cfg[0]) == NULL)
+		return (ENODEV);
+
+	for (int i = 0; i < usec; i += 10) {
+		ts_high = bhnd_bus_read_4(r, SIBA_CFG0_TMSTATEHIGH);
+		if (!(ts_high & SIBA_TMH_BUSY))
+			return (0);
+
+		DELAY(10);
+	}
+
+	device_printf(dev, "SIBA_TMH_BUSY wait timeout\n");
+	return (ETIMEDOUT);
+}
diff --git a/sys/dev/bhnd/siba/sibareg.h b/sys/dev/bhnd/siba/sibareg.h
index 63a6d5bf28ce..60771f982da2 100644
--- a/sys/dev/bhnd/siba/sibareg.h
+++ b/sys/dev/bhnd/siba/sibareg.h
@@ -146,16 +146,16 @@
 #define	SIBA_TML_REJ_MASK	0x0006		/* reject field */
 #define	SIBA_TML_REJ		0x0002		/* reject */
 #define	SIBA_TML_TMPREJ		0x0004		/* temporary reject, for error recovery */
-
-#define	SIBA_TML_SICF_SHIFT	16		/* Shift to locate the SI control flags in sbtml */
+#define	SIBA_TML_SICF_MASK	0xFFFF0000	/* core IOCTL flags */
+#define	SIBA_TML_SICF_SHIFT	16
 
 /* sbtmstatehigh */
 #define	SIBA_TMH_SERR		0x0001		/* serror */
 #define	SIBA_TMH_INT		0x0002		/* interrupt */
 #define	SIBA_TMH_BUSY		0x0004		/* busy */
 #define	SIBA_TMH_TO		0x0020		/* timeout (sonics >= 2.3) */
-
-#define	SIBA_TMH_SISF_SHIFT	16		/* Shift to locate the SI status flags in sbtmh */
+#define	SIBA_TMH_SISF_MASK	0xFFFF0000	/* core IOST flags */
+#define	SIBA_TMH_SISF_SHIFT	16
 
 /* sbbwa0 */
 #define	SIBA_BWA_TAB0_MASK	0xffff		/* lookup table 0 */
diff --git a/sys/dev/bhnd/siba/sibavar.h b/sys/dev/bhnd/siba/sibavar.h
index fc2f26f56847..27364660e8fb 100644
--- a/sys/dev/bhnd/siba/sibavar.h
+++ b/sys/dev/bhnd/siba/sibavar.h
@@ -95,6 +95,12 @@ u_int			 siba_admatch_offset(uint8_t addrspace);
 int			 siba_parse_admatch(uint32_t am, uint32_t *addr,
 			     uint32_t *size);
 
+int			 siba_write_target_state(device_t dev,
+			     struct siba_devinfo *dinfo, bus_size_t reg,
+			     uint32_t value, uint32_t mask);
+int			 siba_wait_target_busy(device_t child,
+			     struct siba_devinfo *dinfo, int usec);
+
 							     
 /* Sonics configuration register blocks */
 #define	SIBA_CFG_NUM_2_2	1			/**< sonics <= 2.2 maps SIBA_CFG0. */
@@ -147,14 +153,13 @@ struct siba_core_id {
  * siba(4) per-device info
  */
 struct siba_devinfo {
-	struct bhnd_devinfo	 bhnd_dinfo;	/**< superclass device info. */
-
-	struct resource_list	 resources;	/**< per-core memory regions. */
-	struct siba_core_id	 core_id;	/**< core identification info */
-	struct siba_addrspace	 addrspace[SIBA_MAX_ADDRSPACE];	/**< memory map descriptors */
+	struct resource_list		 resources;			/**< per-core memory regions. */
+	struct siba_core_id		 core_id;			/**< core identification info */
+	struct siba_addrspace		 addrspace[SIBA_MAX_ADDRSPACE];	/**< memory map descriptors */
 
-	struct bhnd_resource	*cfg[SIBA_MAX_CFG];     /**< SIBA_CFG_* registers */
-	int			 cfg_rid[SIBA_MAX_CFG]; /**< SIBA_CFG_* resource IDs */
+	struct bhnd_resource		*cfg[SIBA_MAX_CFG];		/**< SIBA_CFG_* registers */
+	int				 cfg_rid[SIBA_MAX_CFG];		/**< SIBA_CFG_* resource IDs */
+	struct bhnd_core_pmu_info	*pmu_info;			/**< Bus-managed PMU state, or NULL */
 };
 
 
diff --git a/sys/dev/bxe/bxe.c b/sys/dev/bxe/bxe.c
index a5c13ea600f3..ffbe2a822f85 100644
--- a/sys/dev/bxe/bxe.c
+++ b/sys/dev/bxe/bxe.c
@@ -27,7 +27,7 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
-#define BXE_DRIVER_VERSION "1.78.81"
+#define BXE_DRIVER_VERSION "1.78.89"
 
 #include "bxe.h"
 #include "ecore_sp.h"
@@ -489,7 +489,16 @@ static const struct {
     { STATS_OFFSET32(mbuf_alloc_tpa),
                 4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"},
     { STATS_OFFSET32(tx_queue_full_return),
-                4, STATS_FLAGS_FUNC, "tx_queue_full_return"}
+                4, STATS_FLAGS_FUNC, "tx_queue_full_return"},
+    { STATS_OFFSET32(bxe_tx_mq_start_lock_failures),
+                4, STATS_FLAGS_FUNC, "bxe_tx_mq_start_lock_failures"},
+    { STATS_OFFSET32(tx_request_link_down_failures),
+                4, STATS_FLAGS_FUNC, "tx_request_link_down_failures"},
+    { STATS_OFFSET32(bd_avail_too_less_failures),
+                4, STATS_FLAGS_FUNC, "bd_avail_too_less_failures"},
+    { STATS_OFFSET32(tx_mq_not_empty),
+                4, STATS_FLAGS_FUNC, "tx_mq_not_empty"}
+
 };
 
 static const struct {
@@ -602,7 +611,15 @@ static const struct {
     { Q_STATS_OFFSET32(mbuf_alloc_tpa),
                 4, "mbuf_alloc_tpa"},
     { Q_STATS_OFFSET32(tx_queue_full_return),
-                4, "tx_queue_full_return"}
+                4, "tx_queue_full_return"},
+    { Q_STATS_OFFSET32(bxe_tx_mq_start_lock_failures),
+                4, "bxe_tx_mq_start_lock_failures"},
+    { Q_STATS_OFFSET32(tx_request_link_down_failures),
+                4, "tx_request_link_down_failures"},
+    { Q_STATS_OFFSET32(bd_avail_too_less_failures),
+                4, "bd_avail_too_less_failures"},
+    { Q_STATS_OFFSET32(tx_mq_not_empty),
+                4, "tx_mq_not_empty"}
 };
 
 #define BXE_NUM_ETH_STATS   ARRAY_SIZE(bxe_eth_stats_arr)
@@ -5621,11 +5638,18 @@ bxe_tx_mq_start_locked(struct bxe_softc    *sc,
         return (EINVAL);
     }
 
+    if (m != NULL) {
+        rc = drbr_enqueue(ifp, tx_br, m);
+        if (rc != 0) {
+            fp->eth_q_stats.tx_soft_errors++;
+            goto bxe_tx_mq_start_locked_exit;
+        }
+    }
+
     if (!sc->link_vars.link_up ||
         (if_getdrvflags(ifp) &
         (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) {
-        if (m != NULL)
-            rc = drbr_enqueue(ifp, tx_br, m);
+        fp->eth_q_stats.tx_request_link_down_failures++;
         goto bxe_tx_mq_start_locked_exit;
     }
 
@@ -5635,24 +5659,22 @@ bxe_tx_mq_start_locked(struct bxe_softc    *sc,
         fp->eth_q_stats.tx_max_drbr_queue_depth = depth;
     }
 
-    if (m == NULL) {
-        /* no new work, check for pending frames */
-        next = drbr_dequeue_drv(ifp, tx_br);
-    } else if (drbr_needs_enqueue_drv(ifp, tx_br)) {
-        /* have both new and pending work, maintain packet order */
-        rc = drbr_enqueue(ifp, tx_br, m);
-        if (rc != 0) {
-            fp->eth_q_stats.tx_soft_errors++;
-            goto bxe_tx_mq_start_locked_exit;
-        }
-        next = drbr_dequeue_drv(ifp, tx_br);
-    } else {
-        /* new work only and nothing pending */
-        next = m;
-    }
-
     /* keep adding entries while there are frames to send */
-    while (next != NULL) {
+    while ((next = drbr_peek(ifp, tx_br)) != NULL) {
+        /* handle any completions if we're running low */
+        tx_bd_avail = bxe_tx_avail(sc, fp);
+        if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
+            /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
+            bxe_txeof(sc, fp);
+            tx_bd_avail = bxe_tx_avail(sc, fp);
+            if (tx_bd_avail < (BXE_TSO_MAX_SEGMENTS + 1)) {
+                fp->eth_q_stats.bd_avail_too_less_failures++;
+                m_freem(next);
+                drbr_advance(ifp, tx_br);
+                rc = ENOBUFS;
+                break;
+            }
+        }
 
         /* the mbuf now belongs to us */
         fp->eth_q_stats.mbuf_alloc_tx++;
@@ -5667,12 +5689,12 @@ bxe_tx_mq_start_locked(struct bxe_softc    *sc,
             fp->eth_q_stats.tx_encap_failures++;
             if (next != NULL) {
                 /* mark the TX queue as full and save the frame */
-                if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
-                /* XXX this may reorder the frame */
-                rc = drbr_enqueue(ifp, tx_br, next);
+                ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+                drbr_putback(ifp, tx_br, next);
                 fp->eth_q_stats.mbuf_alloc_tx--;
                 fp->eth_q_stats.tx_frames_deferred++;
-            }
+            } else
+                drbr_advance(ifp, tx_br);
 
             /* stop looking for more work */
             break;
@@ -5682,20 +5704,9 @@ bxe_tx_mq_start_locked(struct bxe_softc    *sc,
         tx_count++;
 
         /* send a copy of the frame to any BPF listeners */
-	if_etherbpfmtap(ifp, next);
-
-        tx_bd_avail = bxe_tx_avail(sc, fp);
+        BPF_MTAP(ifp, next);
 
-        /* handle any completions if we're running low */
-        if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
-            /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
-            bxe_txeof(sc, fp);
-            if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) {
-                break;
-            }
-        }
-
-        next = drbr_dequeue_drv(ifp, tx_br);
+        drbr_advance(ifp, tx_br);
     }
 
     /* all TX packets were dequeued and/or the tx ring is full */
@@ -5705,10 +5716,32 @@ bxe_tx_mq_start_locked(struct bxe_softc    *sc,
     }
 
 bxe_tx_mq_start_locked_exit:
+    /* If we didn't drain the drbr, enqueue a task in the future to do it. */
+    if (!drbr_empty(ifp, tx_br)) {
+        fp->eth_q_stats.tx_mq_not_empty++;
+        taskqueue_enqueue_timeout(fp->tq, &fp->tx_timeout_task, 1);
+    }
 
     return (rc);
 }
 
+static void
+bxe_tx_mq_start_deferred(void *arg,
+                         int pending)
+{
+    struct bxe_fastpath *fp = (struct bxe_fastpath *)arg;
+    struct bxe_softc *sc = fp->sc;
+#if __FreeBSD_version >= 800000
+    if_t ifp = sc->ifp;
+#else
+    struct ifnet *ifp = sc->ifnet;
+#endif /* #if __FreeBSD_version >= 800000 */
+
+    BXE_FP_TX_LOCK(fp);
+    bxe_tx_mq_start_locked(sc, ifp, fp, NULL);
+    BXE_FP_TX_UNLOCK(fp);
+}
+
 /* Multiqueue (TSS) dispatch routine. */
 static int
 bxe_tx_mq_start(struct ifnet *ifp,
@@ -5730,8 +5763,10 @@ bxe_tx_mq_start(struct ifnet *ifp,
     if (BXE_FP_TX_TRYLOCK(fp)) {
         rc = bxe_tx_mq_start_locked(sc, ifp, fp, m);
         BXE_FP_TX_UNLOCK(fp);
-    } else
+    } else {
         rc = drbr_enqueue(ifp, fp->tx_br, m);
+        taskqueue_enqueue(fp->tq, &fp->tx_task);
+    }
 
     return (rc);
 }
@@ -6953,6 +6988,8 @@ bxe_link_attn(struct bxe_softc *sc)
     uint32_t pause_enabled = 0;
     struct host_port_stats *pstats;
     int cmng_fns;
+    struct bxe_fastpath *fp;
+    int i;
 
     /* Make sure that we are synced with the current statistics */
     bxe_stats_handle(sc, STATS_EVENT_STOP);
@@ -6984,6 +7021,12 @@ bxe_link_attn(struct bxe_softc *sc)
         if (sc->state == BXE_STATE_OPEN) {
             bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
         }
+
+        /* Restart tx when the link comes back. */
+        FOR_EACH_ETH_QUEUE(sc, i) {
+            fp = &sc->fp[i];
+            taskqueue_enqueue(fp->tq, &fp->tx_task);
+        }
     }
 
     if (sc->link_vars.link_up && sc->link_vars.line_speed) {
@@ -8593,11 +8636,6 @@ bxe_handle_fp_tq(void *context,
      * we need to add a "process/continue" flag here that the driver
      * can use to tell the task here not to do anything.
      */
-#if 0
-    if (!(if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING)) {
-        return;
-    }
-#endif
 
     /* update the fastpath index */
     bxe_update_fp_sb_idx(fp);
@@ -9035,6 +9073,10 @@ bxe_interrupt_detach(struct bxe_softc *sc)
         fp = &sc->fp[i];
         if (fp->tq) {
             taskqueue_drain(fp->tq, &fp->tq_task);
+            taskqueue_drain(fp->tq, &fp->tx_task);
+            while (taskqueue_cancel_timeout(fp->tq, &fp->tx_timeout_task,
+                NULL))
+                taskqueue_drain_timeout(fp->tq, &fp->tx_timeout_task);
             taskqueue_free(fp->tq);
             fp->tq = NULL;
         }
@@ -9079,9 +9121,12 @@ bxe_interrupt_attach(struct bxe_softc *sc)
         snprintf(fp->tq_name, sizeof(fp->tq_name),
                  "bxe%d_fp%d_tq", sc->unit, i);
         TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp);
+        TASK_INIT(&fp->tx_task, 0, bxe_tx_mq_start_deferred, fp);
         fp->tq = taskqueue_create_fast(fp->tq_name, M_NOWAIT,
                                        taskqueue_thread_enqueue,
                                        &fp->tq);
+        TIMEOUT_TASK_INIT(fp->tq, &fp->tx_timeout_task, 0,
+            bxe_tx_mq_start_deferred, fp);
         taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */
                                 "%s", fp->tq_name);
     }
@@ -12114,9 +12159,12 @@ static void
 bxe_periodic_callout_func(void *xsc)
 {
     struct bxe_softc *sc = (struct bxe_softc *)xsc;
+    int i;
+
+#if __FreeBSD_version < 800000
     struct bxe_fastpath *fp;
     uint16_t tx_bd_avail;
-    int i;
+#endif
 
     if (!BXE_CORE_TRYLOCK(sc)) {
         /* just bail and try again next time */
@@ -12138,28 +12186,7 @@ bxe_periodic_callout_func(void *xsc)
         return;
     }
 
-#if __FreeBSD_version >= 800000
-
-    FOR_EACH_QUEUE(sc, i) {
-        fp = &sc->fp[i];
-
-        if (BXE_FP_TX_TRYLOCK(fp)) {
-            if_t ifp = sc->ifp;
-            /*
-             * If interface was stopped due to unavailable
-             * bds, try to process some tx completions
-             */
-            (void) bxe_txeof(sc, fp);
-           
-            tx_bd_avail = bxe_tx_avail(sc, fp);
-            if (tx_bd_avail >= BXE_TX_CLEANUP_THRESHOLD) {
-                bxe_tx_mq_start_locked(sc, ifp, fp, NULL);
-            }
-            BXE_FP_TX_UNLOCK(fp);
-        }
-    }
-
-#else
+#if __FreeBSD_version < 800000
 
     fp = &sc->fp[0];
     if (BXE_FP_TX_TRYLOCK(fp)) {
@@ -12177,7 +12204,7 @@ bxe_periodic_callout_func(void *xsc)
  
         BXE_FP_TX_UNLOCK(fp);
     }
-
+    
 #endif /* #if __FreeBSD_version >= 800000 */
 
     /* Check for TX timeouts on any fastpath. */
diff --git a/sys/dev/bxe/bxe.h b/sys/dev/bxe/bxe.h
index 40c9a36d93e7..42cdf9550ef1 100644
--- a/sys/dev/bxe/bxe.h
+++ b/sys/dev/bxe/bxe.h
@@ -644,6 +644,9 @@ struct bxe_fastpath {
     struct taskqueue *tq;
     char             tq_name[32];
 
+    struct task tx_task;
+    struct timeout_task tx_timeout_task;
+
     /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
     uint8_t cl_id;
 #define FP_CL_ID(fp) (fp->cl_id)
@@ -2300,7 +2303,7 @@ void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag,
 extern int bxe_grc_dump(struct bxe_softc *sc);
 
 #if __FreeBSD_version >= 800000
-#if __FreeBSD_version >= 1000000
+#if (__FreeBSD_version >= 1001513 && __FreeBSD_version < 1100000) || __FreeBSD_version >= 1100048
 #define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE)
 #define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
 #else
diff --git a/sys/dev/bxe/bxe_stats.h b/sys/dev/bxe/bxe_stats.h
index a0f5792f9248..e86741dd4b47 100644
--- a/sys/dev/bxe/bxe_stats.h
+++ b/sys/dev/bxe/bxe_stats.h
@@ -266,6 +266,12 @@ struct bxe_eth_stats {
 
     /* num. of times tx queue full occurred */
     uint32_t tx_queue_full_return;
+
+    /* debug stats */
+    uint32_t bxe_tx_mq_start_lock_failures;
+    uint32_t tx_request_link_down_failures;
+    uint32_t bd_avail_too_less_failures;
+    uint32_t tx_mq_not_empty;
 };
 
 
@@ -372,6 +378,12 @@ struct bxe_eth_q_stats {
 
     /* num. of times tx queue full occurred */
     uint32_t tx_queue_full_return;
+
+    /* debug stats */
+    uint32_t bxe_tx_mq_start_lock_failures;
+    uint32_t tx_request_link_down_failures;
+    uint32_t bd_avail_too_less_failures;
+    uint32_t tx_mq_not_empty;
 };
 
 struct bxe_eth_stats_old {
diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h
index b8ca1eb53bf3..1666bc781ddf 100644
--- a/sys/dev/cxgbe/adapter.h
+++ b/sys/dev/cxgbe/adapter.h
@@ -231,6 +231,7 @@ struct vi_info {
 	int if_flags;
 
 	uint16_t *rss, *nm_rss;
+	int smt_idx;		/* for convenience */
 	uint16_t viid;
 	int16_t  xact_addr_filt;/* index of exact MAC address filter */
 	uint16_t rss_size;	/* size of VI's RSS table slice */
diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index 976c9bbb5f7c..553993a66f2b 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -8100,6 +8100,10 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
 		return ret;
 
 	p->vi[0].viid = ret;
+	if (chip_id(adap) <= CHELSIO_T5)
+		p->vi[0].smt_idx = (ret & 0x7f) << 1;
+	else
+		p->vi[0].smt_idx = (ret & 0x7f);
 	p->tx_chan = j;
 	p->rx_chan_map = t4_get_mps_bg_map(adap, j);
 	p->lport = j;
diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c
index f2635076e2f6..e5f8dcdc20ae 100644
--- a/sys/dev/cxgbe/t4_main.c
+++ b/sys/dev/cxgbe/t4_main.c
@@ -812,15 +812,6 @@ t4_attach(device_t dev)
 	if (rc != 0)
 		goto done; /* error message displayed already */
 
-	/*
-	 * This is the real PF# to which we're attaching.  Works from within PCI
-	 * passthrough environments too, where pci_get_function() could return a
-	 * different PF# depending on the passthrough configuration.  We need to
-	 * use the real PF# in all our communication with the firmware.
-	 */
-	sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
-	sc->mbox = sc->pf;
-
 	memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
 
 	/* Prepare the adapter for operation. */
@@ -832,6 +823,16 @@ t4_attach(device_t dev)
 		goto done;
 	}
 
+	/*
+	 * This is the real PF# to which we're attaching.  Works from within PCI
+	 * passthrough environments too, where pci_get_function() could return a
+	 * different PF# depending on the passthrough configuration.  We need to
+	 * use the real PF# in all our communication with the firmware.
+	 */
+	j = t4_read_reg(sc, A_PL_WHOAMI);
+	sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
+	sc->mbox = sc->pf;
+
 	t4_init_devnames(sc);
 	if (sc->names == NULL) {
 		rc = ENOTSUP;
@@ -969,7 +970,7 @@ t4_attach(device_t dev)
 		pi->tc = malloc(sizeof(struct tx_sched_class) *
 		    sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
 
-		if (is_10G_port(pi) || is_40G_port(pi)) {
+		if (port_top_speed(pi) >= 10) {
 			n10g++;
 		} else {
 			n1g++;
@@ -1085,7 +1086,7 @@ t4_attach(device_t dev)
 
 			vi->first_rxq = rqidx;
 			vi->first_txq = tqidx;
-			if (is_10G_port(pi) || is_40G_port(pi)) {
+			if (port_top_speed(pi) >= 10) {
 				vi->tmr_idx = t4_tmr_idx_10g;
 				vi->pktc_idx = t4_pktc_idx_10g;
 				vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
@@ -1109,7 +1110,7 @@ t4_attach(device_t dev)
 #ifdef TCP_OFFLOAD
 			vi->first_ofld_rxq = ofld_rqidx;
 			vi->first_ofld_txq = ofld_tqidx;
-			if (is_10G_port(pi) || is_40G_port(pi)) {
+			if (port_top_speed(pi) >= 10) {
 				vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
 				vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
 				    iaq.nofldrxq_vi;
@@ -1736,6 +1737,7 @@ fail:
 
 	case SIOCSIFMEDIA:
 	case SIOCGIFMEDIA:
+	case SIOCGIFXMEDIA:
 		ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
 		break;
 
@@ -2030,6 +2032,10 @@ vcxgbe_attach(device_t dev)
 		return (-rc);
 	}
 	vi->viid = rc;
+	if (chip_id(sc) <= CHELSIO_T5)
+		vi->smt_idx = (rc & 0x7f) << 1;
+	else
+		vi->smt_idx = (rc & 0x7f);
 
 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
@@ -5089,7 +5095,7 @@ t4_sysctls(struct adapter *sc)
 	    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
 	    sysctl_ulprx_la, "A", "ULPRX logic analyzer");
 
-	if (is_t5(sc)) {
+	if (chip_id(sc) >= CHELSIO_T5) {
 		SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
 		    CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
 		    sysctl_wcwr_stats, "A", "write combined work requests");
@@ -7232,7 +7238,12 @@ sysctl_tids(SYSCTL_HANDLER_ARGS)
 
 	if (t->ntids) {
 		if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
-			uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
+			uint32_t b;
+
+			if (chip_id(sc) <= CHELSIO_T5)
+				b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
+			else
+				b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
 
 			if (b) {
 				sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
diff --git a/sys/dev/cxgbe/t4_netmap.c b/sys/dev/cxgbe/t4_netmap.c
index 2e0325755b80..a1722ee7dd70 100644
--- a/sys/dev/cxgbe/t4_netmap.c
+++ b/sys/dev/cxgbe/t4_netmap.c
@@ -178,7 +178,7 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
 	nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
 	    sc->chip_params->sge_fl_db;
 
-	if (is_t5(sc) && cong >= 0) {
+	if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) {
 		uint32_t param, val;
 
 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
@@ -883,19 +883,23 @@ cxgbe_nm_detach(struct vi_info *vi)
 	netmap_detach(vi->ifp);
 }
 
+static inline const void *
+unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl)
+{
+
+	MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL);
+
+	/* data[0] is RSS header */
+	return (&cpl->data[1]);
+}
+
 static void
-handle_nm_fw6_msg(struct adapter *sc, struct ifnet *ifp,
-    const struct cpl_fw6_msg *cpl)
+handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp,
+    const struct cpl_sge_egr_update *egr)
 {
-	const struct cpl_sge_egr_update *egr;
 	uint32_t oq;
 	struct sge_nm_txq *nm_txq;
 
-	if (cpl->type != FW_TYPE_RSSCPL && cpl->type != FW6_TYPE_RSSCPL)
-		panic("%s: FW_TYPE 0x%x on nm_rxq.", __func__, cpl->type);
-
-	/* data[0] is RSS header */
-	egr = (const void *)&cpl->data[1];
 	oq = be32toh(egr->opcode_qid);
 	MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
 	nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
@@ -914,6 +918,7 @@ t4_nm_intr(void *arg)
 	struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid];
 	struct netmap_ring *ring = kring->ring;
 	struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
+	const void *cpl;
 	uint32_t lq;
 	u_int n = 0, work = 0;
 	uint8_t opcode;
@@ -926,6 +931,7 @@ t4_nm_intr(void *arg)
 
 		lq = be32toh(d->rsp.pldbuflen_qid);
 		opcode = d->rss.opcode;
+		cpl = &d->cpl[0];
 
 		switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
 		case X_RSPD_TYPE_FLBUF:
@@ -942,8 +948,10 @@ t4_nm_intr(void *arg)
 			switch (opcode) {
 			case CPL_FW4_MSG:
 			case CPL_FW6_MSG:
-				handle_nm_fw6_msg(sc, ifp,
-				    (const void *)&d->cpl[0]);
+				cpl = unwrap_nm_fw6_msg(cpl);
+				/* fall through */
+			case CPL_SGE_EGR_UPDATE:
+				handle_nm_sge_egr_update(sc, ifp, cpl);
 				break;
 			case CPL_RX_PKT:
 				ring->slot[fl_cidx].len = G_RSPD_LEN(lq) -
diff --git a/sys/dev/cxgbe/t4_sge.c b/sys/dev/cxgbe/t4_sge.c
index 7d37ca48c533..3748b2bc80f7 100644
--- a/sys/dev/cxgbe/t4_sge.c
+++ b/sys/dev/cxgbe/t4_sge.c
@@ -177,8 +177,8 @@ static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
     int, int);
 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
-static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
-    struct sge_fl *);
+static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
+    struct sysctl_oid *, struct sge_fl *);
 static int alloc_fwq(struct adapter *);
 static int free_fwq(struct adapter *);
 static int alloc_mgmtq(struct adapter *);
@@ -1902,6 +1902,7 @@ drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
 			}
 			eq->pidx = n - (eq->sidx - eq->pidx);
 		}
+		wrq->tx_wrs_copied++;
 
 		if (available < eq->sidx / 4 &&
 		    atomic_cmpset_int(&eq->equiq, 0, 1)) {
@@ -2799,7 +2800,7 @@ alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
 		FL_UNLOCK(fl);
 	}
 
-	if (is_t5(sc) && !(sc->flags & IS_VF) && cong >= 0) {
+	if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
 		uint32_t param, val;
 
 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
@@ -2877,8 +2878,8 @@ free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
 }
 
 static void
-add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
-    struct sge_fl *fl)
+add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
+    struct sysctl_oid *oid, struct sge_fl *fl)
 {
 	struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
 
@@ -2886,6 +2887,11 @@ add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
 	    "freelist");
 	children = SYSCTL_CHILDREN(oid);
 
+	SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
+	    &fl->ba, "bus address of descriptor ring");
+	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
+	    fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
+	    "desc ring size in bytes");
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
 	    CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
 	    "SGE context id of the freelist");
@@ -2941,6 +2947,10 @@ alloc_fwq(struct adapter *sc)
 	    NULL, "firmware event queue");
 	children = SYSCTL_CHILDREN(oid);
 
+	SYSCTL_ADD_UAUTO(&sc->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
+	    &fwq->ba, "bus address of descriptor ring");
+	SYSCTL_ADD_INT(&sc->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
+	    fwq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
 	SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
 	    CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
 	    "absolute id of the queue");
@@ -3052,6 +3062,10 @@ alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
 	    NULL, "rx queue");
 	children = SYSCTL_CHILDREN(oid);
 
+	SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
+	    &rxq->iq.ba, "bus address of descriptor ring");
+	SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
+	    rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
 	SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
 	    CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
 	    "absolute id of the queue");
@@ -3073,7 +3087,7 @@ alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
 	    CTLFLAG_RD, &rxq->vlan_extraction,
 	    "# of times hardware extracted 802.1Q tag");
 
-	add_fl_sysctls(&vi->ctx, oid, &rxq->fl);
+	add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
 
 	return (rc);
 }
@@ -3102,12 +3116,13 @@ static int
 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
     int intr_idx, int idx, struct sysctl_oid *oid)
 {
+	struct port_info *pi = vi->pi;
 	int rc;
 	struct sysctl_oid_list *children;
 	char name[16];
 
 	rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
-	    vi->pi->rx_chan_map);
+	    pi->rx_chan_map);
 	if (rc != 0)
 		return (rc);
 
@@ -3118,6 +3133,10 @@ alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
 	    NULL, "rx queue");
 	children = SYSCTL_CHILDREN(oid);
 
+	SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
+	    &ofld_rxq->iq.ba, "bus address of descriptor ring");
+	SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
+	    ofld_rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
 	SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
 	    CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
 	    "I", "absolute id of the queue");
@@ -3128,7 +3147,7 @@ alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
 	    CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
 	    "consumer index");
 
-	add_fl_sysctls(&vi->ctx, oid, &ofld_rxq->fl);
+	add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
 
 	return (rc);
 }
@@ -3549,6 +3568,11 @@ alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
 	wrq->nwr_pending = 0;
 	wrq->ndesc_needed = 0;
 
+	SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
+	    &wrq->eq.ba, "bus address of descriptor ring");
+	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
+	    wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
+	    "desc ring size in bytes");
 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
 	    &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
@@ -3557,10 +3581,14 @@ alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
 	    CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
 	    "producer index");
+	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
+	    wrq->eq.sidx, "status page index");
 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
 	    &wrq->tx_wrs_direct, "# of work requests (direct)");
 	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
 	    &wrq->tx_wrs_copied, "# of work requests (copied)");
+	SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
+	    &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
 
 	return (rc);
 }
@@ -3634,6 +3662,11 @@ alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
 	    NULL, "tx queue");
 	children = SYSCTL_CHILDREN(oid);
 
+	SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
+	    &eq->ba, "bus address of descriptor ring");
+	SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
+	    eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
+	    "desc ring size in bytes");
 	SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
 	    &eq->abs_id, 0, "absolute id of the queue");
 	SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
@@ -3644,6 +3677,8 @@ alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
 	SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
 	    CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
 	    "producer index");
+	SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
+	    eq->sidx, "status page index");
 
 	SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
 	    CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
diff --git a/sys/dev/cxgbe/t4_tracer.c b/sys/dev/cxgbe/t4_tracer.c
index 9e0009e15151..59096bc31ec0 100644
--- a/sys/dev/cxgbe/t4_tracer.c
+++ b/sys/dev/cxgbe/t4_tracer.c
@@ -472,6 +472,7 @@ tracer_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
 		break;
 	case SIOCSIFMEDIA:
 	case SIOCGIFMEDIA:
+	case SIOCGIFXMEDIA:
 		sx_xlock(&t4_trace_lock);
 		sc = ifp->if_softc;
 		if (sc == NULL)
diff --git a/sys/dev/cxgbe/t4_vf.c b/sys/dev/cxgbe/t4_vf.c
index b74686001cc7..bd88a4f4939d 100644
--- a/sys/dev/cxgbe/t4_vf.c
+++ b/sys/dev/cxgbe/t4_vf.c
@@ -662,7 +662,7 @@ t4vf_attach(device_t dev)
 		pi->tc = malloc(sizeof(struct tx_sched_class) *
 		    sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
 
-		if (is_10G_port(pi) || is_40G_port(pi)) {
+		if (port_top_speed(pi) >= 10) {
 			n10g++;
 		} else {
 			n1g++;
@@ -729,7 +729,7 @@ t4vf_attach(device_t dev)
 
 			vi->first_rxq = rqidx;
 			vi->first_txq = tqidx;
-			if (is_10G_port(pi) || is_40G_port(pi)) {
+			if (port_top_speed(pi) >= 10) {
 				vi->tmr_idx = t4_tmr_idx_10g;
 				vi->pktc_idx = t4_pktc_idx_10g;
 				vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
diff --git a/sys/dev/cxgbe/tom/t4_connect.c b/sys/dev/cxgbe/tom/t4_connect.c
index 9eb63551fb20..7ad1fb6fcea6 100644
--- a/sys/dev/cxgbe/tom/t4_connect.c
+++ b/sys/dev/cxgbe/tom/t4_connect.c
@@ -277,19 +277,26 @@ t4_init_connect_cpl_handlers(void)
 static inline int
 act_open_cpl_size(struct adapter *sc, int isipv6)
 {
-	static const int sz_t4[] = {
-		sizeof (struct cpl_act_open_req),
-		sizeof (struct cpl_act_open_req6)
-	};
-	static const int sz_t5[] = {
-		sizeof (struct cpl_t5_act_open_req),
-		sizeof (struct cpl_t5_act_open_req6)
+	int idx;
+	static const int sz_table[3][2] = {
+		{
+			sizeof (struct cpl_act_open_req),
+			sizeof (struct cpl_act_open_req6)
+		},
+		{
+			sizeof (struct cpl_t5_act_open_req),
+			sizeof (struct cpl_t5_act_open_req6)
+		},
+		{
+			sizeof (struct cpl_t6_act_open_req),
+			sizeof (struct cpl_t6_act_open_req6)
+		},
 	};
 
-	if (is_t4(sc))
-		return (sz_t4[!!isipv6]);
-	else
-		return (sz_t5[!!isipv6]);
+	MPASS(chip_id(sc) >= CHELSIO_T4);
+	idx = min(chip_id(sc) - CHELSIO_T4, 2);
+
+	return (sz_table[idx][!!isipv6]);
 }
 
 /*
@@ -373,28 +380,32 @@ t4_connect(struct toedev *tod, struct socket *so, struct rtentry *rt,
 
 	if (isipv6) {
 		struct cpl_act_open_req6 *cpl = wrtod(wr);
+		struct cpl_t5_act_open_req6 *cpl5 = (void *)cpl;
+		struct cpl_t6_act_open_req6 *cpl6 = (void *)cpl;
 
-		if ((inp->inp_vflag & INP_IPV6) == 0) {
-			/* XXX think about this a bit more */
-			log(LOG_ERR,
-			    "%s: time to think about AF_INET6 + vflag 0x%x.\n",
-			    __func__, inp->inp_vflag);
+		if ((inp->inp_vflag & INP_IPV6) == 0)
 			DONT_OFFLOAD_ACTIVE_OPEN(ENOTSUP);
-		}
 
 		toep->ce = hold_lip(td, &inp->in6p_laddr);
 		if (toep->ce == NULL)
 			DONT_OFFLOAD_ACTIVE_OPEN(ENOENT);
 
-		if (is_t4(sc)) {
+		switch (chip_id(sc)) {
+		case CHELSIO_T4:
 			INIT_TP_WR(cpl, 0);
 			cpl->params = select_ntuple(vi, toep->l2te);
-		} else {
-			struct cpl_t5_act_open_req6 *c5 = (void *)cpl;
-
-			INIT_TP_WR(c5, 0);
-			c5->iss = htobe32(tp->iss);
-			c5->params = select_ntuple(vi, toep->l2te);
+			break;
+		case CHELSIO_T5:
+			INIT_TP_WR(cpl5, 0);
+			cpl5->iss = htobe32(tp->iss);
+			cpl5->params = select_ntuple(vi, toep->l2te);
+			break;
+		case CHELSIO_T6:
+		default:
+			INIT_TP_WR(cpl6, 0);
+			cpl6->iss = htobe32(tp->iss);
+			cpl6->params = select_ntuple(vi, toep->l2te);
+			break;
 		}
 		OPCODE_TID(cpl) = htobe32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
 		    qid_atid));
@@ -409,16 +420,25 @@ t4_connect(struct toedev *tod, struct socket *so, struct rtentry *rt,
 		cpl->opt2 = calc_opt2a(so, toep);
 	} else {
 		struct cpl_act_open_req *cpl = wrtod(wr);
+		struct cpl_t5_act_open_req *cpl5 = (void *)cpl;
+		struct cpl_t6_act_open_req *cpl6 = (void *)cpl;
 
-		if (is_t4(sc)) {
+		switch (chip_id(sc)) {
+		case CHELSIO_T4:
 			INIT_TP_WR(cpl, 0);
 			cpl->params = select_ntuple(vi, toep->l2te);
-		} else {
-			struct cpl_t5_act_open_req *c5 = (void *)cpl;
-
-			INIT_TP_WR(c5, 0);
-			c5->iss = htobe32(tp->iss);
-			c5->params = select_ntuple(vi, toep->l2te);
+			break;
+		case CHELSIO_T5:
+			INIT_TP_WR(cpl5, 0);
+			cpl5->iss = htobe32(tp->iss);
+			cpl5->params = select_ntuple(vi, toep->l2te);
+			break;
+		case CHELSIO_T6:
+		default:
+			INIT_TP_WR(cpl6, 0);
+			cpl6->iss = htobe32(tp->iss);
+			cpl6->params = select_ntuple(vi, toep->l2te);
+			break;
 		}
 		OPCODE_TID(cpl) = htobe32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
 		    qid_atid));
diff --git a/sys/dev/cxgbe/tom/t4_listen.c b/sys/dev/cxgbe/tom/t4_listen.c
index f126ca4b224d..472c9a5a9e4b 100644
--- a/sys/dev/cxgbe/tom/t4_listen.c
+++ b/sys/dev/cxgbe/tom/t4_listen.c
@@ -694,7 +694,7 @@ t4_syncache_respond(struct toedev *tod, void *arg, struct mbuf *m)
 	synqe->iss = be32toh(th->th_seq);
 	synqe->ts = to.to_tsval;
 
-	if (is_t5(sc)) {
+	if (chip_id(sc) >= CHELSIO_T5) {
 		struct cpl_t5_pass_accept_rpl *rpl5 = wrtod(wr);
 
 		rpl5->iss = th->th_seq;
@@ -1053,8 +1053,8 @@ calc_opt2p(struct adapter *sc, struct port_info *pi, int rxqid,
 }
 
 static void
-pass_accept_req_to_protohdrs(const struct mbuf *m, struct in_conninfo *inc,
-    struct tcphdr *th)
+pass_accept_req_to_protohdrs(struct adapter *sc, const struct mbuf *m,
+    struct in_conninfo *inc, struct tcphdr *th)
 {
 	const struct cpl_pass_accept_req *cpl = mtod(m, const void *);
 	const struct ether_header *eh;
@@ -1063,8 +1063,13 @@ pass_accept_req_to_protohdrs(const struct mbuf *m, struct in_conninfo *inc,
 	const struct tcphdr *tcp;
 
 	eh = (const void *)(cpl + 1);
-	l3hdr = ((uintptr_t)eh + G_ETH_HDR_LEN(hlen));
-	tcp = (const void *)(l3hdr + G_IP_HDR_LEN(hlen));
+	if (chip_id(sc) >= CHELSIO_T6) {
+		l3hdr = ((uintptr_t)eh + G_T6_ETH_HDR_LEN(hlen));
+		tcp = (const void *)(l3hdr + G_T6_IP_HDR_LEN(hlen));
+	} else {
+		l3hdr = ((uintptr_t)eh + G_ETH_HDR_LEN(hlen));
+		tcp = (const void *)(l3hdr + G_IP_HDR_LEN(hlen));
+	}
 
 	if (inc) {
 		bzero(inc, sizeof(*inc));
@@ -1188,7 +1193,7 @@ do_pass_accept_req(struct sge_iq *iq, const struct rss_header *rss,
 	CTR4(KTR_CXGBE, "%s: stid %u, tid %u, lctx %p", __func__, stid, tid,
 	    lctx);
 
-	pass_accept_req_to_protohdrs(m, &inc, &th);
+	pass_accept_req_to_protohdrs(sc, m, &inc, &th);
 	t4opt_to_tcpopt(&cpl->tcpopt, &to);
 
 	pi = sc->port[G_SYN_INTF(be16toh(cpl->l2info))];
@@ -1427,14 +1432,14 @@ reject:
 }
 
 static void
-synqe_to_protohdrs(struct synq_entry *synqe,
+synqe_to_protohdrs(struct adapter *sc, struct synq_entry *synqe,
     const struct cpl_pass_establish *cpl, struct in_conninfo *inc,
     struct tcphdr *th, struct tcpopt *to)
 {
 	uint16_t tcp_opt = be16toh(cpl->tcp_opt);
 
 	/* start off with the original SYN */
-	pass_accept_req_to_protohdrs(synqe->syn, inc, th);
+	pass_accept_req_to_protohdrs(sc, synqe->syn, inc, th);
 
 	/* modify parts to make it look like the ACK to our SYN|ACK */
 	th->th_flags = TH_ACK;
@@ -1536,7 +1541,7 @@ reset:
 	KASSERT(so != NULL, ("%s: socket is NULL", __func__));
 
 	/* Come up with something that syncache_expand should be ok with. */
-	synqe_to_protohdrs(synqe, cpl, &inc, &th, &to);
+	synqe_to_protohdrs(sc, synqe, cpl, &inc, &th, &to);
 
 	/*
 	 * No more need for anything in the mbuf that carried the
diff --git a/sys/dev/cxgbe/tom/t4_tom.c b/sys/dev/cxgbe/tom/t4_tom.c
index 04f9bcda423c..3df2313fa998 100644
--- a/sys/dev/cxgbe/tom/t4_tom.c
+++ b/sys/dev/cxgbe/tom/t4_tom.c
@@ -538,7 +538,6 @@ select_rcv_wscale(void)
 }
 
 extern int always_keepalive;
-#define VIID_SMACIDX(v)	(((unsigned int)(v) & 0x7f) << 1)
 
 /*
  * socket so could be a listening socket too.
@@ -569,7 +568,7 @@ calc_opt0(struct socket *so, struct vi_info *vi, struct l2t_entry *e,
 		opt0 |= V_L2T_IDX(e->idx);
 
 	if (vi != NULL) {
-		opt0 |= V_SMAC_SEL(VIID_SMACIDX(vi->viid));
+		opt0 |= V_SMAC_SEL(vi->smt_idx);
 		opt0 |= V_TX_CHAN(vi->pi->tx_chan);
 	}
 
diff --git a/sys/dev/evdev/evdev.c b/sys/dev/evdev/evdev.c
index ee433bdd1e60..a2d2a92fd851 100644
--- a/sys/dev/evdev/evdev.c
+++ b/sys/dev/evdev/evdev.c
@@ -92,7 +92,8 @@ void
 evdev_free(struct evdev_dev *evdev)
 {
 
-	if (evdev->ev_cdev != NULL && evdev->ev_cdev->si_drv1 != NULL)
+	if (evdev != NULL && evdev->ev_cdev != NULL &&
+	    evdev->ev_cdev->si_drv1 != NULL)
 		evdev_unregister(evdev);
 
 	free(evdev, M_EVDEV);
diff --git a/sys/dev/hwpmc/hwpmc_logging.c b/sys/dev/hwpmc/hwpmc_logging.c
index 231fbb9aa5c6..f7c0223a9c1f 100644
--- a/sys/dev/hwpmc/hwpmc_logging.c
+++ b/sys/dev/hwpmc/hwpmc_logging.c
@@ -37,11 +37,7 @@
 __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
-#if (__FreeBSD_version >= 1100000)
 #include <sys/capsicum.h>
-#else
-#include <sys/capability.h>
-#endif
 #include <sys/file.h>
 #include <sys/kernel.h>
 #include <sys/kthread.h>
diff --git a/sys/dev/hyperv/include/vmbus.h b/sys/dev/hyperv/include/vmbus.h
index 452d29a92523..090f9b1fcd93 100644
--- a/sys/dev/hyperv/include/vmbus.h
+++ b/sys/dev/hyperv/include/vmbus.h
@@ -108,6 +108,13 @@ struct vmbus_chanpkt_rxbuf {
 	struct vmbus_rxbuf_desc cp_rxbuf[];
 } __packed;
 
+struct vmbus_chan_br {
+	void		*cbr;
+	bus_addr_t	cbr_paddr;
+	int		cbr_txsz;
+	int		cbr_rxsz;
+};
+
 struct vmbus_channel;
 struct hyperv_guid;
 
@@ -122,6 +129,9 @@ vmbus_get_channel(device_t dev)
 int		vmbus_chan_open(struct vmbus_channel *chan,
 		    int txbr_size, int rxbr_size, const void *udata, int udlen,
 		    vmbus_chan_callback_t cb, void *cbarg);
+int		vmbus_chan_open_br(struct vmbus_channel *chan,
+		    const struct vmbus_chan_br *cbr, const void *udata,
+		    int udlen, vmbus_chan_callback_t cb, void *cbarg);
 void		vmbus_chan_close(struct vmbus_channel *chan);
 
 int		vmbus_chan_gpadl_connect(struct vmbus_channel *chan,
diff --git a/sys/dev/hyperv/netvsc/hv_net_vsc.c b/sys/dev/hyperv/netvsc/hv_net_vsc.c
index a64eb6227faa..575f0808bf9b 100644
--- a/sys/dev/hyperv/netvsc/hv_net_vsc.c
+++ b/sys/dev/hyperv/netvsc/hv_net_vsc.c
@@ -444,8 +444,15 @@ hn_nvs_doinit(struct hn_softc *sc, uint32_t nvs_ver)
 	vmbus_xact_put(xact);
 
 	if (status != HN_NVS_STATUS_OK) {
-		if_printf(sc->hn_ifp, "nvs init failed for ver 0x%x\n",
-		    nvs_ver);
+		if (bootverbose) {
+			/*
+			 * Caller may try another NVS version, and will log
+			 * error if there are no more NVS versions to try,
+			 * so don't bark out loud here.
+			 */
+			if_printf(sc->hn_ifp, "nvs init failed for ver 0x%x\n",
+			    nvs_ver);
+		}
 		return (EINVAL);
 	}
 	return (0);
@@ -467,9 +474,15 @@ hn_nvs_conf_ndis(struct hn_softc *sc, int mtu)
 
 	/* NOTE: No response. */
 	error = hn_nvs_req_send(sc, &conf, sizeof(conf));
-	if (error)
+	if (error) {
 		if_printf(sc->hn_ifp, "send nvs ndis conf failed: %d\n", error);
-	return (error);
+		return (error);
+	}
+
+	if (bootverbose)
+		if_printf(sc->hn_ifp, "nvs ndis conf done\n");
+	sc->hn_caps |= HN_CAP_MTU | HN_CAP_VLAN;
+	return (0);
 }
 
 static int
@@ -493,11 +506,31 @@ hn_nvs_init_ndis(struct hn_softc *sc)
 static int
 hn_nvs_init(struct hn_softc *sc)
 {
-	int i;
+	int i, error;
 
-	for (i = 0; i < nitems(hn_nvs_version); ++i) {
-		int error;
+	if (device_is_attached(sc->hn_dev)) {
+		/*
+		 * NVS version and NDIS version MUST NOT be changed.
+		 */
+		if (bootverbose) {
+			if_printf(sc->hn_ifp, "reinit NVS version 0x%x, "
+			    "NDIS version %u.%u\n", sc->hn_nvs_ver,
+			    HN_NDIS_VERSION_MAJOR(sc->hn_ndis_ver),
+			    HN_NDIS_VERSION_MINOR(sc->hn_ndis_ver));
+		}
+
+		error = hn_nvs_doinit(sc, sc->hn_nvs_ver);
+		if (error) {
+			if_printf(sc->hn_ifp, "reinit NVS version 0x%x "
+			    "failed: %d\n", sc->hn_nvs_ver, error);
+		}
+		return (error);
+	}
 
+	/*
+	 * Find the supported NVS version and set NDIS version accordingly.
+	 */
+	for (i = 0; i < nitems(hn_nvs_version); ++i) {
 		error = hn_nvs_doinit(sc, hn_nvs_version[i]);
 		if (!error) {
 			sc->hn_nvs_ver = hn_nvs_version[i];
diff --git a/sys/dev/hyperv/netvsc/hv_net_vsc.h b/sys/dev/hyperv/netvsc/hv_net_vsc.h
index 22e6aa412fe5..6f54446e84ee 100644
--- a/sys/dev/hyperv/netvsc/hv_net_vsc.h
+++ b/sys/dev/hyperv/netvsc/hv_net_vsc.h
@@ -136,6 +136,9 @@ struct hn_rx_ring {
 	/* Rarely used stuffs */
 	struct sysctl_oid *hn_rx_sysctl_tree;
 	int		hn_rx_flags;
+
+	void		*hn_br;		/* TX/RX bufring */
+	struct hyperv_dma hn_br_dma;
 } __aligned(CACHE_LINE_SIZE);
 
 #define HN_TRUST_HCSUM_IP	0x0001
@@ -228,7 +231,8 @@ struct hn_softc {
 	struct vmbus_xact_ctx *hn_xact;
 	uint32_t	hn_nvs_ver;
 
-	uint32_t		hn_flags;
+	uint32_t		hn_caps;	/* HN_CAP_ */
+	uint32_t		hn_flags;	/* HN_FLAG_ */
 	void			*hn_rxbuf;
 	uint32_t		hn_rxbuf_gpadl;
 	struct hyperv_dma	hn_rxbuf_dma;
@@ -244,6 +248,18 @@ struct hn_softc {
 
 #define HN_FLAG_RXBUF_CONNECTED		0x0001
 #define HN_FLAG_CHIM_CONNECTED		0x0002
+#define HN_FLAG_HAS_RSSKEY		0x0004
+#define HN_FLAG_HAS_RSSIND		0x0008
+
+#define HN_CAP_VLAN			0x0001
+#define HN_CAP_MTU			0x0002
+#define HN_CAP_IPCS			0x0004
+#define HN_CAP_TCP4CS			0x0008
+#define HN_CAP_TCP6CS			0x0010
+#define HN_CAP_UDP4CS			0x0020
+#define HN_CAP_UDP6CS			0x0040
+#define HN_CAP_TSO4			0x0080
+#define HN_CAP_TSO6			0x0100
 
 /*
  * Externs
diff --git a/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c b/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c
index 8305ea3c7f55..2c08a2d22158 100644
--- a/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c
+++ b/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c
@@ -180,14 +180,6 @@ struct hn_txdesc {
 #define HN_TXD_FLAG_ONLIST	0x1
 #define HN_TXD_FLAG_DMAMAP	0x2
 
-/*
- * Only enable UDP checksum offloading when it is on 2012R2 or
- * later.  UDP checksum offloading doesn't work on earlier
- * Windows releases.
- */
-#define HN_CSUM_ASSIST_WIN8	(CSUM_IP | CSUM_TCP)
-#define HN_CSUM_ASSIST		(CSUM_IP | CSUM_UDP | CSUM_TCP)
-
 #define HN_LRO_LENLIM_MULTIRX_DEF	(12 * ETHERMTU)
 #define HN_LRO_LENLIM_DEF		(25 * ETHERMTU)
 /* YYY 2*MTU is a bit rough, but should be good enough. */
@@ -202,6 +194,13 @@ struct hn_txdesc {
 #define HN_LOCK(sc)			sx_xlock(&(sc)->hn_lock)
 #define HN_UNLOCK(sc)			sx_xunlock(&(sc)->hn_lock)
 
+#define HN_CSUM_IP_MASK			(CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP)
+#define HN_CSUM_IP6_MASK		(CSUM_IP6_TCP | CSUM_IP6_UDP)
+#define HN_CSUM_IP_HWASSIST(sc)		\
+	((sc)->hn_tx_ring[0].hn_csum_assist & HN_CSUM_IP_MASK)
+#define HN_CSUM_IP6_HWASSIST(sc)	\
+	((sc)->hn_tx_ring[0].hn_csum_assist & HN_CSUM_IP6_MASK)
+
 /*
  * Globals
  */
@@ -325,10 +324,15 @@ static int hn_rx_stat_ulong_sysctl(SYSCTL_HANDLER_ARGS);
 static int hn_tx_stat_ulong_sysctl(SYSCTL_HANDLER_ARGS);
 static int hn_tx_conf_int_sysctl(SYSCTL_HANDLER_ARGS);
 static int hn_ndis_version_sysctl(SYSCTL_HANDLER_ARGS);
+static int hn_caps_sysctl(SYSCTL_HANDLER_ARGS);
+static int hn_hwassist_sysctl(SYSCTL_HANDLER_ARGS);
+static int hn_rss_key_sysctl(SYSCTL_HANDLER_ARGS);
+static int hn_rss_ind_sysctl(SYSCTL_HANDLER_ARGS);
 static int hn_check_iplen(const struct mbuf *, int);
 static int hn_create_tx_ring(struct hn_softc *, int);
 static void hn_destroy_tx_ring(struct hn_tx_ring *);
 static int hn_create_tx_data(struct hn_softc *, int);
+static void hn_fixup_tx_data(struct hn_softc *);
 static void hn_destroy_tx_data(struct hn_softc *);
 static void hn_start_taskfunc(void *, int);
 static void hn_start_txeof_taskfunc(void *, int);
@@ -391,6 +395,64 @@ hn_get_txswq_depth(const struct hn_tx_ring *txr)
 }
 
 static int
+hn_rss_reconfig(struct hn_softc *sc)
+{
+	int error;
+
+	HN_LOCK_ASSERT(sc);
+
+	/*
+	 * Disable RSS first.
+	 *
+	 * NOTE:
+	 * Direct reconfiguration by setting the UNCHG flags does
+	 * _not_ work properly.
+	 */
+	if (bootverbose)
+		if_printf(sc->hn_ifp, "disable RSS\n");
+	error = hn_rndis_conf_rss(sc, NDIS_RSS_FLAG_DISABLE);
+	if (error) {
+		if_printf(sc->hn_ifp, "RSS disable failed\n");
+		return (error);
+	}
+
+	/*
+	 * Reenable the RSS w/ the updated RSS key or indirect
+	 * table.
+	 */
+	if (bootverbose)
+		if_printf(sc->hn_ifp, "reconfig RSS\n");
+	error = hn_rndis_conf_rss(sc, NDIS_RSS_FLAG_NONE);
+	if (error) {
+		if_printf(sc->hn_ifp, "RSS reconfig failed\n");
+		return (error);
+	}
+	return (0);
+}
+
+static void
+hn_rss_ind_fixup(struct hn_softc *sc, int nchan)
+{
+	struct ndis_rssprm_toeplitz *rss = &sc->hn_rss;
+	int i;
+
+	KASSERT(nchan > 1, ("invalid # of channels %d", nchan));
+
+	/*
+	 * Check indirect table to make sure that all channels in it
+	 * can be used.
+	 */
+	for (i = 0; i < NDIS_HASH_INDCNT; ++i) {
+		if (rss->rss_ind[i] >= nchan) {
+			if_printf(sc->hn_ifp,
+			    "RSS indirect table %d fixup: %u -> %d\n",
+			    i, rss->rss_ind[i], nchan - 1);
+			rss->rss_ind[i] = nchan - 1;
+		}
+	}
+}
+
+static int
 hn_ifmedia_upd(struct ifnet *ifp __unused)
 {
 
@@ -456,6 +518,9 @@ netvsc_attach(device_t dev)
 	sc->hn_prichan = vmbus_get_channel(dev);
 	HN_LOCK_INIT(sc);
 
+	/*
+	 * Setup taskqueue for transmission.
+	 */
 	if (hn_tx_taskq == NULL) {
 		sc->hn_tx_taskq = taskqueue_create("hn_tx", M_WAITOK,
 		    taskqueue_thread_enqueue, &sc->hn_tx_taskq);
@@ -477,11 +542,22 @@ netvsc_attach(device_t dev)
 		sc->hn_tx_taskq = hn_tx_taskq;
 	}
 
+	/*
+	 * Allocate ifnet and setup its name earlier, so that if_printf
+	 * can be used by functions, which will be called after
+	 * ether_ifattach().
+	 */
 	ifp = sc->hn_ifp = if_alloc(IFT_ETHER);
 	ifp->if_softc = sc;
 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 
 	/*
+	 * Initialize ifmedia earlier so that it can be unconditionally
+	 * destroyed, if error happened later on.
+	 */
+	ifmedia_init(&sc->hn_media, 0, hn_ifmedia_upd, hn_ifmedia_sts);
+
+	/*
 	 * Figure out the # of RX rings (ring_cnt) and the # of TX rings
 	 * to use (tx_ring_cnt).
 	 *
@@ -511,6 +587,10 @@ netvsc_attach(device_t dev)
 	 */
 	sc->hn_cpu = atomic_fetchadd_int(&hn_cpu_index, ring_cnt) % mp_ncpus;
 
+	/*
+	 * Create enough TX/RX rings, even if only limited number of
+	 * channels can be allocated.
+	 */
 	error = hn_create_tx_data(sc, tx_ring_cnt);
 	if (error)
 		goto failed;
@@ -533,6 +613,63 @@ netvsc_attach(device_t dev)
 	if (error)
 		goto failed;
 
+	error = hn_rndis_get_linkstatus(sc, &link_status);
+	if (error)
+		goto failed;
+	if (link_status == NDIS_MEDIA_STATE_CONNECTED)
+		sc->hn_carrier = 1;
+
+	error = hn_rndis_get_eaddr(sc, eaddr);
+	if (error)
+		goto failed;
+
+#if __FreeBSD_version >= 1100099
+	if (sc->hn_rx_ring_inuse > 1) {
+		/*
+		 * Reduce TCP segment aggregation limit for multiple
+		 * RX rings to increase ACK timeliness.
+		 */
+		hn_set_lro_lenlim(sc, HN_LRO_LENLIM_MULTIRX_DEF);
+	}
+#endif
+
+	/*
+	 * Fixup TX stuffs after synthetic parts are attached.
+	 */
+	hn_fixup_tx_data(sc);
+
+	ctx = device_get_sysctl_ctx(dev);
+	child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
+	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "nvs_version", CTLFLAG_RD,
+	    &sc->hn_nvs_ver, 0, "NVS version");
+	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "ndis_version",
+	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
+	    hn_ndis_version_sysctl, "A", "NDIS version");
+	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "caps",
+	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
+	    hn_caps_sysctl, "A", "capabilities");
+	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "hwassist",
+	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
+	    hn_hwassist_sysctl, "A", "hwassist");
+	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rss_key",
+	    CTLTYPE_OPAQUE | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
+	    hn_rss_key_sysctl, "IU", "RSS key");
+	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rss_ind",
+	    CTLTYPE_OPAQUE | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
+	    hn_rss_ind_sysctl, "IU", "RSS indirect table");
+
+	/*
+	 * Setup the ifmedia, which has been initialized earlier.
+	 */
+	ifmedia_add(&sc->hn_media, IFM_ETHER | IFM_AUTO, 0, NULL);
+	ifmedia_set(&sc->hn_media, IFM_ETHER | IFM_AUTO);
+	/* XXX ifmedia_set really should do this for us */
+	sc->hn_media.ifm_media = sc->hn_media.ifm_cur->ifm_media;
+
+	/*
+	 * Setup the ifnet for this interface.
+	 */
+
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = hn_ioctl;
 	ifp->if_init = hn_init;
@@ -548,74 +685,54 @@ netvsc_attach(device_t dev)
 		ifp->if_qflush = hn_xmit_qflush;
 	}
 
-	ifmedia_init(&sc->hn_media, 0, hn_ifmedia_upd, hn_ifmedia_sts);
-	ifmedia_add(&sc->hn_media, IFM_ETHER | IFM_AUTO, 0, NULL);
-	ifmedia_set(&sc->hn_media, IFM_ETHER | IFM_AUTO);
-	/* XXX ifmedia_set really should do this for us */
-	sc->hn_media.ifm_media = sc->hn_media.ifm_cur->ifm_media;
-
-	/*
-	 * Tell upper layers that we support full VLAN capability.
-	 */
-	ifp->if_capabilities |=
-	    IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_TSO |
-	    IFCAP_LRO;
-	ifp->if_capenable |=
-	    IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_TSO |
-	    IFCAP_LRO;
-	ifp->if_hwassist = sc->hn_tx_ring[0].hn_csum_assist | CSUM_TSO;
+	ifp->if_capabilities |= IFCAP_RXCSUM | IFCAP_LRO;
+#ifdef foo
+	/* We can't diff IPv6 packets from IPv4 packets on RX path. */
+	ifp->if_capabilities |= IFCAP_RXCSUM_IPV6;
+#endif
+	if (sc->hn_caps & HN_CAP_VLAN) {
+		/* XXX not sure about VLAN_MTU. */
+		ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
+	}
 
-#if __FreeBSD_version >= 1100099
-	if (sc->hn_rx_ring_inuse > 1) {
-		/*
-		 * Reduce TCP segment aggregation limit for multiple
-		 * RX rings to increase ACK timeliness.
-		 */
-		hn_set_lro_lenlim(sc, HN_LRO_LENLIM_MULTIRX_DEF);
+	ifp->if_hwassist = sc->hn_tx_ring[0].hn_csum_assist;
+	if (ifp->if_hwassist & HN_CSUM_IP_MASK)
+		ifp->if_capabilities |= IFCAP_TXCSUM;
+	if (ifp->if_hwassist & HN_CSUM_IP6_MASK)
+		ifp->if_capabilities |= IFCAP_TXCSUM_IPV6;
+	if (sc->hn_caps & HN_CAP_TSO4) {
+		ifp->if_capabilities |= IFCAP_TSO4;
+		ifp->if_hwassist |= CSUM_IP_TSO;
+	}
+	if (sc->hn_caps & HN_CAP_TSO6) {
+		ifp->if_capabilities |= IFCAP_TSO6;
+		ifp->if_hwassist |= CSUM_IP6_TSO;
 	}
-#endif
 
-	error = hn_rndis_get_linkstatus(sc, &link_status);
-	if (error)
-		goto failed;
-	if (link_status == NDIS_MEDIA_STATE_CONNECTED)
-		sc->hn_carrier = 1;
+	/* Enable all available capabilities by default. */
+	ifp->if_capenable = ifp->if_capabilities;
 
 	tso_maxlen = hn_tso_maxlen;
 	if (tso_maxlen <= 0 || tso_maxlen > IP_MAXPACKET)
 		tso_maxlen = IP_MAXPACKET;
-
 	ifp->if_hw_tsomaxsegcount = HN_TX_DATA_SEGCNT_MAX;
 	ifp->if_hw_tsomaxsegsize = PAGE_SIZE;
 	ifp->if_hw_tsomax = tso_maxlen -
 	    (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
 
-	error = hn_rndis_get_eaddr(sc, eaddr);
-	if (error)
-		goto failed;
 	ether_ifattach(ifp, eaddr);
 
-	if_printf(ifp, "TSO: %u/%u/%u\n", ifp->if_hw_tsomax,
-	    ifp->if_hw_tsomaxsegcount, ifp->if_hw_tsomaxsegsize);
+	if (bootverbose) {
+		if_printf(ifp, "TSO: %u/%u/%u\n", ifp->if_hw_tsomax,
+		    ifp->if_hw_tsomaxsegcount, ifp->if_hw_tsomaxsegsize);
+	}
 
 	/* Inform the upper layer about the long frame support. */
 	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
 
-	hn_set_chim_size(sc, sc->hn_chim_szmax);
-	if (hn_tx_chimney_size > 0 &&
-	    hn_tx_chimney_size < sc->hn_chim_szmax)
-		hn_set_chim_size(sc, hn_tx_chimney_size);
-
-	ctx = device_get_sysctl_ctx(dev);
-	child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
-	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "nvs_version", CTLFLAG_RD,
-	    &sc->hn_nvs_ver, 0, "NVS version");
-	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "ndis_version",
-	    CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
-	    hn_ndis_version_sysctl, "A", "NDIS version");
-
 	return (0);
 failed:
+	/* TODO: reuse netvsc_detach() */
 	hn_destroy_tx_data(sc);
 	if (ifp != NULL)
 		if_free(ifp);
@@ -947,14 +1064,19 @@ hn_encap(struct hn_tx_ring *txr, struct hn_txdesc *txd, struct mbuf **m_head0)
 	} else if (m_head->m_pkthdr.csum_flags & txr->hn_csum_assist) {
 		pi_data = hn_rndis_pktinfo_append(pkt, HN_RNDIS_PKT_LEN,
 		    NDIS_TXCSUM_INFO_SIZE, NDIS_PKTINFO_TYPE_CSUM);
-		*pi_data = NDIS_TXCSUM_INFO_IPV4;
-
-		if (m_head->m_pkthdr.csum_flags & CSUM_IP)
-			*pi_data |= NDIS_TXCSUM_INFO_IPCS;
+		if (m_head->m_pkthdr.csum_flags &
+		    (CSUM_IP6_TCP | CSUM_IP6_UDP)) {
+			*pi_data = NDIS_TXCSUM_INFO_IPV6;
+		} else {
+			*pi_data = NDIS_TXCSUM_INFO_IPV4;
+			if (m_head->m_pkthdr.csum_flags & CSUM_IP)
+				*pi_data |= NDIS_TXCSUM_INFO_IPCS;
+		}
 
-		if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
+		if (m_head->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP))
 			*pi_data |= NDIS_TXCSUM_INFO_TCPCS;
-		else if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
+		else if (m_head->m_pkthdr.csum_flags &
+		    (CSUM_IP_UDP | CSUM_IP6_UDP))
 			*pi_data |= NDIS_TXCSUM_INFO_UDPCS;
 	}
 
@@ -1480,6 +1602,13 @@ hn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 
 		HN_LOCK(sc);
 
+		if ((sc->hn_caps & HN_CAP_MTU) == 0) {
+			/* Can't change MTU */
+			HN_UNLOCK(sc);
+			error = EOPNOTSUPP;
+			break;
+		}
+
 		if (ifp->if_mtu == ifr->ifr_mtu) {
 			HN_UNLOCK(sc);
 			break;
@@ -1564,21 +1693,31 @@ hn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 
 	case SIOCSIFCAP:
 		HN_LOCK(sc);
-
 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
+
 		if (mask & IFCAP_TXCSUM) {
 			ifp->if_capenable ^= IFCAP_TXCSUM;
-			if (ifp->if_capenable & IFCAP_TXCSUM) {
-				ifp->if_hwassist |=
-				    sc->hn_tx_ring[0].hn_csum_assist;
-			} else {
-				ifp->if_hwassist &=
-				    ~sc->hn_tx_ring[0].hn_csum_assist;
-			}
+			if (ifp->if_capenable & IFCAP_TXCSUM)
+				ifp->if_hwassist |= HN_CSUM_IP_HWASSIST(sc);
+			else
+				ifp->if_hwassist &= ~HN_CSUM_IP_HWASSIST(sc);
+		}
+		if (mask & IFCAP_TXCSUM_IPV6) {
+			ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
+			if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
+				ifp->if_hwassist |= HN_CSUM_IP6_HWASSIST(sc);
+			else
+				ifp->if_hwassist &= ~HN_CSUM_IP6_HWASSIST(sc);
 		}
 
+		/* TODO: flip RNDIS offload parameters for RXCSUM. */
 		if (mask & IFCAP_RXCSUM)
 			ifp->if_capenable ^= IFCAP_RXCSUM;
+#ifdef foo
+		/* We can't diff IPv6 packets from IPv4 packets on RX path. */
+		if (mask & IFCAP_RXCSUM_IPV6)
+			ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
+#endif
 
 		if (mask & IFCAP_LRO)
 			ifp->if_capenable ^= IFCAP_LRO;
@@ -1590,7 +1729,6 @@ hn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 			else
 				ifp->if_hwassist &= ~CSUM_IP_TSO;
 		}
-
 		if (mask & IFCAP_TSO6) {
 			ifp->if_capenable ^= IFCAP_TSO6;
 			if (ifp->if_capenable & IFCAP_TSO6)
@@ -2007,6 +2145,105 @@ hn_ndis_version_sysctl(SYSCTL_HANDLER_ARGS)
 }
 
 static int
+hn_caps_sysctl(SYSCTL_HANDLER_ARGS)
+{
+	struct hn_softc *sc = arg1;
+	char caps_str[128];
+	uint32_t caps;
+
+	HN_LOCK(sc);
+	caps = sc->hn_caps;
+	HN_UNLOCK(sc);
+	snprintf(caps_str, sizeof(caps_str), "%b", caps,
+	    "\020"
+	    "\001VLAN"
+	    "\002MTU"
+	    "\003IPCS"
+	    "\004TCP4CS"
+	    "\005TCP6CS"
+	    "\006UDP4CS"
+	    "\007UDP6CS"
+	    "\010TSO4"
+	    "\011TSO6");
+	return sysctl_handle_string(oidp, caps_str, sizeof(caps_str), req);
+}
+
+static int
+hn_hwassist_sysctl(SYSCTL_HANDLER_ARGS)
+{
+	struct hn_softc *sc = arg1;
+	char assist_str[128];
+	uint32_t hwassist;
+
+	HN_LOCK(sc);
+	hwassist = sc->hn_ifp->if_hwassist;
+	HN_UNLOCK(sc);
+	snprintf(assist_str, sizeof(assist_str), "%b", hwassist, CSUM_BITS);
+	return sysctl_handle_string(oidp, assist_str, sizeof(assist_str), req);
+}
+
+static int
+hn_rss_key_sysctl(SYSCTL_HANDLER_ARGS)
+{
+	struct hn_softc *sc = arg1;
+	int error;
+
+	HN_LOCK(sc);
+
+	error = SYSCTL_OUT(req, sc->hn_rss.rss_key, sizeof(sc->hn_rss.rss_key));
+	if (error || req->newptr == NULL)
+		goto back;
+
+	error = SYSCTL_IN(req, sc->hn_rss.rss_key, sizeof(sc->hn_rss.rss_key));
+	if (error)
+		goto back;
+	sc->hn_flags |= HN_FLAG_HAS_RSSKEY;
+
+	if (sc->hn_rx_ring_inuse > 1) {
+		error = hn_rss_reconfig(sc);
+	} else {
+		/* Not RSS capable, at least for now; just save the RSS key. */
+		error = 0;
+	}
+back:
+	HN_UNLOCK(sc);
+	return (error);
+}
+
+static int
+hn_rss_ind_sysctl(SYSCTL_HANDLER_ARGS)
+{
+	struct hn_softc *sc = arg1;
+	int error;
+
+	HN_LOCK(sc);
+
+	error = SYSCTL_OUT(req, sc->hn_rss.rss_ind, sizeof(sc->hn_rss.rss_ind));
+	if (error || req->newptr == NULL)
+		goto back;
+
+	/*
+	 * Don't allow RSS indirect table change, if this interface is not
+	 * RSS capable currently.
+	 */
+	if (sc->hn_rx_ring_inuse == 1) {
+		error = EOPNOTSUPP;
+		goto back;
+	}
+
+	error = SYSCTL_IN(req, sc->hn_rss.rss_ind, sizeof(sc->hn_rss.rss_ind));
+	if (error)
+		goto back;
+	sc->hn_flags |= HN_FLAG_HAS_RSSIND;
+
+	hn_rss_ind_fixup(sc, sc->hn_rx_ring_inuse);
+	error = hn_rss_reconfig(sc);
+back:
+	HN_UNLOCK(sc);
+	return (error);
+}
+
+static int
 hn_check_iplen(const struct mbuf *m, int hoff)
 {
 	const struct ip *ip;
@@ -2121,7 +2358,8 @@ hn_create_rx_data(struct hn_softc *sc, int ring_cnt)
 	lroent_cnt = hn_lro_entry_count;
 	if (lroent_cnt < TCP_LRO_ENTRIES)
 		lroent_cnt = TCP_LRO_ENTRIES;
-	device_printf(dev, "LRO: entry count %d\n", lroent_cnt);
+	if (bootverbose)
+		device_printf(dev, "LRO: entry count %d\n", lroent_cnt);
 #endif
 #endif	/* INET || INET6 */
 
@@ -2135,6 +2373,16 @@ hn_create_rx_data(struct hn_softc *sc, int ring_cnt)
 	for (i = 0; i < sc->hn_rx_ring_cnt; ++i) {
 		struct hn_rx_ring *rxr = &sc->hn_rx_ring[i];
 
+		rxr->hn_br = hyperv_dmamem_alloc(bus_get_dma_tag(dev),
+		    PAGE_SIZE, 0,
+		    NETVSC_DEVICE_RING_BUFFER_SIZE +
+		    NETVSC_DEVICE_RING_BUFFER_SIZE,
+		    &rxr->hn_br_dma, BUS_DMA_WAITOK);
+		if (rxr->hn_br == NULL) {
+			device_printf(dev, "allocate bufring failed\n");
+			return (ENOMEM);
+		}
+
 		if (hn_trust_hosttcp)
 			rxr->hn_trust_hcsum |= HN_TRUST_HCSUM_TCP;
 		if (hn_trust_hostudp)
@@ -2283,6 +2531,11 @@ hn_destroy_rx_data(struct hn_softc *sc)
 	for (i = 0; i < sc->hn_rx_ring_cnt; ++i) {
 		struct hn_rx_ring *rxr = &sc->hn_rx_ring[i];
 
+		if (rxr->hn_br == NULL)
+			continue;
+		hyperv_dmamem_free(&rxr->hn_br_dma, rxr->hn_br);
+		rxr->hn_br = NULL;
+
 #if defined(INET) || defined(INET6)
 		tcp_lro_free(&rxr->hn_lro);
 #endif
@@ -2302,7 +2555,6 @@ hn_create_tx_ring(struct hn_softc *sc, int id)
 	device_t dev = sc->hn_dev;
 	bus_dma_tag_t parent_dtag;
 	int error, i;
-	uint32_t version;
 
 	txr->hn_sc = sc;
 	txr->hn_tx_idx = id;
@@ -2341,18 +2593,6 @@ hn_create_tx_ring(struct hn_softc *sc, int id)
 	}
 
 	txr->hn_direct_tx_size = hn_direct_tx_size;
-	version = VMBUS_GET_VERSION(device_get_parent(dev), dev);
-	if (version >= VMBUS_VERSION_WIN8_1) {
-		txr->hn_csum_assist = HN_CSUM_ASSIST;
-	} else {
-		txr->hn_csum_assist = HN_CSUM_ASSIST_WIN8;
-		if (id == 0) {
-			device_printf(dev, "bus version %u.%u, "
-			    "no UDP checksum offloading\n",
-			    VMBUS_VERSION_MAJOR(version),
-			    VMBUS_VERSION_MINOR(version));
-		}
-	}
 
 	/*
 	 * Always schedule transmission instead of trying to do direct
@@ -2648,6 +2888,35 @@ hn_set_chim_size(struct hn_softc *sc, int chim_size)
 }
 
 static void
+hn_fixup_tx_data(struct hn_softc *sc)
+{
+	uint64_t csum_assist;
+	int i;
+
+	hn_set_chim_size(sc, sc->hn_chim_szmax);
+	if (hn_tx_chimney_size > 0 &&
+	    hn_tx_chimney_size < sc->hn_chim_szmax)
+		hn_set_chim_size(sc, hn_tx_chimney_size);
+
+	csum_assist = 0;
+	if (sc->hn_caps & HN_CAP_IPCS)
+		csum_assist |= CSUM_IP;
+	if (sc->hn_caps & HN_CAP_TCP4CS)
+		csum_assist |= CSUM_IP_TCP;
+	if (sc->hn_caps & HN_CAP_UDP4CS)
+		csum_assist |= CSUM_IP_UDP;
+#ifdef notyet
+	if (sc->hn_caps & HN_CAP_TCP6CS)
+		csum_assist |= CSUM_IP6_TCP;
+	if (sc->hn_caps & HN_CAP_UDP6CS)
+		csum_assist |= CSUM_IP6_UDP;
+#endif
+
+	for (i = 0; i < sc->hn_tx_ring_cnt; ++i)
+		sc->hn_tx_ring[i].hn_csum_assist = csum_assist;
+}
+
+static void
 hn_destroy_tx_data(struct hn_softc *sc)
 {
 	int i;
@@ -2872,6 +3141,7 @@ hn_xmit_txeof_taskfunc(void *xtxr, int pending __unused)
 static int
 hn_chan_attach(struct hn_softc *sc, struct vmbus_channel *chan)
 {
+	struct vmbus_chan_br cbr;
 	struct hn_rx_ring *rxr;
 	struct hn_tx_ring *txr = NULL;
 	int idx, error;
@@ -2910,9 +3180,14 @@ hn_chan_attach(struct hn_softc *sc, struct vmbus_channel *chan)
 	/* Bind this channel to a proper CPU. */
 	vmbus_chan_cpu_set(chan, (sc->hn_cpu + idx) % mp_ncpus);
 
-	/* Open this channel */
-	error = vmbus_chan_open(chan, NETVSC_DEVICE_RING_BUFFER_SIZE,
-	    NETVSC_DEVICE_RING_BUFFER_SIZE, NULL, 0, hn_chan_callback, rxr);
+	/*
+	 * Open this channel
+	 */
+	cbr.cbr = rxr->hn_br;
+	cbr.cbr_paddr = rxr->hn_br_dma.hv_paddr;
+	cbr.cbr_txsz = NETVSC_DEVICE_RING_BUFFER_SIZE;
+	cbr.cbr_rxsz = NETVSC_DEVICE_RING_BUFFER_SIZE;
+	error = vmbus_chan_open_br(chan, &cbr, NULL, 0, hn_chan_callback, rxr);
 	if (error) {
 		if_printf(sc->hn_ifp, "open chan%u failed: %d\n",
 		    vmbus_chan_id(chan), error);
@@ -3055,8 +3330,10 @@ hn_synth_alloc_subchans(struct hn_softc *sc, int *nsubch)
 		*nsubch = 0;
 		return (0);
 	}
-	if_printf(sc->hn_ifp, "RX rings offered %u, requested %d\n",
-	    rxr_cnt, nchan);
+	if (bootverbose) {
+		if_printf(sc->hn_ifp, "RX rings offered %u, requested %d\n",
+		    rxr_cnt, nchan);
+	}
 
 	if (nchan > rxr_cnt)
 		nchan = rxr_cnt;
@@ -3065,7 +3342,7 @@ hn_synth_alloc_subchans(struct hn_softc *sc, int *nsubch)
 		*nsubch = 0;
 		return (0);
 	}
-	
+
 	/*
 	 * Allocate sub-channels from NVS.
 	 */
@@ -3090,6 +3367,11 @@ hn_synth_attach(struct hn_softc *sc, int mtu)
 {
 	struct ndis_rssprm_toeplitz *rss = &sc->hn_rss;
 	int error, nsubch, nchan, i;
+	uint32_t old_caps;
+
+	/* Save capabilities for later verification. */
+	old_caps = sc->hn_caps;
+	sc->hn_caps = 0;
 
 	/*
 	 * Attach the primary channel _before_ attaching NVS and RNDIS.
@@ -3113,6 +3395,17 @@ hn_synth_attach(struct hn_softc *sc, int mtu)
 		return (error);
 
 	/*
+	 * Make sure capabilities are not changed.
+	 */
+	if (device_is_attached(sc->hn_dev) && old_caps != sc->hn_caps) {
+		if_printf(sc->hn_ifp, "caps mismatch old 0x%08x, new 0x%08x\n",
+		    old_caps, sc->hn_caps);
+		/* Restore old capabilities and abort. */
+		sc->hn_caps = old_caps;
+		return ENXIO;
+	}
+
+	/*
 	 * Allocate sub-channels for multi-TX/RX rings.
 	 *
 	 * NOTE:
@@ -3135,15 +3428,39 @@ hn_synth_attach(struct hn_softc *sc, int mtu)
 	 * are allocated.
 	 */
 
-	/* Setup default RSS key. */
-	memcpy(rss->rss_key, hn_rss_key_default, sizeof(rss->rss_key));
+	if ((sc->hn_flags & HN_FLAG_HAS_RSSKEY) == 0) {
+		/*
+		 * RSS key is not set yet; set it to the default RSS key.
+		 */
+		if (bootverbose)
+			if_printf(sc->hn_ifp, "setup default RSS key\n");
+		memcpy(rss->rss_key, hn_rss_key_default, sizeof(rss->rss_key));
+		sc->hn_flags |= HN_FLAG_HAS_RSSKEY;
+	}
 
-	/* Setup default RSS indirect table. */
-	/* TODO: Take ndis_rss_caps.ndis_nind into account. */
-	for (i = 0; i < NDIS_HASH_INDCNT; ++i)
-		rss->rss_ind[i] = i % nchan;
+	if ((sc->hn_flags & HN_FLAG_HAS_RSSIND) == 0) {
+		/*
+		 * RSS indirect table is not set yet; set it up in round-
+		 * robin fashion.
+		 */
+		if (bootverbose) {
+			if_printf(sc->hn_ifp, "setup default RSS indirect "
+			    "table\n");
+		}
+		/* TODO: Take ndis_rss_caps.ndis_nind into account. */
+		for (i = 0; i < NDIS_HASH_INDCNT; ++i)
+			rss->rss_ind[i] = i % nchan;
+		sc->hn_flags |= HN_FLAG_HAS_RSSIND;
+	} else {
+		/*
+		 * # of usable channels may be changed, so we have to
+		 * make sure that all entries in RSS indirect table
+		 * are valid.
+		 */
+		hn_rss_ind_fixup(sc, nchan);
+	}
 
-	error = hn_rndis_conf_rss(sc);
+	error = hn_rndis_conf_rss(sc, NDIS_RSS_FLAG_NONE);
 	if (error) {
 		/*
 		 * Failed to configure RSS key or indirect table; only
diff --git a/sys/dev/hyperv/netvsc/hv_rndis_filter.c b/sys/dev/hyperv/netvsc/hv_rndis_filter.c
index ff7a84c46c38..451e7d7150d4 100644
--- a/sys/dev/hyperv/netvsc/hv_rndis_filter.c
+++ b/sys/dev/hyperv/netvsc/hv_rndis_filter.c
@@ -800,6 +800,7 @@ static int
 hn_rndis_conf_offload(struct hn_softc *sc)
 {
 	struct ndis_offload_params params;
+	uint32_t caps;
 	size_t paramsz;
 	int error;
 
@@ -816,28 +817,33 @@ hn_rndis_conf_offload(struct hn_softc *sc)
 	}
 	params.ndis_hdr.ndis_size = paramsz;
 
+	caps = HN_CAP_IPCS | HN_CAP_TCP4CS | HN_CAP_TCP6CS;
 	params.ndis_ip4csum = NDIS_OFFLOAD_PARAM_TXRX;
 	params.ndis_tcp4csum = NDIS_OFFLOAD_PARAM_TXRX;
 	params.ndis_tcp6csum = NDIS_OFFLOAD_PARAM_TXRX;
 	if (sc->hn_ndis_ver >= HN_NDIS_VERSION_6_30) {
+		caps |= HN_CAP_UDP4CS | HN_CAP_UDP6CS;
 		params.ndis_udp4csum = NDIS_OFFLOAD_PARAM_TXRX;
 		params.ndis_udp6csum = NDIS_OFFLOAD_PARAM_TXRX;
 	}
+	caps |= HN_CAP_TSO4;
 	params.ndis_lsov2_ip4 = NDIS_OFFLOAD_LSOV2_ON;
 	/* XXX ndis_lsov2_ip6 = NDIS_OFFLOAD_LSOV2_ON */
 
 	error = hn_rndis_set(sc, OID_TCP_OFFLOAD_PARAMETERS, &params, paramsz);
 	if (error) {
 		if_printf(sc->hn_ifp, "offload config failed: %d\n", error);
-	} else {
-		if (bootverbose)
-			if_printf(sc->hn_ifp, "offload config done\n");
+		return (error);
 	}
-	return (error);
+
+	if (bootverbose)
+		if_printf(sc->hn_ifp, "offload config done\n");
+	sc->hn_caps |= caps;
+	return (0);
 }
 
 int
-hn_rndis_conf_rss(struct hn_softc *sc)
+hn_rndis_conf_rss(struct hn_softc *sc, uint16_t flags)
 {
 	struct ndis_rssprm_toeplitz *rss = &sc->hn_rss;
 	struct ndis_rss_params *prm = &rss->rss_params;
@@ -858,6 +864,7 @@ hn_rndis_conf_rss(struct hn_softc *sc)
 	prm->ndis_hdr.ndis_type = NDIS_OBJTYPE_RSS_PARAMS;
 	prm->ndis_hdr.ndis_rev = NDIS_RSS_PARAMS_REV_2;
 	prm->ndis_hdr.ndis_size = sizeof(*rss);
+	prm->ndis_flags = flags;
 	prm->ndis_hash = NDIS_HASH_FUNCTION_TOEPLITZ |
 	    NDIS_HASH_IPV4 | NDIS_HASH_TCP_IPV4 |
 	    NDIS_HASH_IPV6 | NDIS_HASH_TCP_IPV6;
diff --git a/sys/dev/hyperv/netvsc/if_hnvar.h b/sys/dev/hyperv/netvsc/if_hnvar.h
index 23626ee1c1bb..38ff16ee72c9 100644
--- a/sys/dev/hyperv/netvsc/if_hnvar.h
+++ b/sys/dev/hyperv/netvsc/if_hnvar.h
@@ -118,7 +118,7 @@ uint32_t	hn_chim_alloc(struct hn_softc *sc);
 void		hn_chim_free(struct hn_softc *sc, uint32_t chim_idx);
 
 int		hn_rndis_attach(struct hn_softc *sc);
-int		hn_rndis_conf_rss(struct hn_softc *sc);
+int		hn_rndis_conf_rss(struct hn_softc *sc, uint16_t flags);
 void		*hn_rndis_pktinfo_append(struct rndis_packet_msg *,
 		    size_t pktsize, size_t pi_dlen, uint32_t pi_type);
 int		hn_rndis_get_rsscaps(struct hn_softc *sc, int *rxr_cnt);
diff --git a/sys/dev/hyperv/netvsc/ndis.h b/sys/dev/hyperv/netvsc/ndis.h
index 895f756db16e..28920f8e09c8 100644
--- a/sys/dev/hyperv/netvsc/ndis.h
+++ b/sys/dev/hyperv/netvsc/ndis.h
@@ -188,6 +188,7 @@ struct ndis_rss_params {
 #define	NDIS_RSS_PARAMS_REV_1		1	/* NDIS 6.0 */
 #define	NDIS_RSS_PARAMS_REV_2		2	/* NDIS 6.20 */
 
+#define	NDIS_RSS_FLAG_NONE		0x0000
 #define	NDIS_RSS_FLAG_BCPU_UNCHG	0x0001
 #define	NDIS_RSS_FLAG_HASH_UNCHG	0x0002
 #define	NDIS_RSS_FLAG_IND_UNCHG		0x0004
diff --git a/sys/dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c b/sys/dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c
index 530a2d909cac..e1b2fdf9f3db 100644
--- a/sys/dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c
+++ b/sys/dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c
@@ -705,7 +705,8 @@ hv_storvsc_io_request(struct storvsc_softc *sc,
 
 	vstor_packet->flags |= REQUEST_COMPLETION_FLAG;
 
-	vstor_packet->u.vm_srb.length = VSTOR_PKT_SIZE;
+	vstor_packet->u.vm_srb.length =
+	    sizeof(struct vmscsi_req) - vmscsi_size_delta;
 	
 	vstor_packet->u.vm_srb.sense_info_len = sense_buffer_size;
 
diff --git a/sys/dev/hyperv/vmbus/vmbus_chan.c b/sys/dev/hyperv/vmbus/vmbus_chan.c
index 9365db3f8642..cfc71211782d 100644
--- a/sys/dev/hyperv/vmbus/vmbus_chan.c
+++ b/sys/dev/hyperv/vmbus/vmbus_chan.c
@@ -196,13 +196,45 @@ int
 vmbus_chan_open(struct vmbus_channel *chan, int txbr_size, int rxbr_size,
     const void *udata, int udlen, vmbus_chan_callback_t cb, void *cbarg)
 {
+	struct vmbus_chan_br cbr;
+	int error;
+
+	/*
+	 * Allocate the TX+RX bufrings.
+	 */
+	KASSERT(chan->ch_bufring == NULL, ("bufrings are allocated"));
+	chan->ch_bufring = hyperv_dmamem_alloc(bus_get_dma_tag(chan->ch_dev),
+	    PAGE_SIZE, 0, txbr_size + rxbr_size, &chan->ch_bufring_dma,
+	    BUS_DMA_WAITOK);
+	if (chan->ch_bufring == NULL) {
+		device_printf(chan->ch_dev, "bufring allocation failed\n");
+		return (ENOMEM);
+	}
+
+	cbr.cbr = chan->ch_bufring;
+	cbr.cbr_paddr = chan->ch_bufring_dma.hv_paddr;
+	cbr.cbr_txsz = txbr_size;
+	cbr.cbr_rxsz = rxbr_size;
+
+	error = vmbus_chan_open_br(chan, &cbr, udata, udlen, cb, cbarg);
+	if (error) {
+		hyperv_dmamem_free(&chan->ch_bufring_dma, chan->ch_bufring);
+		chan->ch_bufring = NULL;
+	}
+	return (error);
+}
+
+int
+vmbus_chan_open_br(struct vmbus_channel *chan, const struct vmbus_chan_br *cbr,
+    const void *udata, int udlen, vmbus_chan_callback_t cb, void *cbarg)
+{
 	struct vmbus_softc *sc = chan->ch_vmbus;
 	const struct vmbus_chanmsg_chopen_resp *resp;
 	const struct vmbus_message *msg;
 	struct vmbus_chanmsg_chopen *req;
 	struct vmbus_msghc *mh;
 	uint32_t status;
-	int error;
+	int error, txbr_size, rxbr_size;
 	uint8_t *br;
 
 	if (udlen > VMBUS_CHANMSG_CHOPEN_UDATA_SIZE) {
@@ -210,10 +242,21 @@ vmbus_chan_open(struct vmbus_channel *chan, int txbr_size, int rxbr_size,
 		    "invalid udata len %d for chan%u\n", udlen, chan->ch_id);
 		return EINVAL;
 	}
+
+	br = cbr->cbr;
+	txbr_size = cbr->cbr_txsz;
+	rxbr_size = cbr->cbr_rxsz;
 	KASSERT((txbr_size & PAGE_MASK) == 0,
 	    ("send bufring size is not multiple page"));
 	KASSERT((rxbr_size & PAGE_MASK) == 0,
 	    ("recv bufring size is not multiple page"));
+	KASSERT((cbr->cbr_paddr & PAGE_MASK) == 0,
+	    ("bufring is not page aligned"));
+
+	/*
+	 * Zero out the TX/RX bufrings, in case that they were used before.
+	 */
+	memset(br, 0, txbr_size + rxbr_size);
 
 	if (atomic_testandset_int(&chan->ch_stflags,
 	    VMBUS_CHAN_ST_OPENED_SHIFT))
@@ -230,20 +273,6 @@ vmbus_chan_open(struct vmbus_channel *chan, int txbr_size, int rxbr_size,
 	else
 		TASK_INIT(&chan->ch_task, 0, vmbus_chan_task_nobatch, chan);
 
-	/*
-	 * Allocate the TX+RX bufrings.
-	 * XXX should use ch_dev dtag
-	 */
-	br = hyperv_dmamem_alloc(bus_get_dma_tag(sc->vmbus_dev),
-	    PAGE_SIZE, 0, txbr_size + rxbr_size, &chan->ch_bufring_dma,
-	    BUS_DMA_WAITOK | BUS_DMA_ZERO);
-	if (br == NULL) {
-		device_printf(sc->vmbus_dev, "bufring allocation failed\n");
-		error = ENOMEM;
-		goto failed;
-	}
-	chan->ch_bufring = br;
-
 	/* TX bufring comes first */
 	vmbus_txbr_setup(&chan->ch_txbr, br, txbr_size);
 	/* RX bufring immediately follows TX bufring */
@@ -255,7 +284,7 @@ vmbus_chan_open(struct vmbus_channel *chan, int txbr_size, int rxbr_size,
 	/*
 	 * Connect the bufrings, both RX and TX, to this channel.
 	 */
-	error = vmbus_chan_gpadl_connect(chan, chan->ch_bufring_dma.hv_paddr,
+	error = vmbus_chan_gpadl_connect(chan, cbr->cbr_paddr,
 	    txbr_size + rxbr_size, &chan->ch_bufring_gpadl);
 	if (error) {
 		device_printf(sc->vmbus_dev,
@@ -316,10 +345,6 @@ failed:
 		vmbus_chan_gpadl_disconnect(chan, chan->ch_bufring_gpadl);
 		chan->ch_bufring_gpadl = 0;
 	}
-	if (chan->ch_bufring != NULL) {
-		hyperv_dmamem_free(&chan->ch_bufring_dma, chan->ch_bufring);
-		chan->ch_bufring = NULL;
-	}
 	atomic_clear_int(&chan->ch_stflags, VMBUS_CHAN_ST_OPENED);
 	return error;
 }
diff --git a/sys/dev/iicbus/ds1307.c b/sys/dev/iicbus/ds1307.c
index 987db0d0e75b..bd00cda36846 100644
--- a/sys/dev/iicbus/ds1307.c
+++ b/sys/dev/iicbus/ds1307.c
@@ -274,7 +274,7 @@ ds1307_probe(device_t dev)
 
 	compat = ofw_bus_search_compatible(dev, ds1307_compat_data);
 
-	if (compat == NULL)
+	if (compat->ocd_str == NULL)
 		return (ENXIO);
 
 	device_set_desc(dev, (const char *)compat->ocd_data);
diff --git a/sys/dev/intpm/intpm.c b/sys/dev/intpm/intpm.c
index 76076ab80efa..bab2a7b73cfc 100644
--- a/sys/dev/intpm/intpm.c
+++ b/sys/dev/intpm/intpm.c
@@ -43,6 +43,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/intpm/intpmreg.h>
+#include <dev/amdsbwd/amd_chipset.h>
 
 #include "opt_intpm.h"
 
@@ -103,12 +104,11 @@ intsmb_probe(device_t dev)
 	case 0x43721002:
 		device_set_desc(dev, "ATI IXP400 SMBus Controller");
 		break;
-	case 0x43851002:
+	case AMDSB_SMBUS_DEVID:
 		device_set_desc(dev, "AMD SB600/7xx/8xx/9xx SMBus Controller");
 		break;
-	case 0x780b1022:	/* AMD FCH */
-		if (pci_get_revid(dev) < 0x40)
-			return (ENXIO);
+	case AMDFCH_SMBUS_DEVID:	/* AMD FCH */
+	case AMDCZ_SMBUS_DEVID:		/* AMD Carizzo FCH */
 		device_set_desc(dev, "AMD FCH SMBus Controller");
 		break;
 	default:
@@ -119,7 +119,7 @@ intsmb_probe(device_t dev)
 }
 
 static uint8_t
-sb8xx_pmio_read(struct resource *res, uint8_t reg)
+amd_pmio_read(struct resource *res, uint8_t reg)
 {
 	bus_write_1(res, 0, reg);	/* Index */
 	return (bus_read_1(res, 1));	/* Data */
@@ -128,27 +128,18 @@ sb8xx_pmio_read(struct resource *res, uint8_t reg)
 static int
 sb8xx_attach(device_t dev)
 {
-	static const int	AMDSB_PMIO_INDEX = 0xcd6;
-	static const int	AMDSB_PMIO_WIDTH = 2;
-	static const int	AMDSB8_SMBUS_ADDR = 0x2c;
-	static const int		AMDSB8_SMBUS_EN = 0x01;
-	static const int		AMDSB8_SMBUS_ADDR_MASK = ~0x1fu;
 	static const int	AMDSB_SMBIO_WIDTH = 0x14;
-	static const int	AMDSB_SMBUS_CFG = 0x10;
-	static const int		AMDSB_SMBUS_IRQ = 0x01;
-	static const int		AMDSB_SMBUS_REV_MASK = ~0x0fu;
-	static const int		AMDSB_SMBUS_REV_SHIFT = 4;
-	static const int	AMDSB_IO_RID = 0;
-
 	struct intsmb_softc	*sc;
 	struct resource		*res;
+	uint32_t		devid;
+	uint8_t			revid;
 	uint16_t		addr;
-	uint8_t			cfg;
 	int			rid;
 	int			rc;
+	bool			enabled;
 
 	sc = device_get_softc(dev);
-	rid = AMDSB_IO_RID;
+	rid = 0;
 	rc = bus_set_resource(dev, SYS_RES_IOPORT, rid, AMDSB_PMIO_INDEX,
 	    AMDSB_PMIO_WIDTH);
 	if (rc != 0) {
@@ -156,26 +147,38 @@ sb8xx_attach(device_t dev)
 		return (ENXIO);
 	}
 	res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
-	    RF_ACTIVE | RF_SHAREABLE);
+	    RF_ACTIVE);
 	if (res == NULL) {
 		device_printf(dev, "bus_alloc_resource for PM IO failed\n");
 		return (ENXIO);
 	}
 
-	addr = sb8xx_pmio_read(res, AMDSB8_SMBUS_ADDR + 1);
-	addr <<= 8;
-	addr |= sb8xx_pmio_read(res, AMDSB8_SMBUS_ADDR);
+	devid = pci_get_devid(dev);
+	revid = pci_get_revid(dev);
+	if (devid == AMDSB_SMBUS_DEVID ||
+	    (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
+	    (devid == AMDCZ_SMBUS_DEVID  && revid < AMDCZ49_SMBUS_REVID)) {
+		addr = amd_pmio_read(res, AMDSB8_PM_SMBUS_EN + 1);
+		addr <<= 8;
+		addr |= amd_pmio_read(res, AMDSB8_PM_SMBUS_EN);
+		enabled = (addr & AMDSB8_SMBUS_EN) != 0;
+		addr &= AMDSB8_SMBUS_ADDR_MASK;
+	} else {
+		addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN0);
+		enabled = (addr & AMDFCH41_SMBUS_EN) != 0;
+		addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN1);
+		addr <<= 8;
+	}
 
 	bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
 	bus_delete_resource(dev, SYS_RES_IOPORT, rid);
 
-	if ((addr & AMDSB8_SMBUS_EN) == 0) {
-		device_printf(dev, "SB8xx SMBus not enabled\n");
+	if (!enabled) {
+		device_printf(dev, "SB8xx/SB9xx/FCH SMBus not enabled\n");
 		return (ENXIO);
 	}
 
-	addr &= AMDSB8_SMBUS_ADDR_MASK;
-	sc->io_rid = AMDSB_IO_RID;
+	sc->io_rid = 0;
 	rc = bus_set_resource(dev, SYS_RES_IOPORT, sc->io_rid, addr,
 	    AMDSB_SMBIO_WIDTH);
 	if (rc != 0) {
@@ -187,15 +190,8 @@ sb8xx_attach(device_t dev)
 		return (ENXIO);
 	}
 	sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
-	    RF_ACTIVE | RF_SHAREABLE);
-	cfg = bus_read_1(sc->io_res, AMDSB_SMBUS_CFG);
-
+	    RF_ACTIVE);
 	sc->poll = 1;
-	device_printf(dev, "intr %s disabled ",
-	    (cfg & AMDSB_SMBUS_IRQ) != 0 ? "IRQ" : "SMI");
-	printf("revision %d\n",
-	    (cfg & AMDSB_SMBUS_REV_MASK) >> AMDSB_SMBUS_REV_SHIFT);
-
 	return (0);
 }
 
@@ -237,11 +233,12 @@ intsmb_attach(device_t dev)
 		sc->cfg_irq9 = 1;
 		break;
 #endif
-	case 0x43851002:
-		if (pci_get_revid(dev) >= 0x40)
+	case AMDSB_SMBUS_DEVID:
+		if (pci_get_revid(dev) >= AMDSB8_SMBUS_REVID)
 			sc->sb8xx = 1;
 		break;
-	case 0x780b1022:
+	case AMDFCH_SMBUS_DEVID:
+	case AMDCZ_SMBUS_DEVID:
 		sc->sb8xx = 1;
 		break;
 	}
diff --git a/sys/dev/iwm/if_iwm.c b/sys/dev/iwm/if_iwm.c
index 2316cdfcf486..ff6e00cc06b9 100644
--- a/sys/dev/iwm/if_iwm.c
+++ b/sys/dev/iwm/if_iwm.c
@@ -234,13 +234,9 @@ static int	iwm_dma_contig_alloc(bus_dma_tag_t, struct iwm_dma_info *,
                                      bus_size_t, bus_size_t);
 static void	iwm_dma_contig_free(struct iwm_dma_info *);
 static int	iwm_alloc_fwmem(struct iwm_softc *);
-static void	iwm_free_fwmem(struct iwm_softc *);
 static int	iwm_alloc_sched(struct iwm_softc *);
-static void	iwm_free_sched(struct iwm_softc *);
 static int	iwm_alloc_kw(struct iwm_softc *);
-static void	iwm_free_kw(struct iwm_softc *);
 static int	iwm_alloc_ict(struct iwm_softc *);
-static void	iwm_free_ict(struct iwm_softc *);
 static int	iwm_alloc_rx_ring(struct iwm_softc *, struct iwm_rx_ring *);
 static void	iwm_disable_rx_dma(struct iwm_softc *);
 static void	iwm_reset_rx_ring(struct iwm_softc *, struct iwm_rx_ring *);
@@ -312,7 +308,8 @@ static int	iwm_mvm_get_signal_strength(struct iwm_softc *,
 static void	iwm_mvm_rx_rx_phy_cmd(struct iwm_softc *,
                                       struct iwm_rx_packet *,
                                       struct iwm_rx_data *);
-static int	iwm_get_noise(const struct iwm_mvm_statistics_rx_non_phy *);
+static int	iwm_get_noise(struct iwm_softc *sc,
+		    const struct iwm_mvm_statistics_rx_non_phy *);
 static void	iwm_mvm_rx_rx_mpdu(struct iwm_softc *, struct iwm_rx_packet *,
                                    struct iwm_rx_data *);
 static int	iwm_mvm_rx_tx_cmd_single(struct iwm_softc *,
@@ -327,11 +324,13 @@ static void	iwm_update_sched(struct iwm_softc *, int, int, uint8_t,
 #endif
 static const struct iwm_rate *
 	iwm_tx_fill_cmd(struct iwm_softc *, struct iwm_node *,
-			struct ieee80211_frame *, struct iwm_tx_cmd *);
+			struct mbuf *, struct iwm_tx_cmd *);
 static int	iwm_tx(struct iwm_softc *, struct mbuf *,
                        struct ieee80211_node *, int);
 static int	iwm_raw_xmit(struct ieee80211_node *, struct mbuf *,
 			     const struct ieee80211_bpf_params *);
+static int	iwm_mvm_flush_tx_path(struct iwm_softc *sc,
+				      uint32_t tfd_msk, uint32_t flags);
 static int	iwm_mvm_send_add_sta_cmd_status(struct iwm_softc *,
 					        struct iwm_mvm_add_sta_cmd_v7 *,
                                                 int *);
@@ -440,11 +439,12 @@ iwm_firmware_store_section(struct iwm_softc *sc,
 	fwone->fws_len = dlen - sizeof(uint32_t);
 
 	fws->fw_count++;
-	fws->fw_totlen += fwone->fws_len;
 
 	return 0;
 }
 
+#define IWM_DEFAULT_SCAN_CHANNELS 40
+
 /* iwlwifi: iwl-drv.c */
 struct iwm_tlv_calib_data {
 	uint32_t ucode_type;
@@ -521,7 +521,7 @@ iwm_read_firmware(struct iwm_softc *sc, enum iwm_ucode_type ucode_type)
 
 	/* (Re-)Initialize default values. */
 	sc->sc_capaflags = 0;
-	sc->sc_capa_n_scan_channels = IWM_MAX_NUM_SCAN_CHANNELS;
+	sc->sc_capa_n_scan_channels = IWM_DEFAULT_SCAN_CHANNELS;
 	memset(sc->sc_enabled_capa, 0, sizeof(sc->sc_enabled_capa));
 	memset(sc->sc_fw_mcc, 0, sizeof(sc->sc_fw_mcc));
 
@@ -738,7 +738,7 @@ iwm_read_firmware(struct iwm_softc *sc, enum iwm_ucode_type ucode_type)
 			}
 			capa = (const struct iwm_ucode_capa *)tlv_data;
 			idx = le32toh(capa->api_index);
-			if (idx > howmany(IWM_NUM_UCODE_TLV_CAPA, 32)) {
+			if (idx >= howmany(IWM_NUM_UCODE_TLV_CAPA, 32)) {
 				device_printf(sc->sc_dev,
 				    "unsupported API index %d\n", idx);
 				goto parse_out;
@@ -901,12 +901,6 @@ iwm_alloc_fwmem(struct iwm_softc *sc)
 	    sc->sc_fwdmasegsz, 16);
 }
 
-static void
-iwm_free_fwmem(struct iwm_softc *sc)
-{
-	iwm_dma_contig_free(&sc->fw_dma);
-}
-
 /* tx scheduler rings.  not used? */
 static int
 iwm_alloc_sched(struct iwm_softc *sc)
@@ -916,12 +910,6 @@ iwm_alloc_sched(struct iwm_softc *sc)
 	    nitems(sc->txq) * sizeof(struct iwm_agn_scd_bc_tbl), 1024);
 }
 
-static void
-iwm_free_sched(struct iwm_softc *sc)
-{
-	iwm_dma_contig_free(&sc->sched_dma);
-}
-
 /* keep-warm page is used internally by the card.  see iwl-fh.h for more info */
 static int
 iwm_alloc_kw(struct iwm_softc *sc)
@@ -929,12 +917,6 @@ iwm_alloc_kw(struct iwm_softc *sc)
 	return iwm_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, 4096, 4096);
 }
 
-static void
-iwm_free_kw(struct iwm_softc *sc)
-{
-	iwm_dma_contig_free(&sc->kw_dma);
-}
-
 /* interrupt cause table */
 static int
 iwm_alloc_ict(struct iwm_softc *sc)
@@ -943,12 +925,6 @@ iwm_alloc_ict(struct iwm_softc *sc)
 	    IWM_ICT_SIZE, 1<<IWM_ICT_PADDR_SHIFT);
 }
 
-static void
-iwm_free_ict(struct iwm_softc *sc)
-{
-	iwm_dma_contig_free(&sc->ict_dma);
-}
-
 static int
 iwm_alloc_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring)
 {
@@ -2176,11 +2152,6 @@ iwm_parse_nvm_data(struct iwm_softc *sc,
 		memcpy(data->nvm_ch_flags, &regulatory[IWM_NVM_CHANNELS_8000],
 		    IWM_NUM_CHANNELS_8000 * sizeof(uint16_t));
 	}
-	data->calib_version = 255;   /* TODO:
-					this value will prevent some checks from
-					failing, we need to check if this
-					field is still needed, and if it does,
-					where is it in the NVM */
 
 	return 0;
 }
@@ -2701,6 +2672,15 @@ iwm_run_init_mvm_ucode(struct iwm_softc *sc, int justnvm)
 	if (error != 0)
 		return error;
 
+	IWM_DPRINTF(sc, IWM_DEBUG_RESET,
+	    "%s: phy_txant=0x%08x, nvm_valid_tx_ant=0x%02x, valid=0x%02x\n",
+	    __func__,
+	    ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_TX_CHAIN)
+	      >> IWM_FW_PHY_CFG_TX_CHAIN_POS),
+	    sc->sc_nvm.valid_tx_ant,
+	    iwm_fw_valid_tx_ant(sc));
+
+
 	/* Send TX valid antennas before triggering calibrations */
 	if ((error = iwm_send_tx_ant_cfg(sc, iwm_fw_valid_tx_ant(sc))) != 0) {
 		device_printf(sc->sc_dev,
@@ -2871,21 +2851,34 @@ iwm_mvm_rx_rx_phy_cmd(struct iwm_softc *sc,
  * Retrieve the average noise (in dBm) among receivers.
  */
 static int
-iwm_get_noise(const struct iwm_mvm_statistics_rx_non_phy *stats)
+iwm_get_noise(struct iwm_softc *sc,
+    const struct iwm_mvm_statistics_rx_non_phy *stats)
 {
 	int i, total, nbant, noise;
 
 	total = nbant = noise = 0;
 	for (i = 0; i < 3; i++) {
 		noise = le32toh(stats->beacon_silence_rssi[i]) & 0xff;
+		IWM_DPRINTF(sc, IWM_DEBUG_RECV, "%s: i=%d, noise=%d\n",
+		    __func__,
+		    i,
+		    noise);
+
 		if (noise) {
 			total += noise;
 			nbant++;
 		}
 	}
 
+	IWM_DPRINTF(sc, IWM_DEBUG_RECV, "%s: nbant=%d, total=%d\n",
+	    __func__, nbant, total);
+#if 0
 	/* There should be at least one antenna but check anyway. */
 	return (nbant == 0) ? -127 : (total / nbant) - 107;
+#else
+	/* For now, just hard-code it to -96 to be safe */
+	return (-96);
+#endif
 }
 
 /*
@@ -2940,8 +2933,15 @@ iwm_mvm_rx_rx_mpdu(struct iwm_softc *sc,
 	} else {
 		rssi = iwm_mvm_calc_rssi(sc, phy_info);
 	}
-	rssi = (0 - IWM_MIN_DBM) + rssi;	/* normalize */
-	rssi = MIN(rssi, sc->sc_max_rssi);	/* clip to max. 100% */
+
+	/* Note: RSSI is absolute (ie a -ve value) */
+	if (rssi < IWM_MIN_DBM)
+		rssi = IWM_MIN_DBM;
+	else if (rssi > IWM_MAX_DBM)
+		rssi = IWM_MAX_DBM;
+
+	/* Map it to relative value */
+	rssi = rssi - sc->sc_noise;
 
 	/* replenish ring for the buffer we're going to feed to the sharks */
 	if (iwm_rx_addbuf(sc, IWM_RBUF_SIZE, sc->rxq.cur) != 0) {
@@ -2950,6 +2950,9 @@ iwm_mvm_rx_rx_mpdu(struct iwm_softc *sc,
 		return;
 	}
 
+	IWM_DPRINTF(sc, IWM_DEBUG_RECV,
+	    "%s: rssi=%d, noise=%d\n", __func__, rssi, sc->sc_noise);
+
 	ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
 
 	IWM_DPRINTF(sc, IWM_DEBUG_RECV,
@@ -2970,7 +2973,9 @@ iwm_mvm_rx_rx_mpdu(struct iwm_softc *sc,
 	} else {
 		rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, IEEE80211_CHAN_5GHZ);
 	}
-	rxs.rssi = rssi - sc->sc_noise;
+
+	/* rssi is in 1/2db units */
+	rxs.rssi = rssi * 2;
 	rxs.nf = sc->sc_noise;
 
 	if (ieee80211_radiotap_active_vap(vap)) {
@@ -3191,34 +3196,76 @@ iwm_tx_rateidx_lookup(struct iwm_softc *sc, struct iwm_node *in,
 		if (rate == r)
 			return (i);
 	}
+
+	IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE,
+	    "%s: couldn't find an entry for rate=%d\n",
+	    __func__,
+	    rate);
+
 	/* XXX Return the first */
 	/* XXX TODO: have it return the /lowest/ */
 	return (0);
 }
 
+static int
+iwm_tx_rateidx_global_lookup(struct iwm_softc *sc, uint8_t rate)
+{
+	int i;
+
+	for (i = 0; i < nitems(iwm_rates); i++) {
+		if (iwm_rates[i].rate == rate)
+			return (i);
+	}
+	/* XXX error? */
+	IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE,
+	    "%s: couldn't find an entry for rate=%d\n",
+	    __func__,
+	    rate);
+	return (0);
+}
+
 /*
  * Fill in the rate related information for a transmit command.
  */
 static const struct iwm_rate *
 iwm_tx_fill_cmd(struct iwm_softc *sc, struct iwm_node *in,
-	struct ieee80211_frame *wh, struct iwm_tx_cmd *tx)
+	struct mbuf *m, struct iwm_tx_cmd *tx)
 {
-	struct ieee80211com *ic = &sc->sc_ic;
 	struct ieee80211_node *ni = &in->in_ni;
+	struct ieee80211_frame *wh;
+	const struct ieee80211_txparam *tp = ni->ni_txparms;
 	const struct iwm_rate *rinfo;
-	int type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
+	int type;
 	int ridx, rate_flags;
 
+	wh = mtod(m, struct ieee80211_frame *);
+	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
+
 	tx->rts_retry_limit = IWM_RTS_DFAULT_RETRY_LIMIT;
 	tx->data_retry_limit = IWM_DEFAULT_TX_RETRY;
 
-	/*
-	 * XXX TODO: everything about the rate selection here is terrible!
-	 */
-
-	if (type == IEEE80211_FC0_TYPE_DATA) {
+	if (type == IEEE80211_FC0_TYPE_MGT) {
+		ridx = iwm_tx_rateidx_global_lookup(sc, tp->mgmtrate);
+		IWM_DPRINTF(sc, IWM_DEBUG_TXRATE,
+		    "%s: MGT (%d)\n", __func__, tp->mgmtrate);
+	} else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
+		ridx = iwm_tx_rateidx_global_lookup(sc, tp->mcastrate);
+		IWM_DPRINTF(sc, IWM_DEBUG_TXRATE,
+		    "%s: MCAST (%d)\n", __func__, tp->mcastrate);
+	} else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
+		ridx = iwm_tx_rateidx_global_lookup(sc, tp->ucastrate);
+		IWM_DPRINTF(sc, IWM_DEBUG_TXRATE,
+		    "%s: FIXED_RATE (%d)\n", __func__, tp->ucastrate);
+	} else if (m->m_flags & M_EAPOL) {
+		ridx = iwm_tx_rateidx_global_lookup(sc, tp->mgmtrate);
+		IWM_DPRINTF(sc, IWM_DEBUG_TXRATE,
+		    "%s: EAPOL\n", __func__);
+	} else if (type == IEEE80211_FC0_TYPE_DATA) {
 		int i;
+
 		/* for data frames, use RS table */
+		IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: DATA\n", __func__);
+		/* XXX pass pktlen */
 		(void) ieee80211_ratectl_rate(ni, NULL, 0);
 		i = iwm_tx_rateidx_lookup(sc, in, ni->ni_txrate);
 		ridx = in->in_ridx[i];
@@ -3226,33 +3273,20 @@ iwm_tx_fill_cmd(struct iwm_softc *sc, struct iwm_node *in,
 		/* This is the index into the programmed table */
 		tx->initial_rate_index = i;
 		tx->tx_flags |= htole32(IWM_TX_CMD_FLG_STA_RATE);
+
 		IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE,
 		    "%s: start with i=%d, txrate %d\n",
 		    __func__, i, iwm_rates[ridx].rate);
 	} else {
-		/*
-		 * For non-data, use the lowest supported rate for the given
-		 * operational mode.
-		 *
-		 * Note: there may not be any rate control information available.
-		 * This driver currently assumes if we're transmitting data
-		 * frames, use the rate control table.  Grr.
-		 *
-		 * XXX TODO: use the configured rate for the traffic type!
-		 * XXX TODO: this should be per-vap, not curmode; as we later
-		 * on we'll want to handle off-channel stuff (eg TDLS).
-		 */
-		if (ic->ic_curmode == IEEE80211_MODE_11A) {
-			/*
-			 * XXX this assumes the mode is either 11a or not 11a;
-			 * definitely won't work for 11n.
-			 */
-			ridx = IWM_RIDX_OFDM;
-		} else {
-			ridx = IWM_RIDX_CCK;
-		}
+		ridx = iwm_tx_rateidx_global_lookup(sc, tp->mgmtrate);
+		IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: DEFAULT (%d)\n",
+		    __func__, tp->mgmtrate);
 	}
 
+	IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE,
+	    "%s: frame type=%d txrate %d\n",
+	        __func__, type, iwm_rates[ridx].rate);
+
 	rinfo = &iwm_rates[ridx];
 
 	IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: ridx=%d; rate=%d, CCK=%d\n",
@@ -3312,7 +3346,7 @@ iwm_tx(struct iwm_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac)
 	tx = (void *)cmd->data;
 	memset(tx, 0, sizeof(*tx));
 
-	rinfo = iwm_tx_fill_cmd(sc, in, wh, tx);
+	rinfo = iwm_tx_fill_cmd(sc, in, m, tx);
 
 	/* Encrypt the frame if need be. */
 	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
@@ -3523,7 +3557,6 @@ iwm_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
  * mvm/tx.c
  */
 
-#if 0
 /*
  * Note that there are transports that buffer frames before they reach
  * the firmware. This means that after flush_tx_path is called, the
@@ -3533,23 +3566,21 @@ iwm_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
  * 3) wait for the transport queues to be empty
  */
 int
-iwm_mvm_flush_tx_path(struct iwm_softc *sc, int tfd_msk, int sync)
+iwm_mvm_flush_tx_path(struct iwm_softc *sc, uint32_t tfd_msk, uint32_t flags)
 {
+	int ret;
 	struct iwm_tx_path_flush_cmd flush_cmd = {
 		.queues_ctl = htole32(tfd_msk),
 		.flush_ctl = htole16(IWM_DUMP_TX_FIFO_FLUSH),
 	};
-	int ret;
 
-	ret = iwm_mvm_send_cmd_pdu(sc, IWM_TXPATH_FLUSH,
-	    sync ? IWM_CMD_SYNC : IWM_CMD_ASYNC,
+	ret = iwm_mvm_send_cmd_pdu(sc, IWM_TXPATH_FLUSH, flags,
 	    sizeof(flush_cmd), &flush_cmd);
 	if (ret)
                 device_printf(sc->sc_dev,
 		    "Flushing tx queue failed: %d\n", ret);
 	return ret;
 }
-#endif
 
 /*
  * BEGIN mvm/sta.c
@@ -3905,6 +3936,8 @@ iwm_assoc(struct ieee80211vap *vap, struct iwm_softc *sc)
 static int
 iwm_release(struct iwm_softc *sc, struct iwm_node *in)
 {
+	uint32_t tfd_msk;
+
 	/*
 	 * Ok, so *technically* the proper set of calls for going
 	 * from RUN back to SCAN is:
@@ -3924,7 +3957,18 @@ iwm_release(struct iwm_softc *sc, struct iwm_node *in)
 	 * back to nothing anyway, we'll just do a complete device reset.
 	 * Up your's, device!
 	 */
-	/* iwm_mvm_flush_tx_path(sc, 0xf, 1); */
+	/*
+	 * Just using 0xf for the queues mask is fine as long as we only
+	 * get here from RUN state.
+	 */
+	tfd_msk = 0xf;
+	mbufq_drain(&sc->sc_snd);
+	iwm_mvm_flush_tx_path(sc, tfd_msk, IWM_CMD_SYNC);
+	/*
+	 * We seem to get away with just synchronously sending the
+	 * IWM_TXPATH_FLUSH command.
+	 */
+//	iwm_trans_wait_tx_queue_empty(sc, tfd_msk);
 	iwm_stop_device(sc);
 	iwm_init_hw(sc);
 	if (in)
@@ -3974,7 +4018,7 @@ iwm_setrates(struct iwm_softc *sc, struct iwm_node *in)
 	struct iwm_lq_cmd *lq = &in->in_lq;
 	int nrates = ni->ni_rates.rs_nrates;
 	int i, ridx, tab = 0;
-	int txant = 0;
+//	int txant = 0;
 
 	if (nrates > nitems(lq->rs_table)) {
 		device_printf(sc->sc_dev,
@@ -4056,11 +4100,14 @@ iwm_setrates(struct iwm_softc *sc, struct iwm_node *in)
 	for (i = 0; i < nrates; i++) {
 		int nextant;
 
+#if 0
 		if (txant == 0)
 			txant = iwm_fw_valid_tx_ant(sc);
 		nextant = 1<<(ffs(txant)-1);
 		txant &= ~nextant;
-
+#else
+		nextant = iwm_fw_valid_tx_ant(sc);
+#endif
 		/*
 		 * Map the rate id into a rate index into
 		 * our hardware table containing the
@@ -4131,7 +4178,17 @@ iwm_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
 		if (((in = IWM_NODE(vap->iv_bss)) != NULL))
 			in->in_assoc = 0;
 
-		iwm_release(sc, NULL);
+		if (nstate == IEEE80211_S_INIT) {
+			IWM_UNLOCK(sc);
+			IEEE80211_LOCK(ic);
+			error = ivp->iv_newstate(vap, nstate, arg);
+			IEEE80211_UNLOCK(ic);
+			IWM_LOCK(sc);
+			iwm_release(sc, NULL);
+			IWM_UNLOCK(sc);
+			IEEE80211_LOCK(ic);
+			return error;
+		}
 
 		/*
 		 * It's impossible to directly go RUN->SCAN. If we iwm_release()
@@ -5172,7 +5229,7 @@ iwm_notif_intr(struct iwm_softc *sc)
 			struct iwm_notif_statistics *stats;
 			SYNC_RESP_STRUCT(stats, pkt);
 			memcpy(&sc->sc_stats, stats, sizeof(sc->sc_stats));
-			sc->sc_noise = iwm_get_noise(&stats->rx.general);
+			sc->sc_noise = iwm_get_noise(sc, &stats->rx.general);
 			break; }
 
 		case IWM_NVM_ACCESS_CMD:
@@ -5209,7 +5266,6 @@ iwm_notif_intr(struct iwm_softc *sc)
 		case IWM_PHY_CONTEXT_CMD:
 		case IWM_BINDING_CONTEXT_CMD:
 		case IWM_TIME_EVENT_CMD:
-		case IWM_SCAN_REQUEST_CMD:
 		case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_CFG_CMD):
 		case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_REQ_UMAC):
 		case IWM_SCAN_OFFLOAD_REQUEST_CMD:
@@ -5736,7 +5792,7 @@ iwm_attach(device_t dev)
 				   IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 				   IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 				   25000);
-		if (ret < 0) {
+		if (!ret) {
 			device_printf(sc->sc_dev,
 			    "Failed to wake up the nic\n");
 			goto fail;
@@ -5823,8 +5879,12 @@ iwm_attach(device_t dev)
 		sc->sc_phyctxt[i].channel = NULL;
 	}
 
+	/* Default noise floor */
+	sc->sc_noise = -96;
+
 	/* Max RSSI */
 	sc->sc_max_rssi = IWM_MAX_DBM - IWM_MIN_DBM;
+
 	sc->sc_preinit_hook.ich_func = iwm_preinit;
 	sc->sc_preinit_hook.ich_arg = sc;
 	if (config_intrhook_establish(&sc->sc_preinit_hook) != 0) {
@@ -6144,13 +6204,10 @@ iwm_detach_local(struct iwm_softc *sc, int do_net80211)
 		iwm_fw_info_free(fw);
 
 	/* Free scheduler */
-	iwm_free_sched(sc);
-	if (sc->ict_dma.vaddr != NULL)
-		iwm_free_ict(sc);
-	if (sc->kw_dma.vaddr != NULL)
-		iwm_free_kw(sc);
-	if (sc->fw_dma.vaddr != NULL)
-		iwm_free_fwmem(sc);
+	iwm_dma_contig_free(&sc->sched_dma);
+	iwm_dma_contig_free(&sc->ict_dma);
+	iwm_dma_contig_free(&sc->kw_dma);
+	iwm_dma_contig_free(&sc->fw_dma);
 
 	/* Finished with the hardware - detach things */
 	iwm_pci_detach(dev);
diff --git a/sys/dev/iwm/if_iwm_time_event.c b/sys/dev/iwm/if_iwm_time_event.c
index 706b6c62c54d..9655c1e9192c 100644
--- a/sys/dev/iwm/if_iwm_time_event.c
+++ b/sys/dev/iwm/if_iwm_time_event.c
@@ -266,7 +266,7 @@ iwm_mvm_protect_session(struct iwm_softc *sc, struct iwm_node *in,
 	time_cmd.duration = htole32(duration);
 	time_cmd.repeat = 1;
 	time_cmd.policy
-	    = htole32(IWM_TE_V2_NOTIF_HOST_EVENT_START |
+	    = htole16(IWM_TE_V2_NOTIF_HOST_EVENT_START |
 	        IWM_TE_V2_NOTIF_HOST_EVENT_END |
 		IWM_T2_V2_START_IMMEDIATELY);
 
diff --git a/sys/dev/iwm/if_iwmreg.h b/sys/dev/iwm/if_iwmreg.h
index 96a9e9eed9c9..82139a369fde 100644
--- a/sys/dev/iwm/if_iwmreg.h
+++ b/sys/dev/iwm/if_iwmreg.h
@@ -1839,11 +1839,9 @@ enum {
 	IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
 
 	/* Scanning */
-	IWM_SCAN_REQUEST_CMD = 0x80,
 	IWM_SCAN_ABORT_CMD = 0x81,
 	IWM_SCAN_START_NOTIFICATION = 0x82,
 	IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
-	IWM_SCAN_COMPLETE_NOTIFICATION = 0x84,
 
 	/* NVM */
 	IWM_NVM_ACCESS_CMD = 0x88,
@@ -3251,7 +3249,7 @@ enum iwm_sf_scenario {
  * @full_on_timeouts: timer values for each scenario in full on state.
  */
 struct iwm_sf_cfg_cmd {
-	enum iwm_sf_state state;
+	uint32_t state;
 	uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
 	uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
 	uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
@@ -4767,53 +4765,11 @@ struct iwm_scd_txq_cfg_rsp {
 /* Masks for iwm_scan_channel.type flags */
 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE	(1 << 0)
 #define IWM_SCAN_CHANNEL_NSSIDS(x)	(((1 << (x)) - 1) << 1)
-#define IWM_SCAN_CHANNEL_NARROW_BAND	(1 << 22)
 
 /* Max number of IEs for direct SSID scans in a command */
 #define IWM_PROBE_OPTION_MAX		20
 
 /**
- * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table
- * @channel: band is selected by iwm_scan_cmd "flags" field
- * @tx_gain: gain for analog radio
- * @dsp_atten: gain for DSP
- * @active_dwell: dwell time for active scan in TU, typically 5-50
- * @passive_dwell: dwell time for passive scan in TU, typically 20-500
- * @type: type is broken down to these bits:
- *	bit 0: 0 = passive, 1 = active
- *	bits 1-20: SSID direct bit map. If any of these bits is set then
- *		the corresponding SSID IE is transmitted in probe request
- *		(bit i adds IE in position i to the probe request)
- *	bit 22: channel width, 0 = regular, 1 = TGj narrow channel
- *
- * @iteration_count:
- * @iteration_interval:
- * This struct is used once for each channel in the scan list.
- * Each channel can independently select:
- * 1)  SSID for directed active scans
- * 2)  Txpower setting (for rate specified within Tx command)
- * 3)  How long to stay on-channel (behavior may be modified by quiet_time,
- *     quiet_plcp_th, good_CRC_th)
- *
- * To avoid uCode errors, make sure the following are true (see comments
- * under struct iwm_scan_cmd about max_out_time and quiet_time):
- * 1)  If using passive_dwell (i.e. passive_dwell != 0):
- *     active_dwell <= passive_dwell (< max_out_time if max_out_time != 0)
- * 2)  quiet_time <= active_dwell
- * 3)  If restricting off-channel time (i.e. max_out_time !=0):
- *     passive_dwell < max_out_time
- *     active_dwell < max_out_time
- */
-struct iwm_scan_channel {
-	uint32_t type;
-	uint16_t channel;
-	uint16_t iteration_count;
-	uint32_t iteration_interval;
-	uint16_t active_dwell;
-	uint16_t passive_dwell;
-} __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */
-
-/**
  * struct iwm_ssid_ie - directed scan network information element
  *
  * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
@@ -4828,7 +4784,6 @@ struct iwm_ssid_ie {
 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
 
 /* scan offload */
-#define IWM_MAX_SCAN_CHANNELS		40
 #define IWM_SCAN_MAX_BLACKLIST_LEN	64
 #define IWM_SCAN_SHORT_BLACKLIST_LEN	16
 #define IWM_SCAN_MAX_PROFILES		11
@@ -4845,48 +4800,6 @@ struct iwm_ssid_ie {
 #define IWM_MAX_SCHED_SCAN_PLANS 2
 
 /**
- * iwm_scan_flags - masks for scan command flags
- *@IWM_SCAN_FLAGS_PERIODIC_SCAN:
- *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX:
- *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND:
- *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND:
- *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN:
- *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active
- *	in the past hour, even if they are marked as passive.
- */
-enum iwm_scan_flags {
-	IWM_SCAN_FLAGS_PERIODIC_SCAN			= (1 << 0),
-	IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX	= (1 << 1),
-	IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND		= (1 << 2),
-	IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND		= (1 << 3),
-	IWM_SCAN_FLAGS_FRAGMENTED_SCAN			= (1 << 4),
-	IWM_SCAN_FLAGS_PASSIVE2ACTIVE			= (1 << 5),
-};
-
-/**
- * enum iwm_scan_type - Scan types for scan command
- * @IWM_SCAN_TYPE_FORCED:
- * @IWM_SCAN_TYPE_BACKGROUND:
- * @IWM_SCAN_TYPE_OS:
- * @IWM_SCAN_TYPE_ROAMING:
- * @IWM_SCAN_TYPE_ACTION:
- * @IWM_SCAN_TYPE_DISCOVERY:
- * @IWM_SCAN_TYPE_DISCOVERY_FORCED:
- */
-enum iwm_scan_type {
-	IWM_SCAN_TYPE_FORCED		= 0,
-	IWM_SCAN_TYPE_BACKGROUND	= 1,
-	IWM_SCAN_TYPE_OS		= 2,
-	IWM_SCAN_TYPE_ROAMING		= 3,
-	IWM_SCAN_TYPE_ACTION		= 4,
-	IWM_SCAN_TYPE_DISCOVERY		= 5,
-	IWM_SCAN_TYPE_DISCOVERY_FORCED	= 6,
-}; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */
-
-/* Maximal number of channels to scan */
-#define IWM_MAX_NUM_SCAN_CHANNELS 0x24
-
-/**
  * iwm_scan_schedule_lmac - schedule of scan offload
  * @delay:		delay between iterations, in seconds.
  * @iterations:		num of scan iterations
@@ -5076,52 +4989,6 @@ struct iwm_periodic_scan_complete {
 	uint32_t reserved;
 } __packed;
 
-/* Response to scan request contains only status with one of these values */
-#define IWM_SCAN_RESPONSE_OK	0x1
-#define IWM_SCAN_RESPONSE_ERROR	0x2
-
-/*
- * IWM_SCAN_ABORT_CMD = 0x81
- * When scan abort is requested, the command has no fields except the common
- * header. The response contains only a status with one of these values.
- */
-#define IWM_SCAN_ABORT_POSSIBLE	0x1
-#define IWM_SCAN_ABORT_IGNORED	0x2 /* no pending scans */
-
-/* TODO: complete documentation */
-#define  IWM_SCAN_OWNER_STATUS 0x1
-#define  IWM_MEASURE_OWNER_STATUS 0x2
-
-/**
- * struct iwm_scan_start_notif - notifies start of scan in the device
- * ( IWM_SCAN_START_NOTIFICATION = 0x82 )
- * @tsf_low: TSF timer (lower half) in usecs
- * @tsf_high: TSF timer (higher half) in usecs
- * @beacon_timer: structured as follows:
- *	bits 0:19 - beacon interval in usecs
- *	bits 20:23 - reserved (0)
- *	bits 24:31 - number of beacons
- * @channel: which channel is scanned
- * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
- * @status: one of *_OWNER_STATUS
- */
-struct iwm_scan_start_notif {
-	uint32_t tsf_low;
-	uint32_t tsf_high;
-	uint32_t beacon_timer;
-	uint8_t channel;
-	uint8_t band;
-	uint8_t reserved[2];
-	uint32_t status;
-} __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */
-
-/* scan results probe_status first bit indicates success */
-#define IWM_SCAN_PROBE_STATUS_OK	0
-#define IWM_SCAN_PROBE_STATUS_TX_FAILED	(1 << 0)
-/* error statuses combined with TX_FAILED */
-#define IWM_SCAN_PROBE_STATUS_FAIL_TTL	(1 << 1)
-#define IWM_SCAN_PROBE_STATUS_FAIL_BT	(1 << 2)
-
 /* How many statistics are gathered for each channel */
 #define IWM_SCAN_RESULTS_STATISTICS 1
 
@@ -5176,27 +5043,6 @@ struct iwm_scan_results_notif {
 	uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
 
-/**
- * struct iwm_scan_complete_notif - notifies end of scanning (all channels)
- * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 )
- * @scanned_channels: number of channels scanned (and number of valid results)
- * @status: one of IWM_SCAN_COMP_STATUS_*
- * @bt_status: BT on/off status
- * @last_channel: last channel that was scanned
- * @tsf_low: TSF timer (lower half) in usecs
- * @tsf_high: TSF timer (higher half) in usecs
- * @results: all scan results, only "scanned_channels" of them are valid
- */
-struct iwm_scan_complete_notif {
-	uint8_t scanned_channels;
-	uint8_t status;
-	uint8_t bt_status;
-	uint8_t last_channel;
-	uint32_t tsf_low;
-	uint32_t tsf_high;
-	struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS];
-} __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */
-
 enum iwm_scan_framework_client {
 	IWM_SCAN_CLIENT_SCHED_SCAN	= (1 << 0),
 	IWM_SCAN_CLIENT_NETDETECT	= (1 << 1),
@@ -5204,83 +5050,6 @@ enum iwm_scan_framework_client {
 };
 
 /**
- * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6
- * @scan_flags:		see enum iwm_scan_flags
- * @channel_count:	channels in channel list
- * @quiet_time:		dwell time, in milisiconds, on quiet channel
- * @quiet_plcp_th:	quiet channel num of packets threshold
- * @good_CRC_th:	passive to active promotion threshold
- * @rx_chain:		RXON rx chain.
- * @max_out_time:	max uSec to be out of assoceated channel
- * @suspend_time:	pause scan this long when returning to service channel
- * @flags:		RXON flags
- * @filter_flags:	RXONfilter
- * @tx_cmd:		tx command for active scan; for 2GHz and for 5GHz.
- * @direct_scan:	list of SSIDs for directed active scan
- * @scan_type:		see enum iwm_scan_type.
- * @rep_count:		repetition count for each scheduled scan iteration.
- */
-struct iwm_scan_offload_cmd {
-	uint16_t len;
-	uint8_t scan_flags;
-	uint8_t channel_count;
-	uint16_t quiet_time;
-	uint16_t quiet_plcp_th;
-	uint16_t good_CRC_th;
-	uint16_t rx_chain;
-	uint32_t max_out_time;
-	uint32_t suspend_time;
-	/* IWM_RX_ON_FLAGS_API_S_VER_1 */
-	uint32_t flags;
-	uint32_t filter_flags;
-	struct iwm_tx_cmd tx_cmd[2];
-	/* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
-	struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
-	uint32_t scan_type;
-	uint32_t rep_count;
-} __packed;
-
-enum iwm_scan_offload_channel_flags {
-	IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE		= (1 << 0),
-	IWM_SCAN_OFFLOAD_CHANNEL_NARROW		= (1 << 22),
-	IWM_SCAN_OFFLOAD_CHANNEL_FULL		= (1 << 24),
-	IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL	= (1 << 25),
-};
-
-/**
- * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S
- * @type:		bitmap - see enum iwm_scan_offload_channel_flags.
- *			0:	passive (0) or active (1) scan.
- *			1-20:	directed scan to i'th ssid.
- *			22:	channel width configuation - 1 for narrow.
- *			24:	full scan.
- *			25:	partial scan.
- * @channel_number:	channel number 1-13 etc.
- * @iter_count:		repetition count for the channel.
- * @iter_interval:	interval between two innteration on one channel.
- * @dwell_time:	entry 0 - active scan, entry 1 - passive scan.
- */
-struct iwm_scan_channel_cfg {
-	uint32_t type[IWM_MAX_SCAN_CHANNELS];
-	uint16_t channel_number[IWM_MAX_SCAN_CHANNELS];
-	uint16_t iter_count[IWM_MAX_SCAN_CHANNELS];
-	uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS];
-	uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2];
-} __packed;
-
-/**
- * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S
- * @scan_cmd:		scan command fixed part
- * @channel_cfg:	scan channel configuration
- * @data:		probe request frames (one per band)
- */
-struct iwm_scan_offload_cfg {
-	struct iwm_scan_offload_cmd scan_cmd;
-	struct iwm_scan_channel_cfg channel_cfg;
-	uint8_t data[0];
-} __packed;
-
-/**
  * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
  * @ssid:		MAC address to filter out
  * @reported_rssi:	AP rssi reported to the host
@@ -5345,48 +5114,7 @@ struct iwm_scan_offload_profile_cfg {
 	uint8_t reserved[2];
 } __packed;
 
-/**
- * iwm_scan_offload_schedule - schedule of scan offload
- * @delay:		delay between iterations, in seconds.
- * @iterations:		num of scan iterations
- * @full_scan_mul:	number of partial scans before each full scan
- */
-struct iwm_scan_offload_schedule {
-	uint16_t delay;
-	uint8_t iterations;
-	uint8_t full_scan_mul;
-} __packed;
-
-/*
- * iwm_scan_offload_flags
- *
- * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering.
- * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan.
- * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan
- *	on A band.
- */
-enum iwm_scan_offload_flags {
-	IWM_SCAN_OFFLOAD_FLAG_PASS_ALL		= (1 << 0),
-	IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL	= (1 << 2),
-	IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN	= (1 << 3),
-};
-
-/**
- * iwm_scan_offload_req - scan offload request command
- * @flags:		bitmap - enum iwm_scan_offload_flags.
- * @watchdog:		maximum scan duration in TU.
- * @delay:		delay in seconds before first iteration.
- * @schedule_line:	scan offload schedule, for fast and regular scan.
- */
-struct iwm_scan_offload_req {
-	uint16_t flags;
-	uint16_t watchdog;
-	uint16_t delay;
-	uint16_t reserved;
-	struct iwm_scan_offload_schedule schedule_line[2];
-} __packed;
-
-enum iwm_scan_offload_compleate_status {
+enum iwm_scan_offload_complete_status {
 	IWM_SCAN_OFFLOAD_COMPLETED	= 1,
 	IWM_SCAN_OFFLOAD_ABORTED	= 2,
 };
@@ -5413,30 +5141,6 @@ struct iwm_lmac_scan_complete_notif {
 } __packed;
 
 
-/**
- * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1
- * @last_schedule_line:		last schedule line executed (fast or regular)
- * @last_schedule_iteration:	last scan iteration executed before scan abort
- * @status:			enum iwm_scan_offload_compleate_status
- */
-struct iwm_scan_offload_complete {
-	uint8_t last_schedule_line;
-	uint8_t last_schedule_iteration;
-	uint8_t status;
-	uint8_t reserved;
-} __packed;
-
-/**
- * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1
- * @ssid_bitmap:	SSIDs indexes found in this iteration
- * @client_bitmap:	clients that are active and wait for this notification
- */
-struct iwm_sched_scan_results {
-	uint16_t ssid_bitmap;
-	uint8_t client_bitmap;
-	uint8_t reserved;
-};
-
 /*
  * END mvm/fw-api-scan.h
  */
diff --git a/sys/dev/iwm/if_iwmvar.h b/sys/dev/iwm/if_iwmvar.h
index 15a4655c03db..5c6871e6f2e1 100644
--- a/sys/dev/iwm/if_iwmvar.h
+++ b/sys/dev/iwm/if_iwmvar.h
@@ -170,7 +170,6 @@ struct iwm_fw_info {
 			uint32_t fws_len;
 			uint32_t fws_devoff;
 		} fw_sect[IWM_UCODE_SECT_MAX];
-		size_t fw_totlen;
 		int fw_count;
 	} fw_sects[IWM_UCODE_TYPE_MAX];
 };
@@ -179,14 +178,6 @@ struct iwm_nvm_data {
 	int n_hw_addrs;
 	uint8_t hw_addr[IEEE80211_ADDR_LEN];
 
-	uint8_t calib_version;
-	uint16_t calib_voltage;
-
-	uint16_t raw_temperature;
-	uint16_t kelvin_temperature;
-	uint16_t kelvin_voltage;
-	uint16_t xtal_calib[2];
-
 	int sku_cap_band_24GHz_enable;
 	int sku_cap_band_52GHz_enable;
 	int sku_cap_11n_enable;
@@ -275,7 +266,6 @@ struct iwm_tx_ring {
 struct iwm_rx_data {
 	struct mbuf	*m;
 	bus_dmamap_t	map;
-	int		wantresp;
 };
 
 struct iwm_rx_ring {
diff --git a/sys/dev/mrsas/mrsas_linux.c b/sys/dev/mrsas/mrsas_linux.c
index 15f38c53e900..ac74f56ae57e 100644
--- a/sys/dev/mrsas/mrsas_linux.c
+++ b/sys/dev/mrsas/mrsas_linux.c
@@ -43,8 +43,10 @@ __FBSDID("$FreeBSD$");
 #include <sys/param.h>
 #include <sys/systm.h>
 
-#if (__FreeBSD_version > 900000)
-#include <sys/capability.h>
+#if (__FreeBSD_version >= 1001511)
+#include <sys/capsicum.h>
+#elif (__FreeBSD_version > 900000)
+#include <sys/capabilty.h>
 #endif
 
 #include <sys/conf.h>
diff --git a/sys/dev/oce/oce_hw.c b/sys/dev/oce/oce_hw.c
index aad5795a97e5..72f3c556f85e 100644
--- a/sys/dev/oce/oce_hw.c
+++ b/sys/dev/oce/oce_hw.c
@@ -393,6 +393,11 @@ oce_create_nw_interface(POCE_SOFTC sc)
 	if (IS_SH(sc) || IS_XE201(sc))
 		capab_flags |= MBX_RX_IFACE_FLAGS_MULTICAST;
 
+        if (sc->enable_hwlro) {
+                capab_flags |= MBX_RX_IFACE_FLAGS_LRO;
+                capab_en_flags |= MBX_RX_IFACE_FLAGS_LRO;
+        }
+
 	/* enable capabilities controlled via driver startup parameters */
 	if (is_rss_enabled(sc))
 		capab_en_flags |= MBX_RX_IFACE_FLAGS_RSS;
diff --git a/sys/dev/oce/oce_hw.h b/sys/dev/oce/oce_hw.h
index 1ad3f7889e0b..edb029c1e282 100644
--- a/sys/dev/oce/oce_hw.h
+++ b/sys/dev/oce/oce_hw.h
@@ -111,6 +111,9 @@
 #define	PD_MPU_MBOX_DB			0x0160
 #define	PD_MQ_DB			0x0140
 
+#define DB_OFFSET			0xc0
+#define DB_LRO_RQ_ID_MASK		0x7FF
+
 /* EQE completion types */
 #define	EQ_MINOR_CODE_COMPLETION 	0x00
 #define	EQ_MINOR_CODE_OTHER		0x01
@@ -180,6 +183,7 @@
 #define ASYNC_EVENT_GRP5		0x5
 #define ASYNC_EVENT_CODE_DEBUG		0x6
 #define ASYNC_EVENT_PVID_STATE		0x3
+#define ASYNC_EVENT_OS2BMC		0x5
 #define ASYNC_EVENT_DEBUG_QNQ		0x1
 #define ASYNC_EVENT_CODE_SLIPORT	0x11
 #define VLAN_VID_MASK			0x0FFF
@@ -722,6 +726,34 @@ struct oce_async_cqe_link_state {
 	} u0;
 };
 
+/* OS2BMC async event */
+struct oce_async_evt_grp5_os2bmc {
+	union {
+		struct {
+			uint32_t lrn_enable:1;
+			uint32_t lrn_disable:1;
+			uint32_t mgmt_enable:1;
+			uint32_t mgmt_disable:1;
+			uint32_t rsvd0:12;
+			uint32_t vlan_tag:16;
+			uint32_t arp_filter:1;
+			uint32_t dhcp_client_filt:1;
+			uint32_t dhcp_server_filt:1;
+			uint32_t net_bios_filt:1;
+			uint32_t rsvd1:3;
+			uint32_t bcast_filt:1;
+			uint32_t ipv6_nbr_filt:1;
+			uint32_t ipv6_ra_filt:1;
+			uint32_t ipv6_ras_filt:1;
+			uint32_t rsvd2[4];
+			uint32_t mcast_filt:1;
+			uint32_t rsvd3:16;
+			uint32_t evt_tag;
+			uint32_t dword3;
+		} s;
+		uint32_t dword[4];
+	} u;
+};
 
 /* PVID aync event */
 struct oce_async_event_grp5_pvid_state {
@@ -1396,7 +1428,7 @@ typedef union oce_cq_ctx_u {
 		uint32_t dw5rsvd3:1;
 		uint32_t eventable:1;
 		/* dw6 */
-		uint32_t eq_id:8;
+		uint32_t eq_id:16;
 		uint32_t dw6rsvd1:15;
 		uint32_t armed:1;
 		/* dw7 */
@@ -2403,8 +2435,8 @@ struct oce_nic_hdr_wqe {
 			uint32_t tcpcs:1;
 			uint32_t udpcs:1;
 			uint32_t ipcs:1;
-			uint32_t rsvd3:1;
-			uint32_t rsvd2:1;
+			uint32_t mgmt:1;
+			uint32_t lso6:1;
 			uint32_t forward:1;
 			uint32_t crc:1;
 			uint32_t event:1;
@@ -2426,8 +2458,8 @@ struct oce_nic_hdr_wqe {
 			uint32_t event:1;
 			uint32_t crc:1;
 			uint32_t forward:1;
-			uint32_t rsvd2:1;
-			uint32_t rsvd3:1;
+			uint32_t lso6:1;
+			uint32_t mgmt:1;
 			uint32_t ipcs:1;
 			uint32_t udpcs:1;
 			uint32_t tcpcs:1;
@@ -3010,6 +3042,53 @@ struct oce_rxf_stats_v0 {
 	uint32_t rsvd1[6];
 };
 
+struct oce_port_rxf_stats_v2 {
+        uint32_t rsvd0[10];
+        uint32_t roce_bytes_received_lsd;
+        uint32_t roce_bytes_received_msd;
+        uint32_t rsvd1[5];
+        uint32_t roce_frames_received;
+        uint32_t rx_crc_errors;
+        uint32_t rx_alignment_symbol_errors;
+        uint32_t rx_pause_frames;
+        uint32_t rx_priority_pause_frames;
+        uint32_t rx_control_frames;
+        uint32_t rx_in_range_errors;
+        uint32_t rx_out_range_errors;
+        uint32_t rx_frame_too_long;
+        uint32_t rx_address_match_errors;
+        uint32_t rx_dropped_too_small;
+        uint32_t rx_dropped_too_short;
+        uint32_t rx_dropped_header_too_small;
+        uint32_t rx_dropped_tcp_length;
+        uint32_t rx_dropped_runt;
+        uint32_t rsvd2[10];
+        uint32_t rx_ip_checksum_errs;
+        uint32_t rx_tcp_checksum_errs;
+        uint32_t rx_udp_checksum_errs;
+        uint32_t rsvd3[7];
+        uint32_t rx_switched_unicast_packets;
+        uint32_t rx_switched_multicast_packets;
+        uint32_t rx_switched_broadcast_packets;
+        uint32_t rsvd4[3];
+        uint32_t tx_pauseframes;
+        uint32_t tx_priority_pauseframes;
+        uint32_t tx_controlframes;
+        uint32_t rsvd5[10];
+        uint32_t rxpp_fifo_overflow_drop;
+        uint32_t rx_input_fifo_overflow_drop;
+        uint32_t pmem_fifo_overflow_drop;
+        uint32_t jabber_events;
+        uint32_t rsvd6[3];
+        uint32_t rx_drops_payload_size;
+        uint32_t rx_drops_clipped_header;
+        uint32_t rx_drops_crc;
+        uint32_t roce_drops_payload_len;
+        uint32_t roce_drops_crc;
+        uint32_t rsvd7[19];
+};
+
+
 struct oce_port_rxf_stats_v1 {
 	uint32_t rsvd0[12];
 	uint32_t rx_crc_errors;
@@ -3046,6 +3125,20 @@ struct oce_port_rxf_stats_v1 {
 	uint32_t rsvd5[3];
 };
 
+struct oce_rxf_stats_v2 {
+        struct oce_port_rxf_stats_v2 port[4];
+        uint32_t rsvd0[2];
+        uint32_t rx_drops_no_pbuf;
+        uint32_t rx_drops_no_txpb;
+        uint32_t rx_drops_no_erx_descr;
+        uint32_t rx_drops_no_tpre_descr;
+        uint32_t rsvd1[6];
+        uint32_t rx_drops_too_many_frags;
+        uint32_t rx_drops_invalid_ring;
+        uint32_t forwarded_packets;
+        uint32_t rx_drops_mtu;
+        uint32_t rsvd2[35];
+};
 
 struct oce_rxf_stats_v1 {
 	struct oce_port_rxf_stats_v1 port[4];
@@ -3062,6 +3155,11 @@ struct oce_rxf_stats_v1 {
 	uint32_t rsvd2[14];
 };
 
+struct oce_erx_stats_v2 {
+        uint32_t rx_drops_no_fragments[136];
+        uint32_t rsvd[3];
+};
+
 struct oce_erx_stats_v1 {
 	uint32_t rx_drops_no_fragments[68];
 	uint32_t rsvd[4];
@@ -3078,6 +3176,15 @@ struct oce_pmem_stats {
 	uint32_t rsvd[5];
 };
 
+struct oce_hw_stats_v2 {
+        struct oce_rxf_stats_v2 rxf;
+        uint32_t rsvd0[OCE_TXP_SW_SZ];
+        struct oce_erx_stats_v2 erx;
+        struct oce_pmem_stats pmem;
+        uint32_t rsvd1[18];
+};
+
+
 struct oce_hw_stats_v1 {
 	struct oce_rxf_stats_v1 rxf;
 	uint32_t rsvd0[OCE_TXP_SW_SZ];
@@ -3093,32 +3200,22 @@ struct oce_hw_stats_v0 {
 	struct oce_pmem_stats pmem;
 };
 
-struct mbx_get_nic_stats_v0 {
-	struct mbx_hdr hdr;
-	union {
-		struct {
-			uint32_t rsvd0;
-		} req;
-
-		union {
-			struct oce_hw_stats_v0 stats;
-		} rsp;
-	} params;
-};
-
-struct mbx_get_nic_stats {
-	struct mbx_hdr hdr;
-	union {
-		struct {
-			uint32_t rsvd0;
-		} req;
-		
-		struct {
-			struct oce_hw_stats_v1 stats;
-		} rsp;
-	} params;
-};
-
+#define MBX_GET_NIC_STATS(version)				\
+	struct mbx_get_nic_stats_v##version { 			\
+	struct mbx_hdr hdr; 					\
+	union { 						\
+		struct { 					\
+			uint32_t rsvd0; 			\
+		} req; 						\
+		union { 					\
+			struct oce_hw_stats_v##version stats; 	\
+		} rsp; 						\
+	} params; 						\
+}  
+
+MBX_GET_NIC_STATS(0);
+MBX_GET_NIC_STATS(1);
+MBX_GET_NIC_STATS(2);
 
 /* [18(0x12)] NIC_GET_PPORT_STATS */
 struct pport_stats {
@@ -3728,3 +3825,373 @@ enum OCE_QUEUE_RX_STATS {
 	QUEUE_RX_BUFFER_ERRORS = 8,
 	QUEUE_RX_N_WORDS = 10
 };
+
+/* HW LRO structures */
+struct mbx_nic_query_lro_capabilities {
+        struct mbx_hdr hdr;
+        union {
+                struct {
+                        uint32_t rsvd[6];
+                } req;
+                struct {
+#ifdef _BIG_ENDIAN
+                        uint32_t lro_flags;
+                        uint16_t lro_rq_cnt;
+                        uint16_t plro_max_offload;
+                        uint32_t rsvd[4];
+#else
+                        uint32_t lro_flags;
+                        uint16_t plro_max_offload;
+                        uint16_t lro_rq_cnt;
+                        uint32_t rsvd[4];
+#endif
+                } rsp;
+        } params;
+};
+
+struct mbx_nic_set_iface_lro_config {
+        struct mbx_hdr hdr;
+        union {
+                struct {
+#ifdef _BIG_ENDIAN
+                        uint32_t lro_flags;
+                        uint32_t iface_id;
+                        uint32_t max_clsc_byte_cnt;
+                        uint32_t max_clsc_seg_cnt;
+                        uint32_t max_clsc_usec_delay;
+                        uint32_t min_clsc_frame_byte_cnt;
+                        uint32_t rsvd[2];
+#else
+                        uint32_t lro_flags;
+                        uint32_t iface_id;
+                        uint32_t max_clsc_byte_cnt;
+                        uint32_t max_clsc_seg_cnt;
+                        uint32_t max_clsc_usec_delay;
+                        uint32_t min_clsc_frame_byte_cnt;
+                        uint32_t rsvd[2];
+#endif
+                } req;
+                struct {
+#ifdef _BIG_ENDIAN
+                        uint32_t lro_flags;
+                        uint32_t rsvd[7];
+#else
+                        uint32_t lro_flags;
+                        uint32_t rsvd[7];
+#endif
+                } rsp;
+        } params;
+};
+
+
+struct mbx_create_nic_rq_v2 {
+        struct mbx_hdr hdr;
+        union {
+                struct {
+#ifdef _BIG_ENDIAN
+                        uint8_t  num_pages;
+                        uint8_t  frag_size;
+                        uint16_t cq_id;
+
+                        uint32_t if_id;
+
+                        uint16_t page_size;
+                        uint16_t max_frame_size;
+
+                        uint16_t rsvd;
+                        uint16_t pd_id;
+
+                        uint16_t rsvd1;
+                        uint16_t rq_flags;
+
+                        uint16_t hds_fixed_offset;
+                        uint8_t hds_start;
+                        uint8_t hds_frag;
+
+                        uint16_t hds_backfill_size;
+                        uint16_t hds_frag_size;
+
+                        uint32_t rbq_id;
+
+                        uint32_t rsvd2[8];
+
+                        struct phys_addr pages[2];
+#else
+                        uint16_t cq_id;
+                        uint8_t  frag_size;
+                        uint8_t  num_pages;
+
+                        uint32_t if_id;
+
+                        uint16_t max_frame_size;
+                        uint16_t page_size;
+
+                        uint16_t pd_id;
+                        uint16_t rsvd;
+
+                        uint16_t rq_flags;
+                        uint16_t rsvd1;
+
+                        uint8_t hds_frag;
+                        uint8_t hds_start;
+                        uint16_t hds_fixed_offset;
+
+                        uint16_t hds_frag_size;
+                        uint16_t hds_backfill_size;
+
+                        uint32_t rbq_id;
+
+                        uint32_t rsvd2[8];
+
+                        struct phys_addr pages[2];
+#endif
+                } req;
+                struct {
+#ifdef _BIG_ENDIAN
+                        uint8_t rsvd0;
+                        uint8_t rss_cpuid;
+                        uint16_t rq_id;
+
+                        uint8_t db_format;
+                        uint8_t db_reg_set;
+                        uint16_t rsvd1;
+
+                        uint32_t db_offset;
+
+                        uint32_t rsvd2;
+
+                        uint16_t rsvd3;
+                        uint16_t rq_flags;
+
+#else
+                        uint16_t rq_id;
+                        uint8_t rss_cpuid;
+                        uint8_t rsvd0;
+
+                        uint16_t rsvd1;
+                        uint8_t db_reg_set;
+                        uint8_t db_format;
+
+                        uint32_t db_offset;
+
+                        uint32_t rsvd2;
+
+                        uint16_t rq_flags;
+                        uint16_t rsvd3;
+#endif
+                } rsp;
+
+        } params;
+};
+
+struct mbx_delete_nic_rq_v1 {
+        struct mbx_hdr hdr;
+        union {
+                struct {
+#ifdef _BIG_ENDIAN
+                        uint16_t bypass_flush;
+                        uint16_t rq_id;
+                        uint16_t rsvd;
+                        uint16_t rq_flags;
+#else
+                        uint16_t rq_id;
+                        uint16_t bypass_flush;
+                        uint16_t rq_flags;
+                        uint16_t rsvd;
+#endif
+                } req;
+                struct {
+                        uint32_t rsvd[2];
+                } rsp;
+        } params;
+};
+
+struct nic_hwlro_singleton_cqe {
+#ifdef _BIG_ENDIAN
+        /* dw 0 */
+        uint32_t ip_opt:1;
+        uint32_t vtp:1;
+        uint32_t pkt_size:14;
+        uint32_t vlan_tag:16;
+
+        /* dw 1 */
+        uint32_t num_frags:3;
+        uint32_t rsvd1:3;
+        uint32_t frag_index:10;
+        uint32_t rsvd:8;
+        uint32_t ipv6_frame:1;
+        uint32_t l4_cksum_pass:1;
+        uint32_t ip_cksum_pass:1;
+        uint32_t udpframe:1;
+        uint32_t tcpframe:1;
+        uint32_t ipframe:1;
+        uint32_t rss_hp:1;
+        uint32_t error:1;
+
+        /* dw 2 */
+        uint32_t valid:1;
+        uint32_t cqe_type:2;
+        uint32_t debug:7;
+        uint32_t rsvd4:6;
+        uint32_t data_offset:8;
+        uint32_t rsvd3:3;
+        uint32_t rss_bank:1;
+        uint32_t qnq:1;
+        uint32_t rsvd2:3;
+        
+	/* dw 3 */
+        uint32_t rss_hash_value;
+#else
+        /* dw 0 */
+        uint32_t vlan_tag:16;
+        uint32_t pkt_size:14;
+        uint32_t vtp:1;
+        uint32_t ip_opt:1;
+
+        /* dw 1 */
+        uint32_t error:1;
+        uint32_t rss_hp:1;
+        uint32_t ipframe:1;
+        uint32_t tcpframe:1;
+        uint32_t udpframe:1;
+        uint32_t ip_cksum_pass:1;
+        uint32_t l4_cksum_pass:1;
+        uint32_t ipv6_frame:1;
+        uint32_t rsvd:8;
+        uint32_t frag_index:10;
+        uint32_t rsvd1:3;
+        uint32_t num_frags:3;
+
+        /* dw 2 */
+        uint32_t rsvd2:3;
+        uint32_t qnq:1;
+        uint32_t rss_bank:1;
+        uint32_t rsvd3:3;
+        uint32_t data_offset:8;
+        uint32_t rsvd4:6;
+        uint32_t debug:7;
+        uint32_t cqe_type:2;
+        uint32_t valid:1;
+ 
+       /* dw 3 */
+        uint32_t rss_hash_value;
+#endif
+};
+
+struct nic_hwlro_cqe_part1 {
+#ifdef _BIG_ENDIAN
+        /* dw 0 */
+        uint32_t tcp_timestamp_val;
+
+        /* dw 1 */
+        uint32_t tcp_timestamp_ecr;
+
+        /* dw 2 */
+        uint32_t valid:1;
+        uint32_t cqe_type:2;
+        uint32_t rsvd3:7;
+        uint32_t rss_policy:4;
+        uint32_t rsvd2:2;
+        uint32_t data_offset:8;
+        uint32_t rsvd1:1;
+        uint32_t lro_desc:1;
+        uint32_t lro_timer_pop:1;
+        uint32_t rss_bank:1;
+        uint32_t qnq:1;
+        uint32_t rsvd:2;
+        uint32_t rss_flush:1;
+
+	/* dw 3 */
+        uint32_t rss_hash_value;
+#else
+        /* dw 0 */
+        uint32_t tcp_timestamp_val;
+
+        /* dw 1 */
+        uint32_t tcp_timestamp_ecr;
+
+        /* dw 2 */
+        uint32_t rss_flush:1;
+        uint32_t rsvd:2;
+        uint32_t qnq:1;
+        uint32_t rss_bank:1;
+        uint32_t lro_timer_pop:1;
+        uint32_t lro_desc:1;
+        uint32_t rsvd1:1;
+        uint32_t data_offset:8;
+        uint32_t rsvd2:2;
+        uint32_t rss_policy:4;
+        uint32_t rsvd3:7;
+        uint32_t cqe_type:2;
+        uint32_t valid:1;
+
+        /* dw 3 */
+        uint32_t rss_hash_value;
+#endif
+};
+
+struct nic_hwlro_cqe_part2 {
+#ifdef _BIG_ENDIAN
+        /* dw 0 */
+        uint32_t ip_opt:1;
+        uint32_t vtp:1;
+        uint32_t pkt_size:14;
+        uint32_t vlan_tag:16;
+
+        /* dw 1 */
+        uint32_t tcp_window:16;
+        uint32_t coalesced_size:16;
+        
+	/* dw 2 */
+        uint32_t valid:1;
+        uint32_t cqe_type:2;
+        uint32_t rsvd:2;
+        uint32_t push:1;
+        uint32_t ts_opt:1;
+        uint32_t threshold:1;
+        uint32_t seg_cnt:8;
+        uint32_t frame_lifespan:8;
+        uint32_t ipv6_frame:1;
+        uint32_t l4_cksum_pass:1;
+        uint32_t ip_cksum_pass:1;
+        uint32_t udpframe:1;
+        uint32_t tcpframe:1;
+        uint32_t ipframe:1;
+        uint32_t rss_hp:1;
+        uint32_t error:1;
+        
+	/* dw 3 */
+        uint32_t tcp_ack_num;
+#else
+        /* dw 0 */
+        uint32_t vlan_tag:16;
+        uint32_t pkt_size:14;
+        uint32_t vtp:1;
+        uint32_t ip_opt:1;
+
+        /* dw 1 */
+        uint32_t coalesced_size:16;
+        uint32_t tcp_window:16;
+
+        /* dw 2 */
+        uint32_t error:1;
+        uint32_t rss_hp:1;
+        uint32_t ipframe:1;
+        uint32_t tcpframe:1;
+        uint32_t udpframe:1;
+        uint32_t ip_cksum_pass:1;
+        uint32_t l4_cksum_pass:1;
+        uint32_t ipv6_frame:1;
+        uint32_t frame_lifespan:8;
+        uint32_t seg_cnt:8;
+        uint32_t threshold:1;
+        uint32_t ts_opt:1;
+        uint32_t push:1;
+        uint32_t rsvd:2;
+        uint32_t cqe_type:2;
+        uint32_t valid:1;
+
+        /* dw 3 */
+        uint32_t tcp_ack_num;
+#endif
+};
diff --git a/sys/dev/oce/oce_if.c b/sys/dev/oce/oce_if.c
index 370461291234..d09977eb6a89 100644
--- a/sys/dev/oce/oce_if.c
+++ b/sys/dev/oce/oce_if.c
@@ -42,77 +42,92 @@
 #include "opt_inet.h"
 
 #include "oce_if.h"
+#include "oce_user.h"
+
+#define is_tso_pkt(m) (m->m_pkthdr.csum_flags & CSUM_TSO)
 
 /* UE Status Low CSR */
 static char *ue_status_low_desc[] = {
-	"CEV",
-	"CTX",
-	"DBUF",
-	"ERX",
-	"Host",
-	"MPU",
-	"NDMA",
-	"PTC ",
-	"RDMA ",
-	"RXF ",
-	"RXIPS ",
-	"RXULP0 ",
-	"RXULP1 ",
-	"RXULP2 ",
-	"TIM ",
-	"TPOST ",
-	"TPRE ",
-	"TXIPS ",
-	"TXULP0 ",
-	"TXULP1 ",
-	"UC ",
-	"WDMA ",
-	"TXULP2 ",
-	"HOST1 ",
-	"P0_OB_LINK ",
-	"P1_OB_LINK ",
-	"HOST_GPIO ",
-	"MBOX ",
-	"AXGMAC0",
-	"AXGMAC1",
-	"JTAG",
-	"MPU_INTPEND"
+        "CEV",
+        "CTX",
+        "DBUF",
+        "ERX",
+        "Host",
+        "MPU",
+        "NDMA",
+        "PTC ",
+        "RDMA ",
+        "RXF ",
+        "RXIPS ",
+        "RXULP0 ",
+        "RXULP1 ",
+        "RXULP2 ",
+        "TIM ",
+        "TPOST ",
+        "TPRE ",
+        "TXIPS ",
+        "TXULP0 ",
+        "TXULP1 ",
+        "UC ",
+        "WDMA ",
+        "TXULP2 ",
+        "HOST1 ",
+        "P0_OB_LINK ",
+        "P1_OB_LINK ",
+        "HOST_GPIO ",
+        "MBOX ",
+        "AXGMAC0",
+        "AXGMAC1",
+        "JTAG",
+        "MPU_INTPEND"
 };
 
 /* UE Status High CSR */
 static char *ue_status_hi_desc[] = {
-	"LPCMEMHOST",
-	"MGMT_MAC",
-	"PCS0ONLINE",
-	"MPU_IRAM",
-	"PCS1ONLINE",
-	"PCTL0",
-	"PCTL1",
-	"PMEM",
-	"RR",
-	"TXPB",
-	"RXPP",
-	"XAUI",
-	"TXP",
-	"ARM",
-	"IPC",
-	"HOST2",
-	"HOST3",
-	"HOST4",
-	"HOST5",
-	"HOST6",
-	"HOST7",
-	"HOST8",
-	"HOST9",
-	"NETC",
-	"Unknown",
-	"Unknown",
-	"Unknown",
-	"Unknown",
-	"Unknown",
-	"Unknown",
-	"Unknown",
-	"Unknown"
+        "LPCMEMHOST",
+        "MGMT_MAC",
+        "PCS0ONLINE",
+        "MPU_IRAM",
+        "PCS1ONLINE",
+        "PCTL0",
+        "PCTL1",
+        "PMEM",
+        "RR",
+        "TXPB",
+        "RXPP",
+        "XAUI",
+        "TXP",
+        "ARM",
+        "IPC",
+        "HOST2",
+        "HOST3",
+        "HOST4",
+        "HOST5",
+        "HOST6",
+        "HOST7",
+        "HOST8",
+        "HOST9",
+        "NETC",
+        "Unknown",
+        "Unknown",
+        "Unknown",
+        "Unknown",
+        "Unknown",
+        "Unknown",
+        "Unknown",
+        "Unknown"
+};
+
+struct oce_common_cqe_info{
+        uint8_t vtp:1;
+        uint8_t l4_cksum_pass:1;
+        uint8_t ip_cksum_pass:1;
+        uint8_t ipv6_frame:1;
+        uint8_t qnq:1;
+        uint8_t rsvd:3;
+        uint8_t num_frags;
+        uint16_t pkt_size;
+        uint16_t vtag;
 };
 
 
@@ -140,17 +155,19 @@ static int  oce_media_change(struct ifnet *ifp);
 /* Transmit routines prototypes */
 static int  oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index);
 static void oce_tx_restart(POCE_SOFTC sc, struct oce_wq *wq);
-static void oce_tx_complete(struct oce_wq *wq, uint32_t wqe_idx,
-					uint32_t status);
+static void oce_process_tx_completion(struct oce_wq *wq);
 static int  oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m,
 				 struct oce_wq *wq);
 
 /* Receive routines prototypes */
-static void oce_discard_rx_comp(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe);
 static int  oce_cqe_vtp_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
 static int  oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe);
-static void oce_rx(struct oce_rq *rq, uint32_t rqe_idx,
-						struct oce_nic_rx_cqe *cqe);
+static void oce_rx(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe);
+static void oce_check_rx_bufs(POCE_SOFTC sc, uint32_t num_cqes, struct oce_rq *rq);
+static uint16_t oce_rq_handler_lro(void *arg);
+static void oce_correct_header(struct mbuf *m, struct nic_hwlro_cqe_part1 *cqe1, struct nic_hwlro_cqe_part2 *cqe2);
+static void oce_rx_lro(struct oce_rq *rq, struct nic_hwlro_singleton_cqe *cqe, struct nic_hwlro_cqe_part2 *cqe2);
+static void oce_rx_mbuf_chain(struct oce_rq *rq, struct oce_common_cqe_info *cqe_info, struct mbuf **m);
 
 /* Helper function prototypes in this file */
 static int  oce_attach_ifp(POCE_SOFTC sc);
@@ -169,11 +186,12 @@ static void process_link_state(POCE_SOFTC sc,
 static int oce_tx_asic_stall_verify(POCE_SOFTC sc, struct mbuf *m);
 static void oce_get_config(POCE_SOFTC sc);
 static struct mbuf *oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete);
+static void oce_read_env_variables(POCE_SOFTC sc);
+
 
 /* IP specific */
 #if defined(INET6) || defined(INET)
 static int  oce_init_lro(POCE_SOFTC sc);
-static void oce_rx_flush_lro(struct oce_rq *rq);
 static struct mbuf * oce_tso_setup(POCE_SOFTC sc, struct mbuf **mpp);
 #endif
 
@@ -206,7 +224,7 @@ const char component_revision[32] = {"///" COMPONENT_REVISION "///"};
 /* Module capabilites and parameters */
 uint32_t oce_max_rsp_handled = OCE_MAX_RSP_HANDLED;
 uint32_t oce_enable_rss = OCE_MODCAP_RSS;
-
+uint32_t oce_rq_buf_size = 2048;
 
 TUNABLE_INT("hw.oce.max_rsp_handled", &oce_max_rsp_handled);
 TUNABLE_INT("hw.oce.enable_rss", &oce_enable_rss);
@@ -222,8 +240,10 @@ static uint32_t supportedDevices[] =  {
 	(PCI_VENDOR_EMULEX << 16) | PCI_PRODUCT_SH
 };
 
+POCE_SOFTC softc_head = NULL;
+POCE_SOFTC softc_tail = NULL;
 
-
+struct oce_rdma_if *oce_rdma_if = NULL;
 
 /*****************************************************************************
  *			Driver entry points functions                        *
@@ -292,7 +312,8 @@ oce_attach(device_t dev)
 
 	sc->tx_ring_size = OCE_TX_RING_SIZE;
 	sc->rx_ring_size = OCE_RX_RING_SIZE;
-	sc->rq_frag_size = OCE_RQ_BUF_SIZE;
+	/* receive fragment size should be multiple of 2K */
+	sc->rq_frag_size = ((oce_rq_buf_size / 2048) * 2048);
 	sc->flow_control = OCE_DEFAULT_FLOW_CONTROL;
 	sc->promisc	 = OCE_DEFAULT_PROMISCUOUS;
 
@@ -304,6 +325,8 @@ oce_attach(device_t dev)
 	if (rc)
 		goto pci_res_free;
 
+	oce_read_env_variables(sc);
+
 	oce_get_config(sc);
 
 	setup_max_queues_want(sc);	
@@ -341,11 +364,19 @@ oce_attach(device_t dev)
 
 	oce_add_sysctls(sc);
 
-	callout_init(&sc->timer, 1);
+	callout_init(&sc->timer, CALLOUT_MPSAFE);
 	rc = callout_reset(&sc->timer, 2 * hz, oce_local_timer, sc);
 	if (rc)
 		goto stats_free;
 
+	sc->next =NULL;
+	if (softc_tail != NULL) {
+	  softc_tail->next = sc;
+	} else {
+	  softc_head = sc;
+	}
+	softc_tail = sc;
+
 	return 0;
 
 stats_free:
@@ -383,6 +414,22 @@ static int
 oce_detach(device_t dev)
 {
 	POCE_SOFTC sc = device_get_softc(dev);
+	POCE_SOFTC poce_sc_tmp, *ppoce_sc_tmp1, poce_sc_tmp2 = NULL;
+
+        poce_sc_tmp = softc_head;
+        ppoce_sc_tmp1 = &softc_head;
+        while (poce_sc_tmp != NULL) {
+          if (poce_sc_tmp == sc) {
+            *ppoce_sc_tmp1 = sc->next;
+            if (sc->next == NULL) {
+              softc_tail = poce_sc_tmp2;
+            }
+            break;
+          }
+          poce_sc_tmp2 = poce_sc_tmp;
+          ppoce_sc_tmp1 = &poce_sc_tmp->next;
+          poce_sc_tmp = poce_sc_tmp->next;
+        }
 
 	LOCK(&sc->dev_lock);
 	oce_if_deactivate(sc);
@@ -520,8 +567,16 @@ oce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 			oce_vid_config(sc);
 		}
 #if defined(INET6) || defined(INET)
-		if (u & IFCAP_LRO)
+		if (u & IFCAP_LRO) {
 			ifp->if_capenable ^= IFCAP_LRO;
+			if(sc->enable_hwlro) {
+				if(ifp->if_capenable & IFCAP_LRO) {
+					rc = oce_mbox_nic_set_iface_lro_config(sc, 1);
+				}else {
+					rc = oce_mbox_nic_set_iface_lro_config(sc, 0);
+				}
+			}
+		}
 #endif
 
 		break;
@@ -563,6 +618,9 @@ oce_multiq_start(struct ifnet *ifp, struct mbuf *m)
 	int queue_index = 0;
 	int status = 0;
 
+	if (!sc->link_status)
+		return ENXIO;
+
 	if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
 		queue_index = m->m_pkthdr.flowid % sc->nwqs;
 
@@ -653,20 +711,41 @@ oce_setup_intr(POCE_SOFTC sc)
 {
 	int rc = 0, use_intx = 0;
 	int vector = 0, req_vectors = 0;
+	int tot_req_vectors, tot_vectors;
 
 	if (is_rss_enabled(sc))
 		req_vectors = MAX((sc->nrqs - 1), sc->nwqs);
 	else
 		req_vectors = 1;
 
-	if (sc->flags & OCE_FLAGS_MSIX_CAPABLE) {
+	tot_req_vectors = req_vectors;
+	if (sc->rdma_flags & OCE_RDMA_FLAG_SUPPORTED) {
+	  if (req_vectors > 1) {
+	    tot_req_vectors += OCE_RDMA_VECTORS;
+	    sc->roce_intr_count = OCE_RDMA_VECTORS;
+	  }
+	}
+
+        if (sc->flags & OCE_FLAGS_MSIX_CAPABLE) {
 		sc->intr_count = req_vectors;
-		rc = pci_alloc_msix(sc->dev, &sc->intr_count);
+                tot_vectors = tot_req_vectors;
+		rc = pci_alloc_msix(sc->dev, &tot_vectors);
 		if (rc != 0) {
 			use_intx = 1;
 			pci_release_msi(sc->dev);
-		} else
-			sc->flags |= OCE_FLAGS_USING_MSIX;
+		} else {
+		  if (sc->rdma_flags & OCE_RDMA_FLAG_SUPPORTED) {
+		    if (tot_vectors < tot_req_vectors) {
+		      if (sc->intr_count < (2 * OCE_RDMA_VECTORS)) {
+			sc->roce_intr_count = (tot_vectors / 2);
+		      }
+		      sc->intr_count = tot_vectors - sc->roce_intr_count;
+		    }
+		  } else {
+		    sc->intr_count = tot_vectors;
+		  }
+    		  sc->flags |= OCE_FLAGS_USING_MSIX;
+		}
 	} else
 		use_intx = 1;
 
@@ -854,6 +933,79 @@ oce_media_change(struct ifnet *ifp)
 }
 
 
+static void oce_is_pkt_dest_bmc(POCE_SOFTC sc,
+				struct mbuf *m, boolean_t *os2bmc,
+				struct mbuf **m_new)
+{
+	struct ether_header *eh = NULL;
+
+	eh = mtod(m, struct ether_header *);
+
+	if (!is_os2bmc_enabled(sc) || *os2bmc) {
+		*os2bmc = FALSE;
+		goto done;
+	}
+	if (!ETHER_IS_MULTICAST(eh->ether_dhost))
+		goto done;
+
+	if (is_mc_allowed_on_bmc(sc, eh) ||
+	    is_bc_allowed_on_bmc(sc, eh) ||
+	    is_arp_allowed_on_bmc(sc, ntohs(eh->ether_type))) {
+		*os2bmc = TRUE;
+		goto done;
+	}
+
+	if (mtod(m, struct ip *)->ip_p == IPPROTO_IPV6) {
+		struct ip6_hdr *ip6 = mtod(m, struct ip6_hdr *);
+		uint8_t nexthdr = ip6->ip6_nxt;
+		if (nexthdr == IPPROTO_ICMPV6) {
+			struct icmp6_hdr *icmp6 = (struct icmp6_hdr *)(ip6 + 1);
+			switch (icmp6->icmp6_type) {
+			case ND_ROUTER_ADVERT:
+				*os2bmc = is_ipv6_ra_filt_enabled(sc);
+				goto done;
+			case ND_NEIGHBOR_ADVERT:
+				*os2bmc = is_ipv6_na_filt_enabled(sc);
+				goto done;
+			default:
+				break;
+			}
+		}
+	}
+
+	if (mtod(m, struct ip *)->ip_p == IPPROTO_UDP) {
+		struct ip *ip = mtod(m, struct ip *);
+		int iphlen = ip->ip_hl << 2;
+		struct udphdr *uh = (struct udphdr *)((caddr_t)ip + iphlen);
+		switch (uh->uh_dport) {
+		case DHCP_CLIENT_PORT:
+			*os2bmc = is_dhcp_client_filt_enabled(sc);
+			goto done;
+		case DHCP_SERVER_PORT:
+			*os2bmc = is_dhcp_srvr_filt_enabled(sc);
+			goto done;
+		case NET_BIOS_PORT1:
+		case NET_BIOS_PORT2:
+			*os2bmc = is_nbios_filt_enabled(sc);
+			goto done;
+		case DHCPV6_RAS_PORT:
+			*os2bmc = is_ipv6_ras_filt_enabled(sc);
+			goto done;
+		default:
+			break;
+		}
+	}
+done:
+	if (*os2bmc) {
+		*m_new = m_dup(m, M_NOWAIT);
+		if (!*m_new) {
+			*os2bmc = FALSE;
+			return;
+		}
+		*m_new = oce_insert_vlan_tag(sc, *m_new, NULL);
+	}
+}
+
 
 
 /*****************************************************************************
@@ -865,14 +1017,16 @@ oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index)
 {
 	int rc = 0, i, retry_cnt = 0;
 	bus_dma_segment_t segs[OCE_MAX_TX_ELEMENTS];
-	struct mbuf *m, *m_temp;
+	struct mbuf *m, *m_temp, *m_new = NULL;
 	struct oce_wq *wq = sc->wq[wq_index];
 	struct oce_packet_desc *pd;
 	struct oce_nic_hdr_wqe *nichdr;
 	struct oce_nic_frag_wqe *nicfrag;
+	struct ether_header *eh = NULL;
 	int num_wqes;
 	uint32_t reg_value;
 	boolean_t complete = TRUE;
+	boolean_t os2bmc = FALSE;
 
 	m = *mpp;
 	if (!m)
@@ -883,6 +1037,13 @@ oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index)
 		goto free_ret;
 	}
 
+	/* Don't allow non-TSO packets longer than MTU */
+	if (!is_tso_pkt(m)) {
+		eh = mtod(m, struct ether_header *);
+		if(m->m_pkthdr.len > ETHER_MAX_FRAME(sc->ifp, eh->ether_type, FALSE))
+			 goto free_ret;
+	}
+
 	if(oce_tx_asic_stall_verify(sc, m)) {
 		m = oce_insert_vlan_tag(sc, m, &complete);
 		if(!m) {
@@ -892,6 +1053,19 @@ oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index)
 
 	}
 
+	/* Lancer, SH ASIC has a bug wherein Packets that are 32 bytes or less
+	 * may cause a transmit stall on that port. So the work-around is to
+	 * pad short packets (<= 32 bytes) to a 36-byte length.
+	*/
+	if(IS_SH(sc) || IS_XE201(sc) ) {
+		if(m->m_pkthdr.len <= 32) {
+			char buf[36];
+			bzero((void *)buf, 36);
+			m_append(m, (36 - m->m_pkthdr.len), buf);
+		}
+	}
+
+tx_start:
 	if (m->m_pkthdr.csum_flags & CSUM_TSO) {
 		/* consolidate packet buffers for TSO/LSO segment offload */
 #if defined(INET6) || defined(INET)
@@ -905,7 +1079,9 @@ oce_tx(POCE_SOFTC sc, struct mbuf **mpp, int wq_index)
 		}
 	}
 
+
 	pd = &wq->pckts[wq->pkt_desc_head];
+
 retry:
 	rc = bus_dmamap_load_mbuf_sg(wq->tag,
 				     pd->map,
@@ -935,6 +1111,7 @@ retry:
 		nichdr->u0.dw[3] = 0;
 
 		nichdr->u0.s.complete = complete;
+		nichdr->u0.s.mgmt = os2bmc;
 		nichdr->u0.s.event = 1;
 		nichdr->u0.s.crc = 1;
 		nichdr->u0.s.forward = 0;
@@ -998,6 +1175,12 @@ retry:
 		bus_dmamap_sync(wq->ring->dma.tag, wq->ring->dma.map,
 				BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		reg_value = (num_wqes << 16) | wq->wq_id;
+
+		/* if os2bmc is not enabled or if the pkt is already tagged as
+		   bmc, do nothing
+		 */
+		oce_is_pkt_dest_bmc(sc, m, &os2bmc, &m_new);
+
 		OCE_WRITE_REG32(sc, db, wq->db_offset, reg_value);
 
 	} else if (rc == EFBIG)	{
@@ -1015,6 +1198,11 @@ retry:
 		return rc;
 	else
 		goto free_ret;
+
+	if (os2bmc) {
+		m = m_new;
+		goto tx_start;
+	}
 	
 	return 0;
 
@@ -1026,7 +1214,7 @@ free_ret:
 
 
 static void
-oce_tx_complete(struct oce_wq *wq, uint32_t wqe_idx, uint32_t status)
+oce_process_tx_completion(struct oce_wq *wq)
 {
 	struct oce_packet_desc *pd;
 	POCE_SOFTC sc = (POCE_SOFTC) wq->parent;
@@ -1213,6 +1401,7 @@ oce_wq_handler(void *arg)
 	struct oce_nic_tx_cqe *cqe;
 	int num_cqes = 0;
 
+	LOCK(&wq->tx_compl_lock);
 	bus_dmamap_sync(cq->ring->dma.tag,
 			cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
 	cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_tx_cqe);
@@ -1223,7 +1412,7 @@ oce_wq_handler(void *arg)
 		if (wq->ring->cidx >= wq->ring->num_items)
 			wq->ring->cidx -= wq->ring->num_items;
 
-		oce_tx_complete(wq, cqe->u0.s.wqe_index, cqe->u0.s.status);
+		oce_process_tx_completion(wq);
 		wq->tx_stats.tx_compl++;
 		cqe->u0.dw[3] = 0;
 		RING_GET(cq->ring, 1);
@@ -1236,8 +1425,9 @@ oce_wq_handler(void *arg)
 
 	if (num_cqes)
 		oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
-
-	return 0;
+	
+	UNLOCK(&wq->tx_compl_lock);
+	return num_cqes;
 }
 
 
@@ -1292,19 +1482,216 @@ oce_multiq_transmit(struct ifnet *ifp, struct mbuf *m, struct oce_wq *wq)
  *****************************************************************************/
 
 static void
-oce_rx(struct oce_rq *rq, uint32_t rqe_idx, struct oce_nic_rx_cqe *cqe)
+oce_correct_header(struct mbuf *m, struct nic_hwlro_cqe_part1 *cqe1, struct nic_hwlro_cqe_part2 *cqe2)
+{
+	uint32_t *p;
+        struct ether_header *eh = NULL;
+        struct tcphdr *tcp_hdr = NULL;
+        struct ip *ip4_hdr = NULL;
+        struct ip6_hdr *ip6 = NULL;
+        uint32_t payload_len = 0;
+
+        eh = mtod(m, struct ether_header *);
+        /* correct IP header */
+        if(!cqe2->ipv6_frame) {
+		ip4_hdr = (struct ip *)((char*)eh + sizeof(struct ether_header));
+                ip4_hdr->ip_ttl = cqe2->frame_lifespan;
+                ip4_hdr->ip_len = htons(cqe2->coalesced_size - sizeof(struct ether_header));
+                tcp_hdr = (struct tcphdr *)((char*)ip4_hdr + sizeof(struct ip));
+        }else {
+        	ip6 = (struct ip6_hdr *)((char*)eh + sizeof(struct ether_header));
+                ip6->ip6_ctlun.ip6_un1.ip6_un1_hlim = cqe2->frame_lifespan;
+                payload_len = cqe2->coalesced_size - sizeof(struct ether_header)
+                                                - sizeof(struct ip6_hdr);
+                ip6->ip6_ctlun.ip6_un1.ip6_un1_plen = htons(payload_len);
+                tcp_hdr = (struct tcphdr *)((char*)ip6 + sizeof(struct ip6_hdr));
+        }
+
+        /* correct tcp header */
+        tcp_hdr->th_ack = htonl(cqe2->tcp_ack_num);
+        if(cqe2->push) {
+        	tcp_hdr->th_flags |= TH_PUSH;
+        }
+        tcp_hdr->th_win = htons(cqe2->tcp_window);
+        tcp_hdr->th_sum = 0xffff;
+        if(cqe2->ts_opt) {
+                p = (uint32_t *)((char*)tcp_hdr + sizeof(struct tcphdr) + 2);
+                *p = cqe1->tcp_timestamp_val;
+                *(p+1) = cqe1->tcp_timestamp_ecr;
+        }
+
+	return;
+}
+
+static void
+oce_rx_mbuf_chain(struct oce_rq *rq, struct oce_common_cqe_info *cqe_info, struct mbuf **m)
+{
+	POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
+        uint32_t i = 0, frag_len = 0;
+	uint32_t len = cqe_info->pkt_size;
+        struct oce_packet_desc *pd;
+        struct mbuf *tail = NULL;
+
+        for (i = 0; i < cqe_info->num_frags; i++) {
+                if (rq->ring->cidx == rq->ring->pidx) {
+                        device_printf(sc->dev,
+                                  "oce_rx_mbuf_chain: Invalid RX completion - Queue is empty\n");
+                        return;
+                }
+                pd = &rq->pckts[rq->ring->cidx];
+
+                bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
+                bus_dmamap_unload(rq->tag, pd->map);
+		RING_GET(rq->ring, 1);
+                rq->pending--;
+
+                frag_len = (len > rq->cfg.frag_size) ? rq->cfg.frag_size : len;
+                pd->mbuf->m_len = frag_len;
+
+                if (tail != NULL) {
+                        /* additional fragments */
+                        pd->mbuf->m_flags &= ~M_PKTHDR;
+                        tail->m_next = pd->mbuf;
+			if(rq->islro)
+                        	tail->m_nextpkt = NULL;
+                        tail = pd->mbuf;
+                } else {
+                        /* first fragment, fill out much of the packet header */
+                        pd->mbuf->m_pkthdr.len = len;
+			if(rq->islro)
+                        	pd->mbuf->m_nextpkt = NULL;
+                        pd->mbuf->m_pkthdr.csum_flags = 0;
+                        if (IF_CSUM_ENABLED(sc)) {
+                                if (cqe_info->l4_cksum_pass) {
+                                        if(!cqe_info->ipv6_frame) { /* IPV4 */
+                                                pd->mbuf->m_pkthdr.csum_flags |=
+                                                        (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
+                                        }else { /* IPV6 frame */
+						if(rq->islro) {
+                                                	pd->mbuf->m_pkthdr.csum_flags |=
+                                                        (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
+						}
+                                        }
+                                        pd->mbuf->m_pkthdr.csum_data = 0xffff;
+                                }
+                                if (cqe_info->ip_cksum_pass) {
+                                        pd->mbuf->m_pkthdr.csum_flags |=
+                                               (CSUM_IP_CHECKED|CSUM_IP_VALID);
+                                }
+                        }
+                        *m = tail = pd->mbuf;
+               }
+                pd->mbuf = NULL;
+                len -= frag_len;
+        }
+
+        return;
+}
+
+static void
+oce_rx_lro(struct oce_rq *rq, struct nic_hwlro_singleton_cqe *cqe, struct nic_hwlro_cqe_part2 *cqe2)
+{
+        POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
+        struct nic_hwlro_cqe_part1 *cqe1 = NULL;
+        struct mbuf *m = NULL;
+	struct oce_common_cqe_info cq_info;
+
+	/* parse cqe */
+        if(cqe2 == NULL) {
+                cq_info.pkt_size =  cqe->pkt_size;
+                cq_info.vtag = cqe->vlan_tag;
+                cq_info.l4_cksum_pass = cqe->l4_cksum_pass;
+                cq_info.ip_cksum_pass = cqe->ip_cksum_pass;
+                cq_info.ipv6_frame = cqe->ipv6_frame;
+                cq_info.vtp = cqe->vtp;
+                cq_info.qnq = cqe->qnq;
+        }else {
+                cqe1 = (struct nic_hwlro_cqe_part1 *)cqe;
+                cq_info.pkt_size =  cqe2->coalesced_size;
+                cq_info.vtag = cqe2->vlan_tag;
+                cq_info.l4_cksum_pass = cqe2->l4_cksum_pass;
+                cq_info.ip_cksum_pass = cqe2->ip_cksum_pass;
+                cq_info.ipv6_frame = cqe2->ipv6_frame;
+                cq_info.vtp = cqe2->vtp;
+                cq_info.qnq = cqe1->qnq;
+        }
+        
+	cq_info.vtag = BSWAP_16(cq_info.vtag);
+
+        cq_info.num_frags = cq_info.pkt_size / rq->cfg.frag_size;
+        if(cq_info.pkt_size % rq->cfg.frag_size)
+                cq_info.num_frags++;
+
+	oce_rx_mbuf_chain(rq, &cq_info, &m);
+
+	if (m) {
+		if(cqe2) {
+			//assert(cqe2->valid != 0);
+			
+			//assert(cqe2->cqe_type != 2);
+			oce_correct_header(m, cqe1, cqe2);
+		}
+
+		m->m_pkthdr.rcvif = sc->ifp;
+#if __FreeBSD_version >= 800000
+		if (rq->queue_index)
+			m->m_pkthdr.flowid = (rq->queue_index - 1);
+		else
+			m->m_pkthdr.flowid = rq->queue_index;
+		M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE);
+#endif
+		/* This deternies if vlan tag is Valid */
+		if (cq_info.vtp) {
+			if (sc->function_mode & FNM_FLEX10_MODE) {
+				/* FLEX10. If QnQ is not set, neglect VLAN */
+				if (cq_info.qnq) {
+					m->m_pkthdr.ether_vtag = cq_info.vtag;
+					m->m_flags |= M_VLANTAG;
+				}
+			} else if (sc->pvid != (cq_info.vtag & VLAN_VID_MASK))  {
+				/* In UMC mode generally pvid will be striped by
+				   hw. But in some cases we have seen it comes
+				   with pvid. So if pvid == vlan, neglect vlan.
+				 */
+				m->m_pkthdr.ether_vtag = cq_info.vtag;
+				m->m_flags |= M_VLANTAG;
+			}
+		}
+		if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, 1);
+		
+		(*sc->ifp->if_input) (sc->ifp, m);
+
+		/* Update rx stats per queue */
+		rq->rx_stats.rx_pkts++;
+		rq->rx_stats.rx_bytes += cq_info.pkt_size;
+		rq->rx_stats.rx_frags += cq_info.num_frags;
+		rq->rx_stats.rx_ucast_pkts++;
+	}
+        return;
+}
+
+static void
+oce_rx(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe)
 {
-	uint32_t out;
-	struct oce_packet_desc *pd;
 	POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
-	int i, len, frag_len;
-	struct mbuf *m = NULL, *tail = NULL;
-	uint16_t vtag;
+	int len;
+	struct mbuf *m = NULL;
+	struct oce_common_cqe_info cq_info;
+	uint16_t vtag = 0;
+
+	/* Is it a flush compl that has no data */
+	if(!cqe->u0.s.num_fragments)
+		goto exit;
 
 	len = cqe->u0.s.pkt_size;
 	if (!len) {
 		/*partial DMA workaround for Lancer*/
-		oce_discard_rx_comp(rq, cqe);
+		oce_discard_rx_comp(rq, cqe->u0.s.num_fragments);
+		goto exit;
+	}
+
+	if (!oce_cqe_portid_valid(sc, cqe)) {
+		oce_discard_rx_comp(rq, cqe->u0.s.num_fragments);
 		goto exit;
 	}
 
@@ -1313,61 +1700,16 @@ oce_rx(struct oce_rq *rq, uint32_t rqe_idx, struct oce_nic_rx_cqe *cqe)
 		vtag = BSWAP_16(cqe->u0.s.vlan_tag);
 	else
 		vtag = cqe->u0.s.vlan_tag;
+	
+	cq_info.l4_cksum_pass = cqe->u0.s.l4_cksum_pass;
+	cq_info.ip_cksum_pass = cqe->u0.s.ip_cksum_pass;
+	cq_info.ipv6_frame = cqe->u0.s.ip_ver;
+	cq_info.num_frags = cqe->u0.s.num_fragments;
+	cq_info.pkt_size = cqe->u0.s.pkt_size;
 
-
-	for (i = 0; i < cqe->u0.s.num_fragments; i++) {
-
-		if (rq->packets_out == rq->packets_in) {
-			device_printf(sc->dev,
-				  "RQ transmit descriptor missing\n");
-		}
-		out = rq->packets_out + 1;
-		if (out == OCE_RQ_PACKET_ARRAY_SIZE)
-			out = 0;
-		pd = &rq->pckts[rq->packets_out];
-		rq->packets_out = out;
-
-		bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
-		bus_dmamap_unload(rq->tag, pd->map);
-		rq->pending--;
-
-		frag_len = (len > rq->cfg.frag_size) ? rq->cfg.frag_size : len;
-		pd->mbuf->m_len = frag_len;
-
-		if (tail != NULL) {
-			/* additional fragments */
-			pd->mbuf->m_flags &= ~M_PKTHDR;
-			tail->m_next = pd->mbuf;
-			tail = pd->mbuf;
-		} else {
-			/* first fragment, fill out much of the packet header */
-			pd->mbuf->m_pkthdr.len = len;
-			pd->mbuf->m_pkthdr.csum_flags = 0;
-			if (IF_CSUM_ENABLED(sc)) {
-				if (cqe->u0.s.l4_cksum_pass) {
-					pd->mbuf->m_pkthdr.csum_flags |=
-					    (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
-					pd->mbuf->m_pkthdr.csum_data = 0xffff;
-				}
-				if (cqe->u0.s.ip_cksum_pass) {
-					if (!cqe->u0.s.ip_ver) { /* IPV4 */
-						pd->mbuf->m_pkthdr.csum_flags |=
-						(CSUM_IP_CHECKED|CSUM_IP_VALID);
-					}
-				}
-			}
-			m = tail = pd->mbuf;
-		}
-		pd->mbuf = NULL;
-		len -= frag_len;
-	}
+	oce_rx_mbuf_chain(rq, &cq_info, &m);
 
 	if (m) {
-		if (!oce_cqe_portid_valid(sc, cqe)) {
-			 m_freem(m);
-			 goto exit;
-		} 
-
 		m->m_pkthdr.rcvif = sc->ifp;
 #if __FreeBSD_version >= 800000
 		if (rq->queue_index)
@@ -1429,31 +1771,30 @@ exit:
 }
 
 
-static void
-oce_discard_rx_comp(struct oce_rq *rq, struct oce_nic_rx_cqe *cqe)
+void
+oce_discard_rx_comp(struct oce_rq *rq, int num_frags)
 {
-	uint32_t out, i = 0;
+	uint32_t i = 0;
 	struct oce_packet_desc *pd;
 	POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
-	int num_frags = cqe->u0.s.num_fragments;
 
 	for (i = 0; i < num_frags; i++) {
-		if (rq->packets_out == rq->packets_in) {
-			device_printf(sc->dev,
-				"RQ transmit descriptor missing\n");
-		}
-		out = rq->packets_out + 1;
-		if (out == OCE_RQ_PACKET_ARRAY_SIZE)
-			out = 0;
-		pd = &rq->pckts[rq->packets_out];
-		rq->packets_out = out;
+                if (rq->ring->cidx == rq->ring->pidx) {
+                        device_printf(sc->dev,
+                                "oce_discard_rx_comp: Invalid RX completion - Queue is empty\n");
+                        return;
+                }
+                pd = &rq->pckts[rq->ring->cidx];
+                bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
+                bus_dmamap_unload(rq->tag, pd->map);
+                if (pd->mbuf != NULL) {
+                        m_freem(pd->mbuf);
+                        pd->mbuf = NULL;
+                }
 
-		bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
-		bus_dmamap_unload(rq->tag, pd->map);
-		rq->pending--;
-		m_freem(pd->mbuf);
+		RING_GET(rq->ring, 1);
+                rq->pending--;
 	}
-
 }
 
 
@@ -1493,7 +1834,7 @@ oce_cqe_portid_valid(POCE_SOFTC sc, struct oce_nic_rx_cqe *cqe)
 }
 
 #if defined(INET6) || defined(INET)
-static void
+void
 oce_rx_flush_lro(struct oce_rq *rq)
 {
 	struct lro_ctrl	*lro = &rq->lro;
@@ -1553,27 +1894,30 @@ oce_alloc_rx_bufs(struct oce_rq *rq, int count)
 	int nsegs, added = 0;
 	struct oce_nic_rqe *rqe;
 	pd_rxulp_db_t rxdb_reg;
+	uint32_t val = 0;
+	uint32_t oce_max_rq_posts = 64;
 
 	bzero(&rxdb_reg, sizeof(pd_rxulp_db_t));
 	for (i = 0; i < count; i++) {
-		in = rq->packets_in + 1;
-		if (in == OCE_RQ_PACKET_ARRAY_SIZE)
-			in = 0;
-		if (in == rq->packets_out)
-			break;	/* no more room */
-
-		pd = &rq->pckts[rq->packets_in];
-		pd->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
-		if (pd->mbuf == NULL)
+		in = (rq->ring->pidx + 1) % OCE_RQ_PACKET_ARRAY_SIZE;
+
+		pd = &rq->pckts[rq->ring->pidx];
+		pd->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, oce_rq_buf_size);
+		if (pd->mbuf == NULL) {
+			device_printf(sc->dev, "mbuf allocation failed, size = %d\n",oce_rq_buf_size);
 			break;
+		}
+		pd->mbuf->m_nextpkt = NULL;
+
+		pd->mbuf->m_len = pd->mbuf->m_pkthdr.len = rq->cfg.frag_size;
 
-		pd->mbuf->m_len = pd->mbuf->m_pkthdr.len = MCLBYTES;
 		rc = bus_dmamap_load_mbuf_sg(rq->tag,
 					     pd->map,
 					     pd->mbuf,
 					     segs, &nsegs, BUS_DMA_NOWAIT);
 		if (rc) {
 			m_free(pd->mbuf);
+			device_printf(sc->dev, "bus_dmamap_load_mbuf_sg failed rc = %d\n", rc);
 			break;
 		}
 
@@ -1582,7 +1926,6 @@ oce_alloc_rx_bufs(struct oce_rq *rq, int count)
 			continue;
 		}
 
-		rq->packets_in = in;
 		bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_PREREAD);
 
 		rqe = RING_GET_PRODUCER_ITEM_VA(rq->ring, struct oce_nic_rqe);
@@ -1593,23 +1936,124 @@ oce_alloc_rx_bufs(struct oce_rq *rq, int count)
 		added++;
 		rq->pending++;
 	}
+	oce_max_rq_posts = sc->enable_hwlro ? OCE_HWLRO_MAX_RQ_POSTS : OCE_MAX_RQ_POSTS;
 	if (added != 0) {
-		for (i = added / OCE_MAX_RQ_POSTS; i > 0; i--) {
-			rxdb_reg.bits.num_posted = OCE_MAX_RQ_POSTS;
+		for (i = added / oce_max_rq_posts; i > 0; i--) {
+			rxdb_reg.bits.num_posted = oce_max_rq_posts;
 			rxdb_reg.bits.qid = rq->rq_id;
-			OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
-			added -= OCE_MAX_RQ_POSTS;
+			if(rq->islro) {
+                                val |= rq->rq_id & DB_LRO_RQ_ID_MASK;
+                                val |= oce_max_rq_posts << 16;
+                                OCE_WRITE_REG32(sc, db, DB_OFFSET, val);
+			}else {
+				OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
+			}
+			added -= oce_max_rq_posts;
 		}
 		if (added > 0) {
 			rxdb_reg.bits.qid = rq->rq_id;
 			rxdb_reg.bits.num_posted = added;
-			OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
+			if(rq->islro) {
+                                val |= rq->rq_id & DB_LRO_RQ_ID_MASK;
+                                val |= added << 16;
+                                OCE_WRITE_REG32(sc, db, DB_OFFSET, val);
+			}else {
+				OCE_WRITE_REG32(sc, db, PD_RXULP_DB, rxdb_reg.dw0);
+			}
 		}
 	}
 	
 	return 0;	
 }
 
+static void
+oce_check_rx_bufs(POCE_SOFTC sc, uint32_t num_cqes, struct oce_rq *rq)
+{
+        if (num_cqes) {
+                oce_arm_cq(sc, rq->cq->cq_id, num_cqes, FALSE);
+		if(!sc->enable_hwlro) {
+			if((OCE_RQ_PACKET_ARRAY_SIZE - rq->pending) > 1)
+				oce_alloc_rx_bufs(rq, ((OCE_RQ_PACKET_ARRAY_SIZE - rq->pending) - 1));
+		}else {
+                	if ((OCE_RQ_PACKET_ARRAY_SIZE -1 - rq->pending) > 64)
+                        	oce_alloc_rx_bufs(rq, 64);
+        	}
+	}
+
+        return;
+}
+
+uint16_t
+oce_rq_handler_lro(void *arg)
+{
+        struct oce_rq *rq = (struct oce_rq *)arg;
+        struct oce_cq *cq = rq->cq;
+        POCE_SOFTC sc = rq->parent;
+        struct nic_hwlro_singleton_cqe *cqe;
+        struct nic_hwlro_cqe_part2 *cqe2;
+        int num_cqes = 0;
+
+	LOCK(&rq->rx_lock);
+        bus_dmamap_sync(cq->ring->dma.tag,cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
+        cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct nic_hwlro_singleton_cqe);
+        while (cqe->valid) {
+                if(cqe->cqe_type == 0) { /* singleton cqe */
+			/* we should not get singleton cqe after cqe1 on same rq */
+			if(rq->cqe_firstpart != NULL) {
+				device_printf(sc->dev, "Got singleton cqe after cqe1 \n");
+				goto exit_rq_handler_lro;
+			}							
+                        if(cqe->error != 0) {
+                                rq->rx_stats.rxcp_err++;
+				if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
+                        }
+                        oce_rx_lro(rq, cqe, NULL);
+                        rq->rx_stats.rx_compl++;
+                        cqe->valid = 0;
+                        RING_GET(cq->ring, 1);
+                        num_cqes++;
+                        if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
+                                break;
+                }else if(cqe->cqe_type == 0x1) { /* first part */
+			/* we should not get cqe1 after cqe1 on same rq */
+			if(rq->cqe_firstpart != NULL) {
+				device_printf(sc->dev, "Got cqe1 after cqe1 \n");
+				goto exit_rq_handler_lro;
+			}
+			rq->cqe_firstpart = (struct nic_hwlro_cqe_part1 *)cqe;
+                        RING_GET(cq->ring, 1);
+                }else if(cqe->cqe_type == 0x2) { /* second part */
+			cqe2 = (struct nic_hwlro_cqe_part2 *)cqe;
+                        if(cqe2->error != 0) {
+                                rq->rx_stats.rxcp_err++;
+				if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
+                        }
+			/* We should not get cqe2 without cqe1 */
+			if(rq->cqe_firstpart == NULL) {
+				device_printf(sc->dev, "Got cqe2 without cqe1 \n");
+				goto exit_rq_handler_lro;
+			}
+                        oce_rx_lro(rq, (struct nic_hwlro_singleton_cqe *)rq->cqe_firstpart, cqe2);
+
+                        rq->rx_stats.rx_compl++;
+                        rq->cqe_firstpart->valid = 0;
+                        cqe2->valid = 0;
+			rq->cqe_firstpart = NULL;
+
+                        RING_GET(cq->ring, 1);
+                        num_cqes += 2;
+                        if (num_cqes >= (IS_XE201(sc) ? 8 : oce_max_rsp_handled))
+                                break;
+		}
+
+                bus_dmamap_sync(cq->ring->dma.tag,cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
+                cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct nic_hwlro_singleton_cqe);
+        }
+	oce_check_rx_bufs(sc, num_cqes, rq);
+exit_rq_handler_lro:
+	UNLOCK(&rq->rx_lock);
+	return 0;
+}
 
 /* Handle the Completion Queue for receive */
 uint16_t
@@ -1619,23 +2063,26 @@ oce_rq_handler(void *arg)
 	struct oce_cq *cq = rq->cq;
 	POCE_SOFTC sc = rq->parent;
 	struct oce_nic_rx_cqe *cqe;
-	int num_cqes = 0, rq_buffers_used = 0;
-
+	int num_cqes = 0;
 
+	if(rq->islro) {
+		oce_rq_handler_lro(arg);
+		return 0;
+	}
+	LOCK(&rq->rx_lock);
 	bus_dmamap_sync(cq->ring->dma.tag,
 			cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
 	cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
 	while (cqe->u0.dw[2]) {
 		DW_SWAP((uint32_t *) cqe, sizeof(oce_rq_cqe));
 
-		RING_GET(rq->ring, 1);
 		if (cqe->u0.s.error == 0) {
-			oce_rx(rq, cqe->u0.s.frag_index, cqe);
+			oce_rx(rq, cqe);
 		} else {
 			rq->rx_stats.rxcp_err++;
 			if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 1);
 			/* Post L3/L4 errors to stack.*/
-			oce_rx(rq, cqe->u0.s.frag_index, cqe);
+			oce_rx(rq, cqe);
 		}
 		rq->rx_stats.rx_compl++;
 		cqe->u0.dw[2] = 0;
@@ -1657,17 +2104,12 @@ oce_rq_handler(void *arg)
 	}
 
 #if defined(INET6) || defined(INET)
-	if (IF_LRO_ENABLED(sc))
-		oce_rx_flush_lro(rq);
+        if (IF_LRO_ENABLED(sc))
+                oce_rx_flush_lro(rq);
 #endif
-	
-	if (num_cqes) {
-		oce_arm_cq(sc, cq->cq_id, num_cqes, FALSE);
-		rq_buffers_used = OCE_RQ_PACKET_ARRAY_SIZE - rq->pending;
-		if (rq_buffers_used > 1)
-			oce_alloc_rx_bufs(rq, (rq_buffers_used - 1));
-	}
 
+	oce_check_rx_bufs(sc, num_cqes, rq);
+	UNLOCK(&rq->rx_lock);
 	return 0;
 
 }
@@ -1896,45 +2338,53 @@ oce_eqd_set_periodic(POCE_SOFTC sc)
 	struct oce_eq *eqo;
 	uint64_t now = 0, delta;
 	int eqd, i, num = 0;
-	uint32_t ips = 0;
-	int tps;
+	uint32_t tx_reqs = 0, rxpkts = 0, pps;
+	struct oce_wq *wq;
+	struct oce_rq *rq;
+
+	#define ticks_to_msecs(t)       (1000 * (t) / hz)
 
 	for (i = 0 ; i < sc->neqs; i++) {
 		eqo = sc->eq[i];
 		aic = &sc->aic_obj[i];
 		/* When setting the static eq delay from the user space */
 		if (!aic->enable) {
+			if (aic->ticks)
+				aic->ticks = 0;
 			eqd = aic->et_eqd;
 			goto modify_eqd;
 		}
 
+		rq = sc->rq[i];
+		rxpkts = rq->rx_stats.rx_pkts;
+		wq = sc->wq[i];
+		tx_reqs = wq->tx_stats.tx_reqs;
 		now = ticks;
 
-		/* Over flow check */
-		if ((now < aic->ticks) || (eqo->intr < aic->intr_prev))
-			goto done;
-
-		delta = now - aic->ticks;
-		tps = delta/hz;
-
-		/* Interrupt rate based on elapsed ticks */
-		if(tps)
-			ips = (uint32_t)(eqo->intr - aic->intr_prev) / tps;
+		if (!aic->ticks || now < aic->ticks ||
+		    rxpkts < aic->prev_rxpkts || tx_reqs < aic->prev_txreqs) {
+			aic->prev_rxpkts = rxpkts;
+			aic->prev_txreqs = tx_reqs;
+			aic->ticks = now;
+			continue;
+		}
 
-		if (ips > INTR_RATE_HWM)
-			eqd = aic->cur_eqd + 20;
-		else if (ips < INTR_RATE_LWM)
-			eqd = aic->cur_eqd / 2;
-		else
-			goto done;
+		delta = ticks_to_msecs(now - aic->ticks);
 
-		if (eqd < 10)
+		pps = (((uint32_t)(rxpkts - aic->prev_rxpkts) * 1000) / delta) +
+		      (((uint32_t)(tx_reqs - aic->prev_txreqs) * 1000) / delta);
+		eqd = (pps / 15000) << 2;
+		if (eqd < 8)
 			eqd = 0;
 
 		/* Make sure that the eq delay is in the known range */
 		eqd = min(eqd, aic->max_eqd);
 		eqd = max(eqd, aic->min_eqd);
 
+		aic->prev_rxpkts = rxpkts;
+		aic->prev_txreqs = tx_reqs;
+		aic->ticks = now;
+
 modify_eqd:
 		if (eqd != aic->cur_eqd) {
 			set_eqd[num].delay_multiplier = (eqd * 65)/100;
@@ -1942,14 +2392,16 @@ modify_eqd:
 			aic->cur_eqd = eqd;
 			num++;
 		}
-done:
-		aic->intr_prev = eqo->intr;
-		aic->ticks = now;
 	}
 
 	/* Is there atleast one eq that needs to be modified? */
-	if(num)
-		oce_mbox_eqd_modify_periodic(sc, set_eqd, num);
+        for(i = 0; i < num; i += 8) {
+                if((num - i) >=8 )
+                        oce_mbox_eqd_modify_periodic(sc, &set_eqd[i], 8);
+                else
+                        oce_mbox_eqd_modify_periodic(sc, &set_eqd[i], (num - i));
+        }
+
 }
 
 static void oce_detect_hw_error(POCE_SOFTC sc)
@@ -2037,6 +2489,44 @@ oce_local_timer(void *arg)
 	callout_reset(&sc->timer, hz, oce_local_timer, sc);
 }
 
+static void 
+oce_tx_compl_clean(POCE_SOFTC sc) 
+{
+	struct oce_wq *wq;
+	int i = 0, timeo = 0, num_wqes = 0;
+	int pending_txqs = sc->nwqs;
+
+	/* Stop polling for compls when HW has been silent for 10ms or 
+	 * hw_error or no outstanding completions expected
+	 */
+	do {
+		pending_txqs = sc->nwqs;
+		
+		for_all_wq_queues(sc, wq, i) {
+			num_wqes = oce_wq_handler(wq);
+			
+			if(num_wqes)
+				timeo = 0;
+
+			if(!wq->ring->num_used)
+				pending_txqs--;
+		}
+
+		if (pending_txqs == 0 || ++timeo > 10 || sc->hw_error)
+			break;
+
+		DELAY(1000);
+	} while (TRUE);
+
+	for_all_wq_queues(sc, wq, i) {
+		while(wq->ring->num_used) {
+			LOCK(&wq->tx_compl_lock);
+			oce_process_tx_completion(wq);
+			UNLOCK(&wq->tx_compl_lock);
+		}
+	}	
+		
+}
 
 /* NOTE : This should only be called holding
  *        DEVICE_LOCK.
@@ -2044,28 +2534,14 @@ oce_local_timer(void *arg)
 static void
 oce_if_deactivate(POCE_SOFTC sc)
 {
-	int i, mtime = 0;
-	int wait_req = 0;
+	int i;
 	struct oce_rq *rq;
 	struct oce_wq *wq;
 	struct oce_eq *eq;
 
 	sc->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
 
-	/*Wait for max of 400ms for TX completions to be done */
-	while (mtime < 400) {
-		wait_req = 0;
-		for_all_wq_queues(sc, wq, i) {
-			if (wq->ring->num_used) {
-				wait_req = 1;
-				DELAY(1);
-				break;
-			}
-		}
-		mtime += 1;
-		if (!wait_req)
-			break;
-	}
+	oce_tx_compl_clean(sc);
 
 	/* Stop intrs and finish any bottom halves pending */
 	oce_hw_intr_disable(sc);
@@ -2152,6 +2628,50 @@ process_link_state(POCE_SOFTC sc, struct oce_async_cqe_link_state *acqe)
 }
 
 
+static void oce_async_grp5_osbmc_process(POCE_SOFTC sc,
+					 struct oce_async_evt_grp5_os2bmc *evt)
+{
+	DW_SWAP(evt, sizeof(struct oce_async_evt_grp5_os2bmc));
+	if (evt->u.s.mgmt_enable)
+		sc->flags |= OCE_FLAGS_OS2BMC;
+	else
+		return;
+
+	sc->bmc_filt_mask = evt->u.s.arp_filter;
+	sc->bmc_filt_mask |= (evt->u.s.dhcp_client_filt << 1);
+	sc->bmc_filt_mask |= (evt->u.s.dhcp_server_filt << 2);
+	sc->bmc_filt_mask |= (evt->u.s.net_bios_filt << 3);
+	sc->bmc_filt_mask |= (evt->u.s.bcast_filt << 4);
+	sc->bmc_filt_mask |= (evt->u.s.ipv6_nbr_filt << 5);
+	sc->bmc_filt_mask |= (evt->u.s.ipv6_ra_filt << 6);
+	sc->bmc_filt_mask |= (evt->u.s.ipv6_ras_filt << 7);
+	sc->bmc_filt_mask |= (evt->u.s.mcast_filt << 8);
+}
+
+
+static void oce_process_grp5_events(POCE_SOFTC sc, struct oce_mq_cqe *cqe)
+{
+	struct oce_async_event_grp5_pvid_state *gcqe;
+	struct oce_async_evt_grp5_os2bmc *bmccqe;
+
+	switch (cqe->u0.s.async_type) {
+	case ASYNC_EVENT_PVID_STATE:
+		/* GRP5 PVID */
+		gcqe = (struct oce_async_event_grp5_pvid_state *)cqe;
+		if (gcqe->enabled)
+			sc->pvid = gcqe->tag & VLAN_VID_MASK;
+		else
+			sc->pvid = 0;
+		break;
+	case ASYNC_EVENT_OS2BMC:
+		bmccqe = (struct oce_async_evt_grp5_os2bmc *)cqe;
+		oce_async_grp5_osbmc_process(sc, bmccqe);
+		break;
+	default:
+		break;
+	}
+}
+
 /* Handle the Completion Queue for the Mailbox/Async notifications */
 uint16_t
 oce_mq_handler(void *arg)
@@ -2162,7 +2682,6 @@ oce_mq_handler(void *arg)
 	int num_cqes = 0, evt_type = 0, optype = 0;
 	struct oce_mq_cqe *cqe;
 	struct oce_async_cqe_link_state *acqe;
-	struct oce_async_event_grp5_pvid_state *gcqe;
 	struct oce_async_event_qnq *dbgcqe;
 
 
@@ -2179,21 +2698,11 @@ oce_mq_handler(void *arg)
 				/* Link status evt */
 				acqe = (struct oce_async_cqe_link_state *)cqe;
 				process_link_state(sc, acqe);
-			} else if ((evt_type == ASYNC_EVENT_GRP5) &&
-				   (optype == ASYNC_EVENT_PVID_STATE)) {
-				/* GRP5 PVID */
-				gcqe = 
-				(struct oce_async_event_grp5_pvid_state *)cqe;
-				if (gcqe->enabled)
-					sc->pvid = gcqe->tag & VLAN_VID_MASK;
-				else
-					sc->pvid = 0;
-				
-			}
-			else if(evt_type == ASYNC_EVENT_CODE_DEBUG &&
-				optype == ASYNC_EVENT_DEBUG_QNQ) {
-				dbgcqe = 
-				(struct oce_async_event_qnq *)cqe;
+			} else if (evt_type == ASYNC_EVENT_GRP5) {
+				oce_process_grp5_events(sc, cqe);
+			} else if (evt_type == ASYNC_EVENT_CODE_DEBUG &&
+					optype == ASYNC_EVENT_DEBUG_QNQ) {
+				dbgcqe =  (struct oce_async_event_qnq *)cqe;
 				if(dbgcqe->valid)
 					sc->qnqid = dbgcqe->vlan_tag;
 				sc->qnq_debug_event = TRUE;
@@ -2303,7 +2812,8 @@ oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete)
 	if(sc->pvid) {
 		if(!vlan_tag)
 			vlan_tag = sc->pvid;
-		*complete = FALSE;
+		if (complete)
+			*complete = FALSE;
 	}
 
 	if(vlan_tag) {
@@ -2312,7 +2822,9 @@ oce_insert_vlan_tag(POCE_SOFTC sc, struct mbuf *m, boolean_t *complete)
 
 	if(sc->qnqid) {
 		m = ether_vlanencap(m, sc->qnqid);
-		*complete = FALSE;
+
+		if (complete)
+			*complete = FALSE;
 	}
 	return m;
 }
@@ -2353,3 +2865,129 @@ oce_get_config(POCE_SOFTC sc)
 		sc->max_vlans = MAX_VLANFILTER_SIZE; 
 	}
 }
+
+static void
+oce_rdma_close(void)
+{
+  if (oce_rdma_if != NULL) {
+    oce_rdma_if = NULL;
+  }
+}
+
+static void
+oce_get_mac_addr(POCE_SOFTC sc, uint8_t *macaddr)
+{
+  memcpy(macaddr, sc->macaddr.mac_addr, 6);
+}
+
+int
+oce_register_rdma(POCE_RDMA_INFO rdma_info, POCE_RDMA_IF rdma_if)
+{
+  POCE_SOFTC sc;
+  struct oce_dev_info di;
+  int i;
+
+  if ((rdma_info == NULL) || (rdma_if == NULL)) {
+    return -EINVAL;
+  }
+
+  if ((rdma_info->size != OCE_RDMA_INFO_SIZE) ||
+      (rdma_if->size != OCE_RDMA_IF_SIZE)) {
+    return -ENXIO;
+  }
+
+  rdma_info->close = oce_rdma_close;
+  rdma_info->mbox_post = oce_mbox_post;
+  rdma_info->common_req_hdr_init = mbx_common_req_hdr_init;
+  rdma_info->get_mac_addr = oce_get_mac_addr;
+
+  oce_rdma_if = rdma_if;
+
+  sc = softc_head;
+  while (sc != NULL) {
+    if (oce_rdma_if->announce != NULL) {
+      memset(&di, 0, sizeof(di));
+      di.dev = sc->dev;
+      di.softc = sc;
+      di.ifp = sc->ifp;
+      di.db_bhandle = sc->db_bhandle;
+      di.db_btag = sc->db_btag;
+      di.db_page_size = 4096;
+      if (sc->flags & OCE_FLAGS_USING_MSIX) {
+        di.intr_mode = OCE_INTERRUPT_MODE_MSIX;
+      } else if (sc->flags & OCE_FLAGS_USING_MSI) {
+        di.intr_mode = OCE_INTERRUPT_MODE_MSI;
+      } else {
+        di.intr_mode = OCE_INTERRUPT_MODE_INTX;
+      }
+      di.dev_family = OCE_GEN2_FAMILY; // fixme: must detect skyhawk
+      if (di.intr_mode != OCE_INTERRUPT_MODE_INTX) {
+        di.msix.num_vectors = sc->intr_count + sc->roce_intr_count;
+        di.msix.start_vector = sc->intr_count;
+        for (i=0; i<di.msix.num_vectors; i++) {
+          di.msix.vector_list[i] = sc->intrs[i].vector;
+        }
+      } else {
+      }
+      memcpy(di.mac_addr, sc->macaddr.mac_addr, 6);
+      di.vendor_id = pci_get_vendor(sc->dev);
+      di.dev_id = pci_get_device(sc->dev);
+
+      if (sc->rdma_flags & OCE_RDMA_FLAG_SUPPORTED) {
+          di.flags  |= OCE_RDMA_INFO_RDMA_SUPPORTED;
+      }
+
+      rdma_if->announce(&di);
+      sc = sc->next;
+    }
+  }
+
+  return 0;
+}
+
+static void
+oce_read_env_variables( POCE_SOFTC sc )
+{
+	char *value = NULL;
+	int rc = 0;
+
+        /* read if user wants to enable hwlro or swlro */
+        //value = getenv("oce_enable_hwlro");
+        if(value && IS_SH(sc)) {
+                sc->enable_hwlro = strtol(value, NULL, 10);
+                if(sc->enable_hwlro) {
+                        rc = oce_mbox_nic_query_lro_capabilities(sc, NULL, NULL);
+                        if(rc) {
+                                device_printf(sc->dev, "no hardware lro support\n");
+                		device_printf(sc->dev, "software lro enabled\n");
+                                sc->enable_hwlro = 0;
+                        }else {
+                                device_printf(sc->dev, "hardware lro enabled\n");
+				oce_max_rsp_handled = 32;
+                        }
+                }else {
+                        device_printf(sc->dev, "software lro enabled\n");
+                }
+        }else {
+                sc->enable_hwlro = 0;
+        }
+
+        /* read mbuf size */
+        //value = getenv("oce_rq_buf_size");
+        if(value && IS_SH(sc)) {
+                oce_rq_buf_size = strtol(value, NULL, 10);
+                switch(oce_rq_buf_size) {
+                case 2048:
+                case 4096:
+                case 9216:
+                case 16384:
+                        break;
+
+                default:
+                        device_printf(sc->dev, " Supported oce_rq_buf_size values are 2K, 4K, 9K, 16K \n");
+                        oce_rq_buf_size = 2048;
+                }
+        }
+
+	return;
+}
diff --git a/sys/dev/oce/oce_if.h b/sys/dev/oce/oce_if.h
index 99707e496783..d6c1a0a454d4 100644
--- a/sys/dev/oce/oce_if.h
+++ b/sys/dev/oce/oce_if.h
@@ -85,13 +85,14 @@
 #include <netinet/tcp.h>
 #include <netinet/sctp.h>
 #include <netinet/tcp_lro.h>
+#include <netinet/icmp6.h>
 
 #include <machine/bus.h>
 
 #include "oce_hw.h"
 
 /* OCE device driver module component revision informaiton */
-#define COMPONENT_REVISION "10.0.664.0"
+#define COMPONENT_REVISION "11.0.50.0"
 
 /* OCE devices supported by this driver */
 #define PCI_VENDOR_EMULEX		0x10df	/* Emulex */
@@ -142,7 +143,6 @@ extern int mp_ncpus;			/* system's total active cpu cores */
 
 #define OCE_DEFAULT_WQ_EQD		16
 #define OCE_MAX_PACKET_Q		16
-#define OCE_RQ_BUF_SIZE			2048
 #define OCE_LSO_MAX_SIZE		(64 * 1024)
 #define LONG_TIMEOUT			30
 #define OCE_MAX_JUMBO_FRAME_SIZE	9018
@@ -150,11 +150,15 @@ extern int mp_ncpus;			/* system's total active cpu cores */
 						ETHER_VLAN_ENCAP_LEN - \
 						ETHER_HDR_LEN)
 
+#define OCE_RDMA_VECTORS                2
+
 #define OCE_MAX_TX_ELEMENTS		29
 #define OCE_MAX_TX_DESC			1024
 #define OCE_MAX_TX_SIZE			65535
+#define OCE_MAX_TSO_SIZE		(65535 - ETHER_HDR_LEN)
 #define OCE_MAX_RX_SIZE			4096
 #define OCE_MAX_RQ_POSTS		255
+#define OCE_HWLRO_MAX_RQ_POSTS		64
 #define OCE_DEFAULT_PROMISCUOUS		0
 
 
@@ -503,7 +507,7 @@ struct oce_drv_stats {
 #define INTR_RATE_LWM                   10000
 
 #define OCE_MAX_EQD 128u
-#define OCE_MIN_EQD 50u
+#define OCE_MIN_EQD 0u
 
 struct oce_set_eqd {
 	uint32_t eq_id;
@@ -518,7 +522,8 @@ struct oce_aic_obj {             /* Adaptive interrupt coalescing (AIC) info */
 	uint32_t  cur_eqd;            /* in usecs */
 	uint32_t  et_eqd;             /* configured value when aic is off */
 	uint64_t  ticks;
-	uint64_t  intr_prev;
+	uint64_t  prev_rxpkts;
+	uint64_t  prev_txreqs;
 };
 
 #define MAX_LOCK_DESC_LEN			32
@@ -609,7 +614,8 @@ struct oce_eq {
 enum cq_len {
 	CQ_LEN_256  = 256,
 	CQ_LEN_512  = 512,
-	CQ_LEN_1024 = 1024
+	CQ_LEN_1024 = 1024,
+	CQ_LEN_2048 = 2048
 };
 
 struct cq_config {
@@ -685,6 +691,7 @@ struct oce_tx_queue_stats {
 
 struct oce_wq {
 	OCE_LOCK tx_lock;
+	OCE_LOCK tx_compl_lock;
 	void *parent;
 	oce_ring_buffer_t *ring;
 	struct oce_cq *cq;
@@ -730,6 +737,7 @@ struct oce_rx_queue_stats {
 	uint32_t rx_frags;
 	uint32_t prev_rx_frags;
 	uint32_t rx_fps;
+	uint32_t rx_drops_no_frags;  /* HW has no fetched frags */
 };
 
 
@@ -744,8 +752,6 @@ struct oce_rq {
 	void *pad1;
 	bus_dma_tag_t tag;
 	struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
-	uint32_t packets_in;
-	uint32_t packets_out;
 	uint32_t pending;
 #ifdef notdef
 	struct mbuf *head;
@@ -757,6 +763,8 @@ struct oce_rq {
 	struct oce_rx_queue_stats rx_stats;
 	struct lro_ctrl lro;
 	int lro_pkts_queued;
+	int islro;
+	struct nic_hwlro_cqe_part1 *cqe_firstpart;
 
 };
 
@@ -781,6 +789,7 @@ struct link_status {
 #define OCE_FLAGS_XE201			0x00000400
 #define OCE_FLAGS_BE2			0x00000800
 #define OCE_FLAGS_SH			0x00001000
+#define	OCE_FLAGS_OS2BMC		0x00002000
 
 #define OCE_DEV_BE2_CFG_BAR		1
 #define OCE_DEV_CFG_BAR			0
@@ -815,6 +824,7 @@ typedef struct oce_softc {
 
 	OCE_INTR_INFO intrs[OCE_MAX_EQ];
 	int intr_count;
+        int roce_intr_count;
 
 	struct ifnet *ifp;
 
@@ -824,6 +834,7 @@ typedef struct oce_softc {
 	uint8_t duplex;
 	uint32_t qos_link_speed;
 	uint32_t speed;
+	uint32_t enable_hwlro;
 
 	char fw_version[32];
 	struct mac_address_format macaddr;
@@ -881,9 +892,15 @@ typedef struct oce_softc {
 	uint16_t qnqid;
 	uint32_t pvid;
 	uint32_t max_vlans;
+	uint32_t bmc_filt_mask;
+
+        void *rdma_context;
+        uint32_t rdma_flags;
+        struct oce_softc *next;
 
 } OCE_SOFTC, *POCE_SOFTC;
 
+#define OCE_RDMA_FLAG_SUPPORTED         0x00000001
 
 
 /**************************************************
@@ -933,7 +950,7 @@ typedef struct oce_softc {
 				: (bus_space_write_1((sc)->devcfg_btag, \
 					(sc)->devcfg_bhandle,o,v)))
 
-
+void oce_rx_flush_lro(struct oce_rq *rq);
 /***********************************************************
  * DMA memory functions
  ***********************************************************/
@@ -983,6 +1000,9 @@ uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
  * cleanup  functions
  ***********************************************************/
 void oce_stop_rx(POCE_SOFTC sc);
+void oce_discard_rx_comp(struct oce_rq *rq, int num_frags);
+void oce_rx_cq_clean(struct oce_rq *rq);
+void oce_rx_cq_clean_hwlro(struct oce_rq *rq);
 void oce_intr_free(POCE_SOFTC sc);
 void oce_free_posted_rxbuf(struct oce_rq *rq);
 #if defined(INET6) || defined(INET)
@@ -1015,7 +1035,8 @@ int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable);
 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
-int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
+int oce_mbox_get_nic_stats_v1(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
+int oce_mbox_get_nic_stats_v2(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
 				uint32_t reset_stats);
 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
@@ -1086,10 +1107,16 @@ int  oce_refresh_nic_stats(POCE_SOFTC sc);
 int  oce_stats_init(POCE_SOFTC sc);
 void oce_stats_free(POCE_SOFTC sc);
 
+/* hw lro functions */
+int oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags);
+int oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable);
+int oce_mbox_create_rq_v2(struct oce_rq *rq);
+
 /* Capabilities */
 #define OCE_MODCAP_RSS			1
 #define OCE_MAX_RSP_HANDLED		64
 extern uint32_t oce_max_rsp_handled;	/* max responses */
+extern uint32_t oce_rq_buf_size;
 
 #define OCE_MAC_LOOPBACK		0x0
 #define OCE_PHY_LOOPBACK		0x1
@@ -1159,3 +1186,80 @@ static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
 		     || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
 
+struct oce_rdma_info;
+extern struct oce_rdma_if *oce_rdma_if;
+
+
+
+/* OS2BMC related */
+
+#define DHCP_CLIENT_PORT        68
+#define DHCP_SERVER_PORT        67
+#define NET_BIOS_PORT1          137
+#define NET_BIOS_PORT2          138
+#define DHCPV6_RAS_PORT         547
+
+#define BMC_FILT_BROADCAST_ARP                          ((uint32_t)(1))
+#define BMC_FILT_BROADCAST_DHCP_CLIENT                  ((uint32_t)(1 << 1))
+#define BMC_FILT_BROADCAST_DHCP_SERVER                  ((uint32_t)(1 << 2))
+#define BMC_FILT_BROADCAST_NET_BIOS                     ((uint32_t)(1 << 3))
+#define BMC_FILT_BROADCAST                              ((uint32_t)(1 << 4))
+#define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER             ((uint32_t)(1 << 5))
+#define BMC_FILT_MULTICAST_IPV6_RA                      ((uint32_t)(1 << 6))
+#define BMC_FILT_MULTICAST_IPV6_RAS                     ((uint32_t)(1 << 7))
+#define BMC_FILT_MULTICAST                              ((uint32_t)(1 << 8))
+
+#define	ND_ROUTER_ADVERT	134
+#define	ND_NEIGHBOR_ADVERT	136
+
+#define is_mc_allowed_on_bmc(sc, eh)       \
+	(!is_multicast_filt_enabled(sc) && \
+	ETHER_IS_MULTICAST(eh->ether_dhost) && \
+	!ETHER_IS_BROADCAST(eh->ether_dhost))
+
+#define is_bc_allowed_on_bmc(sc, eh)       \
+	(!is_broadcast_filt_enabled(sc) && \
+	ETHER_IS_BROADCAST(eh->ether_dhost))
+
+#define is_arp_allowed_on_bmc(sc, et)     \
+	(is_arp(et) && is_arp_filt_enabled(sc))
+
+#define is_arp(et)     (et == ETHERTYPE_ARP)
+
+#define is_arp_filt_enabled(sc)    \
+	(sc->bmc_filt_mask & (BMC_FILT_BROADCAST_ARP))
+
+#define is_dhcp_client_filt_enabled(sc)    \
+	(sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_CLIENT)
+
+#define is_dhcp_srvr_filt_enabled(sc)      \
+	(sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_SERVER)
+
+#define is_nbios_filt_enabled(sc)  \
+	(sc->bmc_filt_mask & BMC_FILT_BROADCAST_NET_BIOS)
+
+#define is_ipv6_na_filt_enabled(sc)        \
+	(sc->bmc_filt_mask &       \
+	BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER)
+
+#define is_ipv6_ra_filt_enabled(sc)        \
+	(sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RA)
+
+#define is_ipv6_ras_filt_enabled(sc)       \
+	(sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RAS)
+
+#define is_broadcast_filt_enabled(sc)      \
+	(sc->bmc_filt_mask & BMC_FILT_BROADCAST)
+
+#define is_multicast_filt_enabled(sc)      \
+	(sc->bmc_filt_mask & BMC_FILT_MULTICAST)
+
+#define is_os2bmc_enabled(sc) (sc->flags & OCE_FLAGS_OS2BMC)
+
+#define LRO_FLAGS_HASH_MODE 0x00000001
+#define LRO_FLAGS_RSS_MODE 0x00000004
+#define LRO_FLAGS_CLSC_IPV4 0x00000010
+#define LRO_FLAGS_CLSC_IPV6 0x00000020
+#define NIC_RQ_FLAGS_RSS 0x0001
+#define NIC_RQ_FLAGS_LRO 0x0020
+
diff --git a/sys/dev/oce/oce_mbox.c b/sys/dev/oce/oce_mbox.c
index cb2ae81a013d..3c303b5ae17f 100644
--- a/sys/dev/oce/oce_mbox.c
+++ b/sys/dev/oce/oce_mbox.c
@@ -495,6 +495,10 @@ oce_get_fw_config(POCE_SOFTC sc)
 	sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
 	sc->port_id	  = HOST_32(fwcmd->params.rsp.port_id);
 	sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
+	if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) ==
+	    (ULP_NIC_MODE | ULP_RDMA_MODE)) {
+	  sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED;
+	}
 	sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
 
 	if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
@@ -767,7 +771,7 @@ oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
 	
 	/* fill log2 value indicating the size of the CPU table */
 	if (rc == 0)
-		fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(i));
+		fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES));
 
 	return rc;
 }
@@ -808,9 +812,15 @@ oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
 					         RSS_ENABLE_TCP_IPV4 |
 						 RSS_ENABLE_IPV6 |
 						 RSS_ENABLE_TCP_IPV6);
-	fwcmd->params.req.flush = OCE_FLUSH;
+
+	if(!sc->enable_hwlro) 
+		fwcmd->params.req.flush = OCE_FLUSH;
+	else
+		fwcmd->params.req.flush = 0;
+
 	fwcmd->params.req.if_id = LE_32(if_id);
 
+	srandom(arc4random());	/* random entropy seed */
 	read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
 	
 	rc = oce_rss_itbl_init(sc, fwcmd);
@@ -864,7 +874,7 @@ oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable)
 		req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
 
 	if (enable & 0x02)
-		req->iface_flags = MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
+		req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
 
 	req->if_id = sc->if_id;
 
@@ -968,105 +978,59 @@ error:
 }
 
 
-
-int
-oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
-{
-	struct oce_mbx mbx;
-	struct mbx_get_nic_stats_v0 *fwcmd;
-	int rc = 0;
-
-	bzero(&mbx, sizeof(struct oce_mbx));
-
-	fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v0);
-	bzero(fwcmd, sizeof(struct mbx_get_nic_stats_v0));
-	
-	mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
-				MBX_SUBSYSTEM_NIC,
-				NIC_GET_STATS,
-				MBX_TIMEOUT_SEC,
-				sizeof(struct mbx_get_nic_stats_v0),
-				OCE_MBX_VER_V0);
-
-	mbx.u0.s.embedded = 0;
-	mbx.u0.s.sge_count = 1;
-
-	oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
-
-	mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
-	mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
-	mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats_v0);
-	
-	mbx.payload_length = sizeof(struct mbx_get_nic_stats_v0);
-
-	DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
-	
-	rc = oce_mbox_post(sc, &mbx, NULL);
-
-	oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
-
-	if (!rc)
-                rc = fwcmd->hdr.u0.rsp.status;
-	if (rc)
-		device_printf(sc->dev,
-			      "%s failed - cmd status: %d addi status: %d\n",
-			      __FUNCTION__, rc,
-			      fwcmd->hdr.u0.rsp.additional_status);
-	return rc; 
-}
-
-
-
 /**
  * @brief Function to get NIC statistics
- * @param sc 		software handle to the device
- * @param *stats	pointer to where to store statistics
- * @param reset_stats	resets statistics of set
- * @returns		0 on success, EIO on failure
- * @note		command depricated in Lancer
+ * @param sc            software handle to the device
+ * @param *stats        pointer to where to store statistics
+ * @param reset_stats   resets statistics of set
+ * @returns             0 on success, EIO on failure
+ * @note                command depricated in Lancer
  */
-int
-oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
-{
-	struct oce_mbx mbx;
-	struct mbx_get_nic_stats *fwcmd;
-	int rc = 0;
-
-	bzero(&mbx, sizeof(struct oce_mbx));
-	fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats);
-	bzero(fwcmd, sizeof(struct mbx_get_nic_stats));
-
-	mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
-				MBX_SUBSYSTEM_NIC,
-				NIC_GET_STATS,
-				MBX_TIMEOUT_SEC,
-				sizeof(struct mbx_get_nic_stats),
-				OCE_MBX_VER_V1);
-
-
-	mbx.u0.s.embedded = 0;  /* stats too large for embedded mbx rsp */
-	mbx.u0.s.sge_count = 1; /* using scatter gather instead */
-
-	oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
-	mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
-	mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
-	mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats);
-
-	mbx.payload_length = sizeof(struct mbx_get_nic_stats);
-	DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
-
-	rc = oce_mbox_post(sc, &mbx, NULL);
-	oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
-	if (!rc)
-                rc = fwcmd->hdr.u0.rsp.status;
-	if (rc)
-		device_printf(sc->dev,
-			      "%s failed - cmd status: %d addi status: %d\n",
-			      __FUNCTION__, rc,
-			      fwcmd->hdr.u0.rsp.additional_status);
-	return rc; 
+#define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) 				\
+int 											\
+oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) 		\
+{ 											\
+        struct oce_mbx mbx; 								\
+        struct mbx_get_nic_stats_v##version *fwcmd; 					\
+        int rc = 0; 									\
+											\
+        bzero(&mbx, sizeof(struct oce_mbx)); 						\
+        fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); 	\
+        bzero(fwcmd, sizeof(*fwcmd)); 							\
+											\
+        mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 					\
+                                MBX_SUBSYSTEM_NIC, 					\
+                                NIC_GET_STATS, 						\
+                                MBX_TIMEOUT_SEC, 					\
+                                sizeof(*fwcmd), 					\
+                                OCE_MBX_VER_V##version); 				\
+											\
+        mbx.u0.s.embedded = 0;  /* stats too large for embedded mbx rsp */ 		\
+        mbx.u0.s.sge_count = 1; /* using scatter gather instead */ 			\
+											\
+        oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); 				\
+        mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);		\
+        mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); 		\
+        mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); 				\
+        mbx.payload_length = sizeof(*fwcmd); 						\
+        DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 			\
+											\
+        rc = oce_mbox_post(sc, &mbx, NULL); 						\
+        oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); 				\
+        if (!rc) 									\
+                rc = fwcmd->hdr.u0.rsp.status; 						\
+        if (rc) 									\
+                device_printf(sc->dev, 							\
+                              "%s failed - cmd status: %d addi status: %d\n", 		\
+                              __FUNCTION__, rc, 					\
+                              fwcmd->hdr.u0.rsp.additional_status); 			\
+        return rc; 									\
 }
 
+OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0);
+OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1);
+OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2);
+
 
 /**
  * @brief Function to get pport (physical port) statistics
@@ -2220,3 +2184,149 @@ error:
 	return rc;
 
 }
+
+/* hw lro functions */
+
+int
+oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags)
+{
+        struct oce_mbx mbx;
+        struct mbx_nic_query_lro_capabilities *fwcmd;
+        int rc = 0;
+
+        bzero(&mbx, sizeof(struct oce_mbx));
+
+        fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload;
+        mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
+                                MBX_SUBSYSTEM_NIC,
+                                0x20,MBX_TIMEOUT_SEC,
+                                sizeof(struct mbx_nic_query_lro_capabilities),
+                                OCE_MBX_VER_V0);
+
+        mbx.u0.s.embedded = 1;
+        mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities);
+
+        rc = oce_mbox_post(sc, &mbx, NULL);
+        if (!rc)
+                rc = fwcmd->hdr.u0.rsp.status;
+        if (rc) {
+                device_printf(sc->dev,
+                              "%s failed - cmd status: %d addi status: %d\n",
+                              __FUNCTION__, rc,
+                              fwcmd->hdr.u0.rsp.additional_status);
+
+                return rc;
+        }
+        if(lro_flags)
+                *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags);
+
+        if(lro_rq_cnt)
+                *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt);
+
+        return rc;
+}
+
+int
+oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable)
+{
+        struct oce_mbx mbx;
+        struct mbx_nic_set_iface_lro_config *fwcmd;
+        int rc = 0;
+
+        bzero(&mbx, sizeof(struct oce_mbx));
+
+        fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload;
+        mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
+                                MBX_SUBSYSTEM_NIC,
+                                0x26,MBX_TIMEOUT_SEC,
+                                sizeof(struct mbx_nic_set_iface_lro_config),
+                                OCE_MBX_VER_V0);
+
+        mbx.u0.s.embedded = 1;
+        mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config);
+
+        fwcmd->params.req.iface_id = sc->if_id;
+        fwcmd->params.req.lro_flags = 0;
+
+        if(enable) {
+                fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE;
+                fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6;
+
+                fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */
+                fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */
+                fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */
+                fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */
+        }
+
+        rc = oce_mbox_post(sc, &mbx, NULL);
+        if (!rc)
+                rc = fwcmd->hdr.u0.rsp.status;
+        if (rc) {
+                device_printf(sc->dev,
+                              "%s failed - cmd status: %d addi status: %d\n",
+                              __FUNCTION__, rc,
+                              fwcmd->hdr.u0.rsp.additional_status);
+
+                return rc;
+        }
+        return rc;
+}
+
+int
+oce_mbox_create_rq_v2(struct oce_rq *rq)
+{
+        struct oce_mbx mbx;
+        struct mbx_create_nic_rq_v2 *fwcmd;
+        POCE_SOFTC sc = rq->parent;
+        int rc = 0, num_pages = 0;
+
+        if (rq->qstate == QCREATED)
+                return 0;
+
+        bzero(&mbx, sizeof(struct oce_mbx));
+
+        fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload;
+        mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
+                                MBX_SUBSYSTEM_NIC,
+                                0x08, MBX_TIMEOUT_SEC,
+                                sizeof(struct mbx_create_nic_rq_v2),
+                                OCE_MBX_VER_V2);
+
+        /* oce_page_list will also prepare pages */
+        num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
+
+        fwcmd->params.req.cq_id = rq->cq->cq_id;
+        fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
+        fwcmd->params.req.num_pages = num_pages;
+
+        fwcmd->params.req.if_id = sc->if_id;
+
+        fwcmd->params.req.max_frame_size = rq->cfg.mtu;
+        fwcmd->params.req.page_size = 1;
+        if(rq->cfg.is_rss_queue) {
+                fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO);
+        }else {
+                device_printf(sc->dev,
+                        "non rss lro queue should not be created \n");
+                goto error;
+        }
+        mbx.u0.s.embedded = 1;
+        mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2);
+
+        rc = oce_mbox_post(sc, &mbx, NULL);
+        if (!rc)
+                rc = fwcmd->hdr.u0.rsp.status;
+        if (rc) {
+                device_printf(sc->dev,
+                              "%s failed - cmd status: %d addi status: %d\n",
+                              __FUNCTION__, rc,
+                              fwcmd->hdr.u0.rsp.additional_status);
+                goto error;
+        }
+        rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
+        rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
+
+error:
+        return rc;
+}
+
diff --git a/sys/dev/oce/oce_queue.c b/sys/dev/oce/oce_queue.c
index 308c16d54846..e14621e63a3a 100644
--- a/sys/dev/oce/oce_queue.c
+++ b/sys/dev/oce/oce_queue.c
@@ -66,7 +66,7 @@ static struct oce_mq *oce_mq_create(POCE_SOFTC sc,
 				    struct oce_eq *eq, uint32_t q_len);
 static void oce_mq_free(struct oce_mq *mq);
 static int oce_destroy_q(POCE_SOFTC sc, struct oce_mbx
-			 *mbx, size_t req_size, enum qtype qtype);
+			 *mbx, size_t req_size, enum qtype qtype, int version);
 struct oce_cq *oce_cq_create(POCE_SOFTC sc,
 			     struct oce_eq *eq,
 			     uint32_t q_len,
@@ -120,9 +120,10 @@ oce_queue_init_all(POCE_SOFTC sc)
 		aic->min_eqd = OCE_MIN_EQD;
 		aic->et_eqd = OCE_MIN_EQD;
 		aic->enable = TRUE;
+	
+		sc->eq[vector] = oce_eq_create(sc, sc->enable_hwlro ? EQ_LEN_2048 : EQ_LEN_1024,
+						EQE_SIZE_4,0, vector);	
 
-		sc->eq[vector] = oce_eq_create(sc, EQ_LEN_1024, EQE_SIZE_4,
-						 0, vector);
 		if (!sc->eq[vector])
 			goto error;
 	}
@@ -169,6 +170,10 @@ oce_queue_release_all(POCE_SOFTC sc)
 	struct oce_rq *rq;
 	struct oce_eq *eq;
 
+	/* before deleting lro queues, we have to disable hwlro	*/
+	if(sc->enable_hwlro)
+		oce_mbox_nic_set_iface_lro_config(sc, 0);
+
 	for_all_rq_queues(sc, rq, i) {
 		if (rq) {
 			oce_rq_del(sc->rq[i]);
@@ -254,6 +259,7 @@ oce_wq *oce_wq_init(POCE_SOFTC sc, uint32_t q_len, uint32_t wq_type)
 
 
 	LOCK_CREATE(&wq->tx_lock, "TX_lock");
+	LOCK_CREATE(&wq->tx_compl_lock, "WQ_HANDLER_LOCK");
 	
 #if __FreeBSD_version >= 800000
 	/* Allocate buf ring for multiqueue*/
@@ -304,6 +310,7 @@ oce_wq_free(struct oce_wq *wq)
 		buf_ring_free(wq->br, M_DEVBUF);
 
 	LOCK_DESTROY(&wq->tx_lock);
+	LOCK_DESTROY(&wq->tx_compl_lock);
 	free(wq, M_DEVBUF);
 }
 
@@ -374,7 +381,7 @@ oce_wq_del(struct oce_wq *wq)
 		fwcmd = (struct mbx_delete_nic_wq *)&mbx.payload;
 		fwcmd->params.req.wq_id = wq->wq_id;
 		(void)oce_destroy_q(sc, &mbx,
-				sizeof(struct mbx_delete_nic_wq), QTYPE_WQ);
+				sizeof(struct mbx_delete_nic_wq), QTYPE_WQ, 0);
 		wq->qstate = QDELETED;
 	}
 
@@ -422,20 +429,17 @@ oce_rq *oce_rq_init(POCE_SOFTC sc,
 	rq->cfg.eqd = 0;
 	rq->lro_pkts_queued = 0;
 	rq->cfg.is_rss_queue = rss;
-	rq->packets_in = 0;
-        rq->packets_out = 0;
         rq->pending = 0;
 
 	rq->parent = (void *)sc;
 
 	rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
-				1, 0,
-				BUS_SPACE_MAXADDR,
-				BUS_SPACE_MAXADDR,
-				NULL, NULL,
-				OCE_MAX_RX_SIZE,
-				1, PAGE_SIZE, 0, NULL, NULL, &rq->tag);
-
+			1, 0,
+			BUS_SPACE_MAXADDR,
+			BUS_SPACE_MAXADDR,
+			NULL, NULL,
+			oce_rq_buf_size,
+			1, oce_rq_buf_size, 0, NULL, NULL, &rq->tag);
 	if (rc)
 		goto free_rq;
 
@@ -512,10 +516,10 @@ oce_rq_create(struct oce_rq *rq, uint32_t if_id, struct oce_eq *eq)
 	POCE_SOFTC sc = rq->parent;
 	struct oce_cq *cq;
 
-	cq = oce_cq_create(sc,
-			   eq,
-			   CQ_LEN_1024,
-			   sizeof(struct oce_nic_rx_cqe), 0, 1, 0, 3);
+	cq = oce_cq_create(sc, eq,
+		       	sc->enable_hwlro ? CQ_LEN_2048 : CQ_LEN_1024,
+			sizeof(struct oce_nic_rx_cqe), 0, 1, 0, 3);		
+			
 	if (!cq)
 		return ENXIO;
 
@@ -548,14 +552,20 @@ oce_rq_del(struct oce_rq *rq)
 	POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
 	struct oce_mbx mbx;
 	struct mbx_delete_nic_rq *fwcmd;
+	struct mbx_delete_nic_rq_v1 *fwcmd1;
 
 	if (rq->qstate == QCREATED) {
 		bzero(&mbx, sizeof(mbx));
-
-		fwcmd = (struct mbx_delete_nic_rq *)&mbx.payload;
-		fwcmd->params.req.rq_id = rq->rq_id;
-		(void)oce_destroy_q(sc, &mbx,
-				sizeof(struct mbx_delete_nic_rq), QTYPE_RQ);
+		if(!rq->islro) {
+			fwcmd = (struct mbx_delete_nic_rq *)&mbx.payload;
+			fwcmd->params.req.rq_id = rq->rq_id;
+			(void)oce_destroy_q(sc, &mbx, sizeof(struct mbx_delete_nic_rq), QTYPE_RQ, 0);
+		}else {
+			fwcmd1 = (struct mbx_delete_nic_rq_v1 *)&mbx.payload;
+			fwcmd1->params.req.rq_id = rq->rq_id;
+			fwcmd1->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO);
+			(void)oce_destroy_q(sc, &mbx, sizeof(struct mbx_delete_nic_rq_v1), QTYPE_RQ, 1);
+		}
 		rq->qstate = QDELETED;
 	}
 
@@ -632,7 +642,7 @@ oce_eq_del(struct oce_eq *eq)
 		fwcmd = (struct mbx_destroy_common_eq *)&mbx.payload;
 		fwcmd->params.req.id = eq->eq_id;
 		(void)oce_destroy_q(sc, &mbx,
-			sizeof(struct mbx_destroy_common_eq), QTYPE_EQ);
+			sizeof(struct mbx_destroy_common_eq), QTYPE_EQ, 0);
 	}
 
 	if (eq->ring != NULL) {
@@ -783,7 +793,7 @@ oce_mq_free(struct oce_mq *mq)
 			fwcmd->params.req.id = mq->mq_id;
 			(void) oce_destroy_q(sc, &mbx,
 				sizeof (struct mbx_destroy_common_mq),
-				QTYPE_MQ);
+				QTYPE_MQ, 0);
 		}
 		mq->qstate = QDELETED;
 	}
@@ -810,7 +820,7 @@ oce_mq_free(struct oce_mq *mq)
  */
 static int
 oce_destroy_q(POCE_SOFTC sc, struct oce_mbx *mbx, size_t req_size,
-		enum qtype qtype)
+		enum qtype qtype, int version)
 {
 	struct mbx_hdr *hdr = (struct mbx_hdr *)&mbx->payload;
 	int opcode;
@@ -844,7 +854,7 @@ oce_destroy_q(POCE_SOFTC sc, struct oce_mbx *mbx, size_t req_size,
 
 	mbx_common_req_hdr_init(hdr, 0, 0, subsys,
 				opcode, MBX_TIMEOUT_SEC, req_size,
-				OCE_MBX_VER_V0);
+				version);
 
 	mbx->u0.s.embedded = 1;
 	mbx->payload_length = (uint32_t) req_size;
@@ -932,7 +942,7 @@ oce_cq_del(POCE_SOFTC sc, struct oce_cq *cq)
 		fwcmd = (struct mbx_destroy_common_cq *)&mbx.payload;
 		fwcmd->params.req.id = cq->cq_id;
 		(void)oce_destroy_q(sc, &mbx,
-			sizeof(struct mbx_destroy_common_cq), QTYPE_CQ);
+			sizeof(struct mbx_destroy_common_cq), QTYPE_CQ, 0);
 		/*NOW destroy the ring */
 		oce_destroy_ring_buffer(sc, cq->ring);
 		cq->ring = NULL;
@@ -951,12 +961,17 @@ oce_cq_del(POCE_SOFTC sc, struct oce_cq *cq)
 int
 oce_start_rq(struct oce_rq *rq)
 {
+	POCE_SOFTC sc = (POCE_SOFTC) rq->parent;
 	int rc;
 
-	rc = oce_alloc_rx_bufs(rq, rq->cfg.q_len);
+	if(sc->enable_hwlro)
+		rc = oce_alloc_rx_bufs(rq, 960);
+	else
+		rc = oce_alloc_rx_bufs(rq, rq->cfg.q_len - 1);
 
 	if (rc == 0)
 		oce_arm_cq(rq->parent, rq->cq->cq_id, 0, TRUE);
+
 	return rc;
 }
 
@@ -1148,7 +1163,7 @@ oce_free_posted_rxbuf(struct oce_rq *rq)
 	
 	while (rq->pending) {
 
-		pd = &rq->pckts[rq->packets_out];
+		pd = &rq->pckts[rq->ring->cidx];
 		bus_dmamap_sync(rq->tag, pd->map, BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(rq->tag, pd->map);
 		if (pd->mbuf != NULL) {
@@ -1156,44 +1171,179 @@ oce_free_posted_rxbuf(struct oce_rq *rq)
 			pd->mbuf = NULL;
 		}
 
-		if ((rq->packets_out + 1) == OCE_RQ_PACKET_ARRAY_SIZE)
-			rq->packets_out = 0;
-		else
-			rq->packets_out++;
-
+		RING_GET(rq->ring,1);
                 rq->pending--;
 	}
 
 }
 
 void
-oce_stop_rx(POCE_SOFTC sc)
+oce_rx_cq_clean_hwlro(struct oce_rq *rq)
 {
-	struct oce_mbx mbx;
-	struct mbx_delete_nic_rq *fwcmd;
-	struct oce_rq *rq;
-	int i = 0;
-
-	for_all_rq_queues(sc, rq, i) {
-		if (rq->qstate == QCREATED) {
-			/* Delete rxq in firmware */
-
-			bzero(&mbx, sizeof(mbx));
-			fwcmd = (struct mbx_delete_nic_rq *)&mbx.payload;
-			fwcmd->params.req.rq_id = rq->rq_id;
-
-			(void)oce_destroy_q(sc, &mbx, 
-				sizeof(struct mbx_delete_nic_rq), QTYPE_RQ);
+        struct oce_cq *cq = rq->cq;
+        POCE_SOFTC sc = rq->parent;
+        struct nic_hwlro_singleton_cqe *cqe;
+        struct nic_hwlro_cqe_part2 *cqe2;
+        int flush_wait = 0;
+        int flush_compl = 0;
+	int num_frags = 0;
+
+        for (;;) {
+                bus_dmamap_sync(cq->ring->dma.tag,cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
+                cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct nic_hwlro_singleton_cqe);
+                if(cqe->valid) {
+                        if(cqe->cqe_type == 0) { /* singleton cqe */
+                                /* we should not get singleton cqe after cqe1 on same rq */
+                                if(rq->cqe_firstpart != NULL) {
+                                        device_printf(sc->dev, "Got singleton cqe after cqe1 \n");
+                                        goto exit_rx_cq_clean_hwlro;
+                                }
+				num_frags = cqe->pkt_size / rq->cfg.frag_size;
+				if(cqe->pkt_size % rq->cfg.frag_size)
+					num_frags++;
+                                oce_discard_rx_comp(rq, num_frags);
+                                /* Check if CQE is flush completion */
+                                if(!cqe->pkt_size) 
+                                        flush_compl = 1;
+                                cqe->valid = 0;
+                                RING_GET(cq->ring, 1);
+                        }else if(cqe->cqe_type == 0x1) { /* first part */
+                                /* we should not get cqe1 after cqe1 on same rq */
+                                if(rq->cqe_firstpart != NULL) {
+                                        device_printf(sc->dev, "Got cqe1 after cqe1 \n");
+                                        goto exit_rx_cq_clean_hwlro;
+                                }
+                                rq->cqe_firstpart = (struct nic_hwlro_cqe_part1 *)cqe;
+                                RING_GET(cq->ring, 1);
+                        }else if(cqe->cqe_type == 0x2) { /* second part */
+                                cqe2 = (struct nic_hwlro_cqe_part2 *)cqe;
+                                /* We should not get cqe2 without cqe1 */
+                                if(rq->cqe_firstpart == NULL) {
+                                        device_printf(sc->dev, "Got cqe2 without cqe1 \n");
+                                        goto exit_rx_cq_clean_hwlro;
+                                }
+				num_frags = cqe2->coalesced_size / rq->cfg.frag_size;
+				if(cqe2->coalesced_size % rq->cfg.frag_size)
+					num_frags++;
+				
+				/* Flush completion will always come in singleton CQE */
+                                oce_discard_rx_comp(rq, num_frags);
+
+                                rq->cqe_firstpart->valid = 0;
+                                cqe2->valid = 0;
+                                rq->cqe_firstpart = NULL;
+                                RING_GET(cq->ring, 1);
+                        }
+                        oce_arm_cq(sc, cq->cq_id, 1, FALSE);
+                        if(flush_compl)
+                                break;
+                }else {
+                        if (flush_wait++ > 100) {
+                                device_printf(sc->dev, "did not receive hwlro flush compl\n");
+                                break;
+                        }
+                        oce_arm_cq(sc, cq->cq_id, 0, TRUE);
+                        DELAY(1000);
+                }
+        }
+
+        /* After cleanup, leave the CQ in unarmed state */
+        oce_arm_cq(sc, cq->cq_id, 0, FALSE);
+
+exit_rx_cq_clean_hwlro:
+	return;
+}
 
-			rq->qstate = QDELETED;
 
-			DELAY(1);
+void
+oce_rx_cq_clean(struct oce_rq *rq)
+{
+	struct oce_nic_rx_cqe *cqe;
+        struct oce_cq  *cq;
+        POCE_SOFTC sc;
+	int flush_wait = 0;
+	int flush_compl = 0;
+        sc = rq->parent;
+        cq = rq->cq;
+	
+	for (;;) {
+		bus_dmamap_sync(cq->ring->dma.tag,
+			cq->ring->dma.map, BUS_DMASYNC_POSTWRITE);
+        	cqe = RING_GET_CONSUMER_ITEM_VA(cq->ring, struct oce_nic_rx_cqe);
+		if(RQ_CQE_VALID(cqe)) {
+			DW_SWAP((uint32_t *) cqe, sizeof(oce_rq_cqe));
+                        oce_discard_rx_comp(rq, cqe->u0.s.num_fragments);
+                        /* Check if CQE is flush completion */
+                        if((cqe->u0.s.num_fragments==0)&&(cqe->u0.s.pkt_size == 0)&&(cqe->u0.s.error == 0)) 
+				flush_compl = 1;
+                        
+                        RQ_CQE_INVALIDATE(cqe);
+                        RING_GET(cq->ring, 1);
+#if defined(INET6) || defined(INET)
+		        if (IF_LRO_ENABLED(sc))
+                		oce_rx_flush_lro(rq);
+#endif
+                        oce_arm_cq(sc, cq->cq_id, 1, FALSE);
+			if(flush_compl)
+				break;
+		}else {
+			if (flush_wait++ > 100) {
+				device_printf(sc->dev, "did not receive flush compl\n");
+				break;
+			}
+			oce_arm_cq(sc, cq->cq_id, 0, TRUE);
+			DELAY(1000);
+                } 
+        }
+
+	/* After cleanup, leave the CQ in unarmed state */
+	oce_arm_cq(sc, cq->cq_id, 0, FALSE);
+}
 
-			/* Free posted RX buffers that are not used */
-			oce_free_posted_rxbuf(rq);
+void
+oce_stop_rx(POCE_SOFTC sc)
+{
+        struct oce_mbx mbx;
+        struct mbx_delete_nic_rq *fwcmd;
+        struct mbx_delete_nic_rq_v1 *fwcmd1;
+        struct oce_rq *rq;
+        int i = 0;
+ 
+       /* before deleting disable hwlro */
+	if(sc->enable_hwlro)
+        	oce_mbox_nic_set_iface_lro_config(sc, 0);
+
+        for_all_rq_queues(sc, rq, i) {
+                if (rq->qstate == QCREATED) {
+                        /* Delete rxq in firmware */
+			LOCK(&rq->rx_lock);
+
+                        bzero(&mbx, sizeof(mbx));
+                	if(!rq->islro) {
+                        	fwcmd = (struct mbx_delete_nic_rq *)&mbx.payload;
+                        	fwcmd->params.req.rq_id = rq->rq_id;
+                        	(void)oce_destroy_q(sc, &mbx, sizeof(struct mbx_delete_nic_rq), QTYPE_RQ, 0);
+                	}else {
+                        	fwcmd1 = (struct mbx_delete_nic_rq_v1 *)&mbx.payload;
+                        	fwcmd1->params.req.rq_id = rq->rq_id;
+                               	fwcmd1->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO);
+
+                        	(void)oce_destroy_q(sc,&mbx,sizeof(struct mbx_delete_nic_rq_v1),QTYPE_RQ,1);
+                	}
+                        rq->qstate = QDELETED;
+
+                        DELAY(1000);
 			
-		}
-	}
+			if(!rq->islro)
+				oce_rx_cq_clean(rq);
+			else
+				oce_rx_cq_clean_hwlro(rq);
+
+                        /* Free posted RX buffers that are not used */
+                        oce_free_posted_rxbuf(rq);
+			UNLOCK(&rq->rx_lock);
+                }
+        }
 }
 
 
@@ -1207,16 +1357,28 @@ oce_start_rx(POCE_SOFTC sc)
 	for_all_rq_queues(sc, rq, i) {
 		if (rq->qstate == QCREATED)
 			continue;
-		rc = oce_mbox_create_rq(rq);
+		if((i == 0) || (!sc->enable_hwlro)) {
+        	        rc = oce_mbox_create_rq(rq);
+                        if (rc)
+                                goto error;
+			rq->islro = 0;
+		}else {
+			rc = oce_mbox_create_rq_v2(rq);
+                        if (rc)
+                                goto error;
+                        rq->islro = 1;
+		}
+                /* reset queue pointers */
+                rq->qstate       = QCREATED;
+                rq->pending      = 0;
+                rq->ring->cidx   = 0;
+                rq->ring->pidx   = 0;
+	}
+	
+	if(sc->enable_hwlro) {
+		rc = oce_mbox_nic_set_iface_lro_config(sc, 1);
 		if (rc)
 			goto error;
-		/* reset queue pointers */
-		rq->qstate 	 = QCREATED;
-		rq->pending	 = 0;
-		rq->ring->cidx	 = 0;
-		rq->ring->pidx	 = 0;
-		rq->packets_in	 = 0;
-		rq->packets_out	 = 0;
 	}
 
 	DELAY(1);
@@ -1229,6 +1391,7 @@ oce_start_rx(POCE_SOFTC sc)
 
 	}
 
+	DELAY(1);
 	return rc;
 error:
 	device_printf(sc->dev, "Start RX failed\n");
diff --git a/sys/dev/oce/oce_sysctl.c b/sys/dev/oce/oce_sysctl.c
index 61adf93ac69d..1fe4a636af74 100644
--- a/sys/dev/oce/oce_sysctl.c
+++ b/sys/dev/oce/oce_sysctl.c
@@ -43,6 +43,7 @@
 static void copy_stats_to_sc_xe201(POCE_SOFTC sc);
 static void copy_stats_to_sc_be3(POCE_SOFTC sc);
 static void copy_stats_to_sc_be2(POCE_SOFTC sc);
+static void copy_stats_to_sc_sh(POCE_SOFTC sc);
 static int  oce_sysctl_loopback(SYSCTL_HANDLER_ARGS);
 static int  oce_sys_aic_enable(SYSCTL_HANDLER_ARGS);
 static int  oce_be3_fwupgrade(POCE_SOFTC sc, const struct firmware *fw);
@@ -182,6 +183,8 @@ oce_sys_aic_enable(SYSCTL_HANDLER_ARGS)
 	POCE_SOFTC sc = (struct oce_softc *)arg1;
 	struct oce_aic_obj *aic;
 
+	/* set current value for proper sysctl logging */
+	value = sc->aic_obj[0].enable;
 	status = sysctl_handle_int(oidp, &value, 0, req);
 	if (status || !req->newptr)
 		return status; 
@@ -482,34 +485,34 @@ ret:
 	return rc;
 }
 
-#define UFI_TYPE2		2
-#define UFI_TYPE3		3
-#define UFI_TYPE3R		10
-#define UFI_TYPE4		4
-#define UFI_TYPE4R		11
+#define UFI_TYPE2               2
+#define UFI_TYPE3               3
+#define UFI_TYPE3R              10
+#define UFI_TYPE4               4
+#define UFI_TYPE4R              11
 static int oce_get_ufi_type(POCE_SOFTC sc,
-			    const struct flash_file_hdr *fhdr)
+                           const struct flash_file_hdr *fhdr)
 {
-	if (fhdr == NULL)
-		goto be_get_ufi_exit;
-
-	if (IS_SH(sc) && fhdr->build[0] == '4') {
-		if (fhdr->asic_type_rev >= 0x10)
-			return UFI_TYPE4R;
-		else
-			return UFI_TYPE4;
-	} else if (IS_BE3(sc) && fhdr->build[0] == '3') {
-		if (fhdr->asic_type_rev == 0x10)
-			return UFI_TYPE3R;
-		else
-			return UFI_TYPE3;
-	} else if (IS_BE2(sc) && fhdr->build[0] == '2')
-		return UFI_TYPE2;
+        if (fhdr == NULL)
+                goto be_get_ufi_exit;
+
+        if (IS_SH(sc) && fhdr->build[0] == '4') {
+                if (fhdr->asic_type_rev >= 0x10)
+                        return UFI_TYPE4R;
+                else
+                        return UFI_TYPE4;
+        } else if (IS_BE3(sc) && fhdr->build[0] == '3') {
+                if (fhdr->asic_type_rev == 0x10)
+                        return UFI_TYPE3R;
+                else
+                        return UFI_TYPE3;
+        } else if (IS_BE2(sc) && fhdr->build[0] == '2')
+                return UFI_TYPE2;
 
 be_get_ufi_exit:
-	device_printf(sc->dev,
-		"UFI and Interface are not compatible for flashing\n");
-	return -1;
+        device_printf(sc->dev,
+                "UFI and Interface are not compatible for flashing\n");
+        return -1;
 }
 
 
@@ -777,7 +780,11 @@ oce_add_stats_sysctls_be3(POCE_SOFTC sc,
 		SYSCTL_ADD_UINT(ctx, queue_stats_list, OID_AUTO, "rxcp_err",
 			CTLFLAG_RD, &sc->rq[i]->rx_stats.rxcp_err, 0,
 			"Received Completion Errors");
-		
+		if(IS_SH(sc)) {
+			SYSCTL_ADD_UINT(ctx, queue_stats_list, OID_AUTO, "rx_drops_no_frags",
+                        	CTLFLAG_RD, &sc->rq[i]->rx_stats.rx_drops_no_frags, 0,
+                        	"num of packet drops due to no fragments");
+		}
 	}
 	
 	rx_stats_node = SYSCTL_ADD_NODE(ctx,
@@ -1372,10 +1379,10 @@ copy_stats_to_sc_be3(POCE_SOFTC sc)
 	struct oce_pmem_stats *pmem;
 	struct oce_rxf_stats_v1 *rxf_stats;
 	struct oce_port_rxf_stats_v1 *port_stats;
-	struct mbx_get_nic_stats *nic_mbx;
+	struct mbx_get_nic_stats_v1 *nic_mbx;
 	uint32_t port = sc->port_id;
 
-	nic_mbx = OCE_DMAPTR(&sc->stats_mem, struct mbx_get_nic_stats);
+	nic_mbx = OCE_DMAPTR(&sc->stats_mem, struct mbx_get_nic_stats_v1);
 	pmem = &nic_mbx->params.rsp.stats.pmem;
 	rxf_stats = &nic_mbx->params.rsp.stats.rxf;
 	port_stats = &nic_mbx->params.rsp.stats.rxf.port[port];
@@ -1429,18 +1436,91 @@ copy_stats_to_sc_be3(POCE_SOFTC sc)
 	adapter_stats->eth_red_drops = pmem->eth_red_drops;
 }
 
+static void
+copy_stats_to_sc_sh(POCE_SOFTC sc)
+{
+        struct oce_be_stats *adapter_stats;
+        struct oce_pmem_stats *pmem;
+        struct oce_rxf_stats_v2 *rxf_stats;
+        struct oce_port_rxf_stats_v2 *port_stats;
+        struct mbx_get_nic_stats_v2 *nic_mbx;
+	struct oce_erx_stats_v2 *erx_stats;
+        uint32_t port = sc->port_id;
+
+        nic_mbx = OCE_DMAPTR(&sc->stats_mem, struct mbx_get_nic_stats_v2);
+        pmem = &nic_mbx->params.rsp.stats.pmem;
+        rxf_stats = &nic_mbx->params.rsp.stats.rxf;
+	erx_stats = &nic_mbx->params.rsp.stats.erx;
+        port_stats = &nic_mbx->params.rsp.stats.rxf.port[port];
+
+        adapter_stats = &sc->oce_stats_info.u0.be;
+
+        /* Update stats */
+        adapter_stats->pmem_fifo_overflow_drop =
+                port_stats->pmem_fifo_overflow_drop;
+        adapter_stats->rx_priority_pause_frames =
+                port_stats->rx_priority_pause_frames;
+        adapter_stats->rx_pause_frames = port_stats->rx_pause_frames;
+        adapter_stats->rx_crc_errors = port_stats->rx_crc_errors;
+        adapter_stats->rx_control_frames = port_stats->rx_control_frames;
+        adapter_stats->rx_in_range_errors = port_stats->rx_in_range_errors;
+        adapter_stats->rx_frame_too_long = port_stats->rx_frame_too_long;
+        adapter_stats->rx_dropped_runt = port_stats->rx_dropped_runt;
+        adapter_stats->rx_ip_checksum_errs = port_stats->rx_ip_checksum_errs;
+        adapter_stats->rx_tcp_checksum_errs = port_stats->rx_tcp_checksum_errs;
+        adapter_stats->rx_udp_checksum_errs = port_stats->rx_udp_checksum_errs;
+        adapter_stats->rx_dropped_tcp_length =
+                port_stats->rx_dropped_tcp_length;
+        adapter_stats->rx_dropped_too_small = port_stats->rx_dropped_too_small;
+        adapter_stats->rx_dropped_too_short = port_stats->rx_dropped_too_short;
+        adapter_stats->rx_out_range_errors = port_stats->rx_out_range_errors;
+        adapter_stats->rx_dropped_header_too_small =
+                port_stats->rx_dropped_header_too_small;
+        adapter_stats->rx_input_fifo_overflow_drop =
+                port_stats->rx_input_fifo_overflow_drop;
+        adapter_stats->rx_address_match_errors =
+                port_stats->rx_address_match_errors;
+        adapter_stats->rx_alignment_symbol_errors =
+                port_stats->rx_alignment_symbol_errors;
+        adapter_stats->rxpp_fifo_overflow_drop =
+                port_stats->rxpp_fifo_overflow_drop;
+        adapter_stats->tx_pauseframes = port_stats->tx_pauseframes;
+        adapter_stats->tx_controlframes = port_stats->tx_controlframes;
+        adapter_stats->jabber_events = port_stats->jabber_events;
+
+        adapter_stats->rx_drops_no_pbuf = rxf_stats->rx_drops_no_pbuf;
+        adapter_stats->rx_drops_no_txpb = rxf_stats->rx_drops_no_txpb;
+        adapter_stats->rx_drops_no_erx_descr = rxf_stats->rx_drops_no_erx_descr;
+        adapter_stats->rx_drops_invalid_ring = rxf_stats->rx_drops_invalid_ring;
+        adapter_stats->forwarded_packets = rxf_stats->forwarded_packets;
+        adapter_stats->rx_drops_mtu = rxf_stats->rx_drops_mtu;
+        adapter_stats->rx_drops_no_tpre_descr =
+                rxf_stats->rx_drops_no_tpre_descr;
+        adapter_stats->rx_drops_too_many_frags =
+                rxf_stats->rx_drops_too_many_frags;
+
+        adapter_stats->eth_red_drops = pmem->eth_red_drops;
+
+	/* populate erx stats */
+	for (int i = 0; i < sc->nrqs; i++) 
+		sc->rq[i]->rx_stats.rx_drops_no_frags = erx_stats->rx_drops_no_fragments[sc->rq[i]->rq_id];
+}
+
+
 
 int
 oce_stats_init(POCE_SOFTC sc)
 {
-	int rc = 0, sz;
-	
-	if (IS_BE(sc) || IS_SH(sc)) {
-		if (sc->flags & OCE_FLAGS_BE2)
-			sz = sizeof(struct mbx_get_nic_stats_v0);
-		else 
-			sz = sizeof(struct mbx_get_nic_stats);
-	} else 
+	int rc = 0, sz = 0;
+
+
+        if( IS_BE2(sc) ) 
+		sz = sizeof(struct mbx_get_nic_stats_v0);
+        else if( IS_BE3(sc) ) 
+		sz = sizeof(struct mbx_get_nic_stats_v1);
+        else if( IS_SH(sc)) 
+		sz = sizeof(struct mbx_get_nic_stats_v2);
+        else if( IS_XE201(sc) )
 		sz = sizeof(struct mbx_get_pport_stats);
 
 	rc = oce_dma_alloc(sc, sz, &sc->stats_mem, 0);
@@ -1463,23 +1543,24 @@ oce_refresh_nic_stats(POCE_SOFTC sc)
 {
 	int rc = 0, reset = 0;
 
-	if (IS_BE(sc) || IS_SH(sc)) {
-		if (sc->flags & OCE_FLAGS_BE2) {
-			rc = oce_mbox_get_nic_stats_v0(sc, &sc->stats_mem);
-			if (!rc)
-				copy_stats_to_sc_be2(sc);
-		} else {
-			rc = oce_mbox_get_nic_stats(sc, &sc->stats_mem);
-			if (!rc)
-				copy_stats_to_sc_be3(sc);
-		}
-
-	} else {
+	if( IS_BE2(sc) ) {
+		rc = oce_mbox_get_nic_stats_v0(sc, &sc->stats_mem);
+		if (!rc)
+			copy_stats_to_sc_be2(sc);
+	}else if( IS_BE3(sc) ) {
+		rc = oce_mbox_get_nic_stats_v1(sc, &sc->stats_mem);
+		if (!rc)
+			copy_stats_to_sc_be3(sc);
+	}else if( IS_SH(sc)) {
+		rc = oce_mbox_get_nic_stats_v2(sc, &sc->stats_mem);
+		if (!rc)
+			copy_stats_to_sc_sh(sc);
+	}else if( IS_XE201(sc) ){
 		rc = oce_mbox_get_pport_stats(sc, &sc->stats_mem, reset);
 		if (!rc)
 			copy_stats_to_sc_xe201(sc);
 	}
-	
+
 	return rc;
 }
 
diff --git a/sys/dev/oce/oce_user.h b/sys/dev/oce/oce_user.h
new file mode 100644
index 000000000000..ae1f96d5d317
--- /dev/null
+++ b/sys/dev/oce/oce_user.h
@@ -0,0 +1,121 @@
+/*-
+ * Copyright (C) 2013 Emulex
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the Emulex Corporation nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contact Information:
+ * freebsd-drivers@emulex.com
+ *
+ * Emulex
+ * 3333 Susan Street
+ * Costa Mesa, CA 92626
+ */
+
+/* $FreeBSD$ */
+
+struct oce_mbx;
+struct oce_softc;
+struct mbx_hdr;
+
+enum oce_interrupt_mode {
+	OCE_INTERRUPT_MODE_MSIX = 0,
+	OCE_INTERRUPT_MODE_INTX = 1,
+	OCE_INTERRUPT_MODE_MSI = 2,
+};
+
+#define MAX_ROCE_MSIX_VECTORS   16
+#define MIN_ROCE_MSIX_VECTORS   1
+#define ROCE_MSIX_VECTORS       2
+
+struct oce_dev_info {
+	device_t dev;
+	struct ifnet *ifp;
+	struct oce_softc *softc;
+
+	bus_space_handle_t db_bhandle;
+	bus_space_tag_t db_btag;
+	uint64_t unmapped_db;
+	uint32_t unmapped_db_len;
+	uint32_t db_page_size;
+	uint64_t dpp_unmapped_addr;
+	uint32_t dpp_unmapped_len;
+	uint8_t mac_addr[6];
+	uint32_t dev_family;
+	uint16_t vendor_id;
+	uint16_t dev_id;
+	enum oce_interrupt_mode intr_mode;
+	struct {
+		int num_vectors;
+		int start_vector;
+		uint32_t vector_list[MAX_ROCE_MSIX_VECTORS];
+	} msix;
+	uint32_t flags;
+#define OCE_RDMA_INFO_RDMA_SUPPORTED     0x00000001
+};
+
+
+#define OCE_GEN2_FAMILY     2
+
+#ifdef notdef
+struct oce_mbx_ctx {
+	struct oce_mbx *mbx;
+	void (*cb) (void *ctx);
+	void *cb_ctx;
+};
+#endif
+
+struct oce_mbx_ctx;
+
+typedef struct oce_rdma_info {
+	int size;
+	void (*close)(void);
+	int (*mbox_post)(struct oce_softc *sc, 
+			 struct oce_mbx *mbx, 
+			 struct oce_mbx_ctx *mbxctx);
+	void (*common_req_hdr_init)(struct mbx_hdr *hdr,
+				    uint8_t dom,
+				    uint8_t port,
+				    uint8_t subsys,
+				    uint8_t opcode,
+				    uint32_t timeout,
+				    uint32_t pyld_len,
+				    uint8_t version);
+	void (*get_mac_addr)(struct oce_softc *sc,
+			     uint8_t *macaddr);
+} OCE_RDMA_INFO, *POCE_RDMA_INFO;
+
+#define OCE_RDMA_INFO_SIZE (sizeof(OCE_RDMA_INFO))
+
+typedef struct oce_rdma_if {
+	int size;
+	int (*announce)(struct oce_dev_info *devinfo);
+} OCE_RDMA_IF, *POCE_RDMA_IF;
+
+#define OCE_RDMA_IF_SIZE (sizeof(OCE_RDMA_IF))
+
+int oce_register_rdma(POCE_RDMA_INFO rdma_info, POCE_RDMA_IF rdma_if);
diff --git a/sys/dev/ofw/ofw_fdt.c b/sys/dev/ofw/ofw_fdt.c
index 0f7cf07919b3..605166832d9a 100644
--- a/sys/dev/ofw/ofw_fdt.c
+++ b/sys/dev/ofw/ofw_fdt.c
@@ -52,6 +52,15 @@ __FBSDID("$FreeBSD$");
 #define debugf(fmt, args...)
 #endif
 
+#if defined(__arm__)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) || \
+    defined(SOC_MV_DISCOVERY) || defined(SOC_MV_DOVE) || \
+    defined(SOC_MV_FREY) || defined(SOC_MV_KIRKWOOD) || \
+    defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_ORION)
+#define FDT_MARVELL
+#endif
+#endif
+
 static int ofw_fdt_init(ofw_t, void *);
 static phandle_t ofw_fdt_peer(ofw_t, phandle_t);
 static phandle_t ofw_fdt_child(ofw_t, phandle_t);
@@ -415,7 +424,7 @@ ofw_fdt_package_to_path(ofw_t ofw, phandle_t package, char *buf, size_t len)
 	return (-1);
 }
 
-#if defined(__arm__) || defined(__powerpc__)
+#if defined(FDT_MARVELL) || defined(__powerpc__)
 static int
 ofw_fdt_fixup(ofw_t ofw)
 {
@@ -454,7 +463,7 @@ ofw_fdt_fixup(ofw_t ofw)
 static int
 ofw_fdt_interpret(ofw_t ofw, const char *cmd, int nret, cell_t *retvals)
 {
-#if defined(__arm__) || defined(__powerpc__)
+#if defined(FDT_MARVELL) || defined(__powerpc__)
 	int rv;
 
 	/*
diff --git a/sys/dev/ofw/ofw_subr.c b/sys/dev/ofw/ofw_subr.c
index 4d14db798f38..25da73154ff4 100644
--- a/sys/dev/ofw/ofw_subr.c
+++ b/sys/dev/ofw/ofw_subr.c
@@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/libkern.h>
+#include <sys/reboot.h>
 #include <sys/rman.h>
 
 #include <machine/bus.h>
@@ -180,3 +181,64 @@ ofw_reg_to_paddr(phandle_t dev, int regno, bus_addr_t *paddr,
 
 	return (0);
 }
+
+/* Parse cmd line args as env - copied from xlp_machdep. */
+/* XXX-BZ this should really be centrally provided for all (boot) code. */
+static void
+_parse_bootargs(char *cmdline)
+{
+	char *n, *v;
+
+	while ((v = strsep(&cmdline, " \n")) != NULL) {
+		if (*v == '\0')
+			continue;
+		if (*v == '-') {
+			while (*v != '\0') {
+				v++;
+				switch (*v) {
+				case 'a': boothowto |= RB_ASKNAME; break;
+				/* Someone should simulate that ;-) */
+				case 'C': boothowto |= RB_CDROM; break;
+				case 'd': boothowto |= RB_KDB; break;
+				case 'D': boothowto |= RB_MULTIPLE; break;
+				case 'm': boothowto |= RB_MUTE; break;
+				case 'g': boothowto |= RB_GDB; break;
+				case 'h': boothowto |= RB_SERIAL; break;
+				case 'p': boothowto |= RB_PAUSE; break;
+				case 'r': boothowto |= RB_DFLTROOT; break;
+				case 's': boothowto |= RB_SINGLE; break;
+				case 'v': boothowto |= RB_VERBOSE; break;
+				}
+			}
+		} else {
+			n = strsep(&v, "=");
+			if (v == NULL)
+				kern_setenv(n, "1");
+			else
+				kern_setenv(n, v);
+		}
+	}
+}
+
+/*
+ * This is intended to be called early on, right after the OF system is
+ * initialized, so pmap may not be up yet.
+ */
+int
+ofw_parse_bootargs(void)
+{
+	phandle_t chosen;
+	char buf[2048];		/* early stack supposedly big enough */
+	int err;
+
+	chosen = OF_finddevice("/chosen");
+	if (chosen <= 0)
+		return (chosen);
+
+	if ((err = OF_getprop(chosen, "bootargs", buf, sizeof(buf))) != -1) {
+		_parse_bootargs(buf);
+		return (0);
+	}
+
+	return (err);
+}
diff --git a/sys/dev/ofw/ofw_subr.h b/sys/dev/ofw/ofw_subr.h
index 8fa64b2b9726..ed29142d1dab 100644
--- a/sys/dev/ofw/ofw_subr.h
+++ b/sys/dev/ofw/ofw_subr.h
@@ -46,4 +46,6 @@
 int ofw_reg_to_paddr(phandle_t _dev, int _regno, bus_addr_t *_paddr,
     bus_size_t *_size, pcell_t *_pci_hi);
 
+int ofw_parse_bootargs(void);
+
 #endif
diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c
index c92fb4a09021..665f62e0911e 100644
--- a/sys/dev/pci/pci.c
+++ b/sys/dev/pci/pci.c
@@ -3971,7 +3971,7 @@ pci_rescan_method(device_t dev)
 		if (hdrtype & PCIM_MFDEV)
 			pcifunchigh = PCIB_MAXFUNCS(pcib);
 		for (f = 0; f <= pcifunchigh; f++) {
-			if (REG(PCIR_VENDOR, 2) == 0xfff)
+			if (REG(PCIR_VENDOR, 2) == 0xffff)
 				continue;
 
 			/*
diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c
index a5bc3be03999..071b55b10146 100644
--- a/sys/dev/re/if_re.c
+++ b/sys/dev/re/if_re.c
@@ -183,6 +183,8 @@ static const struct rl_type re_devs[] = {
 	    "RealTek 810xE PCIe 10/100baseTX" },
 	{ RT_VENDORID, RT_DEVICEID_8168, 0,
 	    "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" },
+	{ NCUBE_VENDORID, RT_DEVICEID_8168, 0,
+	    "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" },
 	{ RT_VENDORID, RT_DEVICEID_8169, 0,
 	    "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
 	{ RT_VENDORID, RT_DEVICEID_8169SC, 0,
diff --git a/sys/dev/rl/if_rlreg.h b/sys/dev/rl/if_rlreg.h
index 2cef251b8d1f..2fa44efa2f60 100644
--- a/sys/dev/rl/if_rlreg.h
+++ b/sys/dev/rl/if_rlreg.h
@@ -1158,3 +1158,8 @@ struct rl_softc {
 /* US Robotics 997902 device ID */
 
 #define	USR_DEVICEID_997902	0x0116
+
+/* 
+ * NCube vendor ID
+ */
+#define	NCUBE_VENDORID		0x10FF
diff --git a/sys/dev/usb/input/ukbd.c b/sys/dev/usb/input/ukbd.c
index 7631324c8ede..abe908735f73 100644
--- a/sys/dev/usb/input/ukbd.c
+++ b/sys/dev/usb/input/ukbd.c
@@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
 #include "opt_compat.h"
 #include "opt_kbd.h"
 #include "opt_ukbd.h"
+#include "opt_evdev.h"
 
 #include <sys/stdint.h>
 #include <sys/stddef.h>
@@ -71,6 +72,11 @@ __FBSDID("$FreeBSD$");
 
 #include <dev/usb/quirk/usb_quirk.h>
 
+#ifdef EVDEV
+#include <dev/evdev/input.h>
+#include <dev/evdev/evdev.h>
+#endif
+
 #include <sys/ioccom.h>
 #include <sys/filio.h>
 #include <sys/tty.h>
@@ -160,6 +166,9 @@ struct ukbd_softc {
 	struct usb_device *sc_udev;
 	struct usb_interface *sc_iface;
 	struct usb_xfer *sc_xfer[UKBD_N_TRANSFER];
+#ifdef EVDEV
+	struct evdev_dev *sc_evdev;
+#endif
 
 	sbintime_t sc_co_basetime;
 	int	sc_delay;
@@ -354,6 +363,12 @@ static device_attach_t ukbd_attach;
 static device_detach_t ukbd_detach;
 static device_resume_t ukbd_resume;
 
+#ifdef EVDEV
+static struct evdev_methods ukbd_evdev_methods = {
+	.ev_event = evdev_ev_kbd_event,
+};
+#endif
+
 static uint8_t
 ukbd_any_key_pressed(struct ukbd_softc *sc)
 {
@@ -388,6 +403,14 @@ ukbd_put_key(struct ukbd_softc *sc, uint32_t key)
 	DPRINTF("0x%02x (%d) %s\n", key, key,
 	    (key & KEY_RELEASE) ? "released" : "pressed");
 
+#ifdef EVDEV
+	if (evdev_rcpt_mask & EVDEV_RCPT_HW_KBD && sc->sc_evdev != NULL) {
+		evdev_push_event(sc->sc_evdev, EV_KEY,
+		    evdev_hid2key(KEY_INDEX(key)), !(key & KEY_RELEASE));
+		evdev_sync(sc->sc_evdev);
+	}
+#endif
+
 	if (sc->sc_inputs < UKBD_IN_BUF_SIZE) {
 		sc->sc_input[sc->sc_inputtail] = key;
 		++(sc->sc_inputs);
@@ -908,6 +931,11 @@ ukbd_set_leds_callback(struct usb_xfer *xfer, usb_error_t error)
 		if (!any)
 			break;
 
+#ifdef EVDEV
+		if (sc->sc_evdev != NULL)
+			evdev_push_leds(sc->sc_evdev, sc->sc_leds);
+#endif
+
 		/* range check output report length */
 		len = sc->sc_led_size;
 		if (len > (UKBD_BUFFER_SIZE - 1))
@@ -1183,6 +1211,10 @@ ukbd_attach(device_t dev)
 	usb_error_t err;
 	uint16_t n;
 	uint16_t hid_len;
+#ifdef EVDEV
+	struct evdev_dev *evdev;
+	int i;
+#endif
 #ifdef USB_DEBUG
 	int rate;
 #endif
@@ -1297,6 +1329,37 @@ ukbd_attach(device_t dev)
 		goto detach;
 	}
 #endif
+
+#ifdef EVDEV
+	evdev = evdev_alloc();
+	evdev_set_name(evdev, device_get_desc(dev));
+	evdev_set_phys(evdev, device_get_nameunit(dev));
+	evdev_set_id(evdev, BUS_USB, uaa->info.idVendor,
+	   uaa->info.idProduct, 0);
+	evdev_set_serial(evdev, usb_get_serial(uaa->device));
+	evdev_set_methods(evdev, kbd, &ukbd_evdev_methods);
+	evdev_support_event(evdev, EV_SYN);
+	evdev_support_event(evdev, EV_KEY);
+	if (sc->sc_flags & (UKBD_FLAG_NUMLOCK | UKBD_FLAG_CAPSLOCK |
+			    UKBD_FLAG_SCROLLLOCK))
+		evdev_support_event(evdev, EV_LED);
+	evdev_support_event(evdev, EV_REP);
+
+	for (i = 0x00; i <= 0xFF; i++)
+		evdev_support_key(evdev, evdev_hid2key(i));
+	if (sc->sc_flags & UKBD_FLAG_NUMLOCK)
+		evdev_support_led(evdev, LED_NUML);
+	if (sc->sc_flags & UKBD_FLAG_CAPSLOCK)
+		evdev_support_led(evdev, LED_CAPSL);
+	if (sc->sc_flags & UKBD_FLAG_SCROLLLOCK)
+		evdev_support_led(evdev, LED_SCROLLL);
+
+	if (evdev_register(evdev))
+		evdev_free(evdev);
+	else
+		sc->sc_evdev = evdev;
+#endif
+
 	sc->sc_flags |= UKBD_FLAG_ATTACHED;
 
 	if (bootverbose) {
@@ -1367,6 +1430,11 @@ ukbd_detach(device_t dev)
 		}
 	}
 #endif
+
+#ifdef EVDEV
+	evdev_free(sc->sc_evdev);
+#endif
+
 	if (KBD_IS_CONFIGURED(&sc->sc_kbd)) {
 		error = kbd_unregister(&sc->sc_kbd);
 		if (error) {
@@ -1884,6 +1952,10 @@ ukbd_ioctl_locked(keyboard_t *kbd, u_long cmd, caddr_t arg)
 		 */
 		kbd->kb_delay1 = imax(((int *)arg)[0], 250);
 		kbd->kb_delay2 = imax(((int *)arg)[1], 34);
+#ifdef EVDEV
+		if (sc->sc_evdev != NULL)
+			evdev_push_repeats(sc->sc_evdev, kbd);
+#endif
 		return (0);
 
 #if defined(COMPAT_FREEBSD6) || defined(COMPAT_FREEBSD5) || \
@@ -2032,6 +2104,9 @@ ukbd_set_leds(struct ukbd_softc *sc, uint8_t leds)
 static int
 ukbd_set_typematic(keyboard_t *kbd, int code)
 {
+#ifdef EVDEV
+	struct ukbd_softc *sc = kbd->kb_data;
+#endif
 	static const int delays[] = {250, 500, 750, 1000};
 	static const int rates[] = {34, 38, 42, 46, 50, 55, 59, 63,
 		68, 76, 84, 92, 100, 110, 118, 126,
@@ -2043,6 +2118,10 @@ ukbd_set_typematic(keyboard_t *kbd, int code)
 	}
 	kbd->kb_delay1 = delays[(code >> 5) & 3];
 	kbd->kb_delay2 = rates[code & 0x1f];
+#ifdef EVDEV
+	if (sc->sc_evdev != NULL)
+		evdev_push_repeats(sc->sc_evdev, kbd);
+#endif
 	return (0);
 }
 
diff --git a/sys/dev/usb/input/ums.c b/sys/dev/usb/input/ums.c
index a26db87cc8bf..a49870c431c4 100644
--- a/sys/dev/usb/input/ums.c
+++ b/sys/dev/usb/input/ums.c
@@ -35,6 +35,8 @@ __FBSDID("$FreeBSD$");
  * HID spec: http://www.usb.org/developers/devclass_docs/HID1_11.pdf
  */
 
+#include "opt_evdev.h"
+
 #include <sys/stdint.h>
 #include <sys/stddef.h>
 #include <sys/param.h>
@@ -68,6 +70,11 @@ __FBSDID("$FreeBSD$");
 
 #include <dev/usb/quirk/usb_quirk.h>
 
+#ifdef EVDEV
+#include <dev/evdev/input.h>
+#include <dev/evdev/evdev.h>
+#endif
+
 #include <sys/ioccom.h>
 #include <sys/filio.h>
 #include <sys/tty.h>
@@ -135,10 +142,18 @@ struct ums_softc {
 
 	int sc_pollrate;
 	int sc_fflags;
+#ifdef EVDEV
+	int sc_evflags;
+#define	UMS_EVDEV_OPENED	1
+#endif
 
 	uint8_t	sc_buttons;
 	uint8_t	sc_iid;
 	uint8_t	sc_temp[64];
+
+#ifdef EVDEV
+	struct evdev_dev *sc_evdev;
+#endif
 };
 
 static void ums_put_queue_timeout(void *__sc);
@@ -149,25 +164,39 @@ static device_probe_t ums_probe;
 static device_attach_t ums_attach;
 static device_detach_t ums_detach;
 
-static usb_fifo_cmd_t ums_start_read;
-static usb_fifo_cmd_t ums_stop_read;
-static usb_fifo_open_t ums_open;
-static usb_fifo_close_t ums_close;
-static usb_fifo_ioctl_t ums_ioctl;
+static usb_fifo_cmd_t ums_fifo_start_read;
+static usb_fifo_cmd_t ums_fifo_stop_read;
+static usb_fifo_open_t ums_fifo_open;
+static usb_fifo_close_t ums_fifo_close;
+static usb_fifo_ioctl_t ums_fifo_ioctl;
+
+#ifdef EVDEV
+static evdev_open_t ums_ev_open;
+static evdev_close_t ums_ev_close;
+#endif
 
+static void	ums_start_rx(struct ums_softc *);
+static void	ums_stop_rx(struct ums_softc *);
 static void	ums_put_queue(struct ums_softc *, int32_t, int32_t,
 		    int32_t, int32_t, int32_t);
 static int	ums_sysctl_handler_parseinfo(SYSCTL_HANDLER_ARGS);
 
 static struct usb_fifo_methods ums_fifo_methods = {
-	.f_open = &ums_open,
-	.f_close = &ums_close,
-	.f_ioctl = &ums_ioctl,
-	.f_start_read = &ums_start_read,
-	.f_stop_read = &ums_stop_read,
+	.f_open = &ums_fifo_open,
+	.f_close = &ums_fifo_close,
+	.f_ioctl = &ums_fifo_ioctl,
+	.f_start_read = &ums_fifo_start_read,
+	.f_stop_read = &ums_fifo_stop_read,
 	.basename[0] = "ums",
 };
 
+#ifdef EVDEV
+static struct evdev_methods ums_evdev_methods = {
+	.ev_open = &ums_ev_open,
+	.ev_close = &ums_ev_close,
+};
+#endif
+
 static void
 ums_put_queue_timeout(void *__sc)
 {
@@ -327,11 +356,17 @@ ums_intr_callback(struct usb_xfer *xfer, usb_error_t error)
 	case USB_ST_SETUP:
 tr_setup:
 		/* check if we can put more data into the FIFO */
-		if (usb_fifo_put_bytes_max(
-		    sc->sc_fifo.fp[USB_FIFO_RX]) != 0) {
-			usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
-			usbd_transfer_submit(xfer);
+		if (usb_fifo_put_bytes_max(sc->sc_fifo.fp[USB_FIFO_RX]) == 0) {
+#ifdef EVDEV
+			if (sc->sc_evflags == 0)
+				break;
+#else
+			break;
+#endif
 		}
+
+		usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
+		usbd_transfer_submit(xfer);
 		break;
 
 	default:			/* Error */
@@ -655,6 +690,41 @@ ums_attach(device_t dev)
 	if (err)
 		goto detach;
 
+#ifdef EVDEV
+	sc->sc_evdev = evdev_alloc();
+	evdev_set_name(sc->sc_evdev, device_get_desc(dev));
+	evdev_set_phys(sc->sc_evdev, device_get_nameunit(dev));
+	evdev_set_id(sc->sc_evdev, BUS_USB, uaa->info.idVendor,
+	    uaa->info.idProduct, 0);
+	evdev_set_serial(sc->sc_evdev, usb_get_serial(uaa->device));
+	evdev_set_methods(sc->sc_evdev, sc, &ums_evdev_methods);
+	evdev_support_prop(sc->sc_evdev, INPUT_PROP_POINTER);
+	evdev_support_event(sc->sc_evdev, EV_SYN);
+	evdev_support_event(sc->sc_evdev, EV_REL);
+	evdev_support_event(sc->sc_evdev, EV_KEY);
+
+	info = &sc->sc_info[0];
+
+	if (info->sc_flags & UMS_FLAG_X_AXIS)
+		evdev_support_rel(sc->sc_evdev, REL_X);
+
+	if (info->sc_flags & UMS_FLAG_Y_AXIS)
+		evdev_support_rel(sc->sc_evdev, REL_Y);
+
+	if (info->sc_flags & UMS_FLAG_Z_AXIS)
+		evdev_support_rel(sc->sc_evdev, REL_WHEEL);
+
+	if (info->sc_flags & UMS_FLAG_T_AXIS)
+		evdev_support_rel(sc->sc_evdev, REL_HWHEEL);
+
+	for (i = 0; i < info->sc_buttons; i++)
+		evdev_support_key(sc->sc_evdev, BTN_MOUSE + i);
+
+	err = evdev_register(sc->sc_evdev);
+	if (err)
+		goto detach;
+#endif
+
 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 	    OID_AUTO, "parseinfo", CTLTYPE_STRING|CTLFLAG_RD,
@@ -680,6 +750,10 @@ ums_detach(device_t self)
 
 	usb_fifo_detach(&sc->sc_fifo);
 
+#ifdef EVDEV
+	evdev_free(sc->sc_evdev);
+#endif
+
 	usbd_transfer_unsetup(sc->sc_xfer, UMS_N_TRANSFER);
 
 	usb_callout_drain(&sc->sc_callout);
@@ -690,9 +764,44 @@ ums_detach(device_t self)
 }
 
 static void
-ums_start_read(struct usb_fifo *fifo)
+ums_reset(struct ums_softc *sc)
+{
+
+	/* reset all USB mouse parameters */
+
+	if (sc->sc_buttons > MOUSE_MSC_MAXBUTTON)
+		sc->sc_hw.buttons = MOUSE_MSC_MAXBUTTON;
+	else
+		sc->sc_hw.buttons = sc->sc_buttons;
+
+	sc->sc_hw.iftype = MOUSE_IF_USB;
+	sc->sc_hw.type = MOUSE_MOUSE;
+	sc->sc_hw.model = MOUSE_MODEL_GENERIC;
+	sc->sc_hw.hwid = 0;
+
+	sc->sc_mode.protocol = MOUSE_PROTO_MSC;
+	sc->sc_mode.rate = -1;
+	sc->sc_mode.resolution = MOUSE_RES_UNKNOWN;
+	sc->sc_mode.accelfactor = 0;
+	sc->sc_mode.level = 0;
+	sc->sc_mode.packetsize = MOUSE_MSC_PACKETSIZE;
+	sc->sc_mode.syncmask[0] = MOUSE_MSC_SYNCMASK;
+	sc->sc_mode.syncmask[1] = MOUSE_MSC_SYNC;
+
+	/* reset status */
+
+	sc->sc_status.flags = 0;
+	sc->sc_status.button = 0;
+	sc->sc_status.obutton = 0;
+	sc->sc_status.dx = 0;
+	sc->sc_status.dy = 0;
+	sc->sc_status.dz = 0;
+	/* sc->sc_status.dt = 0; */
+}
+
+static void
+ums_start_rx(struct ums_softc *sc)
 {
-	struct ums_softc *sc = usb_fifo_softc(fifo);
 	int rate;
 
 	/* Check if we should override the default polling interval */
@@ -715,14 +824,28 @@ ums_start_read(struct usb_fifo *fifo)
 }
 
 static void
-ums_stop_read(struct usb_fifo *fifo)
+ums_stop_rx(struct ums_softc *sc)
 {
-	struct ums_softc *sc = usb_fifo_softc(fifo);
-
 	usbd_transfer_stop(sc->sc_xfer[UMS_INTR_DT]);
 	usb_callout_stop(&sc->sc_callout);
 }
 
+static void
+ums_fifo_start_read(struct usb_fifo *fifo)
+{
+	struct ums_softc *sc = usb_fifo_softc(fifo);
+
+	ums_start_rx(sc);
+}
+
+static void
+ums_fifo_stop_read(struct usb_fifo *fifo)
+{
+	struct ums_softc *sc = usb_fifo_softc(fifo);
+
+	ums_stop_rx(sc);
+}
+
 
 #if ((MOUSE_SYS_PACKETSIZE != 8) || \
      (MOUSE_MSC_PACKETSIZE != 5))
@@ -769,6 +892,21 @@ ums_put_queue(struct ums_softc *sc, int32_t dx, int32_t dy,
 		usb_fifo_put_data_linear(sc->sc_fifo.fp[USB_FIFO_RX], buf,
 		    sc->sc_mode.packetsize, 1);
 
+#ifdef EVDEV
+		if (evdev_rcpt_mask & EVDEV_RCPT_HW_MOUSE) {
+			/* Push evdev event */
+			evdev_push_event(sc->sc_evdev, EV_REL, REL_X, dx);
+			evdev_push_event(sc->sc_evdev, EV_REL, REL_Y, -dy);
+			evdev_push_event(sc->sc_evdev, EV_REL, REL_WHEEL, -dz);
+			evdev_push_event(sc->sc_evdev, EV_REL, REL_HWHEEL, dt);
+			evdev_push_mouse_btn(sc->sc_evdev,
+			    (buttons & ~MOUSE_STDBUTTONS) |
+			    (buttons & (1 << 2) ? MOUSE_BUTTON1DOWN : 0) |
+			    (buttons & (1 << 1) ? MOUSE_BUTTON2DOWN : 0) |
+			    (buttons & (1 << 0) ? MOUSE_BUTTON3DOWN : 0));
+			evdev_sync(sc->sc_evdev);
+		}
+#endif
 	} else {
 		DPRINTF("Buffer full, discarded packet\n");
 	}
@@ -781,8 +919,44 @@ ums_reset_buf(struct ums_softc *sc)
 	usb_fifo_reset(sc->sc_fifo.fp[USB_FIFO_RX]);
 }
 
+#ifdef EVDEV
+static int
+ums_ev_open(struct evdev_dev *evdev, void *ev_softc)
+{
+	struct ums_softc *sc = (struct ums_softc *)ev_softc;
+
+	mtx_lock(&sc->sc_mtx);
+
+	sc->sc_evflags = UMS_EVDEV_OPENED;
+
+	if (sc->sc_fflags == 0) {
+		ums_reset(sc);
+		ums_start_rx(sc);
+	}
+
+	mtx_unlock(&sc->sc_mtx);
+
+	return (0);
+}
+
+static void
+ums_ev_close(struct evdev_dev *evdev, void *ev_softc)
+{
+	struct ums_softc *sc = (struct ums_softc *)ev_softc;
+
+	mtx_lock(&sc->sc_mtx);
+
+	sc->sc_evflags = 0;
+
+	if (sc->sc_fflags == 0)
+		ums_stop_rx(sc);
+
+	mtx_unlock(&sc->sc_mtx);
+}
+#endif
+
 static int
-ums_open(struct usb_fifo *fifo, int fflags)
+ums_fifo_open(struct usb_fifo *fifo, int fflags)
 {
 	struct ums_softc *sc = usb_fifo_softc(fifo);
 
@@ -793,39 +967,13 @@ ums_open(struct usb_fifo *fifo, int fflags)
 		return (EBUSY);
 
 	/* check for first open */
-	if (sc->sc_fflags == 0) {
-
-		/* reset all USB mouse parameters */
-
-		if (sc->sc_buttons > MOUSE_MSC_MAXBUTTON)
-			sc->sc_hw.buttons = MOUSE_MSC_MAXBUTTON;
-		else
-			sc->sc_hw.buttons = sc->sc_buttons;
-
-		sc->sc_hw.iftype = MOUSE_IF_USB;
-		sc->sc_hw.type = MOUSE_MOUSE;
-		sc->sc_hw.model = MOUSE_MODEL_GENERIC;
-		sc->sc_hw.hwid = 0;
-
-		sc->sc_mode.protocol = MOUSE_PROTO_MSC;
-		sc->sc_mode.rate = -1;
-		sc->sc_mode.resolution = MOUSE_RES_UNKNOWN;
-		sc->sc_mode.accelfactor = 0;
-		sc->sc_mode.level = 0;
-		sc->sc_mode.packetsize = MOUSE_MSC_PACKETSIZE;
-		sc->sc_mode.syncmask[0] = MOUSE_MSC_SYNCMASK;
-		sc->sc_mode.syncmask[1] = MOUSE_MSC_SYNC;
-
-		/* reset status */
-
-		sc->sc_status.flags = 0;
-		sc->sc_status.button = 0;
-		sc->sc_status.obutton = 0;
-		sc->sc_status.dx = 0;
-		sc->sc_status.dy = 0;
-		sc->sc_status.dz = 0;
-		/* sc->sc_status.dt = 0; */
-	}
+#ifdef EVDEV
+	if (sc->sc_fflags == 0 && sc->sc_evflags == 0)
+		ums_reset(sc);
+#else
+	if (sc->sc_fflags == 0)
+		ums_reset(sc);
+#endif
 
 	if (fflags & FREAD) {
 		/* allocate RX buffer */
@@ -840,7 +988,7 @@ ums_open(struct usb_fifo *fifo, int fflags)
 }
 
 static void
-ums_close(struct usb_fifo *fifo, int fflags)
+ums_fifo_close(struct usb_fifo *fifo, int fflags)
 {
 	struct ums_softc *sc = usb_fifo_softc(fifo);
 
@@ -853,7 +1001,7 @@ ums_close(struct usb_fifo *fifo, int fflags)
 }
 
 static int
-ums_ioctl(struct usb_fifo *fifo, u_long cmd, void *addr, int fflags)
+ums_fifo_ioctl(struct usb_fifo *fifo, u_long cmd, void *addr, int fflags)
 {
 	struct ums_softc *sc = usb_fifo_softc(fifo);
 	mousemode_t mode;
diff --git a/sys/dev/usb/serial/u3g.c b/sys/dev/usb/serial/u3g.c
index 0aa26bbffe0b..c053b328ef69 100644
--- a/sys/dev/usb/serial/u3g.c
+++ b/sys/dev/usb/serial/u3g.c
@@ -312,6 +312,7 @@ static const STRUCT_USB_HOST_ID u3g_devs[] = {
 	U3G_DEV(HUAWEI, E220BIS, U3GINIT_HUAWEI),
 	U3G_DEV(HUAWEI, E392, U3GINIT_HUAWEISCSI),
 	U3G_DEV(HUAWEI, ME909U, U3GINIT_HUAWEISCSI2),
+	U3G_DEV(HUAWEI, ME909S, U3GINIT_HUAWEISCSI2),
 	U3G_DEV(HUAWEI, MOBILE, U3GINIT_HUAWEI),
 	U3G_DEV(HUAWEI, E1752, U3GINIT_HUAWEISCSI),
 	U3G_DEV(HUAWEI, E1820, U3GINIT_HUAWEISCSI),
diff --git a/sys/dev/usb/usbdevs b/sys/dev/usb/usbdevs
index 5cd917476fb5..dc86bbbc7777 100644
--- a/sys/dev/usb/usbdevs
+++ b/sys/dev/usb/usbdevs
@@ -739,6 +739,7 @@ vendor VIALABS		0x2109	VIA Labs
 vendor ERICSSON		0x2282	Ericsson
 vendor MOTOROLA2	0x22b8	Motorola
 vendor WETELECOM	0x22de	WeTelecom
+vendor TPLINK		0x2357	TP-Link
 vendor WESTMOUNTAIN	0x2405	West Mountain Radio
 vendor TRIPPLITE	0x2478	Tripp-Lite
 vendor HIROSE		0x2631	Hirose Electric
@@ -1206,6 +1207,7 @@ product ASUS RTL8192CU		0x17ab	RTL8192CU
 product ASUS USBN66		0x17ad	USB-N66
 product ASUS USBN10NANO		0x17ba	USB-N10 Nano
 product ASUS USBAC51		0x17d1	USB-AC51
+product ASUS USBAC56		0x17d2	USB-AC56
 product ASUS A730W		0x4202	ASUS MyPal A730W
 product ASUS P535		0x420f	ASUS P535 PDA
 product ASUS GMSC		0x422f	ASUS Generic Mass Storage
@@ -1426,6 +1428,7 @@ product CISCOLINKSYS WUSB54GC	0x0020	WUSB54GC
 product CISCOLINKSYS WUSB54GR	0x0023	WUSB54GR
 product CISCOLINKSYS WUSBF54G	0x0024	WUSBF54G
 product CISCOLINKSYS AE1000	0x002f	AE1000
+product CISCOLINKSYS WUSB6300	0x003f	WUSB6300
 product CISCOLINKSYS USB3GIGV1	0x0041  USB3GIGV1 USB Ethernet Adapter
 product CISCOLINKSYS2 RT3070	0x4001	RT3070
 product CISCOLINKSYS3 RT3070	0x0101	RT3070
@@ -1620,6 +1623,10 @@ product DLINK DSB650TX4		0x200c	10/100 Ethernet
 product DLINK DWL120E		0x3200	DWL-120 rev E
 product DLINK DWA125D1		0x330f	DWA-125 rev D1
 product DLINK DWA123D1		0x3310	DWA-123 rev D1
+product DLINK DWA171A1		0x3314	DWA-171 rev A1
+product DLINK DWA182C1		0x3315	DWA-182 rev C1
+product DLINK DWA180A1		0x3316	DWA-180 rev A1
+product DLINK DWA172A1		0x3318	DWA-172 rev A1
 product DLINK DWL122		0x3700	DWL-122
 product DLINK DWLG120		0x3701	DWL-G120
 product DLINK DWL120F		0x3702	DWL-120 rev F
@@ -1738,6 +1745,9 @@ product EDIMAX EW7718		0x7718	EW-7718
 product EDIMAX EW7733UND	0x7733	EW-7733UnD
 product EDIMAX EW7811UN		0x7811	EW-7811Un
 product	EDIMAX RTL8192CU	0x7822	RTL8192CU
+product EDIMAX EW7811UTC_1	0xa811	EW-7811UTC
+product EDIMAX EW7811UTC_2	0xa812	EW-7811UTC
+product EDIMAX EW7822UAC	0xa822	EW-7822UAC
 
 /* eGalax Products */
 product EGALAX TPANEL		0x0001	Touch Panel
@@ -2261,6 +2271,7 @@ product HAWKING RTL8192CU	0x0019  RTL8192CU
 product HAWKING UF100		0x400c	10/100 USB Ethernet
 product HAWKING RTL8192SU_1	0x0015	RTL8192SU
 product HAWKING RTL8192SU_2	0x0016	RTL8192SU
+product HAWKING HD65U		0x0023	HD65U
 
 /* HID Global GmbH products */
 product HIDGLOBAL CM2020	0x0596	Omnikey Cardman 2020
@@ -2420,6 +2431,7 @@ product HUAWEI E3272_INIT	0x155b	LTE modem initial
 product HUAWEI ME909U		0x1573  LTE modem
 product HUAWEI R215_INIT	0x1582	LTE modem initial
 product HUAWEI R215		0x1588	LTE modem
+product HUAWEI ME909S		0x15c1  LTE modem
 product HUAWEI ETS2055		0x1803	CDMA modem
 product HUAWEI E173		0x1c05	3G modem
 product HUAWEI E173_INIT	0x1c0b	3G modem initial
@@ -2501,6 +2513,7 @@ product IODATA RT3072_1		0x0944	RT3072
 product IODATA RT3072_2		0x0945	RT3072
 product IODATA RT3072_3		0x0947	RT3072
 product IODATA RT3072_4		0x0948	RT3072
+product IODATA WNAC867U		0x0952	WN-AC867U
 product IODATA USBRSAQ		0x0a03	Serial USB-RSAQ1
 product IODATA USBRSAQ5		0x0a0e  Serial USB-RSAQ5
 product IODATA2 USB2SC		0x0a09	USB2.0-SCSI Bridge USB2-SC
@@ -3060,6 +3073,8 @@ product MELCO WLIUCG301N	0x016f	WLI-UC-G301N
 product MELCO WLIUCGNM		0x01a2	WLI-UC-GNM
 product MELCO WLIUCG300HPV1	0x01a8	WLI-UC-G300HP-V1
 product MELCO WLIUCGNM2		0x01ee	WLI-UC-GNM2
+product MELCO WIU2433DM		0x0242	WI-U2-433DM
+product MELCO WIU3866D		0x025d	WI-U3-866D
 
 /* Merlin products */
 product MERLIN V620             0x1110  Merlin V620
@@ -3239,6 +3254,7 @@ product NATIONAL BEARPAW2400	0x1001	BearPaw 2400
 product NEC HUB_0050		0x0050	USB 2.0 7-Port Hub
 product NEC HUB_005A		0x005a	USB 2.0 4-Port Hub
 product NEC WL300NUG		0x0249	WL300NU-G
+product NEC WL900U		0x0408	Aterm WL900U
 product NEC HUB			0x55aa	hub
 product NEC HUB_B		0x55ab	hub
 
@@ -3278,6 +3294,7 @@ product NETGEAR WNDA3200	0x9018	WNDA3200
 product NETGEAR RTL8192CU	0x9021	RTL8192CU
 product NETGEAR WNA1000		0x9040	WNA1000
 product NETGEAR WNA1000M	0x9041	WNA1000M
+product NETGEAR A6100		0x9052	A6100
 product NETGEAR2 MA101		0x4100	MA101
 product NETGEAR2 MA101B		0x4102	MA101 Rev B
 product NETGEAR3 WG111T		0x4250	WG111T
@@ -3550,6 +3567,7 @@ product PLANEX2 GWUS54HP	0xab01	GW-US54HP
 product PLANEX2 GWUS300MINIS	0xab24	GW-US300MiniS
 product PLANEX2	RT3070		0xab25	RT3070
 product PLANEX2 MZKUE150N	0xab2f	MZK-UE150N
+product PLANEX2 GW900D		0xab30	GW-900D
 product PLANEX2 GWUS54MINI2	0xab50	GW-US54Mini2
 product PLANEX2 GWUS54SG	0xc002	GW-US54SG
 product PLANEX2 GWUS54GZL	0xc007	GW-US54GZL
@@ -3963,6 +3981,7 @@ product SEALEVEL 2803_7		0x2873	FTDI compatible adapter
 product SEALEVEL 2803_8		0x2883	FTDI compatible adapter
 
 /* Senao products */
+product SENAO EUB1200AC		0x0100	EnGenius EUB1200AC
 product SENAO RT2870_3		0x0605	RT2870
 product SENAO RT2870_4		0x0615	RT2870
 product SENAO NUB8301		0x2000	NUB-8301
@@ -4211,6 +4230,7 @@ product SITECOMEU RTL8188CU_1	0x0052	RTL8188CU
 product SITECOMEU RTL8188CU_2	0x005c	RTL8188CU
 product SITECOMEU RTL8192CU	0x0061	RTL8192CU
 product SITECOMEU LN032		0x0072	LN-032
+product SITECOMEU WLA7100	0x0074	WLA-7100
 product SITECOMEU LN031  	0x0056	LN-031
 product SITECOMEU LN028		0x061c	LN-028
 product SITECOMEU WL113		0x9071	WL-113
@@ -4454,6 +4474,9 @@ product TOSHIBA G450		0x0d45	G450 modem
 product TOSHIBA HSDPA		0x1302	G450 modem
 product TOSHIBA TRANSMEMORY	0x6545	USB ThumbDrive
 
+/* TP-Link products */
+product TPLINK T4U		0x0101	Archer T4U
+
 /* Trek Technology products */
 product TREK THUMBDRIVE		0x1111	ThumbDrive
 product TREK MEMKEY		0x8888	IBM USB Memory Key
@@ -4463,6 +4486,7 @@ product TREK THUMBDRIVE_8MB	0x9988	ThumbDrive_8MB
 product TRENDNET RTL8192CU	0x624d	RTL8192CU
 product TRENDNET TEW646UBH	0x646b	TEW-646UBH
 product TRENDNET RTL8188CU	0x648b	RTL8188CU
+product TRENDNET TEW805UB	0x805b	TEW-805UB
 
 /* Tripp-Lite products */
 product TRIPPLITE U209		0x2008	Serial
@@ -4706,3 +4730,4 @@ product ZYXEL RT2870_2		0x341a	RT2870
 product ZYXEL RT3070		0x341e	NWD2105
 product ZYXEL RTL8192CU		0x341f	RTL8192CU
 product ZYXEL NWD2705		0x3421	NWD2705
+product ZYXEL NWD6605		0x3426	NWD6605
diff --git a/sys/dev/usb/wlan/if_rum.c b/sys/dev/usb/wlan/if_rum.c
index 932f2a57de96..f127ae6d72a6 100644
--- a/sys/dev/usb/wlan/if_rum.c
+++ b/sys/dev/usb/wlan/if_rum.c
@@ -1118,7 +1118,6 @@ tr_setup:
 
 				tap->wt_flags = 0;
 				tap->wt_rate = data->rate;
-				rum_get_tsf(sc, &tap->wt_tsf);
 				tap->wt_antenna = sc->tx_ant;
 
 				ieee80211_radiotap_tx(vap, m);
diff --git a/sys/dev/usb/wlan/if_rumvar.h b/sys/dev/usb/wlan/if_rumvar.h
index 6c425697834a..7001e08cba1e 100644
--- a/sys/dev/usb/wlan/if_rumvar.h
+++ b/sys/dev/usb/wlan/if_rumvar.h
@@ -44,7 +44,6 @@ struct rum_rx_radiotap_header {
 
 struct rum_tx_radiotap_header {
 	struct ieee80211_radiotap_header wt_ihdr;
-	uint64_t	wt_tsf;
 	uint8_t		wt_flags;
 	uint8_t		wt_rate;
 	uint16_t	wt_chan_freq;
@@ -53,8 +52,7 @@ struct rum_tx_radiotap_header {
 } __packed __aligned(8);
 
 #define RT2573_TX_RADIOTAP_PRESENT					\
-	((1 << IEEE80211_RADIOTAP_TSFT) |				\
-	 (1 << IEEE80211_RADIOTAP_FLAGS) |				\
+	((1 << IEEE80211_RADIOTAP_FLAGS) |				\
 	 (1 << IEEE80211_RADIOTAP_RATE) |				\
 	 (1 << IEEE80211_RADIOTAP_CHANNEL) |				\
 	 (1 << IEEE80211_RADIOTAP_ANTENNA))
diff --git a/sys/dev/usb/wlan/if_run.c b/sys/dev/usb/wlan/if_run.c
index 58e85449bf0e..49c67b4f3066 100644
--- a/sys/dev/usb/wlan/if_run.c
+++ b/sys/dev/usb/wlan/if_run.c
@@ -3077,7 +3077,6 @@ tr_setup:
 			    (struct rt2860_txwi *)(&data->desc + sizeof(struct rt2870_txd));
 			tap->wt_flags = 0;
 			tap->wt_rate = rt2860_rates[data->ridx].rate;
-			run_get_tsf(sc, &tap->wt_tsf);
 			tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
 			tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
 			tap->wt_hwqueue = index;
diff --git a/sys/dev/usb/wlan/if_runvar.h b/sys/dev/usb/wlan/if_runvar.h
index 987905f38443..c92885558170 100644
--- a/sys/dev/usb/wlan/if_runvar.h
+++ b/sys/dev/usb/wlan/if_runvar.h
@@ -66,7 +66,6 @@ struct run_rx_radiotap_header {
 
 struct run_tx_radiotap_header {
 	struct ieee80211_radiotap_header wt_ihdr;
-	uint64_t	wt_tsf;
 	uint8_t		wt_flags;
 	uint8_t		wt_rate;
 	uint16_t	wt_chan_freq;
@@ -77,8 +76,7 @@ struct run_tx_radiotap_header {
 #define IEEE80211_RADIOTAP_HWQUEUE 15
 
 #define	RUN_TX_RADIOTAP_PRESENT				\
-	(1 << IEEE80211_RADIOTAP_TSFT |			\
-	 1 << IEEE80211_RADIOTAP_FLAGS |		\
+	(1 << IEEE80211_RADIOTAP_FLAGS |		\
 	 1 << IEEE80211_RADIOTAP_RATE |			\
 	 1 << IEEE80211_RADIOTAP_CHANNEL |		\
 	 1 << IEEE80211_RADIOTAP_HWQUEUE)
diff --git a/sys/dev/virtio/console/virtio_console.c b/sys/dev/virtio/console/virtio_console.c
index 0a2fa0a8026f..bfef07f1d94a 100644
--- a/sys/dev/virtio/console/virtio_console.c
+++ b/sys/dev/virtio/console/virtio_console.c
@@ -176,8 +176,10 @@ static void	 vtcon_ctrl_port_add_event(struct vtcon_softc *, int);
 static void	 vtcon_ctrl_port_remove_event(struct vtcon_softc *, int);
 static void	 vtcon_ctrl_port_console_event(struct vtcon_softc *, int);
 static void	 vtcon_ctrl_port_open_event(struct vtcon_softc *, int);
+static void	 vtcon_ctrl_port_name_event(struct vtcon_softc *, int,
+		     const char *, size_t);
 static void	 vtcon_ctrl_process_event(struct vtcon_softc *,
-		     struct virtio_console_control *);
+		     struct virtio_console_control *, void *, size_t);
 static void	 vtcon_ctrl_task_cb(void *, int);
 static void	 vtcon_ctrl_event_intr(void *);
 static void	 vtcon_ctrl_poll(struct vtcon_softc *,
@@ -611,8 +613,10 @@ vtcon_ctrl_event_create(struct vtcon_softc *sc)
 	struct virtio_console_control *control;
 	int error;
 
-	control = malloc(sizeof(struct virtio_console_control), M_DEVBUF,
-	    M_ZERO | M_NOWAIT);
+	control = malloc(
+	    sizeof(struct virtio_console_control) + VTCON_BULK_BUFSZ,
+	    M_DEVBUF, M_ZERO | M_NOWAIT);
+
 	if (control == NULL)
 		return (ENOMEM);
 
@@ -796,8 +800,29 @@ vtcon_ctrl_port_open_event(struct vtcon_softc *sc, int id)
 }
 
 static void
+vtcon_ctrl_port_name_event(struct vtcon_softc *sc, int id, const char *name,
+    size_t len)
+{
+	device_t dev;
+	struct vtcon_softc_port *scport;
+	struct vtcon_port *port;
+
+	dev = sc->vtcon_dev;
+	scport = &sc->vtcon_ports[id];
+
+	port = scport->vcsp_port;
+	if (port == NULL) {
+		device_printf(dev, "%s: name port %d, but does not exist\n",
+		    __func__, id);
+		return;
+	}
+
+	tty_makealias(port->vtcport_tty, "vtcon/%*s", (int)len, name);
+}
+
+static void
 vtcon_ctrl_process_event(struct vtcon_softc *sc,
-    struct virtio_console_control *control)
+    struct virtio_console_control *control, void *payload, size_t plen)
 {
 	device_t dev;
 	int id;
@@ -831,6 +856,9 @@ vtcon_ctrl_process_event(struct vtcon_softc *sc,
 		break;
 
 	case VIRTIO_CONSOLE_PORT_NAME:
+		if (payload != NULL && plen > 0)
+			vtcon_ctrl_port_name_event(sc, id,
+			    (const char *)payload, plen);
 		break;
 	}
 }
@@ -842,6 +870,9 @@ vtcon_ctrl_task_cb(void *xsc, int pending)
 	struct virtqueue *vq;
 	struct virtio_console_control *control;
 	int detached;
+	uint32_t len;
+	size_t plen;
+	void *payload;
 
 	sc = xsc;
 	vq = sc->vtcon_ctrl_rxvq;
@@ -849,12 +880,20 @@ vtcon_ctrl_task_cb(void *xsc, int pending)
 	VTCON_LOCK(sc);
 
 	while ((detached = (sc->vtcon_flags & VTCON_FLAG_DETACHED)) == 0) {
-		control = virtqueue_dequeue(vq, NULL);
+		control = virtqueue_dequeue(vq, &len);
+		payload = NULL;
+		plen = 0;
+
 		if (control == NULL)
 			break;
 
+		if (len > sizeof(control)) {
+			payload = (void *)(control + 1);
+			plen = len - sizeof(control);
+		}
+
 		VTCON_UNLOCK(sc);
-		vtcon_ctrl_process_event(sc, control);
+		vtcon_ctrl_process_event(sc, control, payload, plen);
 		VTCON_LOCK(sc);
 		vtcon_ctrl_event_requeue(sc, control);
 	}
diff --git a/sys/fs/cuse/cuse.c b/sys/fs/cuse/cuse.c
index 6035f8d59d53..33d36c586e2b 100644
--- a/sys/fs/cuse/cuse.c
+++ b/sys/fs/cuse/cuse.c
@@ -63,6 +63,12 @@
 
 MODULE_VERSION(cuse, 1);
 
+/*
+ * Prevent cuse4bsd.ko and cuse.ko from loading at the same time by
+ * declaring support for the cuse4bsd interface in cuse.ko:
+ */
+MODULE_VERSION(cuse4bsd, 1);
+
 #define	NBUSY	((uint8_t *)1)
 
 #ifdef FEATURE
diff --git a/sys/fs/msdosfs/denode.h b/sys/fs/msdosfs/denode.h
index 6446db3478d5..6c467244dd30 100644
--- a/sys/fs/msdosfs/denode.h
+++ b/sys/fs/msdosfs/denode.h
@@ -265,7 +265,6 @@ int msdosfs_reclaim(struct vop_reclaim_args *);
  */
 int deget(struct msdosfsmount *, u_long, u_long, struct denode **);
 int uniqdosname(struct denode *, struct componentname *, u_char *);
-int findwin95(struct denode *);
 
 int readep(struct msdosfsmount *pmp, u_long dirclu, u_long dirofs,  struct buf **bpp, struct direntry **epp);
 int readde(struct denode *dep, struct buf **bpp, struct direntry **epp);
diff --git a/sys/fs/msdosfs/msdosfs_lookup.c b/sys/fs/msdosfs/msdosfs_lookup.c
index f9c11704acc0..405085f32d2f 100644
--- a/sys/fs/msdosfs/msdosfs_lookup.c
+++ b/sys/fs/msdosfs/msdosfs_lookup.c
@@ -1062,55 +1062,3 @@ uniqdosname(struct denode *dep, struct componentname *cnp, u_char *cp)
 		}
 	}
 }
-
-/*
- * Find any Win'95 long filename entry in directory dep
- */
-int
-findwin95(struct denode *dep)
-{
-	struct msdosfsmount *pmp = dep->de_pmp;
-	struct direntry *dentp;
-	int blsize, win95;
-	u_long cn;
-	daddr_t bn;
-	struct buf *bp;
-
-	win95 = 1;
-	/*
-	 * Read through the directory looking for Win'95 entries
-	 * Note: Error currently handled just as EOF			XXX
-	 */
-	for (cn = 0;; cn++) {
-		if (pcbmap(dep, cn, &bn, 0, &blsize))
-			return (win95);
-		if (bread(pmp->pm_devvp, bn, blsize, NOCRED, &bp)) {
-			brelse(bp);
-			return (win95);
-		}
-		for (dentp = (struct direntry *)bp->b_data;
-		     (char *)dentp < bp->b_data + blsize;
-		     dentp++) {
-			if (dentp->deName[0] == SLOT_EMPTY) {
-				/*
-				 * Last used entry and not found
-				 */
-				brelse(bp);
-				return (win95);
-			}
-			if (dentp->deName[0] == SLOT_DELETED) {
-				/*
-				 * Ignore deleted files
-				 * Note: might be an indication of Win'95 anyway	XXX
-				 */
-				continue;
-			}
-			if (dentp->deAttributes == ATTR_WIN95) {
-				brelse(bp);
-				return 1;
-			}
-			win95 = 0;
-		}
-		brelse(bp);
-	}
-}
diff --git a/sys/fs/msdosfs/msdosfs_vfsops.c b/sys/fs/msdosfs/msdosfs_vfsops.c
index 63d60dde015e..9b42b20e1610 100644
--- a/sys/fs/msdosfs/msdosfs_vfsops.c
+++ b/sys/fs/msdosfs/msdosfs_vfsops.c
@@ -175,24 +175,8 @@ update_mp(struct mount *mp, struct thread *td)
 
 	if (pmp->pm_flags & MSDOSFSMNT_NOWIN95)
 		pmp->pm_flags |= MSDOSFSMNT_SHORTNAME;
-	else if (!(pmp->pm_flags &
-	    (MSDOSFSMNT_SHORTNAME | MSDOSFSMNT_LONGNAME))) {
-		struct vnode *rootvp;
-
-		/*
-		 * Try to divine whether to support Win'95 long filenames
-		 */
-		if (FAT32(pmp))
-			pmp->pm_flags |= MSDOSFSMNT_LONGNAME;
-		else {
-			if ((error =
-			    msdosfs_root(mp, LK_EXCLUSIVE, &rootvp)) != 0)
-				return error;
-			pmp->pm_flags |= findwin95(VTODE(rootvp)) ?
-			    MSDOSFSMNT_LONGNAME : MSDOSFSMNT_SHORTNAME;
-			vput(rootvp);
-		}
-	}
+	else
+		pmp->pm_flags |= MSDOSFSMNT_LONGNAME;
 	return 0;
 }
 
diff --git a/sys/geom/bde/g_bde.c b/sys/geom/bde/g_bde.c
index 7eda17fee2c3..6ebd8562222c 100644
--- a/sys/geom/bde/g_bde.c
+++ b/sys/geom/bde/g_bde.c
@@ -85,7 +85,7 @@ g_bde_orphan(struct g_consumer *cp)
 	sc = gp->softc;
 	gp->flags |= G_GEOM_WITHER;
 	LIST_FOREACH(pp, &gp->provider, provider)
-		g_orphan_provider(pp, ENXIO);
+		g_wither_provider(pp, ENXIO);
 	bzero(sc, sizeof(struct g_bde_softc));	/* destroy evidence */
 	return;
 }
diff --git a/sys/geom/concat/g_concat.c b/sys/geom/concat/g_concat.c
index 4627ff9fa2ca..ccd4bad3eaf9 100644
--- a/sys/geom/concat/g_concat.c
+++ b/sys/geom/concat/g_concat.c
@@ -129,10 +129,9 @@ g_concat_remove_disk(struct g_concat_disk *disk)
 	}
 
 	if (sc->sc_provider != NULL) {
-		sc->sc_provider->flags |= G_PF_WITHER;
 		G_CONCAT_DEBUG(0, "Device %s deactivated.",
 		    sc->sc_provider->name);
-		g_orphan_provider(sc->sc_provider, ENXIO);
+		g_wither_provider(sc->sc_provider, ENXIO);
 		sc->sc_provider = NULL;
 	}
 
diff --git a/sys/geom/gate/g_gate.c b/sys/geom/gate/g_gate.c
index 8cfe9d4aaac0..767c6837d165 100644
--- a/sys/geom/gate/g_gate.c
+++ b/sys/geom/gate/g_gate.c
@@ -109,8 +109,7 @@ g_gate_destroy(struct g_gate_softc *sc, boolean_t force)
 	wakeup(sc);
 	mtx_unlock(&sc->sc_queue_mtx);
 	gp = pp->geom;
-	pp->flags |= G_PF_WITHER;
-	g_orphan_provider(pp, ENXIO);
+	g_wither_provider(pp, ENXIO);
 	callout_drain(&sc->sc_callout);
 	bioq_init(&queue);
 	mtx_lock(&sc->sc_queue_mtx);
diff --git a/sys/geom/geom_io.c b/sys/geom/geom_io.c
index 401c20f24286..dbb346842df7 100644
--- a/sys/geom/geom_io.c
+++ b/sys/geom/geom_io.c
@@ -69,7 +69,6 @@ static int	g_io_transient_map_bio(struct bio *bp);
 
 static struct g_bioq g_bio_run_down;
 static struct g_bioq g_bio_run_up;
-static struct g_bioq g_bio_run_task;
 
 /*
  * Pace is a hint that we've had some trouble recently allocating
@@ -280,7 +279,6 @@ g_io_init()
 
 	g_bioq_init(&g_bio_run_down);
 	g_bioq_init(&g_bio_run_up);
-	g_bioq_init(&g_bio_run_task);
 	biozone = uma_zcreate("g_bio", sizeof (struct bio),
 	    NULL, NULL,
 	    NULL, NULL,
@@ -884,54 +882,26 @@ g_io_schedule_down(struct thread *tp __unused)
 }
 
 void
-bio_taskqueue(struct bio *bp, bio_task_t *func, void *arg)
-{
-	bp->bio_task = func;
-	bp->bio_task_arg = arg;
-	/*
-	 * The taskqueue is actually just a second queue off the "up"
-	 * queue, so we use the same lock.
-	 */
-	g_bioq_lock(&g_bio_run_up);
-	KASSERT(!(bp->bio_flags & BIO_ONQUEUE),
-	    ("Bio already on queue bp=%p target taskq", bp));
-	bp->bio_flags |= BIO_ONQUEUE;
-	TAILQ_INSERT_TAIL(&g_bio_run_task.bio_queue, bp, bio_queue);
-	g_bio_run_task.bio_queue_length++;
-	wakeup(&g_wait_up);
-	g_bioq_unlock(&g_bio_run_up);
-}
-
-
-void
 g_io_schedule_up(struct thread *tp __unused)
 {
 	struct bio *bp;
+
 	for(;;) {
 		g_bioq_lock(&g_bio_run_up);
-		bp = g_bioq_first(&g_bio_run_task);
-		if (bp != NULL) {
-			g_bioq_unlock(&g_bio_run_up);
-			THREAD_NO_SLEEPING();
-			CTR1(KTR_GEOM, "g_up processing task bp %p", bp);
-			bp->bio_task(bp->bio_task_arg);
-			THREAD_SLEEPING_OK();
-			continue;
-		}
 		bp = g_bioq_first(&g_bio_run_up);
-		if (bp != NULL) {
-			g_bioq_unlock(&g_bio_run_up);
-			THREAD_NO_SLEEPING();
-			CTR4(KTR_GEOM, "g_up biodone bp %p provider %s off "
-			    "%jd len %ld", bp, bp->bio_to->name,
-			    bp->bio_offset, bp->bio_length);
-			biodone(bp);
-			THREAD_SLEEPING_OK();
+		if (bp == NULL) {
+			CTR0(KTR_GEOM, "g_up going to sleep");
+			msleep(&g_wait_up, &g_bio_run_up.bio_queue_lock,
+			    PRIBIO | PDROP, "-", 0);
 			continue;
 		}
-		CTR0(KTR_GEOM, "g_up going to sleep");
-		msleep(&g_wait_up, &g_bio_run_up.bio_queue_lock,
-		    PRIBIO | PDROP, "-", 0);
+		g_bioq_unlock(&g_bio_run_up);
+		THREAD_NO_SLEEPING();
+		CTR4(KTR_GEOM, "g_up biodone bp %p provider %s off "
+		    "%jd len %ld", bp, bp->bio_to->name,
+		    bp->bio_offset, bp->bio_length);
+		biodone(bp);
+		THREAD_SLEEPING_OK();
 	}
 }
 
diff --git a/sys/geom/journal/g_journal.c b/sys/geom/journal/g_journal.c
index 0678003cbccf..d4d6a6896cb3 100644
--- a/sys/geom/journal/g_journal.c
+++ b/sys/geom/journal/g_journal.c
@@ -2462,8 +2462,7 @@ g_journal_destroy(struct g_journal_softc *sc)
 		GJ_DEBUG(1, "Marking %s as clean.", sc->sc_name);
 		g_journal_metadata_update(sc);
 		g_topology_lock();
-		pp->flags |= G_PF_WITHER;
-		g_orphan_provider(pp, ENXIO);
+		g_wither_provider(pp, ENXIO);
 	} else {
 		g_topology_lock();
 	}
diff --git a/sys/geom/linux_lvm/g_linux_lvm.c b/sys/geom/linux_lvm/g_linux_lvm.c
index bf2f1e795f3b..f03ba10579b0 100644
--- a/sys/geom/linux_lvm/g_linux_lvm.c
+++ b/sys/geom/linux_lvm/g_linux_lvm.c
@@ -333,7 +333,7 @@ g_llvm_remove_disk(struct g_llvm_vg *vg, struct g_consumer *cp)
 		if (found) {
 			G_LLVM_DEBUG(0, "Device %s removed.",
 			    lv->lv_gprov->name);
-			g_orphan_provider(lv->lv_gprov, ENXIO);
+			g_wither_provider(lv->lv_gprov, ENXIO);
 			lv->lv_gprov = NULL;
 		}
 	}
diff --git a/sys/geom/mirror/g_mirror.c b/sys/geom/mirror/g_mirror.c
index 75433d15b6d0..112d9da52dbb 100644
--- a/sys/geom/mirror/g_mirror.c
+++ b/sys/geom/mirror/g_mirror.c
@@ -2154,10 +2154,9 @@ g_mirror_destroy_provider(struct g_mirror_softc *sc)
 	mtx_unlock(&sc->sc_queue_mtx);
 	G_MIRROR_DEBUG(0, "Device %s: provider %s destroyed.", sc->sc_name,
 	    sc->sc_provider->name);
-	sc->sc_provider->flags |= G_PF_WITHER;
-	g_orphan_provider(sc->sc_provider, ENXIO);
-	g_topology_unlock();
+	g_wither_provider(sc->sc_provider, ENXIO);
 	sc->sc_provider = NULL;
+	g_topology_unlock();
 	LIST_FOREACH(disk, &sc->sc_disks, d_next) {
 		if (disk->d_state == G_MIRROR_DISK_STATE_SYNCHRONIZING)
 			g_mirror_sync_stop(disk, 1);
diff --git a/sys/geom/mountver/g_mountver.c b/sys/geom/mountver/g_mountver.c
index 61375efce0e6..278157b355d3 100644
--- a/sys/geom/mountver/g_mountver.c
+++ b/sys/geom/mountver/g_mountver.c
@@ -327,7 +327,7 @@ g_mountver_destroy(struct g_geom *gp, boolean_t force)
 		G_MOUNTVER_DEBUG(0, "Device %s removed.", gp->name);
 	}
 	if (pp != NULL)
-		g_orphan_provider(pp, ENXIO);
+		g_wither_provider(pp, ENXIO);
 	g_mountver_discard_queued(gp);
 	g_free(sc->sc_provider_name);
 	g_free(gp->softc);
diff --git a/sys/geom/raid3/g_raid3.c b/sys/geom/raid3/g_raid3.c
index 9b3c483d44d9..174a89398ef6 100644
--- a/sys/geom/raid3/g_raid3.c
+++ b/sys/geom/raid3/g_raid3.c
@@ -2368,8 +2368,7 @@ g_raid3_destroy_provider(struct g_raid3_softc *sc)
 	mtx_unlock(&sc->sc_queue_mtx);
 	G_RAID3_DEBUG(0, "Device %s: provider %s destroyed.", sc->sc_name,
 	    sc->sc_provider->name);
-	sc->sc_provider->flags |= G_PF_WITHER;
-	g_orphan_provider(sc->sc_provider, ENXIO);
+	g_wither_provider(sc->sc_provider, ENXIO);
 	g_topology_unlock();
 	sc->sc_provider = NULL;
 	if (sc->sc_syncdisk != NULL)
diff --git a/sys/geom/shsec/g_shsec.c b/sys/geom/shsec/g_shsec.c
index bfdc8fdc1672..dddb8713e2fc 100644
--- a/sys/geom/shsec/g_shsec.c
+++ b/sys/geom/shsec/g_shsec.c
@@ -156,7 +156,7 @@ g_shsec_remove_disk(struct g_consumer *cp)
 
 	sc->sc_disks[no] = NULL;
 	if (sc->sc_provider != NULL) {
-		g_orphan_provider(sc->sc_provider, ENXIO);
+		g_wither_provider(sc->sc_provider, ENXIO);
 		sc->sc_provider = NULL;
 		G_SHSEC_DEBUG(0, "Device %s removed.", sc->sc_name);
 	}
diff --git a/sys/geom/stripe/g_stripe.c b/sys/geom/stripe/g_stripe.c
index 1e88e6d606f0..a7e81677e269 100644
--- a/sys/geom/stripe/g_stripe.c
+++ b/sys/geom/stripe/g_stripe.c
@@ -171,10 +171,9 @@ g_stripe_remove_disk(struct g_consumer *cp)
 	}
 
 	if (sc->sc_provider != NULL) {
-		sc->sc_provider->flags |= G_PF_WITHER;
 		G_STRIPE_DEBUG(0, "Device %s deactivated.",
 		    sc->sc_provider->name);
-		g_orphan_provider(sc->sc_provider, ENXIO);
+		g_wither_provider(sc->sc_provider, ENXIO);
 		sc->sc_provider = NULL;
 	}
 
diff --git a/sys/geom/vinum/geom_vinum_rm.c b/sys/geom/vinum/geom_vinum_rm.c
index 0d94de9626ca..049bae07ab20 100644
--- a/sys/geom/vinum/geom_vinum_rm.c
+++ b/sys/geom/vinum/geom_vinum_rm.c
@@ -223,8 +223,7 @@ gv_rm_vol(struct gv_softc *sc, struct gv_volume *v)
 	/* Get rid of the volume's provider. */
 	if (pp != NULL) {
 		g_topology_lock();
-		pp->flags |= G_PF_WITHER;
-		g_orphan_provider(pp, ENXIO);
+		g_wither_provider(pp, ENXIO);
 		g_topology_unlock();
 	}
 }
diff --git a/sys/geom/virstor/g_virstor.c b/sys/geom/virstor/g_virstor.c
index 72d042d60592..bedf406a0742 100644
--- a/sys/geom/virstor/g_virstor.c
+++ b/sys/geom/virstor/g_virstor.c
@@ -900,11 +900,9 @@ remove_component(struct g_virstor_softc *sc, struct g_virstor_component *comp,
 	LOG_MSG(LVL_DEBUG, "Component %s removed from %s", c->provider->name,
 	    sc->geom->name);
 	if (sc->provider != NULL) {
-		/* Whither, GEOM? */
-		sc->provider->flags |= G_PF_WITHER;
-		g_orphan_provider(sc->provider, ENXIO);
+		LOG_MSG(LVL_INFO, "Removing provider %s", sc->provider->name);
+		g_wither_provider(sc->provider, ENXIO);
 		sc->provider = NULL;
-		LOG_MSG(LVL_INFO, "Removing provider %s", sc->geom->name);
 	}
 
 	if (c->acr > 0 || c->acw > 0 || c->ace > 0)
diff --git a/sys/gnu/dts/arm/alpine.dtsi b/sys/gnu/dts/arm/alpine.dtsi
index 9af2d60e9a7f..db8752fc480e 100644
--- a/sys/gnu/dts/arm/alpine.dtsi
+++ b/sys/gnu/dts/arm/alpine.dtsi
@@ -155,6 +155,16 @@
 			ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
 
 			bus-range = <0x00 0x00>;
+			msi-parent = <&msix>;
+		};
+
+		msix: msix@fbe00000 {
+			compatible = "al,alpine-msix";
+			reg = <0x0 0xfbe00000 0x0 0x100000>;
+			interrupt-controller;
+			msi-controller;
+			al,msi-base-spi = <96>;
+			al,msi-num-spis = <64>;
 		};
 	};
 };
diff --git a/sys/gnu/dts/arm/am335x-baltos-ir2110.dts b/sys/gnu/dts/arm/am335x-baltos-ir2110.dts
new file mode 100644
index 000000000000..a9a97307d66c
--- /dev/null
+++ b/sys/gnu/dts/arm/am335x-baltos-ir2110.dts
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/dts-v1/;
+
+#include "am335x-baltos.dtsi"
+
+/ {
+	model = "OnRISC Baltos iR 2110";
+};
+
+&am33xx_pinmux {
+	uart1_pins: pinmux_uart1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)      /* uart1_rxd */
+			AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0)      /* uart1_txd */
+			AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* uart1_ctsn */
+			AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* uart1_rtsn */
+			AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
+			AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
+			AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
+			AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
+		>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
+	dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+	dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+	rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
+
+	status = "okay";
+};
+
+&usb0_phy {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rmii";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <7>;
+	phy-mode = "rgmii-txid";
+	dual_emac_res_vlan = <2>;
+};
+
+&phy_sel {
+	rmii-clock-ext = <1>;
+};
diff --git a/sys/gnu/dts/arm/am335x-baltos-ir3220.dts b/sys/gnu/dts/arm/am335x-baltos-ir3220.dts
new file mode 100644
index 000000000000..fe002a17c04b
--- /dev/null
+++ b/sys/gnu/dts/arm/am335x-baltos-ir3220.dts
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/dts-v1/;
+
+#include "am335x-baltos.dtsi"
+
+/ {
+	model = "OnRISC Baltos iR 3220";
+};
+
+&am33xx_pinmux {
+	tca6416_pins: pinmux_tca6416_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
+		>;
+	};
+
+	uart1_pins: pinmux_uart1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)      /* uart1_rxd */
+			AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0)      /* uart1_txd */
+			AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* uart1_ctsn */
+			AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* uart1_rtsn */
+			AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
+			AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
+			AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
+			AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
+		>;
+	};
+
+	uart2_pins: pinmux_uart2_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
+			AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
+			AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
+			AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
+			AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
+			AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
+			AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
+			AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_ad15.gpio1[15] RI */
+
+			AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7)      /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
+		>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
+	dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+	dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+	rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
+
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+	dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+	dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+	rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+
+	status = "okay";
+};
+
+&i2c1 {
+	tca6416: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <20 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&tca6416_pins>;
+	};
+};
+
+&usb0_phy {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&cpsw_emac0 {
+	phy-mode = "rmii";
+	dual_emac_res_vlan = <1>;
+	fixed-link {
+		speed = <100>;
+		full-duplex;
+	};
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <7>;
+	phy-mode = "rgmii-txid";
+	dual_emac_res_vlan = <2>;
+};
+
+&phy_sel {
+	rmii-clock-ext = <1>;
+};
diff --git a/sys/gnu/dts/arm/am335x-baltos-ir5221.dts b/sys/gnu/dts/arm/am335x-baltos-ir5221.dts
index ded1eb64ea52..d0faa7b8c5da 100644
--- a/sys/gnu/dts/arm/am335x-baltos-ir5221.dts
+++ b/sys/gnu/dts/arm/am335x-baltos-ir5221.dts
@@ -13,83 +13,19 @@
 
 /dts-v1/;
 
-#include "am33xx.dtsi"
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "am335x-baltos.dtsi"
 
 / {
 	model = "OnRISC Baltos iR 5221";
-	compatible = "vscom,onrisc", "ti,am33xx";
-
-	cpus {
-		cpu@0 {
-			cpu0-supply = <&vdd1_reg>;
-		};
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>; /* 256 MB */
-	};
-
-	vbat: fixedregulator@0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vbat";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-	};
-
-	wl12xx_vmmc: fixedregulator@2 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&wl12xx_gpio>;
-		compatible = "regulator-fixed";
-		regulator-name = "vwl1271";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio3 8 0>;
-		startup-delay-us = <70000>;
-		enable-active-high;
-	};
 };
 
 &am33xx_pinmux {
-	mmc2_pins: pinmux_mmc2_pins {
-		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad8.mmc1_dat0_mux0 */
-			AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad9.mmc1_dat1_mux0 */
-			AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad10.mmc1_dat2_mux0 */
-			AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad11.mmc1_dat3_mux0 */
-			AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_csn1.mmc1_clk_mux0 */
-			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_csn2.mmc1_cmd_mux0 */
-			AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7)      /* emu0.gpio3[7] */
-		>;
-	};
-
-	wl12xx_gpio: pinmux_wl12xx_gpio {
-		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* emu1.gpio3[8] */
-		>;
-	};
-
-	tps65910_pins: pinmux_tps65910_pins {
-		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7)      /* gpmc_ben1.gpio1[28] */
-		>;
-	};
-
 	tca6416_pins: pinmux_tca6416_pins {
 		pinctrl-single,pins = <
 			AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7)      /* xdma_event_intr1.gpio0[20] tca6416 stuff */
 		>;
 	};
 
-	i2c1_pins: pinmux_i2c1_pins {
-		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2)      /* spi0_d1.i2c1_sda_mux3 */
-			AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2)      /* spi0_cs0.i2c1_scl_mux3 */
-		>;
-	};
 
 	dcan1_pins: pinmux_dcan1_pins {
 		pinctrl-single,pins = <
@@ -98,19 +34,12 @@
 		>;
 	};
 
-	uart0_pins: pinmux_uart0_pins {
-		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)		/* uart0_txd.uart0_txd */
-		>;
-	};
-
 	uart1_pins: pinmux_uart1_pins {
 		pinctrl-single,pins = <
 			AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)      /* uart1_rxd */
 			AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0)      /* uart1_txd */
-			AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* uart1_ctsn, INPUT | MODE0 */
-			AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* uart1_rtsn, OUTPUT | MODE0 */
+			AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* uart1_ctsn */
+			AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* uart1_rtsn */
 			AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
 			AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
 			AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
@@ -122,8 +51,8 @@
 		pinctrl-single,pins = <
 			AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)      /* spi0_sclk.uart2_rxd_mux3 */
 			AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)      /* spi0_d0.uart2_txd_mux3 */
-			AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* i2c0_sda.uart2_ctsn_mux0 */
-			AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* i2c0_scl.uart2_rtsn_mux0 */
+			AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2)      /* i2c0_sda.uart2_ctsn_mux0 */
+			AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)      /* i2c0_scl.uart2_rtsn_mux0 */
 			AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad12.gpio1[12] DTR */
 			AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad13.gpio1[13] DSR */
 			AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)      /* gpmc_ad14.gpio1[14] DCD */
@@ -133,150 +62,6 @@
 		>;
 	};
 
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 1 */
-			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)       /* mii1_crs.rmii1_crs_dv */
-			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)      /* mii1_tx_en.rmii1_txen */
-			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)      /* mii1_txd1.rmii1_txd1 */
-			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)      /* mii1_txd0.rmii1_txd0 */
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)      /* mii1_rxd1.rmii1_rxd1 */
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)      /* mii1_rxd0.rmii1_rxd0 */
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* rmii1_ref_clk.rmii1_refclk */
-
-
-			/* Slave 2 */
-			AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
-			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
-			AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
-			AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
-			AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
-			AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
-			AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
-			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
-			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
-			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
-			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
-			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
-		>;
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 1 reset value */
-			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
-
-			/* Slave 2 reset value*/
-			AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-		>;
-	};
-
-	davinci_mdio_default: davinci_mdio_default {
-		pinctrl-single,pins = <
-			/* MDIO */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
-			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
-		>;
-	};
-
-	davinci_mdio_sleep: davinci_mdio_sleep {
-		pinctrl-single,pins = <
-			/* MDIO reset value */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-		>;
-	};
-
-	nandflash_pins_s0: nandflash_pins_s0 {
-		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
-			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
-			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
-			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
-			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
-			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
-			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
-			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
-			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
-			AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
-			AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
-			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
-			AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
-			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
-			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
-		>;
-	};
-};
-
-&elm {
-	status = "okay";
-};
-
-&gpmc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&nandflash_pins_s0>;
-	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
-	status = "okay";
-
-	nand@0,0 {
-		reg = <0 0 0>; /* CS0, offset 0 */
-		nand-bus-width = <8>;
-		ti,nand-ecc-opt = "bch8";
-		ti,nand-xfer-type = "polled";
-
-		gpmc,device-nand = "true";
-		gpmc,device-width = <1>;
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <44>;
-		gpmc,cs-wr-off-ns = <44>;
-		gpmc,adv-on-ns = <6>;
-		gpmc,adv-rd-off-ns = <34>;
-		gpmc,adv-wr-off-ns = <44>;
-		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <40>;
-		gpmc,oe-on-ns = <0>;
-		gpmc,oe-off-ns = <54>;
-		gpmc,access-ns = <64>;
-		gpmc,rd-cycle-ns = <82>;
-		gpmc,wr-cycle-ns = <82>;
-		gpmc,wait-on-read = "true";
-		gpmc,wait-on-write = "true";
-		gpmc,bus-turnaround-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <0>;
-		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
-		gpmc,wr-access-ns = <40>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-		elm_id = <&elm>;
-	};
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-
-	status = "okay";
 };
 
 &uart1 {
@@ -286,8 +71,6 @@
 	dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
 	dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
 	rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
-	cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-	rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 
 	status = "okay";
 };
@@ -299,35 +82,11 @@
 	dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
 	dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 	rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
-	cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
-	rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
 
 	status = "okay";
 };
 
 &i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-
-	status = "okay";
-	clock-frequency = <400000>;
-
-	tps: tps@2d {
-		reg = <0x2d>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <28 GPIO_ACTIVE_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&tps65910_pins>;
-	};
-
-	at24@50 {
-		compatible = "at24,24c02";
-		pagesize = <8>;
-		reg = <0x50>;
-	};
-
 	tca6416: gpio@20 {
 		compatible = "ti,tca6416";
 		reg = <0x20>;
@@ -340,14 +99,6 @@
 	};
 };
 
-&usb {
-	status = "okay";
-};
-
-&usb_ctrl_mod {
-	status = "okay";
-};
-
 &usb0_phy {
 	status = "okay";
 };
@@ -366,112 +117,13 @@
 	dr_mode = "otg";
 };
 
-&cppi41dma  {
-	status = "okay";
-};
-
-#include "tps65910.dtsi"
-
-&tps {
-	vcc1-supply = <&vbat>;
-	vcc2-supply = <&vbat>;
-	vcc3-supply = <&vbat>;
-	vcc4-supply = <&vbat>;
-	vcc5-supply = <&vbat>;
-	vcc6-supply = <&vbat>;
-	vcc7-supply = <&vbat>;
-	vccio-supply = <&vbat>;
-
-	ti,en-ck32k-xtal = <1>;
-
-	regulators {
-		vrtc_reg: regulator@0 {
-			regulator-always-on;
-		};
-
-		vio_reg: regulator@1 {
-			regulator-always-on;
-		};
-
-		vdd1_reg: regulator@2 {
-			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
-			regulator-name = "vdd_mpu";
-			regulator-min-microvolt = <912500>;
-			regulator-max-microvolt = <1312500>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-
-		vdd2_reg: regulator@3 {
-			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
-			regulator-name = "vdd_core";
-			regulator-min-microvolt = <912500>;
-			regulator-max-microvolt = <1150000>;
-			regulator-boot-on;
-			regulator-always-on;
-		};
-
-		vdd3_reg: regulator@4 {
-			regulator-always-on;
-		};
-
-		vdig1_reg: regulator@5 {
-			regulator-always-on;
-		};
-
-		vdig2_reg: regulator@6 {
-			regulator-always-on;
-		};
-
-		vpll_reg: regulator@7 {
-			regulator-always-on;
-		};
-
-		vdac_reg: regulator@8 {
-			regulator-always-on;
-		};
-
-		vaux1_reg: regulator@9 {
-			regulator-always-on;
-		};
-
-		vaux2_reg: regulator@10 {
-			regulator-always-on;
-		};
-
-		vaux33_reg: regulator@11 {
-			regulator-always-on;
-		};
-
-		vmmc_reg: regulator@12 {
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <3300000>;
-			regulator-always-on;
-		};
-	};
-};
-
-&mac {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
-	dual_emac = <1>;
-
-	status = "okay";
-};
-
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_default>;
-	pinctrl-1 = <&davinci_mdio_sleep>;
-
-	status = "okay";
-};
-
 &cpsw_emac0 {
-	phy_id = <&davinci_mdio>, <0>;
 	phy-mode = "rmii";
 	dual_emac_res_vlan = <1>;
+	fixed-link {
+		speed = <100>;
+		full-duplex;
+	};
 };
 
 &cpsw_emac1 {
@@ -484,42 +136,6 @@
 	rmii-clock-ext = <1>;
 };
 
-&mmc1 {
-	vmmc-supply = <&vmmc_reg>;
-	status = "okay";
-};
-
-&mmc2 {
-	status = "okay";
-	vmmc-supply = <&wl12xx_vmmc>;
-	ti,non-removable;
-	bus-width = <4>;
-	cap-power-off-card;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	wlcore: wlcore@2 {
-		compatible = "ti,wl1835";
-		reg = <2>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
-	};
-};
-
-&sham {
-	status = "okay";
-};
-
-&aes {
-	status = "okay";
-};
-
-&gpio0 {
-	ti,no-reset-on-init;
-};
-
 &dcan1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&dcan1_pins>;
diff --git a/sys/gnu/dts/arm/am335x-baltos.dtsi b/sys/gnu/dts/arm/am335x-baltos.dtsi
new file mode 100644
index 000000000000..c8609d8d2c55
--- /dev/null
+++ b/sys/gnu/dts/arm/am335x-baltos.dtsi
@@ -0,0 +1,408 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+#include "am33xx.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "vscom,onrisc", "ti,am33xx";
+
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&vdd1_reg>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	vbat: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+
+	wl12xx_vmmc: fixedregulator@2 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&wl12xx_gpio>;
+		compatible = "regulator-fixed";
+		regulator-name = "vwl1271";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio3 8 0>;
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+};
+
+&am33xx_pinmux {
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad8.mmc1_dat0_mux0 */
+			AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad9.mmc1_dat1_mux0 */
+			AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad10.mmc1_dat2_mux0 */
+			AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_ad11.mmc1_dat3_mux0 */
+			AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_csn1.mmc1_clk_mux0 */
+			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)      /* gpmc_csn2.mmc1_cmd_mux0 */
+			AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7)      /* emu0.gpio3[7] */
+		>;
+	};
+
+	wl12xx_gpio: pinmux_wl12xx_gpio {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* emu1.gpio3[8] */
+		>;
+	};
+
+	tps65910_pins: pinmux_tps65910_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7)      /* gpmc_ben1.gpio1[28] */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2)      /* spi0_d1.i2c1_sda_mux3 */
+			AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2)      /* spi0_cs0.i2c1_scl_mux3 */
+		>;
+	};
+
+	uart0_pins: pinmux_uart0_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)		/* uart0_txd.uart0_txd */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)       /* mii1_crs.rmii1_crs_dv */
+			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)      /* mii1_tx_en.rmii1_txen */
+			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)      /* mii1_txd1.rmii1_txd1 */
+			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)      /* mii1_txd0.rmii1_txd0 */
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)      /* mii1_rxd1.rmii1_rxd1 */
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)      /* mii1_rxd0.rmii1_rxd0 */
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* rmii1_ref_clk.rmii1_refclk */
+
+
+			/* Slave 2 */
+			AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
+			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
+			AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
+			AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
+			AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
+			AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
+			AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
+			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
+			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
+			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
+			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
+			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+			/* Slave 2 reset value*/
+			AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	nandflash_pins_s0: nandflash_pins_s0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
+			AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
+			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+			AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+		>;
+	};
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nandflash_pins_s0>;
+	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
+	status = "okay";
+
+	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+		nand-bus-width = <8>;
+		ti,nand-ecc-opt = "bch8";
+		ti,nand-xfer-type = "polled";
+
+		gpmc,device-nand = "true";
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		elm_id = <&elm>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps: tps@2d {
+		reg = <0x2d>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <28 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&tps65910_pins>;
+	};
+
+	at24@50 {
+		compatible = "at24,24c02";
+		pagesize = <8>;
+		reg = <0x50>;
+	};
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_ctrl_mod {
+	status = "okay";
+};
+
+&cppi41dma  {
+	status = "okay";
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vbat>;
+	vcc2-supply = <&vbat>;
+	vcc3-supply = <&vbat>;
+	vcc4-supply = <&vbat>;
+	vcc5-supply = <&vbat>;
+	vcc6-supply = <&vbat>;
+	vcc7-supply = <&vbat>;
+	vccio-supply = <&vbat>;
+
+	ti,en-ck32k-xtal = <1>;
+
+	regulators {
+		vrtc_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator@1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator@2 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1312500>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator@3 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator@5 {
+			regulator-always-on;
+		};
+
+		vdig2_reg: regulator@6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator@7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator@8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator@9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator@10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator@11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator@12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	dual_emac = <1>;
+
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+
+	status = "okay";
+};
+
+&mmc1 {
+	vmmc-supply = <&vmmc_reg>;
+	status = "okay";
+};
+
+&mmc2 {
+	status = "okay";
+	vmmc-supply = <&wl12xx_vmmc>;
+	ti,non-removable;
+	bus-width = <4>;
+	cap-power-off-card;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1835";
+		reg = <2>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&sham {
+	status = "okay";
+};
+
+&aes {
+	status = "okay";
+};
+
+&gpio0 {
+	ti,no-reset-on-init;
+};
diff --git a/sys/gnu/dts/arm/am335x-bone-common.dtsi b/sys/gnu/dts/arm/am335x-bone-common.dtsi
index f3db13d2d90e..0cc150b87b86 100644
--- a/sys/gnu/dts/arm/am335x-bone-common.dtsi
+++ b/sys/gnu/dts/arm/am335x-bone-common.dtsi
@@ -285,8 +285,10 @@
 	};
 };
 
+
+/include/ "tps65217.dtsi"
+
 &tps {
-	compatible = "ti,tps65217";
 	/*
 	 * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
 	 * mode") at poweroff.  Most BeagleBone versions do not support RTC-only
@@ -307,17 +309,12 @@
 	ti,pmic-shutdown-controller;
 
 	regulators {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
 		dcdc1_reg: regulator@0 {
-			reg = <0>;
 			regulator-name = "vdds_dpr";
 			regulator-always-on;
 		};
 
 		dcdc2_reg: regulator@1 {
-			reg = <1>;
 			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 			regulator-name = "vdd_mpu";
 			regulator-min-microvolt = <925000>;
@@ -327,7 +324,6 @@
 		};
 
 		dcdc3_reg: regulator@2 {
-			reg = <2>;
 			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 			regulator-name = "vdd_core";
 			regulator-min-microvolt = <925000>;
@@ -337,25 +333,21 @@
 		};
 
 		ldo1_reg: regulator@3 {
-			reg = <3>;
 			regulator-name = "vio,vrtc,vdds";
 			regulator-always-on;
 		};
 
 		ldo2_reg: regulator@4 {
-			reg = <4>;
 			regulator-name = "vdd_3v3aux";
 			regulator-always-on;
 		};
 
 		ldo3_reg: regulator@5 {
-			reg = <5>;
 			regulator-name = "vdd_1v8";
 			regulator-always-on;
 		};
 
 		ldo4_reg: regulator@6 {
-			reg = <6>;
 			regulator-name = "vdd_3v3a";
 			regulator-always-on;
 		};
diff --git a/sys/gnu/dts/arm/am335x-chiliboard.dts b/sys/gnu/dts/arm/am335x-chiliboard.dts
index 15d47ab28865..2a624b3c9258 100644
--- a/sys/gnu/dts/arm/am335x-chiliboard.dts
+++ b/sys/gnu/dts/arm/am335x-chiliboard.dts
@@ -35,6 +35,59 @@
 };
 
 &am33xx_pinmux {
+	uart0_pins: pinmux_uart0_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
+			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rmii1_txen */
+			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
+			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_ref_clk.rmii_ref_clk */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* mdio_data.mdio_data */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
+			/* mdio_clk.mdio_clk */
+			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
 	usb1_drvvbus: usb1_drvvbus {
 		pinctrl-single,pins = <
 			AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
@@ -61,12 +114,34 @@
 	};
 };
 
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+
+	status = "okay";
+};
+
 &ldo4_reg {
 	regulator-min-microvolt = <3300000>;
 	regulator-max-microvolt = <3300000>;
 };
 
 /* Ethernet */
+&mac {
+	slaves = <1>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+};
+
 &cpsw_emac0 {
 	phy_id = <&davinci_mdio>, <0>;
 	phy-mode = "rmii";
diff --git a/sys/gnu/dts/arm/am335x-chilisom.dtsi b/sys/gnu/dts/arm/am335x-chilisom.dtsi
index fda457b07e15..1d647358f1c1 100644
--- a/sys/gnu/dts/arm/am335x-chilisom.dtsi
+++ b/sys/gnu/dts/arm/am335x-chilisom.dtsi
@@ -7,6 +7,7 @@
  * published by the Free Software Foundation.
  */
 #include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "Grinn AM335x ChiliSOM";
@@ -34,59 +35,6 @@
 		>;
 	};
 
-	uart0_pins: pinmux_uart0_pins {
-		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
-			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
-		>;
-	};
-
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 1 */
-			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
-			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rmii1_txen */
-			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
-			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_ref_clk.rmii_ref_clk */
-		>;
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 1 reset value */
-			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
-		>;
-	};
-
-	davinci_mdio_default: davinci_mdio_default {
-		pinctrl-single,pins = <
-			/* mdio_data.mdio_data */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
-			/* mdio_clk.mdio_clk */
-			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
-		>;
-	};
-
-	davinci_mdio_sleep: davinci_mdio_sleep {
-		pinctrl-single,pins = <
-			/* MDIO reset value */
-			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
-		>;
-	};
-
 	nandflash_pins: nandflash_pins {
 		pinctrl-single,pins = <
 			AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
@@ -108,13 +56,6 @@
 	};
 };
 
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-
-	status = "okay";
-};
-
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
@@ -128,21 +69,16 @@
 
 };
 
-&tps {
-	compatible = "ti,tps65217";
+/include/ "tps65217.dtsi"
 
+&tps {
 	regulators {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
 		dcdc1_reg: regulator@0 {
-			reg = <0>;
 			regulator-name = "vdds_dpr";
 			regulator-always-on;
 		};
 
 		dcdc2_reg: regulator@1 {
-			reg = <1>;
 			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 			regulator-name = "vdd_mpu";
 			regulator-min-microvolt = <925000>;
@@ -152,7 +88,6 @@
 		};
 
 		dcdc3_reg: regulator@2 {
-			reg = <2>;
 			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 			regulator-name = "vdd_core";
 			regulator-min-microvolt = <925000>;
@@ -162,28 +97,24 @@
 		};
 
 		ldo1_reg: regulator@3 {
-			reg = <3>;
 			regulator-name = "vio,vrtc,vdds";
 			regulator-boot-on;
 			regulator-always-on;
 		};
 
 		ldo2_reg: regulator@4 {
-			reg = <4>;
 			regulator-name = "vdd_3v3aux";
 			regulator-boot-on;
 			regulator-always-on;
 		};
 
 		ldo3_reg: regulator@5 {
-			reg = <5>;
 			regulator-name = "vdd_1v8";
 			regulator-boot-on;
 			regulator-always-on;
 		};
 
 		ldo4_reg: regulator@6 {
-			reg = <6>;
 			regulator-name = "vdd_3v3d";
 			regulator-boot-on;
 			regulator-always-on;
@@ -191,20 +122,8 @@
 	};
 };
 
-/* Ethernet MAC */
-&mac {
-	slaves = <1>;
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
-	status = "okay";
-};
-
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_default>;
-	pinctrl-1 = <&davinci_mdio_sleep>;
-	status = "okay";
+&rtc {
+	system-power-controller;
 };
 
 /* NAND Flash */
@@ -218,7 +137,12 @@
 	pinctrl-0 = <&nandflash_pins>;
 	ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 		ti,nand-ecc-opt = "bch8";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <8>;
@@ -237,12 +161,9 @@
 		gpmc,access-ns = <64>;
 		gpmc,rd-cycle-ns = <82>;
 		gpmc,wr-cycle-ns = <82>;
-		gpmc,wait-on-read = "true";
-		gpmc,wait-on-write = "true";
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 	};
diff --git a/sys/gnu/dts/arm/am335x-cm-t335.dts b/sys/gnu/dts/arm/am335x-cm-t335.dts
index 42e9b665582a..817b1dec0683 100644
--- a/sys/gnu/dts/arm/am335x-cm-t335.dts
+++ b/sys/gnu/dts/arm/am335x-cm-t335.dts
@@ -11,6 +11,7 @@
 /dts-v1/;
 
 #include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "CompuLab CM-T335";
@@ -40,12 +41,51 @@
 		regulator-max-microvolt = <3300000>;
 	};
 
+	/* Regulator for WiFi */
+	vwlan_fixed: fixedregulator@2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vwlan_fixed";
+		gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */
+		enable-active-high;
+		regulator-boot-off;
+	};
+
 	backlight {
 		compatible = "pwm-backlight";
 		pwms = <&ecap0 0 50000 0>;
 		brightness-levels = <0 51 53 56 62 75 101 152 255>;
 		default-brightness-level = <8>;
 	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "cm-t335";
+
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Line", "Line In",
+			"Headphone", "Headphone Jack";
+
+		simple-audio-card,routing =
+			"Headphone Jack", "LHPOUT",
+			"Headphone Jack", "RHPOUT",
+			"LLINEIN", "Line In",
+			"RLINEIN", "Line In",
+			"MICIN", "Mic Jack";
+
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&sound_master>;
+		simple-audio-card,frame-master = <&sound_master>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcasp1>;
+		};
+
+		sound_master: simple-audio-card,codec {
+			sound-dai = <&tlv320aic23>;
+			system-clock-frequency = <12000000>;
+		};
+	};
 };
 
 &am33xx_pinmux {
@@ -134,6 +174,24 @@
 		>;
 	};
 
+	dcan0_pins: pinmux_dcan0_pins {
+		pinctrl-single,pins = <
+			/* uart1_ctsn.dcan0_tx */
+			AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)
+			/* uart1_rtsn.dcan0_rx */
+			AM33XX_IOPAD(0x97C, PIN_INPUT | MUX_MODE2)
+		>;
+	};
+
+	dcan1_pins: pinmux_dcan1_pins {
+		pinctrl-single,pins = <
+			/* uart1_rxd.dcan1_tx */
+			AM33XX_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2)
+			/* uart1_txd.dcan1_rx */
+			AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE2)
+		>;
+	};
+
 	ecap0_pins: pinmux_ecap0_pins {
 		pinctrl-single,pins = <
 			/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
@@ -223,6 +281,21 @@
 		>;
 	};
 
+	spi0_pins: pinmux_spi0_pins {
+		pinctrl-single,pins = <
+			/* spi0_sclk.spi0_sclk */
+			AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE0)
+			/* spi0_d0.spi0_d0 */
+			AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
+			/* spi0_d1.spi0_d1 */
+			AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE0)
+			/* spi0_cs0.spi0_cs0 */
+			AM33XX_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0)
+			/* spi0_cs1.spi0_cs1 */
+			AM33XX_IOPAD(0x960, PIN_OUTPUT | MUX_MODE0)
+		>;
+	};
+
 	/* wl1271 bluetooth */
 	bluetooth_pins: pinmux_bluetooth_pins {
 		pinctrl-single,pins = <
@@ -230,6 +303,30 @@
 			AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE7)
 		>;
 	};
+
+	/* TLV320AIC23B codec */
+	mcasp1_pins: pinmux_mcasp1_pins {
+		pinctrl-single,pins = <
+			/* MII1_CRS.mcasp1_aclkx */
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4)
+			/* MII1_RX_ER.mcasp1_fsx */
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4)
+			/* MII1_COL.mcasp1_axr2 */
+			AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE4)
+			/* RMII1_REF_CLK.mcasp1_axr3 */
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4)
+		>;
+	};
+
+	/* wl1271 WiFi */
+	wifi_pins: pinmux_wifi_pins {
+		pinctrl-single,pins = <
+			/* EMU1.gpio3_8 - WiFi IRQ */
+			AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7)
+			/* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */
+			AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7)
+		>;
+	};
 };
 
 &uart0 {
@@ -264,6 +361,13 @@ status = "okay";
 		compatible = "emmicro,em3027";
 		reg = <0x56>;
 	};
+	/* Audio codec */
+	tlv320aic23: codec@1a {
+		compatible = "ti,tlv320aic23";
+		reg = <0x1a>;
+		#sound-dai-cells= <0>;
+		status = "okay";
+	};
 };
 
 &usb {
@@ -302,7 +406,12 @@ status = "okay";
 	pinctrl-0 = <&nandflash_pins>;
 	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: NAND */
 	nand@0,0 {
-		reg = <0 0 0>; /* CS0, offset 0 */
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 		ti,nand-ecc-opt = "bch8";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <8>;
@@ -321,12 +430,9 @@ status = "okay";
 		gpmc,access-ns = <64>;
 		gpmc,rd-cycle-ns = <82>;
 		gpmc,wr-cycle-ns = <82>;
-		gpmc,wait-on-read = "true";
-		gpmc,wait-on-write = "true";
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 		/* MTD partition table */
@@ -394,3 +500,70 @@ status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
 };
+
+&dcan0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan0_pins>;
+};
+
+&dcan1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan1_pins>;
+};
+
+/* Touschscreen and analog digital converter */
+&tscadc {
+	status = "okay";
+	tsc {
+		ti,wires = <4>;
+		ti,x-plate-resistance = <200>;
+		ti,coordinate-readouts = <5>;
+		ti,wire-config = <0x01 0x10 0x23 0x32>;
+		ti,charge-delay = <0x400>;
+	};
+
+	adc {
+		ti,adc-channels = <4 5 6 7>;
+	};
+};
+
+/* CPU audio */
+&mcasp1 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcasp1_pins>;
+
+		op-mode = <0>;          /* MCASP_IIS_MODE */
+		tdm-slots = <2>;
+		/* 16 serializers */
+		num-serializer = <16>;
+		serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+			0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0
+		>;
+		tx-num-evt = <1>;
+		rx-num-evt = <1>;
+
+		#sound-dai-cells= <0>;
+		status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	ti,pindir-d0-out-d1-in = <1>;
+	/* WLS1271 WiFi */
+	wlcore: wlcore@1 {
+		compatible = "ti,wl1271";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_pins>;
+		reg = <1>;
+		spi-max-frequency = <48000000>;
+		clock-xtal;
+		ref-clock-frequency = <38400000>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+		vwlan-supply = <&vwlan_fixed>;
+	};
+};
diff --git a/sys/gnu/dts/arm/am335x-evm.dts b/sys/gnu/dts/arm/am335x-evm.dts
index 0d6a68ce434a..516673bb023d 100644
--- a/sys/gnu/dts/arm/am335x-evm.dts
+++ b/sys/gnu/dts/arm/am335x-evm.dts
@@ -519,7 +519,12 @@
 	pinctrl-0 = <&nandflash_pins_s0>;
 	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 		ti,nand-ecc-opt = "bch8";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <8>;
@@ -538,12 +543,9 @@
 		gpmc,access-ns = <64>;
 		gpmc,rd-cycle-ns = <82>;
 		gpmc,wr-cycle-ns = <82>;
-		gpmc,wait-on-read = "true";
-		gpmc,wait-on-write = "true";
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 		/* MTD partition table */
diff --git a/sys/gnu/dts/arm/am335x-icev2.dts b/sys/gnu/dts/arm/am335x-icev2.dts
new file mode 100644
index 000000000000..e271013e78a6
--- /dev/null
+++ b/sys/gnu/dts/arm/am335x-icev2.dts
@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * AM335x ICE V2 board
+ * http://www.ti.com/tool/tmdsice3359
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+	model = "TI AM3359 ICE-V2";
+	compatible = "ti,am3359-icev2", "ti,am33xx";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	vbat: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+
+	vtt_fixed: fixedregulator@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vtt";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+	};
+
+	leds@0 {
+		compatible = "gpio-leds";
+
+		led@0 {
+			label = "out0";
+			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@1 {
+			label = "out1";
+			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "out2";
+			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "out3";
+			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@4 {
+			label = "out4";
+			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@5 {
+			label = "out5";
+			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@6 {
+			label = "out6";
+			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@7 {
+			label = "out7";
+			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	/* Tricolor status LEDs */
+	leds@1 {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_leds>;
+
+		led@0 {
+			label = "status0:red:cpu0";
+			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "cpu0";
+		};
+
+		led@1 {
+			label = "status0:green:usr";
+			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "status0:yellow:usr";
+			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "status1:red:mmc0";
+			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "mmc0";
+		};
+
+		led@4 {
+			label = "status1:green:usr";
+			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@5 {
+			label = "status1:yellow:usr";
+			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&am33xx_pinmux {
+	user_leds: user_leds {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
+			AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
+			AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
+			AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
+			AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
+			AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
+		>;
+	};
+
+	mmc0_pins_default: mmc0_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
+			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
+			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
+			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
+			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
+			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
+			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
+		>;
+	};
+
+	i2c0_pins_default: i2c0_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
+			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+		>;
+	};
+
+	spi0_pins_default: spi0_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
+			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
+			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
+			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
+		>;
+	};
+
+	uart3_pins_default: uart3_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
+			AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
+		>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_default>;
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps: power-controller@2d {
+		reg = <0x2d>;
+	};
+
+	tpic2810: gpio@60 {
+		compatible = "ti,tpic2810";
+		reg = <0x60>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vbat>;
+	vcc2-supply = <&vbat>;
+	vcc3-supply = <&vbat>;
+	vcc4-supply = <&vbat>;
+	vcc5-supply = <&vbat>;
+	vcc6-supply = <&vbat>;
+	vcc7-supply = <&vbat>;
+	vccio-supply = <&vbat>;
+
+	regulators {
+		vrtc_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator@1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator@2 {
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1326000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator@3 {
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1144000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator@5 {
+			regulator-always-on;
+		};
+
+		vdig2_reg: regulator@6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator@7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator@8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator@9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator@10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator@11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator@12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vmmc_reg>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_default>;
+};
+
+&gpio0 {
+	/* Do not idle the GPIO used for holding the VTT regulator */
+	ti,no-reset-on-init;
+	ti,no-idle-on-init;
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins_default>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/am335x-igep0033.dtsi b/sys/gnu/dts/arm/am335x-igep0033.dtsi
index 54f113546ecc..df63484ef9b3 100644
--- a/sys/gnu/dts/arm/am335x-igep0033.dtsi
+++ b/sys/gnu/dts/arm/am335x-igep0033.dtsi
@@ -11,6 +11,7 @@
 /dts-v1/;
 
 #include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	cpus {
@@ -129,7 +130,12 @@
 	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 		nand-bus-width = <8>;
 		ti,nand-ecc-opt = "bch8";
 		gpmc,device-width = <1>;
@@ -147,12 +153,9 @@
 		gpmc,access-ns = <64>;
 		gpmc,rd-cycle-ns = <82>;
 		gpmc,wr-cycle-ns = <82>;
-		gpmc,wait-on-read = "true";
-		gpmc,wait-on-write = "true";
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 
diff --git a/sys/gnu/dts/arm/am335x-nano.dts b/sys/gnu/dts/arm/am335x-nano.dts
index 77559a1ded60..f313999c503e 100644
--- a/sys/gnu/dts/arm/am335x-nano.dts
+++ b/sys/gnu/dts/arm/am335x-nano.dts
@@ -375,15 +375,11 @@
 	wp-gpios = <&gpio3 18 0>;
 };
 
-&tps {
-	compatible = "ti,tps65217";
+#include "tps65217.dtsi"
 
+&tps {
 	regulators {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
 		dcdc1_reg: regulator@0 {
-			reg = <0>;
 			/* +1.5V voltage with ±4% tolerance */
 			regulator-min-microvolt = <1450000>;
 			regulator-max-microvolt = <1550000>;
@@ -392,7 +388,6 @@
 		};
 
 		dcdc2_reg: regulator@1 {
-			reg = <1>;
 			/* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
 			regulator-name = "vdd_mpu";
 			regulator-min-microvolt = <915000>;
@@ -402,7 +397,6 @@
 		};
 
 		dcdc3_reg: regulator@2 {
-			reg = <2>;
 			/* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
 			regulator-name = "vdd_core";
 			regulator-min-microvolt = <915000>;
@@ -412,7 +406,6 @@
 		};
 
 		ldo1_reg: regulator@3 {
-			reg = <3>;
 			/* +1.8V voltage with ±4% tolerance */
 			regulator-min-microvolt = <1750000>;
 			regulator-max-microvolt = <1870000>;
@@ -421,7 +414,6 @@
 		};
 
 		ldo2_reg: regulator@4 {
-			reg = <4>;
 			/* +3.3V voltage with ±4% tolerance */
 			regulator-min-microvolt = <3175000>;
 			regulator-max-microvolt = <3430000>;
@@ -430,7 +422,6 @@
 		};
 
 		ldo3_reg: regulator@5 {
-			reg = <5>;
 			/* +1.8V voltage with ±4% tolerance */
 			regulator-min-microvolt = <1750000>;
 			regulator-max-microvolt = <1870000>;
@@ -439,7 +430,6 @@
 		};
 
 		ldo4_reg: regulator@6 {
-			reg = <6>;
 			/* +3.3V voltage with ±4% tolerance */
 			regulator-min-microvolt = <3175000>;
 			regulator-max-microvolt = <3430000>;
diff --git a/sys/gnu/dts/arm/am335x-pepper.dts b/sys/gnu/dts/arm/am335x-pepper.dts
index 471a3a70ea1f..8867aaaec54d 100644
--- a/sys/gnu/dts/arm/am335x-pepper.dts
+++ b/sys/gnu/dts/arm/am335x-pepper.dts
@@ -420,9 +420,9 @@
 	vin-supply = <&vbat>;
 };
 
-&tps {
-	compatible = "ti,tps65217";
+/include/ "tps65217.dtsi"
 
+&tps {
 	backlight {
 		isel = <1>; /* ISET1 */
 		fdim = <200>; /* TPS65217_BL_FDIM_200HZ */
@@ -430,17 +430,12 @@
 	};
 
 	regulators {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
 		dcdc1_reg: regulator@0 {
-			reg = <0>;
 			/* VDD_1V8 system supply */
 			regulator-always-on;
 		};
 
 		dcdc2_reg: regulator@1 {
-			reg = <1>;
 			/* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */
 			regulator-name = "vdd_core";
 			regulator-min-microvolt = <925000>;
@@ -450,7 +445,6 @@
 		};
 
 		dcdc3_reg: regulator@2 {
-			reg = <2>;
 			/* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */
 			regulator-name = "vdd_mpu";
 			regulator-min-microvolt = <925000>;
@@ -460,21 +454,18 @@
 		};
 
 		ldo1_reg: regulator@3 {
-			reg = <3>;
 			/* VRTC 1.8V always-on supply */
 			regulator-name = "vrtc,vdds";
 			regulator-always-on;
 		};
 
 		ldo2_reg: regulator@4 {
-			reg = <4>;
 			/* 3.3V rail */
 			regulator-name = "vdd_3v3aux";
 			regulator-always-on;
 		};
 
 		ldo3_reg: regulator@5 {
-			reg = <5>;
 			/* VDD_3V3A 3.3V rail */
 			regulator-name = "vdd_3v3a";
 			regulator-min-microvolt = <3300000>;
@@ -482,7 +473,6 @@
 		};
 
 		ldo4_reg: regulator@6 {
-			reg = <6>;
 			/* VDD_3V3B 3.3V rail */
 			regulator-name = "vdd_3v3b";
 			regulator-always-on;
diff --git a/sys/gnu/dts/arm/am335x-phycore-som.dtsi b/sys/gnu/dts/arm/am335x-phycore-som.dtsi
index c20ae6c6f6c7..86f773165d5c 100644
--- a/sys/gnu/dts/arm/am335x-phycore-som.dtsi
+++ b/sys/gnu/dts/arm/am335x-phycore-som.dtsi
@@ -8,6 +8,7 @@
  */
 
 #include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "Phytec AM335x phyCORE";
@@ -165,7 +166,12 @@
 	pinctrl-0 = <&nandflash_pins>;
 	ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
 	nandflash: nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 		nand-bus-width = <8>;
 		ti,nand-ecc-opt = "bch8";
 		gpmc,device-nand = "true";
@@ -184,13 +190,10 @@
 		gpmc,access-ns = <30>;
 		gpmc,rd-cycle-ns = <30>;
 		gpmc,wr-cycle-ns = <30>;
-		gpmc,wait-on-read = "true";
-		gpmc,wait-on-write = "true";
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <50>;
 		gpmc,cycle2cycle-diffcsen;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <30>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 
diff --git a/sys/gnu/dts/arm/am335x-shc.dts b/sys/gnu/dts/arm/am335x-shc.dts
index 1b5b044fcd91..837d5b80ea1d 100644
--- a/sys/gnu/dts/arm/am335x-shc.dts
+++ b/sys/gnu/dts/arm/am335x-shc.dts
@@ -46,7 +46,7 @@
 			gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_BACK>;
 			debounce-interval = <1000>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		front_button {
@@ -54,7 +54,7 @@
 			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_FRONT>;
 			debounce-interval = <1000>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -138,7 +138,7 @@
 &epwmss1 {
 	status = "okay";
 
-	ehrpwm1: ehrpwm@48302200 {
+	ehrpwm1: pwm@48302200 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&ehrpwm1_pins>;
 		status = "okay";
diff --git a/sys/gnu/dts/arm/am335x-sl50.dts b/sys/gnu/dts/arm/am335x-sl50.dts
index d38edfa53bb9..a6efbe6eda3b 100644
--- a/sys/gnu/dts/arm/am335x-sl50.dts
+++ b/sys/gnu/dts/arm/am335x-sl50.dts
@@ -19,6 +19,10 @@
 		};
 	};
 
+	chosen {
+		stdout-path = &uart0;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
@@ -63,12 +67,28 @@
 		default-brightness-level = <6>;
 	};
 
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* audio external oscillator */
+		tlv320aic3x_mclk: oscillator@0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency  = <24576000>;	/* 24.576MHz */
+		};
+	};
+
 	sound {
 		compatible = "ti,da830-evm-audio";
 		ti,model = "AM335x-SL50";
 		ti,audio-codec = <&audio_codec>;
 		ti,mcasp-controller = <&mcasp0>;
-		ti,codec-clock-rate = <12000000>;
+
+		clocks = <&tlv320aic3x_mclk>;
+		clock-names = "mclk";
+
 		ti,audio-routing =
 			"Headphone Jack",	"HPLOUT",
 			"Headphone Jack",	"HPROUT",
@@ -226,7 +246,7 @@
 			AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_fsx.mcasp0_fsx */
 			AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx.mcasp0_aclkx */
 			AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_axr0.mcasp0_axr0 */
-			AM33XX_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mcasp0_ahclkr.mcasp0_axr2*/
+			AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mcasp0_ahclkr.mcasp0_axr2 */
 		>;
 	};
 
@@ -375,19 +395,16 @@
 	pinctrl-0 = <&uart4_pins>;
 };
 
+#include "tps65217.dtsi"
+
 &tps {
-	compatible = "ti,tps65217";
 	ti,pmic-shutdown-controller;
 
 	interrupt-parent = <&intc>;
 	interrupts = <7>;	/* NNMI */
 
 	regulators {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
 		dcdc1_reg: regulator@0 {
-			reg = <0>;
 			/* VDDS_DDR */
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <1500000>;
@@ -395,7 +412,6 @@
 		};
 
 		dcdc2_reg: regulator@1 {
-			reg = <1>;
 			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 			regulator-name = "vdd_mpu";
 			regulator-min-microvolt = <925000>;
@@ -405,7 +421,6 @@
 		};
 
 		dcdc3_reg: regulator@2 {
-			reg = <2>;
 			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 			regulator-name = "vdd_core";
 			regulator-min-microvolt = <925000>;
@@ -415,7 +430,6 @@
 		};
 
 		ldo1_reg: regulator@3 {
-			reg = <3>;
 			/* VRTC / VIO / VDDS*/
 			regulator-always-on;
 			regulator-min-microvolt = <1800000>;
@@ -423,7 +437,6 @@
 		};
 
 		ldo2_reg: regulator@4 {
-			reg = <4>;
 			/* VDD_3V3AUX */
 			regulator-always-on;
 			regulator-min-microvolt = <3300000>;
@@ -431,7 +444,6 @@
 		};
 
 		ldo3_reg: regulator@5 {
-			reg = <5>;
 			/* VDD_1V8 */
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
@@ -439,7 +451,6 @@
 		};
 
 		ldo4_reg: regulator@6 {
-			reg = <6>;
 			/* VDD_3V3A */
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
diff --git a/sys/gnu/dts/arm/am33xx-clocks.dtsi b/sys/gnu/dts/arm/am33xx-clocks.dtsi
index afb4b3a7bab4..8d8319590cde 100644
--- a/sys/gnu/dts/arm/am33xx-clocks.dtsi
+++ b/sys/gnu/dts/arm/am33xx-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &scm_clocks {
-	sys_clkin_ck: sys_clkin_ck {
+	sys_clkin_ck: sys_clkin_ck@40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -163,7 +163,7 @@
 		clock-frequency = <12000000>;
 	};
 
-	dpll_core_ck: dpll_core_ck {
+	dpll_core_ck: dpll_core_ck@490 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-core-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
@@ -176,7 +176,7 @@
 		clocks = <&dpll_core_ck>;
 	};
 
-	dpll_core_m4_ck: dpll_core_m4_ck {
+	dpll_core_m4_ck: dpll_core_m4_ck@480 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -185,7 +185,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_m5_ck: dpll_core_m5_ck {
+	dpll_core_m5_ck: dpll_core_m5_ck@484 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -194,7 +194,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_m6_ck: dpll_core_m6_ck {
+	dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -203,14 +203,14 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_mpu_ck: dpll_mpu_ck {
+	dpll_mpu_ck: dpll_mpu_ck@488 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0488>, <0x0420>, <0x042c>;
 	};
 
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_mpu_ck>;
@@ -219,14 +219,14 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_ddr_ck: dpll_ddr_ck {
+	dpll_ddr_ck: dpll_ddr_ck@494 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0494>, <0x0434>, <0x0440>;
 	};
 
-	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_ck>;
@@ -243,14 +243,14 @@
 		clock-div = <2>;
 	};
 
-	dpll_disp_ck: dpll_disp_ck {
+	dpll_disp_ck: dpll_disp_ck@498 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x0498>, <0x0448>, <0x0454>;
 	};
 
-	dpll_disp_m2_ck: dpll_disp_m2_ck {
+	dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_disp_ck>;
@@ -260,14 +260,14 @@
 		ti,set-rate-parent;
 	};
 
-	dpll_per_ck: dpll_per_ck {
+	dpll_per_ck: dpll_per_ck@48c {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-j-type-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x048c>, <0x0470>, <0x049c>;
 	};
 
-	dpll_per_m2_ck: dpll_per_m2_ck {
+	dpll_per_m2_ck: dpll_per_m2_ck@4ac {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_ck>;
@@ -292,7 +292,7 @@
 		clock-div = <4>;
 	};
 
-	cefuse_fck: cefuse_fck {
+	cefuse_fck: cefuse_fck@a20 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_clkin_ck>;
@@ -316,7 +316,7 @@
 		clock-div = <732>;
 	};
 
-	clkdiv32k_ick: clkdiv32k_ick {
+	clkdiv32k_ick: clkdiv32k_ick@14c {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ck>;
@@ -332,14 +332,14 @@
 		clock-div = <1>;
 	};
 
-	pruss_ocp_gclk: pruss_ocp_gclk {
+	pruss_ocp_gclk: pruss_ocp_gclk@530 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
 		reg = <0x0530>;
 	};
 
-	mmu_fck: mmu_fck {
+	mmu_fck: mmu_fck@914 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_core_m4_ck>;
@@ -347,56 +347,56 @@
 		reg = <0x0914>;
 	};
 
-	timer1_fck: timer1_fck {
+	timer1_fck: timer1_fck@528 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
 		reg = <0x0528>;
 	};
 
-	timer2_fck: timer2_fck {
+	timer2_fck: timer2_fck@508 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x0508>;
 	};
 
-	timer3_fck: timer3_fck {
+	timer3_fck: timer3_fck@50c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x050c>;
 	};
 
-	timer4_fck: timer4_fck {
+	timer4_fck: timer4_fck@510 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x0510>;
 	};
 
-	timer5_fck: timer5_fck {
+	timer5_fck: timer5_fck@518 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x0518>;
 	};
 
-	timer6_fck: timer6_fck {
+	timer6_fck: timer6_fck@51c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x051c>;
 	};
 
-	timer7_fck: timer7_fck {
+	timer7_fck: timer7_fck@504 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x0504>;
 	};
 
-	usbotg_fck: usbotg_fck {
+	usbotg_fck: usbotg_fck@47c {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_per_ck>;
@@ -412,7 +412,7 @@
 		clock-div = <2>;
 	};
 
-	ieee5000_fck: ieee5000_fck {
+	ieee5000_fck: ieee5000_fck@e4 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_core_m4_div2_ck>;
@@ -420,7 +420,7 @@
 		reg = <0x00e4>;
 	};
 
-	wdt1_fck: wdt1_fck {
+	wdt1_fck: wdt1_fck@538 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
@@ -483,21 +483,21 @@
 		clock-div = <2>;
 	};
 
-	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
 		reg = <0x0520>;
 	};
 
-	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
 		reg = <0x053c>;
 	};
 
-	gpio0_dbclk: gpio0_dbclk {
+	gpio0_dbclk: gpio0_dbclk@408 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&gpio0_dbclk_mux_ck>;
@@ -505,7 +505,7 @@
 		reg = <0x0408>;
 	};
 
-	gpio1_dbclk: gpio1_dbclk {
+	gpio1_dbclk: gpio1_dbclk@ac {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ick>;
@@ -513,7 +513,7 @@
 		reg = <0x00ac>;
 	};
 
-	gpio2_dbclk: gpio2_dbclk {
+	gpio2_dbclk: gpio2_dbclk@b0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ick>;
@@ -521,7 +521,7 @@
 		reg = <0x00b0>;
 	};
 
-	gpio3_dbclk: gpio3_dbclk {
+	gpio3_dbclk: gpio3_dbclk@b4 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ick>;
@@ -529,7 +529,7 @@
 		reg = <0x00b4>;
 	};
 
-	lcd_gclk: lcd_gclk {
+	lcd_gclk: lcd_gclk@534 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@@ -545,7 +545,7 @@
 		clock-div = <2>;
 	};
 
-	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
@@ -553,7 +553,7 @@
 		reg = <0x052c>;
 	};
 
-	gfx_fck_div_ck: gfx_fck_div_ck {
+	gfx_fck_div_ck: gfx_fck_div_ck@52c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&gfx_fclk_clksel_ck>;
@@ -561,14 +561,14 @@
 		ti,max-div = <2>;
 	};
 
-	sysclkout_pre_ck: sysclkout_pre_ck {
+	sysclkout_pre_ck: sysclkout_pre_ck@700 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
 		reg = <0x0700>;
 	};
 
-	clkout2_div_ck: clkout2_div_ck {
+	clkout2_div_ck: clkout2_div_ck@700 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sysclkout_pre_ck>;
@@ -577,7 +577,7 @@
 		reg = <0x0700>;
 	};
 
-	dbg_sysclk_ck: dbg_sysclk_ck {
+	dbg_sysclk_ck: dbg_sysclk_ck@414 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_clkin_ck>;
@@ -585,7 +585,7 @@
 		reg = <0x0414>;
 	};
 
-	dbg_clka_ck: dbg_clka_ck {
+	dbg_clka_ck: dbg_clka_ck@414 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_core_m4_ck>;
@@ -593,7 +593,7 @@
 		reg = <0x0414>;
 	};
 
-	stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
+	stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
@@ -601,7 +601,7 @@
 		reg = <0x0414>;
 	};
 
-	trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
+	trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
@@ -609,7 +609,7 @@
 		reg = <0x0414>;
 	};
 
-	stm_clk_div_ck: stm_clk_div_ck {
+	stm_clk_div_ck: stm_clk_div_ck@414 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&stm_pmd_clock_mux_ck>;
@@ -619,7 +619,7 @@
 		ti,index-power-of-two;
 	};
 
-	trace_clk_div_ck: trace_clk_div_ck {
+	trace_clk_div_ck: trace_clk_div_ck@414 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&trace_pmd_clk_mux_ck>;
@@ -629,7 +629,7 @@
 		ti,index-power-of-two;
 	};
 
-	clkout2_ck: clkout2_ck {
+	clkout2_ck: clkout2_ck@700 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkout2_div_ck>;
diff --git a/sys/gnu/dts/arm/am33xx.dtsi b/sys/gnu/dts/arm/am33xx.dtsi
index 04885f9f959e..52be48bbd2dd 100644
--- a/sys/gnu/dts/arm/am33xx.dtsi
+++ b/sys/gnu/dts/arm/am33xx.dtsi
@@ -439,6 +439,7 @@
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <8>;
 			mbox_wkupm3: wkup_m3 {
+				ti,mbox-send-noirq;
 				ti,mbox-tx = <0 0 0>;
 				ti,mbox-rx = <0 0 3>;
 			};
@@ -687,7 +688,7 @@
 				status = "disabled";
 			};
 
-			ehrpwm0: ehrpwm@48300200 {
+			ehrpwm0: pwm@48300200 {
 				compatible = "ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48300200 0x80>;
@@ -717,7 +718,7 @@
 				status = "disabled";
 			};
 
-			ehrpwm1: ehrpwm@48302200 {
+			ehrpwm1: pwm@48302200 {
 				compatible = "ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48302200 0x80>;
@@ -747,7 +748,7 @@
 				status = "disabled";
 			};
 
-			ehrpwm2: ehrpwm@48304200 {
+			ehrpwm2: pwm@48304200 {
 				compatible = "ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48304200 0x80>;
@@ -859,12 +860,16 @@
 			ti,no-idle-on-init;
 			reg = <0x50000000 0x2000>;
 			interrupts = <100>;
-			dmas = <&edma 52>;
+			dmas = <&edma 52 0>;
 			dma-names = "rxtx";
 			gpmc,num-cs = <7>;
 			gpmc,num-waitpins = <2>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 			status = "disabled";
 		};
 
diff --git a/sys/gnu/dts/arm/am35xx-clocks.dtsi b/sys/gnu/dts/arm/am35xx-clocks.dtsi
index 18cc826e9db5..00dd1f091be5 100644
--- a/sys/gnu/dts/arm/am35xx-clocks.dtsi
+++ b/sys/gnu/dts/arm/am35xx-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &scm_clocks {
-	emac_ick: emac_ick {
+	emac_ick: emac_ick@32c {
 		#clock-cells = <0>;
 		compatible = "ti,am35xx-gate-clock";
 		clocks = <&ipss_ick>;
@@ -16,7 +16,7 @@
 		ti,bit-shift = <1>;
 	};
 
-	emac_fck: emac_fck {
+	emac_fck: emac_fck@32c {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&rmii_ck>;
@@ -24,7 +24,7 @@
 		ti,bit-shift = <9>;
 	};
 
-	vpfe_ick: vpfe_ick {
+	vpfe_ick: vpfe_ick@32c {
 		#clock-cells = <0>;
 		compatible = "ti,am35xx-gate-clock";
 		clocks = <&ipss_ick>;
@@ -32,7 +32,7 @@
 		ti,bit-shift = <2>;
 	};
 
-	vpfe_fck: vpfe_fck {
+	vpfe_fck: vpfe_fck@32c {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&pclk_ck>;
@@ -40,7 +40,7 @@
 		ti,bit-shift = <10>;
 	};
 
-	hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
+	hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
 		#clock-cells = <0>;
 		compatible = "ti,am35xx-gate-clock";
 		clocks = <&ipss_ick>;
@@ -48,7 +48,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
+	hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_ck>;
@@ -56,7 +56,7 @@
 		ti,bit-shift = <8>;
 	};
 
-	hecc_ck: hecc_ck {
+	hecc_ck: hecc_ck@32c {
 		#clock-cells = <0>;
 		compatible = "ti,am35xx-gate-clock";
 		clocks = <&sys_ck>;
@@ -65,7 +65,7 @@
 	};
 };
 &cm_clocks {
-	ipss_ick: ipss_ick {
+	ipss_ick: ipss_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,am35xx-interface-clock";
 		clocks = <&core_l3_ick>;
@@ -85,7 +85,7 @@
 		clock-frequency = <27000000>;
 	};
 
-	uart4_ick_am35xx: uart4_ick_am35xx {
+	uart4_ick_am35xx: uart4_ick_am35xx@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -93,7 +93,7 @@
 		ti,bit-shift = <23>;
 	};
 
-	uart4_fck_am35xx: uart4_fck_am35xx {
+	uart4_fck_am35xx: uart4_fck_am35xx@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_48m_fck>;
diff --git a/sys/gnu/dts/arm/am4372.dtsi b/sys/gnu/dts/arm/am4372.dtsi
index df955ba4dc62..12fcde4d4d2e 100644
--- a/sys/gnu/dts/arm/am4372.dtsi
+++ b/sys/gnu/dts/arm/am4372.dtsi
@@ -73,7 +73,7 @@
 	global_timer: timer@48240200 {
 		compatible = "arm,cortex-a9-global-timer";
 		reg = <0x48240200 0x100>;
-		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
 		interrupt-parent = <&gic>;
 		clocks = <&mpu_periphclk>;
 	};
@@ -81,7 +81,7 @@
 	local_timer: timer@48240600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0x48240600 0x100>;
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
 		interrupt-parent = <&gic>;
 		clocks = <&mpu_periphclk>;
 	};
@@ -207,7 +207,7 @@
 			ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
 				   <&edma_tptc2 0>;
 
-			ti,edma-memcpy-channels = <32 33>;
+			ti,edma-memcpy-channels = <58 59>;
 		};
 
 		edma_tptc0: tptc@49800000 {
@@ -290,6 +290,7 @@
 			ti,mbox-num-users = <4>;
 			ti,mbox-num-fifos = <8>;
 			mbox_wkupm3: wkup_m3 {
+				ti,mbox-send-noirq;
 				ti,mbox-tx = <0 0 0>;
 				ti,mbox-rx = <0 0 3>;
 			};
@@ -678,7 +679,7 @@
 				status = "disabled";
 			};
 
-			ehrpwm0: ehrpwm@48300200 {
+			ehrpwm0: pwm@48300200 {
 				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48300200 0x80>;
@@ -704,7 +705,7 @@
 				status = "disabled";
 			};
 
-			ehrpwm1: ehrpwm@48302200 {
+			ehrpwm1: pwm@48302200 {
 				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48302200 0x80>;
@@ -730,7 +731,7 @@
 				status = "disabled";
 			};
 
-			ehrpwm2: ehrpwm@48304200 {
+			ehrpwm2: pwm@48304200 {
 				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48304200 0x80>;
@@ -748,7 +749,7 @@
 			ti,hwmods = "epwmss3";
 			status = "disabled";
 
-			ehrpwm3: ehrpwm@48306200 {
+			ehrpwm3: pwm@48306200 {
 				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48306200 0x80>;
@@ -766,7 +767,7 @@
 			ti,hwmods = "epwmss4";
 			status = "disabled";
 
-			ehrpwm4: ehrpwm@48308200 {
+			ehrpwm4: pwm@48308200 {
 				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x48308200 0x80>;
@@ -784,7 +785,7 @@
 			ti,hwmods = "epwmss5";
 			status = "disabled";
 
-			ehrpwm5: ehrpwm@4830a200 {
+			ehrpwm5: pwm@4830a200 {
 				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
 				#pwm-cells = <3>;
 				reg = <0x4830a200 0x80>;
@@ -883,7 +884,7 @@
 		gpmc: gpmc@50000000 {
 			compatible = "ti,am3352-gpmc";
 			ti,hwmods = "gpmc";
-			dmas = <&edma 52>;
+			dmas = <&edma 52 0>;
 			dma-names = "rxtx";
 			clocks = <&l3s_gclk>;
 			clock-names = "fck";
@@ -893,21 +894,13 @@
 			gpmc,num-waitpins = <2>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 			status = "disabled";
 		};
 
-		am43xx_control_usb2phy1: control-phy@44e10620 {
-			compatible = "ti,control-phy-usb2-am437";
-			reg = <0x44e10620 0x4>;
-			reg-names = "power";
-		};
-
-		am43xx_control_usb2phy2: control-phy@0x44e10628 {
-			compatible = "ti,control-phy-usb2-am437";
-			reg = <0x44e10628 0x4>;
-			reg-names = "power";
-		};
-
 		ocp2scp0: ocp2scp@483a8000 {
 			compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
 			#address-cells = <1>;
@@ -918,7 +911,7 @@
 			usb2_phy1: phy@483a8000 {
 				compatible = "ti,am437x-usb2";
 				reg = <0x483a8000 0x8000>;
-				ctrl-module = <&am43xx_control_usb2phy1>;
+				syscon-phy-power = <&scm_conf 0x620>;
 				clocks = <&usb_phy0_always_on_clk32k>,
 					 <&usb_otg_ss0_refclk960m>;
 				clock-names = "wkupclk", "refclk";
@@ -937,7 +930,7 @@
 			usb2_phy2: phy@483e8000 {
 				compatible = "ti,am437x-usb2";
 				reg = <0x483e8000 0x8000>;
-				ctrl-module = <&am43xx_control_usb2phy2>;
+				syscon-phy-power = <&scm_conf 0x628>;
 				clocks = <&usb_phy1_always_on_clk32k>,
 					 <&usb_otg_ss1_refclk960m>;
 				clock-names = "wkupclk", "refclk";
diff --git a/sys/gnu/dts/arm/am437x-cm-t43.dts b/sys/gnu/dts/arm/am437x-cm-t43.dts
index 8677f4cce9e9..9551c4713173 100644
--- a/sys/gnu/dts/arm/am437x-cm-t43.dts
+++ b/sys/gnu/dts/arm/am437x-cm-t43.dts
@@ -146,7 +146,11 @@
 	pinctrl-0 = <&nand_flash_x8>;
 	ranges = <0 0 0x08000000 0x1000000>;
 	nand@0,0 {
-		reg = <0 0 0>;
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>;		/* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		ti,nand-ecc-opt = "bch8";
 		ti,elm-id = <&elm>;
 
@@ -166,17 +170,12 @@
 		gpmc,access-ns = <64>;
 		gpmc,rd-cycle-ns = <82>;
 		gpmc,wr-cycle-ns = <82>;
-		gpmc,wait-on-read = "true";
-		gpmc,wait-on-write = "true";
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 
-		gpmc,wait-pin = <0>;
-
 		#address-cells = <1>;
 		#size-cells = <1>;
 		/* MTD partition table */
diff --git a/sys/gnu/dts/arm/am437x-gp-evm.dts b/sys/gnu/dts/arm/am437x-gp-evm.dts
index 64d43325bcbc..5bcd3aa025bc 100644
--- a/sys/gnu/dts/arm/am437x-gp-evm.dts
+++ b/sys/gnu/dts/arm/am437x-gp-evm.dts
@@ -119,7 +119,7 @@
 		clock-frequency = <32768>;
 	};
 
-	sound0: sound@0 {
+	sound0: sound0 {
 		compatible = "simple-audio-card";
 		simple-audio-card,name = "AM437x-GP-EVM";
 		simple-audio-card,widgets =
@@ -590,8 +590,6 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pixcir_ts_pins>;
 		reg = <0x5c>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <22 0>;
 
 		attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 
@@ -599,7 +597,7 @@
 		 * 0x264 represents the offset of padconf register of
 		 * gpio3_22 from am43xx_pinmux base.
 		 */
-		interrupts-extended = <&gpio3 22 IRQ_TYPE_NONE>,
+		interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
 				      <&am43xx_pinmux 0x264>;
 		interrupt-names = "tsc", "wakeup";
 
@@ -812,9 +810,14 @@
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&nand_flash_x8>;
-	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
+	ranges = <0 0 0x08000000 0x01000000>;	/* CS0 space. Min partition = 16MB */
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>;		/* device IO registers */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;	/* gpmc_wait0 */
 		ti,nand-ecc-opt = "bch16";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <8>;
@@ -833,11 +836,9 @@
 		gpmc,access-ns = <30>;
 		gpmc,rd-cycle-ns = <40>;
 		gpmc,wr-cycle-ns = <40>;
-		gpmc,wait-pin = <0>;
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 		/* MTD partition table */
diff --git a/sys/gnu/dts/arm/am437x-sk-evm.dts b/sys/gnu/dts/arm/am437x-sk-evm.dts
index d82dd6e3f9b1..5687d6b4da60 100644
--- a/sys/gnu/dts/arm/am437x-sk-evm.dts
+++ b/sys/gnu/dts/arm/am437x-sk-evm.dts
@@ -418,7 +418,7 @@
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
-	clock-frequency = <400000>;
+	clock-frequency = <100000>;
 
 	tps@24 {
 		compatible = "ti,tps65218";
diff --git a/sys/gnu/dts/arm/am43x-epos-evm.dts b/sys/gnu/dts/arm/am43x-epos-evm.dts
index 746fd2b17958..3549b8c9ac49 100644
--- a/sys/gnu/dts/arm/am43x-epos-evm.dts
+++ b/sys/gnu/dts/arm/am43x-epos-evm.dts
@@ -18,7 +18,7 @@
 
 / {
 	model = "TI AM43x EPOS EVM";
-	compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
+	compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
 
 	aliases {
 		display0 = &lcd0;
@@ -107,7 +107,7 @@
 		default-brightness-level = <8>;
 	};
 
-	sound0: sound@0 {
+	sound0: sound0 {
 		compatible = "simple-audio-card";
 		simple-audio-card,name = "AM43-EPOS-EVM";
 		simple-audio-card,widgets =
@@ -491,7 +491,7 @@
 		pinctrl-0 = <&pixcir_ts_pins>;
 		reg = <0x5c>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <17 0>;
+		interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
 
 		attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
 
@@ -561,9 +561,14 @@
 	status = "okay";	/* Disable QSPI when enabling GPMC (NAND) */
 	pinctrl-names = "default";
 	pinctrl-0 = <&nand_flash_x8>;
-	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
+	ranges = <0 0 0x08000000 0x01000000>;	/* CS0 space. Min partition = 16MB */
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;	/* gpmc_wait0 */
 		ti,nand-ecc-opt = "bch16";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <8>;
@@ -582,11 +587,9 @@
 		gpmc,access-ns = <30>; /* tCEA + 4*/
 		gpmc,rd-cycle-ns = <40>;
 		gpmc,wr-cycle-ns = <40>;
-		gpmc,wait-pin = <0>;
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 		/* MTD partition table */
@@ -792,3 +795,8 @@
 	tx-num-evt = <32>;
 	rx-num-evt = <32>;
 };
+
+&synctimer_32kclk {
+	assigned-clocks = <&mux_synctimer32k_ck>;
+	assigned-clock-parents = <&clkdiv32k_ick>;
+};
diff --git a/sys/gnu/dts/arm/am43xx-clocks.dtsi b/sys/gnu/dts/arm/am43xx-clocks.dtsi
index a38af2bfbfcf..7630ba1d89e4 100644
--- a/sys/gnu/dts/arm/am43xx-clocks.dtsi
+++ b/sys/gnu/dts/arm/am43xx-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &scm_clocks {
-	sys_clkin_ck: sys_clkin_ck {
+	sys_clkin_ck: sys_clkin_ck@40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
@@ -16,7 +16,7 @@
 		reg = <0x0040>;
 	};
 
-	crystal_freq_sel_ck: crystal_freq_sel_ck {
+	crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -104,7 +104,7 @@
 		clock-div = <1>;
 	};
 
-	ehrpwm0_tbclk: ehrpwm0_tbclk {
+	ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4ls_gclk>;
@@ -112,7 +112,7 @@
 		reg = <0x0664>;
 	};
 
-	ehrpwm1_tbclk: ehrpwm1_tbclk {
+	ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4ls_gclk>;
@@ -120,7 +120,7 @@
 		reg = <0x0664>;
 	};
 
-	ehrpwm2_tbclk: ehrpwm2_tbclk {
+	ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4ls_gclk>;
@@ -128,7 +128,7 @@
 		reg = <0x0664>;
 	};
 
-	ehrpwm3_tbclk: ehrpwm3_tbclk {
+	ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4ls_gclk>;
@@ -136,7 +136,7 @@
 		reg = <0x0664>;
 	};
 
-	ehrpwm4_tbclk: ehrpwm4_tbclk {
+	ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4ls_gclk>;
@@ -144,7 +144,7 @@
 		reg = <0x0664>;
 	};
 
-	ehrpwm5_tbclk: ehrpwm5_tbclk {
+	ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4ls_gclk>;
@@ -195,7 +195,7 @@
 		clock-frequency = <26000000>;
 	};
 
-	dpll_core_ck: dpll_core_ck {
+	dpll_core_ck: dpll_core_ck@2d20 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-core-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
@@ -208,7 +208,7 @@
 		clocks = <&dpll_core_ck>;
 	};
 
-	dpll_core_m4_ck: dpll_core_m4_ck {
+	dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -219,7 +219,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_m5_ck: dpll_core_m5_ck {
+	dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -230,7 +230,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_m6_ck: dpll_core_m6_ck {
+	dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -241,14 +241,14 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_mpu_ck: dpll_mpu_ck {
+	dpll_mpu_ck: dpll_mpu_ck@2d60 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x2d60>, <0x2d64>, <0x2d6c>;
 	};
 
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_mpu_ck>;
@@ -267,14 +267,14 @@
 		clock-div = <2>;
 	};
 
-	dpll_ddr_ck: dpll_ddr_ck {
+	dpll_ddr_ck: dpll_ddr_ck@2da0 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x2da0>, <0x2da4>, <0x2dac>;
 	};
 
-	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_ck>;
@@ -285,14 +285,14 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_disp_ck: dpll_disp_ck {
+	dpll_disp_ck: dpll_disp_ck@2e20 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x2e20>, <0x2e24>, <0x2e2c>;
 	};
 
-	dpll_disp_m2_ck: dpll_disp_m2_ck {
+	dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_disp_ck>;
@@ -304,14 +304,14 @@
 		ti,set-rate-parent;
 	};
 
-	dpll_per_ck: dpll_per_ck {
+	dpll_per_ck: dpll_per_ck@2de0 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-j-type-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x2de0>, <0x2de4>, <0x2dec>;
 	};
 
-	dpll_per_m2_ck: dpll_per_m2_ck {
+	dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_ck>;
@@ -354,7 +354,7 @@
 		clock-div = <732>;
 	};
 
-	clkdiv32k_ick: clkdiv32k_ick {
+	clkdiv32k_ick: clkdiv32k_ick@2a38 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ck>;
@@ -370,7 +370,7 @@
 		clock-div = <1>;
 	};
 
-	pruss_ocp_gclk: pruss_ocp_gclk {
+	pruss_ocp_gclk: pruss_ocp_gclk@4248 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
@@ -383,56 +383,56 @@
 		clock-frequency = <32768>;
 	};
 
-	timer1_fck: timer1_fck {
+	timer1_fck: timer1_fck@4200 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 		reg = <0x4200>;
 	};
 
-	timer2_fck: timer2_fck {
+	timer2_fck: timer2_fck@4204 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x4204>;
 	};
 
-	timer3_fck: timer3_fck {
+	timer3_fck: timer3_fck@4208 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x4208>;
 	};
 
-	timer4_fck: timer4_fck {
+	timer4_fck: timer4_fck@420c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x420c>;
 	};
 
-	timer5_fck: timer5_fck {
+	timer5_fck: timer5_fck@4210 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x4210>;
 	};
 
-	timer6_fck: timer6_fck {
+	timer6_fck: timer6_fck@4214 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x4214>;
 	};
 
-	timer7_fck: timer7_fck {
+	timer7_fck: timer7_fck@4218 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
 		reg = <0x4218>;
 	};
 
-	wdt1_fck: wdt1_fck {
+	wdt1_fck: wdt1_fck@422c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
@@ -487,14 +487,14 @@
 		clock-div = <2>;
 	};
 
-	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
 		reg = <0x4238>;
 	};
 
-	dpll_clksel_mac_clk: dpll_clksel_mac_clk {
+	dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_m5_ck>;
@@ -509,14 +509,14 @@
 		clock-frequency = <32768>;
 	};
 
-	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
 		reg = <0x4240>;
 	};
 
-	gpio0_dbclk: gpio0_dbclk {
+	gpio0_dbclk: gpio0_dbclk@2b68 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&gpio0_dbclk_mux_ck>;
@@ -524,7 +524,7 @@
 		reg = <0x2b68>;
 	};
 
-	gpio1_dbclk: gpio1_dbclk {
+	gpio1_dbclk: gpio1_dbclk@8c78 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ick>;
@@ -532,7 +532,7 @@
 		reg = <0x8c78>;
 	};
 
-	gpio2_dbclk: gpio2_dbclk {
+	gpio2_dbclk: gpio2_dbclk@8c80 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ick>;
@@ -540,7 +540,7 @@
 		reg = <0x8c80>;
 	};
 
-	gpio3_dbclk: gpio3_dbclk {
+	gpio3_dbclk: gpio3_dbclk@8c88 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ick>;
@@ -548,7 +548,7 @@
 		reg = <0x8c88>;
 	};
 
-	gpio4_dbclk: gpio4_dbclk {
+	gpio4_dbclk: gpio4_dbclk@8c90 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ick>;
@@ -556,7 +556,7 @@
 		reg = <0x8c90>;
 	};
 
-	gpio5_dbclk: gpio5_dbclk {
+	gpio5_dbclk: gpio5_dbclk@8c98 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkdiv32k_ick>;
@@ -572,7 +572,7 @@
 		clock-div = <2>;
 	};
 
-	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
@@ -580,7 +580,7 @@
 		reg = <0x423c>;
 	};
 
-	gfx_fck_div_ck: gfx_fck_div_ck {
+	gfx_fck_div_ck: gfx_fck_div_ck@423c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&gfx_fclk_clksel_ck>;
@@ -588,7 +588,7 @@
 		ti,max-div = <2>;
 	};
 
-	disp_clk: disp_clk {
+	disp_clk: disp_clk@4244 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@@ -596,14 +596,14 @@
 		ti,set-rate-parent;
 	};
 
-	dpll_extdev_ck: dpll_extdev_ck {
+	dpll_extdev_ck: dpll_extdev_ck@2e60 {
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
 		reg = <0x2e60>, <0x2e64>, <0x2e6c>;
 	};
 
-	dpll_extdev_m2_ck: dpll_extdev_m2_ck {
+	dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_extdev_ck>;
@@ -614,14 +614,14 @@
 		ti,invert-autoidle-bit;
 	};
 
-	mux_synctimer32k_ck: mux_synctimer32k_ck {
+	mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
 		reg = <0x4230>;
 	};
 
-	synctimer_32kclk: synctimer_32kclk {
+	synctimer_32kclk: synctimer_32kclk@2a30 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&mux_synctimer32k_ck>;
@@ -629,28 +629,28 @@
 		reg = <0x2a30>;
 	};
 
-	timer8_fck: timer8_fck {
+	timer8_fck: timer8_fck@421c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 		reg = <0x421c>;
 	};
 
-	timer9_fck: timer9_fck {
+	timer9_fck: timer9_fck@4220 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 		reg = <0x4220>;
 	};
 
-	timer10_fck: timer10_fck {
+	timer10_fck: timer10_fck@4224 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
 		reg = <0x4224>;
 	};
 
-	timer11_fck: timer11_fck {
+	timer11_fck: timer11_fck@4228 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
@@ -679,7 +679,7 @@
 		clocks = <&dpll_ddr_ck>;
 	};
 
-	dpll_ddr_m4_ck: dpll_ddr_m4_ck {
+	dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_x2_ck>;
@@ -690,7 +690,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+	dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
 		#clock-cells = <0>;
 		compatible = "ti,fixed-factor-clock";
 		clocks = <&dpll_per_ck>;
@@ -701,7 +701,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dll_aging_clk_div: dll_aging_clk_div {
+	dll_aging_clk_div: dll_aging_clk_div@4250 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin_ck>;
@@ -733,14 +733,14 @@
 		clock-div = <2>;
 	};
 
-	usbphy_32khz_clkmux: usbphy_32khz_clkmux {
+	usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
 		reg = <0x4260>;
 	};
 
-	usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
+	usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&usbphy_32khz_clkmux>;
@@ -748,7 +748,7 @@
 		reg = <0x2a40>;
 	};
 
-	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&usbphy_32khz_clkmux>;
@@ -756,7 +756,7 @@
 		reg = <0x2a48>;
 	};
 
-	usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
+	usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_per_clkdcoldo>;
@@ -764,11 +764,65 @@
 		reg = <0x8a60>;
 	};
 
-	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_per_clkdcoldo>;
 		ti,bit-shift = <8>;
 		reg = <0x8a68>;
 	};
+
+	clkout1_osc_div_ck: clkout1_osc_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin_ck>;
+		ti,bit-shift = <20>;
+		ti,max-div = <4>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_mux_ck: clkout1_src2_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
+			 <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
+			 <&dpll_mpu_m2_ck>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_mux_ck>;
+		ti,bit-shift = <4>;
+		ti,max-div = <8>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_pre_div_ck>;
+		ti,bit-shift = <8>;
+		ti,max-div = <32>;
+		ti,index-power-of-two;
+		reg = <0x4100>;
+	};
+
+	clkout1_mux_ck: clkout1_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
+			 <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
+		ti,bit-shift = <16>;
+		reg = <0x4100>;
+	};
+
+	clkout1_ck: clkout1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkout1_mux_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x4100>;
+	};
 };
diff --git a/sys/gnu/dts/arm/am572x-idk.dts b/sys/gnu/dts/arm/am572x-idk.dts
new file mode 100644
index 000000000000..e3acb99703e1
--- /dev/null
+++ b/sys/gnu/dts/arm/am572x-idk.dts
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "dra74x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-idk-common.dtsi"
+
+/ {
+	model = "TI AM5728 IDK";
+	compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
+		     "ti,dra7";
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	extcon_usb2: extcon_usb2 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+	};
+
+	status-leds {
+		compatible = "gpio-leds";
+		cpu0-led {
+			label = "status0:red:cpu0";
+			gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "cpu0";
+		};
+
+		usr0-led {
+			label = "status0:green:usr";
+			gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		heartbeat-led {
+			label = "status0:blue:heartbeat";
+			gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "heartbeat";
+		};
+
+		cpu1-led {
+			label = "status1:red:cpu1";
+			gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "cpu1";
+		};
+
+		usr1-led {
+			label = "status1:green:usr";
+			gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		mmc0-led {
+			label = "status1:blue:mmc0";
+			gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "mmc0";
+		};
+	};
+};
+
+&omap_dwc3_2 {
+	extcon = <&extcon_usb2>;
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&v3_3d>;
+	vmmc_aux-supply = <&ldo1_reg>;
+	bus-width = <4>;
+	cd-gpios = <&gpio6 27 0>; /* gpio 219 */
+};
diff --git a/sys/gnu/dts/arm/am57xx-beagle-x15.dts b/sys/gnu/dts/arm/am57xx-beagle-x15.dts
index 36c0fa6c362a..81d6c3033b51 100644
--- a/sys/gnu/dts/arm/am57xx-beagle-x15.dts
+++ b/sys/gnu/dts/arm/am57xx-beagle-x15.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "dra74x.dtsi"
+#include "am57xx-commercial-grade.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
@@ -24,7 +25,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x80000000>;
+		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
 
 	vdd_3v3: fixedregulator-vdd_3v3 {
@@ -99,13 +100,6 @@
 		#cooling-cells = <2>;
 	};
 
-	extcon_usb1: extcon_usb1 {
-		compatible = "linux,extcon-usb-gpio";
-		id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&extcon_usb1_pins>;
-	};
-
 	hdmi0: connector {
 		compatible = "hdmi-connector";
 		label = "hdmi";
@@ -151,7 +145,7 @@
 		};
 	};
 
-	sound0: sound@0 {
+	sound0: sound0 {
 		compatible = "simple-audio-card";
 		simple-audio-card,name = "BeagleBoard-X15";
 		simple-audio-card,widgets =
@@ -347,12 +341,6 @@
 		>;
 	};
 
-	extcon_usb1_pins: extcon_usb1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
-		>;
-	};
-
 	tpd12s015_pins: pinmux_tpd12s015_pins {
 		pinctrl-single,pins = <
 			DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14)		/* gpio7_10 CT_CP_HPD */
@@ -438,7 +426,7 @@
 					/* VDD_DSPEVE, VDD_IVA, VDD_GPU */
 					regulator-name = "smps45";
 					regulator-min-microvolt = < 850000>;
-					regulator-max-microvolt = <1150000>;
+					regulator-max-microvolt = <1250000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};
@@ -447,7 +435,7 @@
 					/* VDD_CORE */
 					regulator-name = "smps6";
 					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1030000>;
+					regulator-max-microvolt = <1150000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};
@@ -560,8 +548,7 @@
 		extcon_usb2: tps659038_usb {
 			compatible = "ti,palmas-usb-vid";
 			ti,enable-vbus-detection;
-			ti,enable-id-detection;
-			id-gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>;
+			vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 		};
 
 	};
@@ -583,6 +570,9 @@
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&clkout2_pins_default>;
 		pinctrl-1 = <&clkout2_pins_sleep>;
+		assigned-clocks = <&clkoutmux2_clk_mux>;
+		assigned-clock-parents = <&sys_clk2_dclk_div>;
+
 		status = "okay";
 		adc-settle-ms = <40>;
 
@@ -591,6 +581,11 @@
 		DRVDD-supply = <&vdd_3v3>;
 		DVDD-supply = <&aic_dvdd>;
 	};
+
+	eeprom: eeprom@50 {
+		compatible = "at,24c32";
+		reg = <0x50>;
+	};
 };
 
 &i2c3 {
@@ -700,10 +695,6 @@
 	pinctrl-0 = <&usb1_pins>;
 };
 
-&omap_dwc3_1 {
-	extcon = <&extcon_usb1>;
-};
-
 &omap_dwc3_2 {
 	extcon = <&extcon_usb2>;
 };
@@ -796,6 +787,8 @@
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&mcasp3_pins_default>;
 	pinctrl-1 = <&mcasp3_pins_sleep>;
+	assigned-clocks = <&mcasp3_ahclkx_mux>;
+	assigned-clock-parents = <&sys_clkin2>;
 	status = "okay";
 
 	op-mode = <0>;	/* MCASP_IIS_MODE */
@@ -804,6 +797,8 @@
 	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
diff --git a/sys/gnu/dts/arm/am57xx-cl-som-am57x.dts b/sys/gnu/dts/arm/am57xx-cl-som-am57x.dts
index c53882643ae9..378b142ef88c 100644
--- a/sys/gnu/dts/arm/am57xx-cl-som-am57x.dts
+++ b/sys/gnu/dts/arm/am57xx-cl-som-am57x.dts
@@ -21,7 +21,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x20000000>; /* 512 MB - minimal configuration */
+		reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
 	};
 
 	leds {
@@ -51,7 +51,7 @@
 		regulator-max-microvolt = <3300000>;
 	};
 
-	sound0: sound@0 {
+	sound0: sound0 {
 		compatible = "simple-audio-card";
 		simple-audio-card,name = "CL-SOM-AM57x-Sound-Card";
 		simple-audio-card,format = "i2s";
@@ -167,7 +167,7 @@
 			DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
 			DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
 			DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
-			DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLUP | MUX_MODE3)	/* vin2a_d23.rgmii1_rd0 */
+			DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
 		>;
 	};
 
@@ -492,14 +492,14 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&qspi1_pins>;
 
-	spi-max-frequency = <20000000>;
+	spi-max-frequency = <48000000>;
 
 	spi_flash: spi_flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "spansion,m25p80", "jedec,spi-nor";
 		reg = <0>;				/* CS0 */
-		spi-max-frequency = <20000000>;
+		spi-max-frequency = <48000000>;
 
 		partition@0 {
 			label = "uboot";
@@ -545,7 +545,7 @@
 		ti,debounce-tol = /bits/ 16 <10>;
 		ti,debounce-rep = /bits/ 16 <1>;
 
-		linux,wakeup;
+		wakeup-source;
 	};
 };
 
@@ -559,13 +559,13 @@
 
 &cpsw_emac0 {
 	phy_id = <&davinci_mdio>, <0>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-txid";
 	dual_emac_res_vlan = <0>;
 };
 
 &cpsw_emac1 {
 	phy_id = <&davinci_mdio>, <1>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-txid";
 	dual_emac_res_vlan = <1>;
 };
 
@@ -588,7 +588,7 @@
 };
 
 &usb2 {
-	dr_mode = "peripheral";
+	dr_mode = "host";
 };
 
 &mcasp3 {
diff --git a/sys/gnu/dts/arm/am57xx-commercial-grade.dtsi b/sys/gnu/dts/arm/am57xx-commercial-grade.dtsi
new file mode 100644
index 000000000000..c183654464e9
--- /dev/null
+++ b/sys/gnu/dts/arm/am57xx-commercial-grade.dtsi
@@ -0,0 +1,23 @@
+&cpu_alert0 {
+	temperature = <80000>; /* milliCelsius */
+};
+
+&cpu_crit {
+	temperature = <90000>; /* milliCelsius */
+};
+
+&gpu_crit {
+	temperature = <90000>; /* milliCelsius */
+};
+
+&core_crit {
+	temperature = <90000>; /* milliCelsius */
+};
+
+&dspeve_crit {
+	temperature = <90000>; /* milliCelsius */
+};
+
+&iva_crit {
+	temperature = <90000>; /* milliCelsius */
+};
diff --git a/sys/gnu/dts/arm/am57xx-idk-common.dtsi b/sys/gnu/dts/arm/am57xx-idk-common.dtsi
new file mode 100644
index 000000000000..0e63b9dff6e7
--- /dev/null
+++ b/sys/gnu/dts/arm/am57xx-idk-common.dtsi
@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am57xx-industrial-grade.dtsi"
+
+/ {
+	aliases {
+		rtc0 = &tps659038_rtc;
+		rtc1 = &rtc;
+	};
+
+	vmain: fixedregulator-vmain {
+		compatible = "regulator-fixed";
+		regulator-name = "VMAIN";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	v3_3d: fixedregulator-v3_3d {
+		compatible = "regulator-fixed";
+		regulator-name = "V3_3D";
+		vin-supply = <&smps9_reg>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vtt_fixed: fixedregulator-vtt {
+		/* TPS51200 */
+		compatible = "regulator-fixed";
+		regulator-name = "vtt_fixed";
+		vin-supply = <&v3_3d>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps659038: tps659038@58 {
+		compatible = "ti,tps659038";
+		reg = <0x58>;
+		interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH
+			       &dra7_pmx_core 0x418>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		ti,system-power-controller;
+
+		tps659038_pmic {
+			compatible = "ti,tps659038-pmic";
+
+			smps12-in-supply = <&vmain>;
+			smps3-in-supply = <&vmain>;
+			smps45-in-supply = <&vmain>;
+			smps6-in-supply = <&vmain>;
+			smps7-in-supply = <&vmain>;
+			smps8-in-supply = <&vmain>;
+			smps9-in-supply = <&vmain>;
+			ldo1-in-supply = <&vmain>;
+			ldo2-in-supply = <&vmain>;
+			ldo3-in-supply = <&vmain>;
+			ldo4-in-supply = <&vmain>;
+			ldo9-in-supply = <&vmain>;
+			ldoln-in-supply = <&vmain>;
+			ldousb-in-supply = <&vmain>;
+			ldortc-in-supply = <&vmain>;
+
+			regulators {
+				smps12_reg: smps12 {
+					/* VDD_MPU */
+					regulator-name = "smps12";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps3_reg: smps3 {
+					/* VDD_DDR EMIF1 EMIF2 */
+					regulator-name = "smps3";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps45_reg: smps45 {
+					/* VDD_DSPEVE on AM572 */
+					/* VDD_IVA + VDD_DSP on AM571 */
+					regulator-name = "smps45";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps6_reg: smps6 {
+					/* VDD_GPU */
+					regulator-name = "smps6";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps7_reg: smps7 {
+					/* VDD_CORE */
+					regulator-name = "smps7";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1150000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps8_reg: smps8 {
+					/* 5728 - VDD_IVAHD */
+					/* 5718 - N.C. test point */
+					regulator-name = "smps8";
+				};
+
+				smps9_reg: smps9 {
+					/* VDD_3_3D */
+					regulator-name = "smps9";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo1_reg: ldo1 {
+					/* VDDSHV8 - VSDMMC  */
+					/* NOTE: on rev 1.3a, data supply */
+					regulator-name = "ldo1";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo2_reg: ldo2 {
+					/* VDDSH18V */
+					regulator-name = "ldo2";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo3_reg: ldo3 {
+					/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
+					regulator-name = "ldo3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo4_reg: ldo4 {
+					/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
+					regulator-name = "ldo4";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				/* LDO5-8 unused */
+
+				ldo9_reg: ldo9 {
+					/* VDD_RTC  */
+					regulator-name = "ldo9";
+					regulator-min-microvolt = <840000>;
+					regulator-max-microvolt = <1160000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldoln_reg: ldoln {
+					/* VDDA_1V8_PLL */
+					regulator-name = "ldoln";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldousb_reg: ldousb {
+					/* VDDA_3V_USB: VDDA_USBHS33 */
+					regulator-name = "ldousb";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldortc_reg: ldortc {
+					/* VDDA_RTC  */
+					regulator-name = "ldortc";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				regen1: regen1 {
+					/* VDD_3V3_ON */
+					regulator-name = "regen1";
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				regen2: regen2 {
+					/* Needed for PMIC internal resource */
+					regulator-name = "regen2";
+					regulator-boot-on;
+					regulator-always-on;
+				};
+			};
+		};
+
+		tps659038_rtc: tps659038_rtc {
+			compatible = "ti,palmas-rtc";
+			interrupt-parent = <&tps659038>;
+			interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+			wakeup-source;
+		};
+
+		tps659038_pwr_button: tps659038_pwr_button {
+			compatible = "ti,palmas-pwrbutton";
+			interrupt-parent = <&tps659038>;
+			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+			wakeup-source;
+			ti,palmas-long-press-seconds = <12>;
+		};
+
+		tps659038_gpio: tps659038_gpio {
+			compatible = "ti,palmas-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};
+
+&uart3 {
+	status = "okay";
+	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
+			       &dra7_pmx_core 0x248>;
+};
+
+&rtc {
+	status = "okay";
+	ext-clk-src;
+};
+
+&mac {
+	status = "okay";
+	dual_emac;
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "rgmii";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rgmii";
+	dual_emac_res_vlan = <2>;
+};
+
+&usb2_phy1 {
+	phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+	phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+	dr_mode = "host";
+};
+
+&usb2 {
+	dr_mode = "otg";
+};
+
+&mmc2 {
+	status = "okay";
+	vmmc-supply = <&v3_3d>;
+	bus-width = <8>;
+	ti,non-removable;
+	max-frequency = <96000000>;
+};
diff --git a/sys/gnu/dts/arm/am57xx-industrial-grade.dtsi b/sys/gnu/dts/arm/am57xx-industrial-grade.dtsi
new file mode 100644
index 000000000000..70c8c4ba1933
--- /dev/null
+++ b/sys/gnu/dts/arm/am57xx-industrial-grade.dtsi
@@ -0,0 +1,23 @@
+&cpu_alert0 {
+	temperature = <90000>; /* milliCelsius */
+};
+
+&cpu_crit {
+	temperature = <105000>; /* milliCelsius */
+};
+
+&gpu_crit {
+	temperature = <105000>; /* milliCelsius */
+};
+
+&core_crit {
+	temperature = <105000>; /* milliCelsius */
+};
+
+&dspeve_crit {
+	temperature = <105000>; /* milliCelsius */
+};
+
+&iva_crit {
+	temperature = <105000>; /* milliCelsius */
+};
diff --git a/sys/gnu/dts/arm/am57xx-sbc-am57x.dts b/sys/gnu/dts/arm/am57xx-sbc-am57x.dts
index 77bb8e17401a..988e99632d49 100644
--- a/sys/gnu/dts/arm/am57xx-sbc-am57x.dts
+++ b/sys/gnu/dts/arm/am57xx-sbc-am57x.dts
@@ -25,8 +25,8 @@
 &dra7_pmx_core {
 	uart3_pins_default: uart3_pins_default {
 		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_SLEW | MUX_MODE2)	/* uart2_ctsn.uart3_rxd */
-			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1)	/* uart2_rtsn.uart3_txd */
+			DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0)	/* uart3_rxd */
+			DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0)	/* uart3_txd */
 		>;
 	};
 
@@ -108,9 +108,9 @@
 	pinctrl-0 = <&i2c5_pins_default>;
 	clock-frequency = <400000>;
 
-	eeprom_base: atmel@50 {
+	eeprom_base: atmel@54 {
 		compatible = "atmel,24c08";
-		reg = <0x50>;
+		reg = <0x54>;
 		pagesize = <16>;
 	};
 
diff --git a/sys/gnu/dts/arm/arm-realview-eb-11mp-revb.dts b/sys/gnu/dts/arm/arm-realview-eb-11mp-revb.dts
new file mode 100644
index 000000000000..e68527b0d552
--- /dev/null
+++ b/sys/gnu/dts/arm/arm-realview-eb-11mp-revb.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "arm-realview-eb-11mp.dts"
+
+/ {
+	model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B";
+};
+
+/*
+ * The revision B has a distinctly different layout of the syscon, so
+ * append a specific compatible-string.
+ */
+&syscon {
+	compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd";
+};
+
+&intc {
+	reg = <0x10101000 0x1000>,
+	      <0x10100100 0x100>;
+};
+
+&L2 {
+	reg = <0x10102000 0x1000>;
+};
+
+&scu {
+	reg = <0x10100000 0x100>;
+};
+
+&twd_timer {
+	reg = <0x10100600 0x20>;
+};
+
+&twd_wdog {
+	reg = <0x10100620 0x20>;
+};
+
+/*
+ * On revision B, we cannot reach the secondary interrupt
+ * controller, as a result, some peripherals that are dependent
+ * on their IRQ cannot be reached, so disable them.
+ */
+&intc_second {
+	status = "disabled";
+};
+
+&gpio0 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "disabled";
+};
+
+&gpio2 {
+	status = "disabled";
+};
+
+&serial2 {
+	status = "disabled";
+};
+
+&serial3 {
+	status = "disabled";
+};
+
+&ssp {
+	status = "disabled";
+};
+
+&wdog {
+	status = "disabled";
+};
diff --git a/sys/gnu/dts/arm/arm-realview-eb-11mp.dts b/sys/gnu/dts/arm/arm-realview-eb-11mp.dts
new file mode 100644
index 000000000000..87ff602a2a2d
--- /dev/null
+++ b/sys/gnu/dts/arm/arm-realview-eb-11mp.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "arm-realview-eb-mp.dtsi"
+
+/ {
+	model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C";
+	arm,hbi = <0x146>;
+
+	/*
+	 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
+	 * Reference: ARM DUI 0318F
+	 *
+	 * To run this machine with QEMU, specify the following:
+	 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
+	 */
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "arm,realview-smp";
+
+		MP11_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,arm11mpcore";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		MP11_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,arm11mpcore";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+
+		MP11_2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,arm11mpcore";
+			reg = <2>;
+			next-level-cache = <&L2>;
+		};
+
+		MP11_3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,arm11mpcore";
+			reg = <3>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
+
+&pmu {
+	interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
+};
diff --git a/sys/gnu/dts/arm/arm-realview-eb-a9mp.dts b/sys/gnu/dts/arm/arm-realview-eb-a9mp.dts
new file mode 100644
index 000000000000..967684b3636c
--- /dev/null
+++ b/sys/gnu/dts/arm/arm-realview-eb-a9mp.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "arm-realview-eb-mp.dtsi"
+
+/ {
+	model = "ARM RealView EB Cortex A9 MPCore";
+
+	/*
+	 * This is the Cortex A9 MPCore tile used with the
+	 * RealView EB.
+	 */
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "arm,realview-smp";
+
+		A9_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		A9_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+
+		A9_2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <2>;
+			next-level-cache = <&L2>;
+		};
+
+		A9_3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <3>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
+
+&pmu {
+	interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
+};
diff --git a/sys/gnu/dts/arm/arm-realview-eb-mp.dtsi b/sys/gnu/dts/arm/arm-realview-eb-mp.dtsi
new file mode 100644
index 000000000000..7b8d90b7aeea
--- /dev/null
+++ b/sys/gnu/dts/arm/arm-realview-eb-mp.dtsi
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "arm-realview-eb.dtsi"
+
+/*
+ * This is the common include file for all MPCore variants of the
+ * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B
+ * and Cortex-A9 MPCore.
+ */
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,realview-eb-soc", "simple-bus";
+		regmap = <&syscon>;
+		ranges;
+
+		/* Primary interrupt controller in the test chip */
+		intc: interrupt-controller@1f000100 {
+			compatible = "arm,eb11mp-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			interrupt-controller;
+			reg = <0x1f001000 0x1000>,
+			      <0x1f000100 0x100>;
+		};
+
+		/* Secondary interrupt controller on the FPGA */
+		intc_second: interrupt-controller@10040000 {
+			compatible = "arm,pl390";
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			interrupt-controller;
+			reg = <0x10041000 0x1000>,
+			      <0x10040000 0x100>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		L2: l2-cache {
+			compatible = "arm,l220-cache";
+			reg = <0x1f002000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 30 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 31 IRQ_TYPE_LEVEL_HIGH>;
+			cache-unified;
+			cache-level = <2>;
+			/*
+			 * Override default cache size, sets and
+			 * associativity as these may be erroneously set
+			 * up by boot loader(s), probably for safety
+			 * since th outer sync operation can cause the
+			 * cache to hang unless disabled.
+			 */
+			cache-size = <1048576>; // 1MB
+			cache-sets = <4096>;
+			cache-line-size = <32>;
+			arm,shared-override;
+			arm,parity-enable;
+			arm,outer-sync-disable;
+		};
+
+		scu: scu@1f000000 {
+			compatible = "arm,arm11mp-scu";
+			reg = <0x1f000000 0x100>;
+		};
+
+		twd_timer: timer@1f000600 {
+			compatible = "arm,arm11mp-twd-timer";
+			reg = <0x1f000600 0x20>;
+			interrupt-parent = <&intc>;
+			interrupts = <1 13 0xf04>;
+		};
+
+		twd_wdog: watchdog@1f000620 {
+			compatible = "arm,arm11mp-twd-wdt";
+			reg = <0x1f000620 0x20>;
+			interrupt-parent = <&intc>;
+			interrupts = <1 14 0xf04>;
+		};
+
+		/* PMU with one IRQ line per core */
+		pmu: pmu@0 {
+			compatible = "arm,arm11mpcore-pmu";
+			interrupt-parent = <&intc>;
+			interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 20 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+};
+
+/*
+ * This adapts all the peripherals to the interrupt routing
+ * to the GIC on the core tile.
+ */
+
+&ethernet {
+	interrupt-parent = <&intc>;
+	interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usb {
+	interrupt-parent = <&intc>;
+	interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&aaci {
+	interrupt-parent = <&intc>;
+	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&mmc {
+	interrupt-parent = <&intc>;
+	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
+			<0 15 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&kmi0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&kmi1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&charlcd {
+	interrupt-parent = <&intc>;
+	interrupts = <0  IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer01 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer23 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&rtc {
+	interrupt-parent = <&intc>;
+	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+/*
+ * On revision A, these peripherals does not have their IRQ lines
+ * routed to the core tile, but they can be reached on the secondary
+ * GIC.
+ */
+&gpio0 {
+	interrupt-parent = <&intc_second>;
+	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio1 {
+	interrupt-parent = <&intc_second>;
+	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio2 {
+	interrupt-parent = <&intc_second>;
+	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial2 {
+	interrupt-parent = <&intc_second>;
+	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+	status = "okay";
+};
+
+&serial3 {
+	interrupt-parent = <&intc_second>;
+	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+	status = "okay";
+};
+
+&ssp {
+	interrupt-parent = <&intc_second>;
+	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+	status = "okay";
+};
+
+&wdog {
+	interrupt-parent = <&intc_second>;
+	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/arm-realview-eb.dts b/sys/gnu/dts/arm/arm-realview-eb.dts
new file mode 100644
index 000000000000..15431077f00c
--- /dev/null
+++ b/sys/gnu/dts/arm/arm-realview-eb.dts
@@ -0,0 +1,166 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "arm-realview-eb.dtsi"
+
+/ {
+	model = "ARM RealView Emulation Baseboard";
+	compatible = "arm,realview-eb";
+	arm,hbi = <0x140>;
+
+	/*
+	 * This is the core tile with the CPU and GIC etc for the
+	 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
+	 * or PMU.
+	 *
+	 * To run this machine with QEMU, specify the following:
+	 * qemu-system-arm -M realview-eb
+	 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
+	 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
+	 * core tiles.
+	 */
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,realview-eb-soc", "simple-bus";
+		regmap = <&syscon>;
+		ranges;
+
+		intc: interrupt-controller@10040000 {
+			compatible = "arm,pl390";
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			interrupt-controller;
+			reg = <0x10041000 0x1000>,
+			      <0x10040000 0x100>;
+		};
+	};
+};
+
+/*
+ * This adapts all the peripherals to the interrupt routing
+ * to the GIC on the core tile.
+ */
+
+&ethernet {
+	interrupt-parent = <&intc>;
+	interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usb {
+	interrupt-parent = <&intc>;
+	interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&aaci {
+	interrupt-parent = <&intc>;
+	interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&mmc {
+	interrupt-parent = <&intc>;
+	interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
+			<0 18 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&kmi0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&kmi1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&charlcd {
+	interrupt-parent = <&intc>;
+	interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial2 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial3 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&ssp {
+	interrupt-parent = <&intc>;
+	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&wdog {
+	interrupt-parent = <&intc>;
+	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer01 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer23 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio2 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&rtc {
+	interrupt-parent = <&intc>;
+	interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&clcd {
+	interrupt-parent = <&intc>;
+	interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/sys/gnu/dts/arm/arm-realview-eb.dtsi b/sys/gnu/dts/arm/arm-realview-eb.dtsi
new file mode 100644
index 000000000000..1c6a040218e3
--- /dev/null
+++ b/sys/gnu/dts/arm/arm-realview-eb.dtsi
@@ -0,0 +1,453 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "arm,realview-eb";
+
+	chosen { };
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		i2c0 = &i2c;
+	};
+
+	memory {
+		/* 128 MiB memory @ 0x0 */
+		reg = <0x00000000 0x08000000>;
+	};
+
+	/* The voltage to the MMC card is hardwired at 3.3V */
+	vmmc: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+        };
+
+	veth: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "veth";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+	};
+
+	xtal24mhz: xtal24mhz@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+	};
+
+	timclk: timclk@1M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <24>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	mclk: mclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	kmiclk: kmiclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	sspclk: sspclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	uartclk: uartclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	wdogclk: wdogclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	/* FIXME: this actually hangs off the PLL clocks */
+	pclk: pclk@0 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	flash0@40000000 {
+		/* 2 * 32MiB NOR Flash memory */
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x40000000 0x04000000>;
+		bank-width = <4>;
+	};
+
+	flash1@44000000 {
+		/* 2 * 32MiB NOR Flash memory */
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x44000000 0x04000000>;
+		bank-width = <4>;
+	};
+
+	/* SMSC 9118 ethernet with PHY and EEPROM */
+	ethernet: ethernet@4e000000 {
+		compatible = "smsc,lan9118", "smsc,lan9115";
+		reg = <0x4e000000 0x10000>;
+		phy-mode = "mii";
+		reg-io-width = <4>;
+		smsc,irq-active-high;
+		smsc,irq-push-pull;
+		vdd33a-supply = <&veth>;
+		vddvario-supply = <&veth>;
+	};
+
+	usb: usb@4f000000 {
+		compatible = "nxp,usb-isp1761";
+		reg = <0x4f000000 0x20000>;
+		port1-otg;
+	};
+
+	/* These peripherals are inside the FPGA */
+	fpga {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		syscon: syscon@10000000 {
+			compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
+			reg = <0x10000000 0x1000>;
+
+			led@08.0 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x01>;
+				label = "versatile:0";
+				linux,default-trigger = "heartbeat";
+				default-state = "on";
+			};
+			led@08.1 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x02>;
+				label = "versatile:1";
+				linux,default-trigger = "mmc0";
+				default-state = "off";
+			};
+			led@08.2 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x04>;
+				label = "versatile:2";
+				linux,default-trigger = "cpu0";
+				default-state = "off";
+			};
+			led@08.3 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x08>;
+				label = "versatile:3";
+				default-state = "off";
+			};
+			led@08.4 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x10>;
+				label = "versatile:4";
+				default-state = "off";
+			};
+			led@08.5 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x20>;
+				label = "versatile:5";
+				default-state = "off";
+			};
+			led@08.6 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x40>;
+				label = "versatile:6";
+				default-state = "off";
+			};
+			led@08.7 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x80>;
+				label = "versatile:7";
+				default-state = "off";
+			};
+			oscclk0: osc0@0c {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x0C>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk1: osc1@10 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x10>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk2: osc2@14 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x14>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk3: osc3@18 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x18>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk4: osc4@1c {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x1c>;
+				clocks = <&xtal24mhz>;
+			};
+		};
+
+		i2c: i2c@10002000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "arm,versatile-i2c";
+			reg = <0x10002000 0x1000>;
+
+			rtc@68 {
+				compatible = "dallas,ds1338";
+				reg = <0x68>;
+			};
+		};
+
+		aaci: aaci@10004000 {
+			compatible = "arm,pl041", "arm,primecell";
+			reg = <0x10004000 0x1000>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		mmc: mmcsd@10005000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x10005000 0x1000>;
+
+			/* Due to frequent FIFO overruns, use just 500 kHz */
+			max-frequency = <500000>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			clocks = <&mclk>, <&pclk>;
+			clock-names = "mclk", "apb_pclk";
+			vmmc-supply = <&vmmc>;
+			cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+			wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		kmi0: kmi@10006000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x10006000 0x1000>;
+			clocks = <&kmiclk>, <&pclk>;
+			clock-names = "KMIREFCLK", "apb_pclk";
+		};
+
+		kmi1: kmi@10007000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x10007000 0x1000>;
+			clocks = <&kmiclk>, <&pclk>;
+			clock-names = "KMIREFCLK", "apb_pclk";
+		};
+
+		charlcd: fpga_charlcd: charlcd@10008000 {
+			compatible = "arm,versatile-lcd";
+			reg = <0x10008000 0x1000>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		serial0: serial@10009000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x10009000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		serial1: serial@1000a000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x1000a000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		serial2: serial@1000b000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x1000b000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		serial3: serial@1000c000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x1000c000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		ssp: ssp@1000d000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x1000d000 0x1000>;
+			clocks = <&sspclk>, <&pclk>;
+			clock-names = "SSPCLK", "apb_pclk";
+		};
+
+		wdog: watchdog@10010000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x10010000 0x1000>;
+			clocks = <&wdogclk>, <&pclk>;
+			clock-names = "wdogclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		timer01: timer@10011000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10011000 0x1000>;
+			clocks = <&timclk>, <&timclk>, <&pclk>;
+			clock-names = "timer1", "timer2", "apb_pclk";
+		};
+
+		timer23: timer@10012000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10012000 0x1000>;
+			clocks = <&timclk>, <&timclk>, <&pclk>;
+			clock-names = "timer1", "timer2", "apb_pclk";
+		};
+
+		gpio0: gpio@10013000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x10013000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio1: gpio@10014000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x10014000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio2: gpio@10015000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x10015000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		rtc: rtc@10017000 {
+			compatible = "arm,pl031", "arm,primecell";
+			reg = <0x10017000 0x1000>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		clcd: clcd@10020000 {
+			compatible = "arm,pl111", "arm,primecell";
+			reg = <0x10020000 0x1000>;
+			interrupt-names = "combined";
+			clocks = <&oscclk0>, <&pclk>;
+			clock-names = "clcdclk", "apb_pclk";
+
+			port {
+				clcd_pads: endpoint {
+					remote-endpoint = <&clcd_panel>;
+					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+				};
+			};
+
+			panel {
+				compatible = "panel-dpi";
+
+				port {
+					clcd_panel: endpoint {
+						remote-endpoint = <&clcd_pads>;
+					};
+				};
+
+				/* Standard 640x480 VGA timings */
+				panel-timing {
+					clock-frequency = <25175000>;
+					hactive = <640>;
+					hback-porch = <48>;
+					hfront-porch = <16>;
+					hsync-len = <96>;
+					vactive = <480>;
+					vback-porch = <33>;
+					vfront-porch = <10>;
+					vsync-len = <2>;
+				};
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/arm-realview-pb1176.dts b/sys/gnu/dts/arm/arm-realview-pb1176.dts
index 1bc64cda819e..c789564f2803 100644
--- a/sys/gnu/dts/arm/arm-realview-pb1176.dts
+++ b/sys/gnu/dts/arm/arm-realview-pb1176.dts
@@ -53,6 +53,14 @@
 		regulator-boot-on;
         };
 
+	veth: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "veth";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+	};
+
 	xtal24mhz: xtal24mhz@24M {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
@@ -106,6 +114,53 @@
 		clock-frequency = <0>;
 	};
 
+	flash@30000000 {
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x30000000 0x4000000>;
+		bank-width = <4>;
+	};
+
+	fpga_flash@38000000 {
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x38000000 0x800000>;
+		bank-width = <4>;
+	};
+
+	/*
+	 * The "secure flash" contains things like the boot
+	 * monitor so we don't want people to accidentally
+	 * screw this up. Mark the device tree node disabled
+	 * by default.
+	 */
+	secflash@3c000000 {
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x3c000000 0x4000000>;
+		bank-width = <4>;
+		status = "disabled";
+	};
+
+	/* SMSC 9118 ethernet with PHY and EEPROM */
+	ethernet@3a000000 {
+		compatible = "smsc,lan9118", "smsc,lan9115";
+		reg = <0x3a000000 0x10000>;
+		interrupt-parent = <&intc_fpga1176>;
+		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+		phy-mode = "mii";
+		reg-io-width = <4>;
+		smsc,irq-active-high;
+		smsc,irq-push-pull;
+		vdd33a-supply = <&veth>;
+		vddvario-supply = <&veth>;
+	};
+
+	usb@3b000000 {
+		compatible = "nxp,usb-isp1761";
+		reg = <0x3b000000 0x20000>;
+		interrupt-parent = <&intc_fpga1176>;
+		interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+		port1-otg;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -176,6 +231,41 @@
 				label = "versatile:7";
 				default-state = "off";
 			};
+			oscclk0: osc0@0c {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x0C>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk1: osc1@10 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x10>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk2: osc2@14 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x14>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk3: osc3@18 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x18>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk4: osc4@1c {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x1c>;
+				clocks = <&xtal24mhz>;
+			};
 		};
 
 		/* Primary DevChip GIC synthesized with the CPU */
@@ -297,6 +387,53 @@
 			clocks = <&uartclk>, <&pclk>;
 			clock-names = "uartclk", "apb_pclk";
 		};
+
+		/* Direct-mapped development chip ROM */
+		pb1176_rom@10200000 {
+			compatible = "direct-mapped";
+			reg = <0x10200000 0x4000>;
+			bank-width = <1>;
+		};
+
+		clcd@10112000 {
+			compatible = "arm,pl111", "arm,primecell";
+			reg = <0x10112000 0x1000>;
+			interrupt-parent = <&intc_dc1176>;
+			interrupt-names = "combined";
+			interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&oscclk0>, <&pclk>;
+			clock-names = "clcdclk", "apb_pclk";
+
+			port {
+				clcd_pads: endpoint {
+					remote-endpoint = <&clcd_panel>;
+					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+				};
+			};
+
+			panel {
+				compatible = "panel-dpi";
+
+				port {
+					clcd_panel: endpoint {
+						remote-endpoint = <&clcd_pads>;
+					};
+				};
+
+				/* Standard 640x480 VGA timings */
+				panel-timing {
+					clock-frequency = <25175000>;
+					hactive = <640>;
+					hback-porch = <48>;
+					hfront-porch = <16>;
+					hsync-len = <96>;
+					vactive = <480>;
+					vback-porch = <33>;
+					vfront-porch = <10>;
+					vsync-len = <2>;
+				};
+			};
+		};
 	};
 
 	/* These peripherals are inside the FPGA rather than the DevChip */
@@ -306,6 +443,27 @@
 		compatible = "simple-bus";
 		ranges;
 
+		i2c0: i2c@10002000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "arm,versatile-i2c";
+			reg = <0x10002000 0x1000>;
+
+			rtc@68 {
+				compatible = "dallas,ds1338";
+				reg = <0x68>;
+			};
+		};
+
+		fpga_aaci: aaci@10004000 {
+			compatible = "arm,pl041", "arm,primecell";
+			reg = <0x10004000 0x1000>;
+			interrupt-parent = <&intc_fpga1176>;
+			interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
 		fpga_mci: mmcsd@10005000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x10005000 0x1000>;
diff --git a/sys/gnu/dts/arm/arm-realview-pb11mp.dts b/sys/gnu/dts/arm/arm-realview-pb11mp.dts
index da755c9851a7..3944765ac4b0 100644
--- a/sys/gnu/dts/arm/arm-realview-pb11mp.dts
+++ b/sys/gnu/dts/arm/arm-realview-pb11mp.dts
@@ -230,14 +230,14 @@
 
 	flash0@40000000 {
 		/* 2 * 32MiB NOR Flash memory */
-		compatible = "arm,vexpress-flash", "cfi-flash";
+		compatible = "arm,versatile-flash", "cfi-flash";
 		reg = <0x40000000 0x04000000>;
 		bank-width = <4>;
 	};
 
 	flash1@44000000 {
 		// 2 * 32MiB NOR Flash memory
-		compatible = "arm,vexpress-flash", "cfi-flash";
+		compatible = "arm,versatile-flash", "cfi-flash";
 		reg = <0x44000000 0x04000000>;
 		bank-width = <4>;
 	};
@@ -627,16 +627,17 @@
 					};
 				};
 
+				/* Standard 640x480 VGA timings */
 				panel-timing {
-					clock-frequency = <63500127>;
-					hactive = <1024>;
-					hback-porch = <152>;
-					hfront-porch = <48>;
-					hsync-len = <104>;
-					vactive = <768>;
-					vback-porch = <23>;
-					vfront-porch = <3>;
-					vsync-len = <4>;
+					clock-frequency = <25175000>;
+					hactive = <640>;
+					hback-porch = <48>;
+					hfront-porch = <16>;
+					hsync-len = <96>;
+					vactive = <480>;
+					vback-porch = <33>;
+					vfront-porch = <10>;
+					vsync-len = <2>;
 				};
 			};
 		};
diff --git a/sys/gnu/dts/arm/arm-realview-pba8.dts b/sys/gnu/dts/arm/arm-realview-pba8.dts
new file mode 100644
index 000000000000..d3238c252b59
--- /dev/null
+++ b/sys/gnu/dts/arm/arm-realview-pba8.dts
@@ -0,0 +1,178 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "arm-realview-pbx.dtsi"
+
+/ {
+	model = "ARM RealView Platform Baseboard for Cortex-A8";
+	compatible = "arm,realview-pba8";
+	arm,hbi = <0x178>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "arm,realview-smp";
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a8";
+			reg = <0>;
+		};
+	};
+
+	pmu: pmu@0 {
+		compatible = "arm,cortex-a8-pmu";
+		interrupt-parent = <&intc>;
+		interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>;
+	};
+
+	/* Primary GIC PL390 interrupt controller in the test chip */
+	intc: interrupt-controller@1e000000 {
+		compatible = "arm,pl390";
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		interrupt-controller;
+		reg = <0x1e001000 0x1000>,
+		      <0x1e000000 0x100>;
+	};
+};
+
+&ethernet {
+	interrupt-parent = <&intc>;
+	interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usb {
+	interrupt-parent = <&intc>;
+	interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&soc {
+	compatible = "arm,realview-pba8-soc", "simple-bus";
+};
+
+&syscon {
+	compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd";
+};
+
+&serial0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial2 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial3 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&ssp {
+	interrupt-parent = <&intc>;
+	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&wdog0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&wdog1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer01 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer23 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio2 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&rtc {
+	interrupt-parent = <&intc>;
+	interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer45 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer67 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&aaci {
+	interrupt-parent = <&intc>;
+	interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&mmc {
+	interrupt-parent = <&intc>;
+	interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
+		     <0 18 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&kmi0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&kmi1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&clcd {
+	interrupt-parent = <&intc>;
+	interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/sys/gnu/dts/arm/arm-realview-pbx-a9.dts b/sys/gnu/dts/arm/arm-realview-pbx-a9.dts
new file mode 100644
index 000000000000..db808f92dd79
--- /dev/null
+++ b/sys/gnu/dts/arm/arm-realview-pbx-a9.dts
@@ -0,0 +1,229 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "arm-realview-pbx.dtsi"
+
+/ {
+	/*
+	 * This is the RealView Platform Baseboard Explore for Cortex-A9
+	 * (HBI0182 + HBI0183) as described in ARM DUI 0440B
+	 */
+	model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
+	arm,hbi = <0x182>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "arm,realview-smp";
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+				core1 {
+					cpu = <&CPU1>;
+				};
+			};
+		};
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x0>;
+			next-level-cache = <&L2>;
+		};
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x1>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	L2: l2-cache {
+		compatible = "arm,pl310-cache";
+		reg = <0x1f002000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+		/*
+		 * Override default cache size, sets and
+		 * associativity as these may be erroneously set
+		 * up by boot loader(s).
+		 */
+		cache-size = <1048576>; // 1MB
+		cache-sets = <4096>;
+		cache-line-size = <32>;
+		arm,parity-disable;
+		arm,tag-latency = <1>;
+		arm,data-latency = <1 1>;
+		arm,dirty-latency = <1>;
+	};
+
+	scu: scu@1f000000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0x1f000000 0x100>;
+	};
+
+	twd_timer: timer@1f000600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0x1f000600 0x20>;
+		interrupt-parent = <&intc>;
+		interrupts = <1 13 0xf04>;
+	};
+
+	twd_wdog: watchdog@1f000620 {
+		compatible = "arm,cortex-a9-twd-wdt";
+		reg = <0x1f000620 0x20>;
+		interrupt-parent = <&intc>;
+		interrupts = <1 14 0xf04>;
+	};
+
+	pmu: pmu@0 {
+		compatible = "arm,cortex-a9-pmu";
+		interrupt-parent = <&intc>;
+		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 45 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CPU0>, <&CPU1>;
+	};
+
+	/* Primary GIC PL390 interrupt controller in the test chip */
+	intc: interrupt-controller@1f000000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		interrupt-controller;
+		reg = <0x1f001000 0x1000>,
+		      <0x1f000100 0x100>;
+	};
+};
+
+&ethernet {
+	interrupt-parent = <&intc>;
+	interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usb {
+	interrupt-parent = <&intc>;
+	interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial2 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&serial3 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&ssp {
+	interrupt-parent = <&intc>;
+	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&wdog0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&wdog1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer01 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer23 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio2 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&rtc {
+	interrupt-parent = <&intc>;
+	interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer45 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&timer67 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&aaci {
+	interrupt-parent = <&intc>;
+	interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&mmc {
+	interrupt-parent = <&intc>;
+	interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
+		     <0 18 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&kmi0 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&kmi1 {
+	interrupt-parent = <&intc>;
+	interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&clcd {
+	interrupt-parent = <&intc>;
+	interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/sys/gnu/dts/arm/arm-realview-pbx.dtsi b/sys/gnu/dts/arm/arm-realview-pbx.dtsi
new file mode 100644
index 000000000000..aeb49c4bd773
--- /dev/null
+++ b/sys/gnu/dts/arm/arm-realview-pbx.dtsi
@@ -0,0 +1,542 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "arm,realview-pbx";
+
+	chosen { };
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		i2c0 = &i2c;
+	};
+
+	memory {
+		/* 128 MiB memory @ 0x0 */
+		reg = <0x00000000 0x08000000>;
+	};
+
+	/* The voltage to the MMC card is hardwired at 3.3V */
+	vmmc: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+        };
+
+	veth: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "veth";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+	};
+
+	xtal24mhz: xtal24mhz@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+	};
+
+	refclk32khz: refclk32khz {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+
+	timclk: timclk@1M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <24>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	mclk: mclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	kmiclk: kmiclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	sspclk: sspclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	uartclk: uartclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	wdogclk: wdogclk@24M {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&xtal24mhz>;
+	};
+
+	/* FIXME: this actually hangs off the PLL clocks */
+	pclk: pclk@0 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	flash0@40000000 {
+		/* 2 * 32MiB NOR Flash memory */
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x40000000 0x04000000>;
+		bank-width = <4>;
+	};
+
+	flash1@44000000 {
+		/* 2 * 32MiB NOR Flash memory */
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x44000000 0x04000000>;
+		bank-width = <4>;
+	};
+
+	/* SMSC 9118 ethernet with PHY and EEPROM */
+	ethernet: ethernet@4e000000 {
+		compatible = "smsc,lan9118", "smsc,lan9115";
+		reg = <0x4e000000 0x10000>;
+		phy-mode = "mii";
+		reg-io-width = <4>;
+		smsc,irq-active-high;
+		smsc,irq-push-pull;
+		vdd33a-supply = <&veth>;
+		vddvario-supply = <&veth>;
+	};
+
+	usb: usb@4f000000 {
+		compatible = "nxp,usb-isp1761";
+		reg = <0x4f000000 0x20000>;
+		port1-otg;
+	};
+
+	soc: soc@0 {
+		compatible = "arm,realview-pbx-soc", "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		regmap = <&syscon>;
+		ranges;
+
+		syscon: syscon@10000000 {
+			compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
+			reg = <0x10000000 0x1000>;
+
+			led@08.0 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x01>;
+				label = "versatile:0";
+				linux,default-trigger = "heartbeat";
+				default-state = "on";
+			};
+			led@08.1 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x02>;
+				label = "versatile:1";
+				linux,default-trigger = "mmc0";
+				default-state = "off";
+			};
+			led@08.2 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x04>;
+				label = "versatile:2";
+				linux,default-trigger = "cpu0";
+				default-state = "off";
+			};
+			led@08.3 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x08>;
+				label = "versatile:3";
+				default-state = "off";
+			};
+			led@08.4 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x10>;
+				label = "versatile:4";
+				default-state = "off";
+			};
+			led@08.5 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x20>;
+				label = "versatile:5";
+				default-state = "off";
+			};
+			led@08.6 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x40>;
+				label = "versatile:6";
+				default-state = "off";
+			};
+			led@08.7 {
+				compatible = "register-bit-led";
+				offset = <0x08>;
+				mask = <0x80>;
+				label = "versatile:7";
+				default-state = "off";
+			};
+			oscclk0: osc0@0c {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x0C>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk1: osc1@10 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x10>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk2: osc2@14 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x14>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk3: osc3@18 {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x18>;
+				clocks = <&xtal24mhz>;
+			};
+			oscclk4: osc4@1c {
+				compatible = "arm,syscon-icst307";
+				#clock-cells = <0>;
+				lock-offset = <0x20>;
+				vco-offset = <0x1c>;
+				clocks = <&xtal24mhz>;
+			};
+		};
+
+		sp810_syscon0: sysctl@10001000 {
+			compatible = "arm,sp810", "arm,primecell";
+			reg = <0x10001000 0x1000>;
+			clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
+			clock-names = "refclk", "timclk", "apb_pclk";
+			#clock-cells = <1>;
+			clock-output-names = "timerclk0",
+					     "timerclk1",
+					     "timerclk2",
+					     "timerclk3";
+			assigned-clocks = <&sp810_syscon0 0>,
+					  <&sp810_syscon0 1>,
+					  <&sp810_syscon0 2>,
+					  <&sp810_syscon0 3>;
+			assigned-clock-parents = <&timclk>,
+					       <&timclk>,
+					       <&timclk>,
+					       <&timclk>;
+		};
+
+		i2c: i2c@10002000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "arm,versatile-i2c";
+			reg = <0x10002000 0x1000>;
+
+			rtc@68 {
+				compatible = "dallas,ds1338";
+				reg = <0x68>;
+			};
+		};
+
+		serial0: serial@10009000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x10009000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		serial1: serial@1000a000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x1000a000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		serial2: serial@1000b000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x1000b000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		ssp: ssp@1000d000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x1000d000 0x1000>;
+			clocks = <&sspclk>, <&pclk>;
+			clock-names = "SSPCLK", "apb_pclk";
+		};
+
+		wdog0: watchdog@1000f000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x1000f000 0x1000>;
+			clocks = <&wdogclk>, <&pclk>;
+			clock-names = "wdogclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		wdog1: watchdog@10010000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x10010000 0x1000>;
+			clocks = <&wdogclk>, <&pclk>;
+			clock-names = "wdogclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		timer01: timer@10011000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10011000 0x1000>;
+			clocks = <&sp810_syscon0 0>,
+			         <&sp810_syscon0 1>,
+				 <&pclk>;
+			clock-names = "timerclk0",
+				    "timerclk1",
+				    "apb_pclk";
+		};
+
+		timer23: timer@10012000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10012000 0x1000>;
+			clocks = <&sp810_syscon0 2>,
+			         <&sp810_syscon0 3>,
+				 <&pclk>;
+			clock-names = "timerclk2",
+				    "timerclk3",
+				    "apb_pclk";
+		};
+
+		gpio0: gpio@10013000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x10013000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio1: gpio@10014000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x10014000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		gpio2: gpio@10015000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0x10015000 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		/* DVI serial bus control is at 10016000 */
+
+		rtc: rtc@10017000 {
+			compatible = "arm,pl031", "arm,primecell";
+			reg = <0x10017000 0x1000>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		timer45: timer@10018000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10018000 0x1000>;
+			clocks = <&timclk>, <&timclk>, <&pclk>;
+			clock-names = "timerclk4", "timerclk5", "apb_pclk";
+		};
+
+		timer67: timer@10019000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x10019000 0x1000>;
+			clocks = <&timclk>, <&timclk>, <&pclk>;
+			clock-names = "timerclk6", "timerclk7", "apb_pclk";
+		};
+
+		sp810_syscon1: sysctl@1001a000 {
+			compatible = "arm,sp810", "arm,primecell";
+			reg = <0x1001a000 0x1000>;
+			clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
+			clock-names = "refclk", "timclk", "apb_pclk";
+			#clock-cells = <1>;
+			clock-output-names = "timerclk4",
+					     "timerclk5",
+					     "timerclk6",
+					     "timerclk7";
+			assigned-clocks = <&sp810_syscon1 0>,
+					  <&sp810_syscon1 1>,
+					  <&sp810_syscon1 2>,
+					  <&sp810_syscon1 3>;
+			assigned-clock-parents = <&timclk>,
+					       <&timclk>,
+					       <&timclk>,
+					       <&timclk>;
+		};
+	};
+
+
+	/* These peripherals are inside the FPGA */
+	fpga {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		aaci: aaci@10004000 {
+			compatible = "arm,pl041", "arm,primecell";
+			reg = <0x10004000 0x1000>;
+			clocks = <&pclk>;
+			clock-names = "apb_pclk";
+		};
+
+		mmc: mmcsd@10005000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x10005000 0x1000>;
+
+			/* Due to frequent FIFO overruns, use just 500 kHz */
+			max-frequency = <500000>;
+			bus-width = <4>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			clocks = <&mclk>, <&pclk>;
+			clock-names = "mclk", "apb_pclk";
+			vmmc-supply = <&vmmc>;
+			cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+			wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		kmi0: kmi@10006000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x10006000 0x1000>;
+			clocks = <&kmiclk>, <&pclk>;
+			clock-names = "KMIREFCLK", "apb_pclk";
+		};
+
+		kmi1: kmi@10007000 {
+			compatible = "arm,pl050", "arm,primecell";
+			reg = <0x10007000 0x1000>;
+			clocks = <&kmiclk>, <&pclk>;
+			clock-names = "KMIREFCLK", "apb_pclk";
+		};
+
+		serial3: serial@1000c000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x1000c000 0x1000>;
+			clocks = <&uartclk>, <&pclk>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+	};
+
+	/* These peripherals are inside the NEC ISSP */
+	issp {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		clcd: clcd@10020000 {
+			compatible = "arm,pl111", "arm,primecell";
+			reg = <0x10020000 0x1000>;
+			interrupt-names = "combined";
+			clocks = <&oscclk4>, <&pclk>;
+			clock-names = "clcdclk", "apb_pclk";
+
+			port {
+				clcd_pads: endpoint {
+					remote-endpoint = <&clcd_panel>;
+					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+				};
+			};
+
+			panel {
+				compatible = "panel-dpi";
+
+				port {
+					clcd_panel: endpoint {
+						remote-endpoint = <&clcd_pads>;
+					};
+				};
+
+				/* Standard 640x480 VGA timings */
+				panel-timing {
+					clock-frequency = <25175000>;
+					hactive = <640>;
+					hback-porch = <48>;
+					hfront-porch = <16>;
+					hsync-len = <96>;
+					vactive = <480>;
+					vback-porch = <33>;
+					vfront-porch = <10>;
+					vsync-len = <2>;
+				};
+			};
+		};
+	};
+};
+
diff --git a/sys/gnu/dts/arm/armada-370-db.dts b/sys/gnu/dts/arm/armada-370-db.dts
index bb280de511da..2364fc56ae13 100644
--- a/sys/gnu/dts/arm/armada-370-db.dts
+++ b/sys/gnu/dts/arm/armada-370-db.dts
@@ -168,6 +168,33 @@
 					spi-max-frequency = <50000000>;
 				};
 			};
+
+			nand@d0000 {
+				status = "okay";
+				num-cs = <1>;
+				marvell,nand-keep-config;
+				marvell,nand-enable-arbiter;
+				nand-on-flash-bbt;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					partition@0 {
+						label = "U-Boot";
+						reg = <0 0x800000>;
+					};
+					partition@800000 {
+						label = "Linux";
+						reg = <0x800000 0x800000>;
+					};
+					partition@1000000 {
+						label = "Filesystem";
+						reg = <0x1000000 0x3f000000>;
+					};
+				};
+			};
 		};
 
 		pcie-controller {
diff --git a/sys/gnu/dts/arm/armada-370-mirabox.dts b/sys/gnu/dts/arm/armada-370-mirabox.dts
index 3aa980ad64f0..d5e19cd4d256 100644
--- a/sys/gnu/dts/arm/armada-370-mirabox.dts
+++ b/sys/gnu/dts/arm/armada-370-mirabox.dts
@@ -200,7 +200,7 @@
 &pinctrl {
 	pwr_led_pin: pwr-led-pin {
 		marvell,pins = "mpp63";
-		marvell,function = "gpo";
+		marvell,function = "gpio";
 	};
 
 	stat_led_pins: stat-led-pins {
diff --git a/sys/gnu/dts/arm/armada-370-netgear-rn104.dts b/sys/gnu/dts/arm/armada-370-netgear-rn104.dts
index faa474874cb8..11565752b9f6 100644
--- a/sys/gnu/dts/arm/armada-370-netgear-rn104.dts
+++ b/sys/gnu/dts/arm/armada-370-netgear-rn104.dts
@@ -297,7 +297,7 @@
 
 	backup_led_pin: backup-led-pin {
 		marvell,pins = "mpp63";
-		marvell,function = "gpo";
+		marvell,function = "gpio";
 	};
 
 	power_led_pin: power-led-pin {
diff --git a/sys/gnu/dts/arm/armada-370-synology-ds213j.dts b/sys/gnu/dts/arm/armada-370-synology-ds213j.dts
index 836bcc07afc5..8ca7a4340c0f 100644
--- a/sys/gnu/dts/arm/armada-370-synology-ds213j.dts
+++ b/sys/gnu/dts/arm/armada-370-synology-ds213j.dts
@@ -339,7 +339,7 @@
 
 	fan_ctrl_high_pin: fan-ctrl-high-pin {
 		marvell,pins = "mpp63";
-		marvell,function = "gpo";
+		marvell,function = "gpio";
 	};
 
 	fan_alarm_pin: fan-alarm-pin {
diff --git a/sys/gnu/dts/arm/armada-375.dtsi b/sys/gnu/dts/arm/armada-375.dtsi
index 7ccce7529b0c..cc952cf8ec30 100644
--- a/sys/gnu/dts/arm/armada-375.dtsi
+++ b/sys/gnu/dts/arm/armada-375.dtsi
@@ -529,7 +529,7 @@
 			};
 
 			sata@a0000 {
-				compatible = "marvell,orion-sata";
+				compatible = "marvell,armada-370-sata";
 				reg = <0xa0000 0x5000>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&gateclk 14>, <&gateclk 20>;
diff --git a/sys/gnu/dts/arm/armada-385-db-ap.dts b/sys/gnu/dts/arm/armada-385-db-ap.dts
index acd5b1519edb..2d3fd6e76e2c 100644
--- a/sys/gnu/dts/arm/armada-385-db-ap.dts
+++ b/sys/gnu/dts/arm/armada-385-db-ap.dts
@@ -61,7 +61,8 @@
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
 			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
-			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
 
 		internal-regs {
 			spi1: spi@10680 {
@@ -134,18 +135,27 @@
 				};
 			};
 
+			/* CON3 */
 			ethernet@30000 {
 				status = "okay";
 				phy = <&phy2>;
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <1>;
+				bm,pool-short = <3>;
 			};
 
+			/* CON2 */
 			ethernet@34000 {
 				status = "okay";
 				phy = <&phy1>;
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <2>;
+				bm,pool-short = <3>;
 			};
 
+			/* CON4 */
 			ethernet@70000 {
 				pinctrl-names = "default";
 
@@ -157,6 +167,13 @@
 				status = "okay";
 				phy = <&phy0>;
 				phy-mode = "rgmii-id";
+				buffer-manager = <&bm>;
+				bm,pool-long = <0>;
+				bm,pool-short = <3>;
+			};
+
+			bm@c8000 {
+				status = "okay";
 			};
 
 			nfc: flash@d0000 {
@@ -178,6 +195,10 @@
 			};
 		};
 
+		bm-bppi {
+			status = "okay";
+		};
+
 		pcie-controller {
 			status = "okay";
 
diff --git a/sys/gnu/dts/arm/armada-385-linksys.dtsi b/sys/gnu/dts/arm/armada-385-linksys.dtsi
index 3710755c6d76..22f7a13e20b4 100644
--- a/sys/gnu/dts/arm/armada-385-linksys.dtsi
+++ b/sys/gnu/dts/arm/armada-385-linksys.dtsi
@@ -58,8 +58,8 @@
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
-			  MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
+			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
 
 		internal-regs {
 
@@ -117,7 +117,7 @@
 			};
 
 			/* USB part of the eSATA/USB 2.0 port */
-			usb@50000 {
+			usb@58000 {
 				status = "okay";
 			};
 
@@ -245,7 +245,7 @@
 		button@2 {
 			label = "Factory Reset Button";
 			linux,code = <KEY_RESTART>;
-			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
 		};
 	};
 
@@ -260,7 +260,7 @@
 		};
 
 		sata {
-			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
 	};
@@ -313,7 +313,7 @@
 
 &pinctrl {
 	keys_pin: keys-pin {
-		marvell,pins = "mpp24", "mpp47";
+		marvell,pins = "mpp24", "mpp29";
 		marvell,function = "gpio";
 	};
 
diff --git a/sys/gnu/dts/arm/armada-388-clearfog.dts b/sys/gnu/dts/arm/armada-388-clearfog.dts
index c6e180eb3b11..c60206efb583 100644
--- a/sys/gnu/dts/arm/armada-388-clearfog.dts
+++ b/sys/gnu/dts/arm/armada-388-clearfog.dts
@@ -78,6 +78,9 @@
 		internal-regs {
 			ethernet@30000 {
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <2>;
+				bm,pool-short = <1>;
 				status = "okay";
 
 				fixed-link {
@@ -88,6 +91,9 @@
 
 			ethernet@34000 {
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <3>;
+				bm,pool-short = <1>;
 				status = "okay";
 
 				fixed-link {
diff --git a/sys/gnu/dts/arm/armada-388-db.dts b/sys/gnu/dts/arm/armada-388-db.dts
index ff47af57f091..ea93ed727030 100644
--- a/sys/gnu/dts/arm/armada-388-db.dts
+++ b/sys/gnu/dts/arm/armada-388-db.dts
@@ -66,7 +66,8 @@
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
 			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
-			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
 
 		internal-regs {
 			spi@10600 {
@@ -99,6 +100,9 @@
 				status = "okay";
 				phy = <&phy1>;
 				phy-mode = "rgmii-id";
+				buffer-manager = <&bm>;
+				bm,pool-long = <2>;
+				bm,pool-short = <3>;
 			};
 
 			usb@58000 {
@@ -109,6 +113,9 @@
 				status = "okay";
 				phy = <&phy0>;
 				phy-mode = "rgmii-id";
+				buffer-manager = <&bm>;
+				bm,pool-long = <0>;
+				bm,pool-short = <1>;
 			};
 
 			mdio@72004 {
@@ -129,6 +136,10 @@
 				status = "okay";
 			};
 
+			bm@c8000 {
+				status = "okay";
+			};
+
 			flash@d0000 {
 				status = "okay";
 				num-cs = <1>;
@@ -169,6 +180,10 @@
 			};
 		};
 
+		bm-bppi {
+			status = "okay";
+		};
+
 		pcie-controller {
 			status = "okay";
 			/*
diff --git a/sys/gnu/dts/arm/armada-388-gp.dts b/sys/gnu/dts/arm/armada-388-gp.dts
index cd316021d6ce..fd75e5e9550f 100644
--- a/sys/gnu/dts/arm/armada-388-gp.dts
+++ b/sys/gnu/dts/arm/armada-388-gp.dts
@@ -44,8 +44,8 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-	model = "Marvell Armada 385 GP";
-	compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
+	model = "Marvell Armada 388 DB-88F6820-GP";
+	compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";
 
 	chosen {
 		stdout-path = "serial0:115200n8";
@@ -60,7 +60,8 @@
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
 			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
-			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
 
 		internal-regs {
 			spi@10600 {
@@ -133,6 +134,9 @@
 				status = "okay";
 				phy = <&phy1>;
 				phy-mode = "rgmii-id";
+				buffer-manager = <&bm>;
+				bm,pool-long = <2>;
+				bm,pool-short = <3>;
 			};
 
 			/* CON4 */
@@ -152,6 +156,9 @@
 				status = "okay";
 				phy = <&phy0>;
 				phy-mode = "rgmii-id";
+				buffer-manager = <&bm>;
+				bm,pool-long = <0>;
+				bm,pool-short = <1>;
 			};
 
 
@@ -186,6 +193,10 @@
 				};
 			};
 
+			bm@c8000 {
+				status = "okay";
+			};
+
 			sata@e0000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
@@ -229,17 +240,21 @@
 
 			/* CON5 */
 			usb3@f0000 {
-				vcc-supply = <&reg_usb2_1_vbus>;
+				usb-phy = <&usb2_1_phy>;
 				status = "okay";
 			};
 
 			/* CON7 */
 			usb3@f8000 {
-				vcc-supply = <&reg_usb3_vbus>;
+				usb-phy = <&usb3_phy>;
 				status = "okay";
 			};
 		};
 
+		bm-bppi {
+			status = "okay";
+		};
+
 		pcie-controller {
 			status = "okay";
 			/*
@@ -273,13 +288,22 @@
 		};
 	};
 
+	usb2_1_phy: usb2_1_phy {
+		compatible = "usb-nop-xceiv";
+		vcc-supply = <&reg_usb2_1_vbus>;
+	};
+
+	usb3_phy: usb3_phy {
+		compatible = "usb-nop-xceiv";
+		vcc-supply = <&reg_usb3_vbus>;
+	};
+
 	reg_usb3_vbus: usb3-vbus {
 		compatible = "regulator-fixed";
 		regulator-name = "usb3-vbus";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 		enable-active-high;
-		regulator-always-on;
 		gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
 	};
 
@@ -299,7 +323,6 @@
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 		enable-active-high;
-		regulator-always-on;
 		gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
 	};
 
@@ -309,7 +332,7 @@
 		regulator-min-microvolt = <12000000>;
 		regulator-max-microvolt = <12000000>;
 		enable-active-high;
-		regulator-always-on;
+		regulator-boot-on;
 		gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
 	};
 
@@ -318,7 +341,6 @@
 		regulator-name = "v5.0-sata0";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
 		vin-supply = <&reg_sata0>;
 	};
 
@@ -327,7 +349,6 @@
 		regulator-name = "v12.0-sata0";
 		regulator-min-microvolt = <12000000>;
 		regulator-max-microvolt = <12000000>;
-		regulator-always-on;
 		vin-supply = <&reg_sata0>;
 	};
 
@@ -337,7 +358,7 @@
 		regulator-min-microvolt = <12000000>;
 		regulator-max-microvolt = <12000000>;
 		enable-active-high;
-		regulator-always-on;
+		regulator-boot-on;
 		gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
 	};
 
@@ -346,7 +367,6 @@
 		regulator-name = "v5.0-sata1";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
 		vin-supply = <&reg_sata1>;
 	};
 
@@ -355,7 +375,6 @@
 		regulator-name = "v12.0-sata1";
 		regulator-min-microvolt = <12000000>;
 		regulator-max-microvolt = <12000000>;
-		regulator-always-on;
 		vin-supply = <&reg_sata1>;
 	};
 
@@ -363,7 +382,7 @@
 		compatible = "regulator-fixed";
 		regulator-name = "pwr_en_sata2";
 		enable-active-high;
-		regulator-always-on;
+		regulator-boot-on;
 		gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
 	};
 
@@ -372,7 +391,6 @@
 		regulator-name = "v5.0-sata2";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
 		vin-supply = <&reg_sata2>;
 	};
 
@@ -381,7 +399,6 @@
 		regulator-name = "v12.0-sata2";
 		regulator-min-microvolt = <12000000>;
 		regulator-max-microvolt = <12000000>;
-		regulator-always-on;
 		vin-supply = <&reg_sata2>;
 	};
 
@@ -389,7 +406,7 @@
 		compatible = "regulator-fixed";
 		regulator-name = "pwr_en_sata3";
 		enable-active-high;
-		regulator-always-on;
+		regulator-boot-on;
 		gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
 	};
 
@@ -398,7 +415,6 @@
 		regulator-name = "v5.0-sata3";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
 		vin-supply = <&reg_sata3>;
 	};
 
@@ -407,7 +423,6 @@
 		regulator-name = "v12.0-sata3";
 		regulator-min-microvolt = <12000000>;
 		regulator-max-microvolt = <12000000>;
-		regulator-always-on;
 		vin-supply = <&reg_sata3>;
 	};
 };
diff --git a/sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi b/sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi
index 3f792a563c05..8c9842237b60 100644
--- a/sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi
+++ b/sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi
@@ -58,7 +58,8 @@
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
 			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
-			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
 
 		internal-regs {
 			ethernet@70000 {
@@ -66,6 +67,9 @@
 				pinctrl-names = "default";
 				phy = <&phy_dedicated>;
 				phy-mode = "rgmii-id";
+				buffer-manager = <&bm>;
+				bm,pool-long = <0>;
+				bm,pool-short = <1>;
 				status = "okay";
 			};
 
@@ -110,6 +114,15 @@
 				pinctrl-names = "default";
 				status = "okay";
 			};
+
+			bm@c8000 {
+				status = "okay";
+			};
 		};
+
+		bm-bppi {
+			status = "okay";
+		};
+
 	};
 };
diff --git a/sys/gnu/dts/arm/armada-38x.dtsi b/sys/gnu/dts/arm/armada-38x.dtsi
index e8b7f6726772..3312be6c82cc 100644
--- a/sys/gnu/dts/arm/armada-38x.dtsi
+++ b/sys/gnu/dts/arm/armada-38x.dtsi
@@ -429,6 +429,27 @@
 				reg = <0x22000 0x1000>;
 			};
 
+			/*
+			 * As a special exception to the "order by
+			 * register address" rule, the eth0 node is
+			 * placed here to ensure that it gets
+			 * registered as the first interface, since
+			 * the network subsystem doesn't allow naming
+			 * interfaces using DT aliases. Without this,
+			 * the ordering of interfaces is different
+			 * from the one used in U-Boot and the
+			 * labeling of interfaces on the boards, which
+			 * is very confusing for users.
+			 */
+			eth0: ethernet@70000 {
+				compatible = "marvell,armada-370-neta";
+				reg = <0x70000 0x4000>;
+				interrupts-extended = <&mpic 8>;
+				clocks = <&gateclk 4>;
+				tx-csum-limit = <9800>;
+				status = "disabled";
+			};
+
 			eth1: ethernet@30000 {
 				compatible = "marvell,armada-370-neta";
 				reg = <0x30000 0x4000>;
@@ -493,15 +514,6 @@
 				};
 			};
 
-			eth0: ethernet@70000 {
-				compatible = "marvell,armada-370-neta";
-				reg = <0x70000 0x4000>;
-				interrupts-extended = <&mpic 8>;
-				clocks = <&gateclk 4>;
-				tx-csum-limit = <9800>;
-				status = "disabled";
-			};
-
 			mdio: mdio@72004 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -540,6 +552,14 @@
 				status = "disabled";
 			};
 
+			bm: bm@c8000 {
+				compatible = "marvell,armada-380-neta-bm";
+				reg = <0xc8000 0xac>;
+				clocks = <&gateclk 13>;
+				internal-mem = <&bm_bppi>;
+				status = "disabled";
+			};
+
 			sata@e0000 {
 				compatible = "marvell,armada-380-ahci";
 				reg = <0xe0000 0x2000>;
@@ -618,6 +638,17 @@
 			#size-cells = <1>;
 			ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
 		};
+
+		bm_bppi: bm-bppi {
+			compatible = "mmio-sram";
+			reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
+			ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&gateclk 13>;
+			no-memory-wc;
+			status = "disabled";
+		};
 	};
 
 	clocks {
diff --git a/sys/gnu/dts/arm/armada-xp-axpwifiap.dts b/sys/gnu/dts/arm/armada-xp-axpwifiap.dts
index 23fc670c0427..5c21b236721f 100644
--- a/sys/gnu/dts/arm/armada-xp-axpwifiap.dts
+++ b/sys/gnu/dts/arm/armada-xp-axpwifiap.dts
@@ -70,8 +70,8 @@
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
-			  MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
+			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
 		pcie-controller {
 			status = "okay";
diff --git a/sys/gnu/dts/arm/armada-xp-db.dts b/sys/gnu/dts/arm/armada-xp-db.dts
index f774101416a5..62422a90aeb2 100644
--- a/sys/gnu/dts/arm/armada-xp-db.dts
+++ b/sys/gnu/dts/arm/armada-xp-db.dts
@@ -76,8 +76,9 @@
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
 			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
-			  MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
-			  MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
+			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
+			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
 
 		devbus-bootcs {
 			status = "okay";
@@ -181,21 +182,33 @@
 				status = "okay";
 				phy = <&phy0>;
 				phy-mode = "rgmii-id";
+				buffer-manager = <&bm>;
+				bm,pool-long = <0>;
 			};
 			ethernet@74000 {
 				status = "okay";
 				phy = <&phy1>;
 				phy-mode = "rgmii-id";
+				buffer-manager = <&bm>;
+				bm,pool-long = <1>;
 			};
 			ethernet@30000 {
 				status = "okay";
 				phy = <&phy2>;
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <2>;
 			};
 			ethernet@34000 {
 				status = "okay";
 				phy = <&phy3>;
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <3>;
+			};
+
+			bm@c0000 {
+				status = "okay";
 			};
 
 			mvsdio@d4000 {
@@ -229,6 +242,38 @@
 					spi-max-frequency = <20000000>;
 				};
 			};
+
+			nand@d0000 {
+				status = "okay";
+				num-cs = <1>;
+				marvell,nand-keep-config;
+				marvell,nand-enable-arbiter;
+				nand-on-flash-bbt;
+
+				partitions {
+					compatible = "fixed-partitions";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					partition@0 {
+						label = "U-Boot";
+						reg = <0 0x800000>;
+					};
+					partition@800000 {
+						label = "Linux";
+						reg = <0x800000 0x800000>;
+					};
+					partition@1000000 {
+						label = "Filesystem";
+						reg = <0x1000000 0x3f000000>;
+
+					};
+				};
+			};
+		};
+
+		bm-bppi {
+			status = "okay";
 		};
 	};
 };
diff --git a/sys/gnu/dts/arm/armada-xp-gp.dts b/sys/gnu/dts/arm/armada-xp-gp.dts
index 4878d7353069..061f4237760e 100644
--- a/sys/gnu/dts/arm/armada-xp-gp.dts
+++ b/sys/gnu/dts/arm/armada-xp-gp.dts
@@ -95,8 +95,9 @@
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
 			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
-			  MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
-			  MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
+			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
+			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
 
 		devbus-bootcs {
 			status = "okay";
@@ -196,21 +197,29 @@
 				status = "okay";
 				phy = <&phy0>;
 				phy-mode = "qsgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <0>;
 			};
 			ethernet@74000 {
 				status = "okay";
 				phy = <&phy1>;
 				phy-mode = "qsgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <1>;
 			};
 			ethernet@30000 {
 				status = "okay";
 				phy = <&phy2>;
 				phy-mode = "qsgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <2>;
 			};
 			ethernet@34000 {
 				status = "okay";
 				phy = <&phy3>;
 				phy-mode = "qsgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <3>;
 			};
 
 			/* Front-side USB slot */
@@ -235,6 +244,10 @@
 				};
 			};
 
+			bm@c0000 {
+				status = "okay";
+			};
+
 			nand@d0000 {
 				status = "okay";
 				num-cs = <1>;
@@ -243,5 +256,9 @@
 				nand-on-flash-bbt;
 			};
 		};
+
+		bm-bppi {
+			status = "okay";
+		};
 	};
 };
diff --git a/sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts b/sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts
index 13cf69a8d0fb..8af463f26ea1 100644
--- a/sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts
+++ b/sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts
@@ -65,8 +65,8 @@
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
 			MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-			MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
-			MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
+			MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+			MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
 		pcie-controller {
 			status = "okay";
@@ -152,6 +152,7 @@
 				nand-on-flash-bbt;
 
 				partitions {
+					compatible = "fixed-partitions";
 					#address-cells = <1>;
 					#size-cells = <1>;
 
diff --git a/sys/gnu/dts/arm/armada-xp-linksys-mamba.dts b/sys/gnu/dts/arm/armada-xp-linksys-mamba.dts
index 6e9820e141f8..7a461541ce50 100644
--- a/sys/gnu/dts/arm/armada-xp-linksys-mamba.dts
+++ b/sys/gnu/dts/arm/armada-xp-linksys-mamba.dts
@@ -70,8 +70,8 @@
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
-			  MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
+			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
 		pcie-controller {
 			status = "okay";
@@ -304,13 +304,13 @@
 		button@1 {
 			label = "WPS";
 			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 		};
 
 		button@2 {
 			label = "Factory Reset Button";
 			linux,code = <KEY_RESTART>;
-			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/armada-xp-matrix.dts b/sys/gnu/dts/arm/armada-xp-matrix.dts
index 6ab33837a2b6..6522b04f4a8e 100644
--- a/sys/gnu/dts/arm/armada-xp-matrix.dts
+++ b/sys/gnu/dts/arm/armada-xp-matrix.dts
@@ -68,8 +68,8 @@
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
-			  MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
+			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
 		internal-regs {
 			serial@12000 {
diff --git a/sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts b/sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts
index 62175a8848bc..d19f44c70925 100644
--- a/sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts
+++ b/sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts
@@ -64,8 +64,8 @@
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
-			  MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
+			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
 		pcie-controller {
 			status = "okay";
diff --git a/sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts b/sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts
index a5db17782e08..ed3b889d16ce 100644
--- a/sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts
+++ b/sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts
@@ -65,9 +65,10 @@
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000
-			  MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
-			  MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
+			  MBUS_ID(0x01, 0x2f) 0 0 0xe8000000 0x8000000
+			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
+			  MBUS_ID(0x0c, 0x04) 0 0 0xd1200000 0x100000>;
 
 		devbus-bootcs {
 			status = "okay";
@@ -176,21 +177,29 @@
 				status = "okay";
 				phy = <&phy0>;
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <0>;
 			};
 			ethernet@74000 {
 				status = "okay";
 				phy = <&phy1>;
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <1>;
 			};
 			ethernet@30000 {
 				status = "okay";
 				phy = <&phy2>;
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <2>;
 			};
 			ethernet@34000 {
 				status = "okay";
 				phy = <&phy3>;
 				phy-mode = "sgmii";
+				buffer-manager = <&bm>;
+				bm,pool-long = <3>;
 			};
 			i2c@11000 {
 				status = "okay";
@@ -219,6 +228,14 @@
 			usb@51000 {
 				status = "okay";
 			};
+
+			bm@c0000 {
+				status = "okay";
+			};
+		};
+
+		bm-bppi {
+			status = "okay";
 		};
 	};
 };
diff --git a/sys/gnu/dts/arm/armada-xp-synology-ds414.dts b/sys/gnu/dts/arm/armada-xp-synology-ds414.dts
index 2391b11dc546..d17dab0a6f51 100644
--- a/sys/gnu/dts/arm/armada-xp-synology-ds414.dts
+++ b/sys/gnu/dts/arm/armada-xp-synology-ds414.dts
@@ -78,8 +78,8 @@
 	soc {
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
-			  MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
-			  MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
+			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
 
 		pcie-controller {
 			status = "okay";
diff --git a/sys/gnu/dts/arm/armada-xp.dtsi b/sys/gnu/dts/arm/armada-xp.dtsi
index be23196829bb..553349c07f28 100644
--- a/sys/gnu/dts/arm/armada-xp.dtsi
+++ b/sys/gnu/dts/arm/armada-xp.dtsi
@@ -253,6 +253,14 @@
 				marvell,crypto-sram-size = <0x800>;
 			};
 
+			bm: bm@c0000 {
+				compatible = "marvell,armada-380-neta-bm";
+				reg = <0xc0000 0xac>;
+				clocks = <&gateclk 13>;
+				internal-mem = <&bm_bppi>;
+				status = "disabled";
+			};
+
 			xor@f0900 {
 				compatible = "marvell,orion-xor";
 				reg = <0xF0900 0x100
@@ -291,6 +299,17 @@
 			#size-cells = <1>;
 			ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
 		};
+
+		bm_bppi: bm-bppi {
+			compatible = "mmio-sram";
+			reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
+			ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&gateclk 13>;
+			no-memory-wc;
+			status = "disabled";
+		};
 	};
 
 	clocks {
diff --git a/sys/gnu/dts/arm/armv7-m.dtsi b/sys/gnu/dts/arm/armv7-m.dtsi
index b1ad7cf6ac02..16331aa79775 100644
--- a/sys/gnu/dts/arm/armv7-m.dtsi
+++ b/sys/gnu/dts/arm/armv7-m.dtsi
@@ -1,7 +1,7 @@
 #include "skeleton.dtsi"
 
 / {
-	nvic: nv-interrupt-controller  {
+	nvic: interrupt-controller@e000e100  {
 		compatible = "arm,armv7m-nvic";
 		interrupt-controller;
 		#interrupt-cells = <1>;
diff --git a/sys/gnu/dts/arm/artpec6-devboard.dts b/sys/gnu/dts/arm/artpec6-devboard.dts
new file mode 100644
index 000000000000..f823ed382ac7
--- /dev/null
+++ b/sys/gnu/dts/arm/artpec6-devboard.dts
@@ -0,0 +1,64 @@
+/*
+ * Axis ARTPEC-6 development board.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "artpec6.dtsi"
+
+/ {
+	model = "ARTPEC-6 development board";
+	compatible = "axis,artpec6-dev-board", "axis,artpec6";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial3:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&ethernet {
+	status = "okay";
+
+	phy-handle = <&phy1>;
+	phy-mode = "gmii";
+
+	mdio {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		phy1: phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			device_type = "ethernet-phy";
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/artpec6.dtsi b/sys/gnu/dts/arm/artpec6.dtsi
new file mode 100644
index 000000000000..3fac4c4d0007
--- /dev/null
+++ b/sys/gnu/dts/arm/artpec6.dtsi
@@ -0,0 +1,211 @@
+/*
+ * Device Tree Source for the Axis ARTPEC-6 SoC
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "axis,artpec6";
+	interrupt-parent = <&intc>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+			next-level-cache = <&pl310>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+			next-level-cache = <&pl310>;
+		};
+	};
+
+	syscon {
+		compatible = "axis,artpec6-syscon", "syscon";
+		reg = <0xf8000000 0x48>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2", "arm,psci";
+		method = "smc";
+		psci_version = <0x84000000>;
+		cpu_on = <0x84000003>;
+		system_reset = <0x84000009>;
+	};
+
+	scu@faf00000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0xfaf00000 0x58>;
+	};
+
+	/* Main external clock driving CPU and peripherals */
+	ext_clk: ext_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+	};
+
+	eth_phy_ref_clk: eth_phy_ref_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+	};
+
+	clkctrl: clkctrl@0xf8000000 {
+		#clock-cells = <1>;
+		compatible = "axis,artpec6-clkctrl";
+		reg = <0xf8000000 0x48>;
+		clocks = <&ext_clk>;
+		clock-names = "sys_refclk";
+	};
+
+	gtimer@faf00200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0xfaf00200 0x20>;
+		interrupts = <GIC_PPI 11 0xf01>;
+		clocks = <&clkctrl 1>;
+	};
+
+	timer@faf00600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0xfaf00600 0x20>;
+		interrupts = <GIC_PPI 13 0xf04>;
+		clocks = <&clkctrl 1>;
+		status = "disabled";
+	};
+
+	intc: interrupt-controller@faf01000 {
+		interrupt-controller;
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
+	};
+
+	pl310: cache-controller@faf10000 {
+		compatible = "arm,pl310-cache";
+		cache-unified;
+		cache-level = <2>;
+		reg = <0xfaf10000 0x1000>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		arm,data-latency = <1 1 1>;
+		arm,tag-latency = <1 1 1>;
+		arm,filter-ranges = <0x0 0x80000000>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&intc>;
+	};
+
+	amba@0 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		interrupt-parent = <&intc>;
+		ranges;
+		dma-ranges = <0x80000000 0x00000000 0x40000000>;
+		dma-coherent;
+
+		ethernet: ethernet@f8010000 {
+			clock-names = "phy_ref_clk", "apb_pclk";
+			clocks = <&eth_phy_ref_clk>,
+				<&clkctrl 4>;
+			compatible = "snps,dwc-qos-ethernet-4.10";
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf8010000 0x4000>;
+
+			snps,write-requests = <2>;
+			snps,read-requests = <16>;
+			snps,txpbl = <8>;
+			snps,rxpbl = <2>;
+
+			status = "disabled";
+		};
+
+		uart0: serial@f8036000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xf8036000 0x1000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkctrl 13>,
+				<&clkctrl 12>;
+			clock-names = "uart_clk", "apb_pclk";
+			status = "disabled";
+		};
+		uart1: serial@f8037000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xf8037000 0x1000>;
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkctrl 13>,
+				<&clkctrl 12>;
+			clock-names = "uart_clk", "apb_pclk";
+			status = "disabled";
+		};
+		uart2: serial@f8038000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xf8038000 0x1000>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkctrl 13>,
+				<&clkctrl 12>;
+			clock-names = "uart_clk", "apb_pclk";
+			status = "disabled";
+		};
+		uart3: serial@f8039000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xf8039000 0x1000>;
+			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkctrl 13>,
+				<&clkctrl 12>;
+			clock-names = "uart_clk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/aspeed-ast2500-evb.dts b/sys/gnu/dts/arm/aspeed-ast2500-evb.dts
new file mode 100644
index 000000000000..1b7a5ff0e533
--- /dev/null
+++ b/sys/gnu/dts/arm/aspeed-ast2500-evb.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+
+/ {
+	model = "AST2500 EVB";
+	compatible = "aspeed,ast2500";
+
+	aliases {
+		serial4 = &uart5;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+		bootargs = "console=ttyS4,115200 earlyprintk";
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+};
+
+&uart5 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts b/sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts
new file mode 100644
index 000000000000..cc5fcf2940bf
--- /dev/null
+++ b/sys/gnu/dts/arm/aspeed-bmc-opp-palmetto.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+
+#include "aspeed-g4.dtsi"
+
+/ {
+	model = "Palmetto BMC";
+	compatible = "tyan,palmetto-bmc", "aspeed,ast2400";
+
+	aliases {
+		serial4 = &uart5;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+		bootargs = "console=ttyS4,38400 earlyprintk";
+	};
+
+	memory {
+		reg = <0x40000000 0x10000000>;
+	};
+};
+
+&uart5 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/aspeed-g4.dtsi b/sys/gnu/dts/arm/aspeed-g4.dtsi
new file mode 100644
index 000000000000..22dee5937d5c
--- /dev/null
+++ b/sys/gnu/dts/arm/aspeed-g4.dtsi
@@ -0,0 +1,161 @@
+#include "skeleton.dtsi"
+
+/ {
+	model = "Aspeed BMC";
+	compatible = "aspeed,ast2400";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&vic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		clk_clkin: clk_clkin {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <48000000>;
+		};
+
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		vic: interrupt-controller@1e6c0080 {
+			compatible = "aspeed,ast2400-vic";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			valid-sources = <0xffffffff 0x0007ffff>;
+			reg = <0x1e6c0080 0x80>;
+		};
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clk_hpll: clk_hpll@1e6e2070 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g4-hpll-clock";
+				reg = <0x1e6e2070 0x4>;
+				clocks = <&clk_clkin>;
+			};
+
+			clk_apb: clk_apb@1e6e2008 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g4-apb-clock";
+				reg = <0x1e6e2008 0x4>;
+				clocks = <&clk_hpll>;
+			};
+
+			clk_uart: clk_uart@1e6e2008 {
+				#clock-cells = <0>;
+				compatible = "aspeed,uart-clock";
+				reg = <0x1e6e202c 0x4>;
+			};
+
+			sram@1e720000 {
+				compatible = "mmio-sram";
+				reg = <0x1e720000 0x8000>;	// 32K
+			};
+
+			timer: timer@1e782000 {
+				compatible = "aspeed,ast2400-timer";
+				reg = <0x1e782000 0x90>;
+				// The moxart_timer driver registers only one
+				// interrupt and assumes it's for timer 1
+				//interrupts = <16 17 18 35 36 37 38 39>;
+				interrupts = <16>;
+				clocks = <&clk_apb>;
+			};
+
+			wdt1: wdt@1e785000 {
+				compatible = "aspeed,wdt";
+				reg = <0x1e785000 0x1c>;
+				interrupts = <27>;
+			};
+
+			wdt2: wdt@1e785020 {
+				compatible = "aspeed,wdt";
+				reg = <0x1e785020 0x1c>;
+				interrupts = <27>;
+				clocks = <&clk_apb>;
+				status = "disabled";
+			};
+
+			uart1: serial@1e783000 {
+				compatible = "ns16550a";
+				reg = <0x1e783000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <9>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart2: serial@1e78d000 {
+				compatible = "ns16550a";
+				reg = <0x1e78d000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <32>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart3: serial@1e78e000 {
+				compatible = "ns16550a";
+				reg = <0x1e78e000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <33>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart4: serial@1e78f000 {
+				compatible = "ns16550a";
+				reg = <0x1e78f000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <34>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart5: serial@1e784000 {
+				compatible = "ns16550a";
+				reg = <0x1e784000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <10>;
+				clocks = <&clk_uart>;
+				current-speed = <38400>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart6: serial@1e787000 {
+				compatible = "ns16550a";
+				reg = <0x1e787000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <10>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/aspeed-g5.dtsi b/sys/gnu/dts/arm/aspeed-g5.dtsi
new file mode 100644
index 000000000000..dd94d9361fda
--- /dev/null
+++ b/sys/gnu/dts/arm/aspeed-g5.dtsi
@@ -0,0 +1,170 @@
+#include "skeleton.dtsi"
+
+/ {
+	model = "Aspeed BMC";
+	compatible = "aspeed,ast2500";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&vic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,arm1176jzf-s";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		vic: interrupt-controller@1e6c0080 {
+			compatible = "aspeed,ast2400-vic";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			valid-sources = <0xfefff7ff 0x0807ffff>;
+			reg = <0x1e6c0080 0x80>;
+		};
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clk_clkin: clk_clkin@1e6e2070 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g5-clkin-clock";
+				reg = <0x1e6e2070 0x04>;
+			};
+
+			clk_hpll: clk_hpll@1e6e2024 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g5-hpll-clock";
+				reg = <0x1e6e2024 0x4>;
+				clocks = <&clk_clkin>;
+			};
+
+			clk_ahb: clk_ahb@1e6e2070 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g5-ahb-clock";
+				reg = <0x1e6e2070 0x4>;
+				clocks = <&clk_hpll>;
+			};
+
+			clk_apb: clk_apb@1e6e2008 {
+				#clock-cells = <0>;
+				compatible = "aspeed,g5-apb-clock";
+				reg = <0x1e6e2008 0x4>;
+				clocks = <&clk_hpll>;
+			};
+
+			clk_uart: clk_uart@1e6e2008 {
+				#clock-cells = <0>;
+				compatible = "aspeed,uart-clock";
+				reg = <0x1e6e202c 0x4>;
+			};
+
+			sram@1e720000 {
+				compatible = "mmio-sram";
+				reg = <0x1e720000 0x9000>;	// 36K
+			};
+
+			timer: timer@1e782000 {
+				compatible = "aspeed,ast2400-timer";
+				reg = <0x1e782000 0x90>;
+				// The moxart_timer driver registers only one
+				// interrupt and assumes it's for timer 1
+				//interrupts = <16 17 18 35 36 37 38 39>;
+				interrupts = <16>;
+				clocks = <&clk_apb>;
+			};
+
+			wdt1: wdt@1e785000 {
+				compatible = "aspeed,wdt";
+				reg = <0x1e785000 0x1c>;
+				interrupts = <27>;
+			};
+
+			wdt2: wdt@1e785020 {
+				compatible = "aspeed,wdt";
+				reg = <0x1e785020 0x1c>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			wdt3: wdt@1e785040 {
+				compatible = "aspeed,wdt";
+				reg = <0x1e785074 0x1c>;
+				status = "disabled";
+			};
+
+			uart1: serial@1e783000 {
+				compatible = "ns16550a";
+				reg = <0x1e783000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <9>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart2: serial@1e78d000 {
+				compatible = "ns16550a";
+				reg = <0x1e78d000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <32>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart3: serial@1e78e000 {
+				compatible = "ns16550a";
+				reg = <0x1e78e000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <33>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart4: serial@1e78f000 {
+				compatible = "ns16550a";
+				reg = <0x1e78f000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <34>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart5: serial@1e784000 {
+				compatible = "ns16550a";
+				reg = <0x1e784000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <10>;
+				clocks = <&clk_uart>;
+				current-speed = <38400>;
+				no-loopback-test;
+				status = "disabled";
+			};
+
+			uart6: serial@1e787000 {
+				compatible = "ns16550a";
+				reg = <0x1e787000 0x1000>;
+				reg-shift = <2>;
+				interrupts = <10>;
+				clocks = <&clk_uart>;
+				no-loopback-test;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/at91-sama5d2_xplained.dts b/sys/gnu/dts/arm/at91-sama5d2_xplained.dts
index 77ddff036409..eb4f1ac96271 100644
--- a/sys/gnu/dts/arm/at91-sama5d2_xplained.dts
+++ b/sys/gnu/dts/arm/at91-sama5d2_xplained.dts
@@ -46,6 +46,7 @@
 #include "sama5d2.dtsi"
 #include "sama5d2-pinfunc.h"
 #include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Atmel SAMA5D2 Xplained";
@@ -71,11 +72,20 @@
 
 	ahb {
 		usb0: gadget@00300000 {
+			atmel,vbus-gpio = <&pioA 31 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usba_vbus>;
 			status = "okay";
 		};
 
 		usb1: ohci@00400000 {
 			num-ports = <3>;
+			atmel,vbus-gpio = <0 /* &pioA 41 GPIO_ACTIVE_HIGH */
+					   &pioA 42 GPIO_ACTIVE_HIGH
+					   0
+					  >;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb_default>;
 			status = "okay";
 		};
 
@@ -114,9 +124,15 @@
 
 			macb0: ethernet@f8008000 {
 				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_macb0_default>;
+				pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
 				phy-mode = "rmii";
 				status = "okay";
+
+				ethernet-phy@1 {
+					reg = <0x1>;
+					interrupt-parent = <&pioA>;
+					interrupts = <73 IRQ_TYPE_LEVEL_LOW>;
+				};
 			};
 
 			pdmic@f8018000 {
@@ -218,6 +234,15 @@
 				};
 			};
 
+			shdwc@f8048010 {
+				atmel,shdwc-debouncer = <976>;
+
+				input@0 {
+					reg = <0>;
+					atmel,wakeup-type = "low";
+				};
+			};
+
 			watchdog@f8048040 {
 				status = "okay";
 			};
@@ -261,7 +286,29 @@
 				};
 			};
 
+			adc: adc@fc030000 {
+				vddana-supply = <&vdd_3v3_lp_reg>;
+				vref-supply = <&vdd_3v3_lp_reg>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_adc_default>;
+				status = "okay";
+			};
+
 			pinctrl@fc038000 {
+				/*
+				 * There is no real pinmux for ADC, if the pin
+				 * is not requested by another peripheral then
+				 * the muxing is done when channel is enabled.
+				 * Requesting pins for ADC is GPIO is
+				 * encouraged to prevent conflicts and to
+				 * disable bias in order to be in the same
+				 * state when the pin is not muxed to the adc.
+				 */
+				pinctrl_adc_default: adc_default {
+					pinmux = <PIN_PD23__GPIO>;
+					bias-disable;
+				};
+
 				pinctrl_flx0_default: flx0_default {
 					pinmux = <PIN_PB28__FLEXCOM0_IO0>,
 						 <PIN_PB29__FLEXCOM0_IO1>;
@@ -286,6 +333,18 @@
 					bias-disable;
 				};
 
+				pinctrl_key_gpio_default: key_gpio_default {
+					pinmux = <PIN_PB9__GPIO>;
+					bias-pull-up;
+				};
+
+				pinctrl_led_gpio_default: led_gpio_default {
+					pinmux = <PIN_PB0__GPIO>,
+						 <PIN_PB5__GPIO>,
+						 <PIN_PB6__GPIO>;
+					bias-pull-up;
+				};
+
 				pinctrl_macb0_default: macb0_default {
 					pinmux = <PIN_PB14__GTXCK>,
 						 <PIN_PB15__GTXEN>,
@@ -300,6 +359,11 @@
 					bias-disable;
 				};
 
+				pinctrl_macb0_phy_irq: macb0_phy_irq {
+					pinmux = <PIN_PC9__GPIO>;
+					bias-disable;
+				};
+
 				pinctrl_pdmic_default: pdmic_default {
 					pinmux = <PIN_PB26__PDMIC_DAT>,
 						<PIN_PB27__PDMIC_CLK>;
@@ -365,7 +429,54 @@
 						 <PIN_PB12__UTXD3>;
 					bias-disable;
 				};
+
+				pinctrl_usb_default: usb_default {
+					pinmux = <PIN_PB10__GPIO>;
+					bias-disable;
+				};
+
+				pinctrl_usba_vbus: usba_vbus {
+					pinmux = <PIN_PA31__GPIO>;
+					bias-disable;
+				};
+
 			};
 		};
 	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+		bp1 {
+			label = "PB_USER";
+			gpios = <&pioA 41 GPIO_ACTIVE_LOW>;
+			linux,code = <0x104>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_led_gpio_default>;
+		status = "okay";
+
+		red {
+			label = "red";
+			gpios = <&pioA 38 GPIO_ACTIVE_LOW>;
+		};
+
+		green {
+			label = "green";
+			gpios = <&pioA 37 GPIO_ACTIVE_LOW>;
+		};
+
+		blue {
+			label = "blue";
+			gpios = <&pioA 32 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
 };
diff --git a/sys/gnu/dts/arm/at91-sama5d3_xplained.dts b/sys/gnu/dts/arm/at91-sama5d3_xplained.dts
index ff888d21c786..f3e2b96c06a3 100644
--- a/sys/gnu/dts/arm/at91-sama5d3_xplained.dts
+++ b/sys/gnu/dts/arm/at91-sama5d3_xplained.dts
@@ -303,6 +303,7 @@
 		regulator-name = "mmc0-card-supply";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
 	};
 
 	gpio_keys {
diff --git a/sys/gnu/dts/arm/at91-sama5d4_xplained.dts b/sys/gnu/dts/arm/at91-sama5d4_xplained.dts
index 131614f28e75..da84e65b56ef 100644
--- a/sys/gnu/dts/arm/at91-sama5d4_xplained.dts
+++ b/sys/gnu/dts/arm/at91-sama5d4_xplained.dts
@@ -86,10 +86,12 @@
 			macb0: ethernet@f8020000 {
 				phy-mode = "rmii";
 				status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
 
 				phy0: ethernet-phy@1 {
 					interrupt-parent = <&pioE>;
-					interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+					interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
 					reg = <1>;
 				};
 			};
@@ -152,6 +154,10 @@
 						atmel,pins =
 							<AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
 					};
+					pinctrl_macb0_phy_irq: macb0_phy_irq_0 {
+						atmel,pins =
+							<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+					};
 				};
 			};
 		};
@@ -262,5 +268,6 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		vin-supply = <&vcc_3v3_reg>;
+		regulator-always-on;
 	};
 };
diff --git a/sys/gnu/dts/arm/at91-sama5d4ek.dts b/sys/gnu/dts/arm/at91-sama5d4ek.dts
index 2d4a33100af6..4e98cda97403 100644
--- a/sys/gnu/dts/arm/at91-sama5d4ek.dts
+++ b/sys/gnu/dts/arm/at91-sama5d4ek.dts
@@ -160,8 +160,15 @@
 			};
 
 			macb0: ethernet@f8020000 {
+				pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
 				phy-mode = "rmii";
 				status = "okay";
+
+				ethernet-phy@1 {
+					reg = <0x1>;
+					interrupt-parent = <&pioE>;
+					interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+				};
 			};
 
 			mmc1: mmc@fc000000 {
@@ -193,6 +200,10 @@
 
 			pinctrl@fc06a000 {
 				board {
+					pinctrl_macb0_phy_irq: macb0_phy_irq {
+						atmel,pins =
+							<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
 					pinctrl_mmc0_cd: mmc0_cd {
 						atmel,pins =
 							<AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
diff --git a/sys/gnu/dts/arm/at91-vinco.dts b/sys/gnu/dts/arm/at91-vinco.dts
index 79aec55e1ebc..6a366ee952a8 100644
--- a/sys/gnu/dts/arm/at91-vinco.dts
+++ b/sys/gnu/dts/arm/at91-vinco.dts
@@ -118,7 +118,7 @@
 
 				ethernet-phy@1 {
 					reg = <0x1>;
-					reset-gpios = <&pioE 8 GPIO_ACTIVE_HIGH>;
+					reset-gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
 					interrupt-parent = <&pioB>;
 					interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
 				};
@@ -162,7 +162,7 @@
 					reg = <0x1>;
 					interrupt-parent = <&pioB>;
 					interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
-					reset-gpios = <&pioE 6 GPIO_ACTIVE_HIGH>;
+					reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>;
 				};
 			};
 
diff --git a/sys/gnu/dts/arm/at91sam9g45.dtsi b/sys/gnu/dts/arm/at91sam9g45.dtsi
index af8b708ac312..8837b7e4292c 100644
--- a/sys/gnu/dts/arm/at91sam9g45.dtsi
+++ b/sys/gnu/dts/arm/at91sam9g45.dtsi
@@ -978,7 +978,7 @@
 
 			trng@fffcc000 {
 				compatible = "atmel,at91sam9g45-trng";
-				reg = <0xfffcc000 0x4000>;
+				reg = <0xfffcc000 0x100>;
 				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
 				clocks = <&trng_clk>;
 			};
diff --git a/sys/gnu/dts/arm/at91sam9n12ek.dts b/sys/gnu/dts/arm/at91sam9n12ek.dts
index ca4ddf86817a..626c67d66626 100644
--- a/sys/gnu/dts/arm/at91sam9n12ek.dts
+++ b/sys/gnu/dts/arm/at91sam9n12ek.dts
@@ -215,7 +215,7 @@
 	};
 
 	panel: panel {
-		compatible = "qd,qd43003c0-40", "simple-panel";
+		compatible = "qiaodian,qd43003c0-40", "simple-panel";
 		backlight = <&backlight>;
 		power-supply = <&panel_reg>;
 		#address-cells = <1>;
diff --git a/sys/gnu/dts/arm/at91sam9x5.dtsi b/sys/gnu/dts/arm/at91sam9x5.dtsi
index 0827d594b1f0..cd0cd5fd09a3 100644
--- a/sys/gnu/dts/arm/at91sam9x5.dtsi
+++ b/sys/gnu/dts/arm/at91sam9x5.dtsi
@@ -106,7 +106,7 @@
 
 			pmc: pmc@fffffc00 {
 				compatible = "atmel,at91sam9x5-pmc", "syscon";
-				reg = <0xfffffc00 0x100>;
+				reg = <0xfffffc00 0x200>;
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				interrupt-controller;
 				#address-cells = <1>;
diff --git a/sys/gnu/dts/arm/axm55xx.dtsi b/sys/gnu/dts/arm/axm55xx.dtsi
index ea288f0a1d39..a9d6d593fc8a 100644
--- a/sys/gnu/dts/arm/axm55xx.dtsi
+++ b/sys/gnu/dts/arm/axm55xx.dtsi
@@ -107,7 +107,7 @@
 		};
 
 		amba {
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
diff --git a/sys/gnu/dts/arm/bcm-cygnus-clock.dtsi b/sys/gnu/dts/arm/bcm-cygnus-clock.dtsi
index 32bcd45ef22b..80b6ba4ca50c 100644
--- a/sys/gnu/dts/arm/bcm-cygnus-clock.dtsi
+++ b/sys/gnu/dts/arm/bcm-cygnus-clock.dtsi
@@ -121,4 +121,13 @@ clocks {
 		clocks = <&osc>;
 		clock-output-names = "keypad", "adc/touch", "pwm";
 	};
+
+	audiopll: audiopll {
+		#clock-cells = <1>;
+		compatible = "brcm,cygnus-audiopll";
+		reg = <0x180aeb00 0x68>;
+		clocks = <&osc>;
+		clock-output-names = "audiopll", "ch0_audio",
+					"ch1_audio", "ch2_audio";
+	};
 };
diff --git a/sys/gnu/dts/arm/bcm-cygnus.dtsi b/sys/gnu/dts/arm/bcm-cygnus.dtsi
index 3878793364f0..b42fe5596b94 100644
--- a/sys/gnu/dts/arm/bcm-cygnus.dtsi
+++ b/sys/gnu/dts/arm/bcm-cygnus.dtsi
@@ -351,9 +351,16 @@
 					<&pinctrl 142 10 1>;
 		};
 
-		touchscreen: tsc@180a6000 {
+		ts_adc_syscon: ts_adc_syscon@180a6000 {
+			compatible = "brcm,iproc-ts-adc-syscon", "syscon";
+			reg = <0x180a6000 0xc30>;
+		};
+
+		touchscreen: touchscreen@180a6000 {
 			compatible = "brcm,iproc-touchscreen";
-			reg = <0x180a6000 0x40>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ts_syscon = <&ts_adc_syscon>;
 			clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
 			clock-names = "tsc_clk";
 			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/sys/gnu/dts/arm/bcm-nsp.dtsi b/sys/gnu/dts/arm/bcm-nsp.dtsi
index 10bdef557ba0..def9e783b5c6 100644
--- a/sys/gnu/dts/arm/bcm-nsp.dtsi
+++ b/sys/gnu/dts/arm/bcm-nsp.dtsi
@@ -45,14 +45,14 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x0>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
@@ -62,24 +62,19 @@
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>;
+	};
+
 	mpcore {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x19000000 0x00023000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpus {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			cpu@0 {
-				device_type = "cpu";
-				compatible = "arm,cortex-a9";
-				next-level-cache = <&L2>;
-				reg = <0x0>;
-			};
-		};
-
 		a9pll: arm_clk@00000 {
 			#clock-cells = <0>;
 			compatible = "brcm,nsp-armpll";
@@ -169,6 +164,18 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		gpioa: gpio@0020 {
+			compatible = "brcm,nsp-gpio-a";
+			reg = <0x0020 0x70>,
+			      <0x3f1c4 0x1c>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			ngpios = <32>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-ranges = <&pinctrl 0 0 32>;
+		};
+
 		uart0: serial@0300 {
 			compatible = "ns16550a";
 			reg = <0x0300 0x100>;
@@ -185,78 +192,6 @@
 			status = "disabled";
 		};
 
-		pcie0: pcie@12000 {
-			compatible = "brcm,iproc-pcie";
-			reg = <0x12000 0x1000>;
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
-
-			linux,pci-domain = <0>;
-
-			bus-range = <0x00 0xff>;
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			device_type = "pci";
-
-			/* Note: The HW does not support I/O resources.  So,
-			 * only the memory resource range is being specified.
-			 */
-			ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
-
-			status = "disabled";
-		};
-
-		pcie1: pcie@13000 {
-			compatible = "brcm,iproc-pcie";
-			reg = <0x13000 0x1000>;
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
-
-			linux,pci-domain = <1>;
-
-			bus-range = <0x00 0xff>;
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			device_type = "pci";
-
-			/* Note: The HW does not support I/O resources.  So,
-			 * only the memory resource range is being specified.
-			 */
-			ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
-
-			status = "disabled";
-		};
-
-		pcie2: pcie@14000 {
-			compatible = "brcm,iproc-pcie";
-			reg = <0x14000 0x1000>;
-
-			#interrupt-cells = <1>;
-			interrupt-map-mask = <0 0 0 0>;
-			interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
-
-			linux,pci-domain = <2>;
-
-			bus-range = <0x00 0xff>;
-
-			#address-cells = <3>;
-			#size-cells = <2>;
-			device_type = "pci";
-
-			/* Note: The HW does not support I/O resources.  So,
-			 * only the memory resource range is being specified.
-			 */
-			ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
-
-			status = "disabled";
-		};
-
 		nand: nand@26000 {
 			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 			reg = <0x026000 0x600>,
@@ -271,6 +206,24 @@
 			brcm,nand-has-wp;
 		};
 
+		ccbtimer0: timer@34000 {
+			compatible = "arm,sp804";
+			reg = <0x34000 0x1000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>;
+			clock-names = "apb_pclk";
+		};
+
+		ccbtimer1: timer@35000 {
+			compatible = "arm,sp804";
+			reg = <0x35000 0x1000>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>;
+			clock-names = "apb_pclk";
+		};
+
 		i2c0: i2c@38000 {
 			compatible = "brcm,iproc-i2c";
 			reg = <0x38000 0x50>;
@@ -280,6 +233,14 @@
 			clock-frequency = <100000>;
 		};
 
+		watchdog@39000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x39000 0x1000>;
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>, <&iprocslow>;
+			clock-names = "wdogclk", "apb_pclk";
+		};
+
 		lcpll0: lcpll0@3f100 {
 			#clock-cells = <1>;
 			compatible = "brcm,nsp-lcpll0";
@@ -306,4 +267,76 @@
 			      <0x3f408 0x04>;
 		};
 	};
+
+	pcie0: pcie@18012000 {
+		compatible = "brcm,iproc-pcie";
+		reg = <0x18012000 0x1000>;
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
+
+		linux,pci-domain = <0>;
+
+		bus-range = <0x00 0xff>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+
+		/* Note: The HW does not support I/O resources.  So,
+		 * only the memory resource range is being specified.
+		 */
+		ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
+
+		status = "disabled";
+	};
+
+	pcie1: pcie@18013000 {
+		compatible = "brcm,iproc-pcie";
+		reg = <0x18013000 0x1000>;
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
+
+		linux,pci-domain = <1>;
+
+		bus-range = <0x00 0xff>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+
+		/* Note: The HW does not support I/O resources.  So,
+		 * only the memory resource range is being specified.
+		 */
+		ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
+
+		status = "disabled";
+	};
+
+	pcie2: pcie@18014000 {
+		compatible = "brcm,iproc-pcie";
+		reg = <0x18014000 0x1000>;
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
+
+		linux,pci-domain = <2>;
+
+		bus-range = <0x00 0xff>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+
+		/* Note: The HW does not support I/O resources.  So,
+		 * only the memory resource range is being specified.
+		 */
+		ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
+
+		status = "disabled";
+	};
 };
diff --git a/sys/gnu/dts/arm/bcm2835-rpi-a-plus.dts b/sys/gnu/dts/arm/bcm2835-rpi-a-plus.dts
index 228614ffff44..35ff4e7a4aac 100644
--- a/sys/gnu/dts/arm/bcm2835-rpi-a-plus.dts
+++ b/sys/gnu/dts/arm/bcm2835-rpi-a-plus.dts
@@ -29,3 +29,7 @@
 		brcm,function = <BCM2835_FSEL_ALT0>;
 	};
 };
+
+&hdmi {
+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
diff --git a/sys/gnu/dts/arm/bcm2835-rpi-a.dts b/sys/gnu/dts/arm/bcm2835-rpi-a.dts
new file mode 100644
index 000000000000..306a84ee9898
--- /dev/null
+++ b/sys/gnu/dts/arm/bcm2835-rpi-a.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+#include "bcm2835.dtsi"
+#include "bcm2835-rpi.dtsi"
+
+/ {
+	compatible = "raspberrypi,model-a", "brcm,bcm2835";
+	model = "Raspberry Pi Model A";
+
+	leds {
+		act {
+			gpios = <&gpio 16 1>;
+		};
+	};
+};
+
+&gpio {
+	pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
+
+	/* I2S interface */
+	i2s_alt2: i2s_alt2 {
+		brcm,pins = <28 29 30 31>;
+		brcm,function = <BCM2835_FSEL_ALT2>;
+	};
+};
+
+&hdmi {
+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+};
diff --git a/sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts b/sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts
index ef5405025223..57d313b6afaf 100644
--- a/sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts
+++ b/sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts
@@ -29,3 +29,7 @@
 		brcm,function = <BCM2835_FSEL_ALT0>;
 	};
 };
+
+&hdmi {
+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
diff --git a/sys/gnu/dts/arm/bcm2835-rpi-b-rev2.dts b/sys/gnu/dts/arm/bcm2835-rpi-b-rev2.dts
index 86f1f2f598a7..cf2774ec0834 100644
--- a/sys/gnu/dts/arm/bcm2835-rpi-b-rev2.dts
+++ b/sys/gnu/dts/arm/bcm2835-rpi-b-rev2.dts
@@ -22,3 +22,7 @@
 		brcm,function = <BCM2835_FSEL_ALT2>;
 	};
 };
+
+&hdmi {
+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
diff --git a/sys/gnu/dts/arm/bcm2835-rpi-b.dts b/sys/gnu/dts/arm/bcm2835-rpi-b.dts
index 4859e9d81b23..8b15f9c35643 100644
--- a/sys/gnu/dts/arm/bcm2835-rpi-b.dts
+++ b/sys/gnu/dts/arm/bcm2835-rpi-b.dts
@@ -16,3 +16,7 @@
 &gpio {
 	pinctrl-0 = <&gpioout &alt0 &alt3>;
 };
+
+&hdmi {
+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+};
diff --git a/sys/gnu/dts/arm/bcm2835-rpi.dtsi b/sys/gnu/dts/arm/bcm2835-rpi.dtsi
index 3afb9fefe2d1..caf2707680c1 100644
--- a/sys/gnu/dts/arm/bcm2835-rpi.dtsi
+++ b/sys/gnu/dts/arm/bcm2835-rpi.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/power/raspberrypi-power.h>
+
 / {
 	memory {
 		reg = <0 0x10000000>;
@@ -18,6 +20,12 @@
 			compatible = "raspberrypi,bcm2835-firmware";
 			mboxes = <&mailbox>;
 		};
+
+		power: power {
+			compatible = "raspberrypi,bcm2835-power";
+			firmware = <&firmware>;
+			#power-domain-cells = <1>;
+		};
 	};
 };
 
@@ -58,3 +66,20 @@
 	status = "okay";
 	bus-width = <4>;
 };
+
+&pwm {
+	status = "okay";
+};
+
+&usb {
+	power-domains = <&power RPI_POWER_DOMAIN_USB>;
+};
+
+&v3d {
+	power-domains = <&power RPI_POWER_DOMAIN_V3D>;
+};
+
+&hdmi {
+	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/bcm2835.dtsi b/sys/gnu/dts/arm/bcm2835.dtsi
index b83b32639358..a78759e73710 100644
--- a/sys/gnu/dts/arm/bcm2835.dtsi
+++ b/sys/gnu/dts/arm/bcm2835.dtsi
@@ -3,6 +3,17 @@
 / {
 	compatible = "brcm,bcm2835";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,arm1176jzf-s";
+			reg = <0x0>;
+		};
+	};
+
 	soc {
 		ranges = <0x7e000000 0x20000000 0x02000000>;
 		dma-ranges = <0x40000000 0x00000000 0x20000000>;
diff --git a/sys/gnu/dts/arm/bcm2836-rpi-2-b.dts b/sys/gnu/dts/arm/bcm2836-rpi-2-b.dts
index ff946661bd13..c4743f42237b 100644
--- a/sys/gnu/dts/arm/bcm2836-rpi-2-b.dts
+++ b/sys/gnu/dts/arm/bcm2836-rpi-2-b.dts
@@ -33,3 +33,7 @@
 		brcm,function = <BCM2835_FSEL_ALT0>;
 	};
 };
+
+&hdmi {
+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+};
diff --git a/sys/gnu/dts/arm/bcm283x.dtsi b/sys/gnu/dts/arm/bcm283x.dtsi
index 971e741e5467..10b27b912bac 100644
--- a/sys/gnu/dts/arm/bcm283x.dtsi
+++ b/sys/gnu/dts/arm/bcm283x.dtsi
@@ -1,5 +1,7 @@
 #include <dt-bindings/pinctrl/bcm2835.h>
 #include <dt-bindings/clock/bcm2835.h>
+#include <dt-bindings/clock/bcm2835-aux.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "skeleton.dtsi"
 
 /* This include file covers the common peripherals and configuration between
@@ -46,9 +48,29 @@
 				     <1 24>,
 				     <1 25>,
 				     <1 26>,
+				     /* dma channel 11-14 share one irq */
 				     <1 27>,
+				     <1 27>,
+				     <1 27>,
+				     <1 27>,
+				     /* unused shared irq for all channels */
 				     <1 28>;
-
+			interrupt-names = "dma0",
+					  "dma1",
+					  "dma2",
+					  "dma3",
+					  "dma4",
+					  "dma5",
+					  "dma6",
+					  "dma7",
+					  "dma8",
+					  "dma9",
+					  "dma10",
+					  "dma11",
+					  "dma12",
+					  "dma13",
+					  "dma14",
+					  "dma-shared-all";
 			#dma-cells = <1>;
 			brcm,dma-channel-mask = <0x7f35>;
 		};
@@ -111,7 +133,7 @@
 			#interrupt-cells = <2>;
 		};
 
-		uart0: uart@7e201000 {
+		uart0: serial@7e201000 {
 			compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 			reg = <0x7e201000 0x1000>;
 			interrupts = <2 25>;
@@ -152,6 +174,18 @@
 			status = "disabled";
 		};
 
+		pixelvalve@7e206000 {
+			compatible = "brcm,bcm2835-pixelvalve0";
+			reg = <0x7e206000 0x100>;
+			interrupts = <2 13>; /* pwa0 */
+		};
+
+		pixelvalve@7e207000 {
+			compatible = "brcm,bcm2835-pixelvalve1";
+			reg = <0x7e207000 0x100>;
+			interrupts = <2 14>; /* pwa1 */
+		};
+
 		aux: aux@0x7e215000 {
 			compatible = "brcm,bcm2835-aux";
 			#clock-cells = <1>;
@@ -159,6 +193,44 @@
 			clocks = <&clocks BCM2835_CLOCK_VPU>;
 		};
 
+		uart1: serial@7e215040 {
+			compatible = "brcm,bcm2835-aux-uart";
+			reg = <0x7e215040 0x40>;
+			interrupts = <1 29>;
+			clocks = <&aux BCM2835_AUX_CLOCK_UART>;
+			status = "disabled";
+		};
+
+		spi1: spi@7e215080 {
+			compatible = "brcm,bcm2835-aux-spi";
+			reg = <0x7e215080 0x40>;
+			interrupts = <1 29>;
+			clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi@7e2150c0 {
+			compatible = "brcm,bcm2835-aux-spi";
+			reg = <0x7e2150c0 0x40>;
+			interrupts = <1 29>;
+			clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		pwm: pwm@7e20c000 {
+			compatible = "brcm,bcm2835-pwm";
+			reg = <0x7e20c000 0x28>;
+			clocks = <&clocks BCM2835_CLOCK_PWM>;
+			assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
+			assigned-clock-rates = <10000000>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
 		sdhci: sdhci@7e300000 {
 			compatible = "brcm,bcm2835-sdhci";
 			reg = <0x7e300000 0x100>;
@@ -167,6 +239,12 @@
 			status = "disabled";
 		};
 
+		hvs@7e400000 {
+			compatible = "brcm,bcm2835-hvs";
+			reg = <0x7e400000 0x6000>;
+			interrupts = <2 1>;
+		};
+
 		i2c1: i2c@7e804000 {
 			compatible = "brcm,bcm2835-i2c";
 			reg = <0x7e804000 0x1000>;
@@ -187,11 +265,39 @@
 			status = "disabled";
 		};
 
-		usb@7e980000 {
+		pixelvalve@7e807000 {
+			compatible = "brcm,bcm2835-pixelvalve2";
+			reg = <0x7e807000 0x100>;
+			interrupts = <2 10>; /* pixelvalve */
+		};
+
+		hdmi: hdmi@7e902000 {
+			compatible = "brcm,bcm2835-hdmi";
+			reg = <0x7e902000 0x600>,
+			      <0x7e808000 0x100>;
+			interrupts = <2 8>, <2 9>;
+			ddc = <&i2c2>;
+			clocks = <&clocks BCM2835_PLLH_PIX>,
+				 <&clocks BCM2835_CLOCK_HSM>;
+			clock-names = "pixel", "hdmi";
+			status = "disabled";
+		};
+
+		usb: usb@7e980000 {
 			compatible = "brcm,bcm2835-usb";
 			reg = <0x7e980000 0x10000>;
 			interrupts = <1 9>;
 		};
+
+		v3d: v3d@7ec00000 {
+			compatible = "brcm,bcm2835-v3d";
+			reg = <0x7ec00000 0x1000>;
+			interrupts = <1 10>;
+		};
+
+		vc4: gpu {
+			compatible = "brcm,bcm2835-vc4";
+		};
 	};
 
 	clocks {
diff --git a/sys/gnu/dts/arm/bcm4708-buffalo-wzr-1750dhp.dts b/sys/gnu/dts/arm/bcm4708-buffalo-wzr-1750dhp.dts
index 42dcdfb769b2..5087aa81efb1 100644
--- a/sys/gnu/dts/arm/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/sys/gnu/dts/arm/bcm4708-buffalo-wzr-1750dhp.dts
@@ -17,7 +17,7 @@
 	model = "Buffalo WZR-1750DHP (BCM4708)";
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
+		bootargs = "console=ttyS0,115200 earlycon";
 	};
 
 	memory {
@@ -139,3 +139,11 @@
 &uart0 {
 	status = "okay";
 };
+
+&usb2 {
+	vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3 {
+	vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+};
diff --git a/sys/gnu/dts/arm/bcm4708-luxul-xwc-1000.dts b/sys/gnu/dts/arm/bcm4708-luxul-xwc-1000.dts
index f18e80e0b61d..1c7e53d60aa4 100644
--- a/sys/gnu/dts/arm/bcm4708-luxul-xwc-1000.dts
+++ b/sys/gnu/dts/arm/bcm4708-luxul-xwc-1000.dts
@@ -17,7 +17,7 @@
 	model = "Luxul XWC-1000 (BCM4708)";
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
+		bootargs = "console=ttyS0,115200 earlycon";
 	};
 
 	memory {
@@ -59,3 +59,7 @@
 &uart0 {
 	status = "okay";
 };
+
+&spi_nor {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/bcm4708-netgear-r6250.dts b/sys/gnu/dts/arm/bcm4708-netgear-r6250.dts
index ca92bba6a8c5..1049ab108b32 100644
--- a/sys/gnu/dts/arm/bcm4708-netgear-r6250.dts
+++ b/sys/gnu/dts/arm/bcm4708-netgear-r6250.dts
@@ -17,24 +17,13 @@
 	model = "Netgear R6250 V1 (BCM4708)";
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
+		bootargs = "console=ttyS0,115200 earlycon";
 	};
 
 	memory {
 		reg = <0x00000000 0x08000000>;
 	};
 
-	axi@18000000 {
-		usb3@23000 {
-			reg = <0x00023000 0x1000>;
-
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
 	leds {
 		compatible = "gpio-leds";
 
@@ -97,3 +86,7 @@
 &uart0 {
 	status = "okay";
 };
+
+&usb3 {
+	vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
+};
diff --git a/sys/gnu/dts/arm/bcm4708-smartrg-sr400ac.dts b/sys/gnu/dts/arm/bcm4708-smartrg-sr400ac.dts
index 64a5e8ab65e0..8b0c440b2e71 100644
--- a/sys/gnu/dts/arm/bcm4708-smartrg-sr400ac.dts
+++ b/sys/gnu/dts/arm/bcm4708-smartrg-sr400ac.dts
@@ -17,7 +17,7 @@
 	model = "SmartRG SR400ac";
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
+		bootargs = "console=ttyS0,115200 earlycon";
 	};
 
 	memory {
@@ -122,3 +122,7 @@
 &uart0 {
 	status = "okay";
 };
+
+&spi_nor {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/bcm47081-buffalo-wzr-600dhp2.dts b/sys/gnu/dts/arm/bcm47081-buffalo-wzr-600dhp2.dts
index 38f0c00d1aca..a9c8defed4d3 100644
--- a/sys/gnu/dts/arm/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/sys/gnu/dts/arm/bcm47081-buffalo-wzr-600dhp2.dts
@@ -17,7 +17,7 @@
 	model = "Buffalo WZR-600DHP2 (BCM47081)";
 
 	chosen {
-		bootargs = "console=ttyS0,115200";
+		bootargs = "console=ttyS0,115200 earlycon";
 	};
 
 	memory {
diff --git a/sys/gnu/dts/arm/bcm4709-buffalo-wxr-1900dhp.dts b/sys/gnu/dts/arm/bcm4709-buffalo-wxr-1900dhp.dts
index 2a92e8d5ab34..791d7225c733 100644
--- a/sys/gnu/dts/arm/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/sys/gnu/dts/arm/bcm4709-buffalo-wxr-1900dhp.dts
@@ -126,3 +126,8 @@
 		};
 	};
 };
+
+
+&usb2 {
+	vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
+};
diff --git a/sys/gnu/dts/arm/bcm4709-netgear-r8000.dts b/sys/gnu/dts/arm/bcm4709-netgear-r8000.dts
index b52927c94e35..ca181516c28a 100644
--- a/sys/gnu/dts/arm/bcm4709-netgear-r8000.dts
+++ b/sys/gnu/dts/arm/bcm4709-netgear-r8000.dts
@@ -106,3 +106,11 @@
 		};
 	};
 };
+
+&usb2 {
+	vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
+};
+
+&usb3 {
+	vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
+};
diff --git a/sys/gnu/dts/arm/bcm47094-dlink-dir-885l.dts b/sys/gnu/dts/arm/bcm47094-dlink-dir-885l.dts
new file mode 100644
index 000000000000..ace38efd2db3
--- /dev/null
+++ b/sys/gnu/dts/arm/bcm47094-dlink-dir-885l.dts
@@ -0,0 +1,115 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for D-Link DIR-885L
+ *
+ * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+	compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708";
+	model = "D-Link DIR-885L";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlycon";
+	};
+
+	memory {
+		reg = <0x00000000 0x08000000>;
+	};
+
+	nand: nand@18028000 {
+		nandcs@0 {
+			partition@0 {
+				label = "firmware";
+				reg = <0x00000000 0x08000000>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		power-white {
+			label = "bcm53xx:white:power";
+			gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-on";
+		};
+
+		wan-white {
+			label = "bcm53xx:white:wan";
+			gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-off";
+		};
+
+		power-amber {
+			label = "bcm53xx:amber:power";
+			gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-off";
+		};
+
+		wan-amber {
+			label = "bcm53xx:amber:wan";
+			gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-off";
+		};
+
+		usb3-white {
+			label = "bcm53xx:white:usb3";
+			gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-off";
+		};
+
+		2ghz {
+			label = "bcm53xx:white:2ghz";
+			gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-off";
+		};
+
+		5ghz {
+			label = "bcm53xx:white:5ghz";
+			gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-off";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		wps {
+			label = "WPS";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
+		};
+
+		/* Switch: router / extender */
+		extender {
+			label = "Extender";
+			linux,code = <BTN_0>;
+			gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+		};
+
+		restart {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+	clock-frequency = <125000000>;
+};
+
+&usb3 {
+	vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
+};
diff --git a/sys/gnu/dts/arm/bcm5301x.dtsi b/sys/gnu/dts/arm/bcm5301x.dtsi
index 65a1309bd6e2..7d4d29bf0ed3 100644
--- a/sys/gnu/dts/arm/bcm5301x.dtsi
+++ b/sys/gnu/dts/arm/bcm5301x.dtsi
@@ -18,6 +18,10 @@
 / {
 	interrupt-parent = <&gic>;
 
+	chosen {
+		stdout-path = &uart0;
+	};
+
 	chipcommonA {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x18000000 0x00001000>;
@@ -207,6 +211,34 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		usb2: usb2@21000 {
+			reg = <0x00021000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		usb3: usb3@23000 {
+			reg = <0x00023000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		spi@29000 {
+			reg = <0x00029000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			spi_nor: spi-nor@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <20000000>;
+				linux,part-probe = "ofpart", "bcm47xxpart";
+				status = "disabled";
+			};
+		};
 	};
 
 	lcpll0: lcpll0@1800c100 {
diff --git a/sys/gnu/dts/arm/cros-adc-thermistors.dtsi b/sys/gnu/dts/arm/cros-adc-thermistors.dtsi
index acd4fe1833f2..ce7fca76b0d6 100644
--- a/sys/gnu/dts/arm/cros-adc-thermistors.dtsi
+++ b/sys/gnu/dts/arm/cros-adc-thermistors.dtsi
@@ -13,28 +13,28 @@
 */
 
 &adc {
-	ncp15wb473@3 {
+	thermistor3 {
 		compatible = "murata,ncp15wb473";
 		pullup-uv = <1800000>;
 		pullup-ohm = <47000>;
 		pulldown-ohm = <0>;
 		io-channels = <&adc 3>;
 	};
-	ncp15wb473@4 {
+	thermistor4 {
 		compatible = "murata,ncp15wb473";
 		pullup-uv = <1800000>;
 		pullup-ohm = <47000>;
 		pulldown-ohm = <0>;
 		io-channels = <&adc 4>;
 	};
-	ncp15wb473@5 {
+	thermistor5 {
 		compatible = "murata,ncp15wb473";
 		pullup-uv = <1800000>;
 		pullup-ohm = <47000>;
 		pulldown-ohm = <0>;
 		io-channels = <&adc 5>;
 	};
-	ncp15wb473@6 {
+	thermistor6 {
 		compatible = "murata,ncp15wb473";
 		pullup-uv = <1800000>;
 		pullup-ohm = <47000>;
diff --git a/sys/gnu/dts/arm/cros-ec-keyboard.dtsi b/sys/gnu/dts/arm/cros-ec-keyboard.dtsi
index 4e42f30cb318..c0451051777e 100644
--- a/sys/gnu/dts/arm/cros-ec-keyboard.dtsi
+++ b/sys/gnu/dts/arm/cros-ec-keyboard.dtsi
@@ -55,6 +55,7 @@
 			MATRIX_KEY(0x03, 0x04, KEY_F5)
 			MATRIX_KEY(0x03, 0x06, KEY_6)
 			MATRIX_KEY(0x03, 0x08, KEY_MINUS)
+			MATRIX_KEY(0x03, 0x09, KEY_F13)
 			MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
 			MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN)
 
diff --git a/sys/gnu/dts/arm/da850-enbw-cmc.dts b/sys/gnu/dts/arm/da850-enbw-cmc.dts
index 645549e14237..14dff3e188ed 100644
--- a/sys/gnu/dts/arm/da850-enbw-cmc.dts
+++ b/sys/gnu/dts/arm/da850-enbw-cmc.dts
@@ -16,14 +16,20 @@
 	compatible = "enbw,cmc", "ti,da850";
 	model = "EnBW CMC";
 
-	soc {
-		serial0: serial@1c42000 {
+	soc@1c00000 {
+		serial0: serial@42000 {
 			status = "okay";
 		};
-		serial1: serial@1d0c000 {
+		serial1: serial@10c000 {
 			status = "okay";
 		};
-		serial2: serial@1d0d000 {
+		serial2: serial@10d000 {
+			status = "okay";
+		};
+		mdio: mdio@224000 {
+			status = "okay";
+		};
+		eth0: ethernet@220000 {
 			status = "okay";
 		};
 	};
diff --git a/sys/gnu/dts/arm/da850-evm.dts b/sys/gnu/dts/arm/da850-evm.dts
index ef061e9a2315..1a15db8e376b 100644
--- a/sys/gnu/dts/arm/da850-evm.dts
+++ b/sys/gnu/dts/arm/da850-evm.dts
@@ -14,8 +14,8 @@
 	compatible = "ti,da850-evm", "ti,da850";
 	model = "DA850/AM1808/OMAP-L138 EVM";
 
-	soc {
-		pmx_core: pinmux@1c14120 {
+	soc@1c00000 {
+		pmx_core: pinmux@14120 {
 			status = "okay";
 
 			mcasp0_pins: pinmux_mcasp0_pins {
@@ -30,19 +30,19 @@
 				>;
 			};
 		};
-		serial0: serial@1c42000 {
+		serial0: serial@42000 {
 			status = "okay";
 		};
-		serial1: serial@1d0c000 {
+		serial1: serial@10c000 {
 			status = "okay";
 		};
-		serial2: serial@1d0d000 {
+		serial2: serial@10d000 {
 			status = "okay";
 		};
-		rtc0: rtc@1c23000 {
+		rtc0: rtc@23000 {
 			status = "okay";
 		};
-		i2c0: i2c@1c22000 {
+		i2c0: i2c@22000 {
 			status = "okay";
 			clock-frequency = <100000>;
 			pinctrl-names = "default";
@@ -66,17 +66,17 @@
 			};
 
 		};
-		wdt: wdt@1c21000 {
+		wdt: wdt@21000 {
 			status = "okay";
 		};
-		mmc0: mmc@1c40000 {
+		mmc0: mmc@40000 {
 			max-frequency = <50000000>;
 			bus-width = <4>;
 			status = "okay";
 			pinctrl-names = "default";
 			pinctrl-0 = <&mmc0_pins>;
 		};
-		spi1: spi@1f0e000 {
+		spi1: spi@30e000 {
 			status = "okay";
 			pinctrl-names = "default";
 			pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
@@ -116,18 +116,18 @@
 				};
 			};
 		};
-		mdio: mdio@1e24000 {
+		mdio: mdio@224000 {
 			status = "okay";
 			pinctrl-names = "default";
 			pinctrl-0 = <&mdio_pins>;
 			bus_freq = <2200000>;
 		};
-		eth0: ethernet@1e20000 {
+		eth0: ethernet@220000 {
 			status = "okay";
 			pinctrl-names = "default";
 			pinctrl-0 = <&mii_pins>;
 		};
-		gpio: gpio@1e26000 {
+		gpio: gpio@226000 {
 			status = "okay";
 		};
 	};
diff --git a/sys/gnu/dts/arm/da850.dtsi b/sys/gnu/dts/arm/da850.dtsi
index 226cda76e77c..25f0f8e6dde5 100644
--- a/sys/gnu/dts/arm/da850.dtsi
+++ b/sys/gnu/dts/arm/da850.dtsi
@@ -15,15 +15,15 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
-		intc: interrupt-controller {
+		intc: interrupt-controller@fffee000 {
 			compatible = "ti,cp-intc";
 			interrupt-controller;
 			#interrupt-cells = <1>;
-			ti,intc-size = <100>;
+			ti,intc-size = <101>;
 			reg = <0xfffee000 0x2000>;
 		};
 	};
-	soc {
+	soc@1c00000 {
 		compatible = "simple-bus";
 		model = "da850";
 		#address-cells = <1>;
@@ -31,7 +31,7 @@
 		ranges = <0x0 0x01c00000 0x400000>;
 		interrupt-parent = <&intc>;
 
-		pmx_core: pinmux@1c14120 {
+		pmx_core: pinmux@14120 {
 			compatible = "pinctrl-single";
 			reg = <0x14120 0x50>;
 			#address-cells = <1>;
@@ -63,6 +63,12 @@
 					0x10 0x00002200 0x0000ff00
 				>;
 			};
+			i2c1_pins: pinmux_i2c1_pins {
+				pinctrl-single,bits = <
+					/* I2C1_SDA, I2C1_SCL */
+					0x10 0x00440000 0x00ff0000
+				>;
+			};
 			mmc0_pins: pinmux_mmc_pins {
 				pinctrl-single,bits = <
 					/* MMCSD0_DAT[3] MMCSD0_DAT[2]
@@ -114,7 +120,19 @@
 					0x4 0x00000004 0x0000000f
 				>;
 			};
-			spi1_pins: pinmux_spi_pins {
+			spi0_pins: pinmux_spi0_pins {
+				pinctrl-single,bits = <
+					/* SIMO, SOMI, CLK */
+					0xc 0x00001101 0x0000ff0f
+				>;
+			};
+			spi0_cs0_pin: pinmux_spi0_cs0 {
+				pinctrl-single,bits = <
+					/* CS0 */
+					0x10 0x00000010 0x000000f0
+				>;
+			};
+			spi1_pins: pinmux_spi1_pins {
 				pinctrl-single,bits = <
 					/* SIMO, SOMI, CLK */
 					0x14 0x00110100 0x00ff0f00
@@ -150,7 +168,7 @@
 			};
 
 		};
-		edma0: edma@01c00000 {
+		edma0: edma@0 {
 			compatible = "ti,edma3-tpcc";
 			/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
 			reg =	<0x0 0x8000>;
@@ -161,19 +179,19 @@
 
 			ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
 		};
-		edma0_tptc0: tptc@01c08000 {
+		edma0_tptc0: tptc@8000 {
 			compatible = "ti,edma3-tptc";
 			reg =	<0x8000 0x400>;
 			interrupts = <13>;
 			interrupt-names = "edm3_tcerrint";
 		};
-		edma0_tptc1: tptc@01c08400 {
+		edma0_tptc1: tptc@8400 {
 			compatible = "ti,edma3-tptc";
 			reg =	<0x8400 0x400>;
 			interrupts = <32>;
 			interrupt-names = "edm3_tcerrint";
 		};
-		edma1: edma@01e30000 {
+		edma1: edma@230000 {
 			compatible = "ti,edma3-tpcc";
 			/* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
 			reg =	<0x230000 0x8000>;
@@ -184,41 +202,41 @@
 
 			ti,tptcs = <&edma1_tptc0 7>;
 		};
-		edma1_tptc0: tptc@01e38000 {
+		edma1_tptc0: tptc@238000 {
 			compatible = "ti,edma3-tptc";
 			reg =	<0x238000 0x400>;
 			interrupts = <95>;
 			interrupt-names = "edm3_tcerrint";
 		};
-		serial0: serial@1c42000 {
+		serial0: serial@42000 {
 			compatible = "ns16550a";
 			reg = <0x42000 0x100>;
 			reg-shift = <2>;
 			interrupts = <25>;
 			status = "disabled";
 		};
-		serial1: serial@1d0c000 {
+		serial1: serial@10c000 {
 			compatible = "ns16550a";
 			reg = <0x10c000 0x100>;
 			reg-shift = <2>;
 			interrupts = <53>;
 			status = "disabled";
 		};
-		serial2: serial@1d0d000 {
+		serial2: serial@10d000 {
 			compatible = "ns16550a";
 			reg = <0x10d000 0x100>;
 			reg-shift = <2>;
 			interrupts = <61>;
 			status = "disabled";
 		};
-		rtc0: rtc@1c23000 {
+		rtc0: rtc@23000 {
 			compatible = "ti,da830-rtc";
 			reg = <0x23000 0x1000>;
 			interrupts = <19
 				      19>;
 			status = "disabled";
 		};
-		i2c0: i2c@1c22000 {
+		i2c0: i2c@22000 {
 			compatible = "ti,davinci-i2c";
 			reg = <0x22000 0x1000>;
 			interrupts = <15>;
@@ -226,12 +244,20 @@
 			#size-cells = <0>;
 			status = "disabled";
 		};
-		wdt: wdt@1c21000 {
+		i2c1: i2c@228000 {
+			compatible = "ti,davinci-i2c";
+			reg = <0x228000 0x1000>;
+			interrupts = <51>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		wdt: wdt@21000 {
 			compatible = "ti,davinci-wdt";
 			reg = <0x21000 0x1000>;
 			status = "disabled";
 		};
-		mmc0: mmc@1c40000 {
+		mmc0: mmc@40000 {
 			compatible = "ti,da830-mmc";
 			reg = <0x40000 0x1000>;
 			interrupts = <16>;
@@ -239,7 +265,7 @@
 			dma-names = "rx", "tx";
 			status = "disabled";
 		};
-		mmc1: mmc@1e1b000 {
+		mmc1: mmc@21b000 {
 			compatible = "ti,da830-mmc";
 			reg = <0x21b000 0x1000>;
 			interrupts = <72>;
@@ -247,37 +273,47 @@
 			dma-names = "rx", "tx";
 			status = "disabled";
 		};
-		ehrpwm0: ehrpwm@01f00000 {
+		ehrpwm0: pwm@300000 {
 			compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
 			#pwm-cells = <3>;
 			reg = <0x300000 0x2000>;
 			status = "disabled";
 		};
-		ehrpwm1: ehrpwm@01f02000 {
+		ehrpwm1: pwm@302000 {
 			compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
 			#pwm-cells = <3>;
 			reg = <0x302000 0x2000>;
 			status = "disabled";
 		};
-		ecap0: ecap@01f06000 {
+		ecap0: ecap@306000 {
 			compatible = "ti,da850-ecap", "ti,am33xx-ecap";
 			#pwm-cells = <3>;
 			reg = <0x306000 0x80>;
 			status = "disabled";
 		};
-		ecap1: ecap@01f07000 {
+		ecap1: ecap@307000 {
 			compatible = "ti,da850-ecap", "ti,am33xx-ecap";
 			#pwm-cells = <3>;
 			reg = <0x307000 0x80>;
 			status = "disabled";
 		};
-		ecap2: ecap@01f08000 {
+		ecap2: ecap@308000 {
 			compatible = "ti,da850-ecap", "ti,am33xx-ecap";
 			#pwm-cells = <3>;
 			reg = <0x308000 0x80>;
 			status = "disabled";
 		};
-		spi1: spi@1f0e000 {
+		spi0: spi@41000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "ti,da830-spi";
+			reg = <0x41000 0x1000>;
+			num-cs = <6>;
+			ti,davinci-spi-intr-line = <1>;
+			interrupts = <20>;
+			status = "disabled";
+		};
+		spi1: spi@30e000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "ti,da830-spi";
@@ -289,13 +325,14 @@
 			dma-names = "rx", "tx";
 			status = "disabled";
 		};
-		mdio: mdio@1e24000 {
+		mdio: mdio@224000 {
 			compatible = "ti,davinci_mdio";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x224000 0x1000>;
+			status = "disabled";
 		};
-		eth0: ethernet@1e20000 {
+		eth0: ethernet@220000 {
 			compatible = "ti,davinci-dm6467-emac";
 			reg = <0x220000 0x4000>;
 			ti,davinci-ctrl-reg-offset = <0x3000>;
@@ -308,10 +345,12 @@
 					35
 					36
 					>;
+			status = "disabled";
 		};
-		gpio: gpio@1e26000 {
+		gpio: gpio@226000 {
 			compatible = "ti,dm6441-gpio";
 			gpio-controller;
+			#gpio-cells = <2>;
 			reg = <0x226000 0x1000>;
 			interrupts = <42 IRQ_TYPE_EDGE_BOTH
 				43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
@@ -323,7 +362,7 @@
 			status = "disabled";
 		};
 
-		mcasp0: mcasp@01d00000 {
+		mcasp0: mcasp@100000 {
 			compatible = "ti,da830-mcasp-audio";
 			reg = <0x100000 0x2000>,
 			      <0x102000 0x400000>;
diff --git a/sys/gnu/dts/arm/dm8148-evm.dts b/sys/gnu/dts/arm/dm8148-evm.dts
index e070862b1038..4128fa91823c 100644
--- a/sys/gnu/dts/arm/dm8148-evm.dts
+++ b/sys/gnu/dts/arm/dm8148-evm.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "dm814x.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "DM8148 EVM";
@@ -35,6 +36,67 @@
 	phy-mode = "rgmii";
 };
 
+&gpmc {
+	ranges = <0 0 0x04000000 0x01000000>;	/* CS0: 16MB for NAND */
+
+	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>; /* termcount */
+		linux,mtd-name= "micron,mt29f2g16aadwp";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ti,nand-ecc-opt = "bch8";
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		partition@0 {
+			label = "X-Loader";
+			reg = <0 0x80000>;
+		};
+		partition@0x80000 {
+			label = "U-Boot";
+			reg = <0x80000 0x1c0000>;
+		};
+		partition@0x1c0000 {
+			label = "Environment";
+			reg = <0x240000 0x40000>;
+		};
+		partition@0x280000 {
+			label = "Kernel";
+			reg = <0x280000 0x500000>;
+		};
+		partition@0x780000 {
+			label = "Filesystem";
+			reg = <0x780000 0xf880000>;
+		};
+	};
+};
+
+&mmc1 {
+        status = "disabled";
+};
+
 &mmc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd1_pins>;
@@ -43,6 +105,10 @@
 	cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
 };
 
+&mmc3 {
+        status = "disabled";
+};
+
 &pincntl {
 	sd1_pins: pinmux_sd1_pins {
 		pinctrl-single,pins = <
diff --git a/sys/gnu/dts/arm/dm8148-t410.dts b/sys/gnu/dts/arm/dm8148-t410.dts
index 5d4313fd5a46..3f184863e0c5 100644
--- a/sys/gnu/dts/arm/dm8148-t410.dts
+++ b/sys/gnu/dts/arm/dm8148-t410.dts
@@ -45,6 +45,14 @@
 	phy-mode = "rgmii";
 };
 
+&mmc1 {
+	status = "disabled";
+};
+
+&mmc2 {
+	status = "disabled";
+};
+
 &mmc3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd2_pins>;
@@ -53,6 +61,7 @@
 	dmas = <&edma_xbar 8 0 1	/* use SDTXEVT1 instead of MCASP0TX */
 		&edma_xbar 9 0 2>;	/* use SDRXEVT1 instead of MCASP0RX */
 	dma-names = "tx", "rx";
+	non-removable;
 };
 
 &pincntl {
diff --git a/sys/gnu/dts/arm/dm814x-clocks.dtsi b/sys/gnu/dts/arm/dm814x-clocks.dtsi
index 26001585673a..c4671af0a28d 100644
--- a/sys/gnu/dts/arm/dm814x-clocks.dtsi
+++ b/sys/gnu/dts/arm/dm814x-clocks.dtsi
@@ -4,8 +4,159 @@
  * published by the Free Software Foundation.
  */
 
+&pllss {
+	/*
+	 * See TRM "2.6.10 Connected outputso DPLLS" and
+	 * "2.6.11 Connected Outputs of DPLLJ". Only clkout is
+	 * connected except for hdmi and usb.
+	 */
+	adpll_mpu_ck: adpll@40 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-s-clock";
+		reg = <0x40 0x40>;
+		clocks = <&devosc_ck &devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow", "clkinphif";
+		clock-output-names = "481c5040.adpll.dcoclkldo",
+				     "481c5040.adpll.clkout",
+				     "481c5040.adpll.clkoutx2",
+				     "481c5040.adpll.clkouthif";
+	};
+
+	adpll_dsp_ck: adpll@80 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x80 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c5080.adpll.dcoclkldo",
+				     "481c5080.adpll.clkout",
+				     "481c5080.adpll.clkoutldo";
+	};
+
+	adpll_sgx_ck: adpll@b0 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0xb0 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c50b0.adpll.dcoclkldo",
+				     "481c50b0.adpll.clkout",
+				     "481c50b0.adpll.clkoutldo";
+	};
+
+	adpll_hdvic_ck: adpll@e0 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0xe0 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c50e0.adpll.dcoclkldo",
+				     "481c50e0.adpll.clkout",
+				     "481c50e0.adpll.clkoutldo";
+	};
+
+	adpll_l3_ck: adpll@110 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x110 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c5110.adpll.dcoclkldo",
+				     "481c5110.adpll.clkout",
+				     "481c5110.adpll.clkoutldo";
+	};
+
+	adpll_isp_ck: adpll@140 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x140 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c5140.adpll.dcoclkldo",
+				     "481c5140.adpll.clkout",
+				     "481c5140.adpll.clkoutldo";
+	};
+
+	adpll_dss_ck: adpll@170 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x170 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c5170.adpll.dcoclkldo",
+				     "481c5170.adpll.clkout",
+				     "481c5170.adpll.clkoutldo";
+	};
+
+	adpll_video0_ck: adpll@1a0 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x1a0 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c51a0.adpll.dcoclkldo",
+				     "481c51a0.adpll.clkout",
+				     "481c51a0.adpll.clkoutldo";
+	};
+
+	adpll_video1_ck: adpll@1d0 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x1d0 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c51d0.adpll.dcoclkldo",
+				     "481c51d0.adpll.clkout",
+				     "481c51d0.adpll.clkoutldo";
+	};
+
+	adpll_hdmi_ck: adpll@200 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x200 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c5200.adpll.dcoclkldo",
+				     "481c5200.adpll.clkout",
+				     "481c5200.adpll.clkoutldo";
+	};
+
+	adpll_audio_ck: adpll@230 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x230 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c5230.adpll.dcoclkldo",
+				     "481c5230.adpll.clkout",
+				     "481c5230.adpll.clkoutldo";
+	};
+
+	adpll_usb_ck: adpll@260 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x260 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c5260.adpll.dcoclkldo",
+				     "481c5260.adpll.clkout",
+				     "481c5260.adpll.clkoutldo";
+	};
+
+	adpll_ddr_ck: adpll@290 {
+		#clock-cells = <1>;
+		compatible = "ti,dm814-adpll-lj-clock";
+		reg = <0x290 0x30>;
+		clocks = <&devosc_ck &devosc_ck>;
+		clock-names = "clkinp", "clkinpulow";
+		clock-output-names = "481c5290.adpll.dcoclkldo",
+				     "481c5290.adpll.clkout",
+				     "481c5290.adpll.clkoutldo";
+	};
+};
+
 &pllss_clocks {
-	timer1_fck: timer1_fck {
+	timer1_fck: timer1_fck@2e0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
@@ -14,7 +165,7 @@
 		reg = <0x2e0>;
 	};
 
-	timer2_fck: timer2_fck {
+	timer2_fck: timer2_fck@2e0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
@@ -23,7 +174,25 @@
 		reg = <0x2e0>;
 	};
 
-	sysclk18_ck: sysclk18_ck {
+	/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
+	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&adpll_video0_ck 1
+			  &adpll_video1_ck 1
+			  &adpll_audio_ck 1>;
+		ti,bit-shift = <1>;
+		reg = <0x2e8>;
+	};
+
+	/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
+	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+	};
+
+	sysclk18_ck: sysclk18_ck@2f0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
@@ -33,7 +202,7 @@
 };
 
 &scm_clocks {
-	devosc_ck: devosc_ck {
+	devosc_ck: devosc_ck@40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
@@ -41,11 +210,11 @@
 		reg = <0x0040>;
 	};
 
-	/* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
+	/* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
 	auxosc_ck: auxosc_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
-		clock-frequency = <27000000>;
+		clock-frequency = <22572900>;
 	};
 
 	/* Optional 32768Hz crystal or clock on RTCOSC pins */
@@ -79,37 +248,6 @@
 		compatible = "fixed-clock";
 		clock-frequency = <1000000000>;
 	};
-
-	sysclk4_ck: sysclk4_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <222000000>;
-	};
-
-	sysclk6_ck: sysclk6_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <100000000>;
-	};
-
-	sysclk10_ck: sysclk10_ck {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <48000000>;
-	};
-
-        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <125000000>;
-	};
-
-	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <250000000>;
-	};
-
 };
 
 &prcm_clocks {
@@ -121,7 +259,7 @@
 		clock-div = <1>;
 	};
 
-	mpu_clksrc_ck: mpu_clksrc_ck {
+	mpu_clksrc_ck: mpu_clksrc_ck@40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&devosc_ck>, <&rtcdivider_ck>;
@@ -138,6 +276,49 @@
 		clock-div = <78125>;
 	};
 
+	/* L4_HS 220 MHz*/
+	sysclk4_ck: sysclk4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&adpll_l3_ck 1>;
+		ti,clock-mult = <1>;
+		ti,clock-div = <1>;
+	};
+
+	/* L4_FWCFG */
+	sysclk5_ck: sysclk5_ck {
+		#clock-cells = <0>;
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&adpll_l3_ck 1>;
+		ti,clock-mult = <1>;
+		ti,clock-div = <2>;
+	};
+
+	/* L4_LS 110 MHz */
+	sysclk6_ck: sysclk6_ck {
+		#clock-cells = <0>;
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&adpll_l3_ck 1>;
+		ti,clock-mult = <1>;
+		ti,clock-div = <2>;
+	};
+
+	sysclk8_ck: sysclk8_ck {
+		#clock-cells = <0>;
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&adpll_usb_ck 1>;
+		ti,clock-mult = <1>;
+		ti,clock-div = <1>;
+	};
+
+	sysclk10_ck: sysclk10_ck {
+		compatible = "ti,divider-clock";
+		reg = <0x324>;
+		ti,max-div = <7>;
+		#clock-cells = <0>;
+		clocks = <&adpll_usb_ck 1>;
+	};
+
 	aud_clkin0_ck: aud_clkin0_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
diff --git a/sys/gnu/dts/arm/dm814x.dtsi b/sys/gnu/dts/arm/dm814x.dtsi
index a25cd51e39ab..d4537dc61497 100644
--- a/sys/gnu/dts/arm/dm814x.dtsi
+++ b/sys/gnu/dts/arm/dm814x.dtsi
@@ -305,6 +305,13 @@
 				reg = <0x60000 0x1000>;
 			};
 
+			rtc: rtc@c0000 {
+				compatible = "ti,am3352-rtc", "ti,da830-rtc";
+				reg = <0xc0000 0x1000>;
+				interrupts = <75 76>;
+				ti,hwmods = "rtc";
+			};
+
 			mmc2: mmc@1d8000 {
 				compatible = "ti,omap4-hsmmc";
 				ti,hwmods = "mmc2";
@@ -548,6 +555,22 @@
 				reg-names = "gmii-sel";
 			};
 		};
+
+		gpmc: gpmc@50000000 {
+			compatible = "ti,am3352-gpmc";
+			ti,hwmods = "gpmc";
+			ti,no-idle-on-init;
+			reg = <0x50000000 0x2000>;
+			interrupts = <100>;
+			gpmc,num-cs = <7>;
+			gpmc,num-waitpins = <2>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 	};
 };
 
diff --git a/sys/gnu/dts/arm/dm8168-evm.dts b/sys/gnu/dts/arm/dm8168-evm.dts
index 169a85578fc9..f50348bdd857 100644
--- a/sys/gnu/dts/arm/dm8168-evm.dts
+++ b/sys/gnu/dts/arm/dm8168-evm.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "dm816x.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "DM8168 EVM";
@@ -85,8 +86,12 @@
 	ranges = <0 0 0x04000000 0x01000000>;	/* CS0: 16MB for NAND */
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		linux,mtd-name= "micron,mt29f2g16aadwp";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>; /* termcount */
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ti,nand-ecc-opt = "bch8";
@@ -106,12 +111,9 @@
 		gpmc,access-ns = <64>;
 		gpmc,rd-cycle-ns = <82>;
 		gpmc,wr-cycle-ns = <82>;
-		gpmc,wait-on-read = "true";
-		gpmc,wait-on-write = "true";
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-access-ns = <40>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 		partition@0 {
diff --git a/sys/gnu/dts/arm/dm816x-clocks.dtsi b/sys/gnu/dts/arm/dm816x-clocks.dtsi
index 50d9d338fbe9..51865eb84a80 100644
--- a/sys/gnu/dts/arm/dm816x-clocks.dtsi
+++ b/sys/gnu/dts/arm/dm816x-clocks.dtsi
@@ -86,7 +86,7 @@
 
 /* 0x48180000 */
 &prcm_clocks {
-	clkout_pre_ck: clkout_pre_ck {
+	clkout_pre_ck: clkout_pre_ck@100 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
@@ -94,7 +94,7 @@
 		reg = <0x100>;
 	};
 
-	clkout_div_ck: clkout_div_ck {
+	clkout_div_ck: clkout_div_ck@100 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&clkout_pre_ck>;
@@ -103,7 +103,7 @@
 		reg = <0x100>;
 	};
 
-	clkout_ck: clkout_ck {
+	clkout_ck: clkout_ck@100 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkout_div_ck>;
@@ -112,7 +112,7 @@
 	};
 
 	/* CM_DPLL clocks p1795 */
-	sysclk1_ck: sysclk1_ck {
+	sysclk1_ck: sysclk1_ck@300 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&main_fapll 1>;
@@ -120,7 +120,7 @@
 		reg = <0x0300>;
 	};
 
-	sysclk2_ck: sysclk2_ck {
+	sysclk2_ck: sysclk2_ck@304 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&main_fapll 2>;
@@ -128,7 +128,7 @@
 		reg = <0x0304>;
 	};
 
-	sysclk3_ck: sysclk3_ck {
+	sysclk3_ck: sysclk3_ck@308 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&main_fapll 3>;
@@ -136,7 +136,7 @@
 		reg = <0x0308>;
 	};
 
-	sysclk4_ck: sysclk4_ck {
+	sysclk4_ck: sysclk4_ck@30c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&main_fapll 4>;
@@ -144,7 +144,7 @@
 		reg = <0x030c>;
 	};
 
-	sysclk5_ck: sysclk5_ck {
+	sysclk5_ck: sysclk5_ck@310 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sysclk4_ck>;
@@ -152,7 +152,7 @@
 		reg = <0x0310>;
 	};
 
-	sysclk6_ck: sysclk6_ck {
+	sysclk6_ck: sysclk6_ck@314 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&main_fapll 4>;
@@ -160,7 +160,7 @@
 		reg = <0x0314>;
 	};
 
-	sysclk10_ck: sysclk10_ck {
+	sysclk10_ck: sysclk10_ck@324 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&ddr_fapll 2>;
@@ -168,7 +168,7 @@
 		reg = <0x0324>;
 	};
 
-	sysclk24_ck: sysclk24_ck {
+	sysclk24_ck: sysclk24_ck@3b4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&main_fapll 5>;
@@ -176,7 +176,7 @@
 		reg = <0x03b4>;
 	};
 
-	mpu_ck: mpu_ck {
+	mpu_ck: mpu_ck@15dc {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sysclk2_ck>;
@@ -184,7 +184,7 @@
                 reg = <0x15dc>;
 	};
 
-	audio_pll_a_ck: audio_pll_a_ck {
+	audio_pll_a_ck: audio_pll_a_ck@35c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&audio_fapll 1>;
@@ -192,56 +192,56 @@
 		reg = <0x035c>;
 	};
 
-	sysclk18_ck: sysclk18_ck {
+	sysclk18_ck: sysclk18_ck@378 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
 		reg = <0x0378>;
 	};
 
-	timer1_fck: timer1_fck {
+	timer1_fck: timer1_fck@390 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 		reg = <0x0390>;
 	};
 
-	timer2_fck: timer2_fck {
+	timer2_fck: timer2_fck@394 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 		reg = <0x0394>;
 	};
 
-	timer3_fck: timer3_fck {
+	timer3_fck: timer3_fck@398 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 		reg = <0x0398>;
 	};
 
-	timer4_fck: timer4_fck {
+	timer4_fck: timer4_fck@39c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 		reg = <0x039c>;
 	};
 
-	timer5_fck: timer5_fck {
+	timer5_fck: timer5_fck@3a0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 		reg = <0x03a0>;
 	};
 
-	timer6_fck: timer6_fck {
+	timer6_fck: timer6_fck@3a4 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 		reg = <0x03a4>;
 	};
 
-	timer7_fck: timer7_fck {
+	timer7_fck: timer7_fck@3a8 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
diff --git a/sys/gnu/dts/arm/dm816x.dtsi b/sys/gnu/dts/arm/dm816x.dtsi
index c3b8811a3e58..44e39c743b53 100644
--- a/sys/gnu/dts/arm/dm816x.dtsi
+++ b/sys/gnu/dts/arm/dm816x.dtsi
@@ -183,6 +183,10 @@
 			dma-names = "rxtx";
 			gpmc,num-cs = <6>;
 			gpmc,num-waitpins = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 		};
 
 		i2c1: i2c@48028000 {
@@ -214,6 +218,13 @@
 			reg = <0x48200000 0x1000>;
 		};
 
+		rtc: rtc@480c0000 {
+			compatible = "ti,am3352-rtc", "ti,da830-rtc";
+			reg = <0x480c0000 0x1000>;
+			interrupts = <75 76>;
+			ti,hwmods = "rtc";
+		};
+
 		mailbox: mailbox@480c8000 {
 			compatible = "ti,omap4-mailbox";
 			reg = <0x480c8000 0x2000>;
diff --git a/sys/gnu/dts/arm/dra62x-clocks.dtsi b/sys/gnu/dts/arm/dra62x-clocks.dtsi
index 6f98dc8df9dd..0e49741747ef 100644
--- a/sys/gnu/dts/arm/dra62x-clocks.dtsi
+++ b/sys/gnu/dts/arm/dra62x-clocks.dtsi
@@ -6,6 +6,32 @@
 
 #include "dm814x-clocks.dtsi"
 
+/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
+&adpll_hdvic_ck {
+	status = "disabled";
+};
+
+&adpll_l3_ck {
+	status = "disabled";
+};
+
+&adpll_dss_ck {
+	status = "disabled";
+};
+
+/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
+&sysclk4_ck {
+	clocks = <&adpll_isp_ck 1>;
+};
+
+&sysclk5_ck {
+	clocks = <&adpll_isp_ck 1>;
+};
+
+&sysclk6_ck {
+	clocks = <&adpll_isp_ck 1>;
+};
+
 /*
  * Compared to dm814x, dra62x has different shifts and more mux options.
  * Please add the extra options for ysclk_14 and 16 if really needed.
diff --git a/sys/gnu/dts/arm/dra62x-j5eco-evm.dts b/sys/gnu/dts/arm/dra62x-j5eco-evm.dts
index 79008069020d..f820573f4a4a 100644
--- a/sys/gnu/dts/arm/dra62x-j5eco-evm.dts
+++ b/sys/gnu/dts/arm/dra62x-j5eco-evm.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "dra62x.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "DRA62x J5 Eco EVM";
@@ -35,6 +36,63 @@
 	phy-mode = "rgmii";
 };
 
+&gpmc {
+	ranges = <0 0 0x04000000 0x01000000>;	/* CS0: 16MB for NAND */
+
+	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>; /* termcount */
+		linux,mtd-name= "micron,mt29f2g16aadwp";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ti,nand-ecc-opt = "bch8";
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		partition@0 {
+			label = "X-Loader";
+			reg = <0 0x80000>;
+		};
+		partition@0x80000 {
+			label = "U-Boot";
+			reg = <0x80000 0x1c0000>;
+		};
+		partition@0x1c0000 {
+			label = "Environment";
+			reg = <0x240000 0x40000>;
+		};
+		partition@0x280000 {
+			label = "Kernel";
+			reg = <0x280000 0x500000>;
+		};
+		partition@0x780000 {
+			label = "Filesystem";
+			reg = <0x780000 0xf880000>;
+		};
+	};
+};
+
 &mmc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&sd1_pins>;
diff --git a/sys/gnu/dts/arm/dra7-dspeve-thermal.dtsi b/sys/gnu/dts/arm/dra7-dspeve-thermal.dtsi
new file mode 100644
index 000000000000..1c39a8459b39
--- /dev/null
+++ b/sys/gnu/dts/arm/dra7-dspeve-thermal.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for DRA7x SoC DSPEVE thermal
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+dspeve_thermal: dspeve_thermal {
+	polling-delay-passive = <250>; /* milliseconds */
+	polling-delay = <500>; /* milliseconds */
+
+			/* sensor       ID */
+	thermal-sensors = <&bandgap     3>;
+
+	trips {
+		dspeve_crit: dspeve_crit {
+			temperature = <125000>; /* milliCelsius */
+			hysteresis = <2000>; /* milliCelsius */
+			type = "critical";
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/dra7-evm.dts b/sys/gnu/dts/arm/dra7-evm.dts
index cfc24e52244e..bafcfac067ec 100644
--- a/sys/gnu/dts/arm/dra7-evm.dts
+++ b/sys/gnu/dts/arm/dra7-evm.dts
@@ -18,7 +18,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x60000000>; /* 1536 MB */
+		reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
 	};
 
 	evm_3v3_sd: fixedregulator-sd {
@@ -33,6 +33,7 @@
 	evm_3v3_sw: fixedregulator-evm_3v3_sw {
 		compatible = "regulator-fixed";
 		regulator-name = "evm_3v3_sw";
+		vin-supply = <&sysen1>;
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
@@ -64,10 +65,11 @@
 		regulator-always-on;
 		regulator-boot-on;
 		enable-active-high;
+		vin-supply = <&sysen2>;
 		gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
 	};
 
-	sound0: sound@0 {
+	sound0: sound0 {
 		compatible = "simple-audio-card";
 		simple-audio-card,name = "DRA7xx-EVM";
 		simple-audio-card,widgets =
@@ -224,21 +226,6 @@
 		>;
 	};
 
-	qspi1_pins: pinmux_qspi1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x344c, PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
-			DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
-			DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
-			DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
-			DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
-			DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
-			DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
-			DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
-			DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
-			DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
-		>;
-	};
-
 	usb1_pins: pinmux_usb1_pins {
                 pinctrl-single,pins = <
 			DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
@@ -254,8 +241,9 @@
 	nand_flash_x16: nand_flash_x16 {
 		/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 		 * So NAND flash requires following switch settings:
-		 * SW5.9 (GPMC_WPN) = LOW
-		 * SW5.1 (NAND_BOOTn) = HIGH */
+		 * SW5.1 (NAND_BOOTn) = ON (LOW)
+		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
+		 */
 		pinctrl-single,pins = <
 			DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad0	*/
 			DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT  | MUX_MODE0)	/* gpmc_ad1	*/
@@ -428,7 +416,7 @@
 					/* VDD_DSPEVE */
 					regulator-name = "smps45";
 					regulator-min-microvolt = < 850000>;
-					regulator-max-microvolt = <1150000>;
+					regulator-max-microvolt = <1250000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};
@@ -446,7 +434,7 @@
 					/* CORE_VDD */
 					regulator-name = "smps7";
 					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1060000>;
+					regulator-max-microvolt = <1150000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};
@@ -523,12 +511,37 @@
 					regulator-max-microvolt = <3300000>;
 					regulator-boot-on;
 				};
+
+				/* REGEN1 is unused */
+
+				regen2: regen2 {
+					/* Needed for PMIC internal resources */
+					regulator-name = "regen2";
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				/* REGEN3 is unused */
+
+				sysen1: sysen1 {
+					/* PMIC_REGEN_3V3 */
+					regulator-name = "sysen1";
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				sysen2: sysen2 {
+					/* PMIC_REGEN_DDR */
+					regulator-name = "sysen2";
+					regulator-boot-on;
+					regulator-always-on;
+				};
 			};
 		};
 	};
 
 	pcf_lcd: gpio@20 {
-		compatible = "nxp,pcf8575";
+		compatible = "ti,pcf8575", "nxp,pcf8575";
 		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
@@ -539,7 +552,7 @@
 	};
 
 	pcf_gpio_21: gpio@21 {
-		compatible = "ti,pcf8575";
+		compatible = "ti,pcf8575", "nxp,pcf8575";
 		reg = <0x21>;
 		lines-initial-states = <0x1408>;
 		gpio-controller;
@@ -573,7 +586,7 @@
 	clock-frequency = <400000>;
 
 	pcf_hdmi: gpio@26 {
-		compatible = "nxp,pcf8575";
+		compatible = "ti,pcf8575", "nxp,pcf8575";
 		reg = <0x26>;
 		gpio-controller;
 		#gpio-cells = <2>;
@@ -650,18 +663,14 @@
 
 &qspi {
 	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&qspi1_pins>;
 
-	spi-max-frequency = <48000000>;
+	spi-max-frequency = <64000000>;
 	m25p80@0 {
 		compatible = "s25fl256s1";
-		spi-max-frequency = <48000000>;
+		spi-max-frequency = <64000000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
-		spi-cpol;
-		spi-cpha;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
@@ -741,9 +750,14 @@
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&nand_flash_x16>;
-	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
+	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>;		/* device IO registers */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>; /* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
 		ti,nand-ecc-opt = "bch8";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <16>;
@@ -766,7 +780,6 @@
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 		/* MTD partition table */
 		/* All SPL-* partitions are sized to minimal length
@@ -901,6 +914,8 @@
 	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 		1 2 0 0
 	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
 };
 
 &mailbox5 {
diff --git a/sys/gnu/dts/arm/dra7-iva-thermal.dtsi b/sys/gnu/dts/arm/dra7-iva-thermal.dtsi
new file mode 100644
index 000000000000..dd74a5337d1f
--- /dev/null
+++ b/sys/gnu/dts/arm/dra7-iva-thermal.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for DRA7x SoC IVA thermal
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+iva_thermal: iva_thermal {
+	polling-delay-passive = <250>; /* milliseconds */
+	polling-delay = <500>; /* milliseconds */
+
+			/* sensor       ID */
+	thermal-sensors = <&bandgap     4>;
+
+	trips {
+		iva_crit: iva_crit {
+			temperature = <125000>; /* milliCelsius */
+			hysteresis = <2000>; /* milliCelsius */
+			type = "critical";
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/dra7.dtsi b/sys/gnu/dts/arm/dra7.dtsi
index c4d9175b90dc..3a8f3976f6f9 100644
--- a/sys/gnu/dts/arm/dra7.dtsi
+++ b/sys/gnu/dts/arm/dra7.dtsi
@@ -15,8 +15,8 @@
 #define MAX_SOURCES 400
 
 / {
-	#address-cells = <1>;
-	#size-cells = <1>;
+	#address-cells = <2>;
+	#size-cells = <2>;
 
 	compatible = "ti,dra7xx";
 	interrupt-parent = <&crossbar_mpu>;
@@ -57,10 +57,10 @@
 		compatible = "arm,cortex-a15-gic";
 		interrupt-controller;
 		#interrupt-cells = <3>;
-		reg = <0x48211000 0x1000>,
-		      <0x48212000 0x1000>,
-		      <0x48214000 0x2000>,
-		      <0x48216000 0x2000>;
+		reg = <0x0 0x48211000 0x0 0x1000>,
+		      <0x0 0x48212000 0x0 0x1000>,
+		      <0x0 0x48214000 0x0 0x2000>,
+		      <0x0 0x48216000 0x0 0x2000>;
 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 		interrupt-parent = <&gic>;
 	};
@@ -69,7 +69,7 @@
 		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 		interrupt-controller;
 		#interrupt-cells = <3>;
-		reg = <0x48281000 0x1000>;
+		reg = <0x0 0x48281000 0x0 0x1000>;
 		interrupt-parent = <&gic>;
 	};
 
@@ -96,10 +96,10 @@
 		compatible = "ti,dra7-l3-noc", "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		ranges;
+		ranges = <0x0 0x0 0x0 0xc0000000>;
 		ti,hwmods = "l3_main_1", "l3_main_2";
-		reg = <0x44000000 0x1000000>,
-		      <0x45000000 0x1000>;
+		reg = <0x0 0x44000000 0x0 0x1000000>,
+		      <0x0 0x45000000 0x0 0x1000>;
 		interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 				      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -123,7 +123,7 @@
 					#size-cells = <1>;
 					ranges = <0 0x0 0x1400>;
 
-					pbias_regulator: pbias_regulator {
+					pbias_regulator: pbias_regulator@e00 {
 						compatible = "ti,pbias-dra7", "ti,pbias-omap";
 						reg = <0xe00 0x4>;
 						syscon = <&scm_conf>;
@@ -156,6 +156,29 @@
 					compatible = "syscon";
 					reg = <0x1c04 0x0020>;
 				};
+
+				scm_conf_pcie: scm_conf@1c24 {
+					compatible = "syscon";
+					reg = <0x1c24 0x0024>;
+				};
+
+				sdma_xbar: dma-router@b78 {
+					compatible = "ti,dra7-dma-crossbar";
+					reg = <0xb78 0xfc>;
+					#dma-cells = <1>;
+					dma-requests = <205>;
+					ti,dma-safe-map = <0>;
+					dma-masters = <&sdma>;
+				};
+
+				edma_xbar: dma-router@c78 {
+					compatible = "ti,dra7-dma-crossbar";
+					reg = <0xc78 0x7c>;
+					#dma-cells = <2>;
+					dma-requests = <204>;
+					ti,dma-safe-map = <0>;
+					dma-masters = <&edma>;
+				};
 			};
 
 			cm_core_aon: cm_core_aon@5000 {
@@ -310,13 +333,43 @@
 			dma-requests = <127>;
 		};
 
-		sdma_xbar: dma-router@4a002b78 {
-			compatible = "ti,dra7-dma-crossbar";
-			reg = <0x4a002b78 0xfc>;
-			#dma-cells = <1>;
-			dma-requests = <205>;
-			ti,dma-safe-map = <0>;
-			dma-masters = <&sdma>;
+		edma: edma@43300000 {
+			compatible = "ti,edma3-tpcc";
+			ti,hwmods = "tpcc";
+			reg = <0x43300000 0x100000>;
+			reg-names = "edma3_cc";
+			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_ccint", "emda3_mperr",
+					  "edma3_ccerrint";
+			dma-requests = <64>;
+			#dma-cells = <2>;
+
+			ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
+
+			/*
+			 * memcpy is disabled, can be enabled with:
+			 * ti,edma-memcpy-channels = <20 21>;
+			 * for example. Note that these channels need to be
+			 * masked in the xbar as well.
+			 */
+		};
+
+		edma_tptc0: tptc@43400000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc0";
+			reg =	<0x43400000 0x100000>;
+			interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_tcerrint";
+		};
+
+		edma_tptc1: tptc@43500000 {
+			compatible = "ti,edma3-tptc";
+			ti,hwmods = "tptc1";
+			reg =	<0x43500000 0x100000>;
+			interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma3_tcerrint";
 		};
 
 		gpio1: gpio@4ae10000 {
@@ -768,12 +821,20 @@
 			ti,hwmods = "timer11";
 		};
 
+		timer12: timer@4ae20000 {
+			compatible = "ti,omap5430-timer";
+			reg = <0x4ae20000 0x80>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			ti,hwmods = "timer12";
+			ti,timer-alwon;
+			ti,timer-secure;
+		};
+
 		timer13: timer@48828000 {
 			compatible = "ti,omap5430-timer";
 			reg = <0x48828000 0x80>;
 			interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer13";
-			status = "disabled";
 		};
 
 		timer14: timer@4882a000 {
@@ -781,7 +842,6 @@
 			reg = <0x4882a000 0x80>;
 			interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer14";
-			status = "disabled";
 		};
 
 		timer15: timer@4882c000 {
@@ -789,7 +849,6 @@
 			reg = <0x4882c000 0x80>;
 			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer15";
-			status = "disabled";
 		};
 
 		timer16: timer@4882e000 {
@@ -797,7 +856,6 @@
 			reg = <0x4882e000 0x80>;
 			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer16";
-			status = "disabled";
 		};
 
 		wdt2: wdt@4ae14000 {
@@ -1168,14 +1226,6 @@
 			status = "disabled";
 		};
 
-		omap_control_sata: control-phy@4a002374 {
-			compatible = "ti,control-phy-pipe3";
-			reg = <0x4a002374 0x4>;
-			reg-names = "power";
-			clocks = <&sys_clkin1>;
-			clock-names = "sysclk";
-		};
-
 		/* OCP2SCP3 */
 		ocp2scp@4a090000 {
 			compatible = "ti,omap-ocp2scp";
@@ -1190,7 +1240,7 @@
 				      <0x4A096400 0x64>, /* phy_tx */
 				      <0x4A096800 0x40>; /* pll_ctrl */
 				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
-				ctrl-module = <&omap_control_sata>;
+				syscon-phy-power = <&scm_conf 0x374>;
 				clocks = <&sys_clkin1>, <&sata_ref_clk>;
 				clock-names = "sysclk", "refclk";
 				syscon-pllreset = <&scm_conf 0x3fc>;
@@ -1202,16 +1252,18 @@
 				reg = <0x4a094000 0x80>, /* phy_rx */
 				      <0x4a094400 0x64>; /* phy_tx */
 				reg-names = "phy_rx", "phy_tx";
-				ctrl-module = <&omap_control_pcie1phy>;
+				syscon-phy-power = <&scm_conf_pcie 0x1c>;
+				syscon-pcs = <&scm_conf_pcie 0x10>;
 				clocks = <&dpll_pcie_ref_ck>,
 					 <&dpll_pcie_ref_m2ldo_ck>,
 					 <&optfclk_pciephy1_32khz>,
 					 <&optfclk_pciephy1_clk>,
 					 <&optfclk_pciephy1_div_clk>,
-					 <&optfclk_pciephy_div>;
+					 <&optfclk_pciephy_div>,
+					 <&sys_clkin1>;
 				clock-names = "dpll_ref", "dpll_ref_m2",
 					      "wkupclk", "refclk",
-					      "div-clk", "phy-div";
+					      "div-clk", "phy-div", "sysclk";
 				#phy-cells = <0>;
 			};
 
@@ -1220,16 +1272,18 @@
 				reg = <0x4a095000 0x80>, /* phy_rx */
 				      <0x4a095400 0x64>; /* phy_tx */
 				reg-names = "phy_rx", "phy_tx";
-				ctrl-module = <&omap_control_pcie2phy>;
+				syscon-phy-power = <&scm_conf_pcie 0x20>;
+				syscon-pcs = <&scm_conf_pcie 0x10>;
 				clocks = <&dpll_pcie_ref_ck>,
 					 <&dpll_pcie_ref_m2ldo_ck>,
 					 <&optfclk_pciephy2_32khz>,
 					 <&optfclk_pciephy2_clk>,
 					 <&optfclk_pciephy2_div_clk>,
-					 <&optfclk_pciephy_div>;
+					 <&optfclk_pciephy_div>,
+					 <&sys_clkin1>;
 				clock-names = "dpll_ref", "dpll_ref_m2",
 					      "wkupclk", "refclk",
-					      "div-clk", "phy-div";
+					      "div-clk", "phy-div", "sysclk";
 				#phy-cells = <0>;
 				status = "disabled";
 			};
@@ -1245,23 +1299,6 @@
 			ti,hwmods = "sata";
 		};
 
-		omap_control_pcie1phy: control-phy@0x4a003c40 {
-			compatible = "ti,control-phy-pcie";
-			reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
-			reg-names = "power", "control_sma", "pcie_pcs";
-			clocks = <&sys_clkin1>;
-			clock-names = "sysclk";
-		};
-
-		omap_control_pcie2phy: control-pcie@0x4a003c44 {
-			compatible = "ti,control-phy-pcie";
-			reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
-			reg-names = "power", "control_sma", "pcie_pcs";
-			clocks = <&sys_clkin1>;
-			clock-names = "sysclk";
-			status = "disabled";
-		};
-
 		rtc: rtc@48838000 {
 			compatible = "ti,am3352-rtc";
 			reg = <0x48838000 0x100>;
@@ -1271,24 +1308,6 @@
 			clocks = <&sys_32k_ck>;
 		};
 
-		omap_control_usb2phy1: control-phy@4a002300 {
-			compatible = "ti,control-phy-usb2";
-			reg = <0x4a002300 0x4>;
-			reg-names = "power";
-		};
-
-		omap_control_usb3phy1: control-phy@4a002370 {
-			compatible = "ti,control-phy-pipe3";
-			reg = <0x4a002370 0x4>;
-			reg-names = "power";
-		};
-
-		omap_control_usb2phy2: control-phy@0x4a002e74 {
-			compatible = "ti,control-phy-usb2-dra7";
-			reg = <0x4a002e74 0x4>;
-			reg-names = "power";
-		};
-
 		/* OCP2SCP1 */
 		ocp2scp@4a080000 {
 			compatible = "ti,omap-ocp2scp";
@@ -1301,7 +1320,7 @@
 			usb2_phy1: phy@4a084000 {
 				compatible = "ti,omap-usb2";
 				reg = <0x4a084000 0x400>;
-				ctrl-module = <&omap_control_usb2phy1>;
+				syscon-phy-power = <&scm_conf 0x300>;
 				clocks = <&usb_phy1_always_on_clk32k>,
 					 <&usb_otg_ss1_refclk960m>;
 				clock-names =	"wkupclk",
@@ -1310,9 +1329,10 @@
 			};
 
 			usb2_phy2: phy@4a085000 {
-				compatible = "ti,omap-usb2";
+				compatible = "ti,dra7x-usb2-phy2",
+					     "ti,omap-usb2";
 				reg = <0x4a085000 0x400>;
-				ctrl-module = <&omap_control_usb2phy2>;
+				syscon-phy-power = <&scm_conf 0xe74>;
 				clocks = <&usb_phy2_always_on_clk32k>,
 					 <&usb_otg_ss2_refclk960m>;
 				clock-names =	"wkupclk",
@@ -1326,7 +1346,7 @@
 				      <0x4a084800 0x64>,
 				      <0x4a084c00 0x40>;
 				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
-				ctrl-module = <&omap_control_usb3phy1>;
+				syscon-phy-power = <&scm_conf 0x370>;
 				clocks = <&usb_phy3_always_on_clk32k>,
 					 <&sys_clkin1>,
 					 <&usb_otg_ss1_refclk960m>;
@@ -1357,7 +1377,6 @@
 						  "otg";
 				phys = <&usb2_phy1>, <&usb3_phy1>;
 				phy-names = "usb2-phy", "usb3-phy";
-				tx-fifo-resize;
 				maximum-speed = "super-speed";
 				dr_mode = "otg";
 				snps,dis_u3_susphy_quirk;
@@ -1385,7 +1404,6 @@
 						  "otg";
 				phys = <&usb2_phy2>;
 				phy-names = "usb2-phy";
-				tx-fifo-resize;
 				maximum-speed = "high-speed";
 				dr_mode = "otg";
 				snps,dis_u3_susphy_quirk;
@@ -1413,7 +1431,6 @@
 				interrupt-names = "peripheral",
 						  "host",
 						  "otg";
-				tx-fifo-resize;
 				maximum-speed = "high-speed";
 				dr_mode = "otg";
 				snps,dis_u3_susphy_quirk;
@@ -1434,10 +1451,16 @@
 			ti,hwmods = "gpmc";
 			reg = <0x50000000 0x37c>;      /* device IO registers */
 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			dmas = <&edma_xbar 4 0>;
+			dma-names = "rxtx";
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <2>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 			status = "disabled";
 		};
 
@@ -1452,21 +1475,136 @@
 			status = "disabled";
 		};
 
+		mcasp1: mcasp@48460000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp1";
+			reg = <0x48460000 0x2000>,
+			      <0x45800000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
+				 <&mcasp1_ahclkr_mux>;
+			clock-names = "fck", "ahclkx", "ahclkr";
+			status = "disabled";
+		};
+
+		mcasp2: mcasp@48464000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp2";
+			reg = <0x48464000 0x2000>,
+			      <0x45c00000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
+				 <&mcasp2_ahclkr_mux>;
+			clock-names = "fck", "ahclkx", "ahclkr";
+			status = "disabled";
+		};
+
 		mcasp3: mcasp@48468000 {
 			compatible = "ti,dra7-mcasp-audio";
 			ti,hwmods = "mcasp3";
-			reg = <0x48468000 0x2000>;
-			reg-names = "mpu";
+			reg = <0x48468000 0x2000>,
+			      <0x46000000 0x1000>;
+			reg-names = "mpu","dat";
 			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "tx", "rx";
-			dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
+			dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
 			dma-names = "tx", "rx";
 			clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
 			clock-names = "fck", "ahclkx";
 			status = "disabled";
 		};
 
+		mcasp4: mcasp@4846c000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp4";
+			reg = <0x4846c000 0x2000>,
+			      <0x48436000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp5: mcasp@48470000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp5";
+			reg = <0x48470000 0x2000>,
+			      <0x4843a000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp6: mcasp@48474000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp6";
+			reg = <0x48474000 0x2000>,
+			      <0x4844c000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp7: mcasp@48478000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp7";
+			reg = <0x48478000 0x2000>,
+			      <0x48450000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
+		mcasp8: mcasp@4847c000 {
+			compatible = "ti,dra7-mcasp-audio";
+			ti,hwmods = "mcasp8";
+			reg = <0x4847c000 0x2000>,
+			      <0x48454000 0x1000>;
+			reg-names = "mpu","dat";
+			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tx", "rx";
+			dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
+			dma-names = "tx", "rx";
+			clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+			clock-names = "fck", "ahclkx";
+			status = "disabled";
+		};
+
 		crossbar_mpu: crossbar@4a002a48 {
 			compatible = "ti,irq-crossbar";
 			reg = <0x4a002a48 0x130>;
@@ -1500,6 +1638,16 @@
 			       0x48485200 0x2E00>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			/*
+			 * Do not allow gating of cpsw clock as workaround
+			 * for errata i877. Keeping internal clock disabled
+			 * causes the device switching characteristics
+			 * to degrade over time and eventually fail to meet
+			 * the data manual delay time/skew specs.
+			 */
+			ti,no-idle;
+
 			/*
 			 * rx_thresh_pend
 			 * rx_pend
@@ -1603,6 +1751,8 @@
 		#include "omap4-cpu-thermal.dtsi"
 		#include "omap5-gpu-thermal.dtsi"
 		#include "omap5-core-thermal.dtsi"
+		#include "dra7-dspeve-thermal.dtsi"
+		#include "dra7-iva-thermal.dtsi"
 	};
 
 };
diff --git a/sys/gnu/dts/arm/dra72-evm-common.dtsi b/sys/gnu/dts/arm/dra72-evm-common.dtsi
new file mode 100644
index 000000000000..093538ea5b5f
--- /dev/null
+++ b/sys/gnu/dts/arm/dra72-evm-common.dtsi
@@ -0,0 +1,817 @@
+/*
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
+
+/ {
+	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
+
+	aliases {
+		display0 = &hdmi0;
+	};
+
+	evm_3v3: fixedregulator-evm_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "evm_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	aic_dvdd: fixedregulator-aic_dvdd {
+		/* TPS77018DBVT */
+		compatible = "regulator-fixed";
+		regulator-name = "aic_dvdd";
+		vin-supply = <&evm_3v3>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	evm_3v3_sd: fixedregulator-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "evm_3v3_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
+	};
+
+	extcon_usb1: extcon_usb1 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+	};
+
+	extcon_usb2: extcon_usb2 {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+	};
+
+	hdmi0: connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&tpd12s015_out>;
+			};
+		};
+	};
+
+	tpd12s015: encoder {
+		compatible = "ti,tpd12s015";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&tpd12s015_pins>;
+
+		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
+			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
+			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				tpd12s015_in: endpoint {
+					remote-endpoint = <&hdmi_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				tpd12s015_out: endpoint {
+					remote-endpoint = <&hdmi_connector_in>;
+				};
+			};
+		};
+	};
+
+	sound0: sound0 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "DRA7xx-EVM";
+		simple-audio-card,widgets =
+			"Headphone", "Headphone Jack",
+			"Line", "Line Out",
+			"Microphone", "Mic Jack",
+			"Line", "Line In";
+		simple-audio-card,routing =
+			"Headphone Jack",       "HPLOUT",
+			"Headphone Jack",       "HPROUT",
+			"Line Out",		"LLOUT",
+			"Line Out",		"RLOUT",
+			"MIC3L",		"Mic Jack",
+			"MIC3R",		"Mic Jack",
+			"Mic Jack",		"Mic Bias",
+			"LINE1L",               "Line In",
+			"LINE1R",               "Line In";
+		simple-audio-card,format = "dsp_b";
+		simple-audio-card,bitclock-master = <&sound0_master>;
+		simple-audio-card,frame-master = <&sound0_master>;
+		simple-audio-card,bitclock-inversion;
+
+		sound0_master: simple-audio-card,cpu {
+			sound-dai = <&mcasp3>;
+			system-clock-frequency = <5644800>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&tlv320aic3106>;
+			clocks = <&atl_clkin2_ck>;
+		};
+	};
+};
+
+&dra7_pmx_core {
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
+			DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
+		>;
+	};
+
+	i2c5_pins: pinmux_i2c5_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
+			DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
+		>;
+	};
+
+	i2c5_pins: pinmux_i2c5_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
+			DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
+		>;
+	};
+
+	nand_default: nand_default {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
+			DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
+			DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
+			DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
+			DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
+			DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
+			DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
+			DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
+			DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
+			DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
+			DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
+			DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
+			DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
+			DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
+			DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
+			DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
+			DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
+			DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+			DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+			DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+			DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
+			DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
+		>;
+	};
+
+	usb1_pins: pinmux_usb1_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+		>;
+	};
+
+	usb2_pins: pinmux_usb2_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+		>;
+	};
+
+	tps65917_pins_default: tps65917_pins_default {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
+		>;
+	};
+
+	mmc1_pins_default: mmc1_pins_default {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)	/* mmc1sdcd.gpio219 */
+			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+		>;
+	};
+
+	mmc2_pins_default: mmc2_pins_default {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+		>;
+	};
+
+	dcan1_pins_default: dcan1_pins_default {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+			DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
+		>;
+	};
+
+	dcan1_pins_sleep: dcan1_pins_sleep {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
+			DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP)	/* wakeup0.off */
+		>;
+	};
+
+	hdmi_pins: pinmux_hdmi_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
+			DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
+		>;
+	};
+
+	tpd12s015_pins: pinmux_tpd12s015_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
+		>;
+	};
+
+	atl_pins: pinmux_atl_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5)	/* xref_clk1.atl_clk1 */
+			DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5)	/* xref_clk2.atl_clk2 */
+		>;
+	};
+
+	mcasp3_pins: pinmux_mcasp3_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_aclkx */
+			DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_fsx */
+			DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_axr0 */
+			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_axr1 */
+		>;
+	};
+
+	mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
+		>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	clock-frequency = <400000>;
+
+	tps65917: tps65917@58 {
+		compatible = "ti,tps65917";
+		reg = <0x58>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&tps65917_pins_default>;
+
+		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		ti,system-power-controller;
+
+		tps65917_pmic {
+			compatible = "ti,tps65917-pmic";
+
+			tps65917_regulators: regulators {
+				smps1_reg: smps1 {
+					/* VDD_MPU */
+					regulator-name = "smps1";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps2_reg: smps2 {
+					/* VDD_CORE */
+					regulator-name = "smps2";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1150000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				smps3_reg: smps3 {
+					/* VDD_GPU IVA DSPEVE */
+					regulator-name = "smps3";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				smps4_reg: smps4 {
+					/* VDDS1V8 */
+					regulator-name = "smps4";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				smps5_reg: smps5 {
+					/* VDD_DDR */
+					regulator-name = "smps5";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo1_reg: ldo1 {
+					/* LDO1_OUT --> SDIO  */
+					regulator-name = "ldo1";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-allow-bypass;
+				};
+
+				ldo3_reg: ldo3 {
+					/* VDDA_1V8_PHY */
+					regulator-name = "ldo3";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				ldo5_reg: ldo5 {
+					/* VDDA_1V8_PLL */
+					regulator-name = "ldo5";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo4_reg: ldo4 {
+					/* VDDA_3V_USB: VDDA_USBHS33 */
+					regulator-name = "ldo4";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-boot-on;
+				};
+			};
+		};
+
+		tps65917_power_button {
+			compatible = "ti,palmas-pwrbutton";
+			interrupt-parent = <&tps65917>;
+			interrupts = <1 IRQ_TYPE_NONE>;
+			wakeup-source;
+			ti,palmas-long-press-seconds = <6>;
+		};
+	};
+
+	pcf_gpio_21: gpio@21 {
+		compatible = "ti,pcf8575", "nxp,pcf8575";
+		reg = <0x21>;
+		lines-initial-states = <0x1408>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	tlv320aic3106: tlv320aic3106@19 {
+		#sound-dai-cells = <0>;
+		compatible = "ti,tlv320aic3106";
+		reg = <0x19>;
+		adc-settle-ms = <40>;
+		ai3x-micbias-vg = <1>;		/* 2.0V */
+		status = "okay";
+
+		/* Regulators */
+		AVDD-supply = <&evm_3v3>;
+		IOVDD-supply = <&evm_3v3>;
+		DRVDD-supply = <&evm_3v3>;
+		DVDD-supply = <&aic_dvdd>;
+	};
+};
+
+&i2c5 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5_pins>;
+	clock-frequency = <400000>;
+
+	pcf_hdmi: pcf8575@26 {
+		compatible = "ti,pcf8575", "nxp,pcf8575";
+		reg = <0x26>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/*
+		 * initial state is used here to keep the mdio interface
+		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
+		 * VIN2_S0 driven high otherwise Ethernet stops working
+		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
+		 */
+		lines-initial-states = <0x0f2b>;
+
+		p1 {
+			/* vin6_sel_s0: high: VIN6, low: audio */
+			gpio-hog;
+			gpios = <1 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "vin6_sel_s0";
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+			      <&dra7_pmx_core 0x3e0>;
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_default>;
+	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
+	nand@0,0 {
+		/* To use NAND, DIP switch SW5 must be set like so:
+		 * SW5.1 (NAND_SELn) = ON (LOW)
+		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
+		 */
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>;		/* device IO registers */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
+		ti,nand-ecc-opt = "bch8";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <80>;
+		gpmc,cs-wr-off-ns = <80>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <60>;
+		gpmc,adv-wr-off-ns = <60>;
+		gpmc,we-on-ns = <10>;
+		gpmc,we-off-ns = <50>;
+		gpmc,oe-on-ns = <4>;
+		gpmc,oe-off-ns = <40>;
+		gpmc,access-ns = <40>;
+		gpmc,wr-access-ns = <80>;
+		gpmc,rd-cycle-ns = <80>;
+		gpmc,wr-cycle-ns = <80>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x000020000>;
+		};
+		partition@1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00020000 0x00020000>;
+		};
+		partition@2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00040000 0x00020000>;
+		};
+		partition@3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x00060000 0x00020000>;
+		};
+		partition@4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@5 {
+			label = "NAND.u-boot";
+			reg = <0x000c0000 0x00100000>;
+		};
+		partition@6 {
+			label = "NAND.u-boot-env";
+			reg = <0x001c0000 0x00020000>;
+		};
+		partition@7 {
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x001e0000 0x00020000>;
+		};
+		partition@8 {
+			label = "NAND.kernel";
+			reg = <0x00200000 0x00800000>;
+		};
+		partition@9 {
+			label = "NAND.file-system";
+			reg = <0x00a00000 0x0f600000>;
+		};
+	};
+};
+
+&usb2_phy1 {
+	phy-supply = <&ldo4_reg>;
+};
+
+&usb2_phy2 {
+	phy-supply = <&ldo4_reg>;
+};
+
+&omap_dwc3_1 {
+	extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+	extcon = <&extcon_usb2>;
+};
+
+&usb1 {
+	dr_mode = "peripheral";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb2_pins>;
+};
+
+&mmc1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_default>;
+	vmmc-supply = <&evm_3v3_sd>;
+	vmmc_aux-supply = <&ldo1_reg>;
+	bus-width = <4>;
+	/*
+	 * SDCD signal is not being used here - using the fact that GPIO mode
+	 * is a viable alternative
+	 */
+	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
+	max-frequency = <192000000>;
+};
+
+&mmc2 {
+	/* SW5-3 in ON position */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins_default>;
+
+	vmmc-supply = <&evm_3v3>;
+	bus-width = <8>;
+	ti,non-removable;
+	max-frequency = <192000000>;
+};
+
+&dra7_pmx_core {
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 2 */
+			DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d12.rgmii1_txc */
+			DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d13.rgmii1_tctl */
+			DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d14.rgmii1_td3 */
+			DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d15.rgmii1_td2 */
+			DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d16.rgmii1_td1 */
+			DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d17.rgmii1_td0 */
+			DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3)	/* vin2a_d18.rgmii1_rclk */
+			DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3)	/* vin2a_d19.rgmii1_rctl */
+			DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3)	/* vin2a_d20.rgmii1_rd3 */
+			DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3)	/* vin2a_d21.rgmii1_rd2 */
+			DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3)	/* vin2a_d22.rgmii1_rd1 */
+			DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3)	/* vin2a_d23.rgmii1_rd0 */
+		>;
+
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 2 */
+			DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mdio_d.mdio_d */
+			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0)	/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
+			DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
+		>;
+	};
+};
+
+&mac {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+};
+
+&dcan1 {
+	status = "ok";
+	pinctrl-names = "default", "sleep", "active";
+	pinctrl-0 = <&dcan1_pins_sleep>;
+	pinctrl-1 = <&dcan1_pins_sleep>;
+	pinctrl-2 = <&dcan1_pins_default>;
+};
+
+&qspi {
+	status = "okay";
+
+	spi-max-frequency = <64000000>;
+	m25p80@0 {
+		compatible = "s25fl256s1";
+		spi-max-frequency = <64000000>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MTD partition table.
+		 * The ROM checks the first four physical blocks
+		 * for a valid file to boot and the flash here is
+		 * 64KiB block size.
+		 */
+		partition@0 {
+			label = "QSPI.SPL";
+			reg = <0x00000000 0x000010000>;
+		};
+		partition@1 {
+			label = "QSPI.SPL.backup1";
+			reg = <0x00010000 0x00010000>;
+		};
+		partition@2 {
+			label = "QSPI.SPL.backup2";
+			reg = <0x00020000 0x00010000>;
+		};
+		partition@3 {
+			label = "QSPI.SPL.backup3";
+			reg = <0x00030000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.u-boot";
+			reg = <0x00040000 0x00100000>;
+		};
+		partition@5 {
+			label = "QSPI.u-boot-spl-os";
+			reg = <0x00140000 0x00080000>;
+		};
+		partition@6 {
+			label = "QSPI.u-boot-env";
+			reg = <0x001c0000 0x00010000>;
+		};
+		partition@7 {
+			label = "QSPI.u-boot-env.backup1";
+			reg = <0x001d0000 0x0010000>;
+		};
+		partition@8 {
+			label = "QSPI.kernel";
+			reg = <0x001e0000 0x0800000>;
+		};
+		partition@9 {
+			label = "QSPI.file-system";
+			reg = <0x009e0000 0x01620000>;
+		};
+	};
+};
+
+&dss {
+	status = "ok";
+
+	vdda_video-supply = <&ldo5_reg>;
+};
+
+&hdmi {
+	status = "ok";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_pins>;
+
+	port {
+		hdmi_out: endpoint {
+			remote-endpoint = <&tpd12s015_in>;
+		};
+	};
+};
+
+&atl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&atl_pins>;
+
+	assigned-clocks = <&abe_dpll_sys_clk_mux>,
+			  <&atl_gfclk_mux>,
+			  <&dpll_abe_ck>,
+			  <&dpll_abe_m2x2_ck>,
+			  <&atl_clkin2_ck>;
+	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
+	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
+
+	status = "okay";
+
+	atl2 {
+		bws = <DRA7_ATL_WS_MCASP2_FSX>;
+		aws = <DRA7_ATL_WS_MCASP3_FSX>;
+	};
+};
+
+&mcasp3 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mcasp3_pins>;
+	pinctrl-1 = <&mcasp3_sleep_pins>;
+
+	assigned-clocks = <&mcasp3_ahclkx_mux>;
+	assigned-clock-parents = <&atl_clkin2_ck>;
+
+	status = "okay";
+
+	op-mode = <0>;          /* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	/* 4 serializer */
+	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+		1 2 0 0
+	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
+};
+
+&mailbox5 {
+	status = "okay";
+	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+		status = "okay";
+	};
+	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+		status = "okay";
+	};
+};
+
+&mailbox6 {
+	status = "okay";
+	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+		status = "okay";
+	};
+};
diff --git a/sys/gnu/dts/arm/dra72-evm-revc.dts b/sys/gnu/dts/arm/dra72-evm-revc.dts
new file mode 100644
index 000000000000..f9cfd3bb4dc2
--- /dev/null
+++ b/sys/gnu/dts/arm/dra72-evm-revc.dts
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "dra72-evm-common.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	model = "TI DRA722 Rev C EVM";
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
+	};
+};
+
+&tps65917_regulators {
+	ldo2_reg: ldo2 {
+		/* LDO2_OUT --> VDDA_1V8_PHY2 */
+		regulator-name = "ldo2";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&hdmi {
+	vdda-supply = <&ldo2_reg>;
+};
+
+&pcf_gpio_21 {
+	interrupt-parent = <&gpio3>;
+	interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&mac {
+	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
+		     <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,	/* P11 */
+		     <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;	/* P12 */
+	dual_emac;
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <2>;
+	phy-mode = "rgmii-id";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <3>;
+	phy-mode = "rgmii-id";
+	dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+	dp83867_0: ethernet-phy@2 {
+		reg = <2>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+	};
+
+	dp83867_1: ethernet-phy@3 {
+		reg = <3>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+	};
+};
diff --git a/sys/gnu/dts/arm/dra72-evm.dts b/sys/gnu/dts/arm/dra72-evm.dts
index 00b12002c07c..cc1d32ca4a8a 100644
--- a/sys/gnu/dts/arm/dra72-evm.dts
+++ b/sys/gnu/dts/arm/dra72-evm.dts
@@ -1,691 +1,40 @@
 /*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/dts-v1/;
-
-#include "dra72x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clk/ti-dra7-atl.h>
-
+#include "dra72-evm-common.dtsi"
 / {
 	model = "TI DRA722";
-	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x40000000>; /* 1024 MB */
-	};
-
-	aliases {
-		display0 = &hdmi0;
-	};
-
-	evm_3v3: fixedregulator-evm_3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "evm_3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
+		reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
 	};
+};
 
-	aic_dvdd: fixedregulator-aic_dvdd {
-		/* TPS77018DBVT */
-		compatible = "regulator-fixed";
-		regulator-name = "aic_dvdd";
-		vin-supply = <&evm_3v3>;
+&tps65917_regulators {
+	ldo2_reg: ldo2 {
+		/* LDO2_OUT --> TP1017 (UNUSED)  */
+		regulator-name = "ldo2";
 		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-	};
-
-	evm_3v3_sd: fixedregulator-sd {
-		compatible = "regulator-fixed";
-		regulator-name = "evm_3v3_sd";
-		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
-	};
-
-	extcon_usb1: extcon_usb1 {
-		compatible = "linux,extcon-usb-gpio";
-		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
-	};
-
-	extcon_usb2: extcon_usb2 {
-		compatible = "linux,extcon-usb-gpio";
-		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
-	};
-
-	hdmi0: connector {
-		compatible = "hdmi-connector";
-		label = "hdmi";
-
-		type = "a";
-
-		port {
-			hdmi_connector_in: endpoint {
-				remote-endpoint = <&tpd12s015_out>;
-			};
-		};
-	};
-
-	tpd12s015: encoder {
-		compatible = "ti,tpd12s015";
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&tpd12s015_pins>;
-
-		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
-			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
-			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-
-				tpd12s015_in: endpoint {
-					remote-endpoint = <&hdmi_out>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				tpd12s015_out: endpoint {
-					remote-endpoint = <&hdmi_connector_in>;
-				};
-			};
-		};
-	};
-
-	sound0: sound@0 {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "DRA7xx-EVM";
-		simple-audio-card,widgets =
-			"Headphone", "Headphone Jack",
-			"Line", "Line Out",
-			"Microphone", "Mic Jack",
-			"Line", "Line In";
-		simple-audio-card,routing =
-			"Headphone Jack",       "HPLOUT",
-			"Headphone Jack",       "HPROUT",
-			"Line Out",		"LLOUT",
-			"Line Out",		"RLOUT",
-			"MIC3L",		"Mic Jack",
-			"MIC3R",		"Mic Jack",
-			"Mic Jack",		"Mic Bias",
-			"LINE1L",               "Line In",
-			"LINE1R",               "Line In";
-		simple-audio-card,format = "dsp_b";
-		simple-audio-card,bitclock-master = <&sound0_master>;
-		simple-audio-card,frame-master = <&sound0_master>;
-		simple-audio-card,bitclock-inversion;
-
-		sound0_master: simple-audio-card,cpu {
-			sound-dai = <&mcasp3>;
-			system-clock-frequency = <5644800>;
-		};
-
-		simple-audio-card,codec {
-			sound-dai = <&tlv320aic3106>;
-			clocks = <&atl_clkin2_ck>;
-		};
-	};
-};
-
-&dra7_pmx_core {
-	i2c1_pins: pinmux_i2c1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
-			DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
-		>;
-	};
-
-	i2c5_pins: pinmux_i2c5_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
-			DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
-		>;
-	};
-
-	i2c5_pins: pinmux_i2c5_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
-			DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
-		>;
-	};
-
-	nand_default: nand_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
-			DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
-			DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
-			DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
-			DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
-			DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
-			DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
-			DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
-			DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
-			DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
-			DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
-			DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
-			DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
-			DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
-			DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
-			DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
-			DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
-			DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
-			DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
-			DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
-			DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
-			DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
-		>;
-	};
-
-	usb1_pins: pinmux_usb1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
-		>;
-	};
-
-	usb2_pins: pinmux_usb2_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
-		>;
-	};
-
-	tps65917_pins_default: tps65917_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
-		>;
-	};
-
-	mmc1_pins_default: mmc1_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)	/* mmc1sdcd.gpio219 */
-			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
-			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
-			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
-			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
-			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
-			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
-		>;
-	};
-
-	mmc2_pins_default: mmc2_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
-			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
-			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
-			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
-			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
-			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
-			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
-			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
-			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
-			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
-		>;
-	};
-
-	dcan1_pins_default: dcan1_pins_default {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
-			DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
-		>;
-	};
-
-	dcan1_pins_sleep: dcan1_pins_sleep {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
-			DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP)	/* wakeup0.off */
-		>;
-	};
-
-	qspi1_pins: pinmux_qspi1_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3474, PIN_OUTPUT | MUX_MODE1)	/* gpmc_a13.qspi1_rtclk */
-			DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1)	/* gpmc_a14.qspi1_d3 */
-			DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1)	/* gpmc_a15.qspi1_d2 */
-			DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1)	/* gpmc_a16.qspi1_d1 */
-			DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)	/* gpmc_a17.qspi1_d0 */
-			DRA7XX_CORE_IOPAD(0x3488, PIN_OUTPUT | MUX_MODE1)	/* qpmc_a18.qspi1_sclk */
-			DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MUX_MODE1)	/* gpmc_cs2.qspi1_cs0 */
-		>;
-	};
-
-	hdmi_pins: pinmux_hdmi_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
-			DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
-		>;
-	};
-
-	tpd12s015_pins: pinmux_tpd12s015_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
-		>;
-	};
-
-	atl_pins: pinmux_atl_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5)	/* xref_clk1.atl_clk1 */
-			DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5)	/* xref_clk2.atl_clk2 */
-		>;
-	};
-
-	mcasp3_pins: pinmux_mcasp3_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_aclkx */
-			DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_fsx */
-			DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_axr0 */
-			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_axr1 */
-		>;
-	};
-
-	mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
-		>;
-	};
-};
-
-&i2c1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-	clock-frequency = <400000>;
-
-	tps65917: tps65917@58 {
-		compatible = "ti,tps65917";
-		reg = <0x58>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&tps65917_pins_default>;
-
-		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
-		interrupt-controller;
-		#interrupt-cells = <2>;
-
-		ti,system-power-controller;
-
-		tps65917_pmic {
-			compatible = "ti,tps65917-pmic";
-
-			regulators {
-				smps1_reg: smps1 {
-					/* VDD_MPU */
-					regulator-name = "smps1";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps2_reg: smps2 {
-					/* VDD_CORE */
-					regulator-name = "smps2";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1060000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				smps3_reg: smps3 {
-					/* VDD_GPU IVA DSPEVE */
-					regulator-name = "smps3";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1250000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				smps4_reg: smps4 {
-					/* VDDS1V8 */
-					regulator-name = "smps4";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				smps5_reg: smps5 {
-					/* VDD_DDR */
-					regulator-name = "smps5";
-					regulator-min-microvolt = <1350000>;
-					regulator-max-microvolt = <1350000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				ldo1_reg: ldo1 {
-					/* LDO1_OUT --> SDIO  */
-					regulator-name = "ldo1";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-always-on;
-					regulator-boot-on;
-					regulator-allow-bypass;
-				};
-
-				ldo2_reg: ldo2 {
-					/* LDO2_OUT --> TP1017 (UNUSED)  */
-					regulator-name = "ldo2";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-allow-bypass;
-				};
-
-				ldo3_reg: ldo3 {
-					/* VDDA_1V8_PHY */
-					regulator-name = "ldo3";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-boot-on;
-					regulator-always-on;
-				};
-
-				ldo5_reg: ldo5 {
-					/* VDDA_1V8_PLL */
-					regulator-name = "ldo5";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo4_reg: ldo4 {
-					/* VDDA_3V_USB: VDDA_USBHS33 */
-					regulator-name = "ldo4";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-boot-on;
-				};
-			};
-		};
-
-		tps65917_power_button {
-			compatible = "ti,palmas-pwrbutton";
-			interrupt-parent = <&tps65917>;
-			interrupts = <1 IRQ_TYPE_NONE>;
-			wakeup-source;
-			ti,palmas-long-press-seconds = <6>;
-		};
-	};
-
-	pcf_gpio_21: gpio@21 {
-		compatible = "ti,pcf8575";
-		reg = <0x21>;
-		lines-initial-states = <0x1408>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&gpio6>;
-		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	tlv320aic3106: tlv320aic3106@19 {
-		#sound-dai-cells = <0>;
-		compatible = "ti,tlv320aic3106";
-		reg = <0x19>;
-		adc-settle-ms = <40>;
-		ai3x-micbias-vg = <1>;		/* 2.0V */
-		status = "okay";
-
-		/* Regulators */
-		AVDD-supply = <&evm_3v3>;
-		IOVDD-supply = <&evm_3v3>;
-		DRVDD-supply = <&evm_3v3>;
-		DVDD-supply = <&aic_dvdd>;
+		regulator-allow-bypass;
 	};
 };
 
-&i2c5 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c5_pins>;
-	clock-frequency = <400000>;
-
-	pcf_hdmi: pcf8575@26 {
-		compatible = "nxp,pcf8575";
-		reg = <0x26>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		/*
-		 * initial state is used here to keep the mdio interface
-		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
-		 * VIN2_S0 driven high otherwise Ethernet stops working
-		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
-		 */
-		lines-initial-states = <0x0f2b>;
-
-		p1 {
-			/* vin6_sel_s0: high: VIN6, low: audio */
-			gpio-hog;
-			gpios = <1 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "vin6_sel_s0";
-		};
-	};
-};
-
-&uart1 {
-	status = "okay";
-	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
-			      <&dra7_pmx_core 0x3e0>;
-};
-
-&elm {
-	status = "okay";
-};
-
-&gpmc {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&nand_default>;
-	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
-	nand@0,0 {
-		/* To use NAND, DIP switch SW5 must be set like so:
-		 * SW5.1 (NAND_SELn) = ON (LOW)
-		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
-		 */
-		reg = <0 0 4>;		/* device IO registers */
-		ti,nand-ecc-opt = "bch8";
-		ti,elm-id = <&elm>;
-		nand-bus-width = <16>;
-		gpmc,device-width = <2>;
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <80>;
-		gpmc,cs-wr-off-ns = <80>;
-		gpmc,adv-on-ns = <0>;
-		gpmc,adv-rd-off-ns = <60>;
-		gpmc,adv-wr-off-ns = <60>;
-		gpmc,we-on-ns = <10>;
-		gpmc,we-off-ns = <50>;
-		gpmc,oe-on-ns = <4>;
-		gpmc,oe-off-ns = <40>;
-		gpmc,access-ns = <40>;
-		gpmc,wr-access-ns = <80>;
-		gpmc,rd-cycle-ns = <80>;
-		gpmc,wr-cycle-ns = <80>;
-		gpmc,bus-turnaround-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <0>;
-		gpmc,clk-activation-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-		/* MTD partition table */
-		/* All SPL-* partitions are sized to minimal length
-		 * which can be independently programmable. For
-		 * NAND flash this is equal to size of erase-block */
-		#address-cells = <1>;
-		#size-cells = <1>;
-		partition@0 {
-			label = "NAND.SPL";
-			reg = <0x00000000 0x000020000>;
-		};
-		partition@1 {
-			label = "NAND.SPL.backup1";
-			reg = <0x00020000 0x00020000>;
-		};
-		partition@2 {
-			label = "NAND.SPL.backup2";
-			reg = <0x00040000 0x00020000>;
-		};
-		partition@3 {
-			label = "NAND.SPL.backup3";
-			reg = <0x00060000 0x00020000>;
-		};
-		partition@4 {
-			label = "NAND.u-boot-spl-os";
-			reg = <0x00080000 0x00040000>;
-		};
-		partition@5 {
-			label = "NAND.u-boot";
-			reg = <0x000c0000 0x00100000>;
-		};
-		partition@6 {
-			label = "NAND.u-boot-env";
-			reg = <0x001c0000 0x00020000>;
-		};
-		partition@7 {
-			label = "NAND.u-boot-env.backup1";
-			reg = <0x001e0000 0x00020000>;
-		};
-		partition@8 {
-			label = "NAND.kernel";
-			reg = <0x00200000 0x00800000>;
-		};
-		partition@9 {
-			label = "NAND.file-system";
-			reg = <0x00a00000 0x0f600000>;
-		};
-	};
-};
-
-&usb2_phy1 {
-	phy-supply = <&ldo4_reg>;
-};
-
-&usb2_phy2 {
-	phy-supply = <&ldo4_reg>;
-};
-
-&omap_dwc3_1 {
-	extcon = <&extcon_usb1>;
-};
-
-&omap_dwc3_2 {
-	extcon = <&extcon_usb2>;
-};
-
-&usb1 {
-	dr_mode = "peripheral";
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb1_pins>;
-};
-
-&usb2 {
-	dr_mode = "host";
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb2_pins>;
-};
-
-&mmc1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins_default>;
-	vmmc-supply = <&evm_3v3_sd>;
-	vmmc_aux-supply = <&ldo1_reg>;
-	bus-width = <4>;
-	/*
-	 * SDCD signal is not being used here - using the fact that GPIO mode
-	 * is a viable alternative
-	 */
-	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
-	max-frequency = <192000000>;
-};
-
-&mmc2 {
-	/* SW5-3 in ON position */
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins_default>;
-
-	vmmc-supply = <&evm_3v3>;
-	bus-width = <8>;
-	ti,non-removable;
-	max-frequency = <192000000>;
+&hdmi {
+	vdda-supply = <&ldo3_reg>;
 };
 
-&dra7_pmx_core {
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 2 */
-			DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d12.rgmii1_txc */
-			DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d13.rgmii1_tctl */
-			DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d14.rgmii1_td3 */
-			DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d15.rgmii1_td2 */
-			DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d16.rgmii1_td1 */
-			DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)	/* vin2a_d17.rgmii1_td0 */
-			DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3)	/* vin2a_d18.rgmii1_rclk */
-			DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3)	/* vin2a_d19.rgmii1_rctl */
-			DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3)	/* vin2a_d20.rgmii1_rd3 */
-			DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3)	/* vin2a_d21.rgmii1_rd2 */
-			DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3)	/* vin2a_d22.rgmii1_rd1 */
-			DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3)	/* vin2a_d23.rgmii1_rd0 */
-		>;
-
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 2 */
-			DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
-		>;
-	};
-
-	davinci_mdio_default: davinci_mdio_default {
-		pinctrl-single,pins = <
-			/* MDIO */
-			DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mdio_d.mdio_d */
-			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0)	/* mdio_clk.mdio_clk */
-		>;
-	};
-
-	davinci_mdio_sleep: davinci_mdio_sleep {
-		pinctrl-single,pins = <
-			DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
-			DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
-		>;
-	};
+&pcf_gpio_21 {
+	interrupt-parent = <&gpio6>;
+	interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 };
 
 &mac {
-	status = "okay";
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
 	slaves = <1>;
 	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
 };
@@ -694,158 +43,3 @@
 	phy_id = <&davinci_mdio>, <3>;
 	phy-mode = "rgmii";
 };
-
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_default>;
-	pinctrl-1 = <&davinci_mdio_sleep>;
-};
-
-&dcan1 {
-	status = "ok";
-	pinctrl-names = "default", "sleep", "active";
-	pinctrl-0 = <&dcan1_pins_sleep>;
-	pinctrl-1 = <&dcan1_pins_sleep>;
-	pinctrl-2 = <&dcan1_pins_default>;
-};
-
-&qspi {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&qspi1_pins>;
-
-	spi-max-frequency = <48000000>;
-	m25p80@0 {
-		compatible = "s25fl256s1";
-		spi-max-frequency = <48000000>;
-		reg = <0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
-		spi-cpol;
-		spi-cpha;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		/* MTD partition table.
-		 * The ROM checks the first four physical blocks
-		 * for a valid file to boot and the flash here is
-		 * 64KiB block size.
-		 */
-		partition@0 {
-			label = "QSPI.SPL";
-			reg = <0x00000000 0x000010000>;
-		};
-		partition@1 {
-			label = "QSPI.SPL.backup1";
-			reg = <0x00010000 0x00010000>;
-		};
-		partition@2 {
-			label = "QSPI.SPL.backup2";
-			reg = <0x00020000 0x00010000>;
-		};
-		partition@3 {
-			label = "QSPI.SPL.backup3";
-			reg = <0x00030000 0x00010000>;
-		};
-		partition@4 {
-			label = "QSPI.u-boot";
-			reg = <0x00040000 0x00100000>;
-		};
-		partition@5 {
-			label = "QSPI.u-boot-spl-os";
-			reg = <0x00140000 0x00080000>;
-		};
-		partition@6 {
-			label = "QSPI.u-boot-env";
-			reg = <0x001c0000 0x00010000>;
-		};
-		partition@7 {
-			label = "QSPI.u-boot-env.backup1";
-			reg = <0x001d0000 0x0010000>;
-		};
-		partition@8 {
-			label = "QSPI.kernel";
-			reg = <0x001e0000 0x0800000>;
-		};
-		partition@9 {
-			label = "QSPI.file-system";
-			reg = <0x009e0000 0x01620000>;
-		};
-	};
-};
-
-&dss {
-	status = "ok";
-
-	vdda_video-supply = <&ldo5_reg>;
-};
-
-&hdmi {
-	status = "ok";
-	vdda-supply = <&ldo3_reg>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&hdmi_pins>;
-
-	port {
-		hdmi_out: endpoint {
-			remote-endpoint = <&tpd12s015_in>;
-		};
-	};
-};
-
-&atl {
-	pinctrl-names = "default";
-	pinctrl-0 = <&atl_pins>;
-
-	assigned-clocks = <&abe_dpll_sys_clk_mux>,
-			  <&atl_gfclk_mux>,
-			  <&dpll_abe_ck>,
-			  <&dpll_abe_m2x2_ck>,
-			  <&atl_clkin2_ck>;
-	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
-	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
-
-	status = "okay";
-
-	atl2 {
-		bws = <DRA7_ATL_WS_MCASP2_FSX>;
-		aws = <DRA7_ATL_WS_MCASP3_FSX>;
-	};
-};
-
-&mcasp3 {
-	#sound-dai-cells = <0>;
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&mcasp3_pins>;
-	pinctrl-1 = <&mcasp3_sleep_pins>;
-
-	assigned-clocks = <&mcasp3_ahclkx_mux>;
-	assigned-clock-parents = <&atl_clkin2_ck>;
-
-	status = "okay";
-
-	op-mode = <0>;          /* MCASP_IIS_MODE */
-	tdm-slots = <2>;
-	/* 4 serializer */
-	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
-		1 2 0 0
-	>;
-};
-
-&mailbox5 {
-	status = "okay";
-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
-		status = "okay";
-	};
-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
-		status = "okay";
-	};
-};
-
-&mailbox6 {
-	status = "okay";
-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
-		status = "okay";
-	};
-};
diff --git a/sys/gnu/dts/arm/dra74x.dtsi b/sys/gnu/dts/arm/dra74x.dtsi
index 8bcc47db1cd1..5e06020f450b 100644
--- a/sys/gnu/dts/arm/dra74x.dtsi
+++ b/sys/gnu/dts/arm/dra74x.dtsi
@@ -76,7 +76,6 @@
 				interrupt-names = "peripheral",
 						  "host",
 						  "otg";
-				tx-fifo-resize;
 				maximum-speed = "high-speed";
 				dr_mode = "otg";
 			};
@@ -108,8 +107,8 @@
 	reg = <0x58000000 0x80>,
 	      <0x58004054 0x4>,
 	      <0x58004300 0x20>,
-	      <0x58005054 0x4>,
-	      <0x58005300 0x20>;
+	      <0x58009054 0x4>,
+	      <0x58009300 0x20>;
 	reg-names = "dss", "pll1_clkctrl", "pll1",
 		    "pll2_clkctrl", "pll2";
 
diff --git a/sys/gnu/dts/arm/dra7xx-clocks.dtsi b/sys/gnu/dts/arm/dra7xx-clocks.dtsi
index 357bedeebfac..8378b44ee567 100644
--- a/sys/gnu/dts/arm/dra7xx-clocks.dtsi
+++ b/sys/gnu/dts/arm/dra7xx-clocks.dtsi
@@ -98,12 +98,20 @@
 		clock-frequency = <32768>;
 	};
 
-	sys_32k_ck: sys_32k_ck {
+	sys_clk32_crystal_ck: sys_clk32_crystal_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
 	};
 
+	sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin1>;
+		clock-mult = <1>;
+		clock-div = <610>;
+	};
+
 	virt_12000000_ck: virt_12000000_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
@@ -188,7 +196,7 @@
 		clock-frequency = <0>;
 	};
 
-	dpll_abe_ck: dpll_abe_ck {
+	dpll_abe_ck: dpll_abe_ck@1e0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-m4xen-clock";
 		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
@@ -201,7 +209,7 @@
 		clocks = <&dpll_abe_ck>;
 	};
 
-	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_x2_ck>;
@@ -212,7 +220,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	abe_clk: abe_clk {
+	abe_clk: abe_clk@108 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2x2_ck>;
@@ -221,7 +229,7 @@
 		ti,index-power-of-two;
 	};
 
-	dpll_abe_m2_ck: dpll_abe_m2_ck {
+	dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_ck>;
@@ -232,7 +240,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_x2_ck>;
@@ -243,7 +251,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_byp_mux: dpll_core_byp_mux {
+	dpll_core_byp_mux: dpll_core_byp_mux@12c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -251,7 +259,7 @@
 		reg = <0x012c>;
 	};
 
-	dpll_core_ck: dpll_core_ck {
+	dpll_core_ck: dpll_core_ck@120 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-core-clock";
 		clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
@@ -264,7 +272,7 @@
 		clocks = <&dpll_core_ck>;
 	};
 
-	dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+	dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -283,14 +291,14 @@
 		clock-div = <1>;
 	};
 
-	dpll_mpu_ck: dpll_mpu_ck {
+	dpll_mpu_ck: dpll_mpu_ck@160 {
 		#clock-cells = <0>;
 		compatible = "ti,omap5-mpu-dpll-clock";
 		clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 	};
 
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_mpu_ck>;
@@ -317,7 +325,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_dsp_byp_mux: dpll_dsp_byp_mux {
+	dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
@@ -325,14 +333,14 @@
 		reg = <0x0240>;
 	};
 
-	dpll_dsp_ck: dpll_dsp_ck {
+	dpll_dsp_ck: dpll_dsp_ck@234 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 		reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 	};
 
-	dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+	dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_dsp_ck>;
@@ -351,7 +359,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_iva_byp_mux: dpll_iva_byp_mux {
+	dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
@@ -359,14 +367,14 @@
 		reg = <0x01ac>;
 	};
 
-	dpll_iva_ck: dpll_iva_ck {
+	dpll_iva_ck: dpll_iva_ck@1a0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 	};
 
-	dpll_iva_m2_ck: dpll_iva_m2_ck {
+	dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_iva_ck>;
@@ -385,7 +393,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_gpu_byp_mux: dpll_gpu_byp_mux {
+	dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -393,14 +401,14 @@
 		reg = <0x02e4>;
 	};
 
-	dpll_gpu_ck: dpll_gpu_ck {
+	dpll_gpu_ck: dpll_gpu_ck@2d8 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 		reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 	};
 
-	dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+	dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gpu_ck>;
@@ -411,7 +419,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_m2_ck: dpll_core_m2_ck {
+	dpll_core_m2_ck: dpll_core_m2_ck@130 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_ck>;
@@ -430,7 +438,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_ddr_byp_mux: dpll_ddr_byp_mux {
+	dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -438,14 +446,14 @@
 		reg = <0x021c>;
 	};
 
-	dpll_ddr_ck: dpll_ddr_ck {
+	dpll_ddr_ck: dpll_ddr_ck@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 		reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 	};
 
-	dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+	dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_ck>;
@@ -456,7 +464,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_gmac_byp_mux: dpll_gmac_byp_mux {
+	dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -464,14 +472,14 @@
 		reg = <0x02b4>;
 	};
 
-	dpll_gmac_ck: dpll_gmac_ck {
+	dpll_gmac_ck: dpll_gmac_ck@2a8 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 		reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 	};
 
-	dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+	dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_ck>;
@@ -530,7 +538,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_eve_byp_mux: dpll_eve_byp_mux {
+	dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
@@ -538,14 +546,14 @@
 		reg = <0x0290>;
 	};
 
-	dpll_eve_ck: dpll_eve_ck {
+	dpll_eve_ck: dpll_eve_ck@284 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 		reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 	};
 
-	dpll_eve_m2_ck: dpll_eve_m2_ck {
+	dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_eve_ck>;
@@ -564,7 +572,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+	dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -575,7 +583,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+	dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -586,7 +594,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+	dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -597,7 +605,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+	dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -608,7 +616,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+	dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -625,7 +633,7 @@
 		clocks = <&dpll_ddr_ck>;
 	};
 
-	dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+	dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_x2_ck>;
@@ -642,7 +650,7 @@
 		clocks = <&dpll_dsp_ck>;
 	};
 
-	dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+	dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_dsp_x2_ck>;
@@ -659,7 +667,7 @@
 		clocks = <&dpll_gmac_ck>;
 	};
 
-	dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+	dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_x2_ck>;
@@ -670,7 +678,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+	dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_x2_ck>;
@@ -681,7 +689,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+	dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_x2_ck>;
@@ -692,7 +700,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+	dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_x2_ck>;
@@ -727,7 +735,7 @@
 		clock-div = <1>;
 	};
 
-	l3_iclk_div: l3_iclk_div {
+	l3_iclk_div: l3_iclk_div@100 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		ti,max-div = <2>;
@@ -777,7 +785,7 @@
 		clock-div = <1>;
 	};
 
-	ipu1_gfclk_mux: ipu1_gfclk_mux {
+	ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
@@ -785,7 +793,7 @@
 		reg = <0x0520>;
 	};
 
-	mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+	mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -793,7 +801,7 @@
 		reg = <0x0550>;
 	};
 
-	mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+	mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -801,7 +809,7 @@
 		reg = <0x0550>;
 	};
 
-	mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+	mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -809,7 +817,7 @@
 		reg = <0x0550>;
 	};
 
-	timer5_gfclk_mux: timer5_gfclk_mux {
+	timer5_gfclk_mux: timer5_gfclk_mux@558 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -817,7 +825,7 @@
 		reg = <0x0558>;
 	};
 
-	timer6_gfclk_mux: timer6_gfclk_mux {
+	timer6_gfclk_mux: timer6_gfclk_mux@560 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -825,7 +833,7 @@
 		reg = <0x0560>;
 	};
 
-	timer7_gfclk_mux: timer7_gfclk_mux {
+	timer7_gfclk_mux: timer7_gfclk_mux@568 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -833,7 +841,7 @@
 		reg = <0x0568>;
 	};
 
-	timer8_gfclk_mux: timer8_gfclk_mux {
+	timer8_gfclk_mux: timer8_gfclk_mux@570 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -841,7 +849,7 @@
 		reg = <0x0570>;
 	};
 
-	uart6_gfclk_mux: uart6_gfclk_mux {
+	uart6_gfclk_mux: uart6_gfclk_mux@580 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -856,7 +864,7 @@
 	};
 };
 &prm_clocks {
-	sys_clkin1: sys_clkin1 {
+	sys_clkin1: sys_clkin1@110 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -864,28 +872,28 @@
 		ti,index-starts-at-one;
 	};
 
-	abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+	abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>;
 		reg = <0x0118>;
 	};
 
-	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 		reg = <0x0114>;
 	};
 
-	abe_dpll_clk_mux: abe_dpll_clk_mux {
+	abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 		reg = <0x010c>;
 	};
 
-	abe_24m_fclk: abe_24m_fclk {
+	abe_24m_fclk: abe_24m_fclk@11c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2x2_ck>;
@@ -893,7 +901,7 @@
 		ti,dividers = <8>, <16>;
 	};
 
-	aess_fclk: aess_fclk {
+	aess_fclk: aess_fclk@178 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&abe_clk>;
@@ -901,7 +909,7 @@
 		ti,max-div = <2>;
 	};
 
-	abe_giclk_div: abe_giclk_div {
+	abe_giclk_div: abe_giclk_div@174 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&aess_fclk>;
@@ -909,7 +917,7 @@
 		ti,max-div = <2>;
 	};
 
-	abe_lp_clk_div: abe_lp_clk_div {
+	abe_lp_clk_div: abe_lp_clk_div@1d8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2x2_ck>;
@@ -917,7 +925,7 @@
 		ti,dividers = <16>, <32>;
 	};
 
-	abe_sys_clk_div: abe_sys_clk_div {
+	abe_sys_clk_div: abe_sys_clk_div@120 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -925,14 +933,14 @@
 		ti,max-div = <2>;
 	};
 
-	adc_gfclk_mux: adc_gfclk_mux {
+	adc_gfclk_mux: adc_gfclk_mux@1dc {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 		reg = <0x01dc>;
 	};
 
-	sys_clk1_dclk_div: sys_clk1_dclk_div {
+	sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -941,7 +949,7 @@
 		ti,index-power-of-two;
 	};
 
-	sys_clk2_dclk_div: sys_clk2_dclk_div {
+	sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin2>;
@@ -950,7 +958,7 @@
 		ti,index-power-of-two;
 	};
 
-	per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+	per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2_ck>;
@@ -959,7 +967,7 @@
 		ti,index-power-of-two;
 	};
 
-	dsp_gclk_div: dsp_gclk_div {
+	dsp_gclk_div: dsp_gclk_div@18c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_dsp_m2_ck>;
@@ -968,7 +976,7 @@
 		ti,index-power-of-two;
 	};
 
-	gpu_dclk: gpu_dclk {
+	gpu_dclk: gpu_dclk@1a0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gpu_m2_ck>;
@@ -977,7 +985,7 @@
 		ti,index-power-of-two;
 	};
 
-	emif_phy_dclk_div: emif_phy_dclk_div {
+	emif_phy_dclk_div: emif_phy_dclk_div@190 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_ddr_m2_ck>;
@@ -986,7 +994,7 @@
 		ti,index-power-of-two;
 	};
 
-	gmac_250m_dclk_div: gmac_250m_dclk_div {
+	gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_m2_ck>;
@@ -995,7 +1003,7 @@
 		ti,index-power-of-two;
 	};
 
-	l3init_480m_dclk_div: l3init_480m_dclk_div {
+	l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -1004,7 +1012,7 @@
 		ti,index-power-of-two;
 	};
 
-	usb_otg_dclk_div: usb_otg_dclk_div {
+	usb_otg_dclk_div: usb_otg_dclk_div@184 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&usb_otg_clkin_ck>;
@@ -1013,7 +1021,7 @@
 		ti,index-power-of-two;
 	};
 
-	sata_dclk_div: sata_dclk_div {
+	sata_dclk_div: sata_dclk_div@1c0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -1022,7 +1030,7 @@
 		ti,index-power-of-two;
 	};
 
-	pcie2_dclk_div: pcie2_dclk_div {
+	pcie2_dclk_div: pcie2_dclk_div@1b8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_pcie_ref_m2_ck>;
@@ -1031,7 +1039,7 @@
 		ti,index-power-of-two;
 	};
 
-	pcie_dclk_div: pcie_dclk_div {
+	pcie_dclk_div: pcie_dclk_div@1b4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&apll_pcie_m2_ck>;
@@ -1040,7 +1048,7 @@
 		ti,index-power-of-two;
 	};
 
-	emu_dclk_div: emu_dclk_div {
+	emu_dclk_div: emu_dclk_div@194 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -1049,7 +1057,7 @@
 		ti,index-power-of-two;
 	};
 
-	secure_32k_dclk_div: secure_32k_dclk_div {
+	secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&secure_32k_clk_src_ck>;
@@ -1058,21 +1066,21 @@
 		ti,index-power-of-two;
 	};
 
-	clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+	clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
 		reg = <0x0158>;
 	};
 
-	clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+	clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
 		reg = <0x015c>;
 	};
 
-	clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+	clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
@@ -1087,21 +1095,21 @@
 		clock-div = <2>;
 	};
 
-	eve_clk: eve_clk {
+	eve_clk: eve_clk@180 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
 		reg = <0x0180>;
 	};
 
-	hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+	hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>;
 		reg = <0x0164>;
 	};
 
-	mlb_clk: mlb_clk {
+	mlb_clk: mlb_clk@134 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mlb_clkin_ck>;
@@ -1110,7 +1118,7 @@
 		ti,index-power-of-two;
 	};
 
-	mlbp_clk: mlbp_clk {
+	mlbp_clk: mlbp_clk@130 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mlbp_clkin_ck>;
@@ -1119,7 +1127,7 @@
 		ti,index-power-of-two;
 	};
 
-	per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+	per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2_ck>;
@@ -1128,7 +1136,7 @@
 		ti,index-power-of-two;
 	};
 
-	timer_sys_clk_div: timer_sys_clk_div {
+	timer_sys_clk_div: timer_sys_clk_div@144 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin1>;
@@ -1136,28 +1144,28 @@
 		ti,max-div = <2>;
 	};
 
-	video1_dpll_clk_mux: video1_dpll_clk_mux {
+	video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>;
 		reg = <0x0168>;
 	};
 
-	video2_dpll_clk_mux: video2_dpll_clk_mux {
+	video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>;
 		reg = <0x016c>;
 	};
 
-	wkupaon_iclk_mux: wkupaon_iclk_mux {
+	wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
 		reg = <0x0108>;
 	};
 
-	gpio1_dbclk: gpio1_dbclk {
+	gpio1_dbclk: gpio1_dbclk@1838 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1165,7 +1173,7 @@
 		reg = <0x1838>;
 	};
 
-	dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+	dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin2>;
@@ -1173,7 +1181,7 @@
 		reg = <0x1888>;
 	};
 
-	timer1_gfclk_mux: timer1_gfclk_mux {
+	timer1_gfclk_mux: timer1_gfclk_mux@1840 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1181,7 +1189,7 @@
 		reg = <0x1840>;
 	};
 
-	uart10_gfclk_mux: uart10_gfclk_mux {
+	uart10_gfclk_mux: uart10_gfclk_mux@1880 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1190,14 +1198,14 @@
 	};
 };
 &cm_core_clocks {
-	dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+	dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&sys_clkin1>;
 		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
 	};
 
-	dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+	dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_pcie_ref_ck>;
@@ -1216,7 +1224,7 @@
 		ti,bit-shift = <7>;
 	};
 
-	apll_pcie_ck: apll_pcie_ck {
+	apll_pcie_ck: apll_pcie_ck@21c {
 		#clock-cells = <0>;
 		compatible = "ti,dra7-apll-clock";
 		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
@@ -1305,7 +1313,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_per_byp_mux: dpll_per_byp_mux {
+	dpll_per_byp_mux: dpll_per_byp_mux@14c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
@@ -1313,14 +1321,14 @@
 		reg = <0x014c>;
 	};
 
-	dpll_per_ck: dpll_per_ck {
+	dpll_per_ck: dpll_per_ck@140 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
 		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
 	};
 
-	dpll_per_m2_ck: dpll_per_m2_ck {
+	dpll_per_m2_ck: dpll_per_m2_ck@150 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_ck>;
@@ -1339,7 +1347,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_usb_byp_mux: dpll_usb_byp_mux {
+	dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
@@ -1347,14 +1355,14 @@
 		reg = <0x018c>;
 	};
 
-	dpll_usb_ck: dpll_usb_ck {
+	dpll_usb_ck: dpll_usb_ck@180 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-j-type-clock";
 		clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
 		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
 	};
 
-	dpll_usb_m2_ck: dpll_usb_m2_ck {
+	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_ck>;
@@ -1365,7 +1373,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+	dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_pcie_ref_ck>;
@@ -1382,7 +1390,7 @@
 		clocks = <&dpll_per_ck>;
 	};
 
-	dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+	dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1393,7 +1401,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+	dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1404,7 +1412,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+	dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1415,7 +1423,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+	dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1426,7 +1434,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -1485,7 +1493,7 @@
 		clock-div = <2>;
 	};
 
-	l3init_60m_fclk: l3init_60m_fclk {
+	l3init_60m_fclk: l3init_60m_fclk@104 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -1493,7 +1501,7 @@
 		ti,dividers = <1>, <8>;
 	};
 
-	clkout2_clk: clkout2_clk {
+	clkout2_clk: clkout2_clk@6b0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&clkoutmux2_clk_mux>;
@@ -1501,7 +1509,7 @@
 		reg = <0x06b0>;
 	};
 
-	l3init_960m_gfclk: l3init_960m_gfclk {
+	l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_usb_clkdcoldo>;
@@ -1509,7 +1517,7 @@
 		reg = <0x06c0>;
 	};
 
-	dss_32khz_clk: dss_32khz_clk {
+	dss_32khz_clk: dss_32khz_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1517,7 +1525,7 @@
 		reg = <0x1120>;
 	};
 
-	dss_48mhz_clk: dss_48mhz_clk {
+	dss_48mhz_clk: dss_48mhz_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_48m_fclk>;
@@ -1525,7 +1533,7 @@
 		reg = <0x1120>;
 	};
 
-	dss_dss_clk: dss_dss_clk {
+	dss_dss_clk: dss_dss_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_per_h12x2_ck>;
@@ -1534,7 +1542,7 @@
 		ti,set-rate-parent;
 	};
 
-	dss_hdmi_clk: dss_hdmi_clk {
+	dss_hdmi_clk: dss_hdmi_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&hdmi_dpll_clk_mux>;
@@ -1542,7 +1550,7 @@
 		reg = <0x1120>;
 	};
 
-	dss_video1_clk: dss_video1_clk {
+	dss_video1_clk: dss_video1_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&video1_dpll_clk_mux>;
@@ -1550,7 +1558,7 @@
 		reg = <0x1120>;
 	};
 
-	dss_video2_clk: dss_video2_clk {
+	dss_video2_clk: dss_video2_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&video2_dpll_clk_mux>;
@@ -1558,7 +1566,7 @@
 		reg = <0x1120>;
 	};
 
-	gpio2_dbclk: gpio2_dbclk {
+	gpio2_dbclk: gpio2_dbclk@1760 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1566,7 +1574,7 @@
 		reg = <0x1760>;
 	};
 
-	gpio3_dbclk: gpio3_dbclk {
+	gpio3_dbclk: gpio3_dbclk@1768 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1574,7 +1582,7 @@
 		reg = <0x1768>;
 	};
 
-	gpio4_dbclk: gpio4_dbclk {
+	gpio4_dbclk: gpio4_dbclk@1770 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1582,7 +1590,7 @@
 		reg = <0x1770>;
 	};
 
-	gpio5_dbclk: gpio5_dbclk {
+	gpio5_dbclk: gpio5_dbclk@1778 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1590,7 +1598,7 @@
 		reg = <0x1778>;
 	};
 
-	gpio6_dbclk: gpio6_dbclk {
+	gpio6_dbclk: gpio6_dbclk@1780 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1598,7 +1606,7 @@
 		reg = <0x1780>;
 	};
 
-	gpio7_dbclk: gpio7_dbclk {
+	gpio7_dbclk: gpio7_dbclk@1810 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1606,7 +1614,7 @@
 		reg = <0x1810>;
 	};
 
-	gpio8_dbclk: gpio8_dbclk {
+	gpio8_dbclk: gpio8_dbclk@1818 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1614,7 +1622,7 @@
 		reg = <0x1818>;
 	};
 
-	mmc1_clk32k: mmc1_clk32k {
+	mmc1_clk32k: mmc1_clk32k@1328 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1622,7 +1630,7 @@
 		reg = <0x1328>;
 	};
 
-	mmc2_clk32k: mmc2_clk32k {
+	mmc2_clk32k: mmc2_clk32k@1330 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1630,7 +1638,7 @@
 		reg = <0x1330>;
 	};
 
-	mmc3_clk32k: mmc3_clk32k {
+	mmc3_clk32k: mmc3_clk32k@1820 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1638,7 +1646,7 @@
 		reg = <0x1820>;
 	};
 
-	mmc4_clk32k: mmc4_clk32k {
+	mmc4_clk32k: mmc4_clk32k@1828 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1646,7 +1654,7 @@
 		reg = <0x1828>;
 	};
 
-	sata_ref_clk: sata_ref_clk {
+	sata_ref_clk: sata_ref_clk@1388 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_clkin1>;
@@ -1654,7 +1662,7 @@
 		reg = <0x1388>;
 	};
 
-	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3init_960m_gfclk>;
@@ -1662,7 +1670,7 @@
 		reg = <0x13f0>;
 	};
 
-	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3init_960m_gfclk>;
@@ -1670,7 +1678,7 @@
 		reg = <0x1340>;
 	};
 
-	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1678,7 +1686,7 @@
 		reg = <0x0640>;
 	};
 
-	usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+	usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1686,7 +1694,7 @@
 		reg = <0x0688>;
 	};
 
-	usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+	usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1694,7 +1702,7 @@
 		reg = <0x0698>;
 	};
 
-	atl_dpll_clk_mux: atl_dpll_clk_mux {
+	atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
@@ -1702,7 +1710,7 @@
 		reg = <0x0c00>;
 	};
 
-	atl_gfclk_mux: atl_gfclk_mux {
+	atl_gfclk_mux: atl_gfclk_mux@c00 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
@@ -1710,7 +1718,7 @@
 		reg = <0x0c00>;
 	};
 
-	gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+	gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_gmac_m2_ck>;
@@ -1719,7 +1727,7 @@
 		ti,dividers = <2>;
 	};
 
-	gmac_rft_clk_mux: gmac_rft_clk_mux {
+	gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
@@ -1727,7 +1735,7 @@
 		reg = <0x13d0>;
 	};
 
-	gpu_core_gclk_mux: gpu_core_gclk_mux {
+	gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1735,7 +1743,7 @@
 		reg = <0x1220>;
 	};
 
-	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1743,7 +1751,7 @@
 		reg = <0x1220>;
 	};
 
-	l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+	l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&wkupaon_iclk_mux>;
@@ -1752,7 +1760,7 @@
 		ti,dividers = <8>, <16>, <32>;
 	};
 
-	mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+	mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1760,7 +1768,7 @@
 		reg = <0x1860>;
 	};
 
-	mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+	mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1768,7 +1776,7 @@
 		reg = <0x1860>;
 	};
 
-	mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+	mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1776,7 +1784,7 @@
 		reg = <0x1860>;
 	};
 
-	mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+	mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1784,7 +1792,7 @@
 		reg = <0x1868>;
 	};
 
-	mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+	mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1792,7 +1800,7 @@
 		reg = <0x1868>;
 	};
 
-	mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+	mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1800,7 +1808,7 @@
 		reg = <0x1898>;
 	};
 
-	mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+	mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1808,7 +1816,7 @@
 		reg = <0x1898>;
 	};
 
-	mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+	mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1816,7 +1824,7 @@
 		reg = <0x1878>;
 	};
 
-	mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+	mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1824,7 +1832,7 @@
 		reg = <0x1878>;
 	};
 
-	mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+	mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1832,7 +1840,7 @@
 		reg = <0x1904>;
 	};
 
-	mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+	mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1840,7 +1848,7 @@
 		reg = <0x1904>;
 	};
 
-	mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+	mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1848,7 +1856,7 @@
 		reg = <0x1908>;
 	};
 
-	mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+	mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1856,7 +1864,7 @@
 		reg = <0x1908>;
 	};
 
-	mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+	mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1864,7 +1872,7 @@
 		reg = <0x1890>;
 	};
 
-	mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+	mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1872,7 +1880,7 @@
 		reg = <0x1890>;
 	};
 
-	mmc1_fclk_mux: mmc1_fclk_mux {
+	mmc1_fclk_mux: mmc1_fclk_mux@1328 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1880,7 +1888,7 @@
 		reg = <0x1328>;
 	};
 
-	mmc1_fclk_div: mmc1_fclk_div {
+	mmc1_fclk_div: mmc1_fclk_div@1328 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mmc1_fclk_mux>;
@@ -1890,7 +1898,7 @@
 		ti,index-power-of-two;
 	};
 
-	mmc2_fclk_mux: mmc2_fclk_mux {
+	mmc2_fclk_mux: mmc2_fclk_mux@1330 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1898,7 +1906,7 @@
 		reg = <0x1330>;
 	};
 
-	mmc2_fclk_div: mmc2_fclk_div {
+	mmc2_fclk_div: mmc2_fclk_div@1330 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mmc2_fclk_mux>;
@@ -1908,7 +1916,7 @@
 		ti,index-power-of-two;
 	};
 
-	mmc3_gfclk_mux: mmc3_gfclk_mux {
+	mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1916,7 +1924,7 @@
 		reg = <0x1820>;
 	};
 
-	mmc3_gfclk_div: mmc3_gfclk_div {
+	mmc3_gfclk_div: mmc3_gfclk_div@1820 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mmc3_gfclk_mux>;
@@ -1926,7 +1934,7 @@
 		ti,index-power-of-two;
 	};
 
-	mmc4_gfclk_mux: mmc4_gfclk_mux {
+	mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1934,7 +1942,7 @@
 		reg = <0x1828>;
 	};
 
-	mmc4_gfclk_div: mmc4_gfclk_div {
+	mmc4_gfclk_div: mmc4_gfclk_div@1828 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mmc4_gfclk_mux>;
@@ -1944,7 +1952,7 @@
 		ti,index-power-of-two;
 	};
 
-	qspi_gfclk_mux: qspi_gfclk_mux {
+	qspi_gfclk_mux: qspi_gfclk_mux@1838 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
@@ -1952,7 +1960,7 @@
 		reg = <0x1838>;
 	};
 
-	qspi_gfclk_div: qspi_gfclk_div {
+	qspi_gfclk_div: qspi_gfclk_div@1838 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&qspi_gfclk_mux>;
@@ -1962,7 +1970,7 @@
 		ti,index-power-of-two;
 	};
 
-	timer10_gfclk_mux: timer10_gfclk_mux {
+	timer10_gfclk_mux: timer10_gfclk_mux@1728 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1970,7 +1978,7 @@
 		reg = <0x1728>;
 	};
 
-	timer11_gfclk_mux: timer11_gfclk_mux {
+	timer11_gfclk_mux: timer11_gfclk_mux@1730 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1978,7 +1986,7 @@
 		reg = <0x1730>;
 	};
 
-	timer13_gfclk_mux: timer13_gfclk_mux {
+	timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1986,7 +1994,7 @@
 		reg = <0x17c8>;
 	};
 
-	timer14_gfclk_mux: timer14_gfclk_mux {
+	timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1994,7 +2002,7 @@
 		reg = <0x17d0>;
 	};
 
-	timer15_gfclk_mux: timer15_gfclk_mux {
+	timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2002,7 +2010,7 @@
 		reg = <0x17d8>;
 	};
 
-	timer16_gfclk_mux: timer16_gfclk_mux {
+	timer16_gfclk_mux: timer16_gfclk_mux@1830 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2010,7 +2018,7 @@
 		reg = <0x1830>;
 	};
 
-	timer2_gfclk_mux: timer2_gfclk_mux {
+	timer2_gfclk_mux: timer2_gfclk_mux@1738 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2018,7 +2026,7 @@
 		reg = <0x1738>;
 	};
 
-	timer3_gfclk_mux: timer3_gfclk_mux {
+	timer3_gfclk_mux: timer3_gfclk_mux@1740 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2026,7 +2034,7 @@
 		reg = <0x1740>;
 	};
 
-	timer4_gfclk_mux: timer4_gfclk_mux {
+	timer4_gfclk_mux: timer4_gfclk_mux@1748 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2034,7 +2042,7 @@
 		reg = <0x1748>;
 	};
 
-	timer9_gfclk_mux: timer9_gfclk_mux {
+	timer9_gfclk_mux: timer9_gfclk_mux@1750 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2042,7 +2050,7 @@
 		reg = <0x1750>;
 	};
 
-	uart1_gfclk_mux: uart1_gfclk_mux {
+	uart1_gfclk_mux: uart1_gfclk_mux@1840 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2050,7 +2058,7 @@
 		reg = <0x1840>;
 	};
 
-	uart2_gfclk_mux: uart2_gfclk_mux {
+	uart2_gfclk_mux: uart2_gfclk_mux@1848 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2058,7 +2066,7 @@
 		reg = <0x1848>;
 	};
 
-	uart3_gfclk_mux: uart3_gfclk_mux {
+	uart3_gfclk_mux: uart3_gfclk_mux@1850 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2066,7 +2074,7 @@
 		reg = <0x1850>;
 	};
 
-	uart4_gfclk_mux: uart4_gfclk_mux {
+	uart4_gfclk_mux: uart4_gfclk_mux@1858 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2074,7 +2082,7 @@
 		reg = <0x1858>;
 	};
 
-	uart5_gfclk_mux: uart5_gfclk_mux {
+	uart5_gfclk_mux: uart5_gfclk_mux@1870 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2082,7 +2090,7 @@
 		reg = <0x1870>;
 	};
 
-	uart7_gfclk_mux: uart7_gfclk_mux {
+	uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2090,7 +2098,7 @@
 		reg = <0x18d0>;
 	};
 
-	uart8_gfclk_mux: uart8_gfclk_mux {
+	uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2098,7 +2106,7 @@
 		reg = <0x18e0>;
 	};
 
-	uart9_gfclk_mux: uart9_gfclk_mux {
+	uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2106,7 +2114,7 @@
 		reg = <0x18e8>;
 	};
 
-	vip1_gclk_mux: vip1_gclk_mux {
+	vip1_gclk_mux: vip1_gclk_mux@1020 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2114,7 +2122,7 @@
 		reg = <0x1020>;
 	};
 
-	vip2_gclk_mux: vip2_gclk_mux {
+	vip2_gclk_mux: vip2_gclk_mux@1028 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2122,7 +2130,7 @@
 		reg = <0x1028>;
 	};
 
-	vip3_gclk_mux: vip3_gclk_mux {
+	vip3_gclk_mux: vip3_gclk_mux@1030 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2139,11 +2147,43 @@
 };
 
 &scm_conf_clocks {
-	dss_deshdcp_clk: dss_deshdcp_clk {
+	dss_deshdcp_clk: dss_deshdcp_clk@558 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3_iclk_div>;
 		ti,bit-shift = <0>;
 		reg = <0x558>;
 	};
+
+       ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_root_clk_div>;
+		ti,bit-shift = <20>;
+		reg = <0x0558>;
+	};
+
+	ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_root_clk_div>;
+		ti,bit-shift = <21>;
+		reg = <0x0558>;
+	};
+
+	ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l4_root_clk_div>;
+		ti,bit-shift = <22>;
+		reg = <0x0558>;
+	};
+
+	sys_32k_ck: sys_32k_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x6c4>;
+	};
 };
diff --git a/sys/gnu/dts/arm/emev2-kzm9d.dts b/sys/gnu/dts/arm/emev2-kzm9d.dts
index 8c24975e8f9d..a35b851e1cd7 100644
--- a/sys/gnu/dts/arm/emev2-kzm9d.dts
+++ b/sys/gnu/dts/arm/emev2-kzm9d.dts
@@ -105,8 +105,8 @@
 
 &pfc {
 	uart1_pins: serial@e1030000 {
-		renesas,groups = "uart1_ctrl", "uart1_data";
-		renesas,function = "uart1";
+		groups = "uart1_ctrl", "uart1_data";
+		function = "uart1";
 	};
 };
 
diff --git a/sys/gnu/dts/arm/emev2.dtsi b/sys/gnu/dts/arm/emev2.dtsi
index 57795da616cb..bcce6f50c93d 100644
--- a/sys/gnu/dts/arm/emev2.dtsi
+++ b/sys/gnu/dts/arm/emev2.dtsi
@@ -9,6 +9,7 @@
  */
 
 #include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -53,8 +54,8 @@
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 121 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	clocks@e0110000 {
@@ -158,7 +159,7 @@
 	timer@e0180000 {
 		compatible = "renesas,em-sti";
 		reg = <0xe0180000 0x54>;
-		interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&sti_sclk>;
 		clock-names = "sclk";
 	};
@@ -166,7 +167,7 @@
 	uart0: serial@e1020000 {
 		compatible = "renesas,em-uart";
 		reg = <0xe1020000 0x38>;
-		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&usia_u0_sclk>;
 		clock-names = "sclk";
 	};
@@ -174,7 +175,7 @@
 	uart1: serial@e1030000 {
 		compatible = "renesas,em-uart";
 		reg = <0xe1030000 0x38>;
-		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&usib_u1_sclk>;
 		clock-names = "sclk";
 	};
@@ -182,7 +183,7 @@
 	uart2: serial@e1040000 {
 		compatible = "renesas,em-uart";
 		reg = <0xe1040000 0x38>;
-		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&usib_u2_sclk>;
 		clock-names = "sclk";
 	};
@@ -190,7 +191,7 @@
 	uart3: serial@e1050000 {
 		compatible = "renesas,em-uart";
 		reg = <0xe1050000 0x38>;
-		interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&usib_u3_sclk>;
 		clock-names = "sclk";
 	};
@@ -203,8 +204,8 @@
 	gpio0: gpio@e0050000 {
 		compatible = "renesas,em-gio";
 		reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
-		interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 68 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 0 32>;
 		#gpio-cells = <2>;
@@ -215,8 +216,8 @@
 	gpio1: gpio@e0050080 {
 		compatible = "renesas,em-gio";
 		reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
-		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 70 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 32 32>;
 		#gpio-cells = <2>;
@@ -227,8 +228,8 @@
 	gpio2: gpio@e0050100 {
 		compatible = "renesas,em-gio";
 		reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
-		interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 72 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 64 32>;
 		#gpio-cells = <2>;
@@ -239,8 +240,8 @@
 	gpio3: gpio@e0050180 {
 		compatible = "renesas,em-gio";
 		reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
-		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 74 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 96 32>;
 		#gpio-cells = <2>;
@@ -251,8 +252,8 @@
 	gpio4: gpio@e0050200 {
 		compatible = "renesas,em-gio";
 		reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
-		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 76 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 128 31>;
 		#gpio-cells = <2>;
@@ -266,7 +267,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-emev2";
 		reg = <0xe0070000 0x28>;
-		interrupts = <0 32 IRQ_TYPE_EDGE_RISING>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
 		clocks = <&iic0_sclk>;
 		clock-names = "sclk";
 		status = "disabled";
@@ -277,7 +278,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-emev2";
 		reg = <0xe10a0000 0x28>;
-		interrupts = <0 33 IRQ_TYPE_EDGE_RISING>;
+		interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
 		clocks = <&iic1_sclk>;
 		clock-names = "sclk";
 		status = "disabled";
diff --git a/sys/gnu/dts/arm/exynos-syscon-restart.dtsi b/sys/gnu/dts/arm/exynos-syscon-restart.dtsi
new file mode 100644
index 000000000000..09a2040054ed
--- /dev/null
+++ b/sys/gnu/dts/arm/exynos-syscon-restart.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+	soc {
+		compatible = "simple-bus";
+
+		poweroff: syscon-poweroff {
+			compatible = "syscon-poweroff";
+			regmap = <&pmu_system_controller>;
+			offset = <0x330C>; /* PS_HOLD_CONTROL */
+			mask = <0x5200>; /* reset value */
+		};
+
+		reboot: syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pmu_system_controller>;
+			offset = <0x0400>; /* SWRESET */
+			mask = <0x1>;
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/exynos3250-artik5-eval.dts b/sys/gnu/dts/arm/exynos3250-artik5-eval.dts
new file mode 100644
index 000000000000..be4d6aa379f3
--- /dev/null
+++ b/sys/gnu/dts/arm/exynos3250-artik5-eval.dts
@@ -0,0 +1,43 @@
+/*
+ * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Device tree source file for Samsung's ARTIK5 evaluation board
+ * which is based on Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos3250-artik5.dtsi"
+
+/ {
+	model = "Samsung ARTIK5 evaluation board";
+	compatible = "samsung,artik5-eval", "samsung,artik5",
+			"samsung,exynos3250", "samsung,exynos3";
+};
+
+&mshc_2 {
+	num-slots = <1>;
+	cap-sd-highspeed;
+	disable-wp;
+	vqmmc-supply = <&ldo3_reg>;
+	card-detect-delay = <200>;
+	clock-frequency = <100000000>;
+	clock-freq-min-max = <400000 100000000>;
+	samsung,dw-mshc-ciu-div = <1>;
+	samsung,dw-mshc-sdr-timing = <0 1>;
+	samsung,dw-mshc-ddr-timing = <1 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&serial_2 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/exynos3250-artik5.dtsi b/sys/gnu/dts/arm/exynos3250-artik5.dtsi
new file mode 100644
index 000000000000..130e946f1414
--- /dev/null
+++ b/sys/gnu/dts/arm/exynos3250-artik5.dtsi
@@ -0,0 +1,334 @@
+/*
+ * Samsung's Exynos3250 based ARTIK5 module device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Device tree source file for Samsung's ARTIK5 module which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "exynos3250.dtsi"
+#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3";
+
+	chosen {
+		stdout-path = &serial_2;
+	};
+
+	memory {
+		reg = <0x40000000 0x1ff00000>;
+	};
+
+	firmware@0205f000 {
+		compatible = "samsung,secure-firmware";
+		reg = <0x0205f000 0x1000>;
+	};
+
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			cooling-maps {
+				map0 {
+					/* Corresponds to 500MHz */
+					cooling-device = <&cpu0 5 5>;
+				};
+				map1 {
+					/* Corresponds to 200MHz */
+					cooling-device = <&cpu0 8 8>;
+				};
+			};
+		};
+	};
+};
+
+&adc {
+	vdd-supply = <&ldo7_reg>;
+	assigned-clocks = <&cmu CLK_SCLK_TSADC>;
+	assigned-clock-rates = <6000000>;
+};
+
+&cpu0 {
+	cpu0-supply = <&buck2_reg>;
+};
+
+&i2c_0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	samsung,i2c-sda-delay = <100>;
+	samsung,i2c-slave-addr = <0x10>;
+	samsung,i2c-max-bus-freq = <100000>;
+	status = "okay";
+
+	s2mps14_pmic@66 {
+		compatible = "samsung,s2mps14-pmic";
+		interrupt-parent = <&gpx3>;
+		interrupts = <5 IRQ_TYPE_NONE>;
+		reg = <0x66>;
+
+		s2mps14_osc: clocks {
+			compatible = "samsung,s2mps14-clk";
+			#clock-cells = <1>;
+			clock-output-names = "s2mps14_ap", "unused",
+				"s2mps14_bt";
+		};
+
+		regulators {
+			ldo1_reg: LDO1 {
+				/* VDD_ALIVE15x */
+				regulator-name = "VLDO1_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				/* VDDQM176 ~ VDDQM185 */
+				regulator-name = "VLDO2_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
+
+			ldo3_reg: LDO3 {
+				/*
+				 * VDD1_E106 ~ VDD1_E111
+				 * DVDD_RTC_AP, DVDD_MMC2_AP
+				 */
+				regulator-name = "VLDO3_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				/*  AVDD_PLL1120 ~ AVDD_PLL11201 */
+				regulator-name = "VLDO4_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo5_reg: LDO5 {
+				/* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */
+				regulator-name = "VLDO5_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			ldo6_reg: LDO6 {
+				/* VDD_USB, VDD10_HSIC */
+				regulator-name = "VLDO6_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			ldo7_reg: LDO7 {
+				/*
+				 * VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2,
+				 * AVDD_ADC, AVDD_ABB_0, M4S_VDD18
+				 */
+				regulator-name = "VLDO7_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo8_reg: LDO8 {
+				/* AVDD33_UOTG */
+				regulator-name = "VLDO8_3.0V";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			ldo9_reg: LDO9 {
+				/* VDDQ_E86 ~ VDDQ_E105*/
+				regulator-name = "VLDO9_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
+
+			ldo10_reg: LDO10 {
+				regulator-name = "VLDO10_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+			};
+
+			ldo11_reg: LDO11 {
+				/* VDD74 ~ VDD75 */
+				regulator-name = "VLDO11_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+			};
+
+			ldo12_reg: LDO12 {
+				/* VDD72 ~ VDD73 */
+				regulator-name = "VLDO12_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+			};
+
+			ldo13_reg: LDO13 {
+				regulator-name = "VLDO13_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+
+			ldo14_reg: LDO14 {
+				regulator-name = "VLDO14_2.7V";
+				regulator-min-microvolt = <2700000>;
+				regulator-max-microvolt = <2700000>;
+			};
+
+			ldo15_reg: LDO15 {
+				regulator-name = "VLDO_3.3V";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo16_reg: LDO16 {
+				regulator-name = "VLDO16_3.3V";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo17_reg: LDO17 {
+				regulator-name = "VLDO17_3.0V";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+			};
+
+			ldo18_reg: LDO18 {
+				/* DVDD_MMC2_AP */
+				regulator-name = "VLDO18_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+
+			ldo19_reg: LDO19 {
+				regulator-name = "VLDO19_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo20_reg: LDO20 {
+				regulator-name = "VLDO20_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo21_reg: LDO21 {
+				regulator-name = "VLDO21_1.25V";
+				regulator-min-microvolt = <1250000>;
+				regulator-max-microvolt = <1250000>;
+			};
+
+			ldo22_reg: LDO22 {
+				regulator-name = "VLDO22_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+			};
+
+			ldo23_reg: LDO23 {
+				/* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */
+				regulator-name = "VLDO23_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo24_reg: LDO24 {
+				regulator-name = "VLDO24_3.0V";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+			};
+
+			ldo25_reg: LDO25 {
+				regulator-name = "VLDO25_3.0V";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+			};
+
+			buck1_reg: BUCK1 {
+				/* VDD_MIF */
+				regulator-name = "VBUCK1_1.0V";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			buck2_reg: BUCK2 {
+				/* VDD_CPU */
+				regulator-name = "VBUCK2_1.2V";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
+
+			buck3_reg: BUCK3 {
+				/* VDD_G3D */
+				regulator-name = "VBUCK3_1.0V";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			buck4_reg: BUCK4 {
+				regulator-name = "VBUCK4_1.95V";
+				regulator-min-microvolt = <1950000>;
+				regulator-max-microvolt = <1950000>;
+				regulator-always-on;
+			};
+
+			buck5_reg: BUCK5 {
+				regulator-name = "VBUCK5_1.35V";
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&mshc_0 {
+	num-slots = <1>;
+	non-removable;
+	cap-mmc-highspeed;
+	card-detect-delay = <200>;
+	vmmc-supply = <&ldo12_reg>;
+	clock-frequency = <100000000>;
+	clock-freq-min-max = <400000 100000000>;
+	samsung,dw-mshc-ciu-div = <1>;
+	samsung,dw-mshc-sdr-timing = <0 1>;
+	samsung,dw-mshc-ddr-timing = <1 2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
+	clock-names = "rtc", "rtc_src";
+	status = "okay";
+};
+
+&tmu {
+	status = "okay";
+};
+
+&xusbxti {
+	clock-frequency = <24000000>;
+};
diff --git a/sys/gnu/dts/arm/exynos3250-monk.dts b/sys/gnu/dts/arm/exynos3250-monk.dts
index 443a35085846..8c8906266310 100644
--- a/sys/gnu/dts/arm/exynos3250-monk.dts
+++ b/sys/gnu/dts/arm/exynos3250-monk.dts
@@ -14,6 +14,7 @@
 
 /dts-v1/;
 #include "exynos3250.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/samsung,s2mps11.h>
@@ -43,7 +44,7 @@
 			linux,code = <KEY_POWER>;
 			label = "power key";
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -67,7 +68,7 @@
 			interrupt-parent = <&gpx1>;
 			interrupts = <5 0>;
 			reg = <0x25>;
-			wakeup;
+			wakeup-source;
 
 			muic: max77836-muic {
 				compatible = "maxim,max77836-muic";
@@ -156,6 +157,12 @@
 	};
 };
 
+&bus_dmc {
+	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
 &cpu0 {
 	cpu0-supply = <&buck2_reg>;
 };
@@ -185,7 +192,7 @@
 		interrupt-parent = <&gpx0>;
 		interrupts = <7 0>;
 		reg = <0x66>;
-		wakeup;
+		wakeup-source;
 
 		s2mps14_osc: clocks {
 			compatible = "samsung,s2mps14-clk";
@@ -458,46 +465,6 @@
 	status = "okay";
 };
 
-&ppmu_dmc0 {
-	status = "okay";
-
-	events {
-		ppmu_dmc0_3: ppmu-event3-dmc0 {
-			event-name = "ppmu-event3-dmc0";
-		};
-	};
-};
-
-&ppmu_dmc1 {
-	status = "okay";
-
-	events {
-		ppmu_dmc1_3: ppmu-event3-dmc1 {
-			event-name = "ppmu-event3-dmc1";
-		};
-	};
-};
-
-&ppmu_leftbus {
-	status = "okay";
-
-	events {
-		ppmu_leftbus_3: ppmu-event3-leftbus {
-			event-name = "ppmu-event3-leftbus";
-		};
-	};
-};
-
-&ppmu_rightbus {
-	status = "okay";
-
-	events {
-		ppmu_rightbus_3: ppmu-event3-rightbus {
-			event-name = "ppmu-event3-rightbus";
-		};
-	};
-};
-
 &xusbxti {
 	clock-frequency = <24000000>;
 };
@@ -558,7 +525,17 @@
 
 &pinctrl_1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&sleep1>;
+	pinctrl-0 = <&initial1 &sleep1>;
+
+	initial1: initial-state {
+		PIN_IN(gpk2-0, DOWN, LV1);
+		PIN_IN(gpk2-1, DOWN, LV1);
+		PIN_IN(gpk2-2, DOWN, LV1);
+		PIN_IN(gpk2-3, DOWN, LV1);
+		PIN_IN(gpk2-4, DOWN, LV1);
+		PIN_IN(gpk2-5, DOWN, LV1);
+		PIN_IN(gpk2-6, DOWN, LV1);
+	};
 
 	sleep1: sleep-state {
 		PIN_SLP(gpe0-0, PREV, NONE);
diff --git a/sys/gnu/dts/arm/exynos3250-pinctrl.dtsi b/sys/gnu/dts/arm/exynos3250-pinctrl.dtsi
index 5ab81c39e2c9..40ea7de44933 100644
--- a/sys/gnu/dts/arm/exynos3250-pinctrl.dtsi
+++ b/sys/gnu/dts/arm/exynos3250-pinctrl.dtsi
@@ -16,11 +16,49 @@
 #define PIN_PULL_DOWN		1
 #define PIN_PULL_UP		3
 
+#define PIN_DRV_LV1		0
+#define PIN_DRV_LV2		2
+#define PIN_DRV_LV3		1
+#define PIN_DRV_LV4		3
+
 #define PIN_PDN_OUT0		0
 #define PIN_PDN_OUT1		1
 #define PIN_PDN_INPUT		2
 #define PIN_PDN_PREV		3
 
+#define PIN_IN(_pin, _pull, _drv)			\
+	_pin {						\
+		samsung,pins = #_pin;			\
+		samsung,pin-function = <0>;		\
+		samsung,pin-pud = <PIN_PULL_ ##_pull>;	\
+		samsung,pin-drv = <PIN_DRV_ ##_drv>;	\
+	}
+
+#define PIN_OUT(_pin, _drv)				\
+	_pin {						\
+		samsung,pins = #_pin;			\
+		samsung,pin-function = <1>;		\
+		samsung,pin-pud = <0>;			\
+		samsung,pin-drv = <PIN_DRV_ ##_drv>;	\
+	}
+
+#define PIN_OUT_SET(_pin, _val, _drv)			\
+	_pin {						\
+		samsung,pins = #_pin;			\
+		samsung,pin-function = <1>;		\
+		samsung,pin-pud = <0>;			\
+		samsung,pin-drv = <PIN_DRV_ ##_drv>;	\
+		samsung,pin-val = <_val>;		\
+	}
+
+#define PIN_CFG(_pin, _sel, _pull, _drv)		\
+	_pin {						\
+		samsung,pins = #_pin;			\
+		samsung,pin-function = <_sel>;		\
+		samsung,pin-pud = <PIN_PULL_ ##_pull>;	\
+		samsung,pin-drv = <PIN_DRV_ ##_drv>;	\
+	}
+
 #define PIN_SLP(_pin, _mode, _pull)				\
 	_pin {							\
 		samsung,pins = #_pin;				\
@@ -120,6 +158,13 @@
 		samsung,pin-drv = <0>;
 	};
 
+	uart2_data: uart2-data {
+		samsung,pins = "gpa1-0", "gpa1-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <0>;
+	};
+
 	i2c3_bus: i2c3-bus {
 		samsung,pins = "gpa1-2", "gpa1-3";
 		samsung,pin-function = <3>;
@@ -445,6 +490,41 @@
 		samsung,pin-drv = <3>;
 	};
 
+	sd2_clk: sd2-clk {
+		samsung,pins = "gpk2-0";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_cmd: sd2-cmd {
+		samsung,pins = "gpk2-1";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <0>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_cd: sd2-cd {
+		samsung,pins = "gpk2-2";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_bus1: sd2-bus-width1 {
+		samsung,pins = "gpk2-3";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
+	sd2_bus4: sd2-bus-width4 {
+		samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <3>;
+	};
+
 	cam_port_b_io: cam-port-b-io {
 		samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
 				"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
diff --git a/sys/gnu/dts/arm/exynos3250-rinato.dts b/sys/gnu/dts/arm/exynos3250-rinato.dts
index 3e64d5dcdd60..e422819591dc 100644
--- a/sys/gnu/dts/arm/exynos3250-rinato.dts
+++ b/sys/gnu/dts/arm/exynos3250-rinato.dts
@@ -14,6 +14,7 @@
 
 /dts-v1/;
 #include "exynos3250.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/samsung,s2mps11.h>
@@ -43,7 +44,7 @@
 			linux,code = <KEY_POWER>;
 			label = "power key";
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -58,7 +59,7 @@
 			interrupt-parent = <&gpx1>;
 			interrupts = <5 0>;
 			reg = <0x25>;
-			wakeup;
+			wakeup-source;
 
 			muic: max77836-muic {
 				compatible = "maxim,max77836-muic";
@@ -147,6 +148,53 @@
 	};
 };
 
+&bus_dmc {
+	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
+&bus_leftbus {
+	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+	vdd-supply = <&buck3_reg>;
+	status = "okay";
+};
+
+&bus_rightbus {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_lcd0 {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_fsys {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_mcuisp {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_isp {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_peril {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_mfc {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
 &cpu0 {
 	cpu0-supply = <&buck2_reg>;
 };
@@ -246,7 +294,7 @@
 		interrupt-parent = <&gpx0>;
 		interrupts = <7 0>;
 		reg = <0x66>;
-		wakeup;
+		wakeup-source;
 
 		s2mps14_osc: clocks {
 			compatible = "samsung,s2mps14-clk";
@@ -635,53 +683,27 @@
 	status = "okay";
 };
 
-&ppmu_dmc0 {
-	status = "okay";
-
-	events {
-		ppmu_dmc0_3: ppmu-event3-dmc0 {
-			event-name = "ppmu-event3-dmc0";
-		};
-	};
-};
-
-&ppmu_dmc1 {
-	status = "okay";
-
-	events {
-		ppmu_dmc1_3: ppmu-event3-dmc1 {
-			event-name = "ppmu-event3-dmc1";
-		};
-	};
-};
-
-&ppmu_leftbus {
-	status = "okay";
-
-	events {
-		ppmu_leftbus_3: ppmu-event3-leftbus {
-			event-name = "ppmu-event3-leftbus";
-		};
-	};
-};
-
-&ppmu_rightbus {
-	status = "okay";
-
-	events {
-		ppmu_rightbus_3: ppmu-event3-rightbus {
-			event-name = "ppmu-event3-rightbus";
-		};
-	};
-};
-
 &xusbxti {
 	clock-frequency = <24000000>;
 };
 
 &pinctrl_0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&sleep0>;
+	pinctrl-0 = <&initial0 &sleep0>;
+
+	initial0: initial-state {
+		PIN_IN(gpa1-4, DOWN, LV1);
+		PIN_IN(gpa1-5, DOWN, LV1);
+
+		PIN_IN(gpc0-0, DOWN, LV1);
+		PIN_IN(gpc0-1, DOWN, LV1);
+		PIN_IN(gpc0-2, DOWN, LV1);
+		PIN_IN(gpc0-3, DOWN, LV1);
+		PIN_IN(gpc0-4, DOWN, LV1);
+
+		PIN_IN(gpd0-0, DOWN, LV1);
+		PIN_IN(gpd0-1, DOWN, LV1);
+	};
 
 	sleep0: sleep-state {
 		PIN_SLP(gpa0-0, INPUT, DOWN);
@@ -735,7 +757,60 @@
 
 &pinctrl_1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&sleep1>;
+	pinctrl-0 = <&initial1 &sleep1>;
+
+	initial1: initial-state {
+		PIN_IN(gpe0-6, DOWN, LV1);
+		PIN_IN(gpe0-7, DOWN, LV1);
+
+		PIN_IN(gpe1-0, DOWN, LV1);
+		PIN_IN(gpe1-3, DOWN, LV1);
+		PIN_IN(gpe1-4, DOWN, LV1);
+		PIN_IN(gpe1-5, DOWN, LV1);
+		PIN_IN(gpe1-6, DOWN, LV1);
+
+		PIN_IN(gpk2-0, DOWN, LV1);
+		PIN_IN(gpk2-1, DOWN, LV1);
+		PIN_IN(gpk2-2, DOWN, LV1);
+		PIN_IN(gpk2-3, DOWN, LV1);
+		PIN_IN(gpk2-4, DOWN, LV1);
+		PIN_IN(gpk2-5, DOWN, LV1);
+		PIN_IN(gpk2-6, DOWN, LV1);
+
+		PIN_IN(gpm0-0, DOWN, LV1);
+		PIN_IN(gpm0-1, DOWN, LV1);
+		PIN_IN(gpm0-2, DOWN, LV1);
+		PIN_IN(gpm0-3, DOWN, LV1);
+		PIN_IN(gpm0-4, DOWN, LV1);
+		PIN_IN(gpm0-5, DOWN, LV1);
+		PIN_IN(gpm0-6, DOWN, LV1);
+		PIN_IN(gpm0-7, DOWN, LV1);
+
+		PIN_IN(gpm1-0, DOWN, LV1);
+		PIN_IN(gpm1-1, DOWN, LV1);
+		PIN_IN(gpm1-2, DOWN, LV1);
+		PIN_IN(gpm1-3, DOWN, LV1);
+		PIN_IN(gpm1-4, DOWN, LV1);
+		PIN_IN(gpm1-5, DOWN, LV1);
+		PIN_IN(gpm1-6, DOWN, LV1);
+
+		PIN_IN(gpm2-0, DOWN, LV1);
+		PIN_IN(gpm2-1, DOWN, LV1);
+
+		PIN_IN(gpm3-0, DOWN, LV1);
+		PIN_IN(gpm3-1, DOWN, LV1);
+		PIN_IN(gpm3-2, DOWN, LV1);
+		PIN_IN(gpm3-3, DOWN, LV1);
+		PIN_IN(gpm3-4, DOWN, LV1);
+
+		PIN_IN(gpm4-1, DOWN, LV1);
+		PIN_IN(gpm4-2, DOWN, LV1);
+		PIN_IN(gpm4-3, DOWN, LV1);
+		PIN_IN(gpm4-4, DOWN, LV1);
+		PIN_IN(gpm4-5, DOWN, LV1);
+		PIN_IN(gpm4-6, DOWN, LV1);
+		PIN_IN(gpm4-7, DOWN, LV1);
+	};
 
 	sleep1: sleep-state {
 		PIN_SLP(gpe0-0, PREV, NONE);
diff --git a/sys/gnu/dts/arm/exynos3250.dtsi b/sys/gnu/dts/arm/exynos3250.dtsi
index 18e3deffbf48..62f3dcd9e046 100644
--- a/sys/gnu/dts/arm/exynos3250.dtsi
+++ b/sys/gnu/dts/arm/exynos3250.dtsi
@@ -19,6 +19,7 @@
 
 #include "skeleton.dtsi"
 #include "exynos4-cpu-thermal.dtsi"
+#include "exynos-syscon-restart.dtsi"
 #include <dt-bindings/clock/exynos3250.h>
 
 / {
@@ -30,6 +31,7 @@
 		pinctrl1 = &pinctrl_1;
 		mshc0 = &mshc_0;
 		mshc1 = &mshc_1;
+		mshc2 = &mshc_2;
 		spi0 = &spi_0;
 		spi1 = &spi_1;
 		i2c0 = &i2c_0;
@@ -42,6 +44,7 @@
 		i2c7 = &i2c_7;
 		serial0 = &serial_0;
 		serial1 = &serial_1;
+		serial2 = &serial_2;
 	};
 
 	cpus {
@@ -152,21 +155,7 @@
 			interrupt-parent = <&gic>;
 		};
 
-		poweroff: syscon-poweroff {
-			compatible = "syscon-poweroff";
-			regmap = <&pmu_system_controller>;
-			offset = <0x330C>; /* PS_HOLD_CONTROL */
-			mask = <0x5200>; /* Reset value */
-		};
-
-		reboot: syscon-reboot {
-			compatible = "syscon-reboot";
-			regmap = <&pmu_system_controller>;
-			offset = <0x0400>; /* SWRESET */
-			mask = <0x1>;
-		};
-
-		mipi_phy: video-phy@10020710 {
+		mipi_phy: video-phy {
 			compatible = "samsung,s5pv210-mipi-video-phy";
 			#phy-cells = <1>;
 			syscon = <&pmu_system_controller>;
@@ -370,6 +359,18 @@
 			status = "disabled";
 		};
 
+		mshc_2: mshc@12530000 {
+			compatible = "samsung,exynos5250-dw-mshc";
+			reg = <0x12530000 0x1000>;
+			interrupts = <0 144 0>;
+			clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		exynos_usbphy: exynos-usbphy@125B0000 {
 			compatible = "samsung,exynos3250-usb2-phy";
 			reg = <0x125B0000 0x100>;
@@ -381,7 +382,7 @@
 		};
 
 		amba {
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -465,6 +466,17 @@
 			status = "disabled";
 		};
 
+		serial_2: serial@13820000 {
+			compatible = "samsung,exynos4210-uart";
+			reg = <0x13820000 0x100>;
+			interrupts = <0 111 0>;
+			clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+			clock-names = "uart", "clk_uart_baud0";
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_data>;
+			status = "disabled";
+		};
+
 		i2c_0: i2c@13860000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -701,6 +713,187 @@
 			clock-names = "ppmu";
 			status = "disabled";
 		};
+
+		bus_dmc: bus_dmc {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu_dmc CLK_DIV_DMC>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_dmc_opp_table>;
+			status = "disabled";
+		};
+
+		bus_dmc_opp_table: opp_table1 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp@50000000 {
+				opp-hz = /bits/ 64 <50000000>;
+				opp-microvolt = <800000>;
+			};
+			opp@100000000 {
+				opp-hz = /bits/ 64 <100000000>;
+				opp-microvolt = <800000>;
+			};
+			opp@134000000 {
+				opp-hz = /bits/ 64 <134000000>;
+				opp-microvolt = <800000>;
+			};
+			opp@200000000 {
+				opp-hz = /bits/ 64 <200000000>;
+				opp-microvolt = <825000>;
+			};
+			opp@400000000 {
+				opp-hz = /bits/ 64 <400000000>;
+				opp-microvolt = <875000>;
+			};
+		};
+
+		bus_leftbus: bus_leftbus {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_GDL>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_rightbus: bus_rightbus {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_GDR>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_lcd0: bus_lcd0 {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_160>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_fsys: bus_fsys {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_200>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_mcuisp: bus_mcuisp {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_mcuisp_opp_table>;
+			status = "disabled";
+		};
+
+		bus_isp: bus_isp {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_266>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_isp_opp_table>;
+			status = "disabled";
+		};
+
+		bus_peril: bus_peril {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_DIV_ACLK_100>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_peril_opp_table>;
+			status = "disabled";
+		};
+
+		bus_mfc: bus_mfc {
+			compatible = "samsung,exynos-bus";
+			clocks = <&cmu CLK_SCLK_MFC>;
+			clock-names = "bus";
+			operating-points-v2 = <&bus_leftbus_opp_table>;
+			status = "disabled";
+		};
+
+		bus_leftbus_opp_table: opp_table2 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp@50000000 {
+				opp-hz = /bits/ 64 <50000000>;
+				opp-microvolt = <900000>;
+			};
+			opp@80000000 {
+				opp-hz = /bits/ 64 <80000000>;
+				opp-microvolt = <900000>;
+			};
+			opp@100000000 {
+				opp-hz = /bits/ 64 <100000000>;
+				opp-microvolt = <1000000>;
+			};
+			opp@134000000 {
+				opp-hz = /bits/ 64 <134000000>;
+				opp-microvolt = <1000000>;
+			};
+			opp@200000000 {
+				opp-hz = /bits/ 64 <200000000>;
+				opp-microvolt = <1000000>;
+			};
+		};
+
+		bus_mcuisp_opp_table: opp_table3 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp@50000000 {
+				opp-hz = /bits/ 64 <50000000>;
+			};
+			opp@80000000 {
+				opp-hz = /bits/ 64 <80000000>;
+			};
+			opp@100000000 {
+				opp-hz = /bits/ 64 <100000000>;
+			};
+			opp@200000000 {
+				opp-hz = /bits/ 64 <200000000>;
+			};
+			opp@400000000 {
+				opp-hz = /bits/ 64 <400000000>;
+			};
+		};
+
+		bus_isp_opp_table: opp_table4 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp@50000000 {
+				opp-hz = /bits/ 64 <50000000>;
+			};
+			opp@80000000 {
+				opp-hz = /bits/ 64 <80000000>;
+			};
+			opp@100000000 {
+				opp-hz = /bits/ 64 <100000000>;
+			};
+			opp@200000000 {
+				opp-hz = /bits/ 64 <200000000>;
+			};
+			opp@300000000 {
+				opp-hz = /bits/ 64 <300000000>;
+			};
+		};
+
+		bus_peril_opp_table: opp_table5 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp@50000000 {
+				opp-hz = /bits/ 64 <50000000>;
+			};
+			opp@80000000 {
+				opp-hz = /bits/ 64 <80000000>;
+			};
+			opp@100000000 {
+				opp-hz = /bits/ 64 <100000000>;
+			};
+		};
 	};
 };
 
diff --git a/sys/gnu/dts/arm/exynos4.dtsi b/sys/gnu/dts/arm/exynos4.dtsi
index 045785c44c04..ca8f3e3cf2f3 100644
--- a/sys/gnu/dts/arm/exynos4.dtsi
+++ b/sys/gnu/dts/arm/exynos4.dtsi
@@ -22,6 +22,7 @@
 #include <dt-bindings/clock/exynos4.h>
 #include <dt-bindings/clock/exynos-audss-clk.h>
 #include "skeleton.dtsi"
+#include "exynos-syscon-restart.dtsi"
 
 / {
 	interrupt-parent = <&gic>;
@@ -76,7 +77,12 @@
 		reg = <0x10000000 0x100>;
 	};
 
-	mipi_phy: video-phy@10020710 {
+	memory-controller@12570000 {
+		compatible = "samsung,exynos4210-srom";
+		reg = <0x12570000 0x14>;
+	};
+
+	mipi_phy: video-phy {
 		compatible = "samsung,s5pv210-mipi-video-phy";
 		#phy-cells = <1>;
 		syscon = <&pmu_system_controller>;
@@ -158,20 +164,6 @@
 		interrupt-parent = <&gic>;
 	};
 
-	poweroff: syscon-poweroff {
-		compatible = "syscon-poweroff";
-		regmap = <&pmu_system_controller>;
-		offset = <0x330C>; /* PS_HOLD_CONTROL */
-		mask = <0x5200>; /* reset value */
-	};
-
-	reboot: syscon-reboot {
-		compatible = "syscon-reboot";
-		regmap = <&pmu_system_controller>;
-		offset = <0x0400>; /* SWRESET */
-		mask = <0x1>;
-	};
-
 	dsi_0: dsi@11C80000 {
 		compatible = "samsung,exynos4210-mipi-dsi";
 		reg = <0x11C80000 0x10000>;
@@ -661,7 +653,7 @@
 	amba {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		interrupt-parent = <&gic>;
 		ranges;
 
@@ -751,6 +743,18 @@
 		status = "disabled";
 	};
 
+	hdmicec: cec@100B0000 {
+		compatible = "samsung,s5p-cec";
+		reg = <0x100B0000 0x200>;
+		interrupts = <0 114 0>;
+		clocks = <&clock CLK_HDMI_CEC>;
+		clock-names = "hdmicec";
+		samsung,syscon-phandle = <&pmu_system_controller>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmi_cec>;
+		status = "disabled";
+	};
+
 	mixer: mixer@12C10000 {
 		compatible = "samsung,exynos4210-mixer";
 		interrupts = <0 91 0>;
@@ -977,11 +981,18 @@
 		#iommu-cells = <0>;
 	};
 
+	sss: sss@10830000 {
+		compatible = "samsung,exynos4210-secss";
+		reg = <0x10830000 0x300>;
+		interrupts = <0 112 0>;
+		clocks = <&clock CLK_SSS>;
+		clock-names = "secss";
+	};
+
 	prng: rng@10830400 {
 		compatible = "samsung,exynos4-rng";
 		reg = <0x10830400 0x200>;
 		clocks = <&clock CLK_SSS>;
 		clock-names = "secss";
-		status = "disabled";
 	};
 };
diff --git a/sys/gnu/dts/arm/exynos4210-origen.dts b/sys/gnu/dts/arm/exynos4210-origen.dts
index 5821ad87e32c..ad7394c1d67a 100644
--- a/sys/gnu/dts/arm/exynos4210-origen.dts
+++ b/sys/gnu/dts/arm/exynos4210-origen.dts
@@ -60,35 +60,35 @@
 			label = "Up";
 			gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_UP>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		down {
 			label = "Down";
 			gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_DOWN>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		back {
 			label = "Back";
 			gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_BACK>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		home {
 			label = "Home";
 			gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_HOME>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		menu {
 			label = "Menu";
 			gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_MENU>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/exynos4210-pinctrl.dtsi b/sys/gnu/dts/arm/exynos4210-pinctrl.dtsi
index a7c212891674..9331c6252eff 100644
--- a/sys/gnu/dts/arm/exynos4210-pinctrl.dtsi
+++ b/sys/gnu/dts/arm/exynos4210-pinctrl.dtsi
@@ -820,6 +820,13 @@
 			samsung,pin-pud = <1>;
 			samsung,pin-drv = <0>;
 		};
+
+		hdmi_cec: hdmi-cec {
+			samsung,pins = "gpx3-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
 	};
 
 	pinctrl@03860000 {
diff --git a/sys/gnu/dts/arm/exynos4210-smdkv310.dts b/sys/gnu/dts/arm/exynos4210-smdkv310.dts
index 104cbb33d2bb..94ca7d36ab37 100644
--- a/sys/gnu/dts/arm/exynos4210-smdkv310.dts
+++ b/sys/gnu/dts/arm/exynos4210-smdkv310.dts
@@ -66,7 +66,7 @@
 	samsung,keypad-num-rows = <2>;
 	samsung,keypad-num-columns = <8>;
 	linux,keypad-no-autorepeat;
-	linux,keypad-wakeup;
+	wakeup-source;
 	pinctrl-names = "default";
 	pinctrl-0 = <&keypad_rows &keypad_cols>;
 	status = "okay";
diff --git a/sys/gnu/dts/arm/exynos4210-trats.dts b/sys/gnu/dts/arm/exynos4210-trats.dts
index a50be640f1b0..79d983036560 100644
--- a/sys/gnu/dts/arm/exynos4210-trats.dts
+++ b/sys/gnu/dts/arm/exynos4210-trats.dts
@@ -112,7 +112,7 @@
 			linux,code = <116>;
 			label = "power";
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		ok-key {
@@ -298,6 +298,8 @@
 		compatible = "maxim,max8997-pmic";
 
 		reg = <0x66>;
+		interrupt-parent = <&gpx0>;
+		interrupts = <7 0>;
 
 		max8997,pmic-buck1-uses-gpio-dvs;
 		max8997,pmic-buck2-uses-gpio-dvs;
@@ -359,7 +361,7 @@
 			};
 
 			vusbdac_reg: LDO8 {
-			     regulator-name = "VUSB/VDAC_3.3V_C210";
+			     regulator-name = "VUSB+VDAC_3.3V_C210";
 			     regulator-min-microvolt = <3300000>;
 			     regulator-max-microvolt = <3300000>;
 			};
diff --git a/sys/gnu/dts/arm/exynos4210-universal_c210.dts b/sys/gnu/dts/arm/exynos4210-universal_c210.dts
index 4f5d37920c8d..9a75e3effbc9 100644
--- a/sys/gnu/dts/arm/exynos4210-universal_c210.dts
+++ b/sys/gnu/dts/arm/exynos4210-universal_c210.dts
@@ -92,7 +92,7 @@
 			linux,code = <171>;
 			label = "config";
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		camera-key {
@@ -107,7 +107,7 @@
 			linux,code = <116>;
 			label = "power";
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		ok-key {
diff --git a/sys/gnu/dts/arm/exynos4210.dtsi b/sys/gnu/dts/arm/exynos4210.dtsi
index c1cb8df6da07..2d9b02967105 100644
--- a/sys/gnu/dts/arm/exynos4210.dtsi
+++ b/sys/gnu/dts/arm/exynos4210.dtsi
@@ -257,6 +257,165 @@
 		power-domains = <&pd_lcd1>;
 		#iommu-cells = <0>;
 	};
+
+	bus_dmc: bus_dmc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_DMC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_acp: bus_acp {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_ACP>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_acp_opp_table>;
+		status = "disabled";
+	};
+
+	bus_peri: bus_peri {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK100>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_peri_opp_table>;
+		status = "disabled";
+	};
+
+	bus_fsys: bus_fsys {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK133>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_fsys_opp_table>;
+		status = "disabled";
+	};
+
+	bus_display: bus_display {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK160>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_display_opp_table>;
+		status = "disabled";
+	};
+
+	bus_lcd0: bus_lcd0 {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK200>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_leftbus: bus_leftbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_GDL>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_rightbus: bus_rightbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_GDR>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_mfc: bus_mfc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_SCLK_MFC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_dmc_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@134000000 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <1025000>;
+		};
+		opp@267000000 {
+			opp-hz = /bits/ 64 <267000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp@400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1150000>;
+		};
+	};
+
+	bus_acp_opp_table: opp_table2 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@134000000 {
+			opp-hz = /bits/ 64 <134000000>;
+		};
+		opp@160000000 {
+			opp-hz = /bits/ 64 <160000000>;
+		};
+		opp@200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+	};
+
+	bus_peri_opp_table: opp_table3 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@5000000 {
+			opp-hz = /bits/ 64 <5000000>;
+		};
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+	};
+
+	bus_fsys_opp_table: opp_table4 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@10000000 {
+			opp-hz = /bits/ 64 <10000000>;
+		};
+		opp@134000000 {
+			opp-hz = /bits/ 64 <134000000>;
+		};
+	};
+
+	bus_display_opp_table: opp_table5 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+		opp@134000000 {
+			opp-hz = /bits/ 64 <134000000>;
+		};
+		opp@160000000 {
+			opp-hz = /bits/ 64 <160000000>;
+		};
+	};
+
+	bus_leftbus_opp_table: opp_table6 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+		opp@160000000 {
+			opp-hz = /bits/ 64 <160000000>;
+		};
+		opp@200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+	};
 };
 
 &gic {
diff --git a/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi b/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi
index 395c3ca9601e..ec7619a384a2 100644
--- a/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi
+++ b/sys/gnu/dts/arm/exynos4412-odroid-common.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/clock/maxim,max77686.h>
 #include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -35,7 +36,7 @@
 			linux,code = <KEY_POWER>;
 			label = "power key";
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -108,6 +109,53 @@
 	};
 };
 
+&bus_dmc {
+	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
+&bus_acp {
+	devfreq = <&bus_dmc>;
+	status = "okay";
+};
+
+&bus_c2c {
+	devfreq = <&bus_dmc>;
+	status = "okay";
+};
+
+&bus_leftbus {
+	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+	vdd-supply = <&buck3_reg>;
+	status = "okay";
+};
+
+&bus_rightbus {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_display {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_fsys {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_peri {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_mfc {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
 &cpu0 {
 	cpu0-supply = <&buck2_reg>;
 };
@@ -188,6 +236,10 @@
 	status = "okay";
 };
 
+&hdmicec {
+	status = "okay";
+};
+
 &hsotg {
 	dr_mode = "peripheral";
 	status = "okay";
@@ -355,8 +407,8 @@
 
 			buck1_reg: BUCK1 {
 				regulator-name = "vdd_mif";
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1000000>;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1100000>;
 				regulator-always-on;
 				regulator-boot-on;
 			};
@@ -371,8 +423,8 @@
 
 			buck3_reg: BUCK3 {
 				regulator-name = "vdd_int";
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1000000>;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1050000>;
 				regulator-always-on;
 				regulator-boot-on;
 			};
diff --git a/sys/gnu/dts/arm/exynos4412-odroidx.dts b/sys/gnu/dts/arm/exynos4412-odroidx.dts
index b44bb682e976..bf7b21b817e4 100644
--- a/sys/gnu/dts/arm/exynos4412-odroidx.dts
+++ b/sys/gnu/dts/arm/exynos4412-odroidx.dts
@@ -48,7 +48,7 @@
 			linux,code = <KEY_HOME>;
 			label = "home key";
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/exynos4412-origen.dts b/sys/gnu/dts/arm/exynos4412-origen.dts
index 9e2e24c6177a..8bca699b7f20 100644
--- a/sys/gnu/dts/arm/exynos4412-origen.dts
+++ b/sys/gnu/dts/arm/exynos4412-origen.dts
@@ -423,7 +423,7 @@
 	samsung,keypad-num-rows = <3>;
 	samsung,keypad-num-columns = <2>;
 	linux,keypad-no-autorepeat;
-	linux,keypad-wakeup;
+	wakeup-source;
 	pinctrl-0 = <&keypad_rows &keypad_cols>;
 	pinctrl-names = "default";
 	status = "okay";
diff --git a/sys/gnu/dts/arm/exynos4412-ppmu-common.dtsi b/sys/gnu/dts/arm/exynos4412-ppmu-common.dtsi
new file mode 100644
index 000000000000..16e4b77d8cb1
--- /dev/null
+++ b/sys/gnu/dts/arm/exynos4412-ppmu-common.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Device tree sources for Exynos4412 PPMU common device tree
+ *
+ * Copyright (C) 2015 Samsung Electronics
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&ppmu_dmc0 {
+       status = "okay";
+
+       events {
+	       ppmu_dmc0_3: ppmu-event3-dmc0 {
+		       event-name = "ppmu-event3-dmc0";
+	       };
+       };
+};
+
+&ppmu_dmc1 {
+       status = "okay";
+
+       events {
+	       ppmu_dmc1_3: ppmu-event3-dmc1 {
+		       event-name = "ppmu-event3-dmc1";
+	       };
+       };
+};
+
+&ppmu_leftbus {
+       status = "okay";
+
+       events {
+	       ppmu_leftbus_3: ppmu-event3-leftbus {
+		       event-name = "ppmu-event3-leftbus";
+	       };
+       };
+};
+
+&ppmu_rightbus {
+       status = "okay";
+
+       events {
+	       ppmu_rightbus_3: ppmu-event3-rightbus {
+		       event-name = "ppmu-event3-rightbus";
+	       };
+       };
+};
diff --git a/sys/gnu/dts/arm/exynos4412-smdk4412.dts b/sys/gnu/dts/arm/exynos4412-smdk4412.dts
index a130ab39fa77..a51069f3c03b 100644
--- a/sys/gnu/dts/arm/exynos4412-smdk4412.dts
+++ b/sys/gnu/dts/arm/exynos4412-smdk4412.dts
@@ -45,7 +45,7 @@
 	samsung,keypad-num-rows = <3>;
 	samsung,keypad-num-columns = <8>;
 	linux,keypad-no-autorepeat;
-	linux,keypad-wakeup;
+	wakeup-source;
 	pinctrl-0 = <&keypad_rows &keypad_cols>;
 	pinctrl-names = "default";
 	status = "okay";
diff --git a/sys/gnu/dts/arm/exynos4412-trats2.dts b/sys/gnu/dts/arm/exynos4412-trats2.dts
index a6f78c3da935..9336fd4824d9 100644
--- a/sys/gnu/dts/arm/exynos4412-trats2.dts
+++ b/sys/gnu/dts/arm/exynos4412-trats2.dts
@@ -14,6 +14,7 @@
 
 /dts-v1/;
 #include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/maxim,max77686.h>
@@ -119,7 +120,7 @@
 			linux,code = <116>;
 			label = "power";
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		key-ok {
@@ -127,7 +128,7 @@
 			linux,code = <139>;
 			label = "ok";
 			debounce-inteval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -146,13 +147,13 @@
 			reg = <0x66>;
 
 			regulators {
-				esafeout1_reg: ESAFEOUT1@1 {
+				esafeout1_reg: ESAFEOUT1 {
 					regulator-name = "ESAFEOUT1";
 				};
-				esafeout2_reg: ESAFEOUT2@2 {
+				esafeout2_reg: ESAFEOUT2 {
 					regulator-name = "ESAFEOUT2";
 				};
-				charger_reg: CHARGER@0 {
+				charger_reg: CHARGER {
 					regulator-name = "CHARGER";
 					regulator-min-microamp = <60000>;
 					regulator-max-microamp = <2580000>;
@@ -251,7 +252,7 @@
 			"SPK", "SPKOUTRP";
 	};
 
-	thermistor-ap@0 {
+	thermistor-ap {
 		compatible = "ntc,ncp15wb473";
 		pullup-uv = <1800000>;	 /* VCC_1.8V_AP */
 		pullup-ohm = <100000>;	 /* 100K */
@@ -259,7 +260,7 @@
 		io-channels = <&adc 1>;  /* AP temperature */
 	};
 
-	thermistor-battery@1 {
+	thermistor-battery {
 		compatible = "ntc,ncp15wb473";
 		pullup-uv = <1800000>;	 /* VCC_1.8V_AP */
 		pullup-ohm = <100000>;	 /* 100K */
@@ -288,6 +289,53 @@
 	status = "okay";
 };
 
+&bus_dmc {
+	devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+	vdd-supply = <&buck1_reg>;
+	status = "okay";
+};
+
+&bus_acp {
+	devfreq = <&bus_dmc>;
+	status = "okay";
+};
+
+&bus_c2c {
+	devfreq = <&bus_dmc>;
+	status = "okay";
+};
+
+&bus_leftbus {
+	devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+	vdd-supply = <&buck3_reg>;
+	status = "okay";
+};
+
+&bus_rightbus {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_display {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_fsys {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_peri {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
+&bus_mfc {
+	devfreq = <&bus_leftbus>;
+	status = "okay";
+};
+
 &cpu0 {
 	cpu0-supply = <&buck2_reg>;
 };
@@ -871,46 +919,6 @@
 	assigned-clock-parents =  <&clock CLK_XUSBXTI>;
 };
 
-&ppmu_dmc0 {
-	status = "okay";
-
-	events {
-		ppmu_dmc0_3: ppmu-event3-dmc0 {
-			event-name = "ppmu-event3-dmc0";
-		};
-	};
-};
-
-&ppmu_dmc1 {
-	status = "okay";
-
-	events {
-		ppmu_dmc1_3: ppmu-event3-dmc1 {
-			event-name = "ppmu-event3-dmc1";
-		};
-	};
-};
-
-&ppmu_leftbus {
-	status = "okay";
-
-	events {
-		ppmu_leftbus_3: ppmu-event3-leftbus {
-			event-name = "ppmu-event3-leftbus";
-		};
-	};
-};
-
-&ppmu_rightbus {
-	status = "okay";
-
-	events {
-		ppmu_rightbus_3: ppmu-event3-rightbus {
-			event-name = "ppmu-event3-rightbus";
-		};
-	};
-};
-
 &pinctrl_0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&sleep0>;
@@ -1234,10 +1242,6 @@
 	status = "okay";
 };
 
-&prng {
-	status = "okay";
-};
-
 &rtc {
 	status = "okay";
 	clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
@@ -1276,7 +1280,7 @@
 	cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
-	s5c73m3_spi: s5c73m3 {
+	s5c73m3_spi: s5c73m3@0 {
 		compatible = "samsung,s5c73m3";
 		spi-max-frequency = <50000000>;
 		reg = <0>;
diff --git a/sys/gnu/dts/arm/exynos4415.dtsi b/sys/gnu/dts/arm/exynos4415.dtsi
index ad764842fff5..28b04b6795c9 100644
--- a/sys/gnu/dts/arm/exynos4415.dtsi
+++ b/sys/gnu/dts/arm/exynos4415.dtsi
@@ -380,7 +380,7 @@
 		};
 
 		amba {
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			interrupt-parent = <&gic>;
diff --git a/sys/gnu/dts/arm/exynos4x12-pinctrl.dtsi b/sys/gnu/dts/arm/exynos4x12-pinctrl.dtsi
index bac25c672789..856b29254374 100644
--- a/sys/gnu/dts/arm/exynos4x12-pinctrl.dtsi
+++ b/sys/gnu/dts/arm/exynos4x12-pinctrl.dtsi
@@ -885,6 +885,13 @@
 			samsung,pin-pud = <0>;
 			samsung,pin-drv = <0>;
 		};
+
+		hdmi_cec: hdmi-cec {
+			samsung,pins = "gpx3-6";
+			samsung,pin-function = <3>;
+			samsung,pin-pud = <0>;
+			samsung,pin-drv = <0>;
+		};
 	};
 
 	pinctrl_2: pinctrl@03860000 {
diff --git a/sys/gnu/dts/arm/exynos4x12.dtsi b/sys/gnu/dts/arm/exynos4x12.dtsi
index 84a23f962946..c452499ae8c9 100644
--- a/sys/gnu/dts/arm/exynos4x12.dtsi
+++ b/sys/gnu/dts/arm/exynos4x12.dtsi
@@ -179,7 +179,7 @@
 			ranges;
 			status = "disabled";
 
-			pmu {
+			pmu@10020000 {
 				reg = <0x10020000 0x3000>;
 			};
 
@@ -281,6 +281,180 @@
 		clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
 		#iommu-cells = <0>;
 	};
+
+	bus_dmc: bus_dmc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_DMC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_acp: bus_acp {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_ACP>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_acp_opp_table>;
+		status = "disabled";
+	};
+
+	bus_c2c: bus_c2c {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_C2C>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_dmc_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <900000>;
+		};
+		opp@134000000 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <900000>;
+		};
+		opp@160000000 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <900000>;
+		};
+		opp@267000000 {
+			opp-hz = /bits/ 64 <267000000>;
+			opp-microvolt = <950000>;
+		};
+		opp@400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1050000>;
+		};
+	};
+
+	bus_acp_opp_table: opp_table2 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+		opp@134000000 {
+			opp-hz = /bits/ 64 <134000000>;
+		};
+		opp@160000000 {
+			opp-hz = /bits/ 64 <160000000>;
+		};
+		opp@267000000 {
+			opp-hz = /bits/ 64 <267000000>;
+		};
+	};
+
+	bus_leftbus: bus_leftbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_GDL>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_rightbus: bus_rightbus {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_GDR>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_display: bus_display {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK160>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_display_opp_table>;
+		status = "disabled";
+	};
+
+	bus_fsys: bus_fsys {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK133>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_fsys_opp_table>;
+		status = "disabled";
+	};
+
+	bus_peri: bus_peri {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_ACLK100>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_peri_opp_table>;
+		status = "disabled";
+	};
+
+	bus_mfc: bus_mfc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_SCLK_MFC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_leftbus_opp_table>;
+		status = "disabled";
+	};
+
+	bus_leftbus_opp_table: opp_table3 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <900000>;
+		};
+		opp@134000000 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <925000>;
+		};
+		opp@160000000 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <950000>;
+		};
+		opp@200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
+	bus_display_opp_table: opp_table4 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@160000000 {
+			opp-hz = /bits/ 64 <160000000>;
+		};
+		opp@200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+	};
+
+	bus_fsys_opp_table: opp_table5 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+		opp@134000000 {
+			opp-hz = /bits/ 64 <134000000>;
+		};
+	};
+
+	bus_peri_opp_table: opp_table6 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@50000000 {
+			opp-hz = /bits/ 64 <50000000>;
+		};
+		opp@100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+	};
 };
 
 &combiner {
diff --git a/sys/gnu/dts/arm/exynos5.dtsi b/sys/gnu/dts/arm/exynos5.dtsi
index e2439e87ee4a..d5c0f18a4223 100644
--- a/sys/gnu/dts/arm/exynos5.dtsi
+++ b/sys/gnu/dts/arm/exynos5.dtsi
@@ -14,6 +14,7 @@
  */
 
 #include "skeleton.dtsi"
+#include "exynos-syscon-restart.dtsi"
 
 / {
 	interrupt-parent = <&gic>;
@@ -30,6 +31,11 @@
 		reg = <0x10000000 0x100>;
 	};
 
+	memory-controller@12250000 {
+		compatible = "samsung,exynos4210-srom";
+		reg = <0x12250000 0x14>;
+	};
+
 	combiner: interrupt-controller@10440000 {
 		compatible = "samsung,exynos4210-combiner";
 		#interrupt-cells = <2>;
@@ -88,20 +94,6 @@
 		status = "disabled";
 	};
 
-	poweroff: syscon-poweroff {
-		compatible = "syscon-poweroff";
-		regmap = <&pmu_system_controller>;
-		offset = <0x330C>; /* PS_HOLD_CONTROL */
-		mask = <0x5200>; /* reset value */
-	};
-
-	reboot: syscon-reboot {
-		compatible = "syscon-reboot";
-		regmap = <&pmu_system_controller>;
-		offset = <0x0400>; /* SWRESET */
-		mask = <0x1>;
-	};
-
 	fimd: fimd@14400000 {
 		compatible = "samsung,exynos5250-fimd";
 		interrupt-parent = <&combiner>;
diff --git a/sys/gnu/dts/arm/exynos5250-arndale.dts b/sys/gnu/dts/arm/exynos5250-arndale.dts
index c000532c1444..85dad29c08dc 100644
--- a/sys/gnu/dts/arm/exynos5250-arndale.dts
+++ b/sys/gnu/dts/arm/exynos5250-arndale.dts
@@ -34,42 +34,42 @@
 			label = "SW-TACT2";
 			gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_MENU>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		home {
 			label = "SW-TACT3";
 			gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_HOME>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		up {
 			label = "SW-TACT4";
 			gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_UP>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		down {
 			label = "SW-TACT5";
 			gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_DOWN>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		back {
 			label = "SW-TACT6";
 			gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_BACK>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		wakeup {
 			label = "SW-TACT7";
 			gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_WAKEUP>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -124,8 +124,6 @@
 &dp {
 	status = "okay";
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
@@ -133,7 +131,7 @@
 	display-timings {
 		native-mode = <&timing0>;
 
-		timing0: timing@0 {
+		timing0: timing {
 			/* 2560x1600 DP panel */
 			clock-frequency = <50000>;
 			hactive = <2560>;
diff --git a/sys/gnu/dts/arm/exynos5250-smdk5250.dts b/sys/gnu/dts/arm/exynos5250-smdk5250.dts
index 0f5dcd418af8..b7992b13c9de 100644
--- a/sys/gnu/dts/arm/exynos5250-smdk5250.dts
+++ b/sys/gnu/dts/arm/exynos5250-smdk5250.dts
@@ -29,7 +29,7 @@
 		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
 	};
 
-	vdd: fixed-regulator@0 {
+	vdd: fixed-regulator-vdd {
 		compatible = "regulator-fixed";
 		regulator-name = "vdd-supply";
 		regulator-min-microvolt = <1800000>;
@@ -37,7 +37,7 @@
 		regulator-always-on;
 	};
 
-	dbvdd: fixed-regulator@1 {
+	dbvdd: fixed-regulator-dbvdd {
 		compatible = "regulator-fixed";
 		regulator-name = "dbvdd-supply";
 		regulator-min-microvolt = <3300000>;
@@ -45,7 +45,7 @@
 		regulator-always-on;
 	};
 
-	spkvdd: fixed-regulator@2 {
+	spkvdd: fixed-regulator-spkvdd {
 		compatible = "regulator-fixed";
 		regulator-name = "spkvdd-supply";
 		regulator-min-microvolt = <5000000>;
@@ -80,8 +80,6 @@
 
 &dp {
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
@@ -93,7 +91,7 @@
 	display-timings {
 		native-mode = <&timing0>;
 
-		timing0: timing@0 {
+		timing0: timing {
 			/* 1280x800 */
 			clock-frequency = <50000>;
 			hactive = <1280>;
diff --git a/sys/gnu/dts/arm/exynos5250-snow-common.dtsi b/sys/gnu/dts/arm/exynos5250-snow-common.dtsi
index 5cb33ba5e296..fa14f77df563 100644
--- a/sys/gnu/dts/arm/exynos5250-snow-common.dtsi
+++ b/sys/gnu/dts/arm/exynos5250-snow-common.dtsi
@@ -37,7 +37,7 @@
 			label = "Power";
 			gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		lid-switch {
@@ -46,7 +46,7 @@
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0>; /* SW_LID */
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -84,7 +84,7 @@
 				sbs,poll-retry-count = <1>;
 			};
 
-			cros_ec: embedded-controller {
+			cros_ec: embedded-controller@1e {
 				compatible = "google,cros-ec-i2c";
 				reg = <0x1e>;
 				interrupts = <6 IRQ_TYPE_NONE>;
@@ -94,7 +94,7 @@
 				wakeup-source;
 			};
 
-			power-regulator {
+			power-regulator@48 {
 				compatible = "ti,tps65090";
 				reg = <0x48>;
 
@@ -236,15 +236,13 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 
 	ports {
-		port@0 {
+		port {
 			dp_out: endpoint {
 				remote-endpoint = <&bridge_in>;
 			};
@@ -428,7 +426,7 @@
 	samsung,i2c-sda-delay = <100>;
 	samsung,i2c-max-bus-freq = <378000>;
 
-	trackpad {
+	trackpad@67 {
 		reg = <0x67>;
 		compatible = "cypress,cyapa";
 		interrupts = <2 IRQ_TYPE_NONE>;
@@ -487,13 +485,20 @@
 		edid-emulation = <5>;
 
 		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
 			port@0 {
+				reg = <0>;
+
 				bridge_out: endpoint {
 					remote-endpoint = <&panel_in>;
 				};
 			};
 
 			port@1 {
+				reg = <1>;
+
 				bridge_in: endpoint {
 					remote-endpoint = <&dp_out>;
 				};
diff --git a/sys/gnu/dts/arm/exynos5250-spring.dts b/sys/gnu/dts/arm/exynos5250-spring.dts
index c1edd6d038a9..ac291f540812 100644
--- a/sys/gnu/dts/arm/exynos5250-spring.dts
+++ b/sys/gnu/dts/arm/exynos5250-spring.dts
@@ -37,7 +37,7 @@
 			label = "Power";
 			gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		lid-switch {
@@ -46,7 +46,7 @@
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0>; /* SW_LID */
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -74,12 +74,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <1>;
-	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
 };
 
 &ehci {
@@ -383,7 +381,7 @@
 	samsung,i2c-sda-delay = <100>;
 	samsung,i2c-max-bus-freq = <66000>;
 
-	cros_ec: embedded-controller {
+	cros_ec: embedded-controller@1e {
 		compatible = "google,cros-ec-i2c";
 		reg = <0x1e>;
 		interrupts = <6 IRQ_TYPE_NONE>;
diff --git a/sys/gnu/dts/arm/exynos5250.dtsi b/sys/gnu/dts/arm/exynos5250.dtsi
index 33e2d5f7315b..c7158b2fb213 100644
--- a/sys/gnu/dts/arm/exynos5250.dtsi
+++ b/sys/gnu/dts/arm/exynos5250.dtsi
@@ -596,7 +596,7 @@
 		pinctrl-0 = <&i2s2_bus>;
 	};
 
-	usb@12000000 {
+	usb_dwc3 {
 		compatible = "samsung,exynos5250-dwusb3";
 		clocks = <&clock CLK_USB3>;
 		clock-names = "usbdrd30";
@@ -604,7 +604,7 @@
 		#size-cells = <1>;
 		ranges;
 
-		usbdrd_dwc3: dwc3 {
+		usbdrd_dwc3: dwc3@12000000 {
 			compatible = "synopsys,dwc3";
 			reg = <0x12000000 0x10000>;
 			interrupts = <0 72 0>;
@@ -674,7 +674,7 @@
 	amba {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		interrupt-parent = <&gic>;
 		ranges;
 
@@ -763,7 +763,7 @@
 		iommu = <&sysmmu_gsc3>;
 	};
 
-	hdmi: hdmi {
+	hdmi: hdmi@14530000 {
 		compatible = "samsung,exynos4212-hdmi";
 		reg = <0x14530000 0x70000>;
 		power-domains = <&pd_disp1>;
@@ -776,7 +776,7 @@
 		samsung,syscon-phandle = <&pmu_system_controller>;
 	};
 
-	mixer {
+	mixer@14450000 {
 		compatible = "samsung,exynos5250-mixer";
 		reg = <0x14450000 0x10000>;
 		power-domains = <&pd_disp1>;
@@ -787,7 +787,7 @@
 		iommus = <&sysmmu_tv>;
 	};
 
-	dp_phy: video-phy@10040720 {
+	dp_phy: video-phy {
 		compatible = "samsung,exynos5250-dp-video-phy";
 		samsung,pmu-syscon = <&pmu_system_controller>;
 		#phy-cells = <0>;
@@ -807,7 +807,7 @@
 
 	sss@10830000 {
 		compatible = "samsung,exynos4210-secss";
-		reg = <0x10830000 0x10000>;
+		reg = <0x10830000 0x300>;
 		interrupts = <0 112 0>;
 		clocks = <&clock CLK_SSS>;
 		clock-names = "secss";
diff --git a/sys/gnu/dts/arm/exynos5410-pinctrl.dtsi b/sys/gnu/dts/arm/exynos5410-pinctrl.dtsi
new file mode 100644
index 000000000000..f9aa6bb55464
--- /dev/null
+++ b/sys/gnu/dts/arm/exynos5410-pinctrl.dtsi
@@ -0,0 +1,406 @@
+/*
+ * Exynos5410 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Hardkernel Co., Ltd.
+ *              http://www.hardkernel.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&pinctrl_0 {
+	gpa0: gpa0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpa1: gpa1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpa2: gpa2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb0: gpb0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb1: gpb1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb2: gpb2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb3: gpb3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpc0: gpc0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpc3: gpc3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpc1: gpc1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpc2: gpc2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpm5: gpm5 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpd1: gpd1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpe0: gpe0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpe1: gpe1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf0: gpf0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf1: gpf1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg0: gpg0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg1: gpg1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg2: gpg2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gph0: gph0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gph1: gph1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpm7: gpm7 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpy0: gpy0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpy1: gpy1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpy2: gpy2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpy3: gpy3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpy4: gpy4 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpy5: gpy5 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpy6: gpy6 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpy7: gpy7 {
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpx0: gpx0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&combiner>;
+		#interrupt-cells = <2>;
+		interrupts = <23 0>,
+		             <24 0>,
+		             <25 0>,
+		             <25 1>,
+		             <26 0>,
+		             <26 1>,
+		             <27 0>,
+		             <27 1>;
+	};
+
+	gpx1: gpx1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&combiner>;
+		#interrupt-cells = <2>;
+		interrupts = <28 0>,
+		             <28 1>,
+		             <29 0>,
+		             <29 1>,
+		             <30 0>,
+		             <30 1>,
+		             <31 0>,
+		             <31 1>;
+	};
+
+	gpx2: gpx2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpx3: gpx3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_1 {
+	gpj0: gpj0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpj1: gpj1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpj2: gpj2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpj3: gpj3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpj4: gpj4 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpk0: gpk0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpk1: gpk1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpk2: gpk2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpk3: gpk3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_2 {
+	gpv0: gpv0 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpv1: gpv1 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpv2: gpv2 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpv3: gpv3 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpv4: gpv4 {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_3 {
+	gpz: gpz {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/sys/gnu/dts/arm/exynos5410-smdk5410.dts b/sys/gnu/dts/arm/exynos5410-smdk5410.dts
index cebeaab3abec..0f6429e1b75c 100644
--- a/sys/gnu/dts/arm/exynos5410-smdk5410.dts
+++ b/sys/gnu/dts/arm/exynos5410-smdk5410.dts
@@ -11,6 +11,7 @@
 
 /dts-v1/;
 #include "exynos5410.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 / {
 	model = "Samsung SMDK5410 board based on EXYNOS5410";
 	compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
@@ -61,6 +62,46 @@
 	disable-wp;
 };
 
+&pinctrl_0 {
+	srom_ctl: srom-ctl {
+		samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5",
+			       "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3";
+		samsung,pin-function = <2>;
+		samsung,pin-drv = <0>;
+	};
+
+	srom_ebi: srom-ebi {
+		samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3",
+			       "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7",
+			       "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3",
+			       "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7",
+			       "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3",
+			       "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7";
+		samsung,pin-function = <2>;
+		samsung,pin-pud = <3>;
+		samsung,pin-drv = <0>;
+	};
+};
+
+&sromc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&srom_ctl>, <&srom_ebi>;
+
+	ethernet@3,0 {
+		compatible = "smsc,lan9115";
+		reg = <3 0 0x10000>;
+		phy-mode = "mii";
+		interrupt-parent = <&gpx0>;
+		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+		reg-io-width = <2>;
+		smsc,irq-push-pull;
+		smsc,force-internal-phy;
+
+		samsung,srom-page-mode;
+		samsung,srom-timing = <9 12 1 9 1 1>;
+	};
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/exynos5410.dtsi b/sys/gnu/dts/arm/exynos5410.dtsi
index fad0779b1b6e..7a56aec2c5ba 100644
--- a/sys/gnu/dts/arm/exynos5410.dtsi
+++ b/sys/gnu/dts/arm/exynos5410.dtsi
@@ -14,6 +14,7 @@
  */
 
 #include "skeleton.dtsi"
+#include "exynos-syscon-restart.dtsi"
 #include <dt-bindings/clock/exynos5410.h>
 
 / {
@@ -21,6 +22,10 @@
 	interrupt-parent = <&gic>;
 
 	aliases {
+		pinctrl0 = &pinctrl_0;
+		pinctrl1 = &pinctrl_1;
+		pinctrl2 = &pinctrl_2;
+		pinctrl3 = &pinctrl_3;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		serial2 = &uart2;
@@ -97,25 +102,22 @@
 			reg = <0x10000000 0x100>;
 		};
 
+		sromc: memory-controller@12250000 {
+			compatible = "samsung,exynos4210-srom";
+			reg = <0x12250000 0x14>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges = <0 0 0x04000000 0x20000
+				  1 0 0x05000000 0x20000
+				  2 0 0x06000000 0x20000
+				  3 0 0x07000000 0x20000>;
+		};
+
 		pmu_system_controller: system-controller@10040000 {
 			compatible = "samsung,exynos5410-pmu", "syscon";
 			reg = <0x10040000 0x5000>;
 		};
 
-		poweroff: syscon-poweroff {
-			compatible = "syscon-poweroff";
-			regmap = <&pmu_system_controller>;
-			offset = <0x330C>; /* PS_HOLD_CONTROL */
-			mask = <0x5200>; /* reset value */
-		};
-
-		reboot: syscon-reboot {
-			compatible = "syscon-reboot";
-			regmap = <&pmu_system_controller>;
-			offset = <0x0400>; /* SWRESET */
-			mask = <0x1>;
-		};
-
 		mct: mct@101C0000 {
 			compatible = "samsung,exynos4210-mct";
 			reg = <0x101C0000 0xB00>;
@@ -205,6 +207,36 @@
 			status = "disabled";
 		};
 
+		pinctrl_0: pinctrl@13400000 {
+			compatible = "samsung,exynos5410-pinctrl";
+			reg = <0x13400000 0x1000>;
+			interrupts = <0 45 0>;
+
+			wakeup-interrupt-controller {
+				compatible = "samsung,exynos4210-wakeup-eint";
+				interrupt-parent = <&gic>;
+				interrupts = <0 32 0>;
+			};
+		};
+
+		pinctrl_1: pinctrl@14000000 {
+			compatible = "samsung,exynos5410-pinctrl";
+			reg = <0x14000000 0x1000>;
+			interrupts = <0 46 0>;
+		};
+
+		pinctrl_2: pinctrl@10d10000 {
+			compatible = "samsung,exynos5410-pinctrl";
+			reg = <0x10d10000 0x1000>;
+			interrupts = <0 50 0>;
+		};
+
+		pinctrl_3: pinctrl@03860000 {
+			compatible = "samsung,exynos5410-pinctrl";
+			reg = <0x03860000 0x1000>;
+			interrupts = <0 47 0>;
+		};
+
 		uart0: serial@12C00000 {
 			compatible = "samsung,exynos4210-uart";
 			reg = <0x12C00000 0x100>;
@@ -233,3 +265,5 @@
 		};
 	};
 };
+
+#include "exynos5410-pinctrl.dtsi"
diff --git a/sys/gnu/dts/arm/exynos5420-arndale-octa.dts b/sys/gnu/dts/arm/exynos5420-arndale-octa.dts
index 4ecef6981d5c..60bc861d0f9d 100644
--- a/sys/gnu/dts/arm/exynos5420-arndale-octa.dts
+++ b/sys/gnu/dts/arm/exynos5420-arndale-octa.dts
@@ -11,6 +11,7 @@
 
 /dts-v1/;
 #include "exynos5420.dtsi"
+#include "exynos5420-cpus.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/input/input.h>
@@ -47,11 +48,19 @@
 			label = "SW-TACT1";
 			gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_WAKEUP>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &usbdrd_dwc3_1 {
 	dr_mode = "host";
 };
@@ -66,13 +75,6 @@
 	s2mps11_pmic@66 {
 		compatible = "samsung,s2mps11-pmic";
 		reg = <0x66>;
-		s2mps11,buck2-ramp-delay = <12>;
-		s2mps11,buck34-ramp-delay = <12>;
-		s2mps11,buck16-ramp-delay = <12>;
-		s2mps11,buck6-ramp-enable = <1>;
-		s2mps11,buck2-ramp-enable = <1>;
-		s2mps11,buck3-ramp-enable = <1>;
-		s2mps11,buck4-ramp-enable = <1>;
 
 		interrupt-parent = <&gpx3>;
 		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
diff --git a/sys/gnu/dts/arm/exynos5420-cpus.dtsi b/sys/gnu/dts/arm/exynos5420-cpus.dtsi
new file mode 100644
index 000000000000..5c052d7ff554
--- /dev/null
+++ b/sys/gnu/dts/arm/exynos5420-cpus.dtsi
@@ -0,0 +1,126 @@
+/*
+ * SAMSUNG EXYNOS5420 SoC cpu device tree source
+ *
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This file provides desired ordering for Exynos5420 and Exynos5800
+ * boards: CPU[0123] being the A15.
+ *
+ * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
+ * but particular boards choose different booting order.
+ *
+ * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
+ * booting cluster (big or LITTLE) is chosen by IROM code by reading
+ * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
+ * from the LITTLE: Cortex-A7.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x0>;
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cluster_a15_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <11>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x1>;
+			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cluster_a15_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <11>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x2>;
+			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cluster_a15_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <11>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x3>;
+			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cluster_a15_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <11>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+
+		cpu4: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x100>;
+			clocks = <&clock CLK_KFC_CLK>;
+			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cluster_a7_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <7>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+
+		cpu5: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x101>;
+			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cluster_a7_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <7>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+
+		cpu6: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x102>;
+			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cluster_a7_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <7>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+
+		cpu7: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x103>;
+			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cluster_a7_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <7>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/exynos5420-peach-pit.dts b/sys/gnu/dts/arm/exynos5420-peach-pit.dts
index 35cfb07dc4bb..1de972d46a87 100644
--- a/sys/gnu/dts/arm/exynos5420-peach-pit.dts
+++ b/sys/gnu/dts/arm/exynos5420-peach-pit.dts
@@ -15,6 +15,7 @@
 #include <dt-bindings/clock/maxim,max77802.h>
 #include <dt-bindings/regulator/maxim,max77802.h>
 #include "exynos5420.dtsi"
+#include "exynos5420-cpus.dtsi"
 
 / {
 	model = "Google Peach Pit Rev 6+";
@@ -64,7 +65,7 @@
 			label = "Power";
 			gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		lid-switch {
@@ -73,7 +74,7 @@
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0>; /* SW_LID */
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -143,20 +144,26 @@
 	vdd-supply = <&ldo9_reg>;
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &dp {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x06>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
 
 	ports {
-		port@0 {
+		port {
 			dp_out: endpoint {
 				remote-endpoint = <&bridge_in>;
 			};
@@ -624,13 +631,20 @@
 		use-external-pwm;
 
 		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
 			port@0 {
+				reg = <0>;
+
 				bridge_out: endpoint {
 					remote-endpoint = <&panel_in>;
 				};
 			};
 
 			port@1 {
+				reg = <1>;
+
 				bridge_in: endpoint {
 					remote-endpoint = <&dp_out>;
 				};
@@ -687,6 +701,11 @@
 	status = "okay";
 };
 
+&mfc {
+	samsung,mfc-r = <0x43000000 0x800000>;
+	samsung,mfc-l = <0x51000000 0x800000>;
+};
+
 &mmc_0 {
 	status = "okay";
 	num-slots = <1>;
diff --git a/sys/gnu/dts/arm/exynos5420-smdk5420.dts b/sys/gnu/dts/arm/exynos5420-smdk5420.dts
index ac35aefd320f..2e748d19322f 100644
--- a/sys/gnu/dts/arm/exynos5420-smdk5420.dts
+++ b/sys/gnu/dts/arm/exynos5420-smdk5420.dts
@@ -11,6 +11,7 @@
 
 /dts-v1/;
 #include "exynos5420.dtsi"
+#include "exynos5420-cpus.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -89,12 +90,18 @@
 
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &dp {
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
@@ -102,7 +109,7 @@
 
 	display-timings {
 		native-mode = <&timing0>;
-		timing0: timing@0 {
+		timing0: timing {
 			clock-frequency = <50000>;
 			hactive = <2560>;
 			vactive = <1600>;
@@ -133,13 +140,6 @@
 	s2mps11_pmic@66 {
 		compatible = "samsung,s2mps11-pmic";
 		reg = <0x66>;
-		s2mps11,buck2-ramp-delay = <12>;
-		s2mps11,buck34-ramp-delay = <12>;
-		s2mps11,buck16-ramp-delay = <12>;
-		s2mps11,buck6-ramp-enable = <1>;
-		s2mps11,buck2-ramp-enable = <1>;
-		s2mps11,buck3-ramp-enable = <1>;
-		s2mps11,buck4-ramp-enable = <1>;
 
 		s2mps11_osc: clocks {
 			#clock-cells = <1>;
diff --git a/sys/gnu/dts/arm/exynos5420.dtsi b/sys/gnu/dts/arm/exynos5420.dtsi
index 48a0a55314f5..c6e05eb88937 100644
--- a/sys/gnu/dts/arm/exynos5420.dtsi
+++ b/sys/gnu/dts/arm/exynos5420.dtsi
@@ -50,75 +50,121 @@
 		usbdrdphy1 = &usbdrd_phy1;
 	};
 
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <0x0>;
-			clock-frequency = <1800000000>;
-			cci-control-port = <&cci_control1>;
+	cluster_a15_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp@1800000000 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1250000>;
+			clock-latency-ns = <140000>;
 		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <0x1>;
-			clock-frequency = <1800000000>;
-			cci-control-port = <&cci_control1>;
+		opp@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <1212500>;
+			clock-latency-ns = <140000>;
 		};
-
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <0x2>;
-			clock-frequency = <1800000000>;
-			cci-control-port = <&cci_control1>;
+		opp@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <1175000>;
+			clock-latency-ns = <140000>;
 		};
-
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <0x3>;
-			clock-frequency = <1800000000>;
-			cci-control-port = <&cci_control1>;
+		opp@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <1137500>;
+			clock-latency-ns = <140000>;
 		};
-
-		cpu4: cpu@100 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x100>;
-			clock-frequency = <1000000000>;
-			cci-control-port = <&cci_control0>;
+		opp@1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt = <1112500>;
+			clock-latency-ns = <140000>;
 		};
-
-		cpu5: cpu@101 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x101>;
-			clock-frequency = <1000000000>;
-			cci-control-port = <&cci_control0>;
+		opp@1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1062500>;
+			clock-latency-ns = <140000>;
 		};
-
-		cpu6: cpu@102 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x102>;
-			clock-frequency = <1000000000>;
-			cci-control-port = <&cci_control0>;
+		opp@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1037500>;
+			clock-latency-ns = <140000>;
+		};
+		opp@1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1012500>;
+			clock-latency-ns = <140000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = < 987500>;
+			clock-latency-ns = <140000>;
+		};
+		opp@900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = < 962500>;
+			clock-latency-ns = <140000>;
 		};
+		opp@800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = < 937500>;
+			clock-latency-ns = <140000>;
+		};
+		opp@700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = < 912500>;
+			clock-latency-ns = <140000>;
+		};
+	};
 
-		cpu7: cpu@103 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0x103>;
-			clock-frequency = <1000000000>;
-			cci-control-port = <&cci_control0>;
+	cluster_a7_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp@1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1275000>;
+			clock-latency-ns = <140000>;
+		};
+		opp@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1212500>;
+			clock-latency-ns = <140000>;
+		};
+		opp@1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			opp-microvolt = <1162500>;
+			clock-latency-ns = <140000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <1112500>;
+			clock-latency-ns = <140000>;
+		};
+		opp@900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1062500>;
+			clock-latency-ns = <140000>;
+		};
+		opp@800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1025000>;
+			clock-latency-ns = <140000>;
+		};
+		opp@700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <975000>;
+			clock-latency-ns = <140000>;
+		};
+		opp@600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <937500>;
+			clock-latency-ns = <140000>;
 		};
 	};
 
+	/*
+	 * The 'cpus' node is not present here but instead it is provided
+	 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
+	 */
+
 	cci: cci@10d20000 {
 		compatible = "arm,cci-400";
 		#address-cells = <1>;
@@ -248,12 +294,50 @@
 		};
 	};
 
+	nocp_mem0_0: nocp@10CA1000 {
+		compatible = "samsung,exynos5420-nocp";
+		reg = <0x10CA1000 0x200>;
+		status = "disabled";
+	};
+
+	nocp_mem0_1: nocp@10CA1400 {
+		compatible = "samsung,exynos5420-nocp";
+		reg = <0x10CA1400 0x200>;
+		status = "disabled";
+	};
+
+	nocp_mem1_0: nocp@10CA1800 {
+		compatible = "samsung,exynos5420-nocp";
+		reg = <0x10CA1800 0x200>;
+		status = "disabled";
+	};
+
+	nocp_mem1_1: nocp@10CA1C00 {
+		compatible = "samsung,exynos5420-nocp";
+		reg = <0x10CA1C00 0x200>;
+		status = "disabled";
+	};
+
+	nocp_g3d_0: nocp@11A51000 {
+		compatible = "samsung,exynos5420-nocp";
+		reg = <0x11A51000 0x200>;
+		status = "disabled";
+	};
+
+	nocp_g3d_1: nocp@11A51400 {
+		compatible = "samsung,exynos5420-nocp";
+		reg = <0x11A51400 0x200>;
+		status = "disabled";
+	};
+
 	gsc_pd: power-domain@10044000 {
 		compatible = "samsung,exynos4210-pd";
 		reg = <0x10044000 0x20>;
 		#power-domain-cells = <0>;
-		clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
-		clock-names = "asb0", "asb1";
+		clocks = <&clock CLK_FIN_PLL>,
+			 <&clock CLK_MOUT_USER_ACLK300_GSCL>,
+			 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
+		clock-names = "oscclk", "clk0", "asb0", "asb1";
 	};
 
 	isp_pd: power-domain@10044020 {
@@ -327,7 +411,7 @@
 	amba {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		interrupt-parent = <&gic>;
 		ranges;
 
@@ -503,13 +587,13 @@
 		clock-names = "timers";
 	};
 
-	dp_phy: video-phy@10040728 {
+	dp_phy: dp-video-phy {
 		compatible = "samsung,exynos5420-dp-video-phy";
 		samsung,pmu-syscon = <&pmu_system_controller>;
 		#phy-cells = <0>;
 	};
 
-	mipi_phy: video-phy@10040714 {
+	mipi_phy: mipi-video-phy {
 		compatible = "samsung,s5pv210-mipi-video-phy";
 		syscon = <&pmu_system_controller>;
 		#phy-cells = <1>;
@@ -859,13 +943,13 @@
 
 	sss: sss@10830000 {
 		compatible = "samsung,exynos4210-secss";
-		reg = <0x10830000 0x10000>;
+		reg = <0x10830000 0x300>;
 		interrupts = <0 112 0>;
 		clocks = <&clock CLK_SSS>;
 		clock-names = "secss";
 	};
 
-	usbdrd3_0: usb@12000000 {
+	usbdrd3_0: usb3-0 {
 		compatible = "samsung,exynos5250-dwusb3";
 		clocks = <&clock CLK_USBD300>;
 		clock-names = "usbdrd30";
@@ -873,7 +957,7 @@
 		#size-cells = <1>;
 		ranges;
 
-		usbdrd_dwc3_0: dwc3 {
+		usbdrd_dwc3_0: dwc3@12000000 {
 			compatible = "snps,dwc3";
 			reg = <0x12000000 0x10000>;
 			interrupts = <0 72 0>;
@@ -891,7 +975,7 @@
 		#phy-cells = <1>;
 	};
 
-	usbdrd3_1: usb@12400000 {
+	usbdrd3_1: usb3-1 {
 		compatible = "samsung,exynos5250-dwusb3";
 		clocks = <&clock CLK_USBD301>;
 		clock-names = "usbdrd30";
@@ -899,7 +983,7 @@
 		#size-cells = <1>;
 		ranges;
 
-		usbdrd_dwc3_1: dwc3 {
+		usbdrd_dwc3_1: dwc3@12400000 {
 			compatible = "snps,dwc3";
 			reg = <0x12400000 0x10000>;
 			interrupts = <0 73 0>;
@@ -1140,6 +1224,377 @@
 		power-domains = <&disp_pd>;
 		#iommu-cells = <0>;
 	};
+
+	bus_wcore: bus_wcore {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_wcore_opp_table>;
+		status = "disabled";
+	};
+
+	bus_noc: bus_noc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK100_NOC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_noc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_fsys_apb: bus_fsys_apb {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_fsys_apb_opp_table>;
+		status = "disabled";
+	};
+
+	bus_fsys: bus_fsys {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_fsys_apb_opp_table>;
+		status = "disabled";
+	};
+
+	bus_fsys2: bus_fsys2 {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_fsys2_opp_table>;
+		status = "disabled";
+	};
+
+	bus_mfc: bus_mfc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK333>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_mfc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_gen: bus_gen {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK266>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_gen_opp_table>;
+		status = "disabled";
+	};
+
+	bus_peri: bus_peri {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK66>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_peri_opp_table>;
+		status = "disabled";
+	};
+
+	bus_g2d: bus_g2d {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK333_G2D>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_g2d_opp_table>;
+		status = "disabled";
+	};
+
+	bus_g2d_acp: bus_g2d_acp {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK266_G2D>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_g2d_acp_opp_table>;
+		status = "disabled";
+	};
+
+	bus_jpeg: bus_jpeg {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_jpeg_opp_table>;
+		status = "disabled";
+	};
+
+	bus_jpeg_apb: bus_jpeg_apb {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK166>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_jpeg_apb_opp_table>;
+		status = "disabled";
+	};
+
+	bus_disp1_fimd: bus_disp1_fimd {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_disp1_fimd_opp_table>;
+		status = "disabled";
+	};
+
+	bus_disp1: bus_disp1 {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_disp1_opp_table>;
+		status = "disabled";
+	};
+
+	bus_gscl_scaler: bus_gscl_scaler {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_gscl_opp_table>;
+		status = "disabled";
+	};
+
+	bus_mscl: bus_mscl {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_mscl_opp_table>;
+		status = "disabled";
+	};
+
+	bus_wcore_opp_table: opp_table2 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <84000000>;
+			opp-microvolt = <925000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <111000000>;
+			opp-microvolt = <950000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <222000000>;
+			opp-microvolt = <950000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <333000000>;
+			opp-microvolt = <950000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <987500>;
+		};
+	};
+
+	bus_noc_opp_table: opp_table3 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <67000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <75000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <86000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+	};
+
+	bus_fsys_apb_opp_table: opp_table4 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+	};
+
+	bus_fsys2_opp_table: opp_table5 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <75000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <100000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <150000000>;
+		};
+	};
+
+	bus_mfc_opp_table: opp_table6 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <96000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <111000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <167000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <222000000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <333000000>;
+		};
+	};
+
+	bus_gen_opp_table: opp_table7 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <89000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <133000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <178000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <267000000>;
+		};
+	};
+
+	bus_peri_opp_table: opp_table8 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <67000000>;
+		};
+	};
+
+	bus_g2d_opp_table: opp_table9 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <84000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <167000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <222000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <300000000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <333000000>;
+		};
+	};
+
+	bus_g2d_acp_opp_table: opp_table10 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <67000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <133000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <178000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <267000000>;
+		};
+	};
+
+	bus_jpeg_opp_table: opp_table11 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <75000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <150000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <300000000>;
+		};
+	};
+
+	bus_jpeg_apb_opp_table: opp_table12 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <84000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <111000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <134000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <167000000>;
+		};
+	};
+
+	bus_disp1_fimd_opp_table: opp_table13 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <120000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+	};
+
+	bus_disp1_opp_table: opp_table14 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <120000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <300000000>;
+		};
+	};
+
+	bus_gscl_opp_table: opp_table15 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <150000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <300000000>;
+		};
+	};
+
+	bus_mscl_opp_table: opp_table16 {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <84000000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <167000000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <222000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <333000000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <400000000>;
+		};
+	};
 };
 
 &dp {
@@ -1151,6 +1606,7 @@
 };
 
 &fimd {
+	compatible = "samsung,exynos5420-fimd";
 	clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 	clock-names = "sclk_fimd", "fimd";
 	power-domains = <&disp_pd>;
diff --git a/sys/gnu/dts/arm/exynos5422-cpu-thermal.dtsi b/sys/gnu/dts/arm/exynos5422-cpu-thermal.dtsi
index 2b289d7c0d13..3e4c4ad96d63 100644
--- a/sys/gnu/dts/arm/exynos5422-cpu-thermal.dtsi
+++ b/sys/gnu/dts/arm/exynos5422-cpu-thermal.dtsi
@@ -16,7 +16,7 @@
 	thermal-zones {
 		cpu0_thermal: cpu0-thermal {
 			thermal-sensors = <&tmu_cpu0 0>;
-			polling-delay-passive = <0>;
+			polling-delay-passive = <250>;
 			polling-delay = <0>;
 			trips {
 				cpu_alert0: cpu-alert-0 {
@@ -39,6 +39,23 @@
 					hysteresis = <0>; /* millicelsius */
 					type = "critical";
 				};
+				/*
+				 * Exyunos542x support only 4 trip-points
+				 * so for these polling mode is required.
+				 * Start polling at temperature level of last
+				 * interrupt-driven trip: cpu_alert2
+				 */
+				cpu_alert3: cpu-alert-3 {
+					temperature = <70000>; /* millicelsius */
+					hysteresis = <10000>; /* millicelsius */
+					type = "passive";
+				};
+				cpu_alert4: cpu-alert-4 {
+					temperature = <85000>; /* millicelsius */
+					hysteresis = <10000>; /* millicelsius */
+					type = "passive";
+				};
+
 			};
 			cooling-maps {
 				map0 {
@@ -53,6 +70,33 @@
 				     trip = <&cpu_alert2>;
 				     cooling-device = <&fan0 2 3>;
 				};
+				/*
+				 * When reaching cpu_alert3, reduce CPU
+				 * by 2 steps. On Exynos5422/5800 that would
+				 * be: 1500 MHz and 1100 MHz.
+				 */
+				map3 {
+				     trip = <&cpu_alert3>;
+				     cooling-device = <&cpu0 0 2>;
+				};
+				map4 {
+				     trip = <&cpu_alert3>;
+				     cooling-device = <&cpu4 0 2>;
+				};
+
+				/*
+				 * When reaching cpu_alert4, reduce CPU
+				 * further, down to 600 MHz (11 steps for big,
+				 * 7 steps for LITTLE).
+				 */
+				map5 {
+				     trip = <&cpu_alert4>;
+				     cooling-device = <&cpu0 3 7>;
+				};
+				map6 {
+				     trip = <&cpu_alert4>;
+				     cooling-device = <&cpu4 3 11>;
+				};
 			};
 		};
 	};
diff --git a/sys/gnu/dts/arm/exynos5422-cpus.dtsi b/sys/gnu/dts/arm/exynos5422-cpus.dtsi
index b7f60c855459..bf3c6f1ec4ee 100644
--- a/sys/gnu/dts/arm/exynos5422-cpus.dtsi
+++ b/sys/gnu/dts/arm/exynos5422-cpus.dtsi
@@ -4,78 +4,122 @@
  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The
- * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting
- * from Cortex-A15 core.
+ * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
  *
- * EXYNOS5422 based board files can include this file to provide cpu ordering
- * which could boot a cortex-a7 from cpu0.
+ * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
+ * but particular boards choose different booting order.
+ *
+ * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
+ * booting cluster (big or LITTLE) is chosen by IROM code by reading
+ * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
+ * from the LITTLE: Cortex-A7.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-&cpu0 {
-	device_type = "cpu";
-	compatible = "arm,cortex-a7";
-	reg = <0x100>;
-	clock-frequency = <1000000000>;
-	cci-control-port = <&cci_control0>;
-};
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 
-&cpu1 {
-	device_type = "cpu";
-	compatible = "arm,cortex-a7";
-	reg = <0x101>;
-	clock-frequency = <1000000000>;
-	cci-control-port = <&cci_control0>;
-};
+		cpu0: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x100>;
+			clocks = <&clock CLK_KFC_CLK>;
+			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cluster_a7_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <11>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
 
-&cpu2 {
-	device_type = "cpu";
-	compatible = "arm,cortex-a7";
-	reg = <0x102>;
-	clock-frequency = <1000000000>;
-	cci-control-port = <&cci_control0>;
-};
+		cpu1: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x101>;
+			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cluster_a7_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <11>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
 
-&cpu3 {
-	device_type = "cpu";
-	compatible = "arm,cortex-a7";
-	reg = <0x103>;
-	clock-frequency = <1000000000>;
-	cci-control-port = <&cci_control0>;
-};
+		cpu2: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x102>;
+			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cluster_a7_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <11>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
 
-&cpu4 {
-	device_type = "cpu";
-	compatible = "arm,cortex-a15";
-	reg = <0x0>;
-	clock-frequency = <1800000000>;
-	cci-control-port = <&cci_control1>;
-};
+		cpu3: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x103>;
+			clock-frequency = <1000000000>;
+			cci-control-port = <&cci_control0>;
+			operating-points-v2 = <&cluster_a7_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <11>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
 
-&cpu5 {
-	device_type = "cpu";
-	compatible = "arm,cortex-a15";
-	reg = <0x1>;
-	clock-frequency = <1800000000>;
-	cci-control-port = <&cci_control1>;
-};
+		cpu4: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			clocks = <&clock CLK_ARM_CLK>;
+			reg = <0x0>;
+			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cluster_a15_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <15>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
 
-&cpu6 {
-	device_type = "cpu";
-	compatible = "arm,cortex-a15";
-	reg = <0x2>;
-	clock-frequency = <1800000000>;
-	cci-control-port = <&cci_control1>;
-};
+		cpu5: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x1>;
+			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cluster_a15_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <15>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+
+		cpu6: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x2>;
+			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cluster_a15_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <15>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
 
-&cpu7 {
-	device_type = "cpu";
-	compatible = "arm,cortex-a15";
-	reg = <0x3>;
-	clock-frequency = <1800000000>;
-	cci-control-port = <&cci_control1>;
+		cpu7: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0x3>;
+			clock-frequency = <1800000000>;
+			cci-control-port = <&cci_control1>;
+			operating-points-v2 = <&cluster_a15_opp_table>;
+			cooling-min-level = <0>;
+			cooling-max-level = <15>;
+			#cooling-cells = <2>; /* min followed by max */
+		};
+	};
 };
diff --git a/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi b/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi
index 9134217446b8..2a4e10bc8801 100644
--- a/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi
+++ b/sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi
@@ -56,6 +56,89 @@
 	};
 };
 
+&bus_wcore {
+	devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
+			<&nocp_mem1_0>, <&nocp_mem1_1>;
+	vdd-supply = <&buck3_reg>;
+	exynos,saturation-ratio = <100>;
+	status = "okay";
+};
+
+&bus_noc {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_fsys_apb {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_fsys {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_fsys2 {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_mfc {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_gen {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_peri {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_g2d {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_g2d_acp {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_jpeg {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_jpeg_apb {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_disp1_fimd {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_disp1 {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_gscl_scaler {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
+&bus_mscl {
+	devfreq = <&bus_wcore>;
+	status = "okay";
+};
+
 &clock_audss {
 	assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
 			<&clock_audss EXYNOS_MOUT_I2S>,
@@ -67,6 +150,14 @@
 			<19200000>;
 };
 
+&cpu0 {
+	cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck2_reg>;
+};
+
 &hdmi {
 	status = "okay";
 	hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
@@ -84,13 +175,6 @@
 	s2mps11_pmic@66 {
 		compatible = "samsung,s2mps11-pmic";
 		reg = <0x66>;
-		s2mps11,buck2-ramp-delay = <12>;
-		s2mps11,buck34-ramp-delay = <12>;
-		s2mps11,buck16-ramp-delay = <12>;
-		s2mps11,buck6-ramp-enable = <1>;
-		s2mps11,buck2-ramp-enable = <1>;
-		s2mps11,buck3-ramp-enable = <1>;
-		s2mps11,buck4-ramp-enable = <1>;
 		samsung,s2mps11-acokb-ground;
 
 		interrupt-parent = <&gpx0>;
@@ -113,10 +197,9 @@
 			};
 
 			ldo3_reg: LDO3 {
-				regulator-name = "vdd_ldo3";
+				regulator-name = "vddq_mmc0";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
-				regulator-always-on;
 			};
 
 			ldo5_reg: LDO5 {
@@ -176,10 +259,9 @@
 			};
 
 			ldo13_reg: LDO13 {
-				regulator-name = "vdd_ldo13";
+				regulator-name = "vddq_mmc2";
 				regulator-min-microvolt = <2800000>;
 				regulator-max-microvolt = <2800000>;
-				regulator-always-on;
 			};
 
 			ldo15_reg: LDO15 {
@@ -203,11 +285,16 @@
 				regulator-always-on;
 			};
 
+			ldo18_reg: LDO18 {
+				regulator-name = "vdd_emmc_1V8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
 			ldo19_reg: LDO19 {
 				regulator-name = "vdd_sd";
 				regulator-min-microvolt = <2800000>;
 				regulator-max-microvolt = <2800000>;
-				regulator-always-on;
 			};
 
 			ldo24_reg: LDO24 {
@@ -339,6 +426,8 @@
 	cap-mmc-highspeed;
 	mmc-hs200-1_8v;
 	mmc-hs400-1_8v;
+	vmmc-supply = <&ldo18_reg>;
+	vqmmc-supply = <&ldo3_reg>;
 };
 
 &mmc_2 {
@@ -351,6 +440,24 @@
 	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
 	bus-width = <4>;
 	cap-sd-highspeed;
+	vmmc-supply = <&ldo19_reg>;
+	vqmmc-supply = <&ldo13_reg>;
+};
+
+&nocp_mem0_0 {
+	status = "okay";
+};
+
+&nocp_mem0_1 {
+	status = "okay";
+};
+
+&nocp_mem1_0 {
+	status = "okay";
+};
+
+&nocp_mem1_1 {
+	status = "okay";
 };
 
 &pinctrl_0 {
diff --git a/sys/gnu/dts/arm/exynos5440.dtsi b/sys/gnu/dts/arm/exynos5440.dtsi
index f18b51f2eeaa..fd176819b4bf 100644
--- a/sys/gnu/dts/arm/exynos5440.dtsi
+++ b/sys/gnu/dts/arm/exynos5440.dtsi
@@ -132,7 +132,7 @@
 		clock-names = "spi", "spi_busclk0";
 	};
 
-	pin_ctrl: pinctrl {
+	pin_ctrl: pinctrl@E0000 {
 		compatible = "samsung,exynos5440-pinctrl";
 		reg = <0xE0000 0x1000>;
 		interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
@@ -200,12 +200,12 @@
 	amba {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		interrupt-parent = <&gic>;
 		ranges;
 	};
 
-	rtc {
+	rtc@130000 {
 		compatible = "samsung,s3c6410-rtc";
 		reg = <0x130000 0x1000>;
 		interrupts = <0 17 0>, <0 16 0>;
diff --git a/sys/gnu/dts/arm/exynos5800-peach-pi.dts b/sys/gnu/dts/arm/exynos5800-peach-pi.dts
index 064176f201e7..62ceb89e073f 100644
--- a/sys/gnu/dts/arm/exynos5800-peach-pi.dts
+++ b/sys/gnu/dts/arm/exynos5800-peach-pi.dts
@@ -15,6 +15,7 @@
 #include <dt-bindings/clock/maxim,max77802.h>
 #include <dt-bindings/regulator/maxim,max77802.h>
 #include "exynos5800.dtsi"
+#include "exynos5420-cpus.dtsi"
 
 / {
 	model = "Google Peach Pi Rev 10+";
@@ -63,7 +64,7 @@
 			label = "Power";
 			gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		lid-switch {
@@ -72,7 +73,7 @@
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0>; /* SW_LID */
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 	};
@@ -143,13 +144,19 @@
 	vdd-supply = <&ldo9_reg>;
 };
 
+&cpu0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+	cpu-supply = <&buck6_reg>;
+};
+
 &dp {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
@@ -662,6 +669,11 @@
 	status = "okay";
 };
 
+&mfc {
+	samsung,mfc-r = <0x43000000 0x800000>;
+	samsung,mfc-l = <0x51000000 0x800000>;
+};
+
 &mmc_0 {
 	status = "okay";
 	num-slots = <1>;
diff --git a/sys/gnu/dts/arm/exynos5800.dtsi b/sys/gnu/dts/arm/exynos5800.dtsi
index c0bb3563cac1..8213016803e5 100644
--- a/sys/gnu/dts/arm/exynos5800.dtsi
+++ b/sys/gnu/dts/arm/exynos5800.dtsi
@@ -23,6 +23,114 @@
 	compatible = "samsung,exynos5800-clock";
 };
 
+&cluster_a15_opp_table {
+	opp@1700000000 {
+		opp-microvolt = <1250000>;
+	};
+	opp@1600000000 {
+		opp-microvolt = <1250000>;
+	};
+	opp@1500000000 {
+		opp-microvolt = <1100000>;
+	};
+	opp@1400000000 {
+		opp-microvolt = <1100000>;
+	};
+	opp@1300000000 {
+		opp-microvolt = <1100000>;
+	};
+	opp@1200000000 {
+		opp-microvolt = <1000000>;
+	};
+	opp@1100000000 {
+		opp-microvolt = <1000000>;
+	};
+	opp@1000000000 {
+		opp-microvolt = <1000000>;
+	};
+	opp@900000000 {
+		opp-microvolt = <1000000>;
+	};
+	opp@800000000 {
+		opp-microvolt = <900000>;
+	};
+	opp@700000000 {
+		opp-microvolt = <900000>;
+	};
+	opp@600000000 {
+		opp-hz = /bits/ 64 <600000000>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <140000>;
+	};
+	opp@500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <140000>;
+	};
+	opp@400000000 {
+		opp-hz = /bits/ 64 <400000000>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <140000>;
+	};
+	opp@300000000 {
+		opp-hz = /bits/ 64 <300000000>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <140000>;
+	};
+	opp@200000000 {
+		opp-hz = /bits/ 64 <200000000>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <140000>;
+	};
+};
+
+&cluster_a7_opp_table {
+	opp@1300000000 {
+		opp-microvolt = <1250000>;
+	};
+	opp@1200000000 {
+		opp-microvolt = <1250000>;
+	};
+	opp@1100000000 {
+		opp-microvolt = <1250000>;
+	};
+	opp@1000000000 {
+		opp-microvolt = <1100000>;
+	};
+	opp@900000000 {
+		opp-microvolt = <1100000>;
+	};
+	opp@800000000 {
+		opp-microvolt = <1100000>;
+	};
+	opp@700000000 {
+		opp-microvolt = <1000000>;
+	};
+	opp@600000000 {
+		opp-microvolt = <1000000>;
+	};
+	opp@500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <140000>;
+	};
+	opp@400000000 {
+		opp-hz = /bits/ 64 <400000000>;
+		opp-microvolt = <1000000>;
+		clock-latency-ns = <140000>;
+	};
+	opp@300000000 {
+		opp-hz = /bits/ 64 <300000000>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <140000>;
+	};
+	opp@200000000 {
+		opp-hz = /bits/ 64 <200000000>;
+		opp-microvolt = <900000>;
+		clock-latency-ns = <140000>;
+	};
+};
+
 &mfc {
 	compatible = "samsung,mfc-v8";
 };
diff --git a/sys/gnu/dts/arm/hi3620.dtsi b/sys/gnu/dts/arm/hi3620.dtsi
index 6cbb62e5c6a9..c85d07e6db61 100644
--- a/sys/gnu/dts/arm/hi3620.dtsi
+++ b/sys/gnu/dts/arm/hi3620.dtsi
@@ -68,7 +68,7 @@
 
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		interrupt-parent = <&gic>;
 		ranges = <0 0xfc000000 0x2000000>;
 
diff --git a/sys/gnu/dts/arm/hip01.dtsi b/sys/gnu/dts/arm/hip01.dtsi
index 33130f8461c3..4e9562f806a2 100644
--- a/sys/gnu/dts/arm/hip01.dtsi
+++ b/sys/gnu/dts/arm/hip01.dtsi
@@ -43,7 +43,7 @@
 		amba {
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			ranges;
 
 			uart0: uart@10001000 {
diff --git a/sys/gnu/dts/arm/hisi-x5hd2.dtsi b/sys/gnu/dts/arm/hisi-x5hd2.dtsi
index c52722b14e4a..fdcc23d203e5 100644
--- a/sys/gnu/dts/arm/hisi-x5hd2.dtsi
+++ b/sys/gnu/dts/arm/hisi-x5hd2.dtsi
@@ -34,7 +34,7 @@
 		amba {
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			ranges;
 
 			timer0: timer@00002000 {
diff --git a/sys/gnu/dts/arm/imx23.dtsi b/sys/gnu/dts/arm/imx23.dtsi
index 1c6c07538a78..302d1168f424 100644
--- a/sys/gnu/dts/arm/imx23.dtsi
+++ b/sys/gnu/dts/arm/imx23.dtsi
@@ -569,7 +569,7 @@
 		};
 	};
 
-	iio_hwmon {
+	iio-hwmon {
 		compatible = "iio-hwmon";
 		io-channels = <&lradc 8>;
 	};
diff --git a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts b/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts
index ed1d0b4578ef..cda6907a27b9 100644
--- a/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/sys/gnu/dts/arm/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -30,7 +30,7 @@
 			label = "BP1";
 			gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_MISC>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/imx25-pinfunc.h b/sys/gnu/dts/arm/imx25-pinfunc.h
index 848ffa785b63..f96fa2df8f11 100644
--- a/sys/gnu/dts/arm/imx25-pinfunc.h
+++ b/sys/gnu/dts/arm/imx25-pinfunc.h
@@ -110,20 +110,20 @@
 #define MX25_PAD_CS4__UART5_CTS			0x054 0x264 0x000 0x13 0x000
 #define MX25_PAD_CS4__GPIO_3_20			0x054 0x264 0x000 0x15 0x000
 
-#define MX25_PAD_CS5__CS5			0x058 0x268 0x000 0x10 0x000
+#define MX25_PAD_CS5__CS5			0x058 0x268 0x000 0x00 0x000
 #define MX25_PAD_CS5__NF_CE2			0x058 0x268 0x000 0x01 0x000
-#define MX25_PAD_CS5__UART5_RTS			0x058 0x268 0x574 0x13 0x000
-#define MX25_PAD_CS5__GPIO_3_21			0x058 0x268 0x000 0x15 0x000
+#define MX25_PAD_CS5__UART5_RTS			0x058 0x268 0x574 0x03 0x000
+#define MX25_PAD_CS5__GPIO_3_21			0x058 0x268 0x000 0x05 0x000
 
 #define MX25_PAD_NF_CE0__NF_CE0			0x05c 0x26c 0x000 0x10 0x000
 #define MX25_PAD_NF_CE0__GPIO_3_22		0x05c 0x26c 0x000 0x15 0x000
 
 #define MX25_PAD_ECB__ECB			0x060 0x270 0x000 0x10 0x000
-#define MX25_PAD_ECB__UART5_TXD_MUX		0x060 0x270 0x000 0x13 0x000
+#define MX25_PAD_ECB__UART5_TXD			0x060 0x270 0x000 0x13 0x000
 #define MX25_PAD_ECB__GPIO_3_23			0x060 0x270 0x000 0x15 0x000
 
 #define MX25_PAD_LBA__LBA			0x064 0x274 0x000 0x10 0x000
-#define MX25_PAD_LBA__UART5_RXD_MUX		0x064 0x274 0x578 0x13 0x000
+#define MX25_PAD_LBA__UART5_RXD			0x064 0x274 0x578 0x13 0x000
 #define MX25_PAD_LBA__GPIO_3_24			0x064 0x274 0x000 0x15 0x000
 
 #define MX25_PAD_BCLK__BCLK			0x068 0x000 0x000 0x00 0x000
@@ -237,17 +237,21 @@
 #define MX25_PAD_LD7__GPIO_1_21			0x0e4 0x2dc 0x000 0x15 0x000
 
 #define MX25_PAD_LD8__LD8			0x0e8 0x2e0 0x000 0x10 0x000
+#define MX25_PAD_LD8__UART4_RXD			0x0e8 0x2e0 0x570 0x12 0x000
 #define MX25_PAD_LD8__FEC_TX_ERR		0x0e8 0x2e0 0x000 0x15 0x000
 #define MX25_PAD_LD8__SDHC2_CMD			0x0e8 0x2e0 0x4e0 0x06 0x000
 
 #define MX25_PAD_LD9__LD9			0x0ec 0x2e4 0x000 0x10 0x000
+#define MX25_PAD_LD9__UART4_TXD			0x0ec 0x2e4 0x000 0x12 0x000
 #define MX25_PAD_LD9__FEC_COL			0x0ec 0x2e4 0x504 0x15 0x001
 #define MX25_PAD_LD9__SDHC2_CLK			0x0ec 0x2e4 0x4dc 0x06 0x000
 
-#define MX25_PAD_LD10__LD10			0x0f0 0x2e8 0x000 0x10 0x000
-#define MX25_PAD_LD10__FEC_RX_ERR		0x0f0 0x2e8 0x518 0x15 0x001
+#define MX25_PAD_LD10__LD10			0x0f0 0x2e8 0x000 0x00 0x000
+#define MX25_PAD_LD10__UART4_RTS		0x0f0 0x2e8 0x56c 0x02 0x000
+#define MX25_PAD_LD10__FEC_RX_ERR		0x0f0 0x2e8 0x518 0x05 0x001
 
 #define MX25_PAD_LD11__LD11			0x0f4 0x2ec 0x000 0x10 0x000
+#define MX25_PAD_LD11__UART4_CTS		0x0f4 0x2ec 0x000 0x12 0x000
 #define MX25_PAD_LD11__FEC_RDATA2		0x0f4 0x2ec 0x50c 0x15 0x001
 #define MX25_PAD_LD11__SDHC2_DAT1		0x0f4 0x2ec 0x4e8 0x06 0x000
 
@@ -291,22 +295,22 @@
 #define MX25_PAD_PWM__USBH2_OC			0x11c 0x314 0x580 0x16 0x001
 
 #define MX25_PAD_CSI_D2__CSI_D2			0x120 0x318 0x000 0x10 0x000
-#define MX25_PAD_CSI_D2__UART5_RXD_MUX		0x120 0x318 0x578 0x11 0x001
+#define MX25_PAD_CSI_D2__UART5_RXD		0x120 0x318 0x578 0x11 0x001
 #define MX25_PAD_CSI_D2__SIM1_CLK0		0x120 0x318 0x000 0x04 0x000
 #define MX25_PAD_CSI_D2__GPIO_1_27		0x120 0x318 0x000 0x15 0x000
 #define MX25_PAD_CSI_D2__CSPI3_MOSI		0x120 0x318 0x000 0x17 0x000
 
 #define MX25_PAD_CSI_D3__CSI_D3			0x124 0x31c 0x000 0x10 0x000
-#define MX25_PAD_CSI_D3__UART5_TXD_MUX		0x124 0x31c 0x000 0x11 0x000
+#define MX25_PAD_CSI_D3__UART5_TXD		0x124 0x31c 0x000 0x11 0x000
 #define MX25_PAD_CSI_D3__SIM1_RST0		0x124 0x31c 0x000 0x04 0x000
 #define MX25_PAD_CSI_D3__GPIO_1_28		0x124 0x31c 0x000 0x15 0x000
 #define MX25_PAD_CSI_D3__CSPI3_MISO		0x124 0x31c 0x4b4 0x17 0x001
 
-#define MX25_PAD_CSI_D4__CSI_D4			0x128 0x320 0x000 0x10 0x000
-#define MX25_PAD_CSI_D4__UART5_RTS		0x128 0x320 0x574 0x11 0x001
+#define MX25_PAD_CSI_D4__CSI_D4			0x128 0x320 0x000 0x00 0x000
+#define MX25_PAD_CSI_D4__UART5_RTS		0x128 0x320 0x574 0x01 0x001
 #define MX25_PAD_CSI_D4__SIM1_VEN0		0x128 0x320 0x000 0x04 0x000
-#define MX25_PAD_CSI_D4__GPIO_1_29		0x128 0x320 0x000 0x15 0x000
-#define MX25_PAD_CSI_D4__CSPI3_SCLK		0x128 0x320 0x000 0x17 0x000
+#define MX25_PAD_CSI_D4__GPIO_1_29		0x128 0x320 0x000 0x05 0x000
+#define MX25_PAD_CSI_D4__CSPI3_SCLK		0x128 0x320 0x000 0x07 0x000
 
 #define MX25_PAD_CSI_D5__CSI_D5			0x12c 0x324 0x000 0x10 0x000
 #define MX25_PAD_CSI_D5__UART5_CTS		0x12c 0x324 0x000 0x11 0x000
@@ -360,7 +364,7 @@
 #define MX25_PAD_I2C1_DAT__GPIO_1_13		0x154 0x34c 0x000 0x15 0x000
 
 #define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		0x158 0x350 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_MOSI__UART3_RXD		0x158 0x350 0x000 0x12 0x000
+#define MX25_PAD_CSPI1_MOSI__UART3_RXD		0x158 0x350 0x568 0x12 0x000
 #define MX25_PAD_CSPI1_MOSI__GPIO_1_14		0x158 0x350 0x000 0x15 0x000
 
 #define MX25_PAD_CSPI1_MISO__CSPI1_MISO		0x15c 0x354 0x000 0x10 0x000
@@ -371,10 +375,10 @@
 #define MX25_PAD_CSPI1_SS0__PWM2_PWMO		0x160 0x358 0x000 0x12 0x000
 #define MX25_PAD_CSPI1_SS0__GPIO_1_16		0x160 0x358 0x000 0x15 0x000
 
-#define MX25_PAD_CSPI1_SS1__CSPI1_SS1		0x164 0x35c 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_SS1__I2C3_DAT		0x164 0x35C 0x528 0x11 0x001
-#define MX25_PAD_CSPI1_SS1__UART3_RTS		0x164 0x35c 0x000 0x12 0x000
-#define MX25_PAD_CSPI1_SS1__GPIO_1_17		0x164 0x35c 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_SS1__CSPI1_SS1		0x164 0x35c 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_SS1__I2C3_DAT		0x164 0x35C 0x528 0x01 0x001
+#define MX25_PAD_CSPI1_SS1__UART3_RTS		0x164 0x35c 0x000 0x02 0x000
+#define MX25_PAD_CSPI1_SS1__GPIO_1_17		0x164 0x35c 0x000 0x05 0x000
 
 #define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK		0x168 0x360 0x000 0x10 0x000
 #define MX25_PAD_CSPI1_SCLK__UART3_CTS		0x168 0x360 0x000 0x12 0x000
@@ -383,20 +387,24 @@
 #define MX25_PAD_CSPI1_RDY__CSPI1_RDY		0x16c 0x364 0x000 0x10 0x000
 #define MX25_PAD_CSPI1_RDY__GPIO_2_22		0x16c 0x364 0x000 0x15 0x000
 
-#define MX25_PAD_UART1_RXD__UART1_RXD		0x170 0x368 0x000 0x10 0x000
-#define MX25_PAD_UART1_RXD__GPIO_4_22		0x170 0x368 0x000 0x15 0x000
+#define MX25_PAD_UART1_RXD__UART1_RXD		0x170 0x368 0x000 0x00 0x000
+#define MX25_PAD_UART1_RXD__UART2_DTR		0x170 0x368 0x000 0x03 0x000
+#define MX25_PAD_UART1_RXD__GPIO_4_22		0x170 0x368 0x000 0x05 0x000
 
-#define MX25_PAD_UART1_TXD__UART1_TXD		0x174 0x36c 0x000 0x10 0x000
-#define MX25_PAD_UART1_TXD__GPIO_4_23		0x174 0x36c 0x000 0x15 0x000
+#define MX25_PAD_UART1_TXD__UART1_TXD		0x174 0x36c 0x000 0x00 0x000
+#define MX25_PAD_UART1_TXD__UART2_DSR		0x174 0x36c 0x000 0x03 0x000
+#define MX25_PAD_UART1_TXD__GPIO_4_23		0x174 0x36c 0x000 0x05 0x000
 
-#define MX25_PAD_UART1_RTS__UART1_RTS		0x178 0x370 0x000 0x10 0x000
-#define MX25_PAD_UART1_RTS__CSI_D0		0x178 0x370 0x488 0x11 0x001
-#define MX25_PAD_UART1_RTS__CC3			0x178 0x370 0x000 0x12 0x000
-#define MX25_PAD_UART1_RTS__GPIO_4_24		0x178 0x370 0x000 0x15 0x000
+#define MX25_PAD_UART1_RTS__UART1_RTS		0x178 0x370 0x000 0x00 0x000
+#define MX25_PAD_UART1_RTS__CSI_D0		0x178 0x370 0x488 0x01 0x001
+#define MX25_PAD_UART1_RTS__CC3			0x178 0x370 0x000 0x02 0x000
+#define MX25_PAD_UART1_RTS__UART2_DCD		0x178 0x370 0x000 0x03 0x000
+#define MX25_PAD_UART1_RTS__GPIO_4_24		0x178 0x370 0x000 0x05 0x000
 
-#define MX25_PAD_UART1_CTS__UART1_CTS		0x17c 0x374 0x000 0x10 0x000
-#define MX25_PAD_UART1_CTS__CSI_D1		0x17c 0x374 0x48c 0x11 0x001
-#define MX25_PAD_UART1_CTS__GPIO_4_25		0x17c 0x374 0x000 0x15 0x000
+#define MX25_PAD_UART1_CTS__UART1_CTS		0x17c 0x374 0x000 0x00 0x000
+#define MX25_PAD_UART1_CTS__CSI_D1		0x17c 0x374 0x48c 0x01 0x001
+#define MX25_PAD_UART1_CTS__UART2_RI		0x17c 0x374 0x000 0x03 0x001
+#define MX25_PAD_UART1_CTS__GPIO_4_25		0x17c 0x374 0x000 0x05 0x000
 
 #define MX25_PAD_UART2_RXD__UART2_RXD		0x180 0x378 0x000 0x10 0x000
 #define MX25_PAD_UART2_RXD__GPIO_4_26		0x180 0x378 0x000 0x15 0x000
@@ -404,10 +412,10 @@
 #define MX25_PAD_UART2_TXD__UART2_TXD		0x184 0x37c 0x000 0x10 0x000
 #define MX25_PAD_UART2_TXD__GPIO_4_27		0x184 0x37c 0x000 0x15 0x000
 
-#define MX25_PAD_UART2_RTS__UART2_RTS		0x188 0x380 0x000 0x10 0x000
-#define MX25_PAD_UART2_RTS__FEC_COL		0x188 0x380 0x504 0x12 0x002
-#define MX25_PAD_UART2_RTS__CC1			0x188 0x380 0x000 0x13 0x000
-#define MX25_PAD_UART2_RTS__GPIO_4_28		0x188 0x380 0x000 0x15 0x000
+#define MX25_PAD_UART2_RTS__UART2_RTS		0x188 0x380 0x000 0x00 0x000
+#define MX25_PAD_UART2_RTS__FEC_COL		0x188 0x380 0x504 0x02 0x002
+#define MX25_PAD_UART2_RTS__CC1			0x188 0x380 0x000 0x03 0x000
+#define MX25_PAD_UART2_RTS__GPIO_4_28		0x188 0x380 0x000 0x05 0x000
 
 #define MX25_PAD_UART2_CTS__UART2_CTS		0x18c 0x384 0x000 0x10 0x000
 #define MX25_PAD_UART2_CTS__FEC_RX_ERR		0x18c 0x384 0x518 0x12 0x002
@@ -439,36 +447,42 @@
 #define MX25_PAD_SD1_DATA3__FEC_CRS		0x1a4 0x39c 0x508 0x12 0x002
 #define MX25_PAD_SD1_DATA3__GPIO_2_28		0x1a4 0x39c 0x000 0x15 0x000
 
-#define MX25_PAD_KPP_ROW0__KPP_ROW0		0x1a8 0x3a0 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW0__UART1_DTR		0x1a8 0x3a0 0x000 0x14 0x000
-#define MX25_PAD_KPP_ROW0__GPIO_2_29		0x1a8 0x3a0 0x000 0x15 0x000
+#define MX25_PAD_KPP_ROW0__KPP_ROW0		0x1a8 0x3a0 0x000 0x00 0x000
+#define MX25_PAD_KPP_ROW0__UART3_RXD		0x1a8 0x3a0 0x568 0x01 0x001
+#define MX25_PAD_KPP_ROW0__UART1_DTR		0x1a8 0x3a0 0x000 0x04 0x000
+#define MX25_PAD_KPP_ROW0__GPIO_2_29		0x1a8 0x3a0 0x000 0x05 0x000
 
-#define MX25_PAD_KPP_ROW1__KPP_ROW1		0x1ac 0x3a4 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW1__GPIO_2_30		0x1ac 0x3a4 0x000 0x15 0x000
+#define MX25_PAD_KPP_ROW1__KPP_ROW1		0x1ac 0x3a4 0x000 0x00 0x000
+#define MX25_PAD_KPP_ROW1__UART3_TXD		0x1ac 0x3a4 0x000 0x01 0x000
+#define MX25_PAD_KPP_ROW1__UART1_DSR		0x1ac 0x3a4 0x000 0x04 0x000
+#define MX25_PAD_KPP_ROW1__GPIO_2_30		0x1ac 0x3a4 0x000 0x05 0x000
 
-#define MX25_PAD_KPP_ROW2__KPP_ROW2		0x1b0 0x3a8 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW2__CSI_D0		0x1b0 0x3a8 0x488 0x13 0x002
-#define MX25_PAD_KPP_ROW2__UART1_DCD		0x1b0 0x3a8 0x000 0x14 0x000
-#define MX25_PAD_KPP_ROW2__GPIO_2_31		0x1b0 0x3a8 0x000 0x15 0x000
+#define MX25_PAD_KPP_ROW2__KPP_ROW2		0x1b0 0x3a8 0x000 0x00 0x000
+#define MX25_PAD_KPP_ROW2__UART3_RTS		0x1b0 0x3a8 0x000 0x01 0x000
+#define MX25_PAD_KPP_ROW2__CSI_D0		0x1b0 0x3a8 0x488 0x03 0x002
+#define MX25_PAD_KPP_ROW2__UART1_DCD		0x1b0 0x3a8 0x000 0x04 0x000
+#define MX25_PAD_KPP_ROW2__GPIO_2_31		0x1b0 0x3a8 0x000 0x05 0x000
 
-#define MX25_PAD_KPP_ROW3__KPP_ROW3		0x1b4 0x3ac 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW3__CSI_D1		0x1b4 0x3ac 0x48c 0x13 0x002
-#define MX25_PAD_KPP_ROW3__GPIO_3_0		0x1b4 0x3ac 0x000 0x15 0x000
+#define MX25_PAD_KPP_ROW3__KPP_ROW3		0x1b4 0x3ac 0x000 0x00 0x000
+#define MX25_PAD_KPP_ROW3__UART3_CTS		0x1b4 0x3ac 0x000 0x01 0x000
+#define MX25_PAD_KPP_ROW3__CSI_D1		0x1b4 0x3ac 0x48c 0x03 0x002
+#define MX25_PAD_KPP_ROW3__UART1_RI		0x1b4 0x3ac 0x000 0x04 0x000
+#define MX25_PAD_KPP_ROW3__GPIO_3_0		0x1b4 0x3ac 0x000 0x05 0x000
 
 #define MX25_PAD_KPP_COL0__KPP_COL0		0x1b8 0x3b0 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL0__UART4_RXD_MUX	0x1b8 0x3b0 0x570 0x11 0x001
+#define MX25_PAD_KPP_COL0__UART4_RXD		0x1b8 0x3b0 0x570 0x11 0x001
 #define MX25_PAD_KPP_COL0__AUD5_TXD		0x1b8 0x3b0 0x000 0x12 0x000
 #define MX25_PAD_KPP_COL0__GPIO_3_1		0x1b8 0x3b0 0x000 0x15 0x000
 
 #define MX25_PAD_KPP_COL1__KPP_COL1		0x1bc 0x3b4 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL1__UART4_TXD_MUX	0x1bc 0x3b4 0x000 0x11 0x000
+#define MX25_PAD_KPP_COL1__UART4_TXD		0x1bc 0x3b4 0x000 0x11 0x000
 #define MX25_PAD_KPP_COL1__AUD5_RXD		0x1bc 0x3b4 0x000 0x12 0x000
 #define MX25_PAD_KPP_COL1__GPIO_3_2		0x1bc 0x3b4 0x000 0x15 0x000
 
-#define MX25_PAD_KPP_COL2__KPP_COL2		0x1c0 0x3b8 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL2__UART4_RTS		0x1c0 0x3b8 0x000 0x11 0x000
-#define MX25_PAD_KPP_COL2__AUD5_TXC		0x1c0 0x3b8 0x000 0x12 0x000
-#define MX25_PAD_KPP_COL2__GPIO_3_3		0x1c0 0x3b8 0x000 0x15 0x000
+#define MX25_PAD_KPP_COL2__KPP_COL2		0x1c0 0x3b8 0x000 0x00 0x000
+#define MX25_PAD_KPP_COL2__UART4_RTS		0x1c0 0x3b8 0x56c 0x01 0x001
+#define MX25_PAD_KPP_COL2__AUD5_TXC		0x1c0 0x3b8 0x000 0x02 0x000
+#define MX25_PAD_KPP_COL2__GPIO_3_3		0x1c0 0x3b8 0x000 0x05 0x000
 
 #define MX25_PAD_KPP_COL3__KPP_COL3		0x1c4 0x3bc 0x000 0x10 0x000
 #define MX25_PAD_KPP_COL3__UART4_CTS		0x1c4 0x3bc 0x000 0x11 0x000
@@ -557,9 +571,10 @@
 #define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK	0x210 0x000 0x000 0x10 0x000
 #define MX25_PAD_UPLL_BYPCLK__GPIO_3_16		0x210 0x000 0x000 0x15 0x000
 
-#define MX25_PAD_VSTBY_REQ__VSTBY_REQ		0x214 0x408 0x000 0x10 0x000
-#define MX25_PAD_VSTBY_REQ__AUD7_TXFS		0x214 0x408 0x000 0x14 0x000
-#define MX25_PAD_VSTBY_REQ__GPIO_3_17		0x214 0x408 0x000 0x15 0x000
+#define MX25_PAD_VSTBY_REQ__VSTBY_REQ		0x214 0x408 0x000 0x00 0x000
+#define MX25_PAD_VSTBY_REQ__AUD7_TXFS		0x214 0x408 0x000 0x04 0x000
+#define MX25_PAD_VSTBY_REQ__GPIO_3_17		0x214 0x408 0x000 0x05 0x000
+#define MX25_PAD_VSTBY_REQ__UART4_RTS		0x214 0x408 0x56c 0x06 0x002
 
 #define MX25_PAD_VSTBY_ACK__VSTBY_ACK		0x218 0x40c 0x000 0x10 0x000
 #define MX25_PAD_VSTBY_ACK__GPIO_3_18		0x218 0x40c 0x000 0x15 0x000
@@ -567,6 +582,7 @@
 #define MX25_PAD_POWER_FAIL__POWER_FAIL		0x21c 0x410 0x000 0x10 0x000
 #define MX25_PAD_POWER_FAIL__AUD7_RXD		0x21c 0x410 0x478 0x14 0x001
 #define MX25_PAD_POWER_FAIL__GPIO_3_19		0x21c 0x410 0x000 0x15 0x000
+#define MX25_PAD_POWER_FAIL__UART4_CTS		0x21c 0x410 0x000 0x16 0x000
 
 #define MX25_PAD_CLKO__CLKO			0x220 0x414 0x000 0x10 0x000
 #define MX25_PAD_CLKO__GPIO_2_21		0x220 0x414 0x000 0x15 0x000
diff --git a/sys/gnu/dts/arm/imx25.dtsi b/sys/gnu/dts/arm/imx25.dtsi
index cde329e9b9e3..af6af8741fe5 100644
--- a/sys/gnu/dts/arm/imx25.dtsi
+++ b/sys/gnu/dts/arm/imx25.dtsi
@@ -269,13 +269,36 @@
 				status = "disabled";
 			};
 
-			tsc: tsc@50030000 {
-				compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
-				reg = <0x50030000 0x4000>;
+			tscadc: tscadc@50030000 {
+				compatible = "fsl,imx25-tsadc";
+				reg = <0x50030000 0xc>;
 				interrupts = <46>;
 				clocks = <&clks 119>;
 				clock-names = "ipg";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <1>;
 				status = "disabled";
+
+				adc: adc@50030800 {
+					compatible = "fsl,imx25-gcq";
+					reg = <0x50030800 0x60>;
+					interrupt-parent = <&tscadc>;
+					interrupts = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					status = "disabled";
+				};
+
+				tsc: tcq@50030400 {
+					compatible = "fsl,imx25-tcq";
+					reg = <0x50030400 0x60>;
+					interrupt-parent = <&tscadc>;
+					interrupts = <0>;
+					fsl,wires = <4>;
+					status = "disabled";
+				};
 			};
 
 			ssi1: ssi@50034000 {
@@ -397,6 +420,15 @@
 				interrupts = <41>;
 			};
 
+			scc: crypto@53fac000 {
+				compatible = "fsl,imx25-scc";
+				reg = <0x53fac000 0x4000>;
+				clocks = <&clks 111>;
+				clock-names = "ipg";
+				interrupts = <49>, <50>;
+				interrupt-names = "scm", "smn";
+			};
+
 			esdhc1: esdhc@53fb4000 {
 				compatible = "fsl,imx25-esdhc";
 				reg = <0x53fb4000 0x4000>;
@@ -497,7 +529,8 @@
 				compatible = "fsl,imx25-usb", "fsl,imx27-usb";
 				reg = <0x53ff4000 0x0200>;
 				interrupts = <37>;
-				clocks = <&clks 70>;
+				clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+				clock-names = "ipg", "ahb", "per";
 				fsl,usbmisc = <&usbmisc 0>;
 				fsl,usbphy = <&usbphy0>;
 				status = "disabled";
@@ -507,7 +540,8 @@
 				compatible = "fsl,imx25-usb", "fsl,imx27-usb";
 				reg = <0x53ff4400 0x0200>;
 				interrupts = <35>;
-				clocks = <&clks 70>;
+				clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+				clock-names = "ipg", "ahb", "per";
 				fsl,usbmisc = <&usbmisc 1>;
 				fsl,usbphy = <&usbphy1>;
 				status = "disabled";
@@ -516,8 +550,6 @@
 			usbmisc: usbmisc@53ff4600 {
 				#index-cells = <1>;
 				compatible = "fsl,imx25-usbmisc";
-				clocks = <&clks 9>, <&clks 70>, <&clks 8>;
-				clock-names = "ipg", "ahb", "per";
 				reg = <0x53ff4600 0x00f>;
 			};
 
diff --git a/sys/gnu/dts/arm/imx28-apf28dev.dts b/sys/gnu/dts/arm/imx28-apf28dev.dts
index 7ac4f1af16ac..1eaa131e2d18 100644
--- a/sys/gnu/dts/arm/imx28-apf28dev.dts
+++ b/sys/gnu/dts/arm/imx28-apf28dev.dts
@@ -225,7 +225,7 @@
 			label = "User button";
 			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
 			linux,code = <0x100>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 };
diff --git a/sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi b/sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi
index 927b391d2058..88594747f454 100644
--- a/sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi
+++ b/sys/gnu/dts/arm/imx28-eukrea-mbmx28lc.dtsi
@@ -36,7 +36,7 @@
 			label = "SW3";
 			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_MISC>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -49,7 +49,7 @@
 			label = "SW4";
 			gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_MISC>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/imx28-m28.dtsi b/sys/gnu/dts/arm/imx28-m28.dtsi
index 759cc56253dd..6cebaa6b8833 100644
--- a/sys/gnu/dts/arm/imx28-m28.dtsi
+++ b/sys/gnu/dts/arm/imx28-m28.dtsi
@@ -27,32 +27,6 @@
 				pinctrl-names = "default";
 				pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
 				status = "okay";
-
-				partition@0 {
-					label = "bootloader";
-					reg = <0x00000000 0x00300000>;
-					read-only;
-				};
-
-				partition@1 {
-					label = "environment";
-					reg = <0x00300000 0x00080000>;
-				};
-
-				partition@2 {
-					label = "redundant-environment";
-					reg = <0x00380000 0x00080000>;
-				};
-
-				partition@3 {
-					label = "kernel";
-					reg = <0x00400000 0x00400000>;
-				};
-
-				partition@4 {
-					label = "filesystem";
-					reg = <0x00800000 0x0f800000>;
-				};
 			};
 		};
 
diff --git a/sys/gnu/dts/arm/imx28-tx28.dts b/sys/gnu/dts/arm/imx28-tx28.dts
index 4ea89344a5ff..fd20e99c777e 100644
--- a/sys/gnu/dts/arm/imx28-tx28.dts
+++ b/sys/gnu/dts/arm/imx28-tx28.dts
@@ -130,7 +130,7 @@
 			compatible = "fixed-clock";
 			reg = <0>;
 			#clock-cells = <0>;
-			clock-frequency = <27000000>;
+			clock-frequency = <26000000>;
 		};
 	};
 
@@ -202,7 +202,7 @@
 			0x02020049 /* row 2, col 2, KEY_KP9 */
 		>;
 		gpio-activelow;
-		linux,wakeup;
+		wakeup-source;
 		debounce-delay-ms = <100>;
 		col-scan-delay-us = <5000>;
 		linux,no-autorepeat;
diff --git a/sys/gnu/dts/arm/imx28.dtsi b/sys/gnu/dts/arm/imx28.dtsi
index fae7b9069fc4..74aa151cdb45 100644
--- a/sys/gnu/dts/arm/imx28.dtsi
+++ b/sys/gnu/dts/arm/imx28.dtsi
@@ -434,6 +434,32 @@
 					fsl,pull-up = <MXS_PULL_ENABLE>;
 				};
 
+				mac0_pins_b: mac0@1 {
+					reg = <1>;
+					fsl,pinmux-ids = <
+						MX28_PAD_ENET0_MDC__ENET0_MDC
+						MX28_PAD_ENET0_MDIO__ENET0_MDIO
+						MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
+						MX28_PAD_ENET0_RXD0__ENET0_RXD0
+						MX28_PAD_ENET0_RXD1__ENET0_RXD1
+						MX28_PAD_ENET0_RXD2__ENET0_RXD2
+						MX28_PAD_ENET0_RXD3__ENET0_RXD3
+						MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
+						MX28_PAD_ENET0_TXD0__ENET0_TXD0
+						MX28_PAD_ENET0_TXD1__ENET0_TXD1
+						MX28_PAD_ENET0_TXD2__ENET0_TXD2
+						MX28_PAD_ENET0_TXD3__ENET0_TXD3
+						MX28_PAD_ENET_CLK__CLKCTRL_ENET
+						MX28_PAD_ENET0_COL__ENET0_COL
+						MX28_PAD_ENET0_CRS__ENET0_CRS
+						MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
+						MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
+						>;
+					fsl,drive-strength = <MXS_DRIVE_8mA>;
+					fsl,voltage = <MXS_VOLTAGE_HIGH>;
+					fsl,pull-up = <MXS_PULL_ENABLE>;
+				};
+
 				mac1_pins_a: mac1@0 {
 					reg = <0>;
 					fsl,pinmux-ids = <
@@ -1256,7 +1282,7 @@
 		};
 	};
 
-	iio_hwmon {
+	iio-hwmon {
 		compatible = "iio-hwmon";
 		io-channels = <&lradc 8>;
 	};
diff --git a/sys/gnu/dts/arm/imx31.dtsi b/sys/gnu/dts/arm/imx31.dtsi
index 5fdb222636a7..1ce7ae94e7ad 100644
--- a/sys/gnu/dts/arm/imx31.dtsi
+++ b/sys/gnu/dts/arm/imx31.dtsi
@@ -69,6 +69,14 @@
 				status = "disabled";
 			};
 
+			kpp: kpp@43fa8000 {
+				compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
+				reg = <0x43fa8000 0x4000>;
+				interrupts = <24>;
+				clocks = <&clks 46>;
+				status = "disabled";
+			};
+
 			uart4: serial@43fb0000 {
 				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
 				reg = <0x43fb0000 0x4000>;
diff --git a/sys/gnu/dts/arm/imx35-eukrea-mbimxsd35-baseboard.dts b/sys/gnu/dts/arm/imx35-eukrea-mbimxsd35-baseboard.dts
index 75b036700d31..4727bbb804e1 100644
--- a/sys/gnu/dts/arm/imx35-eukrea-mbimxsd35-baseboard.dts
+++ b/sys/gnu/dts/arm/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -30,7 +30,7 @@
 			label = "BP1";
 			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_MISC>;
-			gpio-key,wakeup;
+			wakeup-source;
 			linux,input-type = <1>;
 		};
 	};
diff --git a/sys/gnu/dts/arm/imx35.dtsi b/sys/gnu/dts/arm/imx35.dtsi
index ed3dc3391d1c..490b7b44f1e7 100644
--- a/sys/gnu/dts/arm/imx35.dtsi
+++ b/sys/gnu/dts/arm/imx35.dtsi
@@ -137,6 +137,14 @@
 				status = "disabled";
 			};
 
+			kpp: kpp@43fa8000 {
+				compatible = "fsl,imx35-kpp", "fsl,imx21-kpp";
+				reg = <0x43fa8000 0x4000>;
+				interrupts = <24>;
+				clocks = <&clks 56>;
+				status = "disabled";
+			};
+
 			iomuxc: iomuxc@43fac000 {
 				compatible = "fsl,imx35-iomuxc";
 				reg = <0x43fac000 0x4000>;
@@ -305,7 +313,8 @@
 				compatible = "fsl,imx35-usb", "fsl,imx27-usb";
 				reg = <0x53ff4000 0x0200>;
 				interrupts = <37>;
-				clocks = <&clks 73>;
+				clocks = <&clks 9>, <&clks 73>, <&clks 28>;
+				clock-names = "ipg", "ahb", "per";
 				fsl,usbmisc = <&usbmisc 0>;
 				fsl,usbphy = <&usbphy0>;
 				status = "disabled";
@@ -315,7 +324,8 @@
 				compatible = "fsl,imx35-usb", "fsl,imx27-usb";
 				reg = <0x53ff4400 0x0200>;
 				interrupts = <35>;
-				clocks = <&clks 73>;
+				clocks = <&clks 9>, <&clks 73>, <&clks 28>;
+				clock-names = "ipg", "ahb", "per";
 				fsl,usbmisc = <&usbmisc 1>;
 				fsl,usbphy = <&usbphy1>;
 				dr_mode = "host";
@@ -325,8 +335,6 @@
 			usbmisc: usbmisc@53ff4600 {
 				#index-cells = <1>;
 				compatible = "fsl,imx35-usbmisc";
-				clocks = <&clks 9>, <&clks 73>, <&clks 28>;
-				clock-names = "ipg", "ahb", "per";
 				reg = <0x53ff4600 0x00f>;
 			};
 		};
diff --git a/sys/gnu/dts/arm/imx51-babbage.dts b/sys/gnu/dts/arm/imx51-babbage.dts
index 649befeb2cf9..018d24eb9965 100644
--- a/sys/gnu/dts/arm/imx51-babbage.dts
+++ b/sys/gnu/dts/arm/imx51-babbage.dts
@@ -107,7 +107,7 @@
 			label = "Power Button";
 			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi b/sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi
index 321662f53e33..16fc69c69ab2 100644
--- a/sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi
+++ b/sys/gnu/dts/arm/imx51-digi-connectcore-som.dtsi
@@ -156,7 +156,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_esdhc2>;
 	cap-sdio-irq;
-	enable-sdio-wakeup;
+	wakeup-source;
 	keep-power-in-suspend;
 	max-frequency = <50000000>;
 	no-1-8-v;
diff --git a/sys/gnu/dts/arm/imx51-eukrea-mbimxsd51-baseboard.dts b/sys/gnu/dts/arm/imx51-eukrea-mbimxsd51-baseboard.dts
index 34599c547459..d270df3e5891 100644
--- a/sys/gnu/dts/arm/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/sys/gnu/dts/arm/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -41,7 +41,7 @@
 			label = "BP1";
 			gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
 			linux,code = <256>;
-			gpio-key,wakeup;
+			wakeup-source;
 			linux,input-type = <1>;
 		};
 	};
diff --git a/sys/gnu/dts/arm/imx51-pinfunc.h b/sys/gnu/dts/arm/imx51-pinfunc.h
index 9eb92abaeb6d..82eae3c8a3ce 100644
--- a/sys/gnu/dts/arm/imx51-pinfunc.h
+++ b/sys/gnu/dts/arm/imx51-pinfunc.h
@@ -536,7 +536,6 @@
 #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7		0x2c4 0x6c4 0x000 0x3 0x0
 #define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK		0x2c4 0x6c4 0x000 0x0 0x0
 #define MX51_PAD_DISPB2_SER_CLK__GPIO3_7		0x2c4 0x6c4 0x990 0x4 0x1
-#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK		0x2c8 0x6c8 0x000 0x2 0x0
 #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16		0x2c8 0x6c8 0x000 0x2 0x0
 #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8		0x2c8 0x6c8 0x000 0x3 0x0
 #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS		0x2c8 0x6c8 0x000 0x0 0x0
diff --git a/sys/gnu/dts/arm/imx53-ard.dts b/sys/gnu/dts/arm/imx53-ard.dts
index 3bc18835fb4b..4486bc47d140 100644
--- a/sys/gnu/dts/arm/imx53-ard.dts
+++ b/sys/gnu/dts/arm/imx53-ard.dts
@@ -69,21 +69,21 @@
 			label = "Home";
 			gpios = <&gpio5 10 0>;
 			linux,code = <102>; /* KEY_HOME */
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		back {
 			label = "Back";
 			gpios = <&gpio5 11 0>;
 			linux,code = <158>; /* KEY_BACK */
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		program {
 			label = "Program";
 			gpios = <&gpio5 12 0>;
 			linux,code = <362>; /* KEY_PROGRAM */
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		volume-up {
diff --git a/sys/gnu/dts/arm/imx53-m53evk.dts b/sys/gnu/dts/arm/imx53-m53evk.dts
index 53f40885c530..dcee1e0f968f 100644
--- a/sys/gnu/dts/arm/imx53-m53evk.dts
+++ b/sys/gnu/dts/arm/imx53-m53evk.dts
@@ -84,6 +84,15 @@
 			regulator-max-microvolt = <5000000>;
 			gpio = <&gpio1 2 0>;
 		};
+
+		reg_usb_otg_vbus: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "usb_otg_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 4 0>;
+		};
 	};
 
 	sound {
@@ -168,6 +177,12 @@
 			>;
 		};
 
+		pinctrl_usbotg: usbotggrp {
+			fsl,pins = <
+				MX53_PAD_GPIO_4__GPIO1_4		0x000b0
+			>;
+		};
+
 		led_pin_gpio: led_gpio@0 {
 			fsl,pins = <
 				MX53_PAD_PATA_DATA8__GPIO2_8		0x80000000
@@ -351,6 +366,10 @@
 };
 
 &usbotg {
-	dr_mode = "peripheral";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	dr_mode = "otg";
+	vbus-supply = <&reg_usb_otg_vbus>;
+	disable-over-current;
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/imx53-qsb-common.dtsi b/sys/gnu/dts/arm/imx53-qsb-common.dtsi
index 53fd75c8ffcf..c05e7cfd0cbc 100644
--- a/sys/gnu/dts/arm/imx53-qsb-common.dtsi
+++ b/sys/gnu/dts/arm/imx53-qsb-common.dtsi
@@ -59,22 +59,22 @@
 
 		power {
 			label = "Power Button";
-			gpios = <&gpio1 8 0>;
-			linux,code = <116>; /* KEY_POWER */
+			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
 		};
 
 		volume-up {
 			label = "Volume Up";
-			gpios = <&gpio2 14 0>;
-			linux,code = <115>; /* KEY_VOLUMEUP */
-			gpio-key,wakeup;
+			gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+			wakeup-source;
 		};
 
 		volume-down {
 			label = "Volume Down";
-			gpios = <&gpio2 15 0>;
-			linux,code = <114>; /* KEY_VOLUMEDOWN */
-			gpio-key,wakeup;
+			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/imx53-tx53-x03x.dts b/sys/gnu/dts/arm/imx53-tx53-x03x.dts
index 13e842b0c785..0ecb43d88522 100644
--- a/sys/gnu/dts/arm/imx53-tx53-x03x.dts
+++ b/sys/gnu/dts/arm/imx53-tx53-x03x.dts
@@ -231,7 +231,7 @@
 		interrupts = <26 0>;
 		gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 		ti,x-plate-ohms = <660>;
-		linux,wakeup;
+		wakeup-source;
 	};
 };
 
diff --git a/sys/gnu/dts/arm/imx53-tx53-x13x.dts b/sys/gnu/dts/arm/imx53-tx53-x13x.dts
index 64804719f0f4..3cf682a681f4 100644
--- a/sys/gnu/dts/arm/imx53-tx53-x13x.dts
+++ b/sys/gnu/dts/arm/imx53-tx53-x13x.dts
@@ -101,7 +101,7 @@
 		interrupt-parent = <&gpio3>;
 		interrupts = <23 0>;
 		wakeup-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
-		linux,wakeup;
+		wakeup-source;
 	};
 };
 
@@ -126,7 +126,7 @@
 		interrupt-parent = <&gpio3>;
 		interrupts = <22 0>;
 		wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
-		linux,wakeup;
+		wakeup-source;
 	};
 };
 
@@ -183,13 +183,14 @@
 	status = "okay";
 
 	lvds0: lvds-channel@0 {
-		fsl,data-mapping = "jeida";
-		fsl,data-width = <24>;
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
 		status = "okay";
 
 		display-timings {
-			native-mode = <&lvds_timing0>;
-			lvds_timing0: hsd100pxn1 {
+			native-mode = <&lvds0_timing0>;
+
+			lvds0_timing0: hsd100pxn1 {
 				clock-frequency = <65000000>;
 				hactive = <1024>;
 				vactive = <768>;
@@ -202,19 +203,36 @@
 				hsync-active = <0>;
 				vsync-active = <0>;
 				de-active = <1>;
-				pixelclk-active = <0>;
+				pixelclk-active = <1>;
+			};
+
+			lvds0_timing1: nl12880bc20 {
+				clock-frequency = <71000000>;
+				hactive = <1280>;
+				vactive = <800>;
+				hback-porch = <50>;
+				hsync-len = <60>;
+				hfront-porch = <50>;
+				vback-porch = <5>;
+				vsync-len = <13>;
+				vfront-porch = <5>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
 			};
 		};
 	};
 
 	lvds1: lvds-channel@1 {
-		fsl,data-mapping = "jeida";
-		fsl,data-width = <24>;
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
 		status = "okay";
 
 		display-timings {
-			native-mode = <&lvds_timing1>;
-			lvds_timing1: hsd100pxn1 {
+			native-mode = <&lvds1_timing0>;
+
+			lvds1_timing0: hsd100pxn1 {
 				clock-frequency = <65000000>;
 				hactive = <1024>;
 				vactive = <768>;
@@ -227,7 +245,7 @@
 				hsync-active = <0>;
 				vsync-active = <0>;
 				de-active = <1>;
-				pixelclk-active = <0>;
+				pixelclk-active = <1>;
 			};
 		};
 	};
diff --git a/sys/gnu/dts/arm/imx53-tx53.dtsi b/sys/gnu/dts/arm/imx53-tx53.dtsi
index d3e50b22064f..bd3dfefa5778 100644
--- a/sys/gnu/dts/arm/imx53-tx53.dtsi
+++ b/sys/gnu/dts/arm/imx53-tx53.dtsi
@@ -37,7 +37,7 @@
 			compatible = "fixed-clock";
 			reg = <0>;
 			#clock-cells = <0>;
-			clock-frequency = <27000000>;
+			clock-frequency = <26000000>;
 		};
 	};
 
@@ -50,7 +50,7 @@
 			label = "Power Button";
 			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 			linux,code = <116>; /* KEY_POWER */
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/imx6dl-riotboard.dts b/sys/gnu/dts/arm/imx6dl-riotboard.dts
index 5111f5170d53..bfbed52ce1bd 100644
--- a/sys/gnu/dts/arm/imx6dl-riotboard.dts
+++ b/sys/gnu/dts/arm/imx6dl-riotboard.dts
@@ -114,7 +114,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_2p5v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
diff --git a/sys/gnu/dts/arm/imx6dl-tx6dl-comtft.dts b/sys/gnu/dts/arm/imx6dl-tx6dl-comtft.dts
index 913bb9a0466a..063fe7510da5 100644
--- a/sys/gnu/dts/arm/imx6dl-tx6dl-comtft.dts
+++ b/sys/gnu/dts/arm/imx6dl-tx6dl-comtft.dts
@@ -1,12 +1,42 @@
 /*
- * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/sys/gnu/dts/arm/imx6dl-tx6s-8034.dts b/sys/gnu/dts/arm/imx6dl-tx6s-8034.dts
new file mode 100644
index 000000000000..ff8f7b1c4282
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6dl-tx6s-8034.dts
@@ -0,0 +1,237 @@
+/*
+ * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-tx6.dtsi"
+
+/ {
+	model = "Ka-Ro electronics TX6S-8034 Module";
+	compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
+
+	aliases {
+		display = &display;
+		ipu1 = &ipu1;
+	};
+
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd0_pwr>;
+		enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+		power-supply = <&reg_lcd1_pwr>;
+		/*
+		 * a poor man's way to create a 1:1 relationship between
+		 * the PWM value and the actual duty cycle
+		 */
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <50>;
+	};
+
+	display: display@di0 {
+		compatible = "fsl,imx-parallel-display";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_disp0_2>;
+		interface-pix-fmt = "rgb24";
+		status = "okay";
+
+		port {
+			display0_in: endpoint {
+				remote-endpoint = <&ipu1_di0_disp0>;
+			};
+		};
+
+		display-timings {
+			native-mode = <&vga>;
+
+			vga: VGA {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hsync-len = <96>;
+				hfront-porch = <16>;
+				vback-porch = <31>;
+				vsync-len = <2>;
+				vfront-porch = <12>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ETV570 {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <114>;
+				hsync-len = <30>;
+				hfront-porch = <16>;
+				vback-porch = <32>;
+				vsync-len = <3>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0350 {
+				clock-frequency = <6413760>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <34>;
+				hsync-len = <34>;
+				hfront-porch = <20>;
+				vback-porch = <15>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0430 {
+				clock-frequency = <9009000>;
+				hactive = <480>;
+				vactive = <272>;
+				hback-porch = <2>;
+				hsync-len = <41>;
+				hfront-porch = <2>;
+				vback-porch = <2>;
+				vsync-len = <10>;
+				vfront-porch = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			ET0500 {
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0700 { /* same as ET0500 */
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ETQ570 {
+				clock-frequency = <6596040>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <38>;
+				hsync-len = <30>;
+				hfront-porch = <30>;
+				vback-porch = <16>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&ds1339 {
+	status = "disabled";
+};
+
+&pinctrl_usdhc1 {
+	fsl,pins = <
+		MX6QDL_PAD_SD1_CMD__SD1_CMD		0x070b1
+		MX6QDL_PAD_SD1_CLK__SD1_CLK		0x070b1
+		MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x070b1
+		MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x070b1
+		MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x070b1
+		MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x070b1
+		MX6QDL_PAD_SD3_CMD__GPIO7_IO02		0x170b0 /* SD1 CD */
+	>;
+};
+
+&ipu1_di0_disp0 {
+	remote-endpoint = <&display0_in>;
+};
+
+&reg_lcd0_pwr {
+	status = "disabled";
+};
diff --git a/sys/gnu/dts/arm/imx6dl-tx6s-8035.dts b/sys/gnu/dts/arm/imx6dl-tx6s-8035.dts
new file mode 100644
index 000000000000..f988950e9443
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6dl-tx6s-8035.dts
@@ -0,0 +1,253 @@
+/*
+ * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-tx6.dtsi"
+
+/ {
+	model = "Ka-Ro electronics TX6S-8035 Module";
+	compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
+
+	aliases {
+		display = &display;
+		ipu1 = &ipu1;
+	};
+
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd0_pwr>;
+		enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+		power-supply = <&reg_lcd1_pwr>;
+		/*
+		 * a poor man's way to create a 1:1 relationship between
+		 * the PWM value and the actual duty cycle
+		 */
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <50>;
+	};
+
+	display: display@di0 {
+		compatible = "fsl,imx-parallel-display";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_disp0_2>;
+		interface-pix-fmt = "rgb24";
+		status = "okay";
+
+		port {
+			display0_in: endpoint {
+				remote-endpoint = <&ipu1_di0_disp0>;
+			};
+		};
+
+		display-timings {
+			native-mode = <&vga>;
+
+			vga: VGA {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hsync-len = <96>;
+				hfront-porch = <16>;
+				vback-porch = <31>;
+				vsync-len = <2>;
+				vfront-porch = <12>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ETV570 {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <114>;
+				hsync-len = <30>;
+				hfront-porch = <16>;
+				vback-porch = <32>;
+				vsync-len = <3>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0350 {
+				clock-frequency = <6413760>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <34>;
+				hsync-len = <34>;
+				hfront-porch = <20>;
+				vback-porch = <15>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0430 {
+				clock-frequency = <9009000>;
+				hactive = <480>;
+				vactive = <272>;
+				hback-porch = <2>;
+				hsync-len = <41>;
+				hfront-porch = <2>;
+				vback-porch = <2>;
+				vsync-len = <10>;
+				vfront-porch = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			ET0500 {
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0700 { /* same as ET0500 */
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ETQ570 {
+				clock-frequency = <6596040>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <38>;
+				hsync-len = <30>;
+				hfront-porch = <30>;
+				vback-porch = <16>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&ds1339 {
+	status = "disabled";
+};
+
+&gpmi {
+	status = "disabled";
+};
+
+&ipu1_di0_disp0 {
+	remote-endpoint = <&display0_in>;
+};
+
+&reg_lcd0_pwr {
+	status = "disabled";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <4>;
+	non-removable;
+	no-1-8-v;
+	fsl,wp-controller;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x070b1
+			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x070b1
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x070b1
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x070b1
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x070b1
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x070b1
+			MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x0b0b1
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-801x.dts b/sys/gnu/dts/arm/imx6dl-tx6u-801x.dts
index 5fe465c2814e..b7a72840b7f0 100644
--- a/sys/gnu/dts/arm/imx6dl-tx6u-801x.dts
+++ b/sys/gnu/dts/arm/imx6dl-tx6u-801x.dts
@@ -1,12 +1,42 @@
 /*
- * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-8033.dts b/sys/gnu/dts/arm/imx6dl-tx6u-8033.dts
new file mode 100644
index 000000000000..4d3204a56f46
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6dl-tx6u-8033.dts
@@ -0,0 +1,248 @@
+/*
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-tx6.dtsi"
+
+/ {
+	model = "Ka-Ro electronics TX6U-8033 Module";
+	compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
+
+	aliases {
+		display = &display;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd0_pwr>;
+		enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+		power-supply = <&reg_lcd1_pwr>;
+		/*
+		 * a poor man's way to create a 1:1 relationship between
+		 * the PWM value and the actual duty cycle
+		 */
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <50>;
+	};
+
+	display: display@di0 {
+		compatible = "fsl,imx-parallel-display";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_disp0_2>;
+		interface-pix-fmt = "rgb24";
+		status = "okay";
+
+		port {
+			display0_in: endpoint {
+				remote-endpoint = <&ipu1_di0_disp0>;
+			};
+		};
+
+		display-timings {
+			native-mode = <&vga>;
+
+			vga: VGA {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hsync-len = <96>;
+				hfront-porch = <16>;
+				vback-porch = <31>;
+				vsync-len = <2>;
+				vfront-porch = <12>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ETV570 {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <114>;
+				hsync-len = <30>;
+				hfront-porch = <16>;
+				vback-porch = <32>;
+				vsync-len = <3>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0350 {
+				clock-frequency = <6413760>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <34>;
+				hsync-len = <34>;
+				hfront-porch = <20>;
+				vback-porch = <15>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0430 {
+				clock-frequency = <9009000>;
+				hactive = <480>;
+				vactive = <272>;
+				hback-porch = <2>;
+				hsync-len = <41>;
+				hfront-porch = <2>;
+				vback-porch = <2>;
+				vsync-len = <10>;
+				vfront-porch = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			ET0500 {
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0700 { /* same as ET0500 */
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ETQ570 {
+				clock-frequency = <6596040>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <38>;
+				hsync-len = <30>;
+				hfront-porch = <30>;
+				vback-porch = <16>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&ds1339 {
+	status = "disabled";
+};
+
+&gpmi {
+	status = "disabled";
+};
+
+&ipu1_di0_disp0 {
+	remote-endpoint = <&display0_in>;
+};
+
+&reg_lcd0_pwr {
+	status = "disabled";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <4>;
+	non-removable;
+	no-1-8-v;
+	fsl,wp-controller;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x070b1
+			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x070b1
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x070b1
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x070b1
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x070b1
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x070b1
+			MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x0b0b1
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-811x.dts b/sys/gnu/dts/arm/imx6dl-tx6u-811x.dts
index c275eecc9472..5e0c6bb49f37 100644
--- a/sys/gnu/dts/arm/imx6dl-tx6u-811x.dts
+++ b/sys/gnu/dts/arm/imx6dl-tx6u-811x.dts
@@ -1,12 +1,42 @@
 /*
- * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -77,17 +107,7 @@
 		interrupt-parent = <&gpio3>;
 		interrupts = <22 0>;
 		wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
-		linux,wakeup;
-	};
-};
-
-&iomuxc {
-	imx6dl-tx6u-811x {
-		pinctrl_eeti: eetigrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
-			>;
-		};
+		wakeup-source;
 	};
 };
 
@@ -148,3 +168,11 @@
 &pwm1 {
 	status = "okay";
 };
+
+&iomuxc {
+	pinctrl_eeti: eetigrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6dl-tx6u-81xx-mb7.dts b/sys/gnu/dts/arm/imx6dl-tx6u-81xx-mb7.dts
new file mode 100644
index 000000000000..b9a783f7160e
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6dl-tx6u-81xx-mb7.dts
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-tx6.dtsi"
+
+/ {
+	model = "Ka-Ro electronics TX6U-81xx Module on MB7 baseboard";
+	compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
+
+	aliases {
+		display = &lvds0;
+		lvds0 = &lvds0;
+		lvds1 = &lvds1;
+	};
+
+	backlight0: backlight0 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
+		power-supply = <&reg_lcd0_pwr>;
+		/*
+		 * a poor man's way to create a 1:1 relationship between
+		 * the PWM value and the actual duty cycle
+		 */
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <50>;
+	};
+
+	backlight1: backlight1 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
+		power-supply = <&reg_lcd1_pwr>;
+		/*
+		 * a poor man's way to create a 1:1 relationship between
+		 * the PWM value and the actual duty cycle
+		 */
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <50>;
+	};
+};
+
+&can1 {
+	status = "disabled";
+};
+
+&can2 {
+	xceiver-supply = <&reg_3v3>;
+};
+
+&i2c3 {
+	polytouch1: eeti@04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_eeti>;
+		interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>;
+		wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+		wakeup-source;
+	};
+};
+
+&kpp {
+	status = "disabled"; /* pads partially clash with backlight1 PWM */
+};
+
+&ldb {
+	status = "okay";
+
+	lvds0: lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&lvds0_timing1>;
+
+			lvds0_timing0: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			lvds0_timing1: VGA {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hfront-porch = <16>;
+				vback-porch = <31>;
+				vfront-porch = <12>;
+				hsync-len = <96>;
+				vsync-len = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			lvds0_timing2: nl12880bc20 {
+				clock-frequency = <71000000>;
+				hactive = <1280>;
+				vactive = <800>;
+				hback-porch = <50>;
+				hfront-porch = <50>;
+				vback-porch = <5>;
+				vfront-porch = <5>;
+				hsync-len = <60>;
+				vsync-len = <13>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+		};
+	};
+
+	lvds1: lvds-channel@1 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&lvds1_timing2>;
+
+			lvds1_timing0: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			lvds1_timing1: VGA {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hfront-porch = <16>;
+				vback-porch = <31>;
+				vfront-porch = <12>;
+				hsync-len = <96>;
+				vsync-len = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			lvds1_timing2: nl12880bc20 {
+				clock-frequency = <71000000>;
+				hactive = <1280>;
+				vactive = <800>;
+				hback-porch = <50>;
+				hfront-porch = <50>;
+				vback-porch = <5>;
+				vfront-porch = <5>;
+				hsync-len = <60>;
+				vsync-len = <13>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_eeti: eetigrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts b/sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts
index f607d4f1d244..8c314eee4fdd 100644
--- a/sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts
+++ b/sys/gnu/dts/arm/imx6dl-wandboard-revb1.dts
@@ -13,7 +13,7 @@
 #include "imx6qdl-wandboard-revb1.dtsi"
 
 / {
-	model = "Wandboard i.MX6 Dual Lite Board";
+	model = "Wandboard i.MX6 Dual Lite Board rev B1";
 	compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
 
 	memory {
diff --git a/sys/gnu/dts/arm/imx6dl.dtsi b/sys/gnu/dts/arm/imx6dl.dtsi
index c13a73aa55ca..9a4c22c2dade 100644
--- a/sys/gnu/dts/arm/imx6dl.dtsi
+++ b/sys/gnu/dts/arm/imx6dl.dtsi
@@ -30,7 +30,7 @@
 				/* kHz    uV */
 				996000  1250000
 				792000  1175000
-				396000  1075000
+				396000  1150000
 			>;
 			fsl,soc-operating-points = <
 				/* ARM kHz  SOC-PU uV */
diff --git a/sys/gnu/dts/arm/imx6q-apalis-ixora.dts b/sys/gnu/dts/arm/imx6q-apalis-ixora.dts
new file mode 100644
index 000000000000..8e67ca27ad79
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-apalis-ixora.dts
@@ -0,0 +1,318 @@
+/*
+ * Copyright 2014-2016 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-apalis.dtsi"
+
+/ {
+	model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board";
+	compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
+		     "fsl,imx6q";
+
+	aliases {
+		i2c0 = &i2cddc;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+	};
+
+	aliases {
+		rtc0 = &rtc_i2c;
+		rtc1 = &snvs_rtc;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+
+		wakeup {
+			label = "Wake-Up";
+			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WAKEUP>;
+			debounce-interval = <10>;
+			wakeup-source;
+		};
+	};
+
+	lcd_display: display@di0 {
+		compatible = "fsl,imx-parallel-display";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interface-pix-fmt = "rgb24";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+		status = "okay";
+
+		port@0 {
+			reg = <0>;
+
+			lcd_display_in: endpoint {
+				remote-endpoint = <&ipu1_di0_disp1>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			lcd_display_out: endpoint {
+				remote-endpoint = <&lcd_panel_in>;
+			};
+		};
+	};
+
+	panel: panel {
+		/*
+		 * edt,et057090dhu: EDT 5.7" LCD TFT
+		 * edt,et070080dh6: EDT 7.0" LCD TFT
+		 */
+		compatible = "edt,et057090dhu";
+		backlight = <&backlight>;
+
+		port {
+			lcd_panel_in: endpoint {
+				remote-endpoint = <&lcd_display_out>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_leds_ixora>;
+
+		led4-green {
+			label = "LED_4_GREEN";
+			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+		};
+
+		led4-red {
+			label = "LED_4_RED";
+			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+		};
+
+		led5-green {
+			label = "LED_5_GREEN";
+			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		led5-red {
+			label = "LED_5_RED";
+			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		ledpwm1 {
+			label = "PWM1";
+			pwms = <&pwm1 0 50000>;
+			max-brightness = <255>;
+		};
+
+		ledpwm2 {
+			label = "PWM2";
+			pwms = <&pwm2 0 50000>;
+			max-brightness = <255>;
+		};
+
+		ledpwm3 {
+			label = "PWM3";
+			pwms = <&pwm3 0 50000>;
+			max-brightness = <255>;
+		};
+	};
+};
+
+&backlight {
+	brightness-levels = <0 127 191 223 239 247 251 255>;
+	default-brightness-level = <1>;
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&can2 {
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2cddc>;
+	status = "okay";
+};
+
+&i2cddc {
+	status = "okay";
+};
+
+/* GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
+&i2c1 {
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+	};
+
+	/* M41T0M6 real time clock on carrier board */
+	rtc_i2c: rtc@68 {
+		compatible = "st,m41t00";
+		reg = <0x68>;
+	};
+};
+
+&ipu1_di0_disp1 {
+	remote-endpoint = <&lcd_display_in>;
+};
+
+&ldb {
+	status = "okay";
+};
+
+&pcie {
+	/* active-high meaning opposite of regular PERST# active-low polarity */
+	reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+	reset-gpio-active-high;
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&pwm3 {
+	status = "okay";
+};
+
+&pwm4 {
+	status = "okay";
+};
+
+&reg_usb_otg_vbus {
+	status = "okay";
+};
+
+&reg_usb_host_vbus {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&sound_spdif {
+	status = "okay";
+};
+
+&spdif {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usb_host_vbus>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	status = "okay";
+};
+
+/* SD1 */
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sd_cd>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&iomuxc {
+	/*
+	 * Mux the Apalis GPIOs
+	 * GPIO5, 6 used by optional fusion_F0710A kernel module
+	 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
+		     &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
+		     &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
+		     &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
+		    >;
+
+	pinctrl_leds_ixora: ledsixoragrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
+			MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0
+			MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+			MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-b450v3.dts b/sys/gnu/dts/arm/imx6q-b450v3.dts
new file mode 100644
index 000000000000..f0a2be5268e3
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-b450v3.dts
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+	model = "General Electric B450v3";
+	compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+	chosen {
+		stdout-path = &uart3;
+	};
+
+	panel-lvds0 {
+		compatible = "innolux,g121x1-l03";
+		backlight = <&backlight_lvds>;
+		power-supply = <&reg_lvds>;
+
+		port {
+			panel_in_lvds0: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ldb {
+	status = "okay";
+
+	lvds0: lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <24>;
+		status = "okay";
+
+		port@4 {
+			reg = <4>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&panel_in_lvds0>;
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-b650v3.dts b/sys/gnu/dts/arm/imx6q-b650v3.dts
new file mode 100644
index 000000000000..33cb71acadcc
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-b650v3.dts
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+	model = "General Electric B650v3";
+	compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+	chosen {
+		stdout-path = &uart3;
+	};
+
+	panel-lvds0 {
+		compatible = "innolux,g121x1-l03";
+		backlight = <&backlight_lvds>;
+		power-supply = <&reg_lvds>;
+
+		port {
+			panel_in_lvds0: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ldb {
+	status = "okay";
+
+	lvds0: lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <24>;
+		status = "okay";
+
+		port@4 {
+			reg = <4>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&panel_in_lvds0>;
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-b850v3.dts b/sys/gnu/dts/arm/imx6q-b850v3.dts
new file mode 100644
index 000000000000..167f7446722a
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-b850v3.dts
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+	model = "General Electric B850v3";
+	compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+	chosen {
+		stdout-path = &uart3;
+	};
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+			  <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
+};
+
+&ldb {
+	fsl,dual-channel;
+	status = "okay";
+
+	lvds0: lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <24>;
+		status = "okay";
+	};
+};
+
+&i2c2 {
+	pca9547_ddc: mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mux2_i2c1: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+		};
+
+		mux2_i2c2: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1>;
+		};
+
+		mux2_i2c3: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+		};
+
+		mux2_i2c4: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+		};
+
+		mux2_i2c5: i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+
+		mux2_i2c6: i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x5>;
+		};
+
+		mux2_i2c7: i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x6>;
+		};
+
+		mux2_i2c8: i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x7>;
+		};
+	};
+};
+
+&hdmi {
+	ddc-i2c-bus = <&mux2_i2c1>;
+};
+
+&mux1_i2c1 {
+	ads7830@4a {
+		compatible = "ti,ads7830";
+		reg = <0x4a>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-ba16.dtsi b/sys/gnu/dts/arm/imx6q-ba16.dtsi
new file mode 100644
index 000000000000..f7e17e2004ac
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-ba16.dtsi
@@ -0,0 +1,634 @@
+/*
+ * Support for imx6 based Advantech DMS-BA16 Qseven module
+ *
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	backlight_lvds: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_display>;
+		pwms = <&pwm1 0 5000000>;
+		brightness-levels = <  0   1   2   3   4   5   6   7   8   9
+				      10  11  12  13  14  15  16  17  18  19
+				      20  21  22  23  24  25  26  27  28  29
+				      30  31  32  33  34  35  36  37  38  39
+				      40  41  42  43  44  45  46  47  48  49
+				      50  51  52  53  54  55  56  57  58  59
+				      60  61  62  63  64  65  66  67  68  69
+				      70  71  72  73  74  75  76  77  78  79
+				      80  81  82  83  84  85  86  87  88  89
+				      90  91  92  93  94  95  96  97  98  99
+				     100 101 102 103 104 105 106 107 108 109
+				     110 111 112 113 114 115 116 117 118 119
+				     120 121 122 123 124 125 126 127 128 129
+				     130 131 132 133 134 135 136 137 138 139
+				     140 141 142 143 144 145 146 147 148 149
+				     150 151 152 153 154 155 156 157 158 159
+				     160 161 162 163 164 165 166 167 168 169
+				     170 171 172 173 174 175 176 177 178 179
+				     180 181 182 183 184 185 186 187 188 189
+				     190 191 192 193 194 195 196 197 198 199
+				     200 201 202 203 204 205 206 207 208 209
+				     210 211 212 213 214 215 216 217 218 219
+				     220 221 222 223 224 225 226 227 228 229
+				     230 231 232 233 234 235 236 237 238 239
+				     240 241 242 243 244 245 246 247 248 249
+				     250 251 252 253 254 255>;
+		default-brightness-level = <255>;
+		enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "1P8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_lvds: regulator-lvds {
+		compatible = "regulator-fixed";
+		regulator-name = "lvds_ppen";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usb_h1_vbus: regulator-usbh1vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_h1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_usb_otg_vbus: regulator-usbotgvbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "okay";
+
+	flash: n25q032@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+
+		partition@0 {
+			label = "U-Boot";
+			reg = <0x0 0xc0000>;
+		};
+
+		partition@c0000 {
+			label = "env";
+			reg = <0xc0000 0x10000>;
+		};
+
+		partition@d0000 {
+			label = "spare";
+			reg = <0xd0000 0x130000>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	pmic@58 {
+		compatible = "dlg,da9063";
+		reg = <0x58>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio7>;
+		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
+		onkey {
+			compatible = "dlg,da9063-onkey";
+		};
+
+		regulators {
+			vdd_bcore1: bcore1 {
+				regulator-min-microvolt = <1420000>;
+				regulator-max-microvolt = <1420000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd_bcore2: bcore2 {
+				regulator-min-microvolt = <1420000>;
+				regulator-max-microvolt = <1420000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd_bpro: bpro {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd_bmem: bmem {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd_bio: bio {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd_bperi: bperi {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vdd_ldo1: ldo1 {
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1860000>;
+			};
+
+			vdd_ldo2: ldo2 {
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1860000>;
+			};
+
+			vdd_ldo3: ldo3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3440000>;
+			};
+
+			vdd_ldo4: ldo4 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3440000>;
+			};
+
+			vdd_ldo5: ldo5 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+
+			vdd_ldo6: ldo6 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+
+			vdd_ldo7: ldo7 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+
+			vdd_ldo8: ldo8 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+
+			vdd_ldo9: ldo9 {
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <3600000>;
+			};
+
+			vdd_ldo10: ldo10 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+
+			vdd_ldo11: ldo11 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+		};
+	};
+
+	rtc@32 {
+		compatible = "epson,rx8010";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_rtc>;
+		reg = <0x32>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+	fsl,tx-swing-full = <103>;
+	fsl,tx-swing-low = <103>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "disabled";
+};
+
+&sata {
+	status = "okay";
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usbh1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbhub>;
+	vbus-supply = <&reg_usb_h1_vbus>;
+	reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
+	bus-width = <8>;
+	vmmc-supply = <&vdd_bperi>;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
+			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x130b0
+			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
+		>;
+	};
+
+	pinctrl_display: dispgrp {
+		fsl,pins = <
+			/* BLEN_OUT */
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00    0x1b0b0
+			/* LVDS_PPEN_OUT */
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22   0x1b0b0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__ECSPI1_MISO	0x100b1
+			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI	0x100b1
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK	0x100b1
+			/* SPI1 CS */
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30	0x1b0b0
+		>;
+	};
+
+	pinctrl_ecspi5: ecspi5grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO	0x1b0b0
+			MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI		0x1b0b0
+			MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK		0x1b0b0
+			MX6QDL_PAD_SD1_DAT1__GPIO1_IO17		0x1b0b0
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x100b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x100b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x100b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x100b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x100b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x100b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x100b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+			/* FEC Reset */
+			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28     0x1b0b0
+			/* AR8033 Interrupt */
+			MX6QDL_PAD_GPIO_19__GPIO4_IO05        0x1b0b0
+		>;
+	};
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			/* GPIO 0-7 */
+			MX6QDL_PAD_NANDF_D0__GPIO2_IO00  0x1b0b0
+			MX6QDL_PAD_NANDF_D1__GPIO2_IO01  0x1b0b0
+			MX6QDL_PAD_NANDF_D2__GPIO2_IO02  0x1b0b0
+			MX6QDL_PAD_NANDF_D3__GPIO2_IO03  0x1b0b0
+			MX6QDL_PAD_NANDF_D4__GPIO2_IO04  0x1b0b0
+			MX6QDL_PAD_NANDF_D5__GPIO2_IO05  0x1b0b0
+			MX6QDL_PAD_NANDF_D6__GPIO2_IO06  0x1b0b0
+			MX6QDL_PAD_NANDF_D7__GPIO2_IO07  0x1b0b0
+			/* SUS_S3_OUT to CPLD */
+			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11  0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA	0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL	0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL	0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			/* PCIe Reset */
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
+			/* PCIe Wake */
+			MX6QDL_PAD_GPIO_5__GPIO1_IO05	0x1b0b0
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			/* PMIC Interrupt */
+			MX6QDL_PAD_GPIO_18__GPIO7_IO13	0x1b0b0
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT3__PWM1_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__PWM2_OUT	0x1b0b1
+		>;
+	};
+
+	pinctrl_rtc: rtcgrp {
+		fsl,pins = <
+			/* RTC_INT */
+			MX6QDL_PAD_KEY_COL2__GPIO4_IO10	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+			MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+			MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
+			MX6QDL_PAD_EIM_D31__UART3_RTS_B   0x1b0b1
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+		>;
+	};
+
+	pinctrl_usbhub: usbhubgrp {
+		fsl,pins = <
+			/* HUB_RESET */
+			MX6QDL_PAD_GPIO_16__GPIO7_IO11	0x1b0b0
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD	0x17059
+			MX6QDL_PAD_SD2_CLK__SD2_CLK	0x10059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0	0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1	0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2	0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3	0x17059
+			/* uSDHC2 CD */
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04	0x1b0b0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
+		>;
+	};
+
+	pinctrl_usdhc3_reset: usdhc3grp-reset {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_RST__SD3_RESET   0x170F9
+		>;
+	};
+
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD	0x17059
+			MX6QDL_PAD_SD4_CLK__SD4_CLK	0x17059
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0	0x17059
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1	0x17059
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2	0x17059
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3	0x17059
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4	0x17059
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5	0x17059
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6	0x17059
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7	0x17059
+			/* uSDHC4 CD */
+			MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
+			/* uSDHC4 SDIO PWR */
+			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
+			/* uSDHC4 SDIO WP */
+			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
+			/* uSDHC4 SDIO LED */
+			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_9__WDOG1_B	0x1b0b0
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-bx50v3.dtsi b/sys/gnu/dts/arm/imx6q-bx50v3.dtsi
new file mode 100644
index 000000000000..bb66dfd5294c
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-bx50v3.dtsi
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6q-ba16.dtsi"
+
+/ {
+	clocks {
+		mclk: clock@0 {
+			compatible = "fixed-clock";
+			reg = <0>;
+			#clock-cells = <0>;
+			clock-frequency = <22000000>;
+		};
+	};
+
+	reg_wl18xx_vmmc: regulator-wl18xx {
+		compatible = "regulator-fixed";
+		regulator-name = "vwl1807";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	reg_wlan: regulator-wlan {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V_wlan";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>;
+	};
+
+	sound {
+		compatible = "fsl,imx6q-ba16-sgtl5000",
+			     "fsl,imx-audio-sgtl5000";
+		model = "imx6q-ba16-sgtl5000";
+		ssi-controller = <&ssi1>;
+		audio-codec = <&sgtl5000>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"LINE_IN", "Line In Jack",
+			"Headphone Jack", "HP_OUT";
+		mux-int-port = <1>;
+		mux-ext-port = <4>;
+	};
+};
+
+&ecspi5 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi5>;
+	status = "okay";
+
+	m25_eeprom: m25p80@0 {
+		compatible = "atmel,at25";
+		spi-max-frequency = <20000000>;
+		size = <0x8000>;
+		pagesize = <64>;
+		reg = <0>;
+		address-width = <16>;
+	};
+};
+
+&i2c1 {
+	pca9547: mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mux1_i2c1: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			ads7830: ads7830@48 {
+				compatible = "ti,ads7830";
+				reg = <0x48>;
+			};
+
+			mma8453: mma8453@1c {
+				compatible = "fsl,mma8453";
+				reg = <0x1c>;
+			};
+		};
+
+		mux1_i2c2: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1>;
+
+			eeprom: eeprom@50 {
+				compatible = "atmel,24c08";
+				reg = <0x50>;
+			};
+
+			mpl3115: mpl3115@60 {
+				compatible = "fsl,mpl3115";
+				reg = <0x60>;
+			};
+		};
+
+		mux1_i2c3: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+		};
+
+		mux1_i2c4: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			sgtl5000: codec@0a {
+				compatible = "fsl,sgtl5000";
+				reg = <0x0a>;
+				clocks = <&mclk>;
+				VDDA-supply = <&reg_1p8v>;
+				VDDIO-supply = <&reg_3p3v>;
+			};
+		};
+
+		mux1_i2c5: i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+
+			pca9539: pca9539@74 {
+				compatible = "nxp,pca9539";
+				reg = <0x74>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				interrupt-parent = <&gpio2>;
+				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+			};
+		};
+
+		mux1_i2c6: i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x5>;
+		};
+
+		mux1_i2c7: i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x6>;
+		};
+
+		mux1_i2c8: i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x7>;
+		};
+	};
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_wl18xx_vmmc>;
+	no-1-8-v;
+	non-removable;
+	wakeup-source;
+	keep-power-in-suspend;
+	cap-power-off-card;
+	max-frequency = <25000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1837";
+		reg = <2>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+		tcxo-clock-frequency = <26000000>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-evi.dts b/sys/gnu/dts/arm/imx6q-evi.dts
new file mode 100644
index 000000000000..4fa56019225e
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-evi.dts
@@ -0,0 +1,502 @@
+/*
+ * Copyright 2016 United Western Technologies.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "Uniwest Evi";
+	compatible = "uniwest,imx6q-evi", "fsl,imx6q";
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	reg_usbh1_vbus: regulator-usbhubreset {
+		compatible = "regulator-fixed";
+		regulator-name = "usbh1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		startup-delay-us = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh1_hubreset>;
+		gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_usb_otg_vbus: regulator-usbotgvbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbotgvbus>;
+		gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	panel {
+		compatible = "sharp,lq101k1ly04";
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
+	status = "okay";
+};
+
+&ecspi3 {
+	fsl,spi-num-chipselects = <3>;
+	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>,
+		<&gpio4 25 GPIO_ACTIVE_LOW>,
+		<&gpio4 26 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3cs>;
+	status = "okay";
+};
+
+&ecspi5 {
+	fsl,spi-num-chipselects = <4>;
+	cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
+		<&gpio1 13 GPIO_ACTIVE_LOW>,
+		<&gpio1 12 GPIO_ACTIVE_LOW>,
+		<&gpio2 9 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>;
+	status = "okay";
+
+	eeprom: m95m02@1 {
+		compatible = "st,m95m02", "atmel,at25";
+		size = <262144>;
+		pagesize = <256>;
+		address-width = <24>;
+		spi-max-frequency = <5000000>;
+		reg = <1>;
+	};
+
+	pb_rtc: rtc@3 {
+		compatible = "nxp,rtc-pcf2123";
+		spi-max-frequency = <2450000>;
+		spi-cs-high;
+		reg = <3>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio1 25 0>;
+	status = "okay";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpminand>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c3 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	clock-frequency = <100000>;
+	scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	battery: sbs-battery@b {
+		compatible = "sbs,sbs-battery";
+		reg = <0x0b>;
+		sbs,poll-retry-count = <100>;
+		sbs,i2c-retry-count = <100>;
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	lvds0: lvds-channel@0 {
+		status = "okay";
+
+		port@4 {
+			reg = <4>;
+			lvds0_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usbh1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbh1>;
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	non-removable;
+	status = "okay";
+};
+
+&weim {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x08000000 0x08000000>;
+	fsl,weim-cs-gpr = <&gpr>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			/* pwr mcu alert irq */
+			MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
+			/* remainder ???? */
+			MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+			MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+			MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+		>;
+	};
+
+	pinctrl_ecspi1cs: ecspi1csgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+		>;
+	};
+
+	pinctrl_ecspi3: ecspi3grp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x10068
+			MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x10068
+			MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1f068
+		>;
+	};
+
+	pinctrl_ecspi3cs: ecspi3csgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
+			MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0
+			MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0
+			MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
+		>;
+	};
+
+	pinctrl_ecspi5: ecspi5grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x100b1
+			MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1
+			MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1
+		>;
+	};
+
+	pinctrl_ecspi5cs: ecspi5csgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
+			MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
+			MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
+			MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+		>;
+	};
+
+	pinctrl_gpminand: gpminandgrp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+			MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+			MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+			MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+			MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+			MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+			MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+			MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+			MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+			MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+			MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+			MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+			MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+			MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+			MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1
+			MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1
+		>;
+	};
+
+	pinctrl_weimcs: weimcsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+			MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
+		>;
+	};
+
+	pinctrl_weimfpga: weimfpgagrp {
+		fsl,pins = <
+			/* weim misc */
+			MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+			MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+			MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+			MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0b1
+			MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0b1
+			MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0xb0b1
+			MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0xb0b1
+			MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0xb0b1
+			MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0xb0b1
+			/* weim data */
+			MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
+			MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
+			MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
+			MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+			MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+			MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+			MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+			MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+			MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+			MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+			MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+			MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+			MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+			MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+			MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+			MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+			MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+			MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+			MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+			/* weim address */
+			MX6QDL_PAD_EIM_A25__EIM_ADDR25 0xb0b1
+			MX6QDL_PAD_EIM_A24__EIM_ADDR24 0xb0b1
+			MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+			MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+			MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+			MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+			MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+			MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+			MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+			MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+			MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+			MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+			MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+			MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+			MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+			MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+			MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+			MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+			MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+			MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+			MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+			MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+			MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+			MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+			MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+			MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
+			MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
+			MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1
+			MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1
+		>;
+	};
+
+	pinctrl_usbh1: usbh1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0
+			/* usbh1_b OC */
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+		>;
+	};
+
+	pinctrl_usbh1_hubreset: usbh1hubresetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+			MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
+		>;
+	};
+
+	pinctrl_usbotgvbus: usbotgvbusgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+			MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-gk802.dts b/sys/gnu/dts/arm/imx6q-gk802.dts
index 00bd63e63d0c..b715deb4ea46 100644
--- a/sys/gnu/dts/arm/imx6q-gk802.dts
+++ b/sys/gnu/dts/arm/imx6q-gk802.dts
@@ -44,7 +44,7 @@
 			label = "recovery";
 			gpios = <&gpio3 16 1>;
 			linux,code = <0x198>; /* KEY_RESTART */
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 };
diff --git a/sys/gnu/dts/arm/imx6q-gw5400-a.dts b/sys/gnu/dts/arm/imx6q-gw5400-a.dts
index a51834e1dd27..0511137d1e23 100644
--- a/sys/gnu/dts/arm/imx6q-gw5400-a.dts
+++ b/sys/gnu/dts/arm/imx6q-gw5400-a.dts
@@ -327,7 +327,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&sw4_reg>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
diff --git a/sys/gnu/dts/arm/imx6q-icore-rqs.dts b/sys/gnu/dts/arm/imx6q-icore-rqs.dts
new file mode 100644
index 000000000000..005318865f66
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-icore-rqs.dts
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2015 Amarula Solutions B.V.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore-rqs.dtsi"
+
+/ {
+	model = "Engicam i.CoreM6 Quad SOM";
+	compatible = "engicam,imx6-icore-rqs", "fsl,imx6q";
+
+	sound {
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "imx-audio-sgtl5000";
+		ssi-controller = <&ssi1>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+		mux-int-port = <1>;
+		mux-ext-port = <4>;
+	};
+};
+
+&i2c3 {
+	codec: sgtl5000@0a {
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		VDDA-supply = <&reg_2p5v>;
+		VDDIO-supply = <&reg_3p3v>;
+		VDDD-supply = <&reg_1p8v>;
+	};
+};
+
+&sata {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/imx6q-marsboard.dts b/sys/gnu/dts/arm/imx6q-marsboard.dts
new file mode 100644
index 000000000000..3f8013c85fb9
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-marsboard.dts
@@ -0,0 +1,403 @@
+/*
+ * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com)
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Embest MarS Board i.MX6Dual";
+	compatible = "embest,imx6q-marsboard", "fsl,imx6q";
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_led>;
+
+		user1 {
+			label = "imx6:green:user1";
+			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "heartbeat";
+		};
+
+		user2 {
+			label = "imx6:green:user2";
+			gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+	fsl,spi-num-chipselects = <1>;
+	status = "okay";
+
+	m25p80@0 {
+		compatible = "microchip,sst25vf016b";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>;
+	status = "okay";
+};
+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	status = "okay";
+};
+
+&usbh1 {
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	dr_mode = "otg";
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	vmmc-supply = <&reg_3p3v>;
+	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	vmmc-supply = <&reg_3p3v>;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
+			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
+			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
+			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
+			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0	/* CAM_MCLK */
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
+			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
+			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x000b1	/* CS0 */
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0a0b1
+			/* AR8035 pin strapping: IO voltage: pull up */
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+			/* AR8035 pin strapping: PHYADDR#0: pull down */
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x130b0
+			/* AR8035 pin strapping: PHYADDR#1: pull down */
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x130b0
+			/* AR8035 pin strapping: MODE#1: pull up */
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
+			/* AR8035 pin strapping: MODE#3: pull up */
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
+			/* AR8035 pin strapping: MODE#0: pull down */
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x130b0
+			/* GPIO16 -> AR8035 25MHz */
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+			/* RGMII_nRST */
+			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x130b0
+			/* AR8035 interrupt */
+			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x180b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_led: ledgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b1	/* LED1 */
+			MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x1b0b1	/* LED2 */
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT8__PWM1_OUT		0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT9__PWM2_OUT		0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm4: pwm4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
+			MX6QDL_PAD_EIM_D21__USB_OTG_OC		0x1b0b0
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x000b0	/* USB OTG POWER ENABLE */
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1f0b0	/* WP */
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17009
+			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10009
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17009
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17009
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17009
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17009
+			MX6QDL_PAD_SD3_RST__SD3_RESET		0x17009
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-tbs2910.dts b/sys/gnu/dts/arm/imx6q-tbs2910.dts
index 5645d52850a7..1926b1348a62 100644
--- a/sys/gnu/dts/arm/imx6q-tbs2910.dts
+++ b/sys/gnu/dts/arm/imx6q-tbs2910.dts
@@ -91,34 +91,25 @@
 		};
 	};
 
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		reg_2p5v: regulator@0 {
-			compatible = "regulator-fixed";
-			reg = <0>;
-			regulator-name = "2P5V";
-			regulator-min-microvolt = <2500000>;
-			regulator-max-microvolt = <2500000>;
-		};
+	reg_2p5v: regulator-2p5v {
+		compatible = "regulator-fixed";
+		regulator-name = "2P5V";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+	};
 
-		reg_3p3v: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "3P3V";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-		};
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
 
-		reg_5p0v: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <2>;
-			regulator-name = "5P0V";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-		};
+	reg_5p0v: regulator-5p0v {
+		compatible = "regulator-fixed";
+		regulator-name = "5P0V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
 	};
 
 	sound-sgtl5000 {
@@ -150,7 +141,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
@@ -168,7 +159,7 @@
 	status = "okay";
 
 	sgtl5000: sgtl5000@0a {
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		compatible = "fsl,sgtl5000";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_sgtl5000>;
@@ -205,6 +196,10 @@
 };
 
 &sata {
+	fsl,transmit-level-mV = <1104>;
+	fsl,transmit-boost-mdB = <3330>;
+	fsl,transmit-atten-16ths = <16>;
+	fsl,receive-eq-mdB = <3000>;
 	status = "okay";
 };
 
@@ -253,6 +248,9 @@
 	bus-width = <4>;
 	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	voltage-ranges = <3300 3300>;
+	no-1-8-v;
 	status = "okay";
 };
 
@@ -263,6 +261,9 @@
 	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	voltage-ranges = <3300 3300>;
+	no-1-8-v;
 	status = "okay";
 };
 
@@ -270,163 +271,160 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc4>;
 	bus-width = <8>;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	voltage-ranges = <3300 3300>;
 	non-removable;
 	no-1-8-v;
 	status = "okay";
 };
 
 &iomuxc {
-	imx6q-tbs2910 {
-		pinctrl_enet: enetgrp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
-				MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-				MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-				MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-				MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-				MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-				MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-				MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-				MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-				MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-				MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-				MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
-				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
-			>;
-		};
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
+		>;
+	};
 
-		pinctrl_hdmi: hdmigrp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
-			>;
-		};
+	pinctrl_gpio_fan: gpiofangrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D28__GPIO3_IO28        0x130b1
+		>;
+	};
 
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL        0x4001b8b1
-				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA        0x4001b8b1
-			>;
-		};
+	pinctrl_gpio_leds: gpioledsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02         0x130b1
+		>;
+	};
 
-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_COL3__I2C2_SCL         0x4001b8b1
-				MX6QDL_PAD_KEY_ROW3__I2C2_SDA         0x4001b8b1
-			>;
-		};
+	pinctrl_hdmi: hdmigrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+		>;
+	};
 
-		pinctrl_i2c3: i2c3grp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_3__I2C3_SCL           0x4001b8b1
-				MX6QDL_PAD_GPIO_6__I2C3_SDA           0x4001b8b1
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL        0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA        0x4001b8b1
+		>;
+	};
 
-		pinctrl_ir: irgrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D18__GPIO3_IO18        0x17059
-			>;
-		};
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL         0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA         0x4001b8b1
+		>;
+	};
 
-		pinctrl_pcie: pciegrp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_17__GPIO7_IO12        0x17059
-			>;
-		};
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL           0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA           0x4001b8b1
+		>;
+	};
 
-		pinctrl_sgtl5000: sgtl5000grp {
-			fsl,pins = <
-				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD        0x130b0
-				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC        0x130b0
-				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD        0x110b0
-				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS       0x130b0
-				MX6QDL_PAD_GPIO_0__CCM_CLKO1          0x130b0
-			>;
-		};
+	pinctrl_ir: irgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D18__GPIO3_IO18        0x17059
+		>;
+	};
 
-		pinctrl_spdif: spdifgrp {
-			fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT     0x13091
-			>;
-		};
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12        0x17059
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA  0x1b0b1
-				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA  0x1b0b1
-			>;
-		};
+	pinctrl_sgtl5000: sgtl5000grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD        0x130b0
+			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC        0x130b0
+			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD        0x110b0
+			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS       0x130b0
+			MX6QDL_PAD_GPIO_0__CCM_CLKO1          0x130b0
+		>;
+	};
 
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D26__UART2_TX_DATA     0x1b0b1
-				MX6QDL_PAD_EIM_D27__UART2_RX_DATA     0x1b0b1
-			>;
-		};
+	pinctrl_spdif: spdifgrp {
+		fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT     0x13091
+		>;
+	};
 
-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID     0x17059
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA  0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA  0x1b0b1
+		>;
+	};
 
-		pinctrl_usdhc2: usdhc2grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD2_CMD__SD2_CMD           0x17059
-				MX6QDL_PAD_SD2_CLK__SD2_CLK           0x10059
-				MX6QDL_PAD_SD2_DAT0__SD2_DATA0        0x17059
-				MX6QDL_PAD_SD2_DAT1__SD2_DATA1        0x17059
-				MX6QDL_PAD_SD2_DAT2__SD2_DATA2        0x17059
-				MX6QDL_PAD_SD2_DAT3__SD2_DATA3        0x17059
-				MX6QDL_PAD_NANDF_D2__GPIO2_IO02       0x17059
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__UART2_TX_DATA     0x1b0b1
+			MX6QDL_PAD_EIM_D27__UART2_RX_DATA     0x1b0b1
+		>;
+	};
 
-		pinctrl_usdhc3: usdhc3grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD3_CMD__SD3_CMD           0x17059
-				MX6QDL_PAD_SD3_CLK__SD3_CLK           0x10059
-				MX6QDL_PAD_SD3_DAT0__SD3_DATA0        0x17059
-				MX6QDL_PAD_SD3_DAT1__SD3_DATA1        0x17059
-				MX6QDL_PAD_SD3_DAT2__SD3_DATA2        0x17059
-				MX6QDL_PAD_SD3_DAT3__SD3_DATA3        0x17059
-				MX6QDL_PAD_NANDF_D0__GPIO2_IO00       0x17059
-				MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x17059
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID     0x17059
+		>;
+	};
 
-		pinctrl_usdhc4: usdhc4grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD4_CMD__SD4_CMD           0x17059
-				MX6QDL_PAD_SD4_CLK__SD4_CLK           0x10059
-				MX6QDL_PAD_SD4_DAT0__SD4_DATA0        0x17059
-				MX6QDL_PAD_SD4_DAT1__SD4_DATA1        0x17059
-				MX6QDL_PAD_SD4_DAT2__SD4_DATA2        0x17059
-				MX6QDL_PAD_SD4_DAT3__SD4_DATA3        0x17059
-				MX6QDL_PAD_SD4_DAT4__SD4_DATA4        0x17059
-				MX6QDL_PAD_SD4_DAT5__SD4_DATA5        0x17059
-				MX6QDL_PAD_SD4_DAT6__SD4_DATA6        0x17059
-				MX6QDL_PAD_SD4_DAT7__SD4_DATA7        0x17059
-			>;
-		};
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD           0x17059
+			MX6QDL_PAD_SD2_CLK__SD2_CLK           0x10059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0        0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1        0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2        0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3        0x17059
+			MX6QDL_PAD_NANDF_D2__GPIO2_IO02       0x17059
+		>;
 	};
 
-	gpio_fan {
-		pinctrl_gpio_fan: gpiofangrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D28__GPIO3_IO28        0x130b1
-			>;
-		};
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD           0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK           0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0        0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1        0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2        0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3        0x17059
+			MX6QDL_PAD_NANDF_D0__GPIO2_IO00       0x17059
+			MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x17059
+		>;
 	};
 
-	gpio_leds {
-		pinctrl_gpio_leds: gpioledsgrp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_2__GPIO1_IO02         0x130b1
-			>;
-		};
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD           0x17059
+			MX6QDL_PAD_SD4_CLK__SD4_CLK           0x10059
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0        0x17059
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1        0x17059
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2        0x17059
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3        0x17059
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4        0x17059
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5        0x17059
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6        0x17059
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7        0x17059
+		>;
 	};
 };
diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1010-comtft.dts b/sys/gnu/dts/arm/imx6q-tx6q-1010-comtft.dts
index b18fae10b2e3..65e95ae7509a 100644
--- a/sys/gnu/dts/arm/imx6q-tx6q-1010-comtft.dts
+++ b/sys/gnu/dts/arm/imx6q-tx6q-1010-comtft.dts
@@ -1,12 +1,42 @@
 /*
- * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1010.dts b/sys/gnu/dts/arm/imx6q-tx6q-1010.dts
index b58ec9c966c8..20cd0e7b3e21 100644
--- a/sys/gnu/dts/arm/imx6q-tx6q-1010.dts
+++ b/sys/gnu/dts/arm/imx6q-tx6q-1010.dts
@@ -1,12 +1,42 @@
 /*
- * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1020-comtft.dts b/sys/gnu/dts/arm/imx6q-tx6q-1020-comtft.dts
index 0bb9a9de62a9..9ed243b704ff 100644
--- a/sys/gnu/dts/arm/imx6q-tx6q-1020-comtft.dts
+++ b/sys/gnu/dts/arm/imx6q-tx6q-1020-comtft.dts
@@ -1,12 +1,42 @@
 /*
- * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -94,22 +124,6 @@
 	status = "disabled";
 };
 
-&iomuxc {
-	imx6qdl-tx6 {
-		pinctrl_usdhc4: usdhc4grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x070b1
-				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x070b1
-				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x070b1
-				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x070b1
-				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x070b1
-				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x070b1
-				MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x0b0b1
-			>;
-		};
-	};
-};
-
 &ipu1_di0_disp0 {
 	remote-endpoint = <&display0_in>;
 };
@@ -134,3 +148,17 @@
 	fsl,wp-controller;
 	status = "okay";
 };
+
+&iomuxc {
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x070b1
+			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x070b1
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x070b1
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x070b1
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x070b1
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x070b1
+			MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x0b0b1
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1020.dts b/sys/gnu/dts/arm/imx6q-tx6q-1020.dts
index b96d80a35d39..347b531d3763 100644
--- a/sys/gnu/dts/arm/imx6q-tx6q-1020.dts
+++ b/sys/gnu/dts/arm/imx6q-tx6q-1020.dts
@@ -1,12 +1,42 @@
 /*
- * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -180,22 +210,6 @@
 	status = "disabled";
 };
 
-&iomuxc {
-	imx6qdl-tx6 {
-		pinctrl_usdhc4: usdhc4grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x070b1
-				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x070b1
-				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x070b1
-				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x070b1
-				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x070b1
-				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x070b1
-				MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x0b0b1
-			>;
-		};
-	};
-};
-
 &ipu1_di0_disp0 {
 	remote-endpoint = <&display0_in>;
 };
@@ -208,3 +222,17 @@
 	fsl,wp-controller;
 	status = "okay";
 };
+
+&iomuxc {
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x070b1
+			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x070b1
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x070b1
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x070b1
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x070b1
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x070b1
+			MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x0b0b1
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1036.dts b/sys/gnu/dts/arm/imx6q-tx6q-1036.dts
new file mode 100644
index 000000000000..7c152e32758c
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-tx6q-1036.dts
@@ -0,0 +1,252 @@
+/*
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-tx6.dtsi"
+
+/ {
+	model = "Ka-Ro electronics TX6Q-1036 Module";
+	compatible = "karo,imx6q-tx6q", "fsl,imx6q";
+
+	aliases {
+		display = &display;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd0_pwr>;
+		enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+		power-supply = <&reg_lcd1_pwr>;
+		/*
+		 * a poor man's way to create a 1:1 relationship between
+		 * the PWM value and the actual duty cycle
+		 */
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <50>;
+	};
+
+	display: display@di0 {
+		compatible = "fsl,imx-parallel-display";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_disp0_2>;
+		interface-pix-fmt = "rgb24";
+		status = "okay";
+
+		port {
+			display0_in: endpoint {
+				remote-endpoint = <&ipu1_di0_disp0>;
+			};
+		};
+
+		display-timings {
+			native-mode = <&vga>;
+
+			vga: VGA {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hsync-len = <96>;
+				hfront-porch = <16>;
+				vback-porch = <31>;
+				vsync-len = <2>;
+				vfront-porch = <12>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ETV570 {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <114>;
+				hsync-len = <30>;
+				hfront-porch = <16>;
+				vback-porch = <32>;
+				vsync-len = <3>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0350 {
+				clock-frequency = <6413760>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <34>;
+				hsync-len = <34>;
+				hfront-porch = <20>;
+				vback-porch = <15>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0430 {
+				clock-frequency = <9009000>;
+				hactive = <480>;
+				vactive = <272>;
+				hback-porch = <2>;
+				hsync-len = <41>;
+				hfront-porch = <2>;
+				vback-porch = <2>;
+				vsync-len = <10>;
+				vfront-porch = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			ET0500 {
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0700 { /* same as ET0500 */
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ETQ570 {
+				clock-frequency = <6596040>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <38>;
+				hsync-len = <30>;
+				hfront-porch = <30>;
+				vback-porch = <16>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&ds1339 {
+	status = "disabled";
+};
+
+&gpmi {
+	status = "disabled";
+};
+
+&ipu1_di0_disp0 {
+	remote-endpoint = <&display0_in>;
+};
+
+&ipu2 {
+	status = "disabled";
+};
+
+&reg_lcd0_pwr {
+	status = "disabled";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <4>;
+	non-removable;
+	no-1-8-v;
+	fsl,wp-controller;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x070b1
+			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x070b1
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x070b1
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x070b1
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x070b1
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x070b1
+			MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x0b0b1
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-tx6q-1110.dts b/sys/gnu/dts/arm/imx6q-tx6q-1110.dts
index 88aa1e4c792d..0433e220a931 100644
--- a/sys/gnu/dts/arm/imx6q-tx6q-1110.dts
+++ b/sys/gnu/dts/arm/imx6q-tx6q-1110.dts
@@ -1,12 +1,42 @@
 /*
- * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -77,17 +107,7 @@
 		interrupt-parent = <&gpio3>;
 		interrupts = <22 0>;
 		wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
-		linux,wakeup;
-	};
-};
-
-&iomuxc {
-	imx6q-tx6q-1110 {
-		pinctrl_eeti: eetigrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
-			>;
-		};
+		wakeup-source;
 	};
 };
 
@@ -152,3 +172,11 @@
 &sata {
 	status = "okay";
 };
+
+&iomuxc {
+	pinctrl_eeti: eetigrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-tx6q-11x0-mb7.dts b/sys/gnu/dts/arm/imx6q-tx6q-11x0-mb7.dts
new file mode 100644
index 000000000000..d78b129d01ea
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6q-tx6q-11x0-mb7.dts
@@ -0,0 +1,264 @@
+/*
+ * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-tx6.dtsi"
+
+/ {
+	model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard";
+	compatible = "karo,imx6q-tx6q", "fsl,imx6q";
+
+	aliases {
+		display = &lvds0;
+		ipu1 = &ipu2;
+		lvds0 = &lvds0;
+		lvds1 = &lvds1;
+	};
+
+	backlight0: backlight0 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
+		power-supply = <&reg_lcd0_pwr>;
+		/*
+		 * a poor man's way to create a 1:1 relationship between
+		 * the PWM value and the actual duty cycle
+		 */
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <50>;
+	};
+
+	backlight1: backlight1 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
+		power-supply = <&reg_lcd1_pwr>;
+		/*
+		 * a poor man's way to create a 1:1 relationship between
+		 * the PWM value and the actual duty cycle
+		 */
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <50>;
+	};
+};
+
+&can1 {
+	status = "disabled";
+};
+
+&can2 {
+	xceiver-supply = <&reg_3v3>;
+};
+
+&i2c3 {
+	polytouch1: eeti@04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_eeti>;
+		interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>;
+		wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+		wakeup-source;
+	};
+};
+
+&ipu2 {
+	status = "disabled";
+};
+
+&kpp {
+	status = "disabled"; /* pads partially clash with backlight1 PWM */
+};
+
+&ldb {
+	status = "okay";
+
+	lvds0: lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&lvds0_timing1>;
+
+			lvds0_timing0: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			lvds0_timing1: VGA {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hfront-porch = <16>;
+				vback-porch = <31>;
+				vfront-porch = <12>;
+				hsync-len = <96>;
+				vsync-len = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			lvds0_timing2: nl12880bc20 {
+				clock-frequency = <71000000>;
+				hactive = <1280>;
+				vactive = <800>;
+				hback-porch = <50>;
+				hfront-porch = <50>;
+				vback-porch = <5>;
+				vfront-porch = <5>;
+				hsync-len = <60>;
+				vsync-len = <13>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+		};
+	};
+
+	lvds1: lvds-channel@1 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&lvds1_timing2>;
+
+			lvds1_timing0: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			lvds1_timing1: VGA {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hfront-porch = <16>;
+				vback-porch = <31>;
+				vfront-porch = <12>;
+				hsync-len = <96>;
+				vsync-len = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			lvds1_timing2: nl12880bc20 {
+				clock-frequency = <71000000>;
+				hactive = <1280>;
+				vactive = <800>;
+				hback-porch = <50>;
+				hfront-porch = <50>;
+				vback-porch = <5>;
+				vfront-porch = <5>;
+				hsync-len = <60>;
+				vsync-len = <13>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_eeti: eetigrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6q-wandboard-revb1.dts b/sys/gnu/dts/arm/imx6q-wandboard-revb1.dts
index 20bf3c282623..9207d80f9cfb 100644
--- a/sys/gnu/dts/arm/imx6q-wandboard-revb1.dts
+++ b/sys/gnu/dts/arm/imx6q-wandboard-revb1.dts
@@ -13,7 +13,7 @@
 #include "imx6qdl-wandboard-revb1.dtsi"
 
 / {
-	model = "Wandboard i.MX6 Quad Board";
+	model = "Wandboard i.MX6 Quad Board rev B1";
 	compatible = "wand,imx6q-wandboard", "fsl,imx6q";
 
 	memory {
diff --git a/sys/gnu/dts/arm/imx6q.dtsi b/sys/gnu/dts/arm/imx6q.dtsi
index 0d93c0e8f9ba..c30c8368cae0 100644
--- a/sys/gnu/dts/arm/imx6q.dtsi
+++ b/sys/gnu/dts/arm/imx6q.dtsi
@@ -22,7 +22,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <0>;
@@ -154,21 +154,22 @@
 				#size-cells = <0>;
 				reg = <2>;
 
-				ipu2_di0_disp0: endpoint@0 {
+				ipu2_di0_disp0: disp0-endpoint {
 				};
 
-				ipu2_di0_hdmi: endpoint@1 {
+				ipu2_di0_hdmi: hdmi-endpoint {
 					remote-endpoint = <&hdmi_mux_2>;
 				};
 
-				ipu2_di0_mipi: endpoint@2 {
+				ipu2_di0_mipi: mipi-endpoint {
+					remote-endpoint = <&mipi_mux_2>;
 				};
 
-				ipu2_di0_lvds0: endpoint@3 {
+				ipu2_di0_lvds0: lvds0-endpoint {
 					remote-endpoint = <&lvds0_mux_2>;
 				};
 
-				ipu2_di0_lvds1: endpoint@4 {
+				ipu2_di0_lvds1: lvds1-endpoint {
 					remote-endpoint = <&lvds1_mux_2>;
 				};
 			};
@@ -178,18 +179,19 @@
 				#size-cells = <0>;
 				reg = <3>;
 
-				ipu2_di1_hdmi: endpoint@1 {
+				ipu2_di1_hdmi: hdmi-endpoint {
 					remote-endpoint = <&hdmi_mux_3>;
 				};
 
-				ipu2_di1_mipi: endpoint@2 {
+				ipu2_di1_mipi: mipi-endpoint {
+					remote-endpoint = <&mipi_mux_3>;
 				};
 
-				ipu2_di1_lvds0: endpoint@3 {
+				ipu2_di1_lvds0: lvds0-endpoint {
 					remote-endpoint = <&lvds0_mux_3>;
 				};
 
-				ipu2_di1_lvds1: endpoint@4 {
+				ipu2_di1_lvds1: lvds1-endpoint {
 					remote-endpoint = <&lvds1_mux_3>;
 				};
 			};
diff --git a/sys/gnu/dts/arm/imx6qdl-apalis.dtsi b/sys/gnu/dts/arm/imx6qdl-apalis.dtsi
new file mode 100644
index 000000000000..922b1dd06fda
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6qdl-apalis.dtsi
@@ -0,0 +1,984 @@
+/*
+ * Copyright 2014-2016 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Toradex Apalis iMX6Q/D Module";
+	compatible = "toradex,apalis_imx6q", "fsl,imx6q";
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm4 0 5000000>;
+		status = "disabled";
+	};
+
+	/* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */
+	i2cddc: i2c@0 {
+		compatible = "i2c-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c_ddc>;
+		gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */
+			 &gpio2 30 GPIO_ACTIVE_HIGH /* scl */
+			>;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		status = "disabled";
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "1P8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	reg_2p5v: regulator-2p5v {
+		compatible = "regulator-fixed";
+		regulator-name = "2P5V";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		status = "disabled";
+	};
+
+	/* on module USB hub */
+	reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
+		regulator-name = "usb_host_vbus_hub";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <2000>;
+		enable-active-high;
+		status = "okay";
+	};
+
+	reg_usb_host_vbus: regulator-usb-host-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
+		regulator-name = "usb_host_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&reg_usb_host_vbus_hub>;
+		status = "disabled";
+	};
+
+	sound {
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "imx6q-apalis-sgtl5000";
+		ssi-controller = <&ssi1>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"LINE_IN", "Line In Jack",
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+		mux-int-port = <1>;
+		mux-ext-port = <4>;
+	};
+
+	sound_spdif: sound-spdif {
+		compatible = "fsl,imx-audio-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif>;
+		spdif-in;
+		spdif-out;
+		status = "disabled";
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	status = "disabled";
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	status = "disabled";
+};
+
+/* Apalis SPI1 */
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "disabled";
+};
+
+/* Apalis SPI2 */
+&ecspi2 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2>;
+	status = "disabled";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy>;
+	phy-reset-duration = <10>;
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy: ethernet-phy@7 {
+			interrupt-parent = <&gpio1>;
+			interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+			reg = <7>;
+		};
+	};
+};
+
+/*
+ * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
+ * board)
+ */
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "disabled";
+};
+
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pmic: pfuze100@08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
+	codec: sgtl5000@0a {
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
+		VDDA-supply = <&reg_2p5v>;
+		VDDIO-supply = <&reg_3p3v>;
+	};
+
+	/* STMPE811 touch screen controller */
+	stmpe811@41 {
+		compatible = "st,stmpe811";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_touch_int>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x41>;
+		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-parent = <&gpio4>;
+		interrupt-controller;
+		id = <0>;
+		blocks = <0x5>;
+		irq-trigger = <0x1>;
+
+		stmpe_touchscreen {
+			compatible = "st,stmpe-ts";
+			reg = <0>;
+			/* 3.25 MHz ADC clock speed */
+			st,adc-freq = <1>;
+			/* 8 sample average control */
+			st,ave-ctrl = <3>;
+			/* 7 length fractional part in z */
+			st,fraction-z = <7>;
+			/*
+			 * 50 mA typical 80 mA max touchscreen drivers
+			 * current limit value
+			 */
+			st,i-drive = <1>;
+			/* 12-bit ADC */
+			st,mod-12b = <1>;
+			/* internal ADC reference */
+			st,ref-sel = <0>;
+			/* ADC converstion time: 80 clocks */
+			st,sample-time = <4>;
+			/* 1 ms panel driver settling time */
+			st,settling = <3>;
+			/* 5 ms touch detect interrupt delay */
+			st,touch-det-delay = <5>;
+		};
+	};
+};
+
+/*
+ * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
+ */
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "recovery";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_recovery>;
+	scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+	status = "disabled";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "disabled";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "disabled";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>;
+	status = "disabled";
+};
+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	status = "disabled";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	status = "disabled";
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
+	fsl,dte-mode;
+	fsl,uart-has-rtscts;
+	status = "disabled";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_dte>;
+	fsl,dte-mode;
+	fsl,uart-has-rtscts;
+	status = "disabled";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4_dte>;
+	fsl,dte-mode;
+	status = "disabled";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5_dte>;
+	fsl,dte-mode;
+	status = "disabled";
+};
+
+&usbotg {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "disabled";
+};
+
+/* MMC1 */
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	vqmmc-supply = <&reg_3p3v>;
+	bus-width = <8>;
+	voltage-ranges = <3300 3300>;
+	status = "disabled";
+};
+
+/* SD1 */
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	vqmmc-supply = <&reg_3p3v>;
+	bus-width = <4>;
+	voltage-ranges = <3300 3300>;
+	status = "disabled";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	vqmmc-supply = <&reg_3p3v>;
+	bus-width = <8>;
+	voltage-ranges = <3300 3300>;
+	non-removable;
+	status = "okay";
+};
+
+&weim {
+	status = "disabled";
+};
+
+&iomuxc {
+	/* pins used on module */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_reset_moci>;
+
+	pinctrl_apalis_gpio1: gpio2io04grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio2: gpio2io05grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio3: gpio2io06grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio4: gpio2io07grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio5: gpio6io10grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio6: gpio6io09grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio7: gpio1io02grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
+		>;
+	};
+
+	pinctrl_apalis_gpio8: gpio1io06grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
+		>;
+	};
+
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC	0x130b0
+			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD	0x130b0
+			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS	0x130b0
+			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD	0x130b0
+			/* SGTL5000 sys_mclk */
+			MX6QDL_PAD_GPIO_5__CCM_CLKO1		0x130b0
+		>;
+	};
+
+	pinctrl_cam_mclk: cammclkgrp {
+		fsl,pins = <
+			/* CAM sys_mclk */
+			MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
+			MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
+			MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
+			/* SPI1 cs */
+			MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
+		>;
+	};
+
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
+			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+			/* SPI2 cs */
+			MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			/* Ethernet PHY reset */
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x000b0
+			/* Ethernet PHY interrupt */
+			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x000b1
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
+			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
+			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+		>;
+	};
+
+	pinctrl_gpio_keys: gpio1io04grp {
+		fsl,pins = <
+			/* Power button */
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+		>;
+	};
+
+	pinctrl_hdmi_cec: hdmicecgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+		>;
+	};
+
+	pinctrl_i2c_ddc: gpioi2cddcgrp {
+		fsl,pins = <
+			/* DDC bitbang */
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
+			MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+			MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3_recovery: i2c3recoverygrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
+			MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
+		>;
+	};
+
+	pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0xb0b1
+			MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0xb0b1
+			MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0xb0b1
+			MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0xb0b1
+			MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0xb0b1
+			MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0xb0b1
+			MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0xb0b1
+			MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0xb0b1
+			MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
+			MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0xb0b1
+			MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0xb0b1
+		>;
+	};
+
+	pinctrl_ipu1_lcdif: ipu1lcdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK	0x61
+			/* DE */
+			MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15	0x61
+			/* HSync */
+			MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02	0x61
+			/* VSync */
+			MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03	0x61
+			MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00	0x61
+			MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01	0x61
+			MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02	0x61
+			MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03	0x61
+			MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04	0x61
+			MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05	0x61
+			MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06	0x61
+			MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07	0x61
+			MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08	0x61
+			MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09	0x61
+			MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10	0x61
+			MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11	0x61
+			MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12	0x61
+			MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13	0x61
+			MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14	0x61
+			MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15	0x61
+			MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16	0x61
+			MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17	0x61
+			MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18	0x61
+			MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19	0x61
+			MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20	0x61
+			MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21	0x61
+			MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22	0x61
+			MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23	0x61
+		>;
+	};
+
+	pinctrl_ipu2_vdac: ipu2vdacgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
+			MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xd1
+			MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xd1
+			MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xd1
+			MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xf9
+			MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xf9
+			MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xf9
+			MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xf9
+			MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xf9
+			MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xf9
+			MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xf9
+			MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xf9
+			MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xf9
+			MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xf9
+			MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xf9
+			MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xf9
+			MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xf9
+			MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xf9
+			MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xf9
+			MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xf9
+		>;
+	};
+
+	pinctrl_mmc_cd: gpiommccdgrp {
+		fsl,pins = <
+			 /* MMC1 CD */
+			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+		>;
+	};
+
+	pinctrl_pwm4: pwm4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
+		>;
+	};
+
+	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
+		fsl,pins = <
+			/* USBH_EN */
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
+		>;
+	};
+
+	pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
+		fsl,pins = <
+			/* USBH_HUB_EN */
+			MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
+		>;
+	};
+
+	pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
+		fsl,pins = <
+			/* USBO1 power en */
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
+		>;
+	};
+
+	pinctrl_reset_moci: gpioresetmocigrp {
+		fsl,pins = <
+			/* RESET_MOCI control */
+			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
+		>;
+	};
+
+	pinctrl_sd_cd: gpiosdcdgrp {
+		fsl,pins = <
+			/* SD1 CD */
+			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
+		>;
+	};
+
+	pinctrl_spdif: spdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
+			MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+		>;
+	};
+
+	pinctrl_touch_int: gpiotouchintgrp {
+		fsl,pins = <
+			/* STMPE811 interrupt */
+			MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+		>;
+	};
+
+	pinctrl_uart1_dce: uart1dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart1_dte: uart1dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
+			MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
+			MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
+			MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
+		>;
+	};
+
+	/* Additional DTR, DSR, DCD */
+	pinctrl_uart1_ctrl: uart1ctrlgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
+			MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
+			MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
+		>;
+	};
+
+	pinctrl_uart2_dce: uart2dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart2_dte: uart2dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT6__UART2_RTS_B	0x1b0b1
+			MX6QDL_PAD_SD4_DAT5__UART2_CTS_B	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart4_dce: uart4dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart4_dte: uart4dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
+		>;
+	};
+
+	pinctrl_uart5_dce: uart5dcegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+		>;
+	};
+
+	/* DTE mode */
+	pinctrl_uart5_dte: uart5dtegrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
+			MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
+			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+			MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
+			MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
+			MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
+			MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17071
+			MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10071
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+			/* eMMC reset */
+			MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170b9
+			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100b9
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
+			/* eMMC reset */
+			MX6QDL_PAD_SD3_RST__SD3_RESET  0x170b9
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170f9
+			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100f9
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
+			/* eMMC reset */
+			MX6QDL_PAD_SD3_RST__SD3_RESET  0x170f9
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6qdl-apf6dev.dtsi b/sys/gnu/dts/arm/imx6qdl-apf6dev.dtsi
index e26ebeb5b45c..865c9a264a43 100644
--- a/sys/gnu/dts/arm/imx6qdl-apf6dev.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-apf6dev.dtsi
@@ -94,7 +94,7 @@
 			label = "User button";
 			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_MISC>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -213,7 +213,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_3p3v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
diff --git a/sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi
index 5cd16f2178b8..9d7ab6cdc9a6 100644
--- a/sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-gw51xx.dtsi
@@ -320,13 +320,13 @@
 
 		pinctrl_pwm3: pwm3grp {
 			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
 			>;
 		};
 
 		pinctrl_pwm4: pwm4grp {
 			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
 			>;
 		};
 
diff --git a/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi
index 9fa8a10c7cc8..7191b84770b9 100644
--- a/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi
@@ -244,7 +244,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_1p8v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
@@ -473,7 +473,7 @@
 
 		pinctrl_pwm3: pwm3grp {
 			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
 			>;
 		};
 
diff --git a/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi
index e8375e173873..40d06b09deba 100644
--- a/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi
@@ -237,7 +237,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_1p8v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
@@ -462,7 +462,7 @@
 
 		pinctrl_pwm3: pwm3grp {
 			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
 			>;
 		};
 
diff --git a/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi b/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi
index 66983dc5cbda..d6dbe2a88ee6 100644
--- a/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-gw54xx.dtsi
@@ -328,7 +328,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&sw4_reg>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
@@ -397,8 +397,9 @@
 };
 
 &pwm4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm4>;
+	pinctrl-names = "default", "state_dio";
+	pinctrl-0 = <&pinctrl_pwm4_backlight>;
+	pinctrl-1 = <&pinctrl_pwm4_dio>;
 	status = "okay";
 };
 
@@ -573,12 +574,20 @@
 			>;
 		};
 
-		pinctrl_pwm4: pwm4grp {
+		pinctrl_pwm4_backlight: pwm4grpbacklight {
 			fsl,pins = <
+				/* LVDS_PWM J6.5 */
 				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
 			>;
 		};
 
+		pinctrl_pwm4_dio: pwm4grpdio {
+			fsl,pins = <
+				/* DIO3 J16.4 */
+				MX6QDL_PAD_SD4_DAT2__PWM4_OUT		0x1b0b1
+			>;
+		};
+
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
 				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
diff --git a/sys/gnu/dts/arm/imx6qdl-gw552x.dtsi b/sys/gnu/dts/arm/imx6qdl-gw552x.dtsi
index cca39f194017..f27f184558fb 100644
--- a/sys/gnu/dts/arm/imx6qdl-gw552x.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-gw552x.dtsi
@@ -262,7 +262,7 @@
 
 		pinctrl_pwm3: pwm3grp {
 			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
 			>;
 		};
 
diff --git a/sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi b/sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi
index 6dd0b764e036..d6c2358ffad4 100644
--- a/sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-hummingboard.dtsi
@@ -48,7 +48,7 @@
 
 	ir_recv: ir-receiver {
 		compatible = "gpio-ir-receiver";
-		gpios = <&gpio3 5 1>;
+		gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>;
 	};
@@ -67,7 +67,7 @@
 		reg_usbh1_vbus: usb-h1-vbus {
 			compatible = "regulator-fixed";
 			enable-active-high;
-			gpio = <&gpio1 0 0>;
+			gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
 			regulator-name = "usb_h1_vbus";
@@ -78,7 +78,7 @@
 		reg_usbotg_vbus: usb-otg-vbus {
 			compatible = "regulator-fixed";
 			enable-active-high;
-			gpio = <&gpio3 22 0>;
+			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
 			regulator-name = "usb_otg_vbus";
@@ -253,7 +253,7 @@
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hummingboard_pcie_reset>;
-	reset-gpio = <&gpio3 4 0>;
+	reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi b/sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi
new file mode 100644
index 000000000000..f8d945a56525
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6qdl-icore-rqs.dtsi
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2015 Amarula Solutions B.V.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+
+/ {
+	memory {
+		reg = <0x10000000 0x80000000>;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "1P8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_2p5v: regulator-2p5v {
+		compatible = "regulator-fixed";
+		regulator-name = "2P5V";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_sd3_vmmc: regulator-sd3-vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "P3V3_SD3_SWITCHED";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
+		enable-active-high;
+	};
+
+	reg_sd4_vmmc: regulator-sd4-vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "P3V3_SD4_SWITCHED";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_usb_h1_vbus: regulator-usb-h1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_h1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	usb_hub: usb-hub {
+		compatible = "smsc,usb3503a";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbhub>;
+		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+		clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
+		clock-names = "refclk";
+	};
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-handle = <&eth_phy>;
+	phy-mode = "rgmii";
+	status = "okay";
+
+	mdio {
+		eth_phy: ethernet-phy {
+			rxc-skew-ps = <1140>;
+			txc-skew-ps = <1140>;
+			txen-skew-ps = <600>;
+			rxdv-skew-ps = <240>;
+			rxd0-skew-ps = <420>;
+			rxd1-skew-ps = <600>;
+			rxd2-skew-ps = <420>;
+			rxd3-skew-ps = <240>;
+			txd0-skew-ps = <60>;
+			txd1-skew-ps = <60>;
+			txd2-skew-ps = <60>;
+			txd3-skew-ps = <240>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&ssi1 {
+	fsl,mode = "i2s-slave";
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	disable-over-current;
+	clocks = <&clks IMX6QDL_CLK_USBOH3>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	vmcc-supply = <&reg_sd3_vmmc>;
+	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+	bus-witdh=<4>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
+	vmcc-supply = <&reg_sd4_vmmc>;
+	bus-witdh=<8>;
+	no-1-8-v;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_audmux: audmux {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
+			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
+			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+			MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
+			MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+			MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
+		>;
+	};
+
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059	/* PCIe Reset */
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+		>;
+	};
+
+	pinctrl_usbhub: usbhubgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_6__GPIO1_IO06  0x1f059	/* HUB USB Reset */
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
+			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
+			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
+			MX6QDL_PAD_GPIO_1__GPIO1_IO01  0x1f059	/* CD */
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1f059	/* PWR */
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170B1
+			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100B1
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170F9
+			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100F9
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
+		>;
+	};
+
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
+			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
+		>;
+	};
+
+	pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170B1
+			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100B1
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
+		>;
+	};
+
+	pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170F9
+			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100F9
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6qdl-microsom.dtsi b/sys/gnu/dts/arm/imx6qdl-microsom.dtsi
index 6d4069cc9419..86460e46d055 100644
--- a/sys/gnu/dts/arm/imx6qdl-microsom.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-microsom.dtsi
@@ -154,6 +154,7 @@
 	bus-width = <4>;
 	mmc-pwrseq = <&usdhc1_pwrseq>;
 	keep-power-in-suspend;
+	no-1-8-v;
 	non-removable;
 	vmmc-supply = <&reg_brcm>;
 	status = "okay";
diff --git a/sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi b/sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi
index 24d7d3f18464..e456b5cc1b03 100644
--- a/sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-nit6xlite.dtsi
@@ -269,7 +269,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_sgtl5000>;
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_2p5v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
diff --git a/sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi b/sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi
index a35d54fd9cd3..657da6b6ccd2 100644
--- a/sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-nitrogen6_max.dtsi
@@ -138,7 +138,7 @@
 			label = "Power Button";
 			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		menu {
@@ -402,7 +402,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_2p5v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
diff --git a/sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi b/sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi
index caeed56b74a3..73915db704a0 100644
--- a/sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-nitrogen6x.dtsi
@@ -119,7 +119,7 @@
 			label = "Power Button";
 			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		menu {
@@ -304,7 +304,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_2p5v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
diff --git a/sys/gnu/dts/arm/imx6qdl-rex.dtsi b/sys/gnu/dts/arm/imx6qdl-rex.dtsi
index a50356243888..cacf5933707d 100644
--- a/sys/gnu/dts/arm/imx6qdl-rex.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-rex.dtsi
@@ -126,7 +126,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_3p3v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
diff --git a/sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi b/sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi
index 1a69a3420ac8..c47fe6c79b36 100644
--- a/sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-sabrelite.dtsi
@@ -105,7 +105,7 @@
 			label = "Power Button";
 			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		menu {
@@ -290,7 +290,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_2p5v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
diff --git a/sys/gnu/dts/arm/imx6qdl-sabresd.dtsi b/sys/gnu/dts/arm/imx6qdl-sabresd.dtsi
index a6d445c17779..5248e7bd2b06 100644
--- a/sys/gnu/dts/arm/imx6qdl-sabresd.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-sabresd.dtsi
@@ -79,21 +79,21 @@
 		power {
 			label = "Power Button";
 			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
-			gpio-key,wakeup;
+			wakeup-source;
 			linux,code = <KEY_POWER>;
 		};
 
 		volume-up {
 			label = "Volume Up";
 			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
-			gpio-key,wakeup;
+			wakeup-source;
 			linux,code = <KEY_VOLUMEUP>;
 		};
 
 		volume-down {
 			label = "Volume Down";
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
-			gpio-key,wakeup;
+			wakeup-source;
 			linux,code = <KEY_VOLUMEDOWN>;
 		};
 	};
@@ -115,7 +115,7 @@
 		mux-ext-port = <3>;
 	};
 
-	backlight {
+	backlight_lvds: backlight-lvds {
 		compatible = "pwm-backlight";
 		pwms = <&pwm1 0 5000000>;
 		brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -133,6 +133,17 @@
 		        default-state = "on";
 		};
 	};
+
+	panel {
+		compatible = "hannstar,hsd100pxn1";
+		backlight = <&backlight_lvds>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
 };
 
 &audmux {
@@ -238,6 +249,7 @@
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
+				regulator-ramp-delay = <6250>;
 			};
 
 			sw3a_reg: sw3a {
@@ -508,18 +520,11 @@
 		fsl,data-width = <18>;
 		status = "okay";
 
-		display-timings {
-			native-mode = <&timing0>;
-			timing0: hsd100pxn1 {
-				clock-frequency = <65000000>;
-				hactive = <1024>;
-				vactive = <768>;
-				hback-porch = <220>;
-				hfront-porch = <40>;
-				vback-porch = <21>;
-				vfront-porch = <7>;
-				hsync-len = <60>;
-				vsync-len = <10>;
+		port@4 {
+			reg = <4>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&panel_in>;
 			};
 		};
 	};
diff --git a/sys/gnu/dts/arm/imx6qdl-tx6.dtsi b/sys/gnu/dts/arm/imx6qdl-tx6.dtsi
index 13cb7ccfea44..39b85aef93e1 100644
--- a/sys/gnu/dts/arm/imx6qdl-tx6.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-tx6.dtsi
@@ -1,12 +1,42 @@
 /*
- * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -37,11 +67,12 @@
 	clocks {
 		#address-cells = <1>;
 		#size-cells = <0>;
+
 		mclk: clock@0 {
 			compatible = "fixed-clock";
 			reg = <0>;
 			#clock-cells = <0>;
-			clock-frequency = <27000000>;
+			clock-frequency = <26000000>;
 		};
 	};
 
@@ -52,7 +83,7 @@
 			label = "Power Button";
 			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -61,109 +92,95 @@
 
 		user_led: user {
 			label = "Heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_user_led>;
 			gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};
 
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		reg_3v3_etn: regulator@0 {
-			compatible = "regulator-fixed";
-			reg = <0>;
-			regulator-name = "3V3_ETN";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_etnphy_power>;
-			gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-		};
+	reg_3v3_etn: regulator-3v3-etn {
+		compatible = "regulator-fixed";
+		regulator-name = "3V3_ETN";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_etnphy_power>;
+		gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 
-		reg_2v5: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "2V5";
-			regulator-min-microvolt = <2500000>;
-			regulator-max-microvolt = <2500000>;
-			regulator-always-on;
-		};
+	reg_2v5: regulator-2v5 {
+		compatible = "regulator-fixed";
+		regulator-name = "2V5";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-always-on;
+	};
 
-		reg_3v3: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <2>;
-			regulator-name = "3V3";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			regulator-always-on;
-		};
+	reg_3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
 
-		reg_can_xcvr: regulator@3 {
-			compatible = "regulator-fixed";
-			reg = <3>;
-			regulator-name = "CAN XCVR";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_flexcan_xcvr>;
-			gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
-			enable-active-low;
-		};
+	reg_can_xcvr: regulator-can-xcvr {
+		compatible = "regulator-fixed";
+		regulator-name = "CAN XCVR";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan_xcvr>;
+		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+		enable-active-low;
+	};
 
-		reg_lcd0_pwr: regulator@4 {
-			compatible = "regulator-fixed";
-			reg = <4>;
-			regulator-name = "LCD0 POWER";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_lcd0_pwr>;
-			gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-			regulator-boot-on;
-			regulator-always-on;
-		};
+	reg_lcd0_pwr: regulator-lcd0-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "LCD0 POWER";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd0_pwr>;
+		gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+	};
 
-		reg_lcd1_pwr: regulator@5 {
-			compatible = "regulator-fixed";
-			reg = <5>;
-			regulator-name = "LCD1 POWER";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_lcd1_pwr>;
-			gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-			regulator-boot-on;
-			regulator-always-on;
-		};
+	reg_lcd1_pwr: regulator-lcd1-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "LCD1 POWER";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd1_pwr>;
+		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+	};
 
-		reg_usbh1_vbus: regulator@6 {
-			compatible = "regulator-fixed";
-			reg = <6>;
-			regulator-name = "usbh1_vbus";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usbh1_vbus>;
-			gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-		};
+	reg_usbh1_vbus: regulator-usbh1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usbh1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh1_vbus>;
+		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 
-		reg_usbotg_vbus: regulator@7 {
-			compatible = "regulator-fixed";
-			reg = <7>;
-			regulator-name = "usbotg_vbus";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usbotg_vbus>;
-			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-		};
+	reg_usbotg_vbus: regulator-usbotg-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usbotg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbotg_vbus>;
+		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
 	};
 
 	sound {
@@ -209,7 +226,7 @@
 		&gpio2 30 GPIO_ACTIVE_HIGH
 		&gpio3 19 GPIO_ACTIVE_HIGH
 	>;
-	status = "okay";
+	status = "disabled";
 
 	spidev0: spi@0 {
 		compatible = "spidev";
@@ -227,10 +244,29 @@
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
+	clocks = <&clks IMX6QDL_CLK_ENET>,
+		 <&clks IMX6QDL_CLK_ENET>,
+		 <&clks IMX6QDL_CLK_ENET_REF>,
+		 <&clks IMX6QDL_CLK_ENET_REF>;
+	clock-names = "ipg", "ahb", "ptp", "enet_out";
 	phy-mode = "rmii";
 	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
+	phy-handle = <&etnphy>;
 	phy-supply = <&reg_3v3_etn>;
 	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		etnphy: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_enet_mdio>;
+			interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>;
+		};
+	};
 };
 
 &gpmi {
@@ -276,7 +312,7 @@
 		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
 		reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 		wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
-		linux,wakeup;
+		wakeup-source;
 	};
 
 	touchscreen: tsc2007@48 {
@@ -288,7 +324,7 @@
 		interrupts = <26 0>;
 		gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 		ti,x-plate-ohms = <660>;
-		linux,wakeup;
+		wakeup-source;
 	};
 };
 
@@ -296,310 +332,318 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6qdl-tx6 {
-		pinctrl_hog: hoggrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_A18__GPIO2_IO20		0x1b0b1 /* LED */
-				MX6QDL_PAD_SD3_DAT2__GPIO7_IO06		0x1b0b1 /* ETN PHY RESET */
-				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x1b0b1 /* ETN PHY INT */
-				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b1 /* PWR BTN */
-			>;
-		};
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT2__GPIO7_IO06		0x1b0b1 /* ETN PHY RESET */
+			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x1b0b1 /* ETN PHY INT */
+			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b1 /* PWR BTN */
+		>;
+	};
 
-		pinctrl_audmux: audmuxgrp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_ROW1__AUD5_RXD		0x130b0 /* SSI1_RXD */
-				MX6QDL_PAD_KEY_ROW0__AUD5_TXD		0x110b0 /* SSI1_TXD */
-				MX6QDL_PAD_KEY_COL0__AUD5_TXC		0x130b0 /* SSI1_CLK */
-				MX6QDL_PAD_KEY_COL1__AUD5_TXFS		0x130b0 /* SSI1_FS */
-			>;
-		};
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW1__AUD5_RXD		0x130b0 /* SSI1_RXD */
+			MX6QDL_PAD_KEY_ROW0__AUD5_TXD		0x110b0 /* SSI1_TXD */
+			MX6QDL_PAD_KEY_COL0__AUD5_TXC		0x130b0 /* SSI1_CLK */
+			MX6QDL_PAD_KEY_COL1__AUD5_TXFS		0x130b0 /* SSI1_FS */
+		>;
+	};
 
-		pinctrl_disp0_1: disp0grp-1 {
-			fsl,pins = <
-				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
-				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
-				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
-				/* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
-				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
-				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
-				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
-				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
-				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
-				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
-				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
-				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
-				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
-				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
-				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
-				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
-				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
-				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
-				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
-				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
-				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
-				MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
-				MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
-				MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
-				MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
-				MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
-				MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
-			>;
-		};
+	pinctrl_disp0_1: disp0grp-1 {
+		fsl,pins = <
+			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
+			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
+			/* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
+			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
+			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
+			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
+			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
+			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
+			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
+			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
+			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
+			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
+			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
+			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
+			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
+			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
+			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
+			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
+			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
+			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
+			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
+			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
+			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
+			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
+			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
+			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
+		>;
+	};
 
-		pinctrl_disp0_2: disp0grp-2 {
-			fsl,pins = <
-				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
-				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
-				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
-				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
-				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
-				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
-				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
-				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
-				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
-				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
-				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
-				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
-				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
-				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
-				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
-				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
-				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
-				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
-				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
-				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
-				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
-				MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
-				MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
-				MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
-				MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
-				MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
-				MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
-			>;
-		};
+	pinctrl_disp0_2: disp0grp-2 {
+		fsl,pins = <
+			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
+			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
+			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
+			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
+			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
+			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
+			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
+			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
+			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
+			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
+			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
+			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
+			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
+			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
+			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
+			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
+			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
+			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
+			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
+			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
+			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
+			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
+			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
+			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
+			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
+			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
+		>;
+	};
 
-		pinctrl_ecspi1: ecspi1grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x0b0b0
-				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x0b0b0
-				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x0b0b0
-				MX6QDL_PAD_GPIO_19__ECSPI1_RDY		0x0b0b0
-				MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x0b0b0 /* SPI CS0 */
-				MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x0b0b0 /* SPI CS1 */
-			>;
-		};
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x0b0b0
+			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x0b0b0
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x0b0b0
+			MX6QDL_PAD_GPIO_19__ECSPI1_RDY		0x0b0b0
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x0b0b0 /* SPI CS0 */
+			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x0b0b0 /* SPI CS1 */
+		>;
+	};
 
-		pinctrl_edt_ft5x06: edt-ft5x06grp {
-			fsl,pins = <
-				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x1b0b0 /* Interrupt */
-				MX6QDL_PAD_EIM_A16__GPIO2_IO22  	0x1b0b0 /* Reset */
-				MX6QDL_PAD_EIM_A17__GPIO2_IO21  	0x1b0b0 /* Wake */
-			>;
-		};
+	pinctrl_edt_ft5x06: edt-ft5x06grp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x1b0b0 /* Interrupt */
+			MX6QDL_PAD_EIM_A16__GPIO2_IO22  	0x1b0b0 /* Reset */
+			MX6QDL_PAD_EIM_A17__GPIO2_IO21  	0x1b0b0 /* Wake */
+		>;
+	};
 
-		pinctrl_enet: enetgrp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-				MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
-				MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
-				MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
-				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
-				MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
-				MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
-				MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
-			>;
-		};
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+		>;
+	};
 
-		pinctrl_etnphy_power: etnphy-pwrgrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D20__GPIO3_IO20		0x1b0b1 /* ETN PHY POWER */
-			>;
-		};
+	pinctrl_enet_mdio: enet-mdiogrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+		>;
+	};
 
-		pinctrl_flexcan1: flexcan1grp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x1b0b0
-				MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
-			>;
-		};
+	pinctrl_etnphy_power: etnphy-pwrgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D20__GPIO3_IO20		0x1b0b1 /* ETN PHY POWER */
+		>;
+	};
 
-		pinctrl_flexcan2: flexcan2grp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
-				MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
-			>;
-		};
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x1b0b0
+			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
+		>;
+	};
 
-		pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
-			fsl,pins = <
-				MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21	0x1b0b0 /* Flexcan XCVR enable */
-			>;
-		};
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
+			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
+		>;
+	};
 
-		pinctrl_gpmi_nand: gpminandgrp {
-			fsl,pins = <
-				MX6QDL_PAD_NANDF_CLE__NAND_CLE    	0x0b0b1
-				MX6QDL_PAD_NANDF_ALE__NAND_ALE    	0x0b0b1
-				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B  	0x0b0b1
-				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0x0b000
-				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B  	0x0b0b1
-				MX6QDL_PAD_SD4_CMD__NAND_RE_B     	0x0b0b1
-				MX6QDL_PAD_SD4_CLK__NAND_WE_B     	0x0b0b1
-				MX6QDL_PAD_NANDF_D0__NAND_DATA00  	0x0b0b1
-				MX6QDL_PAD_NANDF_D1__NAND_DATA01  	0x0b0b1
-				MX6QDL_PAD_NANDF_D2__NAND_DATA02  	0x0b0b1
-				MX6QDL_PAD_NANDF_D3__NAND_DATA03  	0x0b0b1
-				MX6QDL_PAD_NANDF_D4__NAND_DATA04  	0x0b0b1
-				MX6QDL_PAD_NANDF_D5__NAND_DATA05  	0x0b0b1
-				MX6QDL_PAD_NANDF_D6__NAND_DATA06  	0x0b0b1
-				MX6QDL_PAD_NANDF_D7__NAND_DATA07  	0x0b0b1
-			>;
-		};
+	pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
+		fsl,pins = <
+			MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21	0x1b0b0 /* Flexcan XCVR enable */
+		>;
+	};
 
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
-				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
-			>;
-		};
+	pinctrl_gpmi_nand: gpminandgrp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_CLE__NAND_CLE    	0x0b0b1
+			MX6QDL_PAD_NANDF_ALE__NAND_ALE    	0x0b0b1
+			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B  	0x0b0b1
+			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0x0b000
+			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B  	0x0b0b1
+			MX6QDL_PAD_SD4_CMD__NAND_RE_B     	0x0b0b1
+			MX6QDL_PAD_SD4_CLK__NAND_WE_B     	0x0b0b1
+			MX6QDL_PAD_NANDF_D0__NAND_DATA00  	0x0b0b1
+			MX6QDL_PAD_NANDF_D1__NAND_DATA01  	0x0b0b1
+			MX6QDL_PAD_NANDF_D2__NAND_DATA02  	0x0b0b1
+			MX6QDL_PAD_NANDF_D3__NAND_DATA03  	0x0b0b1
+			MX6QDL_PAD_NANDF_D4__NAND_DATA04  	0x0b0b1
+			MX6QDL_PAD_NANDF_D5__NAND_DATA05  	0x0b0b1
+			MX6QDL_PAD_NANDF_D6__NAND_DATA06  	0x0b0b1
+			MX6QDL_PAD_NANDF_D7__NAND_DATA07  	0x0b0b1
+		>;
+	};
 
-		pinctrl_i2c3: i2c3grp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
-				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
-			>;
-		};
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
+			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
+		>;
+	};
 
-		pinctrl_kpp: kppgrp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_9__KEY_COL6		0x1b0b1
-				MX6QDL_PAD_GPIO_4__KEY_COL7		0x1b0b1
-				MX6QDL_PAD_KEY_COL2__KEY_COL2		0x1b0b1
-				MX6QDL_PAD_KEY_COL3__KEY_COL3		0x1b0b1
-				MX6QDL_PAD_GPIO_2__KEY_ROW6		0x1b0b1
-				MX6QDL_PAD_GPIO_5__KEY_ROW7		0x1b0b1
-				MX6QDL_PAD_KEY_ROW2__KEY_ROW2		0x1b0b1
-				MX6QDL_PAD_KEY_ROW3__KEY_ROW3		0x1b0b1
-			>;
-		};
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
+		>;
+	};
 
-		pinctrl_lcd0_pwr: lcd0-pwrgrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x1b0b1 /* LCD Reset */
-			>;
-		};
+	pinctrl_kpp: kppgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_9__KEY_COL6		0x1b0b1
+			MX6QDL_PAD_GPIO_4__KEY_COL7		0x1b0b1
+			MX6QDL_PAD_KEY_COL2__KEY_COL2		0x1b0b1
+			MX6QDL_PAD_KEY_COL3__KEY_COL3		0x1b0b1
+			MX6QDL_PAD_GPIO_2__KEY_ROW6		0x1b0b1
+			MX6QDL_PAD_GPIO_5__KEY_ROW7		0x1b0b1
+			MX6QDL_PAD_KEY_ROW2__KEY_ROW2		0x1b0b1
+			MX6QDL_PAD_KEY_ROW3__KEY_ROW3		0x1b0b1
+		>;
+	};
 
-		pinctrl_lcd1_pwr: lcd1-pwrgrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x1b0b1 /* LCD Power Enable */
-			>;
-		};
+	pinctrl_lcd0_pwr: lcd0-pwrgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x1b0b1 /* LCD Reset */
+		>;
+	};
 
-		pinctrl_pwm1: pwm1grp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
-			>;
-		};
+	pinctrl_lcd1_pwr: lcd-pwrgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x1b0b1 /* LCD Power Enable */
+		>;
+	};
 
-		pinctrl_pwm2: pwm2grp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_1__PWM2_OUT		0x1b0b1
-			>;
-		};
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
+		>;
+	};
 
-		pinctrl_tsc2007: tsc2007grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D26__GPIO3_IO26		0x1b0b0 /* Interrupt */
-			>;
-		};
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__PWM2_OUT		0x1b0b1
+		>;
+	};
 
-		pinctrl_uart1: uart1grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
-				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
-			>;
-		};
+	pinctrl_tsc2007: tsc2007grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0x1b0b0 /* Interrupt */
+		>;
+	};
 
-		pinctrl_uart1_rtscts: uart1_rtsctsgrp {
-			fsl,pins = <
-				MX6QDL_PAD_SD3_DAT1__UART1_RTS_B	0x1b0b1
-				MX6QDL_PAD_SD3_DAT0__UART1_CTS_B	0x1b0b1
-			>;
-		};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
+		>;
+	};
 
-		pinctrl_uart2: uart2grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
-				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
-			>;
-		};
+	pinctrl_uart1_rtscts: uart1_rtsctsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT1__UART1_RTS_B	0x1b0b1
+			MX6QDL_PAD_SD3_DAT0__UART1_CTS_B	0x1b0b1
+		>;
+	};
 
-		pinctrl_uart2_rtscts: uart2_rtsctsgrp {
-			fsl,pins = <
-				MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b1
-				MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b1
-			>;
-		};
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
+			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
+		>;
+	};
 
-		pinctrl_uart3: uart3grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
-				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
-			>;
-		};
+	pinctrl_uart2_rtscts: uart2_rtsctsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b1
+			MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b1
+		>;
+	};
 
-		pinctrl_uart3_rtscts: uart3_rtsctsgrp {
-			fsl,pins = <
-				MX6QDL_PAD_SD3_DAT3__UART3_CTS_B	0x1b0b1
-				MX6QDL_PAD_SD3_RST__UART3_RTS_B		0x1b0b1
-			>;
-		};
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
+		>;
+	};
 
-		pinctrl_usbh1_vbus: usbh1-vbusgrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x1b0b0 /* USBH1_VBUSEN */
-			>;
-		};
+	pinctrl_uart3_rtscts: uart3_rtsctsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT3__UART3_CTS_B	0x1b0b1
+			MX6QDL_PAD_SD3_RST__UART3_RTS_B		0x1b0b1
+		>;
+	};
 
-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x17059
-			>;
-		};
+	pinctrl_usbh1_vbus: usbh1-vbusgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x1b0b0 /* USBH1_VBUSEN */
+		>;
+	};
 
-		pinctrl_usbotg_vbus: usbotg-vbusgrp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_7__GPIO1_IO07		0x1b0b0 /* USBOTG_VBUSEN */
-			>;
-		};
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x17059
+		>;
+	};
 
-		pinctrl_usdhc1: usdhc1grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x070b1
-				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x070b1
-				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x070b1
-				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x070b1
-				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x070b1
-				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x070b1
-				MX6QDL_PAD_SD3_CMD__GPIO7_IO02		0x170b0 /* SD1 CD */
-			>;
-		};
+	pinctrl_usbotg_vbus: usbotg-vbusgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_7__GPIO1_IO07		0x1b0b0 /* USBOTG_VBUSEN */
+		>;
+	};
 
-		pinctrl_usdhc2: usdhc2grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x070b1
-				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x070b1
-				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x070b1
-				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x070b1
-				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x070b1
-				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x070b1
-				MX6QDL_PAD_SD3_CLK__GPIO7_IO03		0x170b0 /* SD2 CD */
-			>;
-		};
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD		0x070b1
+			MX6QDL_PAD_SD1_CLK__SD1_CLK		0x070b1
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x070b1
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x070b1
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x070b1
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x070b1
+			MX6QDL_PAD_SD3_CMD__GPIO7_IO02		0x170b0 /* SD1 CD */
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x070b1
+			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x070b1
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x070b1
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x070b1
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x070b1
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x070b1
+			MX6QDL_PAD_SD3_CLK__GPIO7_IO03		0x170b0 /* SD2 CD */
+		>;
+	};
+
+	pinctrl_user_led: user-ledgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_A18__GPIO2_IO20		0x1b0b1 /* LED */
+		>;
 	};
 };
 
@@ -644,19 +688,22 @@
 
 &uart1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
+	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
+	fsl,uart-has-rtscts;
 	status = "okay";
 };
 
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
+	fsl,uart-has-rtscts;
 	status = "okay";
 };
 
 &uart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
+	fsl,uart-has-rtscts;
 	status = "okay";
 };
 
diff --git a/sys/gnu/dts/arm/imx6qdl-udoo.dtsi b/sys/gnu/dts/arm/imx6qdl-udoo.dtsi
index 1211da894ee9..3bee2f910067 100644
--- a/sys/gnu/dts/arm/imx6qdl-udoo.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-udoo.dtsi
@@ -10,14 +10,49 @@
  */
 
 / {
+	aliases {
+		backlight = &backlight;
+		panelchan = &panelchan;
+		panel7 = &panel7;
+		touchscreenp7 = &touchscreenp7;
+	};
+
 	chosen {
 		stdout-path = &uart2;
 	};
 
+	backlight: backlight {
+		compatible = "gpio-backlight";
+		gpios = <&gpio1 4 0>;
+		default-on;
+		status = "disabled";
+	};
+
 	memory {
 		reg = <0x10000000 0x40000000>;
 	};
 
+	panel7: panel7 {
+		/*
+		 * in reality it is a -20t (parallel) model,
+		 * but with LVDS bridge chip attached,
+		 * so it is equivalent to -19t model in drive
+		 * characteristics
+		 */
+		compatible = "urt,umsh-8596md-19t";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_panel>;
+		power-supply = <&reg_panel>;
+		backlight = <&backlight>;
+		status = "disabled";
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -33,6 +68,26 @@
 			startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
 			gpio = <&gpio7 12 0>;
 		};
+
+		reg_panel: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "lcd_panel";
+			enable-active-high;
+			gpio = <&gpio1 2 0>;
+		};
+	};
+
+	sound {
+		compatible = "fsl,imx6q-udoo-ac97",
+			     "fsl,imx-audio-ac97";
+		model = "fsl,imx6q-udoo-ac97";
+		audio-cpu = <&ssi1>;
+		audio-routing =
+			"RX", "Mic Jack",
+			"Headphone Jack", "TX";
+		mux-int-port = <1>;
+		mux-ext-port = <6>;
 	};
 };
 
@@ -55,6 +110,24 @@
 	status = "okay";
 };
 
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	touchscreenp7: touchscreenp7@55 {
+		compatible = "sitronix,st1232";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_touchscreenp7>;
+		reg = <0x55>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <13 8>;
+		gpios = <&gpio1 15 0>;
+		status = "disabled";
+	};
+};
+
 &iomuxc {
 	imx6q-udoo {
 		pinctrl_enet: enetgrp {
@@ -85,6 +158,27 @@
 			>;
 		};
 
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001f8b1
+				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001f8b1
+			>;
+		};
+
+		pinctrl_panel: panelgrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x70
+				MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x70
+			>;
+		};
+
+		pinctrl_touchscreenp7: touchscreenp7grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15		0x70
+				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13		0x1b0b0
+			>;
+		};
+
 		pinctrl_uart2: uart2grp {
 			fsl,pins = <
 				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
@@ -109,6 +203,50 @@
 				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
 			>;
 		};
+
+		pinctrl_ac97_running: ac97running {
+			fsl,pins = <
+				MX6QDL_PAD_DI0_PIN2__AUD6_TXD		0x1b0b0
+				MX6QDL_PAD_DI0_PIN3__AUD6_TXFS		0x1b0b0
+				MX6QDL_PAD_DI0_PIN4__AUD6_RXD		0x1b0b0
+				MX6QDL_PAD_DI0_PIN15__AUD6_TXC		0x1b0b0
+				MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b0
+			>;
+		};
+
+		pinctrl_ac97_warm_reset: ac97warmreset {
+			fsl,pins = <
+				MX6QDL_PAD_DI0_PIN2__AUD6_TXD		0x1b0b0
+				MX6QDL_PAD_DI0_PIN3__GPIO4_IO19		0x1b0b0
+				MX6QDL_PAD_DI0_PIN4__AUD6_RXD		0x1b0b0
+				MX6QDL_PAD_DI0_PIN15__AUD6_TXC		0x1b0b0
+				MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b0
+			>;
+		};
+
+		pinctrl_ac97_reset: ac97reset {
+			fsl,pins = <
+				MX6QDL_PAD_DI0_PIN2__GPIO4_IO18		0x1b0b0
+				MX6QDL_PAD_DI0_PIN3__GPIO4_IO19		0x1b0b0
+				MX6QDL_PAD_DI0_PIN4__AUD6_RXD		0x1b0b0
+				MX6QDL_PAD_DI0_PIN15__AUD6_TXC		0x1b0b0
+				MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b0
+			>;
+		};
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	panelchan: lvds-channel@0 {
+		port@4 {
+			reg = <4>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
 	};
 };
 
@@ -122,7 +260,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usbh>;
 	vbus-supply = <&reg_usb_h1_vbus>;
-	clocks = <&clks 201>;
+	clocks = <&clks IMX6QDL_CLK_CKO>;
 	status = "okay";
 };
 
@@ -132,3 +270,18 @@
 	non-removable;
 	status = "okay";
 };
+
+&audmux {
+	status = "okay";
+};
+
+&ssi1 {
+	cell-index = <0>;
+	fsl,mode = "ac97-slave";
+	pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset";
+	pinctrl-0 = <&pinctrl_ac97_running>;
+	pinctrl-1 = <&pinctrl_ac97_reset>;
+	pinctrl-2 = <&pinctrl_ac97_warm_reset>;
+	ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/imx6qdl-wandboard.dtsi b/sys/gnu/dts/arm/imx6qdl-wandboard.dtsi
index 9e096d811bed..8e7c40e114dd 100644
--- a/sys/gnu/dts/arm/imx6qdl-wandboard.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl-wandboard.dtsi
@@ -85,7 +85,7 @@
 	codec: sgtl5000@0a {
 		compatible = "fsl,sgtl5000";
 		reg = <0x0a>;
-		clocks = <&clks 201>;
+		clocks = <&clks IMX6QDL_CLK_CKO>;
 		VDDA-supply = <&reg_2p5v>;
 		VDDIO-supply = <&reg_3p3v>;
 	};
diff --git a/sys/gnu/dts/arm/imx6qdl.dtsi b/sys/gnu/dts/arm/imx6qdl.dtsi
index 4f6ae921656f..ed613ebe0812 100644
--- a/sys/gnu/dts/arm/imx6qdl.dtsi
+++ b/sys/gnu/dts/arm/imx6qdl.dtsi
@@ -261,7 +261,7 @@
 					clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 						 <&clks IMX6QDL_CLK_ECSPI1>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
+					dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
@@ -275,7 +275,7 @@
 					clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 						 <&clks IMX6QDL_CLK_ECSPI2>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
+					dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
@@ -289,7 +289,7 @@
 					clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 						 <&clks IMX6QDL_CLK_ECSPI3>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
+					dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
@@ -303,7 +303,7 @@
 					clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 						 <&clks IMX6QDL_CLK_ECSPI4>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
+					dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
@@ -621,7 +621,7 @@
 					     <0 54 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 127 IRQ_TYPE_LEVEL_HIGH>;
 
-				regulator-1p1@110 {
+				regulator-1p1 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd1p1";
 					regulator-min-microvolt = <800000>;
@@ -635,7 +635,7 @@
 					anatop-max-voltage = <1375000>;
 				};
 
-				regulator-3p0@120 {
+				regulator-3p0 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd3p0";
 					regulator-min-microvolt = <2800000>;
@@ -649,7 +649,7 @@
 					anatop-max-voltage = <3400000>;
 				};
 
-				regulator-2p5@130 {
+				regulator-2p5 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd2p5";
 					regulator-min-microvolt = <2000000>;
@@ -663,7 +663,7 @@
 					anatop-max-voltage = <2750000>;
 				};
 
-				reg_arm: regulator-vddcore@140 {
+				reg_arm: regulator-vddcore {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vddarm";
 					regulator-min-microvolt = <725000>;
@@ -680,7 +680,7 @@
 					anatop-max-voltage = <1450000>;
 				};
 
-				reg_pu: regulator-vddpu@140 {
+				reg_pu: regulator-vddpu {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vddpu";
 					regulator-min-microvolt = <725000>;
@@ -697,7 +697,7 @@
 					anatop-max-voltage = <1450000>;
 				};
 
-				reg_soc: regulator-vddsoc@140 {
+				reg_soc: regulator-vddsoc {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vddsoc";
 					regulator-min-microvolt = <725000>;
@@ -896,7 +896,6 @@
 				#size-cells = <1>;
 				reg = <0x2100000 0x10000>;
 				ranges = <0 0x2100000 0x10000>;
-				interrupt-parent = <&intc>;
 				clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
 					 <&clks IMX6QDL_CLK_CAAM_ACLK>,
 					 <&clks IMX6QDL_CLK_CAAM_IPG>,
@@ -1231,22 +1230,22 @@
 				#size-cells = <0>;
 				reg = <2>;
 
-				ipu1_di0_disp0: endpoint@0 {
+				ipu1_di0_disp0: disp0-endpoint {
 				};
 
-				ipu1_di0_hdmi: endpoint@1 {
+				ipu1_di0_hdmi: hdmi-endpoint {
 					remote-endpoint = <&hdmi_mux_0>;
 				};
 
-				ipu1_di0_mipi: endpoint@2 {
+				ipu1_di0_mipi: mipi-endpoint {
 					remote-endpoint = <&mipi_mux_0>;
 				};
 
-				ipu1_di0_lvds0: endpoint@3 {
+				ipu1_di0_lvds0: lvds0-endpoint {
 					remote-endpoint = <&lvds0_mux_0>;
 				};
 
-				ipu1_di0_lvds1: endpoint@4 {
+				ipu1_di0_lvds1: lvds1-endpoint {
 					remote-endpoint = <&lvds1_mux_0>;
 				};
 			};
@@ -1256,22 +1255,22 @@
 				#size-cells = <0>;
 				reg = <3>;
 
-				ipu1_di0_disp1: endpoint@0 {
+				ipu1_di0_disp1: disp1-endpoint {
 				};
 
-				ipu1_di1_hdmi: endpoint@1 {
+				ipu1_di1_hdmi: hdmi-endpoint {
 					remote-endpoint = <&hdmi_mux_1>;
 				};
 
-				ipu1_di1_mipi: endpoint@2 {
+				ipu1_di1_mipi: mipi-endpoint {
 					remote-endpoint = <&mipi_mux_1>;
 				};
 
-				ipu1_di1_lvds0: endpoint@3 {
+				ipu1_di1_lvds0: lvds0-endpoint {
 					remote-endpoint = <&lvds0_mux_1>;
 				};
 
-				ipu1_di1_lvds1: endpoint@4 {
+				ipu1_di1_lvds1: lvds1-endpoint {
 					remote-endpoint = <&lvds1_mux_1>;
 				};
 			};
diff --git a/sys/gnu/dts/arm/imx6qp-nitrogen6_max.dts b/sys/gnu/dts/arm/imx6qp-nitrogen6_max.dts
new file mode 100644
index 000000000000..a39b86036581
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6qp-nitrogen6_max.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2016 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6qp.dtsi"
+#include "imx6qdl-nitrogen6_max.dtsi"
+
+/ {
+	model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board";
+	compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp";
+};
+
+&pcie {
+	status = "disabled";
+};
+
+&sata {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/imx6qp-sabreauto.dts b/sys/gnu/dts/arm/imx6qp-sabreauto.dts
new file mode 100644
index 000000000000..5ce3840d83d3
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6qp-sabreauto.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6qp.dtsi"
+#include "imx6qdl-sabreauto.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
+	compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
+};
+
+&i2c2 {
+	max7322: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&iomuxc {
+	imx6qdl-sabreauto {
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
+				MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b018
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b018
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b018
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b018
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b018
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b018
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b018
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b018
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b018
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b018
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b018
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b018
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
+			>;
+		};
+	};
+};
+
+&pcie {
+	status = "disabled";
+};
+
+&vgen3_reg {
+	regulator-always-on;
+};
diff --git a/sys/gnu/dts/arm/imx6qp-sabresd.dts b/sys/gnu/dts/arm/imx6qp-sabresd.dts
new file mode 100644
index 000000000000..b23458062f5e
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6qp-sabresd.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6qp.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
+	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
+};
+
+&cpu0 {
+	arm-supply = <&sw2_reg>;
+};
+
+&iomuxc {
+	imx6qdl-sabresd {
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
+				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
+				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
+				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10071
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			>;
+		};
+	};
+};
+
+&pcie {
+	status = "disabled";
+};
diff --git a/sys/gnu/dts/arm/imx6qp.dtsi b/sys/gnu/dts/arm/imx6qp.dtsi
new file mode 100644
index 000000000000..886dbf2eca49
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6qp.dtsi
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6q.dtsi"
+
+/ {
+	soc {
+		ocram2: sram@00940000 {
+			compatible = "mmio-sram";
+			reg = <0x00940000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		ocram3: sram@00960000 {
+			compatible = "mmio-sram";
+			reg = <0x00960000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		ipu1: ipu@02400000 {
+			compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+			clocks = <&clks IMX6QDL_CLK_IPU1>,
+				 <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
+				 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+				 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>,
+				 <&clks IMX6QDL_CLK_PRG0_APB>;
+			clock-names = "bus",
+				      "di0", "di1",
+				      "di0_sel", "di1_sel",
+				      "ldb_di0", "ldb_di1", "prg";
+		};
+
+		ipu2: ipu@02800000 {
+			compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+			clocks = <&clks IMX6QDL_CLK_IPU2>,
+				 <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
+				 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+				 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>,
+				 <&clks IMX6QDL_CLK_PRG1_APB>;
+			clock-names = "bus",
+				      "di0", "di1",
+				      "di0_sel", "di1_sel",
+				      "ldb_di0", "ldb_di1", "prg";
+		};
+
+		pcie: pcie@0x01000000 {
+			compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6sl-warp.dts b/sys/gnu/dts/arm/imx6sl-warp.dts
index 10c69963100f..058bcdceb81a 100644
--- a/sys/gnu/dts/arm/imx6sl-warp.dts
+++ b/sys/gnu/dts/arm/imx6sl-warp.dts
@@ -118,7 +118,7 @@
 	bus-width = <4>;
 	non-removable;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	mmc-pwrseq = <&usdhc3_pwrseq>;
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts b/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts
new file mode 100644
index 000000000000..ba62348d8284
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6sx-nitrogen6sx.dts
@@ -0,0 +1,709 @@
+/*
+ * Copyright (C) 2016 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6sx.dtsi"
+
+/ {
+	model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board";
+	compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx";
+
+	aliases {
+		fb_lcd = &lcdif1;
+		t_lcd = &t_lcd;
+	};
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	backlight-lvds {
+		compatible = "pwm-backlight";
+		pwms = <&pwm4 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		power-supply = <&reg_3p3v>;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "1P8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_can1_3v3: regulator-can1-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "can1-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_can2_3v3: regulator-can2-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "can2-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_wlan: regulator-wlan {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_wlan>;
+		compatible = "regulator-fixed";
+		clocks = <&clks IMX6SX_CLK_CKO>;
+		clock-names = "slow";
+		regulator-name = "wlan-en";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <70000>;
+		gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	sound {
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "imx6sx-nitrogen6sx-sgtl5000";
+		cpu-dai = <&ssi1>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+		mux-int-port = <1>;
+		mux-ext-port = <5>;
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "okay";
+
+	flash: m25p80@0 {
+		compatible = "microchip,sst25vf016b";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "U-Boot";
+			reg = <0x0 0xc0000>;
+			read-only;
+		};
+
+		partition@c0000 {
+			label = "env";
+			reg = <0xc0000 0x2000>;
+			read-only;
+		};
+
+		partition@c2000 {
+			label = "Kernel";
+			reg = <0xc2000 0x11e000>;
+		};
+
+		partition@1e0000 {
+			label = "M4";
+			reg = <0x1e0000 0x20000>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	phy-supply = <&reg_3p3v>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@4 {
+			reg = <4>;
+		};
+
+		ethphy2: ethernet-phy@5 {
+			reg = <5>;
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy2>;
+	phy-supply = <&reg_3p3v>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can1_3v3>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_3v3>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	codec: sgtl5000@0a {
+		compatible = "fsl,sgtl5000";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sgtl5000>;
+		reg = <0x0a>;
+		clocks = <&clks IMX6SX_CLK_CKO2>;
+		VDDA-supply = <&reg_1p8v>;
+		VDDIO-supply = <&reg_1p8v>;
+		VDDD-supply = <&reg_1p8v>;
+		assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>,
+				  <&clks IMX6SX_CLK_CKO2>;
+		assigned-clock-parents = <&clks IMX6SX_CLK_OSC>;
+		assigned-clock-rates = <0>, <24000000>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&lcdif1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif1>;
+	lcd-supply = <&reg_3p3v>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display0 {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&t_lcd>;
+			t_lcd: t_lcd_default {
+				clock-frequency = <74160000>;
+				hactive = <1280>;
+				vactive = <720>;
+				hback-porch = <220>;
+				hfront-porch = <110>;
+				vback-porch = <20>;
+				vfront-porch = <5>;
+				hsync-len = <40>;
+				vsync-len = <5>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	status = "okay";
+};
+
+&ssi1 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1>;
+	status = "okay";
+};
+
+&usbotg2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg2>;
+	dr_mode = "host";
+	disable-over-current;
+	reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "okay";
+};
+
+&usdhc3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <4>;
+	non-removable;
+	keep-power-in-suspend;
+	vmmc-supply = <&reg_wlan>;
+	cap-power-off-card;
+	cap-sdio-irq;
+	status = "okay";
+
+	brcmf: bcrmf@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+		interrupt-parent = <&gpio7>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1271";
+		reg = <2>;
+		interrupt-parent = <&gpio7>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		ref-clock-frequency = <38400000>;
+	};
+};
+
+&usdhc4 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
+	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	vmmc-supply = <&reg_1p8v>;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD	0x1b0b0
+			MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC	0x1b0b0
+			MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS	0x1b0b0
+			MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD	0x1b0b0
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6SX_PAD_KEY_COL1__ECSPI1_MISO		0x100b1
+			MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI		0x100b1
+			MX6SX_PAD_KEY_COL0__ECSPI1_SCLK		0x100b1
+			MX6SX_PAD_KEY_ROW1__GPIO2_IO_16		0x0b0b1
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX6SX_PAD_ENET1_MDIO__ENET1_MDIO	0x1b0b0
+			MX6SX_PAD_ENET1_MDC__ENET1_MDC		0x1b0b0
+			MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0	0x30b1
+			MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1	0x30b1
+			MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2	0x30b1
+			MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3	0x30b1
+			MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC	0x30b1
+			MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN	0x30b1
+			MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0	0x3081
+			MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1	0x3081
+			MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
+			MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
+			MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
+			MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK	0x3081
+			MX6SX_PAD_ENET2_CRS__GPIO2_IO_7		0xb0b0
+			MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4	0xb0b0
+			MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5	0xb0b0
+		>;
+	};
+
+	pinctrl_enet2: enet2grp {
+		fsl,pins = <
+			MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0x30b1
+			MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0x30b1
+			MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0x30b1
+			MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0x30b1
+			MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0x30b1
+			MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0x30b1
+			MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
+			MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
+			MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
+			MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
+			MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
+			MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
+			MX6SX_PAD_ENET2_COL__GPIO2_IO_6		0xb0b0
+			MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8	0xb0b0
+			MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9	0xb0b0
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX6SX_PAD_QSPI1B_DQS__CAN1_TX		0x1b0b0
+			MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX		0x1b0b0
+			MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27	0x1b0b0
+			MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27	0x0b0b0
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX6SX_PAD_QSPI1A_DQS__CAN2_TX		0x1b0b0
+			MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX		0x1b0b0
+			MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24	0x0b0b0
+		>;
+	};
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1	0x1b0b0
+			MX6SX_PAD_NAND_CLE__GPIO4_IO_3		0x1b0b0
+			MX6SX_PAD_NAND_RE_B__GPIO4_IO_12	0x1b0b0
+			MX6SX_PAD_NAND_WE_B__GPIO4_IO_14	0x1b0b0
+			MX6SX_PAD_NAND_WP_B__GPIO4_IO_15	0x1b0b0
+			MX6SX_PAD_NAND_READY_B__GPIO4_IO_13	0x1b0b0
+			MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x1b0b0
+			MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17	0x1b0b0
+			MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18	0x1b0b0
+			MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19	0x1b0b0
+			MX6SX_PAD_SD1_CMD__CCM_CLKO1		0x000b0
+			MX6SX_PAD_SD3_DATA5__GPIO7_IO_7		0x1b0b0
+			/* Test points */
+			MX6SX_PAD_NAND_DATA04__GPIO4_IO_8	0x1b0b0
+			MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25	0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6SX_PAD_GPIO1_IO00__I2C1_SCL		0x4001b8b1
+			MX6SX_PAD_GPIO1_IO01__I2C1_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6SX_PAD_GPIO1_IO02__I2C2_SCL		0x4001b8b1
+			MX6SX_PAD_GPIO1_IO03__I2C2_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6SX_PAD_KEY_COL4__I2C3_SCL		0x4001b8b1
+			MX6SX_PAD_KEY_ROW4__I2C3_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_lcdif1: lcdif1grp {
+		fsl,pins = <
+			MX6SX_PAD_LCD1_CLK__LCDIF1_CLK		0x4001b0b0
+			MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE	0x4001b0b0
+			MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC	0x4001b0b0
+			MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC	0x4001b0b0
+			MX6SX_PAD_LCD1_RESET__GPIO3_IO_27	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22	0x4001b0b0
+			MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23	0x4001b0b0
+		>;
+	};
+
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX6SX_PAD_NAND_DATA05__GPIO4_IO_9	0xb0b0
+			MX6SX_PAD_NAND_DATA06__GPIO4_IO_10	0xb0b0
+			MX6SX_PAD_NAND_DATA07__GPIO4_IO_11	0xb0b0
+		>;
+	};
+
+	pinctrl_pwm4: pwm4grp {
+		fsl,pins = <
+			MX6SX_PAD_GPIO1_IO13__PWM4_OUT		0x110b0
+		>;
+	};
+
+	pinctrl_reg_wlan: reg-wlangrp {
+		fsl,pins = <
+			MX6SX_PAD_SD3_DATA4__GPIO7_IO_6		0x1b0b0
+			MX6SX_PAD_GPIO1_IO11__CCM_CLKO1		0x000b0
+		>;
+	};
+
+	pinctrl_sgtl5000: sgtl5000grp {
+		fsl,pins = <
+			MX6SX_PAD_GPIO1_IO12__CCM_CLKO2		0x000b0
+			MX6SX_PAD_ENET1_COL__GPIO2_IO_0		0x1b0b0
+			MX6SX_PAD_ENET1_CRS__GPIO2_IO_1		0x1b0b0
+			MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22	0xb0b0
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
+			MX6SX_PAD_GPIO1_IO05__UART1_RX		0x1b0b1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6SX_PAD_GPIO1_IO06__UART2_TX		0x1b0b1
+			MX6SX_PAD_GPIO1_IO07__UART2_RX		0x1b0b1
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6SX_PAD_QSPI1B_SS0_B__UART3_TX	0x1b0b1
+			MX6SX_PAD_QSPI1B_SCLK__UART3_RX		0x1b0b1
+		>;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX6SX_PAD_KEY_COL3__UART5_TX		0x1b0b1
+			MX6SX_PAD_KEY_ROW3__UART5_RX		0x1b0b1
+			MX6SX_PAD_SD3_DATA6__UART3_RTS_B	0x1b0b1
+			MX6SX_PAD_SD3_DATA7__UART3_CTS_B	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg1: usbotg1grp {
+		fsl,pins = <
+			MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC	0x1b0b0
+			MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID	0x170b1
+		>;
+	};
+
+	pinctrl_usbotg1_vbus: usbotg1-vbusgrp {
+		fsl,pins = <
+			MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9	0x1b0b0
+		>;
+	};
+
+	pinctrl_usbotg2: usbotg2grp {
+		fsl,pins = <
+			MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26	0xb0b0
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6SX_PAD_SD2_CMD__USDHC2_CMD		0x17059
+			MX6SX_PAD_SD2_CLK__USDHC2_CLK		0x10059
+			MX6SX_PAD_SD2_DATA0__USDHC2_DATA0	0x17059
+			MX6SX_PAD_SD2_DATA1__USDHC2_DATA1	0x17059
+			MX6SX_PAD_SD2_DATA2__USDHC2_DATA2	0x17059
+			MX6SX_PAD_SD2_DATA3__USDHC2_DATA3	0x17059
+			MX6SX_PAD_KEY_COL2__GPIO2_IO_12		0x1b0b0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x10071
+			MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x17071
+			MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x17071
+			MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x17071
+			MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x17071
+			MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x17071
+		>;
+	};
+
+	pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp {
+		fsl,pins = <
+			MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10071
+			MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17071
+			MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B	0x17071
+			MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17071
+			MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17071
+			MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17071
+			MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17071
+			MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x17071
+			MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x17071
+			MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x17071
+			MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x17071
+		>;
+	};
+
+	pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp {
+		fsl,pins = <
+			MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x100b9
+			MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x170b9
+			MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x170b9
+			MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x170b9
+			MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x170b9
+			MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x170b9
+			MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x170b9
+			MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x170b9
+			MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x170b9
+			MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x170b9
+		>;
+	};
+
+	pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp {
+		fsl,pins = <
+			MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x100f9
+			MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x170f9
+			MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x170f9
+			MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x170f9
+			MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x170f9
+			MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x170f9
+			MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x170f9
+			MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x170f9
+			MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x170f9
+			MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x170f9
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6sx-sabreauto.dts b/sys/gnu/dts/arm/imx6sx-sabreauto.dts
index 115f3fd78971..96ea936eeeb0 100644
--- a/sys/gnu/dts/arm/imx6sx-sabreauto.dts
+++ b/sys/gnu/dts/arm/imx6sx-sabreauto.dts
@@ -52,7 +52,7 @@
 	cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	vmmc-supply = <&vcc_sd3>;
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/imx6sx-sdb-sai.dts b/sys/gnu/dts/arm/imx6sx-sdb-sai.dts
new file mode 100644
index 000000000000..0155450d680e
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6sx-sdb-sai.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6sx-sdb.dts"
+
+/ {
+	sound {
+		audio-cpu = <&sai1>;
+	};
+};
+
+&audmux {
+	/* pin conflict with sai */
+	status = "disabled";
+};
+
+&sai1 {
+	status = "okay";
+};
+
+&sdma {
+	gpr = <&gpr>;
+	/* SDMA event remap for SAI1 */
+	fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
+};
+
+&ssi2 {
+	status = "disabled";
+};
diff --git a/sys/gnu/dts/arm/imx6sx-sdb.dts b/sys/gnu/dts/arm/imx6sx-sdb.dts
index 0ad164ab5729..5bb8fd57e7f5 100644
--- a/sys/gnu/dts/arm/imx6sx-sdb.dts
+++ b/sys/gnu/dts/arm/imx6sx-sdb.dts
@@ -18,12 +18,14 @@
 		996000  1250000
 		792000  1175000
 		396000  1175000
+		198000  1175000
 		>;
 	fsl,soc-operating-points = <
 		/* ARM kHz      SOC uV */
 		996000	1250000
 		792000	1175000
 		396000	1175000
+		198000  1175000
 	>;
 };
 
diff --git a/sys/gnu/dts/arm/imx6sx-sdb.dtsi b/sys/gnu/dts/arm/imx6sx-sdb.dtsi
index 94ac4005d9cd..e5eafe4d9a70 100644
--- a/sys/gnu/dts/arm/imx6sx-sdb.dtsi
+++ b/sys/gnu/dts/arm/imx6sx-sdb.dtsi
@@ -184,6 +184,13 @@
 	status = "okay";
 };
 
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
 &i2c4 {
         clock-frequency = <100000>;
         pinctrl-names = "default";
@@ -247,6 +254,12 @@
 	status = "okay";
 };
 
+&sai1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai1>;
+	status = "disabled";
+};
+
 &ssi2 {
 	status = "okay";
 };
@@ -283,7 +296,7 @@
 	non-removable;
 	no-1-8-v;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	status = "okay";
 };
 
@@ -296,7 +309,7 @@
 	cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	vmmc-supply = <&vcc_sd3>;
 	status = "okay";
 };
@@ -378,6 +391,13 @@
 			>;
 		};
 
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW4__I2C3_SDA		0x4001b8b1
+				MX6SX_PAD_KEY_COL4__I2C3_SCL		0x4001b8b1
+			>;
+		};
+
 		pinctrl_i2c4: i2c4grp {
 			fsl,pins = <
 				MX6SX_PAD_CSI_DATA07__I2C4_SDA		0x4001b8b1
@@ -454,6 +474,16 @@
 			>;
 		};
 
+		pinctrl_sai1: sai1grp {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK	0x130b0
+				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC	0x130b0
+				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0	0x120b0
+				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0	0x130b0
+				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK	0x130b0
+			>;
+		};
+
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
 				MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
diff --git a/sys/gnu/dts/arm/imx6sx.dtsi b/sys/gnu/dts/arm/imx6sx.dtsi
index a5f76025a0ce..6a993bfda248 100644
--- a/sys/gnu/dts/arm/imx6sx.dtsi
+++ b/sys/gnu/dts/arm/imx6sx.dtsi
@@ -63,12 +63,14 @@
 				996000  1250000
 				792000  1175000
 				396000  1075000
+				198000	975000
 			>;
 			fsl,soc-operating-points = <
 				/* ARM kHz  SOC uV */
 				996000      1175000
 				792000      1175000
 				396000      1175000
+				198000	    1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
 			clocks = <&clks IMX6SX_CLK_ARM>,
@@ -970,8 +972,7 @@
 					 <&clks 0>, <&clks 0>;
 				clock-names = "bus", "mclk1", "mclk2", "mclk3";
 				dma-names = "rx", "tx";
-				dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
-				dma-source = <&gpr 0 15 0 16>;
+				dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
 				status = "disabled";
 			};
 
@@ -990,8 +991,7 @@
 					 <&clks 0>, <&clks 0>;
 				clock-names = "bus", "mclk1", "mclk2", "mclk3";
 				dma-names = "rx", "tx";
-				dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
-				dma-source = <&gpr 0 17 0 18>;
+				dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
 				status = "disabled";
 			};
 
diff --git a/sys/gnu/dts/arm/imx6ul-14x14-evk.dts b/sys/gnu/dts/arm/imx6ul-14x14-evk.dts
index 6aaa5ec3d846..668a72997590 100644
--- a/sys/gnu/dts/arm/imx6ul-14x14-evk.dts
+++ b/sys/gnu/dts/arm/imx6ul-14x14-evk.dts
@@ -8,7 +8,6 @@
 
 /dts-v1/;
 
-#include <dt-bindings/input/input.h>
 #include "imx6ul.dtsi"
 
 / {
@@ -37,6 +36,45 @@
 			enable-active-high;
 		};
 	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "mx6ul-wm8960";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&dailink_master>;
+		simple-audio-card,frame-master = <&dailink_master>;
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Line", "Line In",
+			"Line", "Line Out",
+			"Speaker", "Speaker",
+			"Headphone", "Headphone Jack";
+		simple-audio-card,routing =
+			"Headphone Jack", "HP_L",
+			"Headphone Jack", "HP_R",
+			"Speaker", "SPK_LP",
+			"Speaker", "SPK_LN",
+			"Speaker", "SPK_RP",
+			"Speaker", "SPK_RN",
+			"LINPUT1", "Mic Jack",
+			"LINPUT3", "Mic Jack",
+			"RINPUT1", "Mic Jack",
+			"RINPUT2", "Mic Jack";
+
+		simple-audio-card,cpu {
+			sound-dai = <&sai2>;
+		};
+
+		dailink_master: simple-audio-card,codec {
+			sound-dai = <&codec>;
+			clocks = <&clks IMX6UL_CLK_SAI2>;
+		};
+	};
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <786432000>;
 };
 
 &cpu0 {
@@ -44,6 +82,20 @@
 	soc-supply = <&reg_soc>;
 };
 
+&i2c2 {
+	clock_frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	codec: wm8960@1a {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8960";
+		reg = <0x1a>;
+		wlf,shared-lrclk;
+	};
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>;
@@ -87,6 +139,16 @@
 	};
 };
 
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+			  <&clks IMX6UL_CLK_SAI2>;
+	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <0>, <12288000>;
+	status = "okay";
+};
+
 &snvs_poweroff {
 	status = "okay";
 };
@@ -131,7 +193,7 @@
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	vmmc-supply = <&reg_sd1_vmmc>;
 	status = "okay";
 };
@@ -141,7 +203,7 @@
 	pinctrl-0 = <&pinctrl_usdhc2>;
 	no-1-8-v;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
+	wakeup-source;
 	status = "okay";
 };
 
@@ -273,6 +335,17 @@
 		>;
 	};
 
+	pinctrl_sai2: sai2grp {
+		fsl,pins = <
+			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
+			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
+			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
+			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
+			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
+			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x17059
+		>;
+	};
+
 	pinctrl_pwm1: pwm1grp {
 		fsl,pins = <
 			MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
diff --git a/sys/gnu/dts/arm/imx6ul-pico-hobbit.dts b/sys/gnu/dts/arm/imx6ul-pico-hobbit.dts
new file mode 100644
index 000000000000..8ce1fec36e86
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6ul-pico-hobbit.dts
@@ -0,0 +1,516 @@
+/*
+ * Copyright 2015 Technexion Ltd.
+ *
+ * Author: Wig Cheng  <wig.cheng@technexion.com>
+ *	   Richard Hu <richard.hu@technexion.com>
+ *	   Tapani Utriainen <tapani@technexion.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+
+/ {
+	model = "Technexion Pico i.MX6UL Board";
+	compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
+
+	memory {
+		reg = <0x80000000 0x10000000>;
+	};
+
+	chosen {
+		stdout-path = &uart6;
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm3 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
+
+	reg_2p5v: regulator-2p5v {
+		compatible = "regulator-fixed";
+		regulator-name = "2P5V";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "3P3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_sd1_vmmc: regulator-sd1-vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb_otg1>;
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 6 0>;
+	};
+
+	sound {
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "imx6ul-sgtl5000";
+		audio-cpu = <&sai1>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"LINE_IN", "Line In Jack",
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+	};
+
+	sys_mclk: clock-sys-mclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24576000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		hobbitled {
+			label = "hobbitled";
+			gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	status = "okay";
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	status = "okay";
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <786432000>;
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+	phy-reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <11>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			max-speed = <100>;
+			interrupt-parent = <&gpio5>;
+			interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pfuze3000@08 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			/* VDD_ARM_SOC_IN*/
+			sw1b_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			/* DRAM */
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* DRAM */
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock_frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	codec: sgtl5000@0a {
+		reg = <0x0a>;
+		compatible = "fsl,sgtl5000";
+		clocks = <&sys_mclk>;
+		VDDA-supply = <&reg_2p5v>;
+		VDDIO-supply = <&reg_3p3v>;
+	};
+};
+
+&i2c3 {
+	clock_frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display0 {
+		bits-per-pixel = <32>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+
+			timing0: timing0 {
+				clock-frequency = <33200000>;
+				hactive = <800>;
+				vactive = <480>;
+				hfront-porch = <210>;
+				hback-porch = <46>;
+				hsync-len = <1>;
+				vback-porch = <22>;
+				vfront-porch = <23>;
+				vsync-len = <1>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>;
+	status = "okay";
+};
+
+&pwm7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm7>;
+	status = "okay";
+};
+
+&pwm8 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm8>;
+	status = "okay";
+};
+
+&sai1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai1>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart6>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1_id>;
+	dr_mode = "otg";
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	no-1-8-v;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&usdhc2 {  /* Wifi SDIO */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet2: enet2grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO	0x1b0b0
+			MX6UL_PAD_ENET1_TX_EN__ENET2_MDC	0x1b0b0
+			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
+			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x800
+			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x79
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX	0x1b020
+			MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX	0x1b020
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
+			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO02__I2C1_SCL		0x4001b8b0
+			MX6UL_PAD_GPIO1_IO03__I2C1_SDA		0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
+			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__I2C3_SCL	0x4001b8b0
+			MX6UL_PAD_UART1_RX_DATA__I2C3_SDA	0x4001b8b0
+			>;
+	};
+
+	pinctrl_lcdif_dat: lcdifdatgrp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00	0x79
+			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x79
+			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x79
+			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x79
+			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x79
+			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x79
+			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x79
+			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x79
+			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x79
+			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x79
+			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x79
+			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x79
+			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x79
+			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x79
+			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x79
+			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x79
+			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x79
+			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x79
+			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x79
+			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x79
+			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x79
+			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x79
+			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x79
+			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x79
+		>;
+	};
+
+	pinctrl_lcdif_ctrl: lcdifctrlgrp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x79
+			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x79
+			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x79
+			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x79
+			/* LCD reset */
+			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x79
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_ALE__PWM3_OUT		0x110b0
+		>;
+	};
+
+	pinctrl_pwm7: pwm7grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT	0x110b0
+		>;
+	};
+
+	pinctrl_pwm8: pwm8grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_RX_ER__PWM8_OUT		0x110b0
+		>;
+	};
+
+	pinctrl_sai1: sai1grp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC	0x1b0b0
+			MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK	0x1b0b0
+			MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA	0x110b0
+			MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA	0x1f0b8
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b0
+			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b0
+			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b0
+			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX	0x1b0b1
+			MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX	0x1b0b1
+			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
+			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
+		>;
+	};
+
+	pinctrl_uart6: uart6grp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x1b0b1
+			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x1b0b1
+		>;
+	};
+
+	pinctrl_usb_otg1: usbotg1grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO06__GPIO1_IO06	0x10b0
+			>;
+	};
+
+	pinctrl_usb_otg1_id: usbotg1idgrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10071
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
+			MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B	0x03029
+			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
+			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
+			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
+			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10059
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6ul-pinfunc.h b/sys/gnu/dts/arm/imx6ul-pinfunc.h
index 20c7da1affce..0034eeb84542 100644
--- a/sys/gnu/dts/arm/imx6ul-pinfunc.h
+++ b/sys/gnu/dts/arm/imx6ul-pinfunc.h
@@ -14,925 +14,925 @@
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
-#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10				0x0014 0x02a0 0x0000 5 0
-#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11				0x0018 0x02a4 0x0000 5 0
+#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10		0x0014 0x02a0 0x0000 5 0
+#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11		0x0018 0x02a4 0x0000 5 0
 
-#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00				0x001c 0x02a8 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01				0x0020 0x02ac 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02				0x0024 0x02b0 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03				0x0028 0x02b4 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04				0x002c 0x02b8 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05				0x0030 0x02bc 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06				0x0034 0x02c0 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07				0x0038 0x02c4 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08				0x003c 0x02c8 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09				0x0040 0x02cc 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00		0x001c 0x02a8 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01		0x0020 0x02ac 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02		0x0024 0x02b0 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03		0x0028 0x02b4 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04		0x002c 0x02b8 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05		0x0030 0x02bc 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06		0x0034 0x02c0 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07		0x0038 0x02c4 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08		0x003c 0x02c8 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09		0x0040 0x02cc 0x0000 5 0
 
-#define MX6UL_PAD_JTAG_MOD__SJC_MOD                              	0x0044 0x02d0 0x0000 0 0
-#define MX6UL_PAD_JTAG_MOD__GPT2_CLK                             	0x0044 0x02d0 0x05a0 1 0
-#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT                            	0x0044 0x02d0 0x0000 2 0
-#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M                    	0x0044 0x02d0 0x0000 3 0
-#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY                         	0x0044 0x02d0 0x04c0 4 0
-#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10                           	0x0044 0x02d0 0x0000 5 0
-#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00                     	0x0044 0x02d0 0x0000 6 0
-#define MX6UL_PAD_JTAG_TMS__SJC_TMS                              	0x0048 0x02d4 0x0000 0 0
-#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1                        	0x0048 0x02d4 0x0598 1 0
-#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK                            	0x0048 0x02d4 0x0000 2 0
-#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1                            	0x0048 0x02d4 0x0000 3 0
-#define MX6UL_PAD_JTAG_TMS__CCM_WAIT                             	0x0048 0x02d4 0x0000 4 0
-#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11                           	0x0048 0x02d4 0x0000 5 0
-#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01                     	0x0048 0x02d4 0x0000 6 0
-#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT                            	0x0048 0x02d4 0x0000 8 0
-#define MX6UL_PAD_JTAG_TDO__SJC_TDO                              	0x004c 0x02d8 0x0000 0 0
-#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2                        	0x004c 0x02d8 0x059c 1 0
-#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC                         	0x004c 0x02d8 0x05fc 2 0
-#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2                            	0x004c 0x02d8 0x0000 3 0
-#define MX6UL_PAD_JTAG_TDO__CCM_STOP                             	0x004c 0x02d8 0x0000 4 0
-#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12                           	0x004c 0x02d8 0x0000 5 0
-#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT                            	0x004c 0x02d8 0x0000 6 0
-#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT                            	0x004c 0x02d8 0x0000 8 0
-#define MX6UL_PAD_JTAG_TDI__SJC_TDI                              	0x0050 0x02dc 0x0000 0 0
-#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1                        	0x0050 0x02dc 0x0000 1 0
-#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK                         	0x0050 0x02dc 0x05f8 2 0
-#define MX6UL_PAD_JTAG_TDI__PWM6_OUT                             	0x0050 0x02dc 0x0000 4 0
-#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13                           	0x0050 0x02dc 0x0000 5 0
-#define MX6UL_PAD_JTAG_TDI__MQS_LEFT                             	0x0050 0x02dc 0x0000 6 0
-#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL                      	0x0050 0x02dc 0x0000 8 0
-#define MX6UL_PAD_JTAG_TCK__SJC_TCK                              	0x0054 0x02e0 0x0000 0 0
-#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2                        	0x0054 0x02e0 0x0000 1 0
-#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA                         	0x0054 0x02e0 0x0000 2 0
-#define MX6UL_PAD_JTAG_TCK__PWM7_OUT                             	0x0054 0x02e0 0x0000 4 0
-#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14                           	0x0054 0x02e0 0x0000 5 0
-#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL                      	0x0054 0x02e0 0x0000 8 0
-#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB                         	0x0058 0x02e4 0x0000 0 0
-#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3                     	0x0058 0x02e4 0x0000 1 0
-#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA                      	0x0058 0x02e4 0x0000 2 0
-#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT                          	0x0058 0x02e4 0x0000 4 0
-#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15                        	0x0058 0x02e4 0x0000 5 0
-#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS                  	0x0058 0x02e4 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL                           	0x005c 0x02e8 0x05ac 0 1
-#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1                      	0x005c 0x02e8 0x058c 1 0
-#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID                     	0x005c 0x02e8 0x04b8 2 0
-#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1                     	0x005c 0x02e8 0x0574 3 0
-#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT                          	0x005c 0x02e8 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00                         	0x005c 0x02e8 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN               	0x005c 0x02e8 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET                   	0x005c 0x02e8 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B                       	0x005c 0x02e8 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA                           	0x0060 0x02ec 0x05b0 0 1
-#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1                      	0x0060 0x02ec 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC                        	0x0060 0x02ec 0x0664 2 0
-#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2                     	0x0060 0x02ec 0x057c 3 0
-#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT                           	0x0060 0x02ec 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                         	0x0060 0x02ec 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT              	0x0060 0x02ec 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET                    	0x0060 0x02ec 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B                       	0x0060 0x02ec 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL                           	0x0064 0x02f0 0x05a4 0 0
-#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2                      	0x0064 0x02f0 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR                       	0x0064 0x02f0 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M                  	0x0064 0x02f0 0x0000 3 0
-#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP                          	0x0064 0x02f0 0x066c 4 0
-#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                         	0x0064 0x02f0 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00                   	0x0064 0x02f0 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET                   	0x0064 0x02f0 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX                           	0x0064 0x02f0 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX                           	0x0064 0x02f0 0x0624 8 0
-#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA                           	0x0068 0x02f4 0x05a8 0 1
-#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3                      	0x0068 0x02f4 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC                        	0x0068 0x02f4 0x0660 2 0
-#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B                        	0x0068 0x02f4 0x0668 4 0
-#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                         	0x0068 0x02f4 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK                    	0x0068 0x02f4 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK                     	0x0068 0x02f4 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX                           	0x0068 0x02f4 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX                           	0x0068 0x02f4 0x0624 8 1
-#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1                     	0x006c 0x02f8 0x0574 0 1
-#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT                           	0x006c 0x02f8 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR                       	0x006c 0x02f8 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B                     	0x006c 0x02f8 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                         	0x006c 0x02f8 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN               	0x006c 0x02f8 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX                           	0x006c 0x02f8 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX                           	0x006c 0x02f8 0x0644 8 2
-#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2                     	0x0070 0x02fc 0x057c 0 1
-#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT                           	0x0070 0x02fc 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID                     	0x0070 0x02fc 0x04bc 2 0
-#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD                          	0x0070 0x02fc 0x0530 3 0
-#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT                     	0x0070 0x02fc 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05                         	0x0070 0x02fc 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT              	0x0070 0x02fc 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX                           	0x0070 0x02fc 0x0644 8 3
-#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX                           	0x0070 0x02fc 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO                         	0x0074 0x0300 0x0578 0 0
-#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO                         	0x0074 0x0300 0x0580 1 0
-#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE                   	0x0074 0x0300 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK                           	0x0074 0x0300 0x0000 3 0
-#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP                          	0x0074 0x0300 0x069c 4 0
-#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06                         	0x0074 0x0300 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT                           	0x0074 0x0300 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B                       	0x0074 0x0300 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS                      	0x0074 0x0300 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS                      	0x0074 0x0300 0x0620 8 0
-#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC                          	0x0078 0x0304 0x0000 0 0
-#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC                          	0x0078 0x0304 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE                  	0x0078 0x0304 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK                         	0x0078 0x0304 0x0528 3 0
-#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B                        	0x0078 0x0304 0x0674 4 1
-#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07                         	0x0078 0x0304 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO07__CCM_STOP                           	0x0078 0x0304 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS                      	0x0078 0x0304 0x0620 8 1
-#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS                      	0x0078 0x0304 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT                           	0x007c 0x0308 0x0000 0 0
-#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B                       	0x007c 0x0308 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT                          	0x007c 0x0308 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC                          	0x007c 0x0308 0x052c 3 1
-#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT                     	0x007c 0x0308 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08                         	0x007c 0x0308 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY                       	0x007c 0x0308 0x04c0 6 1
-#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS                      	0x007c 0x0308 0x0640 8 1
-#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS                      	0x007c 0x0308 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT                           	0x0080 0x030c 0x0000 0 0
-#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY                     	0x0080 0x030c 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN                           	0x0080 0x030c 0x0618 2 0
-#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC                          	0x0080 0x030c 0x0524 3 1
-#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B                     	0x0080 0x030c 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09                         	0x0080 0x030c 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B                     	0x0080 0x030c 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS                      	0x0080 0x030c 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS                      	0x0080 0x030c 0x0640 8 2
-#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX                        	0x0084 0x0310 0x0000 0 0
-#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX                        	0x0084 0x0310 0x0624 0 2
-#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02                   	0x0084 0x0310 0x0000 1 0
-#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL                        	0x0084 0x0310 0x05b4 2 0
-#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02                      	0x0084 0x0310 0x0000 3 0
-#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1                   	0x0084 0x0310 0x0000 4 0
-#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16                      	0x0084 0x0310 0x0000 5 0
-#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT                       	0x0084 0x0310 0x0000 8 0
-#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX                        	0x0088 0x0314 0x0624 0 3
-#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX                        	0x0088 0x0314 0x0000 0 0
-#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03                   	0x0088 0x0314 0x0000 1 0
-#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA                        	0x0088 0x0314 0x05b8 2 0
-#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03                      	0x0088 0x0314 0x0000 3 0
-#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK                        	0x0088 0x0314 0x0594 4 0
-#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17                      	0x0088 0x0314 0x0000 5 0
-#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN                        	0x0088 0x0314 0x0000 8 0
-#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS                     	0x008c 0x0318 0x0000 0 0
-#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS                     	0x008c 0x0318 0x0620 0 2
-#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK                      	0x008c 0x0318 0x0000 1 0
-#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP                         	0x008c 0x0318 0x066c 2 1
-#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04                        	0x008c 0x0318 0x0000 3 0
-#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN              	0x008c 0x0318 0x0000 4 0
-#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18                        	0x008c 0x0318 0x0000 5 0
-#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP                         	0x008c 0x0318 0x0000 8 0
-#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS                     	0x0090 0x031c 0x0620 0 3
-#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS                     	0x0090 0x031c 0x0000 0 0
-#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER                       	0x0090 0x031c 0x0000 1 0
-#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B                       	0x0090 0x031c 0x0668 2 1
-#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05                        	0x0090 0x031c 0x0000 3 0
-#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT             	0x0090 0x031c 0x0000 4 0
-#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19                        	0x0090 0x031c 0x0000 5 0
-#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B                       	0x0090 0x031c 0x0000 8 0
-#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX                        	0x0094 0x0320 0x0000 0 0
-#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX                        	0x0094 0x0320 0x062c 0 0
-#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02                   	0x0094 0x0320 0x0000 1 0
-#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL                        	0x0094 0x0320 0x05bc 2 0
-#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06                      	0x0094 0x0320 0x0000 3 0
-#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1                   	0x0094 0x0320 0x058c 4 1
-#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20                      	0x0094 0x0320 0x0000 5 0
-#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0                      	0x0094 0x0320 0x0000 8 0
-#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX                        	0x0098 0x0324 0x062c 0 1
-#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX                        	0x0098 0x0324 0x0000 0 0
-#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03                   	0x0098 0x0324 0x0000 1 0
-#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA                        	0x0098 0x0324 0x05c0 2 0
-#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07                      	0x0098 0x0324 0x0000 3 0
-#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2                   	0x0098 0x0324 0x0590 4 0
-#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21                      	0x0098 0x0324 0x0000 5 0
-#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE                        	0x0098 0x0324 0x0000 7 0
-#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK                     	0x0098 0x0324 0x0000 8 0
-#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS                     	0x009c 0x0328 0x0000 0 0
-#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS                     	0x009c 0x0328 0x0628 0 0
-#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS                         	0x009c 0x0328 0x0000 1 0
-#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX                       	0x009c 0x0328 0x0000 2 0
-#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08                        	0x009c 0x0328 0x0000 3 0
-#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2                     	0x009c 0x0328 0x0000 4 0
-#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22                        	0x009c 0x0328 0x0000 5 0
-#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B                          	0x009c 0x0328 0x0000 7 0
-#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI                       	0x009c 0x0328 0x0000 8 0
-#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS                     	0x00a0 0x032c 0x0628 0 1
-#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS                     	0x00a0 0x032c 0x0000 0 0
-#define MX6UL_PAD_UART2_RTS_B__ENET1_COL                         	0x00a0 0x032c 0x0000 1 0
-#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX                       	0x00a0 0x032c 0x0588 2 0
-#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09                        	0x00a0 0x032c 0x0000 3 0
-#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3                     	0x00a0 0x032c 0x0000 4 0
-#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23                        	0x00a0 0x032c 0x0000 5 0
-#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL                          	0x00a0 0x032c 0x0000 7 0
-#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO                       	0x00a0 0x032c 0x0000 8 0
-#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX                        	0x00a4 0x0330 0x0000 0 0
-#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX                        	0x00a4 0x0330 0x0634 0 0
-#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02                   	0x00a4 0x0330 0x0000 1 0
-#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD                   	0x00a4 0x0330 0x0000 2 0
-#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01                      	0x00a4 0x0330 0x0000 3 0
-#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS                   	0x00a4 0x0330 0x0000 4 0
-#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS                   	0x00a4 0x0330 0x0628 4 2
-#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24                      	0x00a4 0x0330 0x0000 5 0
-#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT                    	0x00a4 0x0330 0x0000 7 0
-#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID                  	0x00a4 0x0330 0x0000 8 0
-#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX                        	0x00a8 0x0334 0x0634 0 1
-#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX                        	0x00a8 0x0334 0x0000 0 0
-#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03                   	0x00a8 0x0334 0x0000 1 0
-#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD                   	0x00a8 0x0334 0x0000 2 0
-#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00                      	0x00a8 0x0334 0x0000 3 0
-#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS                   	0x00a8 0x0334 0x0628 4 3
-#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS                   	0x00a8 0x0334 0x0000 4 0
-#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25                      	0x00a8 0x0334 0x0000 5 0
-#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT                       	0x00a8 0x0334 0x0000 8 0
-#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS                     	0x00ac 0x0338 0x0000 0 0
-#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS                     	0x00ac 0x0338 0x0630 0 0
-#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK                      	0x00ac 0x0338 0x0000 1 0
-#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX                       	0x00ac 0x0338 0x0000 2 0
-#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10                        	0x00ac 0x0338 0x0000 3 0
-#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN              	0x00ac 0x0338 0x0000 4 0
-#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26                        	0x00ac 0x0338 0x0000 5 0
-#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT                         	0x00ac 0x0338 0x0000 8 0
-#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS                     	0x00b0 0x033c 0x0630 0 1
-#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS                     	0x00b0 0x033c 0x0000 0 0
-#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER                       	0x00b0 0x033c 0x0000 1 0
-#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX                       	0x00b0 0x033c 0x0584 2 0
-#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11                        	0x00b0 0x033c 0x0000 3 0
-#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT             	0x00b0 0x033c 0x0000 4 0
-#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27                        	0x00b0 0x033c 0x0000 5 0
-#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B                      	0x00b0 0x033c 0x0000 8 0
-#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX                        	0x00b4 0x0340 0x0000 0 0
-#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX                        	0x00b4 0x0340 0x063c 0 0
-#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02                   	0x00b4 0x0340 0x0000 1 0
-#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL                        	0x00b4 0x0340 0x05a4 2 1
-#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12                      	0x00b4 0x0340 0x0000 3 0
-#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02             	0x00b4 0x0340 0x0000 4 0
-#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28                      	0x00b4 0x0340 0x0000 5 0
-#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK                     	0x00b4 0x0340 0x0000 8 0
-#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX                        	0x00b8 0x0344 0x063c 0 1
-#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX                        	0x00b8 0x0344 0x0000 0 0
-#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03                   	0x00b8 0x0344 0x0000 1 0
-#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA                        	0x00b8 0x0344 0x05a8 2 2
-#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13                      	0x00b8 0x0344 0x0000 3 0
-#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01             	0x00b8 0x0344 0x0000 4 0
-#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29                      	0x00b8 0x0344 0x0000 5 0
-#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0                      	0x00b8 0x0344 0x0000 8 0
-#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30                      	0x00bc 0x0348 0x0000 5 0
-#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI                     	0x00bc 0x0348 0x0000 8 0
-#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX                        	0x00bc 0x0348 0x0000 0 0
-#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX                        	0x00bc 0x0348 0x0644 0 4
-#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS                       	0x00bc 0x0348 0x0000 1 0
-#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL                        	0x00bc 0x0348 0x05ac 2 2
-#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14                      	0x00bc 0x0348 0x0000 3 0
-#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00             	0x00bc 0x0348 0x0000 4 0
-#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX                        	0x00c0 0x034c 0x0644 0 5
-#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX                        	0x00c0 0x034c 0x0000 0 0
-#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL                       	0x00c0 0x034c 0x0000 1 0
-#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA                        	0x00c0 0x034c 0x05b0 2 2
-#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15                      	0x00c0 0x034c 0x0000 3 0
-#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB                 	0x00c0 0x034c 0x0000 4 0
-#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31                      	0x00c0 0x034c 0x0000 5 0
-#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO                     	0x00c0 0x034c 0x0000 8 0
-#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00                  	0x00c4 0x0350 0x0000 0 0
-#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS                  	0x00c4 0x0350 0x0638 1 0
-#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS                  	0x00c4 0x0350 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT                       	0x00c4 0x0350 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16                     	0x00c4 0x0350 0x0000 3 0
-#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX                    	0x00c4 0x0350 0x0000 4 0
-#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00                     	0x00c4 0x0350 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00                      	0x00c4 0x0350 0x0000 6 0
-#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL                    	0x00c4 0x0350 0x0000 8 0
-#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01                  	0x00c8 0x0354 0x0000 0 0
-#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS                  	0x00c8 0x0354 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS                  	0x00c8 0x0354 0x0638 1 1
-#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT                       	0x00c8 0x0354 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17                     	0x00c8 0x0354 0x0000 3 0
-#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX                    	0x00c8 0x0354 0x0584 4 1
-#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01                     	0x00c8 0x0354 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00                      	0x00c8 0x0354 0x0000 6 0
-#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL                    	0x00c8 0x0354 0x0000 8 0
-#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN                       	0x00cc 0x0358 0x0000 0 0
-#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS                     	0x00cc 0x0358 0x0640 1 3
-#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS                     	0x00cc 0x0358 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18                        	0x00cc 0x0358 0x0000 3 0
-#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX                       	0x00cc 0x0358 0x0000 4 0
-#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02                        	0x00cc 0x0358 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01                         	0x00cc 0x0358 0x0000 6 0
-#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT                    	0x00cc 0x0358 0x0000 8 0
-#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00                  	0x00d0 0x035c 0x0000 0 0
-#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS                  	0x00d0 0x035c 0x0000 1 0
-#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                  	0x00d0 0x035c 0x0640 1 4
-#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19                     	0x00d0 0x035c 0x0000 3 0
-#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX                    	0x00d0 0x035c 0x0588 4 1
-#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03                     	0x00d0 0x035c 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01                      	0x00d0 0x035c 0x0000 6 0
-#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT                 	0x00d0 0x035c 0x0000 8 0
-#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01                  	0x00d4 0x0360 0x0000 0 0
-#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS                  	0x00d4 0x0360 0x0000 1 0
-#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS                  	0x00d4 0x0360 0x0648 1 2
-#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT                       	0x00d4 0x0360 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20                     	0x00d4 0x0360 0x0000 3 0
-#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO                     	0x00d4 0x0360 0x0580 4 1
-#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04                     	0x00d4 0x0360 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02                      	0x00d4 0x0360 0x0000 6 0
-#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB           	0x00d4 0x0360 0x0000 8 0
-#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN                       	0x00d8 0x0364 0x0000 0 0
-#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS                     	0x00d8 0x0364 0x0648 1 3
-#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS                     	0x00d8 0x0364 0x0000 1 0
-#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT                          	0x00d8 0x0364 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21                        	0x00d8 0x0364 0x0000 3 0
-#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC                         	0x00d8 0x0364 0x0000 4 0
-#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05                        	0x00d8 0x0364 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02                         	0x00d8 0x0364 0x0000 6 0
-#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB              	0x00d8 0x0364 0x0000 8 0
-#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK                     	0x00dc 0x0368 0x0000 0 0
-#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS                    	0x00dc 0x0368 0x0000 1 0
-#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS                    	0x00dc 0x0368 0x0650 1 0
-#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT                         	0x00dc 0x0368 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22                       	0x00dc 0x0368 0x0000 3 0
-#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                   	0x00dc 0x0368 0x0574 4 2
-#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06                       	0x00dc 0x0368 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03                        	0x00dc 0x0368 0x0000 6 0
-#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK                         	0x00dc 0x0368 0x0000 8 0
-#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER                       	0x00e0 0x036c 0x0000 0 0
-#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS                     	0x00e0 0x036c 0x0650 1 1
-#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS                     	0x00e0 0x036c 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT                          	0x00e0 0x036c 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23                        	0x00e0 0x036c 0x0000 3 0
-#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE                           	0x00e0 0x036c 0x0000 4 0
-#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07                        	0x00e0 0x036c 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03                         	0x00e0 0x036c 0x0000 6 0
-#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2                     	0x00e0 0x036c 0x0000 8 0
-#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00                  	0x00e4 0x0370 0x0000 0 0
-#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX                       	0x00e4 0x0370 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX                    	0x00e4 0x0370 0x064c 1 1
-#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD                	0x00e4 0x0370 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL                       	0x00e4 0x0370 0x05b4 3 1
-#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO                     	0x00e4 0x0370 0x0578 4 1
-#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08                     	0x00e4 0x0370 0x0000 5 0
-#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04                      	0x00e4 0x0370 0x0000 6 0
-#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR                   	0x00e4 0x0370 0x0000 8 0
-#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01                  	0x00e8 0x0374 0x0000 0 0
-#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX                       	0x00e8 0x0374 0x064c 1 2
-#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX                       	0x00e8 0x0374 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK                 	0x00e8 0x0374 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA                       	0x00e8 0x0374 0x05b8 3 1
-#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC                      	0x00e8 0x0374 0x0000 4 0
-#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09                     	0x00e8 0x0374 0x0000 5 0
-#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04                      	0x00e8 0x0374 0x0000 6 0
-#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC                    	0x00e8 0x0374 0x0000 8 0
-#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN                       	0x00ec 0x0378 0x0000 0 0
-#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX                          	0x00ec 0x0378 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX                          	0x00ec 0x0378 0x0654 1 0
-#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B                  	0x00ec 0x0378 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL                          	0x00ec 0x0378 0x05bc 3 1
-#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26                        	0x00ec 0x0378 0x0000 4 0
-#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10                        	0x00ec 0x0378 0x0000 5 0
-#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05                         	0x00ec 0x0378 0x0000 6 0
-#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M                 	0x00ec 0x0378 0x0000 8 0
-#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00                  	0x00f0 0x037c 0x0000 0 0
-#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX                       	0x00f0 0x037c 0x0654 1 1
-#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX                       	0x00f0 0x037c 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN                	0x00f0 0x037c 0x0000 2 0
-#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA                       	0x00f0 0x037c 0x05c0 3 1
-#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02                     	0x00f0 0x037c 0x0000 4 0
-#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11                     	0x00f0 0x037c 0x0000 5 0
-#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05                      	0x00f0 0x037c 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01                  	0x00f4 0x0380 0x0000 0 0
-#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX                       	0x00f4 0x0380 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX                       	0x00f4 0x0380 0x065c 1 0
-#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD                	0x00f4 0x0380 0x0000 2 0
-#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK                    	0x00f4 0x0380 0x0564 3 0
-#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03                     	0x00f4 0x0380 0x0000 4 0
-#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12                     	0x00f4 0x0380 0x0000 5 0
-#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06                      	0x00f4 0x0380 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR                   	0x00f4 0x0380 0x0000 8 0
-#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN                       	0x00f8 0x0384 0x0000 0 0
-#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX                          	0x00f8 0x0384 0x065c 1 1
-#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX                          	0x00f8 0x0384 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK                    	0x00f8 0x0384 0x0000 2 0
-#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI                       	0x00f8 0x0384 0x056c 3 0
-#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN                  	0x00f8 0x0384 0x0000 4 0
-#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13                        	0x00f8 0x0384 0x0000 5 0
-#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06                         	0x00f8 0x0384 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC                       	0x00f8 0x0384 0x0000 8 0
-#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK                     	0x00fc 0x0388 0x0000 0 0
-#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS                    	0x00fc 0x0388 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS                    	0x00fc 0x0388 0x0658 1 0
-#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B                 	0x00fc 0x0388 0x0000 2 0
-#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO                      	0x00fc 0x0388 0x0568 3 0
-#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2                   	0x00fc 0x0388 0x057c 4 2
-#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14                       	0x00fc 0x0388 0x0000 5 0
-#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07                        	0x00fc 0x0388 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID                   	0x00fc 0x0388 0x0000 8 0
-#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER                       	0x0100 0x038c 0x0000 0 0
-#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS                     	0x0100 0x038c 0x0658 1 1
-#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS                     	0x0100 0x038c 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN                   	0x0100 0x038c 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0                        	0x0100 0x038c 0x0000 3 0
-#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25                        	0x0100 0x038c 0x0000 4 0
-#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15                        	0x0100 0x038c 0x0000 5 0
-#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07                         	0x0100 0x038c 0x0000 6 0
-#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY                    	0x0100 0x038c 0x0000 8 0
-#define MX6UL_PAD_LCD_CLK__LCDIF_CLK                             	0x0104 0x0390 0x0000 0 0
-#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN                          	0x0104 0x0390 0x0000 1 0
-#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX                              	0x0104 0x0390 0x0000 2 0
-#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX                              	0x0104 0x0390 0x063c 2 2
-#define MX6UL_PAD_LCD_CLK__SAI3_MCLK                             	0x0104 0x0390 0x0000 3 0
-#define MX6UL_PAD_LCD_CLK__EIM_CS2_B                             	0x0104 0x0390 0x0000 4 0
-#define MX6UL_PAD_LCD_CLK__GPIO3_IO00                            	0x0104 0x0390 0x0000 5 0
-#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB                  	0x0104 0x0390 0x0000 8 0
-#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE                       	0x0108 0x0394 0x0000 0 0
-#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E                         	0x0108 0x0394 0x0000 1 0
-#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX                           	0x0108 0x0394 0x063c 2 3
-#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX                           	0x0108 0x0394 0x0000 2 0
-#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC                       	0x0108 0x0394 0x060c 3 0
-#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B                          	0x0108 0x0394 0x0000 4 0
-#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01                         	0x0108 0x0394 0x0000 5 0
-#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY                         	0x0108 0x0394 0x0000 8 0
-#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC                         	0x010c 0x0398 0x05dc 0 0
-#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS                            	0x010c 0x0398 0x0000 1 0
-#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS                       	0x010c 0x0398 0x0000 2 0
-#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS                       	0x010c 0x0398 0x0638 2 2
-#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK                        	0x010c 0x0398 0x0608 3 0
-#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB                	0x010c 0x0398 0x0000 4 0
-#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02                          	0x010c 0x0398 0x0000 5 0
-#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1                          	0x010c 0x0398 0x0000 8 0
-#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC                         	0x0110 0x039c 0x0000 0 0
-#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY                          	0x0110 0x039c 0x05dc 1 1
-#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS                       	0x0110 0x039c 0x0638 2 3
-#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS                       	0x0110 0x039c 0x0000 2 0
-#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA                        	0x0110 0x039c 0x0000 3 0
-#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B                        	0x0110 0x039c 0x0000 4 0
-#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03                          	0x0110 0x039c 0x0000 5 0
-#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2                          	0x0110 0x039c 0x0000 8 0
-#define MX6UL_PAD_LCD_RESET__LCDIF_RESET                         	0x0114 0x03a0 0x0000 0 0
-#define MX6UL_PAD_LCD_RESET__LCDIF_CS                            	0x0114 0x03a0 0x0000 1 0
-#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI                    	0x0114 0x03a0 0x0000 2 0
-#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA                        	0x0114 0x03a0 0x0000 3 0
-#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY                      	0x0114 0x03a0 0x0000 4 0
-#define MX6UL_PAD_LCD_RESET__GPIO3_IO04                          	0x0114 0x03a0 0x0000 5 0
-#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3                          	0x0114 0x03a0 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00                       	0x0118 0x03a4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA00__PWM1_OUT                           	0x0118 0x03a4 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN               	0x0118 0x03a4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA00__I2C3_SDA                           	0x0118 0x03a4 0x05b8 4 2
-#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05                         	0x0118 0x03a4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00                       	0x0118 0x03a4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK                          	0x0118 0x03a4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01                       	0x011c 0x03a8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA01__PWM2_OUT                           	0x011c 0x03a8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT              	0x011c 0x03a8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA01__I2C3_SCL                           	0x011c 0x03a8 0x05b4 4 2
-#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06                         	0x011c 0x03a8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01                       	0x011c 0x03a8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC                       	0x011c 0x03a8 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02                       	0x0120 0x03ac 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA02__PWM3_OUT                           	0x0120 0x03ac 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN               	0x0120 0x03ac 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA02__I2C4_SDA                           	0x0120 0x03ac 0x05c0 4 2
-#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07                         	0x0120 0x03ac 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02                       	0x0120 0x03ac 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK                       	0x0120 0x03ac 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03                       	0x0124 0x03b0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA03__PWM4_OUT                           	0x0124 0x03b0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT              	0x0124 0x03b0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA03__I2C4_SCL                           	0x0124 0x03b0 0x05bc 4 2
-#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08                         	0x0124 0x03b0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03                       	0x0124 0x03b0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA                       	0x0124 0x03b0 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04                       	0x0128 0x03b4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS                      	0x0128 0x03b4 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS                      	0x0128 0x03b4 0x0658 1 2
-#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN               	0x0128 0x03b4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK                       	0x0128 0x03b4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09                         	0x0128 0x03b4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04                       	0x0128 0x03b4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA                       	0x0128 0x03b4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05                       	0x012c 0x03b8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS                      	0x012c 0x03b8 0x0658 1 3
-#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS                      	0x012c 0x03b8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT              	0x012c 0x03b8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT                          	0x012c 0x03b8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10                         	0x012c 0x03b8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05                       	0x012c 0x03b8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1                         	0x012c 0x03b8 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06                       	0x0130 0x03bc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS                      	0x0130 0x03bc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS                      	0x0130 0x03bc 0x0650 1 2
-#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN               	0x0130 0x03bc 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK                         	0x0130 0x03bc 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11                         	0x0130 0x03bc 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06                       	0x0130 0x03bc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2                         	0x0130 0x03bc 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07                       	0x0134 0x03c0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS                      	0x0134 0x03c0 0x0650 1 3
-#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS                      	0x0134 0x03c0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT              	0x0134 0x03c0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK                      	0x0134 0x03c0 0x061c 4 0
-#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12                         	0x0134 0x03c0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07                       	0x0134 0x03c0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3                         	0x0134 0x03c0 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08                       	0x0138 0x03c4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA08__SPDIF_IN                           	0x0138 0x03c4 0x0618 1 2
-#define MX6UL_PAD_LCD_DATA08__CSI_DATA16                         	0x0138 0x03c4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA08__EIM_DATA00                         	0x0138 0x03c4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13                         	0x0138 0x03c4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08                       	0x0138 0x03c4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX                        	0x0138 0x03c4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09                       	0x013c 0x03c8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK                          	0x013c 0x03c8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA09__CSI_DATA17                         	0x013c 0x03c8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA09__EIM_DATA01                         	0x013c 0x03c8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14                         	0x013c 0x03c8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09                       	0x013c 0x03c8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX                        	0x013c 0x03c8 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10                       	0x0140 0x03cc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC                       	0x0140 0x03cc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA10__CSI_DATA18                         	0x0140 0x03cc 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA10__EIM_DATA02                         	0x0140 0x03cc 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15                         	0x0140 0x03cc 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10                       	0x0140 0x03cc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX                        	0x0140 0x03cc 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11                       	0x0144 0x03d0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK                       	0x0144 0x03d0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA11__CSI_DATA19                         	0x0144 0x03d0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA11__EIM_DATA03                         	0x0144 0x03d0 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16                         	0x0144 0x03d0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11                       	0x0144 0x03d0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX                        	0x0144 0x03d0 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12                       	0x0148 0x03d4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC                       	0x0148 0x03d4 0x060c 1 1
-#define MX6UL_PAD_LCD_DATA12__CSI_DATA20                         	0x0148 0x03d4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA12__EIM_DATA04                         	0x0148 0x03d4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17                         	0x0148 0x03d4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12                       	0x0148 0x03d4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY                         	0x0148 0x03d4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13                       	0x014c 0x03d8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK                       	0x014c 0x03d8 0x0608 1 1
-#define MX6UL_PAD_LCD_DATA13__CSI_DATA21                         	0x014c 0x03d8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA13__EIM_DATA05                         	0x014c 0x03d8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18                         	0x014c 0x03d8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13                       	0x014c 0x03d8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B                     	0x014c 0x03d8 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14                       	0x0150 0x03dc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA                       	0x0150 0x03dc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA14__CSI_DATA22                         	0x0150 0x03dc 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA14__EIM_DATA06                         	0x0150 0x03dc 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19                         	0x0150 0x03dc 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14                       	0x0150 0x03dc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4                       	0x0150 0x03dc 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15                       	0x0154 0x03e0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA                       	0x0154 0x03e0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA15__CSI_DATA23                         	0x0154 0x03e0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA15__EIM_DATA07                         	0x0154 0x03e0 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20                         	0x0154 0x03e0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15                       	0x0154 0x03e0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5                       	0x0154 0x03e0 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16                       	0x0158 0x03e4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX                           	0x0158 0x03e4 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX                           	0x0158 0x03e4 0x0654 1 2
-#define MX6UL_PAD_LCD_DATA16__CSI_DATA01                         	0x0158 0x03e4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA16__EIM_DATA08                         	0x0158 0x03e4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21                         	0x0158 0x03e4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24                       	0x0158 0x03e4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6                       	0x0158 0x03e4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17                       	0x015c 0x03e8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX                           	0x015c 0x03e8 0x0654 1 3
-#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX                           	0x015c 0x03e8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA17__CSI_DATA00                         	0x015c 0x03e8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA17__EIM_DATA09                         	0x015c 0x03e8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22                         	0x015c 0x03e8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25                       	0x015c 0x03e8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7                       	0x015c 0x03e8 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18                       	0x0160 0x03ec 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA18__PWM5_OUT                           	0x0160 0x03ec 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO                   	0x0160 0x03ec 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA18__CSI_DATA10                         	0x0160 0x03ec 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA18__EIM_DATA10                         	0x0160 0x03ec 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23                         	0x0160 0x03ec 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26                       	0x0160 0x03ec 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD                         	0x0160 0x03ec 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA19__EIM_DATA11                         	0x0164 0x03f0 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24                         	0x0164 0x03f0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27                       	0x0164 0x03f0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK                         	0x0164 0x03f0 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19                       	0x0164 0x03f0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA19__PWM6_OUT                           	0x0164 0x03f0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY                     	0x0164 0x03f0 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA19__CSI_DATA11                         	0x0164 0x03f0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA20__EIM_DATA12                         	0x0168 0x03f4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25                         	0x0168 0x03f4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28                       	0x0168 0x03f4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0                       	0x0168 0x03f4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20                       	0x0168 0x03f4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX                           	0x0168 0x03f4 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX                           	0x0168 0x03f4 0x065c 1 2
-#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK                        	0x0168 0x03f4 0x0534 2 0
-#define MX6UL_PAD_LCD_DATA20__CSI_DATA12                         	0x0168 0x03f4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21                       	0x016c 0x03f8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX                           	0x016c 0x03f8 0x065c 1 3
-#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX                           	0x016c 0x03f8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0                         	0x016c 0x03f8 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA21__CSI_DATA13                         	0x016c 0x03f8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA21__EIM_DATA13                         	0x016c 0x03f8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26                         	0x016c 0x03f8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29                       	0x016c 0x03f8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1                       	0x016c 0x03f8 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22                       	0x0170 0x03fc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT                          	0x0170 0x03fc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI                        	0x0170 0x03fc 0x053c 2 0
-#define MX6UL_PAD_LCD_DATA22__CSI_DATA14                         	0x0170 0x03fc 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA22__EIM_DATA14                         	0x0170 0x03fc 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27                         	0x0170 0x03fc 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30                       	0x0170 0x03fc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2                       	0x0170 0x03fc 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23                       	0x0174 0x0400 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA23__MQS_LEFT                           	0x0174 0x0400 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO                        	0x0174 0x0400 0x0538 2 0
-#define MX6UL_PAD_LCD_DATA23__CSI_DATA15                         	0x0174 0x0400 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA23__EIM_DATA15                         	0x0174 0x0400 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28                         	0x0174 0x0400 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31                       	0x0174 0x0400 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3                       	0x0174 0x0400 0x0000 8 0
-#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B                        	0x0178 0x0404 0x0000 0 0
-#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK                          	0x0178 0x0404 0x0670 1 2
-#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK                         	0x0178 0x0404 0x0000 2 0
-#define MX6UL_PAD_NAND_RE_B__KPP_ROW00                           	0x0178 0x0404 0x0000 3 0
-#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00                          	0x0178 0x0404 0x0000 4 0
-#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00                          	0x0178 0x0404 0x0000 5 0
-#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2                          	0x0178 0x0404 0x0000 8 0
-#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B                        	0x017c 0x0408 0x0000 0 0
-#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD                          	0x017c 0x0408 0x0678 1 2
-#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B                        	0x017c 0x0408 0x0000 2 0
-#define MX6UL_PAD_NAND_WE_B__KPP_COL00                           	0x017c 0x0408 0x0000 3 0
-#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01                          	0x017c 0x0408 0x0000 4 0
-#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01                          	0x017c 0x0408 0x0000 5 0
-#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3                          	0x017c 0x0408 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00                    	0x0180 0x040c 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0                      	0x0180 0x040c 0x067c 1 2
-#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B                      	0x0180 0x040c 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA00__KPP_ROW01                         	0x0180 0x040c 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA00__EIM_AD08                          	0x0180 0x040c 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02                        	0x0180 0x040c 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY                        	0x0180 0x040c 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01                    	0x0184 0x0410 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1                      	0x0184 0x0410 0x0680 1 2
-#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS                        	0x0184 0x0410 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA01__KPP_COL01                         	0x0184 0x0410 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA01__EIM_AD09                          	0x0184 0x0410 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03                        	0x0184 0x0410 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1                        	0x0184 0x0410 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02                    	0x0188 0x0414 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2                      	0x0188 0x0414 0x0684 1 1
-#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00                     	0x0188 0x0414 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA02__KPP_ROW02                         	0x0188 0x0414 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA02__EIM_AD10                          	0x0188 0x0414 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04                        	0x0188 0x0414 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2                        	0x0188 0x0414 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03                    	0x018c 0x0418 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3                      	0x018c 0x0418 0x0688 1 2
-#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01                     	0x018c 0x0418 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA03__KPP_COL02                         	0x018c 0x0418 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA03__EIM_AD11                          	0x018c 0x0418 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05                        	0x018c 0x0418 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3                        	0x018c 0x0418 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04                    	0x0190 0x041c 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4                      	0x0190 0x041c 0x068c 1 1
-#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02                     	0x0190 0x041c 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK                       	0x0190 0x041c 0x0564 3 1
-#define MX6UL_PAD_NAND_DATA04__EIM_AD12                          	0x0190 0x041c 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06                        	0x0190 0x041c 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX                          	0x0190 0x041c 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX                          	0x0190 0x041c 0x062c 8 2
-#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05                    	0x0194 0x0420 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5                      	0x0194 0x0420 0x0690 1 1
-#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03                     	0x0194 0x0420 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI                       	0x0194 0x0420 0x056c 3 1
-#define MX6UL_PAD_NAND_DATA05__EIM_AD13                          	0x0194 0x0420 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07                        	0x0194 0x0420 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX                          	0x0194 0x0420 0x062c 8 3
-#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX                          	0x0194 0x0420 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06                    	0x0198 0x0424 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6                      	0x0198 0x0424 0x0694 1 1
-#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK                      	0x0198 0x0424 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO                       	0x0198 0x0424 0x0568 3 1
-#define MX6UL_PAD_NAND_DATA06__EIM_AD14                          	0x0198 0x0424 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08                        	0x0198 0x0424 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS                     	0x0198 0x0424 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS                     	0x0198 0x0424 0x0628 8 4
-#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07                    	0x019c 0x0428 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7                      	0x019c 0x0428 0x0698 1 1
-#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B                      	0x019c 0x0428 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0                        	0x019c 0x0428 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA07__EIM_AD15                          	0x019c 0x0428 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09                        	0x019c 0x0428 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS                     	0x019c 0x0428 0x0628 8 5
-#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS                     	0x019c 0x0428 0x0000 8 0
-#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE                          	0x01a0 0x042c 0x0000 0 0
-#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B                       	0x01a0 0x042c 0x0000 1 0
-#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS                           	0x01a0 0x042c 0x0000 2 0
-#define MX6UL_PAD_NAND_ALE__PWM3_OUT                             	0x01a0 0x042c 0x0000 3 0
-#define MX6UL_PAD_NAND_ALE__EIM_ADDR17                           	0x01a0 0x042c 0x0000 4 0
-#define MX6UL_PAD_NAND_ALE__GPIO4_IO10                           	0x01a0 0x042c 0x0000 5 0
-#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1                           	0x01a0 0x042c 0x0000 8 0
-#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B                        	0x01a4 0x0430 0x0000 0 0
-#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B                      	0x01a4 0x0430 0x0000 1 0
-#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK                         	0x01a4 0x0430 0x0000 2 0
-#define MX6UL_PAD_NAND_WP_B__PWM4_OUT                            	0x01a4 0x0430 0x0000 3 0
-#define MX6UL_PAD_NAND_WP_B__EIM_BCLK                            	0x01a4 0x0430 0x0000 4 0
-#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11                          	0x01a4 0x0430 0x0000 5 0
-#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY                          	0x01a4 0x0430 0x0000 8 0
-#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B                  	0x01a8 0x0434 0x0000 0 0
-#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4                     	0x01a8 0x0434 0x0000 1 0
-#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00                    	0x01a8 0x0434 0x0000 2 0
-#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0                       	0x01a8 0x0434 0x0000 3 0
-#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B                        	0x01a8 0x0434 0x0000 4 0
-#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12                       	0x01a8 0x0434 0x0000 5 0
-#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX                         	0x01a8 0x0434 0x0000 8 0
-#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX                         	0x01a8 0x0434 0x0634 8 2
-#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B                      	0x01ac 0x0438 0x0000 0 0
-#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5                       	0x01ac 0x0438 0x0000 1 0
-#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01                      	0x01ac 0x0438 0x0000 2 0
-#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK                        	0x01ac 0x0438 0x0554 3 1
-#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B                        	0x01ac 0x0438 0x0000 4 0
-#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13                         	0x01ac 0x0438 0x0000 5 0
-#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX                           	0x01ac 0x0438 0x0634 8 3
-#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX                           	0x01ac 0x0438 0x0000 8 0
-#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B                      	0x01b0 0x043c 0x0000 0 0
-#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6                       	0x01b0 0x043c 0x0000 1 0
-#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02                      	0x01b0 0x043c 0x0000 2 0
-#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI                        	0x01b0 0x043c 0x055c 3 1
-#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18                         	0x01b0 0x043c 0x0000 4 0
-#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14                         	0x01b0 0x043c 0x0000 5 0
-#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS                      	0x01b0 0x043c 0x0000 8 0
-#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS                      	0x01b0 0x043c 0x0630 8 2
-#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE                          	0x01b4 0x0440 0x0000 0 0
-#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7                         	0x01b4 0x0440 0x0000 1 0
-#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03                        	0x01b4 0x0440 0x0000 2 0
-#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO                          	0x01b4 0x0440 0x0558 3 1
-#define MX6UL_PAD_NAND_CLE__EIM_ADDR16                           	0x01b4 0x0440 0x0000 4 0
-#define MX6UL_PAD_NAND_CLE__GPIO4_IO15                           	0x01b4 0x0440 0x0000 5 0
-#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS                        	0x01b4 0x0440 0x0630 8 3
-#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS                        	0x01b4 0x0440 0x0000 8 0
-#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS                          	0x01b8 0x0444 0x0000 0 0
-#define MX6UL_PAD_NAND_DQS__CSI_FIELD                            	0x01b8 0x0444 0x0530 1 1
-#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B                         	0x01b8 0x0444 0x0000 2 0
-#define MX6UL_PAD_NAND_DQS__PWM5_OUT                             	0x01b8 0x0444 0x0000 3 0
-#define MX6UL_PAD_NAND_DQS__EIM_WAIT                             	0x01b8 0x0444 0x0000 4 0
-#define MX6UL_PAD_NAND_DQS__GPIO4_IO16                           	0x01b8 0x0444 0x0000 5 0
-#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01                     	0x01b8 0x0444 0x0000 6 0
-#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK                        	0x01b8 0x0444 0x0000 8 0
-#define MX6UL_PAD_SD1_CMD__USDHC1_CMD                            	0x01bc 0x0448 0x0000 0 0
-#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1                         	0x01bc 0x0448 0x0000 1 0
-#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC                          	0x01bc 0x0448 0x0000 2 0
-#define MX6UL_PAD_SD1_CMD__SPDIF_OUT                             	0x01bc 0x0448 0x0000 3 0
-#define MX6UL_PAD_SD1_CMD__EIM_ADDR19                            	0x01bc 0x0448 0x0000 4 0
-#define MX6UL_PAD_SD1_CMD__GPIO2_IO16                            	0x01bc 0x0448 0x0000 5 0
-#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00                      	0x01bc 0x0448 0x0000 6 0
-#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR                          	0x01bc 0x0448 0x0000 8 0
-#define MX6UL_PAD_SD1_CLK__USDHC1_CLK                            	0x01c0 0x044c 0x0000 0 0
-#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2                         	0x01c0 0x044c 0x0000 1 0
-#define MX6UL_PAD_SD1_CLK__SAI2_MCLK                             	0x01c0 0x044c 0x0000 2 0
-#define MX6UL_PAD_SD1_CLK__SPDIF_IN                              	0x01c0 0x044c 0x0618 3 3
-#define MX6UL_PAD_SD1_CLK__EIM_ADDR20                            	0x01c0 0x044c 0x0000 4 0
-#define MX6UL_PAD_SD1_CLK__GPIO2_IO17                            	0x01c0 0x044c 0x0000 5 0
-#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC                           	0x01c0 0x044c 0x0000 8 0
-#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0                        	0x01c4 0x0450 0x0000 0 0
-#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3                       	0x01c4 0x0450 0x0000 1 0
-#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC                        	0x01c4 0x0450 0x05fc 2 1
-#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX                         	0x01c4 0x0450 0x0000 3 0
-#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21                          	0x01c4 0x0450 0x0000 4 0
-#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18                          	0x01c4 0x0450 0x0000 5 0
-#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID                      	0x01c4 0x0450 0x0000 8 0
-#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1                        	0x01c8 0x0454 0x0000 0 0
-#define MX6UL_PAD_SD1_DATA1__GPT2_CLK                            	0x01c8 0x0454 0x05a0 1 1
-#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK                        	0x01c8 0x0454 0x05f8 2 1
-#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX                         	0x01c8 0x0454 0x0584 3 3
-#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22                          	0x01c8 0x0454 0x0000 4 0
-#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19                          	0x01c8 0x0454 0x0000 5 0
-#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR                        	0x01c8 0x0454 0x0000 8 0
-#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2                        	0x01cc 0x0458 0x0000 0 0
-#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1                       	0x01cc 0x0458 0x0598 1 1
-#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA                        	0x01cc 0x0458 0x05f4 2 1
-#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX                         	0x01cc 0x0458 0x0000 3 0
-#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23                          	0x01cc 0x0458 0x0000 4 0
-#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20                          	0x01cc 0x0458 0x0000 5 0
-#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1                           	0x01cc 0x0458 0x0000 6 0
-#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC                         	0x01cc 0x0458 0x0000 8 0
-#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3                        	0x01d0 0x045c 0x0000 0 0
-#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2                       	0x01d0 0x045c 0x059c 1 1
-#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA                        	0x01d0 0x045c 0x0000 2 0
-#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX                         	0x01d0 0x045c 0x0588 3 3
-#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24                          	0x01d0 0x045c 0x0000 4 0
-#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21                          	0x01d0 0x045c 0x0000 5 0
-#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2                           	0x01d0 0x045c 0x0000 6 0
-#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID                      	0x01d0 0x045c 0x0000 8 0
-#define MX6UL_PAD_CSI_MCLK__CSI_MCLK                             	0x01d4 0x0460 0x0000 0 0
-#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B                          	0x01d4 0x0460 0x0674 1 0
-#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B                        	0x01d4 0x0460 0x0000 2 0
-#define MX6UL_PAD_CSI_MCLK__I2C1_SDA                             	0x01d4 0x0460 0x05a8 3 0
-#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B                            	0x01d4 0x0460 0x0000 4 0
-#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17                           	0x01d4 0x0460 0x0000 5 0
-#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL                    	0x01d4 0x0460 0x0000 6 0
-#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX                             	0x01d4 0x0460 0x0000 8 0
-#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX                             	0x01d4 0x0460 0x064c 8 0
-#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK                         	0x01d8 0x0464 0x0528 0 1
-#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP                          	0x01d8 0x0464 0x069c 1 2
-#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B                      	0x01d8 0x0464 0x0000 2 0
-#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL                           	0x01d8 0x0464 0x05a4 3 2
-#define MX6UL_PAD_CSI_PIXCLK__EIM_OE                             	0x01d8 0x0464 0x0000 4 0
-#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18                         	0x01d8 0x0464 0x0000 5 0
-#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5                      	0x01d8 0x0464 0x0000 6 0
-#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX                           	0x01d8 0x0464 0x064c 8 3
-#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX                           	0x01d8 0x0464 0x0000 8 0
-#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC                           	0x01dc 0x0468 0x052c 0 0
-#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK                          	0x01dc 0x0468 0x0670 1 0
-#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK                      	0x01dc 0x0468 0x0000 2 0
-#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA                            	0x01dc 0x0468 0x05b0 3 0
-#define MX6UL_PAD_CSI_VSYNC__EIM_RW                              	0x01dc 0x0468 0x0000 4 0
-#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19                          	0x01dc 0x0468 0x0000 5 0
-#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT                            	0x01dc 0x0468 0x0000 6 0
-#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS                       	0x01dc 0x0468 0x0648 8 0
-#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS                       	0x01dc 0x0468 0x0000 8 0
-#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC                           	0x01e0 0x046c 0x0524 0 0
-#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD                          	0x01e0 0x046c 0x0678 1 0
-#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD                       	0x01e0 0x046c 0x0000 2 0
-#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL                            	0x01e0 0x046c 0x05ac 3 0
-#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B                           	0x01e0 0x046c 0x0000 4 0
-#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20                          	0x01e0 0x046c 0x0000 5 0
-#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT                            	0x01e0 0x046c 0x0000 6 0
-#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS                       	0x01e0 0x046c 0x0000 8 0
-#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS                       	0x01e0 0x046c 0x0648 8 1
-#define MX6UL_PAD_CSI_DATA00__CSI_DATA02                         	0x01e4 0x0470 0x04c4 0 0
-#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0                       	0x01e4 0x0470 0x067c 1 0
-#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B                   	0x01e4 0x0470 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK                        	0x01e4 0x0470 0x0544 3 0
-#define MX6UL_PAD_CSI_DATA00__EIM_AD00                           	0x01e4 0x0470 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21                         	0x01e4 0x0470 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT                       	0x01e4 0x0470 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX                           	0x01e4 0x0470 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX                           	0x01e4 0x0470 0x0644 8 0
-#define MX6UL_PAD_CSI_DATA01__CSI_DATA03                         	0x01e8 0x0474 0x04c8 0 0
-#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1                       	0x01e8 0x0474 0x0680 1 0
-#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN                    	0x01e8 0x0474 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0                         	0x01e8 0x0474 0x0000 3 0
-#define MX6UL_PAD_CSI_DATA01__EIM_AD01                           	0x01e8 0x0474 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22                         	0x01e8 0x0474 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK                          	0x01e8 0x0474 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX                           	0x01e8 0x0474 0x0644 8 1
-#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX                           	0x01e8 0x0474 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA02__CSI_DATA04                         	0x01ec 0x0478 0x04d8 0 1
-#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2                       	0x01ec 0x0478 0x0684 1 2
-#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD                    	0x01ec 0x0478 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI                        	0x01ec 0x0478 0x054c 3 1
-#define MX6UL_PAD_CSI_DATA02__EIM_AD02                           	0x01ec 0x0478 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23                         	0x01ec 0x0478 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC                       	0x01ec 0x0478 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS                      	0x01ec 0x0478 0x0640 8 5
-#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS                      	0x01ec 0x0478 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA03__CSI_DATA05                         	0x01f0 0x047c 0x04cc 0 0
-#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3                       	0x01f0 0x047c 0x0688 1 0
-#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD                      	0x01f0 0x047c 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO                        	0x01f0 0x047c 0x0548 3 0
-#define MX6UL_PAD_CSI_DATA03__EIM_AD03                           	0x01f0 0x047c 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24                         	0x01f0 0x047c 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK                       	0x01f0 0x047c 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS                      	0x01f0 0x047c 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS                      	0x01f0 0x047c 0x0640 8 0
-#define MX6UL_PAD_CSI_DATA04__CSI_DATA06                         	0x01f4 0x0480 0x04dc 0 1
-#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4                       	0x01f4 0x0480 0x068c 1 2
-#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK                     	0x01f4 0x0480 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK                        	0x01f4 0x0480 0x0534 3 1
-#define MX6UL_PAD_CSI_DATA04__EIM_AD04                           	0x01f4 0x0480 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25                         	0x01f4 0x0480 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC                       	0x01f4 0x0480 0x05ec 6 1
-#define MX6UL_PAD_CSI_DATA04__USDHC1_WP                          	0x01f4 0x0480 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA05__CSI_DATA07                         	0x01f8 0x0484 0x04e0 0 1
-#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5                       	0x01f8 0x0484 0x0690 1 2
-#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B                   	0x01f8 0x0484 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0                         	0x01f8 0x0484 0x0000 3 0
-#define MX6UL_PAD_CSI_DATA05__EIM_AD05                           	0x01f8 0x0484 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26                         	0x01f8 0x0484 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK                       	0x01f8 0x0484 0x05e8 6 1
-#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B                        	0x01f8 0x0484 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA06__CSI_DATA08                         	0x01fc 0x0488 0x04e4 0 1
-#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6                       	0x01fc 0x0488 0x0694 1 2
-#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN                    	0x01fc 0x0488 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI                        	0x01fc 0x0488 0x053c 3 1
-#define MX6UL_PAD_CSI_DATA06__EIM_AD06                           	0x01fc 0x0488 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27                         	0x01fc 0x0488 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA                       	0x01fc 0x0488 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B                     	0x01fc 0x0488 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA07__CSI_DATA09                         	0x0200 0x048c 0x04e8 0 1
-#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7                       	0x0200 0x048c 0x0698 1 2
-#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD                    	0x0200 0x048c 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO                        	0x0200 0x048c 0x0538 3 1
-#define MX6UL_PAD_CSI_DATA07__EIM_AD07                           	0x0200 0x048c 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28                         	0x0200 0x048c 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA                       	0x0200 0x048c 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT                     	0x0200 0x048c 0x0000 8 0
+#define MX6UL_PAD_JTAG_MOD__SJC_MOD			0x0044 0x02d0 0x0000 0 0
+#define MX6UL_PAD_JTAG_MOD__GPT2_CLK			0x0044 0x02d0 0x05a0 1 0
+#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT			0x0044 0x02d0 0x0000 2 0
+#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M		0x0044 0x02d0 0x0000 3 0
+#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY		0x0044 0x02d0 0x04c0 4 0
+#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10			0x0044 0x02d0 0x0000 5 0
+#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00		0x0044 0x02d0 0x0000 6 0
+#define MX6UL_PAD_JTAG_TMS__SJC_TMS			0x0048 0x02d4 0x0000 0 0
+#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1		0x0048 0x02d4 0x0598 1 0
+#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK			0x0048 0x02d4 0x0000 2 0
+#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1			0x0048 0x02d4 0x0000 3 0
+#define MX6UL_PAD_JTAG_TMS__CCM_WAIT			0x0048 0x02d4 0x0000 4 0
+#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11			0x0048 0x02d4 0x0000 5 0
+#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01		0x0048 0x02d4 0x0000 6 0
+#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT			0x0048 0x02d4 0x0000 8 0
+#define MX6UL_PAD_JTAG_TDO__SJC_TDO			0x004c 0x02d8 0x0000 0 0
+#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2		0x004c 0x02d8 0x059c 1 0
+#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC		0x004c 0x02d8 0x05fc 2 0
+#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2			0x004c 0x02d8 0x0000 3 0
+#define MX6UL_PAD_JTAG_TDO__CCM_STOP			0x004c 0x02d8 0x0000 4 0
+#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12			0x004c 0x02d8 0x0000 5 0
+#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT			0x004c 0x02d8 0x0000 6 0
+#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT			0x004c 0x02d8 0x0000 8 0
+#define MX6UL_PAD_JTAG_TDI__SJC_TDI			0x0050 0x02dc 0x0000 0 0
+#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1		0x0050 0x02dc 0x0000 1 0
+#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK		0x0050 0x02dc 0x05f8 2 0
+#define MX6UL_PAD_JTAG_TDI__PWM6_OUT			0x0050 0x02dc 0x0000 4 0
+#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13			0x0050 0x02dc 0x0000 5 0
+#define MX6UL_PAD_JTAG_TDI__MQS_LEFT			0x0050 0x02dc 0x0000 6 0
+#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL		0x0050 0x02dc 0x0000 8 0
+#define MX6UL_PAD_JTAG_TCK__SJC_TCK			0x0054 0x02e0 0x0000 0 0
+#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2		0x0054 0x02e0 0x0000 1 0
+#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA		0x0054 0x02e0 0x05f4 2 0
+#define MX6UL_PAD_JTAG_TCK__PWM7_OUT			0x0054 0x02e0 0x0000 4 0
+#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14			0x0054 0x02e0 0x0000 5 0
+#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL		0x0054 0x02e0 0x0000 8 0
+#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB		0x0058 0x02e4 0x0000 0 0
+#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3		0x0058 0x02e4 0x0000 1 0
+#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA		0x0058 0x02e4 0x0000 2 0
+#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT			0x0058 0x02e4 0x0000 4 0
+#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15		0x0058 0x02e4 0x0000 5 0
+#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS		0x0058 0x02e4 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL			0x005c 0x02e8 0x05ac 0 1
+#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1		0x005c 0x02e8 0x058c 1 0
+#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID		0x005c 0x02e8 0x04b8 2 0
+#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1		0x005c 0x02e8 0x0574 3 0
+#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT			0x005c 0x02e8 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00		0x005c 0x02e8 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN	0x005c 0x02e8 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET		0x005c 0x02e8 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B		0x005c 0x02e8 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA			0x0060 0x02ec 0x05b0 0 1
+#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1		0x0060 0x02ec 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC		0x0060 0x02ec 0x0664 2 0
+#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2		0x0060 0x02ec 0x057c 3 0
+#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT			0x0060 0x02ec 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01		0x0060 0x02ec 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT	0x0060 0x02ec 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET		0x0060 0x02ec 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B		0x0060 0x02ec 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL			0x0064 0x02f0 0x05a4 0 0
+#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2		0x0064 0x02f0 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR		0x0064 0x02f0 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M		0x0064 0x02f0 0x0000 3 0
+#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP			0x0064 0x02f0 0x066c 4 0
+#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02		0x0064 0x02f0 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00		0x0064 0x02f0 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET		0x0064 0x02f0 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX		0x0064 0x02f0 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX		0x0064 0x02f0 0x0624 8 0
+#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA			0x0068 0x02f4 0x05a8 0 1
+#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3		0x0068 0x02f4 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC		0x0068 0x02f4 0x0660 2 0
+#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B		0x0068 0x02f4 0x0668 4 0
+#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03		0x0068 0x02f4 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK		0x0068 0x02f4 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK		0x0068 0x02f4 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX		0x0068 0x02f4 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX		0x0068 0x02f4 0x0624 8 1
+#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1		0x006c 0x02f8 0x0574 0 1
+#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT			0x006c 0x02f8 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR		0x006c 0x02f8 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B		0x006c 0x02f8 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04		0x006c 0x02f8 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN	0x006c 0x02f8 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX		0x006c 0x02f8 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX		0x006c 0x02f8 0x0644 8 2
+#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2		0x0070 0x02fc 0x057c 0 1
+#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT			0x0070 0x02fc 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID		0x0070 0x02fc 0x04bc 2 0
+#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD			0x0070 0x02fc 0x0530 3 0
+#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT		0x0070 0x02fc 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05		0x0070 0x02fc 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT	0x0070 0x02fc 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX		0x0070 0x02fc 0x0644 8 3
+#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX		0x0070 0x02fc 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO		0x0074 0x0300 0x0578 0 0
+#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO		0x0074 0x0300 0x0580 1 0
+#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE		0x0074 0x0300 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK			0x0074 0x0300 0x0000 3 0
+#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP			0x0074 0x0300 0x069c 4 0
+#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06		0x0074 0x0300 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT			0x0074 0x0300 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B		0x0074 0x0300 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS		0x0074 0x0300 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS		0x0074 0x0300 0x0620 8 0
+#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC			0x0078 0x0304 0x0000 0 0
+#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC			0x0078 0x0304 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE		0x0078 0x0304 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK		0x0078 0x0304 0x0528 3 0
+#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B		0x0078 0x0304 0x0674 4 1
+#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07		0x0078 0x0304 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO07__CCM_STOP			0x0078 0x0304 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS		0x0078 0x0304 0x0620 8 1
+#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS		0x0078 0x0304 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT			0x007c 0x0308 0x0000 0 0
+#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B		0x007c 0x0308 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT			0x007c 0x0308 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC			0x007c 0x0308 0x052c 3 1
+#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT		0x007c 0x0308 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08		0x007c 0x0308 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY		0x007c 0x0308 0x04c0 6 1
+#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS		0x007c 0x0308 0x0640 8 1
+#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS		0x007c 0x0308 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT			0x0080 0x030c 0x0000 0 0
+#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY		0x0080 0x030c 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN			0x0080 0x030c 0x0618 2 0
+#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC			0x0080 0x030c 0x0524 3 1
+#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B		0x0080 0x030c 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09		0x0080 0x030c 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B		0x0080 0x030c 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS		0x0080 0x030c 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS		0x0080 0x030c 0x0640 8 2
+#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX		0x0084 0x0310 0x0000 0 0
+#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX		0x0084 0x0310 0x0624 0 2
+#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02		0x0084 0x0310 0x0000 1 0
+#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL		0x0084 0x0310 0x05b4 2 0
+#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02		0x0084 0x0310 0x04c4 3 1
+#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1		0x0084 0x0310 0x0000 4 0
+#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16		0x0084 0x0310 0x0000 5 0
+#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT		0x0084 0x0310 0x0000 8 0
+#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX		0x0088 0x0314 0x0624 0 3
+#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX		0x0088 0x0314 0x0000 0 0
+#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03		0x0088 0x0314 0x0000 1 0
+#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA		0x0088 0x0314 0x05b8 2 0
+#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03		0x0088 0x0314 0x04c8 3 1
+#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK		0x0088 0x0314 0x0594 4 0
+#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17		0x0088 0x0314 0x0000 5 0
+#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN		0x0088 0x0314 0x0618 8 1
+#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS		0x008c 0x0318 0x0000 0 0
+#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS		0x008c 0x0318 0x0620 0 2
+#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK		0x008c 0x0318 0x0000 1 0
+#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP		0x008c 0x0318 0x066c 2 1
+#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04		0x008c 0x0318 0x04d8 3 0
+#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN	0x008c 0x0318 0x0000 4 0
+#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18		0x008c 0x0318 0x0000 5 0
+#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP		0x008c 0x0318 0x069c 8 1
+#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS		0x0090 0x031c 0x0620 0 3
+#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS		0x0090 0x031c 0x0000 0 0
+#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER		0x0090 0x031c 0x0000 1 0
+#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B		0x0090 0x031c 0x0668 2 1
+#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05		0x0090 0x031c 0x04cc 3 1
+#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT	0x0090 0x031c 0x0000 4 0
+#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19		0x0090 0x031c 0x0000 5 0
+#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B		0x0090 0x031c 0x0674 8 2
+#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX		0x0094 0x0320 0x0000 0 0
+#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX		0x0094 0x0320 0x062c 0 0
+#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02		0x0094 0x0320 0x0000 1 0
+#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL		0x0094 0x0320 0x05bc 2 0
+#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06		0x0094 0x0320 0x04dc 3 0
+#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1		0x0094 0x0320 0x058c 4 1
+#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20		0x0094 0x0320 0x0000 5 0
+#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0		0x0094 0x0320 0x0000 8 0
+#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX		0x0098 0x0324 0x062c 0 1
+#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX		0x0098 0x0324 0x0000 0 0
+#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03		0x0098 0x0324 0x0000 1 0
+#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA		0x0098 0x0324 0x05c0 2 0
+#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07		0x0098 0x0324 0x04e0 3 0
+#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2		0x0098 0x0324 0x0590 4 0
+#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21		0x0098 0x0324 0x0000 5 0
+#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE		0x0098 0x0324 0x0000 7 0
+#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK		0x0098 0x0324 0x0554 8 0
+#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS		0x009c 0x0328 0x0000 0 0
+#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS		0x009c 0x0328 0x0628 0 0
+#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS		0x009c 0x0328 0x0000 1 0
+#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX		0x009c 0x0328 0x0000 2 0
+#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08		0x009c 0x0328 0x04e4 3 0
+#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2		0x009c 0x0328 0x0000 4 0
+#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22		0x009c 0x0328 0x0000 5 0
+#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B			0x009c 0x0328 0x0000 7 0
+#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI		0x009c 0x0328 0x055c 8 0
+#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS		0x00a0 0x032c 0x0628 0 1
+#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS		0x00a0 0x032c 0x0000 0 0
+#define MX6UL_PAD_UART2_RTS_B__ENET1_COL		0x00a0 0x032c 0x0000 1 0
+#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX		0x00a0 0x032c 0x0588 2 0
+#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09		0x00a0 0x032c 0x04e8 3 0
+#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3		0x00a0 0x032c 0x0000 4 0
+#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23		0x00a0 0x032c 0x0000 5 0
+#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL			0x00a0 0x032c 0x0000 7 0
+#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO		0x00a0 0x032c 0x0558 8 0
+#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX		0x00a4 0x0330 0x0000 0 0
+#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX		0x00a4 0x0330 0x0634 0 0
+#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02		0x00a4 0x0330 0x0000 1 0
+#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD		0x00a4 0x0330 0x0000 2 0
+#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01		0x00a4 0x0330 0x0000 3 0
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS		0x00a4 0x0330 0x0000 4 0
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS		0x00a4 0x0330 0x0628 4 2
+#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24		0x00a4 0x0330 0x0000 5 0
+#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT		0x00a4 0x0330 0x0000 7 0
+#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID		0x00a4 0x0330 0x04b8 8 1
+#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX		0x00a8 0x0334 0x0634 0 1
+#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX		0x00a8 0x0334 0x0000 0 0
+#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03		0x00a8 0x0334 0x0000 1 0
+#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD		0x00a8 0x0334 0x0000 2 0
+#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00		0x00a8 0x0334 0x0000 3 0
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS		0x00a8 0x0334 0x0628 4 3
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS		0x00a8 0x0334 0x0000 4 0
+#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25		0x00a8 0x0334 0x0000 5 0
+#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT		0x00a8 0x0334 0x0000 8 0
+#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS		0x00ac 0x0338 0x0000 0 0
+#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS		0x00ac 0x0338 0x0630 0 0
+#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK		0x00ac 0x0338 0x0000 1 0
+#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX		0x00ac 0x0338 0x0000 2 0
+#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10		0x00ac 0x0338 0x0000 3 0
+#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN	0x00ac 0x0338 0x0000 4 0
+#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26		0x00ac 0x0338 0x0000 5 0
+#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT		0x00ac 0x0338 0x0000 8 0
+#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS		0x00b0 0x033c 0x0630 0 1
+#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS		0x00b0 0x033c 0x0000 0 0
+#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER		0x00b0 0x033c 0x0000 1 0
+#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX		0x00b0 0x033c 0x0584 2 0
+#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11		0x00b0 0x033c 0x0000 3 0
+#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT	0x00b0 0x033c 0x0000 4 0
+#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27		0x00b0 0x033c 0x0000 5 0
+#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B		0x00b0 0x033c 0x0000 8 0
+#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX		0x00b4 0x0340 0x0000 0 0
+#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX		0x00b4 0x0340 0x063c 0 0
+#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02		0x00b4 0x0340 0x0000 1 0
+#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL		0x00b4 0x0340 0x05a4 2 1
+#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12		0x00b4 0x0340 0x0000 3 0
+#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02	0x00b4 0x0340 0x0000 4 0
+#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28		0x00b4 0x0340 0x0000 5 0
+#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK		0x00b4 0x0340 0x0544 8 1
+#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX		0x00b8 0x0344 0x063c 0 1
+#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX		0x00b8 0x0344 0x0000 0 0
+#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03		0x00b8 0x0344 0x0000 1 0
+#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA		0x00b8 0x0344 0x05a8 2 2
+#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13		0x00b8 0x0344 0x0000 3 0
+#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01	0x00b8 0x0344 0x0000 4 0
+#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29		0x00b8 0x0344 0x0000 5 0
+#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0		0x00b8 0x0344 0x0000 8 0
+#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30		0x00bc 0x0348 0x0000 5 0
+#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI		0x00bc 0x0348 0x054c 8 0
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX		0x00bc 0x0348 0x0000 0 0
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX		0x00bc 0x0348 0x0644 0 4
+#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS		0x00bc 0x0348 0x0000 1 0
+#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL		0x00bc 0x0348 0x05ac 2 2
+#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14		0x00bc 0x0348 0x0000 3 0
+#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00	0x00bc 0x0348 0x0000 4 0
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX		0x00c0 0x034c 0x0644 0 5
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX		0x00c0 0x034c 0x0000 0 0
+#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL		0x00c0 0x034c 0x0000 1 0
+#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA		0x00c0 0x034c 0x05b0 2 2
+#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15		0x00c0 0x034c 0x0000 3 0
+#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB	0x00c0 0x034c 0x0000 4 0
+#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31		0x00c0 0x034c 0x0000 5 0
+#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO		0x00c0 0x034c 0x0548 8 1
+#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00		0x00c4 0x0350 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS		0x00c4 0x0350 0x0638 1 0
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS		0x00c4 0x0350 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT		0x00c4 0x0350 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16		0x00c4 0x0350 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX		0x00c4 0x0350 0x0000 4 0
+#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00		0x00c4 0x0350 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00		0x00c4 0x0350 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL		0x00c4 0x0350 0x0000 8 0
+#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01		0x00c8 0x0354 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS		0x00c8 0x0354 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS		0x00c8 0x0354 0x0638 1 1
+#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT		0x00c8 0x0354 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17		0x00c8 0x0354 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX		0x00c8 0x0354 0x0584 4 1
+#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01		0x00c8 0x0354 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00		0x00c8 0x0354 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL		0x00c8 0x0354 0x0000 8 0
+#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN		0x00cc 0x0358 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS		0x00cc 0x0358 0x0640 1 3
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS		0x00cc 0x0358 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18		0x00cc 0x0358 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX		0x00cc 0x0358 0x0000 4 0
+#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02		0x00cc 0x0358 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01		0x00cc 0x0358 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT		0x00cc 0x0358 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00		0x00d0 0x035c 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS		0x00d0 0x035c 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS		0x00d0 0x035c 0x0640 1 4
+#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19		0x00d0 0x035c 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX		0x00d0 0x035c 0x0588 4 1
+#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03		0x00d0 0x035c 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01		0x00d0 0x035c 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT	0x00d0 0x035c 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01		0x00d4 0x0360 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS		0x00d4 0x0360 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS		0x00d4 0x0360 0x0648 1 2
+#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT		0x00d4 0x0360 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20		0x00d4 0x0360 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO		0x00d4 0x0360 0x0580 4 1
+#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04		0x00d4 0x0360 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02		0x00d4 0x0360 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB	0x00d4 0x0360 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN		0x00d8 0x0364 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS		0x00d8 0x0364 0x0648 1 3
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS		0x00d8 0x0364 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT			0x00d8 0x0364 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21		0x00d8 0x0364 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC		0x00d8 0x0364 0x0000 4 0
+#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05		0x00d8 0x0364 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02		0x00d8 0x0364 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB	0x00d8 0x0364 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK		0x00dc 0x0368 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS		0x00dc 0x0368 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS		0x00dc 0x0368 0x0650 1 0
+#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT		0x00dc 0x0368 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22		0x00dc 0x0368 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1		0x00dc 0x0368 0x0574 4 2
+#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06		0x00dc 0x0368 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03		0x00dc 0x0368 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK		0x00dc 0x0368 0x0594 8 1
+#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER		0x00e0 0x036c 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS		0x00e0 0x036c 0x0650 1 1
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS		0x00e0 0x036c 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT			0x00e0 0x036c 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23		0x00e0 0x036c 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE			0x00e0 0x036c 0x0000 4 0
+#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07		0x00e0 0x036c 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03		0x00e0 0x036c 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2		0x00e0 0x036c 0x0590 8 1
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00		0x00e4 0x0370 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX		0x00e4 0x0370 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX		0x00e4 0x0370 0x064c 1 1
+#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD	0x00e4 0x0370 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL		0x00e4 0x0370 0x05b4 3 1
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO		0x00e4 0x0370 0x0578 4 1
+#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08		0x00e4 0x0370 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04		0x00e4 0x0370 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR		0x00e4 0x0370 0x0000 8 0
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01		0x00e8 0x0374 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX		0x00e8 0x0374 0x064c 1 2
+#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX		0x00e8 0x0374 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK	0x00e8 0x0374 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA		0x00e8 0x0374 0x05b8 3 1
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC		0x00e8 0x0374 0x0000 4 0
+#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09		0x00e8 0x0374 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04		0x00e8 0x0374 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC		0x00e8 0x0374 0x0664 8 1
+#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN		0x00ec 0x0378 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX		0x00ec 0x0378 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX		0x00ec 0x0378 0x0654 1 0
+#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B		0x00ec 0x0378 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL			0x00ec 0x0378 0x05bc 3 1
+#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26		0x00ec 0x0378 0x0000 4 0
+#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10		0x00ec 0x0378 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05		0x00ec 0x0378 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M	0x00ec 0x0378 0x0000 8 0
+#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00		0x00f0 0x037c 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX		0x00f0 0x037c 0x0654 1 1
+#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX		0x00f0 0x037c 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN	0x00f0 0x037c 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA		0x00f0 0x037c 0x05c0 3 1
+#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02		0x00f0 0x037c 0x0000 4 0
+#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11		0x00f0 0x037c 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05		0x00f0 0x037c 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01		0x00f4 0x0380 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX		0x00f4 0x0380 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX		0x00f4 0x0380 0x065c 1 0
+#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD	0x00f4 0x0380 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK		0x00f4 0x0380 0x0564 3 0
+#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03		0x00f4 0x0380 0x0000 4 0
+#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12		0x00f4 0x0380 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06		0x00f4 0x0380 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR		0x00f4 0x0380 0x0000 8 0
+#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN		0x00f8 0x0384 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX		0x00f8 0x0384 0x065c 1 1
+#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX		0x00f8 0x0384 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK		0x00f8 0x0384 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI		0x00f8 0x0384 0x056c 3 0
+#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN		0x00f8 0x0384 0x0000 4 0
+#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13		0x00f8 0x0384 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06		0x00f8 0x0384 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC		0x00f8 0x0384 0x0660 8 1
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK		0x00fc 0x0388 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS		0x00fc 0x0388 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS		0x00fc 0x0388 0x0658 1 0
+#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B	0x00fc 0x0388 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO		0x00fc 0x0388 0x0568 3 0
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2		0x00fc 0x0388 0x057c 4 2
+#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14		0x00fc 0x0388 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07		0x00fc 0x0388 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID		0x00fc 0x0388 0x04bc 8 1
+#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER		0x0100 0x038c 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS		0x0100 0x038c 0x0658 1 1
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS		0x0100 0x038c 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN		0x0100 0x038c 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0		0x0100 0x038c 0x0000 3 0
+#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25		0x0100 0x038c 0x0000 4 0
+#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15		0x0100 0x038c 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07		0x0100 0x038c 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY		0x0100 0x038c 0x0000 8 0
+#define MX6UL_PAD_LCD_CLK__LCDIF_CLK			0x0104 0x0390 0x0000 0 0
+#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN			0x0104 0x0390 0x0000 1 0
+#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX			0x0104 0x0390 0x0000 2 0
+#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX			0x0104 0x0390 0x063c 2 2
+#define MX6UL_PAD_LCD_CLK__SAI3_MCLK			0x0104 0x0390 0x0000 3 0
+#define MX6UL_PAD_LCD_CLK__EIM_CS2_B			0x0104 0x0390 0x0000 4 0
+#define MX6UL_PAD_LCD_CLK__GPIO3_IO00			0x0104 0x0390 0x0000 5 0
+#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB		0x0104 0x0390 0x0000 8 0
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE		0x0108 0x0394 0x0000 0 0
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E		0x0108 0x0394 0x0000 1 0
+#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX		0x0108 0x0394 0x063c 2 3
+#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX		0x0108 0x0394 0x0000 2 0
+#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC		0x0108 0x0394 0x060c 3 0
+#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B			0x0108 0x0394 0x0000 4 0
+#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01		0x0108 0x0394 0x0000 5 0
+#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY		0x0108 0x0394 0x0000 8 0
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC		0x010c 0x0398 0x05dc 0 0
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS			0x010c 0x0398 0x0000 1 0
+#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS		0x010c 0x0398 0x0000 2 0
+#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS		0x010c 0x0398 0x0638 2 2
+#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK		0x010c 0x0398 0x0608 3 0
+#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB	0x010c 0x0398 0x0000 4 0
+#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02			0x010c 0x0398 0x0000 5 0
+#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1			0x010c 0x0398 0x0000 8 0
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC		0x0110 0x039c 0x0000 0 0
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY			0x0110 0x039c 0x05dc 1 1
+#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS		0x0110 0x039c 0x0638 2 3
+#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS		0x0110 0x039c 0x0000 2 0
+#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA		0x0110 0x039c 0x0000 3 0
+#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B		0x0110 0x039c 0x0000 4 0
+#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03			0x0110 0x039c 0x0000 5 0
+#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2			0x0110 0x039c 0x0000 8 0
+#define MX6UL_PAD_LCD_RESET__LCDIF_RESET		0x0114 0x03a0 0x0000 0 0
+#define MX6UL_PAD_LCD_RESET__LCDIF_CS			0x0114 0x03a0 0x0000 1 0
+#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI		0x0114 0x03a0 0x0000 2 0
+#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA		0x0114 0x03a0 0x0000 3 0
+#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY		0x0114 0x03a0 0x0000 4 0
+#define MX6UL_PAD_LCD_RESET__GPIO3_IO04			0x0114 0x03a0 0x0000 5 0
+#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3			0x0114 0x03a0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00		0x0118 0x03a4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA00__PWM1_OUT			0x0118 0x03a4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN	0x0118 0x03a4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA00__I2C3_SDA			0x0118 0x03a4 0x05b8 4 2
+#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05		0x0118 0x03a4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00		0x0118 0x03a4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK			0x0118 0x03a4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01		0x011c 0x03a8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA01__PWM2_OUT			0x011c 0x03a8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT	0x011c 0x03a8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA01__I2C3_SCL			0x011c 0x03a8 0x05b4 4 2
+#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06		0x011c 0x03a8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01		0x011c 0x03a8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC		0x011c 0x03a8 0x05ec 8 0
+#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02		0x0120 0x03ac 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA02__PWM3_OUT			0x0120 0x03ac 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN	0x0120 0x03ac 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA02__I2C4_SDA			0x0120 0x03ac 0x05c0 4 2
+#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07		0x0120 0x03ac 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02		0x0120 0x03ac 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK		0x0120 0x03ac 0x05e8 8 0
+#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03		0x0124 0x03b0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA03__PWM4_OUT			0x0124 0x03b0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT	0x0124 0x03b0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA03__I2C4_SCL			0x0124 0x03b0 0x05bc 4 2
+#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08		0x0124 0x03b0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03		0x0124 0x03b0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA		0x0124 0x03b0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04		0x0128 0x03b4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS		0x0128 0x03b4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS		0x0128 0x03b4 0x0658 1 2
+#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN	0x0128 0x03b4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK		0x0128 0x03b4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09		0x0128 0x03b4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04		0x0128 0x03b4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA		0x0128 0x03b4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05		0x012c 0x03b8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS		0x012c 0x03b8 0x0658 1 3
+#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS		0x012c 0x03b8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT	0x012c 0x03b8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT			0x012c 0x03b8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10		0x012c 0x03b8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05		0x012c 0x03b8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1		0x012c 0x03b8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06		0x0130 0x03bc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS		0x0130 0x03bc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS		0x0130 0x03bc 0x0650 1 2
+#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN	0x0130 0x03bc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK		0x0130 0x03bc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11		0x0130 0x03bc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06		0x0130 0x03bc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2		0x0130 0x03bc 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07		0x0134 0x03c0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS		0x0134 0x03c0 0x0650 1 3
+#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS		0x0134 0x03c0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT	0x0134 0x03c0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK		0x0134 0x03c0 0x061c 4 0
+#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12		0x0134 0x03c0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07		0x0134 0x03c0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3		0x0134 0x03c0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08		0x0138 0x03c4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA08__SPDIF_IN			0x0138 0x03c4 0x0618 1 2
+#define MX6UL_PAD_LCD_DATA08__CSI_DATA16		0x0138 0x03c4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA08__EIM_DATA00		0x0138 0x03c4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13		0x0138 0x03c4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08		0x0138 0x03c4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX		0x0138 0x03c4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09		0x013c 0x03c8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK			0x013c 0x03c8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA09__CSI_DATA17		0x013c 0x03c8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA09__EIM_DATA01		0x013c 0x03c8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14		0x013c 0x03c8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09		0x013c 0x03c8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX		0x013c 0x03c8 0x0584 8 2
+#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10		0x0140 0x03cc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC		0x0140 0x03cc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA10__CSI_DATA18		0x0140 0x03cc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA10__EIM_DATA02		0x0140 0x03cc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15		0x0140 0x03cc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10		0x0140 0x03cc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX		0x0140 0x03cc 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11		0x0144 0x03d0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK		0x0144 0x03d0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA11__CSI_DATA19		0x0144 0x03d0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA11__EIM_DATA03		0x0144 0x03d0 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16		0x0144 0x03d0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11		0x0144 0x03d0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX		0x0144 0x03d0 0x0588 8 2
+#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12		0x0148 0x03d4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC		0x0148 0x03d4 0x060c 1 1
+#define MX6UL_PAD_LCD_DATA12__CSI_DATA20		0x0148 0x03d4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA12__EIM_DATA04		0x0148 0x03d4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17		0x0148 0x03d4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12		0x0148 0x03d4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY		0x0148 0x03d4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13		0x014c 0x03d8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK		0x014c 0x03d8 0x0608 1 1
+#define MX6UL_PAD_LCD_DATA13__CSI_DATA21		0x014c 0x03d8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA13__EIM_DATA05		0x014c 0x03d8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18		0x014c 0x03d8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13		0x014c 0x03d8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B		0x014c 0x03d8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14		0x0150 0x03dc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA		0x0150 0x03dc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA14__CSI_DATA22		0x0150 0x03dc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA14__EIM_DATA06		0x0150 0x03dc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19		0x0150 0x03dc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14		0x0150 0x03dc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4		0x0150 0x03dc 0x068c 8 0
+#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15		0x0154 0x03e0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA		0x0154 0x03e0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA15__CSI_DATA23		0x0154 0x03e0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA15__EIM_DATA07		0x0154 0x03e0 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20		0x0154 0x03e0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15		0x0154 0x03e0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5		0x0154 0x03e0 0x0690 8 0
+#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16		0x0158 0x03e4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX		0x0158 0x03e4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX		0x0158 0x03e4 0x0654 1 2
+#define MX6UL_PAD_LCD_DATA16__CSI_DATA01		0x0158 0x03e4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA16__EIM_DATA08		0x0158 0x03e4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21		0x0158 0x03e4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24		0x0158 0x03e4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6		0x0158 0x03e4 0x0694 8 0
+#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17		0x015c 0x03e8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX		0x015c 0x03e8 0x0654 1 3
+#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX		0x015c 0x03e8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA17__CSI_DATA00		0x015c 0x03e8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA17__EIM_DATA09		0x015c 0x03e8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22		0x015c 0x03e8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25		0x015c 0x03e8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7		0x015c 0x03e8 0x0698 8 0
+#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18		0x0160 0x03ec 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA18__PWM5_OUT			0x0160 0x03ec 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO		0x0160 0x03ec 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA18__CSI_DATA10		0x0160 0x03ec 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA18__EIM_DATA10		0x0160 0x03ec 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23		0x0160 0x03ec 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26		0x0160 0x03ec 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD		0x0160 0x03ec 0x0678 8 1
+#define MX6UL_PAD_LCD_DATA19__EIM_DATA11		0x0164 0x03f0 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24		0x0164 0x03f0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27		0x0164 0x03f0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK		0x0164 0x03f0 0x0670 8 1
+#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19		0x0164 0x03f0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA19__PWM6_OUT			0x0164 0x03f0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY		0x0164 0x03f0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA19__CSI_DATA11		0x0164 0x03f0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA20__EIM_DATA12		0x0168 0x03f4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25		0x0168 0x03f4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28		0x0168 0x03f4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0		0x0168 0x03f4 0x067c 8 1
+#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20		0x0168 0x03f4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX		0x0168 0x03f4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX		0x0168 0x03f4 0x065c 1 2
+#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK		0x0168 0x03f4 0x0534 2 0
+#define MX6UL_PAD_LCD_DATA20__CSI_DATA12		0x0168 0x03f4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21		0x016c 0x03f8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX		0x016c 0x03f8 0x065c 1 3
+#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX		0x016c 0x03f8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0		0x016c 0x03f8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA21__CSI_DATA13		0x016c 0x03f8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA21__EIM_DATA13		0x016c 0x03f8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26		0x016c 0x03f8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29		0x016c 0x03f8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1		0x016c 0x03f8 0x0680 8 1
+#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22		0x0170 0x03fc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT			0x0170 0x03fc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI		0x0170 0x03fc 0x053c 2 0
+#define MX6UL_PAD_LCD_DATA22__CSI_DATA14		0x0170 0x03fc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA22__EIM_DATA14		0x0170 0x03fc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27		0x0170 0x03fc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30		0x0170 0x03fc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2		0x0170 0x03fc 0x0684 8 0
+#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23		0x0174 0x0400 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA23__MQS_LEFT			0x0174 0x0400 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO		0x0174 0x0400 0x0538 2 0
+#define MX6UL_PAD_LCD_DATA23__CSI_DATA15		0x0174 0x0400 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA23__EIM_DATA15		0x0174 0x0400 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28		0x0174 0x0400 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31		0x0174 0x0400 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3		0x0174 0x0400 0x0688 8 1
+#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B		0x0178 0x0404 0x0000 0 0
+#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK			0x0178 0x0404 0x0670 1 2
+#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK		0x0178 0x0404 0x0000 2 0
+#define MX6UL_PAD_NAND_RE_B__KPP_ROW00			0x0178 0x0404 0x0000 3 0
+#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00			0x0178 0x0404 0x0000 4 0
+#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00			0x0178 0x0404 0x0000 5 0
+#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2			0x0178 0x0404 0x0000 8 0
+#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B		0x017c 0x0408 0x0000 0 0
+#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD			0x017c 0x0408 0x0678 1 2
+#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B		0x017c 0x0408 0x0000 2 0
+#define MX6UL_PAD_NAND_WE_B__KPP_COL00			0x017c 0x0408 0x0000 3 0
+#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01			0x017c 0x0408 0x0000 4 0
+#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01			0x017c 0x0408 0x0000 5 0
+#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3			0x017c 0x0408 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00		0x0180 0x040c 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0		0x0180 0x040c 0x067c 1 2
+#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B		0x0180 0x040c 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA00__KPP_ROW01		0x0180 0x040c 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA00__EIM_AD08			0x0180 0x040c 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02		0x0180 0x040c 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY		0x0180 0x040c 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01		0x0184 0x0410 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1		0x0184 0x0410 0x0680 1 2
+#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS		0x0184 0x0410 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA01__KPP_COL01		0x0184 0x0410 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA01__EIM_AD09			0x0184 0x0410 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03		0x0184 0x0410 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1		0x0184 0x0410 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02		0x0188 0x0414 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2		0x0188 0x0414 0x0684 1 1
+#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00		0x0188 0x0414 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA02__KPP_ROW02		0x0188 0x0414 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA02__EIM_AD10			0x0188 0x0414 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04		0x0188 0x0414 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2		0x0188 0x0414 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03		0x018c 0x0418 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3		0x018c 0x0418 0x0688 1 2
+#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01		0x018c 0x0418 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA03__KPP_COL02		0x018c 0x0418 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA03__EIM_AD11			0x018c 0x0418 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05		0x018c 0x0418 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3		0x018c 0x0418 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04		0x0190 0x041c 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4		0x0190 0x041c 0x068c 1 1
+#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02		0x0190 0x041c 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK		0x0190 0x041c 0x0564 3 1
+#define MX6UL_PAD_NAND_DATA04__EIM_AD12			0x0190 0x041c 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06		0x0190 0x041c 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX		0x0190 0x041c 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX		0x0190 0x041c 0x062c 8 2
+#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05		0x0194 0x0420 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5		0x0194 0x0420 0x0690 1 1
+#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03		0x0194 0x0420 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI		0x0194 0x0420 0x056c 3 1
+#define MX6UL_PAD_NAND_DATA05__EIM_AD13			0x0194 0x0420 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07		0x0194 0x0420 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX		0x0194 0x0420 0x062c 8 3
+#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX		0x0194 0x0420 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06		0x0198 0x0424 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6		0x0198 0x0424 0x0694 1 1
+#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK		0x0198 0x0424 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO		0x0198 0x0424 0x0568 3 1
+#define MX6UL_PAD_NAND_DATA06__EIM_AD14			0x0198 0x0424 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08		0x0198 0x0424 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS		0x0198 0x0424 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS		0x0198 0x0424 0x0628 8 4
+#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07		0x019c 0x0428 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7		0x019c 0x0428 0x0698 1 1
+#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B		0x019c 0x0428 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0		0x019c 0x0428 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA07__EIM_AD15			0x019c 0x0428 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09		0x019c 0x0428 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS		0x019c 0x0428 0x0628 8 5
+#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS		0x019c 0x0428 0x0000 8 0
+#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE			0x01a0 0x042c 0x0000 0 0
+#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B		0x01a0 0x042c 0x0000 1 0
+#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS			0x01a0 0x042c 0x0000 2 0
+#define MX6UL_PAD_NAND_ALE__PWM3_OUT			0x01a0 0x042c 0x0000 3 0
+#define MX6UL_PAD_NAND_ALE__EIM_ADDR17			0x01a0 0x042c 0x0000 4 0
+#define MX6UL_PAD_NAND_ALE__GPIO4_IO10			0x01a0 0x042c 0x0000 5 0
+#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1			0x01a0 0x042c 0x0000 8 0
+#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B		0x01a4 0x0430 0x0000 0 0
+#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B		0x01a4 0x0430 0x0000 1 0
+#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK		0x01a4 0x0430 0x0000 2 0
+#define MX6UL_PAD_NAND_WP_B__PWM4_OUT			0x01a4 0x0430 0x0000 3 0
+#define MX6UL_PAD_NAND_WP_B__EIM_BCLK			0x01a4 0x0430 0x0000 4 0
+#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11			0x01a4 0x0430 0x0000 5 0
+#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY			0x01a4 0x0430 0x0000 8 0
+#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B		0x01a8 0x0434 0x0000 0 0
+#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4		0x01a8 0x0434 0x0000 1 0
+#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00		0x01a8 0x0434 0x0000 2 0
+#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0		0x01a8 0x0434 0x0000 3 0
+#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B		0x01a8 0x0434 0x0000 4 0
+#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12		0x01a8 0x0434 0x0000 5 0
+#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX		0x01a8 0x0434 0x0000 8 0
+#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX		0x01a8 0x0434 0x0634 8 2
+#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B		0x01ac 0x0438 0x0000 0 0
+#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5		0x01ac 0x0438 0x0000 1 0
+#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01		0x01ac 0x0438 0x0000 2 0
+#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK		0x01ac 0x0438 0x0554 3 1
+#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B		0x01ac 0x0438 0x0000 4 0
+#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13		0x01ac 0x0438 0x0000 5 0
+#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX		0x01ac 0x0438 0x0634 8 3
+#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX		0x01ac 0x0438 0x0000 8 0
+#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B		0x01b0 0x043c 0x0000 0 0
+#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6		0x01b0 0x043c 0x0000 1 0
+#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02		0x01b0 0x043c 0x0000 2 0
+#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI		0x01b0 0x043c 0x055c 3 1
+#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18		0x01b0 0x043c 0x0000 4 0
+#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14		0x01b0 0x043c 0x0000 5 0
+#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS		0x01b0 0x043c 0x0000 8 0
+#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS		0x01b0 0x043c 0x0630 8 2
+#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE			0x01b4 0x0440 0x0000 0 0
+#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7		0x01b4 0x0440 0x0000 1 0
+#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03		0x01b4 0x0440 0x0000 2 0
+#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO			0x01b4 0x0440 0x0558 3 1
+#define MX6UL_PAD_NAND_CLE__EIM_ADDR16			0x01b4 0x0440 0x0000 4 0
+#define MX6UL_PAD_NAND_CLE__GPIO4_IO15			0x01b4 0x0440 0x0000 5 0
+#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS		0x01b4 0x0440 0x0630 8 3
+#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS		0x01b4 0x0440 0x0000 8 0
+#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS			0x01b8 0x0444 0x0000 0 0
+#define MX6UL_PAD_NAND_DQS__CSI_FIELD			0x01b8 0x0444 0x0530 1 1
+#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B		0x01b8 0x0444 0x0000 2 0
+#define MX6UL_PAD_NAND_DQS__PWM5_OUT			0x01b8 0x0444 0x0000 3 0
+#define MX6UL_PAD_NAND_DQS__EIM_WAIT			0x01b8 0x0444 0x0000 4 0
+#define MX6UL_PAD_NAND_DQS__GPIO4_IO16			0x01b8 0x0444 0x0000 5 0
+#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01		0x01b8 0x0444 0x0000 6 0
+#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK		0x01b8 0x0444 0x061c 8 1
+#define MX6UL_PAD_SD1_CMD__USDHC1_CMD			0x01bc 0x0448 0x0000 0 0
+#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1		0x01bc 0x0448 0x0000 1 0
+#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC			0x01bc 0x0448 0x0000 2 0
+#define MX6UL_PAD_SD1_CMD__SPDIF_OUT			0x01bc 0x0448 0x0000 3 0
+#define MX6UL_PAD_SD1_CMD__EIM_ADDR19			0x01bc 0x0448 0x0000 4 0
+#define MX6UL_PAD_SD1_CMD__GPIO2_IO16			0x01bc 0x0448 0x0000 5 0
+#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00		0x01bc 0x0448 0x0000 6 0
+#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR			0x01bc 0x0448 0x0000 8 0
+#define MX6UL_PAD_SD1_CLK__USDHC1_CLK			0x01c0 0x044c 0x0000 0 0
+#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2		0x01c0 0x044c 0x0000 1 0
+#define MX6UL_PAD_SD1_CLK__SAI2_MCLK			0x01c0 0x044c 0x0000 2 0
+#define MX6UL_PAD_SD1_CLK__SPDIF_IN			0x01c0 0x044c 0x0618 3 3
+#define MX6UL_PAD_SD1_CLK__EIM_ADDR20			0x01c0 0x044c 0x0000 4 0
+#define MX6UL_PAD_SD1_CLK__GPIO2_IO17			0x01c0 0x044c 0x0000 5 0
+#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC			0x01c0 0x044c 0x0664 8 2
+#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0		0x01c4 0x0450 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3		0x01c4 0x0450 0x0000 1 0
+#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC		0x01c4 0x0450 0x05fc 2 1
+#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX		0x01c4 0x0450 0x0000 3 0
+#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21			0x01c4 0x0450 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18			0x01c4 0x0450 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID		0x01c4 0x0450 0x04b8 8 2
+#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1		0x01c8 0x0454 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA1__GPT2_CLK			0x01c8 0x0454 0x05a0 1 1
+#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK		0x01c8 0x0454 0x05f8 2 1
+#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX		0x01c8 0x0454 0x0584 3 3
+#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22			0x01c8 0x0454 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19			0x01c8 0x0454 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR		0x01c8 0x0454 0x0000 8 0
+#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2		0x01cc 0x0458 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1		0x01cc 0x0458 0x0598 1 1
+#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA		0x01cc 0x0458 0x05f4 2 1
+#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX		0x01cc 0x0458 0x0000 3 0
+#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23			0x01cc 0x0458 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20			0x01cc 0x0458 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1			0x01cc 0x0458 0x0000 6 0
+#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC		0x01cc 0x0458 0x0660 8 2
+#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3		0x01d0 0x045c 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2		0x01d0 0x045c 0x059c 1 1
+#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA		0x01d0 0x045c 0x0000 2 0
+#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX		0x01d0 0x045c 0x0588 3 3
+#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24			0x01d0 0x045c 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21			0x01d0 0x045c 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2			0x01d0 0x045c 0x0000 6 0
+#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID		0x01d0 0x045c 0x04bc 8 2
+#define MX6UL_PAD_CSI_MCLK__CSI_MCLK			0x01d4 0x0460 0x0000 0 0
+#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B			0x01d4 0x0460 0x0674 1 0
+#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B		0x01d4 0x0460 0x0000 2 0
+#define MX6UL_PAD_CSI_MCLK__I2C1_SDA			0x01d4 0x0460 0x05a8 3 0
+#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B			0x01d4 0x0460 0x0000 4 0
+#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17			0x01d4 0x0460 0x0000 5 0
+#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL		0x01d4 0x0460 0x0000 6 0
+#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX		0x01d4 0x0460 0x0000 8 0
+#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX		0x01d4 0x0460 0x064c 8 0
+#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK		0x01d8 0x0464 0x0528 0 1
+#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP			0x01d8 0x0464 0x069c 1 2
+#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B		0x01d8 0x0464 0x0000 2 0
+#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL			0x01d8 0x0464 0x05a4 3 2
+#define MX6UL_PAD_CSI_PIXCLK__EIM_OE			0x01d8 0x0464 0x0000 4 0
+#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18		0x01d8 0x0464 0x0000 5 0
+#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5		0x01d8 0x0464 0x0000 6 0
+#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX		0x01d8 0x0464 0x064c 8 3
+#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX		0x01d8 0x0464 0x0000 8 0
+#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC			0x01dc 0x0468 0x052c 0 0
+#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK			0x01dc 0x0468 0x0670 1 0
+#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK		0x01dc 0x0468 0x0000 2 0
+#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA			0x01dc 0x0468 0x05b0 3 0
+#define MX6UL_PAD_CSI_VSYNC__EIM_RW			0x01dc 0x0468 0x0000 4 0
+#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19			0x01dc 0x0468 0x0000 5 0
+#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT			0x01dc 0x0468 0x0000 6 0
+#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS		0x01dc 0x0468 0x0648 8 0
+#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS		0x01dc 0x0468 0x0000 8 0
+#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC			0x01e0 0x046c 0x0524 0 0
+#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD			0x01e0 0x046c 0x0678 1 0
+#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD		0x01e0 0x046c 0x0000 2 0
+#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL			0x01e0 0x046c 0x05ac 3 0
+#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B			0x01e0 0x046c 0x0000 4 0
+#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20			0x01e0 0x046c 0x0000 5 0
+#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT			0x01e0 0x046c 0x0000 6 0
+#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS		0x01e0 0x046c 0x0000 8 0
+#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS		0x01e0 0x046c 0x0648 8 1
+#define MX6UL_PAD_CSI_DATA00__CSI_DATA02		0x01e4 0x0470 0x04c4 0 0
+#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0		0x01e4 0x0470 0x067c 1 0
+#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B		0x01e4 0x0470 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK		0x01e4 0x0470 0x0544 3 0
+#define MX6UL_PAD_CSI_DATA00__EIM_AD00			0x01e4 0x0470 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21		0x01e4 0x0470 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT		0x01e4 0x0470 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX		0x01e4 0x0470 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX		0x01e4 0x0470 0x0644 8 0
+#define MX6UL_PAD_CSI_DATA01__CSI_DATA03		0x01e8 0x0474 0x04c8 0 0
+#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1		0x01e8 0x0474 0x0680 1 0
+#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN		0x01e8 0x0474 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0		0x01e8 0x0474 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA01__EIM_AD01			0x01e8 0x0474 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22		0x01e8 0x0474 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK			0x01e8 0x0474 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX		0x01e8 0x0474 0x0644 8 1
+#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX		0x01e8 0x0474 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA02__CSI_DATA04		0x01ec 0x0478 0x04d8 0 1
+#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2		0x01ec 0x0478 0x0684 1 2
+#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD		0x01ec 0x0478 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI		0x01ec 0x0478 0x054c 3 1
+#define MX6UL_PAD_CSI_DATA02__EIM_AD02			0x01ec 0x0478 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23		0x01ec 0x0478 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC		0x01ec 0x0478 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS		0x01ec 0x0478 0x0640 8 5
+#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS		0x01ec 0x0478 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA03__CSI_DATA05		0x01f0 0x047c 0x04cc 0 0
+#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3		0x01f0 0x047c 0x0688 1 0
+#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD		0x01f0 0x047c 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO		0x01f0 0x047c 0x0548 3 0
+#define MX6UL_PAD_CSI_DATA03__EIM_AD03			0x01f0 0x047c 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24		0x01f0 0x047c 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK		0x01f0 0x047c 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS		0x01f0 0x047c 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS		0x01f0 0x047c 0x0640 8 0
+#define MX6UL_PAD_CSI_DATA04__CSI_DATA06		0x01f4 0x0480 0x04dc 0 1
+#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4		0x01f4 0x0480 0x068c 1 2
+#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK		0x01f4 0x0480 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK		0x01f4 0x0480 0x0534 3 1
+#define MX6UL_PAD_CSI_DATA04__EIM_AD04			0x01f4 0x0480 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25		0x01f4 0x0480 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC		0x01f4 0x0480 0x05ec 6 1
+#define MX6UL_PAD_CSI_DATA04__USDHC1_WP			0x01f4 0x0480 0x066c 8 2
+#define MX6UL_PAD_CSI_DATA05__CSI_DATA07		0x01f8 0x0484 0x04e0 0 1
+#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5		0x01f8 0x0484 0x0690 1 2
+#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B		0x01f8 0x0484 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0		0x01f8 0x0484 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA05__EIM_AD05			0x01f8 0x0484 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26		0x01f8 0x0484 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK		0x01f8 0x0484 0x05e8 6 1
+#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B		0x01f8 0x0484 0x0668 8 2
+#define MX6UL_PAD_CSI_DATA06__CSI_DATA08		0x01fc 0x0488 0x04e4 0 1
+#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6		0x01fc 0x0488 0x0694 1 2
+#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN		0x01fc 0x0488 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI		0x01fc 0x0488 0x053c 3 1
+#define MX6UL_PAD_CSI_DATA06__EIM_AD06			0x01fc 0x0488 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27		0x01fc 0x0488 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA		0x01fc 0x0488 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B		0x01fc 0x0488 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA07__CSI_DATA09		0x0200 0x048c 0x04e8 0 1
+#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7		0x0200 0x048c 0x0698 1 2
+#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD		0x0200 0x048c 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO		0x0200 0x048c 0x0538 3 1
+#define MX6UL_PAD_CSI_DATA07__EIM_AD07			0x0200 0x048c 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28		0x0200 0x048c 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA		0x0200 0x048c 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT		0x0200 0x048c 0x0000 8 0
 
 #endif /* __DTS_IMX6UL_PINFUNC_H */
diff --git a/sys/gnu/dts/arm/imx6ul-tx6ul-0010.dts b/sys/gnu/dts/arm/imx6ul-tx6ul-0010.dts
new file mode 100644
index 000000000000..8c2f3df79b47
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6ul-tx6ul-0010.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6ul.dtsi"
+#include "imx6ul-tx6ul.dtsi"
+
+/ {
+	model = "Ka-Ro electronics TXUL-0010 Module";
+	compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
+
+	aliases {
+		/delete-property/ mmc1;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6ul-tx6ul-0011.dts b/sys/gnu/dts/arm/imx6ul-tx6ul-0011.dts
new file mode 100644
index 000000000000..d82698e7d50f
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6ul-tx6ul-0011.dts
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6ul.dtsi"
+#include "imx6ul-tx6ul.dtsi"
+
+/ {
+	model = "Ka-Ro electronics TXUL-0011 Module";
+	compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
+
+	aliases {
+		mmc0 = &usdhc2;
+		mmc1 = &usdhc1;
+	};
+};
+
+&gpmi {
+	status = "disabled";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <4>;
+	no-1-8-v;
+	non-removable;
+	fsl,wp-controller;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/imx6ul-tx6ul-mainboard.dts b/sys/gnu/dts/arm/imx6ul-tx6ul-mainboard.dts
new file mode 100644
index 000000000000..d25899b71575
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6ul-tx6ul-mainboard.dts
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6ul.dtsi"
+#include "imx6ul-tx6ul.dtsi"
+
+/ {
+	model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard";
+	compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
+
+	aliases {
+		lcdif_24bit_pins_a = &pinctrl_disp0_3;
+		mmc0 = &usdhc1;
+		/delete-property/ mmc1;
+		serial2 = &uart3;
+		serial4 = &uart5;
+	};
+	/delete-node/ sound;
+};
+
+&can1 {
+	xceiver-supply = <&reg_3v3>;
+};
+
+&can2 {
+	xceiver-supply = <&reg_3v3>;
+};
+
+&ds1339 {
+	status = "disabled";
+};
+
+&fec1 {
+	pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>;
+	/delete-node/ mdio;
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
+	phy-mode = "rmii";
+	phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+	phy-supply = <&reg_3v3_etn>;
+	phy-handle = <&etnphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		etnphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_etnphy0_int>;
+			interrupt-parent = <&gpio5>;
+			interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+			interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>;
+			status = "okay";
+		};
+
+		etnphy1: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_etnphy1_int>;
+			interrupt-parent = <&gpio4>;
+			interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+			interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>;
+			status = "okay";
+		};
+	};
+};
+
+&i2c_gpio {
+	status = "disabled";
+};
+
+&i2c2 {
+	/delete-node/ codec@0a;
+	/delete-node/ touchscreen@48;
+
+	rtc: mcp7940x@6f {
+		compatible = "microchip,mcp7940x";
+		reg = <0x6f>;
+	};
+};
+
+&kpp {
+	status = "disabled";
+};
+
+&lcdif {
+	pinctrl-0 = <&pinctrl_disp0_3>;
+};
+
+&reg_usbotg_vbus{
+	status = "disabled";
+};
+
+&usdhc1 {
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	non-removable;
+	/delete-property/ cd-gpios;
+	cap-sdio-irq;
+};
+
+&uart1 {
+	pinctrl-0 = <&pinctrl_uart1>;
+	/delete-property/ fsl,uart-has-rtscts;
+};
+
+&uart2 {
+	pinctrl-0 = <&pinctrl_uart2>;
+	/delete-property/ fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	status = "okay";
+};
+
+&uart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart6>;
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart7>;
+	status = "okay";
+};
+
+&uart8 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart8>;
+	status = "disabled"; /* conflicts with LCDIF */
+};
+
+&iomuxc {
+	hoggrp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x0b0b0 /* WLAN_RESET */
+		>;
+	};
+
+	pinctrl_disp0_3: disp0grp-3 {
+		fsl,pins = <
+			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x10 /* LSCLK */
+			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x10 /* OE_ACD */
+			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x10 /* HSYNC */
+			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x10 /* VSYNC */
+			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x10
+			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x10
+			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x10
+			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x10
+			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x10
+			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x10
+			/* LCD_DATA08..09 not wired */
+			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x10
+			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x10
+			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x10
+			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x10
+			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x10
+			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x10
+			/* LCD_DATA16..17 not wired */
+			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x10
+			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x10
+			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x10
+			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x10
+			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x10
+			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x10
+		>;
+	};
+
+	pinctrl_enet2_mdio: enet2-mdiogrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x0b0b0
+			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x0b0b0
+			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x0b0b0
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x0b0b0
+			MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX	0x0b0b0
+		>;
+	};
+
+	pinctrl_uart6: uart6grp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x0b0b0
+			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x0b0b0
+		>;
+	};
+
+	pinctrl_uart7: uart7grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA16__UART7_DCE_TX	0x0b0b0
+			MX6UL_PAD_LCD_DATA17__UART7_DCE_RX	0x0b0b0
+		>;
+	};
+
+	pinctrl_uart8: uart8grp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA20__UART8_DCE_TX	0x0b0b0
+			MX6UL_PAD_LCD_DATA21__UART8_DCE_RX	0x0b0b0
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6ul-tx6ul.dtsi b/sys/gnu/dts/arm/imx6ul-tx6ul.dtsi
new file mode 100644
index 000000000000..437e9aad5920
--- /dev/null
+++ b/sys/gnu/dts/arm/imx6ul-tx6ul.dtsi
@@ -0,0 +1,973 @@
+/*
+ * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	aliases {
+		can0 = &can2;
+		can1 = &can1;
+		display = &display;
+		i2c0 = &i2c2;
+		i2c1 = &i2c_gpio;
+		i2c2 = &i2c1;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		lcdif_23bit_pins_a = &pinctrl_disp0_1;
+		lcdif_24bit_pins_a = &pinctrl_disp0_2;
+		pwm0 = &pwm5;
+		reg_can_xcvr = &reg_can_xcvr;
+		serial2 = &uart5;
+		serial4 = &uart3;
+		spi0 = &ecspi2;
+		spi1 = &spi_gpio;
+		stk5led = &user_led;
+		usbh1 = &usbotg2;
+		usbotg = &usbotg1;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0 0>; /* will be filled by U-Boot */
+	};
+
+	clocks {
+		mclk: mclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <26000000>;
+		};
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd_rst>;
+		enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+		pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
+		power-supply = <&reg_lcd_pwr>;
+		/*
+		 * a poor man's way to create a 1:1 relationship between
+		 * the PWM value and the actual duty cycle
+		 */
+		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
+				     10 11 12 13 14 15 16 17 18 19
+				     20 21 22 23 24 25 26 27 28 29
+				     30 31 32 33 34 35 36 37 38 39
+				     40 41 42 43 44 45 46 47 48 49
+				     50 51 52 53 54 55 56 57 58 59
+				     60 61 62 63 64 65 66 67 68 69
+				     70 71 72 73 74 75 76 77 78 79
+				     80 81 82 83 84 85 86 87 88 89
+				     90 91 92 93 94 95 96 97 98 99
+				    100>;
+		default-brightness-level = <50>;
+	};
+
+	i2c_gpio: i2c-gpio {
+		compatible = "i2c-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c_gpio>;
+		gpios = <
+			&gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
+			&gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
+		>;
+		clock-frequency = <400000>;
+		status = "okay";
+
+		ds1339: rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+			status = "disabled";
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		user_led: user {
+			label = "Heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_led>;
+			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	reg_3v3_etn: regulator-3v3etn {
+		compatible = "regulator-fixed";
+		regulator-name = "3V3_ETN";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_etnphy_power>;
+		gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_2v5: regulator-2v5 {
+		compatible = "regulator-fixed";
+		regulator-name = "2V5";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-always-on;
+	};
+
+	reg_3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_can_xcvr: regulator-canxcvr {
+		compatible = "regulator-fixed";
+		regulator-name = "CAN XCVR";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan_xcvr>;
+		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+		enable-active-low;
+	};
+
+	reg_lcd_pwr: regulator-lcdpwr {
+		compatible = "regulator-fixed";
+		regulator-name = "LCD POWER";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd_pwr>;
+		gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_usbh1_vbus: regulator-usbh1vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usbh1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
+		gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usbotg_vbus: regulator-usbotgvbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usbotg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
+		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	spi_gpio: spi-gpio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "spi-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_spi_gpio>;
+		gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+		gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+		gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+		num-chipselects = <2>;
+		cs-gpios = <
+			&gpio1 29 GPIO_ACTIVE_HIGH
+			&gpio1 10 GPIO_ACTIVE_HIGH
+		>;
+		status = "disabled";
+
+		spi@0 {
+			compatible = "spidev";
+			reg = <0>;
+			spi-max-frequency = <660000>;
+		};
+
+		spi@1 {
+			compatible = "spidev";
+			reg = <1>;
+			spi-max-frequency = <660000>;
+		};
+	};
+
+	sound {
+		compatible = "karo,imx6ul-tx6ul-sgtl5000",
+			     "simple-audio-card";
+		simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&codec_dai>;
+		simple-audio-card,frame-master = <&codec_dai>;
+		simple-audio-card,widgets =
+			"Microphone", "Mic Jack",
+			"Line", "Line In",
+			"Line", "Line Out",
+			"Headphone", "Headphone Jack";
+		simple-audio-card,routing =
+			"MIC_IN", "Mic Jack",
+			"Mic Jack", "Mic Bias",
+			"Headphone Jack", "HP_OUT";
+
+		cpu_dai: simple-audio-card,cpu {
+			sound-dai = <&sai2>;
+		};
+
+		codec_dai: simple-audio-card,codec {
+			sound-dai = <&sgtl5000>;
+		};
+	};
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can_xcvr>;
+	status = "okay";
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can_xcvr>;
+	status = "okay";
+};
+
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2>;
+	fsl,spi-num-chipselects = <2>;
+	cs-gpios = <
+		&gpio1 29 GPIO_ACTIVE_HIGH
+		&gpio1 10 GPIO_ACTIVE_HIGH
+	>;
+	status = "disabled";
+
+	spidev0: spi@0 {
+		compatible = "spidev";
+		reg = <0>;
+		spi-max-frequency = <60000000>;
+	};
+
+	spidev1: spi@1 {
+		compatible = "spidev";
+		reg = <1>;
+		spi-max-frequency = <60000000>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
+	phy-mode = "rmii";
+	phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
+	phy-supply = <&reg_3v3_etn>;
+	phy-handle = <&etnphy0>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		etnphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_etnphy0_int>;
+			interrupt-parent = <&gpio5>;
+			interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+			status = "okay";
+		};
+
+		etnphy1: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_etnphy1_int>;
+			interrupt-parent = <&gpio4>;
+			interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+			status = "okay";
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
+	phy-mode = "rmii";
+	phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+	phy-supply = <&reg_3v3_etn>;
+	phy-handle = <&etnphy1>;
+	status = "disabled";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	nand-on-flash-bbt;
+	fsl,no-blockmark-swap;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	sgtl5000: codec@0a {
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		#sound-dai-cells = <0>;
+		VDDA-supply = <&reg_2v5>;
+		VDDIO-supply = <&reg_3v3>;
+		clocks = <&mclk>;
+	};
+
+	polytouch: polytouch@38 {
+		compatible = "edt,edt-ft5x06";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_edt_ft5x06>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+		reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+		wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
+		wakeup-source;
+	};
+
+	touchscreen: touchscreen@48 {
+		compatible = "ti,tsc2007";
+		reg = <0x48>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_tsc2007>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <26 IRQ_TYPE_NONE>;
+		gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+		ti,x-plate-ohms = <660>;
+		wakeup-source;
+	};
+};
+
+&kpp {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_kpp>;
+	/* sample keymap */
+	/* row/col 0..3 are mapped to KPP row/col 4..7 */
+	linux,keymap = <
+		MATRIX_KEY(4, 4, KEY_POWER)
+		MATRIX_KEY(4, 5, KEY_KP0)
+		MATRIX_KEY(4, 6, KEY_KP1)
+		MATRIX_KEY(4, 7, KEY_KP2)
+		MATRIX_KEY(5, 4, KEY_KP3)
+		MATRIX_KEY(5, 5, KEY_KP4)
+		MATRIX_KEY(5, 6, KEY_KP5)
+		MATRIX_KEY(5, 7, KEY_KP6)
+		MATRIX_KEY(6, 4, KEY_KP7)
+		MATRIX_KEY(6, 5, KEY_KP8)
+		MATRIX_KEY(6, 6, KEY_KP9)
+	>;
+	status = "okay";
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_disp0_1>;
+	lcd-supply = <&reg_lcd_pwr>;
+	display = <&display>;
+	status = "okay";
+
+	display: display@di0 {
+		bits-per-pixel = <32>;
+		bus-width = <24>;
+		status = "okay";
+
+		display-timings {
+			VGA {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <48>;
+				hsync-len = <96>;
+				hfront-porch = <16>;
+				vback-porch = <31>;
+				vsync-len = <2>;
+				vfront-porch = <12>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			ETV570 {
+				clock-frequency = <25200000>;
+				hactive = <640>;
+				vactive = <480>;
+				hback-porch = <114>;
+				hsync-len = <30>;
+				hfront-porch = <16>;
+				vback-porch = <32>;
+				vsync-len = <3>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			ET0350 {
+				clock-frequency = <6413760>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <34>;
+				hsync-len = <34>;
+				hfront-porch = <20>;
+				vback-porch = <15>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			ET0430 {
+				clock-frequency = <9009000>;
+				hactive = <480>;
+				vactive = <272>;
+				hback-porch = <2>;
+				hsync-len = <41>;
+				hfront-porch = <2>;
+				vback-porch = <2>;
+				vsync-len = <10>;
+				vfront-porch = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+
+			ET0500 {
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			ET0700 { /* same as ET0500 */
+				clock-frequency = <33264000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <88>;
+				hsync-len = <128>;
+				hfront-porch = <40>;
+				vback-porch = <33>;
+				vsync-len = <2>;
+				vfront-porch = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+
+			ETQ570 {
+				clock-frequency = <6596040>;
+				hactive = <320>;
+				vactive = <240>;
+				hback-porch = <38>;
+				hsync-len = <30>;
+				hfront-porch = <30>;
+				vback-porch = <16>;
+				vsync-len = <3>;
+				vfront-porch = <4>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <1>;
+			};
+		};
+	};
+};
+
+&pwm5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm5>;
+	#pwm-cells = <3>;
+	status = "okay";
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usbotg_vbus>;
+	dr_mode = "peripheral";
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usbh1_vbus>;
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
+	bus-width = <4>;
+	no-1-8-v;
+	cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
+	fsl,wp-controller;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+	};
+
+	pinctrl_led: ledgrp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x0b0b0 /* LED */
+		>;
+	};
+
+	pinctrl_disp0_1: disp0grp-1 {
+		fsl,pins = <
+			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x10 /* LSCLK */
+			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x10 /* OE_ACD */
+			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x10 /* HSYNC */
+			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x10 /* VSYNC */
+			/* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
+			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x10
+			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x10
+			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x10
+			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x10
+			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x10
+			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x10
+			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x10
+			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x10
+			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x10
+			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x10
+			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x10
+			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x10
+			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x10
+			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x10
+			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x10
+			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x10
+			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x10
+			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x10
+			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x10
+			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x10
+			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x10
+			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x10
+			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x10
+		>;
+	};
+
+	pinctrl_disp0_2: disp0grp-2 {
+		fsl,pins = <
+			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x10 /* LSCLK */
+			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x10 /* OE_ACD */
+			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x10 /* HSYNC */
+			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x10 /* VSYNC */
+			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00	0x10
+			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x10
+			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x10
+			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x10
+			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x10
+			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x10
+			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x10
+			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x10
+			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x10
+			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x10
+			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x10
+			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x10
+			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x10
+			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x10
+			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x10
+			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x10
+			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x10
+			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x10
+			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x10
+			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x10
+			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x10
+			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x10
+			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x10
+			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x10
+		>;
+	};
+
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x0b0b0 /* CSPI_SS */
+			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x0b0b0 /* CSPI_SS */
+			MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI	0x0b0b0 /* CSPI_MOSI */
+			MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO	0x0b0b0 /* CSPI_MISO */
+			MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK	0x0b0b0 /* CSPI_SCLK */
+		>;
+	};
+
+	pinctrl_edt_ft5x06: edt-ft5x06grp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0 /* Interrupt */
+			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x1b0b0 /* Reset */
+			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x1b0b0 /* Wake */
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x000b0
+			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x000b0
+			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x000b0
+			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x000b0
+			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x000b0
+			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x000b0
+			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x000b0
+			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x400000b1
+		>;
+	};
+
+	pinctrl_enet2: enet2grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x000b0
+			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x000b0
+			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x000b0
+			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x000b0
+			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x000b0
+			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x000b0
+			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x000b0
+			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x400000b1
+		>;
+	};
+
+	pinctrl_enet1_mdio: enet1-mdiogrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x0b0b0
+			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
+		>;
+	};
+
+	pinctrl_etnphy_power: etnphy-pwrgrp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x0b0b0 /* ETN PHY POWER */
+		>;
+	};
+
+	pinctrl_etnphy0_int: etnphy-intgrp-0 {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x0b0b0 /* ETN PHY INT */
+		>;
+	};
+
+	pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x0b0b0 /* ETN PHY RESET */
+		>;
+	};
+
+	pinctrl_etnphy1_int: etnphy-intgrp-1 {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x0b0b0 /* ETN PHY INT */
+		>;
+	};
+
+	pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
+		fsl,pins = <
+			MX6UL_PAD_CSI_DATA07__GPIO4_IO28	0x0b0b0 /* ETN PHY RESET */
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
+			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x0b0b0
+			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x0b0b0
+		>;
+	};
+
+	pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA00__GPIO3_IO05	0x0b0b0 /* Flexcan XCVR enable */
+		>;
+	};
+
+	pinctrl_gpmi_nand: gpminandgrp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0b1
+			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0b1
+			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
+			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b000
+			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0b1
+			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
+			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
+			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0b1
+			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0b1
+			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0b1
+			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0b1
+			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0b1
+			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0b1
+			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x0b0b1
+			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0b1
+		>;
+	};
+
+	pinctrl_i2c_gpio: i2c-gpiogrp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x4001b8b1 /* I2C SCL */
+			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x4001b8b1 /* I2C SDA */
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO00__I2C2_SCL		0x4001b8b1
+			MX6UL_PAD_GPIO1_IO01__I2C2_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_kpp: kppgrp {
+		fsl,pins = <
+			MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05	0x1b0b0
+			MX6UL_PAD_ENET2_TX_EN__KPP_COL06	0x1b0b0
+			MX6UL_PAD_ENET2_RX_ER__KPP_COL07	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04	0x1b0b0
+			MX6UL_PAD_ENET2_RX_EN__KPP_ROW05	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06	0x1b0b0
+			MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07	0x1b0b0
+		>;
+	};
+
+	pinctrl_lcd_pwr: lcd-pwrgrp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x0b0b0 /* LCD Power Enable */
+		>;
+	};
+
+	pinctrl_lcd_rst: lcd-rstgrp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_RESET__GPIO3_IO04	0x0b0b0 /* LCD Reset */
+		>;
+	};
+
+	pinctrl_pwm5: pwm5grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_DQS__PWM5_OUT		0x0b0b0
+		>;
+	};
+
+	pinctrl_sai2: sai2grp {
+		fsl,pins = <
+			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x0b0b0 /* SSI1_RXD */
+			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x0b0b0 /* SSI1_TXD */
+			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x0b0b0 /* SSI1_CLK */
+			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x0b0b0 /* SSI1_FS */
+		>;
+	};
+
+	pinctrl_spi_gpio: spi-gpiogrp {
+		fsl,pins = <
+			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x0b0b0 /* CSPI_SS */
+			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x0b0b0 /* CSPI_SS */
+			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30	0x0b0b0 /* CSPI_MOSI */
+			MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31	0x0b0b0 /* CSPI_MISO */
+			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x0b0b0 /* CSPI_SCLK */
+		>;
+	};
+
+	pinctrl_tsc2007: tsc2007grp {
+		fsl,pins = <
+			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x1b0b0 /* Interrupt */
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x0b0b0
+			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x0b0b0
+		>;
+	};
+
+	pinctrl_uart1_rtscts: uart1-rtsctsgrp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS	0x0b0b0
+			MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS	0x0b0b0
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x0b0b0
+			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x0b0b0
+		>;
+	};
+
+	pinctrl_uart2_rtscts: uart2-rtsctsgrp {
+		fsl,pins = <
+			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x0b0b0
+			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x0b0b0
+		>;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX	0x0b0b0
+			MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX	0x0b0b0
+		>;
+	};
+
+	pinctrl_uart5_rtscts: uart5-rtsctsgrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x0b0b0
+			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x0b0b0
+		>;
+	};
+
+	pinctrl_usbh1_oc: usbh1-ocgrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x17059 /* USBH1_OC */
+		>;
+	};
+
+	pinctrl_usbh1_vbus: usbh1-vbusgrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x0b0b0 /* USBH1_VBUSEN */
+		>;
+	};
+
+	pinctrl_usbotg_oc: usbotg-ocgrp {
+		fsl,pins = <
+			MX6UL_PAD_UART3_RTS_B__GPIO1_IO27	0x17059 /* USBOTG_OC */
+		>;
+	};
+
+	pinctrl_usbotg_vbus: usbotg-vbusgrp {
+		fsl,pins = <
+			MX6UL_PAD_UART3_CTS_B__GPIO1_IO26	0x1b0b0 /* USBOTG_VBUSEN */
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x070b1
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x07099
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x070b1
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x070b1
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x070b1
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x070b1
+		>;
+	};
+
+	pinctrl_usdhc1_cd: usdhc1cdgrp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x170b0 /* SD1 CD */
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x070b1
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x070b1
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x070b1
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x070b1
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x070b1
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x070b1
+			/* eMMC RESET */
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B	0x170b0
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx6ul.dtsi b/sys/gnu/dts/arm/imx6ul.dtsi
index 99b646506fc9..4356b655ef02 100644
--- a/sys/gnu/dts/arm/imx6ul.dtsi
+++ b/sys/gnu/dts/arm/imx6ul.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/clock/imx6ul-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "imx6ul-pinfunc.h"
 #include "skeleton.dtsi"
@@ -54,15 +55,15 @@
 			clock-latency = <61036>; /* two CLK32 periods */
 			operating-points = <
 				/* kHz	uV */
-				528000	1250000
-				396000	1150000
-				198000	1150000
+				528000	1175000
+				396000	1025000
+				198000	950000
 			>;
 			fsl,soc-operating-points = <
 				/* KHz	uV */
-				528000	1250000
-				396000	1150000
-				198000	1150000
+				528000	1175000
+				396000	1175000
+				198000	1175000
 			>;
 			clocks = <&clks IMX6UL_CLK_ARM>,
 				 <&clks IMX6UL_CLK_PLL2_BUS>,
@@ -140,6 +141,39 @@
 			reg = <0x00900000 0x20000>;
 		};
 
+		dma_apbh: dma-apbh@01804000 {
+			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+			reg = <0x01804000 0x2000>;
+			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 13 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			clocks = <&clks IMX6UL_CLK_APBHDMA>;
+		};
+
+		gpmi: gpmi-nand@01806000         {
+			compatible = "fsl,imx6q-gpmi-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
+			reg-names = "gpmi-nand", "bch";
+			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "bch";
+			clocks = <&clks IMX6UL_CLK_GPMI_IO>,
+				 <&clks IMX6UL_CLK_GPMI_APB>,
+				 <&clks IMX6UL_CLK_GPMI_BCH>,
+				 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
+				 <&clks IMX6UL_CLK_PER_BCH>;
+			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+				      "gpmi_bch_apb", "per1_bch";
+			dmas = <&dma_apbh 0>;
+			dma-names = "rx-tx";
+			status = "disabled";
+		};
+
 		aips1: aips-bus@02000000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
@@ -234,6 +268,126 @@
 					clock-names = "ipg", "per";
 					status = "disabled";
 				};
+
+				sai1: sai@02028000 {
+					#sound-dai-cells = <0>;
+					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+					reg = <0x02028000 0x4000>;
+					interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
+						 <&clks IMX6UL_CLK_SAI1>,
+						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
+					clock-names = "bus", "mclk1", "mclk2", "mclk3";
+					dmas = <&sdma 35 24 0>,
+					       <&sdma 36 24 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+
+				sai2: sai@0202c000 {
+					#sound-dai-cells = <0>;
+					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+					reg = <0x0202c000 0x4000>;
+					interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
+						 <&clks IMX6UL_CLK_SAI2>,
+						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
+					clock-names = "bus", "mclk1", "mclk2", "mclk3";
+					dmas = <&sdma 37 24 0>,
+					       <&sdma 38 24 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+
+				sai3: sai@02030000 {
+					#sound-dai-cells = <0>;
+					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+					reg = <0x02030000 0x4000>;
+					interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
+						 <&clks IMX6UL_CLK_SAI3>,
+						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
+					clock-names = "bus", "mclk1", "mclk2", "mclk3";
+					dmas = <&sdma 39 24 0>,
+					       <&sdma 40 24 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+			};
+
+			tsc: tsc@02040000 {
+				compatible = "fsl,imx6ul-tsc";
+				reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_IPG>,
+					 <&clks IMX6UL_CLK_ADC2>;
+				clock-names = "tsc", "adc";
+				status = "disabled";
+			};
+
+			pwm1: pwm@02080000 {
+				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+				reg = <0x02080000 0x4000>;
+				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_PWM1>,
+					 <&clks IMX6UL_CLK_PWM1>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			pwm2: pwm@02084000 {
+				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+				reg = <0x02084000 0x4000>;
+				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_PWM2>,
+					 <&clks IMX6UL_CLK_PWM2>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			pwm3: pwm@02088000 {
+				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+				reg = <0x02088000 0x4000>;
+				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_PWM3>,
+					 <&clks IMX6UL_CLK_PWM3>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			pwm4: pwm@0208c000 {
+				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
+				reg = <0x0208c000 0x4000>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_PWM4>,
+					 <&clks IMX6UL_CLK_PWM4>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			can1: flexcan@02090000 {
+				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
+				reg = <0x02090000 0x4000>;
+				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
+					 <&clks IMX6UL_CLK_CAN1_SERIAL>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			can2: flexcan@02094000 {
+				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
+				reg = <0x02094000 0x4000>;
+				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
+					 <&clks IMX6UL_CLK_CAN2_SERIAL>;
+				clock-names = "ipg", "per";
+				status = "disabled";
 			};
 
 			gpt1: gpt@02098000 {
@@ -317,6 +471,14 @@
 				status = "disabled";
 			};
 
+			kpp: kpp@020b8000 {
+				compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
+				reg = <0x020b8000 0x4000>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_KPP>;
+				status = "disabled";
+			};
+
 			wdog1: wdog@020bc000 {
 				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 				reg = <0x020bc000 0x4000>;
@@ -487,49 +649,65 @@
 				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 				reg = <0x020e8000 0x4000>;
 				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6UL_CLK_DUMMY>,
-					 <&clks IMX6UL_CLK_DUMMY>;
+				clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
+					 <&clks IMX6UL_CLK_GPT2_SERIAL>;
 				clock-names = "ipg", "per";
 			};
 
+			sdma: sdma@020ec000 {
+				compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
+					     "fsl,imx35-sdma";
+				reg = <0x020ec000 0x4000>;
+				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_SDMA>,
+					 <&clks IMX6UL_CLK_SDMA>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <3>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+			};
+
 			pwm5: pwm@020f0000 {
 				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 				reg = <0x020f0000 0x4000>;
 				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6UL_CLK_DUMMY>,
-					 <&clks IMX6UL_CLK_DUMMY>;
+				clocks = <&clks IMX6UL_CLK_PWM5>,
+					 <&clks IMX6UL_CLK_PWM5>;
 				clock-names = "ipg", "per";
 				#pwm-cells = <2>;
+				status = "disabled";
 			};
 
 			pwm6: pwm@020f4000 {
 				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 				reg = <0x020f4000 0x4000>;
 				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6UL_CLK_DUMMY>,
-					 <&clks IMX6UL_CLK_DUMMY>;
+				clocks = <&clks IMX6UL_CLK_PWM6>,
+					 <&clks IMX6UL_CLK_PWM6>;
 				clock-names = "ipg", "per";
 				#pwm-cells = <2>;
+				status = "disabled";
 			};
 
 			pwm7: pwm@020f8000 {
 				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 				reg = <0x020f8000 0x4000>;
 				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6UL_CLK_DUMMY>,
-					 <&clks IMX6UL_CLK_DUMMY>;
+				clocks = <&clks IMX6UL_CLK_PWM7>,
+					 <&clks IMX6UL_CLK_PWM7>;
 				clock-names = "ipg", "per";
 				#pwm-cells = <2>;
+				status = "disabled";
 			};
 
 			pwm8: pwm@020fc000 {
 				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 				reg = <0x020fc000 0x4000>;
 				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6UL_CLK_DUMMY>,
-					 <&clks IMX6UL_CLK_DUMMY>;
+				clocks = <&clks IMX6UL_CLK_PWM8>,
+					 <&clks IMX6UL_CLK_PWM8>;
 				clock-names = "ipg", "per";
 				#pwm-cells = <2>;
+				status = "disabled";
 			};
 		};
 
@@ -590,17 +768,6 @@
 				status = "disabled";
 			};
 
-			tsc: tsc@02040000 {
-				compatible = "fsl,imx6ul-tsc";
-				reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
-				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6UL_CLK_IPG>,
-					 <&clks IMX6UL_CLK_ADC2>;
-				clock-names = "tsc", "adc";
-				status = "disabled";
-			};
-
 			usdhc1: usdhc@02190000 {
 				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 				reg = <0x02190000 0x4000>;
@@ -672,6 +839,17 @@
 				reg = <0x021b0000 0x4000>;
 			};
 
+			lcdif: lcdif@021c8000 {
+				compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
+				reg = <0x021c8000 0x4000>;
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
+					 <&clks IMX6UL_CLK_LCDIF_APB>,
+					 <&clks IMX6UL_CLK_DUMMY>;
+				clock-names = "pix", "axi", "disp_axi";
+				status = "disabled";
+			};
+
 			qspi: qspi@021e0000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
diff --git a/sys/gnu/dts/arm/imx7d-nitrogen7.dts b/sys/gnu/dts/arm/imx7d-nitrogen7.dts
new file mode 100644
index 000000000000..1ce97800f0c5
--- /dev/null
+++ b/sys/gnu/dts/arm/imx7d-nitrogen7.dts
@@ -0,0 +1,745 @@
+/*
+ * Copyright 2016 Boundary Devices, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx7d.dtsi"
+
+/ {
+	model = "Boundary Devices i.MX7 Nitrogen7 Board";
+	compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
+
+	aliases {
+		fb_lcd = &lcdif;
+		t_lcd = &t_lcd;
+	};
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	backlight-j9 {
+		compatible = "gpio-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_backlight_j9>;
+		gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		default-on;
+	};
+
+	backlight-j20 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
+
+	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg2_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_can2_3v3: regulator-can2-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "can2-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_vref_1v8: regulator-vref-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vref-1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	reg_vref_3v3: regulator-vref-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vref-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_wlan: regulator-wlan {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
+		clock-names = "slow";
+		regulator-name = "reg_wlan";
+		startup-delay-us = <70000>;
+		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&adc2 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&clks {
+	assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
+			  <&clks IMX7D_CLKO2_ROOT_DIV>;
+	assigned-clock-parents = <&clks IMX7D_CKIL>;
+	assigned-clock-rates = <0>, <32768>;
+};
+
+&cpu0 {
+	arm-supply = <&sw1a_reg>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <100000000>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@4 {
+			reg = <4>;
+		};
+	};
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_3v3>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pfuze3000@08 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	rtc@68 {
+		compatible = "rv4162";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c2_rv4162>;
+		reg = <0x68>;
+		interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	touch@48 {
+		compatible = "ti,tsc2004";
+		reg = <0x48>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
+		interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
+		wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	codec: wm8960@1a {
+		compatible = "wlf,wm8960";
+		reg = <0x1a>;
+		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+		clock-names = "mclk";
+		wlf,shared-lrclk;
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	lcd-supply = <&reg_vref_3v3>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: lcd-display {
+		bits-per-pixel = <16>;
+		bus-width = <18>;
+
+		display-timings {
+			native-mode = <&t_lcd>;
+			t_lcd: t_lcd_default {
+				/* default to Okaya display */
+				clock-frequency = <30000000>;
+				hactive = <800>;
+				vactive = <480>;
+				hfront-porch = <40>;
+				hback-porch = <40>;
+				hsync-len = <48>;
+				vback-porch = <29>;
+				vfront-porch = <13>;
+				vsync-len = <3>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart6>;
+	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1>;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg2>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&vgen3_reg>;
+	bus-width = <4>;
+	fsl,tuning-step = <2>;
+	wakeup-source;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&usdhc2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <4>;
+	non-removable;
+	vmmc-supply = <&reg_wlan>;
+	cap-power-off-card;
+	keep-power-in-suspend;
+	status = "okay";
+
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1271";
+		reg = <2>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+		ref-clock-frequency = <38400000>;
+	};
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+	assigned-clock-rates = <400000000>;
+	bus-width = <8>;
+	fsl,tuning-step = <2>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog1>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
+
+	pinctrl_hog_1: hoggrp-1 {
+		fsl,pins = <
+			MX7D_PAD_SD3_RESET_B__GPIO6_IO11	0x5d
+			MX7D_PAD_GPIO1_IO13__GPIO1_IO13		0x7d
+			MX7D_PAD_ECSPI2_MISO__GPIO4_IO22	0x7d
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x3
+			MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x3
+			MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1		0x3
+			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x71
+			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x71
+			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x71
+			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x71
+			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x71
+			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x71
+			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x71
+			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x11
+			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x11
+			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x11
+			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x71
+			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x11
+			MX7D_PAD_SD3_STROBE__GPIO6_IO10			0x75
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x7d
+			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x7d
+			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x7d
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
+			MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
+			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
+		>;
+	};
+
+	pinctrl_i2c2_rv4162: i2c2-rv4162grp {
+		fsl,pins = <
+			MX7D_PAD_EPDC_DATA15__GPIO2_IO15	0x7d
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX7D_PAD_I2C3_SDA__I2C3_SDA		0x4000007f
+			MX7D_PAD_I2C3_SCL__I2C3_SCL		0x4000007f
+		>;
+	};
+
+	pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
+		fsl,pins = <
+			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x79
+			MX7D_PAD_SD2_WP__GPIO5_IO10		0x7d
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX7D_PAD_I2C4_SDA__I2C4_SDA		0x4000007f
+			MX7D_PAD_I2C4_SCL__I2C4_SCL		0x4000007f
+		>;
+	};
+
+	pinctrl_j2: j2grp {
+		fsl,pins = <
+			MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15	0x7d
+			MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x7d
+			MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12	0x7d
+			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x7d
+			MX7D_PAD_SD1_WP__GPIO5_IO1		0x7d
+			MX7D_PAD_EPDC_SDSHR__GPIO2_IO19		0x7d
+			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x7d
+			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x7d
+			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x7d
+			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x7d
+			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x7d
+			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x7d
+			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x7d
+			MX7D_PAD_EPDC_DATA12__GPIO2_IO12	0x7d
+			MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14	0x7d
+			MX7D_PAD_EPDC_DATA13__GPIO2_IO13	0x7d
+			MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13	0x7d
+			MX7D_PAD_SD2_CD_B__GPIO5_IO9		0x7d
+			MX7D_PAD_EPDC_GDCLK__GPIO2_IO24		0x7d
+			MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21	0x7d
+			MX7D_PAD_EPDC_GDOE__GPIO2_IO25		0x7d
+			MX7D_PAD_EPDC_GDRL__GPIO2_IO26		0x7d
+			MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22	0x7d
+			MX7D_PAD_EPDC_SDCE0__GPIO2_IO20		0x7d
+			MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20	0x7d
+			MX7D_PAD_EPDC_SDCE1__GPIO2_IO21		0x7d
+			MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19	0x7d
+			MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x7d
+			MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x7d
+			MX7D_PAD_EPDC_GDSP__GPIO2_IO27		0x7d
+			MX7D_PAD_EPDC_SDCLK__GPIO2_IO16		0x7d
+			MX7D_PAD_EPDC_SDLE__GPIO2_IO17		0x7d
+			MX7D_PAD_EPDC_SDOE__GPIO2_IO18		0x7d
+			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x7d
+			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x7d
+		>;
+	};
+
+	pinctrl_lcdif_dat: lcdifdatgrp {
+		fsl,pins = <
+			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
+			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
+			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
+			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
+			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
+			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
+			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
+			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
+			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
+			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
+			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
+			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
+			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
+			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
+			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
+			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
+			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
+			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
+			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
+			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
+			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
+			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
+			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
+			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
+		>;
+	};
+
+	pinctrl_lcdif_ctrl: lcdifctrlgrp {
+		fsl,pins = <
+			MX7D_PAD_LCD_CLK__LCD_CLK		0x79
+			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79
+			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79
+			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO09__PWM2_OUT		0x7d
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
+			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX	0x79
+			MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX	0x79
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x79
+			MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x79
+			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x7d
+		>;
+	};
+
+	pinctrl_uart6: uart6grp {
+		fsl,pins = <
+			MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX	0x79
+			MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX	0x79
+			MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS	0x79
+			MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS	0x79
+		>;
+	};
+
+	pinctrl_usbotg2: usbotg2grp {
+		fsl,pins = <
+			MX7D_PAD_UART3_RTS_B__USB_OTG2_OC	0x7d
+			MX7D_PAD_UART3_CTS_B__GPIO4_IO7		0x14
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
+			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
+			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
+			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
+			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
+			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
+			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x75
+			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x75
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX7D_PAD_SD2_CMD__SD2_CMD		0x59
+			MX7D_PAD_SD2_CLK__SD2_CLK		0x19
+			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
+			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
+			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
+			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
+			MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20	0x59
+			MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x59
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
+			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
+			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
+			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
+			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
+			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
+			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
+			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
+			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
+			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
+		>;
+	};
+};
+
+&iomuxc_lpsr {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_2>;
+
+	pinctrl_hog_2: hoggrp-2 {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO02__GPIO1_IO2		0x7d
+			MX7D_PAD_GPIO1_IO03__CCM_CLKO2		0x7d
+		>;
+	};
+
+	pinctrl_backlight_j9: backlightj9grp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO07__GPIO1_IO7		0x7d
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO01__PWM1_OUT		0x7d
+		>;
+	};
+
+	pinctrl_usbotg1: usbotg1grp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO04__USB_OTG1_OC	0x7d
+			MX7D_PAD_GPIO1_IO05__GPIO1_IO5		0x14
+		>;
+	};
+
+	pinctrl_wdog1: wdog1grp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B	0x75
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/imx7d-sbc-imx7.dts b/sys/gnu/dts/arm/imx7d-sbc-imx7.dts
index d63c597c0783..f8a868552707 100644
--- a/sys/gnu/dts/arm/imx7d-sbc-imx7.dts
+++ b/sys/gnu/dts/arm/imx7d-sbc-imx7.dts
@@ -22,7 +22,7 @@
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-	enable-sdio-wakeup;
+	wakeup-source;
 	status = "okay";
 };
 
diff --git a/sys/gnu/dts/arm/imx7d-sdb.dts b/sys/gnu/dts/arm/imx7d-sdb.dts
index b2c453662905..b267f79e3059 100644
--- a/sys/gnu/dts/arm/imx7d-sdb.dts
+++ b/sys/gnu/dts/arm/imx7d-sdb.dts
@@ -296,7 +296,7 @@
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-	enable-sdio-wakeup;
+	wakeup-source;
 	keep-power-in-suspend;
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/imx7d.dtsi b/sys/gnu/dts/arm/imx7d.dtsi
index 25ad30978740..6b3faa298417 100644
--- a/sys/gnu/dts/arm/imx7d.dtsi
+++ b/sys/gnu/dts/arm/imx7d.dtsi
@@ -119,6 +119,15 @@
 		clock-output-names = "osc";
 	};
 
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupt-parent = <&intc>;
+	};
+
 	etr@30086000 {
 		compatible = "arm,coresight-tmc", "arm,primecell";
 		reg = <0x30086000 0x1000>;
@@ -642,6 +651,17 @@
 				#pwm-cells = <2>;
 				status = "disabled";
 			};
+
+			lcdif: lcdif@30730000 {
+				compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
+				reg = <0x30730000 0x10000>;
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
+					<&clks IMX7D_CLK_DUMMY>,
+					<&clks IMX7D_CLK_DUMMY>;
+				clock-names = "pix", "axi", "disp_axi";
+				status = "disabled";
+			};
 		};
 
 		aips3: aips-bus@30800000 {
@@ -684,6 +704,26 @@
 				status = "disabled";
 			};
 
+			flexcan1: can@30a00000 {
+				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
+				reg = <0x30a00000 0x10000>;
+				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_CLK_DUMMY>,
+					<&clks IMX7D_CAN1_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			flexcan2: can@30a10000 {
+				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
+				reg = <0x30a10000 0x10000>;
+				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_CLK_DUMMY>,
+					<&clks IMX7D_CAN2_ROOT_CLK>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
 			i2c1: i2c@30a20000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
diff --git a/sys/gnu/dts/arm/integrator.dtsi b/sys/gnu/dts/arm/integrator.dtsi
index 3807d4f46ef7..6fe0dd1d3541 100644
--- a/sys/gnu/dts/arm/integrator.dtsi
+++ b/sys/gnu/dts/arm/integrator.dtsi
@@ -52,12 +52,13 @@
 	};
 
 	flash@24000000 {
-		compatible = "cfi-flash";
+		compatible = "arm,versatile-flash", "cfi-flash";
 		reg = <0x24000000 0x02000000>;
+		bank-width = <4>;
 	};
 
 	fpga {
-		compatible = "arm,amba-bus", "simple-bus";
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
diff --git a/sys/gnu/dts/arm/k2e-clocks.dtsi b/sys/gnu/dts/arm/keystone-k2e-clocks.dtsi
index d56d68fe7ffc..d56d68fe7ffc 100644
--- a/sys/gnu/dts/arm/k2e-clocks.dtsi
+++ b/sys/gnu/dts/arm/keystone-k2e-clocks.dtsi
diff --git a/sys/gnu/dts/arm/k2e-evm.dts b/sys/gnu/dts/arm/keystone-k2e-evm.dts
index b7e99807f5c2..4c32ebc1425a 100644
--- a/sys/gnu/dts/arm/k2e-evm.dts
+++ b/sys/gnu/dts/arm/keystone-k2e-evm.dts
@@ -10,7 +10,7 @@
 /dts-v1/;
 
 #include "keystone.dtsi"
-#include "k2e.dtsi"
+#include "keystone-k2e.dtsi"
 
 / {
 	compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
diff --git a/sys/gnu/dts/arm/k2e-netcp.dtsi b/sys/gnu/dts/arm/keystone-k2e-netcp.dtsi
index ac990f679725..ac990f679725 100644
--- a/sys/gnu/dts/arm/k2e-netcp.dtsi
+++ b/sys/gnu/dts/arm/keystone-k2e-netcp.dtsi
diff --git a/sys/gnu/dts/arm/k2e.dtsi b/sys/gnu/dts/arm/keystone-k2e.dtsi
index 1097dada56d2..96b349fb0430 100644
--- a/sys/gnu/dts/arm/k2e.dtsi
+++ b/sys/gnu/dts/arm/keystone-k2e.dtsi
@@ -44,7 +44,7 @@
 	};
 
 	soc {
-		/include/ "k2e-clocks.dtsi"
+		/include/ "keystone-k2e-clocks.dtsi"
 
 		usb: usb@2680000 {
 			interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
@@ -145,6 +145,6 @@
 			clock-names = "fck";
 			bus_freq	= <2500000>;
 		};
-		/include/ "k2e-netcp.dtsi"
+		/include/ "keystone-k2e-netcp.dtsi"
 	};
 };
diff --git a/sys/gnu/dts/arm/keystone-k2g-evm.dts b/sys/gnu/dts/arm/keystone-k2g-evm.dts
new file mode 100644
index 000000000000..5bfd9e7845f2
--- /dev/null
+++ b/sys/gnu/dts/arm/keystone-k2g-evm.dts
@@ -0,0 +1,32 @@
+/*
+ * Device Tree Source for K2G EVM
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+
+#include "keystone-k2g.dtsi"
+
+/ {
+	compatible =  "ti,k2g-evm", "ti,k2g", "ti,keystone";
+	model = "Texas Instruments K2G General Purpose EVM";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
+	};
+
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/keystone-k2g.dtsi b/sys/gnu/dts/arm/keystone-k2g.dtsi
new file mode 100644
index 000000000000..7ff2796ae925
--- /dev/null
+++ b/sys/gnu/dts/arm/keystone-k2g.dtsi
@@ -0,0 +1,89 @@
+/*
+ * Device Tree Source for K2G SOC
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "ti,k2g","ti,keystone";
+	model = "Texas Instruments K2G SoC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a15";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	gic: interrupt-controller@02561000 {
+		compatible = "arm,cortex-a15-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0x02561000 0x0 0x1000>,
+		      <0x0 0x02562000 0x0 0x2000>,
+		      <0x0 0x02564000 0x0 0x1000>,
+		      <0x0 0x02566000 0x0 0x2000>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+				IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts =
+			<GIC_PPI 13
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a15-pmu";
+		interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "ti,keystone","simple-bus";
+		ranges = <0x0 0x0 0x0 0xc0000000>;
+		dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
+
+		uart0: serial@02530c00 {
+			compatible = "ns16550a";
+			current-speed = <115200>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			reg = <0x02530c00 0x100>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
+			clock-frequency = <200000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/k2hk-clocks.dtsi b/sys/gnu/dts/arm/keystone-k2hk-clocks.dtsi
index af9b7190533a..af9b7190533a 100644
--- a/sys/gnu/dts/arm/k2hk-clocks.dtsi
+++ b/sys/gnu/dts/arm/keystone-k2hk-clocks.dtsi
diff --git a/sys/gnu/dts/arm/k2hk-evm.dts b/sys/gnu/dts/arm/keystone-k2hk-evm.dts
index 8161bf53271b..b38b3441818b 100644
--- a/sys/gnu/dts/arm/k2hk-evm.dts
+++ b/sys/gnu/dts/arm/keystone-k2hk-evm.dts
@@ -10,7 +10,7 @@
 /dts-v1/;
 
 #include "keystone.dtsi"
-#include "k2hk.dtsi"
+#include "keystone-k2hk.dtsi"
 
 / {
 	compatible =  "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
diff --git a/sys/gnu/dts/arm/k2hk-netcp.dtsi b/sys/gnu/dts/arm/keystone-k2hk-netcp.dtsi
index f86d6ddb832b..f86d6ddb832b 100644
--- a/sys/gnu/dts/arm/k2hk-netcp.dtsi
+++ b/sys/gnu/dts/arm/keystone-k2hk-netcp.dtsi
diff --git a/sys/gnu/dts/arm/k2hk.dtsi b/sys/gnu/dts/arm/keystone-k2hk.dtsi
index ada4c7ac96e7..8f67fa8df936 100644
--- a/sys/gnu/dts/arm/k2hk.dtsi
+++ b/sys/gnu/dts/arm/keystone-k2hk.dtsi
@@ -44,7 +44,7 @@
 	};
 
 	soc {
-		/include/ "k2hk-clocks.dtsi"
+		/include/ "keystone-k2hk-clocks.dtsi"
 
 		dspgpio0: keystone_dsp_gpio@02620240 {
 			compatible = "ti,keystone-dsp-gpio";
@@ -112,6 +112,6 @@
 			clock-names = "fck";
 			bus_freq	= <2500000>;
 		};
-		/include/ "k2hk-netcp.dtsi"
+		/include/ "keystone-k2hk-netcp.dtsi"
 	};
 };
diff --git a/sys/gnu/dts/arm/k2l-clocks.dtsi b/sys/gnu/dts/arm/keystone-k2l-clocks.dtsi
index ef8464bb11ff..ef8464bb11ff 100644
--- a/sys/gnu/dts/arm/k2l-clocks.dtsi
+++ b/sys/gnu/dts/arm/keystone-k2l-clocks.dtsi
diff --git a/sys/gnu/dts/arm/k2l-evm.dts b/sys/gnu/dts/arm/keystone-k2l-evm.dts
index 00861244d788..7f9c2e94d605 100644
--- a/sys/gnu/dts/arm/k2l-evm.dts
+++ b/sys/gnu/dts/arm/keystone-k2l-evm.dts
@@ -10,7 +10,7 @@
 /dts-v1/;
 
 #include "keystone.dtsi"
-#include "k2l.dtsi"
+#include "keystone-k2l.dtsi"
 
 / {
 	compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone";
diff --git a/sys/gnu/dts/arm/k2l-netcp.dtsi b/sys/gnu/dts/arm/keystone-k2l-netcp.dtsi
index 5acbd0dcc2ab..5acbd0dcc2ab 100644
--- a/sys/gnu/dts/arm/k2l-netcp.dtsi
+++ b/sys/gnu/dts/arm/keystone-k2l-netcp.dtsi
diff --git a/sys/gnu/dts/arm/k2l.dtsi b/sys/gnu/dts/arm/keystone-k2l.dtsi
index 4446da72b0ae..ff22ffc3dee7 100644
--- a/sys/gnu/dts/arm/k2l.dtsi
+++ b/sys/gnu/dts/arm/keystone-k2l.dtsi
@@ -32,7 +32,7 @@
 	};
 
 	soc {
-		/include/ "k2l-clocks.dtsi"
+		/include/ "keystone-k2l-clocks.dtsi"
 
 		uart2: serial@02348400 {
 			compatible = "ns16550a";
@@ -92,7 +92,7 @@
 			clock-names = "fck";
 			bus_freq	= <2500000>;
 		};
-		/include/ "k2l-netcp.dtsi"
+		/include/ "keystone-k2l-netcp.dtsi"
 	};
 };
 
diff --git a/sys/gnu/dts/arm/keystone.dtsi b/sys/gnu/dts/arm/keystone.dtsi
index 3f272826f537..e34b2265458a 100644
--- a/sys/gnu/dts/arm/keystone.dtsi
+++ b/sys/gnu/dts/arm/keystone.dtsi
@@ -20,6 +20,9 @@
 
 	aliases {
 		serial0	= &uart0;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
 	};
 
 	memory {
@@ -59,6 +62,14 @@
 			     <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
 	};
 
+	psci {
+		compatible	= "arm,psci";
+		method		= "smc";
+		cpu_suspend	= <0x84000001>;
+		cpu_off		= <0x84000002>;
+		cpu_on		= <0x84000003>;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/sys/gnu/dts/arm/kirkwood-6192.dtsi b/sys/gnu/dts/arm/kirkwood-6192.dtsi
index 9e6e9e2691d5..d573e03f3134 100644
--- a/sys/gnu/dts/arm/kirkwood-6192.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-6192.dtsi
@@ -1,6 +1,6 @@
 / {
-	mbus {
-		pciec: pcie-controller {
+	mbus@f1000000 {
+		pciec: pcie-controller@82000000 {
 			compatible = "marvell,kirkwood-pcie";
 			status = "disabled";
 			device_type = "pci";
diff --git a/sys/gnu/dts/arm/kirkwood-6281.dtsi b/sys/gnu/dts/arm/kirkwood-6281.dtsi
index 7dc7d6782e83..748d0b62f233 100644
--- a/sys/gnu/dts/arm/kirkwood-6281.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-6281.dtsi
@@ -1,6 +1,6 @@
 / {
-	mbus {
-		pciec: pcie-controller {
+	mbus@f1000000 {
+		pciec: pcie-controller@82000000 {
 			compatible = "marvell,kirkwood-pcie";
 			status = "disabled";
 			device_type = "pci";
diff --git a/sys/gnu/dts/arm/kirkwood-6282.dtsi b/sys/gnu/dts/arm/kirkwood-6282.dtsi
index 4680eec990f0..bb63d2d50fc5 100644
--- a/sys/gnu/dts/arm/kirkwood-6282.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-6282.dtsi
@@ -1,6 +1,6 @@
 / {
-	mbus {
-		pciec: pcie-controller {
+	mbus@f1000000 {
+		pciec: pcie-controller@82000000 {
 			compatible = "marvell,kirkwood-pcie";
 			status = "disabled";
 			device_type = "pci";
diff --git a/sys/gnu/dts/arm/kirkwood-98dx4122.dtsi b/sys/gnu/dts/arm/kirkwood-98dx4122.dtsi
index 9e1f741d74ff..720c210d491d 100644
--- a/sys/gnu/dts/arm/kirkwood-98dx4122.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-98dx4122.dtsi
@@ -1,6 +1,6 @@
 / {
-	mbus {
-		pciec: pcie-controller {
+	mbus@f1000000 {
+		pciec: pcie-controller@82000000 {
 			compatible = "marvell,kirkwood-pcie";
 			status = "disabled";
 			device_type = "pci";
diff --git a/sys/gnu/dts/arm/kirkwood-b3.dts b/sys/gnu/dts/arm/kirkwood-b3.dts
index d2936ad3af1d..d091ecb61cd2 100644
--- a/sys/gnu/dts/arm/kirkwood-b3.dts
+++ b/sys/gnu/dts/arm/kirkwood-b3.dts
@@ -33,17 +33,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			/* Wifi model has Atheros chipset on pcie port */
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pmx_button_power: pmx-button-power {
@@ -199,3 +188,11 @@
 	};
 };
 
+/* Wifi model has Atheros chipset on pcie port */
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts b/sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts
index fa02a9aff05e..f16a73e49a88 100644
--- a/sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts
+++ b/sys/gnu/dts/arm/kirkwood-blackarmor-nas220.dts
@@ -36,13 +36,13 @@
 	gpio_keys {
 		compatible = "gpio-keys";
 
-		button@1{
+		reset {
 			label = "Reset";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
 		};
 
-		button@2{
+		button {
 			label = "Power";
 			linux,code = <KEY_SLEEP>;
 			gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
diff --git a/sys/gnu/dts/arm/kirkwood-cloudbox.dts b/sys/gnu/dts/arm/kirkwood-cloudbox.dts
index 7ec76566acf2..555b7e4c58a5 100644
--- a/sys/gnu/dts/arm/kirkwood-cloudbox.dts
+++ b/sys/gnu/dts/arm/kirkwood-cloudbox.dts
@@ -60,7 +60,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		button@1 {
+		power {
 			label = "Power push button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
diff --git a/sys/gnu/dts/arm/kirkwood-db-88f6281.dts b/sys/gnu/dts/arm/kirkwood-db-88f6281.dts
index c39dd766c75a..aee6f02b1c80 100644
--- a/sys/gnu/dts/arm/kirkwood-db-88f6281.dts
+++ b/sys/gnu/dts/arm/kirkwood-db-88f6281.dts
@@ -17,14 +17,12 @@
 / {
 	model = "Marvell DB-88F6281-BP Development Board";
 	compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
+&pciec {
+        status = "okay";
+};
 
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
+&pcie0 {
+	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/kirkwood-db-88f6282.dts b/sys/gnu/dts/arm/kirkwood-db-88f6282.dts
index 701c6b6cdaa2..e8b23e13ec0c 100644
--- a/sys/gnu/dts/arm/kirkwood-db-88f6282.dts
+++ b/sys/gnu/dts/arm/kirkwood-db-88f6282.dts
@@ -17,18 +17,16 @@
 / {
 	model = "Marvell DB-88F6282-BP Development Board";
 	compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
+&pciec {
+        status = "okay";
+};
 
-			pcie@1,0 {
-				status = "okay";
-			};
+&pcie0 {
+	status = "okay";
+};
 
-			pcie@2,0 {
-				status = "okay";
-			};
-		};
-	};
+&pcie1 {
+	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/kirkwood-dir665.dts b/sys/gnu/dts/arm/kirkwood-dir665.dts
index 0473fcc260f7..41acbb6dd6ab 100644
--- a/sys/gnu/dts/arm/kirkwood-dir665.dts
+++ b/sys/gnu/dts/arm/kirkwood-dir665.dts
@@ -25,16 +25,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pinctrl-0 =< &pmx_led_usb
@@ -203,7 +193,7 @@
 		};
 	};
 
-	dsa@0 {
+	dsa {
 		compatible = "marvell,dsa";
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -276,3 +266,11 @@
 &rtc {
 	status = "disabled";
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-dnskw.dtsi b/sys/gnu/dts/arm/kirkwood-dnskw.dtsi
index 113dcf056dcf..d8fca9db46d0 100644
--- a/sys/gnu/dts/arm/kirkwood-dnskw.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-dnskw.dtsi
@@ -13,17 +13,17 @@
 			     &pmx_button_reset>;
 		pinctrl-names = "default";
 
-		button@1 {
+		power {
 			label = "Power button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 		};
-		button@2 {
+		eject {
 			label = "USB unmount button";
 			linux,code = <KEY_EJECTCD>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
-		button@3 {
+		reset {
 			label = "Reset button";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
diff --git a/sys/gnu/dts/arm/kirkwood-ds111.dts b/sys/gnu/dts/arm/kirkwood-ds111.dts
index 61f47fbe44d0..a85a4664431b 100644
--- a/sys/gnu/dts/arm/kirkwood-ds111.dts
+++ b/sys/gnu/dts/arm/kirkwood-ds111.dts
@@ -40,6 +40,6 @@
 	status = "okay";
 };
 
-&pcie2 {
+&pcie1 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/kirkwood-ds112.dts b/sys/gnu/dts/arm/kirkwood-ds112.dts
index bf4143c6cb8f..6cef4bdbc01b 100644
--- a/sys/gnu/dts/arm/kirkwood-ds112.dts
+++ b/sys/gnu/dts/arm/kirkwood-ds112.dts
@@ -14,7 +14,7 @@
 #include "kirkwood-synology.dtsi"
 
 / {
-	model = "Synology DS111";
+	model = "Synology DS112";
 	compatible = "synology,ds111", "marvell,kirkwood";
 
 	memory {
@@ -44,6 +44,10 @@
 	status = "okay";
 };
 
-&pcie2 {
+&pciec {
+        status = "okay";
+};
+
+&pcie1 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/kirkwood-ds212.dts b/sys/gnu/dts/arm/kirkwood-ds212.dts
index 99afd462f956..7f32e7abffac 100644
--- a/sys/gnu/dts/arm/kirkwood-ds212.dts
+++ b/sys/gnu/dts/arm/kirkwood-ds212.dts
@@ -43,6 +43,6 @@
 	status = "okay";
 };
 
-&pcie2 {
+&pcie1 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/kirkwood-ds411.dts b/sys/gnu/dts/arm/kirkwood-ds411.dts
index 623cd4a37d71..72e58307416d 100644
--- a/sys/gnu/dts/arm/kirkwood-ds411.dts
+++ b/sys/gnu/dts/arm/kirkwood-ds411.dts
@@ -48,6 +48,10 @@
 	status = "okay";
 };
 
-&pcie2 {
+&pciec {
+        status = "okay";
+};
+
+&pcie1 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/kirkwood-ds411slim.dts b/sys/gnu/dts/arm/kirkwood-ds411slim.dts
index a0a1fad8b4de..aaaf31b81522 100644
--- a/sys/gnu/dts/arm/kirkwood-ds411slim.dts
+++ b/sys/gnu/dts/arm/kirkwood-ds411slim.dts
@@ -44,6 +44,6 @@
 	status = "okay";
 };
 
-&pcie2 {
+&pcie1 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/kirkwood-ib62x0.dts b/sys/gnu/dts/arm/kirkwood-ib62x0.dts
index bfa5edde179c..ef84d8699a76 100644
--- a/sys/gnu/dts/arm/kirkwood-ib62x0.dts
+++ b/sys/gnu/dts/arm/kirkwood-ib62x0.dts
@@ -62,12 +62,12 @@
 		pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>;
 		pinctrl-names = "default";
 
-		button@1 {
+		copy {
 			label = "USB Copy";
 			linux,code = <KEY_COPY>;
 			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
 		};
-		button@2 {
+		reset {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
diff --git a/sys/gnu/dts/arm/kirkwood-iconnect.dts b/sys/gnu/dts/arm/kirkwood-iconnect.dts
index 38e31d15a62d..d25184ae4af3 100644
--- a/sys/gnu/dts/arm/kirkwood-iconnect.dts
+++ b/sys/gnu/dts/arm/kirkwood-iconnect.dts
@@ -19,16 +19,6 @@
 		linux,initrd-end   = <0x4800000>;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pmx_button_reset: pmx-button-reset {
@@ -136,13 +126,13 @@
 		pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
 		pinctrl-names = "default";
 
-		button@1 {
+		otb {
 			label = "OTB Button";
 			linux,code = <KEY_COPY>;
 			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
 			debounce-interval = <100>;
 		};
-		button@2 {
+		reset {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
@@ -194,3 +184,11 @@
 		phy-handle = <&ethphy0>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-km_common.dtsi b/sys/gnu/dts/arm/kirkwood-km_common.dtsi
index 8367c772c764..7962bdefde49 100644
--- a/sys/gnu/dts/arm/kirkwood-km_common.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-km_common.dtsi
@@ -4,16 +4,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
@@ -34,7 +24,7 @@
 		};
 	};
 
-	i2c@0 {
+	i2c {
 		compatible = "i2c-gpio";
 		gpios = < &gpio0 8 GPIO_ACTIVE_HIGH		/* sda */
 			  &gpio0 9 GPIO_ACTIVE_HIGH>;		/* scl */
@@ -46,3 +36,11 @@
 	status = "okay";
 	chip-delay = <25>;
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-laplug.dts b/sys/gnu/dts/arm/kirkwood-laplug.dts
index 24425660e973..1b0f070c2676 100644
--- a/sys/gnu/dts/arm/kirkwood-laplug.dts
+++ b/sys/gnu/dts/arm/kirkwood-laplug.dts
@@ -27,15 +27,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		serial@12000 {
 			status = "okay";
@@ -62,7 +53,7 @@
 	gpio_keys {
 		compatible = "gpio-keys";
 
-		button@1{
+		power {
 			label = "Power push button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
@@ -169,3 +160,11 @@
 		phy-handle = <&ethphy0>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-6282.dtsi b/sys/gnu/dts/arm/kirkwood-linkstation-6282.dtsi
new file mode 100644
index 000000000000..6548e68a20d0
--- /dev/null
+++ b/sys/gnu/dts/arm/kirkwood-linkstation-6282.dtsi
@@ -0,0 +1,192 @@
+/*
+ * Device Tree common file for kirkwood-6282 based Buffalo Linkstation
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-linkstation.dtsi"
+
+/ {
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_power_hdd0: pmx-power-hdd0 {
+				marvell,pins = "mpp8";
+				marvell,function = "gpio";
+			};
+			pmx_usb_vbus: pmx-usb-vbus {
+				marvell,pins = "mpp12";
+				marvell,function = "gpio";
+			};
+			pmx_fan_high: pmx-fan-high {
+				marvell,pins = "mpp16";
+				marvell,function = "gpio";
+			};
+			pmx_fan_low: pmx-fan-low {
+				marvell,pins = "mpp17";
+				marvell,function = "gpio";
+			};
+			pmx_led_alarm: pmx-led-alarm {
+				marvell,pins = "mpp36";
+				marvell,function = "gpio";
+			};
+			pmx_led_function_red: pmx-led-function-red {
+				marvell,pins = "mpp37";
+				marvell,function = "gpio";
+			};
+			pmx_led_info: pmx-led-info {
+				marvell,pins = "mpp38";
+				marvell,function = "gpio";
+			};
+			pmx_led_function_blue: pmx-led-function-blue {
+				marvell,pins = "mpp39";
+				marvell,function = "gpio";
+			};
+			pmx_led_power: pmx-led-power {
+				marvell,pins = "mpp40";
+				marvell,function = "gpio";
+			};
+			pmx_fan_lock: pmx-fan-lock {
+				marvell,pins = "mpp43";
+				marvell,function = "gpio";
+			};
+			pmx_button_function: pmx-button-function {
+				marvell,pins = "mpp45";
+				marvell,function = "gpio";
+			};
+			pmx_power_switch: pmx-power-switch {
+				marvell,pins = "mpp46";
+				marvell,function = "gpio";
+			};
+			pmx_power_auto_switch: pmx-power-auto-switch {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+		};
+	};
+
+	gpio_keys {
+		function-button {
+			gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+		};
+
+		power-on-switch {
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+		};
+
+		power-auto-switch {
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_leds {
+		red-alarm-led {
+			label = "linkstation:red:alarm";
+			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+		};
+
+		red-function-led {
+			label = "linkstation:red:function";
+			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		amber-info-led {
+			label = "linkstation:amber:info";
+			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+		};
+
+		blue-function-led {
+			label = "linkstation:blue:function";
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		};
+
+		blue-power-led {
+			label = "linkstation:blue:power";
+			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+		};
+	};
+
+	gpio_fan {
+		compatible = "gpio-fan";
+		pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
+		pinctrl-names = "default";
+
+		gpios = <&gpio0 17 GPIO_ACTIVE_LOW
+			 &gpio0 16 GPIO_ACTIVE_LOW>;
+
+		gpio-fan,speed-map = <0 3
+				1500 2
+				3250 1
+				5000 0>;
+
+		alarm-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+	};
+
+	regulators {
+		usb_power: regulator@1 {
+			gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+		};
+
+		hdd_power0: regulator@2 {
+			gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		device_type = "ethernet-phy";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};
diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-duo-6281.dtsi b/sys/gnu/dts/arm/kirkwood-linkstation-duo-6281.dtsi
new file mode 100644
index 000000000000..cf2e69f0d54f
--- /dev/null
+++ b/sys/gnu/dts/arm/kirkwood-linkstation-duo-6281.dtsi
@@ -0,0 +1,186 @@
+/*
+ * Device Tree common file for kirkwood-6281 based 2-Bay Buffalo Linkstation
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-linkstation.dtsi"
+
+/ {
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_power_hdd0: pmx-power-hdd0 {
+				marvell,pins = "mpp28";
+				marvell,function = "gpio";
+			};
+			pmx_power_hdd1: pmx-power-hdd1 {
+				marvell,pins = "mpp29";
+				marvell,function = "gpio";
+			};
+			pmx_usb_vbus: pmx-usb-vbus {
+				marvell,pins = "mpp37";
+				marvell,function = "gpio";
+			};
+			pmx_led_alarm: pmx-led-alarm {
+				marvell,pins = "mpp49";
+				marvell,function = "gpio";
+			};
+			pmx_led_function_red: pmx-led-function-red {
+				marvell,pins = "mpp34";
+				marvell,function = "gpio";
+			};
+			pmx_led_function_blue: pmx-led-function-blue {
+				marvell,pins = "mpp36";
+				marvell,function = "gpio";
+			};
+			pmx_led_info: pmx-led-info {
+				marvell,pins = "mpp38";
+				marvell,function = "gpio";
+			};
+			pmx_led_power: pmx-led-power {
+				marvell,pins = "mpp39";
+				marvell,function = "gpio";
+			};
+			pmx_button_function: pmx-button-function {
+				marvell,pins = "mpp41";
+				marvell,function = "gpio";
+			};
+			pmx_power_switch: pmx-power-switch {
+				marvell,pins = "mpp42";
+				marvell,function = "gpio";
+			};
+			pmx_power_auto_switch: pmx-power-auto-switch {
+				marvell,pins = "mpp43";
+				marvell,function = "gpio";
+			};
+		};
+
+		sata@80000 {
+			nr-ports = <2>;
+		};
+	};
+
+	gpio_keys {
+		function-button {
+			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+		};
+
+		power-on-switch {
+			gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+		};
+
+		power-auto-switch {
+			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_leds {
+		red-alarm-led {
+			label = "linkstation:red:alarm";
+			gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+		};
+
+		red-function-led {
+			label = "linkstation:red:function";
+			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		amber-info-led {
+			label = "linkstation:amber:info";
+			gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+		};
+
+		blue-function-led {
+			label = "linkstation:blue:function";
+			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+		};
+
+		blue-power-led {
+			label = "linkstation:blue:power";
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			default-state = "keep";
+		};
+	};
+
+	regulators {
+		pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>;
+
+		usb_power: regulator@1 {
+			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		hdd_power0: regulator@2 {
+			gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+		};
+
+		hdd_power1: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "HDD1 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy1: ethernet-phy@8 {
+		device_type = "ethernet-phy";
+		reg = <8>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+
+	ethernet1-port@0 {
+		phy-handle = <&ethphy1>;
+	};
+};
diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lsqvl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lsqvl.dts
new file mode 100644
index 000000000000..6dc0df2969f0
--- /dev/null
+++ b/sys/gnu/dts/arm/kirkwood-linkstation-lsqvl.dts
@@ -0,0 +1,135 @@
+/*
+ * Device Tree file for Buffalo Linkstation LS-QVL
+ *
+ * Copyright (C) 2016, Mario Lange <mario_lange@gmx.net>
+ *
+ * Based on kirkwood-linkstation-lswvl.dts,
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "kirkwood-linkstation-6282.dtsi"
+
+/ {
+	model = "Buffalo Linkstation LS-QVL";
+	compatible = "buffalo,lsqvl", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+	memory { /* 256 MB */
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_power_hdd1: pmx-power-hdd1 {
+				marvell,pins = "mpp9";
+				marvell,function = "gpio";
+			};
+			pmx_led_hdderr0: pmx-led-hdderr0 {
+				marvell,pins = "mpp34";
+				marvell,function = "gpio";
+			};
+			pmx_led_hdderr1: pmx-led-hdderr1 {
+				marvell,pins = "mpp35";
+				marvell,function = "gpio";
+			};
+			pmx_led_hdderr2: pmx-led-hdderr2 {
+				marvell,pins = "mpp24";
+				marvell,function = "gpio";
+			};
+			pmx_led_hdderr3: pmx-led-hdderr3 {
+				marvell,pins = "mpp25";
+				marvell,function = "gpio";
+			};
+		};
+
+		sata@80000 {
+			nr-ports = <2>;
+		};
+	};
+
+	gpio_leds {
+		pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
+			     &pmx_led_info &pmx_led_power
+			     &pmx_led_function_blue
+			     &pmx_led_hdderr0
+			     &pmx_led_hdderr1
+			     &pmx_led_hdderr2
+			     &pmx_led_hdderr3>;
+
+		red-hdderr0-led {
+			label = "linkstation:red:hdderr0";
+			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+		};
+
+		red-hdderr1-led {
+			label = "linkstation:red:hdderr1";
+			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+		};
+
+		red-hdderr2-led {
+			label = "linkstation:red:hdderr2";
+			gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
+		};
+
+		red-hdderr3-led {
+			label = "linkstation:red:hdderr3";
+			gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	regulators {
+		pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>;
+
+		hdd_power1: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "HDD1 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lsvl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lsvl.dts
new file mode 100644
index 000000000000..edcba5c44b05
--- /dev/null
+++ b/sys/gnu/dts/arm/kirkwood-linkstation-lsvl.dts
@@ -0,0 +1,57 @@
+/*
+ * Device Tree file for Buffalo Linkstation LS-VL
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "kirkwood-linkstation-6282.dtsi"
+
+/ {
+	model = "Buffalo Linkstation LS-VL";
+	compatible = "buffalo,lsvl", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+	memory { /* 256 MB */
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+};
diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lswsxl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lswsxl.dts
new file mode 100644
index 000000000000..4b6450186af5
--- /dev/null
+++ b/sys/gnu/dts/arm/kirkwood-linkstation-lswsxl.dts
@@ -0,0 +1,57 @@
+/*
+ * Device Tree file for Buffalo Linkstation LS-WSXL
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "kirkwood-linkstation-duo-6281.dtsi"
+
+/ {
+	model = "Buffalo Linkstation LS-WSXL";
+	compatible = "buffalo,lswsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory { /* 128 MB */
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+};
diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lswvl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lswvl.dts
new file mode 100644
index 000000000000..954ec1d5b6dc
--- /dev/null
+++ b/sys/gnu/dts/arm/kirkwood-linkstation-lswvl.dts
@@ -0,0 +1,112 @@
+/*
+ * Device Tree file for Buffalo Linkstation LS-WVL
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "kirkwood-linkstation-6282.dtsi"
+
+/ {
+	model = "Buffalo Linkstation LS-WVL";
+	compatible = "buffalo,lswvl","marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+	memory { /* 256 MB */
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_power_hdd1: pmx-power-hdd1 {
+				marvell,pins = "mpp9";
+				marvell,function = "gpio";
+			};
+			pmx_led_hdderr0: pmx-led-hdderr0 {
+				marvell,pins = "mpp34";
+				marvell,function = "gpio";
+			};
+			pmx_led_hdderr1: pmx-led-hdderr1 {
+				marvell,pins = "mpp35";
+				marvell,function = "gpio";
+			};
+		};
+
+		sata@80000 {
+			nr-ports = <2>;
+		};
+	};
+
+	gpio_leds {
+		pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
+			     &pmx_led_info &pmx_led_power
+			     &pmx_led_function_blue
+			     &pmx_led_hdderr0
+			     &pmx_led_hdderr1>;
+
+		red-hdderr0-led {
+			label = "linkstation:red:hdderr0";
+			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		red-hdderr1-led {
+			label = "linkstation:red:hdderr1";
+			gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	regulators {
+		pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>;
+
+		hdd_power1: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "HDD1 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/kirkwood-linkstation-lswxl.dts b/sys/gnu/dts/arm/kirkwood-linkstation-lswxl.dts
new file mode 100644
index 000000000000..ecd5c12a805d
--- /dev/null
+++ b/sys/gnu/dts/arm/kirkwood-linkstation-lswxl.dts
@@ -0,0 +1,116 @@
+/*
+ * Device Tree file for Buffalo Linkstation LS-WXL
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "kirkwood-linkstation-duo-6281.dtsi"
+
+/ {
+	model = "Buffalo Linkstation LS-WXL";
+	compatible = "buffalo,lswxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory { /* 128 MB */
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_led_hdderr0: pmx-led-hdderr0 {
+				marvell,pins = "mpp8";
+				marvell,function = "gpio";
+			};
+			pmx_led_hdderr1: pmx-led-hdderr1 {
+				marvell,pins = "mpp46";
+				marvell,function = "gpio";
+			};
+			pmx_fan_lock: pmx-fan-lock {
+				marvell,pins = "mpp40";
+				marvell,function = "gpio";
+			};
+			pmx_fan_high: pmx-fan-high {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+			pmx_fan_low: pmx-fan-low {
+				marvell,pins = "mpp48";
+				marvell,function = "gpio";
+			};
+		};
+	};
+
+	gpio_leds {
+		pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
+			     &pmx_led_info &pmx_led_power
+			     &pmx_led_function_blue
+			     &pmx_led_hdderr0
+			     &pmx_led_hdderr1>;
+
+		red-hdderr0-led {
+			label = "linkstation:red:hdderr0";
+			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+		};
+
+		red-hdderr1-led {
+			label = "linkstation:red:hdderr1";
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio_fan {
+		compatible = "gpio-fan";
+		pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
+		pinctrl-names = "default";
+
+		gpios = <&gpio1 16 GPIO_ACTIVE_LOW
+			 &gpio1 15 GPIO_ACTIVE_LOW>;
+
+		gpio-fan,speed-map = <0 3
+				1500 2
+				3250 1
+				5000 0>;
+
+		alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/sys/gnu/dts/arm/kirkwood-linkstation.dtsi b/sys/gnu/dts/arm/kirkwood-linkstation.dtsi
new file mode 100644
index 000000000000..36c54c9dfa30
--- /dev/null
+++ b/sys/gnu/dts/arm/kirkwood-linkstation.dtsi
@@ -0,0 +1,201 @@
+/*
+ * Device Tree common file for kirkwood based Buffalo Linkstation
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_power_hdd0: pmx-power-hdd0 {
+				marvell,function = "gpio";
+			};
+			pmx_usb_vbus: pmx-usb-vbus {
+				marvell,function = "gpio";
+			};
+			pmx_led_alarm: pmx-led-alarm {
+				marvell,function = "gpio";
+			};
+			pmx_led_function_red: pmx-led-function-red {
+				marvell,function = "gpio";
+			};
+			pmx_led_function_blue: pmx-led-function-blue {
+				marvell,function = "gpio";
+			};
+			pmx_led_info: pmx-led-info {
+				marvell,function = "gpio";
+			};
+			pmx_led_power: pmx-led-power {
+				marvell,function = "gpio";
+			};
+			pmx_button_function: pmx-button-function {
+				marvell,function = "gpio";
+			};
+			pmx_power_switch: pmx-power-switch {
+				marvell,function = "gpio";
+			};
+			pmx_power_auto_switch: pmx-power-auto-switch {
+				marvell,function = "gpio";
+			};
+		};
+
+		serial@12000 {
+			status = "okay";
+		};
+
+		sata@80000 {
+			status = "okay";
+			nr-ports = <1>;
+		};
+
+		spi@10600 {
+			status = "okay";
+
+			m25p40@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "st,m25p40", "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <25000000>;
+				mode = <0>;
+
+				partition@0 {
+					reg = <0x0 0x60000>;
+					label = "uboot";
+					read-only;
+				};
+
+				partition@60000 {
+					reg = <0x60000 0x10000>;
+					label = "dtb";
+					read-only;
+				};
+
+				partition@70000 {
+					reg = <0x70000 0x10000>;
+					label = "uboot_env";
+				};
+			};
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_button_function &pmx_power_switch
+			     &pmx_power_auto_switch>;
+		pinctrl-names = "default";
+
+		function-button {
+			label = "Function Button";
+			linux,code = <KEY_OPTION>;
+		};
+
+		power-on-switch {
+			label = "Power-on Switch";
+			linux,code = <KEY_RESERVED>;
+			linux,input-type = <5>;
+		};
+
+		power-auto-switch {
+			label = "Power-auto Switch";
+			linux,code = <KEY_ESC>;
+			linux,input-type = <5>;
+		};
+	};
+
+	gpio_leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
+			     &pmx_led_info &pmx_led_power
+			     &pmx_led_function_blue>;
+		pinctrl-names = "default";
+	};
+
+	restart_poweroff {
+		compatible = "restart-poweroff";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_power_hdd0 &pmx_usb_vbus>;
+		pinctrl-names = "default";
+
+		usb_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "USB Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		hdd_power0: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "HDD0 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+	};
+};
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-linksys-viper.dts b/sys/gnu/dts/arm/kirkwood-linksys-viper.dts
new file mode 100644
index 000000000000..345fcac48dc7
--- /dev/null
+++ b/sys/gnu/dts/arm/kirkwood-linksys-viper.dts
@@ -0,0 +1,240 @@
+/*
+ * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500)
+ *
+ * (c) 2013 Jonas Gorski <jogo@openwrt.org>
+ * (c) 2013 Deutsche Telekom Innovation Laboratories
+ * (c) 2014 Luka Perkov <luka@openwrt.org>
+ * (c) 2014 Randy C. Will <randall.will@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+
+/ {
+	model = "Linksys Viper (E4200v2 / EA4500)";
+	compatible = "linksys,viper", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >;
+		pinctrl-names = "default";
+
+		wps {
+			label = "WPS Button";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+
+		reset {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >;
+		pinctrl-names = "default";
+
+		white-health {
+			label = "viper:white:health";
+			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+		};
+
+		white-pulse {
+			label = "viper:white:pulse";
+			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	dsa {
+		compatible = "marvell,dsa";
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		dsa,ethernet = <&eth0port>;
+		dsa,mii-bus = <&mdio>;
+
+		switch@16,0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <16 0>;	/* MDIO address 16, switch 0 in tree */
+
+			port@0 {
+				reg = <0>;
+				label = "ethernet1";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "ethernet2";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "ethernet3";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "ethernet4";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "internet";
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "cpu";
+			};
+		};
+	};
+};
+
+&pinctrl {
+	pmx_led_white_health: pmx-led-white-health {
+		marvell,pins = "mpp7";
+		marvell,function = "gpo";
+	};
+	pmx_led_white_pulse: pmx-led-white-pulse {
+		marvell,pins = "mpp14";
+		marvell,function = "gpio";
+	};
+	pmx_btn_wps: pmx-btn-wps {
+		marvell,pins = "mpp47";
+		marvell,function = "gpio";
+	};
+	pmx_btn_reset: pmx-btn-reset {
+		marvell,pins = "mpp48";
+		marvell,function = "gpio";
+	};
+};
+
+&nand {
+	status = "okay";
+	pinctrl-0 = <&pmx_nand>;
+	pinctrl-names = "default";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "u-boot";
+			reg = <0x0 0x80000>;
+			read-only;
+		};
+
+		partition@80000 {
+			label = "u_env";
+			reg = <0x80000 0x20000>;
+		};
+
+		partition@A0000 {
+			label = "s_env";
+			reg = <0xA0000 0x20000>;
+		};
+
+		partition@200000 {
+			label = "kernel";
+			reg = <0x200000 0x2A0000>;
+		};
+
+		partition@4A0000 {
+			label = "rootfs";
+			reg = <0x4A0000 0x1760000>;
+		};
+
+		partition@1C00000 {
+			label = "alt_kernel";
+			reg = <0x1C00000 0x2A0000>;
+		};
+
+		partition@1EA0000 {
+			label = "alt_rootfs";
+			reg = <0x1EA0000 0x1760000>;
+		};
+
+		partition@3600000 {
+			label = "syscfg";
+			reg = <0x3600000 0x4A00000>;
+		};
+
+		partition@C0000 {
+			label = "unused";
+			reg = <0xC0000 0x140000>;
+		};
+
+	};
+};
+
+&pciec {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set
+ * fixed speed and duplex.
+ */
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		speed = <1000>;
+		duplex = <1>;
+	};
+};
+
+/* eth1 is connected to the switch at port 6. However DSA only supports a
+ * single CPU port. So leave this port disabled to avoid confusion.
+ */
+&eth1 {
+	status = "disabled";
+};
+
+/* There is no battery on the board, so the RTC does not keep
+ * time when there is no power, making it useless.
+ */
+&rtc {
+	status = "disabled";
+};
+
diff --git a/sys/gnu/dts/arm/kirkwood-lswvl.dts b/sys/gnu/dts/arm/kirkwood-lswvl.dts
deleted file mode 100644
index 09eed3cea0af..000000000000
--- a/sys/gnu/dts/arm/kirkwood-lswvl.dts
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Device Tree file for Buffalo Linkstation LS-WVL/VL
- *
- * Copyright (C) 2015, rogershimizu@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6282.dtsi"
-
-/ {
-	model = "Buffalo Linkstation LS-WVL/VL";
-	compatible = "buffalo,lswvl", "buffalo,lsvl", "marvell,kirkwood-88f6282", "marvell,kirkwood";
-
-	memory { /* 256 MB */
-		device_type = "memory";
-		reg = <0x00000000 0x10000000>;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200n8 earlyprintk";
-		stdout-path = &uart0;
-	};
-
-	mbus {
-		pcie-controller {
-			status = "okay";
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
-	ocp@f1000000 {
-		pinctrl: pin-controller@10000 {
-			pmx_power_hdd0: pmx-power-hdd0 {
-				marvell,pins = "mpp8";
-				marvell,function = "gpio";
-			};
-			pmx_power_hdd1: pmx-power-hdd1 {
-				marvell,pins = "mpp9";
-				marvell,function = "gpio";
-			};
-			pmx_usb_vbus: pmx-usb-vbus {
-				marvell,pins = "mpp12";
-				marvell,function = "gpio";
-			};
-			pmx_fan_high: pmx-fan-high {
-				marvell,pins = "mpp16";
-				marvell,function = "gpio";
-			};
-			pmx_fan_low: pmx-fan-low {
-				marvell,pins = "mpp17";
-				marvell,function = "gpio";
-			};
-			pmx_led_hdderr0: pmx-led-hdderr0 {
-				marvell,pins = "mpp34";
-				marvell,function = "gpio";
-			};
-			pmx_led_hdderr1: pmx-led-hdderr1 {
-				marvell,pins = "mpp35";
-				marvell,function = "gpio";
-			};
-			pmx_led_alarm: pmx-led-alarm {
-				marvell,pins = "mpp36";
-				marvell,function = "gpio";
-			};
-			pmx_led_function_red: pmx-led-function-red {
-				marvell,pins = "mpp37";
-				marvell,function = "gpio";
-			};
-			pmx_led_info: pmx-led-info {
-				marvell,pins = "mpp38";
-				marvell,function = "gpio";
-			};
-			pmx_led_function_blue: pmx-led-function-blue {
-				marvell,pins = "mpp39";
-				marvell,function = "gpio";
-			};
-			pmx_led_power: pmx-led-power {
-				marvell,pins = "mpp40";
-				marvell,function = "gpio";
-			};
-			pmx_fan_lock: pmx-fan-lock {
-				marvell,pins = "mpp43";
-				marvell,function = "gpio";
-			};
-			pmx_button_function: pmx-button-function {
-				marvell,pins = "mpp45";
-				marvell,function = "gpio";
-			};
-			pmx_power_switch: pmx-power-switch {
-				marvell,pins = "mpp46";
-				marvell,function = "gpio";
-			};
-			pmx_power_auto_switch: pmx-power-auto-switch {
-				marvell,pins = "mpp47";
-				marvell,function = "gpio";
-			};
-		};
-
-		serial@12000 {
-			status = "okay";
-		};
-
-		sata@80000 {
-			status = "okay";
-			nr-ports = <2>;
-		};
-
-		spi@10600 {
-			status = "okay";
-
-			m25p40@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "st,m25p40", "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <25000000>;
-				mode = <0>;
-
-				partition@0 {
-					reg = <0x0 0x60000>;
-					label = "uboot";
-					read-only;
-				};
-
-				partition@60000 {
-					reg = <0x60000 0x10000>;
-					label = "dtb";
-					read-only;
-				};
-
-				partition@70000 {
-					reg = <0x70000 0x10000>;
-					label = "uboot_env";
-				};
-			};
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-0 = <&pmx_button_function &pmx_power_switch
-			     &pmx_power_auto_switch>;
-		pinctrl-names = "default";
-
-		button@1 {
-			label = "Function Button";
-			linux,code = <KEY_OPTION>;
-			gpios = <&gpio0 45 GPIO_ACTIVE_LOW>;
-		};
-
-		button@2 {
-			label = "Power-on Switch";
-			linux,code = <KEY_RESERVED>;
-			linux,input-type = <5>;
-			gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
-		};
-
-		button@3 {
-			label = "Power-auto Switch";
-			linux,code = <KEY_ESC>;
-			linux,input-type = <5>;
-			gpios = <&gpio0 47 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio_leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
-			     &pmx_led_info &pmx_led_power
-			     &pmx_led_function_blue
-			     &pmx_led_hdderr0
-			     &pmx_led_hdderr1>;
-		pinctrl-names = "default";
-
-		led@1 {
-			label = "lswvl:red:alarm";
-			gpios = <&gpio0 36 GPIO_ACTIVE_LOW>;
-		};
-
-		led@2 {
-			label = "lswvl:red:func";
-			gpios = <&gpio0 37 GPIO_ACTIVE_LOW>;
-		};
-
-		led@3 {
-			label = "lswvl:amber:info";
-			gpios = <&gpio0 38 GPIO_ACTIVE_LOW>;
-		};
-
-		led@4 {
-			label = "lswvl:blue:func";
-			gpios = <&gpio0 39 GPIO_ACTIVE_LOW>;
-		};
-
-		led@5 {
-			label = "lswvl:blue:power";
-			gpios = <&gpio0 40 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-		};
-
-		led@6 {
-			label = "lswvl:red:hdderr0";
-			gpios = <&gpio0 34 GPIO_ACTIVE_LOW>;
-		};
-
-		led@7 {
-			label = "lswvl:red:hdderr1";
-			gpios = <&gpio0 35 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio_fan {
-		compatible = "gpio-fan";
-		pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
-		pinctrl-names = "default";
-
-		gpios = <&gpio0 17 GPIO_ACTIVE_LOW
-			 &gpio0 16 GPIO_ACTIVE_LOW>;
-
-		gpio-fan,speed-map = <0 3
-				1500 2
-				3250 1
-				5000 0>;
-
-		alarm-gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>;
-	};
-
-	restart_poweroff {
-		compatible = "restart-poweroff";
-	};
-
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>;
-		pinctrl-names = "default";
-
-		usb_power: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "USB Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
-		};
-		hdd_power0: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <2>;
-			regulator-name = "HDD0 Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
-		};
-		hdd_power1: regulator@3 {
-			compatible = "regulator-fixed";
-			reg = <3>;
-			regulator-name = "HDD1 Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&mdio {
-	status = "okay";
-
-	ethphy0: ethernet-phy@0 {
-		device_type = "ethernet-phy";
-		reg = <0>;
-	};
-};
-
-&eth0 {
-	status = "okay";
-
-	ethernet0-port@0 {
-		phy-handle = <&ethphy0>;
-	};
-};
diff --git a/sys/gnu/dts/arm/kirkwood-lswxl.dts b/sys/gnu/dts/arm/kirkwood-lswxl.dts
deleted file mode 100644
index f5db16a08597..000000000000
--- a/sys/gnu/dts/arm/kirkwood-lswxl.dts
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Device Tree file for Buffalo Linkstation LS-WXL/WSXL
- *
- * Copyright (C) 2015, rogershimizu@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
-	model = "Buffalo Linkstation LS-WXL/WSXL";
-	compatible = "buffalo,lswxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
-	memory { /* 128 MB */
-		device_type = "memory";
-		reg = <0x00000000 0x8000000>;
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200n8 earlyprintk";
-		stdout-path = &uart0;
-	};
-
-	mbus {
-		pcie-controller {
-			status = "okay";
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
-	ocp@f1000000 {
-		pinctrl: pin-controller@10000 {
-			pmx_power_hdd0: pmx-power-hdd0 {
-				marvell,pins = "mpp28";
-				marvell,function = "gpio";
-			};
-			pmx_power_hdd1: pmx-power-hdd1 {
-				marvell,pins = "mpp29";
-				marvell,function = "gpio";
-			};
-			pmx_usb_vbus: pmx-usb-vbus {
-				marvell,pins = "mpp37";
-				marvell,function = "gpio";
-			};
-			pmx_fan_high: pmx-fan-high {
-				marvell,pins = "mpp47";
-				marvell,function = "gpio";
-			};
-			pmx_fan_low: pmx-fan-low {
-				marvell,pins = "mpp48";
-				marvell,function = "gpio";
-			};
-			pmx_led_hdderr0: pmx-led-hdderr0 {
-				marvell,pins = "mpp8";
-				marvell,function = "gpio";
-			};
-			pmx_led_hdderr1: pmx-led-hdderr1 {
-				marvell,pins = "mpp46";
-				marvell,function = "gpio";
-			};
-			pmx_led_alarm: pmx-led-alarm {
-				marvell,pins = "mpp49";
-				marvell,function = "gpio";
-			};
-			pmx_led_function_red: pmx-led-function-red {
-				marvell,pins = "mpp34";
-				marvell,function = "gpio";
-			};
-			pmx_led_function_blue: pmx-led-function-blue {
-				marvell,pins = "mpp36";
-				marvell,function = "gpio";
-			};
-			pmx_led_info: pmx-led-info {
-				marvell,pins = "mpp38";
-				marvell,function = "gpio";
-			};
-			pmx_led_power: pmx-led-power {
-				marvell,pins = "mpp39";
-				marvell,function = "gpio";
-			};
-			pmx_fan_lock: pmx-fan-lock {
-				marvell,pins = "mpp40";
-				marvell,function = "gpio";
-			};
-			pmx_button_function: pmx-button-function {
-				marvell,pins = "mpp41";
-				marvell,function = "gpio";
-			};
-			pmx_power_switch: pmx-power-switch {
-				marvell,pins = "mpp42";
-				marvell,function = "gpio";
-			};
-			pmx_power_auto_switch: pmx-power-auto-switch {
-				marvell,pins = "mpp43";
-				marvell,function = "gpio";
-			};
-		};
-
-		serial@12000 {
-			status = "okay";
-		};
-
-		sata@80000 {
-			status = "okay";
-			nr-ports = <2>;
-		};
-
-		spi@10600 {
-			status = "okay";
-
-			m25p40@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "st,m25p40", "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <25000000>;
-				mode = <0>;
-
-				partition@0 {
-					reg = <0x0 0x60000>;
-					label = "uboot";
-					read-only;
-				};
-
-				partition@60000 {
-					reg = <0x60000 0x10000>;
-					label = "dtb";
-					read-only;
-				};
-
-				partition@70000 {
-					reg = <0x70000 0x10000>;
-					label = "uboot_env";
-				};
-			};
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-0 = <&pmx_button_function &pmx_power_switch
-			     &pmx_power_auto_switch>;
-		pinctrl-names = "default";
-
-		button@1 {
-			label = "Function Button";
-			linux,code = <KEY_OPTION>;
-			gpios = <&gpio1 41 GPIO_ACTIVE_LOW>;
-		};
-
-		button@2 {
-			label = "Power-on Switch";
-			linux,code = <KEY_RESERVED>;
-			linux,input-type = <5>;
-			gpios = <&gpio1 42 GPIO_ACTIVE_LOW>;
-		};
-
-		button@3 {
-			label = "Power-auto Switch";
-			linux,code = <KEY_ESC>;
-			linux,input-type = <5>;
-			gpios = <&gpio1 43 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio_leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
-			     &pmx_led_info &pmx_led_power
-			     &pmx_led_function_blue
-			     &pmx_led_hdderr0
-			     &pmx_led_hdderr1>;
-		pinctrl-names = "default";
-
-		led@1 {
-			label = "lswxl:blue:func";
-			gpios = <&gpio1 36 GPIO_ACTIVE_LOW>;
-		};
-
-		led@2 {
-			label = "lswxl:red:alarm";
-			gpios = <&gpio1 49 GPIO_ACTIVE_LOW>;
-		};
-
-		led@3 {
-			label = "lswxl:amber:info";
-			gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
-		};
-
-		led@4 {
-			label = "lswxl:blue:power";
-			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
-		};
-
-		led@5 {
-			label = "lswxl:red:func";
-			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-		};
-
-		led@6 {
-			label = "lswxl:red:hdderr0";
-			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
-		};
-
-		led@7 {
-			label = "lswxl:red:hdderr1";
-			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	gpio_fan {
-		compatible = "gpio-fan";
-		pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
-		pinctrl-names = "default";
-
-		gpios = <&gpio0 47 GPIO_ACTIVE_LOW
-			 &gpio0 48 GPIO_ACTIVE_LOW>;
-
-		gpio-fan,speed-map = <0 3
-				1500 2
-				3250 1
-				5000 0>;
-
-		alarm-gpios = <&gpio1 49 GPIO_ACTIVE_HIGH>;
-	};
-
-	restart_poweroff {
-		compatible = "restart-poweroff";
-	};
-
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-0 = <&pmx_power_hdd0 &pmx_power_hdd1 &pmx_usb_vbus>;
-		pinctrl-names = "default";
-
-		usb_power: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "USB Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 37 GPIO_ACTIVE_HIGH>;
-		};
-		hdd_power0: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <2>;
-			regulator-name = "HDD0 Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>;
-		};
-		hdd_power1: regulator@3 {
-			compatible = "regulator-fixed";
-			reg = <3>;
-			regulator-name = "HDD1 Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&mdio {
-	status = "okay";
-
-	ethphy1: ethernet-phy@8 {
-		device_type = "ethernet-phy";
-		reg = <8>;
-	};
-};
-
-&eth1 {
-	status = "okay";
-
-	ethernet1-port@0 {
-		phy-handle = <&ethphy1>;
-	};
-};
diff --git a/sys/gnu/dts/arm/kirkwood-lsxl.dtsi b/sys/gnu/dts/arm/kirkwood-lsxl.dtsi
index 1d6528d82969..8b7c6ce79a41 100644
--- a/sys/gnu/dts/arm/kirkwood-lsxl.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-lsxl.dtsi
@@ -107,18 +107,18 @@
 			     &pmx_power_auto_switch>;
 		pinctrl-names = "default";
 
-		button@1 {
+		option {
 			label = "Function Button";
 			linux,code = <KEY_OPTION>;
 			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 		};
-		button@2 {
+		reserved {
 			label = "Power-on Switch";
 			linux,code = <KEY_RESERVED>;
 			linux,input-type = <5>;
 			gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
 		};
-		button@3 {
+		power {
 			label = "Power-auto Switch";
 			linux,code = <KEY_ESC>;
 			linux,input-type = <5>;
@@ -133,28 +133,28 @@
 			     &pmx_led_function_blue>;
 		pinctrl-names = "default";
 
-		led@1 {
+		func_blue {
 			label = "lsxl:blue:func";
 			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 		};
 
-		led@2 {
+		alarm {
 			label = "lsxl:red:alarm";
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 		};
 
-		led@3 {
+		info {
 			label = "lsxl:amber:info";
 			gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
 		};
 
-		led@4 {
+		power {
 			label = "lsxl:blue:power";
 			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
 			default-state = "keep";
 		};
 
-		led@5 {
+		func_red {
 			label = "lsxl:red:func";
 			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
 		};
diff --git a/sys/gnu/dts/arm/kirkwood-mplcec4.dts b/sys/gnu/dts/arm/kirkwood-mplcec4.dts
index f3a991837515..aa413b0bcce2 100644
--- a/sys/gnu/dts/arm/kirkwood-mplcec4.dts
+++ b/sys/gnu/dts/arm/kirkwood-mplcec4.dts
@@ -17,16 +17,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pmx_led_health: pmx-led-health {
@@ -215,3 +205,11 @@
 		phy-handle = <&ethphy1>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts b/sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts
index b7e7d78c484e..172a38c0b8a9 100644
--- a/sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts
+++ b/sys/gnu/dts/arm/kirkwood-mv88f6281gtw-ge.dts
@@ -31,16 +31,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-        };
-
 	ocp@f1000000 {
 		pin-controller@10000 {
 			pmx_usb_led: pmx-usb-led {
@@ -109,19 +99,19 @@
 		pinctrl-0 = <&pmx_keys>;
 		pinctrl-names = "default";
 
-		button@1 {
+		restart {
 			label = "SWR Button";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 		};
-		button@2 {
+		wps {
 			label = "WPS Button";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
 		};
 	};
 
-	dsa@0 {
+	dsa {
 		compatible = "marvell,dsa";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -179,3 +169,11 @@
 		duplex = <1>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-nas2big.dts b/sys/gnu/dts/arm/kirkwood-nas2big.dts
index 7427ec50b829..f53bcacf6b63 100644
--- a/sys/gnu/dts/arm/kirkwood-nas2big.dts
+++ b/sys/gnu/dts/arm/kirkwood-nas2big.dts
@@ -28,16 +28,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		rtc@10300 {
 			/* The on-chip RTC is not powered (no supercap). */
@@ -141,3 +131,11 @@
 		reg = <0x9100000 0x6f00000>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts b/sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts
index fd733c63bc27..c0413b63cf2e 100644
--- a/sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts
+++ b/sys/gnu/dts/arm/kirkwood-netgear_readynas_duo_v2.dts
@@ -28,16 +28,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pmx_button_power: pmx-button-power {
@@ -193,7 +183,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		usb3_regulator: usb3-regulator {
+		usb3_regulator: usb3-regulator@1 {
 			compatible = "regulator-fixed";
 			reg = <1>;
 			regulator-name = "USB 3.0 Power";
@@ -251,3 +241,11 @@
 		phy-handle = <&ethphy0>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts b/sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts
index b514d643fb6c..2bfc6cfa151d 100644
--- a/sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts
+++ b/sys/gnu/dts/arm/kirkwood-netgear_readynas_nv+_v2.dts
@@ -28,18 +28,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			/* Connected to NEC uPD720200 USB 3.0 controller */
-			pcie@1,0 {
-				/* Port 0, Lane 0 */
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pmx_button_power: pmx-button-power {
@@ -205,7 +193,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		usb3_regulator: usb3-regulator {
+		usb3_regulator: usb3-regulator@1 {
 			compatible = "regulator-fixed";
 			reg = <1>;
 			regulator-name = "USB 3.0 Power";
@@ -265,3 +253,12 @@
 		phy-handle = <&ethphy0>;
 	};
 };
+
+/* Connected to NEC uPD720200 USB 3.0 controller */
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-netxbig.dtsi b/sys/gnu/dts/arm/kirkwood-netxbig.dtsi
index 62515a8b99b9..52b58fe0c4fe 100644
--- a/sys/gnu/dts/arm/kirkwood-netxbig.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-netxbig.dtsi
@@ -59,22 +59,22 @@
 		#size-cells = <0>;
 
 		/*
-		 * button@1 and button@2 represent a three position rocker
+		 * esc and power represent a three position rocker
 		 * switch. Thus the conventional KEY_POWER does not fit
 		 */
-		button@1 {
+		exc {
 			label = "Back power switch (on|auto)";
 			linux,code = <KEY_ESC>;
 			linux,input-type = <5>;
 			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
 		};
-		button@2 {
+		power {
 			label = "Back power switch (auto|off)";
 			linux,code = <KEY_1>;
 			linux,input-type = <5>;
 			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
 		};
-		button@3 {
+		option {
 			label = "Function button";
 			linux,code = <KEY_OPTION>;
 			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
diff --git a/sys/gnu/dts/arm/kirkwood-ns2-common.dtsi b/sys/gnu/dts/arm/kirkwood-ns2-common.dtsi
index e832b6320264..282605f4c92c 100644
--- a/sys/gnu/dts/arm/kirkwood-ns2-common.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-ns2-common.dtsi
@@ -57,7 +57,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		button@1 {
+		power {
 			label = "Power push button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
@@ -83,7 +83,7 @@
 &mdio {
 	status = "okay";
 
-	ethphy0: ethernet-phy {
+	ethphy0: ethernet-phy@X {
                 /* overwrite reg property in board file */
 	};
 };
diff --git a/sys/gnu/dts/arm/kirkwood-nsa310.dts b/sys/gnu/dts/arm/kirkwood-nsa310.dts
index 6139df0f376c..0b69ee4934fa 100644
--- a/sys/gnu/dts/arm/kirkwood-nsa310.dts
+++ b/sys/gnu/dts/arm/kirkwood-nsa310.dts
@@ -15,16 +15,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pinctrl-0 = <&pmx_unknown>;
@@ -138,3 +128,11 @@
 		};
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-nsa320.dts b/sys/gnu/dts/arm/kirkwood-nsa320.dts
index 24f686d1044d..6ab104b4bb42 100644
--- a/sys/gnu/dts/arm/kirkwood-nsa320.dts
+++ b/sys/gnu/dts/arm/kirkwood-nsa320.dts
@@ -27,16 +27,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pinctrl-names = "default";
@@ -193,10 +183,19 @@
 		};
 	};
 
+	hwmon {
+		compatible = "zyxel,nsa320-mcu";
+		pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>;
+		pinctrl-names = "default";
+
+		data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+		act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
+	};
+
 	/* The following pins are currently not assigned to a driver,
 	   some of them should be configured as inputs.
-	pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act
-		     &pmx_htp &pmx_vid_b1
+	pinctrl-0 = <&pmx_htp &pmx_vid_b1
 		     &pmx_power_resume_data &pmx_power_resume_clk>; */
 };
 
@@ -213,3 +212,11 @@
 		phy-handle = <&ethphy0>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-nsa325.dts b/sys/gnu/dts/arm/kirkwood-nsa325.dts
index bc4ec9332387..36c64816bf7f 100644
--- a/sys/gnu/dts/arm/kirkwood-nsa325.dts
+++ b/sys/gnu/dts/arm/kirkwood-nsa325.dts
@@ -28,16 +28,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pinctrl-names = "default";
@@ -236,3 +226,10 @@
 	};
 };
 
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-nsa3x0-common.dtsi b/sys/gnu/dts/arm/kirkwood-nsa3x0-common.dtsi
index 2075a2e828f1..e09b79ac73fd 100644
--- a/sys/gnu/dts/arm/kirkwood-nsa3x0-common.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-nsa3x0-common.dtsi
@@ -4,16 +4,6 @@
 / {
 	model = "ZyXEL NSA310";
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 
@@ -77,17 +67,17 @@
 		pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
 		pinctrl-names = "default";
 
-		button@1 {
+		power {
 			label = "Power Button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 		};
-		button@2 {
+		copy {
 			label = "Copy Button";
 			linux,code = <KEY_COPY>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 		};
-		button@3 {
+		reset {
 			label = "Reset Button";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
@@ -157,3 +147,11 @@
 		reg = <0x5040000 0x2fc0000>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-openblocks_a6.dts b/sys/gnu/dts/arm/kirkwood-openblocks_a6.dts
index fb9dc227255d..0db0e3edc88f 100644
--- a/sys/gnu/dts/arm/kirkwood-openblocks_a6.dts
+++ b/sys/gnu/dts/arm/kirkwood-openblocks_a6.dts
@@ -117,7 +117,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		button@1 {
+		power {
 			label = "Init Button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
diff --git a/sys/gnu/dts/arm/kirkwood-openblocks_a7.dts b/sys/gnu/dts/arm/kirkwood-openblocks_a7.dts
index d5e3bc518968..cf2f5240e176 100644
--- a/sys/gnu/dts/arm/kirkwood-openblocks_a7.dts
+++ b/sys/gnu/dts/arm/kirkwood-openblocks_a7.dts
@@ -135,7 +135,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		button@1 {
+		button {
 			label = "Init Button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
diff --git a/sys/gnu/dts/arm/kirkwood-openrd-client.dts b/sys/gnu/dts/arm/kirkwood-openrd-client.dts
index 887b9c1fee43..96ff59d68f44 100644
--- a/sys/gnu/dts/arm/kirkwood-openrd-client.dts
+++ b/sys/gnu/dts/arm/kirkwood-openrd-client.dts
@@ -20,6 +20,9 @@
 	compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
 	ocp@f1000000 {
+		audio-controller@a0000 {
+			status = "okay";
+		};
 		i2c@11000 {
 			status = "okay";
 			clock-frequency = <400000>;
@@ -27,6 +30,7 @@
 			cs42l51: cs42l51@4a {
 				compatible = "cirrus,cs42l51";
 				reg = <0x4a>;
+				#sound-dai-cells = <0>;
 			};
 		};
 	};
@@ -37,7 +41,7 @@
 		simple-audio-card,mclk-fs = <256>;
 
 		simple-audio-card,cpu {
-			sound-dai = <&audio0>;
+			sound-dai = <&audio0 0>;
 		};
 
 		simple-audio-card,codec {
diff --git a/sys/gnu/dts/arm/kirkwood-openrd.dtsi b/sys/gnu/dts/arm/kirkwood-openrd.dtsi
index d3330dadf7ed..e4ecab112601 100644
--- a/sys/gnu/dts/arm/kirkwood-openrd.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-openrd.dtsi
@@ -25,22 +25,12 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>;
 			pinctrl-names = "default";
 
-			pmx_select28: pmx-select-uart-sd {
+			pmx_select28: pmx-select-rs232-rs485 {
 				marvell,pins = "mpp28";
 				marvell,function = "gpio";
 			};
@@ -48,7 +38,7 @@
 				marvell,pins = "mpp29";
 				marvell,function = "gpio";
 			};
-			pmx_select34: pmx-select-rs232-rs484 {
+			pmx_select34: pmx-select-uart-sd {
 				marvell,pins = "mpp34";
 				marvell,function = "gpio";
 			};
@@ -65,6 +55,43 @@
 			status = "okay";
 			cd-gpios = <&gpio0 29 9>;
 		};
+		gpio@10100 {
+			p28 {
+				gpio-hog;
+				gpios = <28 GPIO_ACTIVE_HIGH>;
+				/*
+				 * SelRS232or485 selects between RS-232 or RS-485
+				 * mode for the second UART.
+				 *
+				 * Low: RS-232
+				 * High: RS-485
+				 *
+				 * To use the second UART, you need to change also
+				 * the SelUARTorSD.
+				 */
+				output-low;
+				line-name = "SelRS232or485";
+			};
+		};
+		gpio@10140 {
+			p2 {
+				gpio-hog;
+				gpios = <2 GPIO_ACTIVE_HIGH>;
+				/*
+				 * SelUARTorSD selects between the second UART
+				 * (serial@12100) and SD (mvsdio@90000).
+				 *
+				 * Low: UART
+				 * High: SD
+				 *
+				 * When changing this line make sure the newly
+				 * selected device node is enabled and the
+				 * previously selected device node is disabled.
+				 */
+				output-high; /* Select SD by default */
+				line-name = "SelUARTorSD";
+			};
+		};
 	};
 };
 
@@ -88,3 +115,7 @@
 		reg = <0x0600000 0x1FA00000>;
 	};
 };
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts b/sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts
index 1db6f2c506cc..b2f26239d298 100644
--- a/sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts
+++ b/sys/gnu/dts/arm/kirkwood-pogoplug-series-4.dts
@@ -33,7 +33,7 @@
 		pinctrl-0 = <&pmx_button_eject>;
 		pinctrl-names = "default";
 
-		button@1 {
+		eject {
 			debounce_interval = <50>;
 			wakeup-source;
 			linux,code = <KEY_EJECTCD>;
@@ -131,6 +131,7 @@
 	chip-delay = <40>;
 	status = "okay";
 	partitions {
+		compatible = "fixed-partitions";
 		#address-cells = <1>;
 		#size-cells = <1>;
 
diff --git a/sys/gnu/dts/arm/kirkwood-rd88f6192.dts b/sys/gnu/dts/arm/kirkwood-rd88f6192.dts
index e0b959396ca2..b8af907249fb 100644
--- a/sys/gnu/dts/arm/kirkwood-rd88f6192.dts
+++ b/sys/gnu/dts/arm/kirkwood-rd88f6192.dts
@@ -29,16 +29,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pinctrl-0 = <&pmx_usb_power>;
@@ -108,4 +98,12 @@
         ethernet0-port@0 {
                 phy-handle = <&ethphy0>;
         };
-};
\ No newline at end of file
+};
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts b/sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts
index f2e08b3b33ea..6f771a99cb02 100644
--- a/sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts
+++ b/sys/gnu/dts/arm/kirkwood-rd88f6281-a.dts
@@ -19,7 +19,7 @@
 	model = "Marvell RD88f6281 Reference design, with A0 or higher SoC";
 	compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
 
-	dsa@0 {
+	dsa {
 		switch@0 {
 			reg = <10 0>;	 /* MDIO address 10, switch 0 in tree */
 		};
diff --git a/sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts b/sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts
index f4272b64ed7f..1a797381d3d4 100644
--- a/sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts
+++ b/sys/gnu/dts/arm/kirkwood-rd88f6281-z0.dts
@@ -19,7 +19,7 @@
 	model = "Marvell RD88f6281 Reference design, with Z0 SoC";
 	compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood";
 
-	dsa@0 {
+	dsa {
 		switch@0 {
 			reg = <0 0>;    /* MDIO address 0, switch 0 in tree */
 			port@4 {
diff --git a/sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi b/sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi
index d195e884b3b5..d5aacf137e40 100644
--- a/sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-rd88f6281.dtsi
@@ -25,16 +25,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pinctrl-names = "default";
@@ -63,7 +53,7 @@
 		};
 	};
 
-	dsa@0 {
+	dsa {
 		compatible = "marvell,dsa";
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -134,3 +124,11 @@
 		duplex = <1>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-rs212.dts b/sys/gnu/dts/arm/kirkwood-rs212.dts
index 3b19f1fd4cac..2c722ecd5331 100644
--- a/sys/gnu/dts/arm/kirkwood-rs212.dts
+++ b/sys/gnu/dts/arm/kirkwood-rs212.dts
@@ -44,6 +44,10 @@
 	status = "okay";
 };
 
-&pcie2 {
+&pciec {
+        status = "okay";
+};
+
+&pcie1 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/kirkwood-synology.dtsi b/sys/gnu/dts/arm/kirkwood-synology.dtsi
index 04015c174b99..65e9524e852a 100644
--- a/sys/gnu/dts/arm/kirkwood-synology.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-synology.dtsi
@@ -10,20 +10,6 @@
  */
 
 / {
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-
-			pcie2: pcie@2,0 {
-				status = "disabled";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pmx_alarmled_12: pmx-alarmled-12 {
@@ -861,3 +847,11 @@
 		phy-handle = <&ethphy1>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-t5325.dts b/sys/gnu/dts/arm/kirkwood-t5325.dts
index ed956b849a71..3500f4738fb0 100644
--- a/sys/gnu/dts/arm/kirkwood-t5325.dts
+++ b/sys/gnu/dts/arm/kirkwood-t5325.dts
@@ -30,16 +30,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 			pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
@@ -173,7 +163,7 @@
 		pinctrl-0 = <&pmx_button_power>;
 		pinctrl-names = "default";
 
-		button@1 {
+		power {
 			label = "Power Button";
 			linux,code = <KEY_POWER>;
 			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
@@ -217,7 +207,7 @@
 &mdio {
 	status = "okay";
 
-	ethphy0: ethernet-phy {
+	ethphy0: ethernet-phy@8 {
 		device_type = "ethernet-phy";
 		reg = <8>;
 	};
@@ -229,3 +219,11 @@
 		phy-handle = <&ethphy0>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-ts219-6281.dts b/sys/gnu/dts/arm/kirkwood-ts219-6281.dts
index 9767d73f3857..ee62204e4ecd 100644
--- a/sys/gnu/dts/arm/kirkwood-ts219-6281.dts
+++ b/sys/gnu/dts/arm/kirkwood-ts219-6281.dts
@@ -39,12 +39,12 @@
 		pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
 		pinctrl-names = "default";
 
-		button@1 {
+		copy {
 			label = "USB Copy";
 			linux,code = <KEY_COPY>;
 			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
 		};
-		button@2 {
+		reset {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
diff --git a/sys/gnu/dts/arm/kirkwood-ts219-6282.dts b/sys/gnu/dts/arm/kirkwood-ts219-6282.dts
index bfc1a32d4e42..3437bb396844 100644
--- a/sys/gnu/dts/arm/kirkwood-ts219-6282.dts
+++ b/sys/gnu/dts/arm/kirkwood-ts219-6282.dts
@@ -5,16 +5,6 @@
 #include "kirkwood-ts219.dtsi"
 
 / {
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@2,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		pinctrl: pin-controller@10000 {
 
@@ -49,12 +39,12 @@
 		pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
 		pinctrl-names = "default";
 
-		button@1 {
+		copy {
 			label = "USB Copy";
 			linux,code = <KEY_COPY>;
 			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 		};
-		button@2 {
+		reset {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
@@ -63,3 +53,5 @@
 };
 
 &ethphy0 { reg = <0>; };
+
+&pcie1 { status = "okay"; };
diff --git a/sys/gnu/dts/arm/kirkwood-ts219.dtsi b/sys/gnu/dts/arm/kirkwood-ts219.dtsi
index 0e46560551f4..62e5e2d5c348 100644
--- a/sys/gnu/dts/arm/kirkwood-ts219.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-ts219.dtsi
@@ -12,16 +12,6 @@
 		stdout-path = &uart0;
 	};
 
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@1,0 {
-				status = "okay";
-			};
-		};
-	};
-
 	ocp@f1000000 {
 		i2c@11000 {
 			status = "okay";
@@ -94,7 +84,7 @@
 &mdio {
 	status = "okay";
 
-	ethphy0: ethernet-phy {
+	ethphy0: ethernet-phy@X {
                 /* overwrite reg property in board file */
 	};
 };
@@ -105,3 +95,11 @@
 		phy-handle = <&ethphy0>;
 	};
 };
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/kirkwood-ts419-6282.dts b/sys/gnu/dts/arm/kirkwood-ts419-6282.dts
index d7512d4cdced..e3e71f48acc8 100644
--- a/sys/gnu/dts/arm/kirkwood-ts419-6282.dts
+++ b/sys/gnu/dts/arm/kirkwood-ts419-6282.dts
@@ -16,17 +16,8 @@
 #include "kirkwood-ts219.dtsi"
 #include "kirkwood-ts419.dtsi"
 
-/ {
-	mbus {
-		pcie-controller {
-			status = "okay";
-
-			pcie@2,0 {
-				status = "okay";
-			};
-		};
-	};
-};
-
 &ethphy0 { reg = <0>; };
 &ethphy1 { reg = <1>; };
+
+&pciec { status = "okay"; };
+&pcie1 { status = "okay"; };
diff --git a/sys/gnu/dts/arm/kirkwood-ts419.dtsi b/sys/gnu/dts/arm/kirkwood-ts419.dtsi
index 30ab93bfb1e4..02bd53762705 100644
--- a/sys/gnu/dts/arm/kirkwood-ts419.dtsi
+++ b/sys/gnu/dts/arm/kirkwood-ts419.dtsi
@@ -45,12 +45,12 @@
 		pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
 		pinctrl-names = "default";
 
-		button@1 {
+		copy {
 			label = "USB Copy";
 			linux,code = <KEY_COPY>;
 			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 		};
-		button@2 {
+		reset {
 			label = "Reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
diff --git a/sys/gnu/dts/arm/kirkwood.dtsi b/sys/gnu/dts/arm/kirkwood.dtsi
index 7b5a4a18f49c..29b8bd7e0d93 100644
--- a/sys/gnu/dts/arm/kirkwood.dtsi
+++ b/sys/gnu/dts/arm/kirkwood.dtsi
@@ -27,7 +27,7 @@
 	       i2c0 = &i2c0;
 	};
 
-	mbus {
+	mbus@f1000000 {
 		compatible = "marvell,kirkwood-mbus", "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <1>;
@@ -381,7 +381,7 @@
 
 		audio0: audio-controller@a0000 {
 			compatible = "marvell,kirkwood-audio";
-			#sound-dai-cells = <0>;
+			#sound-dai-cells = <1>;
 			reg = <0xa0000 0x2210>;
 			interrupts = <24>;
 			clocks = <&gate_clk 9>;
diff --git a/sys/gnu/dts/arm/logicpd-som-lv-37xx-devkit.dts b/sys/gnu/dts/arm/logicpd-som-lv-37xx-devkit.dts
new file mode 100644
index 000000000000..da8598402ab8
--- /dev/null
+++ b/sys/gnu/dts/arm/logicpd-som-lv-37xx-devkit.dts
@@ -0,0 +1,268 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include "logicpd-som-lv.dtsi"
+#include "omap-gpmc-smsc9221.dtsi"
+
+/ {
+	model = "LogicPD Zoom DM3730 SOM-LV Development Kit";
+	compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_key_pins>;
+
+		sysboot2 {
+			label = "gpio3";
+			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;	/* gpio_111 / uP_GPIO_3 */
+			linux,code = <BTN_0>;
+			wakeup-source;
+		};
+	};
+
+	sound {
+		compatible = "ti,omap-twl4030";
+		ti,model = "omap3logic";
+		ti,mcbsp = <&mcbsp2>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins &led_pins_wkup>;
+
+		led1 {
+			label = "led1";
+			gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;	/* gpio133 */
+			linux,default-trigger = "cpu0";
+		};
+
+		led2 {
+			label = "led2";
+			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;	/* gpio11 */
+			linux,default-trigger = "none";
+		};
+	};
+};
+
+&vaux1 {
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+};
+
+&vaux4 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+};
+
+&mcbsp2 {
+	status = "okay";
+};
+
+&charger {
+	ti,bb-uvolt = <3200000>;
+	ti,bb-uamp = <150>;
+};
+
+&gpmc {
+	ranges = <1 0 0x08000000 0x1000000>;	/* CS1: 16MB for LAN9221 */
+
+	ethernet@gpmc {
+		pinctrl-names = "default";
+		pinctrl-0 = <&lan9221_pins>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;		/* gpio_152 */
+		reg = <1 0 0xff>;
+	};
+};
+
+&vpll2 {
+	regulator-always-on;
+};
+
+&dss {
+	status = "ok";
+	vdds_dsi-supply = <&vpll2>;
+	vdda_video-supply = <&video_reg>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&dss_dpi_pins1>;
+	port {
+		dpi_out: endpoint {
+			remote-endpoint = <&lcd_in>;
+			data-lines = <16>;
+		};
+	};
+};
+
+/ {
+	aliases {
+		display0 = &lcd0;
+	};
+
+	video_reg: video_reg {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	lcd0: display@0 {
+		compatible = "panel-dpi";
+		label = "28";
+		status = "okay";
+		/* default-on; */
+		pinctrl-names = "default";
+		pinctrl-0 = <&lcd_enable_pin>;
+		enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;	/* gpio155, lcd INI */
+		port {
+			lcd_in: endpoint {
+				remote-endpoint = <&dpi_out>;
+			};
+		};
+
+		panel-timing {
+			clock-frequency = <9000000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <3>;
+			hback-porch = <2>;
+			hsync-len = <42>;
+			vback-porch = <3>;
+			vfront-porch = <2>;
+			vsync-len = <11>;
+			hsync-active = <1>;
+			vsync-active = <1>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+		};
+	};
+
+	bl: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&backlight_pins>;
+		pwms = <&twl_pwm 0 5000000>;
+		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <7>;
+		enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */
+	};
+};
+
+&mmc1 {
+	interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins &mmc1_cd>;
+	wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;		/* gpio_126 */
+	cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>;		/* gpio_110 */
+	vmmc-supply = <&vmmc1>;
+	bus-width = <4>;
+	cap-power-off-card;
+};
+
+&omap3_pmx_core {
+	gpio_key_pins: pinmux_gpio_key_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4)	/* cam_xclkb.gpio_111 / uP_GPIO_3*/
+		>;
+	};
+
+	led_pins: pinmux_led_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4)	/* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */
+		>;
+	};
+
+	lan9221_pins: pinmux_lan9221_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4)	/* mcbsp4_clkx.gpio_152 */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
+			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0)	/* sdmmc1_cmd.sdmmc1_cmd */
+			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat0.sdmmc1_dat0 */
+			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
+			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
+			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
+			OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4)	/* cam_strobe.gpio_126 sdmmc1_wp*/
+		>;
+	};
+
+	lcd_enable_pin: pinmux_lcd_enable_pin {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4)       /* mcbsp4_fs.gpio_155 */
+		>;
+	};
+
+	dss_dpi_pins1: pinmux_dss_dpi_pins1 {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_pclk.dss_pclk */
+			OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_hsync.dss_hsync */
+			OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_vsync.dss_vsync */
+			OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_acbias.dss_acbias */
+
+			OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data0.dss_data0 */
+			OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data1.dss_data1 */
+			OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data2.dss_data2 */
+			OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data3.dss_data3 */
+			OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data4.dss_data4 */
+			OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data5.dss_data5 */
+			OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data6.dss_data6 */
+			OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data7.dss_data7 */
+			OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data8.dss_data8 */
+			OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data9.dss_data9 */
+			OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data10.dss_data10 */
+			OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data11.dss_data11 */
+			OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data12.dss_data12 */
+			OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data13.dss_data13 */
+			OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data14.dss_data14 */
+			OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data15.dss_data15 */
+		>;
+	};
+};
+
+&omap3_pmx_wkup {
+	led_pins_wkup: pinmux_led_pins_wkup {
+		pinctrl-single,pins = <
+			OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4)	/* jtag_emu0.gpio_11 / uP_GPIO_1 */
+		>;
+	};
+
+	backlight_pins: pinmux_backlight_pins {
+		pinctrl-single,pins = <
+			OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4)       /* sys_boot6.gpio_8 */
+		>;
+	};
+
+	mmc1_cd: pinmux_mmc1_cd {
+		pinctrl-single,pins = <
+			OMAP3_WKUP_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4)	/* cam_d11.gpio_110 */
+		>;
+	};
+};
+
+
+&uart1 {
+	interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
+};
+
+/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */
+&usb_otg_hs {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb_otg_pins>;
+	interface-type = <0>;
+	usb-phy = <&usb2_phy>;
+	phys = <&usb2_phy>;
+	phy-names = "usb2-phy";
+	mode = <3>;
+	power = <50>;
+};
diff --git a/sys/gnu/dts/arm/logicpd-som-lv.dtsi b/sys/gnu/dts/arm/logicpd-som-lv.dtsi
new file mode 100644
index 000000000000..365f39ff58bb
--- /dev/null
+++ b/sys/gnu/dts/arm/logicpd-som-lv.dtsi
@@ -0,0 +1,265 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&vcc>;
+		};
+	};
+
+	wl12xx_vmmc: wl12xx_vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "vwl1271";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio1 3 0>;   /* gpio_3 */
+		startup-delay-us = <70000>;
+		enable-active-high;
+		vin-supply = <&vmmc2>;
+	};
+
+	/* HS USB Host PHY on PORT 1 */
+	hsusb2_phy: hsusb2_phy {
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
+	};
+};
+
+&gpmc {
+	ranges = <0 0 0x00000000 0x1000000>;	/* CS0: 16MB for NAND */
+
+	nand@0,0 {
+		linux,mtd-name = "micron,mt29f4g16abbda3w";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		nand-bus-width = <16>;
+		ti,nand-ecc-opt = "bch8";
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		gpmc,device-width = <2>;
+
+		gpmc,page-burst-access-ns = <5>;
+		gpmc,cycle2cycle-delay-ns = <50>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */
+
+		x-loader@0 {
+			label = "x-loader";
+			reg = <0 0x80000>;
+		};
+
+		bootloaders@80000 {
+			label = "u-boot";
+			reg = <0x80000 0x1e0000>;
+		};
+
+		bootloaders_env@260000 {
+			label = "u-boot-env";
+			reg = <0x260000 0x20000>;
+		};
+
+		kernel@280000 {
+			label = "kernel";
+			reg = <0x280000 0x400000>;
+		};
+
+		filesystem@680000 {
+			label = "fs";
+			reg = <0x680000 0>;	/* 0 = MTDPART_SIZ_FULL */
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <2600000>;
+
+	twl: twl@48 {
+		reg = <0x48>;
+		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+		twl_audio: audio {
+			compatible = "ti,twl4030-audio";
+			codec {
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+};
+
+&mmc3 {
+	interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
+	pinctrl-0 = <&mmc3_pins>;
+	pinctrl-names = "default";
+	vmmc-supply = <&wl12xx_vmmc>;
+	non-removable;
+	bus-width = <4>;
+	cap-power-off-card;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1273";
+		reg = <2>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */
+		ref-clock-frequency = <26000000>;
+	};
+};
+
+&usbhshost {
+	port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+	phys = <0 &hsusb2_phy>;
+};
+
+
+&omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_pins>;
+
+	mmc3_pins: pinmux_mm3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat4.sdmmc3_dat0 */
+			OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat5.sdmmc3_dat1 */
+			OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat6.sdmmc3_dat2 */
+			OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3)	/* sdmmc2_dat6.sdmmc3_dat3 */
+			OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4)	/* mcbsp4_clkx.gpio_152 */
+			OMAP3_CORE1_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)	/* sys_boot1.gpio_3 */
+			OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
+			OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3)	/* mcspi1_cs2.sdmmc_clk */
+		>;
+	};
+	mcbsp2_pins: pinmux_mcbsp2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
+			OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
+			OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
+			OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
+		>;
+	};
+	uart2_pins: pinmux_uart2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)	/* uart2_cts.uart2_cts */
+			OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)	/* uart2_rts .uart2_rts*/
+			OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)	/* uart2_tx.uart2_tx */
+			OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)	/* uart2_rx.uart2_rx */
+			OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)	/* GPIO_162,BT_EN */
+		>;
+	};
+	mcspi1_pins: pinmux_mcspi1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
+			OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
+			OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
+			OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
+		>;
+	};
+
+	hsusb2_pins: pinmux_hsusb2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
+		>;
+	};
+
+	hsusb_otg_pins: pinmux_hsusb_otg_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)	/* hsusb0_clk.hsusb0_clk */
+			OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)	/* hsusb0_stp.hsusb0_stp */
+			OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)	/* hsusb0_dir.hsusb0_dir */
+			OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)	/* hsusb0_nxt.hsusb0_nxt */
+			OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)	/* hsusb0_data0.hsusb0_data0 */
+			OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)	/* hsusb0_data1.hsusb0_data1 */
+			OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)	/* hsusb0_data2.hsusb0_data2 */
+			OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)	/* hsusb0_data3.hsusb0_data3 */
+			OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)	/* hsusb0_data4.hsusb0_data4 */
+			OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)	/* hsusb0_data5.hsusb0_data5 */
+			OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)	/* hsusb0_data6.hsusb0_data6 */
+			OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)	/* hsusb0_data7.hsusb0_data7 */
+		>;
+	};
+
+
+};
+
+&omap3_pmx_wkup {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_reset_pin>;
+	hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
+		pinctrl-single,pins = <
+			OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4)	/* sys_boot2.gpio_4 */
+		>;
+	};
+};
+
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_2_pins>;
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+		>;
+	};
+};
+
+&uart2 {
+	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+};
+
+&mcspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcspi1_pins>;
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&twl {
+	twl_power: power {
+		compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
+		ti,use_poweroff;
+	};
+};
+
+&twl_gpio {
+	ti,use-leds;
+};
diff --git a/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit.dts b/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit.dts
index fb13f18c08cc..015f795a8d19 100644
--- a/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit.dts
+++ b/sys/gnu/dts/arm/logicpd-torpedo-37xx-devkit.dts
@@ -11,7 +11,7 @@
 #include "omap-gpmc-smsc9221.dtsi"
 
 / {
-	model = "LogicPD Zoom DM3730 Torpedo Development Kit";
+	model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit";
 	compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3";
 
 	gpio_keys {
@@ -71,6 +71,15 @@
 			linux,default-trigger = "none";
 		};
 	};
+
+	pwm10: dmtimer-pwm@10 {
+		compatible = "ti,omap-dmtimer-pwm";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm_pins>;
+		ti,timers = <&timer10>;
+		#pwm-cells = <3>;
+	};
+
 };
 
 &vaux1 {
@@ -93,7 +102,8 @@
 };
 
 &gpmc {
-	ranges = <1 0 0x08000000 0x1000000>;	/* CS1: 16MB for LAN9221 */
+	ranges = <0 0 0x30000000 0x1000000	/* CS0: 16MB for NAND */
+		  1 0 0x2c000000 0x1000000>;	/* CS1: 16MB for LAN9221 */
 
 	ethernet@gpmc {
 		pinctrl-names = "default";
@@ -111,6 +121,7 @@
 &dss {
 	status = "ok";
 	vdds_dsi-supply = <&vpll2>;
+	vdda_video-supply = <&video_reg>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&dss_dpi_pins1>;
 	port {
@@ -126,13 +137,22 @@
 		display0 = &lcd0;
 	};
 
+	video_reg: video_reg {
+		pinctrl-names = "default";
+		pinctrl-0 = <&panel_pwr_pins>;
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>;	/* gpio155, lcd INI */
+	};
+
 	lcd0: display@0 {
 		compatible = "panel-dpi";
 		label = "15";
 		status = "okay";
 		/* default-on; */
 		pinctrl-names = "default";
-		enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;	/* gpio155, lcd INI */
 
 		port {
 			lcd_in: endpoint {
@@ -158,13 +178,13 @@
 	};
 
 	bl: backlight {
-		compatible = "gpio-backlight";
+		compatible = "pwm-backlight";
 		pinctrl-names = "default";
 		pinctrl-0 = <&backlight_pins>;
-
-		gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>, /* gpio_56 */
-			<&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */
-		default-on;
+		pwms = <&pwm10 0 5000000 0>;
+		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <7>;
+		enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */
 	};
 };
 
@@ -186,6 +206,12 @@
 		>;
 	};
 
+	pwm_pins: pinmux_pwm_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3)       /* gpmc_ncs5.gpt_10_pwm_evt */
+		>;
+	};
+
 	led_pins: pinmux_led_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4)	/* gpio_179 */
@@ -212,37 +238,60 @@
 
 	backlight_pins: pinmux_backlight_pins {
 		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | MUX_MODE4)       /* gpmc_ncs5.gpio_56 */
-			OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4)       /* mcbsp4_dx.gpio_154 */
+			OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4)       /* mcbsp4_dx.gpio_154 */
+		>;
+	};
+
+	isp_pins: pinmux_isp_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0)   /* cam_hs.cam_hs */
+			OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0)   /* cam_vs.cam_vs */
+			OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0)   /* cam_xclka.cam_xclka */
+			OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0)   /* cam_pclk.cam_pclk */
+
+			OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE0)   /* cam_d0.cam_d0 */
+			OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0)   /* cam_d1.cam_d1 */
+			OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0)   /* cam_d2.cam_d2 */
+			OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0)   /* cam_d3.cam_d3 */
+			OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0)   /* cam_d4.cam_d4 */
+			OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0)   /* cam_d5.cam_d5 */
+			OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0)   /* cam_d6.cam_d6 */
+			OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0)   /* cam_d7.cam_d7 */
+		>;
+	};
+
+	panel_pwr_pins: pinmux_panel_pwr_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4)       /* mcbsp4_fs.gpio_155 */
 		>;
 	};
 
 	dss_dpi_pins1: pinmux_dss_dpi_pins1 {
 		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
-			OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
-			OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
-			OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
-
-			OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
-			OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
-			OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
-			OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
-			OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
-			OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
-			OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
-			OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
-			OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
-			OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
-			OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
-			OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
-
-			OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3)   /* dss_data18.dss_data0 */
-			OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3)   /* dss_data19.dss_data1 */
-			OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3)   /* dss_data20.dss_data2 */
-			OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3)   /* dss_data21.dss_data3 */
-			OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3)   /* dss_data22.dss_data4 */
-			OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3)   /* dss_data23.dss_data5 */
+			OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_pclk.dss_pclk */
+			OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_hsync.dss_hsync */
+			OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_vsync.dss_vsync */
+			OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_acbias.dss_acbias */
+
+			OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data6.dss_data6 */
+			OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data7.dss_data7 */
+			OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data8.dss_data8 */
+			OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data9.dss_data9 */
+			OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data10.dss_data10 */
+			OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data11.dss_data11 */
+			OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data12.dss_data12 */
+			OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data13.dss_data13 */
+			OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data14.dss_data14 */
+			OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data15.dss_data15 */
+			OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data16.dss_data16 */
+			OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0)   /* dss_data17.dss_data17 */
+
+			OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3)   /* dss_data18.dss_data0 */
+			OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3)   /* dss_data19.dss_data1 */
+			OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3)   /* dss_data20.dss_data2 */
+			OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3)   /* dss_data21.dss_data3 */
+			OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3)   /* dss_data22.dss_data4 */
+			OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3)   /* dss_data23.dss_data5 */
 		>;
 	};
 };
@@ -268,6 +317,24 @@
 	};
 };
 
+&i2c2 {
+	mt9p031@48 {
+		compatible = "aptina,mt9p031";
+		reg = <0x48>;
+		clocks = <&isp 0>;
+		vaa-supply = <&vaux4>;
+		vdd-supply = <&vaux4>;
+		vdd_io-supply = <&vaux4>;
+		port {
+			mt9p031_out: endpoint {
+				input-clock-frequency = <24000000>;
+				pixel-clock-frequency = <72000000>;
+				remote-endpoint = <&ccdc_ep>;
+			};
+		};
+	};
+};
+
 &i2c3 {
 	touchscreen: tsc2004@48 {
 		compatible = "ti,tsc2004";
@@ -289,12 +356,45 @@
 	};
 };
 
+&mcspi1 {
+	at25@0 {
+		compatible = "atmel,at25";
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		spi-cpha;
+		spi-cpol;
+
+		pagesize = <64>;
+		size = <32768>;
+		address-width = <16>;
+	};
+};
+
+&isp {
+	pinctrl-names = "default";
+	pinctrl-0 = <&isp_pins>;
+	ports {
+		port@0 {
+			reg = <0>;
+			ccdc_ep: endpoint {
+				remote-endpoint = <&mt9p031_out>;
+				bus-width = <8>;
+				hsync-active = <1>;
+				vsync-active = <1>;
+				pclk-sample = <0>;
+			};
+		};
+	};
+};
+
 &uart1 {
 	interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
 };
 
 /* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */
 &usb_otg_hs {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb_otg_pins>;
 	interface-type = <0>;
 	usb-phy = <&usb2_phy>;
 	phys = <&usb2_phy>;
diff --git a/sys/gnu/dts/arm/logicpd-torpedo-som.dtsi b/sys/gnu/dts/arm/logicpd-torpedo-som.dtsi
index 7fed0bd4f3de..5e9a13c0eaf7 100644
--- a/sys/gnu/dts/arm/logicpd-torpedo-som.dtsi
+++ b/sys/gnu/dts/arm/logicpd-torpedo-som.dtsi
@@ -35,11 +35,15 @@
 };
 
 &gpmc {
-	ranges = <0 0 0x00000000 0x1000000>;	/* CS0: 16MB for NAND */
+	ranges = <0 0 0x30000000 0x1000000>;	/* CS0: 16MB for NAND */
 
 	nand@0,0 {
-		linux,mtd-name = "micron,mt29f4g16abbda3w";
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		linux,mtd-name = "micron,mt29f4g16abbda3w";
 		nand-bus-width = <16>;
 		ti,nand-ecc-opt = "bch8";
 		gpmc,sync-clk-ps = <0>;
@@ -110,14 +114,11 @@
 
 &i2c3 {
 	clock-frequency = <400000>;
-};
-
-&i2c2 {
-	clock-frequency = <400000>;
-};
-
-&i2c3 {
-	clock-frequency = <400000>;
+	at24@50 {
+		compatible = "at24,24c02";
+		readonly;
+		reg = <0x50>;
+	};
 };
 
 /*
@@ -143,6 +144,7 @@
 		interrupt-parent = <&gpio5>;
 		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */
 		ref-clock-frequency = <26000000>;
+		tcxo-clock-frequency = <26000000>;
 	};
 };
 
@@ -174,6 +176,31 @@
 			OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)	/* GPIO_162,BT_EN */
 		>;
 	};
+	mcspi1_pins: pinmux_mcspi1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
+			OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
+			OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
+			OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
+		>;
+	};
+	hsusb_otg_pins: pinmux_hsusb_otg_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)	/* hsusb0_clk.hsusb0_clk */
+			OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)	/* hsusb0_stp.hsusb0_stp */
+			OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)	/* hsusb0_dir.hsusb0_dir */
+			OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)	/* hsusb0_nxt.hsusb0_nxt */
+
+			OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)	/* hsusb0_data0.hsusb0_data0 */
+			OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)	/* hsusb0_data1.hsusb0_data1 */
+			OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)	/* hsusb0_data2.hsusb0_data2 */
+			OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)	/* hsusb0_data3.hsusb0_data3 */
+			OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)	/* hsusb0_data4.hsusb0_data4 */
+			OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)	/* hsusb0_data5.hsusb0_data5 */
+			OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)	/* hsusb0_data6.hsusb0_data6 */
+			OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)	/* hsusb0_data7.hsusb0_data7 */
+		>;
+	};
 };
 
 &uart2 {
@@ -182,6 +209,11 @@
 	pinctrl-0 = <&uart2_pins>;
 };
 
+&mcspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcspi1_pins>;
+};
+
 &omap3_pmx_core2 {
 	mmc3_core2_pins: pinmux_mmc3_core2_pins {
 		pinctrl-single,pins = <
diff --git a/sys/gnu/dts/arm/lpc18xx.dtsi b/sys/gnu/dts/arm/lpc18xx.dtsi
index 053a1f54f4bb..fdb736c82045 100644
--- a/sys/gnu/dts/arm/lpc18xx.dtsi
+++ b/sys/gnu/dts/arm/lpc18xx.dtsi
@@ -195,13 +195,19 @@
 			clocks = <&ccu1 CLK_CPU_CREG>;
 			resets = <&rgu 5>;
 
-			usb0_otg_phy: phy@004 {
+			creg_clk: clock-controller {
+				compatible = "nxp,lpc1850-creg-clk";
+				clocks = <&xtal32>;
+				#clock-cells = <1>;
+			};
+
+			usb0_otg_phy: phy {
 				compatible = "nxp,lpc1850-usb-otg-phy";
 				clocks = <&ccu1 CLK_USB0>;
 				#phy-cells = <0>;
 			};
 
-			dmamux: dma-mux@11c {
+			dmamux: dma-mux {
 				compatible = "nxp,lpc1850-dmamux";
 				#dma-cells = <3>;
 				dma-requests = <64>;
@@ -209,11 +215,19 @@
 			};
 		};
 
+		rtc: rtc@40046000 {
+			compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
+			reg = <0x40046000 0x1000>;
+			interrupts = <47>;
+			clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
+			clock-names = "rtc", "reg";
+		};
+
 		cgu: clock-controller@40050000 {
 			compatible = "nxp,lpc1850-cgu";
 			reg = <0x40050000 0x1000>;
 			#clock-cells = <1>;
-			clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
+			clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
 		};
 
 		ccu1: clock-controller@40051000 {
@@ -430,6 +444,15 @@
 			status = "disabled";
 		};
 
+		dac: dac@400e1000 {
+			compatible = "nxp,lpc1850-dac";
+			reg = <0x400e1000 0x1000>;
+			interrupts = <0>;
+			clocks = <&ccu1 CLK_APB3_DAC>;
+			resets = <&rgu 42>;
+			status = "disabled";
+		};
+
 		can0: can@400e2000 {
 			compatible = "bosch,c_can";
 			reg = <0x400e2000 0x1000>;
@@ -439,6 +462,24 @@
 			status = "disabled";
 		};
 
+		adc0: adc@400e3000 {
+			compatible = "nxp,lpc1850-adc";
+			reg = <0x400e3000 0x1000>;
+			interrupts = <17>;
+			clocks = <&ccu1 CLK_APB3_ADC0>;
+			resets = <&rgu 40>;
+			status = "disabled";
+		};
+
+		adc1: adc@400e4000 {
+			compatible = "nxp,lpc1850-adc";
+			reg = <0x400e4000 0x1000>;
+			interrupts = <21>;
+			clocks = <&ccu1 CLK_APB3_ADC1>;
+			resets = <&rgu 41>;
+			status = "disabled";
+		};
+
 		gpio: gpio@400f4000 {
 			compatible = "nxp,lpc1850-gpio";
 			reg = <0x400f4000 0x4000>;
diff --git a/sys/gnu/dts/arm/ea3250.dts b/sys/gnu/dts/arm/lpc3250-ea3250.dts
index a4a281fe82af..52b3ed10283a 100644
--- a/sys/gnu/dts/arm/ea3250.dts
+++ b/sys/gnu/dts/arm/lpc3250-ea3250.dts
@@ -25,119 +25,6 @@
 		reg = <0x80000000 0x4000000>;
 	};
 
-	ahb {
-		mac: ethernet@31060000 {
-			phy-mode = "rmii";
-			use-iram;
-		};
-
-		/* 128MB Flash via SLC NAND controller */
-		slc: flash@20020000 {
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			nxp,wdr-clks = <14>;
-			nxp,wwidth = <260000000>;
-			nxp,whold = <104000000>;
-			nxp,wsetup = <200000000>;
-			nxp,rdr-clks = <14>;
-			nxp,rwidth = <34666666>;
-			nxp,rhold = <104000000>;
-			nxp,rsetup = <200000000>;
-			nand-on-flash-bbt;
-			gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
-
-			mtd0@00000000 {
-				label = "ea3250-boot";
-				reg = <0x00000000 0x00080000>;
-				read-only;
-			};
-
-			mtd1@00080000 {
-				label = "ea3250-uboot";
-				reg = <0x00080000 0x000c0000>;
-				read-only;
-			};
-
-			mtd2@00140000 {
-				label = "ea3250-kernel";
-				reg = <0x00140000 0x00400000>;
-			};
-
-			mtd3@00540000 {
-				label = "ea3250-rootfs";
-				reg = <0x00540000 0x07ac0000>;
-			};
-		};
-
-		apb {
-			uart5: serial@40090000 {
-				status = "okay";
-			};
-
-			uart3: serial@40080000 {
-				status = "okay";
-			};
-
-			uart6: serial@40098000 {
-				status = "okay";
-			};
-
-			i2c1: i2c@400A0000 {
-				clock-frequency = <100000>;
-
-				eeprom@50 {
-					compatible = "at,24c256";
-					reg = <0x50>;
-				};
-
-				eeprom@57 {
-					compatible = "at,24c64";
-					reg = <0x57>;
-				};
-
-				uda1380: uda1380@18 {
-					compatible = "nxp,uda1380";
-					reg = <0x18>;
-					power-gpio = <&gpio 0x59 0>;
-					reset-gpio = <&gpio 0x51 0>;
-					dac-clk = "wspll";
-				};
-
-				pca9532: pca9532@60 {
-					compatible = "nxp,pca9532";
-					gpio-controller;
-					#gpio-cells = <2>;
-					reg = <0x60>;
-				};
-			};
-
-			i2c2: i2c@400A8000 {
-				clock-frequency = <100000>;
-			};
-
-			sd@20098000 {
-				wp-gpios = <&pca9532 5 0>;
-				cd-gpios = <&pca9532 4 0>;
-				cd-inverted;
-				bus-width = <4>;
-				status = "okay";
-			};
-		};
-
-		fab {
-			uart1: serial@40014000 {
-				status = "okay";
-			};
-
-			/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
-			adc@40048000 {
-				status = "okay";
-			};
-		};
-	};
-
 	gpio_keys {
 		compatible = "gpio-keys";
 		#address-cells = <1>;
@@ -258,12 +145,44 @@
 	};
 };
 
-/* Here, choose exactly one from: ohci, usbd */
-&ohci /* &usbd */ {
-	transceiver = <&isp1301>;
+/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
+&adc {
 	status = "okay";
 };
 
+&i2c1 {
+	clock-frequency = <100000>;
+
+	uda1380: uda1380@18 {
+		compatible = "nxp,uda1380";
+		reg = <0x18>;
+		power-gpio = <&gpio 0x59 0>;
+		reset-gpio = <&gpio 0x51 0>;
+		dac-clk = "wspll";
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+	};
+
+	eeprom@57 {
+		compatible = "atmel,24c64";
+		reg = <0x57>;
+	};
+
+	pca9532: pca9532@60 {
+		compatible = "nxp,pca9532";
+		gpio-controller;
+		#gpio-cells = <2>;
+		reg = <0x60>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+};
+
 &i2cusb {
 	clock-frequency = <100000>;
 
@@ -272,3 +191,82 @@
 		reg = <0x2d>;
 	};
 };
+
+&mac {
+	phy-mode = "rmii";
+	use-iram;
+};
+
+/* Here, choose exactly one from: ohci, usbd */
+&ohci /* &usbd */ {
+	transceiver = <&isp1301>;
+	status = "okay";
+};
+
+&sd {
+	wp-gpios = <&pca9532 5 0>;
+	cd-gpios = <&pca9532 4 0>;
+	cd-inverted;
+	bus-width = <4>;
+	status = "okay";
+};
+
+/* 128MB Flash via SLC NAND controller */
+&slc {
+	status = "okay";
+
+	nxp,wdr-clks = <14>;
+	nxp,wwidth = <260000000>;
+	nxp,whold = <104000000>;
+	nxp,wsetup = <200000000>;
+	nxp,rdr-clks = <14>;
+	nxp,rwidth = <34666666>;
+	nxp,rhold = <104000000>;
+	nxp,rsetup = <200000000>;
+	nand-on-flash-bbt;
+	gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mtd0@00000000 {
+			label = "ea3250-boot";
+			reg = <0x00000000 0x00080000>;
+			read-only;
+		};
+
+		mtd1@00080000 {
+			label = "ea3250-uboot";
+			reg = <0x00080000 0x000c0000>;
+			read-only;
+		};
+
+		mtd2@00140000 {
+			label = "ea3250-kernel";
+			reg = <0x00140000 0x00400000>;
+		};
+
+		mtd3@00540000 {
+			label = "ea3250-rootfs";
+			reg = <0x00540000 0x07ac0000>;
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&uart6 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/lpc3250-phy3250.dts b/sys/gnu/dts/arm/lpc3250-phy3250.dts
new file mode 100644
index 000000000000..fd95e2b10357
--- /dev/null
+++ b/sys/gnu/dts/arm/lpc3250-phy3250.dts
@@ -0,0 +1,226 @@
+/*
+ * PHYTEC phyCORE-LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "lpc32xx.dtsi"
+
+/ {
+	model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
+	compatible = "phytec,phy3250", "nxp,lpc3250";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x4000000>;
+	};
+
+	regulators {
+		backlight_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "backlight_reg";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			gpio = <&gpio 5 4 0>;
+			enable-active-high;
+			regulator-boot-on;
+		};
+
+		lcd_reg: regulator@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "lcd_reg";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			gpio = <&gpio 5 0 0>;
+			enable-active-high;
+			regulator-boot-on;
+		};
+
+		sd_reg: regulator@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "sd_reg";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			gpio = <&gpio 5 5 0>;
+			enable-active-high;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0 { /* red */
+			gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
+			default-state = "off";
+		};
+
+		led1 { /* green */
+			gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
+			linux,default-trigger = "heartbeat";
+		};
+	};
+};
+
+&clcd {
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+
+	uda1380: uda1380@18 {
+		compatible = "nxp,uda1380";
+		reg = <0x18>;
+		power-gpio = <&gpio 0x59 0>;
+		reset-gpio = <&gpio 0x51 0>;
+		dac-clk = "wspll";
+	};
+
+	pcf8563: rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+};
+
+&i2cusb {
+	clock-frequency = <100000>;
+
+	isp1301: usb-transceiver@2c {
+		compatible = "nxp,isp1301";
+		reg = <0x2c>;
+	};
+};
+
+&key {
+	keypad,num-rows = <1>;
+	keypad,num-columns = <1>;
+	nxp,debounce-delay-ms = <3>;
+	nxp,scan-delay-ms = <34>;
+	linux,keymap = <0x00000002>;
+	status = "okay";
+};
+
+&mac {
+	phy-mode = "rmii";
+	use-iram;
+};
+
+/* Here, choose exactly one from: ohci, usbd */
+&ohci /* &usbd */ {
+	transceiver = <&isp1301>;
+	status = "okay";
+};
+
+&sd {
+	wp-gpios = <&gpio 3 0 0>;
+	cd-gpios = <&gpio 3 1 0>;
+	cd-inverted;
+	bus-width = <4>;
+	vmmc-supply = <&sd_reg>;
+	status = "okay";
+};
+
+/* 64MB Flash via SLC NAND controller */
+&slc {
+	status = "okay";
+
+	nxp,wdr-clks = <14>;
+	nxp,wwidth = <40000000>;
+	nxp,whold = <100000000>;
+	nxp,wsetup = <100000000>;
+	nxp,rdr-clks = <14>;
+	nxp,rwidth = <40000000>;
+	nxp,rhold = <66666666>;
+	nxp,rsetup = <100000000>;
+	nand-on-flash-bbt;
+	gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mtd0@00000000 {
+			label = "phy3250-boot";
+			reg = <0x00000000 0x00064000>;
+			read-only;
+		};
+
+		mtd1@00064000 {
+			label = "phy3250-uboot";
+			reg = <0x00064000 0x00190000>;
+			read-only;
+		};
+
+		mtd2@001f4000 {
+			label = "phy3250-ubt-prms";
+			reg = <0x001f4000 0x00010000>;
+		};
+
+		mtd3@00204000 {
+			label = "phy3250-kernel";
+			reg = <0x00204000 0x00400000>;
+		};
+
+		mtd4@00604000 {
+			label = "phy3250-rootfs";
+			reg = <0x00604000 0x039fc000>;
+		};
+	};
+};
+
+&ssp0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	num-cs = <1>;
+	cs-gpios = <&gpio 3 5 0>;
+	status = "okay";
+
+	eeprom: at25@0 {
+		compatible = "atmel,at25";
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+
+		pl022,interface = <0>;
+		pl022,com-mode = <0>;
+		pl022,rx-level-trig = <1>;
+		pl022,tx-level-trig = <1>;
+		pl022,ctrl-len = <11>;
+		pl022,wait-state = <0>;
+		pl022,duplex = <0>;
+
+		at25,byte-len = <0x8000>;
+		at25,addr-mode = <2>;
+		at25,page-size = <64>;
+	};
+};
+
+&tsc {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/lpc32xx.dtsi b/sys/gnu/dts/arm/lpc32xx.dtsi
index c85cf979725e..e295e1ec82a5 100644
--- a/sys/gnu/dts/arm/lpc32xx.dtsi
+++ b/sys/gnu/dts/arm/lpc32xx.dtsi
@@ -13,6 +13,9 @@
 
 #include "skeleton.dtsi"
 
+#include <dt-bindings/clock/lpc32xx-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
 	compatible = "nxp,lpc3220";
 	interrupt-parent = <&mic>;
@@ -28,6 +31,22 @@
 		};
 	};
 
+	clocks {
+		xtal_32k: xtal_32k {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+			clock-output-names = "xtal_32k";
+		};
+
+		xtal: xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <13000000>;
+			clock-output-names = "xtal";
+		};
+	};
+
 	ahb {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -41,20 +60,24 @@
 		slc: flash@20020000 {
 			compatible = "nxp,lpc3220-slc";
 			reg = <0x20020000 0x1000>;
+			clocks = <&clk LPC32XX_CLK_SLC>;
 			status = "disabled";
 		};
 
 		mlc: flash@200a8000 {
 			compatible = "nxp,lpc3220-mlc";
 			reg = <0x200a8000 0x11000>;
-			interrupts = <11 0>;
+			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk LPC32XX_CLK_MLC>;
 			status = "disabled";
 		};
 
 		dma: dma@31000000 {
 			compatible = "arm,pl080", "arm,primecell";
 			reg = <0x31000000 0x1000>;
-			interrupts = <0x1c 0>;
+			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk LPC32XX_CLK_DMA>;
+			clock-names = "apb_pclk";
 		};
 
 		usb {
@@ -69,43 +92,63 @@
 			ohci: ohci@0 {
 				compatible = "nxp,ohci-nxp", "usb-ohci";
 				reg = <0x0 0x300>;
-				interrupts = <0x3b 0>;
+				interrupt-parent = <&sic1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
 				status = "disabled";
 			};
 
 			usbd: usbd@0 {
 				compatible = "nxp,lpc3220-udc";
 				reg = <0x0 0x300>;
-				interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
+				interrupt-parent = <&sic1>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+					     <30 IRQ_TYPE_LEVEL_HIGH>,
+					     <28 IRQ_TYPE_LEVEL_HIGH>,
+					     <26 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 				status = "disabled";
 			};
 
 			i2cusb: i2c@300 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x300 0x100>;
-				interrupts = <0x3f 0>;
+				interrupt-parent = <&sic1>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
 			};
+
+			usbclk: clock-controller@f00 {
+				compatible = "nxp,lpc3220-usb-clk";
+				reg = <0xf00 0x100>;
+				#clock-cells = <1>;
+			};
 		};
 
 		clcd: clcd@31040000 {
 			compatible = "arm,pl110", "arm,primecell";
 			reg = <0x31040000 0x1000>;
-			interrupts = <0x0e 0>;
+			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk LPC32XX_CLK_LCD>;
+			clock-names = "apb_pclk";
 			status = "disabled";
 		};
 
 		mac: ethernet@31060000 {
 			compatible = "nxp,lpc-eth";
 			reg = <0x31060000 0x1000>;
-			interrupts = <0x1d 0>;
+			interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk LPC32XX_CLK_MAC>;
 		};
 
 		emc: memory-controller@31080000 {
 			compatible = "arm,pl175", "arm,primecell";
 			reg = <0x31080000 0x1000>;
+			clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
+			clock-names = "mpmcclk", "apb_pclk";
 			#address-cells = <1>;
 			#size-cells = <1>;
 
@@ -122,26 +165,44 @@
 			compatible = "simple-bus";
 			ranges = <0x20000000 0x20000000 0x30000000>;
 
+			/*
+			 * ssp0 and spi1 are shared pins;
+			 * enable one in your board dts, as needed.
+			 */
 			ssp0: ssp@20084000 {
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0x20084000 0x1000>;
-				interrupts = <0x14 0>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_SSP0>;
+				clock-names = "apb_pclk";
+				status = "disabled";
 			};
 
 			spi1: spi@20088000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20088000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_SPI1>;
+				status = "disabled";
 			};
 
+			/*
+			 * ssp1 and spi2 are shared pins;
+			 * enable one in your board dts, as needed.
+			 */
 			ssp1: ssp@2008c000 {
 				compatible = "arm,pl022", "arm,primecell";
 				reg = <0x2008c000 0x1000>;
-				interrupts = <0x15 0>;
+				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_SSP1>;
+				clock-names = "apb_pclk";
+				status = "disabled";
 			};
 
 			spi2: spi@20090000 {
 				compatible = "nxp,lpc3220-spi";
 				reg = <0x20090000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_SPI2>;
+				status = "disabled";
 			};
 
 			i2s0: i2s@20094000 {
@@ -152,7 +213,10 @@
 			sd: sd@20098000 {
 				compatible = "arm,pl18x", "arm,primecell";
 				reg = <0x20098000 0x1000>;
-				interrupts = <0x0f 0>, <0x0d 0>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+					     <13 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_SD>;
+				clock-names = "apb_pclk";
 				status = "disabled";
 			};
 
@@ -166,55 +230,59 @@
 				/* actually, ns16550a w/ 64 byte fifos! */
 				compatible = "nxp,lpc3220-uart";
 				reg = <0x40090000 0x1000>;
-				interrupts = <9 0>;
-				clock-frequency = <13000000>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
+				clocks = <&clk LPC32XX_CLK_UART5>;
 				status = "disabled";
 			};
 
 			uart3: serial@40080000 {
 				compatible = "nxp,lpc3220-uart";
 				reg = <0x40080000 0x1000>;
-				interrupts = <7 0>;
-				clock-frequency = <13000000>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
+				clocks = <&clk LPC32XX_CLK_UART3>;
 				status = "disabled";
 			};
 
 			uart4: serial@40088000 {
 				compatible = "nxp,lpc3220-uart";
 				reg = <0x40088000 0x1000>;
-				interrupts = <8 0>;
-				clock-frequency = <13000000>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
+				clocks = <&clk LPC32XX_CLK_UART4>;
 				status = "disabled";
 			};
 
 			uart6: serial@40098000 {
 				compatible = "nxp,lpc3220-uart";
 				reg = <0x40098000 0x1000>;
-				interrupts = <10 0>;
-				clock-frequency = <13000000>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
 				reg-shift = <2>;
+				clocks = <&clk LPC32XX_CLK_UART6>;
 				status = "disabled";
 			};
 
 			i2c1: i2c@400A0000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A0000 0x100>;
-				interrupts = <0x33 0>;
+				interrupt-parent = <&sic1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
+				clocks = <&clk LPC32XX_CLK_I2C1>;
 			};
 
 			i2c2: i2c@400A8000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A8000 0x100>;
-				interrupts = <0x32 0>;
+				interrupt-parent = <&sic1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
+				clocks = <&clk LPC32XX_CLK_I2C2>;
 			};
 
 			mpwm: mpwm@400E8000 {
@@ -231,44 +299,82 @@
 			compatible = "simple-bus";
 			ranges = <0x20000000 0x20000000 0x30000000>;
 
-			/*
-			 * MIC Interrupt controller includes:
-			 *   MIC @40008000
-			 *   SIC1 @4000C000
-			 *   SIC2 @40010000
-			 */
+			/* System Control Block */
+			scb {
+				compatible = "simple-bus";
+				ranges = <0x0 0x040004000 0x00001000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				clk: clock-controller@0 {
+					compatible = "nxp,lpc3220-clk";
+					reg = <0x00 0x114>;
+					#clock-cells = <1>;
+
+					clocks = <&xtal_32k>, <&xtal>;
+					clock-names = "xtal_32k", "xtal";
+
+					assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
+					assigned-clock-rates = <208000000>;
+				};
+			};
+
 			mic: interrupt-controller@40008000 {
 				compatible = "nxp,lpc3220-mic";
+				reg = <0x40008000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			sic1: interrupt-controller@4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller@40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
 				interrupt-controller;
-				reg = <0x40008000 0xC000>;
 				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
 			};
 
 			uart1: serial@40014000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40014000 0x1000>;
-				interrupts = <26 0>;
+				interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			uart2: serial@40018000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40018000 0x1000>;
-				interrupts = <25 0>;
+				interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			uart7: serial@4001c000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x4001c000 0x1000>;
-				interrupts = <24 0>;
+				interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			rtc: rtc@40024000 {
 				compatible = "nxp,lpc3220-rtc";
 				reg = <0x40024000 0x1000>;
-				interrupts = <0x34 0>;
+				interrupt-parent = <&sic1>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_RTC>;
 			};
 
 			gpio: gpio@40028000 {
@@ -281,26 +387,33 @@
 			timer4: timer@4002C000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x4002C000 0x1000>;
-				interrupts = <0x3 0>;
+				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER4>;
+				clock-names = "timerclk";
 				status = "disabled";
 			};
 
 			timer5: timer@40030000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x40030000 0x1000>;
-				interrupts = <0x4 0>;
+				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER5>;
+				clock-names = "timerclk";
 				status = "disabled";
 			};
 
 			watchdog: watchdog@4003C000 {
 				compatible = "nxp,pnx4008-wdt";
 				reg = <0x4003C000 0x1000>;
+				clocks = <&clk LPC32XX_CLK_WDOG>;
 			};
 
 			timer0: timer@40044000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x40044000 0x1000>;
-				interrupts = <0x10 0>;
+				clocks = <&clk LPC32XX_CLK_TIMER0>;
+				clock-names = "timerclk";
+				interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
 			};
 
 			/*
@@ -313,53 +426,65 @@
 			adc: adc@40048000 {
 				compatible = "nxp,lpc3220-adc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <0x27 0>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
 
 			tsc: tsc@40048000 {
 				compatible = "nxp,lpc3220-tsc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <0x27 0>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
 
 			timer1: timer@4004C000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x4004C000 0x1000>;
-				interrupts = <0x11 0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER1>;
+				clock-names = "timerclk";
 			};
 
 			key: key@40050000 {
 				compatible = "nxp,lpc3220-key";
 				reg = <0x40050000 0x1000>;
-				interrupts = <54 0>;
+				interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
 			timer2: timer@40058000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x40058000 0x1000>;
-				interrupts = <0x12 0>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER2>;
+				clock-names = "timerclk";
 				status = "disabled";
 			};
 
 			pwm1: pwm@4005C000 {
 				compatible = "nxp,lpc3220-pwm";
 				reg = <0x4005C000 0x4>;
+				clocks = <&clk LPC32XX_CLK_PWM1>;
 				status = "disabled";
 			};
 
 			pwm2: pwm@4005C004 {
 				compatible = "nxp,lpc3220-pwm";
 				reg = <0x4005C004 0x4>;
+				clocks = <&clk LPC32XX_CLK_PWM2>;
 				status = "disabled";
 			};
 
 			timer3: timer@40060000 {
 				compatible = "nxp,lpc3220-timer";
 				reg = <0x40060000 0x1000>;
-				interrupts = <0x13 0>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+				clocks = <&clk LPC32XX_CLK_TIMER3>;
+				clock-names = "timerclk";
 				status = "disabled";
 			};
 		};
diff --git a/sys/gnu/dts/arm/lpc4350-hitex-eval.dts b/sys/gnu/dts/arm/lpc4350-hitex-eval.dts
index 022d495432c1..6c9048d4d03c 100644
--- a/sys/gnu/dts/arm/lpc4350-hitex-eval.dts
+++ b/sys/gnu/dts/arm/lpc4350-hitex-eval.dts
@@ -45,50 +45,50 @@
 		poll-interval = <100>;
 		autorepeat;
 
-		button@0 {
+		button0 {
 			label = "joy:right";
 			linux,code = <KEY_RIGHT>;
 			gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>;
 		};
 
-		button@1 {
+		button1 {
 			label = "joy:up";
 			linux,code = <KEY_UP>;
 			gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>;
 		};
 
 
-		button@2 {
+		button2 {
 			label = "joy:enter";
 			linux,code = <KEY_ENTER>;
 			gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>;
 		};
 
-		button@3 {
+		button3 {
 			label = "joy:left";
 			linux,code = <KEY_LEFT>;
 			gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>;
 		};
 
-		button@4 {
+		button4 {
 			label = "joy:down";
 			linux,code = <KEY_DOWN>;
 			gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>;
 		};
 
-		button@5 {
+		button5 {
 			label = "user:sw3";
 			linux,code = <KEY_F1>;
 			gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>;
 		};
 
-		button@6 {
+		button6 {
 			label = "user:sw4";
 			linux,code = <KEY_F2>;
 			gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>;
 		};
 
-		button@7 {
+		button7 {
 			label = "user:sw5";
 			linux,code = <KEY_F3>;
 			gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>;
@@ -119,9 +119,25 @@
 			gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>;
 		};
 	};
+
+	vcc: vcc_fixed {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3io";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
 };
 
 &pinctrl {
+	adc1_pins: adc1-pins {
+		adc1_pins_cfg {
+			pins = "pf_9";
+			function = "adc";
+			input-disable;
+			bias-disable;
+		};
+	};
+
 	emc_pins: emc-pins {
 		emc_addr0_23_cfg {
 			pins =	"p2_9",  "p2_10", "p2_11", "p2_12",
@@ -325,6 +341,13 @@
 	};
 };
 
+&adc1 {
+	status = "okay";
+	vref-supply = <&vcc>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&adc1_pins>;
+};
+
 &emc {
 	status = "okay";
 	pinctrl-names = "default";
@@ -430,7 +453,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spifi_pins>;
 
-	flash@0 {
+	flash {
 		compatible = "jedec,spi-nor";
 		spi-rx-bus-width = <4>;
 		#address-cells = <1>;
diff --git a/sys/gnu/dts/arm/lpc4357-ea4357-devkit.dts b/sys/gnu/dts/arm/lpc4357-ea4357-devkit.dts
index 079d3cf8c00b..1919be4dab2b 100644
--- a/sys/gnu/dts/arm/lpc4357-ea4357-devkit.dts
+++ b/sys/gnu/dts/arm/lpc4357-ea4357-devkit.dts
@@ -38,6 +38,13 @@
 		reg = <0x28000000 0x2000000>; /* 32 MB */
 	};
 
+	vcc: vcc_fixed {
+		compatible = "regulator-fixed";
+		regulator-name = "3v3-supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
 	/* vmmc is controlled by sdmmc host internally */
 	vmmc: vmmc_fixed {
 		compatible = "regulator-fixed";
@@ -55,31 +62,31 @@
 		poll-interval = <100>;
 		autorepeat;
 
-		button@0 {
+		button0 {
 			label = "joy_enter";
 			linux,code = <KEY_ENTER>;
 			gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>;
 		};
 
-		button@1 {
+		button1 {
 			label = "joy_left";
 			linux,code = <KEY_LEFT>;
 			gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>;
 		};
 
-		button@2 {
+		button2 {
 			label = "joy_up";
 			linux,code = <KEY_UP>;
 			gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>;
 		};
 
-		button@3 {
+		button3 {
 			label = "joy_right";
 			linux,code = <KEY_RIGHT>;
 			gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>;
 		};
 
-		button@4 {
+		button4 {
 			label = "joy_down";
 			linux,code = <KEY_DOWN>;
 			gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>;
@@ -461,6 +468,11 @@
 	};
 };
 
+&adc0 {
+	status = "okay";
+	vref-supply = <&vcc>;
+};
+
 &i2c0 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -483,6 +495,11 @@
 	};
 };
 
+&dac {
+	status = "okay";
+	vref-supply = <&vcc>;
+};
+
 &emc {
 	status = "okay";
 	pinctrl-names = "default";
@@ -567,7 +584,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spifi_pins>;
 
-	flash@0 {
+	flash {
 		compatible = "jedec,spi-nor";
 		spi-cpol;
 		spi-cpha;
diff --git a/sys/gnu/dts/arm/ls1021a.dtsi b/sys/gnu/dts/arm/ls1021a.dtsi
index 2c84ca236473..5ae8e9297e9a 100644
--- a/sys/gnu/dts/arm/ls1021a.dtsi
+++ b/sys/gnu/dts/arm/ls1021a.dtsi
@@ -119,6 +119,20 @@
 
 		};
 
+		msi1: msi-controller@1570e00 {
+			compatible = "fsl,1s1021a-msi";
+			reg = <0x0 0x1570e00 0x0 0x8>;
+			msi-controller;
+			interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		msi2: msi-controller@1570e08 {
+			compatible = "fsl,1s1021a-msi";
+			reg = <0x0 0x1570e08 0x0 0x8>;
+			msi-controller;
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		ifc: ifc@1530000 {
 			compatible = "fsl,ifc", "simple-bus";
 			reg = <0x0 0x1530000 0x0 0x10000>;
@@ -245,7 +259,7 @@
 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "dspi";
 			clocks = <&platform_clk 1>;
-			spi-num-chipselects = <5>;
+			spi-num-chipselects = <6>;
 			big-endian;
 			status = "disabled";
 		};
@@ -258,7 +272,7 @@
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "dspi";
 			clocks = <&platform_clk 1>;
-			spi-num-chipselects = <5>;
+			spi-num-chipselects = <6>;
 			big-endian;
 			status = "disabled";
 		};
@@ -332,6 +346,46 @@
 			status = "disabled";
 		};
 
+		gpio0: gpio@2300000 {
+			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+			reg = <0x0 0x2300000 0x0 0x10000>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio1: gpio@2310000 {
+			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+			reg = <0x0 0x2310000 0x0 0x10000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@2320000 {
+			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+			reg = <0x0 0x2320000 0x0 0x10000>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@2330000 {
+			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+			reg = <0x0 0x2330000 0x0 0x10000>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
 		lpuart0: serial@2950000 {
 			compatible = "fsl,ls1021a-lpuart";
 			reg = <0x0 0x2950000 0x0 0x1000>;
@@ -443,8 +497,9 @@
 			compatible = "fsl,ls1021a-dcu";
 			reg = <0x0 0x2ce0000 0x0 0x10000>;
 			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&platform_clk 0>;
-			clock-names = "dcu";
+			clocks = <&platform_clk 0>,
+				<&platform_clk 0>;
+			clock-names = "dcu", "pix";
 			big-endian;
 			status = "disabled";
 		};
@@ -457,6 +512,18 @@
 			reg = <0x0 0x2d24000 0x0 0x4000>;
 		};
 
+		ptp_clock@2d10e00 {
+			compatible = "fsl,etsec-ptp";
+			reg = <0x0 0x2d10e00 0x0 0xb0>;
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,tclk-period = <5>;
+			fsl,tmr-prsc    = <2>;
+			fsl,tmr-add     = <0xaaaaaaab>;
+			fsl,tmr-fiper1  = <999999990>;
+			fsl,tmr-fiper2  = <99990>;
+			fsl,max-adj     = <499999999>;
+		};
+
 		enet0: ethernet@2d10000 {
 			compatible = "fsl,etsec2";
 			device_type = "network";
@@ -560,5 +627,51 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 		};
+
+		pcie@3400000 {
+			compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
+			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+			fsl,pcie-scfg = <&scfg 0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&msi1>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pcie@3500000 {
+			compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
+			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,pcie-scfg = <&scfg 1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&msi2>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+		};
 	};
 };
diff --git a/sys/gnu/dts/arm/meson8.dtsi b/sys/gnu/dts/arm/meson8.dtsi
index 9917f5f65794..3f21e4fba42d 100644
--- a/sys/gnu/dts/arm/meson8.dtsi
+++ b/sys/gnu/dts/arm/meson8.dtsi
@@ -91,8 +91,8 @@
 		clock-frequency = <141666666>;
 	};
 
-	pinctrl: pinctrl@c1109880 {
-		compatible = "amlogic,meson8-pinctrl";
+	pinctrl_cbus: pinctrl@c1109880 {
+		compatible = "amlogic,meson8-cbus-pinctrl";
 		reg = <0xc1109880 0x10>;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -108,29 +108,6 @@
 			#gpio-cells = <2>;
 		};
 
-		gpio_ao: ao-bank@c1108030 {
-			reg = <0xc8100014 0x4>,
-			      <0xc810002c 0x4>,
-			      <0xc8100024 0x8>;
-			reg-names = "mux", "pull", "gpio";
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		uart_ao_a_pins: uart_ao_a {
-			mux {
-				groups = "uart_tx_ao_a", "uart_rx_ao_a";
-				function = "uart_ao";
-			};
-		};
-
-		i2c_ao_pins: i2c_mst_ao {
-			mux {
-				groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
-				function = "i2c_mst_ao";
-			};
-		};
-
 		spi_nor_pins: nor {
 			mux {
 				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
@@ -157,6 +134,36 @@
 		};
 	};
 
+	pinctrl_aobus: pinctrl@c8100084 {
+		compatible = "amlogic,meson8-aobus-pinctrl";
+		reg = <0xc8100084 0xc>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gpio_ao: ao-bank@c1108030 {
+			reg = <0xc8100014 0x4>,
+			      <0xc810002c 0x4>,
+			      <0xc8100024 0x8>;
+			reg-names = "mux", "pull", "gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		uart_ao_a_pins: uart_ao_a {
+			mux {
+				groups = "uart_tx_ao_a", "uart_rx_ao_a";
+				function = "uart_ao";
+			};
+		};
+
+		i2c_ao_pins: i2c_mst_ao {
+			mux {
+				groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
+				function = "i2c_mst_ao";
+			};
+		};
+	};
 }; /* end of / */
 
 &L2 {
diff --git a/sys/gnu/dts/arm/meson8b.dtsi b/sys/gnu/dts/arm/meson8b.dtsi
index 8bad5571af46..2bfe401a4da9 100644
--- a/sys/gnu/dts/arm/meson8b.dtsi
+++ b/sys/gnu/dts/arm/meson8b.dtsi
@@ -155,8 +155,8 @@
 			reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
 		};
 
-		pinctrl: pinctrl@c1109880 {
-			compatible = "amlogic,meson8b-pinctrl";
+		pinctrl_cbus: pinctrl@c1109880 {
+			compatible = "amlogic,meson8b-cbus-pinctrl";
 			reg = <0xc1109880 0x10>;
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -171,6 +171,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 			};
+		};
+
+		pinctrl_aobus: pinctrl@c8100084 {
+			compatible = "amlogic,meson8b-aobus-pinctrl";
+			reg = <0xc8100084 0xc>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
 
 			gpio_ao: ao-bank@c1108030 {
 				reg = <0xc8100014 0x4>,
diff --git a/sys/gnu/dts/arm/rk3288-thermal.dtsi b/sys/gnu/dts/arm/mps2-an385.dts
index 651b962e3d53..31c374d72a6f 100644
--- a/sys/gnu/dts/arm/rk3288-thermal.dtsi
+++ b/sys/gnu/dts/arm/mps2-an385.dts
@@ -1,7 +1,7 @@
 /*
- * Device Tree Source for RK3288 SoC thermal
+ * Copyright (C) 2015 ARM Limited
  *
- * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Vladimir Murzin <vladimir.murzin@arm.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,77 +42,51 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <dt-bindings/thermal/thermal.h>
+/dts-v1/;
 
-reserve_thermal: reserve_thermal {
-	polling-delay-passive = <1000>; /* milliseconds */
-	polling-delay = <5000>; /* milliseconds */
+#include "mps2.dtsi"
 
-	thermal-sensors = <&tsadc 0>;
-};
+/ {
+	model = "ARM MPS2 Application Note 385/386";
+	compatible = "arm,mps2";
 
-cpu_thermal: cpu_thermal {
-	polling-delay-passive = <100>; /* milliseconds */
-	polling-delay = <5000>; /* milliseconds */
+	aliases {
+		serial0 = &uart0;
+	};
 
-	thermal-sensors = <&tsadc 1>;
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:9600n8";
+	};
 
-	trips {
-		cpu_alert0: cpu_alert0 {
-			temperature = <70000>; /* millicelsius */
-			hysteresis = <2000>; /* millicelsius */
-			type = "passive";
-		};
-		cpu_alert1: cpu_alert1 {
-			temperature = <75000>; /* millicelsius */
-			hysteresis = <2000>; /* millicelsius */
-			type = "passive";
-		};
-		cpu_crit: cpu_crit {
-			temperature = <90000>; /* millicelsius */
-			hysteresis = <2000>; /* millicelsius */
-			type = "critical";
-		};
+	memory {
+		device_type = "memory";
+		reg = <0x21000000 0x1000000>;
 	};
 
-	cooling-maps {
-		map0 {
-			trip = <&cpu_alert0>;
-			cooling-device =
-				<&cpu0 THERMAL_NO_LIMIT 6>;
-		};
-		map1 {
-			trip = <&cpu_alert1>;
-			cooling-device =
-				<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+	smb {
+		ethernet@0,0 {
+			compatible = "smsc,lan9220", "smsc,lan9115";
+			reg = <0 0x0 0x10000>;
+			interrupts = <13>;
+			interrupt-parent = <&nvic>;
+			smsc,irq-active-high;
 		};
 	};
 };
 
-gpu_thermal: gpu_thermal {
-	polling-delay-passive = <100>; /* milliseconds */
-	polling-delay = <5000>; /* milliseconds */
+&uart0 {
+	status = "okay";
+};
 
-	thermal-sensors = <&tsadc 2>;
+&timer0 {
+	status = "okay";
+};
 
-	trips {
-		gpu_alert0: gpu_alert0 {
-			temperature = <70000>; /* millicelsius */
-			hysteresis = <2000>; /* millicelsius */
-			type = "passive";
-		};
-		gpu_crit: gpu_crit {
-			temperature = <90000>; /* millicelsius */
-			hysteresis = <2000>; /* millicelsius */
-			type = "critical";
-		};
-	};
+&timer1 {
+	status = "okay";
+};
 
-	cooling-maps {
-		map0 {
-			trip = <&gpu_alert0>;
-			cooling-device =
-				<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-		};
-	};
+&wdt {
+	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/mps2-an399.dts b/sys/gnu/dts/arm/mps2-an399.dts
new file mode 100644
index 000000000000..5e7e5ca2edbf
--- /dev/null
+++ b/sys/gnu/dts/arm/mps2-an399.dts
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2015 ARM Limited
+ *
+ * Author: Vladimir Murzin <vladimir.murzin@arm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "mps2.dtsi"
+
+/ {
+	model = "ARM MPS2 Application Note 399/400";
+	compatible = "arm,mps2";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:9600n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x1000000>;
+	};
+
+	smb {
+		ethernet@1,0 {
+			compatible = "smsc,lan9220", "smsc,lan9115";
+			reg = <1 0x0 0x10000>;
+			interrupts = <13>;
+			interrupt-parent = <&nvic>;
+			smsc,irq-active-high;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/mps2.dtsi b/sys/gnu/dts/arm/mps2.dtsi
new file mode 100644
index 000000000000..e3fed8d34558
--- /dev/null
+++ b/sys/gnu/dts/arm/mps2.dtsi
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2015 ARM Limited
+ *
+ * Author: Vladimir Murzin <vladimir.murzin@arm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armv7-m.dtsi"
+
+/ {
+	oscclk0: clk-osc0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+	};
+
+	oscclk1: clk-osc1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24576000>;
+	};
+
+	oscclk2: clk-osc2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	cfgclk: clk-cfg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <5000000>;
+	};
+
+	spicfgclk: clk-spicfg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <75000000>;
+	};
+
+	sysclk: clk-sys {
+		compatible = "fixed-factor-clock";
+		clocks = <&oscclk0>;
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+	};
+
+	audmclk: clk-audm {
+		compatible = "fixed-factor-clock";
+		clocks = <&oscclk1>;
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+	};
+
+	audsclk: clk-auds {
+		compatible = "fixed-factor-clock";
+		clocks = <&oscclk1>;
+		#clock-cells = <0>;
+		clock-div = <8>;
+		clock-mult = <1>;
+	};
+
+	spiclcd: clk-cpiclcd {
+		compatible = "fixed-factor-clock";
+		clocks = <&oscclk0>;
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+	};
+
+	spicon: clk-spicon {
+		compatible = "fixed-factor-clock";
+		clocks = <&oscclk0>;
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+	};
+
+	i2cclcd: clk-i2cclcd {
+		compatible = "fixed-factor-clock";
+		clocks = <&oscclk0>;
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+	};
+
+	i2caud: clk-i2caud {
+		compatible = "fixed-factor-clock";
+		clocks = <&oscclk0>;
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+
+		apb@40000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x40000000 0x10000>;
+
+			timer0: mps2-timer0@0 {
+				compatible = "arm,mps2-timer";
+				reg = <0x0 0x1000>;
+				interrupts = <8>;
+				clocks = <&sysclk>;
+				status = "disabled";
+			};
+
+			timer1: mps2-timer1@1000 {
+				compatible = "arm,mps2-timer";
+				reg = <0x1000 0x1000>;
+				interrupts = <9>;
+				clocks = <&sysclk>;
+				status = "disabled";
+			};
+
+			timer2: dual-timer@2000 {
+				compatible = "arm,sp804";
+				reg = <0x2000 0x1000>;
+				clocks = <&sysclk>;
+				interrupts = <10>;
+				status = "disabled";
+			};
+
+			uart0: serial@4000 {
+				compatible = "arm,mps2-uart";
+				reg = <0x4000 0x1000>;
+				interrupts = <0 1 12>;
+				clocks = <&sysclk>;
+				status = "disabled";
+			};
+
+			uart1: serial@5000 {
+				compatible = "arm,mps2-uart";
+				reg = <0x5000 0x1000>;
+				interrupts = <2 3 12>;
+				clocks = <&sysclk>;
+				status = "disabled";
+			};
+
+			uart2: serial@6000 {
+				compatible = "arm,mps2-uart";
+				reg = <0x6000 0x1000>;
+				interrupts = <4 5 12>;
+				clocks = <&sysclk>;
+				status = "disabled";
+			};
+
+			wdt: watchdog@8000 {
+				compatible = "arm,sp805", "arm,primecell";
+				arm,primecell-periphid = <0x00141805>;
+				reg = <0x8000 0x1000>;
+				interrupts = <0>;
+				clocks = <&sysclk>;
+				clock-names = "apb_pclk";
+				status = "disabled";
+			};
+		};
+	};
+
+	fpga@40020000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x40020000 0x10000>;
+
+		fpgaio@8000 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x8000 0x10>;
+
+			led0 {
+				compatible = "register-bit-led";
+				offset = <0x0>;
+				mask = <0x01>;
+				label = "userled:0";
+				linux,default-trigger = "heartbeat";
+				default-state = "on";
+			};
+
+			led1 {
+				compatible = "register-bit-led";
+				offset = <0x0>;
+				mask = <0x02>;
+				label = "userled:1";
+				linux,default-trigger = "usr";
+				default-state = "off";
+			};
+		};
+	};
+
+	smb {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <0 0 0x40200000 0x10000>,
+			 <1 0 0xa0000000 0x10000>;
+	};
+};
diff --git a/sys/gnu/dts/arm/mt2701-pinfunc.h b/sys/gnu/dts/arm/mt2701-pinfunc.h
new file mode 100644
index 000000000000..e24ebc8d928e
--- /dev/null
+++ b/sys/gnu/dts/arm/mt2701-pinfunc.h
@@ -0,0 +1,735 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DTS_MT2701_PINFUNC_H
+#define __DTS_MT2701_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
+
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
+
+#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
+
+#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
+
+#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
+
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)
+
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7)
+
+#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7)
+
+#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
+#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
+#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
+#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7)
+
+#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
+#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
+#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
+#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
+#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7)
+
+#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
+
+#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
+
+#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
+
+#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
+
+#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1)
+#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
+#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
+#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7)
+
+#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
+#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2)
+#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7)
+
+#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
+#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
+#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
+#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
+#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6)
+#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7)
+
+#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7)
+
+#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
+#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
+#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
+#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
+#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
+#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6)
+#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7)
+
+#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
+#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
+#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
+#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
+#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
+#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6)
+#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7)
+
+#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
+#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
+#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
+#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
+#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7)
+#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10)
+
+#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1)
+#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
+#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
+#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
+#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7)
+#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10)
+
+#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
+#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
+#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
+#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7)
+#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10)
+
+#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1)
+#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
+#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
+#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7)
+
+#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
+#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
+#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3)
+#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
+#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
+#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
+#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7)
+
+#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1)
+#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
+#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3)
+#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
+#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
+#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7)
+
+#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
+#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3)
+#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
+#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
+#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7)
+
+#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1)
+#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
+#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3)
+#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
+#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
+#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7)
+#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14)
+
+#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7)
+
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7)
+
+#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7)
+
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7)
+
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7)
+
+#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1)
+#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
+#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
+#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)
+
+#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1)
+#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
+#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
+#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)
+
+#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1)
+#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
+#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)
+
+#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1)
+#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
+#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)
+
+#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1)
+#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
+
+#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
+#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2)
+
+#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
+#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
+
+#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1)
+
+#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1)
+#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)
+
+#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1)
+#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)
+
+#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7)
+
+#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7)
+
+#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
+#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
+#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
+#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7)
+
+#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
+#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
+#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
+#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
+#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5)
+#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7)
+
+#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
+#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7)
+
+#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1)
+
+#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1)
+
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7)
+
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7)
+
+#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7)
+
+#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1)
+
+#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+
+#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1)
+
+#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1)
+
+#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1)
+#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
+#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5)
+
+#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
+#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2)
+
+#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1)
+#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
+
+#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
+#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2)
+
+#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
+#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
+#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7)
+
+#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
+#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7)
+
+#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
+#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1)
+
+#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
+#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1)
+
+#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
+#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1)
+
+#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
+#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1)
+
+#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
+#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1)
+
+#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
+#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1)
+
+#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
+#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1)
+
+#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
+#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1)
+
+#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
+#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1)
+
+#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0)
+#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1)
+
+#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4)
+
+#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3)
+#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4)
+
+#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3)
+#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4)
+
+#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4)
+
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7)
+
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7)
+
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7)
+
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7)
+
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7)
+
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7)
+
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4)
+
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4)
+
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4)
+
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4)
+
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4)
+
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4)
+
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4)
+
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4)
+
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4)
+
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4)
+
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
+
+#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1)
+#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4)
+#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5)
+
+#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1)
+#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+
+#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
+#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4)
+#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5)
+
+#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1)
+#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4)
+#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5)
+
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7)
+
+#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7)
+
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7)
+
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7)
+
+#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1)
+
+#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1)
+#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
+#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5)
+#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7)
+#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9)
+
+#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1)
+#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2)
+#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5)
+#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7)
+#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9)
+
+#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1)
+#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2)
+#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5)
+#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7)
+
+#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1)
+#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2)
+#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3)
+#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5)
+#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7)
+
+#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1)
+#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2)
+#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3)
+#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5)
+#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7)
+
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11)
+
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11)
+
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7)
+
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
+
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2)
+
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2)
+
+#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
+#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
+
+#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
+#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
+
+#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
+#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1)
+#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
+#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3)
+#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4)
+#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7)
+
+#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
+#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
+#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2)
+#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
+#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4)
+#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7)
+
+#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
+#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1)
+
+#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
+#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1)
+
+#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)
+
+#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
+#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1)
+
+#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
+#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1)
+
+#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9)
+
+#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9)
+#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14)
+
+#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9)
+#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14)
+
+#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9)
+#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14)
+
+#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9)
+#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14)
+
+#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9)
+#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14)
+
+#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9)
+#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14)
+
+#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9)
+
+#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9)
+
+#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9)
+
+#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9)
+
+#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9)
+
+#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
+#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
+#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7)
+
+#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
+#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
+
+#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
+#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
+#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6)
+
+#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
+#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
+#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6)
+
+#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
+#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
+#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6)
+
+#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
+#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
+#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6)
+
+#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
+#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
+
+#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
+#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
+
+#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
+#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
+
+#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
+#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
+
+#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
+#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
+
+#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
+#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
+
+#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
+#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
+
+#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
+#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1)
+#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6)
+
+#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
+#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1)
+#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6)
+
+#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
+#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
+
+#endif /* __DTS_MT2701_PINFUNC_H */
diff --git a/sys/gnu/dts/arm/mt2701.dtsi b/sys/gnu/dts/arm/mt2701.dtsi
index 3766904b60f3..18596a2c58a1 100644
--- a/sys/gnu/dts/arm/mt2701.dtsi
+++ b/sys/gnu/dts/arm/mt2701.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "skeleton64.dtsi"
+#include "mt2701-pinfunc.h"
 
 / {
 	compatible = "mediatek,mt2701";
@@ -23,6 +24,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "mediatek,mt81xx-tz-smp";
 
 		cpu@0 {
 			device_type = "cpu";
@@ -46,6 +48,17 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		trustzone-bootinfo@80002000 {
+			compatible = "mediatek,trustzone-bootinfo";
+			reg = <0 0x80002000 0 0x1000>;
+		};
+	};
+
 	system_clk: dummy13m {
 		compatible = "fixed-clock";
 		clock-frequency = <13000000>;
@@ -73,6 +86,24 @@
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	pio: pinctrl@10005000 {
+		compatible = "mediatek,mt2701-pinctrl";
+		reg = <0 0x1000b000 0 0x1000>;
+		mediatek,pctl-regmap = <&syscfg_pctl_a>;
+		pins-are-numbered;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	syscfg_pctl_a: syscfg@10005000 {
+		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
+		reg = <0 0x10005000 0 0x1000>;
+	};
+
 	watchdog: watchdog@10007000 {
 		compatible = "mediatek,mt2701-wdt",
 			     "mediatek,mt6589-wdt";
diff --git a/sys/gnu/dts/arm/mt7623-evb.dts b/sys/gnu/dts/arm/mt7623-evb.dts
new file mode 100644
index 000000000000..a9ee2d64c6f7
--- /dev/null
+++ b/sys/gnu/dts/arm/mt7623-evb.dts
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt7623.dtsi"
+
+/ {
+	model = "MediaTek MT7623 evaluation board";
+	compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	memory {
+		reg = <0 0x80000000 0 0x40000000>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/mt7623.dtsi b/sys/gnu/dts/arm/mt7623.dtsi
new file mode 100644
index 000000000000..fd2b614ae6f3
--- /dev/null
+++ b/sys/gnu/dts/arm/mt7623.dtsi
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton64.dtsi"
+
+/ {
+	compatible = "mediatek,mt7623";
+	interrupt-parent = <&sysirq>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "mediatek,mt6589-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x1>;
+		};
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x2>;
+		};
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x3>;
+		};
+	};
+
+	system_clk: dummy13m {
+		compatible = "fixed-clock";
+		clock-frequency = <13000000>;
+		#clock-cells = <0>;
+	};
+
+	rtc_clk: dummy32k {
+		compatible = "fixed-clock";
+		clock-frequency = <32000>;
+		#clock-cells = <0>;
+	};
+
+	uart_clk: dummy26m {
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+		#clock-cells = <0>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	watchdog: watchdog@10007000 {
+		compatible = "mediatek,mt7623-wdt",
+			     "mediatek,mt6589-wdt";
+		reg = <0 0x10007000 0 0x100>;
+	};
+
+	timer: timer@10008000 {
+		compatible = "mediatek,mt7623-timer",
+			     "mediatek,mt6577-timer";
+		reg = <0 0x10008000 0 0x80>;
+		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&system_clk>, <&rtc_clk>;
+		clock-names = "system-clk", "rtc-clk";
+	};
+
+	sysirq: interrupt-controller@10200100 {
+		compatible = "mediatek,mt7623-sysirq",
+			     "mediatek,mt6577-sysirq";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		reg = <0 0x10200100 0 0x1c>;
+	};
+
+	gic: interrupt-controller@10211000 {
+		compatible = "arm,cortex-a7-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		reg = <0 0x10211000 0 0x1000>,
+		      <0 0x10212000 0 0x1000>,
+		      <0 0x10214000 0 0x2000>,
+		      <0 0x10216000 0 0x2000>;
+	};
+
+	uart0: serial@11002000 {
+		compatible = "mediatek,mt7623-uart",
+			     "mediatek,mt6577-uart";
+		reg = <0 0x11002000 0 0x400>;
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&uart_clk>;
+		status = "disabled";
+	};
+
+	uart1: serial@11003000 {
+		compatible = "mediatek,mt7623-uart",
+			     "mediatek,mt6577-uart";
+		reg = <0 0x11003000 0 0x400>;
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&uart_clk>;
+		status = "disabled";
+	};
+
+	uart2: serial@11004000 {
+		compatible = "mediatek,mt7623-uart",
+			     "mediatek,mt6577-uart";
+		reg = <0 0x11004000 0 0x400>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&uart_clk>;
+		status = "disabled";
+	};
+
+	uart3: serial@11005000 {
+		compatible = "mediatek,mt7623-uart",
+			     "mediatek,mt6577-uart";
+		reg = <0 0x11005000 0 0x400>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&uart_clk>;
+		status = "disabled";
+	};
+};
diff --git a/sys/gnu/dts/arm/mvebu-linkstation-fan.dtsi b/sys/gnu/dts/arm/mvebu-linkstation-fan.dtsi
new file mode 100644
index 000000000000..e211a3c47a76
--- /dev/null
+++ b/sys/gnu/dts/arm/mvebu-linkstation-fan.dtsi
@@ -0,0 +1,72 @@
+/*
+ * Device Tree common file for gpio-fan on Buffalo Linkstation
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+	gpio_fan {
+		compatible = "gpio-fan";
+		pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
+		pinctrl-names = "default";
+
+		gpio-fan,speed-map =
+			<0		3
+			1500	2
+			3250	1
+			5000	0>;
+	};
+};
+
+&pinctrl {
+	pmx_fan_low: pmx-fan-low {
+		marvell,function = "gpio";
+	};
+
+	pmx_fan_high: pmx-fan-high {
+		marvell,function = "gpio";
+	};
+
+	pmx_fan_lock: pmx-fan-lock {
+		marvell,function = "gpio";
+	};
+};
diff --git a/sys/gnu/dts/arm/mvebu-linkstation-gpio-simple.dtsi b/sys/gnu/dts/arm/mvebu-linkstation-gpio-simple.dtsi
new file mode 100644
index 000000000000..68d75e79a360
--- /dev/null
+++ b/sys/gnu/dts/arm/mvebu-linkstation-gpio-simple.dtsi
@@ -0,0 +1,105 @@
+/*
+ * Device Tree common file for gpio-{keys,leds} on Buffalo Linkstation
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_power_switch>;
+		pinctrl-names = "default";
+
+		power-on-switch {
+			label = "Power-on Switch";
+			linux,code = <KEY_RESERVED>;
+			linux,input-type = <5>;
+		};
+
+		power-auto-switch {
+			label = "Power-auto Switch";
+			linux,code = <KEY_ESC>;
+			linux,input-type = <5>;
+		};
+	};
+
+	gpio_leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info>;
+		pinctrl-names = "default";
+
+		blue-power-led {
+			label = "linkstation:blue:power";
+			default-state = "keep";
+		};
+
+		red-alarm-led {
+			label = "linkstation:red:alarm";
+		};
+
+		amber-info-led {
+			label = "linkstation:amber:info";
+		};
+	};
+};
+
+&pinctrl {
+	pmx_power_switch: pmx-power-switch {
+		marvell,function = "gpio";
+	};
+
+	pmx_led_power: pmx-leds {
+		marvell,function = "gpio";
+	};
+
+	pmx_led_alarm: pmx-leds {
+		marvell,function = "gpio";
+	};
+
+	pmx_led_info: pmx-leds {
+		marvell,function = "gpio";
+	};
+};
diff --git a/sys/gnu/dts/arm/omap2420-clocks.dtsi b/sys/gnu/dts/arm/omap2420-clocks.dtsi
index ce8c742d7e92..f8e5bd3cc628 100644
--- a/sys/gnu/dts/arm/omap2420-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap2420-clocks.dtsi
@@ -9,7 +9,7 @@
  */
 
 &prcm_clocks {
-	sys_clkout2_src_gate: sys_clkout2_src_gate {
+	sys_clkout2_src_gate: sys_clkout2_src_gate@70 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&core_ck>;
@@ -17,7 +17,7 @@
 		reg = <0x0070>;
 	};
 
-	sys_clkout2_src_mux: sys_clkout2_src_mux {
+	sys_clkout2_src_mux: sys_clkout2_src_mux@70 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
@@ -31,7 +31,7 @@
 		clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
 	};
 
-	sys_clkout2: sys_clkout2 {
+	sys_clkout2: sys_clkout2@70 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkout2_src>;
@@ -41,7 +41,7 @@
 		ti,index-power-of-two;
 	};
 
-	dsp_gate_ick: dsp_gate_ick {
+	dsp_gate_ick: dsp_gate_ick@810 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-interface-clock";
 		clocks = <&dsp_fck>;
@@ -49,7 +49,7 @@
 		reg = <0x0810>;
 	};
 
-	dsp_div_ick: dsp_div_ick {
+	dsp_div_ick: dsp_div_ick@840 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&dsp_fck>;
@@ -65,7 +65,7 @@
 		clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
 	};
 
-	iva1_gate_ifck: iva1_gate_ifck {
+	iva1_gate_ifck: iva1_gate_ifck@800 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&core_ck>;
@@ -73,7 +73,7 @@
 		reg = <0x0800>;
 	};
 
-	iva1_div_ifck: iva1_div_ifck {
+	iva1_div_ifck: iva1_div_ifck@840 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&core_ck>;
@@ -96,7 +96,7 @@
 		clock-div = <2>;
 	};
 
-	iva1_mpu_int_ifck: iva1_mpu_int_ifck {
+	iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&iva1_ifck_div>;
@@ -104,7 +104,7 @@
 		reg = <0x0800>;
 	};
 
-	wdt3_ick: wdt3_ick {
+	wdt3_ick: wdt3_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -112,7 +112,7 @@
 		reg = <0x0210>;
 	};
 
-	wdt3_fck: wdt3_fck {
+	wdt3_fck: wdt3_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -120,7 +120,7 @@
 		reg = <0x0200>;
 	};
 
-	mmc_ick: mmc_ick {
+	mmc_ick: mmc_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -128,7 +128,7 @@
 		reg = <0x0210>;
 	};
 
-	mmc_fck: mmc_fck {
+	mmc_fck: mmc_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_96m_ck>;
@@ -136,7 +136,7 @@
 		reg = <0x0200>;
 	};
 
-	eac_ick: eac_ick {
+	eac_ick: eac_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -144,7 +144,7 @@
 		reg = <0x0210>;
 	};
 
-	eac_fck: eac_fck {
+	eac_fck: eac_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_96m_ck>;
@@ -152,7 +152,7 @@
 		reg = <0x0200>;
 	};
 
-	i2c1_fck: i2c1_fck {
+	i2c1_fck: i2c1_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_12m_ck>;
@@ -160,7 +160,7 @@
 		reg = <0x0200>;
 	};
 
-	i2c2_fck: i2c2_fck {
+	i2c2_fck: i2c2_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_12m_ck>;
@@ -168,7 +168,7 @@
 		reg = <0x0200>;
 	};
 
-	vlynq_ick: vlynq_ick {
+	vlynq_ick: vlynq_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l3_ck>;
@@ -176,7 +176,7 @@
 		reg = <0x0210>;
 	};
 
-	vlynq_gate_fck: vlynq_gate_fck {
+	vlynq_gate_fck: vlynq_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&core_ck>;
@@ -192,7 +192,7 @@
 		clock-div = <18>;
 	};
 
-	vlynq_mux_fck: vlynq_mux_fck {
+	vlynq_mux_fck: vlynq_mux_fck@240 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
diff --git a/sys/gnu/dts/arm/omap2420-n8x0-common.dtsi b/sys/gnu/dts/arm/omap2420-n8x0-common.dtsi
index 8491f46c61b7..db95aadcca70 100644
--- a/sys/gnu/dts/arm/omap2420-n8x0-common.dtsi
+++ b/sys/gnu/dts/arm/omap2420-n8x0-common.dtsi
@@ -7,7 +7,7 @@
 	};
 
 	ocp {
-		i2c@0 {
+		i2c0 {
 			compatible = "i2c-cbus-gpio";
 			gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */
 				 &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */
diff --git a/sys/gnu/dts/arm/omap2420.dtsi b/sys/gnu/dts/arm/omap2420.dtsi
index 5b9a376cc31e..fb712b9aa874 100644
--- a/sys/gnu/dts/arm/omap2420.dtsi
+++ b/sys/gnu/dts/arm/omap2420.dtsi
@@ -130,6 +130,10 @@
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 		};
 
 		mcbsp1: mcbsp@48074000 {
diff --git a/sys/gnu/dts/arm/omap2430-clocks.dtsi b/sys/gnu/dts/arm/omap2430-clocks.dtsi
index 93fed68839b9..a5aa7d619849 100644
--- a/sys/gnu/dts/arm/omap2430-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap2430-clocks.dtsi
@@ -9,7 +9,7 @@
  */
 
 &scm_clocks {
-	mcbsp3_mux_fck: mcbsp3_mux_fck {
+	mcbsp3_mux_fck: mcbsp3_mux_fck@78 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_96m_ck>, <&mcbsp_clks>;
@@ -22,7 +22,7 @@
 		clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
 	};
 
-	mcbsp4_mux_fck: mcbsp4_mux_fck {
+	mcbsp4_mux_fck: mcbsp4_mux_fck@78 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_96m_ck>, <&mcbsp_clks>;
@@ -36,7 +36,7 @@
 		clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
 	};
 
-	mcbsp5_mux_fck: mcbsp5_mux_fck {
+	mcbsp5_mux_fck: mcbsp5_mux_fck@78 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_96m_ck>, <&mcbsp_clks>;
@@ -52,7 +52,7 @@
 };
 
 &prcm_clocks {
-	iva2_1_gate_ick: iva2_1_gate_ick {
+	iva2_1_gate_ick: iva2_1_gate_ick@800 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&dsp_fck>;
@@ -60,7 +60,7 @@
 		reg = <0x0800>;
 	};
 
-	iva2_1_div_ick: iva2_1_div_ick {
+	iva2_1_div_ick: iva2_1_div_ick@840 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&dsp_fck>;
@@ -76,7 +76,7 @@
 		clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
 	};
 
-	mdm_gate_ick: mdm_gate_ick {
+	mdm_gate_ick: mdm_gate_ick@c10 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-interface-clock";
 		clocks = <&core_ck>;
@@ -84,7 +84,7 @@
 		reg = <0x0c10>;
 	};
 
-	mdm_div_ick: mdm_div_ick {
+	mdm_div_ick: mdm_div_ick@c40 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&core_ck>;
@@ -98,7 +98,7 @@
 		clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
 	};
 
-	mdm_osc_ck: mdm_osc_ck {
+	mdm_osc_ck: mdm_osc_ck@c00 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&osc_ck>;
@@ -106,7 +106,7 @@
 		reg = <0x0c00>;
 	};
 
-	mcbsp3_ick: mcbsp3_ick {
+	mcbsp3_ick: mcbsp3_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -114,7 +114,7 @@
 		reg = <0x0214>;
 	};
 
-	mcbsp3_gate_fck: mcbsp3_gate_fck {
+	mcbsp3_gate_fck: mcbsp3_gate_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -122,7 +122,7 @@
 		reg = <0x0204>;
 	};
 
-	mcbsp4_ick: mcbsp4_ick {
+	mcbsp4_ick: mcbsp4_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -130,7 +130,7 @@
 		reg = <0x0214>;
 	};
 
-	mcbsp4_gate_fck: mcbsp4_gate_fck {
+	mcbsp4_gate_fck: mcbsp4_gate_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -138,7 +138,7 @@
 		reg = <0x0204>;
 	};
 
-	mcbsp5_ick: mcbsp5_ick {
+	mcbsp5_ick: mcbsp5_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -146,7 +146,7 @@
 		reg = <0x0214>;
 	};
 
-	mcbsp5_gate_fck: mcbsp5_gate_fck {
+	mcbsp5_gate_fck: mcbsp5_gate_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -154,7 +154,7 @@
 		reg = <0x0204>;
 	};
 
-	mcspi3_ick: mcspi3_ick {
+	mcspi3_ick: mcspi3_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -162,7 +162,7 @@
 		reg = <0x0214>;
 	};
 
-	mcspi3_fck: mcspi3_fck {
+	mcspi3_fck: mcspi3_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_48m_ck>;
@@ -170,7 +170,7 @@
 		reg = <0x0204>;
 	};
 
-	icr_ick: icr_ick {
+	icr_ick: icr_ick@410 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&sys_ck>;
@@ -178,7 +178,7 @@
 		reg = <0x0410>;
 	};
 
-	i2chs1_fck: i2chs1_fck {
+	i2chs1_fck: i2chs1_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,omap2430-interface-clock";
 		clocks = <&func_96m_ck>;
@@ -186,7 +186,7 @@
 		reg = <0x0204>;
 	};
 
-	i2chs2_fck: i2chs2_fck {
+	i2chs2_fck: i2chs2_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,omap2430-interface-clock";
 		clocks = <&func_96m_ck>;
@@ -194,7 +194,7 @@
 		reg = <0x0204>;
 	};
 
-	usbhs_ick: usbhs_ick {
+	usbhs_ick: usbhs_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l3_ck>;
@@ -202,7 +202,7 @@
 		reg = <0x0214>;
 	};
 
-	mmchs1_ick: mmchs1_ick {
+	mmchs1_ick: mmchs1_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -210,7 +210,7 @@
 		reg = <0x0214>;
 	};
 
-	mmchs1_fck: mmchs1_fck {
+	mmchs1_fck: mmchs1_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_96m_ck>;
@@ -218,7 +218,7 @@
 		reg = <0x0204>;
 	};
 
-	mmchs2_ick: mmchs2_ick {
+	mmchs2_ick: mmchs2_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -226,7 +226,7 @@
 		reg = <0x0214>;
 	};
 
-	mmchs2_fck: mmchs2_fck {
+	mmchs2_fck: mmchs2_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_96m_ck>;
@@ -234,7 +234,7 @@
 		reg = <0x0204>;
 	};
 
-	gpio5_ick: gpio5_ick {
+	gpio5_ick: gpio5_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -242,7 +242,7 @@
 		reg = <0x0214>;
 	};
 
-	gpio5_fck: gpio5_fck {
+	gpio5_fck: gpio5_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -250,7 +250,7 @@
 		reg = <0x0204>;
 	};
 
-	mdm_intc_ick: mdm_intc_ick {
+	mdm_intc_ick: mdm_intc_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -258,7 +258,7 @@
 		reg = <0x0214>;
 	};
 
-	mmchsdb1_fck: mmchsdb1_fck {
+	mmchsdb1_fck: mmchsdb1_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -266,7 +266,7 @@
 		reg = <0x0204>;
 	};
 
-	mmchsdb2_fck: mmchsdb2_fck {
+	mmchsdb2_fck: mmchsdb2_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_32k_ck>;
diff --git a/sys/gnu/dts/arm/omap2430.dtsi b/sys/gnu/dts/arm/omap2430.dtsi
index 798dda072b2a..455aaea407dd 100644
--- a/sys/gnu/dts/arm/omap2430.dtsi
+++ b/sys/gnu/dts/arm/omap2430.dtsi
@@ -63,7 +63,7 @@
 						#size-cells = <0>;
 					};
 
-					pbias_regulator: pbias_regulator {
+					pbias_regulator: pbias_regulator@230 {
 						compatible = "ti,pbias-omap2", "ti,pbias-omap";
 						reg = <0x230 0x4>;
 						syscon = <&scm_conf>;
@@ -154,6 +154,10 @@
 			gpmc,num-cs = <8>;
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 		};
 
 		mcbsp1: mcbsp@48074000 {
diff --git a/sys/gnu/dts/arm/omap24xx-clocks.dtsi b/sys/gnu/dts/arm/omap24xx-clocks.dtsi
index 63965b876973..ca73722b5ea4 100644
--- a/sys/gnu/dts/arm/omap24xx-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap24xx-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &scm_clocks {
-	mcbsp1_mux_fck: mcbsp1_mux_fck {
+	mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_96m_ck>, <&mcbsp_clks>;
@@ -22,7 +22,7 @@
 		clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
 	};
 
-	mcbsp2_mux_fck: mcbsp2_mux_fck {
+	mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_96m_ck>, <&mcbsp_clks>;
@@ -74,7 +74,7 @@
 		clock-frequency = <26000000>;
 	};
 
-	aplls_clkin_ck: aplls_clkin_ck {
+	aplls_clkin_ck: aplls_clkin_ck@540 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
@@ -90,7 +90,7 @@
 		clock-div = <1>;
 	};
 
-	osc_ck: osc_ck {
+	osc_ck: osc_ck@60 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
@@ -99,7 +99,7 @@
 		ti,index-starts-at-one;
 	};
 
-	sys_ck: sys_ck {
+	sys_ck: sys_ck@60 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&osc_ck>;
@@ -121,14 +121,14 @@
 		clock-frequency = <0x0>;
 	};
 
-	dpll_ck: dpll_ck {
+	dpll_ck: dpll_ck@500 {
 		#clock-cells = <0>;
 		compatible = "ti,omap2-dpll-core-clock";
 		clocks = <&sys_ck>, <&sys_ck>;
 		reg = <0x0500>, <0x0540>;
 	};
 
-	apll96_ck: apll96_ck {
+	apll96_ck: apll96_ck@500 {
 		#clock-cells = <0>;
 		compatible = "ti,omap2-apll-clock";
 		clocks = <&sys_ck>;
@@ -138,7 +138,7 @@
 		reg = <0x0500>, <0x0530>, <0x0520>;
 	};
 
-	apll54_ck: apll54_ck {
+	apll54_ck: apll54_ck@500 {
 		#clock-cells = <0>;
 		compatible = "ti,omap2-apll-clock";
 		clocks = <&sys_ck>;
@@ -148,7 +148,7 @@
 		reg = <0x0500>, <0x0530>, <0x0520>;
 	};
 
-	func_54m_ck: func_54m_ck {
+	func_54m_ck: func_54m_ck@540 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&apll54_ck>, <&alt_ck>;
@@ -176,7 +176,7 @@
 		clock-div = <2>;
 	};
 
-	func_48m_ck: func_48m_ck {
+	func_48m_ck: func_48m_ck@540 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&apll96_d2_ck>, <&alt_ck>;
@@ -192,7 +192,7 @@
 		clock-div = <4>;
 	};
 
-	sys_clkout_src_gate: sys_clkout_src_gate {
+	sys_clkout_src_gate: sys_clkout_src_gate@70 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&core_ck>;
@@ -200,7 +200,7 @@
 		reg = <0x0070>;
 	};
 
-	sys_clkout_src_mux: sys_clkout_src_mux {
+	sys_clkout_src_mux: sys_clkout_src_mux@70 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
@@ -213,7 +213,7 @@
 		clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
 	};
 
-	sys_clkout: sys_clkout {
+	sys_clkout: sys_clkout@70 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkout_src>;
@@ -223,7 +223,7 @@
 		ti,index-power-of-two;
 	};
 
-	emul_ck: emul_ck {
+	emul_ck: emul_ck@78 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_54m_ck>;
@@ -231,7 +231,7 @@
 		reg = <0x0078>;
 	};
 
-	mpu_ck: mpu_ck {
+	mpu_ck: mpu_ck@140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&core_ck>;
@@ -240,7 +240,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dsp_gate_fck: dsp_gate_fck {
+	dsp_gate_fck: dsp_gate_fck@800 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&core_ck>;
@@ -248,7 +248,7 @@
 		reg = <0x0800>;
 	};
 
-	dsp_div_fck: dsp_div_fck {
+	dsp_div_fck: dsp_div_fck@840 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&core_ck>;
@@ -261,7 +261,7 @@
 		clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
 	};
 
-	core_l3_ck: core_l3_ck {
+	core_l3_ck: core_l3_ck@240 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&core_ck>;
@@ -270,7 +270,7 @@
 		ti,index-starts-at-one;
 	};
 
-	gfx_3d_gate_fck: gfx_3d_gate_fck {
+	gfx_3d_gate_fck: gfx_3d_gate_fck@300 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&core_l3_ck>;
@@ -278,7 +278,7 @@
 		reg = <0x0300>;
 	};
 
-	gfx_3d_div_fck: gfx_3d_div_fck {
+	gfx_3d_div_fck: gfx_3d_div_fck@340 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&core_l3_ck>;
@@ -293,7 +293,7 @@
 		clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
 	};
 
-	gfx_2d_gate_fck: gfx_2d_gate_fck {
+	gfx_2d_gate_fck: gfx_2d_gate_fck@300 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&core_l3_ck>;
@@ -301,7 +301,7 @@
 		reg = <0x0300>;
 	};
 
-	gfx_2d_div_fck: gfx_2d_div_fck {
+	gfx_2d_div_fck: gfx_2d_div_fck@340 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&core_l3_ck>;
@@ -316,7 +316,7 @@
 		clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
 	};
 
-	gfx_ick: gfx_ick {
+	gfx_ick: gfx_ick@310 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_l3_ck>;
@@ -324,7 +324,7 @@
 		reg = <0x0310>;
 	};
 
-	l4_ck: l4_ck {
+	l4_ck: l4_ck@240 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&core_l3_ck>;
@@ -334,7 +334,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dss_ick: dss_ick {
+	dss_ick: dss_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-no-wait-interface-clock";
 		clocks = <&l4_ck>;
@@ -342,7 +342,7 @@
 		reg = <0x0210>;
 	};
 
-	dss1_gate_fck: dss1_gate_fck {
+	dss1_gate_fck: dss1_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&core_ck>;
@@ -428,7 +428,7 @@
 		clock-div = <16>;
 	};
 
-	dss1_mux_fck: dss1_mux_fck {
+	dss1_mux_fck: dss1_mux_fck@240 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
@@ -442,7 +442,7 @@
 		clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
 	};
 
-	dss2_gate_fck: dss2_gate_fck {
+	dss2_gate_fck: dss2_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&func_48m_ck>;
@@ -450,7 +450,7 @@
 		reg = <0x0200>;
 	};
 
-	dss2_mux_fck: dss2_mux_fck {
+	dss2_mux_fck: dss2_mux_fck@240 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_ck>, <&func_48m_ck>;
@@ -464,7 +464,7 @@
 		clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
 	};
 
-	dss_54m_fck: dss_54m_fck {
+	dss_54m_fck: dss_54m_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_54m_ck>;
@@ -472,7 +472,7 @@
 		reg = <0x0200>;
 	};
 
-	ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck {
+	ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&core_ck>;
@@ -480,7 +480,7 @@
 		reg = <0x0204>;
 	};
 
-	ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck {
+	ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&core_ck>;
@@ -494,7 +494,7 @@
 		clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
 	};
 
-	usb_l4_gate_ick: usb_l4_gate_ick {
+	usb_l4_gate_ick: usb_l4_gate_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-interface-clock";
 		clocks = <&core_l3_ck>;
@@ -502,7 +502,7 @@
 		reg = <0x0214>;
 	};
 
-	usb_l4_div_ick: usb_l4_div_ick {
+	usb_l4_div_ick: usb_l4_div_ick@240 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&core_l3_ck>;
@@ -517,7 +517,7 @@
 		clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
 	};
 
-	ssi_l4_ick: ssi_l4_ick {
+	ssi_l4_ick: ssi_l4_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -525,7 +525,7 @@
 		reg = <0x0214>;
 	};
 
-	gpt1_ick: gpt1_ick {
+	gpt1_ick: gpt1_ick@410 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&sys_ck>;
@@ -533,7 +533,7 @@
 		reg = <0x0410>;
 	};
 
-	gpt1_gate_fck: gpt1_gate_fck {
+	gpt1_gate_fck: gpt1_gate_fck@400 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -541,7 +541,7 @@
 		reg = <0x0400>;
 	};
 
-	gpt1_mux_fck: gpt1_mux_fck {
+	gpt1_mux_fck: gpt1_mux_fck@440 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -554,7 +554,7 @@
 		clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
 	};
 
-	gpt2_ick: gpt2_ick {
+	gpt2_ick: gpt2_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -562,7 +562,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt2_gate_fck: gpt2_gate_fck {
+	gpt2_gate_fck: gpt2_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -570,7 +570,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt2_mux_fck: gpt2_mux_fck {
+	gpt2_mux_fck: gpt2_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -584,7 +584,7 @@
 		clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
 	};
 
-	gpt3_ick: gpt3_ick {
+	gpt3_ick: gpt3_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -592,7 +592,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt3_gate_fck: gpt3_gate_fck {
+	gpt3_gate_fck: gpt3_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -600,7 +600,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt3_mux_fck: gpt3_mux_fck {
+	gpt3_mux_fck: gpt3_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -614,7 +614,7 @@
 		clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
 	};
 
-	gpt4_ick: gpt4_ick {
+	gpt4_ick: gpt4_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -622,7 +622,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt4_gate_fck: gpt4_gate_fck {
+	gpt4_gate_fck: gpt4_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -630,7 +630,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt4_mux_fck: gpt4_mux_fck {
+	gpt4_mux_fck: gpt4_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -644,7 +644,7 @@
 		clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
 	};
 
-	gpt5_ick: gpt5_ick {
+	gpt5_ick: gpt5_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -652,7 +652,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt5_gate_fck: gpt5_gate_fck {
+	gpt5_gate_fck: gpt5_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -660,7 +660,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt5_mux_fck: gpt5_mux_fck {
+	gpt5_mux_fck: gpt5_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -674,7 +674,7 @@
 		clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
 	};
 
-	gpt6_ick: gpt6_ick {
+	gpt6_ick: gpt6_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -682,7 +682,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt6_gate_fck: gpt6_gate_fck {
+	gpt6_gate_fck: gpt6_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -690,7 +690,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt6_mux_fck: gpt6_mux_fck {
+	gpt6_mux_fck: gpt6_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -704,7 +704,7 @@
 		clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
 	};
 
-	gpt7_ick: gpt7_ick {
+	gpt7_ick: gpt7_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -712,7 +712,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt7_gate_fck: gpt7_gate_fck {
+	gpt7_gate_fck: gpt7_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -720,7 +720,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt7_mux_fck: gpt7_mux_fck {
+	gpt7_mux_fck: gpt7_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -734,7 +734,7 @@
 		clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
 	};
 
-	gpt8_ick: gpt8_ick {
+	gpt8_ick: gpt8_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -742,7 +742,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt8_gate_fck: gpt8_gate_fck {
+	gpt8_gate_fck: gpt8_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -750,7 +750,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt8_mux_fck: gpt8_mux_fck {
+	gpt8_mux_fck: gpt8_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -764,7 +764,7 @@
 		clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
 	};
 
-	gpt9_ick: gpt9_ick {
+	gpt9_ick: gpt9_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -772,7 +772,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt9_gate_fck: gpt9_gate_fck {
+	gpt9_gate_fck: gpt9_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -780,7 +780,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt9_mux_fck: gpt9_mux_fck {
+	gpt9_mux_fck: gpt9_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -794,7 +794,7 @@
 		clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
 	};
 
-	gpt10_ick: gpt10_ick {
+	gpt10_ick: gpt10_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -802,7 +802,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt10_gate_fck: gpt10_gate_fck {
+	gpt10_gate_fck: gpt10_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -810,7 +810,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt10_mux_fck: gpt10_mux_fck {
+	gpt10_mux_fck: gpt10_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -824,7 +824,7 @@
 		clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
 	};
 
-	gpt11_ick: gpt11_ick {
+	gpt11_ick: gpt11_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -832,7 +832,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt11_gate_fck: gpt11_gate_fck {
+	gpt11_gate_fck: gpt11_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -840,7 +840,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt11_mux_fck: gpt11_mux_fck {
+	gpt11_mux_fck: gpt11_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -854,7 +854,7 @@
 		clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
 	};
 
-	gpt12_ick: gpt12_ick {
+	gpt12_ick: gpt12_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -862,7 +862,7 @@
 		reg = <0x0210>;
 	};
 
-	gpt12_gate_fck: gpt12_gate_fck {
+	gpt12_gate_fck: gpt12_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -870,7 +870,7 @@
 		reg = <0x0200>;
 	};
 
-	gpt12_mux_fck: gpt12_mux_fck {
+	gpt12_mux_fck: gpt12_mux_fck@244 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
@@ -884,7 +884,7 @@
 		clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
 	};
 
-	mcbsp1_ick: mcbsp1_ick {
+	mcbsp1_ick: mcbsp1_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -892,7 +892,7 @@
 		reg = <0x0210>;
 	};
 
-	mcbsp1_gate_fck: mcbsp1_gate_fck {
+	mcbsp1_gate_fck: mcbsp1_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -900,7 +900,7 @@
 		reg = <0x0200>;
 	};
 
-	mcbsp2_ick: mcbsp2_ick {
+	mcbsp2_ick: mcbsp2_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -908,7 +908,7 @@
 		reg = <0x0210>;
 	};
 
-	mcbsp2_gate_fck: mcbsp2_gate_fck {
+	mcbsp2_gate_fck: mcbsp2_gate_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -916,7 +916,7 @@
 		reg = <0x0200>;
 	};
 
-	mcspi1_ick: mcspi1_ick {
+	mcspi1_ick: mcspi1_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -924,7 +924,7 @@
 		reg = <0x0210>;
 	};
 
-	mcspi1_fck: mcspi1_fck {
+	mcspi1_fck: mcspi1_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_48m_ck>;
@@ -932,7 +932,7 @@
 		reg = <0x0200>;
 	};
 
-	mcspi2_ick: mcspi2_ick {
+	mcspi2_ick: mcspi2_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -940,7 +940,7 @@
 		reg = <0x0210>;
 	};
 
-	mcspi2_fck: mcspi2_fck {
+	mcspi2_fck: mcspi2_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_48m_ck>;
@@ -948,7 +948,7 @@
 		reg = <0x0200>;
 	};
 
-	uart1_ick: uart1_ick {
+	uart1_ick: uart1_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -956,7 +956,7 @@
 		reg = <0x0210>;
 	};
 
-	uart1_fck: uart1_fck {
+	uart1_fck: uart1_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_48m_ck>;
@@ -964,7 +964,7 @@
 		reg = <0x0200>;
 	};
 
-	uart2_ick: uart2_ick {
+	uart2_ick: uart2_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -972,7 +972,7 @@
 		reg = <0x0210>;
 	};
 
-	uart2_fck: uart2_fck {
+	uart2_fck: uart2_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_48m_ck>;
@@ -980,7 +980,7 @@
 		reg = <0x0200>;
 	};
 
-	uart3_ick: uart3_ick {
+	uart3_ick: uart3_ick@214 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -988,7 +988,7 @@
 		reg = <0x0214>;
 	};
 
-	uart3_fck: uart3_fck {
+	uart3_fck: uart3_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_48m_ck>;
@@ -996,7 +996,7 @@
 		reg = <0x0204>;
 	};
 
-	gpios_ick: gpios_ick {
+	gpios_ick: gpios_ick@410 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&sys_ck>;
@@ -1004,7 +1004,7 @@
 		reg = <0x0410>;
 	};
 
-	gpios_fck: gpios_fck {
+	gpios_fck: gpios_fck@400 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -1012,7 +1012,7 @@
 		reg = <0x0400>;
 	};
 
-	mpu_wdt_ick: mpu_wdt_ick {
+	mpu_wdt_ick: mpu_wdt_ick@410 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&sys_ck>;
@@ -1020,7 +1020,7 @@
 		reg = <0x0410>;
 	};
 
-	mpu_wdt_fck: mpu_wdt_fck {
+	mpu_wdt_fck: mpu_wdt_fck@400 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -1028,7 +1028,7 @@
 		reg = <0x0400>;
 	};
 
-	sync_32k_ick: sync_32k_ick {
+	sync_32k_ick: sync_32k_ick@410 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&sys_ck>;
@@ -1036,7 +1036,7 @@
 		reg = <0x0410>;
 	};
 
-	wdt1_ick: wdt1_ick {
+	wdt1_ick: wdt1_ick@410 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&sys_ck>;
@@ -1044,7 +1044,7 @@
 		reg = <0x0410>;
 	};
 
-	omapctrl_ick: omapctrl_ick {
+	omapctrl_ick: omapctrl_ick@410 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&sys_ck>;
@@ -1052,7 +1052,7 @@
 		reg = <0x0410>;
 	};
 
-	cam_fck: cam_fck {
+	cam_fck: cam_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_96m_ck>;
@@ -1060,7 +1060,7 @@
 		reg = <0x0200>;
 	};
 
-	cam_ick: cam_ick {
+	cam_ick: cam_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-no-wait-interface-clock";
 		clocks = <&l4_ck>;
@@ -1068,7 +1068,7 @@
 		reg = <0x0210>;
 	};
 
-	mailboxes_ick: mailboxes_ick {
+	mailboxes_ick: mailboxes_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1076,7 +1076,7 @@
 		reg = <0x0210>;
 	};
 
-	wdt4_ick: wdt4_ick {
+	wdt4_ick: wdt4_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1084,7 +1084,7 @@
 		reg = <0x0210>;
 	};
 
-	wdt4_fck: wdt4_fck {
+	wdt4_fck: wdt4_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_32k_ck>;
@@ -1092,7 +1092,7 @@
 		reg = <0x0200>;
 	};
 
-	mspro_ick: mspro_ick {
+	mspro_ick: mspro_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1100,7 +1100,7 @@
 		reg = <0x0210>;
 	};
 
-	mspro_fck: mspro_fck {
+	mspro_fck: mspro_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_96m_ck>;
@@ -1108,7 +1108,7 @@
 		reg = <0x0200>;
 	};
 
-	fac_ick: fac_ick {
+	fac_ick: fac_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1116,7 +1116,7 @@
 		reg = <0x0210>;
 	};
 
-	fac_fck: fac_fck {
+	fac_fck: fac_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_12m_ck>;
@@ -1124,7 +1124,7 @@
 		reg = <0x0200>;
 	};
 
-	hdq_ick: hdq_ick {
+	hdq_ick: hdq_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1132,7 +1132,7 @@
 		reg = <0x0210>;
 	};
 
-	hdq_fck: hdq_fck {
+	hdq_fck: hdq_fck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_12m_ck>;
@@ -1140,7 +1140,7 @@
 		reg = <0x0200>;
 	};
 
-	i2c1_ick: i2c1_ick {
+	i2c1_ick: i2c1_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1148,7 +1148,7 @@
 		reg = <0x0210>;
 	};
 
-	i2c2_ick: i2c2_ick {
+	i2c2_ick: i2c2_ick@210 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1156,7 +1156,7 @@
 		reg = <0x0210>;
 	};
 
-	gpmc_fck: gpmc_fck {
+	gpmc_fck: gpmc_fck@238 {
 		#clock-cells = <0>;
 		compatible = "ti,fixed-factor-clock";
 		clocks = <&core_l3_ck>;
@@ -1174,7 +1174,7 @@
 		clock-div = <1>;
 	};
 
-	sdma_ick: sdma_ick {
+	sdma_ick: sdma_ick@238 {
 		#clock-cells = <0>;
 		compatible = "ti,fixed-factor-clock";
 		clocks = <&core_l3_ck>;
@@ -1184,7 +1184,7 @@
 		ti,clock-mult = <1>;
 	};
 
-	sdrc_ick: sdrc_ick {
+	sdrc_ick: sdrc_ick@238 {
 		#clock-cells = <0>;
 		compatible = "ti,fixed-factor-clock";
 		clocks = <&core_l3_ck>;
@@ -1194,7 +1194,7 @@
 		ti,clock-mult = <1>;
 	};
 
-	des_ick: des_ick {
+	des_ick: des_ick@21c {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1202,7 +1202,7 @@
 		reg = <0x021c>;
 	};
 
-	sha_ick: sha_ick {
+	sha_ick: sha_ick@21c {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1210,7 +1210,7 @@
 		reg = <0x021c>;
 	};
 
-	rng_ick: rng_ick {
+	rng_ick: rng_ick@21c {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1218,7 +1218,7 @@
 		reg = <0x021c>;
 	};
 
-	aes_ick: aes_ick {
+	aes_ick: aes_ick@21c {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1226,7 +1226,7 @@
 		reg = <0x021c>;
 	};
 
-	pka_ick: pka_ick {
+	pka_ick: pka_ick@21c {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l4_ck>;
@@ -1234,7 +1234,7 @@
 		reg = <0x021c>;
 	};
 
-	usb_fck: usb_fck {
+	usb_fck: usb_fck@204 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&func_48m_ck>;
diff --git a/sys/gnu/dts/arm/omap3-beagle.dts b/sys/gnu/dts/arm/omap3-beagle.dts
index 8ba465d57635..a4deff0e2d52 100644
--- a/sys/gnu/dts/arm/omap3-beagle.dts
+++ b/sys/gnu/dts/arm/omap3-beagle.dts
@@ -384,9 +384,13 @@
 
 	/* Chip select 0 */
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>;		/* NAND I/O window, 4 bytes */
-		interrupts = <20>;
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		ti,nand-ecc-opt = "ham1";
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 		nand-bus-width = <16>;
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/sys/gnu/dts/arm/omap3-cm-t3x.dtsi b/sys/gnu/dts/arm/omap3-cm-t3x.dtsi
index e5f7f5c92c1a..a8127bc31fd9 100644
--- a/sys/gnu/dts/arm/omap3-cm-t3x.dtsi
+++ b/sys/gnu/dts/arm/omap3-cm-t3x.dtsi
@@ -261,10 +261,14 @@
 };
 
 &gpmc {
-	ranges = <0 0 0x00000000 0x01000000>;
+	ranges = <0 0 0x30000000 0x01000000>;	/* CS0: 16MB for NAND */
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		nand-bus-width = <8>;
 		gpmc,device-width = <1>;
 		ti,nand-ecc-opt = "sw";
diff --git a/sys/gnu/dts/arm/omap3-devkit8000-common.dtsi b/sys/gnu/dts/arm/omap3-devkit8000-common.dtsi
index 86850bb311eb..b1b8ebf90c1c 100644
--- a/sys/gnu/dts/arm/omap3-devkit8000-common.dtsi
+++ b/sys/gnu/dts/arm/omap3-devkit8000-common.dtsi
@@ -204,7 +204,11 @@
 	ranges = <0 0 0x30000000 0x1000000>;       /* CS0: 16MB for NAND */
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;
 		ti,nand-ecc-opt = "sw";
diff --git a/sys/gnu/dts/arm/omap3-evm-37xx.dts b/sys/gnu/dts/arm/omap3-evm-37xx.dts
index ac188657a95d..ed449827c3d3 100644
--- a/sys/gnu/dts/arm/omap3-evm-37xx.dts
+++ b/sys/gnu/dts/arm/omap3-evm-37xx.dts
@@ -85,7 +85,7 @@
 			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_clk.sdmmc2_clk */
 			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_cmd.sdmmc2_cmd */
 			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat0.sdmmc2_dat0 */
-			OMAP3_CORE1_IOPAD(0x215e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
+			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
 			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat2.sdmmc2_dat2 */
 			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat3.sdmmc2_dat3 */
 		>;
@@ -154,12 +154,16 @@
 };
 
 &gpmc {
-	ranges = <0 0 0x00000000 0x1000000>,	/* CS0: 16MB for NAND */
+	ranges = <0 0 0x30000000 0x1000000>,	/* CS0: 16MB for NAND */
 		 <5 0 0x2c000000 0x01000000>;
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		linux,mtd-name= "hynix,h8kds0un0mer-4em";
-		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;
 		ti,nand-ecc-opt = "bch8";
diff --git a/sys/gnu/dts/arm/omap3-gta04.dtsi b/sys/gnu/dts/arm/omap3-gta04.dtsi
index 5e2d6433d939..ab9fb8f49ff3 100644
--- a/sys/gnu/dts/arm/omap3-gta04.dtsi
+++ b/sys/gnu/dts/arm/omap3-gta04.dtsi
@@ -492,7 +492,11 @@
 	ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		nand-bus-width = <16>;
 		ti,nand-ecc-opt = "bch8";
 
diff --git a/sys/gnu/dts/arm/omap3-igep.dtsi b/sys/gnu/dts/arm/omap3-igep.dtsi
index 3caf062f882c..f4f2ce46d681 100644
--- a/sys/gnu/dts/arm/omap3-igep.dtsi
+++ b/sys/gnu/dts/arm/omap3-igep.dtsi
@@ -18,6 +18,10 @@
 		reg = <0x80000000 0x20000000>; /* 512 MB */
 	};
 
+	chosen {
+		stdout-path = &uart3;
+	};
+
 	sound {
 		compatible = "ti,omap-twl4030";
 		ti,model = "igep2";
@@ -95,8 +99,12 @@
 
 &gpmc {
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		linux,mtd-name= "micron,mt29c4g96maz";
-		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;
 		ti,nand-ecc-opt = "bch8";
@@ -180,6 +188,7 @@
 	vmmc-supply = <&vmmc1>;
 	vmmc_aux-supply = <&vsim>;
 	bus-width = <4>;
+	cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
 };
 
 &mmc3 {
diff --git a/sys/gnu/dts/arm/omap3-igep0020-common.dtsi b/sys/gnu/dts/arm/omap3-igep0020-common.dtsi
index d90f12c39307..b6971060648a 100644
--- a/sys/gnu/dts/arm/omap3-igep0020-common.dtsi
+++ b/sys/gnu/dts/arm/omap3-igep0020-common.dtsi
@@ -194,6 +194,12 @@
 			OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
 		>;
 	};
+
+	mmc1_wp_pins: pinmux_mmc1_cd_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4)   /* etk_d15.gpio_29 */
+		>;
+	};
 };
 
 &i2c3 {
@@ -210,8 +216,8 @@
 };
 
 &gpmc {
-	ranges = <0 0 0x00000000 0x20000000>,
-		 <5 0 0x2c000000 0x01000000>;
+	ranges = <0 0 0x30000000 0x01000000>,	/* CS0: 16MB for NAND */
+		 <5 0 0x2c000000 0x01000000>;	/* CS5: 16MB for ethernet */
 
 	ethernet@gpmc {
 		pinctrl-names = "default";
@@ -250,3 +256,8 @@
 		};
 	};
 };
+
+&mmc1 {
+	pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
+	wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;	/* gpio_29 */
+};
diff --git a/sys/gnu/dts/arm/omap3-igep0030-common.dtsi b/sys/gnu/dts/arm/omap3-igep0030-common.dtsi
index 640f06603966..e94d9427450c 100644
--- a/sys/gnu/dts/arm/omap3-igep0030-common.dtsi
+++ b/sys/gnu/dts/arm/omap3-igep0030-common.dtsi
@@ -33,9 +33,28 @@
 			 default-state = "off";
 		};
 	};
+
+	hsusb2_phy: hsusb2_phy {
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;		/* gpio_54 */
+	};
 };
 
 &omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_pins>;
+
+	hsusb2_pins: pinmux_hsusb2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
+			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
+			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
+			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
+		>;
+	};
+
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */
@@ -47,6 +66,20 @@
 };
 
 &omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_core2_pins>;
+
+	hsusb2_core2_pins: pinmux_hsusb2_core2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		      /* etk_d10.hsusb2_clk */
+			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		      /* etk_d11.hsusb2_stp */
+			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
+			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
+			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
+			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
+		>;
+	};
+
 	leds_core2_pins: pinmux_leds_core2_pins {
 		pinctrl-single,pins = <
 			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)	/* etk_d2.gpio_16 */
@@ -54,7 +87,19 @@
 	};
 };
 
+&usbhshost {
+	port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+	phys = <0 &hsusb2_phy>;
+};
+
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart2_pins>;
 };
+
+&gpmc {
+	ranges = <0 0 0x30000000 0x01000000>;   /* CS0: 16MB for NAND */
+};
diff --git a/sys/gnu/dts/arm/omap3-ldp.dts b/sys/gnu/dts/arm/omap3-ldp.dts
index 540163025dd3..2f353dadfa40 100644
--- a/sys/gnu/dts/arm/omap3-ldp.dts
+++ b/sys/gnu/dts/arm/omap3-ldp.dts
@@ -97,12 +97,16 @@
 };
 
 &gpmc {
-	ranges = <0 0 0x00000000 0x01000000>,
-		 <1 0 0x08000000 0x01000000>;
+	ranges = <0 0 0x30000000 0x1000000>,	/* CS0 space, 16MB */
+		 <1 0 0x08000000 0x1000000>;	/* CS1 space, 16MB */
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		linux,mtd-name= "micron,nand";
-		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;
 		ti,nand-ecc-opt = "bch8";
diff --git a/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi b/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi
index 93f8dfe20f13..eff816e0bc0a 100644
--- a/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi
+++ b/sys/gnu/dts/arm/omap3-lilly-a83x.dtsi
@@ -362,7 +362,11 @@
 		<7 0 0x15000000 0x01000000>;
 
 	nand@0,0 {
-		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		nand-bus-width = <16>;
 		ti,nand-ecc-opt = "bch8";
 		/* no elm on omap3 */
diff --git a/sys/gnu/dts/arm/omap3-n9.dts b/sys/gnu/dts/arm/omap3-n9.dts
index f2e213931e09..b9e58c536afd 100644
--- a/sys/gnu/dts/arm/omap3-n9.dts
+++ b/sys/gnu/dts/arm/omap3-n9.dts
@@ -53,3 +53,21 @@
 		};
 	};
 };
+
+&modem {
+	compatible = "nokia,n9-modem";
+};
+
+&lis302 {
+	st,axis-x = <1>;    /* LIS3_DEV_X */
+	st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
+	st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
+
+	st,min-limit-x = <(-46)>;
+	st,min-limit-y = <3>;
+	st,min-limit-z = <3>;
+
+	st,max-limit-x = <(-3)>;
+	st,max-limit-y = <46>;
+	st,max-limit-z = <46>;
+};
diff --git a/sys/gnu/dts/arm/omap3-n900.dts b/sys/gnu/dts/arm/omap3-n900.dts
index 74d8f7eb5563..2b74a81d1de2 100644
--- a/sys/gnu/dts/arm/omap3-n900.dts
+++ b/sys/gnu/dts/arm/omap3-n900.dts
@@ -65,50 +65,51 @@
 		camera_lens_cover {
 			label = "Camera Lens Cover";
 			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
-			linux,input-type = <5>; /* EV_SW */
-			linux,code = <0x09>; /* SW_CAMERA_LENS_COVER */
-			wakeup-source;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_CAMERA_LENS_COVER>;
+			linux,can-disable;
 		};
 
 		camera_focus {
 			label = "Camera Focus";
 			gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
-			linux,code = <0x210>; /* KEY_CAMERA_FOCUS */
-			wakeup-source;
+			linux,code = <KEY_CAMERA_FOCUS>;
+			linux,can-disable;
 		};
 
 		camera_capture {
 			label = "Camera Capture";
 			gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
-			linux,code = <0xd4>; /* KEY_CAMERA */
-			wakeup-source;
+			linux,code = <KEY_CAMERA>;
+			linux,can-disable;
 		};
 
 		lock_button {
 			label = "Lock Button";
 			gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
-			linux,code = <0x98>; /* KEY_SCREENLOCK */
-			wakeup-source;
+			linux,code = <KEY_SCREENLOCK>;
+			linux,can-disable;
 		};
 
 		keypad_slide {
 			label = "Keypad Slide";
 			gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
-			linux,input-type = <5>; /* EV_SW */
-			linux,code = <0x0a>; /* SW_KEYPAD_SLIDE */
-			wakeup-source;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_KEYPAD_SLIDE>;
+			linux,can-disable;
 		};
 
 		proximity_sensor {
 			label = "Proximity Sensor";
 			gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
-			linux,input-type = <5>; /* EV_SW */
-			linux,code = <0x0b>; /* SW_FRONT_PROXIMITY */
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_FRONT_PROXIMITY>;
+			linux,can-disable;
 		};
 	};
 
-	isp1704: isp1704 {
-		compatible = "nxp,isp1704";
+	isp1707: isp1707 {
+		compatible = "nxp,isp1707";
 		nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
 		usb-phy = <&usb2_phy>;
 	};
@@ -287,7 +288,7 @@
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1)	/* ssi1_rdy_tx */
 			OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1)		/* ssi1_flag_tx */
-			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
+			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4)		/* ssi1_wake_tx (cawake) */
 			OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1)		/* ssi1_dat_tx */
 			OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1)		/* ssi1_dat_rx */
 			OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1)		/* ssi1_flag_rx */
@@ -299,7 +300,7 @@
 	modem_pins: pinmux_modem {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4)		/* gpio 70 => cmt_apeslpx */
-			OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */
+			OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4)		/* gpio 72 => ape_rst_rq */
 			OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4)		/* gpio 73 => cmt_rst_rq */
 			OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4)		/* gpio 74 => cmt_en */
 			OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4)		/* gpio 75 => cmt_rst */
@@ -328,6 +329,7 @@
 	regulator-name = "V28";
 	regulator-min-microvolt = <2800000>;
 	regulator-max-microvolt = <2800000>;
+	regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
 	regulator-always-on; /* due to battery cover sensor */
 };
 
@@ -335,30 +337,35 @@
 	regulator-name = "VCSI";
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
+	regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
 };
 
 &vaux3 {
 	regulator-name = "VMMC2_30";
 	regulator-min-microvolt = <2800000>;
 	regulator-max-microvolt = <3000000>;
+	regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
 };
 
 &vaux4 {
 	regulator-name = "VCAM_ANA_28";
 	regulator-min-microvolt = <2800000>;
 	regulator-max-microvolt = <2800000>;
+	regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
 };
 
 &vmmc1 {
 	regulator-name = "VMMC1";
 	regulator-min-microvolt = <1850000>;
 	regulator-max-microvolt = <3150000>;
+	regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
 };
 
 &vmmc2 {
 	regulator-name = "V28_A";
 	regulator-min-microvolt = <2800000>;
 	regulator-max-microvolt = <3000000>;
+	regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
 	regulator-always-on; /* due VIO leak to AIC34 VDDs */
 };
 
@@ -366,6 +373,7 @@
 	regulator-name = "VPLL";
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
+	regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
 	regulator-always-on;
 };
 
@@ -373,6 +381,7 @@
 	regulator-name = "VSDI_CSI";
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
+	regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
 	regulator-always-on;
 };
 
@@ -380,6 +389,7 @@
 	regulator-name = "VMMC2_IO_18";
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
+	regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
 };
 
 &vio {
@@ -522,6 +532,21 @@
 		amstaos,cover-comp-gain = <16>;
 	};
 
+	adp1653: led-controller@30 {
+		compatible = "adi,adp1653";
+		reg = <0x30>;
+		enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */
+
+		flash {
+			flash-timeout-us = <500000>;
+			flash-max-microamp = <320000>;
+			led-max-microamp = <50000>;
+		};
+		indicator {
+			led-max-microamp = <17500>;
+		};
+	};
+
 	lp5523: lp5523@32 {
 		compatible = "national,lp5523";
 		reg = <0x32>;
@@ -618,7 +643,7 @@
 		ti,termination-current = <100>;
 		ti,resistor-sense = <68>;
 
-		ti,usb-charger-detection = <&isp1704>;
+		ti,usb-charger-detection = <&isp1707>;
 	};
 };
 
diff --git a/sys/gnu/dts/arm/omap3-n950-n9.dtsi b/sys/gnu/dts/arm/omap3-n950-n9.dtsi
index a2c2b8d8dd2c..927b17fc4ed8 100644
--- a/sys/gnu/dts/arm/omap3-n950-n9.dtsi
+++ b/sys/gnu/dts/arm/omap3-n950-n9.dtsi
@@ -14,6 +14,13 @@
 	cpus {
 		cpu@0 {
 			cpu0-supply = <&vcc>;
+			operating-points = <
+				/* kHz    uV */
+				300000  1012500
+				600000  1200000
+				800000  1325000
+				1000000	1375000
+			>;
 		};
 	};
 
@@ -31,9 +38,42 @@
 		startup-delay-us = <150>;
 		enable-active-high;
 	};
+
+	vwlan_fixed: fixedregulator@2 {
+		compatible = "regulator-fixed";
+		regulator-name = "VWLAN";
+		gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */
+		enable-active-high;
+		regulator-boot-off;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		heartbeat {
+			label = "debug::sleep";
+			gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;  /* gpio92 */
+			linux,default-trigger = "default-on";
+			pinctrl-names = "default";
+			pinctrl-0 = <&debug_leds>;
+		};
+	};
 };
 
 &omap3_pmx_core {
+	accelerator_pins: pinmux_accelerator_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4)	/* mcspi2_somi.gpio_180 -> LIS302 INT1 */
+			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4)	/* mcspi2_cs0.gpio_181 -> LIS302 INT2 */
+		>;
+	};
+
+	debug_leds: pinmux_debug_led_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4)       /* dss_data22.gpio_92 */
+		>;
+	};
+
 	mmc2_pins: pinmux_mmc2_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
@@ -44,6 +84,55 @@
 			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
 		>;
 	};
+
+	wlan_pins: pinmux_wlan_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */
+			OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */
+		>;
+	};
+
+	ssi_pins: pinmux_ssi_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1)            /* ssi1_dat_tx */
+			OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1)            /* ssi1_flag_tx */
+			OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1)      /* ssi1_rdy_tx */
+			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4)	/* ssi1_wake_tx (cawake) */
+			OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1)             /* ssi1_dat_rx */
+			OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1)             /* ssi1_flag_rx */
+			OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1)            /* ssi1_rdy_rx */
+			OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1)            /* ssi1_wake */
+		>;
+	};
+
+	ssi_pins_idle: pinmux_ssi_pins_idle {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7)            /* ssi1_dat_tx */
+			OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7)            /* ssi1_flag_tx */
+			OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7)    /* ssi1_rdy_tx */
+			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4)	/* ssi1_wake_tx (cawake) */
+			OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7)             /* ssi1_dat_rx */
+			OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7)             /* ssi1_flag_rx */
+			OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4)            /* ssi1_rdy_rx */
+			OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7)            /* ssi1_wake */
+		>;
+	};
+
+	modem_pins1: pinmux_modem_core1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4)	/* gpio_34 (ape_rst_rq) */
+			OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4)            /* gpio_88 (cmt_rst_rq) */
+			OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4)            /* gpio_93 (cmt_apeslpx) */
+		>;
+	};
+};
+
+&omap3_pmx_core2 {
+	modem_pins2: pinmux_modem_core2_pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)         /* gpio_23 (cmt_en) */
+		>;
+	};
 };
 
 &i2c1 {
@@ -72,6 +161,30 @@
 	ti,pulldowns	= <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */
 };
 
+&vdac {
+	regulator-name = "vdac";
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+};
+
+&vpll1 {
+	regulator-name = "vpll1";
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+};
+
+&vpll2 {
+	regulator-name = "vpll2";
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+};
+
+&vaux1 {
+	regulator-name = "vaux1";
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+};
+
 /* CSI-2 receiver */
 &vaux2 {
 	regulator-name = "vaux2";
@@ -86,12 +199,107 @@
 	regulator-max-microvolt = <2800000>;
 };
 
+&vaux4 {
+	regulator-name = "vaux4";
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+};
+
+&vmmc1 {
+	regulator-name = "vmmc1";
+	regulator-min-microvolt = <1850000>;
+	regulator-max-microvolt = <3150000>;
+};
+
+&vmmc2 {
+	regulator-name = "vmmc2";
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+};
+
+&vintana1 {
+	regulator-name = "vintana1";
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+};
+
+&vintana2 {
+	regulator-name = "vintana2";
+	regulator-min-microvolt = <2750000>;
+	regulator-max-microvolt = <2750000>;
+};
+
+&vintdig {
+	regulator-name = "vintdig";
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+};
+
+&vsim {
+	regulator-name = "vsim";
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+};
+
+&vio {
+	regulator-name = "vio";
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+};
+
 &i2c2 {
 	clock-frequency = <400000>;
 };
 
 &i2c3 {
 	clock-frequency = <400000>;
+
+	lis302: lis302@1d {
+		compatible = "st,lis3lv02d";
+		reg = <0x1d>;
+
+		Vdd-supply = <&vaux1>;
+		Vdd_IO-supply = <&vio>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&accelerator_pins>;
+
+                interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */
+
+		/* click flags */
+		st,click-single-x;
+		st,click-single-y;
+		st,click-single-z;
+
+		/* Limits are 0.5g * value */
+		st,click-threshold-x = <8>;
+		st,click-threshold-y = <8>;
+		st,click-threshold-z = <10>;
+
+		/* Click must be longer than time limit */
+		st,click-time-limit = <9>;
+
+		/* Kind of debounce filter */
+		st,click-latency = <50>;
+
+		st,wakeup-x-hi;
+		st,wakeup-y-hi;
+		st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
+
+		st,wakeup2-z-hi;
+		st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */
+
+		st,highpass-cutoff-hz = <2>;
+
+		/* Interrupt line 1 for thresholds */
+		st,irq1-ff-wu-1;
+		st,irq1-ff-wu-2;
+		/* Interrupt line 2 for click detection */
+		st,irq2-click;
+
+		st,wu-duration-1 = <8>;
+		st,wu-duration-2 = <8>;
+	};
 };
 
 &mmc1 {
@@ -191,3 +399,39 @@
 		};
 	};
 };
+
+&ssi_port1 {
+	pinctrl-names = "default", "idle";
+	pinctrl-0 = <&ssi_pins>;
+	pinctrl-1 = <&ssi_pins_idle>;
+
+	ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
+
+	modem: hsi-client {
+		pinctrl-names = "default";
+		pinctrl-0 = <&modem_pins1 &modem_pins2>;
+
+		hsi-channel-ids = <0>, <1>, <2>, <3>;
+		hsi-channel-names = "mcsaab-control",
+				    "speech-control",
+				    "speech-data",
+				    "mcsaab-data";
+		hsi-speed-kbps = <96000>;
+		hsi-mode = "frame";
+		hsi-flow = "synchronized";
+		hsi-arb-mode = "round-robin";
+
+		interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */
+
+		gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */
+			<&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */
+			<&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */
+		gpio-names = "cmt_apeslpx",
+			     "cmt_rst_rq",
+			     "cmt_en";
+	};
+};
+
+&ssi_port2 {
+	status = "disabled";
+};
diff --git a/sys/gnu/dts/arm/omap3-n950.dts b/sys/gnu/dts/arm/omap3-n950.dts
index 0885b34d5d7d..646601a3ebd8 100644
--- a/sys/gnu/dts/arm/omap3-n950.dts
+++ b/sys/gnu/dts/arm/omap3-n950.dts
@@ -11,10 +11,44 @@
 /dts-v1/;
 
 #include "omap3-n950-n9.dtsi"
+#include <dt-bindings/input/input.h>
 
 / {
 	model = "Nokia N950";
 	compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
+
+	keys {
+		compatible = "gpio-keys";
+
+		keypad_slide {
+			label = "Keypad Slide";
+			gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* 109 */
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_KEYPAD_SLIDE>;
+			wakeup-source;
+			pinctrl-names = "default";
+			pinctrl-0 = <&keypad_slide_pins>;
+		};
+	};
+};
+
+&omap3_pmx_core {
+	keypad_slide_pins: pinmux_debug_led_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4)       /* cam_d10.gpio_109 */
+		>;
+	};
+};
+
+&omap3_pmx_core {
+	spi4_pins: pinmux_spi4_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
+			OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
+			OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
+			OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
+		>;
+	};
 };
 
 &i2c2 {
@@ -53,3 +87,101 @@
 		};
 	};
 };
+
+&mcspi4 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi4_pins>;
+
+	wlcore: wlcore@0 {
+		compatible = "ti,wl1271";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wlan_pins>;
+		reg = <0>;
+		spi-max-frequency = <48000000>;
+		clock-xtal;
+		ref-clock-frequency = <38400000>;
+		interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_HIGH>; /* gpio 42 */
+		vwlan-supply = <&vwlan_fixed>;
+	};
+};
+
+&modem {
+	compatible = "nokia,n950-modem";
+};
+
+&twl {
+	twl_audio: audio {
+		compatible = "ti,twl4030-audio";
+		ti,enable-vibra = <1>;
+	};
+};
+
+&twl_keypad {
+	linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_BACKSLASH)
+			 MATRIX_KEY(0x01, 0x00, KEY_LEFTSHIFT)
+			 MATRIX_KEY(0x02, 0x00, KEY_COMPOSE)
+			 MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA)
+			 MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
+			 MATRIX_KEY(0x05, 0x00, KEY_BACKSPACE)
+			 MATRIX_KEY(0x06, 0x00, KEY_VOLUMEDOWN)
+			 MATRIX_KEY(0x07, 0x00, KEY_VOLUMEUP)
+
+			 MATRIX_KEY(0x03, 0x01, KEY_Z)
+			 MATRIX_KEY(0x04, 0x01, KEY_A)
+			 MATRIX_KEY(0x05, 0x01, KEY_Q)
+			 MATRIX_KEY(0x06, 0x01, KEY_W)
+			 MATRIX_KEY(0x07, 0x01, KEY_E)
+
+			 MATRIX_KEY(0x03, 0x02, KEY_X)
+			 MATRIX_KEY(0x04, 0x02, KEY_S)
+			 MATRIX_KEY(0x05, 0x02, KEY_D)
+			 MATRIX_KEY(0x06, 0x02, KEY_C)
+			 MATRIX_KEY(0x07, 0x02, KEY_V)
+
+			 MATRIX_KEY(0x03, 0x03, KEY_O)
+			 MATRIX_KEY(0x04, 0x03, KEY_I)
+			 MATRIX_KEY(0x05, 0x03, KEY_U)
+			 MATRIX_KEY(0x06, 0x03, KEY_L)
+			 MATRIX_KEY(0x07, 0x03, KEY_APOSTROPHE)
+
+			 MATRIX_KEY(0x03, 0x04, KEY_Y)
+			 MATRIX_KEY(0x04, 0x04, KEY_K)
+			 MATRIX_KEY(0x05, 0x04, KEY_J)
+			 MATRIX_KEY(0x06, 0x04, KEY_H)
+			 MATRIX_KEY(0x07, 0x04, KEY_G)
+
+			 MATRIX_KEY(0x03, 0x05, KEY_B)
+			 MATRIX_KEY(0x04, 0x05, KEY_COMMA)
+			 MATRIX_KEY(0x05, 0x05, KEY_M)
+			 MATRIX_KEY(0x06, 0x05, KEY_N)
+			 MATRIX_KEY(0x07, 0x05, KEY_DOT)
+
+			 MATRIX_KEY(0x00, 0x06, KEY_SPACE)
+			 MATRIX_KEY(0x03, 0x06, KEY_T)
+			 MATRIX_KEY(0x04, 0x06, KEY_UP)
+			 MATRIX_KEY(0x05, 0x06, KEY_LEFT)
+			 MATRIX_KEY(0x06, 0x06, KEY_RIGHT)
+			 MATRIX_KEY(0x07, 0x06, KEY_DOWN)
+
+			 MATRIX_KEY(0x03, 0x07, KEY_P)
+			 MATRIX_KEY(0x04, 0x07, KEY_ENTER)
+			 MATRIX_KEY(0x05, 0x07, KEY_SLASH)
+			 MATRIX_KEY(0x06, 0x07, KEY_F)
+			 MATRIX_KEY(0x07, 0x07, KEY_R)
+			 >;
+};
+
+&lis302 {
+	st,axis-x = <(-2)>; /* LIS3_INV_DEV_Y */
+	st,axis-y = <(-1)>; /* LIS3_INV_DEV_X */
+	st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
+
+	st,min-limit-x = <(-32)>;
+	st,min-limit-y = <3>;
+	st,min-limit-z = <3>;
+
+	st,max-limit-x = <(-3)>;
+	st,max-limit-y = <32>;
+	st,max-limit-z = <32>;
+};
diff --git a/sys/gnu/dts/arm/omap3-overo-base.dtsi b/sys/gnu/dts/arm/omap3-overo-base.dtsi
index a29ad16cc9bb..de256fa8da48 100644
--- a/sys/gnu/dts/arm/omap3-overo-base.dtsi
+++ b/sys/gnu/dts/arm/omap3-overo-base.dtsi
@@ -226,8 +226,12 @@
 	ranges = <0 0 0x00000000 0x20000000>;
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		linux,mtd-name= "micron,mt29c4g96maz";
-		reg = <0 0 0>;
+		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;
 		ti,nand-ecc-opt = "bch8";
diff --git a/sys/gnu/dts/arm/omap3-pandora-common.dtsi b/sys/gnu/dts/arm/omap3-pandora-common.dtsi
index 13e9d1f987af..bcf39d606b65 100644
--- a/sys/gnu/dts/arm/omap3-pandora-common.dtsi
+++ b/sys/gnu/dts/arm/omap3-pandora-common.dtsi
@@ -546,7 +546,11 @@
 	ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		nand-bus-width = <16>;
 		ti,nand-ecc-opt = "sw";
 
diff --git a/sys/gnu/dts/arm/omap3-sniper.dts b/sys/gnu/dts/arm/omap3-sniper.dts
new file mode 100644
index 000000000000..78a1184cb312
--- /dev/null
+++ b/sys/gnu/dts/arm/omap3-sniper.dts
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2015-2016 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "LG Optimus Black";
+	compatible = "lg,omap3-sniper", "ti,omap36xx", "ti,omap3";
+
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&vcc>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x20000000>; /* 512 MB */
+	};
+};
+
+&omap3_pmx_core {
+	pinctrl-names = "default";
+
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)	/* uart3_rx_irrx */
+			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)	/* uart3_tx_irtx */
+		>;
+	};
+
+	dp3t_sel_pins: pinmux_dp3t_sel_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4)	/* gpio_161 */
+			OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)	/* gpio_162 */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)	/* i2c1_scl */
+			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)	/* i2c1_sda */
+		>;
+	};
+
+	i2c2_pins: pinmux_i2c2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)	/* i2c2_scl */
+			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)	/* i2c2_sda */
+		>;
+	};
+
+	i2c3_pins: pinmux_i2c3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl */
+			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda */
+		>;
+	};
+
+	lp8720_en_pin: pinmux_lp8720_en_pin {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4)	/* gpio_37 */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0)	/* sdmmc1_clk */
+			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0)	/* sdmmc1_cmd */
+			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat0 */
+			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat1 */
+			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat2 */
+			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat3 */
+		>;
+	};
+
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0)	/* sdmmc2_clk */
+			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0)	/* sdmmc2_cmd */
+			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT | MUX_MODE0)	/* sdmmc2_dat0 */
+			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT | MUX_MODE0)	/* sdmmc2_dat1 */
+			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT | MUX_MODE0)	/* sdmmc2_dat2 */
+			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT | MUX_MODE0)	/* sdmmc2_dat3 */
+			OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE0)	/* sdmmc2_dat4 */
+			OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT | MUX_MODE0)	/* sdmmc2_dat5 */
+			OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT | MUX_MODE0)	/* sdmmc2_dat6 */
+			OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0)	/* sdmmc2_dat7 */
+		>;
+	};
+
+	usb_otg_hs_pins: pinmux_usb_otg_hs_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)	/* hsusb0_clk */
+			OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)	/* hsusb0_stp */
+			OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)	/* hsusb0_dir */
+			OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)	/* hsusb0_nxt */
+			OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)	/* hsusb0_data0 */
+			OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)	/* hsusb0_data1 */
+			OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)	/* hsusb0_data2 */
+			OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)	/* hsusb0_data3 */
+			OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)	/* hsusb0_data4 */
+			OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)	/* hsusb0_data5 */
+			OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)	/* hsusb0_data6 */
+			OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)	/* hsusb0_data7 */
+		>;
+	};
+};
+
+&omap3_pmx_wkup {
+	pinctrl-names = "default";
+
+	mmc1_cd_pin: pinmux_mmc1_cd_pin {
+		pinctrl-single,pins = <
+			OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4)		/* gpio_10 */
+		>;
+	};
+};
+
+&gpio2 {
+	ti,no-reset-on-init;
+};
+
+&gpio5 {
+	ti,no-reset-on-init;
+};
+
+&gpio6 {
+	ti,no-reset-on-init;
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins &dp3t_sel_pins>;
+
+	interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+
+	clock-frequency = <2600000>;
+
+	twl: twl@48 {
+		reg = <0x48>;
+		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+
+		power {
+			compatible = "ti,twl4030-power";
+			ti,use_poweroff;
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+
+	clock-frequency = <400000>;
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+
+	clock-frequency = <400000>;
+
+	lp8720@7d {
+		pinctrl-names = "default";
+		pinctrl-0 = <&lp8720_en_pin>;
+
+		compatible = "ti,lp8720";
+		reg = <0x7d>;
+
+		enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio_37 */
+
+		lp8720_ldo1: ldo1 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+		};
+	};
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins &mmc1_cd_pin>;
+
+	vmmc-supply = <&lp8720_ldo1>;
+	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio 10 */
+	bus-width = <4>;
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+
+	vmmc-supply = <&vmmc2>;
+	ti,non-removable;
+	bus-width = <8>;
+};
+
+&mmc3 {
+	status = "disabled";
+};
+
+&usb_otg_hs {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb_otg_hs_pins>;
+
+	interface-type = <0>;
+	usb-phy = <&usb2_phy>;
+	phys = <&usb2_phy>;
+	phy-names = "usb2-phy";
+	mode = <3>;
+	power = <50>;
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+
+&twl_keypad {
+	linux,keymap = <
+		MATRIX_KEY(0x00, 0x00, KEY_VOLUMEUP)
+		MATRIX_KEY(0x01, 0x00, KEY_VOLUMEDOWN)
+		MATRIX_KEY(0x02, 0x00, KEY_SELECT)
+	>;
+};
+
+/*
+ * The TWL4030 VAUX2 and VDAC regulators power sensors that are slaves on I2C3.
+ * When not powered, these sensors cause the I2C3 clock to stay low at all times,
+ * making it impossible to reach other devices on I2C3.
+ */
+
+&vaux2 {
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+	regulator-always-on;
+};
+
+&vdac {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-always-on;
+};
diff --git a/sys/gnu/dts/arm/omap3-tao3530.dtsi b/sys/gnu/dts/arm/omap3-tao3530.dtsi
index ae5dbbd9d569..644d3c8ea66a 100644
--- a/sys/gnu/dts/arm/omap3-tao3530.dtsi
+++ b/sys/gnu/dts/arm/omap3-tao3530.dtsi
@@ -275,10 +275,14 @@
 };
 
 &gpmc {
-	ranges = <0 0 0x00000000 0x01000000>;
+	ranges = <0 0 0x30000000 0x01000000>;	/* CS0: 16MB for NAND */
 
 	nand@0,0 {
+		compatible = "ti,omap2-nand";
 		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;	/* GPMC_DEVWIDTH_16BIT */
 		ti,nand-ecc-opt = "sw";
diff --git a/sys/gnu/dts/arm/omap3-zoom3.dts b/sys/gnu/dts/arm/omap3-zoom3.dts
index f19170bdcc1f..c29b41dc7b95 100644
--- a/sys/gnu/dts/arm/omap3-zoom3.dts
+++ b/sys/gnu/dts/arm/omap3-zoom3.dts
@@ -98,7 +98,7 @@
 		pinctrl-single,pins = <
                         OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart2_cts.uart2_cts */
                         OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)		/* uart2_rts.uart2_rts */
-                        OMAP3_CORE1_IOPAD(0x217a, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
+                        OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)		/* uart2_rx.uart2_rx */
                         OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)		/* uart2_tx.uart2_tx */
 		>;
 	};
@@ -107,7 +107,7 @@
 		pinctrl-single,pins = <
                         OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* uart3_cts_rctx.uart3_cts_rctx */
                         OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0)		/* uart3_rts_sd.uart3_rts_sd */
-                        OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)		/* uart3_rx_irrx.uart3_rx_irrx */
                         OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx.uart3_tx_irtx */
 		>;
 	};
@@ -125,7 +125,7 @@
 		pinctrl-single,pins = <
 			OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_clk.sdmmc3_clk */
 			OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d4.sdmmc3_dat0 */
-			OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
+			OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d5.sdmmc3_dat1 */
 			OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d6.sdmmc3_dat2 */
 			OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2)	/* etk_d3.sdmmc3_dat3 */
 		>;
diff --git a/sys/gnu/dts/arm/omap3.dtsi b/sys/gnu/dts/arm/omap3.dtsi
index d1ffabb7c74f..9fbda38528dc 100644
--- a/sys/gnu/dts/arm/omap3.dtsi
+++ b/sys/gnu/dts/arm/omap3.dtsi
@@ -43,7 +43,7 @@
 		};
 	};
 
-	pmu {
+	pmu@54000000 {
 		compatible = "arm,cortex-a8-pmu";
 		reg = <0x54000000 0x800000>;
 		interrupts = <3>;
@@ -119,7 +119,7 @@
 					#size-cells = <1>;
 					ranges = <0 0x270 0x330>;
 
-					pbias_regulator: pbias_regulator {
+					pbias_regulator: pbias_regulator@2b0 {
 						compatible = "ti,pbias-omap3", "ti,pbias-omap";
 						reg = <0x2b0 0x4>;
 						syscon = <&scm_conf>;
@@ -723,6 +723,10 @@
 			gpmc,num-waitpins = <4>;
 			#address-cells = <2>;
 			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 		};
 
 		usb_otg_hs: usb_otg_hs@480ab000 {
diff --git a/sys/gnu/dts/arm/omap3430-sdp.dts b/sys/gnu/dts/arm/omap3430-sdp.dts
index 16b0cdfbee9c..a0dc8d854142 100644
--- a/sys/gnu/dts/arm/omap3430-sdp.dts
+++ b/sys/gnu/dts/arm/omap3430-sdp.dts
@@ -103,10 +103,14 @@
 	};
 
 	nand@1,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		linux,mtd-name= "micron,mt29f1g08abb";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		reg = <1 0 4>;	/* CS1, offset 0, IO size 4 */
 		ti,nand-ecc-opt = "sw";
 		nand-bus-width = <8>;
 		gpmc,cs-on-ns = <0>;
diff --git a/sys/gnu/dts/arm/omap3430es1-clocks.dtsi b/sys/gnu/dts/arm/omap3430es1-clocks.dtsi
index 4c22f3a7f813..86de819a0dcf 100644
--- a/sys/gnu/dts/arm/omap3430es1-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap3430es1-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &cm_clocks {
-	gfx_l3_ck: gfx_l3_ck {
+	gfx_l3_ck: gfx_l3_ck@b10 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&l3_ick>;
@@ -16,7 +16,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	gfx_l3_fck: gfx_l3_fck {
+	gfx_l3_fck: gfx_l3_fck@b40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&l3_ick>;
@@ -33,7 +33,7 @@
 		clock-div = <1>;
 	};
 
-	gfx_cg1_ck: gfx_cg1_ck {
+	gfx_cg1_ck: gfx_cg1_ck@b00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&gfx_l3_fck>;
@@ -41,7 +41,7 @@
 		ti,bit-shift = <1>;
 	};
 
-	gfx_cg2_ck: gfx_cg2_ck {
+	gfx_cg2_ck: gfx_cg2_ck@b00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&gfx_l3_fck>;
@@ -49,7 +49,7 @@
 		ti,bit-shift = <2>;
 	};
 
-	d2d_26m_fck: d2d_26m_fck {
+	d2d_26m_fck: d2d_26m_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&sys_ck>;
@@ -57,7 +57,7 @@
 		ti,bit-shift = <3>;
 	};
 
-	fshostusb_fck: fshostusb_fck {
+	fshostusb_fck: fshostusb_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_48m_fck>;
@@ -65,7 +65,7 @@
 		ti,bit-shift = <5>;
 	};
 
-	ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
+	ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&corex2_fck>;
@@ -73,7 +73,7 @@
 		reg = <0x0a00>;
 	};
 
-	ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
+	ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&corex2_fck>;
@@ -96,7 +96,7 @@
 		clock-div = <2>;
 	};
 
-	hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
+	hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-no-wait-interface-clock";
 		clocks = <&core_l3_ick>;
@@ -104,7 +104,7 @@
 		ti,bit-shift = <4>;
 	};
 
-	fac_ick: fac_ick {
+	fac_ick: fac_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -120,7 +120,7 @@
 		clock-div = <1>;
 	};
 
-	ssi_ick: ssi_ick_3430es1 {
+	ssi_ick: ssi_ick_3430es1@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-no-wait-interface-clock";
 		clocks = <&ssi_l4_ick>;
@@ -128,7 +128,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	usb_l4_gate_ick: usb_l4_gate_ick {
+	usb_l4_gate_ick: usb_l4_gate_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-interface-clock";
 		clocks = <&l4_ick>;
@@ -136,7 +136,7 @@
 		reg = <0x0a10>;
 	};
 
-	usb_l4_div_ick: usb_l4_div_ick {
+	usb_l4_div_ick: usb_l4_div_ick@a40 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&l4_ick>;
@@ -152,7 +152,7 @@
 		clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
 	};
 
-	dss1_alwon_fck: dss1_alwon_fck_3430es1 {
+	dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll4_m4x2_ck>;
@@ -161,7 +161,7 @@
 		ti,set-rate-parent;
 	};
 
-	dss_ick: dss_ick_3430es1 {
+	dss_ick: dss_ick_3430es1@e10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-no-wait-interface-clock";
 		clocks = <&l4_ick>;
diff --git a/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi b/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi
index b02017b7630e..858aa0796ec8 100644
--- a/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap34xx-omap36xx-clocks.dtsi
@@ -16,7 +16,7 @@
 		clock-div = <1>;
 	};
 
-	aes1_ick: aes1_ick {
+	aes1_ick: aes1_ick@a14 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&security_l4_ick2>;
@@ -24,7 +24,7 @@
 		reg = <0x0a14>;
 	};
 
-	rng_ick: rng_ick {
+	rng_ick: rng_ick@a14 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&security_l4_ick2>;
@@ -32,7 +32,7 @@
 		ti,bit-shift = <2>;
 	};
 
-	sha11_ick: sha11_ick {
+	sha11_ick: sha11_ick@a14 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&security_l4_ick2>;
@@ -40,7 +40,7 @@
 		ti,bit-shift = <1>;
 	};
 
-	des1_ick: des1_ick {
+	des1_ick: des1_ick@a14 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&security_l4_ick2>;
@@ -48,7 +48,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	cam_mclk: cam_mclk {
+	cam_mclk: cam_mclk@f00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll4_m5x2_ck>;
@@ -57,7 +57,7 @@
 		ti,set-rate-parent;
 	};
 
-	cam_ick: cam_ick {
+	cam_ick: cam_ick@f10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-no-wait-interface-clock";
 		clocks = <&l4_ick>;
@@ -65,7 +65,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	csi2_96m_fck: csi2_96m_fck {
+	csi2_96m_fck: csi2_96m_fck@f00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&core_96m_fck>;
@@ -81,7 +81,7 @@
 		clock-div = <1>;
 	};
 
-	pka_ick: pka_ick {
+	pka_ick: pka_ick@a14 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&security_l3_ick>;
@@ -89,7 +89,7 @@
 		ti,bit-shift = <4>;
 	};
 
-	icr_ick: icr_ick {
+	icr_ick: icr_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -97,7 +97,7 @@
 		ti,bit-shift = <29>;
 	};
 
-	des2_ick: des2_ick {
+	des2_ick: des2_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -105,7 +105,7 @@
 		ti,bit-shift = <26>;
 	};
 
-	mspro_ick: mspro_ick {
+	mspro_ick: mspro_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -113,7 +113,7 @@
 		ti,bit-shift = <23>;
 	};
 
-	mailboxes_ick: mailboxes_ick {
+	mailboxes_ick: mailboxes_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -129,7 +129,7 @@
 		clock-div = <1>;
 	};
 
-	sr1_fck: sr1_fck {
+	sr1_fck: sr1_fck@c00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&sys_ck>;
@@ -137,7 +137,7 @@
 		ti,bit-shift = <6>;
 	};
 
-	sr2_fck: sr2_fck {
+	sr2_fck: sr2_fck@c00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&sys_ck>;
@@ -153,7 +153,7 @@
 		clock-div = <1>;
 	};
 
-	dpll2_fck: dpll2_fck {
+	dpll2_fck: dpll2_fck@40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&core_ck>;
@@ -163,7 +163,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll2_ck: dpll2_ck {
+	dpll2_ck: dpll2_ck@4 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-dpll-clock";
 		clocks = <&sys_ck>, <&dpll2_fck>;
@@ -173,7 +173,7 @@
 		ti,low-power-bypass;
 	};
 
-	dpll2_m2_ck: dpll2_m2_ck {
+	dpll2_m2_ck: dpll2_m2_ck@44 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll2_ck>;
@@ -182,7 +182,7 @@
 		ti,index-starts-at-one;
 	};
 
-	iva2_ck: iva2_ck {
+	iva2_ck: iva2_ck@0 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&dpll2_m2_ck>;
@@ -190,7 +190,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	modem_fck: modem_fck {
+	modem_fck: modem_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&sys_ck>;
@@ -198,7 +198,7 @@
 		ti,bit-shift = <31>;
 	};
 
-	sad2d_ick: sad2d_ick {
+	sad2d_ick: sad2d_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l3_ick>;
@@ -206,7 +206,7 @@
 		ti,bit-shift = <3>;
 	};
 
-	mad2d_ick: mad2d_ick {
+	mad2d_ick: mad2d_ick@a18 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&l3_ick>;
@@ -214,7 +214,7 @@
 		ti,bit-shift = <3>;
 	};
 
-	mspro_fck: mspro_fck {
+	mspro_fck: mspro_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_96m_fck>;
diff --git a/sys/gnu/dts/arm/omap34xx.dtsi b/sys/gnu/dts/arm/omap34xx.dtsi
index 4f6b2d5b1902..e44656258225 100644
--- a/sys/gnu/dts/arm/omap34xx.dtsi
+++ b/sys/gnu/dts/arm/omap34xx.dtsi
@@ -46,7 +46,7 @@
 			       0x480bd800 0x017c>;
 			interrupts = <24>;
 			iommus = <&mmu_isp>;
-			syscon = <&scm_conf 0xdc>;
+			syscon = <&scm_conf 0x6c>;
 			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
 			#clock-cells = <1>;
 			ports {
@@ -54,6 +54,12 @@
 				#size-cells = <0>;
 			};
 		};
+
+		bandgap@48002524 {
+			reg = <0x48002524 0x4>;
+			compatible = "ti,omap34xx-bandgap";
+			#thermal-sensor-cells = <0>;
+		};
 	};
 };
 
diff --git a/sys/gnu/dts/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/sys/gnu/dts/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
index 080fb3f4e429..15d18669000e 100644
--- a/sys/gnu/dts/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -25,7 +25,7 @@
 	};
 };
 &cm_clocks {
-	dpll5_ck: dpll5_ck {
+	dpll5_ck: dpll5_ck@d04 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-dpll-clock";
 		clocks = <&sys_ck>, <&sys_ck>;
@@ -34,7 +34,7 @@
 		ti,lock;
 	};
 
-	dpll5_m2_ck: dpll5_m2_ck {
+	dpll5_m2_ck: dpll5_m2_ck@d50 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll5_ck>;
@@ -43,7 +43,7 @@
 		ti,index-starts-at-one;
 	};
 
-	sgx_gate_fck: sgx_gate_fck {
+	sgx_gate_fck: sgx_gate_fck@b00 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&core_ck>;
@@ -91,7 +91,7 @@
 		clock-div = <2>;
 	};
 
-	sgx_mux_fck: sgx_mux_fck {
+	sgx_mux_fck: sgx_mux_fck@b40 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
@@ -104,7 +104,7 @@
 		clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
 	};
 
-	sgx_ick: sgx_ick {
+	sgx_ick: sgx_ick@b10 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&l3_ick>;
@@ -112,7 +112,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	cpefuse_fck: cpefuse_fck {
+	cpefuse_fck: cpefuse_fck@a08 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_ck>;
@@ -120,7 +120,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	ts_fck: ts_fck {
+	ts_fck: ts_fck@a08 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&omap_32k_fck>;
@@ -128,7 +128,7 @@
 		ti,bit-shift = <1>;
 	};
 
-	usbtll_fck: usbtll_fck {
+	usbtll_fck: usbtll_fck@a08 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&dpll5_m2_ck>;
@@ -136,7 +136,7 @@
 		ti,bit-shift = <2>;
 	};
 
-	usbtll_ick: usbtll_ick {
+	usbtll_ick: usbtll_ick@a18 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -144,7 +144,7 @@
 		ti,bit-shift = <2>;
 	};
 
-	mmchs3_ick: mmchs3_ick {
+	mmchs3_ick: mmchs3_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -152,7 +152,7 @@
 		ti,bit-shift = <30>;
 	};
 
-	mmchs3_fck: mmchs3_fck {
+	mmchs3_fck: mmchs3_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_96m_fck>;
@@ -160,7 +160,7 @@
 		ti,bit-shift = <30>;
 	};
 
-	dss1_alwon_fck: dss1_alwon_fck_3430es2 {
+	dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
 		#clock-cells = <0>;
 		compatible = "ti,dss-gate-clock";
 		clocks = <&dpll4_m4x2_ck>;
@@ -169,7 +169,7 @@
 		ti,set-rate-parent;
 	};
 
-	dss_ick: dss_ick_3430es2 {
+	dss_ick: dss_ick_3430es2@e10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-dss-interface-clock";
 		clocks = <&l4_ick>;
@@ -177,7 +177,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	usbhost_120m_fck: usbhost_120m_fck {
+	usbhost_120m_fck: usbhost_120m_fck@1400 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll5_m2_ck>;
@@ -185,7 +185,7 @@
 		ti,bit-shift = <1>;
 	};
 
-	usbhost_48m_fck: usbhost_48m_fck {
+	usbhost_48m_fck: usbhost_48m_fck@1400 {
 		#clock-cells = <0>;
 		compatible = "ti,dss-gate-clock";
 		clocks = <&omap_48m_fck>;
@@ -193,7 +193,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	usbhost_ick: usbhost_ick {
+	usbhost_ick: usbhost_ick@1410 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-dss-interface-clock";
 		clocks = <&l4_ick>;
diff --git a/sys/gnu/dts/arm/omap36xx-clocks.dtsi b/sys/gnu/dts/arm/omap36xx-clocks.dtsi
index 200ae3a5cbbb..a21d1f021267 100644
--- a/sys/gnu/dts/arm/omap36xx-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap36xx-clocks.dtsi
@@ -8,14 +8,14 @@
  * published by the Free Software Foundation.
  */
 &cm_clocks {
-	dpll4_ck: dpll4_ck {
+	dpll4_ck: dpll4_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-dpll-per-j-type-clock";
 		clocks = <&sys_ck>, <&sys_ck>;
 		reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
 	};
 
-	dpll4_m5x2_ck: dpll4_m5x2_ck {
+	dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,hsdiv-gate-clock";
 		clocks = <&dpll4_m5x2_mul_ck>;
@@ -25,7 +25,7 @@
 		ti,set-bit-to-disable;
 	};
 
-	dpll4_m2x2_ck: dpll4_m2x2_ck {
+	dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,hsdiv-gate-clock";
 		clocks = <&dpll4_m2x2_mul_ck>;
@@ -34,7 +34,7 @@
 		ti,set-bit-to-disable;
 	};
 
-	dpll3_m3x2_ck: dpll3_m3x2_ck {
+	dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,hsdiv-gate-clock";
 		clocks = <&dpll3_m3x2_mul_ck>;
@@ -43,7 +43,7 @@
 		ti,set-bit-to-disable;
 	};
 
-	dpll4_m3x2_ck: dpll4_m3x2_ck {
+	dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,hsdiv-gate-clock";
 		clocks = <&dpll4_m3x2_mul_ck>;
@@ -52,7 +52,7 @@
 		ti,set-bit-to-disable;
 	};
 
-	dpll4_m6x2_ck: dpll4_m6x2_ck {
+	dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,hsdiv-gate-clock";
 		clocks = <&dpll4_m6x2_mul_ck>;
@@ -61,7 +61,7 @@
 		ti,set-bit-to-disable;
 	};
 
-	uart4_fck: uart4_fck {
+	uart4_fck: uart4_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&per_48m_fck>;
diff --git a/sys/gnu/dts/arm/omap36xx-omap3430es2plus-clocks.dtsi b/sys/gnu/dts/arm/omap36xx-omap3430es2plus-clocks.dtsi
index 877318c28364..1a4fbdf0d9cc 100644
--- a/sys/gnu/dts/arm/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap36xx-omap3430es2plus-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &cm_clocks {
-	ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
+	ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&corex2_fck>;
@@ -16,7 +16,7 @@
 		reg = <0x0a00>;
 	};
 
-	ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
+	ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&corex2_fck>;
@@ -39,7 +39,7 @@
 		clock-div = <2>;
 	};
 
-	hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
+	hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-hsotgusb-interface-clock";
 		clocks = <&core_l3_ick>;
@@ -55,7 +55,7 @@
 		clock-div = <1>;
 	};
 
-	ssi_ick: ssi_ick_3430es2 {
+	ssi_ick: ssi_ick_3430es2@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-ssi-interface-clock";
 		clocks = <&ssi_l4_ick>;
@@ -63,7 +63,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	usim_gate_fck: usim_gate_fck {
+	usim_gate_fck: usim_gate_fck@c00 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&omap_96m_fck>;
@@ -143,7 +143,7 @@
 		clock-div = <20>;
 	};
 
-	usim_mux_fck: usim_mux_fck {
+	usim_mux_fck: usim_mux_fck@c40 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
@@ -158,7 +158,7 @@
 		clocks = <&usim_gate_fck>, <&usim_mux_fck>;
 	};
 
-	usim_ick: usim_ick {
+	usim_ick: usim_ick@c10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&wkup_l4_ick>;
diff --git a/sys/gnu/dts/arm/omap36xx.dtsi b/sys/gnu/dts/arm/omap36xx.dtsi
index 86253de5a97a..8b7979153008 100644
--- a/sys/gnu/dts/arm/omap36xx.dtsi
+++ b/sys/gnu/dts/arm/omap36xx.dtsi
@@ -44,7 +44,7 @@
 		abb_mpu_iva: regulator-abb-mpu {
 			compatible = "ti,abb-v1";
 			regulator-name = "abb_mpu_iva";
-			#address-cell = <0>;
+			#address-cells = <0>;
 			#size-cells = <0>;
 			reg = <0x483072f0 0x8>, <0x48306818 0x4>;
 			reg-names = "base-address", "int-address";
@@ -86,6 +86,12 @@
 				#size-cells = <0>;
 			};
 		};
+
+		bandgap@48002524 {
+			reg = <0x48002524 0x4>;
+			compatible = "ti,omap36xx-bandgap";
+			#thermal-sensor-cells = <0>;
+		};
 	};
 };
 
diff --git a/sys/gnu/dts/arm/omap3xxx-clocks.dtsi b/sys/gnu/dts/arm/omap3xxx-clocks.dtsi
index bbba5bdc4bc9..9bd91641aa7c 100644
--- a/sys/gnu/dts/arm/omap3xxx-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap3xxx-clocks.dtsi
@@ -14,14 +14,14 @@
 		clock-frequency = <16800000>;
 	};
 
-	osc_sys_ck: osc_sys_ck {
+	osc_sys_ck: osc_sys_ck@d40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
 		reg = <0x0d40>;
 	};
 
-	sys_ck: sys_ck {
+	sys_ck: sys_ck@1270 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&osc_sys_ck>;
@@ -31,7 +31,7 @@
 		ti,index-starts-at-one;
 	};
 
-	sys_clkout1: sys_clkout1 {
+	sys_clkout1: sys_clkout1@d70 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&osc_sys_ck>;
@@ -81,7 +81,7 @@
 };
 
 &scm_clocks {
-	mcbsp5_mux_fck: mcbsp5_mux_fck {
+	mcbsp5_mux_fck: mcbsp5_mux_fck@68 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&core_96m_fck>, <&mcbsp_clks>;
@@ -95,7 +95,7 @@
 		clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
 	};
 
-	mcbsp1_mux_fck: mcbsp1_mux_fck {
+	mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&core_96m_fck>, <&mcbsp_clks>;
@@ -109,7 +109,7 @@
 		clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
 	};
 
-	mcbsp2_mux_fck: mcbsp2_mux_fck {
+	mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&per_96m_fck>, <&mcbsp_clks>;
@@ -123,7 +123,7 @@
 		clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
 	};
 
-	mcbsp3_mux_fck: mcbsp3_mux_fck {
+	mcbsp3_mux_fck: mcbsp3_mux_fck@68 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&per_96m_fck>, <&mcbsp_clks>;
@@ -136,7 +136,7 @@
 		clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
 	};
 
-	mcbsp4_mux_fck: mcbsp4_mux_fck {
+	mcbsp4_mux_fck: mcbsp4_mux_fck@68 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&per_96m_fck>, <&mcbsp_clks>;
@@ -193,14 +193,14 @@
 		clock-frequency = <38400000>;
 	};
 
-	dpll4_ck: dpll4_ck {
+	dpll4_ck: dpll4_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-dpll-per-clock";
 		clocks = <&sys_ck>, <&sys_ck>;
 		reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
 	};
 
-	dpll4_m2_ck: dpll4_m2_ck {
+	dpll4_m2_ck: dpll4_m2_ck@d48 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll4_ck>;
@@ -217,7 +217,7 @@
 		clock-div = <1>;
 	};
 
-	dpll4_m2x2_ck: dpll4_m2x2_ck {
+	dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll4_m2x2_mul_ck>;
@@ -234,14 +234,14 @@
 		clock-div = <1>;
 	};
 
-	dpll3_ck: dpll3_ck {
+	dpll3_ck: dpll3_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-dpll-core-clock";
 		clocks = <&sys_ck>, <&sys_ck>;
 		reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
 	};
 
-	dpll3_m3_ck: dpll3_m3_ck {
+	dpll3_m3_ck: dpll3_m3_ck@1140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll3_ck>;
@@ -259,7 +259,7 @@
 		clock-div = <1>;
 	};
 
-	dpll3_m3x2_ck: dpll3_m3x2_ck {
+	dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll3_m3x2_mul_ck>;
@@ -288,7 +288,7 @@
 		clock-frequency = <0x0>;
 	};
 
-	dpll3_m2_ck: dpll3_m2_ck {
+	dpll3_m2_ck: dpll3_m2_ck@d40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll3_ck>;
@@ -306,7 +306,7 @@
 		clock-div = <1>;
 	};
 
-	dpll1_fck: dpll1_fck {
+	dpll1_fck: dpll1_fck@940 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&core_ck>;
@@ -316,7 +316,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll1_ck: dpll1_ck {
+	dpll1_ck: dpll1_ck@904 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-dpll-clock";
 		clocks = <&sys_ck>, <&dpll1_fck>;
@@ -331,7 +331,7 @@
 		clock-div = <1>;
 	};
 
-	dpll1_x2m2_ck: dpll1_x2m2_ck {
+	dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll1_x2_ck>;
@@ -348,7 +348,7 @@
 		clock-div = <1>;
 	};
 
-	omap_96m_fck: omap_96m_fck {
+	omap_96m_fck: omap_96m_fck@d40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&cm_96m_fck>, <&sys_ck>;
@@ -356,7 +356,7 @@
 		reg = <0x0d40>;
 	};
 
-	dpll4_m3_ck: dpll4_m3_ck {
+	dpll4_m3_ck: dpll4_m3_ck@e40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll4_ck>;
@@ -374,7 +374,7 @@
 		clock-div = <1>;
 	};
 
-	dpll4_m3x2_ck: dpll4_m3x2_ck {
+	dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll4_m3x2_mul_ck>;
@@ -383,7 +383,7 @@
 		ti,set-bit-to-disable;
 	};
 
-	omap_54m_fck: omap_54m_fck {
+	omap_54m_fck: omap_54m_fck@d40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
@@ -399,7 +399,7 @@
 		clock-div = <2>;
 	};
 
-	omap_48m_fck: omap_48m_fck {
+	omap_48m_fck: omap_48m_fck@d40 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
@@ -415,7 +415,7 @@
 		clock-div = <4>;
 	};
 
-	dpll4_m4_ck: dpll4_m4_ck {
+	dpll4_m4_ck: dpll4_m4_ck@e40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll4_ck>;
@@ -433,7 +433,7 @@
 		ti,set-rate-parent;
 	};
 
-	dpll4_m4x2_ck: dpll4_m4x2_ck {
+	dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll4_m4x2_mul_ck>;
@@ -443,7 +443,7 @@
 		ti,set-rate-parent;
 	};
 
-	dpll4_m5_ck: dpll4_m5_ck {
+	dpll4_m5_ck: dpll4_m5_ck@f40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll4_ck>;
@@ -461,7 +461,7 @@
 		ti,set-rate-parent;
 	};
 
-	dpll4_m5x2_ck: dpll4_m5x2_ck {
+	dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll4_m5x2_mul_ck>;
@@ -471,7 +471,7 @@
 		ti,set-rate-parent;
 	};
 
-	dpll4_m6_ck: dpll4_m6_ck {
+	dpll4_m6_ck: dpll4_m6_ck@1140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll4_ck>;
@@ -489,7 +489,7 @@
 		clock-div = <1>;
 	};
 
-	dpll4_m6x2_ck: dpll4_m6x2_ck {
+	dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll4_m6x2_mul_ck>;
@@ -506,7 +506,7 @@
 		clock-div = <1>;
 	};
 
-	clkout2_src_gate_ck: clkout2_src_gate_ck {
+	clkout2_src_gate_ck: clkout2_src_gate_ck@d70 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&core_ck>;
@@ -514,7 +514,7 @@
 		reg = <0x0d70>;
 	};
 
-	clkout2_src_mux_ck: clkout2_src_mux_ck {
+	clkout2_src_mux_ck: clkout2_src_mux_ck@d70 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
@@ -527,7 +527,7 @@
 		clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
 	};
 
-	sys_clkout2: sys_clkout2 {
+	sys_clkout2: sys_clkout2@d70 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&clkout2_src_ck>;
@@ -545,7 +545,7 @@
 		clock-div = <1>;
 	};
 
-	arm_fck: arm_fck {
+	arm_fck: arm_fck@924 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mpu_ck>;
@@ -561,7 +561,7 @@
 		clock-div = <1>;
 	};
 
-	l3_ick: l3_ick {
+	l3_ick: l3_ick@a40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&core_ck>;
@@ -570,7 +570,7 @@
 		ti,index-starts-at-one;
 	};
 
-	l4_ick: l4_ick {
+	l4_ick: l4_ick@a40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&l3_ick>;
@@ -580,7 +580,7 @@
 		ti,index-starts-at-one;
 	};
 
-	rm_ick: rm_ick {
+	rm_ick: rm_ick@c40 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&l4_ick>;
@@ -590,7 +590,7 @@
 		ti,index-starts-at-one;
 	};
 
-	gpt10_gate_fck: gpt10_gate_fck {
+	gpt10_gate_fck: gpt10_gate_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -598,7 +598,7 @@
 		reg = <0x0a00>;
 	};
 
-	gpt10_mux_fck: gpt10_mux_fck {
+	gpt10_mux_fck: gpt10_mux_fck@a40 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -612,7 +612,7 @@
 		clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
 	};
 
-	gpt11_gate_fck: gpt11_gate_fck {
+	gpt11_gate_fck: gpt11_gate_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -620,7 +620,7 @@
 		reg = <0x0a00>;
 	};
 
-	gpt11_mux_fck: gpt11_mux_fck {
+	gpt11_mux_fck: gpt11_mux_fck@a40 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -642,7 +642,7 @@
 		clock-div = <1>;
 	};
 
-	mmchs2_fck: mmchs2_fck {
+	mmchs2_fck: mmchs2_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_96m_fck>;
@@ -650,7 +650,7 @@
 		ti,bit-shift = <25>;
 	};
 
-	mmchs1_fck: mmchs1_fck {
+	mmchs1_fck: mmchs1_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_96m_fck>;
@@ -658,7 +658,7 @@
 		ti,bit-shift = <24>;
 	};
 
-	i2c3_fck: i2c3_fck {
+	i2c3_fck: i2c3_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_96m_fck>;
@@ -666,7 +666,7 @@
 		ti,bit-shift = <17>;
 	};
 
-	i2c2_fck: i2c2_fck {
+	i2c2_fck: i2c2_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_96m_fck>;
@@ -674,7 +674,7 @@
 		ti,bit-shift = <16>;
 	};
 
-	i2c1_fck: i2c1_fck {
+	i2c1_fck: i2c1_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_96m_fck>;
@@ -682,7 +682,7 @@
 		ti,bit-shift = <15>;
 	};
 
-	mcbsp5_gate_fck: mcbsp5_gate_fck {
+	mcbsp5_gate_fck: mcbsp5_gate_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -690,7 +690,7 @@
 		reg = <0x0a00>;
 	};
 
-	mcbsp1_gate_fck: mcbsp1_gate_fck {
+	mcbsp1_gate_fck: mcbsp1_gate_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -706,7 +706,7 @@
 		clock-div = <1>;
 	};
 
-	mcspi4_fck: mcspi4_fck {
+	mcspi4_fck: mcspi4_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_48m_fck>;
@@ -714,7 +714,7 @@
 		ti,bit-shift = <21>;
 	};
 
-	mcspi3_fck: mcspi3_fck {
+	mcspi3_fck: mcspi3_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_48m_fck>;
@@ -722,7 +722,7 @@
 		ti,bit-shift = <20>;
 	};
 
-	mcspi2_fck: mcspi2_fck {
+	mcspi2_fck: mcspi2_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_48m_fck>;
@@ -730,7 +730,7 @@
 		ti,bit-shift = <19>;
 	};
 
-	mcspi1_fck: mcspi1_fck {
+	mcspi1_fck: mcspi1_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_48m_fck>;
@@ -738,7 +738,7 @@
 		ti,bit-shift = <18>;
 	};
 
-	uart2_fck: uart2_fck {
+	uart2_fck: uart2_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_48m_fck>;
@@ -746,7 +746,7 @@
 		ti,bit-shift = <14>;
 	};
 
-	uart1_fck: uart1_fck {
+	uart1_fck: uart1_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_48m_fck>;
@@ -762,7 +762,7 @@
 		clock-div = <1>;
 	};
 
-	hdq_fck: hdq_fck {
+	hdq_fck: hdq_fck@a00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_12m_fck>;
@@ -778,7 +778,7 @@
 		clock-div = <1>;
 	};
 
-	sdrc_ick: sdrc_ick {
+	sdrc_ick: sdrc_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&core_l3_ick>;
@@ -802,7 +802,7 @@
 		clock-div = <1>;
 	};
 
-	mmchs2_ick: mmchs2_ick {
+	mmchs2_ick: mmchs2_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -810,7 +810,7 @@
 		ti,bit-shift = <25>;
 	};
 
-	mmchs1_ick: mmchs1_ick {
+	mmchs1_ick: mmchs1_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -818,7 +818,7 @@
 		ti,bit-shift = <24>;
 	};
 
-	hdq_ick: hdq_ick {
+	hdq_ick: hdq_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -826,7 +826,7 @@
 		ti,bit-shift = <22>;
 	};
 
-	mcspi4_ick: mcspi4_ick {
+	mcspi4_ick: mcspi4_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -834,7 +834,7 @@
 		ti,bit-shift = <21>;
 	};
 
-	mcspi3_ick: mcspi3_ick {
+	mcspi3_ick: mcspi3_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -842,7 +842,7 @@
 		ti,bit-shift = <20>;
 	};
 
-	mcspi2_ick: mcspi2_ick {
+	mcspi2_ick: mcspi2_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -850,7 +850,7 @@
 		ti,bit-shift = <19>;
 	};
 
-	mcspi1_ick: mcspi1_ick {
+	mcspi1_ick: mcspi1_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -858,7 +858,7 @@
 		ti,bit-shift = <18>;
 	};
 
-	i2c3_ick: i2c3_ick {
+	i2c3_ick: i2c3_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -866,7 +866,7 @@
 		ti,bit-shift = <17>;
 	};
 
-	i2c2_ick: i2c2_ick {
+	i2c2_ick: i2c2_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -874,7 +874,7 @@
 		ti,bit-shift = <16>;
 	};
 
-	i2c1_ick: i2c1_ick {
+	i2c1_ick: i2c1_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -882,7 +882,7 @@
 		ti,bit-shift = <15>;
 	};
 
-	uart2_ick: uart2_ick {
+	uart2_ick: uart2_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -890,7 +890,7 @@
 		ti,bit-shift = <14>;
 	};
 
-	uart1_ick: uart1_ick {
+	uart1_ick: uart1_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -898,7 +898,7 @@
 		ti,bit-shift = <13>;
 	};
 
-	gpt11_ick: gpt11_ick {
+	gpt11_ick: gpt11_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -906,7 +906,7 @@
 		ti,bit-shift = <12>;
 	};
 
-	gpt10_ick: gpt10_ick {
+	gpt10_ick: gpt10_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -914,7 +914,7 @@
 		ti,bit-shift = <11>;
 	};
 
-	mcbsp5_ick: mcbsp5_ick {
+	mcbsp5_ick: mcbsp5_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -922,7 +922,7 @@
 		ti,bit-shift = <10>;
 	};
 
-	mcbsp1_ick: mcbsp1_ick {
+	mcbsp1_ick: mcbsp1_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -930,7 +930,7 @@
 		ti,bit-shift = <9>;
 	};
 
-	omapctrl_ick: omapctrl_ick {
+	omapctrl_ick: omapctrl_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -938,7 +938,7 @@
 		ti,bit-shift = <6>;
 	};
 
-	dss_tv_fck: dss_tv_fck {
+	dss_tv_fck: dss_tv_fck@e00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&omap_54m_fck>;
@@ -946,7 +946,7 @@
 		ti,bit-shift = <2>;
 	};
 
-	dss_96m_fck: dss_96m_fck {
+	dss_96m_fck: dss_96m_fck@e00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&omap_96m_fck>;
@@ -954,7 +954,7 @@
 		ti,bit-shift = <2>;
 	};
 
-	dss2_alwon_fck: dss2_alwon_fck {
+	dss2_alwon_fck: dss2_alwon_fck@e00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_ck>;
@@ -968,7 +968,7 @@
 		clock-frequency = <0>;
 	};
 
-	gpt1_gate_fck: gpt1_gate_fck {
+	gpt1_gate_fck: gpt1_gate_fck@c00 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -976,7 +976,7 @@
 		reg = <0x0c00>;
 	};
 
-	gpt1_mux_fck: gpt1_mux_fck {
+	gpt1_mux_fck: gpt1_mux_fck@c40 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -989,7 +989,7 @@
 		clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
 	};
 
-	aes2_ick: aes2_ick {
+	aes2_ick: aes2_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -1005,7 +1005,7 @@
 		clock-div = <1>;
 	};
 
-	gpio1_dbck: gpio1_dbck {
+	gpio1_dbck: gpio1_dbck@c00 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&wkup_32k_fck>;
@@ -1013,7 +1013,7 @@
 		ti,bit-shift = <3>;
 	};
 
-	sha12_ick: sha12_ick {
+	sha12_ick: sha12_ick@a10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&core_l4_ick>;
@@ -1021,7 +1021,7 @@
 		ti,bit-shift = <27>;
 	};
 
-	wdt2_fck: wdt2_fck {
+	wdt2_fck: wdt2_fck@c00 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&wkup_32k_fck>;
@@ -1029,7 +1029,7 @@
 		ti,bit-shift = <5>;
 	};
 
-	wdt2_ick: wdt2_ick {
+	wdt2_ick: wdt2_ick@c10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&wkup_l4_ick>;
@@ -1037,7 +1037,7 @@
 		ti,bit-shift = <5>;
 	};
 
-	wdt1_ick: wdt1_ick {
+	wdt1_ick: wdt1_ick@c10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&wkup_l4_ick>;
@@ -1045,7 +1045,7 @@
 		ti,bit-shift = <4>;
 	};
 
-	gpio1_ick: gpio1_ick {
+	gpio1_ick: gpio1_ick@c10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&wkup_l4_ick>;
@@ -1053,7 +1053,7 @@
 		ti,bit-shift = <3>;
 	};
 
-	omap_32ksync_ick: omap_32ksync_ick {
+	omap_32ksync_ick: omap_32ksync_ick@c10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&wkup_l4_ick>;
@@ -1061,7 +1061,7 @@
 		ti,bit-shift = <2>;
 	};
 
-	gpt12_ick: gpt12_ick {
+	gpt12_ick: gpt12_ick@c10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&wkup_l4_ick>;
@@ -1069,7 +1069,7 @@
 		ti,bit-shift = <1>;
 	};
 
-	gpt1_ick: gpt1_ick {
+	gpt1_ick: gpt1_ick@c10 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&wkup_l4_ick>;
@@ -1093,7 +1093,7 @@
 		clock-div = <1>;
 	};
 
-	uart3_fck: uart3_fck {
+	uart3_fck: uart3_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&per_48m_fck>;
@@ -1101,7 +1101,7 @@
 		ti,bit-shift = <11>;
 	};
 
-	gpt2_gate_fck: gpt2_gate_fck {
+	gpt2_gate_fck: gpt2_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -1109,7 +1109,7 @@
 		reg = <0x1000>;
 	};
 
-	gpt2_mux_fck: gpt2_mux_fck {
+	gpt2_mux_fck: gpt2_mux_fck@1040 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1122,7 +1122,7 @@
 		clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
 	};
 
-	gpt3_gate_fck: gpt3_gate_fck {
+	gpt3_gate_fck: gpt3_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -1130,7 +1130,7 @@
 		reg = <0x1000>;
 	};
 
-	gpt3_mux_fck: gpt3_mux_fck {
+	gpt3_mux_fck: gpt3_mux_fck@1040 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1144,7 +1144,7 @@
 		clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
 	};
 
-	gpt4_gate_fck: gpt4_gate_fck {
+	gpt4_gate_fck: gpt4_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -1152,7 +1152,7 @@
 		reg = <0x1000>;
 	};
 
-	gpt4_mux_fck: gpt4_mux_fck {
+	gpt4_mux_fck: gpt4_mux_fck@1040 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1166,7 +1166,7 @@
 		clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
 	};
 
-	gpt5_gate_fck: gpt5_gate_fck {
+	gpt5_gate_fck: gpt5_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -1174,7 +1174,7 @@
 		reg = <0x1000>;
 	};
 
-	gpt5_mux_fck: gpt5_mux_fck {
+	gpt5_mux_fck: gpt5_mux_fck@1040 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1188,7 +1188,7 @@
 		clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
 	};
 
-	gpt6_gate_fck: gpt6_gate_fck {
+	gpt6_gate_fck: gpt6_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -1196,7 +1196,7 @@
 		reg = <0x1000>;
 	};
 
-	gpt6_mux_fck: gpt6_mux_fck {
+	gpt6_mux_fck: gpt6_mux_fck@1040 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1210,7 +1210,7 @@
 		clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
 	};
 
-	gpt7_gate_fck: gpt7_gate_fck {
+	gpt7_gate_fck: gpt7_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -1218,7 +1218,7 @@
 		reg = <0x1000>;
 	};
 
-	gpt7_mux_fck: gpt7_mux_fck {
+	gpt7_mux_fck: gpt7_mux_fck@1040 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1232,7 +1232,7 @@
 		clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
 	};
 
-	gpt8_gate_fck: gpt8_gate_fck {
+	gpt8_gate_fck: gpt8_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -1240,7 +1240,7 @@
 		reg = <0x1000>;
 	};
 
-	gpt8_mux_fck: gpt8_mux_fck {
+	gpt8_mux_fck: gpt8_mux_fck@1040 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1254,7 +1254,7 @@
 		clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
 	};
 
-	gpt9_gate_fck: gpt9_gate_fck {
+	gpt9_gate_fck: gpt9_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&sys_ck>;
@@ -1262,7 +1262,7 @@
 		reg = <0x1000>;
 	};
 
-	gpt9_mux_fck: gpt9_mux_fck {
+	gpt9_mux_fck: gpt9_mux_fck@1040 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&omap_32k_fck>, <&sys_ck>;
@@ -1284,7 +1284,7 @@
 		clock-div = <1>;
 	};
 
-	gpio6_dbck: gpio6_dbck {
+	gpio6_dbck: gpio6_dbck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&per_32k_alwon_fck>;
@@ -1292,7 +1292,7 @@
 		ti,bit-shift = <17>;
 	};
 
-	gpio5_dbck: gpio5_dbck {
+	gpio5_dbck: gpio5_dbck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&per_32k_alwon_fck>;
@@ -1300,7 +1300,7 @@
 		ti,bit-shift = <16>;
 	};
 
-	gpio4_dbck: gpio4_dbck {
+	gpio4_dbck: gpio4_dbck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&per_32k_alwon_fck>;
@@ -1308,7 +1308,7 @@
 		ti,bit-shift = <15>;
 	};
 
-	gpio3_dbck: gpio3_dbck {
+	gpio3_dbck: gpio3_dbck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&per_32k_alwon_fck>;
@@ -1316,7 +1316,7 @@
 		ti,bit-shift = <14>;
 	};
 
-	gpio2_dbck: gpio2_dbck {
+	gpio2_dbck: gpio2_dbck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&per_32k_alwon_fck>;
@@ -1324,7 +1324,7 @@
 		ti,bit-shift = <13>;
 	};
 
-	wdt3_fck: wdt3_fck {
+	wdt3_fck: wdt3_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,wait-gate-clock";
 		clocks = <&per_32k_alwon_fck>;
@@ -1340,7 +1340,7 @@
 		clock-div = <1>;
 	};
 
-	gpio6_ick: gpio6_ick {
+	gpio6_ick: gpio6_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1348,7 +1348,7 @@
 		ti,bit-shift = <17>;
 	};
 
-	gpio5_ick: gpio5_ick {
+	gpio5_ick: gpio5_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1356,7 +1356,7 @@
 		ti,bit-shift = <16>;
 	};
 
-	gpio4_ick: gpio4_ick {
+	gpio4_ick: gpio4_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1364,7 +1364,7 @@
 		ti,bit-shift = <15>;
 	};
 
-	gpio3_ick: gpio3_ick {
+	gpio3_ick: gpio3_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1372,7 +1372,7 @@
 		ti,bit-shift = <14>;
 	};
 
-	gpio2_ick: gpio2_ick {
+	gpio2_ick: gpio2_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1380,7 +1380,7 @@
 		ti,bit-shift = <13>;
 	};
 
-	wdt3_ick: wdt3_ick {
+	wdt3_ick: wdt3_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1388,7 +1388,7 @@
 		ti,bit-shift = <12>;
 	};
 
-	uart3_ick: uart3_ick {
+	uart3_ick: uart3_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1396,7 +1396,7 @@
 		ti,bit-shift = <11>;
 	};
 
-	uart4_ick: uart4_ick {
+	uart4_ick: uart4_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1404,7 +1404,7 @@
 		ti,bit-shift = <18>;
 	};
 
-	gpt9_ick: gpt9_ick {
+	gpt9_ick: gpt9_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1412,7 +1412,7 @@
 		ti,bit-shift = <10>;
 	};
 
-	gpt8_ick: gpt8_ick {
+	gpt8_ick: gpt8_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1420,7 +1420,7 @@
 		ti,bit-shift = <9>;
 	};
 
-	gpt7_ick: gpt7_ick {
+	gpt7_ick: gpt7_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1428,7 +1428,7 @@
 		ti,bit-shift = <8>;
 	};
 
-	gpt6_ick: gpt6_ick {
+	gpt6_ick: gpt6_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1436,7 +1436,7 @@
 		ti,bit-shift = <7>;
 	};
 
-	gpt5_ick: gpt5_ick {
+	gpt5_ick: gpt5_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1444,7 +1444,7 @@
 		ti,bit-shift = <6>;
 	};
 
-	gpt4_ick: gpt4_ick {
+	gpt4_ick: gpt4_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1452,7 +1452,7 @@
 		ti,bit-shift = <5>;
 	};
 
-	gpt3_ick: gpt3_ick {
+	gpt3_ick: gpt3_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1460,7 +1460,7 @@
 		ti,bit-shift = <4>;
 	};
 
-	gpt2_ick: gpt2_ick {
+	gpt2_ick: gpt2_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1468,7 +1468,7 @@
 		ti,bit-shift = <3>;
 	};
 
-	mcbsp2_ick: mcbsp2_ick {
+	mcbsp2_ick: mcbsp2_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1476,7 +1476,7 @@
 		ti,bit-shift = <0>;
 	};
 
-	mcbsp3_ick: mcbsp3_ick {
+	mcbsp3_ick: mcbsp3_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1484,7 +1484,7 @@
 		ti,bit-shift = <1>;
 	};
 
-	mcbsp4_ick: mcbsp4_ick {
+	mcbsp4_ick: mcbsp4_ick@1010 {
 		#clock-cells = <0>;
 		compatible = "ti,omap3-interface-clock";
 		clocks = <&per_l4_ick>;
@@ -1492,7 +1492,7 @@
 		ti,bit-shift = <2>;
 	};
 
-	mcbsp2_gate_fck: mcbsp2_gate_fck {
+	mcbsp2_gate_fck: mcbsp2_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -1500,7 +1500,7 @@
 		reg = <0x1000>;
 	};
 
-	mcbsp3_gate_fck: mcbsp3_gate_fck {
+	mcbsp3_gate_fck: mcbsp3_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -1508,7 +1508,7 @@
 		reg = <0x1000>;
 	};
 
-	mcbsp4_gate_fck: mcbsp4_gate_fck {
+	mcbsp4_gate_fck: mcbsp4_gate_fck@1000 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-gate-clock";
 		clocks = <&mcbsp_clks>;
@@ -1516,7 +1516,7 @@
 		reg = <0x1000>;
 	};
 
-	emu_src_mux_ck: emu_src_mux_ck {
+	emu_src_mux_ck: emu_src_mux_ck@1140 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
@@ -1529,7 +1529,7 @@
 		clocks = <&emu_src_mux_ck>;
 	};
 
-	pclk_fck: pclk_fck {
+	pclk_fck: pclk_fck@1140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&emu_src_ck>;
@@ -1539,7 +1539,7 @@
 		ti,index-starts-at-one;
 	};
 
-	pclkx2_fck: pclkx2_fck {
+	pclkx2_fck: pclkx2_fck@1140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&emu_src_ck>;
@@ -1549,7 +1549,7 @@
 		ti,index-starts-at-one;
 	};
 
-	atclk_fck: atclk_fck {
+	atclk_fck: atclk_fck@1140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&emu_src_ck>;
@@ -1559,7 +1559,7 @@
 		ti,index-starts-at-one;
 	};
 
-	traceclk_src_fck: traceclk_src_fck {
+	traceclk_src_fck: traceclk_src_fck@1140 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
@@ -1567,7 +1567,7 @@
 		reg = <0x1140>;
 	};
 
-	traceclk_fck: traceclk_fck {
+	traceclk_fck: traceclk_fck@1140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&traceclk_src_fck>;
diff --git a/sys/gnu/dts/arm/omap4-kc1.dts b/sys/gnu/dts/arm/omap4-kc1.dts
new file mode 100644
index 000000000000..2251bd54e4e6
--- /dev/null
+++ b/sys/gnu/dts/arm/omap4-kc1.dts
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap443x.dtsi"
+
+/ {
+	model = "Amazon Kindle Fire (first generation)";
+	compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x20000000>; /* 512 MB */
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		green {
+			label = "green";
+			pwms = <&twl_pwm 0 7812500>;
+			max-brightness = <127>;
+		};
+
+		orange {
+			label = "orange";
+			pwms = <&twl_pwm 1 7812500>;
+			max-brightness = <127>;
+		};
+	};
+};
+
+&omap4_pmx_core {
+	pinctrl-names = "default";
+
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0)		/* uart3_rx_irrx */
+			OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
+			OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
+		>;
+	};
+
+	i2c2_pins: pinmux_i2c2_pins {
+		pinctrl-single,pins = <
+			OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_scl */
+			OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_sda */
+		>;
+	};
+
+	i2c3_pins: pinmux_i2c3_pins {
+		pinctrl-single,pins = <
+			OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_scl */
+			OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_sda */
+		>;
+	};
+
+	i2c4_pins: pinmux_i2c4_pins {
+		pinctrl-single,pins = <
+			OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_scl */
+			OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_sda */
+		>;
+	};
+
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat0 */
+			OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat1 */
+			OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat2 */
+			OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat3 */
+			OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat4 */
+			OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat5 */
+			OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat6 */
+			OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat7 */
+			OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_clk */
+			OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_cmd */
+		>;
+	};
+
+	usb_otg_hs_pins: pinmux_usb_otg_hs_pins {
+		pinctrl-single,pins = <
+			OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* usba0_otg_ce */
+			OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0)		/* usba0_otg_dp */
+			OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0)		/* usba0_otg_dm */
+		>;
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+
+	interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+			       &omap4_pmx_core OMAP4_UART3_RX>;
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+
+	clock-frequency = <400000>;
+
+	twl: twl@48 {
+		reg = <0x48>;
+		/* IRQ# = 7 */
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
+
+		twl_power: power {
+			compatible = "ti,twl6030-power";
+			ti,system-power-controller;
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+
+	clock-frequency = <400000>;
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+
+	clock-frequency = <400000>;
+};
+
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c4_pins>;
+
+	clock-frequency = <400000>;
+};
+
+&mmc1 {
+	status = "disabled";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+
+	vmmc-supply = <&vaux1>;
+	ti,non-removable;
+	bus-width = <8>;
+};
+
+&mmc3 {
+	status = "disabled";
+};
+
+&mmc4 {
+	status = "disabled";
+};
+
+&usb_otg_hs {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb_otg_hs_pins>;
+
+	interface-type = <1>;
+	mode = <3>;
+	power = <50>;
+};
+
+#include "twl6030.dtsi"
+#include "twl6030_omap4.dtsi"
+
+&twl_usb_comparator {
+	usb-supply = <&vusb>;
+};
diff --git a/sys/gnu/dts/arm/omap4-var-som-om44.dtsi b/sys/gnu/dts/arm/omap4-var-som-om44.dtsi
index 49d032b846be..a17997f4e9aa 100644
--- a/sys/gnu/dts/arm/omap4-var-som-om44.dtsi
+++ b/sys/gnu/dts/arm/omap4-var-som-om44.dtsi
@@ -17,7 +17,7 @@
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
 
-	sound: sound@0 {
+	sound: sound {
 		compatible = "ti,abe-twl6040";
 		ti,model = "VAR-SOM-OM44";
 
diff --git a/sys/gnu/dts/arm/omap4.dtsi b/sys/gnu/dts/arm/omap4.dtsi
index 2bd9c83300b2..3fdc51cd0fad 100644
--- a/sys/gnu/dts/arm/omap4.dtsi
+++ b/sys/gnu/dts/arm/omap4.dtsi
@@ -70,7 +70,7 @@
 		compatible = "arm,cortex-a9-twd-timer";
 		clocks = <&mpu_periphclk>;
 		reg = <0x48240600 0x20>;
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
 		interrupt-parent = <&gic>;
 	};
 
@@ -198,7 +198,7 @@
 					#size-cells = <1>;
 					ranges = <0 0x5a0 0x170>;
 
-					pbias_regulator: pbias_regulator {
+					pbias_regulator: pbias_regulator@60 {
 						compatible = "ti,pbias-omap4", "ti,pbias-omap";
 						reg = <0x60 0x4>;
 						syscon = <&omap4_padconf_global>;
@@ -370,6 +370,10 @@
 			ti,no-idle-on-init;
 			clocks = <&l3_div_ck>;
 			clock-names = "fck";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 		};
 
 		uart1: serial@4806a000 {
diff --git a/sys/gnu/dts/arm/omap443x-clocks.dtsi b/sys/gnu/dts/arm/omap443x-clocks.dtsi
index 2bd2166f88d3..f370d96a87e5 100644
--- a/sys/gnu/dts/arm/omap443x-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap443x-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &prm_clocks {
-	bandgap_fclk: bandgap_fclk {
+	bandgap_fclk: bandgap_fclk@1888 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
diff --git a/sys/gnu/dts/arm/omap443x.dtsi b/sys/gnu/dts/arm/omap443x.dtsi
index 0adfa1d1ef20..fc6a8610c24c 100644
--- a/sys/gnu/dts/arm/omap443x.dtsi
+++ b/sys/gnu/dts/arm/omap443x.dtsi
@@ -35,7 +35,7 @@
 	};
 
 	ocp {
-		bandgap: bandgap {
+		bandgap: bandgap@4a002260 {
 			reg = <0x4a002260 0x4
 			       0x4a00232C 0x4>;
 			compatible = "ti,omap4430-bandgap";
diff --git a/sys/gnu/dts/arm/omap4460.dtsi b/sys/gnu/dts/arm/omap4460.dtsi
index 5fa68f191af7..ef66e12e0a67 100644
--- a/sys/gnu/dts/arm/omap4460.dtsi
+++ b/sys/gnu/dts/arm/omap4460.dtsi
@@ -40,7 +40,7 @@
 	};
 
 	ocp {
-		bandgap: bandgap {
+		bandgap: bandgap@4a002260 {
 			reg = <0x4a002260 0x4
 			       0x4a00232C 0x4
 			       0x4a002378 0x18>;
diff --git a/sys/gnu/dts/arm/omap446x-clocks.dtsi b/sys/gnu/dts/arm/omap446x-clocks.dtsi
index be033e9803e9..fb5929b742d4 100644
--- a/sys/gnu/dts/arm/omap446x-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap446x-clocks.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 &prm_clocks {
-	div_ts_ck: div_ts_ck {
+	div_ts_ck: div_ts_ck@1888 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&l4_wkup_clk_mux_ck>;
@@ -17,7 +17,7 @@
 		ti,dividers = <8>, <16>, <32>;
 	};
 
-	bandgap_ts_fclk: bandgap_ts_fclk {
+	bandgap_ts_fclk: bandgap_ts_fclk@1888 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&div_ts_ck>;
diff --git a/sys/gnu/dts/arm/omap44xx-clocks.dtsi b/sys/gnu/dts/arm/omap44xx-clocks.dtsi
index f2c48f09824e..9573b37fbaa7 100644
--- a/sys/gnu/dts/arm/omap44xx-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap44xx-clocks.dtsi
@@ -20,7 +20,7 @@
 		clock-frequency = <12000000>;
 	};
 
-	pad_clks_ck: pad_clks_ck {
+	pad_clks_ck: pad_clks_ck@108 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&pad_clks_src_ck>;
@@ -46,7 +46,7 @@
 		clock-frequency = <12000000>;
 	};
 
-	slimbus_clk: slimbus_clk {
+	slimbus_clk: slimbus_clk@108 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&slimbus_src_clk>;
@@ -132,21 +132,21 @@
 		clock-frequency = <60000000>;
 	};
 
-	dpll_abe_ck: dpll_abe_ck {
+	dpll_abe_ck: dpll_abe_ck@1e0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-m4xen-clock";
 		clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
 		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 	};
 
-	dpll_abe_x2_ck: dpll_abe_x2_ck {
+	dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-x2-clock";
 		clocks = <&dpll_abe_ck>;
 		reg = <0x01f0>;
 	};
 
-	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_x2_ck>;
@@ -165,7 +165,7 @@
 		clock-div = <8>;
 	};
 
-	abe_clk: abe_clk {
+	abe_clk: abe_clk@108 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2x2_ck>;
@@ -174,7 +174,7 @@
 		ti,index-power-of-two;
 	};
 
-	aess_fclk: aess_fclk {
+	aess_fclk: aess_fclk@528 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&abe_clk>;
@@ -183,7 +183,7 @@
 		reg = <0x0528>;
 	};
 
-	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_x2_ck>;
@@ -194,7 +194,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck {
+	core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
@@ -202,7 +202,7 @@
 		reg = <0x012c>;
 	};
 
-	dpll_core_ck: dpll_core_ck {
+	dpll_core_ck: dpll_core_ck@120 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-core-clock";
 		clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
@@ -215,7 +215,7 @@
 		clocks = <&dpll_core_ck>;
 	};
 
-	dpll_core_m6x2_ck: dpll_core_m6x2_ck {
+	dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -226,7 +226,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_core_m2_ck: dpll_core_m2_ck {
+	dpll_core_m2_ck: dpll_core_m2_ck@130 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_ck>;
@@ -245,7 +245,7 @@
 		clock-div = <2>;
 	};
 
-	dpll_core_m5x2_ck: dpll_core_m5x2_ck {
+	dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -256,7 +256,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	div_core_ck: div_core_ck {
+	div_core_ck: div_core_ck@100 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_m5x2_ck>;
@@ -264,7 +264,7 @@
 		ti,max-div = <2>;
 	};
 
-	div_iva_hs_clk: div_iva_hs_clk {
+	div_iva_hs_clk: div_iva_hs_clk@1dc {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_m5x2_ck>;
@@ -273,7 +273,7 @@
 		ti,index-power-of-two;
 	};
 
-	div_mpu_hs_clk: div_mpu_hs_clk {
+	div_mpu_hs_clk: div_mpu_hs_clk@19c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_m5x2_ck>;
@@ -282,7 +282,7 @@
 		ti,index-power-of-two;
 	};
 
-	dpll_core_m4x2_ck: dpll_core_m4x2_ck {
+	dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -301,7 +301,7 @@
 		clock-div = <2>;
 	};
 
-	dpll_abe_m2_ck: dpll_abe_m2_ck {
+	dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_ck>;
@@ -310,7 +310,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck {
+	dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -318,7 +318,7 @@
 		reg = <0x0134>;
 	};
 
-	dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
+	dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -333,7 +333,7 @@
 		clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
 	};
 
-	dpll_core_m7x2_ck: dpll_core_m7x2_ck {
+	dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -344,7 +344,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck {
+	iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
@@ -352,7 +352,7 @@
 		reg = <0x01ac>;
 	};
 
-	dpll_iva_ck: dpll_iva_ck {
+	dpll_iva_ck: dpll_iva_ck@1a0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
@@ -365,7 +365,7 @@
 		clocks = <&dpll_iva_ck>;
 	};
 
-	dpll_iva_m4x2_ck: dpll_iva_m4x2_ck {
+	dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_iva_x2_ck>;
@@ -376,7 +376,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_iva_m5x2_ck: dpll_iva_m5x2_ck {
+	dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_iva_x2_ck>;
@@ -387,14 +387,14 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_mpu_ck: dpll_mpu_ck {
+	dpll_mpu_ck: dpll_mpu_ck@160 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
 		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 	};
 
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_mpu_ck>;
@@ -421,7 +421,7 @@
 		clock-div = <3>;
 	};
 
-	l3_div_ck: l3_div_ck {
+	l3_div_ck: l3_div_ck@100 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&div_core_ck>;
@@ -430,7 +430,7 @@
 		reg = <0x0100>;
 	};
 
-	l4_div_ck: l4_div_ck {
+	l4_div_ck: l4_div_ck@100 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&l3_div_ck>;
@@ -455,7 +455,7 @@
 		clock-div = <2>;
 	};
 
-	ocp_abe_iclk: ocp_abe_iclk {
+	ocp_abe_iclk: ocp_abe_iclk@528 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&aess_fclk>;
@@ -472,7 +472,7 @@
 		clock-div = <4>;
 	};
 
-	dmic_sync_mux_ck: dmic_sync_mux_ck {
+	dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
@@ -480,7 +480,7 @@
 		reg = <0x0538>;
 	};
 
-	func_dmic_abe_gfclk: func_dmic_abe_gfclk {
+	func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -488,7 +488,7 @@
 		reg = <0x0538>;
 	};
 
-	mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+	mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
@@ -496,7 +496,7 @@
 		reg = <0x0540>;
 	};
 
-	func_mcasp_abe_gfclk: func_mcasp_abe_gfclk {
+	func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -504,7 +504,7 @@
 		reg = <0x0540>;
 	};
 
-	mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+	mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
@@ -512,7 +512,7 @@
 		reg = <0x0548>;
 	};
 
-	func_mcbsp1_gfclk: func_mcbsp1_gfclk {
+	func_mcbsp1_gfclk: func_mcbsp1_gfclk@548 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -520,7 +520,7 @@
 		reg = <0x0548>;
 	};
 
-	mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+	mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
@@ -528,7 +528,7 @@
 		reg = <0x0550>;
 	};
 
-	func_mcbsp2_gfclk: func_mcbsp2_gfclk {
+	func_mcbsp2_gfclk: func_mcbsp2_gfclk@550 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -536,7 +536,7 @@
 		reg = <0x0550>;
 	};
 
-	mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+	mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
@@ -544,7 +544,7 @@
 		reg = <0x0558>;
 	};
 
-	func_mcbsp3_gfclk: func_mcbsp3_gfclk {
+	func_mcbsp3_gfclk: func_mcbsp3_gfclk@558 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -552,7 +552,7 @@
 		reg = <0x0558>;
 	};
 
-	slimbus1_fclk_1: slimbus1_fclk_1 {
+	slimbus1_fclk_1: slimbus1_fclk_1@560 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_24m_clk>;
@@ -560,7 +560,7 @@
 		reg = <0x0560>;
 	};
 
-	slimbus1_fclk_0: slimbus1_fclk_0 {
+	slimbus1_fclk_0: slimbus1_fclk_0@560 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&abe_24m_fclk>;
@@ -568,7 +568,7 @@
 		reg = <0x0560>;
 	};
 
-	slimbus1_fclk_2: slimbus1_fclk_2 {
+	slimbus1_fclk_2: slimbus1_fclk_2@560 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&pad_clks_ck>;
@@ -576,7 +576,7 @@
 		reg = <0x0560>;
 	};
 
-	slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+	slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&slimbus_clk>;
@@ -584,7 +584,7 @@
 		reg = <0x0560>;
 	};
 
-	timer5_sync_mux: timer5_sync_mux {
+	timer5_sync_mux: timer5_sync_mux@568 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
@@ -592,7 +592,7 @@
 		reg = <0x0568>;
 	};
 
-	timer6_sync_mux: timer6_sync_mux {
+	timer6_sync_mux: timer6_sync_mux@570 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
@@ -600,7 +600,7 @@
 		reg = <0x0570>;
 	};
 
-	timer7_sync_mux: timer7_sync_mux {
+	timer7_sync_mux: timer7_sync_mux@578 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
@@ -608,7 +608,7 @@
 		reg = <0x0578>;
 	};
 
-	timer8_sync_mux: timer8_sync_mux {
+	timer8_sync_mux: timer8_sync_mux@580 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
@@ -623,7 +623,7 @@
 	};
 };
 &prm_clocks {
-	sys_clkin_ck: sys_clkin_ck {
+	sys_clkin_ck: sys_clkin_ck@110 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -631,7 +631,7 @@
 		ti,index-starts-at-one;
 	};
 
-	abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck {
+	abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -639,7 +639,7 @@
 		reg = <0x0108>;
 	};
 
-	abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck {
+	abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -654,14 +654,14 @@
 		clock-div = <1>;
 	};
 
-	l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck {
+	l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
 		reg = <0x0108>;
 	};
 
-	syc_clk_div_ck: syc_clk_div_ck {
+	syc_clk_div_ck: syc_clk_div_ck@100 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&sys_clkin_ck>;
@@ -669,7 +669,7 @@
 		ti,max-div = <2>;
 	};
 
-	gpio1_dbclk: gpio1_dbclk {
+	gpio1_dbclk: gpio1_dbclk@1838 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -677,7 +677,7 @@
 		reg = <0x1838>;
 	};
 
-	dmt1_clk_mux: dmt1_clk_mux {
+	dmt1_clk_mux: dmt1_clk_mux@1840 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -685,7 +685,7 @@
 		reg = <0x1840>;
 	};
 
-	usim_ck: usim_ck {
+	usim_ck: usim_ck@1858 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_m4x2_ck>;
@@ -694,7 +694,7 @@
 		ti,dividers = <14>, <18>;
 	};
 
-	usim_fclk: usim_fclk {
+	usim_fclk: usim_fclk@1858 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&usim_ck>;
@@ -702,7 +702,7 @@
 		reg = <0x1858>;
 	};
 
-	pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck {
+	pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@1a20 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
@@ -710,7 +710,7 @@
 		reg = <0x1a20>;
 	};
 
-	pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck {
+	pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@1a20 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
@@ -718,7 +718,7 @@
 		reg = <0x1a20>;
 	};
 
-	stm_clk_div_ck: stm_clk_div_ck {
+	stm_clk_div_ck: stm_clk_div_ck@1a20 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&pmd_stm_clock_mux_ck>;
@@ -728,7 +728,7 @@
 		ti,index-power-of-two;
 	};
 
-	trace_clk_div_div_ck: trace_clk_div_div_ck {
+	trace_clk_div_div_ck: trace_clk_div_div_ck@1a20 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&pmd_trace_clk_mux_ck>;
@@ -752,7 +752,7 @@
 };
 
 &cm2_clocks {
-	per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck {
+	per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
@@ -760,14 +760,14 @@
 		reg = <0x014c>;
 	};
 
-	dpll_per_ck: dpll_per_ck {
+	dpll_per_ck: dpll_per_ck@140 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
 		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
 	};
 
-	dpll_per_m2_ck: dpll_per_m2_ck {
+	dpll_per_m2_ck: dpll_per_m2_ck@150 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_ck>;
@@ -776,14 +776,14 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_per_x2_ck: dpll_per_x2_ck {
+	dpll_per_x2_ck: dpll_per_x2_ck@150 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-x2-clock";
 		clocks = <&dpll_per_ck>;
 		reg = <0x0150>;
 	};
 
-	dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -794,7 +794,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck {
+	dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -802,7 +802,7 @@
 		reg = <0x0154>;
 	};
 
-	dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck {
+	dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -817,7 +817,7 @@
 		clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
 	};
 
-	dpll_per_m4x2_ck: dpll_per_m4x2_ck {
+	dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -828,7 +828,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_m5x2_ck: dpll_per_m5x2_ck {
+	dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -839,7 +839,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_m6x2_ck: dpll_per_m6x2_ck {
+	dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -850,7 +850,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_per_m7x2_ck: dpll_per_m7x2_ck {
+	dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -861,14 +861,14 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_usb_ck: dpll_usb_ck {
+	dpll_usb_ck: dpll_usb_ck@180 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-j-type-clock";
 		clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
 		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
 	};
 
-	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
 		#clock-cells = <0>;
 		compatible = "ti,fixed-factor-clock";
 		clocks = <&dpll_usb_ck>;
@@ -879,7 +879,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	dpll_usb_m2_ck: dpll_usb_m2_ck {
+	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_ck>;
@@ -890,7 +890,7 @@
 		ti,invert-autoidle-bit;
 	};
 
-	ducati_clk_mux_ck: ducati_clk_mux_ck {
+	ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
@@ -921,7 +921,7 @@
 		clock-div = <8>;
 	};
 
-	func_48m_fclk: func_48m_fclk {
+	func_48m_fclk: func_48m_fclk@108 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_m2x2_ck>;
@@ -937,7 +937,7 @@
 		clock-div = <4>;
 	};
 
-	func_64m_fclk: func_64m_fclk {
+	func_64m_fclk: func_64m_fclk@108 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_m4x2_ck>;
@@ -945,7 +945,7 @@
 		ti,dividers = <2>, <4>;
 	};
 
-	func_96m_fclk: func_96m_fclk {
+	func_96m_fclk: func_96m_fclk@108 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_m2x2_ck>;
@@ -953,7 +953,7 @@
 		ti,dividers = <2>, <4>;
 	};
 
-	init_60m_fclk: init_60m_fclk {
+	init_60m_fclk: init_60m_fclk@104 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -961,7 +961,7 @@
 		ti,dividers = <1>, <8>;
 	};
 
-	per_abe_nc_fclk: per_abe_nc_fclk {
+	per_abe_nc_fclk: per_abe_nc_fclk@108 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2_ck>;
@@ -969,7 +969,7 @@
 		ti,max-div = <2>;
 	};
 
-	aes1_fck: aes1_fck {
+	aes1_fck: aes1_fck@15a0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3_div_ck>;
@@ -977,7 +977,7 @@
 		reg = <0x15a0>;
 	};
 
-	aes2_fck: aes2_fck {
+	aes2_fck: aes2_fck@15a8 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3_div_ck>;
@@ -985,7 +985,7 @@
 		reg = <0x15a8>;
 	};
 
-	dss_sys_clk: dss_sys_clk {
+	dss_sys_clk: dss_sys_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&syc_clk_div_ck>;
@@ -993,7 +993,7 @@
 		reg = <0x1120>;
 	};
 
-	dss_tv_clk: dss_tv_clk {
+	dss_tv_clk: dss_tv_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&extalt_clkin_ck>;
@@ -1001,7 +1001,7 @@
 		reg = <0x1120>;
 	};
 
-	dss_dss_clk: dss_dss_clk {
+	dss_dss_clk: dss_dss_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_per_m5x2_ck>;
@@ -1010,7 +1010,7 @@
 		ti,set-rate-parent;
 	};
 
-	dss_48mhz_clk: dss_48mhz_clk {
+	dss_48mhz_clk: dss_48mhz_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_48mc_fclk>;
@@ -1018,7 +1018,7 @@
 		reg = <0x1120>;
 	};
 
-	fdif_fck: fdif_fck {
+	fdif_fck: fdif_fck@1028 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_m4x2_ck>;
@@ -1028,7 +1028,7 @@
 		ti,index-power-of-two;
 	};
 
-	gpio2_dbclk: gpio2_dbclk {
+	gpio2_dbclk: gpio2_dbclk@1460 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1036,7 +1036,7 @@
 		reg = <0x1460>;
 	};
 
-	gpio3_dbclk: gpio3_dbclk {
+	gpio3_dbclk: gpio3_dbclk@1468 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1044,7 +1044,7 @@
 		reg = <0x1468>;
 	};
 
-	gpio4_dbclk: gpio4_dbclk {
+	gpio4_dbclk: gpio4_dbclk@1470 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1052,7 +1052,7 @@
 		reg = <0x1470>;
 	};
 
-	gpio5_dbclk: gpio5_dbclk {
+	gpio5_dbclk: gpio5_dbclk@1478 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1060,7 +1060,7 @@
 		reg = <0x1478>;
 	};
 
-	gpio6_dbclk: gpio6_dbclk {
+	gpio6_dbclk: gpio6_dbclk@1480 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1068,7 +1068,7 @@
 		reg = <0x1480>;
 	};
 
-	sgx_clk_mux: sgx_clk_mux {
+	sgx_clk_mux: sgx_clk_mux@1220 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
@@ -1076,7 +1076,7 @@
 		reg = <0x1220>;
 	};
 
-	hsi_fck: hsi_fck {
+	hsi_fck: hsi_fck@1338 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_m2x2_ck>;
@@ -1086,7 +1086,7 @@
 		ti,index-power-of-two;
 	};
 
-	iss_ctrlclk: iss_ctrlclk {
+	iss_ctrlclk: iss_ctrlclk@1020 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_96m_fclk>;
@@ -1094,7 +1094,7 @@
 		reg = <0x1020>;
 	};
 
-	mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck {
+	mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
@@ -1102,7 +1102,7 @@
 		reg = <0x14e0>;
 	};
 
-	per_mcbsp4_gfclk: per_mcbsp4_gfclk {
+	per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
@@ -1110,7 +1110,7 @@
 		reg = <0x14e0>;
 	};
 
-	hsmmc1_fclk: hsmmc1_fclk {
+	hsmmc1_fclk: hsmmc1_fclk@1328 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_64m_fclk>, <&func_96m_fclk>;
@@ -1118,7 +1118,7 @@
 		reg = <0x1328>;
 	};
 
-	hsmmc2_fclk: hsmmc2_fclk {
+	hsmmc2_fclk: hsmmc2_fclk@1330 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_64m_fclk>, <&func_96m_fclk>;
@@ -1126,7 +1126,7 @@
 		reg = <0x1330>;
 	};
 
-	ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m {
+	ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_48m_fclk>;
@@ -1134,7 +1134,7 @@
 		reg = <0x13e0>;
 	};
 
-	sha2md5_fck: sha2md5_fck {
+	sha2md5_fck: sha2md5_fck@15c8 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3_div_ck>;
@@ -1142,7 +1142,7 @@
 		reg = <0x15c8>;
 	};
 
-	slimbus2_fclk_1: slimbus2_fclk_1 {
+	slimbus2_fclk_1: slimbus2_fclk_1@1538 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&per_abe_24m_fclk>;
@@ -1150,7 +1150,7 @@
 		reg = <0x1538>;
 	};
 
-	slimbus2_fclk_0: slimbus2_fclk_0 {
+	slimbus2_fclk_0: slimbus2_fclk_0@1538 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_24mc_fclk>;
@@ -1158,7 +1158,7 @@
 		reg = <0x1538>;
 	};
 
-	slimbus2_slimbus_clk: slimbus2_slimbus_clk {
+	slimbus2_slimbus_clk: slimbus2_slimbus_clk@1538 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&pad_slimbus_core_clks_ck>;
@@ -1166,7 +1166,7 @@
 		reg = <0x1538>;
 	};
 
-	smartreflex_core_fck: smartreflex_core_fck {
+	smartreflex_core_fck: smartreflex_core_fck@638 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4_wkup_clk_mux_ck>;
@@ -1174,7 +1174,7 @@
 		reg = <0x0638>;
 	};
 
-	smartreflex_iva_fck: smartreflex_iva_fck {
+	smartreflex_iva_fck: smartreflex_iva_fck@630 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4_wkup_clk_mux_ck>;
@@ -1182,7 +1182,7 @@
 		reg = <0x0630>;
 	};
 
-	smartreflex_mpu_fck: smartreflex_mpu_fck {
+	smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4_wkup_clk_mux_ck>;
@@ -1190,7 +1190,7 @@
 		reg = <0x0628>;
 	};
 
-	cm2_dm10_mux: cm2_dm10_mux {
+	cm2_dm10_mux: cm2_dm10_mux@1428 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -1198,7 +1198,7 @@
 		reg = <0x1428>;
 	};
 
-	cm2_dm11_mux: cm2_dm11_mux {
+	cm2_dm11_mux: cm2_dm11_mux@1430 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -1206,7 +1206,7 @@
 		reg = <0x1430>;
 	};
 
-	cm2_dm2_mux: cm2_dm2_mux {
+	cm2_dm2_mux: cm2_dm2_mux@1438 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -1214,7 +1214,7 @@
 		reg = <0x1438>;
 	};
 
-	cm2_dm3_mux: cm2_dm3_mux {
+	cm2_dm3_mux: cm2_dm3_mux@1440 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -1222,7 +1222,7 @@
 		reg = <0x1440>;
 	};
 
-	cm2_dm4_mux: cm2_dm4_mux {
+	cm2_dm4_mux: cm2_dm4_mux@1448 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -1230,7 +1230,7 @@
 		reg = <0x1448>;
 	};
 
-	cm2_dm9_mux: cm2_dm9_mux {
+	cm2_dm9_mux: cm2_dm9_mux@1450 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
@@ -1238,7 +1238,7 @@
 		reg = <0x1450>;
 	};
 
-	usb_host_fs_fck: usb_host_fs_fck {
+	usb_host_fs_fck: usb_host_fs_fck@13d0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_48mc_fclk>;
@@ -1246,7 +1246,7 @@
 		reg = <0x13d0>;
 	};
 
-	utmi_p1_gfclk: utmi_p1_gfclk {
+	utmi_p1_gfclk: utmi_p1_gfclk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
@@ -1254,7 +1254,7 @@
 		reg = <0x1358>;
 	};
 
-	usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+	usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&utmi_p1_gfclk>;
@@ -1262,7 +1262,7 @@
 		reg = <0x1358>;
 	};
 
-	utmi_p2_gfclk: utmi_p2_gfclk {
+	utmi_p2_gfclk: utmi_p2_gfclk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
@@ -1270,7 +1270,7 @@
 		reg = <0x1358>;
 	};
 
-	usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+	usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&utmi_p2_gfclk>;
@@ -1278,7 +1278,7 @@
 		reg = <0x1358>;
 	};
 
-	usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+	usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&init_60m_fclk>;
@@ -1286,7 +1286,7 @@
 		reg = <0x1358>;
 	};
 
-	usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+	usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -1294,7 +1294,7 @@
 		reg = <0x1358>;
 	};
 
-	usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+	usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&init_60m_fclk>;
@@ -1302,7 +1302,7 @@
 		reg = <0x1358>;
 	};
 
-	usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+	usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&init_60m_fclk>;
@@ -1310,7 +1310,7 @@
 		reg = <0x1358>;
 	};
 
-	usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+	usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -1318,7 +1318,7 @@
 		reg = <0x1358>;
 	};
 
-	usb_host_hs_func48mclk: usb_host_hs_func48mclk {
+	usb_host_hs_func48mclk: usb_host_hs_func48mclk@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_48mc_fclk>;
@@ -1326,7 +1326,7 @@
 		reg = <0x1358>;
 	};
 
-	usb_host_hs_fck: usb_host_hs_fck {
+	usb_host_hs_fck: usb_host_hs_fck@1358 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&init_60m_fclk>;
@@ -1334,7 +1334,7 @@
 		reg = <0x1358>;
 	};
 
-	otg_60m_gfclk: otg_60m_gfclk {
+	otg_60m_gfclk: otg_60m_gfclk@1360 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
@@ -1342,7 +1342,7 @@
 		reg = <0x1360>;
 	};
 
-	usb_otg_hs_xclk: usb_otg_hs_xclk {
+	usb_otg_hs_xclk: usb_otg_hs_xclk@1360 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&otg_60m_gfclk>;
@@ -1350,7 +1350,7 @@
 		reg = <0x1360>;
 	};
 
-	usb_otg_hs_ick: usb_otg_hs_ick {
+	usb_otg_hs_ick: usb_otg_hs_ick@1360 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3_div_ck>;
@@ -1358,7 +1358,7 @@
 		reg = <0x1360>;
 	};
 
-	usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+	usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1366,7 +1366,7 @@
 		reg = <0x0640>;
 	};
 
-	usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+	usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&init_60m_fclk>;
@@ -1374,7 +1374,7 @@
 		reg = <0x1368>;
 	};
 
-	usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+	usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1368 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&init_60m_fclk>;
@@ -1382,7 +1382,7 @@
 		reg = <0x1368>;
 	};
 
-	usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+	usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1368 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&init_60m_fclk>;
@@ -1390,7 +1390,7 @@
 		reg = <0x1368>;
 	};
 
-	usb_tll_hs_ick: usb_tll_hs_ick {
+	usb_tll_hs_ick: usb_tll_hs_ick@1368 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l4_div_ck>;
@@ -1407,7 +1407,7 @@
 };
 
 &scrm_clocks {
-	auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+	auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1415,7 +1415,7 @@
 		reg = <0x0310>;
 	};
 
-	auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+	auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1429,7 +1429,7 @@
 		clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
 	};
 
-	auxclk0_ck: auxclk0_ck {
+	auxclk0_ck: auxclk0_ck@310 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk0_src_ck>;
@@ -1438,7 +1438,7 @@
 		reg = <0x0310>;
 	};
 
-	auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+	auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1446,7 +1446,7 @@
 		reg = <0x0314>;
 	};
 
-	auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+	auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1460,7 +1460,7 @@
 		clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
 	};
 
-	auxclk1_ck: auxclk1_ck {
+	auxclk1_ck: auxclk1_ck@314 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk1_src_ck>;
@@ -1469,7 +1469,7 @@
 		reg = <0x0314>;
 	};
 
-	auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+	auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1477,7 +1477,7 @@
 		reg = <0x0318>;
 	};
 
-	auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+	auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1491,7 +1491,7 @@
 		clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
 	};
 
-	auxclk2_ck: auxclk2_ck {
+	auxclk2_ck: auxclk2_ck@318 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk2_src_ck>;
@@ -1500,7 +1500,7 @@
 		reg = <0x0318>;
 	};
 
-	auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+	auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1508,7 +1508,7 @@
 		reg = <0x031c>;
 	};
 
-	auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+	auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1522,7 +1522,7 @@
 		clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
 	};
 
-	auxclk3_ck: auxclk3_ck {
+	auxclk3_ck: auxclk3_ck@31c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk3_src_ck>;
@@ -1531,7 +1531,7 @@
 		reg = <0x031c>;
 	};
 
-	auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+	auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1539,7 +1539,7 @@
 		reg = <0x0320>;
 	};
 
-	auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+	auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1553,7 +1553,7 @@
 		clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
 	};
 
-	auxclk4_ck: auxclk4_ck {
+	auxclk4_ck: auxclk4_ck@320 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk4_src_ck>;
@@ -1562,7 +1562,7 @@
 		reg = <0x0320>;
 	};
 
-	auxclk5_src_gate_ck: auxclk5_src_gate_ck {
+	auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1570,7 +1570,7 @@
 		reg = <0x0324>;
 	};
 
-	auxclk5_src_mux_ck: auxclk5_src_mux_ck {
+	auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1584,7 +1584,7 @@
 		clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
 	};
 
-	auxclk5_ck: auxclk5_ck {
+	auxclk5_ck: auxclk5_ck@324 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk5_src_ck>;
@@ -1593,7 +1593,7 @@
 		reg = <0x0324>;
 	};
 
-	auxclkreq0_ck: auxclkreq0_ck {
+	auxclkreq0_ck: auxclkreq0_ck@210 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
@@ -1601,7 +1601,7 @@
 		reg = <0x0210>;
 	};
 
-	auxclkreq1_ck: auxclkreq1_ck {
+	auxclkreq1_ck: auxclkreq1_ck@214 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
@@ -1609,7 +1609,7 @@
 		reg = <0x0214>;
 	};
 
-	auxclkreq2_ck: auxclkreq2_ck {
+	auxclkreq2_ck: auxclkreq2_ck@218 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
@@ -1617,7 +1617,7 @@
 		reg = <0x0218>;
 	};
 
-	auxclkreq3_ck: auxclkreq3_ck {
+	auxclkreq3_ck: auxclkreq3_ck@21c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
@@ -1625,7 +1625,7 @@
 		reg = <0x021c>;
 	};
 
-	auxclkreq4_ck: auxclkreq4_ck {
+	auxclkreq4_ck: auxclkreq4_ck@220 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
@@ -1633,7 +1633,7 @@
 		reg = <0x0220>;
 	};
 
-	auxclkreq5_ck: auxclkreq5_ck {
+	auxclkreq5_ck: auxclkreq5_ck@224 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
diff --git a/sys/gnu/dts/arm/omap5-board-common.dtsi b/sys/gnu/dts/arm/omap5-board-common.dtsi
index 888412c63f97..5d5b620b7d9b 100644
--- a/sys/gnu/dts/arm/omap5-board-common.dtsi
+++ b/sys/gnu/dts/arm/omap5-board-common.dtsi
@@ -14,6 +14,29 @@
 		display0 = &hdmi0;
 	};
 
+	vmain: fixedregulator-vmain {
+		compatible = "regulator-fixed";
+		regulator-name = "vmain";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vsys_cobra: fixedregulator-vsys_cobra {
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_cobra";
+		vin-supply = <&vmain>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vdds_1v8_main: fixedregulator-vdds_1v8_main {
+		compatible = "regulator-fixed";
+		regulator-name = "vdds_1v8_main";
+		vin-supply = <&smps7_reg>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
 	vmmcsd_fixed: fixedregulator-mmcsd {
 		compatible = "regulator-fixed";
 		regulator-name = "vmmcsd_fixed";
@@ -130,6 +153,16 @@
 	};
 };
 
+&gpio8 {
+	/* TI trees use GPIO instead of msecure, see also muxing */
+	p234 {
+		gpio-hog;
+		gpios = <10 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "gpio8_234/msecure";
+	};
+};
+
 &omap5_pmx_core {
 	pinctrl-names = "default";
 	pinctrl-0 = <
@@ -213,6 +246,13 @@
 		>;
 	};
 
+	/* TI trees use GPIO mode; msecure mode does not work reliably? */
+	palmas_msecure_pins: palmas_msecure_pins {
+		pinctrl-single,pins = <
+			OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */
+		>;
+	};
+
 	usbhost_pins: pinmux_usbhost_pins {
 		pinctrl-single,pins = <
 			OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
@@ -278,6 +318,12 @@
 			&usbhost_wkup_pins
 	>;
 
+	palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
+		pinctrl-single,pins = <
+			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */
+		>;
+	};
+
 	usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
 		pinctrl-single,pins = <
 			OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
@@ -286,7 +332,7 @@
 
 	wlcore_irq_pin: pinmux_wlcore_irq_pin {
 		pinctrl-single,pins = <
-			OMAP5_IOPAD(0x40, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE6)	/* llia_wakereqin.gpio1_wk14 */
+			OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6)	/* llia_wakereqin.gpio1_wk14 */
 		>;
 	};
 };
@@ -345,6 +391,8 @@
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		ti,system-power-controller;
+		pinctrl-names = "default";
+		pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
 
 		extcon_usb3: palmas_usb {
 			compatible = "ti,palmas-usb-vid";
@@ -358,14 +406,52 @@
 			#clock-cells = <0>;
 		};
 
+		rtc {
+			compatible = "ti,palmas-rtc";
+			interrupt-parent = <&palmas>;
+			interrupts = <8 IRQ_TYPE_NONE>;
+			ti,backup-battery-chargeable;
+			ti,backup-battery-charge-high-current;
+		};
+
+		gpadc {
+			compatible = "ti,palmas-gpadc";
+			interrupts = <18 0
+				      16 0
+				      17 0>;
+			#io-channel-cells = <1>;
+			ti,channel0-current-microamp = <5>;
+			ti,channel3-current-microamp = <10>;
+		};
+
 		palmas_pmic {
 			compatible = "ti,palmas-pmic";
 			interrupt-parent = <&palmas>;
 			interrupts = <14 IRQ_TYPE_NONE>;
-			interrupt-name = "short-irq";
+			interrupt-names = "short-irq";
 
 			ti,ldo6-vibrator;
 
+			smps123-in-supply = <&vsys_cobra>;
+			smps45-in-supply = <&vsys_cobra>;
+			smps6-in-supply = <&vsys_cobra>;
+			smps7-in-supply = <&vsys_cobra>;
+			smps8-in-supply = <&vsys_cobra>;
+			smps9-in-supply = <&vsys_cobra>;
+			smps10_out2-in-supply = <&vsys_cobra>;
+			smps10_out1-in-supply = <&vsys_cobra>;
+			ldo1-in-supply = <&vsys_cobra>;
+			ldo2-in-supply = <&vsys_cobra>;
+			ldo3-in-supply = <&vdds_1v8_main>;
+			ldo4-in-supply = <&vdds_1v8_main>;
+			ldo5-in-supply = <&vsys_cobra>;
+			ldo6-in-supply = <&vdds_1v8_main>;
+			ldo7-in-supply = <&vsys_cobra>;
+			ldo8-in-supply = <&vsys_cobra>;
+			ldo9-in-supply = <&vmmcsd_fixed>;
+			ldoln-in-supply = <&vsys_cobra>;
+			ldousb-in-supply = <&vsys_cobra>;
+
 			regulators {
 				smps123_reg: smps123 {
 					/* VDD_OPP_MPU */
@@ -439,7 +525,7 @@
 				ldo1_reg: ldo1 {
 					/* VDDAPHY_CAM: vdda_csiport */
 					regulator-name = "ldo1";
-					regulator-min-microvolt = <1500000>;
+					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
@@ -465,7 +551,7 @@
 				ldo4_reg: ldo4 {
 					/* VDDAPHY_DISP: vdda_dsiport/hdmi */
 					regulator-name = "ldo4";
-					regulator-min-microvolt = <1500000>;
+					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
@@ -557,7 +643,8 @@
 		pinctrl-0 = <&twl6040_pins>;
 
 		interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
-		ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;  /* gpio line 141 */
+
+		/* audpwron gpio defined in the board specific dts */
 
 		vio-supply = <&smps7_reg>;
 		v2v1-supply = <&smps9_reg>;
diff --git a/sys/gnu/dts/arm/omap5-cm-t54.dts b/sys/gnu/dts/arm/omap5-cm-t54.dts
index ecc591dc0778..93fdfa96776e 100644
--- a/sys/gnu/dts/arm/omap5-cm-t54.dts
+++ b/sys/gnu/dts/arm/omap5-cm-t54.dts
@@ -434,7 +434,7 @@
 			compatible = "ti,palmas-pmic";
 			interrupt-parent = <&palmas>;
 			interrupts = <14 IRQ_TYPE_NONE>;
-			interrupt-name = "short-irq";
+			interrupt-names = "short-irq";
 
 			ti,ldo6-vibrator;
 
@@ -513,7 +513,7 @@
 				ldo1_reg: ldo1 {
 					/* VDDAPHY_CAM: vdda_csiport */
 					regulator-name = "ldo1";
-					regulator-min-microvolt = <1500000>;
+					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
@@ -537,7 +537,7 @@
 				ldo4_reg: ldo4 {
 					/* VDDAPHY_DISP: vdda_dsiport/hdmi */
 					regulator-name = "ldo4";
-					regulator-min-microvolt = <1500000>;
+					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 				};
 
diff --git a/sys/gnu/dts/arm/omap5-igep0050.dts b/sys/gnu/dts/arm/omap5-igep0050.dts
index 46ecb1dd3b5c..f75ce02fb398 100644
--- a/sys/gnu/dts/arm/omap5-igep0050.dts
+++ b/sys/gnu/dts/arm/omap5-igep0050.dts
@@ -35,6 +35,22 @@
 	};
 };
 
+/* LDO4 is VPP1 - ball AD9 */
+&ldo4_reg {
+	regulator-min-microvolt = <2000000>;
+	regulator-max-microvolt = <2000000>;
+};
+
+/*
+ * LDO7 is used for HDMI: VDDA_DSIPORTA - ball AA33, VDDA_DSIPORTC - ball AE33,
+ * VDDA_HDMI - ball AN25
+ */
+&ldo7_reg {
+	status = "okay";
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+};
+
 &omap5_pmx_core {
 	i2c4_pins: pinmux_i2c4_pins {
 		pinctrl-single,pins = <
@@ -52,3 +68,13 @@
 		<&gpio7 3 0>;		/* 195, SDA */
 };
 
+&twl6040 {
+	ti,audpwron-gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>;  /* gpio line 144 */
+};
+
+&twl6040_pins {
+	pinctrl-single,pins = <
+		OMAP5_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE6)	/* mcspi1_somi.gpio5_144 */
+		OMAP5_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE6)	/* perslimbus2_clock.gpio5_145 */
+	>;
+};
diff --git a/sys/gnu/dts/arm/omap5-uevm.dts b/sys/gnu/dts/arm/omap5-uevm.dts
index 60b3fbb3bf07..a51e60518eb6 100644
--- a/sys/gnu/dts/arm/omap5-uevm.dts
+++ b/sys/gnu/dts/arm/omap5-uevm.dts
@@ -51,3 +51,13 @@
 		<&gpio9 1 GPIO_ACTIVE_HIGH>,	/* TCA6424A P00, LS OE */
 		<&gpio7 1 GPIO_ACTIVE_HIGH>;	/* GPIO 193, HPD */
 };
+
+&twl6040 {
+	ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;  /* gpio line 141 */
+};
+
+&twl6040_pins {
+	pinctrl-single,pins = <
+		OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6)	/* mcspi1_somi.gpio5_141 */
+	>;
+};
diff --git a/sys/gnu/dts/arm/omap5.dtsi b/sys/gnu/dts/arm/omap5.dtsi
index ca3c17fde5a0..84c10195e79b 100644
--- a/sys/gnu/dts/arm/omap5.dtsi
+++ b/sys/gnu/dts/arm/omap5.dtsi
@@ -187,7 +187,7 @@
 					#size-cells = <1>;
 					ranges = <0 0x5a0 0xec>;
 
-					pbias_regulator: pbias_regulator {
+					pbias_regulator: pbias_regulator@60 {
 						compatible = "ti,pbias-omap5", "ti,pbias-omap";
 						reg = <0x60 0x4>;
 						syscon = <&omap5_padconf_global>;
@@ -269,7 +269,7 @@
 			omap5_pmx_wkup: pinmux@c840 {
 				compatible = "ti,omap5-padconf",
 					     "pinctrl-single";
-				reg = <0xc840 0x0038>;
+				reg = <0xc840 0x003c>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				#interrupt-cells = <1>;
@@ -398,6 +398,10 @@
 			ti,hwmods = "gpmc";
 			clocks = <&l3_iclk_div>;
 			clock-names = "fck";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 		};
 
 		i2c1: i2c@48070000 {
@@ -852,18 +856,6 @@
 			hw-caps-temp-alert;
 		};
 
-		omap_control_usb2phy: control-phy@4a002300 {
-			compatible = "ti,control-phy-usb2";
-			reg = <0x4a002300 0x4>;
-			reg-names = "power";
-		};
-
-		omap_control_usb3phy: control-phy@4a002370 {
-			compatible = "ti,control-phy-pipe3";
-			reg = <0x4a002370 0x4>;
-			reg-names = "power";
-		};
-
 		usb3: omap_dwc3@4a020000 {
 			compatible = "ti,dwc3";
 			ti,hwmods = "usb_otg_ss";
@@ -885,7 +877,6 @@
 				phys = <&usb2_phy>, <&usb3_phy>;
 				phy-names = "usb2-phy", "usb3-phy";
 				dr_mode = "peripheral";
-				tx-fifo-resize;
 			};
 		};
 
@@ -899,7 +890,7 @@
 			usb2_phy: usb2phy@4a084000 {
 				compatible = "ti,omap-usb2";
 				reg = <0x4a084000 0x7c>;
-				ctrl-module = <&omap_control_usb2phy>;
+				syscon-phy-power = <&scm_conf 0x300>;
 				clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 				clock-names = "wkupclk", "refclk";
 				#phy-cells = <0>;
@@ -911,7 +902,7 @@
 				      <0x4a084800 0x64>,
 				      <0x4a084c00 0x40>;
 				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
-				ctrl-module = <&omap_control_usb3phy>;
+				syscon-phy-power = <&scm_conf 0x370>;
 				clocks = <&usb_phy_cm_clk32k>,
 					 <&sys_clkin>,
 					 <&usb_otg_ss_refclk960m>;
@@ -967,14 +958,6 @@
 			#thermal-sensor-cells = <1>;
 		};
 
-		omap_control_sata: control-phy@4a002374 {
-			compatible = "ti,control-phy-pipe3";
-			reg = <0x4a002374 0x4>;
-			reg-names = "power";
-			clocks = <&sys_clkin>;
-			clock-names = "sysclk";
-		};
-
 		/* OCP2SCP3 */
 		ocp2scp@4a090000 {
 			compatible = "ti,omap-ocp2scp";
@@ -989,7 +972,7 @@
 				      <0x4A096400 0x64>, /* phy_tx */
 				      <0x4A096800 0x40>; /* pll_ctrl */
 				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
-				ctrl-module = <&omap_control_sata>;
+				syscon-phy-power = <&scm_conf 0x374>;
 				clocks = <&sys_clkin>, <&sata_ref_clk>;
 				clock-names = "sysclk", "refclk";
 				#phy-cells = <0>;
diff --git a/sys/gnu/dts/arm/omap54xx-clocks.dtsi b/sys/gnu/dts/arm/omap54xx-clocks.dtsi
index 83b425fb3ac2..4899c2359d0a 100644
--- a/sys/gnu/dts/arm/omap54xx-clocks.dtsi
+++ b/sys/gnu/dts/arm/omap54xx-clocks.dtsi
@@ -14,7 +14,7 @@
 		clock-frequency = <12000000>;
 	};
 
-	pad_clks_ck: pad_clks_ck {
+	pad_clks_ck: pad_clks_ck@108 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&pad_clks_src_ck>;
@@ -34,7 +34,7 @@
 		clock-frequency = <12000000>;
 	};
 
-	slimbus_clk: slimbus_clk {
+	slimbus_clk: slimbus_clk@108 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&slimbus_src_clk>;
@@ -102,7 +102,7 @@
 		clock-frequency = <60000000>;
 	};
 
-	dpll_abe_ck: dpll_abe_ck {
+	dpll_abe_ck: dpll_abe_ck@1e0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-m4xen-clock";
 		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
@@ -115,7 +115,7 @@
 		clocks = <&dpll_abe_ck>;
 	};
 
-	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_x2_ck>;
@@ -132,7 +132,7 @@
 		clock-div = <8>;
 	};
 
-	abe_clk: abe_clk {
+	abe_clk: abe_clk@108 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_m2x2_ck>;
@@ -141,7 +141,7 @@
 		ti,index-power-of-two;
 	};
 
-	abe_iclk: abe_iclk {
+	abe_iclk: abe_iclk@528 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&aess_fclk>;
@@ -158,7 +158,7 @@
 		clock-div = <16>;
 	};
 
-	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_abe_x2_ck>;
@@ -167,7 +167,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_byp_mux: dpll_core_byp_mux {
+	dpll_core_byp_mux: dpll_core_byp_mux@12c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
@@ -175,7 +175,7 @@
 		reg = <0x012c>;
 	};
 
-	dpll_core_ck: dpll_core_ck {
+	dpll_core_ck: dpll_core_ck@120 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-core-clock";
 		clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
@@ -188,7 +188,7 @@
 		clocks = <&dpll_core_ck>;
 	};
 
-	dpll_core_h21x2_ck: dpll_core_h21x2_ck {
+	dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -213,7 +213,7 @@
 		clock-div = <2>;
 	};
 
-	dpll_core_h11x2_ck: dpll_core_h11x2_ck {
+	dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -222,7 +222,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+	dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -231,7 +231,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+	dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -240,7 +240,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+	dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -249,7 +249,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+	dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -258,7 +258,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+	dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -267,7 +267,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+	dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -276,7 +276,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_m2_ck: dpll_core_m2_ck {
+	dpll_core_m2_ck: dpll_core_m2_ck@130 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_ck>;
@@ -285,7 +285,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+	dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_core_x2_ck>;
@@ -302,7 +302,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_iva_byp_mux: dpll_iva_byp_mux {
+	dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
@@ -310,7 +310,7 @@
 		reg = <0x01ac>;
 	};
 
-	dpll_iva_ck: dpll_iva_ck {
+	dpll_iva_ck: dpll_iva_ck@1a0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
@@ -323,7 +323,7 @@
 		clocks = <&dpll_iva_ck>;
 	};
 
-	dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
+	dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_iva_x2_ck>;
@@ -332,7 +332,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
+	dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_iva_x2_ck>;
@@ -349,14 +349,14 @@
 		clock-div = <1>;
 	};
 
-	dpll_mpu_ck: dpll_mpu_ck {
+	dpll_mpu_ck: dpll_mpu_ck@160 {
 		#clock-cells = <0>;
 		compatible = "ti,omap5-mpu-dpll-clock";
 		clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
 		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 	};
 
-	dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_mpu_ck>;
@@ -381,7 +381,7 @@
 		clock-div = <3>;
 	};
 
-	l3_iclk_div: l3_iclk_div {
+	l3_iclk_div: l3_iclk_div@100 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		ti,max-div = <2>;
@@ -399,7 +399,7 @@
 		clock-div = <1>;
 	};
 
-	l4_root_clk_div: l4_root_clk_div {
+	l4_root_clk_div: l4_root_clk_div@100 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		ti,max-div = <2>;
@@ -409,7 +409,7 @@
 		ti,index-power-of-two;
 	};
 
-	slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+	slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&slimbus_clk>;
@@ -417,7 +417,7 @@
 		reg = <0x0560>;
 	};
 
-	aess_fclk: aess_fclk {
+	aess_fclk: aess_fclk@528 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&abe_clk>;
@@ -426,7 +426,7 @@
 		reg = <0x0528>;
 	};
 
-	dmic_sync_mux_ck: dmic_sync_mux_ck {
+	dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -434,7 +434,7 @@
 		reg = <0x0538>;
 	};
 
-	dmic_gfclk: dmic_gfclk {
+	dmic_gfclk: dmic_gfclk@538 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -442,7 +442,7 @@
 		reg = <0x0538>;
 	};
 
-	mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+	mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -450,7 +450,7 @@
 		reg = <0x0540>;
 	};
 
-	mcasp_gfclk: mcasp_gfclk {
+	mcasp_gfclk: mcasp_gfclk@540 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -458,7 +458,7 @@
 		reg = <0x0540>;
 	};
 
-	mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+	mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -466,7 +466,7 @@
 		reg = <0x0548>;
 	};
 
-	mcbsp1_gfclk: mcbsp1_gfclk {
+	mcbsp1_gfclk: mcbsp1_gfclk@548 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -474,7 +474,7 @@
 		reg = <0x0548>;
 	};
 
-	mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+	mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -482,7 +482,7 @@
 		reg = <0x0550>;
 	};
 
-	mcbsp2_gfclk: mcbsp2_gfclk {
+	mcbsp2_gfclk: mcbsp2_gfclk@550 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -490,7 +490,7 @@
 		reg = <0x0550>;
 	};
 
-	mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+	mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -498,7 +498,7 @@
 		reg = <0x0558>;
 	};
 
-	mcbsp3_gfclk: mcbsp3_gfclk {
+	mcbsp3_gfclk: mcbsp3_gfclk@558 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -506,7 +506,7 @@
 		reg = <0x0558>;
 	};
 
-	timer5_gfclk_mux: timer5_gfclk_mux {
+	timer5_gfclk_mux: timer5_gfclk_mux@568 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -514,7 +514,7 @@
 		reg = <0x0568>;
 	};
 
-	timer6_gfclk_mux: timer6_gfclk_mux {
+	timer6_gfclk_mux: timer6_gfclk_mux@570 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -522,7 +522,7 @@
 		reg = <0x0570>;
 	};
 
-	timer7_gfclk_mux: timer7_gfclk_mux {
+	timer7_gfclk_mux: timer7_gfclk_mux@578 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -530,7 +530,7 @@
 		reg = <0x0578>;
 	};
 
-	timer8_gfclk_mux: timer8_gfclk_mux {
+	timer8_gfclk_mux: timer8_gfclk_mux@580 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -545,7 +545,7 @@
 	};
 };
 &prm_clocks {
-	sys_clkin: sys_clkin {
+	sys_clkin: sys_clkin@110 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -553,14 +553,14 @@
 		ti,index-starts-at-one;
 	};
 
-	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&sys_32k_ck>;
 		reg = <0x0108>;
 	};
 
-	abe_dpll_clk_mux: abe_dpll_clk_mux {
+	abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -583,7 +583,7 @@
 		clock-div = <1>;
 	};
 
-	wkupaon_iclk_mux: wkupaon_iclk_mux {
+	wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&abe_lp_clk_div>;
@@ -598,7 +598,7 @@
 		clock-div = <1>;
 	};
 
-	gpio1_dbclk: gpio1_dbclk {
+	gpio1_dbclk: gpio1_dbclk@1938 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -606,7 +606,7 @@
 		reg = <0x1938>;
 	};
 
-	timer1_gfclk_mux: timer1_gfclk_mux {
+	timer1_gfclk_mux: timer1_gfclk_mux@1940 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -616,7 +616,7 @@
 };
 &cm_core_clocks {
 
-	dpll_per_byp_mux: dpll_per_byp_mux {
+	dpll_per_byp_mux: dpll_per_byp_mux@14c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
@@ -624,7 +624,7 @@
 		reg = <0x014c>;
 	};
 
-	dpll_per_ck: dpll_per_ck {
+	dpll_per_ck: dpll_per_ck@140 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
@@ -637,7 +637,7 @@
 		clocks = <&dpll_per_ck>;
 	};
 
-	dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+	dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -646,7 +646,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+	dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -655,7 +655,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+	dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -664,7 +664,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_per_m2_ck: dpll_per_m2_ck {
+	dpll_per_m2_ck: dpll_per_m2_ck@150 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_ck>;
@@ -673,7 +673,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -682,7 +682,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+	dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_x2_ck>;
@@ -691,7 +691,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_unipro1_ck: dpll_unipro1_ck {
+	dpll_unipro1_ck: dpll_unipro1_ck@200 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin>, <&sys_clkin>;
@@ -706,7 +706,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
+	dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_unipro1_ck>;
@@ -715,7 +715,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_unipro2_ck: dpll_unipro2_ck {
+	dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-clock";
 		clocks = <&sys_clkin>, <&sys_clkin>;
@@ -730,7 +730,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
+	dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_unipro2_ck>;
@@ -739,7 +739,7 @@
 		ti,index-starts-at-one;
 	};
 
-	dpll_usb_byp_mux: dpll_usb_byp_mux {
+	dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
@@ -747,7 +747,7 @@
 		reg = <0x018c>;
 	};
 
-	dpll_usb_ck: dpll_usb_ck {
+	dpll_usb_ck: dpll_usb_ck@180 {
 		#clock-cells = <0>;
 		compatible = "ti,omap4-dpll-j-type-clock";
 		clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
@@ -762,7 +762,7 @@
 		clock-div = <1>;
 	};
 
-	dpll_usb_m2_ck: dpll_usb_m2_ck {
+	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_ck>;
@@ -811,7 +811,7 @@
 		clock-div = <2>;
 	};
 
-	l3init_60m_fclk: l3init_60m_fclk {
+	l3init_60m_fclk: l3init_60m_fclk@104 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -819,7 +819,7 @@
 		ti,dividers = <1>, <8>;
 	};
 
-	dss_32khz_clk: dss_32khz_clk {
+	dss_32khz_clk: dss_32khz_clk@1420 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -827,7 +827,7 @@
 		reg = <0x1420>;
 	};
 
-	dss_48mhz_clk: dss_48mhz_clk {
+	dss_48mhz_clk: dss_48mhz_clk@1420 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_48m_fclk>;
@@ -835,7 +835,7 @@
 		reg = <0x1420>;
 	};
 
-	dss_dss_clk: dss_dss_clk {
+	dss_dss_clk: dss_dss_clk@1420 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_per_h12x2_ck>;
@@ -844,7 +844,7 @@
 		ti,set-rate-parent;
 	};
 
-	dss_sys_clk: dss_sys_clk {
+	dss_sys_clk: dss_sys_clk@1420 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dss_syc_gfclk_div>;
@@ -852,7 +852,7 @@
 		reg = <0x1420>;
 	};
 
-	gpio2_dbclk: gpio2_dbclk {
+	gpio2_dbclk: gpio2_dbclk@1060 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -860,7 +860,7 @@
 		reg = <0x1060>;
 	};
 
-	gpio3_dbclk: gpio3_dbclk {
+	gpio3_dbclk: gpio3_dbclk@1068 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -868,7 +868,7 @@
 		reg = <0x1068>;
 	};
 
-	gpio4_dbclk: gpio4_dbclk {
+	gpio4_dbclk: gpio4_dbclk@1070 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -876,7 +876,7 @@
 		reg = <0x1070>;
 	};
 
-	gpio5_dbclk: gpio5_dbclk {
+	gpio5_dbclk: gpio5_dbclk@1078 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -884,7 +884,7 @@
 		reg = <0x1078>;
 	};
 
-	gpio6_dbclk: gpio6_dbclk {
+	gpio6_dbclk: gpio6_dbclk@1080 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -892,7 +892,7 @@
 		reg = <0x1080>;
 	};
 
-	gpio7_dbclk: gpio7_dbclk {
+	gpio7_dbclk: gpio7_dbclk@1110 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -900,7 +900,7 @@
 		reg = <0x1110>;
 	};
 
-	gpio8_dbclk: gpio8_dbclk {
+	gpio8_dbclk: gpio8_dbclk@1118 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -908,7 +908,7 @@
 		reg = <0x1118>;
 	};
 
-	iss_ctrlclk: iss_ctrlclk {
+	iss_ctrlclk: iss_ctrlclk@1320 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&func_96m_fclk>;
@@ -916,7 +916,7 @@
 		reg = <0x1320>;
 	};
 
-	lli_txphy_clk: lli_txphy_clk {
+	lli_txphy_clk: lli_txphy_clk@f20 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_unipro1_clkdcoldo>;
@@ -924,7 +924,7 @@
 		reg = <0x0f20>;
 	};
 
-	lli_txphy_ls_clk: lli_txphy_ls_clk {
+	lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_unipro1_m2_ck>;
@@ -932,7 +932,7 @@
 		reg = <0x0f20>;
 	};
 
-	mmc1_32khz_clk: mmc1_32khz_clk {
+	mmc1_32khz_clk: mmc1_32khz_clk@1628 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -940,7 +940,7 @@
 		reg = <0x1628>;
 	};
 
-	sata_ref_clk: sata_ref_clk {
+	sata_ref_clk: sata_ref_clk@1688 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_clkin>;
@@ -948,7 +948,7 @@
 		reg = <0x1688>;
 	};
 
-	usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+	usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -956,7 +956,7 @@
 		reg = <0x1658>;
 	};
 
-	usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+	usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -964,7 +964,7 @@
 		reg = <0x1658>;
 	};
 
-	usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
+	usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_usb_m2_ck>;
@@ -972,7 +972,7 @@
 		reg = <0x1658>;
 	};
 
-	usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+	usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3init_60m_fclk>;
@@ -980,7 +980,7 @@
 		reg = <0x1658>;
 	};
 
-	usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+	usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3init_60m_fclk>;
@@ -988,7 +988,7 @@
 		reg = <0x1658>;
 	};
 
-	usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
+	usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3init_60m_fclk>;
@@ -996,7 +996,7 @@
 		reg = <0x1658>;
 	};
 
-	utmi_p1_gfclk: utmi_p1_gfclk {
+	utmi_p1_gfclk: utmi_p1_gfclk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
@@ -1004,7 +1004,7 @@
 		reg = <0x1658>;
 	};
 
-	usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+	usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&utmi_p1_gfclk>;
@@ -1012,7 +1012,7 @@
 		reg = <0x1658>;
 	};
 
-	utmi_p2_gfclk: utmi_p2_gfclk {
+	utmi_p2_gfclk: utmi_p2_gfclk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
@@ -1020,7 +1020,7 @@
 		reg = <0x1658>;
 	};
 
-	usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+	usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&utmi_p2_gfclk>;
@@ -1028,7 +1028,7 @@
 		reg = <0x1658>;
 	};
 
-	usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+	usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3init_60m_fclk>;
@@ -1036,7 +1036,7 @@
 		reg = <0x1658>;
 	};
 
-	usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
+	usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&dpll_usb_clkdcoldo>;
@@ -1044,7 +1044,7 @@
 		reg = <0x16f0>;
 	};
 
-	usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+	usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
@@ -1052,7 +1052,7 @@
 		reg = <0x0640>;
 	};
 
-	usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+	usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3init_60m_fclk>;
@@ -1060,7 +1060,7 @@
 		reg = <0x1668>;
 	};
 
-	usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+	usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3init_60m_fclk>;
@@ -1068,7 +1068,7 @@
 		reg = <0x1668>;
 	};
 
-	usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+	usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
 		clocks = <&l3init_60m_fclk>;
@@ -1076,7 +1076,7 @@
 		reg = <0x1668>;
 	};
 
-	fdif_fclk: fdif_fclk {
+	fdif_fclk: fdif_fclk@1328 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_h11x2_ck>;
@@ -1085,7 +1085,7 @@
 		reg = <0x1328>;
 	};
 
-	gpu_core_gclk_mux: gpu_core_gclk_mux {
+	gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
@@ -1093,7 +1093,7 @@
 		reg = <0x1520>;
 	};
 
-	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
@@ -1101,7 +1101,7 @@
 		reg = <0x1520>;
 	};
 
-	hsi_fclk: hsi_fclk {
+	hsi_fclk: hsi_fclk@1638 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&dpll_per_m2x2_ck>;
@@ -1110,7 +1110,7 @@
 		reg = <0x1638>;
 	};
 
-	mmc1_fclk_mux: mmc1_fclk_mux {
+	mmc1_fclk_mux: mmc1_fclk_mux@1628 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1118,7 +1118,7 @@
 		reg = <0x1628>;
 	};
 
-	mmc1_fclk: mmc1_fclk {
+	mmc1_fclk: mmc1_fclk@1628 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mmc1_fclk_mux>;
@@ -1127,7 +1127,7 @@
 		reg = <0x1628>;
 	};
 
-	mmc2_fclk_mux: mmc2_fclk_mux {
+	mmc2_fclk_mux: mmc2_fclk_mux@1630 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1135,7 +1135,7 @@
 		reg = <0x1630>;
 	};
 
-	mmc2_fclk: mmc2_fclk {
+	mmc2_fclk: mmc2_fclk@1630 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&mmc2_fclk_mux>;
@@ -1144,7 +1144,7 @@
 		reg = <0x1630>;
 	};
 
-	timer10_gfclk_mux: timer10_gfclk_mux {
+	timer10_gfclk_mux: timer10_gfclk_mux@1028 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1152,7 +1152,7 @@
 		reg = <0x1028>;
 	};
 
-	timer11_gfclk_mux: timer11_gfclk_mux {
+	timer11_gfclk_mux: timer11_gfclk_mux@1030 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1160,7 +1160,7 @@
 		reg = <0x1030>;
 	};
 
-	timer2_gfclk_mux: timer2_gfclk_mux {
+	timer2_gfclk_mux: timer2_gfclk_mux@1038 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1168,7 +1168,7 @@
 		reg = <0x1038>;
 	};
 
-	timer3_gfclk_mux: timer3_gfclk_mux {
+	timer3_gfclk_mux: timer3_gfclk_mux@1040 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1176,7 +1176,7 @@
 		reg = <0x1040>;
 	};
 
-	timer4_gfclk_mux: timer4_gfclk_mux {
+	timer4_gfclk_mux: timer4_gfclk_mux@1048 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1184,7 +1184,7 @@
 		reg = <0x1048>;
 	};
 
-	timer9_gfclk_mux: timer9_gfclk_mux {
+	timer9_gfclk_mux: timer9_gfclk_mux@1050 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1201,7 +1201,7 @@
 };
 
 &scrm_clocks {
-	auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+	auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1209,7 +1209,7 @@
 		reg = <0x0310>;
 	};
 
-	auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+	auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1223,7 +1223,7 @@
 		clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
 	};
 
-	auxclk0_ck: auxclk0_ck {
+	auxclk0_ck: auxclk0_ck@310 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk0_src_ck>;
@@ -1232,7 +1232,7 @@
 		reg = <0x0310>;
 	};
 
-	auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+	auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1240,7 +1240,7 @@
 		reg = <0x0314>;
 	};
 
-	auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+	auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1254,7 +1254,7 @@
 		clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
 	};
 
-	auxclk1_ck: auxclk1_ck {
+	auxclk1_ck: auxclk1_ck@314 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk1_src_ck>;
@@ -1263,7 +1263,7 @@
 		reg = <0x0314>;
 	};
 
-	auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+	auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1271,7 +1271,7 @@
 		reg = <0x0318>;
 	};
 
-	auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+	auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1285,7 +1285,7 @@
 		clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
 	};
 
-	auxclk2_ck: auxclk2_ck {
+	auxclk2_ck: auxclk2_ck@318 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk2_src_ck>;
@@ -1294,7 +1294,7 @@
 		reg = <0x0318>;
 	};
 
-	auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+	auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1302,7 +1302,7 @@
 		reg = <0x031c>;
 	};
 
-	auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+	auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1316,7 +1316,7 @@
 		clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
 	};
 
-	auxclk3_ck: auxclk3_ck {
+	auxclk3_ck: auxclk3_ck@31c {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk3_src_ck>;
@@ -1325,7 +1325,7 @@
 		reg = <0x031c>;
 	};
 
-	auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+	auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-no-wait-gate-clock";
 		clocks = <&dpll_core_m3x2_ck>;
@@ -1333,7 +1333,7 @@
 		reg = <0x0320>;
 	};
 
-	auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+	auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
 		#clock-cells = <0>;
 		compatible = "ti,composite-mux-clock";
 		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1347,7 +1347,7 @@
 		clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
 	};
 
-	auxclk4_ck: auxclk4_ck {
+	auxclk4_ck: auxclk4_ck@320 {
 		#clock-cells = <0>;
 		compatible = "ti,divider-clock";
 		clocks = <&auxclk4_src_ck>;
@@ -1356,7 +1356,7 @@
 		reg = <0x0320>;
 	};
 
-	auxclkreq0_ck: auxclkreq0_ck {
+	auxclkreq0_ck: auxclkreq0_ck@210 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
@@ -1364,7 +1364,7 @@
 		reg = <0x0210>;
 	};
 
-	auxclkreq1_ck: auxclkreq1_ck {
+	auxclkreq1_ck: auxclkreq1_ck@214 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
@@ -1372,7 +1372,7 @@
 		reg = <0x0214>;
 	};
 
-	auxclkreq2_ck: auxclkreq2_ck {
+	auxclkreq2_ck: auxclkreq2_ck@218 {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
@@ -1380,7 +1380,7 @@
 		reg = <0x0218>;
 	};
 
-	auxclkreq3_ck: auxclkreq3_ck {
+	auxclkreq3_ck: auxclkreq3_ck@21c {
 		#clock-cells = <0>;
 		compatible = "ti,mux-clock";
 		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
diff --git a/sys/gnu/dts/arm/orion5x-kuroboxpro.dts b/sys/gnu/dts/arm/orion5x-kuroboxpro.dts
new file mode 100644
index 000000000000..1a672b098d0b
--- /dev/null
+++ b/sys/gnu/dts/arm/orion5x-kuroboxpro.dts
@@ -0,0 +1,127 @@
+/*
+ * Device Tree file for Buffalo/Revogear Kurobox Pro
+ *
+ * Copyright (C) 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c
+ * Copyright (C) Ronen Shitrit <rshitrit@marvell.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "orion5x-linkstation.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Buffalo/Revogear Kurobox Pro";
+	compatible = "buffalo,kurobox-pro", "marvell,orion5x-88f5182", "marvell,orion5x";
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+				 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+				 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>,
+				 <MBUS_ID(0x01, 0x1e) 0 0xfc000000 0x1000000>;
+	};
+
+	memory { /* 128 MB */
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+};
+
+&pinctrl {
+	pmx_power_hdd: pmx-power-hdd {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_usb: pmx-power-usb {
+		marvell,pins = "mpp9";
+		marvell,function = "gpio";
+	};
+};
+
+&devbus_cs0 {
+	status = "okay";
+	compatible = "marvell,orion-nand";
+	reg = <MBUS_ID(0x01, 0x1e) 0 0x400>;
+	cle = <0>;
+	ale = <1>;
+	bank-width = <1>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uImage@0 { /* 4 MB */
+			reg = <0 0x400000>;
+			read-only;
+		};
+
+		rootfs@400000 { /* 64 MB */
+			reg = <0x400000 0x4000000>;
+			read-only;
+		};
+
+		extra@4400000 { /* 188 MB */
+			reg = <0x4400000 0xBC00000>;
+			read-only;
+		};
+	};
+};
+
+&hdd_power {
+	gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+};
+
+&usb_power {
+	gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+};
+
+&sata {
+	nr-ports = <2>;
+};
+
+&ehci1 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/orion5x-linkstation-lsgl.dts b/sys/gnu/dts/arm/orion5x-linkstation-lsgl.dts
new file mode 100644
index 000000000000..1cf644bfd7ea
--- /dev/null
+++ b/sys/gnu/dts/arm/orion5x-linkstation-lsgl.dts
@@ -0,0 +1,87 @@
+/*
+ * Device Tree file for Buffalo Linkstation LS-GL
+ *       (also known as Buffalo Linkstation Pro/Live)
+ *
+ * Copyright (C) 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c
+ * Copyright (C) Ronen Shitrit <rshitrit@marvell.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "orion5x-linkstation.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Buffalo Linkstation Pro/Live";
+	compatible = "buffalo,lsgl", "marvell,orion5x-88f5182", "marvell,orion5x";
+
+	memory { /* 128 MB */
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+};
+
+&pinctrl {
+	pmx_power_hdd: pmx-power-hdd {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_usb: pmx-power-usb {
+		marvell,pins = "mpp9";
+		marvell,function = "gpio";
+	};
+};
+
+&hdd_power {
+	gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+};
+
+&usb_power {
+	gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+};
+
+&ehci1 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/orion5x-linkstation-lswtgl.dts b/sys/gnu/dts/arm/orion5x-linkstation-lswtgl.dts
index 3daec912b4bf..0eead400f427 100644
--- a/sys/gnu/dts/arm/orion5x-linkstation-lswtgl.dts
+++ b/sys/gnu/dts/arm/orion5x-linkstation-lswtgl.dts
@@ -1,7 +1,8 @@
 /*
  * Device Tree file for Buffalo Linkstation LS-WTGL
  *
- * Copyright (C) 2015, Roger Shimizu <rogershimizu@gmail.com>
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -44,9 +45,10 @@
 
 /dts-v1/;
 
+#include "orion5x-linkstation.dtsi"
+#include "mvebu-linkstation-gpio-simple.dtsi"
+#include "mvebu-linkstation-fan.dtsi"
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "orion5x-mv88f5182.dtsi"
 
 / {
 	model = "Buffalo Linkstation LS-WTGL";
@@ -57,217 +59,93 @@
 		reg = <0x00000000 0x4000000>;
 	};
 
-	chosen {
-		bootargs = "console=ttyS0,115200n8 earlyprintk";
-		linux,stdout-path = &uart0;
-	};
-
-	soc {
-		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
-		         <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
-			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>;
-
-		internal-regs {
-			pinctrl: pinctrl@10000 {
-				pinctrl-0 = <&pmx_usb_power &pmx_power_hdd
-					&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
-				pinctrl-names = "default";
-
-				pmx_led_power: pmx-leds {
-					marvell,pins = "mpp0";
-					marvell,function = "gpio";
-				};
-
-				pmx_led_alarm: pmx-leds {
-					marvell,pins = "mpp2";
-					marvell,function = "gpio";
-				};
-
-				pmx_led_info: pmx-leds {
-					marvell,pins = "mpp3";
-					marvell,function = "gpio";
-				};
-
-				pmx_power_hdd: pmx-power-hdd {
-					marvell,pins = "mpp1";
-					marvell,function = "gpio";
-				};
-
-				pmx_usb_power: pmx-usb-power {
-					marvell,pins = "mpp9";
-					marvell,function = "gpio";
-				};
-
-				pmx_sata0: pmx-sata0 {
-					marvell,pins = "mpp12";
-					marvell,function = "sata0";
-				};
-
-				pmx_sata1: pmx-sata1 {
-					marvell,pins = "mpp13";
-					marvell,function = "sata1";
-				};
-
-				pmx_fan_high: pmx-fan-high {
-					marvell,pins = "mpp14";
-					marvell,function = "gpio";
-				};
-
-				pmx_fan_low: pmx-fan-low {
-					marvell,pins = "mpp17";
-					marvell,function = "gpio";
-				};
-
-				pmx_fan_lock: pmx-fan-lock {
-					marvell,pins = "mpp6";
-					marvell,function = "gpio";
-				};
-
-				pmx_power_switch: pmx-power-switch {
-					marvell,pins = "mpp8", "mpp10";
-					marvell,function = "gpio";
-				};
-			};
-		};
-	};
-
 	gpio_keys {
-		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-0 = <&pmx_power_switch>;
-		pinctrl-names = "default";
-
-		button@1 {
-			label = "Power-on Switch";
-			linux,code = <KEY_RESERVED>;
-			linux,input-type = <5>;
+		power-on-switch {
 			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
 		};
 
-		button@2 {
-			label = "Power-auto Switch";
-			linux,code = <KEY_ESC>;
-			linux,input-type = <5>;
+		power-auto-switch {
 			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 		};
 	};
 
 	gpio_leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&pmx_led_power &pmx_led_alarm
-			     &pmx_led_info>;
-		pinctrl-names = "default";
-
-		led@1 {
-			label = "lswtgl:blue:power";
+		blue-power-led {
 			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
 		};
 
-		led@2 {
-			label = "lswtgl:red:alarm";
+		red-alarm-led {
 			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
 		};
 
-		led@3 {
-			label = "lswtgl:amber:info";
+		amber-info-led {
 			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
 		};
 	};
 
 	gpio_fan {
-		compatible = "gpio-fan";
-		pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
-		pinctrl-names = "default";
-
 		gpios = <&gpio0 14 GPIO_ACTIVE_LOW
 			 &gpio0 17 GPIO_ACTIVE_LOW>;
 
-		gpio-fan,speed-map = <0 3
-				1500 2
-				3250 1
-				5000 0>;
-
-		alarm-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+		alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 	};
+};
 
-	restart_poweroff {
-		compatible = "restart-poweroff";
+&pinctrl {
+	pmx_led_power: pmx-leds {
+		marvell,pins = "mpp0";
+		marvell,function = "gpio";
 	};
 
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		pinctrl-0 = <&pmx_power_hdd &pmx_usb_power>;
-		pinctrl-names = "default";
+	pmx_power_hdd: pmx-power-hdd {
+		marvell,pins = "mpp1";
+		marvell,function = "gpio";
+	};
 
-		usb_power: regulator@1 {
-			compatible = "regulator-fixed";
-			reg = <1>;
-			regulator-name = "USB Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
-		};
+	pmx_led_alarm: pmx-leds {
+		marvell,pins = "mpp2";
+		marvell,function = "gpio";
+	};
 
-		hdd_power: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <2>;
-			regulator-name = "HDD Power";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			enable-active-high;
-			regulator-always-on;
-			regulator-boot-on;
-			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
-		};
+	pmx_led_info: pmx-leds {
+		marvell,pins = "mpp3";
+		marvell,function = "gpio";
 	};
-};
 
-&mdio {
-	status = "okay";
+	pmx_fan_lock: pmx-fan-lock {
+		marvell,pins = "mpp6";
+		marvell,function = "gpio";
+	};
 
-	ethphy: ethernet-phy {
-		reg = <8>;
+	pmx_power_switch: pmx-power-switch {
+		marvell,pins = "mpp8", "mpp10";
+		marvell,function = "gpio";
 	};
-};
 
-&eth {
-	status = "okay";
+	pmx_power_usb: pmx-power-usb {
+		marvell,pins = "mpp9";
+		marvell,function = "gpio";
+	};
 
-	ethernet-port@0 {
-		phy-handle = <&ethphy>;
+	pmx_fan_high: pmx-fan-high {
+		marvell,pins = "mpp14";
+		marvell,function = "gpio";
 	};
-};
 
-&ehci0 {
-	status = "okay";
+	pmx_fan_low: pmx-fan-low {
+		marvell,pins = "mpp17";
+		marvell,function = "gpio";
+	};
 };
 
-&i2c {
-	status = "okay";
-
-	rtc {
-		compatible = "ricoh,rs5c372a";
-		reg = <0x32>;
-	};
+&hdd_power {
+	gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
 };
 
-&wdt {
-	status = "disabled";
+&usb_power {
+	gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
 };
 
 &sata {
-	pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
-	pinctrl-names = "default";
-	status = "okay";
 	nr-ports = <2>;
 };
-
-&uart0 {
-	status = "okay";
-};
diff --git a/sys/gnu/dts/arm/orion5x-linkstation.dtsi b/sys/gnu/dts/arm/orion5x-linkstation.dtsi
new file mode 100644
index 000000000000..ed456ab35fd8
--- /dev/null
+++ b/sys/gnu/dts/arm/orion5x-linkstation.dtsi
@@ -0,0 +1,180 @@
+/*
+ * Device Tree common file for orion5x based Buffalo Linkstation
+ *
+ * Copyright (C) 2015, 2016
+ * Roger Shimizu <rogershimizu@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "orion5x-mv88f5182.dtsi"
+
+/ {
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		linux,stdout-path = &uart0;
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+				 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+				 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>;
+	};
+
+	restart_poweroff {
+		compatible = "restart-poweroff";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>;
+		pinctrl-names = "default";
+
+		usb_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "USB Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		hdd_power: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "HDD Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+	};
+};
+
+&pinctrl {
+	pmx_power_hdd: pmx-power-hdd {
+		marvell,function = "gpio";
+	};
+
+	pmx_power_usb: pmx-power-usb {
+		marvell,function = "gpio";
+	};
+};
+
+&devbus_bootcs {
+	status = "okay";
+	devbus,keep-config;
+
+	flash@0 {
+		compatible = "jedec-flash";
+		reg = <0 0x40000>;
+		bank-width = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			header@0 {
+				reg = <0 0x30000>;
+				read-only;
+			};
+
+			uboot@30000 {
+				reg = <0x30000 0xF000>;
+				read-only;
+			};
+
+			uboot_env@3F000 {
+				reg = <0x3F000 0x1000>;
+			};
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy: ethernet-phy {
+		reg = <8>;
+	};
+};
+
+&eth {
+	status = "okay";
+
+	ethernet-port@0 {
+		phy-handle = <&ethphy>;
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&i2c {
+	status = "okay";
+
+	rtc {
+		compatible = "ricoh,rs5c372a";
+		reg = <0x32>;
+	};
+};
+
+&wdt {
+	status = "disabled";
+};
+
+&sata {
+	status = "okay";
+	nr-ports = <1>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/ox810se.dtsi b/sys/gnu/dts/arm/ox810se.dtsi
new file mode 100644
index 000000000000..ce13705c38d4
--- /dev/null
+++ b/sys/gnu/dts/arm/ox810se.dtsi
@@ -0,0 +1,336 @@
+/*
+ * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "oxsemi,ox810se";
+
+	cpus {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			device_type = "cpu";
+			compatible = "arm,arm926ej-s";
+			clocks = <&armclk>;
+		};
+	};
+
+	memory {
+		/* Max 256MB @ 0x48000000 */
+		reg = <0x48000000 0x10000000>;
+	};
+
+	clocks {
+		osc: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+
+		gmacclk: gmacclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <125000000>;
+		};
+
+		rpsclk: rpsclk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <1>;
+			clocks = <&osc>;
+		};
+
+		pll400: pll400 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <733333333>;
+		};
+
+		sysclk: sysclk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <4>;
+			clock-mult = <1>;
+			clocks = <&pll400>;
+		};
+
+		armclk: armclk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+			clocks = <&pll400>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&intc>;
+
+		apb-bridge@44000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0 0x44000000 0x1000000>;
+
+			pinctrl: pinctrl {
+				compatible = "oxsemi,ox810se-pinctrl";
+
+				/* Regmap for sys registers */
+				oxsemi,sys-ctrl = <&sys>;
+
+				pinctrl_uart0: uart0 {
+					uart0a {
+						pins = "gpio31";
+						function = "fct3";
+					};
+					uart0b {
+						pins = "gpio32";
+						function = "fct3";
+					};
+				};
+
+				pinctrl_uart0_modem: uart0_modem {
+					uart0c {
+						pins = "gpio27";
+						function = "fct3";
+					};
+					uart0d {
+						pins = "gpio28";
+						function = "fct3";
+					};
+					uart0e {
+						pins = "gpio29";
+						function = "fct3";
+					};
+					uart0f {
+						pins = "gpio30";
+						function = "fct3";
+					};
+					uart0g {
+						pins = "gpio33";
+						function = "fct3";
+					};
+					uart0h {
+						pins = "gpio34";
+						function = "fct3";
+					};
+				};
+
+				pinctrl_uart1: uart1 {
+					uart1a {
+						pins = "gpio20";
+						function = "fct3";
+					};
+					uart1b {
+						pins = "gpio22";
+						function = "fct3";
+					};
+				};
+
+				pinctrl_uart1_modem: uart1_modem {
+					uart1c {
+						pins = "gpio8";
+						function = "fct3";
+					};
+					uart1d {
+						pins = "gpio9";
+						function = "fct3";
+					};
+					uart1e {
+						pins = "gpio23";
+						function = "fct3";
+					};
+					uart1f {
+						pins = "gpio24";
+						function = "fct3";
+					};
+					uart1g {
+						pins = "gpio25";
+						function = "fct3";
+					};
+					uart1h {
+						pins = "gpio26";
+						function = "fct3";
+					};
+				};
+
+				pinctrl_uart2: uart2 {
+					uart2a {
+						pins = "gpio6";
+						function = "fct3";
+					};
+					uart2b {
+						pins = "gpio7";
+						function = "fct3";
+					};
+				};
+
+				pinctrl_uart2_modem: uart2_modem {
+					uart2c {
+						pins = "gpio0";
+						function = "fct3";
+					};
+					uart2d {
+						pins = "gpio1";
+						function = "fct3";
+					};
+					uart2e {
+						pins = "gpio2";
+						function = "fct3";
+					};
+					uart2f {
+						pins = "gpio3";
+						function = "fct3";
+					};
+					uart2g {
+						pins = "gpio4";
+						function = "fct3";
+					};
+					uart2h {
+						pins = "gpio5";
+						function = "fct3";
+					};
+				};
+			};
+
+			gpio0: gpio@000000 {
+				compatible = "oxsemi,ox810se-gpio";
+				reg = <0x000000 0x100000>;
+				interrupts = <21>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <32>;
+				oxsemi,gpio-bank = <0>;
+				gpio-ranges = <&pinctrl 0 0 32>;
+			};
+
+			gpio1: gpio@100000 {
+				compatible = "oxsemi,ox810se-gpio";
+				reg = <0x100000 0x100000>;
+				interrupts = <22>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				ngpios = <3>;
+				oxsemi,gpio-bank = <1>;
+				gpio-ranges = <&pinctrl 0 32 3>;
+			};
+
+			uart0: serial@200000 {
+			       compatible = "ns16550a";
+			       reg = <0x200000 0x100000>;
+			       clocks = <&sysclk>;
+			       interrupts = <23>;
+			       reg-shift = <0>;
+			       fifo-size = <16>;
+			       reg-io-width = <1>;
+			       current-speed = <115200>;
+			       no-loopback-test;
+			       status = "disabled";
+			       resets = <&reset 17>;
+			};
+
+			uart1: serial@300000 {
+			       compatible = "ns16550a";
+			       reg = <0x300000 0x100000>;
+			       clocks = <&sysclk>;
+			       interrupts = <24>;
+			       reg-shift = <0>;
+			       fifo-size = <16>;
+			       reg-io-width = <1>;
+			       current-speed = <115200>;
+			       no-loopback-test;
+			       status = "disabled";
+			       resets = <&reset 18>;
+			};
+
+			uart2: serial@900000 {
+			       compatible = "ns16550a";
+			       reg = <0x900000 0x100000>;
+			       clocks = <&sysclk>;
+			       interrupts = <29>;
+			       reg-shift = <0>;
+			       fifo-size = <16>;
+			       reg-io-width = <1>;
+			       current-speed = <115200>;
+			       no-loopback-test;
+			       status = "disabled";
+			       resets = <&reset 22>;
+			};
+
+			uart3: serial@a00000 {
+			       compatible = "ns16550a";
+			       reg = <0xa00000 0x100000>;
+			       clocks = <&sysclk>;
+			       interrupts = <30>;
+			       reg-shift = <0>;
+			       fifo-size = <16>;
+			       reg-io-width = <1>;
+			       current-speed = <115200>;
+			       no-loopback-test;
+			       status = "disabled";
+			       resets = <&reset 23>;
+			};
+		};
+
+		apb-bridge@45000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0 0x45000000 0x1000000>;
+
+			sys: sys-ctrl@000000 {
+				compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
+				reg = <0x000000 0x100000>;
+
+				reset: reset-controller {
+					compatible = "oxsemi,ox810se-reset";
+					#reset-cells = <1>;
+				};
+
+				stdclk: stdclk {
+					compatible = "oxsemi,ox810se-stdclk";
+					#clock-cells = <1>;
+				};
+			};
+
+			rps@300000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "simple-bus";
+				ranges = <0 0x300000 0x100000>;
+
+				intc: interrupt-controller@0 {
+					compatible = "oxsemi,ox810se-rps-irq";
+					interrupt-controller;
+					reg = <0 0x200>;
+					#interrupt-cells = <1>;
+					valid-mask = <0xFFFFFFFF>;
+					clear-mask = <0>;
+				};
+
+				timer0: timer@200 {
+					compatible = "oxsemi,ox810se-rps-timer";
+					reg = <0x200 0x40>;
+					clocks = <&rpsclk>;
+					interrupts = <4 5>;
+				};
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/phy3250.dts b/sys/gnu/dts/arm/phy3250.dts
deleted file mode 100644
index 7d253bb6265a..000000000000
--- a/sys/gnu/dts/arm/phy3250.dts
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * PHYTEC phyCORE-LPC3250 board
- *
- * Copyright 2012 Roland Stigge <stigge@antcom.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "lpc32xx.dtsi"
-
-/ {
-	model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
-	compatible = "phytec,phy3250", "nxp,lpc3250";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x4000000>;
-	};
-
-	ahb {
-		mac: ethernet@31060000 {
-			phy-mode = "rmii";
-			use-iram;
-		};
-
-		clcd@31040000 {
-			status = "okay";
-		};
-
-		/* 64MB Flash via SLC NAND controller */
-		slc: flash@20020000 {
-			status = "okay";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			nxp,wdr-clks = <14>;
-			nxp,wwidth = <40000000>;
-			nxp,whold = <100000000>;
-			nxp,wsetup = <100000000>;
-			nxp,rdr-clks = <14>;
-			nxp,rwidth = <40000000>;
-			nxp,rhold = <66666666>;
-			nxp,rsetup = <100000000>;
-			nand-on-flash-bbt;
-			gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
-
-			mtd0@00000000 {
-				label = "phy3250-boot";
-				reg = <0x00000000 0x00064000>;
-				read-only;
-			};
-
-			mtd1@00064000 {
-				label = "phy3250-uboot";
-				reg = <0x00064000 0x00190000>;
-				read-only;
-			};
-
-			mtd2@001f4000 {
-				label = "phy3250-ubt-prms";
-				reg = <0x001f4000 0x00010000>;
-			};
-
-			mtd3@00204000 {
-				label = "phy3250-kernel";
-				reg = <0x00204000 0x00400000>;
-			};
-
-			mtd4@00604000 {
-				label = "phy3250-rootfs";
-				reg = <0x00604000 0x039fc000>;
-			};
-		};
-
-		apb {
-			uart5: serial@40090000 {
-				status = "okay";
-			};
-
-			uart3: serial@40080000 {
-				status = "okay";
-			};
-
-			i2c1: i2c@400A0000 {
-				clock-frequency = <100000>;
-
-				pcf8563: rtc@51 {
-					compatible = "nxp,pcf8563";
-					reg = <0x51>;
-				};
-
-				uda1380: uda1380@18 {
-					compatible = "nxp,uda1380";
-					reg = <0x18>;
-					power-gpio = <&gpio 0x59 0>;
-					reset-gpio = <&gpio 0x51 0>;
-					dac-clk = "wspll";
-				};
-			};
-
-			i2c2: i2c@400A8000 {
-				clock-frequency = <100000>;
-			};
-
-			ssp0: ssp@20084000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				num-cs = <1>;
-				cs-gpios = <&gpio 3 5 0>;
-
-				eeprom: at25@0 {
-					pl022,interface = <0>;
-					pl022,com-mode = <0>;
-					pl022,rx-level-trig = <1>;
-					pl022,tx-level-trig = <1>;
-					pl022,ctrl-len = <11>;
-					pl022,wait-state = <0>;
-					pl022,duplex = <0>;
-
-					at25,byte-len = <0x8000>;
-					at25,addr-mode = <2>;
-					at25,page-size = <64>;
-
-					compatible = "atmel,at25";
-					reg = <0>;
-					spi-max-frequency = <5000000>;
-				};
-			};
-
-			sd@20098000 {
-				wp-gpios = <&gpio 3 0 0>;
-				cd-gpios = <&gpio 3 1 0>;
-				cd-inverted;
-				bus-width = <4>;
-				status = "okay";
-			};
-		};
-
-		fab {
-			uart2: serial@40018000 {
-				status = "okay";
-			};
-
-			tsc@40048000 {
-				status = "okay";
-			};
-
-			key@40050000 {
-				status = "okay";
-				keypad,num-rows = <1>;
-				keypad,num-columns = <1>;
-				nxp,debounce-delay-ms = <3>;
-				nxp,scan-delay-ms = <34>;
-				linux,keymap = <0x00000002>;
-			};
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led0 { /* red */
-			gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
-			default-state = "off";
-		};
-
-		led1 { /* green */
-			gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
-			linux,default-trigger = "heartbeat";
-		};
-	};
-};
-
-/* Here, choose exactly one from: ohci, usbd */
-&ohci /* &usbd */ {
-	transceiver = <&isp1301>;
-	status = "okay";
-};
-
-&i2cusb {
-	clock-frequency = <100000>;
-
-	isp1301: usb-transceiver@2c {
-		compatible = "nxp,isp1301";
-		reg = <0x2c>;
-	};
-};
diff --git a/sys/gnu/dts/arm/pxa27x.dtsi b/sys/gnu/dts/arm/pxa27x.dtsi
index 7f68a1ee7073..210192c38df3 100644
--- a/sys/gnu/dts/arm/pxa27x.dtsi
+++ b/sys/gnu/dts/arm/pxa27x.dtsi
@@ -13,6 +13,7 @@
 			interrupts = <25>;
 			#dma-channels = <32>;
 			#dma-cells = <2>;
+			#dma-requests = <75>;
 			status = "okay";
 		};
 
diff --git a/sys/gnu/dts/arm/pxa3xx.dtsi b/sys/gnu/dts/arm/pxa3xx.dtsi
index cf6998a0804d..fec47bcd8292 100644
--- a/sys/gnu/dts/arm/pxa3xx.dtsi
+++ b/sys/gnu/dts/arm/pxa3xx.dtsi
@@ -12,6 +12,7 @@
 			interrupts = <25>;
 			#dma-channels = <32>;
 			#dma-cells = <2>;
+			#dma-requests = <100>;
 			status = "okay";
 		};
 
@@ -30,7 +31,7 @@
 			reg = <0x43100000 90>;
 			interrupts = <45>;
 			clocks = <&clks CLK_NAND>;
-			dmas = <&pdma 97>;
+			dmas = <&pdma 97 3>;
 			dma-names = "data";
 			#address-cells = <1>;
 			#size-cells = <1>;	
diff --git a/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c-pins.dtsi b/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c-pins.dtsi
new file mode 100644
index 000000000000..a3efb9704fcd
--- /dev/null
+++ b/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c-pins.dtsi
@@ -0,0 +1,52 @@
+&tlmm_pinmux {
+	card_detect: card-detect {
+		mux {
+			pins = "gpio26";
+			function = "gpio";
+			bias-disable;
+		};
+	};
+
+	pcie_pins: pcie-pinmux {
+		mux {
+			pins = "gpio27";
+			function = "gpio";
+		};
+		conf {
+			pins = "gpio27";
+			drive-strength = <12>;
+			bias-disable;
+		};
+	};
+
+	user_leds: user-leds {
+		mux {
+			pins = "gpio3", "gpio7", "gpio10", "gpio11";
+			function = "gpio";
+		};
+
+		conf {
+			pins = "gpio3", "gpio7", "gpio10", "gpio11";
+			function = "gpio";
+			output-low;
+		};
+	};
+
+	magneto_pins: magneto-pins {
+		mux {
+			pins = "gpio31", "gpio48";
+			function = "gpio";
+			bias-disable;
+		};
+	};
+};
+
+&pm8921_mpps {
+	mpp_leds: mpp-leds {
+		pinconf {
+			pins = "mpp7", "mpp8";
+			function = "digital";
+			output-low;
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c.dts b/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c.dts
new file mode 100644
index 000000000000..e01b27ea7fba
--- /dev/null
+++ b/sys/gnu/dts/arm/qcom-apq8064-arrow-db600c.dts
@@ -0,0 +1,349 @@
+#include "qcom-apq8064-v2.0.dtsi"
+#include "qcom-apq8064-arrow-db600c-pins.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Arrow Electronics, APQ8064 DB600c";
+	compatible = "arrow,db600c", "qcom,apq8064";
+
+	aliases {
+		serial0 = &gsbi7_serial;
+		serial1 = &gsbi1_serial;
+		i2c0 = &gsbi2_i2c;
+		i2c1 = &gsbi3_i2c;
+		i2c2 = &gsbi4_i2c;
+		i2c3 = &gsbi7_i2c;
+		spi0 = &gsbi5_spi;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		vph: regulator-fixed@1 {
+			compatible = "regulator-fixed";
+			regulator-min-microvolt = <4500000>;
+			regulator-max-microvolt = <4500000>;
+			regulator-name = "VPH";
+			regulator-type = "voltage";
+			regulator-boot-on;
+		};
+
+		/* on board fixed 3.3v supply */
+		vcc3v3: vcc3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "VCC3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+	};
+
+	soc {
+		rpm@108000 {
+			regulators {
+				vdd_s1-supply = <&vph>;
+				vdd_s2-supply = <&vph>;
+				vdd_s3-supply = <&vph>;
+				vdd_s4-supply = <&vph>;
+				vdd_s5-supply = <&vph>;
+				vdd_s6-supply = <&vph>;
+				vdd_s7-supply = <&vph>;
+				vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
+				vdd_l3_l15_l17-supply = <&vph>;
+				vdd_l4_l14-supply = <&vph>;
+				vdd_l5_l8_l16-supply = <&vph>;
+				vdd_l6_l7-supply = <&vph>;
+				vdd_l9_l11-supply = <&vph>;
+				vdd_l10_l22-supply = <&vph>;
+				vdd_l21_l23_l29-supply = <&vph>;
+				vdd_l24-supply = <&pm8921_s1>;
+				vdd_l25-supply = <&pm8921_s1>;
+				vdd_l26-supply = <&pm8921_s7>;
+				vdd_l27-supply = <&pm8921_s7>;
+				vdd_l28-supply = <&pm8921_s7>;
+				vin_lvs1_3_6-supply = <&pm8921_s4>;
+				vin_lvs2-supply = <&pm8921_s1>;
+				vin_lvs4_5_7-supply = <&pm8921_s4>;
+
+				s1 {
+					regulator-always-on;
+					regulator-min-microvolt = <1225000>;
+					regulator-max-microvolt = <1225000>;
+					qcom,switch-mode-frequency = <3200000>;
+					bias-pull-down;
+				};
+
+				s3 {
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1400000>;
+					qcom,switch-mode-frequency = <4800000>;
+				};
+
+				s4 {
+					regulator-min-microvolt	= <1800000>;
+					regulator-max-microvolt	= <1800000>;
+					qcom,switch-mode-frequency = <3200000>;
+					bias-pull-down;
+					regulator-always-on;
+				};
+
+				s7 {
+					regulator-min-microvolt = <1300000>;
+					regulator-max-microvolt = <1300000>;
+					qcom,switch-mode-frequency = <3200000>;
+				 };
+
+				l3 {
+					regulator-min-microvolt = <3050000>;
+					regulator-max-microvolt = <3300000>;
+					bias-pull-down;
+				};
+
+				l4 {
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1800000>;
+					bias-pull-down;
+				};
+
+				l5 {
+					regulator-min-microvolt = <2750000>;
+					regulator-max-microvolt = <3000000>;
+					bias-pull-down;
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				l6 {
+					regulator-min-microvolt = <2950000>;
+					regulator-max-microvolt = <2950000>;
+					bias-pull-down;
+				};
+
+				l23 {
+					regulator-min-microvolt = <1700000>;
+					regulator-max-microvolt = <1900000>;
+					bias-pull-down;
+				};
+
+				lvs6 {
+					bias-pull-down;
+				};
+
+				lvs7 {
+					bias-pull-down;
+				};
+			};
+		};
+
+		gsbi@12440000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_UART_W_FC>;
+			serial@12450000 {
+				label = "LS-UART1";
+				status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <&gsbi1_uart_4pins>;
+			};
+		};
+
+		gsbi@12480000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C>;
+			i2c@124a0000 {
+				/* On Low speed expansion and Sensors */
+				label = "LS-I2C0";
+				status = "okay";
+				lis3mdl_mag@1e {
+					compatible = "st,lis3mdl-magn";
+					reg = <0x1e>;
+					vdd-supply = <&vcc3v3>;
+					vddio-supply = <&pm8921_s4>;
+					pinctrl-names = "default";
+					pinctrl-0 = <&magneto_pins>;
+					interrupt-parent = <&tlmm_pinmux>;
+
+					st,drdy-int-pin = <2>;
+					interrupts = <48 IRQ_TYPE_EDGE_RISING>, /* DRDY line */
+						     <31 IRQ_TYPE_EDGE_RISING>; /* INT */
+				};
+			};
+		};
+
+		gsbi@16200000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C>;
+			i2c@16280000 {
+			/* On Low speed expansion */
+				status = "okay";
+				label = "LS-I2C1";
+				clock-frequency = <200000>;
+				eeprom@52 {
+					compatible = "atmel,24c128";
+					reg = <0x52>;
+					pagesize = <64>;
+				};
+			};
+		};
+
+		gsbi@16300000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C>;
+			i2c@16380000 {
+				/* On High speed expansion */
+				label = "HS-CAM-I2C3";
+				status = "okay";
+			};
+		};
+
+		gsbi@1a200000 {
+			status = "okay";
+			spi@1a280000 {
+				/* On Low speed expansion */
+				label = "LS-SPI0";
+				status = "okay";
+			};
+		};
+
+		/* DEBUG UART  */
+		gsbi@16600000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C_UART>;
+			serial@16640000 {
+				label = "LS-UART0";
+				status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <&gsbi7_uart_2pins>;
+			};
+
+			i2c@16680000 {
+				/* On High speed expansion */
+				status = "okay";
+				label = "HS-CAM-I2C2";
+			};
+		};
+
+		leds {
+			pinctrl-names = "default";
+			pinctrl-0 = <&user_leds>, <&mpp_leds>;
+
+			compatible = "gpio-leds";
+
+			user-led0 {
+				label = "user0-led";
+				gpios = <&tlmm_pinmux 3 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "heartbeat";
+				default-state = "off";
+			};
+
+			user-led1 {
+				label = "user1-led";
+				gpios = <&tlmm_pinmux 7 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "mmc0";
+				default-state = "off";
+			};
+
+			user-led2 {
+				label = "user2-led";
+				gpios = <&tlmm_pinmux 10 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "mmc1";
+				default-state = "off";
+			};
+
+			user-led3 {
+				label = "user3-led";
+				gpios = <&tlmm_pinmux 11 GPIO_ACTIVE_HIGH>;
+				linux,default-trigger = "none";
+				default-state = "off";
+			};
+
+			wifi-led {
+				label = "WiFi-led";
+				gpios = <&pm8921_mpps 7 GPIO_ACTIVE_HIGH>;
+				default-state = "off";
+			};
+
+			bt-led {
+				label = "BT-led";
+				gpios = <&pm8921_mpps 8 GPIO_ACTIVE_HIGH>;
+				default-state = "off";
+			};
+		};
+
+		pci@1b500000 {
+			status = "okay";
+			vdda-supply = <&pm8921_s3>;
+			vdda_phy-supply = <&pm8921_lvs6>;
+			vdda_refclk-supply = <&vcc3v3>;
+			pinctrl-0 = <&pcie_pins>;
+			pinctrl-names = "default";
+			perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+		};
+
+		phy@1b400000 {
+			status = "okay";
+		};
+
+		sata@29000000 {
+			status	= "okay";
+			target-supply	= <&pm8921_lvs7>;
+		};
+
+		/* OTG */
+		phy@12500000 {
+			status		= "okay";
+			dr_mode		= "peripheral";
+			vddcx-supply	= <&pm8921_s3>;
+			v3p3-supply	= <&pm8921_l3>;
+			v1p8-supply	= <&pm8921_l4>;
+		};
+
+		phy@12520000 {
+			status		= "okay";
+			vddcx-supply	= <&pm8921_s3>;
+			v3p3-supply	= <&pm8921_l3>;
+			v1p8-supply	= <&pm8921_l23>;
+		};
+
+		phy@12530000 {
+			status		= "okay";
+			vddcx-supply	= <&pm8921_s3>;
+			v3p3-supply	= <&pm8921_l3>;
+			v1p8-supply	= <&pm8921_l23>;
+		};
+
+		gadget@12500000 {
+			status = "okay";
+		};
+
+		/* OTG */
+		usb@12500000 {
+			status = "okay";
+		};
+
+		usb@12520000 {
+			status = "okay";
+		};
+
+		usb@12530000 {
+			status = "okay";
+		};
+
+		amba {
+			/* eMMC */
+			sdcc@12400000 {
+				status = "okay";
+				vmmc-supply = <&pm8921_l5>;
+				vqmmc-supply = <&pm8921_s4>;
+			};
+
+			/* External micro SD card */
+			sdcc@12180000 {
+				status = "okay";
+				vmmc-supply = <&pm8921_l6>;
+				pinctrl-names	= "default";
+				pinctrl-0	= <&card_detect>;
+				cd-gpios	= <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>;
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/qcom-apq8064-asus-nexus7-flo.dts b/sys/gnu/dts/arm/qcom-apq8064-asus-nexus7-flo.dts
new file mode 100644
index 000000000000..32fedfa149d0
--- /dev/null
+++ b/sys/gnu/dts/arm/qcom-apq8064-asus-nexus7-flo.dts
@@ -0,0 +1,282 @@
+#include "qcom-apq8064-v2.0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+/ {
+	model = "Asus Nexus7(flo)";
+	compatible = "asus,nexus7-flo", "qcom,apq8064";
+
+	aliases {
+		serial0 = &gsbi7_serial;
+		serial1 = &gsbi6_serial;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	ext_3p3v: regulator-fixed@1 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "ext_3p3v";
+		regulator-type = "voltage";
+		startup-delay-us = <0>;
+		gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		power {
+			label = "Power";
+			gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+			gpio-key,wakeup;
+		};
+		volume_up {
+			label = "Volume Up";
+			gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+		volume_down {
+			label = "Volume Down";
+			gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	soc {
+		rpm@108000 {
+			regulators {
+				vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
+				vin_lvs1_3_6-supply = <&pm8921_s4>;
+				vin_lvs4_5_7-supply = <&pm8921_s4>;
+
+
+				vdd_l24-supply = <&pm8921_s1>;
+				vdd_l25-supply = <&pm8921_s1>;
+				vin_lvs2-supply = <&pm8921_s1>;
+
+				vdd_l26-supply = <&pm8921_s7>;
+				vdd_l27-supply = <&pm8921_s7>;
+				vdd_l28-supply = <&pm8921_s7>;
+
+				vdd_ncp-supply = <&pm8921_l6>;
+
+				/* Buck SMPS */
+				s1 {
+					regulator-always-on;
+					regulator-min-microvolt = <1225000>;
+					regulator-max-microvolt = <1225000>;
+					qcom,switch-mode-frequency = <3200000>;
+					bias-pull-down;
+				};
+
+				/* msm otg HSUSB_VDDCX */
+				s3 {
+					regulator-min-microvolt = <500000>;
+					regulator-max-microvolt = <1150000>;
+					qcom,switch-mode-frequency = <4800000>;
+				};
+
+				/*
+				 * msm_sdcc.1-sdc-vdd_io
+				 * tabla2x-slim-CDC_VDDA_RX
+				 * tabla2x-slim-CDC_VDDA_TX
+				 * tabla2x-slim-CDC_VDD_CP
+				 * tabla2x-slim-VDDIO_CDC
+				 */
+				s4 {
+					regulator-min-microvolt	= <1800000>;
+					regulator-max-microvolt	= <1800000>;
+					qcom,switch-mode-frequency = <3200000>;
+					regulator-always-on;
+				};
+
+				s7 {
+					regulator-min-microvolt = <1300000>;
+					regulator-max-microvolt = <1300000>;
+					qcom,switch-mode-frequency = <3200000>;
+				};
+
+				/* mipi_dsi.1-dsi1_pll_vdda */
+				l2 {
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				/* msm_otg-HSUSB_3p3 */
+				l3 {
+					regulator-min-microvolt = <3075000>;
+					regulator-max-microvolt = <3075000>;
+					bias-pull-down;
+				};
+
+				/* msm_otg-HSUSB_1p8 */
+				l4 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					bias-pull-down;
+				};
+
+				/* msm_sdcc.1-sdc_vdd */
+				l5 {
+					regulator-min-microvolt = <2950000>;
+					regulator-max-microvolt = <2950000>;
+					regulator-always-on;
+					bias-pull-down;
+				};
+
+				l6 {
+					regulator-min-microvolt = <2950000>;
+					regulator-max-microvolt = <2950000>;
+				};
+
+				/* mipi_dsi.1-dsi1_avdd */
+				l11 {
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					bias-pull-down;
+				};
+
+				/* pwm_power for backlight */
+				l17 {
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3600000>;
+					bias-pull-down;
+				};
+
+				/* camera, qdsp6 */
+				l23 {
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					bias-pull-down;
+				};
+
+				/*
+				 * tabla2x-slim-CDC_VDDA_A_1P2V
+				 * tabla2x-slim-VDDD_CDC_D
+				 */
+				l25 {
+					regulator-min-microvolt = <1250000>;
+					regulator-max-microvolt = <1250000>;
+					bias-pull-down;
+				};
+
+				lvs1 {
+					bias-pull-down;
+				};
+
+				lvs4 {
+					bias-pull-down;
+				};
+
+				lvs5 {
+					bias-pull-down;
+				};
+
+				lvs6 {
+					bias-pull-down;
+				};
+				/*
+				 * mipi_dsi.1-dsi1_vddio
+				 * pil_riva-pll_vdd
+				 */
+				lvs7 {
+					bias-pull-down;
+				};
+			};
+		};
+
+		gsbi@16200000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C>;
+			i2c@16280000 {
+				status = "okay";
+				clock-frequency = <200000>;
+				pinctrl-0 = <&i2c3_pins>;
+				pinctrl-names = "default";
+
+				trackpad@10 {
+					compatible = "elan,ekth3500";
+					reg = <0x10>;
+					interrupt-parent = <&tlmm_pinmux>;
+					interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+				};
+			};
+		};
+
+
+		gsbi@12440000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C>;
+
+			i2c@12460000 {
+				status = "okay";
+				clock-frequency = <200000>;
+				pinctrl-0 = <&i2c1_pins>;
+				pinctrl-names = "default";
+
+				eeprom@52 {
+					compatible = "atmel,24c128";
+					reg = <0x52>;
+					pagesize = <32>;
+				};
+
+				bq27541@55 {
+					compatible = "ti,bq27541";
+					reg = <0x55>;
+				};
+
+			};
+		};
+
+		gsbi@16500000 {
+			status = "ok";
+			qcom,mode = <GSBI_PROT_I2C_UART>;
+
+			serial@16540000 {
+				status = "ok";
+
+				pinctrl-names = "default";
+				pinctrl-0 = <&gsbi6_uart_4pins>;
+			};
+		};
+
+		gsbi@16600000 {
+			status = "ok";
+			qcom,mode = <GSBI_PROT_I2C_UART>;
+			serial@16640000 {
+				status = "ok";
+			};
+		};
+
+		/* OTG */
+		phy@12500000 {
+			status		= "okay";
+			vddcx-supply	= <&pm8921_s3>;
+			v3p3-supply	= <&pm8921_l3>;
+			v1p8-supply	= <&pm8921_l4>;
+		};
+
+		gadget@12500000 {
+			status = "okay";
+		};
+
+		/* OTG */
+		usb@12500000 {
+			status = "okay";
+		};
+
+		amba {
+			/* eMMC */
+			sdcc@12400000 {
+				status = "okay";
+				vmmc-supply = <&pm8921_l5>;
+				vqmmc-supply = <&pm8921_s4>;
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts b/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts
index 21095dad7741..35f1d46edded 100644
--- a/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts
+++ b/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts
@@ -37,6 +37,18 @@
 					bias-disable;
 				};
 			};
+
+			pcie_pins: pcie_pinmux {
+				mux {
+					pins = "gpio27";
+					function = "gpio";
+				};
+				conf {
+					pins = "gpio27";
+					drive-strength = <12>;
+					bias-disable;
+				};
+			};
 		};
 
 		rpm@108000 {
@@ -103,6 +115,11 @@
 					regulator-max-microvolt = <1900000>;
 					bias-pull-down;
 				};
+
+				pm8921_lvs6: lvs6 {
+					bias-pull-down;
+				};
+
 			};
 		};
 
@@ -195,6 +212,16 @@
 			};
 		};
 
+		pci@1b500000 {
+			status = "ok";
+			vdda-supply = <&pm8921_s3>;
+			vdda_phy-supply = <&pm8921_lvs6>;
+			vdda_refclk-supply = <&v3p3_fixed>;
+			pinctrl-0 = <&pcie_pins>;
+			pinctrl-names = "default";
+			perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
+		};
+
 		amba {
 			/* eMMC */
 			sdcc1: sdcc@12400000 {
diff --git a/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts b/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts
index fd4d49ef9ef2..2eeb0904eaa7 100644
--- a/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts
+++ b/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts
@@ -9,6 +9,11 @@
 	aliases {
 		serial0 = &gsbi7_serial;
 		serial1 = &gsbi6_serial;
+		i2c0 = &gsbi1_i2c;
+		i2c1 = &gsbi2_i2c;
+		i2c2 = &gsbi3_i2c;
+		i2c3 = &gsbi4_i2c;
+		spi0 = &gsbi5_spi;
 	};
 
 	chosen {
@@ -157,7 +162,16 @@
 		gsbi3: gsbi@16200000 {
 			status = "okay";
 			qcom,mode = <GSBI_PROT_I2C>;
-			i2c3: i2c@16280000 {
+			i2c@16280000 {
+				status = "okay";
+			};
+		};
+
+		gsbi@16300000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C>;
+			/* CAM I2C MIPI-CSI connector */
+			i2c@16380000 {
 				status = "okay";
 			};
 		};
@@ -178,6 +192,16 @@
 			};
 		};
 
+		gsbi@1a200000 {
+			qcom,mode = <GSBI_PROT_SPI>;
+			status = "okay";
+			spi4: spi@1a280000 {
+				status = "okay";
+				num-cs = <1>;
+				cs-gpios = <&tlmm_pinmux 53 0>;
+			};
+		};
+
 		gsbi@16500000 {
 			status = "ok";
 			qcom,mode = <GSBI_PROT_UART_W_FC>;
diff --git a/sys/gnu/dts/arm/qcom-apq8064-pins.dtsi b/sys/gnu/dts/arm/qcom-apq8064-pins.dtsi
new file mode 100644
index 000000000000..4102a98f475b
--- /dev/null
+++ b/sys/gnu/dts/arm/qcom-apq8064-pins.dtsi
@@ -0,0 +1,247 @@
+
+&tlmm_pinmux {
+	sdc4_gpios: sdc4-gpios {
+		pios {
+			pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
+			function = "sdc4";
+		};
+	};
+
+	ps_hold: ps_hold {
+		mux {
+			pins = "gpio78";
+			function = "ps_hold";
+		};
+	};
+
+	i2c1_pins: i2c1 {
+		mux {
+			pins = "gpio20", "gpio21";
+			function = "gsbi1";
+		};
+
+		pinconf {
+			pins = "gpio20", "gpio21";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	i2c1_pins_sleep: i2c1_pins_sleep {
+		mux {
+			pins = "gpio20", "gpio21";
+			function = "gpio";
+		};
+		pinconf {
+			pins = "gpio20", "gpio21";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+
+	gsbi1_uart_2pins: gsbi1_uart_2pins {
+		mux {
+			pins = "gpio18", "gpio19";
+			function = "gsbi1";
+		};
+	};
+
+	gsbi1_uart_4pins: gsbi1_uart_4pins {
+		mux {
+			pins = "gpio18", "gpio19", "gpio20", "gpio21";
+			function = "gsbi1";
+		};
+	};
+
+	i2c2_pins: i2c2 {
+		mux {
+			pins = "gpio24", "gpio25";
+			function = "gsbi2";
+		};
+
+		pinconf {
+			pins = "gpio24", "gpio25";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	i2c2_pins_sleep: i2c2_pins_sleep {
+		mux {
+			pins = "gpio24", "gpio25";
+			function = "gpio";
+		};
+
+		pinconf {
+			pins = "gpio24", "gpio25";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+
+	i2c3_pins: i2c3 {
+		mux {
+			pins = "gpio8", "gpio9";
+			function = "gsbi3";
+		};
+
+		pinconf {
+			pins = "gpio8", "gpio9";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	i2c3_pins_sleep: i2c3_pins_sleep {
+		mux {
+			pins = "gpio8", "gpio9";
+			function = "gpio";
+		};
+		pinconf {
+			pins = "gpio8", "gpio9";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+
+	i2c4_pins: i2c4 {
+		mux {
+			pins = "gpio12", "gpio13";
+			function = "gsbi4";
+		};
+
+		pinconf {
+			pins = "gpio12", "gpio13";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	i2c4_pins_sleep: i2c4_pins_sleep {
+		mux {
+			pins = "gpio12", "gpio13";
+			function = "gpio";
+		};
+		pinconf {
+			pins = "gpio12", "gpio13";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+
+	spi5_default: spi5_default {
+		pinmux {
+			pins = "gpio51", "gpio52", "gpio54";
+			function = "gsbi5";
+		};
+
+		pinmux_cs {
+			function = "gpio";
+			pins = "gpio53";
+		};
+
+		pinconf {
+			pins = "gpio51", "gpio52", "gpio54";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		pinconf_cs {
+			pins = "gpio53";
+			drive-strength = <16>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	spi5_sleep: spi5_sleep {
+		pinmux {
+			function = "gpio";
+			pins = "gpio51", "gpio52", "gpio53", "gpio54";
+		};
+
+		pinconf {
+			pins = "gpio51", "gpio52", "gpio53", "gpio54";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
+	i2c6_pins: i2c6 {
+		mux {
+			pins = "gpio16", "gpio17";
+			function = "gsbi6";
+		};
+
+		pinconf {
+			pins = "gpio16", "gpio17";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	i2c6_pins_sleep: i2c6_pins_sleep {
+		mux {
+			pins = "gpio16", "gpio17";
+			function = "gpio";
+		};
+		pinconf {
+			pins = "gpio16", "gpio17";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+
+	gsbi6_uart_2pins: gsbi6_uart_2pins {
+		mux {
+			pins = "gpio14", "gpio15";
+			function = "gsbi6";
+		};
+	};
+
+	gsbi6_uart_4pins: gsbi6_uart_4pins {
+		mux {
+			pins = "gpio14", "gpio15", "gpio16", "gpio17";
+			function = "gsbi6";
+		};
+	};
+
+	gsbi7_uart_2pins: gsbi7_uart_2pins {
+		mux {
+			pins = "gpio82", "gpio83";
+			function = "gsbi7";
+		};
+	};
+
+	gsbi7_uart_4pins: gsbi7_uart_4pins {
+		mux {
+			pins = "gpio82", "gpio83", "gpio84", "gpio85";
+			function = "gsbi7";
+		};
+	};
+
+	i2c7_pins: i2c7 {
+		mux {
+			pins = "gpio84", "gpio85";
+			function = "gsbi7";
+		};
+
+		pinconf {
+			pins = "gpio84", "gpio85";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	i2c7_pins_sleep: i2c7_pins_sleep {
+		mux {
+			pins = "gpio84", "gpio85";
+			function = "gpio";
+		};
+		pinconf {
+			pins = "gpio84", "gpio85";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/qcom-apq8064.dtsi b/sys/gnu/dts/arm/qcom-apq8064.dtsi
index ed521e85e208..df96ccdc9bb4 100644
--- a/sys/gnu/dts/arm/qcom-apq8064.dtsi
+++ b/sys/gnu/dts/arm/qcom-apq8064.dtsi
@@ -124,6 +124,95 @@
 		hwlocks = <&sfpb_mutex 3>;
 	};
 
+	smd {
+		compatible = "qcom,smd";
+
+		modem@0 {
+			interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
+
+			qcom,ipc = <&l2cc 8 3>;
+			qcom,smd-edge = <0>;
+
+			status = "disabled";
+		};
+
+		q6@1 {
+			interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
+
+			qcom,ipc = <&l2cc 8 15>;
+			qcom,smd-edge = <1>;
+
+			status = "disabled";
+		};
+
+		dsps@3 {
+			interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
+
+			qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
+			qcom,smd-edge = <3>;
+
+			status = "disabled";
+		};
+
+		riva@6 {
+			interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
+
+			qcom,ipc = <&l2cc 8 25>;
+			qcom,smd-edge = <6>;
+
+			status = "disabled";
+		};
+	};
+
+	smsm {
+		compatible = "qcom,smsm";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,ipc-1 = <&l2cc 8 4>;
+		qcom,ipc-2 = <&l2cc 8 14>;
+		qcom,ipc-3 = <&l2cc 8 23>;
+		qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
+
+		apps_smsm: apps@0 {
+			reg = <0>;
+			#qcom,state-cells = <1>;
+		};
+
+		modem_smsm: modem@1 {
+			reg = <1>;
+			interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		q6_smsm: q6@2 {
+			reg = <2>;
+			interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		wcnss_smsm: wcnss@3 {
+			reg = <3>;
+			interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		dsps_smsm: dsps@4 {
+			reg = <4>;
+			interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -142,62 +231,6 @@
 
 			pinctrl-names = "default";
 			pinctrl-0 = <&ps_hold>;
-
-			sdc4_gpios: sdc4-gpios {
-				pios {
-					pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
-					function = "sdc4";
-				};
-			};
-
-			ps_hold: ps_hold {
-				mux {
-					pins = "gpio78";
-					function = "ps_hold";
-				};
-			};
-
-			i2c1_pins: i2c1 {
-				mux {
-					pins = "gpio20", "gpio21";
-					function = "gsbi1";
-				};
-			};
-
-			i2c3_pins: i2c3 {
-				mux {
-					pins = "gpio8", "gpio9";
-					function = "gsbi3";
-				};
-			};
-
-			gsbi6_uart_2pins: gsbi6_uart_2pins {
-				mux {
-					pins = "gpio14", "gpio15";
-					function = "gsbi6";
-				};
-			};
-
-			gsbi6_uart_4pins: gsbi6_uart_4pins {
-				mux {
-					pins = "gpio14", "gpio15", "gpio16", "gpio17";
-					function = "gsbi6";
-				};
-			};
-
-			gsbi7_uart_2pins: gsbi7_uart_2pins {
-				mux {
-					pins = "gpio82", "gpio83";
-					function = "gsbi7";
-				};
-			};
-
-			gsbi7_uart_4pins: gsbi7_uart_4pins {
-				mux {
-					pins = "gpio82", "gpio83", "gpio84", "gpio85";
-					function = "gsbi7";
-				};
-			};
 		};
 
 		sfpb_wrapper_mutex: syscon@1200000 {
@@ -268,6 +301,11 @@
 			regulator;
 		};
 
+		sps_sic_non_secure: sps-sic-non-secure@12100000 {
+			compatible	= "syscon";
+			reg		= <0x12100000 0x10000>;
+		};
+
 		gsbi1: gsbi@12440000 {
 			status = "disabled";
 			compatible = "qcom,gsbi-v1.0.0";
@@ -281,10 +319,21 @@
 
 			syscon-tcsr = <&tcsr>;
 
-			i2c1: i2c@12460000 {
+			gsbi1_serial: serial@12450000 {
+				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+				reg = <0x12450000 0x100>,
+				      <0x12400000 0x03>;
+				interrupts = <0 193 0x0>;
+				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+				clock-names = "core", "iface";
+				status = "disabled";
+			};
+
+			gsbi1_i2c: i2c@12460000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
 				pinctrl-0 = <&i2c1_pins>;
-				pinctrl-names = "default";
+				pinctrl-1 = <&i2c1_pins_sleep>;
+				pinctrl-names = "default", "sleep";
 				reg = <0x12460000 0x1000>;
 				interrupts = <0 194 IRQ_TYPE_NONE>;
 				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
@@ -292,6 +341,7 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 			};
+
 		};
 
 		gsbi2: gsbi@12480000 {
@@ -307,9 +357,12 @@
 
 			syscon-tcsr = <&tcsr>;
 
-			i2c2: i2c@124a0000 {
+			gsbi2_i2c: i2c@124a0000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
 				reg = <0x124a0000 0x1000>;
+				pinctrl-0 = <&i2c2_pins>;
+				pinctrl-1 = <&i2c2_pins_sleep>;
+				pinctrl-names = "default", "sleep";
 				interrupts = <0 196 IRQ_TYPE_NONE>;
 				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 				clock-names = "core", "iface";
@@ -328,15 +381,42 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
-			i2c3: i2c@16280000 {
+			gsbi3_i2c: i2c@16280000 {
 				compatible = "qcom,i2c-qup-v1.1.1";
 				pinctrl-0 = <&i2c3_pins>;
-				pinctrl-names = "default";
+				pinctrl-1 = <&i2c3_pins_sleep>;
+				pinctrl-names = "default", "sleep";
 				reg = <0x16280000 0x1000>;
 				interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 				clocks = <&gcc GSBI3_QUP_CLK>,
 					 <&gcc GSBI3_H_CLK>;
 				clock-names = "core", "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		gsbi4: gsbi@16300000 {
+			status = "disabled";
+			compatible = "qcom,gsbi-v1.0.0";
+			cell-index = <4>;
+			reg = <0x16300000 0x03>;
+			clocks = <&gcc GSBI4_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			gsbi4_i2c: i2c@16380000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				pinctrl-0 = <&i2c4_pins>;
+				pinctrl-1 = <&i2c4_pins_sleep>;
+				pinctrl-names = "default", "sleep";
+				reg = <0x16380000 0x1000>;
+				interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+				clocks = <&gcc GSBI4_QUP_CLK>,
+					 <&gcc GSBI4_H_CLK>;
+				clock-names = "core", "iface";
 			};
 		};
 
@@ -360,6 +440,20 @@
 				clock-names = "core", "iface";
 				status = "disabled";
 			};
+
+			gsbi5_spi: spi@1a280000 {
+				compatible = "qcom,spi-qup-v1.1.1";
+				reg = <0x1a280000 0x1000>;
+				interrupts = <0 155 0>;
+				pinctrl-0 = <&spi5_default>;
+				pinctrl-1 = <&spi5_sleep>;
+				pinctrl-names = "default", "sleep";
+				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
+				clock-names = "core", "iface";
+				status = "disabled";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
 		};
 
 		gsbi6: gsbi@16500000 {
@@ -382,6 +476,18 @@
 				clock-names = "core", "iface";
 				status = "disabled";
 			};
+
+			gsbi6_i2c: i2c@16580000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				pinctrl-0 = <&i2c6_pins>;
+				pinctrl-1 = <&i2c6_pins_sleep>;
+				pinctrl-names = "default", "sleep";
+				reg = <0x16580000 0x1000>;
+				interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
+				clocks = <&gcc GSBI6_QUP_CLK>,
+					 <&gcc GSBI6_H_CLK>;
+				clock-names = "core", "iface";
+			};
 		};
 
 		gsbi7: gsbi@16600000 {
@@ -405,6 +511,19 @@
 				clock-names = "core", "iface";
 				status = "disabled";
 			};
+
+			gsbi7_i2c: i2c@16680000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				pinctrl-0 = <&i2c7_pins>;
+				pinctrl-1 = <&i2c7_pins_sleep>;
+				pinctrl-names = "default", "sleep";
+				reg = <0x16680000 0x1000>;
+				interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
+				clocks = <&gcc GSBI7_QUP_CLK>,
+					 <&gcc GSBI7_H_CLK>;
+				clock-names = "core", "iface";
+				status = "disabled";
+			};
 		};
 
 		rng@1a500000 {
@@ -521,6 +640,11 @@
 					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names	= "ack", "err", "wakeup";
 
+			rpmcc: clock-controller {
+				compatible	= "qcom,rpmcc-apq8064", "qcom,rpmcc";
+				#clock-cells = <1>;
+			};
+
 			regulators {
 				compatible = "qcom,rpm-pm8921-regulators";
 
@@ -665,7 +789,7 @@
 		};
 
 		sata0: sata@29000000 {
-			compatible		= "generic-ahci";
+			compatible		= "qcom,apq8064-ahci", "generic-ahci";
 			status			= "disabled";
 			reg			= <0x29000000 0x180>;
 			interrupts		= <GIC_SPI 209 IRQ_TYPE_NONE>;
@@ -687,6 +811,7 @@
 
 			phys			= <&sata_phy0>;
 			phy-names		= "sata-phy";
+			ports-implemented	= <0x1>;
 		};
 
 		/* Temporary fixed regulator */
@@ -721,7 +846,7 @@
 		};
 
 		amba {
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -823,3 +948,4 @@
 		};
 	};
 };
+#include "qcom-apq8064-pins.dtsi"
diff --git a/sys/gnu/dts/arm/qcom-apq8084.dtsi b/sys/gnu/dts/arm/qcom-apq8084.dtsi
index 08214cbae16d..a33a09f6821e 100644
--- a/sys/gnu/dts/arm/qcom-apq8084.dtsi
+++ b/sys/gnu/dts/arm/qcom-apq8084.dtsi
@@ -91,6 +91,20 @@
 		interrupts = <1 7 0xf04>;
 	};
 
+	clocks {
+		xo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
+		sleep_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <1 2 0xf08>,
diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1-c1.dts b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1-c1.dts
new file mode 100644
index 000000000000..0d92f1bc3a13
--- /dev/null
+++ b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -0,0 +1,22 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019-ap.dk01.1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+
+};
diff --git a/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1.dtsi b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1.dtsi
new file mode 100644
index 000000000000..b9457dd21a69
--- /dev/null
+++ b/sys/gnu/dts/arm/qcom-ipq4019-ap.dk01.1.dtsi
@@ -0,0 +1,112 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qcom-ipq4019.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
+	compatible = "qcom,ipq4019";
+
+	clocks {
+                xo: xo {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+	};
+
+	soc {
+
+
+		timer {
+			compatible = "arm,armv7-timer";
+			interrupts = <1 2 0xf08>,
+				     <1 3 0xf08>,
+				     <1 4 0xf08>,
+				     <1 1 0xf08>;
+			clock-frequency = <48000000>;
+		};
+
+		pinctrl@0x01000000 {
+			serial_pins: serial_pinmux {
+				mux {
+					pins = "gpio60", "gpio61";
+					function = "blsp_uart0";
+					bias-disable;
+				};
+			};
+
+			spi_0_pins: spi_0_pinmux {
+				pinmux {
+					function = "blsp_spi0";
+					pins = "gpio55", "gpio56", "gpio57";
+				};
+				pinmux_cs {
+					function = "gpio";
+					pins = "gpio54";
+				};
+				pinconf {
+					pins = "gpio55", "gpio56", "gpio57";
+					drive-strength = <12>;
+					bias-disable;
+				};
+				pinconf_cs {
+					pins = "gpio54";
+					drive-strength = <2>;
+					bias-disable;
+					output-high;
+				};
+			};
+		};
+
+		blsp_dma: dma@7884000 {
+			status = "ok";
+		};
+
+		spi_0: spi@78b5000 {
+			pinctrl-0 = <&spi_0_pins>;
+			pinctrl-names = "default";
+			status = "ok";
+			cs-gpios = <&tlmm 54 0>;
+
+			mx25l25635e@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0>;
+				compatible = "mx25l25635e";
+				spi-max-frequency = <24000000>;
+			};
+		};
+
+		serial@78af000 {
+			pinctrl-0 = <&serial_pins>;
+			pinctrl-names = "default";
+			status = "ok";
+		};
+
+		cryptobam: dma@8e04000 {
+			status = "ok";
+		};
+
+		crypto@8e3a000 {
+			status = "ok";
+		};
+
+		watchdog@b017000 {
+			status = "ok";
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/qcom-ipq4019.dtsi b/sys/gnu/dts/arm/qcom-ipq4019.dtsi
new file mode 100644
index 000000000000..5c08d19066c2
--- /dev/null
+++ b/sys/gnu/dts/arm/qcom-ipq4019.dtsi
@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ4019";
+	compatible = "qcom,ipq4019";
+	interrupt-parent = <&intc>;
+
+	aliases {
+		spi0 = &spi_0;
+		i2c0 = &i2c_0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			enable-method = "qcom,kpss-acc-v1";
+			qcom,acc = <&acc0>;
+			qcom,saw = <&saw0>;
+			reg = <0x0>;
+			clocks = <&gcc GCC_APPS_CLK_SRC>;
+			clock-frequency = <0>;
+			operating-points = <
+				/* kHz	uV (fixed) */
+				48000	1100000
+				200000	1100000
+				500000	1100000
+				666000	1100000
+			>;
+			clock-latency = <256000>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			enable-method = "qcom,kpss-acc-v1";
+			qcom,acc = <&acc1>;
+			qcom,saw = <&saw1>;
+			reg = <0x1>;
+			clocks = <&gcc GCC_APPS_CLK_SRC>;
+			clock-frequency = <0>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			enable-method = "qcom,kpss-acc-v1";
+			qcom,acc = <&acc2>;
+			qcom,saw = <&saw2>;
+			reg = <0x2>;
+			clocks = <&gcc GCC_APPS_CLK_SRC>;
+			clock-frequency = <0>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			enable-method = "qcom,kpss-acc-v1";
+			qcom,acc = <&acc3>;
+			qcom,saw = <&saw3>;
+			reg = <0x3>;
+			clocks = <&gcc GCC_APPS_CLK_SRC>;
+			clock-frequency = <0>;
+		};
+	};
+
+	clocks {
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "simple-bus";
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x0b000000 0x1000>,
+			<0x0b002000 0x1000>;
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-ipq4019";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			reg = <0x1800000 0x60000>;
+		};
+
+		tlmm: pinctrl@0x01000000 {
+			compatible = "qcom,ipq4019-pinctrl";
+			reg = <0x01000000 0x300000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <0 208 0>;
+		};
+
+		blsp_dma: dma@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x23000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			status = "disabled";
+		};
+
+		spi_0: spi@78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x78b5000 0x600>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c_0: i2c@78b7000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x78b7000 0x6000>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+
+		cryptobam: dma@8e04000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x08e04000 0x20000>;
+			interrupts = <GIC_SPI 207 0>;
+			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <1>;
+			qcom,controlled-remotely;
+			status = "disabled";
+		};
+
+		crypto@8e3a000 {
+			compatible = "qcom,crypto-v5.1";
+			reg = <0x08e3a000 0x6000>;
+			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
+				 <&gcc GCC_CRYPTO_AXI_CLK>,
+				 <&gcc GCC_CRYPTO_CLK>;
+			clock-names = "iface", "bus", "core";
+			dmas = <&cryptobam 2>, <&cryptobam 3>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+                acc0: clock-controller@b088000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+                };
+
+                acc1: clock-controller@b098000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+                };
+
+                acc2: clock-controller@b0a8000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+                };
+
+                acc3: clock-controller@b0b8000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+                };
+
+                saw0: regulator@b089000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
+                        regulator;
+                };
+
+                saw1: regulator@b099000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
+                        regulator;
+                };
+
+                saw2: regulator@b0a9000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
+                        regulator;
+                };
+
+                saw3: regulator@b0b9000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
+                        regulator;
+                };
+
+		serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x78af000 0x200>;
+			interrupts = <0 107 0>;
+			status = "disabled";
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+				<&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
+			dma-names = "rx", "tx";
+		};
+
+		serial@78b0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x78b0000 0x200>;
+			interrupts = <0 108 0>;
+			status = "disabled";
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+				<&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
+			dma-names = "rx", "tx";
+		};
+
+		watchdog@b017000 {
+			compatible = "qcom,kpss-standalone";
+			reg = <0xb017000 0x40>;
+			clocks = <&sleep_clk>;
+			timeout-sec = <10>;
+			status = "disabled";
+		};
+
+		restart@4ab000 {
+			compatible = "qcom,pshold";
+			reg = <0x4ab000 0x4>;
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/qcom-ipq8064.dtsi b/sys/gnu/dts/arm/qcom-ipq8064.dtsi
index fa698635eea0..2601a907947b 100644
--- a/sys/gnu/dts/arm/qcom-ipq8064.dtsi
+++ b/sys/gnu/dts/arm/qcom-ipq8064.dtsi
@@ -62,6 +62,18 @@
 	};
 
 	clocks {
+		cxo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
+		pxo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <27000000>;
+		};
+
 		sleep_clk: sleep_clk {
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
diff --git a/sys/gnu/dts/arm/qcom-msm8660.dtsi b/sys/gnu/dts/arm/qcom-msm8660.dtsi
index e5f7f33aa467..cd214030b84a 100644
--- a/sys/gnu/dts/arm/qcom-msm8660.dtsi
+++ b/sys/gnu/dts/arm/qcom-msm8660.dtsi
@@ -42,6 +42,26 @@
 		interrupts = <1 9 0x304>;
 	};
 
+	clocks {
+		cxo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
+		pxo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <27000000>;
+		};
+
+		sleep_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
 	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -167,7 +187,7 @@
 		};
 
 		amba {
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
diff --git a/sys/gnu/dts/arm/qcom-msm8960.dtsi b/sys/gnu/dts/arm/qcom-msm8960.dtsi
index 51a40d84145c..da05e28a81a7 100644
--- a/sys/gnu/dts/arm/qcom-msm8960.dtsi
+++ b/sys/gnu/dts/arm/qcom-msm8960.dtsi
@@ -251,7 +251,7 @@
 		};
 
 		amba {
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
diff --git a/sys/gnu/dts/arm/qcom-msm8974.dtsi b/sys/gnu/dts/arm/qcom-msm8974.dtsi
index dfdafdcb8aae..6f164266a010 100644
--- a/sys/gnu/dts/arm/qcom-msm8974.dtsi
+++ b/sys/gnu/dts/arm/qcom-msm8974.dtsi
@@ -14,10 +14,55 @@
 		#size-cells = <1>;
 		ranges;
 
+		mpss@08000000 {
+			reg = <0x08000000 0x5100000>;
+			no-map;
+		};
+
+		mba@00d100000 {
+			reg = <0x0d100000 0x100000>;
+			no-map;
+		};
+
+		reserved@0d200000 {
+			reg = <0x0d200000 0xa00000>;
+			no-map;
+		};
+
+		adsp@0dc00000 {
+			reg = <0x0dc00000 0x1900000>;
+			no-map;
+		};
+
+		venus@0f500000 {
+			reg = <0x0f500000 0x500000>;
+			no-map;
+		};
+
 		smem_region: smem@fa00000 {
 			reg = <0xfa00000 0x200000>;
 			no-map;
 		};
+
+		tz@0fc00000 {
+			reg = <0x0fc00000 0x160000>;
+			no-map;
+		};
+
+		rfsa@0fd60000 {
+			reg = <0x0fd60000 0x20000>;
+			no-map;
+		};
+
+		rmtfs@0fd80000 {
+			reg = <0x0fd80000 0x180000>;
+			no-map;
+		};
+
+		unused@0ff00000 {
+			reg = <0x0ff00000 0x10100000>;
+			no-map;
+		};
 	};
 
 	cpus {
@@ -91,6 +136,20 @@
 		interrupts = <1 7 0xf04>;
 	};
 
+	clocks {
+		xo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
+		sleep_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <1 2 0xf08>,
@@ -109,6 +168,98 @@
 		hwlocks = <&tcsr_mutex 3>;
 	};
 
+	smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
+
+		qcom,ipc = <&apcs 8 14>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-wcnss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <451>, <431>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
+
+		qcom,ipc = <&apcs 8 18>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <4>;
+
+		wcnss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,state-cells = <1>;
+		};
+
+		wcnss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smsm {
+		compatible = "qcom,smsm";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,ipc-1 = <&apcs 8 13>;
+		qcom,ipc-2 = <&apcs 8 9>;
+		qcom,ipc-3 = <&apcs 8 19>;
+
+		apps_smsm: apps@0 {
+			reg = <0>;
+
+			#qcom,state-cells = <1>;
+		};
+
+		modem_smsm: modem@1 {
+			reg = <1>;
+			interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		adsp_smsm: adsp@2 {
+			reg = <2>;
+			interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		wcnss_smsm: wcnss@7 {
+			reg = <7>;
+			interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -319,6 +470,17 @@
 			interrupts = <0 208 0>;
 		};
 
+		i2c@f9924000 {
+			status = "disabled";
+			compatible = "qcom,i2c-qup-v2.1.1";
+			reg = <0xf9924000 0x1000>;
+			interrupts = <0 96 IRQ_TYPE_NONE>;
+			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		blsp_i2c8: i2c@f9964000 {
 			status = "disabled";
 			compatible = "qcom,i2c-qup-v2.1.1";
@@ -361,6 +523,13 @@
 	smd {
 		compatible = "qcom,smd";
 
+		modem {
+			interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
+
+			qcom,ipc = <&apcs 8 12>;
+			qcom,smd-edge = <0>;
+		};
+
 		rpm {
 			interrupts = <0 168 1>;
 			qcom,ipc = <&apcs 8 0>;
diff --git a/sys/gnu/dts/arm/qcom-pm8841.dtsi b/sys/gnu/dts/arm/qcom-pm8841.dtsi
index 9f357f68713c..0512f645922e 100644
--- a/sys/gnu/dts/arm/qcom-pm8841.dtsi
+++ b/sys/gnu/dts/arm/qcom-pm8841.dtsi
@@ -11,7 +11,7 @@
 
 		pm8841_mpps: mpps@a000 {
 			compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp";
-			reg = <0xa000 0x400>;
+			reg = <0xa000>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupts = <4 0xa0 0 IRQ_TYPE_NONE>,
@@ -22,7 +22,7 @@
 
 		temp-alarm@2400 {
 			compatible = "qcom,spmi-temp-alarm";
-			reg = <0x2400 0x100>;
+			reg = <0x2400>;
 			interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>;
 		};
 	};
diff --git a/sys/gnu/dts/arm/qcom-pm8941.dtsi b/sys/gnu/dts/arm/qcom-pm8941.dtsi
index ca53a5947437..d95edb6f6265 100644
--- a/sys/gnu/dts/arm/qcom-pm8941.dtsi
+++ b/sys/gnu/dts/arm/qcom-pm8941.dtsi
@@ -12,15 +12,15 @@
 
 		rtc@6000 {
 			compatible = "qcom,pm8941-rtc";
-			reg = <0x6000 0x100>,
-			      <0x6100 0x100>;
+			reg = <0x6000>,
+			      <0x6100>;
 			reg-names = "rtc", "alarm";
 			interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
 		};
 
 		pwrkey@800 {
 			compatible = "qcom,pm8941-pwrkey";
-			reg = <0x800 0x100>;
+			reg = <0x800>;
 			interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
 			debounce = <15625>;
 			bias-pull-up;
@@ -28,7 +28,7 @@
 
 		charger@1000 {
 			compatible = "qcom,pm8941-charger";
-			reg = <0x1000 0x700>;
+			reg = <0x1000>;
 			interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
 				     <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
 				     <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>,
@@ -49,7 +49,7 @@
 
 		pm8941_gpios: gpios@c000 {
 			compatible = "qcom,pm8941-gpio", "qcom,spmi-gpio";
-			reg = <0xc000 0x2400>;
+			reg = <0xc000>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
@@ -92,7 +92,7 @@
 
 		pm8941_mpps: mpps@a000 {
 			compatible = "qcom,pm8941-mpp", "qcom,spmi-mpp";
-			reg = <0xa000 0x800>;
+			reg = <0xa000>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
@@ -107,7 +107,7 @@
 
 		pm8941_temp: temp-alarm@2400 {
 			compatible = "qcom,spmi-temp-alarm";
-			reg = <0x2400 0x100>;
+			reg = <0x2400>;
 			interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
 			io-channels = <&pm8941_vadc VADC_DIE_TEMP>;
 			io-channel-names = "thermal";
@@ -116,7 +116,7 @@
 
 		pm8941_vadc: vadc@3100 {
 			compatible = "qcom,spmi-vadc";
-			reg = <0x3100 0x100>;
+			reg = <0x3100>;
 			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -141,7 +141,7 @@
 
 		pm8941_iadc: iadc@3600 {
 			compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc";
-			reg = <0x3600 0x100>;
+			reg = <0x3600>;
 			interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
 			qcom,external-resistor-micro-ohms = <10000>;
 		};
@@ -161,7 +161,7 @@
 
 		pm8941_wled: wled@d800 {
 			compatible = "qcom,pm8941-wled";
-			reg = <0xd800 0x100>;
+			reg = <0xd800>;
 			label = "backlight";
 
 			status = "disabled";
diff --git a/sys/gnu/dts/arm/r7s72100.dtsi b/sys/gnu/dts/arm/r7s72100.dtsi
index 4657d7fb5bce..e8e2a5d71976 100644
--- a/sys/gnu/dts/arm/r7s72100.dtsi
+++ b/sys/gnu/dts/arm/r7s72100.dtsi
@@ -10,6 +10,7 @@
  */
 
 #include <dt-bindings/clock/r7s72100-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -36,46 +37,41 @@
 		#size-cells = <1>;
 
 		/* External clocks */
-		extal_clk: extal_clk {
+		extal_clk: extal {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			/* If clk present, value must be set by board */
 			clock-frequency = <0>;
-			clock-output-names = "extal";
 		};
 
-		usb_x1_clk: usb_x1_clk {
+		usb_x1_clk: usb_x1 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			/* If clk present, value must be set by board */
 			clock-frequency = <0>;
-			clock-output-names = "usb_x1";
 		};
 
 		/* Fixed factor clocks */
-		b_clk: b_clk {
+		b_clk: b {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
 			clock-mult = <1>;
 			clock-div = <3>;
-			clock-output-names = "b";
 		};
-		p1_clk: p1_clk {
+		p1_clk: p1 {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
 			clock-mult = <1>;
 			clock-div = <6>;
-			clock-output-names = "p1";
 		};
-		p0_clk: p0_clk {
+		p0_clk: p0 {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
 			clock-mult = <1>;
 			clock-div = <12>;
-			clock-output-names = "p0";
 		};
 
 		/* Special CPG clocks */
@@ -152,12 +148,12 @@
 	scif0: serial@e8007000 {
 		compatible = "renesas,scif-r7s72100", "renesas,scif";
 		reg = <0xe8007000 64>;
-		interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 191 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 192 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 189 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
@@ -165,12 +161,12 @@
 	scif1: serial@e8007800 {
 		compatible = "renesas,scif-r7s72100", "renesas,scif";
 		reg = <0xe8007800 64>;
-		interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 195 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 196 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 193 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
@@ -178,12 +174,12 @@
 	scif2: serial@e8008000 {
 		compatible = "renesas,scif-r7s72100", "renesas,scif";
 		reg = <0xe8008000 64>;
-		interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 199 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 200 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 197 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
@@ -191,12 +187,12 @@
 	scif3: serial@e8008800 {
 		compatible = "renesas,scif-r7s72100", "renesas,scif";
 		reg = <0xe8008800 64>;
-		interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 203 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 204 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 201 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
@@ -204,12 +200,12 @@
 	scif4: serial@e8009000 {
 		compatible = "renesas,scif-r7s72100", "renesas,scif";
 		reg = <0xe8009000 64>;
-		interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 207 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 208 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 205 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
@@ -217,12 +213,12 @@
 	scif5: serial@e8009800 {
 		compatible = "renesas,scif-r7s72100", "renesas,scif";
 		reg = <0xe8009800 64>;
-		interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 211 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 212 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 209 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
@@ -230,12 +226,12 @@
 	scif6: serial@e800a000 {
 		compatible = "renesas,scif-r7s72100", "renesas,scif";
 		reg = <0xe800a000 64>;
-		interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 215 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 216 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 213 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
@@ -243,12 +239,12 @@
 	scif7: serial@e800a800 {
 		compatible = "renesas,scif-r7s72100", "renesas,scif";
 		reg = <0xe800a800 64>;
-		interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 219 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 220 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 217 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
@@ -256,9 +252,9 @@
 	spi0: spi@e800c800 {
 		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 		reg = <0xe800c800 0x24>;
-		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 239 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 240 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
 		power-domains = <&cpg_clocks>;
@@ -271,9 +267,9 @@
 	spi1: spi@e800d000 {
 		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 		reg = <0xe800d000 0x24>;
-		interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 242 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 243 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
 		power-domains = <&cpg_clocks>;
@@ -286,9 +282,9 @@
 	spi2: spi@e800d800 {
 		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 		reg = <0xe800d800 0x24>;
-		interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 245 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 246 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
 		power-domains = <&cpg_clocks>;
@@ -301,9 +297,9 @@
 	spi3: spi@e800e000 {
 		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 		reg = <0xe800e000 0x24>;
-		interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 248 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 249 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
 		power-domains = <&cpg_clocks>;
@@ -316,9 +312,9 @@
 	spi4: spi@e800e800 {
 		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 		reg = <0xe800e800 0x24>;
-		interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 251 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 252 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
 		power-domains = <&cpg_clocks>;
@@ -342,14 +338,14 @@
 		#size-cells = <0>;
 		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 		reg = <0xfcfee000 0x44>;
-		interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 158 IRQ_TYPE_EDGE_RISING>,
-			     <0 159 IRQ_TYPE_EDGE_RISING>,
-			     <0 160 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 161 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 162 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 163 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 164 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
 		clock-frequency = <100000>;
 		power-domains = <&cpg_clocks>;
@@ -361,14 +357,14 @@
 		#size-cells = <0>;
 		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 		reg = <0xfcfee400 0x44>;
-		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 166 IRQ_TYPE_EDGE_RISING>,
-			     <0 167 IRQ_TYPE_EDGE_RISING>,
-			     <0 168 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 169 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 170 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 171 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 172 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
 		clock-frequency = <100000>;
 		power-domains = <&cpg_clocks>;
@@ -380,14 +376,14 @@
 		#size-cells = <0>;
 		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 		reg = <0xfcfee800 0x44>;
-		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 174 IRQ_TYPE_EDGE_RISING>,
-			     <0 175 IRQ_TYPE_EDGE_RISING>,
-			     <0 176 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 177 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 178 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 179 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 180 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
 		clock-frequency = <100000>;
 		power-domains = <&cpg_clocks>;
@@ -399,14 +395,14 @@
 		#size-cells = <0>;
 		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 		reg = <0xfcfeec00 0x44>;
-		interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 182 IRQ_TYPE_EDGE_RISING>,
-			     <0 183 IRQ_TYPE_EDGE_RISING>,
-			     <0 184 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 185 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 186 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 187 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 188 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
 		clock-frequency = <100000>;
 		power-domains = <&cpg_clocks>;
@@ -416,7 +412,7 @@
 	mtu2: timer@fcff0000 {
 		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
 		reg = <0xfcff0000 0x400>;
-		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "tgi0a";
 		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
 		clock-names = "fck";
diff --git a/sys/gnu/dts/arm/r8a73a4-ape6evm.dts b/sys/gnu/dts/arm/r8a73a4-ape6evm.dts
index 590257095700..93ace33e3e36 100644
--- a/sys/gnu/dts/arm/r8a73a4-ape6evm.dts
+++ b/sys/gnu/dts/arm/r8a73a4-ape6evm.dts
@@ -189,28 +189,28 @@
 
 &pfc {
 	scifa0_pins: serial0 {
-		renesas,groups = "scifa0_data";
-		renesas,function = "scifa0";
+		groups = "scifa0_data";
+		function = "scifa0";
 	};
 
 	mmc0_pins: mmc {
-		renesas,groups = "mmc0_data8", "mmc0_ctrl";
-		renesas,function = "mmc0";
+		groups = "mmc0_data8", "mmc0_ctrl";
+		function = "mmc0";
 	};
 
 	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
-		renesas,function = "sdhi0";
+		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
+		function = "sdhi0";
 	};
 
 	sdhi1_pins: sd1 {
-		renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
-		renesas,function = "sdhi1";
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
 	};
 
 	keyboard_pins: keyboard {
-		renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327",
-			       "PORT328", "PORT329";
+		pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328",
+		       "PORT329";
 		bias-pull-up;
 	};
 };
diff --git a/sys/gnu/dts/arm/r8a73a4.dtsi b/sys/gnu/dts/arm/r8a73a4.dtsi
index cb4f7b2798fe..6954912a3753 100644
--- a/sys/gnu/dts/arm/r8a73a4.dtsi
+++ b/sys/gnu/dts/arm/r8a73a4.dtsi
@@ -29,6 +29,7 @@
 			reg = <0>;
 			clock-frequency = <1500000000>;
 			power-domains = <&pd_a2sl>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
@@ -39,10 +40,26 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+		power-domains = <&pd_a3sm>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+		power-domains = <&pd_a3km>;
+		cache-unified;
+		cache-level = <2>;
 	};
 
 	dbsc1: memory-controller@e6790000 {
@@ -69,27 +86,27 @@
 		dma0: dma-controller@e6700020 {
 			compatible = "renesas,shdma-r8a73a4";
 			reg = <0 0xe6700020 0 0x89e0>;
-			interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
-					0 200 IRQ_TYPE_LEVEL_HIGH
-					0 201 IRQ_TYPE_LEVEL_HIGH
-					0 202 IRQ_TYPE_LEVEL_HIGH
-					0 203 IRQ_TYPE_LEVEL_HIGH
-					0 204 IRQ_TYPE_LEVEL_HIGH
-					0 205 IRQ_TYPE_LEVEL_HIGH
-					0 206 IRQ_TYPE_LEVEL_HIGH
-					0 207 IRQ_TYPE_LEVEL_HIGH
-					0 208 IRQ_TYPE_LEVEL_HIGH
-					0 209 IRQ_TYPE_LEVEL_HIGH
-					0 210 IRQ_TYPE_LEVEL_HIGH
-					0 211 IRQ_TYPE_LEVEL_HIGH
-					0 212 IRQ_TYPE_LEVEL_HIGH
-					0 213 IRQ_TYPE_LEVEL_HIGH
-					0 214 IRQ_TYPE_LEVEL_HIGH
-					0 215 IRQ_TYPE_LEVEL_HIGH
-					0 216 IRQ_TYPE_LEVEL_HIGH
-					0 217 IRQ_TYPE_LEVEL_HIGH
-					0 218 IRQ_TYPE_LEVEL_HIGH
-					0 219 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+					GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error",
 					"ch0", "ch1", "ch2", "ch3",
 					"ch4", "ch5", "ch6", "ch7",
@@ -106,7 +123,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
 		reg = <0 0xe60b0000 0 0x428>;
-		interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
 		power-domains = <&pd_a3sp>;
 
@@ -116,7 +133,7 @@
 	cmt1: timer@e6130000 {
 		compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
 		reg = <0 0xe6130000 0 0x1004>;
-		interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
 		clock-names = "fck";
 		power-domains = <&pd_c5>;
@@ -131,38 +148,38 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		reg = <0 0xe61c0000 0 0x200>;
-		interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 3 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 4 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 5 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 6 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 7 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 8 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 9 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 10 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 11 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 12 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 13 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 14 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 15 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 16 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 17 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 18 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 19 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 20 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 21 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 22 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 23 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 24 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 25 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 26 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 27 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 28 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 29 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 30 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 31 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
 		power-domains = <&pd_c4>;
 	};
@@ -172,32 +189,32 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		reg = <0 0xe61c0200 0 0x200>;
-		interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 33 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 34 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 35 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 36 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 37 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 38 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 39 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 40 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 41 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 42 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 43 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 44 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 45 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 46 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 47 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 48 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 49 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 50 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 51 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 52 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 53 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 54 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 55 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 56 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 57 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
 		power-domains = <&pd_c4>;
 	};
@@ -237,7 +254,7 @@
 		compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
 		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
 			 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
-		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
 		power-domains = <&pd_c5>;
 	};
@@ -247,7 +264,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
 		reg = <0 0xe6500000 0 0x428>;
-		interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -258,7 +275,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
 		reg = <0 0xe6510000 0 0x428>;
-		interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -269,7 +286,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
 		reg = <0 0xe6520000 0 0x428>;
-		interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -280,7 +297,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
 		reg = <0 0xe6530000 0 0x428>;
-		interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -291,7 +308,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
 		reg = <0 0xe6540000 0 0x428>;
-		interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -302,7 +319,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
 		reg = <0 0xe6550000 0 0x428>;
-		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -313,7 +330,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
 		reg = <0 0xe6560000 0 0x428>;
-		interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -324,7 +341,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
 		reg = <0 0xe6570000 0 0x428>;
-		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -333,9 +350,9 @@
 	scifb0: serial@e6c20000 {
 		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
 		reg = <0 0xe6c20000 0 0x100>;
-		interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -343,9 +360,9 @@
 	scifb1: serial@e6c30000 {
 		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
 		reg = <0 0xe6c30000 0 0x100>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -353,9 +370,9 @@
 	scifa0: serial@e6c40000 {
 		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
 		reg = <0 0xe6c40000 0 0x100>;
-		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -363,9 +380,9 @@
 	scifa1: serial@e6c50000 {
 		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
 		reg = <0 0xe6c50000 0 0x100>;
-		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -373,9 +390,9 @@
 	scifb2: serial@e6ce0000 {
 		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
 		reg = <0 0xe6ce0000 0 0x100>;
-		interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -383,9 +400,9 @@
 	scifb3: serial@e6cf0000 {
 		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
 		reg = <0 0xe6cf0000 0 0x100>;
-		interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_c4>;
 		status = "disabled";
 	};
@@ -393,7 +410,7 @@
 	sdhi0: sd@ee100000 {
 		compatible = "renesas,sdhi-r8a73a4";
 		reg = <0 0xee100000 0 0x100>;
-		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
 		power-domains = <&pd_a3sp>;
 		cap-sd-highspeed;
@@ -403,7 +420,7 @@
 	sdhi1: sd@ee120000 {
 		compatible = "renesas,sdhi-r8a73a4";
 		reg = <0 0xee120000 0 0x100>;
-		interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
 		power-domains = <&pd_a3sp>;
 		cap-sd-highspeed;
@@ -413,7 +430,7 @@
 	sdhi2: sd@ee140000 {
 		compatible = "renesas,sdhi-r8a73a4";
 		reg = <0 0xee140000 0 0x100>;
-		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
 		power-domains = <&pd_a3sp>;
 		cap-sd-highspeed;
@@ -423,7 +440,7 @@
 	mmcif0: mmc@ee200000 {
 		compatible = "renesas,sh-mmcif";
 		reg = <0 0xee200000 0 0x80>;
-		interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
 		power-domains = <&pd_a3sp>;
 		reg-io-width = <4>;
@@ -433,7 +450,7 @@
 	mmcif1: mmc@ee220000 {
 		compatible = "renesas,sh-mmcif";
 		reg = <0 0xee220000 0 0x80>;
-		interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
 		power-domains = <&pd_a3sp>;
 		reg-io-width = <4>;
@@ -449,7 +466,7 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	bsc: bus@fec10000 {
@@ -469,37 +486,32 @@
 		ranges;
 
 		/* External root clocks */
-		extalr_clk: extalr_clk {
+		extalr_clk: extalr {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <32768>;
-			clock-output-names = "extalr";
 		};
-		extal1_clk: extal1_clk {
+		extal1_clk: extal1 {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <25000000>;
-			clock-output-names = "extal1";
 		};
-		extal2_clk: extal2_clk {
+		extal2_clk: extal2 {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <48000000>;
-			clock-output-names = "extal2";
 		};
-		fsiack_clk: fsiack_clk {
+		fsiack_clk: fsiack {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			/* This value must be overridden by the board. */
 			clock-frequency = <0>;
-			clock-output-names = "fsiack";
 		};
-		fsibck_clk: fsibck_clk {
+		fsibck_clk: fsibck {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			/* This value must be overridden by the board. */
 			clock-frequency = <0>;
-			clock-output-names = "fsibck";
 		};
 
 		/* Special CPG clocks */
@@ -523,171 +535,151 @@
 			#clock-cells = <0>;
 			clock-output-names = "zb";
 		};
-		sdhi0_clk: sdhi0_clk@e6150074 {
+		sdhi0_clk: sdhi0ck@e6150074 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150074 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sdhi0ck";
 		};
-		sdhi1_clk: sdhi1_clk@e6150078 {
+		sdhi1_clk: sdhi1ck@e6150078 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150078 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sdhi1ck";
 		};
-		sdhi2_clk: sdhi2_clk@e615007c {
+		sdhi2_clk: sdhi2ck@e615007c {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe615007c 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sdhi2ck";
 		};
-		mmc0_clk: mmc0_clk@e6150240 {
+		mmc0_clk: mmc0@e6150240 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150240 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "mmc0";
 		};
-		mmc1_clk: mmc1_clk@e6150244 {
+		mmc1_clk: mmc1@e6150244 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150244 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "mmc1";
 		};
-		vclk1_clk: vclk1_clk@e6150008 {
+		vclk1_clk: vclk1@e6150008 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150008 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>, <&main_div2_clk>,
 				 <&extalr_clk>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk1";
 		};
-		vclk2_clk: vclk2_clk@e615000c {
+		vclk2_clk: vclk2@e615000c {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe615000c 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>, <&main_div2_clk>,
 				 <&extalr_clk>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk2";
 		};
-		vclk3_clk: vclk3_clk@e615001c {
+		vclk3_clk: vclk3@e615001c {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe615001c 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>, <&main_div2_clk>,
 				 <&extalr_clk>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk3";
 		};
-		vclk4_clk: vclk4_clk@e6150014 {
+		vclk4_clk: vclk4@e6150014 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150014 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>, <&main_div2_clk>,
 				 <&extalr_clk>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk4";
 		};
-		vclk5_clk: vclk5_clk@e6150034 {
+		vclk5_clk: vclk5@e6150034 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150034 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <0>, <&extal2_clk>, <&main_div2_clk>,
 				 <&extalr_clk>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk5";
 		};
-		fsia_clk: fsia_clk@e6150018 {
+		fsia_clk: fsia@e6150018 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150018 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <&fsiack_clk>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "fsia";
 		};
-		fsib_clk: fsib_clk@e6150090 {
+		fsib_clk: fsib@e6150090 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150090 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <&fsibck_clk>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "fsib";
 		};
-		mp_clk: mp_clk@e6150080 {
+		mp_clk: mp@e6150080 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150080 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <&extal2_clk>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "mp";
 		};
-		m4_clk: m4_clk@e6150098 {
+		m4_clk: m4@e6150098 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150098 0 4>;
 			clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
 			#clock-cells = <0>;
-			clock-output-names = "m4";
 		};
-		hsi_clk: hsi_clk@e615026c {
+		hsi_clk: hsi@e615026c {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe615026c 0 4>;
 			clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
 				 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "hsi";
 		};
-		spuv_clk: spuv_clk@e6150094 {
+		spuv_clk: spuv@e6150094 {
 			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150094 0 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
 				 <&extal2_clk>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "spuv";
 		};
 
 		/* Fixed factor clocks */
-		main_div2_clk: main_div2_clk {
+		main_div2_clk: main_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "main_div2";
 		};
-		pll0_div2_clk: pll0_div2_clk {
+		pll0_div2_clk: pll0_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "pll0_div2";
 		};
-		pll1_div2_clk: pll1_div2_clk {
+		pll1_div2_clk: pll1_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "pll1_div2";
 		};
-		extal1_div2_clk: extal1_div2_clk {
+		extal1_div2_clk: extal1_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&extal1_clk>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "extal1_div2";
 		};
 
 		/* Gate clocks */
diff --git a/sys/gnu/dts/arm/r8a7740-armadillo800eva.dts b/sys/gnu/dts/arm/r8a7740-armadillo800eva.dts
index c548cabb102f..2c82dab2b6f4 100644
--- a/sys/gnu/dts/arm/r8a7740-armadillo800eva.dts
+++ b/sys/gnu/dts/arm/r8a7740-armadillo800eva.dts
@@ -228,44 +228,44 @@
 	pinctrl-names = "default";
 
 	ether_pins: ether {
-		renesas,groups = "gether_mii", "gether_int";
-		renesas,function = "gether";
+		groups = "gether_mii", "gether_int";
+		function = "gether";
 	};
 
 	scifa1_pins: serial1 {
-		renesas,groups = "scifa1_data";
-		renesas,function = "scifa1";
+		groups = "scifa1_data";
+		function = "scifa1";
 	};
 
 	st1232_pins: touchscreen {
-		renesas,groups = "intc_irq10";
-		renesas,function = "intc";
+		groups = "intc_irq10";
+		function = "intc";
 	};
 
 	backlight_pins: backlight {
-		renesas,groups = "tpu0_to2_1";
-		renesas,function = "tpu0";
+		groups = "tpu0_to2_1";
+		function = "tpu0";
 	};
 
 	mmc0_pins: mmc0 {
-		renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";
-		renesas,function = "mmc0";
+		groups = "mmc0_data8_1", "mmc0_ctrl_1";
+		function = "mmc0";
 	};
 
 	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
-		renesas,function = "sdhi0";
+		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
+		function = "sdhi0";
 	};
 
 	fsia_pins: sounda {
-		renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
-				 "fsia_data_in_1", "fsia_data_out_0";
-		renesas,function = "fsia";
+		groups = "fsia_sclk_in", "fsia_mclk_out",
+			 "fsia_data_in_1", "fsia_data_out_0";
+		function = "fsia";
 	};
 
 	lcd0_pins: lcd0 {
-		renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
-		renesas,function = "lcd0";
+		groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
+		function = "lcd0";
 
 		/* DBGMD/LCDC0/FSIA MUX */
 		gpio-hog;
diff --git a/sys/gnu/dts/arm/r8a7740.dtsi b/sys/gnu/dts/arm/r8a7740.dtsi
index 6ef954766eef..39b2f88ad151 100644
--- a/sys/gnu/dts/arm/r8a7740.dtsi
+++ b/sys/gnu/dts/arm/r8a7740.dtsi
@@ -11,6 +11,7 @@
 /include/ "skeleton.dtsi"
 
 #include <dt-bindings/clock/r8a7740-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -41,7 +42,7 @@
 	L2: cache-controller {
 		compatible = "arm,pl310-cache";
 		reg = <0xf0100000 0x1000>;
-		interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		power-domains = <&pd_a3sm>;
 		arm,data-latency = <3 3 3>;
 		arm,tag-latency = <2 2 2>;
@@ -58,7 +59,7 @@
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	ptm {
@@ -69,7 +70,7 @@
 	cmt1: timer@e6138000 {
 		compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
 		reg = <0xe6138000 0x170>;
-		interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
 		clock-names = "fck";
 		power-domains = <&pd_c5>;
@@ -89,14 +90,14 @@
 			<0xe6900020 1>,
 			<0xe6900040 1>,
 			<0xe6900060 1>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 		power-domains = <&pd_a4s>;
 	};
@@ -111,14 +112,14 @@
 			<0xe6900024 1>,
 			<0xe6900044 1>,
 			<0xe6900064 1>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 		power-domains = <&pd_a4s>;
 	};
@@ -133,14 +134,14 @@
 			<0xe6900028 1>,
 			<0xe6900048 1>,
 			<0xe6900068 1>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 		power-domains = <&pd_a4s>;
 	};
@@ -155,14 +156,14 @@
 			<0xe690002c 1>,
 			<0xe690004c 1>,
 			<0xe690006c 1>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH
-			      0 149 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
 		power-domains = <&pd_a4s>;
 	};
@@ -171,7 +172,7 @@
 		compatible = "renesas,gether-r8a7740";
 		reg = <0xe9a00000 0x800>,
 		      <0xe9a01800 0x800>;
-		interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
 		power-domains = <&pd_a4s>;
 		phy-mode = "mii";
@@ -185,10 +186,10 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 		reg = <0xfff20000 0x425>;
-		interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
-			      0 202 IRQ_TYPE_LEVEL_HIGH
-			      0 203 IRQ_TYPE_LEVEL_HIGH
-			      0 204 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
 		power-domains = <&pd_a4r>;
 		status = "disabled";
@@ -199,10 +200,10 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
 		reg = <0xe6c20000 0x425>;
-		interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
-			      0 71 IRQ_TYPE_LEVEL_HIGH
-			      0 72 IRQ_TYPE_LEVEL_HIGH
-			      0 73 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -211,9 +212,9 @@
 	scifa0: serial@e6c40000 {
 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 		reg = <0xe6c40000 0x100>;
-		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -221,9 +222,9 @@
 	scifa1: serial@e6c50000 {
 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 		reg = <0xe6c50000 0x100>;
-		interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -231,9 +232,9 @@
 	scifa2: serial@e6c60000 {
 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 		reg = <0xe6c60000 0x100>;
-		interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -241,9 +242,9 @@
 	scifa3: serial@e6c70000 {
 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 		reg = <0xe6c70000 0x100>;
-		interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -251,9 +252,9 @@
 	scifa4: serial@e6c80000 {
 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 		reg = <0xe6c80000 0x100>;
-		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -261,9 +262,9 @@
 	scifa5: serial@e6cb0000 {
 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 		reg = <0xe6cb0000 0x100>;
-		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -271,9 +272,9 @@
 	scifa6: serial@e6cc0000 {
 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 		reg = <0xe6cc0000 0x100>;
-		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -281,9 +282,9 @@
 	scifa7: serial@e6cd0000 {
 		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
 		reg = <0xe6cd0000 0x100>;
-		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -291,9 +292,9 @@
 	scifb: serial@e6c30000 {
 		compatible = "renesas,scifb-r8a7740", "renesas,scifb";
 		reg = <0xe6c30000 0x100>;
-		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -329,8 +330,8 @@
 	mmcif0: mmc@e6bd0000 {
 		compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
 		reg = <0xe6bd0000 0x100>;
-		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
-			      0 57 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7740_CLK_MMC>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -339,9 +340,9 @@
 	sdhi0: sd@e6850000 {
 		compatible = "renesas,sdhi-r8a7740";
 		reg = <0xe6850000 0x100>;
-		interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
-			      0 118 IRQ_TYPE_LEVEL_HIGH
-			      0 119 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
 		power-domains = <&pd_a3sp>;
 		cap-sd-highspeed;
@@ -352,9 +353,9 @@
 	sdhi1: sd@e6860000 {
 		compatible = "renesas,sdhi-r8a7740";
 		reg = <0xe6860000 0x100>;
-		interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
-			      0 122 IRQ_TYPE_LEVEL_HIGH
-			      0 123 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
 		power-domains = <&pd_a3sp>;
 		cap-sd-highspeed;
@@ -365,9 +366,9 @@
 	sdhi2: sd@e6870000 {
 		compatible = "renesas,sdhi-r8a7740";
 		reg = <0xe6870000 0x100>;
-		interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
-			      0 126 IRQ_TYPE_LEVEL_HIGH
-			      0 127 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
 		power-domains = <&pd_a3sp>;
 		cap-sd-highspeed;
@@ -379,7 +380,7 @@
 		#sound-dai-cells = <1>;
 		compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
 		reg = <0xfe1f0000 0x400>;
-		interrupts = <0 9 0x4>;
+		interrupts = <GIC_SPI 9 0x4>;
 		clocks = <&mstp3_clks R8A7740_CLK_FSI>;
 		power-domains = <&pd_a4mp>;
 		status = "disabled";
@@ -388,9 +389,9 @@
 	tmu0: timer@fff80000 {
 		compatible = "renesas,tmu-r8a7740", "renesas,tmu";
 		reg = <0xfff80000 0x2c>;
-		interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 199 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 200 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
 		clock-names = "fck";
 		power-domains = <&pd_a4r>;
@@ -403,9 +404,9 @@
 	tmu1: timer@fff90000 {
 		compatible = "renesas,tmu-r8a7740", "renesas,tmu";
 		reg = <0xfff90000 0x2c>;
-		interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 171 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 172 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
 		clock-names = "fck";
 		power-domains = <&pd_a4r>;
@@ -421,53 +422,45 @@
 		ranges;
 
 		/* External root clock */
-		extalr_clk: extalr_clk {
+		extalr_clk: extalr {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <32768>;
-			clock-output-names = "extalr";
 		};
-		extal1_clk: extal1_clk {
+		extal1_clk: extal1 {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "extal1";
 		};
-		extal2_clk: extal2_clk {
+		extal2_clk: extal2 {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "extal2";
 		};
-		dv_clk: dv_clk {
+		dv_clk: dv {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <27000000>;
-			clock-output-names = "dv";
 		};
-		fmsick_clk: fmsick_clk {
+		fmsick_clk: fmsick {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "fmsick";
 		};
-		fmsock_clk: fmsock_clk {
+		fmsock_clk: fmsock {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "fmsock";
 		};
-		fsiack_clk: fsiack_clk {
+		fsiack_clk: fsiack {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "fsiack";
 		};
-		fsibck_clk: fsibck_clk {
+		fsibck_clk: fsibck {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "fsibck";
 		};
 
 		/* Special CPG clocks */
@@ -485,7 +478,7 @@
 		};
 
 		/* Variable factor clocks (DIV6) */
-		vclk1_clk: vclk1_clk@e6150008 {
+		vclk1_clk: vclk1@e6150008 {
 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150008 4>;
 			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
@@ -493,9 +486,8 @@
 				 <&extal1_div2_clk>, <&extalr_clk>, <0>,
 				 <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk1";
 		};
-		vclk2_clk: vclk2_clk@e615000c {
+		vclk2_clk: vclk2@e615000c {
 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615000c 4>;
 			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
@@ -503,77 +495,67 @@
 				 <&extal1_div2_clk>, <&extalr_clk>, <0>,
 				 <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk2";
 		};
-		fmsi_clk: fmsi_clk@e6150010 {
+		fmsi_clk: fmsi@e6150010 {
 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150010 4>;
 			clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "fmsi";
 		};
-		fmso_clk: fmso_clk@e6150014 {
+		fmso_clk: fmso@e6150014 {
 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150014 4>;
 			clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "fmso";
 		};
-		fsia_clk: fsia_clk@e6150018 {
+		fsia_clk: fsia@e6150018 {
 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150018 4>;
 			clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "fsia";
 		};
-		sub_clk: sub_clk@e6150080 {
+		sub_clk: sub@e6150080 {
 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150080 4>;
 			clocks = <&pllc1_div2_clk>,
 				 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "sub";
 		};
-		spu_clk: spu_clk@e6150084 {
+		spu_clk: spu@e6150084 {
 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150084 4>;
 			clocks = <&pllc1_div2_clk>,
 				 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "spu";
 		};
-		vou_clk: vou_clk@e6150088 {
+		vou_clk: vou@e6150088 {
 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150088 4>;
 			clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
 				 <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vou";
 		};
-		stpro_clk: stpro_clk@e615009c {
+		stpro_clk: stpro@e615009c {
 			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615009c 4>;
 			clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
 			#clock-cells = <0>;
-			clock-output-names = "stpro";
 		};
 
 		/* Fixed factor clocks */
-		pllc1_div2_clk: pllc1_div2_clk {
+		pllc1_div2_clk: pllc1_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "pllc1_div2";
 		};
-		extal1_div2_clk: extal1_div2_clk {
+		extal1_div2_clk: extal1_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&extal1_clk>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "extal1_div2";
 		};
 
 		/* Gate clocks */
diff --git a/sys/gnu/dts/arm/r8a7778-bockw.dts b/sys/gnu/dts/arm/r8a7778-bockw.dts
index a52b359e2ae2..e0dab1464648 100644
--- a/sys/gnu/dts/arm/r8a7778-bockw.dts
+++ b/sys/gnu/dts/arm/r8a7778-bockw.dts
@@ -126,49 +126,57 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif0_pins: serial0 {
-		renesas,groups = "scif0_data_a", "scif0_ctrl";
-		renesas,function = "scif0";
+		groups = "scif0_data_a", "scif0_ctrl";
+		function = "scif0";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk";
+		function = "scif_clk";
 	};
 
 	mmc_pins: mmc {
-		renesas,groups = "mmc_data8", "mmc_ctrl";
-		renesas,function = "mmc";
+		groups = "mmc_data8", "mmc_ctrl";
+		function = "mmc";
 	};
 
 	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
-		renesas,function = "sdhi0";
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
 	};
 	sdhi0_pup_pins: sd0_pup {
-		renesas,groups = "sdhi0_cd", "sdhi0_wp";
-		renesas,function = "sdhi0";
+		groups = "sdhi0_cd", "sdhi0_wp";
+		function = "sdhi0";
 		bias-pull-up;
 	};
 
 	hspi0_pins: hspi0 {
-		renesas,groups = "hspi0_a";
-		renesas,function = "hspi0";
+		groups = "hspi0_a";
+		function = "hspi0";
 	};
 
 	usb0_pins: usb0 {
-		renesas,groups = "usb0";
-		renesas,function = "usb0";
+		groups = "usb0";
+		function = "usb0";
 	};
 
 	usb1_pins: usb1 {
-		renesas,groups = "usb1";
-		renesas,function = "usb1";
+		groups = "usb1";
+		function = "usb1";
 	};
 
 	vin0_pins: vin0 {
-		renesas,groups = "vin0_data8", "vin0_clk";
-		renesas,function = "vin0";
+		groups = "vin0_data8", "vin0_clk";
+		function = "vin0";
 	};
 
 	vin1_pins: vin1 {
-		renesas,groups = "vin1_data8", "vin1_clk";
-		renesas,function = "vin1";
+		groups = "vin1_data8", "vin1_clk";
+		function = "vin1";
 	};
 };
 
@@ -217,3 +225,8 @@
 
 	status = "okay";
 };
+
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/r8a7778.dtsi b/sys/gnu/dts/arm/r8a7778.dtsi
index 791aafd310a5..fe787b4751d2 100644
--- a/sys/gnu/dts/arm/r8a7778.dtsi
+++ b/sys/gnu/dts/arm/r8a7778.dtsi
@@ -17,6 +17,7 @@
 /include/ "skeleton.dtsi"
 
 #include <dt-bindings/clock/r8a7778-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -51,7 +52,7 @@
 	ether: ethernet@fde00000 {
 		compatible = "renesas,ether-r8a7778";
 		reg = <0xfde00000 0x400>;
-		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
 		power-domains = <&cpg_clocks>;
 		phy-mode = "rmii";
@@ -79,17 +80,17 @@
 			<0xfe780024 4>,
 			<0xfe780044 4>,
 			<0xfe780064 4>;
-		interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
-				0 28 IRQ_TYPE_LEVEL_HIGH
-				0 29 IRQ_TYPE_LEVEL_HIGH
-				0 30 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts =   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 		sense-bitfield-width = <2>;
 	};
 
 	gpio0: gpio@ffc40000 {
 		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 		reg = <0xffc40000 0x2c>;
-		interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 0 32>;
@@ -100,7 +101,7 @@
 	gpio1: gpio@ffc41000 {
 		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 		reg = <0xffc41000 0x2c>;
-		interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 32 32>;
@@ -111,7 +112,7 @@
 	gpio2: gpio@ffc42000 {
 		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 		reg = <0xffc42000 0x2c>;
-		interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 64 32>;
@@ -122,7 +123,7 @@
 	gpio3: gpio@ffc43000 {
 		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 		reg = <0xffc43000 0x2c>;
-		interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 96 32>;
@@ -133,7 +134,7 @@
 	gpio4: gpio@ffc44000 {
 		compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
 		reg = <0xffc44000 0x2c>;
-		interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 128 27>;
@@ -151,7 +152,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7778";
 		reg = <0xffc70000 0x1000>;
-		interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
@@ -162,7 +163,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7778";
 		reg = <0xffc71000 0x1000>;
-		interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
@@ -173,7 +174,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7778";
 		reg = <0xffc72000 0x1000>;
-		interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
@@ -184,7 +185,7 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7778";
 		reg = <0xffc73000 0x1000>;
-		interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
@@ -193,9 +194,9 @@
 	tmu0: timer@ffd80000 {
 		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 		reg = <0xffd80000 0x30>;
-		interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 33 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 34 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
@@ -208,9 +209,9 @@
 	tmu1: timer@ffd81000 {
 		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 		reg = <0xffd81000 0x30>;
-		interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 37 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 38 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
@@ -223,9 +224,9 @@
 	tmu2: timer@ffd82000 {
 		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
 		reg = <0xffd82000 0x30>;
-		interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 41 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 42 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 		clock-names = "fck";
 		power-domains = <&cpg_clocks>;
@@ -285,72 +286,84 @@
 		};
 
 		rcar_sound,ssi {
-			ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
-			ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
-			ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-			ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-			ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-			ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-			ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+			ssi3: ssi@3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
+			ssi4: ssi@4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
+			ssi5: ssi@5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+			ssi6: ssi@6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+			ssi7: ssi@7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+			ssi8: ssi@8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+			ssi9: ssi@9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
 		};
 	};
 
 	scif0: serial@ffe40000 {
-		compatible = "renesas,scif-r8a7778", "renesas,scif";
+		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe40000 0x100>;
-		interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
+			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	scif1: serial@ffe41000 {
-		compatible = "renesas,scif-r8a7778", "renesas,scif";
+		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe41000 0x100>;
-		interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
+			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	scif2: serial@ffe42000 {
-		compatible = "renesas,scif-r8a7778", "renesas,scif";
+		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe42000 0x100>;
-		interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
+			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	scif3: serial@ffe43000 {
-		compatible = "renesas,scif-r8a7778", "renesas,scif";
+		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe43000 0x100>;
-		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
+			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	scif4: serial@ffe44000 {
-		compatible = "renesas,scif-r8a7778", "renesas,scif";
+		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe44000 0x100>;
-		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
+			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
 	scif5: serial@ffe45000 {
-		compatible = "renesas,scif-r8a7778", "renesas,scif";
+		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe45000 0x100>;
-		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
+			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
@@ -358,7 +371,7 @@
 	mmcif: mmc@ffe4e000 {
 		compatible = "renesas,sh-mmcif";
 		reg = <0xffe4e000 0x100>;
-		interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7778_CLK_MMC>;
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
@@ -367,7 +380,7 @@
 	sdhi0: sd@ffe4c000 {
 		compatible = "renesas,sdhi-r8a7778";
 		reg = <0xffe4c000 0x100>;
-		interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
@@ -376,7 +389,7 @@
 	sdhi1: sd@ffe4d000 {
 		compatible = "renesas,sdhi-r8a7778";
 		reg = <0xffe4d000 0x100>;
-		interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
@@ -385,7 +398,7 @@
 	sdhi2: sd@ffe4f000 {
 		compatible = "renesas,sdhi-r8a7778";
 		reg = <0xffe4f000 0x100>;
-		interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
 		power-domains = <&cpg_clocks>;
 		status = "disabled";
@@ -394,7 +407,7 @@
 	hspi0: spi@fffc7000 {
 		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 		reg = <0xfffc7000 0x18>;
-		interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
@@ -405,7 +418,7 @@
 	hspi1: spi@fffc8000 {
 		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 		reg = <0xfffc8000 0x18>;
-		interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
@@ -416,7 +429,7 @@
 	hspi2: spi@fffc6000 {
 		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
 		reg = <0xfffc6000 0x18>;
-		interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
 		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
@@ -430,11 +443,18 @@
 		ranges;
 
 		/* External input clock */
-		extal_clk: extal_clk {
+		extal_clk: extal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "extal";
+		};
+
+		/* External SCIF clock */
+		scif_clk: scif {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
 		};
 
 		/* Special CPG clocks */
@@ -452,59 +472,51 @@
 		audio_clk_a: audio_clk_a {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-output-names = "audio_clk_a";
 		};
 		audio_clk_b: audio_clk_b {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-output-names = "audio_clk_b";
 		};
 		audio_clk_c: audio_clk_c {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-output-names = "audio_clk_c";
 		};
 
 		/* Fixed ratio clocks */
-		g_clk: g_clk {
+		g_clk: g {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 			#clock-cells = <0>;
 			clock-div = <12>;
 			clock-mult = <1>;
-			clock-output-names = "g";
 		};
-		i_clk: i_clk {
+		i_clk: i {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 			#clock-cells = <0>;
 			clock-div = <1>;
 			clock-mult = <1>;
-			clock-output-names = "i";
 		};
-		s3_clk: s3_clk {
+		s3_clk: s3 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 			#clock-cells = <0>;
 			clock-div = <4>;
 			clock-mult = <1>;
-			clock-output-names = "s3";
 		};
-		s4_clk: s4_clk {
+		s4_clk: s4 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "s4";
 		};
-		z_clk: z_clk {
+		z_clk: z {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
 			#clock-cells = <0>;
 			clock-div = <1>;
 			clock-mult = <1>;
-			clock-output-names = "z";
 		};
 
 		/* Gate clocks */
diff --git a/sys/gnu/dts/arm/r8a7779-marzen.dts b/sys/gnu/dts/arm/r8a7779-marzen.dts
index fe396c8d58db..b795da6f5503 100644
--- a/sys/gnu/dts/arm/r8a7779-marzen.dts
+++ b/sys/gnu/dts/arm/r8a7779-marzen.dts
@@ -165,46 +165,54 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
 		du0 {
-			renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
-			renesas,function = "du0";
+			groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
+			function = "du0";
 		};
 		du1 {
-			renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
-			renesas,function = "du1";
+			groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
+			function = "du1";
 		};
 	};
 
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk_b";
+		function = "scif_clk";
+	};
+
 	ethernet_pins: ethernet {
 		intc {
-			renesas,groups = "intc_irq1_b";
-			renesas,function = "intc";
+			groups = "intc_irq1_b";
+			function = "intc";
 		};
 		lbsc {
-			renesas,groups = "lbsc_ex_cs0";
-			renesas,function = "lbsc";
+			groups = "lbsc_ex_cs0";
+			function = "lbsc";
 		};
 	};
 
 	scif2_pins: serial2 {
-		renesas,groups = "scif2_data_c";
-		renesas,function = "scif2";
+		groups = "scif2_data_c";
+		function = "scif2";
 	};
 
 	scif4_pins: serial4 {
-		renesas,groups = "scif4_data";
-		renesas,function = "scif4";
+		groups = "scif4_data";
+		function = "scif4";
 	};
 
 	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
-		renesas,function = "sdhi0";
+		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
+		function = "sdhi0";
 	};
 
 	hspi0_pins: hspi0 {
-		renesas,groups = "hspi0";
-		renesas,function = "hspi0";
+		groups = "hspi0";
+		function = "hspi0";
 	};
 };
 
@@ -222,6 +230,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
diff --git a/sys/gnu/dts/arm/r8a7779.dtsi b/sys/gnu/dts/arm/r8a7779.dtsi
index 6afa909865b5..b9bbcce69dfb 100644
--- a/sys/gnu/dts/arm/r8a7779.dtsi
+++ b/sys/gnu/dts/arm/r8a7779.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/clock/r8a7779-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7779-sysc.h>
 
 / {
 	compatible = "renesas,r8a7779";
@@ -34,18 +35,21 @@
 			compatible = "arm,cortex-a9";
 			reg = <1>;
 			clock-frequency = <1000000000>;
+			power-domains = <&sysc R8A7779_PD_ARM1>;
 		};
 		cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <2>;
 			clock-frequency = <1000000000>;
+			power-domains = <&sysc R8A7779_PD_ARM2>;
 		};
 		cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <3>;
 			clock-frequency = <1000000000>;
+			power-domains = <&sysc R8A7779_PD_ARM3>;
 		};
 	};
 
@@ -67,14 +71,14 @@
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0xf0000600 0x20>;
 		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
 	};
 
 	gpio0: gpio@ffc40000 {
 		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 		reg = <0xffc40000 0x2c>;
-		interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 0 32>;
@@ -85,7 +89,7 @@
 	gpio1: gpio@ffc41000 {
 		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 		reg = <0xffc41000 0x2c>;
-		interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 32 32>;
@@ -96,7 +100,7 @@
 	gpio2: gpio@ffc42000 {
 		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 		reg = <0xffc42000 0x2c>;
-		interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 64 32>;
@@ -107,7 +111,7 @@
 	gpio3: gpio@ffc43000 {
 		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 		reg = <0xffc43000 0x2c>;
-		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 96 32>;
@@ -118,7 +122,7 @@
 	gpio4: gpio@ffc44000 {
 		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 		reg = <0xffc44000 0x2c>;
-		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 128 32>;
@@ -129,7 +133,7 @@
 	gpio5: gpio@ffc45000 {
 		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 		reg = <0xffc45000 0x2c>;
-		interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 160 32>;
@@ -140,7 +144,7 @@
 	gpio6: gpio@ffc46000 {
 		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 		reg = <0xffc46000 0x2c>;
-		interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 192 9>;
@@ -159,10 +163,10 @@
 			<0xfe780044 4>,
 			<0xfe780064 4>,
 			<0xfe780000 4>;
-		interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
-			      0 28 IRQ_TYPE_LEVEL_HIGH
-			      0 29 IRQ_TYPE_LEVEL_HIGH
-			      0 30 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 		sense-bitfield-width = <2>;
 	};
 
@@ -171,9 +175,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7779";
 		reg = <0xffc70000 0x1000>;
-		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -182,9 +186,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7779";
 		reg = <0xffc71000 0x1000>;
-		interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -193,9 +197,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7779";
 		reg = <0xffc72000 0x1000>;
-		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -204,69 +208,81 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7779";
 		reg = <0xffc73000 0x1000>;
-		interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif0: serial@ffe40000 {
-		compatible = "renesas,scif-r8a7779", "renesas,scif";
+		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe40000 0x100>;
-		interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
-		clock-names = "sci_ick";
-		power-domains = <&cpg_clocks>;
+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
+			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif1: serial@ffe41000 {
-		compatible = "renesas,scif-r8a7779", "renesas,scif";
+		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe41000 0x100>;
-		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
-		clock-names = "sci_ick";
-		power-domains = <&cpg_clocks>;
+		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
+			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif2: serial@ffe42000 {
-		compatible = "renesas,scif-r8a7779", "renesas,scif";
+		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe42000 0x100>;
-		interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
-		clock-names = "sci_ick";
-		power-domains = <&cpg_clocks>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
+			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif3: serial@ffe43000 {
-		compatible = "renesas,scif-r8a7779", "renesas,scif";
+		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe43000 0x100>;
-		interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
-		clock-names = "sci_ick";
-		power-domains = <&cpg_clocks>;
+		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
+			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif4: serial@ffe44000 {
-		compatible = "renesas,scif-r8a7779", "renesas,scif";
+		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe44000 0x100>;
-		interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
-		clock-names = "sci_ick";
-		power-domains = <&cpg_clocks>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
+			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif5: serial@ffe45000 {
-		compatible = "renesas,scif-r8a7779", "renesas,scif";
+		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
+			     "renesas,scif";
 		reg = <0xffe45000 0x100>;
-		interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
-		clock-names = "sci_ick";
-		power-domains = <&cpg_clocks>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
+			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -283,12 +299,12 @@
 	tmu0: timer@ffd80000 {
 		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 		reg = <0xffd80000 0x30>;
-		interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 33 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 34 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 
 		#renesas,channels = <3>;
 
@@ -298,12 +314,12 @@
 	tmu1: timer@ffd81000 {
 		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 		reg = <0xffd81000 0x30>;
-		interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 37 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 38 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 
 		#renesas,channels = <3>;
 
@@ -313,12 +329,12 @@
 	tmu2: timer@ffd82000 {
 		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 		reg = <0xffd82000 0x30>;
-		interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 41 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 42 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 
 		#renesas,channels = <3>;
 
@@ -328,86 +344,86 @@
 	sata: sata@fc600000 {
 		compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
 		reg = <0xfc600000 0x2000>;
-		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 	};
 
 	sdhi0: sd@ffe4c000 {
 		compatible = "renesas,sdhi-r8a7779";
 		reg = <0xffe4c000 0x100>;
-		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi1: sd@ffe4d000 {
 		compatible = "renesas,sdhi-r8a7779";
 		reg = <0xffe4d000 0x100>;
-		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi2: sd@ffe4e000 {
 		compatible = "renesas,sdhi-r8a7779";
 		reg = <0xffe4e000 0x100>;
-		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi3: sd@ffe4f000 {
 		compatible = "renesas,sdhi-r8a7779";
 		reg = <0xffe4f000 0x100>;
-		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hspi0: spi@fffc7000 {
 		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 		reg = <0xfffc7000 0x18>;
-		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hspi1: spi@fffc8000 {
 		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 		reg = <0xfffc8000 0x18>;
-		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hspi2: spi@fffc6000 {
 		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 		reg = <0xfffc6000 0x18>;
-		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	du: display@fff80000 {
 		compatible = "renesas,du-r8a7779";
 		reg = <0 0xfff80000 0 0x40000>;
-		interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7779_CLK_DU>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		ports {
@@ -433,12 +449,19 @@
 		ranges;
 
 		/* External root clock */
-		extal_clk: extal_clk {
+		extal_clk: extal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			/* This value must be overriden by the board. */
 			clock-frequency = <0>;
-			clock-output-names = "extal";
+		};
+
+		/* External SCIF clock */
+		scif_clk: scif {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
 		};
 
 		/* Special CPG clocks */
@@ -453,37 +476,33 @@
 		};
 
 		/* Fixed factor clocks */
-		i_clk: i_clk {
+		i_clk: i {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "i";
 		};
-		s3_clk: s3_clk {
+		s3_clk: s3 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "s3";
 		};
-		s4_clk: s4_clk {
+		s4_clk: s4 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 			#clock-cells = <0>;
 			clock-div = <16>;
 			clock-mult = <1>;
-			clock-output-names = "s4";
 		};
-		g_clk: g_clk {
+		g_clk: g {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 			#clock-cells = <0>;
 			clock-div = <24>;
 			clock-mult = <1>;
-			clock-output-names = "g";
 		};
 
 		/* Gate clocks */
@@ -570,4 +589,10 @@
 				"mmc1", "mmc0";
 		};
 	};
+
+	sysc: system-controller@ffd85000 {
+		compatible = "renesas,r8a7779-sysc";
+		reg = <0xffd85000 0x0200>;
+		#power-domain-cells = <1>;
+	};
 };
diff --git a/sys/gnu/dts/arm/r8a7790-lager.dts b/sys/gnu/dts/arm/r8a7790-lager.dts
index 052dcee4790d..749ba02b6a53 100644
--- a/sys/gnu/dts/arm/r8a7790-lager.dts
+++ b/sys/gnu/dts/arm/r8a7790-lager.dts
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013-2014 Renesas Solutions Corp.
  * Copyright (C) 2014 Cogent Embedded, Inc.
+ * Copyright (C) 2015-2016 Renesas Electronics Corporation
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2.  This program is licensed "as is" without any warranty of any
@@ -49,6 +50,7 @@
 	aliases {
 		serial0 = &scif0;
 		serial1 = &scifa1;
+		i2c8 = "i2cexio";
 	};
 
 	chosen {
@@ -174,11 +176,10 @@
 			  1800000 0>;
 	};
 
-	audio_clock: clock {
+	audio_clock: audio_clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <11289600>;
-		clock-output-names = "audio_clock";
 	};
 
 	rsnd_ak4643: sound {
@@ -252,6 +253,23 @@
 		#clock-cells = <0>;
 		clock-frequency = <148500000>;
 	};
+
+	/*
+	 * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
+	 * We use the I2C demuxer, so the desired IP core can be selected at runtime
+	 * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
+	 * Note: For testing the I2C slave feature, it is convenient to connect this
+	 * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
+	 * instantiate the slave device at runtime according to the documentation.
+	 * You can then communicate with the slave via IIC3.
+	 */
+	i2cexio: i2c@8 {
+		compatible = "i2c-demux-pinctrl";
+		i2c-parent = <&iic0>, <&i2c0>;
+		i2c-bus-name = "i2c-exio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
 };
 
 &du {
@@ -291,110 +309,137 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
-		renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
-		renesas,function = "du";
+		groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
+		function = "du";
 	};
 
 	scif0_pins: serial0 {
-		renesas,groups = "scif0_data";
-		renesas,function = "scif0";
+		groups = "scif0_data";
+		function = "scif0";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk";
+		function = "scif_clk";
 	};
 
 	ether_pins: ether {
-		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
-		renesas,function = "eth";
+		groups = "eth_link", "eth_mdio", "eth_rmii";
+		function = "eth";
 	};
 
 	phy1_pins: phy1 {
-		renesas,groups = "intc_irq0";
-		renesas,function = "intc";
+		groups = "intc_irq0";
+		function = "intc";
 	};
 
 	scifa1_pins: serial1 {
-		renesas,groups = "scifa1_data";
-		renesas,function = "scifa1";
+		groups = "scifa1_data";
+		function = "scifa1";
 	};
 
 	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
-		renesas,function = "sdhi0";
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
+
+	sdhi0_pins_uhs: sd0_uhs {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <1800>;
 	};
 
 	sdhi2_pins: sd2 {
-		renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
-		renesas,function = "sdhi2";
+		groups = "sdhi2_data4", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <3300>;
+	};
+
+	sdhi2_pins_uhs: sd2_uhs {
+		groups = "sdhi2_data4", "sdhi2_ctrl";
+		function = "sdhi2";
+		power-source = <1800>;
 	};
 
 	mmc1_pins: mmc1 {
-		renesas,groups = "mmc1_data8", "mmc1_ctrl";
-		renesas,function = "mmc1";
+		groups = "mmc1_data8", "mmc1_ctrl";
+		function = "mmc1";
 	};
 
 	qspi_pins: spi0 {
-		renesas,groups = "qspi_ctrl", "qspi_data4";
-		renesas,function = "qspi";
+		groups = "qspi_ctrl", "qspi_data4";
+		function = "qspi";
 	};
 
 	msiof1_pins: spi2 {
-		renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
+		groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
 				 "msiof1_tx";
-		renesas,function = "msiof1";
+		function = "msiof1";
+	};
+
+	i2c0_pins: i2c0 {
+		groups = "i2c0";
+		function = "i2c0";
 	};
 
 	iic0_pins: iic0 {
-		renesas,groups = "iic0";
-		renesas,function = "iic0";
+		groups = "iic0";
+		function = "iic0";
 	};
 
 	iic1_pins: iic1 {
-		renesas,groups = "iic1";
-		renesas,function = "iic1";
+		groups = "iic1";
+		function = "iic1";
 	};
 
 	iic2_pins: iic2 {
-		renesas,groups = "iic2";
-		renesas,function = "iic2";
+		groups = "iic2";
+		function = "iic2";
 	};
 
 	iic3_pins: iic3 {
-		renesas,groups = "iic3";
-		renesas,function = "iic3";
+		groups = "iic3";
+		function = "iic3";
 	};
 
 	hsusb_pins: hsusb {
-		renesas,groups = "usb0_ovc_vbus";
-		renesas,function = "usb0";
+		groups = "usb0_ovc_vbus";
+		function = "usb0";
 	};
 
 	usb0_pins: usb0 {
-		renesas,groups = "usb0";
-		renesas,function = "usb0";
+		groups = "usb0";
+		function = "usb0";
 	};
 
 	usb1_pins: usb1 {
-		renesas,groups = "usb1";
-		renesas,function = "usb1";
+		groups = "usb1";
+		function = "usb1";
 	};
 
 	usb2_pins: usb2 {
-		renesas,groups = "usb2";
-		renesas,function = "usb2";
+		groups = "usb2";
+		function = "usb2";
 	};
 
 	vin1_pins: vin {
-		renesas,groups = "vin1_data8", "vin1_clk";
-		renesas,function = "vin1";
+		groups = "vin1_data8", "vin1_clk";
+		function = "vin1";
 	};
 
 	sound_pins: sound {
-		renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
-		renesas,function = "ssi";
+		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+		function = "ssi";
 	};
 
 	sound_clk_pins: sound_clk {
-		renesas,groups = "audio_clk_a";
-		renesas,function = "audio_clk";
+		groups = "audio_clk_a";
+		function = "audio_clk";
 	};
 };
 
@@ -485,6 +530,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &msiof1 {
 	pinctrl-0 = <&msiof1_pins>;
 	pinctrl-names = "default";
@@ -502,21 +552,25 @@
 
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdhi0_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
 
 	vmmc-supply = <&vcc_sdhi0>;
 	vqmmc-supply = <&vccq_sdhi0>;
 	cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+	sd-uhs-sdr50;
 	status = "okay";
 };
 
 &sdhi2 {
 	pinctrl-0 = <&sdhi2_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdhi2_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
 
 	vmmc-supply = <&vcc_sdhi2>;
 	vqmmc-supply = <&vccq_sdhi2>;
 	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+	sd-uhs-sdr50;
 	status = "okay";
 };
 
@@ -524,10 +578,14 @@
 	cpu0-supply = <&vdd_dvfs>;
 };
 
+&i2c0	{
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "i2c-exio";
+};
+
 &iic0	{
-	status = "okay";
 	pinctrl-0 = <&iic0_pins>;
-	pinctrl-names = "default";
+	pinctrl-names = "i2c-exio";
 };
 
 &iic1	{
diff --git a/sys/gnu/dts/arm/r8a7790.dtsi b/sys/gnu/dts/arm/r8a7790.dtsi
index 7dfd393bfc7e..83cf23cd26bb 100644
--- a/sys/gnu/dts/arm/r8a7790.dtsi
+++ b/sys/gnu/dts/arm/r8a7790.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/clock/r8a7790-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7790-sysc.h>
 
 / {
 	compatible = "renesas,r8a7790";
@@ -52,6 +53,8 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7790_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1400000 1000000>,
@@ -67,6 +70,8 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1300000000>;
+			power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu2: cpu@2 {
@@ -74,6 +79,8 @@
 			compatible = "arm,cortex-a15";
 			reg = <2>;
 			clock-frequency = <1300000000>;
+			power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu3: cpu@3 {
@@ -81,6 +88,8 @@
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 			clock-frequency = <1300000000>;
+			power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
+			next-level-cache = <&L2_CA15>;
 		};
 
 		cpu4: cpu@4 {
@@ -88,6 +97,8 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			clock-frequency = <780000000>;
+			power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu5: cpu@5 {
@@ -95,6 +106,8 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			clock-frequency = <780000000>;
+			power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu6: cpu@6 {
@@ -102,6 +115,8 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			clock-frequency = <780000000>;
+			power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu7: cpu@7 {
@@ -109,9 +124,44 @@
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;
 			clock-frequency = <780000000>;
+			power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive	= <0>;
+			polling-delay		= <0>;
+
+			thermal-sensors = <&thermal>;
+
+			trips {
+				cpu-crit {
+					temperature	= <115000>;
+					hysteresis	= <0>;
+					type		= "critical";
+				};
+			};
+			cooling-maps {
+			};
+		};
+	};
+
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		power-domains = <&sysc R8A7790_PD_CA15_SCU>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		power-domains = <&sysc R8A7790_PD_CA7_SCU>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
@@ -121,111 +171,114 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	gpio0: gpio@e6050000 {
 		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 		reg = <0 0xe6050000 0 0x50>;
-		interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 0 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 	};
 
 	gpio1: gpio@e6051000 {
 		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 		reg = <0 0xe6051000 0 0x50>;
-		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 32 30>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 	};
 
 	gpio2: gpio@e6052000 {
 		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 		reg = <0 0xe6052000 0 0x50>;
-		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 64 30>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 	};
 
 	gpio3: gpio@e6053000 {
 		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 		reg = <0 0xe6053000 0 0x50>;
-		interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 96 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 	};
 
 	gpio4: gpio@e6054000 {
 		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 		reg = <0 0xe6054000 0 0x50>;
-		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 128 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 	};
 
 	gpio5: gpio@e6055000 {
 		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 		reg = <0 0xe6055000 0 0x50>;
-		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 160 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 	};
 
-	thermal@e61f0000 {
-		compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+	thermal: thermal@e61f0000 {
+		compatible =	"renesas,thermal-r8a7790",
+				"renesas,rcar-gen2-thermal",
+				"renesas,rcar-thermal";
 		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
-		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+		#thermal-sensor-cells = <0>;
 	};
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	cmt0: timer@ffca0000 {
 		compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 		reg = <0 0xffca0000 0 0x1004>;
-		interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 
 		renesas,channels-mask = <0x60>;
 
@@ -235,17 +288,17 @@
 	cmt1: timer@e6130000 {
 		compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
 		reg = <0 0xe6130000 0 0x1004>;
-		interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 121 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 122 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 123 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 124 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 125 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 126 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 127 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 
 		renesas,channels-mask = <0xff>;
 
@@ -257,33 +310,33 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		reg = <0 0xe61c0000 0 0x200>;
-		interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 3 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 	};
 
 	dmac0: dma-controller@e6700000 {
 		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 		reg = <0 0xe6700000 0 0x20000>;
-		interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
-			      0 200 IRQ_TYPE_LEVEL_HIGH
-			      0 201 IRQ_TYPE_LEVEL_HIGH
-			      0 202 IRQ_TYPE_LEVEL_HIGH
-			      0 203 IRQ_TYPE_LEVEL_HIGH
-			      0 204 IRQ_TYPE_LEVEL_HIGH
-			      0 205 IRQ_TYPE_LEVEL_HIGH
-			      0 206 IRQ_TYPE_LEVEL_HIGH
-			      0 207 IRQ_TYPE_LEVEL_HIGH
-			      0 208 IRQ_TYPE_LEVEL_HIGH
-			      0 209 IRQ_TYPE_LEVEL_HIGH
-			      0 210 IRQ_TYPE_LEVEL_HIGH
-			      0 211 IRQ_TYPE_LEVEL_HIGH
-			      0 212 IRQ_TYPE_LEVEL_HIGH
-			      0 213 IRQ_TYPE_LEVEL_HIGH
-			      0 214 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -291,7 +344,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
@@ -299,22 +352,22 @@
 	dmac1: dma-controller@e6720000 {
 		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 		reg = <0 0xe6720000 0 0x20000>;
-		interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
-			      0 216 IRQ_TYPE_LEVEL_HIGH
-			      0 217 IRQ_TYPE_LEVEL_HIGH
-			      0 218 IRQ_TYPE_LEVEL_HIGH
-			      0 219 IRQ_TYPE_LEVEL_HIGH
-			      0 308 IRQ_TYPE_LEVEL_HIGH
-			      0 309 IRQ_TYPE_LEVEL_HIGH
-			      0 310 IRQ_TYPE_LEVEL_HIGH
-			      0 311 IRQ_TYPE_LEVEL_HIGH
-			      0 312 IRQ_TYPE_LEVEL_HIGH
-			      0 313 IRQ_TYPE_LEVEL_HIGH
-			      0 314 IRQ_TYPE_LEVEL_HIGH
-			      0 315 IRQ_TYPE_LEVEL_HIGH
-			      0 316 IRQ_TYPE_LEVEL_HIGH
-			      0 317 IRQ_TYPE_LEVEL_HIGH
-			      0 318 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -322,7 +375,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
@@ -330,20 +383,20 @@
 	audma0: dma-controller@ec700000 {
 		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 		reg = <0 0xec700000 0 0x10000>;
-		interrupts =	<0 346 IRQ_TYPE_LEVEL_HIGH
-				 0 320 IRQ_TYPE_LEVEL_HIGH
-				 0 321 IRQ_TYPE_LEVEL_HIGH
-				 0 322 IRQ_TYPE_LEVEL_HIGH
-				 0 323 IRQ_TYPE_LEVEL_HIGH
-				 0 324 IRQ_TYPE_LEVEL_HIGH
-				 0 325 IRQ_TYPE_LEVEL_HIGH
-				 0 326 IRQ_TYPE_LEVEL_HIGH
-				 0 327 IRQ_TYPE_LEVEL_HIGH
-				 0 328 IRQ_TYPE_LEVEL_HIGH
-				 0 329 IRQ_TYPE_LEVEL_HIGH
-				 0 330 IRQ_TYPE_LEVEL_HIGH
-				 0 331 IRQ_TYPE_LEVEL_HIGH
-				 0 332 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts =	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -351,7 +404,7 @@
 				"ch12";
 		clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <13>;
 	};
@@ -359,20 +412,20 @@
 	audma1: dma-controller@ec720000 {
 		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
 		reg = <0 0xec720000 0 0x10000>;
-		interrupts =	<0 347 IRQ_TYPE_LEVEL_HIGH
-				 0 333 IRQ_TYPE_LEVEL_HIGH
-				 0 334 IRQ_TYPE_LEVEL_HIGH
-				 0 335 IRQ_TYPE_LEVEL_HIGH
-				 0 336 IRQ_TYPE_LEVEL_HIGH
-				 0 337 IRQ_TYPE_LEVEL_HIGH
-				 0 338 IRQ_TYPE_LEVEL_HIGH
-				 0 339 IRQ_TYPE_LEVEL_HIGH
-				 0 340 IRQ_TYPE_LEVEL_HIGH
-				 0 341 IRQ_TYPE_LEVEL_HIGH
-				 0 342 IRQ_TYPE_LEVEL_HIGH
-				 0 343 IRQ_TYPE_LEVEL_HIGH
-				 0 344 IRQ_TYPE_LEVEL_HIGH
-				 0 345 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts =	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -380,7 +433,7 @@
 				"ch12";
 		clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <13>;
 	};
@@ -388,11 +441,11 @@
 	usb_dmac0: dma-controller@e65a0000 {
 		compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
 		reg = <0 0xe65a0000 0 0x100>;
-		interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
-			      0 109 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "ch0", "ch1";
 		clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <2>;
 	};
@@ -400,11 +453,11 @@
 	usb_dmac1: dma-controller@e65b0000 {
 		compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
 		reg = <0 0xe65b0000 0 0x100>;
-		interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
-			      0 110 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "ch0", "ch1";
 		clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <2>;
 	};
@@ -414,9 +467,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7790";
 		reg = <0 0xe6508000 0 0x40>;
-		interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <110>;
 		status = "disabled";
 	};
@@ -426,9 +479,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7790";
 		reg = <0 0xe6518000 0 0x40>;
-		interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <6>;
 		status = "disabled";
 	};
@@ -438,9 +491,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7790";
 		reg = <0 0xe6530000 0 0x40>;
-		interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <6>;
 		status = "disabled";
 	};
@@ -450,9 +503,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7790";
 		reg = <0 0xe6540000 0 0x40>;
-		interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <110>;
 		status = "disabled";
 	};
@@ -462,11 +515,11 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 		reg = <0 0xe6500000 0 0x425>;
-		interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
 		dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -475,11 +528,11 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 		reg = <0 0xe6510000 0 0x425>;
-		interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
 		dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -488,11 +541,11 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 		reg = <0 0xe6520000 0 0x425>;
-		interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
 		dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -501,22 +554,22 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
 		reg = <0 0xe60b0000 0 0x425>;
-		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
 		dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	mmcif0: mmc@ee200000 {
 		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 		reg = <0 0xee200000 0 0x80>;
-		interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		reg-io-width = <4>;
 		status = "disabled";
 		max-frequency = <97500000>;
@@ -525,11 +578,11 @@
 	mmcif1: mmc@ee220000 {
 		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 		reg = <0 0xee220000 0 0x80>;
-		interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 		dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		reg-io-width = <4>;
 		status = "disabled";
 		max-frequency = <97500000>;
@@ -543,173 +596,205 @@
 	sdhi0: sd@ee100000 {
 		compatible = "renesas,sdhi-r8a7790";
 		reg = <0 0xee100000 0 0x328>;
-		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 		dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		max-frequency = <195000000>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi1: sd@ee120000 {
 		compatible = "renesas,sdhi-r8a7790";
 		reg = <0 0xee120000 0 0x328>;
-		interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 		dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		max-frequency = <195000000>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi2: sd@ee140000 {
 		compatible = "renesas,sdhi-r8a7790";
 		reg = <0 0xee140000 0 0x100>;
-		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 		dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		max-frequency = <97500000>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi3: sd@ee160000 {
 		compatible = "renesas,sdhi-r8a7790";
 		reg = <0 0xee160000 0 0x100>;
-		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 		dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		max-frequency = <97500000>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa0: serial@e6c40000 {
-		compatible = "renesas,scifa-r8a7790", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7790",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c40000 0 64>;
-		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa1: serial@e6c50000 {
-		compatible = "renesas,scifa-r8a7790", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7790",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c50000 0 64>;
-		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa2: serial@e6c60000 {
-		compatible = "renesas,scifa-r8a7790", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7790",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c60000 0 64>;
-		interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb0: serial@e6c20000 {
-		compatible = "renesas,scifb-r8a7790", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7790",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6c20000 0 64>;
-		interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb1: serial@e6c30000 {
-		compatible = "renesas,scifb-r8a7790", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7790",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6c30000 0 64>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb2: serial@e6ce0000 {
-		compatible = "renesas,scifb-r8a7790", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7790",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6ce0000 0 64>;
-		interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif0: serial@e6e60000 {
-		compatible = "renesas,scif-r8a7790", "renesas,scif";
+		compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e60000 0 64>;
-		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif1: serial@e6e68000 {
-		compatible = "renesas,scif-r8a7790", "renesas,scif";
+		compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e68000 0 64>;
-		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	scif2: serial@e6e56000 {
+		compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
+		reg = <0 0xe6e56000 0 64>;
+		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
+		dma-names = "tx", "rx";
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif0: serial@e62c0000 {
-		compatible = "renesas,hscif-r8a7790", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7790",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62c0000 0 96>;
-		interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif1: serial@e62c8000 {
-		compatible = "renesas,hscif-r8a7790", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7790",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62c8000 0 96>;
-		interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	ether: ethernet@ee700000 {
 		compatible = "renesas,ether-r8a7790";
 		reg = <0 0xee700000 0 0x400>;
-		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -717,11 +802,12 @@
 	};
 
 	avb: ethernet@e6800000 {
-		compatible = "renesas,etheravb-r8a7790";
+		compatible = "renesas,etheravb-r8a7790",
+			     "renesas,etheravb-rcar-gen2";
 		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
-		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -730,30 +816,30 @@
 	sata0: sata@ee300000 {
 		compatible = "renesas,sata-r8a7790";
 		reg = <0 0xee300000 0 0x2000>;
-		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sata1: sata@ee500000 {
 		compatible = "renesas,sata-r8a7790";
 		reg = <0 0xee500000 0 0x2000>;
-		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hsusb: usb@e6590000 {
-		compatible = "renesas,usbhs-r8a7790";
+		compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
 		reg = <0 0xe6590000 0 0x100>;
-		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 		dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 		       <&usb_dmac1 0>, <&usb_dmac1 1>;
 		dma-names = "ch0", "ch1", "ch2", "ch3";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		renesas,buswait = <4>;
 		phys = <&usb0 1>;
 		phy-names = "usb";
@@ -767,7 +853,7 @@
 		#size-cells = <0>;
 		clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
 		clock-names = "usbhs";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		usb0: usb-channel@0 {
@@ -783,45 +869,45 @@
 	vin0: video@e6ef0000 {
 		compatible = "renesas,vin-r8a7790";
 		reg = <0 0xe6ef0000 0 0x1000>;
-		interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	vin1: video@e6ef1000 {
 		compatible = "renesas,vin-r8a7790";
 		reg = <0 0xe6ef1000 0 0x1000>;
-		interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	vin2: video@e6ef2000 {
 		compatible = "renesas,vin-r8a7790";
 		reg = <0 0xe6ef2000 0 0x1000>;
-		interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	vin3: video@e6ef3000 {
 		compatible = "renesas,vin-r8a7790";
 		reg = <0 0xe6ef3000 0 0x1000>;
-		interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	vsp1@fe920000 {
 		compatible = "renesas,vsp1";
 		reg = <0 0xfe920000 0 0x8000>;
-		interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 
 		renesas,has-sru;
 		renesas,#rpf = <5>;
@@ -832,9 +918,9 @@
 	vsp1@fe928000 {
 		compatible = "renesas,vsp1";
 		reg = <0 0xfe928000 0 0x8000>;
-		interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 
 		renesas,has-lut;
 		renesas,has-sru;
@@ -846,9 +932,9 @@
 	vsp1@fe930000 {
 		compatible = "renesas,vsp1";
 		reg = <0 0xfe930000 0 0x8000>;
-		interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 
 		renesas,has-lif;
 		renesas,has-lut;
@@ -860,9 +946,9 @@
 	vsp1@fe938000 {
 		compatible = "renesas,vsp1";
 		reg = <0 0xfe938000 0 0x8000>;
-		interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 
 		renesas,has-lif;
 		renesas,has-lut;
@@ -877,9 +963,9 @@
 		      <0 0xfeb90000 0 0x1c>,
 		      <0 0xfeb94000 0 0x1c>;
 		reg-names = "du", "lvds.0", "lvds.1";
-		interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 268 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 269 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7790_CLK_DU0>,
 			 <&mstp7_clks R8A7790_CLK_DU1>,
 			 <&mstp7_clks R8A7790_CLK_DU2>,
@@ -911,33 +997,33 @@
 	};
 
 	can0: can@e6e80000 {
-		compatible = "renesas,can-r8a7790";
+		compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
 		reg = <0 0xe6e80000 0 0x1000>;
-		interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
 			 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 		clock-names = "clkp1", "clkp2", "can_clk";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	can1: can@e6e88000 {
-		compatible = "renesas,can-r8a7790";
+		compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
 		reg = <0 0xe6e88000 0 0x1000>;
-		interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
 			 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
 		clock-names = "clkp1", "clkp2", "can_clk";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	jpu: jpeg-codec@fe980000 {
-		compatible = "renesas,jpu-r8a7790";
+		compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
 		reg = <0 0xfe980000 0 0x10300>;
-		interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7790_CLK_JPU>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 	};
 
 	clocks {
@@ -946,21 +1032,18 @@
 		ranges;
 
 		/* External root clock */
-		extal_clk: extal_clk {
+		extal_clk: extal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			/* This value must be overriden by the board. */
 			clock-frequency = <0>;
-			clock-output-names = "extal";
 		};
 
 		/* External PCIe clock - can be overridden by the board */
-		pcie_bus_clk: pcie_bus_clk {
+		pcie_bus_clk: pcie_bus {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <100000000>;
-			clock-output-names = "pcie_bus";
-			status = "disabled";
+			clock-frequency = <0>;
 		};
 
 		/*
@@ -971,27 +1054,31 @@
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "audio_clk_a";
 		};
 		audio_clk_b: audio_clk_b {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "audio_clk_b";
 		};
 		audio_clk_c: audio_clk_c {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "audio_clk_c";
+		};
+
+		/* External SCIF clock */
+		scif_clk: scif {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
 		};
 
 		/* External USB clock - can be overridden by the board */
-		usb_extal_clk: usb_extal_clk {
+		usb_extal_clk: usb_extal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <48000000>;
-			clock-output-names = "usb_extal";
 		};
 
 		/* External CAN clock */
@@ -1000,8 +1087,6 @@
 			#clock-cells = <0>;
 			/* This value must be overridden by the board. */
 			clock-frequency = <0>;
-			clock-output-names = "can_clk";
-			status = "disabled";
 		};
 
 		/* Special CPG clocks */
@@ -1018,201 +1103,176 @@
 		};
 
 		/* Variable factor clocks */
-		sd2_clk: sd2_clk@e6150078 {
+		sd2_clk: sd2@e6150078 {
 			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150078 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sd2";
 		};
-		sd3_clk: sd3_clk@e615026c {
+		sd3_clk: sd3@e615026c {
 			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe615026c 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sd3";
 		};
-		mmc0_clk: mmc0_clk@e6150240 {
+		mmc0_clk: mmc0@e6150240 {
 			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150240 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "mmc0";
 		};
-		mmc1_clk: mmc1_clk@e6150244 {
+		mmc1_clk: mmc1@e6150244 {
 			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150244 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "mmc1";
 		};
-		ssp_clk: ssp_clk@e6150248 {
+		ssp_clk: ssp@e6150248 {
 			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150248 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "ssp";
 		};
-		ssprs_clk: ssprs_clk@e615024c {
+		ssprs_clk: ssprs@e615024c {
 			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe615024c 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "ssprs";
 		};
 
 		/* Fixed factor clocks */
-		pll1_div2_clk: pll1_div2_clk {
+		pll1_div2_clk: pll1_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "pll1_div2";
 		};
-		z2_clk: z2_clk {
+		z2_clk: z2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "z2";
 		};
-		zg_clk: zg_clk {
+		zg_clk: zg {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <3>;
 			clock-mult = <1>;
-			clock-output-names = "zg";
 		};
-		zx_clk: zx_clk {
+		zx_clk: zx {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <3>;
 			clock-mult = <1>;
-			clock-output-names = "zx";
 		};
-		zs_clk: zs_clk {
+		zs_clk: zs {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <6>;
 			clock-mult = <1>;
-			clock-output-names = "zs";
 		};
-		hp_clk: hp_clk {
+		hp_clk: hp {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <12>;
 			clock-mult = <1>;
-			clock-output-names = "hp";
 		};
-		i_clk: i_clk {
+		i_clk: i {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "i";
 		};
-		b_clk: b_clk {
+		b_clk: b {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <12>;
 			clock-mult = <1>;
-			clock-output-names = "b";
 		};
-		p_clk: p_clk {
+		p_clk: p {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <24>;
 			clock-mult = <1>;
-			clock-output-names = "p";
 		};
-		cl_clk: cl_clk {
+		cl_clk: cl {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <48>;
 			clock-mult = <1>;
-			clock-output-names = "cl";
 		};
-		m2_clk: m2_clk {
+		m2_clk: m2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "m2";
 		};
-		imp_clk: imp_clk {
+		imp_clk: imp {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <4>;
 			clock-mult = <1>;
-			clock-output-names = "imp";
 		};
-		rclk_clk: rclk_clk {
+		rclk_clk: rclk {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <(48 * 1024)>;
 			clock-mult = <1>;
-			clock-output-names = "rclk";
 		};
-		oscclk_clk: oscclk_clk {
+		oscclk_clk: oscclk {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <(12 * 1024)>;
 			clock-mult = <1>;
-			clock-output-names = "oscclk";
 		};
-		zb3_clk: zb3_clk {
+		zb3_clk: zb3 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 			#clock-cells = <0>;
 			clock-div = <4>;
 			clock-mult = <1>;
-			clock-output-names = "zb3";
 		};
-		zb3d2_clk: zb3d2_clk {
+		zb3d2_clk: zb3d2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "zb3d2";
 		};
-		ddr_clk: ddr_clk {
+		ddr_clk: ddr {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "ddr";
 		};
-		mp_clk: mp_clk {
+		mp_clk: mp {
 			compatible = "fixed-factor-clock";
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
 			clock-div = <15>;
 			clock-mult = <1>;
-			clock-output-names = "mp";
 		};
-		cp_clk: cp_clk {
+		cp_clk: cp {
 			compatible = "fixed-factor-clock";
 			clocks = <&extal_clk>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "cp";
 		};
 
 		/* Gate clocks */
@@ -1268,19 +1328,19 @@
 		mstp3_clks: mstp3_clks@e615013c {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-			clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
+			clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
 				 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
 				 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
 				 <&hp_clk>, <&hp_clk>;
 			#clock-cells = <1>;
 			clock-indices = <
-				R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
+				R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
 				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
 				R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
 				R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
 			>;
 			clock-output-names =
-				"iic2", "tpu0", "mmcif1", "sdhi3",
+				"iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
 				"sdhi2", "sdhi1", "sdhi0", "mmcif0",
 				"iic0", "pciec", "iic1", "ssusb", "cmt1",
 				"usbdmac0", "usbdmac1";
@@ -1398,14 +1458,20 @@
 		};
 	};
 
+	sysc: system-controller@e6180000 {
+		compatible = "renesas,r8a7790-sysc";
+		reg = <0 0xe6180000 0 0x0200>;
+		#power-domain-cells = <1>;
+	};
+
 	qspi: spi@e6b10000 {
 		compatible = "renesas,qspi-r8a7790", "renesas,qspi";
 		reg = <0 0xe6b10000 0 0x2c>;
-		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
 		dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -1415,11 +1481,11 @@
 	msiof0: spi@e6e20000 {
 		compatible = "renesas,msiof-r8a7790";
 		reg = <0 0xe6e20000 0 0x0064>;
-		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
 		dmas = <&dmac0 0x51>, <&dmac0 0x52>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -1428,11 +1494,11 @@
 	msiof1: spi@e6e10000 {
 		compatible = "renesas,msiof-r8a7790";
 		reg = <0 0xe6e10000 0 0x0064>;
-		interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
 		dmas = <&dmac0 0x55>, <&dmac0 0x56>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -1441,11 +1507,11 @@
 	msiof2: spi@e6e00000 {
 		compatible = "renesas,msiof-r8a7790";
 		reg = <0 0xe6e00000 0 0x0064>;
-		interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
 		dmas = <&dmac0 0x41>, <&dmac0 0x42>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -1454,35 +1520,35 @@
 	msiof3: spi@e6c90000 {
 		compatible = "renesas,msiof-r8a7790";
 		reg = <0 0xe6c90000 0 0x0064>;
-		interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
 		dmas = <&dmac0 0x45>, <&dmac0 0x46>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
 	};
 
 	xhci: usb@ee000000 {
-		compatible = "renesas,xhci-r8a7790";
+		compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
 		reg = <0 0xee000000 0 0xc00>;
-		interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		phys = <&usb2 1>;
 		phy-names = "usb";
 		status = "disabled";
 	};
 
 	pci0: pci@ee090000 {
-		compatible = "renesas,pci-r8a7790";
+		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
 		device_type = "pci";
 		reg = <0 0xee090000 0 0xc00>,
 		      <0 0xee080000 0 0x1100>;
-		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		bus-range = <0 0>;
@@ -1491,9 +1557,9 @@
 		#interrupt-cells = <1>;
 		ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 		interrupt-map-mask = <0xff00 0 0 0x7>;
-		interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+				 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+				 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 
 		usb@0,1 {
 			reg = <0x800 0 0 0 0>;
@@ -1511,13 +1577,13 @@
 	};
 
 	pci1: pci@ee0b0000 {
-		compatible = "renesas,pci-r8a7790";
+		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
 		device_type = "pci";
 		reg = <0 0xee0b0000 0 0xc00>,
 		      <0 0xee0a0000 0 0x1100>;
-		interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		bus-range = <1 1>;
@@ -1526,19 +1592,19 @@
 		#interrupt-cells = <1>;
 		ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
 		interrupt-map-mask = <0xff00 0 0 0x7>;
-		interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
-				 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
-				 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+				 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+				 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	pci2: pci@ee0d0000 {
-		compatible = "renesas,pci-r8a7790";
+		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
 		device_type = "pci";
 		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		reg = <0 0xee0d0000 0 0xc00>,
 		      <0 0xee0c0000 0 0x1100>;
-		interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 
 		bus-range = <2 2>;
@@ -1547,9 +1613,9 @@
 		#interrupt-cells = <1>;
 		ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 		interrupt-map-mask = <0xff00 0 0 0x7>;
-		interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
-				 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
-				 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+				 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+				 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 
 		usb@0,1 {
 			reg = <0x800 0 0 0 0>;
@@ -1567,7 +1633,7 @@
 	};
 
 	pciec: pcie@fe000000 {
-		compatible = "renesas,pcie-r8a7790";
+		compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
 		reg = <0 0xfe000000 0 0x80000>;
 		#address-cells = <3>;
 		#size-cells = <2>;
@@ -1580,15 +1646,15 @@
 		/* Map all possible DDR as inbound ranges */
 		dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
 			      0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
-		interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 117 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 118 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 0>;
-		interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
 		clock-names = "pcie", "pcie_bus";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -1631,7 +1697,7 @@
 				"mix.0", "mix.1",
 				"dvc.0", "dvc.1",
 				"clk_a", "clk_b", "clk_c", "clk_i";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
 
 		status = "disabled";
 
@@ -1664,52 +1730,52 @@
 
 		rcar_sound,src {
 			src0: src@0 {
-				interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x85>, <&audma1 0x9a>;
 				dma-names = "rx", "tx";
 			};
 			src1: src@1 {
-				interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x87>, <&audma1 0x9c>;
 				dma-names = "rx", "tx";
 			};
 			src2: src@2 {
-				interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x89>, <&audma1 0x9e>;
 				dma-names = "rx", "tx";
 			};
 			src3: src@3 {
-				interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x8b>, <&audma1 0xa0>;
 				dma-names = "rx", "tx";
 			};
 			src4: src@4 {
-				interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x8d>, <&audma1 0xb0>;
 				dma-names = "rx", "tx";
 			};
 			src5: src@5 {
-				interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x8f>, <&audma1 0xb2>;
 				dma-names = "rx", "tx";
 			};
 			src6: src@6 {
-				interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x91>, <&audma1 0xb4>;
 				dma-names = "rx", "tx";
 			};
 			src7: src@7 {
-				interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x93>, <&audma1 0xb6>;
 				dma-names = "rx", "tx";
 			};
 			src8: src@8 {
-				interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x95>, <&audma1 0xb8>;
 				dma-names = "rx", "tx";
 			};
 			src9: src@9 {
-				interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x97>, <&audma1 0xba>;
 				dma-names = "rx", "tx";
 			};
@@ -1717,52 +1783,52 @@
 
 		rcar_sound,ssi {
 			ssi0: ssi@0 {
-				interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi1: ssi@1 {
-				 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
+				 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi2: ssi@2 {
-				interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi3: ssi@3 {
-				interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi4: ssi@4 {
-				interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi5: ssi@5 {
-				interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi6: ssi@6 {
-				interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi7: ssi@7 {
-				interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi8: ssi@8 {
-				interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi9: ssi@9 {
-				interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
@@ -1772,8 +1838,8 @@
 	ipmmu_sy0: mmu@e6280000 {
 		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6280000 0 0x1000>;
-		interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 224 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1781,7 +1847,7 @@
 	ipmmu_sy1: mmu@e6290000 {
 		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6290000 0 0x1000>;
-		interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1789,8 +1855,8 @@
 	ipmmu_ds: mmu@e6740000 {
 		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6740000 0 0x1000>;
-		interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 199 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1798,7 +1864,7 @@
 	ipmmu_mp: mmu@ec680000 {
 		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
 		reg = <0 0xec680000 0 0x1000>;
-		interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1806,8 +1872,8 @@
 	ipmmu_mx: mmu@fe951000 {
 		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
 		reg = <0 0xfe951000 0 0x1000>;
-		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 221 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1815,7 +1881,7 @@
 	ipmmu_rt: mmu@ffc80000 {
 		compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
 		reg = <0 0xffc80000 0 0x1000>;
-		interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
diff --git a/sys/gnu/dts/arm/r8a7791-koelsch.dts b/sys/gnu/dts/arm/r8a7791-koelsch.dts
index 45256f3cc835..da59c2844b8a 100644
--- a/sys/gnu/dts/arm/r8a7791-koelsch.dts
+++ b/sys/gnu/dts/arm/r8a7791-koelsch.dts
@@ -242,11 +242,10 @@
 			  1800000 0>;
 	};
 
-	audio_clock: clock {
+	audio_clock: audio_clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <11289600>;
-		clock-output-names = "audio_clock";
 	};
 
 	rsnd_ak4643: sound {
@@ -320,85 +319,93 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	i2c2_pins: i2c2 {
-		renesas,groups = "i2c2";
-		renesas,function = "i2c2";
+		groups = "i2c2";
+		function = "i2c2";
 	};
 
 	du_pins: du {
-		renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
-		renesas,function = "du";
+		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+		function = "du";
 	};
 
 	scif0_pins: serial0 {
-		renesas,groups = "scif0_data_d";
-		renesas,function = "scif0";
+		groups = "scif0_data_d";
+		function = "scif0";
 	};
 
 	scif1_pins: serial1 {
-		renesas,groups = "scif1_data_d";
-		renesas,function = "scif1";
+		groups = "scif1_data_d";
+		function = "scif1";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk";
+		function = "scif_clk";
 	};
 
 	ether_pins: ether {
-		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
-		renesas,function = "eth";
+		groups = "eth_link", "eth_mdio", "eth_rmii";
+		function = "eth";
 	};
 
 	phy1_pins: phy1 {
-		renesas,groups = "intc_irq0";
-		renesas,function = "intc";
+		groups = "intc_irq0";
+		function = "intc";
 	};
 
 	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
-		renesas,function = "sdhi0";
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
 	};
 
 	sdhi1_pins: sd1 {
-		renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
-		renesas,function = "sdhi1";
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
 	};
 
 	sdhi2_pins: sd2 {
-		renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
-		renesas,function = "sdhi2";
+		groups = "sdhi2_data4", "sdhi2_ctrl";
+		function = "sdhi2";
 	};
 
 	qspi_pins: spi0 {
-		renesas,groups = "qspi_ctrl", "qspi_data4";
-		renesas,function = "qspi";
+		groups = "qspi_ctrl", "qspi_data4";
+		function = "qspi";
 	};
 
 	msiof0_pins: spi1 {
-		renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
+		groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
 				 "msiof0_tx";
-		renesas,function = "msiof0";
+		function = "msiof0";
 	};
 
 	usb0_pins: usb0 {
-		renesas,groups = "usb0";
-		renesas,function = "usb0";
+		groups = "usb0";
+		function = "usb0";
 	};
 
 	usb1_pins: usb1 {
-		renesas,groups = "usb1";
-		renesas,function = "usb1";
+		groups = "usb1";
+		function = "usb1";
 	};
 
 	vin1_pins: vin1 {
-		renesas,groups = "vin1_data8", "vin1_clk";
-		renesas,function = "vin1";
+		groups = "vin1_data8", "vin1_clk";
+		function = "vin1";
 	};
 
 	sound_pins: sound {
-		renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
-		renesas,function = "ssi";
+		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+		function = "ssi";
 	};
 
 	sound_clk_pins: sound_clk {
-		renesas,groups = "audio_clk_a";
-		renesas,function = "audio_clk";
+		groups = "audio_clk_a";
+		function = "audio_clk";
 	};
 };
 
@@ -440,6 +447,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-names = "default";
@@ -648,6 +660,7 @@
 };
 
 &pcie_bus_clk {
+	clock-frequency = <100000000>;
 	status = "okay";
 };
 
diff --git a/sys/gnu/dts/arm/r8a7791-porter.dts b/sys/gnu/dts/arm/r8a7791-porter.dts
index 6713b1ea732b..6a1bb1a8209b 100644
--- a/sys/gnu/dts/arm/r8a7791-porter.dts
+++ b/sys/gnu/dts/arm/r8a7791-porter.dts
@@ -8,6 +8,17 @@
  * kind, whether express or implied.
  */
 
+/*
+ * SSI-AK4642
+ *
+ * JP3: 2-1: AK4642
+ *      2-3: ADV7511
+ *
+ * This command is required before playback/capture:
+ *
+ *	amixer set "LINEOUT Mixer DACL" on
+ */
+
 /dts-v1/;
 #include "r8a7791.dtsi"
 #include <dt-bindings/gpio/gpio.h>
@@ -78,6 +89,52 @@
 		states = <3300000 1
 			  1800000 0>;
 	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&adv7511_out>;
+			};
+		};
+	};
+
+	x3_clk: x3-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <148500000>;
+	};
+
+	x16_clk: x16-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <74250000>;
+	};
+
+	x14_clk: audio_clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <11289600>;
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+
+		simple-audio-card,format = "left_j";
+		simple-audio-card,bitclock-master = <&soundcodec>;
+		simple-audio-card,frame-master = <&soundcodec>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&rcar_sound>;
+		};
+
+		soundcodec: simple-audio-card,codec {
+			sound-dai = <&ak4642>;
+			clocks = <&x14_clk>;
+		};
+	};
 };
 
 &extal_clk {
@@ -86,58 +143,73 @@
 
 &pfc {
 	scif0_pins: serial0 {
-		renesas,groups = "scif0_data_d";
-		renesas,function = "scif0";
+		groups = "scif0_data_d";
+		function = "scif0";
 	};
 
 	ether_pins: ether {
-		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
-		renesas,function = "eth";
+		groups = "eth_link", "eth_mdio", "eth_rmii";
+		function = "eth";
 	};
 
 	phy1_pins: phy1 {
-		renesas,groups = "intc_irq0";
-		renesas,function = "intc";
+		groups = "intc_irq0";
+		function = "intc";
 	};
 
 	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
-		renesas,function = "sdhi0";
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
 	};
 
 	sdhi2_pins: sd2 {
-		renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
-		renesas,function = "sdhi2";
+		groups = "sdhi2_data4", "sdhi2_ctrl";
+		function = "sdhi2";
 	};
 
 	qspi_pins: spi0 {
-		renesas,groups = "qspi_ctrl", "qspi_data4";
-		renesas,function = "qspi";
+		groups = "qspi_ctrl", "qspi_data4";
+		function = "qspi";
 	};
 
 	i2c2_pins: i2c2 {
-		renesas,groups = "i2c2";
-		renesas,function = "i2c2";
+		groups = "i2c2";
+		function = "i2c2";
 	};
 
 	usb0_pins: usb0 {
-		renesas,groups = "usb0";
-		renesas,function = "usb0";
+		groups = "usb0";
+		function = "usb0";
 	};
 
 	usb1_pins: usb1 {
-		renesas,groups = "usb1";
-		renesas,function = "usb1";
+		groups = "usb1";
+		function = "usb1";
 	};
 
 	vin0_pins: vin0 {
-		renesas,groups = "vin0_data8", "vin0_clk";
-		renesas,function = "vin0";
+		groups = "vin0_data8", "vin0_clk";
+		function = "vin0";
 	};
 
 	can0_pins: can0 {
-		renesas,groups = "can0_data";
-		renesas,function = "can0";
+		groups = "can0_data";
+		function = "can0";
+	};
+
+	du_pins: du {
+		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+		function = "du";
+	};
+
+	ssi_pins: sound {
+		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+		function = "ssi";
+	};
+
+	audio_clk_pins: audio_clk {
+		groups = "audio_clk_a";
+		function = "audio_clk";
 	};
 };
 
@@ -229,6 +301,12 @@
 	status = "okay";
 	clock-frequency = <400000>;
 
+	ak4642: codec@12 {
+		compatible = "asahi-kasei,ak4642";
+		#sound-dai-cells = <0>;
+		reg = <0x12>;
+	};
+
 	composite-in@20 {
 		compatible = "adi,adv7180";
 		reg = <0x20>;
@@ -241,6 +319,38 @@
 			};
 		};
 	};
+
+	hdmi@39 {
+		compatible = "adi,adv7511w";
+		reg = <0x39>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+		adi,input-depth = <8>;
+		adi,input-colorspace = "rgb";
+		adi,input-clock = "1x";
+		adi,input-style = <1>;
+		adi,input-justification = "evenly";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7511_in: endpoint {
+					remote-endpoint = <&du_out_rgb>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7511_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
 };
 
 &sata0 {
@@ -283,7 +393,6 @@
 	pinctrl-names = "default";
 
 	status = "okay";
-	renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
 };
 
 &usbphy {
@@ -291,6 +400,7 @@
 };
 
 &pcie_bus_clk {
+	clock-frequency = <100000000>;
 	status = "okay";
 };
 
@@ -304,3 +414,44 @@
 
 	status = "okay";
 };
+
+&du {
+	pinctrl-0 = <&du_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	clocks = <&mstp7_clks R8A7791_CLK_DU0>,
+		 <&mstp7_clks R8A7791_CLK_DU1>,
+		 <&mstp7_clks R8A7791_CLK_LVDS0>,
+		 <&x3_clk>, <&x16_clk>;
+	clock-names = "du.0", "du.1", "lvds.0",
+		      "dclkin.0", "dclkin.1";
+
+	ports {
+		port@1 {
+			endpoint {
+				remote-endpoint = <&adv7511_in>;
+			};
+		};
+	};
+};
+
+&rcar_sound {
+	pinctrl-0 = <&ssi_pins &audio_clk_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	/* Single DAI */
+	#sound-dai-cells = <0>;
+
+	rcar_sound,dai {
+		dai0 {
+			playback = <&ssi0>;
+			capture  = <&ssi1>;
+		};
+	};
+};
+
+&ssi1 {
+	shared-pin;
+};
diff --git a/sys/gnu/dts/arm/r8a7791.dtsi b/sys/gnu/dts/arm/r8a7791.dtsi
index 2a369ddcb6fd..db67e342c585 100644
--- a/sys/gnu/dts/arm/r8a7791.dtsi
+++ b/sys/gnu/dts/arm/r8a7791.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/clock/r8a7791-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7791-sysc.h>
 
 / {
 	compatible = "renesas,r8a7791";
@@ -51,6 +52,8 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7791_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
+			next-level-cache = <&L2_CA15>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1500000 1000000>,
@@ -66,9 +69,37 @@
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 			clock-frequency = <1500000000>;
+			power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive	= <0>;
+			polling-delay		= <0>;
+
+			thermal-sensors = <&thermal>;
+
+			trips {
+				cpu-crit {
+					temperature	= <115000>;
+					hysteresis	= <0>;
+					type		= "critical";
+				};
+			};
+			cooling-maps {
+			};
+		};
+	};
+
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		power-domains = <&sysc R8A7791_PD_CA15_SCU>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
@@ -78,137 +109,140 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	gpio0: gpio@e6050000 {
 		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 		reg = <0 0xe6050000 0 0x50>;
-		interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 0 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
 	gpio1: gpio@e6051000 {
 		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 		reg = <0 0xe6051000 0 0x50>;
-		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 32 26>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
 	gpio2: gpio@e6052000 {
 		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 		reg = <0 0xe6052000 0 0x50>;
-		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 64 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
 	gpio3: gpio@e6053000 {
 		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 		reg = <0 0xe6053000 0 0x50>;
-		interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 96 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
 	gpio4: gpio@e6054000 {
 		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 		reg = <0 0xe6054000 0 0x50>;
-		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 128 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
 	gpio5: gpio@e6055000 {
 		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 		reg = <0 0xe6055000 0 0x50>;
-		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 160 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
 	gpio6: gpio@e6055400 {
 		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 		reg = <0 0xe6055400 0 0x50>;
-		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 192 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
 	gpio7: gpio@e6055800 {
 		compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 		reg = <0 0xe6055800 0 0x50>;
-		interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 224 26>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
-	thermal@e61f0000 {
-		compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
+	thermal: thermal@e61f0000 {
+		compatible =	"renesas,thermal-r8a7791",
+				"renesas,rcar-gen2-thermal",
+				"renesas,rcar-thermal";
 		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
-		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+		#thermal-sensor-cells = <0>;
 	};
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	cmt0: timer@ffca0000 {
 		compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 		reg = <0 0xffca0000 0 0x1004>;
-		interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 
 		renesas,channels-mask = <0x60>;
 
@@ -218,17 +252,17 @@
 	cmt1: timer@e6130000 {
 		compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 		reg = <0 0xe6130000 0 0x1004>;
-		interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 121 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 122 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 123 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 124 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 125 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 126 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 127 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 
 		renesas,channels-mask = <0xff>;
 
@@ -240,39 +274,39 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		reg = <0 0xe61c0000 0 0x200>;
-		interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 3 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 12 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 13 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 14 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 15 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 16 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
 	dmac0: dma-controller@e6700000 {
 		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 		reg = <0 0xe6700000 0 0x20000>;
-		interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
-			      0 200 IRQ_TYPE_LEVEL_HIGH
-			      0 201 IRQ_TYPE_LEVEL_HIGH
-			      0 202 IRQ_TYPE_LEVEL_HIGH
-			      0 203 IRQ_TYPE_LEVEL_HIGH
-			      0 204 IRQ_TYPE_LEVEL_HIGH
-			      0 205 IRQ_TYPE_LEVEL_HIGH
-			      0 206 IRQ_TYPE_LEVEL_HIGH
-			      0 207 IRQ_TYPE_LEVEL_HIGH
-			      0 208 IRQ_TYPE_LEVEL_HIGH
-			      0 209 IRQ_TYPE_LEVEL_HIGH
-			      0 210 IRQ_TYPE_LEVEL_HIGH
-			      0 211 IRQ_TYPE_LEVEL_HIGH
-			      0 212 IRQ_TYPE_LEVEL_HIGH
-			      0 213 IRQ_TYPE_LEVEL_HIGH
-			      0 214 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -280,7 +314,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
@@ -288,22 +322,22 @@
 	dmac1: dma-controller@e6720000 {
 		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 		reg = <0 0xe6720000 0 0x20000>;
-		interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
-			      0 216 IRQ_TYPE_LEVEL_HIGH
-			      0 217 IRQ_TYPE_LEVEL_HIGH
-			      0 218 IRQ_TYPE_LEVEL_HIGH
-			      0 219 IRQ_TYPE_LEVEL_HIGH
-			      0 308 IRQ_TYPE_LEVEL_HIGH
-			      0 309 IRQ_TYPE_LEVEL_HIGH
-			      0 310 IRQ_TYPE_LEVEL_HIGH
-			      0 311 IRQ_TYPE_LEVEL_HIGH
-			      0 312 IRQ_TYPE_LEVEL_HIGH
-			      0 313 IRQ_TYPE_LEVEL_HIGH
-			      0 314 IRQ_TYPE_LEVEL_HIGH
-			      0 315 IRQ_TYPE_LEVEL_HIGH
-			      0 316 IRQ_TYPE_LEVEL_HIGH
-			      0 317 IRQ_TYPE_LEVEL_HIGH
-			      0 318 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -311,7 +345,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
@@ -319,20 +353,20 @@
 	audma0: dma-controller@ec700000 {
 		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 		reg = <0 0xec700000 0 0x10000>;
-		interrupts =	<0 346 IRQ_TYPE_LEVEL_HIGH
-				 0 320 IRQ_TYPE_LEVEL_HIGH
-				 0 321 IRQ_TYPE_LEVEL_HIGH
-				 0 322 IRQ_TYPE_LEVEL_HIGH
-				 0 323 IRQ_TYPE_LEVEL_HIGH
-				 0 324 IRQ_TYPE_LEVEL_HIGH
-				 0 325 IRQ_TYPE_LEVEL_HIGH
-				 0 326 IRQ_TYPE_LEVEL_HIGH
-				 0 327 IRQ_TYPE_LEVEL_HIGH
-				 0 328 IRQ_TYPE_LEVEL_HIGH
-				 0 329 IRQ_TYPE_LEVEL_HIGH
-				 0 330 IRQ_TYPE_LEVEL_HIGH
-				 0 331 IRQ_TYPE_LEVEL_HIGH
-				 0 332 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts =	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -340,7 +374,7 @@
 				"ch12";
 		clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <13>;
 	};
@@ -348,20 +382,20 @@
 	audma1: dma-controller@ec720000 {
 		compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
 		reg = <0 0xec720000 0 0x10000>;
-		interrupts =	<0 347 IRQ_TYPE_LEVEL_HIGH
-				 0 333 IRQ_TYPE_LEVEL_HIGH
-				 0 334 IRQ_TYPE_LEVEL_HIGH
-				 0 335 IRQ_TYPE_LEVEL_HIGH
-				 0 336 IRQ_TYPE_LEVEL_HIGH
-				 0 337 IRQ_TYPE_LEVEL_HIGH
-				 0 338 IRQ_TYPE_LEVEL_HIGH
-				 0 339 IRQ_TYPE_LEVEL_HIGH
-				 0 340 IRQ_TYPE_LEVEL_HIGH
-				 0 341 IRQ_TYPE_LEVEL_HIGH
-				 0 342 IRQ_TYPE_LEVEL_HIGH
-				 0 343 IRQ_TYPE_LEVEL_HIGH
-				 0 344 IRQ_TYPE_LEVEL_HIGH
-				 0 345 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts =	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+				 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -369,7 +403,7 @@
 				"ch12";
 		clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <13>;
 	};
@@ -377,11 +411,11 @@
 	usb_dmac0: dma-controller@e65a0000 {
 		compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 		reg = <0 0xe65a0000 0 0x100>;
-		interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
-			      0 109 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "ch0", "ch1";
 		clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <2>;
 	};
@@ -389,11 +423,11 @@
 	usb_dmac1: dma-controller@e65b0000 {
 		compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
 		reg = <0 0xe65b0000 0 0x100>;
-		interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
-			      0 110 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "ch0", "ch1";
 		clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <2>;
 	};
@@ -404,9 +438,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7791";
 		reg = <0 0xe6508000 0 0x40>;
-		interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <6>;
 		status = "disabled";
 	};
@@ -416,9 +450,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7791";
 		reg = <0 0xe6518000 0 0x40>;
-		interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <6>;
 		status = "disabled";
 	};
@@ -428,9 +462,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7791";
 		reg = <0 0xe6530000 0 0x40>;
-		interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <6>;
 		status = "disabled";
 	};
@@ -440,9 +474,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7791";
 		reg = <0 0xe6540000 0 0x40>;
-		interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <6>;
 		status = "disabled";
 	};
@@ -452,9 +486,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7791";
 		reg = <0 0xe6520000 0 0x40>;
-		interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <6>;
 		status = "disabled";
 	};
@@ -465,9 +499,9 @@
 		#size-cells = <0>;
 		compatible = "renesas,i2c-r8a7791";
 		reg = <0 0xe6528000 0 0x40>;
-		interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		i2c-scl-internal-delay-ns = <110>;
 		status = "disabled";
 	};
@@ -478,11 +512,11 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 		reg = <0 0xe60b0000 0 0x425>;
-		interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 		dmas = <&dmac0 0x77>, <&dmac0 0x78>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -491,11 +525,11 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 		reg = <0 0xe6500000 0 0x425>;
-		interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 		dmas = <&dmac0 0x61>, <&dmac0 0x62>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -504,11 +538,11 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 		reg = <0 0xe6510000 0 0x425>;
-		interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 		dmas = <&dmac0 0x65>, <&dmac0 0x66>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
@@ -520,11 +554,11 @@
 	mmcif0: mmc@ee200000 {
 		compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
 		reg = <0 0xee200000 0 0x80>;
-		interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		reg-io-width = <4>;
 		status = "disabled";
 		max-frequency = <97500000>;
@@ -533,258 +567,285 @@
 	sdhi0: sd@ee100000 {
 		compatible = "renesas,sdhi-r8a7791";
 		reg = <0 0xee100000 0 0x328>;
-		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 		dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi1: sd@ee140000 {
 		compatible = "renesas,sdhi-r8a7791";
 		reg = <0 0xee140000 0 0x100>;
-		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 		dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi2: sd@ee160000 {
 		compatible = "renesas,sdhi-r8a7791";
 		reg = <0 0xee160000 0 0x100>;
-		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 		dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa0: serial@e6c40000 {
-		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7791",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c40000 0 64>;
-		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa1: serial@e6c50000 {
-		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7791",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c50000 0 64>;
-		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa2: serial@e6c60000 {
-		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7791",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c60000 0 64>;
-		interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa3: serial@e6c70000 {
-		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7791",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c70000 0 64>;
-		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa4: serial@e6c78000 {
-		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7791",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c78000 0 64>;
-		interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa5: serial@e6c80000 {
-		compatible = "renesas,scifa-r8a7791", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7791",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c80000 0 64>;
-		interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb0: serial@e6c20000 {
-		compatible = "renesas,scifb-r8a7791", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7791",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6c20000 0 64>;
-		interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb1: serial@e6c30000 {
-		compatible = "renesas,scifb-r8a7791", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7791",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6c30000 0 64>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb2: serial@e6ce0000 {
-		compatible = "renesas,scifb-r8a7791", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7791",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6ce0000 0 64>;
-		interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif0: serial@e6e60000 {
-		compatible = "renesas,scif-r8a7791", "renesas,scif";
+		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e60000 0 64>;
-		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif1: serial@e6e68000 {
-		compatible = "renesas,scif-r8a7791", "renesas,scif";
+		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e68000 0 64>;
-		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif2: serial@e6e58000 {
-		compatible = "renesas,scif-r8a7791", "renesas,scif";
+		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e58000 0 64>;
-		interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif3: serial@e6ea8000 {
-		compatible = "renesas,scif-r8a7791", "renesas,scif";
+		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6ea8000 0 64>;
-		interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif4: serial@e6ee0000 {
-		compatible = "renesas,scif-r8a7791", "renesas,scif";
+		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6ee0000 0 64>;
-		interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif5: serial@e6ee8000 {
-		compatible = "renesas,scif-r8a7791", "renesas,scif";
+		compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6ee8000 0 64>;
-		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif0: serial@e62c0000 {
-		compatible = "renesas,hscif-r8a7791", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7791",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62c0000 0 96>;
-		interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif1: serial@e62c8000 {
-		compatible = "renesas,hscif-r8a7791", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7791",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62c8000 0 96>;
-		interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif2: serial@e62d0000 {
-		compatible = "renesas,hscif-r8a7791", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7791",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62d0000 0 96>;
-		interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	ether: ethernet@ee700000 {
 		compatible = "renesas,ether-r8a7791";
 		reg = <0 0xee700000 0 0x400>;
-		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -795,9 +856,9 @@
 		compatible = "renesas,etheravb-r8a7791",
 			     "renesas,etheravb-rcar-gen2";
 		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
-		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -806,30 +867,30 @@
 	sata0: sata@ee300000 {
 		compatible = "renesas,sata-r8a7791";
 		reg = <0 0xee300000 0 0x2000>;
-		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sata1: sata@ee500000 {
 		compatible = "renesas,sata-r8a7791";
 		reg = <0 0xee500000 0 0x2000>;
-		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hsusb: usb@e6590000 {
-		compatible = "renesas,usbhs-r8a7791";
+		compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
 		reg = <0 0xe6590000 0 0x100>;
-		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 		dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
 		       <&usb_dmac1 0>, <&usb_dmac1 1>;
 		dma-names = "ch0", "ch1", "ch2", "ch3";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		renesas,buswait = <4>;
 		phys = <&usb0 1>;
 		phy-names = "usb";
@@ -843,7 +904,7 @@
 		#size-cells = <0>;
 		clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 		clock-names = "usbhs";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		usb0: usb-channel@0 {
@@ -859,36 +920,36 @@
 	vin0: video@e6ef0000 {
 		compatible = "renesas,vin-r8a7791";
 		reg = <0 0xe6ef0000 0 0x1000>;
-		interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	vin1: video@e6ef1000 {
 		compatible = "renesas,vin-r8a7791";
 		reg = <0 0xe6ef1000 0 0x1000>;
-		interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	vin2: video@e6ef2000 {
 		compatible = "renesas,vin-r8a7791";
 		reg = <0 0xe6ef2000 0 0x1000>;
-		interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	vsp1@fe928000 {
 		compatible = "renesas,vsp1";
 		reg = <0 0xfe928000 0 0x8000>;
-		interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 
 		renesas,has-lut;
 		renesas,has-sru;
@@ -900,9 +961,9 @@
 	vsp1@fe930000 {
 		compatible = "renesas,vsp1";
 		reg = <0 0xfe930000 0 0x8000>;
-		interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 
 		renesas,has-lif;
 		renesas,has-lut;
@@ -914,9 +975,9 @@
 	vsp1@fe938000 {
 		compatible = "renesas,vsp1";
 		reg = <0 0xfe938000 0 0x8000>;
-		interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 
 		renesas,has-lif;
 		renesas,has-lut;
@@ -930,8 +991,8 @@
 		reg = <0 0xfeb00000 0 0x40000>,
 		      <0 0xfeb90000 0 0x1c>;
 		reg-names = "du", "lvds.0";
-		interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 268 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_DU0>,
 			 <&mstp7_clks R8A7791_CLK_DU1>,
 			 <&mstp7_clks R8A7791_CLK_LVDS0>;
@@ -956,33 +1017,33 @@
 	};
 
 	can0: can@e6e80000 {
-		compatible = "renesas,can-r8a7791";
+		compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
 		reg = <0 0xe6e80000 0 0x1000>;
-		interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
 			 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
 		clock-names = "clkp1", "clkp2", "can_clk";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	can1: can@e6e88000 {
-		compatible = "renesas,can-r8a7791";
+		compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
 		reg = <0 0xe6e88000 0 0x1000>;
-		interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
 			 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
 		clock-names = "clkp1", "clkp2", "can_clk";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	jpu: jpeg-codec@fe980000 {
-		compatible = "renesas,jpu-r8a7791";
+		compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
 		reg = <0 0xfe980000 0 0x10300>;
-		interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7791_CLK_JPU>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 	};
 
 	clocks {
@@ -991,12 +1052,11 @@
 		ranges;
 
 		/* External root clock */
-		extal_clk: extal_clk {
+		extal_clk: extal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			/* This value must be overriden by the board. */
 			clock-frequency = <0>;
-			clock-output-names = "extal";
 		};
 
 		/*
@@ -1007,36 +1067,38 @@
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "audio_clk_a";
 		};
 		audio_clk_b: audio_clk_b {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "audio_clk_b";
 		};
 		audio_clk_c: audio_clk_c {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "audio_clk_c";
 		};
 
 		/* External PCIe clock - can be overridden by the board */
-		pcie_bus_clk: pcie_bus_clk {
+		pcie_bus_clk: pcie_bus {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		/* External SCIF clock */
+		scif_clk: scif {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <100000000>;
-			clock-output-names = "pcie_bus";
-			status = "disabled";
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
 		};
 
 		/* External USB clock - can be overridden by the board */
-		usb_extal_clk: usb_extal_clk {
+		usb_extal_clk: usb_extal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <48000000>;
-			clock-output-names = "usb_extal";
 		};
 
 		/* External CAN clock */
@@ -1045,8 +1107,6 @@
 			#clock-cells = <0>;
 			/* This value must be overridden by the board. */
 			clock-frequency = <0>;
-			clock-output-names = "can_clk";
-			status = "disabled";
 		};
 
 		/* Special CPG clocks */
@@ -1063,178 +1123,156 @@
 		};
 
 		/* Variable factor clocks */
-		sd2_clk: sd2_clk@e6150078 {
+		sd2_clk: sd2@e6150078 {
 			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150078 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sd2";
 		};
-		sd3_clk: sd3_clk@e615026c {
+		sd3_clk: sd3@e615026c {
 			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe615026c 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sd3";
 		};
-		mmc0_clk: mmc0_clk@e6150240 {
+		mmc0_clk: mmc0@e6150240 {
 			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150240 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "mmc0";
 		};
-		ssp_clk: ssp_clk@e6150248 {
+		ssp_clk: ssp@e6150248 {
 			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150248 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "ssp";
 		};
-		ssprs_clk: ssprs_clk@e615024c {
+		ssprs_clk: ssprs@e615024c {
 			compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe615024c 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "ssprs";
 		};
 
 		/* Fixed factor clocks */
-		pll1_div2_clk: pll1_div2_clk {
+		pll1_div2_clk: pll1_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "pll1_div2";
 		};
-		zg_clk: zg_clk {
+		zg_clk: zg {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <3>;
 			clock-mult = <1>;
-			clock-output-names = "zg";
 		};
-		zx_clk: zx_clk {
+		zx_clk: zx {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <3>;
 			clock-mult = <1>;
-			clock-output-names = "zx";
 		};
-		zs_clk: zs_clk {
+		zs_clk: zs {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <6>;
 			clock-mult = <1>;
-			clock-output-names = "zs";
 		};
-		hp_clk: hp_clk {
+		hp_clk: hp {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <12>;
 			clock-mult = <1>;
-			clock-output-names = "hp";
 		};
-		i_clk: i_clk {
+		i_clk: i {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "i";
 		};
-		b_clk: b_clk {
+		b_clk: b {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <12>;
 			clock-mult = <1>;
-			clock-output-names = "b";
 		};
-		p_clk: p_clk {
+		p_clk: p {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <24>;
 			clock-mult = <1>;
-			clock-output-names = "p";
 		};
-		cl_clk: cl_clk {
+		cl_clk: cl {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <48>;
 			clock-mult = <1>;
-			clock-output-names = "cl";
 		};
-		m2_clk: m2_clk {
+		m2_clk: m2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "m2";
 		};
-		rclk_clk: rclk_clk {
+		rclk_clk: rclk {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <(48 * 1024)>;
 			clock-mult = <1>;
-			clock-output-names = "rclk";
 		};
-		oscclk_clk: oscclk_clk {
+		oscclk_clk: oscclk {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <(12 * 1024)>;
 			clock-mult = <1>;
-			clock-output-names = "oscclk";
 		};
-		zb3_clk: zb3_clk {
+		zb3_clk: zb3 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 			#clock-cells = <0>;
 			clock-div = <4>;
 			clock-mult = <1>;
-			clock-output-names = "zb3";
 		};
-		zb3d2_clk: zb3d2_clk {
+		zb3d2_clk: zb3d2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "zb3d2";
 		};
-		ddr_clk: ddr_clk {
+		ddr_clk: ddr {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "ddr";
 		};
-		mp_clk: mp_clk {
+		mp_clk: mp {
 			compatible = "fixed-factor-clock";
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
 			clock-div = <15>;
 			clock-mult = <1>;
-			clock-output-names = "mp";
 		};
-		cp_clk: cp_clk {
+		cp_clk: cp {
 			compatible = "fixed-factor-clock";
 			clocks = <&extal_clk>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "cp";
 		};
 
 		/* Gate clocks */
@@ -1429,14 +1467,20 @@
 		};
 	};
 
+	sysc: system-controller@e6180000 {
+		compatible = "renesas,r8a7791-sysc";
+		reg = <0 0xe6180000 0 0x0200>;
+		#power-domain-cells = <1>;
+	};
+
 	qspi: spi@e6b10000 {
 		compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 		reg = <0 0xe6b10000 0 0x2c>;
-		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 		dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -1446,11 +1490,11 @@
 	msiof0: spi@e6e20000 {
 		compatible = "renesas,msiof-r8a7791";
 		reg = <0 0xe6e20000 0 0x0064>;
-		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
 		dmas = <&dmac0 0x51>, <&dmac0 0x52>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -1459,11 +1503,11 @@
 	msiof1: spi@e6e10000 {
 		compatible = "renesas,msiof-r8a7791";
 		reg = <0 0xe6e10000 0 0x0064>;
-		interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
 		dmas = <&dmac0 0x55>, <&dmac0 0x56>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -1472,35 +1516,35 @@
 	msiof2: spi@e6e00000 {
 		compatible = "renesas,msiof-r8a7791";
 		reg = <0 0xe6e00000 0 0x0064>;
-		interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
 		dmas = <&dmac0 0x41>, <&dmac0 0x42>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
 	};
 
 	xhci: usb@ee000000 {
-		compatible = "renesas,xhci-r8a7791";
+		compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
 		reg = <0 0xee000000 0 0xc00>;
-		interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		phys = <&usb2 1>;
 		phy-names = "usb";
 		status = "disabled";
 	};
 
 	pci0: pci@ee090000 {
-		compatible = "renesas,pci-r8a7791";
+		compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
 		device_type = "pci";
 		reg = <0 0xee090000 0 0xc00>,
 		      <0 0xee080000 0 0x1100>;
-		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		bus-range = <0 0>;
@@ -1509,9 +1553,9 @@
 		#interrupt-cells = <1>;
 		ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 		interrupt-map-mask = <0xff00 0 0 0x7>;
-		interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+				 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+				 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 
 		usb@0,1 {
 			reg = <0x800 0 0 0 0>;
@@ -1529,13 +1573,13 @@
 	};
 
 	pci1: pci@ee0d0000 {
-		compatible = "renesas,pci-r8a7791";
+		compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
 		device_type = "pci";
 		reg = <0 0xee0d0000 0 0xc00>,
 		      <0 0xee0c0000 0 0x1100>;
-		interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		bus-range = <1 1>;
@@ -1544,9 +1588,9 @@
 		#interrupt-cells = <1>;
 		ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 		interrupt-map-mask = <0xff00 0 0 0x7>;
-		interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
-				 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
-				 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+				 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+				 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 
 		usb@0,1 {
 			reg = <0x800 0 0 0 0>;
@@ -1564,7 +1608,7 @@
 	};
 
 	pciec: pcie@fe000000 {
-		compatible = "renesas,pcie-r8a7791";
+		compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
 		reg = <0 0xfe000000 0 0x80000>;
 		#address-cells = <3>;
 		#size-cells = <2>;
@@ -1577,23 +1621,23 @@
 		/* Map all possible DDR as inbound ranges */
 		dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
 			      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
-		interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 117 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 118 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 0>;
-		interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
 		clock-names = "pcie", "pcie_bus";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	ipmmu_sy0: mmu@e6280000 {
 		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6280000 0 0x1000>;
-		interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 224 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1601,7 +1645,7 @@
 	ipmmu_sy1: mmu@e6290000 {
 		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6290000 0 0x1000>;
-		interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1609,8 +1653,8 @@
 	ipmmu_ds: mmu@e6740000 {
 		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6740000 0 0x1000>;
-		interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 199 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1618,7 +1662,7 @@
 	ipmmu_mp: mmu@ec680000 {
 		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
 		reg = <0 0xec680000 0 0x1000>;
-		interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1626,8 +1670,8 @@
 	ipmmu_mx: mmu@fe951000 {
 		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
 		reg = <0 0xfe951000 0 0x1000>;
-		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 221 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1635,7 +1679,7 @@
 	ipmmu_rt: mmu@ffc80000 {
 		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
 		reg = <0 0xffc80000 0 0x1000>;
-		interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1643,8 +1687,8 @@
 	ipmmu_gp: mmu@e62a0000 {
 		compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
 		reg = <0 0xe62a0000 0 0x1000>;
-		interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 261 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1688,7 +1732,7 @@
 				"mix.0", "mix.1",
 				"dvc.0", "dvc.1",
 				"clk_a", "clk_b", "clk_c", "clk_i";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 
 		status = "disabled";
 
@@ -1721,52 +1765,52 @@
 
 		rcar_sound,src {
 			src0: src@0 {
-				interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x85>, <&audma1 0x9a>;
 				dma-names = "rx", "tx";
 			};
 			src1: src@1 {
-				interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x87>, <&audma1 0x9c>;
 				dma-names = "rx", "tx";
 			};
 			src2: src@2 {
-				interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x89>, <&audma1 0x9e>;
 				dma-names = "rx", "tx";
 			};
 			src3: src@3 {
-				interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x8b>, <&audma1 0xa0>;
 				dma-names = "rx", "tx";
 			};
 			src4: src@4 {
-				interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x8d>, <&audma1 0xb0>;
 				dma-names = "rx", "tx";
 			};
 			src5: src@5 {
-				interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x8f>, <&audma1 0xb2>;
 				dma-names = "rx", "tx";
 			};
 			src6: src@6 {
-				interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x91>, <&audma1 0xb4>;
 				dma-names = "rx", "tx";
 			};
 			src7: src@7 {
-				interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x93>, <&audma1 0xb6>;
 				dma-names = "rx", "tx";
 			};
 			src8: src@8 {
-				interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x95>, <&audma1 0xb8>;
 				dma-names = "rx", "tx";
 			};
 			src9: src@9 {
-				interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x97>, <&audma1 0xba>;
 				dma-names = "rx", "tx";
 			};
@@ -1774,52 +1818,52 @@
 
 		rcar_sound,ssi {
 			ssi0: ssi@0 {
-				interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi1: ssi@1 {
-				 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
+				 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi2: ssi@2 {
-				interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi3: ssi@3 {
-				interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi4: ssi@4 {
-				interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi5: ssi@5 {
-				interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi6: ssi@6 {
-				interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi7: ssi@7 {
-				interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi8: ssi@8 {
-				interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
 			ssi9: ssi@9 {
-				interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
 				dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
 				dma-names = "rx", "tx", "rxu", "txu";
 			};
diff --git a/sys/gnu/dts/arm/r8a7793-gose.dts b/sys/gnu/dts/arm/r8a7793-gose.dts
index baa59fe84298..0ebc3ee34923 100644
--- a/sys/gnu/dts/arm/r8a7793-gose.dts
+++ b/sys/gnu/dts/arm/r8a7793-gose.dts
@@ -8,6 +8,34 @@
  * kind, whether express or implied.
  */
 
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ *      2: CN22
+ *      3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ *	amixer set "LINEOUT Mixer DACL" on
+ *	amixer set "DVC Out" 100%
+ *	amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ *	amixer set "DVC Out Mute" on
+ *	amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ *	amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
+ *	amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ *	amixer set "DVC Out Ramp" on
+ *	aplay xxx.wav &
+ *	amixer set "DVC Out"  80%  // Volume Down
+ *	amixer set "DVC Out" 100%  // Volume Up
+ */
+
 /dts-v1/;
 #include "r8a7793.dtsi"
 #include <dt-bindings/gpio/gpio.h>
@@ -31,6 +59,247 @@
 		device_type = "memory";
 		reg = <0 0x40000000 0 0x40000000>;
 	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-1 {
+		        gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_1>;
+		        label = "SW2-1";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-2 {
+		        gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_2>;
+		        label = "SW2-2";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-3 {
+		        gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_3>;
+		        label = "SW2-3";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-4 {
+		        gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_4>;
+		        label = "SW2-4";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-a {
+		        gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_A>;
+		        label = "SW30";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-b {
+		        gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_B>;
+		        label = "SW31";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-c {
+		        gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_C>;
+		        label = "SW32";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-d {
+		        gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_D>;
+		        label = "SW33";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-e {
+		        gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_E>;
+		        label = "SW34";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-f {
+		        gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_F>;
+		        label = "SW35";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+		key-g {
+		        gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+		        linux,code = <KEY_G>;
+		        label = "SW36";
+		        wakeup-source;
+		        debounce-interval = <20>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led6 {
+			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			label = "LED6";
+		};
+		led7 {
+			gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+			label = "LED7";
+		};
+		led8 {
+			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+			label = "LED8";
+		};
+	};
+
+	vcc_sdhi0: regulator@0 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI0 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vccq_sdhi0: regulator@1 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
+
+	vcc_sdhi1: regulator@2 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI1 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vccq_sdhi1: regulator@3 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI1 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
+
+	vcc_sdhi2: regulator@4 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI2 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vccq_sdhi2: regulator@5 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI2 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
+
+	audio_clock: audio_clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <11289600>;
+	};
+
+	rsnd_ak4643: sound {
+		compatible = "simple-audio-card";
+
+		simple-audio-card,format = "left_j";
+		simple-audio-card,bitclock-master = <&sndcodec>;
+		simple-audio-card,frame-master = <&sndcodec>;
+
+		sndcpu: simple-audio-card,cpu {
+			sound-dai = <&rcar_sound>;
+		};
+
+		sndcodec: simple-audio-card,codec {
+			sound-dai = <&ak4643>;
+			clocks = <&audio_clock>;
+		};
+	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&adv7511_out>;
+			};
+		};
+	};
+
+	x2_clk: x2-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <74250000>;
+	};
+
+	x13_clk: x13-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <148500000>;
+	};
+};
+
+&du {
+	pinctrl-0 = <&du_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	clocks = <&mstp7_clks R8A7793_CLK_DU0>,
+		 <&mstp7_clks R8A7793_CLK_DU1>,
+		 <&mstp7_clks R8A7793_CLK_LVDS0>,
+		 <&x13_clk>, <&x2_clk>;
+	clock-names = "du.0", "du.1", "lvds.0",
+		      "dclkin.0", "dclkin.1";
+
+	ports {
+		port@0 {
+			endpoint {
+				remote-endpoint = <&adv7511_in>;
+			};
+		};
+		port@1 {
+			lvds_connector: endpoint {
+			};
+		};
+	};
 };
 
 &extal_clk {
@@ -38,29 +307,72 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	i2c2_pins: i2c2 {
+		groups = "i2c2";
+		function = "i2c2";
+	};
+
+	du_pins: du {
+		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+		function = "du";
+	};
+
 	scif0_pins: serial0 {
-		renesas,groups = "scif0_data_d";
-		renesas,function = "scif0";
+		groups = "scif0_data_d";
+		function = "scif0";
 	};
 
 	scif1_pins: serial1 {
-		renesas,groups = "scif1_data_d";
-		renesas,function = "scif1";
+		groups = "scif1_data_d";
+		function = "scif1";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk";
+		function = "scif_clk";
 	};
 
 	ether_pins: ether {
-		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
-		renesas,function = "eth";
+		groups = "eth_link", "eth_mdio", "eth_rmii";
+		function = "eth";
 	};
 
 	phy1_pins: phy1 {
-		renesas,groups = "intc_irq0";
-		renesas,function = "intc";
+		groups = "intc_irq0";
+		function = "intc";
+	};
+
+	sdhi0_pins: sd0 {
+		renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
+		renesas,function = "sdhi0";
+	};
+
+	sdhi1_pins: sd1 {
+		renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
+		renesas,function = "sdhi1";
+	};
+
+	sdhi2_pins: sd2 {
+		renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
+		renesas,function = "sdhi2";
 	};
 
 	qspi_pins: spi0 {
-		renesas,groups = "qspi_ctrl", "qspi_data4";
-		renesas,function = "qspi";
+		groups = "qspi_ctrl", "qspi_data4";
+		function = "qspi";
+	};
+
+	sound_pins: sound {
+		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+		function = "ssi";
+	};
+
+	sound_clk_pins: sound_clk {
+		groups = "audio_clk_a";
+		function = "audio_clk";
 	};
 };
 
@@ -98,6 +410,43 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&vcc_sdhi0>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&vcc_sdhi1>;
+	vqmmc-supply = <&vccq_sdhi1>;
+	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&sdhi2 {
+	pinctrl-0 = <&sdhi2_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&vcc_sdhi2>;
+	vqmmc-supply = <&vccq_sdhi2>;
+	cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &qspi {
 	pinctrl-0 = <&qspi_pins>;
 	pinctrl-names = "default";
@@ -136,3 +485,76 @@
 		};
 	};
 };
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	clock-frequency = <100000>;
+
+	ak4643: codec@12 {
+		compatible = "asahi-kasei,ak4643";
+		#sound-dai-cells = <0>;
+		reg = <0x12>;
+	};
+
+	hdmi@39 {
+		compatible = "adi,adv7511w";
+		reg = <0x39>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+		adi,input-depth = <8>;
+		adi,input-colorspace = "rgb";
+		adi,input-clock = "1x";
+		adi,input-style = <1>;
+		adi,input-justification = "evenly";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7511_in: endpoint {
+					remote-endpoint = <&du_out_rgb>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7511_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+
+	eeprom@50 {
+		compatible = "renesas,r1ex24002", "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&rcar_sound {
+	pinctrl-0 = <&sound_pins &sound_clk_pins>;
+	pinctrl-names = "default";
+
+	/* Single DAI */
+	#sound-dai-cells = <0>;
+
+	status = "okay";
+
+	rcar_sound,dai {
+		dai0 {
+			playback = <&ssi0 &src2 &dvc0>;
+			capture  = <&ssi1 &src3 &dvc1>;
+		};
+	};
+};
+
+&ssi1 {
+	shared-pin;
+};
diff --git a/sys/gnu/dts/arm/r8a7793.dtsi b/sys/gnu/dts/arm/r8a7793.dtsi
index aef9e69d6c26..1dd6d202cd4c 100644
--- a/sys/gnu/dts/arm/r8a7793.dtsi
+++ b/sys/gnu/dts/arm/r8a7793.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/r8a7793-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7793-sysc.h>
 
 / {
 	compatible = "renesas,r8a7793";
@@ -19,6 +20,15 @@
 	#size-cells = <2>;
 
 	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
 		spi0 = &qspi;
 	};
 
@@ -34,6 +44,7 @@
 			voltage-tolerance = <1>; /* 1% */
 			clocks = <&cpg_clocks R8A7793_CLK_Z>;
 			clock-latency = <300000>; /* 300 us */
+			power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
 
 			/* kHz - uV - OPPs unknown yet */
 			operating-points = <1500000 1000000>,
@@ -42,9 +53,36 @@
 					   < 937500 1000000>,
 					   < 750000 1000000>,
 					   < 375000 1000000>;
+			next-level-cache = <&L2_CA15>;
 		};
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive	= <0>;
+			polling-delay		= <0>;
+
+			thermal-sensors = <&thermal>;
+
+			trips {
+				cpu-crit {
+					temperature	= <115000>;
+					hysteresis	= <0>;
+					type		= "critical";
+				};
+			};
+			cooling-maps {
+			};
+		};
+	};
+
+	L2_CA15: cache-controller@0 {
+		compatible = "cache";
+		power-domains = <&sysc R8A7793_PD_CA15_SCU>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
@@ -54,137 +92,140 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	gpio0: gpio@e6050000 {
 		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 		reg = <0 0xe6050000 0 0x50>;
-		interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 0 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 	};
 
 	gpio1: gpio@e6051000 {
 		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 		reg = <0 0xe6051000 0 0x50>;
-		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 32 26>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 	};
 
 	gpio2: gpio@e6052000 {
 		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 		reg = <0 0xe6052000 0 0x50>;
-		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 64 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 	};
 
 	gpio3: gpio@e6053000 {
 		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 		reg = <0 0xe6053000 0 0x50>;
-		interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 96 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 	};
 
 	gpio4: gpio@e6054000 {
 		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 		reg = <0 0xe6054000 0 0x50>;
-		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 128 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 	};
 
 	gpio5: gpio@e6055000 {
 		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 		reg = <0 0xe6055000 0 0x50>;
-		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 160 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 	};
 
 	gpio6: gpio@e6055400 {
 		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 		reg = <0 0xe6055400 0 0x50>;
-		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 192 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 	};
 
 	gpio7: gpio@e6055800 {
 		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 		reg = <0 0xe6055800 0 0x50>;
-		interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 224 26>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 	};
 
-	thermal@e61f0000 {
-		compatible = "renesas,thermal-r8a7793", "renesas,rcar-thermal";
+	thermal: thermal@e61f0000 {
+		compatible =	"renesas,thermal-r8a7793",
+				"renesas,rcar-gen2-thermal",
+				"renesas,rcar-thermal";
 		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
-		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		#thermal-sensor-cells = <0>;
 	};
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	cmt0: timer@ffca0000 {
 		compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 		reg = <0 0xffca0000 0 0x1004>;
-		interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 
 		renesas,channels-mask = <0x60>;
 
@@ -194,17 +235,17 @@
 	cmt1: timer@e6130000 {
 		compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 		reg = <0 0xe6130000 0 0x1004>;
-		interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 121 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 122 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 123 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 124 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 125 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 126 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 127 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 
 		renesas,channels-mask = <0xff>;
 
@@ -216,44 +257,39 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		reg = <0 0xe61c0000 0 0x200>;
-		interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 3 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 12 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 13 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 14 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 15 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 16 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
-		power-domains = <&cpg_clocks>;
-	};
-
-	pfc: pfc@e6060000 {
-		compatible = "renesas,pfc-r8a7793";
-		reg = <0 0xe6060000 0 0x250>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 	};
 
 	dmac0: dma-controller@e6700000 {
 		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 		reg = <0 0xe6700000 0 0x20000>;
-		interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
-			      0 200 IRQ_TYPE_LEVEL_HIGH
-			      0 201 IRQ_TYPE_LEVEL_HIGH
-			      0 202 IRQ_TYPE_LEVEL_HIGH
-			      0 203 IRQ_TYPE_LEVEL_HIGH
-			      0 204 IRQ_TYPE_LEVEL_HIGH
-			      0 205 IRQ_TYPE_LEVEL_HIGH
-			      0 206 IRQ_TYPE_LEVEL_HIGH
-			      0 207 IRQ_TYPE_LEVEL_HIGH
-			      0 208 IRQ_TYPE_LEVEL_HIGH
-			      0 209 IRQ_TYPE_LEVEL_HIGH
-			      0 210 IRQ_TYPE_LEVEL_HIGH
-			      0 211 IRQ_TYPE_LEVEL_HIGH
-			      0 212 IRQ_TYPE_LEVEL_HIGH
-			      0 213 IRQ_TYPE_LEVEL_HIGH
-			      0 214 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -261,7 +297,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
@@ -269,22 +305,22 @@
 	dmac1: dma-controller@e6720000 {
 		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 		reg = <0 0xe6720000 0 0x20000>;
-		interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
-			      0 216 IRQ_TYPE_LEVEL_HIGH
-			      0 217 IRQ_TYPE_LEVEL_HIGH
-			      0 218 IRQ_TYPE_LEVEL_HIGH
-			      0 219 IRQ_TYPE_LEVEL_HIGH
-			      0 308 IRQ_TYPE_LEVEL_HIGH
-			      0 309 IRQ_TYPE_LEVEL_HIGH
-			      0 310 IRQ_TYPE_LEVEL_HIGH
-			      0 311 IRQ_TYPE_LEVEL_HIGH
-			      0 312 IRQ_TYPE_LEVEL_HIGH
-			      0 313 IRQ_TYPE_LEVEL_HIGH
-			      0 314 IRQ_TYPE_LEVEL_HIGH
-			      0 315 IRQ_TYPE_LEVEL_HIGH
-			      0 316 IRQ_TYPE_LEVEL_HIGH
-			      0 317 IRQ_TYPE_LEVEL_HIGH
-			      0 318 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -292,233 +328,470 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
 
+	audma0: dma-controller@ec700000 {
+		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+		reg = <0 0xec700000 0 0x10000>;
+		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				"ch0", "ch1", "ch2", "ch3",
+				"ch4", "ch5", "ch6", "ch7",
+				"ch8", "ch9", "ch10", "ch11",
+				"ch12";
+		clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
+		clock-names = "fck";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		#dma-cells = <1>;
+		dma-channels = <13>;
+	};
+
+	audma1: dma-controller@ec720000 {
+		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
+		reg = <0 0xec720000 0 0x10000>;
+		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				"ch0", "ch1", "ch2", "ch3",
+				"ch4", "ch5", "ch6", "ch7",
+				"ch8", "ch9", "ch10", "ch11",
+				"ch12";
+		clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
+		clock-names = "fck";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		#dma-cells = <1>;
+		dma-channels = <13>;
+	};
+
+	/* The memory map in the User's Manual maps the cores to bus numbers */
+	i2c0: i2c@e6508000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-r8a7793";
+		reg = <0 0xe6508000 0 0x40>;
+		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		i2c-scl-internal-delay-ns = <6>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@e6518000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-r8a7793";
+		reg = <0 0xe6518000 0 0x40>;
+		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		i2c-scl-internal-delay-ns = <6>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@e6530000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-r8a7793";
+		reg = <0 0xe6530000 0 0x40>;
+		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		i2c-scl-internal-delay-ns = <6>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@e6540000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-r8a7793";
+		reg = <0 0xe6540000 0 0x40>;
+		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		i2c-scl-internal-delay-ns = <6>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@e6520000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-r8a7793";
+		reg = <0 0xe6520000 0 0x40>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		i2c-scl-internal-delay-ns = <6>;
+		status = "disabled";
+	};
+
+	i2c5: i2c@e6528000 {
+		/* doesn't need pinmux */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,i2c-r8a7793";
+		reg = <0 0xe6528000 0 0x40>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		i2c-scl-internal-delay-ns = <110>;
+		status = "disabled";
+	};
+
+	i2c6: i2c@e60b0000 {
+		/* doesn't need pinmux */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
+		reg = <0 0xe60b0000 0 0x425>;
+		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
+		dmas = <&dmac0 0x77>, <&dmac0 0x78>;
+		dma-names = "tx", "rx";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	i2c7: i2c@e6500000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
+		reg = <0 0xe6500000 0 0x425>;
+		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
+		dmas = <&dmac0 0x61>, <&dmac0 0x62>;
+		dma-names = "tx", "rx";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	i2c8: i2c@e6510000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
+		reg = <0 0xe6510000 0 0x425>;
+		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
+		dmas = <&dmac0 0x65>, <&dmac0 0x66>;
+		dma-names = "tx", "rx";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	pfc: pfc@e6060000 {
+		compatible = "renesas,pfc-r8a7793";
+		reg = <0 0xe6060000 0 0x250>;
+	};
+
+	sdhi0: sd@ee100000 {
+		compatible = "renesas,sdhi-r8a7793";
+		reg = <0 0xee100000 0 0x328>;
+		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
+		dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
+		dma-names = "tx", "rx";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	sdhi1: sd@ee140000 {
+		compatible = "renesas,sdhi-r8a7793";
+		reg = <0 0xee140000 0 0x100>;
+		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
+		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
+		dma-names = "tx", "rx";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	sdhi2: sd@ee160000 {
+		compatible = "renesas,sdhi-r8a7793";
+		reg = <0 0xee160000 0 0x100>;
+		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
+		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
+		dma-names = "tx", "rx";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
 	scifa0: serial@e6c40000 {
-		compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7793",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c40000 0 64>;
-		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa1: serial@e6c50000 {
-		compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7793",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c50000 0 64>;
-		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa2: serial@e6c60000 {
-		compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7793",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c60000 0 64>;
-		interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa3: serial@e6c70000 {
-		compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7793",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c70000 0 64>;
-		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa4: serial@e6c78000 {
-		compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7793",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c78000 0 64>;
-		interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa5: serial@e6c80000 {
-		compatible = "renesas,scifa-r8a7793", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7793",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c80000 0 64>;
-		interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb0: serial@e6c20000 {
-		compatible = "renesas,scifb-r8a7793", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7793",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6c20000 0 64>;
-		interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb1: serial@e6c30000 {
-		compatible = "renesas,scifb-r8a7793", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7793",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6c30000 0 64>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb2: serial@e6ce0000 {
-		compatible = "renesas,scifb-r8a7793", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7793",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6ce0000 0 64>;
-		interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif0: serial@e6e60000 {
-		compatible = "renesas,scif-r8a7793", "renesas,scif";
+		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e60000 0 64>;
-		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif1: serial@e6e68000 {
-		compatible = "renesas,scif-r8a7793", "renesas,scif";
+		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e68000 0 64>;
-		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif2: serial@e6e58000 {
-		compatible = "renesas,scif-r8a7793", "renesas,scif";
+		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e58000 0 64>;
-		interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7793_CLK_SCIF2>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif3: serial@e6ea8000 {
-		compatible = "renesas,scif-r8a7793", "renesas,scif";
+		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6ea8000 0 64>;
-		interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7793_CLK_SCIF3>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif4: serial@e6ee0000 {
-		compatible = "renesas,scif-r8a7793", "renesas,scif";
+		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6ee0000 0 64>;
-		interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7793_CLK_SCIF4>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif5: serial@e6ee8000 {
-		compatible = "renesas,scif-r8a7793", "renesas,scif";
+		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6ee8000 0 64>;
-		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7793_CLK_SCIF5>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif0: serial@e62c0000 {
-		compatible = "renesas,hscif-r8a7793", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7793",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62c0000 0 96>;
-		interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif1: serial@e62c8000 {
-		compatible = "renesas,hscif-r8a7793", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7793",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62c8000 0 96>;
-		interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif2: serial@e62d0000 {
-		compatible = "renesas,hscif-r8a7793", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7793",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62d0000 0 96>;
-		interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	ether: ethernet@ee700000 {
 		compatible = "renesas,ether-r8a7793";
 		reg = <0 0xee700000 0 0x400>;
-		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -528,11 +801,11 @@
 	qspi: spi@e6b10000 {
 		compatible = "renesas,qspi-r8a7793", "renesas,qspi";
 		reg = <0 0xe6b10000 0 0x2c>;
-		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
 		dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -544,8 +817,8 @@
 		reg = <0 0xfeb00000 0 0x40000>,
 		      <0 0xfeb90000 0 0x1c>;
 		reg-names = "du", "lvds.0";
-		interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 268 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7793_CLK_DU0>,
 			 <&mstp7_clks R8A7793_CLK_DU1>,
 			 <&mstp7_clks R8A7793_CLK_LVDS0>;
@@ -569,18 +842,82 @@
 		};
 	};
 
+	can0: can@e6e80000 {
+		compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
+		reg = <0 0xe6e80000 0 0x1000>;
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
+			 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
+		clock-names = "clkp1", "clkp2", "can_clk";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	can1: can@e6e88000 {
+		compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
+		reg = <0 0xe6e88000 0 0x1000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
+			 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
+		clock-names = "clkp1", "clkp2", "can_clk";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
 
 		/* External root clock */
-		extal_clk: extal_clk {
+		extal_clk: extal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
+		};
+
+		/*
+		 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
+		 * default. Boards that provide audio clocks should override them.
+		 */
+		audio_clk_a: audio_clk_a {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+		audio_clk_b: audio_clk_b {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+		audio_clk_c: audio_clk_c {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+		};
+
+		/* External USB clock - can be overridden by the board */
+		usb_extal_clk: usb_extal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <48000000>;
+		};
+
+		/* External CAN clock */
+		can_clk: can {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
+		};
+
+		/* External SCIF clock */
+		scif_clk: scif {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			/* This value must be overridden by the board. */
 			clock-frequency = <0>;
-			clock-output-names = "extal";
 		};
 
 		/* Special CPG clocks */
@@ -588,7 +925,7 @@
 			compatible = "renesas,r8a7793-cpg-clocks",
 				     "renesas,rcar-gen2-cpg-clocks";
 			reg = <0 0xe6150000 0 0x1000>;
-			clocks = <&extal_clk>;
+			clocks = <&extal_clk &usb_extal_clk>;
 			#clock-cells = <1>;
 			clock-output-names = "main", "pll0", "pll1", "pll3",
 					     "lb", "qspi", "sdh", "sd0", "z",
@@ -597,103 +934,98 @@
 		};
 
 		/* Variable factor clocks */
-		sd2_clk: sd2_clk@e6150078 {
+		sd2_clk: sd2@e6150078 {
 			compatible = "renesas,r8a7793-div6-clock",
 				     "renesas,cpg-div6-clock";
 			reg = <0 0xe6150078 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sd2";
 		};
-		sd3_clk: sd3_clk@e615026c {
+		sd3_clk: sd3@e615026c {
 			compatible = "renesas,r8a7793-div6-clock",
 				     "renesas,cpg-div6-clock";
 			reg = <0 0xe615026c 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sd3";
 		};
-		mmc0_clk: mmc0_clk@e6150240 {
+		mmc0_clk: mmc0@e6150240 {
 			compatible = "renesas,r8a7793-div6-clock",
 				     "renesas,cpg-div6-clock";
 			reg = <0 0xe6150240 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "mmc0";
 		};
 
 		/* Fixed factor clocks */
-		pll1_div2_clk: pll1_div2_clk {
+		pll1_div2_clk: pll1_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "pll1_div2";
 		};
-		zg_clk: zg_clk {
+		zg_clk: zg {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <5>;
 			clock-mult = <1>;
-			clock-output-names = "zg";
 		};
-		zx_clk: zx_clk {
+		zx_clk: zx {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <3>;
 			clock-mult = <1>;
-			clock-output-names = "zx";
 		};
-		zs_clk: zs_clk {
+		zs_clk: zs {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <6>;
 			clock-mult = <1>;
-			clock-output-names = "zs";
 		};
-		hp_clk: hp_clk {
+		hp_clk: hp {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <12>;
 			clock-mult = <1>;
-			clock-output-names = "hp";
 		};
-		p_clk: p_clk {
+		p_clk: p {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <24>;
 			clock-mult = <1>;
-			clock-output-names = "p";
 		};
-		rclk_clk: rclk_clk {
+		m2_clk: m2 {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+		};
+		rclk_clk: rclk {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <(48 * 1024)>;
 			clock-mult = <1>;
-			clock-output-names = "rclk";
 		};
-		mp_clk: mp_clk {
+		mp_clk: mp {
 			compatible = "fixed-factor-clock";
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
 			clock-div = <15>;
 			clock-mult = <1>;
-			clock-output-names = "mp";
 		};
-		cp_clk: cp_clk {
+		cp_clk: cp {
 			compatible = "fixed-factor-clock";
 			clocks = <&extal_clk>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "cp";
 		};
 
 		/* Gate clocks */
@@ -770,10 +1102,11 @@
 		mstp5_clks: mstp5_clks@e6150144 {
 			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
-			clocks = <&extal_clk>;
+			clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
 			#clock-cells = <1>;
-			clock-indices = <R8A7793_CLK_THERMAL>;
-			clock-output-names = "thermal";
+			clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
+					 R8A7793_CLK_THERMAL>;
+			clock-output-names = "audmac0", "audmac1", "thermal";
 		};
 		mstp7_clks: mstp7_clks@e615014c {
 			compatible = "renesas,r8a7793-mstp-clocks",
@@ -820,19 +1153,64 @@
 			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
-				 <&cpg_clocks R8A7793_CLK_QSPI>;
+				 <&p_clk>, <&p_clk>,
+				 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
+				 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+				 <&hp_clk>, <&hp_clk>;
 			#clock-cells = <1>;
 			clock-indices = <
 				R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
 				R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
 				R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
 				R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
-				R8A7793_CLK_QSPI_MOD
+				R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
+				R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
+				R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
+				R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
+				R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
 			>;
 			clock-output-names =
 				"gpio7", "gpio6", "gpio5", "gpio4",
 				"gpio3", "gpio2", "gpio1", "gpio0",
-				"qspi_mod";
+				"rcan1", "rcan0", "qspi_mod", "i2c5",
+				"i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
+				"i2c0";
+		};
+		mstp10_clks: mstp10_clks@e6150998 {
+			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+			clocks = <&p_clk>,
+				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+				<&p_clk>,
+				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
+				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
+
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7793_CLK_SSI_ALL
+				R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
+				R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
+				R8A7793_CLK_SCU_ALL
+				R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
+				R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
+				R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
+				R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
+			>;
+			clock-output-names =
+				"ssi-all",
+				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+				"scu-all",
+				"scu-dvc1", "scu-dvc0",
+				"scu-ctu1-mix1", "scu-ctu0-mix0",
+				"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
+				"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
 		};
 		mstp11_clks: mstp11_clks@e615099c {
 			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -846,11 +1224,17 @@
 		};
 	};
 
+	sysc: system-controller@e6180000 {
+		compatible = "renesas,r8a7793-sysc";
+		reg = <0 0xe6180000 0 0x0200>;
+		#power-domain-cells = <1>;
+	};
+
 	ipmmu_sy0: mmu@e6280000 {
 		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6280000 0 0x1000>;
-		interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 224 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -858,7 +1242,7 @@
 	ipmmu_sy1: mmu@e6290000 {
 		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6290000 0 0x1000>;
-		interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -866,8 +1250,8 @@
 	ipmmu_ds: mmu@e6740000 {
 		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6740000 0 0x1000>;
-		interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 199 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -875,7 +1259,7 @@
 	ipmmu_mp: mmu@ec680000 {
 		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 		reg = <0 0xec680000 0 0x1000>;
-		interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -883,8 +1267,8 @@
 	ipmmu_mx: mmu@fe951000 {
 		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 		reg = <0 0xfe951000 0 0x1000>;
-		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 221 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -892,7 +1276,7 @@
 	ipmmu_rt: mmu@ffc80000 {
 		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 		reg = <0 0xffc80000 0 0x1000>;
-		interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -900,9 +1284,166 @@
 	ipmmu_gp: mmu@e62a0000 {
 		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
 		reg = <0 0xe62a0000 0 0x1000>;
-		interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 261 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
+
+	rcar_sound: sound@ec500000 {
+		/*
+		 * #sound-dai-cells is required
+		 *
+		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+		 */
+		compatible =  "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
+		reg =	<0 0xec500000 0 0x1000>, /* SCU */
+			<0 0xec5a0000 0 0x100>,  /* ADG */
+			<0 0xec540000 0 0x1000>, /* SSIU */
+			<0 0xec541000 0 0x280>,  /* SSI */
+			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+		clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
+			<&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
+			<&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
+			<&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
+			<&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
+			<&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
+			<&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
+			<&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
+			<&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
+			<&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
+			<&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
+			<&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
+			<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
+		clock-names = "ssi-all",
+				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+				"src.9", "src.8", "src.7", "src.6", "src.5",
+				"src.4", "src.3", "src.2", "src.1", "src.0",
+				"dvc.0", "dvc.1",
+				"clk_a", "clk_b", "clk_c", "clk_i";
+		power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+
+		status = "disabled";
+
+		rcar_sound,dvc {
+			dvc0: dvc@0 {
+				dmas = <&audma0 0xbc>;
+				dma-names = "tx";
+			};
+			dvc1: dvc@1 {
+				dmas = <&audma0 0xbe>;
+				dma-names = "tx";
+			};
+		};
+
+		rcar_sound,src {
+			src0: src@0 {
+				interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x85>, <&audma1 0x9a>;
+				dma-names = "rx", "tx";
+			};
+			src1: src@1 {
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x87>, <&audma1 0x9c>;
+				dma-names = "rx", "tx";
+			};
+			src2: src@2 {
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x89>, <&audma1 0x9e>;
+				dma-names = "rx", "tx";
+			};
+			src3: src@3 {
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+				dma-names = "rx", "tx";
+			};
+			src4: src@4 {
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+				dma-names = "rx", "tx";
+			};
+			src5: src@5 {
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+				dma-names = "rx", "tx";
+			};
+			src6: src@6 {
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x91>, <&audma1 0xb4>;
+				dma-names = "rx", "tx";
+			};
+			src7: src@7 {
+				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x93>, <&audma1 0xb6>;
+				dma-names = "rx", "tx";
+			};
+			src8: src@8 {
+				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x95>, <&audma1 0xb8>;
+				dma-names = "rx", "tx";
+			};
+			src9: src@9 {
+				interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x97>, <&audma1 0xba>;
+				dma-names = "rx", "tx";
+			};
+		};
+
+		rcar_sound,ssi {
+			ssi0: ssi@0 {
+				interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+			ssi1: ssi@1 {
+				 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+			ssi2: ssi@2 {
+				interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+			ssi3: ssi@3 {
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+			ssi4: ssi@4 {
+				interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+			ssi5: ssi@5 {
+				interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+			ssi6: ssi@6 {
+				interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+			ssi7: ssi@7 {
+				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+			ssi8: ssi@8 {
+				interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+			ssi9: ssi@9 {
+				interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+				dma-names = "rx", "tx", "rxu", "txu";
+			};
+		};
+	};
 };
diff --git a/sys/gnu/dts/arm/r8a7794-alt.dts b/sys/gnu/dts/arm/r8a7794-alt.dts
index 2394e4883786..383ad791f1db 100644
--- a/sys/gnu/dts/arm/r8a7794-alt.dts
+++ b/sys/gnu/dts/arm/r8a7794-alt.dts
@@ -103,34 +103,42 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	du_pins: du {
-		renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
-		renesas,function = "du";
+		groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
+		function = "du";
 	};
 
 	scif2_pins: serial2 {
-		renesas,groups = "scif2_data";
-		renesas,function = "scif2";
+		groups = "scif2_data";
+		function = "scif2";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk";
+		function = "scif_clk";
 	};
 
 	ether_pins: ether {
-		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
-		renesas,function = "eth";
+		groups = "eth_link", "eth_mdio", "eth_rmii";
+		function = "eth";
 	};
 
 	phy1_pins: phy1 {
-		renesas,groups = "intc_irq8";
-		renesas,function = "intc";
+		groups = "intc_irq8";
+		function = "intc";
 	};
 
 	i2c1_pins: i2c1 {
-		renesas,groups = "i2c1";
-		renesas,function = "i2c1";
+		groups = "i2c1";
+		function = "i2c1";
 	};
 
 	vin0_pins: vin0 {
-		renesas,groups = "vin0_data8", "vin0_clk";
-		renesas,function = "vin0";
+		groups = "vin0_data8", "vin0_clk";
+		function = "vin0";
 	};
 };
 
@@ -138,6 +146,13 @@
 	status = "okay";
 };
 
+&pfc {
+	qspi_pins: spi0 {
+		groups = "qspi_ctrl", "qspi_data4";
+		function = "qspi";
+	};
+};
+
 &ether {
 	pinctrl-0 = <&ether_pins &phy1_pins>;
 	pinctrl-names = "default";
@@ -197,3 +212,47 @@
 
 	status = "okay";
 };
+
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
+&qspi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash@0 {
+		compatible = "spansion,s25fl512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		spi-cpol;
+		spi-cpha;
+		m25p,fast-read;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "loader";
+				reg = <0x00000000 0x00040000>;
+				read-only;
+			};
+			partition@40000 {
+				label = "system";
+				reg = <0x00040000 0x00040000>;
+				read-only;
+			};
+			partition@80000 {
+				label = "user";
+				reg = <0x00080000 0x03f80000>;
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/r8a7794-silk.dts b/sys/gnu/dts/arm/r8a7794-silk.dts
index 5153e3af25d9..56d98d5b2185 100644
--- a/sys/gnu/dts/arm/r8a7794-silk.dts
+++ b/sys/gnu/dts/arm/r8a7794-silk.dts
@@ -64,6 +64,61 @@
 		states = <3300000 1
 			  1800000 0>;
 	};
+
+	vga-encoder {
+		compatible = "adi,adv7123";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7123_in: endpoint {
+					remote-endpoint = <&du_out_rgb1>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				adv7123_out: endpoint {
+					remote-endpoint = <&vga_in>;
+				};
+			};
+		};
+	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&adv7511_out>;
+			};
+		};
+	};
+
+	vga {
+		compatible = "vga-connector";
+
+		port {
+			vga_in: endpoint {
+				remote-endpoint = <&adv7123_out>;
+			};
+		};
+	};
+
+	x2_clk: x2-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <148500000>;
+	};
+
+	x3_clk: x3-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <74250000>;
+	};
 };
 
 &extal_clk {
@@ -71,54 +126,62 @@
 };
 
 &pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
 	scif2_pins: serial2 {
-		renesas,groups = "scif2_data";
-		renesas,function = "scif2";
+		groups = "scif2_data";
+		function = "scif2";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk";
+		function = "scif_clk";
 	};
 
 	ether_pins: ether {
-		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
-		renesas,function = "eth";
+		groups = "eth_link", "eth_mdio", "eth_rmii";
+		function = "eth";
 	};
 
 	phy1_pins: phy1 {
-		renesas,groups = "intc_irq8";
-		renesas,function = "intc";
+		groups = "intc_irq8";
+		function = "intc";
 	};
 
 	i2c1_pins: i2c1 {
-		renesas,groups = "i2c1";
-		renesas,function = "i2c1";
+		groups = "i2c1";
+		function = "i2c1";
 	};
 
 	mmcif0_pins: mmcif0 {
-		renesas,groups = "mmc_data8", "mmc_ctrl";
-		renesas,function = "mmc";
+		groups = "mmc_data8", "mmc_ctrl";
+		function = "mmc";
 	};
 
 	sdhi1_pins: sd1 {
-		renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
-		renesas,function = "sdhi1";
+		groups = "sdhi1_data4", "sdhi1_ctrl";
+		function = "sdhi1";
 	};
 
 	qspi_pins: spi0 {
-		renesas,groups = "qspi_ctrl", "qspi_data4";
-		renesas,function = "qspi";
+		groups = "qspi_ctrl", "qspi_data4";
+		function = "qspi";
 	};
 
 	vin0_pins: vin0 {
-		renesas,groups = "vin0_data8", "vin0_clk";
-		renesas,function = "vin0";
+		groups = "vin0_data8", "vin0_clk";
+		function = "vin0";
 	};
 
 	usb0_pins: usb0 {
-		renesas,groups = "usb0";
-		renesas,function = "usb0";
+		groups = "usb0";
+		function = "usb0";
 	};
 
 	usb1_pins: usb1 {
-		renesas,groups = "usb1";
-		renesas,function = "usb1";
+		groups = "usb1";
+		function = "usb1";
 	};
 };
 
@@ -129,6 +192,11 @@
 	status = "okay";
 };
 
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
 &ether {
 	pinctrl-0 = <&ether_pins &phy1_pins>;
 	pinctrl-names = "default";
@@ -164,6 +232,38 @@
 			};
 		};
 	};
+
+	hdmi@39 {
+		compatible = "adi,adv7511w";
+		reg = <0x39>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+		adi,input-depth = <8>;
+		adi,input-colorspace = "rgb";
+		adi,input-clock = "1x";
+		adi,input-style = <1>;
+		adi,input-justification = "evenly";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7511_in: endpoint {
+					remote-endpoint = <&du_out_rgb0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7511_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
 };
 
 &mmcif0 {
@@ -258,3 +358,25 @@
 &usbphy {
 	status = "okay";
 };
+
+&du {
+	status = "okay";
+
+	clocks = <&mstp7_clks R8A7794_CLK_DU0>,
+		 <&mstp7_clks R8A7794_CLK_DU0>,
+		 <&x2_clk>, <&x3_clk>;
+	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+
+	ports {
+		port@0 {
+			endpoint {
+				remote-endpoint = <&adv7511_in>;
+			};
+		};
+		port@1 {
+			endpoint {
+				remote-endpoint = <&adv7123_in>;
+			};
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/r8a7794.dtsi b/sys/gnu/dts/arm/r8a7794.dtsi
index 6c78f1fae90f..f334a3a715f2 100644
--- a/sys/gnu/dts/arm/r8a7794.dtsi
+++ b/sys/gnu/dts/arm/r8a7794.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/clock/r8a7794-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7794-sysc.h>
 
 / {
 	compatible = "renesas,r8a7794";
@@ -26,6 +27,8 @@
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
 		spi0 = &qspi;
 		vin0 = &vin0;
 		vin1 = &vin1;
@@ -40,6 +43,8 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
+			next-level-cache = <&L2_CA7>;
 		};
 
 		cpu1: cpu@1 {
@@ -47,9 +52,18 @@
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clock-frequency = <1000000000>;
+			power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
+			next-level-cache = <&L2_CA7>;
 		};
 	};
 
+	L2_CA7: cache-controller@1 {
+		compatible = "cache";
+		power-domains = <&sysc R8A7794_PD_CA7_SCU>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
@@ -59,108 +73,108 @@
 			<0 0xf1002000 0 0x1000>,
 			<0 0xf1004000 0 0x2000>,
 			<0 0xf1006000 0 0x2000>;
-		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	gpio0: gpio@e6050000 {
 		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 		reg = <0 0xe6050000 0 0x50>;
-		interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 0 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 	};
 
 	gpio1: gpio@e6051000 {
 		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 		reg = <0 0xe6051000 0 0x50>;
-		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 32 26>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 	};
 
 	gpio2: gpio@e6052000 {
 		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 		reg = <0 0xe6052000 0 0x50>;
-		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 64 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 	};
 
 	gpio3: gpio@e6053000 {
 		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 		reg = <0 0xe6053000 0 0x50>;
-		interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 96 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 	};
 
 	gpio4: gpio@e6054000 {
 		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 		reg = <0 0xe6054000 0 0x50>;
-		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 128 32>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 	};
 
 	gpio5: gpio@e6055000 {
 		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 		reg = <0 0xe6055000 0 0x50>;
-		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 160 28>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 	};
 
 	gpio6: gpio@e6055400 {
 		compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
 		reg = <0 0xe6055400 0 0x50>;
-		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		gpio-ranges = <&pfc 0 192 26>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 	};
 
 	cmt0: timer@ffca0000 {
 		compatible = "renesas,cmt-48-gen2";
 		reg = <0 0xffca0000 0 0x1004>;
-		interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 
 		renesas,channels-mask = <0x60>;
 
@@ -170,17 +184,17 @@
 	cmt1: timer@e6130000 {
 		compatible = "renesas,cmt-48-gen2";
 		reg = <0 0xe6130000 0 0x1004>;
-		interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 121 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 122 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 123 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 124 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 125 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 126 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 127 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 
 		renesas,channels-mask = <0xff>;
 
@@ -189,10 +203,10 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			     <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	irqc0: interrupt-controller@e61c0000 {
@@ -200,18 +214,18 @@
 		#interrupt-cells = <2>;
 		interrupt-controller;
 		reg = <0 0xe61c0000 0 0x200>;
-		interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 3 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 12 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 13 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 14 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 15 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 16 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 	};
 
 	pfc: pin-controller@e6060000 {
@@ -222,22 +236,22 @@
 	dmac0: dma-controller@e6700000 {
 		compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 		reg = <0 0xe6700000 0 0x20000>;
-		interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
-			      0 200 IRQ_TYPE_LEVEL_HIGH
-			      0 201 IRQ_TYPE_LEVEL_HIGH
-			      0 202 IRQ_TYPE_LEVEL_HIGH
-			      0 203 IRQ_TYPE_LEVEL_HIGH
-			      0 204 IRQ_TYPE_LEVEL_HIGH
-			      0 205 IRQ_TYPE_LEVEL_HIGH
-			      0 206 IRQ_TYPE_LEVEL_HIGH
-			      0 207 IRQ_TYPE_LEVEL_HIGH
-			      0 208 IRQ_TYPE_LEVEL_HIGH
-			      0 209 IRQ_TYPE_LEVEL_HIGH
-			      0 210 IRQ_TYPE_LEVEL_HIGH
-			      0 211 IRQ_TYPE_LEVEL_HIGH
-			      0 212 IRQ_TYPE_LEVEL_HIGH
-			      0 213 IRQ_TYPE_LEVEL_HIGH
-			      0 214 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -245,7 +259,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
@@ -253,22 +267,22 @@
 	dmac1: dma-controller@e6720000 {
 		compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
 		reg = <0 0xe6720000 0 0x20000>;
-		interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
-			      0 216 IRQ_TYPE_LEVEL_HIGH
-			      0 217 IRQ_TYPE_LEVEL_HIGH
-			      0 218 IRQ_TYPE_LEVEL_HIGH
-			      0 219 IRQ_TYPE_LEVEL_HIGH
-			      0 308 IRQ_TYPE_LEVEL_HIGH
-			      0 309 IRQ_TYPE_LEVEL_HIGH
-			      0 310 IRQ_TYPE_LEVEL_HIGH
-			      0 311 IRQ_TYPE_LEVEL_HIGH
-			      0 312 IRQ_TYPE_LEVEL_HIGH
-			      0 313 IRQ_TYPE_LEVEL_HIGH
-			      0 314 IRQ_TYPE_LEVEL_HIGH
-			      0 315 IRQ_TYPE_LEVEL_HIGH
-			      0 316 IRQ_TYPE_LEVEL_HIGH
-			      0 317 IRQ_TYPE_LEVEL_HIGH
-			      0 318 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error",
 				"ch0", "ch1", "ch2", "ch3",
 				"ch4", "ch5", "ch6", "ch7",
@@ -276,246 +290,285 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 		clock-names = "fck";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
 
 	scifa0: serial@e6c40000 {
-		compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7794",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c40000 0 64>;
-		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa1: serial@e6c50000 {
-		compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7794",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c50000 0 64>;
-		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa2: serial@e6c60000 {
-		compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7794",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c60000 0 64>;
-		interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa3: serial@e6c70000 {
-		compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7794",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c70000 0 64>;
-		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa4: serial@e6c78000 {
-		compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7794",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c78000 0 64>;
-		interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifa5: serial@e6c80000 {
-		compatible = "renesas,scifa-r8a7794", "renesas,scifa";
+		compatible = "renesas,scifa-r8a7794",
+			     "renesas,rcar-gen2-scifa", "renesas,scifa";
 		reg = <0 0xe6c80000 0 64>;
-		interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb0: serial@e6c20000 {
-		compatible = "renesas,scifb-r8a7794", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7794",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6c20000 0 64>;
-		interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb1: serial@e6c30000 {
-		compatible = "renesas,scifb-r8a7794", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7794",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6c30000 0 64>;
-		interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scifb2: serial@e6ce0000 {
-		compatible = "renesas,scifb-r8a7794", "renesas,scifb";
+		compatible = "renesas,scifb-r8a7794",
+			     "renesas,rcar-gen2-scifb", "renesas,scifb";
 		reg = <0 0xe6ce0000 0 64>;
-		interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif0: serial@e6e60000 {
-		compatible = "renesas,scif-r8a7794", "renesas,scif";
+		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e60000 0 64>;
-		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7794_CLK_SCIF0>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif1: serial@e6e68000 {
-		compatible = "renesas,scif-r8a7794", "renesas,scif";
+		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e68000 0 64>;
-		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7794_CLK_SCIF1>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif2: serial@e6e58000 {
-		compatible = "renesas,scif-r8a7794", "renesas,scif";
+		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6e58000 0 64>;
-		interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7794_CLK_SCIF2>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif3: serial@e6ea8000 {
-		compatible = "renesas,scif-r8a7794", "renesas,scif";
+		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6ea8000 0 64>;
-		interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7794_CLK_SCIF3>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif4: serial@e6ee0000 {
-		compatible = "renesas,scif-r8a7794", "renesas,scif";
+		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6ee0000 0 64>;
-		interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7794_CLK_SCIF4>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	scif5: serial@e6ee8000 {
-		compatible = "renesas,scif-r8a7794", "renesas,scif";
+		compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
 		reg = <0 0xe6ee8000 0 64>;
-		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7794_CLK_SCIF5>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif0: serial@e62c0000 {
-		compatible = "renesas,hscif-r8a7794", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7794",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62c0000 0 96>;
-		interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif1: serial@e62c8000 {
-		compatible = "renesas,hscif-r8a7794", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7794",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62c8000 0 96>;
-		interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	hscif2: serial@e62d0000 {
-		compatible = "renesas,hscif-r8a7794", "renesas,hscif";
+		compatible = "renesas,hscif-r8a7794",
+			     "renesas,rcar-gen2-hscif", "renesas,hscif";
 		reg = <0 0xe62d0000 0 96>;
-		interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>;
-		clock-names = "sci_ick";
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
 		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	ether: ethernet@ee700000 {
 		compatible = "renesas,ether-r8a7794";
 		reg = <0 0xee700000 0 0x400>;
-		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
 	};
 
+	avb: ethernet@e6800000 {
+		compatible = "renesas,etheravb-r8a7794",
+			     "renesas,etheravb-rcar-gen2";
+		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	/* The memory map in the User's Manual maps the cores to bus numbers */
 	i2c0: i2c@e6508000 {
 		compatible = "renesas,i2c-r8a7794";
 		reg = <0 0xe6508000 0 0x40>;
-		interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		i2c-scl-internal-delay-ns = <6>;
@@ -525,9 +578,9 @@
 	i2c1: i2c@e6518000 {
 		compatible = "renesas,i2c-r8a7794";
 		reg = <0 0xe6518000 0 0x40>;
-		interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		i2c-scl-internal-delay-ns = <6>;
@@ -537,9 +590,9 @@
 	i2c2: i2c@e6530000 {
 		compatible = "renesas,i2c-r8a7794";
 		reg = <0 0xe6530000 0 0x40>;
-		interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		i2c-scl-internal-delay-ns = <6>;
@@ -549,9 +602,9 @@
 	i2c3: i2c@e6540000 {
 		compatible = "renesas,i2c-r8a7794";
 		reg = <0 0xe6540000 0 0x40>;
-		interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		i2c-scl-internal-delay-ns = <6>;
@@ -561,9 +614,9 @@
 	i2c4: i2c@e6520000 {
 		compatible = "renesas,i2c-r8a7794";
 		reg = <0 0xe6520000 0 0x40>;
-		interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		i2c-scl-internal-delay-ns = <6>;
@@ -573,23 +626,49 @@
 	i2c5: i2c@e6528000 {
 		compatible = "renesas,i2c-r8a7794";
 		reg = <0 0xe6528000 0 0x40>;
-		interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		i2c-scl-internal-delay-ns = <6>;
 		status = "disabled";
 	};
 
+	i2c6: i2c@e6500000 {
+		compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
+		reg = <0 0xe6500000 0 0x425>;
+		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
+		dmas = <&dmac0 0x61>, <&dmac0 0x62>;
+		dma-names = "tx", "rx";
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c7: i2c@e6510000 {
+		compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
+		reg = <0 0xe6510000 0 0x425>;
+		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
+		dmas = <&dmac0 0x65>, <&dmac0 0x66>;
+		dma-names = "tx", "rx";
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	mmcif0: mmc@ee200000 {
 		compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
 		reg = <0 0xee200000 0 0x80>;
-		interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		reg-io-width = <4>;
 		status = "disabled";
 	};
@@ -597,38 +676,38 @@
 	sdhi0: sd@ee100000 {
 		compatible = "renesas,sdhi-r8a7794";
 		reg = <0 0xee100000 0 0x200>;
-		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi1: sd@ee140000 {
 		compatible = "renesas,sdhi-r8a7794";
 		reg = <0 0xee140000 0 0x100>;
-		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	sdhi2: sd@ee160000 {
 		compatible = "renesas,sdhi-r8a7794";
 		reg = <0 0xee160000 0 0x100>;
-		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	qspi: spi@e6b10000 {
 		compatible = "renesas,qspi-r8a7794", "renesas,qspi";
 		reg = <0 0xe6b10000 0 0x2c>;
-		interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
 		dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 		dma-names = "tx", "rx";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -638,29 +717,29 @@
 	vin0: video@e6ef0000 {
 		compatible = "renesas,vin-r8a7794";
 		reg = <0 0xe6ef0000 0 0x1000>;
-		interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	vin1: video@e6ef1000 {
 		compatible = "renesas,vin-r8a7794";
 		reg = <0 0xe6ef1000 0 0x1000>;
-		interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 	};
 
 	pci0: pci@ee090000 {
-		compatible = "renesas,pci-r8a7794";
+		compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 		device_type = "pci";
 		reg = <0 0xee090000 0 0xc00>,
 		      <0 0xee080000 0 0x1100>;
-		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		bus-range = <0 0>;
@@ -669,9 +748,9 @@
 		#interrupt-cells = <1>;
 		ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
 		interrupt-map-mask = <0xff00 0 0 0x7>;
-		interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+				 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+				 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 
 		usb@0,1 {
 			reg = <0x800 0 0 0 0>;
@@ -689,13 +768,13 @@
 	};
 
 	pci1: pci@ee0d0000 {
-		compatible = "renesas,pci-r8a7794";
+		compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
 		device_type = "pci";
 		reg = <0 0xee0d0000 0 0xc00>,
 		      <0 0xee0c0000 0 0x1100>;
-		interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		bus-range = <1 1>;
@@ -704,9 +783,9 @@
 		#interrupt-cells = <1>;
 		ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
 		interrupt-map-mask = <0xff00 0 0 0x7>;
-		interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
-				 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
-				 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+				 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+				 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 
 		usb@0,1 {
 			reg = <0x800 0 0 0 0>;
@@ -724,11 +803,11 @@
 	};
 
 	hsusb: usb@e6590000 {
-		compatible = "renesas,usbhs-r8a7794";
+		compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
 		reg = <0 0xe6590000 0 0x100>;
-		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		renesas,buswait = <4>;
 		phys = <&usb0 1>;
 		phy-names = "usb";
@@ -742,7 +821,7 @@
 		#size-cells = <0>;
 		clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
 		clock-names = "usbhs";
-		power-domains = <&cpg_clocks>;
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
 		status = "disabled";
 
 		usb0: usb-channel@0 {
@@ -759,8 +838,8 @@
 		compatible = "renesas,du-r8a7794";
 		reg = <0 0xfeb00000 0 0x40000>;
 		reg-names = "du";
-		interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 268 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7794_CLK_DU0>,
 			 <&mstp7_clks R8A7794_CLK_DU0>;
 		clock-names = "du.0", "du.1";
@@ -783,18 +862,62 @@
 		};
 	};
 
+	can0: can@e6e80000 {
+		compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+		reg = <0 0xe6e80000 0 0x1000>;
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
+			 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
+		clock-names = "clkp1", "clkp2", "can_clk";
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	can1: can@e6e88000 {
+		compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+		reg = <0 0xe6e88000 0 0x1000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
+			 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
+		clock-names = "clkp1", "clkp2", "can_clk";
+		power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
 
 		/* External root clock */
-		extal_clk: extal_clk {
+		extal_clk: extal {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			/* This value must be overriden by the board. */
 			clock-frequency = <0>;
-			clock-output-names = "extal";
+		};
+
+		/* External USB clock - can be overridden by the board */
+		usb_extal_clk: usb_extal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <48000000>;
+		};
+
+		/* External CAN clock */
+		can_clk: can {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
+		};
+
+		/* External SCIF clock */
+		scif_clk: scif {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
 		};
 
 		/* Special CPG clocks */
@@ -802,180 +925,160 @@
 			compatible = "renesas,r8a7794-cpg-clocks",
 				     "renesas,rcar-gen2-cpg-clocks";
 			reg = <0 0xe6150000 0 0x1000>;
-			clocks = <&extal_clk>;
+			clocks = <&extal_clk &usb_extal_clk>;
 			#clock-cells = <1>;
 			clock-output-names = "main", "pll0", "pll1", "pll3",
-					     "lb", "qspi", "sdh", "sd0", "z";
+					     "lb", "qspi", "sdh", "sd0", "z",
+					     "rcan";
 			#power-domain-cells = <0>;
 		};
 		/* Variable factor clocks */
-		sd2_clk: sd2_clk@e6150078 {
+		sd2_clk: sd2@e6150078 {
 			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150078 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sd2";
 		};
-		sd3_clk: sd3_clk@e615026c {
+		sd3_clk: sd3@e615026c {
 			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe615026c 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sd3";
 		};
-		mmc0_clk: mmc0_clk@e6150240 {
+		mmc0_clk: mmc0@e6150240 {
 			compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0 0xe6150240 0 4>;
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "mmc0";
 		};
 
 		/* Fixed factor clocks */
-		pll1_div2_clk: pll1_div2_clk {
+		pll1_div2_clk: pll1_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "pll1_div2";
 		};
-		zg_clk: zg_clk {
+		zg_clk: zg {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <6>;
 			clock-mult = <1>;
-			clock-output-names = "zg";
 		};
-		zx_clk: zx_clk {
+		zx_clk: zx {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <3>;
 			clock-mult = <1>;
-			clock-output-names = "zx";
 		};
-		zs_clk: zs_clk {
+		zs_clk: zs {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <6>;
 			clock-mult = <1>;
-			clock-output-names = "zs";
 		};
-		hp_clk: hp_clk {
+		hp_clk: hp {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <12>;
 			clock-mult = <1>;
-			clock-output-names = "hp";
 		};
-		i_clk: i_clk {
+		i_clk: i {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "i";
 		};
-		b_clk: b_clk {
+		b_clk: b {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <12>;
 			clock-mult = <1>;
-			clock-output-names = "b";
 		};
-		p_clk: p_clk {
+		p_clk: p {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <24>;
 			clock-mult = <1>;
-			clock-output-names = "p";
 		};
-		cl_clk: cl_clk {
+		cl_clk: cl {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <48>;
 			clock-mult = <1>;
-			clock-output-names = "cl";
 		};
-		m2_clk: m2_clk {
+		m2_clk: m2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "m2";
 		};
-		rclk_clk: rclk_clk {
+		rclk_clk: rclk {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <(48 * 1024)>;
 			clock-mult = <1>;
-			clock-output-names = "rclk";
 		};
-		oscclk_clk: oscclk_clk {
+		oscclk_clk: oscclk {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <(12 * 1024)>;
 			clock-mult = <1>;
-			clock-output-names = "oscclk";
 		};
-		zb3_clk: zb3_clk {
+		zb3_clk: zb3 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 			#clock-cells = <0>;
 			clock-div = <4>;
 			clock-mult = <1>;
-			clock-output-names = "zb3";
 		};
-		zb3d2_clk: zb3d2_clk {
+		zb3d2_clk: zb3d2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "zb3d2";
 		};
-		ddr_clk: ddr_clk {
+		ddr_clk: ddr {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
 			#clock-cells = <0>;
 			clock-div = <8>;
 			clock-mult = <1>;
-			clock-output-names = "ddr";
 		};
-		mp_clk: mp_clk {
+		mp_clk: mp {
 			compatible = "fixed-factor-clock";
 			clocks = <&pll1_div2_clk>;
 			#clock-cells = <0>;
 			clock-div = <15>;
 			clock-mult = <1>;
-			clock-output-names = "mp";
 		};
-		cp_clk: cp_clk {
+		cp_clk: cp {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <48>;
 			clock-mult = <1>;
-			clock-output-names = "cp";
 		};
 
-		acp_clk: acp_clk {
+		acp_clk: acp {
 			compatible = "fixed-factor-clock";
 			clocks = <&extal_clk>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "acp";
 		};
 
 		/* Gate clocks */
@@ -1026,16 +1129,19 @@
 			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 			clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
-			         <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
+				 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
+				 <&hp_clk>, <&hp_clk>;
 			#clock-cells = <1>;
 			clock-indices = <
 			        R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
-				R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
+				R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
+				R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
 				R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
 			>;
 			clock-output-names =
 			        "sdhi2", "sdhi1", "sdhi0",
-				"mmcif0", "cmt1", "usbdmac0", "usbdmac1";
+				"mmcif0", "i2c6", "i2c7",
+				"cmt1", "usbdmac0", "usbdmac1";
 		};
 		mstp4_clks: mstp4_clks@e6150140 {
 			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1068,32 +1174,35 @@
 		mstp8_clks: mstp8_clks@e6150990 {
 			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
-			clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
+			clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
 			#clock-cells = <1>;
 			clock-indices = <
-				R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
+				R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
+				R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
 			>;
 			clock-output-names =
-				"vin1", "vin0", "ether";
+				"vin1", "vin0", "etheravb", "ether";
 		};
 		mstp9_clks: mstp9_clks@e6150994 {
 			compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
-				 <&cp_clk>, <&cp_clk>, <&cp_clk>,
-				 <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
-				 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
+				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
+				 <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
+				 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+				 <&hp_clk>, <&hp_clk>;
 			#clock-cells = <1>;
 			clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
 					 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
 					 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
-					 R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
+					 R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
+					 R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
 					 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
 					 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
 					 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
 			clock-output-names =
 				"gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
-				"gpio1", "gpio0", "qspi_mod",
+				"gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
 				"i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
 		};
 		mstp11_clks: mstp11_clks@e615099c {
@@ -1108,11 +1217,17 @@
 		};
 	};
 
+	sysc: system-controller@e6180000 {
+		compatible = "renesas,r8a7794-sysc";
+		reg = <0 0xe6180000 0 0x0200>;
+		#power-domain-cells = <1>;
+	};
+
 	ipmmu_sy0: mmu@e6280000 {
 		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6280000 0 0x1000>;
-		interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 224 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1120,7 +1235,7 @@
 	ipmmu_sy1: mmu@e6290000 {
 		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6290000 0 0x1000>;
-		interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1128,8 +1243,8 @@
 	ipmmu_ds: mmu@e6740000 {
 		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
 		reg = <0 0xe6740000 0 0x1000>;
-		interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 199 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1137,7 +1252,7 @@
 	ipmmu_mp: mmu@ec680000 {
 		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
 		reg = <0 0xec680000 0 0x1000>;
-		interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1145,8 +1260,8 @@
 	ipmmu_mx: mmu@fe951000 {
 		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
 		reg = <0 0xfe951000 0 0x1000>;
-		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 221 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
@@ -1154,8 +1269,8 @@
 	ipmmu_gp: mmu@e62a0000 {
 		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
 		reg = <0 0xe62a0000 0 0x1000>;
-		interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 261 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
 		status = "disabled";
 	};
diff --git a/sys/gnu/dts/arm/rk3036-evb.dts b/sys/gnu/dts/arm/rk3036-evb.dts
index 28a033666017..8db9e9b197a2 100644
--- a/sys/gnu/dts/arm/rk3036-evb.dts
+++ b/sys/gnu/dts/arm/rk3036-evb.dts
@@ -45,6 +45,25 @@
 / {
 	model = "Rockchip RK3036 Evaluation board";
 	compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+	phy = <&phy0>;
+	phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
+	phy-reset-duration = <10>; /* millisecond */
+
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
 };
 
 &i2c1 {
diff --git a/sys/gnu/dts/arm/rk3036-kylin.dts b/sys/gnu/dts/arm/rk3036-kylin.dts
index 992f9cadbc04..1df1557a46c3 100644
--- a/sys/gnu/dts/arm/rk3036-kylin.dts
+++ b/sys/gnu/dts/arm/rk3036-kylin.dts
@@ -46,6 +46,63 @@
 	model = "Rockchip RK3036 KylinBoard";
 	compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
 
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x20000000>;
+	};
+
+	leds: gpio-leds {
+		compatible = "gpio-leds";
+
+		work {
+			gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+			label = "kylin:red:led";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_ctl>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_wake_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - SDIO_RESET_L_WL_RST
+		 * - SDIO_RESET_L_BT_EN
+		 */
+		reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
+			      <&gpio0 27 GPIO_ACTIVE_LOW>, /* WL_RST */
+			      <&gpio2 9  GPIO_ACTIVE_LOW>; /* BT_EN */
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "rockchip,rt5616-codec";
+		simple-audio-card,mclk-fs = <512>;
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Headphone", "Headphone Jack";
+		simple-audio-card,routing =
+			"MIC1", "Microphone Jack",
+			"MIC2", "Microphone Jack",
+			"Microphone Jack", "micbias1",
+			"Headphone Jack", "HPOL",
+			"Headphone Jack", "HPOR";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rt5616>;
+		};
+	};
+
 	vcc_sys: vsys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc_sys";
@@ -60,10 +117,28 @@
 	status = "okay";
 };
 
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+	phy = <&phy0>;
+	phy-reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* PHY_RST */
+	phy-reset-duration = <10>; /* millisecond */
+
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
 &emmc {
 	status = "okay";
 };
 
+&hdmi {
+	status = "okay";
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 
@@ -257,20 +332,53 @@
 
 &i2c2 {
 	status = "okay";
+
+	rt5616: rt5616@1b {
+		compatible = "rt5616";
+		reg = <0x1b>;
+		clocks = <&cru SCLK_I2S_OUT>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+	};
+};
+
+&i2s {
+	#sound-dai-cells = <0>;
+	status = "okay";
 };
 
 &sdio {
 	status = "okay";
 
-	broken-cd;
 	bus-width = <4>;
+	cap-sd-highspeed;
 	cap-sdio-irq;
 	default-sample-phase = <90>;
 	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
 	non-removable;
 	num-slots = <1>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+};
+
+&uart0 {
+	status = "okay";
 };
 
 &uart2 {
@@ -285,13 +393,39 @@
 	status = "okay";
 };
 
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
 &pinctrl {
+	leds {
+		led_ctl: led-ctl {
+			rockchip,pins = <2 30 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	pmic {
 		pmic_int: pmic-int {
 			rockchip,pins = <2 2 RK_FUNC_GPIO &pcfg_pull_default>;
 		};
 	};
 
+	sdio {
+		bt_wake_h: bt-wake-h {
+			rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_default>;
+		};
+	};
+
+	sdmmc {
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	sleep {
 		global_pwroff: global-pwroff {
 			rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>;
diff --git a/sys/gnu/dts/arm/rk3036.dtsi b/sys/gnu/dts/arm/rk3036.dtsi
index b9567c1e0687..843d2be2e4e9 100644
--- a/sys/gnu/dts/arm/rk3036.dtsi
+++ b/sys/gnu/dts/arm/rk3036.dtsi
@@ -60,11 +60,7 @@
 		serial0 = &uart0;
 		serial1 = &uart1;
 		serial2 = &uart2;
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x60000000 0x40000000>;
+		spi = &spi;
 	};
 
 	cpus {
@@ -94,7 +90,7 @@
 	};
 
 	amba {
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
@@ -105,6 +101,7 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
+			arm,pl330-broken-no-flushp;
 			clocks = <&cru ACLK_DMAC2>;
 			clock-names = "apb_pclk";
 		};
@@ -117,6 +114,11 @@
 		interrupt-affinity = <&cpu0>, <&cpu1>;
 	};
 
+	display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <&vop_out>;
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		arm,cpu-registers-not-fw-configured;
@@ -147,6 +149,36 @@
 		};
 	};
 
+	vop: vop@10118000 {
+		compatible = "rockchip,rk3036-vop";
+		reg = <0x10118000 0x19c>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
+		reset-names = "axi", "ahb", "dclk";
+		iommus = <&vop_mmu>;
+		status = "disabled";
+
+		vop_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vop_out_hdmi: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&hdmi_in_vop>;
+			};
+		};
+	};
+
+	vop_mmu: iommu@10118300 {
+		compatible = "rockchip,iommu";
+		reg = <0x10118300 0x100>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vop_mmu";
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@10139000 {
 		compatible = "arm,gic-400";
 		interrupt-controller;
@@ -161,7 +193,7 @@
 	};
 
 	usb_otg: usb@10180000 {
-		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+		compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 				"snps,dwc2";
 		reg = <0x10180000 0x40000>;
 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -176,7 +208,7 @@
 	};
 
 	usb_host: usb@101c0000 {
-		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+		compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
 				"snps,dwc2";
 		reg = <0x101c0000 0x40000>;
 		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -186,6 +218,27 @@
 		status = "disabled";
 	};
 
+	emac: ethernet@10200000 {
+		compatible = "rockchip,rk3036-emac", "snps,arc-emac";
+		reg = <0x10200000 0x4000>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		rockchip,grf = <&grf>;
+		clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
+		clock-names = "hclk", "macref", "macclk";
+		/*
+		 * Fix the emac parent clock is DPLL instead of APLL.
+		 * since that will cause some unstable things if the cpufreq
+		 * is working. (e.g: the accurate 50MHz what mac_ref need)
+		 */
+		assigned-clocks = <&cru SCLK_MACPLL>;
+		assigned-clock-parents = <&cru PLL_DPLL>;
+		max-speed = <100>;
+		phy-mode = "rmii";
+		status = "disabled";
+	};
+
 	sdmmc: dwmmc@10214000 {
 		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x10214000 0x4000>;
@@ -211,10 +264,9 @@
 	};
 
 	emmc: dwmmc@1021c000 {
-		compatible = "rockchip,rk3288-dw-mshc";
+		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x1021c000 0x4000>;
 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-		broken-cd;
 		bus-width = <8>;
 		cap-mmc-highspeed;
 		clock-frequency = <37500000>;
@@ -241,8 +293,8 @@
 		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clock-names = "i2s_hclk", "i2s_clk";
-		clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
+		clock-names = "i2s_clk", "i2s_hclk";
+		clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
 		dmas = <&pdma 0>, <&pdma 1>;
 		dma-names = "tx", "rx";
 		pinctrl-names = "default";
@@ -274,6 +326,27 @@
 		status = "disabled";
 	};
 
+	hdmi: hdmi@20034000 {
+		compatible = "rockchip,rk3036-inno-hdmi";
+		reg = <0x20034000 0x4000>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru  PCLK_HDMI>;
+		clock-names = "pclk";
+		rockchip,grf = <&grf>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmi_ctl>;
+		status = "disabled";
+
+		hdmi_in: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			hdmi_in_vop: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&vop_out_hdmi>;
+			};
+		};
+	};
+
 	timer: timer@20044000 {
 		compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
 		reg = <0x20044000 0x20>;
@@ -327,7 +400,7 @@
 	};
 
 	i2c1: i2c@20056000 {
-		compatible = "rockchip,rk3288-i2c";
+		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 		reg = <0x20056000 0x1000>;
 		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
@@ -340,7 +413,7 @@
 	};
 
 	i2c2: i2c@2005a000 {
-		compatible = "rockchip,rk3288-i2c";
+		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 		reg = <0x2005a000 0x1000>;
 		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
@@ -395,7 +468,7 @@
 	};
 
 	i2c0: i2c@20072000 {
-		compatible = "rockchip,rk3288-i2c";
+		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
 		reg = <0x20072000 0x1000>;
 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
@@ -407,6 +480,21 @@
 		status = "disabled";
 	};
 
+	spi: spi@20074000 {
+		compatible = "rockchip,rockchip-spi";
+		reg = <0x20074000 0x1000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
+		clock-names = "apb-pclk","spi_pclk";
+		dmas = <&pdma 8>, <&pdma 9>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3036-pinctrl";
 		rockchip,grf = <&grf>;
@@ -556,6 +644,24 @@
 			};
 		};
 
+		emac {
+			emac_xfer: emac-xfer {
+				rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
+						<2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
+						<2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
+						<2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
+						<2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
+						<2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
+						<2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
+						<2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
+			};
+
+			emac_mdio: emac-mdio {
+				rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
+						<2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
+			};
+		};
+
 		i2c0 {
 			i2c0_xfer: i2c0-xfer {
 				rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
@@ -579,12 +685,21 @@
 
 		i2s {
 			i2s_bus: i2s-bus {
-				rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>,
-						<1 1 RK_FUNC_1 &pcfg_pull_none>,
-						<1 2 RK_FUNC_1 &pcfg_pull_none>,
-						<1 3 RK_FUNC_1 &pcfg_pull_none>,
-						<1 4 RK_FUNC_1 &pcfg_pull_none>,
-						<1 5 RK_FUNC_1 &pcfg_pull_none>;
+				rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
+						<1 1 RK_FUNC_1 &pcfg_pull_default>,
+						<1 2 RK_FUNC_1 &pcfg_pull_default>,
+						<1 3 RK_FUNC_1 &pcfg_pull_default>,
+						<1 4 RK_FUNC_1 &pcfg_pull_default>,
+						<1 5 RK_FUNC_1 &pcfg_pull_default>;
+			};
+		};
+
+		hdmi {
+			hdmi_ctl: hdmi-ctl {
+				rockchip,pins = <1 8  RK_FUNC_1 &pcfg_pull_none>,
+						<1 9  RK_FUNC_1 &pcfg_pull_none>,
+						<1 10 RK_FUNC_1 &pcfg_pull_none>,
+						<1 11 RK_FUNC_1 &pcfg_pull_none>;
 			};
 		};
 
@@ -618,5 +733,29 @@
 			};
 			/* no rts / cts for uart2 */
 		};
+
+		spi {
+			spi_txd:spi-txd {
+				rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
+			};
+
+			spi_rxd:spi-rxd {
+				rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
+			};
+
+			spi_clk:spi-clk {
+				rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
+			};
+
+			spi_cs0:spi-cs0 {
+				rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
+
+			};
+
+			spi_cs1:spi-cs1 {
+				rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
+
+			};
+		};
 	};
 };
diff --git a/sys/gnu/dts/arm/rk3066a-bqcurie2.dts b/sys/gnu/dts/arm/rk3066a-bqcurie2.dts
index 38c91a839795..bc674ee206ec 100644
--- a/sys/gnu/dts/arm/rk3066a-bqcurie2.dts
+++ b/sys/gnu/dts/arm/rk3066a-bqcurie2.dts
@@ -42,6 +42,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/input/input.h>
 #include "rk3066a.dtsi"
 
 / {
@@ -53,6 +54,18 @@
 		reg = <0x60000000 0x40000000>;
 	};
 
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm3 0 1000>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		voltage-table = <1000000 100>,
+				<1200000 42>;
+		status = "okay";
+	};
+
 	vcc_sd0: fixed-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "sdmmc-supply";
@@ -65,24 +78,21 @@
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		autorepeat;
 
-		button@0 {
+		power {
 			gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
-			linux,code = <116>;
+			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
 			linux,input-type = <1>;
-			gpio-key,wakeup = <1>;
+			wakeup-source;
 			debounce-interval = <100>;
 		};
-		button@1 {
+		volume-down {
 			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
-			linux,code = <104>;
+			linux,code = <KEY_VOLUMEDOWN>;
 			label = "GPIO Key Vol-";
 			linux,input-type = <1>;
-			gpio-key,wakeup = <0>;
 			debounce-interval = <100>;
 		};
 		/* VOL+ comes somehow thru the ADC */
@@ -203,6 +213,10 @@
 	disable-wp;
 };
 
+&pwm3 {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/rk3066a-marsboard.dts b/sys/gnu/dts/arm/rk3066a-marsboard.dts
index 7cdc308bfac5..a2b763e949b4 100644
--- a/sys/gnu/dts/arm/rk3066a-marsboard.dts
+++ b/sys/gnu/dts/arm/rk3066a-marsboard.dts
@@ -52,6 +52,18 @@
 		reg = <0x60000000 0x40000000>;
 	};
 
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm3 0 1000>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		voltage-table = <1000000 100>,
+				<1200000 42>;
+		status = "okay";
+	};
+
 	vcc_sd0: sdmmc-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "sdmmc-supply";
@@ -194,6 +206,10 @@
 	};
 };
 
+&pwm3 {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/rk3066a-rayeager.dts b/sys/gnu/dts/arm/rk3066a-rayeager.dts
index 341c1f87936a..6e7f2187a0e3 100644
--- a/sys/gnu/dts/arm/rk3066a-rayeager.dts
+++ b/sys/gnu/dts/arm/rk3066a-rayeager.dts
@@ -41,6 +41,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/input/input.h>
 #include "rk3066a.dtsi"
 
 / {
@@ -61,19 +62,29 @@
 
 	keys: gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		button@0 {
-			gpio-key,wakeup = <1>;
+		power {
+			wakeup-source;
 			gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
-			linux,code = <116>;
+			linux,code = <KEY_POWER>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pwr_key>;
 		};
 	};
 
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm3 0 1000>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		voltage-table = <1000000 100>,
+				<1200000 42>;
+		status = "okay";
+	};
+
 	vsys: vsys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vsys";
@@ -170,7 +181,6 @@
 };
 
 &emmc {
-	broken-cd;
 	bus-width = <8>;
 	cap-mmc-highspeed;
 	disable-wp;
@@ -336,7 +346,6 @@
 };
 
 &mmc1 {
-	broken-cd;
 	bus-width = <4>;
 	disable-wp;
 	non-removable;
@@ -431,6 +440,10 @@
 	status = "okay";
 };
 
+&pwm3 {
+	status = "okay";
+};
+
 &saradc {
 	vref-supply = <&vcc_25>;
 	status = "okay";
diff --git a/sys/gnu/dts/arm/rk3066a.dtsi b/sys/gnu/dts/arm/rk3066a.dtsi
index 58bac5053858..c0ba86c3a2ab 100644
--- a/sys/gnu/dts/arm/rk3066a.dtsi
+++ b/sys/gnu/dts/arm/rk3066a.dtsi
@@ -61,11 +61,13 @@
 			reg = <0x0>;
 			operating-points = <
 				/* kHz    uV */
-				1008000 1075000
-				 816000 1025000
-				 600000 1025000
-				 504000 1000000
-				 312000  975000
+				1416000 1300000
+				1200000 1175000
+				1008000 1125000
+				816000  1125000
+				600000  1100000
+				504000  1100000
+				312000  1075000
 			>;
 			clock-latency = <40000>;
 			clocks = <&cru ARMCLK>;
@@ -167,7 +169,7 @@
 		clocks = <&cru PCLK_EFUSE>;
 		clock-names = "pclk_efuse";
 
-		cpu_leakage: cpu_leakage {
+		cpu_leakage: cpu_leakage@17 {
 			reg = <0x17 0x1>;
 		};
 	};
@@ -188,6 +190,16 @@
 		clock-names = "timer", "pclk";
 	};
 
+	tsadc: tsadc@20060000 {
+		compatible = "rockchip,rk3066-tsadc";
+		reg = <0x20060000 0x100>;
+		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+		clock-names = "saradc", "apb_pclk";
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		#io-channel-cells = <1>;
+		status = "disabled";
+	};
+
 	usbphy: phy {
 		compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
 		rockchip,grf = <&grf>;
@@ -195,18 +207,20 @@
 		#size-cells = <0>;
 		status = "disabled";
 
-		usbphy0: usb-phy0 {
+		usbphy0: usb-phy@17c {
 			#phy-cells = <0>;
 			reg = <0x17c>;
 			clocks = <&cru SCLK_OTGPHY0>;
 			clock-names = "phyclk";
+			#clock-cells = <0>;
 		};
 
-		usbphy1: usb-phy1 {
+		usbphy1: usb-phy@188 {
 			#phy-cells = <0>;
 			reg = <0x188>;
 			clocks = <&cru SCLK_OTGPHY1>;
 			clock-names = "phyclk";
+			#clock-cells = <0>;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/rk3188-radxarock.dts b/sys/gnu/dts/arm/rk3188-radxarock.dts
index 66fa87d1e2c2..1da46d138029 100644
--- a/sys/gnu/dts/arm/rk3188-radxarock.dts
+++ b/sys/gnu/dts/arm/rk3188-radxarock.dts
@@ -41,6 +41,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/input/input.h>
 #include "rk3188.dtsi"
 
 / {
@@ -54,16 +55,14 @@
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		autorepeat;
 
-		button@0 {
+		power {
 			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
-			linux,code = <116>;
+			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
 			linux,input-type = <1>;
-			gpio-key,wakeup = <1>;
+			wakeup-source;
 			debounce-interval = <100>;
 		};
 	};
diff --git a/sys/gnu/dts/arm/rk3188.dtsi b/sys/gnu/dts/arm/rk3188.dtsi
index 348d46b7ada5..31f81b265cef 100644
--- a/sys/gnu/dts/arm/rk3188.dtsi
+++ b/sys/gnu/dts/arm/rk3188.dtsi
@@ -154,7 +154,7 @@
 		clocks = <&cru PCLK_EFUSE>;
 		clock-names = "pclk_efuse";
 
-		cpu_leakage: cpu_leakage {
+		cpu_leakage: cpu_leakage@17 {
 			reg = <0x17 0x1>;
 		};
 	};
@@ -166,18 +166,20 @@
 		#size-cells = <0>;
 		status = "disabled";
 
-		usbphy0: usb-phy0 {
+		usbphy0: usb-phy@10c {
 			#phy-cells = <0>;
 			reg = <0x10c>;
 			clocks = <&cru SCLK_OTGPHY0>;
 			clock-names = "phyclk";
+			#clock-cells = <0>;
 		};
 
-		usbphy1: usb-phy1 {
+		usbphy1: usb-phy@11c {
 			#phy-cells = <0>;
 			reg = <0x11c>;
 			clocks = <&cru SCLK_OTGPHY1>;
 			clock-names = "phyclk";
+			#clock-cells = <0>;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/rk3228-evb.dts b/sys/gnu/dts/arm/rk3228-evb.dts
index e3898b810150..5956e8246abe 100644
--- a/sys/gnu/dts/arm/rk3228-evb.dts
+++ b/sys/gnu/dts/arm/rk3228-evb.dts
@@ -53,7 +53,6 @@
 };
 
 &emmc {
-	broken-cd;
 	cap-mmc-highspeed;
 	mmc-ddr-1_8v;
 	disable-wp;
@@ -61,6 +60,13 @@
 	status = "okay";
 };
 
+&tsadc {
+	status = "okay";
+
+	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+};
+
 &uart2 {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/rk3228.dtsi b/sys/gnu/dts/arm/rk3228.dtsi
index 119ff12ab440..e23a22e29155 100644
--- a/sys/gnu/dts/arm/rk3228.dtsi
+++ b/sys/gnu/dts/arm/rk3228.dtsi
@@ -43,6 +43,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3228-cru.h>
+#include <dt-bindings/thermal/thermal.h>
 #include "skeleton.dtsi"
 
 / {
@@ -69,6 +70,7 @@
 				/* KHz    uV */
 				 816000 1000000
 			>;
+			#cooling-cells = <2>; /* min followed by max */
 			clock-latency = <40000>;
 			clocks = <&cru ARMCLK>;
 		};
@@ -96,7 +98,7 @@
 	};
 
 	amba {
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
@@ -185,6 +187,58 @@
 		status = "disabled";
 	};
 
+	i2c0: i2c@11050000 {
+		compatible = "rockchip,rk3228-i2c";
+		reg = <0x11050000 0x1000>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "i2c";
+		clocks = <&cru PCLK_I2C0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c0_xfer>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@11060000 {
+		compatible = "rockchip,rk3228-i2c";
+		reg = <0x11060000 0x1000>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "i2c";
+		clocks = <&cru PCLK_I2C1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c1_xfer>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@11070000 {
+		compatible = "rockchip,rk3228-i2c";
+		reg = <0x11070000 0x1000>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "i2c";
+		clocks = <&cru PCLK_I2C2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c2_xfer>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@11080000 {
+		compatible = "rockchip,rk3228-i2c";
+		reg = <0x11080000 0x1000>;
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "i2c";
+		clocks = <&cru PCLK_I2C3>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c3_xfer>;
+		status = "disabled";
+	};
+
 	pwm0: pwm@110b0000 {
 		compatible = "rockchip,rk3288-pwm";
 		reg = <0x110b0000 0x10>;
@@ -247,6 +301,63 @@
 		assigned-clock-rates = <594000000>;
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <100>; /* milliseconds */
+			polling-delay = <5000>; /* milliseconds */
+
+			thermal-sensors = <&tsadc 0>;
+
+			trips {
+				cpu_alert0: cpu_alert0 {
+					temperature = <70000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+				cpu_alert1: cpu_alert1 {
+					temperature = <75000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+				cpu_crit: cpu_crit {
+					temperature = <90000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT 6>;
+				};
+				map1 {
+					trip = <&cpu_alert1>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	tsadc: tsadc@11150000 {
+		compatible = "rockchip,rk3228-tsadc";
+		reg = <0x11150000 0x100>;
+		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+		clock-names = "tsadc", "apb_pclk";
+		resets = <&cru SRST_TSADC>;
+		reset-names = "tsadc-apb";
+		pinctrl-names = "init", "default", "sleep";
+		pinctrl-0 = <&otp_gpio>;
+		pinctrl-1 = <&otp_out>;
+		pinctrl-2 = <&otp_gpio>;
+		#thermal-sensor-cells = <0>;
+		rockchip,hw-tshut-temp = <95000>;
+		status = "disabled";
+	};
+
 	emmc: dwmmc@30020000 {
 		compatible = "rockchip,rk3288-dw-mshc";
 		reg = <0x30020000 0x4000>;
@@ -370,6 +481,34 @@
 			};
 		};
 
+		i2c0 {
+			i2c0_xfer: i2c0-xfer {
+				rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
+						<0 1 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		i2c1 {
+			i2c1_xfer: i2c1-xfer {
+				rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
+						<0 3 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		i2c2 {
+			i2c2_xfer: i2c2-xfer {
+				rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
+						<2 21 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		i2c3 {
+			i2c3_xfer: i2c3-xfer {
+				rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
+						<0 7 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
 		pwm0 {
 			pwm0_pin: pwm0-pin {
 				rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
@@ -394,6 +533,16 @@
 			};
 		};
 
+		tsadc {
+			otp_gpio: otp-gpio {
+				rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
+			otp_out: otp-out {
+				rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
 		uart0 {
 			uart0_xfer: uart0-xfer {
 				rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
diff --git a/sys/gnu/dts/arm/rk3288-evb.dtsi b/sys/gnu/dts/arm/rk3288-evb.dtsi
index 4faabdb65868..963365d12208 100644
--- a/sys/gnu/dts/arm/rk3288-evb.dtsi
+++ b/sys/gnu/dts/arm/rk3288-evb.dtsi
@@ -38,6 +38,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/pwm/pwm.h>
 #include "rk3288.dtsi"
 
@@ -98,19 +99,17 @@
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		autorepeat;
 
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		button@0 {
+		power {
 			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
-			linux,code = <116>;
+			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
 			linux,input-type = <1>;
-			gpio-key,wakeup = <1>;
+			wakeup-source;
 			debounce-interval = <100>;
 		};
 	};
@@ -172,7 +171,6 @@
 };
 
 &emmc {
-	broken-cd;
 	bus-width = <8>;
 	cap-mmc-highspeed;
 	disable-wp;
diff --git a/sys/gnu/dts/arm/rk3288-firefly.dtsi b/sys/gnu/dts/arm/rk3288-firefly.dtsi
index 4e3fd9aefe34..d6cf9ada13c9 100644
--- a/sys/gnu/dts/arm/rk3288-firefly.dtsi
+++ b/sys/gnu/dts/arm/rk3288-firefly.dtsi
@@ -40,6 +40,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/input/input.h>
 #include "rk3288.dtsi"
 
 / {
@@ -87,14 +88,12 @@
 
 	keys: gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
-		button@0 {
-			gpio-key,wakeup = <1>;
+		power {
+			wakeup-source;
 			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 			label = "GPIO Power";
-			linux,code = <116>;
+			linux,code = <KEY_POWER>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pwr_key>;
 		};
@@ -208,7 +207,6 @@
 };
 
 &emmc {
-	broken-cd;
 	bus-width = <8>;
 	cap-mmc-highspeed;
 	disable-wp;
@@ -408,6 +406,11 @@
 		output-low;
 	};
 
+	pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
+		bias-pull-up;
+		drive-strength = <12>;
+	};
+
 	act8846 {
 		pwr_hold: pwr-hold {
 			rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>;
@@ -457,6 +460,25 @@
 	};
 
 	sdmmc {
+		/*
+		 * Default drive strength isn't enough to achieve even
+		 * high-speed mode on firefly board so bump up to 12ma.
+		 */
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+					<6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+					<6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+					<6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+		};
+
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+		};
+
 		sdmmc_pwr: sdmmc-pwr {
 			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
@@ -485,7 +507,6 @@
 };
 
 &sdio0 {
-	broken-cd;
 	bus-width = <4>;
 	disable-wp;
 	non-removable;
diff --git a/sys/gnu/dts/arm/rk3288-miqi.dts b/sys/gnu/dts/arm/rk3288-miqi.dts
new file mode 100644
index 000000000000..8643103d8cd8
--- /dev/null
+++ b/sys/gnu/dts/arm/rk3288-miqi.dts
@@ -0,0 +1,472 @@
+/*
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "rk3288.dtsi"
+
+/ {
+	model = "mqmaker MiQi";
+	compatible = "mqmaker,miqi", "rockchip,rk3288";
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000>;
+	};
+
+	ext_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+	};
+
+	io_domains: io-domains {
+		compatible = "rockchip,rk3288-io-voltage-domain";
+
+		audio-supply = <&vcca_33>;
+		flash0-supply = <&vcc_flash>;
+		flash1-supply = <&vcc_lan>;
+		gpio30-supply = <&vcc_io>;
+		gpio1830-supply = <&vcc_io>;
+		lcdc-supply = <&vcc_io>;
+		sdcard-supply = <&vccio_sd>;
+		wifi-supply = <&vcc_18>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		work {
+			gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+			label = "miqi:green:user";
+			linux,default-trigger = "default-on";
+			pinctrl-names = "default";
+			pinctrl-0 = <&led_ctl>;
+		};
+	};
+
+	vcc_flash: flash-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_flash";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_host: usb-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_sd: sdmmc-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwr>;
+		regulator-name = "vcc_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		vin-supply = <&vcc_io>;
+	};
+
+	vcc_sys: vsys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&cpu0 {
+	cpu0-supply = <&vdd_cpu>;
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_flash>;
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 1000000>;
+	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	status = "ok";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c5>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	vdd_cpu: syr827@40 {
+		compatible = "silergy,syr827";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x40>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-enable-ramp-delay = <300>;
+		regulator-ramp-delay = <8000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_gpu: syr828@41 {
+		compatible = "silergy,syr828";
+		fcs,suspend-voltage-selector = <1>;
+		reg = <0x41>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <1350000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+	};
+
+	act8846: act8846@5a {
+		compatible = "active-semi,act8846";
+		reg = <0x5a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_vsel>;
+		system-power-controller;
+
+		vp1-supply = <&vcc_sys>;
+		vp2-supply = <&vcc_sys>;
+		vp3-supply = <&vcc_sys>;
+		vp4-supply = <&vcc_sys>;
+		inl1-supply = <&vcc_sys>;
+		inl2-supply = <&vcc_sys>;
+		inl3-supply = <&vcc_20>;
+
+		regulators {
+			vcc_ddr: REG1 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+			};
+
+			vcc_io: REG2 {
+				regulator-name = "vcc_io";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vdd_log: REG3 {
+				regulator-name = "vdd_log";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			vcc_20: REG4 {
+				regulator-name = "vcc_20";
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-always-on;
+			};
+
+			vccio_sd: REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vdd10_lcd: REG6 {
+				regulator-name = "vdd10_lcd";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			vcca_18: REG7 {
+				regulator-name = "vcca_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			vcca_33: REG8 {
+				regulator-name = "vcca_33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vcc_lan: REG9 {
+				regulator-name = "vcc_lan";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vdd_10: REG10 {
+				regulator-name = "vdd_10";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+			};
+
+			vcc_18: REG11 {
+				regulator-name = "vcc_18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			vcc18_lcd: REG12 {
+				regulator-name = "vcc18_lcd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&pinctrl {
+	pcfg_output_high: pcfg-output-high {
+		output-high;
+	};
+
+	pcfg_output_low: pcfg-output-low {
+		output-low;
+	};
+
+	pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
+		bias-pull-up;
+		drive-strength = <12>;
+	};
+
+	act8846 {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		pmic_sleep: pmic-sleep {
+			rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+
+		pmic_vsel: pmic-vsel {
+			rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+	};
+
+	gmac {
+		phy_int: phy-int {
+			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_pmeb: phy-pmeb {
+			rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		phy_rst: phy-rst {
+			rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	leds {
+		led_ctl: led-ctl {
+			rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdmmc {
+		/*
+		 * Default drive strength isn't enough to achieve even
+		 * high-speed mode on firefly board so bump up to 12ma.
+		 */
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+					<6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+					<6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>,
+					<6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+		};
+
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>;
+		};
+
+		sdmmc_pwr: sdmmc-pwr {
+			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb_host {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&vcc_18>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	disable-wp;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
+
+&usb_host1 {
+	status = "okay";
+};
+
+&usb_otg {
+	/*
+	 * The otg controller is the only system power source,
+	 * so needs to always stay in device mode.
+	 */
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/rk3288-popmetal.dts b/sys/gnu/dts/arm/rk3288-popmetal.dts
index 65c475642d5a..720717bb3614 100644
--- a/sys/gnu/dts/arm/rk3288-popmetal.dts
+++ b/sys/gnu/dts/arm/rk3288-popmetal.dts
@@ -41,7 +41,7 @@
  */
 
 /dts-v1/;
-
+#include <dt-bindings/input/input.h>
 #include "rk3288.dtsi"
 
 / {
@@ -62,19 +62,17 @@
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		autorepeat;
 
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		button@0 {
+		power {
 			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
-			linux,code = <116>;
+			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
 			linux,input-type = <1>;
-			gpio-key,wakeup = <1>;
+			wakeup-source;
 			debounce-interval = <100>;
 		};
 	};
@@ -162,7 +160,6 @@
 };
 
 &emmc {
-	broken-cd;
 	bus-width = <8>;
 	cap-mmc-highspeed;
 	disable-wp;
diff --git a/sys/gnu/dts/arm/rk3288-r89.dts b/sys/gnu/dts/arm/rk3288-r89.dts
index 17f13c73fe5e..4b8a8adb243c 100644
--- a/sys/gnu/dts/arm/rk3288-r89.dts
+++ b/sys/gnu/dts/arm/rk3288-r89.dts
@@ -41,6 +41,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/pwm/pwm.h>
 #include "rk3288.dtsi"
 
@@ -61,19 +62,17 @@
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		autorepeat;
 
 		pinctrl-names = "default";
 		pinctrl-0 = <&pwrbtn>;
 
-		button@0 {
+		power {
 			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
-			linux,code = <116>;
+			linux,code = <KEY_POWER>;
 			label = "GPIO Key Power";
 			linux,input-type = <1>;
-			gpio-key,wakeup = <1>;
+			wakeup-source;
 			debounce-interval = <100>;
 		};
 	};
diff --git a/sys/gnu/dts/arm/rk3288-rock2-som.dtsi b/sys/gnu/dts/arm/rk3288-rock2-som.dtsi
index 1ece66f3e162..e1ee9f949035 100644
--- a/sys/gnu/dts/arm/rk3288-rock2-som.dtsi
+++ b/sys/gnu/dts/arm/rk3288-rock2-som.dtsi
@@ -61,6 +61,31 @@
 		clock-output-names = "ext_gmac";
 	};
 
+	io_domains: io-domains {
+		compatible = "rockchip,rk3288-io-voltage-domain";
+		rockchip,grf = <&grf>;
+
+		audio-supply = <&vcc_io>;
+		bb-supply = <&vcc_io>;
+		dvp-supply = <&vcc_18>;
+		flash0-supply = <&vcc_flash>;
+		flash1-supply = <&vccio_pmu>;
+		gpio30-supply = <&vccio_pmu>;
+		gpio1830 = <&vcc_io>;
+		lcdc-supply = <&vcc_io>;
+		sdcard-supply = <&vccio_sd>;
+		wifi-supply = <&vcc_18>;
+	};
+
+	vcc_flash: flash-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		startup-delay-us = <150>;
+		vin-supply = <&vcc_io>;
+	};
+
 	vcc_sys: vsys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc_sys";
@@ -85,6 +110,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_flash>;
 	status = "okay";
 };
 
diff --git a/sys/gnu/dts/arm/rk3288-rock2-square.dts b/sys/gnu/dts/arm/rk3288-rock2-square.dts
index c5453a0b07fc..dd3ad2e93a6d 100644
--- a/sys/gnu/dts/arm/rk3288-rock2-square.dts
+++ b/sys/gnu/dts/arm/rk3288-rock2-square.dts
@@ -49,6 +49,22 @@
 		stdout-path = "serial2:115200n8";
 	};
 
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		heartbeat {
+			gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+			label = "rock2:green:state1";
+			linux,default-trigger = "heartbeat";
+		};
+
+		mmc {
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+			label = "rock2:blue:state2";
+			linux,default-trigger = "mmc0";
+		};
+	};
+
 	ir: ir-receiver {
 		compatible = "gpio-ir-receiver";
 		gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
@@ -70,6 +86,15 @@
 		#sound-dai-cells = <0>;
 	};
 
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&hym8563>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable>;
+		reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+	};
+
 	vcc_usb_host: vcc-host-regulator {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -95,6 +120,21 @@
 	};
 };
 
+&sdio0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	disable-wp;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	num-slots = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>;
+	vmmc-supply = <&vcc_io>;
+	vqmmc-supply = <&vcc_18>;
+	status = "okay";
+};
+
 &sdmmc {
 	bus-width = <4>;
 	cap-mmc-highspeed;
@@ -119,7 +159,7 @@
 };
 
 &i2c0 {
-	hym8563@51 {
+	hym8563: hym8563@51 {
 		compatible = "haoyu,hym8563";
 		reg = <0x51>;
 		#clock-cells = <0>;
@@ -161,6 +201,12 @@
 			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
+
+	sdio {
+		wifi_enable: wifi-enable {
+			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &spdif {
diff --git a/sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi b/sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi
index 136d650dd05f..2958c36d12a0 100644
--- a/sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi
+++ b/sys/gnu/dts/arm/rk3288-veyron-chromebook.dtsi
@@ -54,6 +54,50 @@
 		i2c20 = &i2c_tunnel;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		brightness-levels = <
+			  0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+		default-brightness-level = <128>;
+		enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+		backlight-boot-off;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bl_en>;
+		pwms = <&pwm0 0 1000000 0>;
+		pwm-delay-us = <10000>;
+	};
+
 	gpio-charger {
 		compatible = "gpio-charger";
 		charger-type = "mains";
@@ -62,6 +106,21 @@
 		pinctrl-0 = <&ac_present_ap>;
 	};
 
+	panel: panel {
+		compatible ="innolux,n116bge", "simple-panel";
+		status = "okay";
+		power-supply = <&vcc33_lcd>;
+		backlight = <&backlight>;
+
+		ports {
+			panel_in: port {
+				panel_in_edp: endpoint {
+					remote-endpoint = <&edp_out_panel>;
+				};
+			};
+		};
+	};
+
 	/* A non-regulated voltage from power supply or battery */
 	vccsys: vccsys {
 		compatible = "regulator-fixed";
@@ -103,18 +162,45 @@
 	};
 };
 
+&edp {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&edp_hpd>;
+
+	ports {
+		edp_out: port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			edp_out_panel: endpoint {
+				reg = <0>;
+				remote-endpoint = <&panel_in_edp>;
+			};
+		};
+	};
+};
+
+&edp_phy {
+	status = "okay";
+};
+
 &gpio_keys {
 	pinctrl-0 = <&pwr_key_l &ap_lid_int_l>;
 	lid {
 		label = "Lid";
 		gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
-		gpio-key,wakeup;
+		wakeup-source;
 		linux,code = <0>; /* SW_LID */
 		linux,input-type = <5>; /* EV_SW */
 		debounce-interval = <1>;
 	};
 };
 
+&pwm0 {
+	status = "okay";
+};
+
 &rk808 {
 	vcc11-supply = <&vcc_5v>;
 
@@ -168,6 +254,14 @@
 	};
 };
 
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
+
 &pinctrl {
 	pinctrl-0 = <
 		/* Common for sleep and wake, but no owners */
@@ -184,6 +278,12 @@
 		&suspend_l_sleep
 	>;
 
+	backlight {
+		bl_en: bl-en {
+			rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	buttons {
 		ap_lid_int_l: ap-lid-int-l {
 			rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/sys/gnu/dts/arm/rk3288-veyron-jaq.dts b/sys/gnu/dts/arm/rk3288-veyron-jaq.dts
index c2f52cfb4d06..3748abf562b1 100644
--- a/sys/gnu/dts/arm/rk3288-veyron-jaq.dts
+++ b/sys/gnu/dts/arm/rk3288-veyron-jaq.dts
@@ -61,6 +61,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&lcd_enable_h>;
 		regulator-name = "panel_regulator";
+		startup-delay-us = <100000>;
 		vin-supply = <&vcc33_sys>;
 	};
 
@@ -88,6 +89,48 @@
 	};
 };
 
+&backlight {
+	/* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
+	brightness-levels = <
+		  0
+		  8   9  10  11  12  13  14  15
+		 16  17  18  19  20  21  22  23
+		 24  25  26  27  28  29  30  31
+		 32  33  34  35  36  37  38  39
+		 40  41  42  43  44  45  46  47
+		 48  49  50  51  52  53  54  55
+		 56  57  58  59  60  61  62  63
+		 64  65  66  67  68  69  70  71
+		 72  73  74  75  76  77  78  79
+		 80  81  82  83  84  85  86  87
+		 88  89  90  91  92  93  94  95
+		 96  97  98  99 100 101 102 103
+		104 105 106 107 108 109 110 111
+		112 113 114 115 116 117 118 119
+		120 121 122 123 124 125 126 127
+		128 129 130 131 132 133 134 135
+		136 137 138 139 140 141 142 143
+		144 145 146 147 148 149 150 151
+		152 153 154 155 156 157 158 159
+		160 161 162 163 164 165 166 167
+		168 169 170 171 172 173 174 175
+		176 177 178 179 180 181 182 183
+		184 185 186 187 188 189 190 191
+		192 193 194 195 196 197 198 199
+		200 201 202 203 204 205 206 207
+		208 209 210 211 212 213 214 215
+		216 217 218 219 220 221 222 223
+		224 225 226 227 228 229 230 231
+		232 233 234 235 236 237 238 239
+		240 241 242 243 244 245 246 247
+		248 249 250 251 252 253 254 255>;
+	power-supply = <&backlight_regulator>;
+};
+
+&panel {
+	power-supply = <&panel_regulator>;
+};
+
 &rk808 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
@@ -142,12 +185,6 @@
 		};
 	};
 
-	edp {
-		edp_hpd: edp_hpd {
-			rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
-		};
-	};
-
 	hdmi {
 		vcc50_hdmi_en: vcc50-hdmi-en {
 			rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/sys/gnu/dts/arm/rk3288-veyron-jerry.dts b/sys/gnu/dts/arm/rk3288-veyron-jerry.dts
index 60bd6e91e308..f6b2eaaebb9a 100644
--- a/sys/gnu/dts/arm/rk3288-veyron-jerry.dts
+++ b/sys/gnu/dts/arm/rk3288-veyron-jerry.dts
@@ -60,6 +60,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&lcd_enable_h>;
 		regulator-name = "panel_regulator";
+		startup-delay-us = <100000>;
 		vin-supply = <&vcc33_sys>;
 	};
 
@@ -87,6 +88,14 @@
 	};
 };
 
+&backlight {
+	power-supply = <&backlight_regulator>;
+};
+
+&panel {
+	power-supply= <&panel_regulator>;
+};
+
 &rk808 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pmic_int_l>;
diff --git a/sys/gnu/dts/arm/rk3288-veyron-minnie.dts b/sys/gnu/dts/arm/rk3288-veyron-minnie.dts
index 699beb0a9481..f72d616d1bf8 100644
--- a/sys/gnu/dts/arm/rk3288-veyron-minnie.dts
+++ b/sys/gnu/dts/arm/rk3288-veyron-minnie.dts
@@ -70,6 +70,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&lcd_enable_h>;
 		regulator-name = "panel_regulator";
+		startup-delay-us = <100000>;
 		vin-supply = <&vcc33_sys>;
 	};
 
@@ -86,6 +87,44 @@
 	};
 };
 
+&backlight {
+	/* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
+	brightness-levels = <
+			  0   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+	power-supply = <&backlight_regulator>;
+};
+
 &emmc {
 	/delete-property/mmc-hs200-1_8v;
 };
@@ -135,6 +174,11 @@
 	};
 };
 
+&panel {
+	compatible = "auo,b101ean01", "simple-panel";
+	power-supply= <&panel_regulator>;
+};
+
 &rk808 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
diff --git a/sys/gnu/dts/arm/rk3288-veyron-pinky.dts b/sys/gnu/dts/arm/rk3288-veyron-pinky.dts
index 94b56e33d947..d44351ec2333 100644
--- a/sys/gnu/dts/arm/rk3288-veyron-pinky.dts
+++ b/sys/gnu/dts/arm/rk3288-veyron-pinky.dts
@@ -65,6 +65,13 @@
 	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>;
 };
 
+&edp {
+	/delete-property/pinctrl-names;
+	/delete-property/pinctrl-0;
+
+	force-hpd;
+};
+
 &gpio_keys {
 	pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
 
diff --git a/sys/gnu/dts/arm/rk3288-veyron-speedy.dts b/sys/gnu/dts/arm/rk3288-veyron-speedy.dts
index b34a7b5b3f62..a0d033f6fe52 100644
--- a/sys/gnu/dts/arm/rk3288-veyron-speedy.dts
+++ b/sys/gnu/dts/arm/rk3288-veyron-speedy.dts
@@ -61,6 +61,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&lcd_enable_h>;
 		regulator-name = "panel_regulator";
+		startup-delay-us = <100000>;
 		vin-supply = <&vcc33_sys>;
 	};
 
@@ -88,6 +89,10 @@
 	};
 };
 
+&backlight {
+	power-supply = <&backlight_regulator>;
+};
+
 &cpu_alert0 {
 	temperature = <65000>;
 };
@@ -96,6 +101,17 @@
 	temperature = <70000>;
 };
 
+&edp {
+	/delete-property/pinctrl-names;
+	/delete-property/pinctrl-0;
+
+	force-hpd;
+};
+
+&panel {
+	power-supply= <&panel_regulator>;
+};
+
 &rk808 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pmic_int_l>;
diff --git a/sys/gnu/dts/arm/rk3288-veyron.dtsi b/sys/gnu/dts/arm/rk3288-veyron.dtsi
index 9fce91ffff6f..b2557bf5a58f 100644
--- a/sys/gnu/dts/arm/rk3288-veyron.dtsi
+++ b/sys/gnu/dts/arm/rk3288-veyron.dtsi
@@ -64,7 +64,7 @@
 			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			debounce-interval = <100>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
@@ -141,12 +141,27 @@
 
 &cpu0 {
 	cpu0-supply = <&vdd_cpu>;
+	operating-points = <
+		/* KHz    uV */
+		1800000 1400000
+		1704000 1350000
+		1608000 1300000
+		1512000 1250000
+		1416000 1200000
+		1200000 1100000
+		1008000 1050000
+		 816000 1000000
+		 696000  950000
+		 600000  900000
+		 408000  900000
+		 216000  900000
+		 126000  900000
+	>;
 };
 
 &emmc {
 	status = "okay";
 
-	broken-cd;
 	bus-width = <8>;
 	cap-mmc-highspeed;
 	rockchip,default-sample-phase = <158>;
@@ -340,11 +355,6 @@
 	i2c-scl-rising-time-ns = <1000>;
 };
 
-&power {
-	assigned-clocks = <&cru SCLK_EDP_24M>;
-	assigned-clock-parents = <&xin24m>;
-};
-
 &pwm1 {
 	status = "okay";
 };
@@ -352,7 +362,6 @@
 &sdio0 {
 	status = "okay";
 
-	broken-cd;
 	bus-width = <4>;
 	cap-sd-highspeed;
 	cap-sdio-irq;
@@ -421,7 +430,7 @@
 	status = "okay";
 
 	assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
-	assigned-clock-parents = <&cru SCLK_OTGPHY0>;
+	assigned-clock-parents = <&usbphy0>;
 	dr_mode = "host";
 };
 
diff --git a/sys/gnu/dts/arm/rk3288.dtsi b/sys/gnu/dts/arm/rk3288.dtsi
index 8ac49f3efc17..3b44ef3cff12 100644
--- a/sys/gnu/dts/arm/rk3288.dtsi
+++ b/sys/gnu/dts/arm/rk3288.dtsi
@@ -134,7 +134,7 @@
 	};
 
 	amba {
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
@@ -145,6 +145,7 @@
 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
+			arm,pl330-broken-no-flushp;
 			clocks = <&cru ACLK_DMAC2>;
 			clock-names = "apb_pclk";
 		};
@@ -155,6 +156,7 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
+			arm,pl330-broken-no-flushp;
 			clocks = <&cru ACLK_DMAC1>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -166,6 +168,7 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
+			arm,pl330-broken-no-flushp;
 			clocks = <&cru ACLK_DMAC1>;
 			clock-names = "apb_pclk";
 		};
@@ -442,7 +445,78 @@
 	};
 
 	thermal-zones {
-		#include "rk3288-thermal.dtsi"
+		reserve_thermal: reserve_thermal {
+			polling-delay-passive = <1000>; /* milliseconds */
+			polling-delay = <5000>; /* milliseconds */
+
+			thermal-sensors = <&tsadc 0>;
+		};
+
+		cpu_thermal: cpu_thermal {
+			polling-delay-passive = <100>; /* milliseconds */
+			polling-delay = <5000>; /* milliseconds */
+
+			thermal-sensors = <&tsadc 1>;
+
+			trips {
+				cpu_alert0: cpu_alert0 {
+					temperature = <70000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+				cpu_alert1: cpu_alert1 {
+					temperature = <75000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+				cpu_crit: cpu_crit {
+					temperature = <90000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT 6>;
+				};
+				map1 {
+					trip = <&cpu_alert1>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu_thermal: gpu_thermal {
+			polling-delay-passive = <100>; /* milliseconds */
+			polling-delay = <5000>; /* milliseconds */
+
+			thermal-sensors = <&tsadc 2>;
+
+			trips {
+				gpu_alert0: gpu_alert0 {
+					temperature = <70000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "passive";
+				};
+				gpu_crit: gpu_crit {
+					temperature = <90000>; /* millicelsius */
+					hysteresis = <2000>; /* millicelsius */
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu_alert0>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
 	};
 
 	tsadc: tsadc@ff280000 {
@@ -630,6 +704,9 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
+			assigned-clocks = <&cru SCLK_EDP_24M>;
+			assigned-clock-parents = <&xin24m>;
+
 			/*
 			 * Note: Although SCLK_* are the working clocks
 			 * of device without including on the NOC, needed for
@@ -653,7 +730,7 @@
 			 *	*_HDMI		HDMI
 			 *	*_MIPI_*	MIPI
 			 */
-			pd_vio {
+			pd_vio@RK3288_PD_VIO {
 				reg = <RK3288_PD_VIO>;
 				clocks = <&cru ACLK_IEP>,
 					 <&cru ACLK_ISP>,
@@ -686,7 +763,7 @@
 			 * Note: The following 3 are HEVC(H.265) clocks,
 			 * and on the ACLK_HEVC_NIU (NOC).
 			 */
-			pd_hevc {
+			pd_hevc@RK3288_PD_HEVC {
 				reg = <RK3288_PD_HEVC>;
 				clocks = <&cru ACLK_HEVC>,
 					 <&cru SCLK_HEVC_CABAC>,
@@ -698,7 +775,7 @@
 			 * (video endecoder & decoder) clocks that on the
 			 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 			 */
-			pd_video {
+			pd_video@RK3288_PD_VIDEO {
 				reg = <RK3288_PD_VIDEO>;
 				clocks = <&cru ACLK_VCODEC>,
 					 <&cru HCLK_VCODEC>;
@@ -708,7 +785,7 @@
 			 * Note: ACLK_GPU is the GPU clock,
 			 * and on the ACLK_GPU_NIU (NOC).
 			 */
-			pd_gpu {
+			pd_gpu@RK3288_PD_GPU {
 				reg = <RK3288_PD_GPU>;
 				clocks = <&cru ACLK_GPU>;
 			};
@@ -739,8 +816,16 @@
 	};
 
 	grf: syscon@ff770000 {
-		compatible = "rockchip,rk3288-grf", "syscon";
+		compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 		reg = <0xff770000 0x1000>;
+
+		edp_phy: edp-phy {
+			compatible = "rockchip,rk3288-dp-phy";
+			clocks = <&cru SCLK_EDP_24M>;
+			clock-names = "24m";
+			#phy-cells = <0>;
+			status = "disabled";
+		};
 	};
 
 	wdt: watchdog@ff800000 {
@@ -759,7 +844,7 @@
 		clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 		dmas = <&dmac_bus_s 3>;
 		dma-names = "tx";
-		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&spdif_tx>;
 		rockchip,grf = <&grf>;
@@ -769,7 +854,7 @@
 	i2s: i2s@ff890000 {
 		compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 		reg = <0xff890000 0x10000>;
-		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
@@ -815,6 +900,16 @@
 				reg = <0>;
 				remote-endpoint = <&hdmi_in_vopb>;
 			};
+
+			vopb_out_edp: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&edp_in_vopb>;
+			};
+
+			vopb_out_mipi: endpoint@2 {
+				reg = <2>;
+				remote-endpoint = <&mipi_in_vopb>;
+			};
 		};
 	};
 
@@ -848,6 +943,16 @@
 				reg = <0>;
 				remote-endpoint = <&hdmi_in_vopl>;
 			};
+
+			vopl_out_edp: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&edp_in_vopl>;
+			};
+
+			vopl_out_mipi: endpoint@2 {
+				reg = <2>;
+				remote-endpoint = <&mipi_in_vopl>;
+			};
 		};
 	};
 
@@ -861,6 +966,66 @@
 		status = "disabled";
 	};
 
+	mipi_dsi: mipi@ff960000 {
+		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0xff960000 0x4000>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
+		clock-names = "ref", "pclk";
+		power-domains = <&power RK3288_PD_VIO>;
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		ports {
+			mipi_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				mipi_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_mipi>;
+				};
+				mipi_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_mipi>;
+				};
+			};
+		};
+	};
+
+	edp: dp@ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&edp_phy>;
+		phy-names = "dp";
+		resets = <&cru SRST_EDP>;
+		reset-names = "dp";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			edp_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+		};
+	};
+
 	hdmi: hdmi@ff980000 {
 		compatible = "rockchip,rk3288-dw-hdmi";
 		reg = <0xff980000 0x20000>;
@@ -921,25 +1086,28 @@
 		#size-cells = <0>;
 		status = "disabled";
 
-		usbphy0: usb-phy0 {
+		usbphy0: usb-phy@320 {
 			#phy-cells = <0>;
 			reg = <0x320>;
 			clocks = <&cru SCLK_OTGPHY0>;
 			clock-names = "phyclk";
+			#clock-cells = <0>;
 		};
 
-		usbphy1: usb-phy1 {
+		usbphy1: usb-phy@334 {
 			#phy-cells = <0>;
 			reg = <0x334>;
 			clocks = <&cru SCLK_OTGPHY1>;
 			clock-names = "phyclk";
+			#clock-cells = <0>;
 		};
 
-		usbphy2: usb-phy2 {
+		usbphy2: usb-phy@348 {
 			#phy-cells = <0>;
 			reg = <0x348>;
 			clocks = <&cru SCLK_OTGPHY2>;
 			clock-names = "phyclk";
+			#clock-cells = <0>;
 		};
 	};
 
@@ -1110,6 +1278,12 @@
 			};
 		};
 
+		edp {
+			edp_hpd: edp-hpd {
+				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
+			};
+		};
+
 		i2c0 {
 			i2c0_xfer: i2c0-xfer {
 				rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
diff --git a/sys/gnu/dts/arm/rk3xxx.dtsi b/sys/gnu/dts/arm/rk3xxx.dtsi
index 99eeea70223b..99bbcc2c9b89 100644
--- a/sys/gnu/dts/arm/rk3xxx.dtsi
+++ b/sys/gnu/dts/arm/rk3xxx.dtsi
@@ -67,7 +67,7 @@
 	};
 
 	amba {
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
@@ -78,6 +78,7 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
+			arm,pl330-broken-no-flushp;
 			clocks = <&cru ACLK_DMA1>;
 			clock-names = "apb_pclk";
 		};
@@ -88,6 +89,7 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
+			arm,pl330-broken-no-flushp;
 			clocks = <&cru ACLK_DMA1>;
 			clock-names = "apb_pclk";
 			status = "disabled";
@@ -99,6 +101,7 @@
 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
+			arm,pl330-broken-no-flushp;
 			clocks = <&cru ACLK_DMA2>;
 			clock-names = "apb_pclk";
 		};
diff --git a/sys/gnu/dts/arm/s5pv210-aquila.dts b/sys/gnu/dts/arm/s5pv210-aquila.dts
index aa64faa72970..da24ab570b0e 100644
--- a/sys/gnu/dts/arm/s5pv210-aquila.dts
+++ b/sys/gnu/dts/arm/s5pv210-aquila.dts
@@ -257,7 +257,7 @@
 			linux,code = <KEY_POWER>;
 			label = "power";
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 };
@@ -268,7 +268,7 @@
 
 &keypad {
 	linux,input-no-autorepeat;
-	linux,input-wakeup;
+	wakeup-source;
 	samsung,keypad-num-rows = <3>;
 	samsung,keypad-num-columns = <3>;
 	pinctrl-names = "default";
diff --git a/sys/gnu/dts/arm/s5pv210-goni.dts b/sys/gnu/dts/arm/s5pv210-goni.dts
index 3b76eeeb8410..0a33d402138e 100644
--- a/sys/gnu/dts/arm/s5pv210-goni.dts
+++ b/sys/gnu/dts/arm/s5pv210-goni.dts
@@ -239,7 +239,7 @@
 			linux,code = <KEY_POWER>;
 			label = "power";
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 };
@@ -250,7 +250,7 @@
 
 &keypad {
 	linux,input-no-autorepeat;
-	linux,input-wakeup;
+	wakeup-source;
 	samsung,keypad-num-rows = <3>;
 	samsung,keypad-num-columns = <3>;
 	pinctrl-names = "default";
diff --git a/sys/gnu/dts/arm/s5pv210-smdkv210.dts b/sys/gnu/dts/arm/s5pv210-smdkv210.dts
index da7d210df670..9eb6aff3e38f 100644
--- a/sys/gnu/dts/arm/s5pv210-smdkv210.dts
+++ b/sys/gnu/dts/arm/s5pv210-smdkv210.dts
@@ -59,7 +59,7 @@
 
 &keypad {
 	linux,input-no-autorepeat;
-	linux,input-wakeup;
+	wakeup-source;
 	samsung,keypad-num-rows = <8>;
 	samsung,keypad-num-columns = <8>;
 	pinctrl-names = "default";
@@ -197,7 +197,7 @@
 	display-timings {
 		native-mode = <&timing0>;
 
-		timing0: timing@0 {
+		timing0: timing {
 			/* 800x480@60Hz */
 			clock-frequency = <24373920>;
 			hactive = <800>;
diff --git a/sys/gnu/dts/arm/s5pv210.dtsi b/sys/gnu/dts/arm/s5pv210.dtsi
index 8344a0ee2b86..ffc36bd24d2f 100644
--- a/sys/gnu/dts/arm/s5pv210.dtsi
+++ b/sys/gnu/dts/arm/s5pv210.dtsi
@@ -130,7 +130,7 @@
 		amba {
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			ranges;
 
 			pdma0: dma@e0900000 {
diff --git a/sys/gnu/dts/arm/sama5d2-pinfunc.h b/sys/gnu/dts/arm/sama5d2-pinfunc.h
index 1afe24629d1f..8a394f336003 100644
--- a/sys/gnu/dts/arm/sama5d2-pinfunc.h
+++ b/sys/gnu/dts/arm/sama5d2-pinfunc.h
@@ -90,7 +90,7 @@
 #define PIN_PA14__I2SC1_MCK		PINMUX_PIN(PIN_PA14, 4, 2)
 #define PIN_PA14__FLEXCOM3_IO2		PINMUX_PIN(PIN_PA14, 5, 1)
 #define PIN_PA14__D9			PINMUX_PIN(PIN_PA14, 6, 2)
-#define PIN_PA15			14
+#define PIN_PA15			15
 #define PIN_PA15__GPIO			PINMUX_PIN(PIN_PA15, 0, 0)
 #define PIN_PA15__SPI0_MOSI		PINMUX_PIN(PIN_PA15, 1, 1)
 #define PIN_PA15__TF1			PINMUX_PIN(PIN_PA15, 2, 1)
@@ -837,8 +837,8 @@
 #define PIN_PD23__ISC_FIELD		PINMUX_PIN(PIN_PD23, 6, 4)
 #define PIN_PD24			120
 #define PIN_PD24__GPIO			PINMUX_PIN(PIN_PD24, 0, 0)
-#define PIN_PD24__UTXD2			PINMUX_PIN(PIN_PD23, 1, 2)
-#define PIN_PD24__FLEXCOM4_IO3		PINMUX_PIN(PIN_PD23, 3, 3)
+#define PIN_PD24__UTXD2			PINMUX_PIN(PIN_PD24, 1, 2)
+#define PIN_PD24__FLEXCOM4_IO3		PINMUX_PIN(PIN_PD24, 3, 3)
 #define PIN_PD25			121
 #define PIN_PD25__GPIO			PINMUX_PIN(PIN_PD25, 0, 0)
 #define PIN_PD25__SPI1_SPCK		PINMUX_PIN(PIN_PD25, 1, 3)
diff --git a/sys/gnu/dts/arm/sama5d2.dtsi b/sys/gnu/dts/arm/sama5d2.dtsi
index 3f750f6170f2..2827e7ab5ebc 100644
--- a/sys/gnu/dts/arm/sama5d2.dtsi
+++ b/sys/gnu/dts/arm/sama5d2.dtsi
@@ -88,12 +88,6 @@
 			#clock-cells = <0>;
 			clock-frequency = <0>;
 		};
-
-		adc_op_clk: adc_op_clk{
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <1000000>;
-		};
 	};
 
 	ns_sram: sram@00200000 {
@@ -263,6 +257,44 @@
 			cache-level = <2>;
 		};
 
+		nand0: nand@80000000 {
+			compatible = "atmel,sama5d2-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = < /* EBI CS3 */
+				0x80000000 0x08000000
+				/* SMC PMECC regs */
+				0xf8014070 0x00000490
+				/* SMC PMECC Error Location regs */
+				0xf8014500 0x00000200
+				/* ROM Galois tables */
+				0x00040000 0x00018000
+				>;
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
+			atmel,nand-addr-offset = <21>;
+			atmel,nand-cmd-offset = <22>;
+			atmel,nand-has-dma;
+			atmel,has-pmecc;
+			atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
+			status = "disabled";
+
+			nfc@c0000000 {
+				compatible = "atmel,sama5d3-nfc";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = < /* NFC Command Registers */
+					0xc0000000 0x08000000
+					/* NFC HSMC regs */
+					0xf8014000 0x00000070
+					/* NFC SRAM banks */
+					0x00100000 0x00100000
+					>;
+				clocks = <&hsmc_clk>;
+				atmel,write-by-sram;
+			};
+		};
+
 		sdmmc0: sdio-host@a0000000 {
 			compatible = "atmel,sama5d2-sdhci";
 			reg = <0xa0000000 0x300>;
@@ -287,6 +319,32 @@
 			#size-cells = <1>;
 			ranges;
 
+			hlcdc: hlcdc@f0000000 {
+				compatible = "atmel,sama5d2-hlcdc";
+				reg = <0xf0000000 0x2000>;
+				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+				clock-names = "periph_clk","sys_clk", "slow_clk";
+				status = "disabled";
+
+				hlcdc-display-controller {
+					compatible = "atmel,hlcdc-display-controller";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
+						reg = <0>;
+					};
+				};
+
+				hlcdc_pwm: hlcdc-pwm {
+					compatible = "atmel,hlcdc-pwm";
+					#pwm-cells = <3>;
+				};
+			};
+
 			ramc0: ramc@f000c000 {
 				compatible = "atmel,sama5d3-ddramc";
 				reg = <0xf000c000 0x200>;
@@ -880,6 +938,13 @@
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf801c000 0x100>;
 				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(35))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(36))>;
+				dma-names = "tx", "rx";
 				clocks = <&uart0_clk>;
 				clock-names = "usart";
 				status = "disabled";
@@ -889,6 +954,13 @@
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8020000 0x100>;
 				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(37))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(38))>;
+				dma-names = "tx", "rx";
 				clocks = <&uart1_clk>;
 				clock-names = "usart";
 				status = "disabled";
@@ -898,6 +970,13 @@
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8024000 0x100>;
 				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(39))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(40))>;
+				dma-names = "tx", "rx";
 				clocks = <&uart2_clk>;
 				clock-names = "usart";
 				status = "disabled";
@@ -920,6 +999,11 @@
 				status = "disabled";
 			};
 
+			sfr: sfr@f8030000 {
+				compatible = "atmel,sama5d2-sfr", "syscon";
+				reg = <0xf8030000 0x98>;
+			};
+
 			flx0: flexcom@f8034000 {
 				compatible = "atmel,sama5d2-flexcom";
 				reg = <0xf8034000 0x200>;
@@ -946,6 +1030,15 @@
 				clocks = <&clk32k>;
 			};
 
+			shdwc@f8048010 {
+				compatible = "atmel,sama5d2-shdwc";
+				reg = <0xf8048010 0x10>;
+				clocks = <&clk32k>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				atmel,wakeup-rtc-timer;
+			};
+
 			pit: timer@f8048030 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xf8048030 0x10>;
@@ -957,6 +1050,7 @@
 				compatible = "atmel,sama5d4-wdt";
 				reg = <0xf8048040 0x10>;
 				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&clk32k>;
 				status = "disabled";
 			};
 
@@ -1016,6 +1110,13 @@
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfc008000 0x100>;
 				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(41))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(42))>;
+				dma-names = "tx", "rx";
 				clocks = <&uart3_clk>;
 				clock-names = "usart";
 				status = "disabled";
@@ -1024,6 +1125,13 @@
 			uart4: serial@fc00c000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xfc00c000 0x100>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(43))>,
+				       <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(44))>;
+				dma-names = "tx", "rx";
 				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
 				clocks = <&uart4_clk>;
 				clock-names = "usart";
@@ -1060,6 +1168,13 @@
 				status = "disabled";
 			};
 
+			trng@fc01c000 {
+				compatible = "atmel,at91sam9g45-trng";
+				reg = <0xfc01c000 0x100>;
+				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&trng_clk>;
+			};
+
 			aic: interrupt-controller@fc020000 {
 				#interrupt-cells = <3>;
 				compatible = "atmel,sama5d2-aic";
@@ -1085,6 +1200,18 @@
 				status = "disabled";
 			};
 
+			adc: adc@fc030000 {
+				compatible = "atmel,sama5d2-adc";
+				reg = <0xfc030000 0x100>;
+				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&adc_clk>;
+				clock-names = "adc_clk";
+				atmel,min-sample-rate-hz = <200000>;
+				atmel,max-sample-rate-hz = <20000000>;
+				atmel,startup-time-ms = <4>;
+				status = "disabled";
+			};
+
 			pioA: pinctrl@fc038000 {
 				compatible = "atmel,sama5d2-pinctrl";
 				reg = <0xfc038000 0x600>;
@@ -1114,6 +1241,11 @@
 				clock-names = "tdes_clk";
 				status = "okay";
 			};
+
+			chipid@fc069000 {
+				compatible = "atmel,sama5d2-chipid";
+				reg = <0xfc069000 0x8>;
+			};
 		};
 	};
 };
diff --git a/sys/gnu/dts/arm/sama5d3.dtsi b/sys/gnu/dts/arm/sama5d3.dtsi
index a53279160f98..36301bd9a14a 100644
--- a/sys/gnu/dts/arm/sama5d3.dtsi
+++ b/sys/gnu/dts/arm/sama5d3.dtsi
@@ -426,6 +426,13 @@
 				clock-names = "tdes_clk";
 			};
 
+			trng@f8040000 {
+				compatible = "atmel,at91sam9g45-trng";
+				reg = <0xf8040000 0x100>;
+				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&trng_clk>;
+			};
+
 			dma0: dma-controller@ffffe600 {
 				compatible = "atmel,at91sam9g45-dma";
 				reg = <0xffffe600 0x200>;
diff --git a/sys/gnu/dts/arm/sama5d4.dtsi b/sys/gnu/dts/arm/sama5d4.dtsi
index b8032bca4621..4e2cc30d6615 100644
--- a/sys/gnu/dts/arm/sama5d4.dtsi
+++ b/sys/gnu/dts/arm/sama5d4.dtsi
@@ -1202,6 +1202,13 @@
 				status = "disabled";
 			};
 
+			trng@fc030000 {
+				compatible = "atmel,at91sam9g45-trng";
+				reg = <0xfc030000 0x100>;
+				interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&trng_clk>;
+			};
+
 			adc0: adc@fc034000 {
 				compatible = "atmel,at91sam9x5-adc";
 				reg = <0xfc034000 0x100>;
@@ -1302,6 +1309,7 @@
 			watchdog@fc068640 {
 				compatible = "atmel,sama5d4-wdt";
 				reg = <0xfc068640 0x10>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
 				clocks = <&clk32k>;
 				status = "disabled";
 			};
@@ -1342,7 +1350,7 @@
 			dbgu: serial@fc069000 {
 				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
 				reg = <0xfc069000 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
+				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
 				clocks = <&dbgu_clk>;
diff --git a/sys/gnu/dts/arm/sh73a0-kzm9g.dts b/sys/gnu/dts/arm/sh73a0-kzm9g.dts
index aa8bae3b8fcf..c2d8a080e392 100644
--- a/sys/gnu/dts/arm/sh73a0-kzm9g.dts
+++ b/sys/gnu/dts/arm/sh73a0-kzm9g.dts
@@ -149,6 +149,13 @@
 			label = "SW1";
 			wakeup-source;
 		};
+
+		wakeup-key {
+			gpios = <&pfc 159 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WAKEUP>;
+			label = "NMI";
+			wakeup-source;
+		};
 	};
 
 	sound {
@@ -329,41 +336,41 @@
 
 &pfc {
 	i2c3_pins: i2c3 {
-		renesas,groups = "i2c3_1";
-		renesas,function = "i2c3";
+		groups = "i2c3_1";
+		function = "i2c3";
 	};
 
 	mmcif_pins: mmc {
 		mux {
-			renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
-			renesas,function = "mmc0";
+			groups = "mmc0_data8_0", "mmc0_ctrl_0";
+			function = "mmc0";
 		};
 		cfg {
-			renesas,groups = "mmc0_data8_0";
-			renesas,pins = "PORT279";
+			groups = "mmc0_data8_0";
+			pins = "PORT279";
 			bias-pull-up;
 		};
 	};
 
 	scifa4_pins: serial4 {
-		renesas,groups = "scifa4_data", "scifa4_ctrl";
-		renesas,function = "scifa4";
+		groups = "scifa4_data", "scifa4_ctrl";
+		function = "scifa4";
 	};
 
 	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
-		renesas,function = "sdhi0";
+		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
+		function = "sdhi0";
 	};
 
 	sdhi2_pins: sd2 {
-		renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
-		renesas,function = "sdhi2";
+		groups = "sdhi2_data4", "sdhi2_ctrl";
+		function = "sdhi2";
 	};
 
 	fsia_pins: sounda {
-		renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
-				 "fsia_data_in", "fsia_data_out";
-		renesas,function = "fsia";
+		groups = "fsia_mclk_in", "fsia_sclk_in",
+			 "fsia_data_in", "fsia_data_out";
+		function = "fsia";
 	};
 };
 
diff --git a/sys/gnu/dts/arm/sh73a0.dtsi b/sys/gnu/dts/arm/sh73a0.dtsi
index 3a6056f9f0d2..c4f434cdec60 100644
--- a/sys/gnu/dts/arm/sh73a0.dtsi
+++ b/sys/gnu/dts/arm/sh73a0.dtsi
@@ -43,7 +43,7 @@
 	timer@f0000600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0xf0000600 0x20>;
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 		clocks = <&twd_clk>;
 	};
 
@@ -58,7 +58,7 @@
 	L2: cache-controller {
 		compatible = "arm,pl310-cache";
 		reg = <0xf0100000 0x1000>;
-		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 		power-domains = <&pd_a3sm>;
 		arm,data-latency = <3 3 3>;
 		arm,tag-latency = <2 2 2>;
@@ -70,8 +70,8 @@
 	sbsc2: memory-controller@fb400000 {
 		compatible = "renesas,sbsc-sh73a0";
 		reg = <0xfb400000 0x400>;
-		interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 38 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "sec", "temp";
 		power-domains = <&pd_a4bc1>;
 	};
@@ -79,22 +79,22 @@
 	sbsc1: memory-controller@fe400000 {
 		compatible = "renesas,sbsc-sh73a0";
 		reg = <0xfe400000 0x400>;
-		interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 36 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "sec", "temp";
 		power-domains = <&pd_a4bc0>;
 	};
 
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
-		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
-			     <0 56 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	cmt1: timer@e6138000 {
 		compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
 		reg = <0xe6138000 0x200>;
-		interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
 		clock-names = "fck";
 		power-domains = <&pd_c5>;
@@ -113,14 +113,14 @@
 			<0xe6900020 1>,
 			<0xe6900040 1>,
 			<0xe6900060 1>;
-		interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
-			      0 2 IRQ_TYPE_LEVEL_HIGH
-			      0 3 IRQ_TYPE_LEVEL_HIGH
-			      0 4 IRQ_TYPE_LEVEL_HIGH
-			      0 5 IRQ_TYPE_LEVEL_HIGH
-			      0 6 IRQ_TYPE_LEVEL_HIGH
-			      0 7 IRQ_TYPE_LEVEL_HIGH
-			      0 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 		power-domains = <&pd_a4s>;
 		control-parent;
@@ -135,14 +135,14 @@
 			<0xe6900024 1>,
 			<0xe6900044 1>,
 			<0xe6900064 1>;
-		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
-			      0 10 IRQ_TYPE_LEVEL_HIGH
-			      0 11 IRQ_TYPE_LEVEL_HIGH
-			      0 12 IRQ_TYPE_LEVEL_HIGH
-			      0 13 IRQ_TYPE_LEVEL_HIGH
-			      0 14 IRQ_TYPE_LEVEL_HIGH
-			      0 15 IRQ_TYPE_LEVEL_HIGH
-			      0 16 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 		power-domains = <&pd_a4s>;
 		control-parent;
@@ -157,14 +157,14 @@
 			<0xe6900028 1>,
 			<0xe6900048 1>,
 			<0xe6900068 1>;
-		interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
-			      0 18 IRQ_TYPE_LEVEL_HIGH
-			      0 19 IRQ_TYPE_LEVEL_HIGH
-			      0 20 IRQ_TYPE_LEVEL_HIGH
-			      0 21 IRQ_TYPE_LEVEL_HIGH
-			      0 22 IRQ_TYPE_LEVEL_HIGH
-			      0 23 IRQ_TYPE_LEVEL_HIGH
-			      0 24 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 		power-domains = <&pd_a4s>;
 		control-parent;
@@ -179,14 +179,14 @@
 			<0xe690002c 1>,
 			<0xe690004c 1>,
 			<0xe690006c 1>;
-		interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
-			      0 26 IRQ_TYPE_LEVEL_HIGH
-			      0 27 IRQ_TYPE_LEVEL_HIGH
-			      0 28 IRQ_TYPE_LEVEL_HIGH
-			      0 29 IRQ_TYPE_LEVEL_HIGH
-			      0 30 IRQ_TYPE_LEVEL_HIGH
-			      0 31 IRQ_TYPE_LEVEL_HIGH
-			      0 32 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 		power-domains = <&pd_a4s>;
 		control-parent;
@@ -197,10 +197,10 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 		reg = <0xe6820000 0x425>;
-		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
-			      0 168 IRQ_TYPE_LEVEL_HIGH
-			      0 169 IRQ_TYPE_LEVEL_HIGH
-			      0 170 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -211,10 +211,10 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 		reg = <0xe6822000 0x425>;
-		interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
-			      0 52 IRQ_TYPE_LEVEL_HIGH
-			      0 53 IRQ_TYPE_LEVEL_HIGH
-			      0 54 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -225,10 +225,10 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 		reg = <0xe6824000 0x425>;
-		interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
-			      0 172 IRQ_TYPE_LEVEL_HIGH
-			      0 173 IRQ_TYPE_LEVEL_HIGH
-			      0 174 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -239,10 +239,10 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 		reg = <0xe6826000 0x425>;
-		interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
-			      0 184 IRQ_TYPE_LEVEL_HIGH
-			      0 185 IRQ_TYPE_LEVEL_HIGH
-			      0 186 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
@@ -253,10 +253,10 @@
 		#size-cells = <0>;
 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 		reg = <0xe6828000 0x425>;
-		interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
-			      0 188 IRQ_TYPE_LEVEL_HIGH
-			      0 189 IRQ_TYPE_LEVEL_HIGH
-			      0 190 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
 		power-domains = <&pd_c5>;
 		status = "disabled";
@@ -265,8 +265,8 @@
 	mmcif: mmc@e6bd0000 {
 		compatible = "renesas,sh-mmcif";
 		reg = <0xe6bd0000 0x100>;
-		interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
-			      0 141 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
 		power-domains = <&pd_a3sp>;
 		reg-io-width = <4>;
@@ -276,7 +276,7 @@
 	msiof0: spi@e6e20000 {
 		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 		reg = <0xe6e20000 0x0064>;
-		interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
 		power-domains = <&pd_a3sp>;
 		#address-cells = <1>;
@@ -287,7 +287,7 @@
 	msiof1: spi@e6e10000 {
 		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 		reg = <0xe6e10000 0x0064>;
-		interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
 		power-domains = <&pd_a3sp>;
 		#address-cells = <1>;
@@ -298,7 +298,7 @@
 	msiof2: spi@e6e00000 {
 		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 		reg = <0xe6e00000 0x0064>;
-		interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
 		power-domains = <&pd_a3sp>;
 		#address-cells = <1>;
@@ -309,7 +309,7 @@
 	msiof3: spi@e6c90000 {
 		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 		reg = <0xe6c90000 0x0064>;
-		interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
 		power-domains = <&pd_a3sp>;
 		#address-cells = <1>;
@@ -320,9 +320,9 @@
 	sdhi0: sd@ee100000 {
 		compatible = "renesas,sdhi-sh73a0";
 		reg = <0xee100000 0x100>;
-		interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
-			      0 84 IRQ_TYPE_LEVEL_HIGH
-			      0 85 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
 		power-domains = <&pd_a3sp>;
 		cap-sd-highspeed;
@@ -333,8 +333,8 @@
 	sdhi1: sd@ee120000 {
 		compatible = "renesas,sdhi-sh73a0";
 		reg = <0xee120000 0x100>;
-		interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
-			      0 89 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
 		power-domains = <&pd_a3sp>;
 		toshiba,mmc-wrprotect-disable;
@@ -345,8 +345,8 @@
 	sdhi2: sd@ee140000 {
 		compatible = "renesas,sdhi-sh73a0";
 		reg = <0xee140000 0x100>;
-		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
-			      0 105 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
 		power-domains = <&pd_a3sp>;
 		toshiba,mmc-wrprotect-disable;
@@ -357,9 +357,9 @@
 	scifa0: serial@e6c40000 {
 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 		reg = <0xe6c40000 0x100>;
-		interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -367,9 +367,9 @@
 	scifa1: serial@e6c50000 {
 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 		reg = <0xe6c50000 0x100>;
-		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -377,9 +377,9 @@
 	scifa2: serial@e6c60000 {
 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 		reg = <0xe6c60000 0x100>;
-		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -387,9 +387,9 @@
 	scifa3: serial@e6c70000 {
 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 		reg = <0xe6c70000 0x100>;
-		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -397,9 +397,9 @@
 	scifa4: serial@e6c80000 {
 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 		reg = <0xe6c80000 0x100>;
-		interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -407,9 +407,9 @@
 	scifa5: serial@e6cb0000 {
 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 		reg = <0xe6cb0000 0x100>;
-		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -417,9 +417,9 @@
 	scifa6: serial@e6cc0000 {
 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 		reg = <0xe6cc0000 0x100>;
-		interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -427,9 +427,9 @@
 	scifa7: serial@e6cd0000 {
 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 		reg = <0xe6cd0000 0x100>;
-		interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -437,9 +437,9 @@
 	scifb: serial@e6c30000 {
 		compatible = "renesas,scifb-sh73a0", "renesas,scifb";
 		reg = <0xe6c30000 0x100>;
-		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
-		clock-names = "sci_ick";
+		clock-names = "fck";
 		power-domains = <&pd_a3sp>;
 		status = "disabled";
 	};
@@ -579,7 +579,7 @@
 		#sound-dai-cells = <1>;
 		compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
 		reg = <0xec230000 0x400>;
-		interrupts = <0 146 0x4>;
+		interrupts = <GIC_SPI 146 0x4>;
 		power-domains = <&pd_a4mp>;
 		status = "disabled";
 	};
@@ -591,7 +591,7 @@
 		#size-cells = <1>;
 		ranges = <0 0 0x20000000>;
 		reg = <0xfec10000 0x400>;
-		interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&zb_clk>;
 		power-domains = <&pd_a4s>;
 	};
@@ -602,39 +602,33 @@
 		ranges;
 
 		/* External root clocks */
-		extalr_clk: extalr_clk {
+		extalr_clk: extalr {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <32768>;
-			clock-output-names = "extalr";
 		};
-		extal1_clk: extal1_clk {
+		extal1_clk: extal1 {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <26000000>;
-			clock-output-names = "extal1";
 		};
-		extal2_clk: extal2_clk {
+		extal2_clk: extal2 {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-output-names = "extal2";
 		};
-		extcki_clk: extcki_clk {
+		extcki_clk: extcki {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-output-names = "extcki";
 		};
-		fsiack_clk: fsiack_clk {
+		fsiack_clk: fsiack {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "fsiack";
 		};
-		fsibck_clk: fsibck_clk {
+		fsibck_clk: fsibck {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <0>;
-			clock-output-names = "fsibck";
 		};
 
 		/* Special CPG clocks */
@@ -650,7 +644,7 @@
 		};
 
 		/* Variable factor clocks (DIV6) */
-		vclk1_clk: vclk1_clk@e6150008 {
+		vclk1_clk: vclk1@e6150008 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150008 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
@@ -658,9 +652,8 @@
 				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 				 <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk1";
 		};
-		vclk2_clk: vclk2_clk@e615000c {
+		vclk2_clk: vclk2@e615000c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615000c 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
@@ -668,9 +661,8 @@
 				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 				 <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk2";
 		};
-		vclk3_clk: vclk3_clk@e615001c {
+		vclk3_clk: vclk3@e615001c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615001c 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
@@ -678,7 +670,6 @@
 				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 				 <0>;
 			#clock-cells = <0>;
-			clock-output-names = "vclk3";
 		};
 		zb_clk: zb_clk@e6150010 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
@@ -688,168 +679,148 @@
 			#clock-cells = <0>;
 			clock-output-names = "zb";
 		};
-		flctl_clk: flctl_clk@e6150014 {
+		flctl_clk: flctlck@e6150014 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150014 4>;
 			clocks = <&pll1_div2_clk>, <0>,
 				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "flctlck";
 		};
-		sdhi0_clk: sdhi0_clk@e6150074 {
+		sdhi0_clk: sdhi0ck@e6150074 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150074 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&pll1_div13_clk>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "sdhi0ck";
 		};
-		sdhi1_clk: sdhi1_clk@e6150078 {
+		sdhi1_clk: sdhi1ck@e6150078 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150078 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&pll1_div13_clk>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "sdhi1ck";
 		};
-		sdhi2_clk: sdhi2_clk@e615007c {
+		sdhi2_clk: sdhi2ck@e615007c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615007c 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&pll1_div13_clk>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "sdhi2ck";
 		};
-		fsia_clk: fsia_clk@e6150018 {
+		fsia_clk: fsia@e6150018 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150018 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&fsiack_clk>, <&fsiack_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "fsia";
 		};
-		fsib_clk: fsib_clk@e6150090 {
+		fsib_clk: fsib@e6150090 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150090 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&fsibck_clk>, <&fsibck_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "fsib";
 		};
-		sub_clk: sub_clk@e6150080 {
+		sub_clk: sub@e6150080 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150080 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&extal2_clk>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "sub";
 		};
-		spua_clk: spua_clk@e6150084 {
+		spua_clk: spua@e6150084 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150084 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&extal2_clk>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "spua";
 		};
-		spuv_clk: spuv_clk@e6150094 {
+		spuv_clk: spuv@e6150094 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150094 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&extal2_clk>, <&extal2_clk>;
 			#clock-cells = <0>;
-			clock-output-names = "spuv";
 		};
-		msu_clk: msu_clk@e6150088 {
+		msu_clk: msu@e6150088 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150088 4>;
 			clocks = <&pll1_div2_clk>, <0>,
 				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "msu";
 		};
-		hsi_clk: hsi_clk@e615008c {
+		hsi_clk: hsi@e615008c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615008c 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&pll1_div7_clk>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "hsi";
 		};
-		mfg1_clk: mfg1_clk@e6150098 {
+		mfg1_clk: mfg1@e6150098 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150098 4>;
 			clocks = <&pll1_div2_clk>, <0>,
 				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "mfg1";
 		};
-		mfg2_clk: mfg2_clk@e615009c {
+		mfg2_clk: mfg2@e615009c {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe615009c 4>;
 			clocks = <&pll1_div2_clk>, <0>,
 				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "mfg2";
 		};
-		dsit_clk: dsit_clk@e6150060 {
+		dsit_clk: dsit@e6150060 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150060 4>;
 			clocks = <&pll1_div2_clk>, <0>,
 				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "dsit";
 		};
-		dsi0p_clk: dsi0p_clk@e6150064 {
+		dsi0p_clk: dsi0pck@e6150064 {
 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 			reg = <0xe6150064 4>;
 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 				 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
 				 <&extcki_clk>, <0>, <0>, <0>;
 			#clock-cells = <0>;
-			clock-output-names = "dsi0pck";
 		};
 
 		/* Fixed factor clocks */
-		main_div2_clk: main_div2_clk {
+		main_div2_clk: main_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "main_div2";
 		};
-		pll1_div2_clk: pll1_div2_clk {
+		pll1_div2_clk: pll1_div2 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <2>;
 			clock-mult = <1>;
-			clock-output-names = "pll1_div2";
 		};
-		pll1_div7_clk: pll1_div7_clk {
+		pll1_div7_clk: pll1_div7 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <7>;
 			clock-mult = <1>;
-			clock-output-names = "pll1_div7";
 		};
-		pll1_div13_clk: pll1_div13_clk {
+		pll1_div13_clk: pll1_div13 {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 			#clock-cells = <0>;
 			clock-div = <13>;
 			clock-mult = <1>;
-			clock-output-names = "pll1_div13";
 		};
-		twd_clk: twd_clk {
+		twd_clk: twd {
 			compatible = "fixed-factor-clock";
 			clocks = <&cpg_clocks SH73A0_CLK_Z>;
 			#clock-cells = <0>;
 			clock-div = <4>;
 			clock-mult = <1>;
-			clock-output-names = "twd";
 		};
 
 		/* Gate clocks */
diff --git a/sys/gnu/dts/arm/socfpga.dtsi b/sys/gnu/dts/arm/socfpga.dtsi
index 3ed4abdaaa9c..9f48141270b8 100644
--- a/sys/gnu/dts/arm/socfpga.dtsi
+++ b/sys/gnu/dts/arm/socfpga.dtsi
@@ -69,7 +69,7 @@
 		ranges;
 
 		amba {
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -656,6 +656,26 @@
 			status = "disabled";
 		};
 
+		eccmgr: eccmgr@ffd08140 {
+			compatible = "altr,socfpga-ecc-manager";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			l2-ecc@ffd08140 {
+				compatible = "altr,socfpga-l2-ecc";
+				reg = <0xffd08140 0x4>;
+				interrupts = <0 36 1>, <0 37 1>;
+			};
+
+			ocram-ecc@ffd08144 {
+				compatible = "altr,socfpga-ocram-ecc";
+				reg = <0xffd08144 0x4>;
+				iram = <&ocram>;
+				interrupts = <0 178 1>, <0 179 1>;
+			};
+		};
+
 		L2: l2-cache@fffef000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xfffef000 0x1000>;
@@ -811,6 +831,8 @@
 			interrupts = <0 125 4>;
 			clocks = <&usb_mp_clk>;
 			clock-names = "otg";
+			resets = <&rst USB0_RESET>;
+			reset-names = "dwc2";
 			phys = <&usbphy0>;
 			phy-names = "usb2-phy";
 			status = "disabled";
@@ -822,6 +844,8 @@
 			interrupts = <0 128 4>;
 			clocks = <&usb_mp_clk>;
 			clock-names = "otg";
+			resets = <&rst USB1_RESET>;
+			reset-names = "dwc2";
 			phys = <&usbphy0>;
 			phy-names = "usb2-phy";
 			status = "disabled";
diff --git a/sys/gnu/dts/arm/socfpga_arria10.dtsi b/sys/gnu/dts/arm/socfpga_arria10.dtsi
index cce9e50acf68..17e81dc9213e 100644
--- a/sys/gnu/dts/arm/socfpga_arria10.dtsi
+++ b/sys/gnu/dts/arm/socfpga_arria10.dtsi
@@ -63,7 +63,7 @@
 		ranges;
 
 		amba {
-			compatible = "arm,amba-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -78,10 +78,13 @@
 					     <0 87 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 88 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 89 IRQ_TYPE_LEVEL_HIGH>,
-					     <0 90 IRQ_TYPE_LEVEL_HIGH>;
+					     <0 90 IRQ_TYPE_LEVEL_HIGH>,
+					     <0 91 IRQ_TYPE_LEVEL_HIGH>;
 				#dma-cells = <1>;
 				#dma-channels = <8>;
 				#dma-requests = <32>;
+				clocks = <&l4_main_clk>;
+				clock-names = "apb_pclk";
 			};
 		};
 
@@ -362,6 +365,7 @@
 						compatible = "altr,socfpga-a10-gate-clk";
 						clocks = <&sdmmc_free_clk>;
 						clk-gate = <0xC8 5>;
+						clk-phase = <0 135>;
 					};
 
 					qspi_clk: qspi_clk {
@@ -589,7 +593,7 @@
 			reg = <0xff808000 0x1000>;
 			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 			fifo-depth = <0x400>;
-			clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
+			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 			clock-names = "biu", "ciu";
 			status = "disabled";
 		};
@@ -599,6 +603,26 @@
 			reg = <0xffe00000 0x40000>;
 		};
 
+		eccmgr: eccmgr@ffd06000 {
+			compatible = "altr,socfpga-a10-ecc-manager";
+			altr,sysmgr-syscon = <&sysmgr>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 0 IRQ_TYPE_LEVEL_HIGH>;
+			ranges;
+
+			l2-ecc@ffd06010 {
+				compatible = "altr,socfpga-a10-l2-ecc";
+				reg = <0xffd06010 0x4>;
+			};
+
+			ocram-ecc@ff8c3000 {
+				compatible = "altr,socfpga-a10-ocram-ecc";
+				reg = <0xff8c3000 0x400>;
+			};
+		};
+
 		rst: rstmgr@ffd05000 {
 			#reset-cells = <1>;
 			compatible = "altr,rst-mgr";
@@ -689,6 +713,8 @@
 			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&usb_clk>;
 			clock-names = "otg";
+			resets = <&rst USB0_RESET>;
+			reset-names = "dwc2";
 			phys = <&usbphy0>;
 			phy-names = "usb2-phy";
 			status = "disabled";
@@ -700,6 +726,8 @@
 			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&usb_clk>;
 			clock-names = "otg";
+			resets = <&rst USB1_RESET>;
+			reset-names = "dwc2";
 			phys = <&usbphy0>;
 			phy-names = "usb2-phy";
 			status = "disabled";
diff --git a/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts b/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts
index dbbb751ac1ba..8a7dfa473e98 100644
--- a/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts
+++ b/sys/gnu/dts/arm/socfpga_arria10_socdk_sdmmc.dts
@@ -21,6 +21,7 @@
 &mmc {
 	status = "okay";
 	num-slots = <1>;
+	cap-sd-highspeed;
 	broken-cd;
 	bus-width = <4>;
 };
diff --git a/sys/gnu/dts/arm/socfpga_cyclone5.dtsi b/sys/gnu/dts/arm/socfpga_cyclone5.dtsi
index 06db951e06f8..a05e3df23103 100644
--- a/sys/gnu/dts/arm/socfpga_cyclone5.dtsi
+++ b/sys/gnu/dts/arm/socfpga_cyclone5.dtsi
@@ -38,12 +38,6 @@
 			cap-sd-highspeed;
 		};
 
-		ethernet@ff702000 {
-			phy-mode = "rgmii";
-			phy-addr = <0xffffffff>; /* probe for phy addr */
-			status = "okay";
-		};
-
 		sysmgr@ffd08000 {
 			cpu1-start-addr = <0xffd080c4>;
 		};
diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts b/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts
index b61f22f9ac9f..02e22f554ef0 100644
--- a/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts
+++ b/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts
@@ -39,6 +39,90 @@
 		ethernet0 = &gmac1;
 	};
 
+	leds {
+		compatible = "gpio-leds";
+
+		hps_led0 {
+			label = "hps:blue:led0";
+			gpios = <&portb 24 0>;	/* HPS_GPIO53 */
+			linux,default-trigger = "heartbeat";
+		};
+
+		hps_led1 {
+			label = "hps:blue:led1";
+			gpios = <&portb 25 0>;	/* HPS_GPIO54 */
+			linux,default-trigger = "heartbeat";
+		};
+
+		hps_led2 {
+			label = "hps:blue:led2";
+			gpios = <&portb 26 0>;	/* HPS_GPIO55 */
+			linux,default-trigger = "heartbeat";
+		};
+
+		hps_led3 {
+			label = "hps:blue:led3";
+			gpios = <&portb 27 0>;	/* HPS_GPIO56 */
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		hps_sw0 {
+			label = "hps_sw0";
+			gpios = <&portc 20 0>;	/* HPS_GPI7 */
+			linux,input-type = <5>;	/* EV_SW */
+			linux,code = <0x0>;	/* SW_LID */
+		};
+
+		hps_sw1 {
+			label = "hps_sw1";
+			gpios = <&portc 19 0>;	/* HPS_GPI6 */
+			linux,input-type = <5>;	/* EV_SW */
+			linux,code = <0x5>;	/* SW_DOCK */
+		};
+
+		hps_sw2 {
+			label = "hps_sw2";
+			gpios = <&portc 18 0>;	/* HPS_GPI5 */
+			linux,input-type = <5>;	/* EV_SW */
+			linux,code = <0xa>;	/* SW_KEYPAD_SLIDE */
+		};
+
+		hps_sw3 {
+			label = "hps_sw3";
+			gpios = <&portc 17 0>;	/* HPS_GPI4 */
+			linux,input-type = <5>;	/* EV_SW */
+			linux,code = <0xc>;	/* SW_ROTATE_LOCK */
+		};
+
+		hps_hkey0 {
+			label = "hps_hkey0";
+			gpios = <&portc 21 1>;	/* HPS_GPI8 */
+			linux,code = <187>;	/* KEY_F17 */
+		};
+
+		hps_hkey1 {
+			label = "hps_hkey1";
+			gpios = <&portc 22 1>;	/* HPS_GPI9 */
+			linux,code = <188>;	/* KEY_F18 */
+		};
+
+		hps_hkey2 {
+			label = "hps_hkey2";
+			gpios = <&portc 23 1>;	/* HPS_GPI10 */
+			linux,code = <189>;	/* KEY_F19 */
+		};
+
+		hps_hkey3 {
+			label = "hps_hkey3";
+			gpios = <&portc 24 1>;	/* HPS_GPI11 */
+			linux,code = <190>;	/* KEY_F20 */
+		};
+	};
+
 	regulator_3_3v: vcc3p3-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "VCC3P3";
@@ -61,7 +145,15 @@
 	rxc-skew-ps = <2000>;
 };
 
-&gpio2 {
+&gpio0 {	/* GPIO 0..29 */
+	status = "okay";
+};
+
+&gpio1 {	/* GPIO 30..57 */
+	status = "okay";
+};
+
+&gpio2 {	/* GPIO 58..66 (HLGPI 0..13 at offset 13) */
 	status = "okay";
 };
 
diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts b/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts
index 019dd2fea208..e1a61f20873f 100644
--- a/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts
+++ b/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts
@@ -36,6 +36,7 @@
 };
 
 &gmac1 {
+	phy-mode = "rgmii";
 	status = "okay";
 };
 
diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_vining_fpga.dts b/sys/gnu/dts/arm/socfpga_cyclone5_vining_fpga.dts
new file mode 100644
index 000000000000..b844473601d2
--- /dev/null
+++ b/sys/gnu/dts/arm/socfpga_cyclone5_vining_fpga.dts
@@ -0,0 +1,311 @@
+/*
+ *  Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "socfpga_cyclone5.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "samtec VIN|ING FPGA";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	aliases {
+		/*
+		 * This allow the ethaddr uboot environment variable contents
+		 * to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		hps_led0 {
+			label = "hps:green:led0";	/* ALIVE_LED_GR */
+			gpios = <&portb 19 0>;	/* HPS_GPIO48 */
+			linux,default-trigger = "heartbeat";
+		};
+
+		hps_led1 {
+			label = "hps:red:led0";		/* ALIVE_LED_RD */
+			gpios = <&portb 24 0>;	/* HPS_GPIO53 */
+			linux,default-trigger = "none";
+		};
+
+		hps_led2 {
+			label = "hps:green:led1";	/* LINK2HOST_LED_GR */
+			gpios = <&portb 25 0>;	/* HPS_GPIO54 */
+			linux,default-trigger = "heartbeat";
+		};
+
+		hps_led3 {
+			label = "hps:red:led1";		/* LINK2HOST_LED_RD */
+			gpios = <&portc 7 0>;	/* HPS_GPIO65 */
+			linux,default-trigger = "none";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		hps_temp0 {
+			label = "BTN_0";			/* TEMP_OS */
+			gpios = <&portc 18 GPIO_ACTIVE_LOW>;	/* HPS_GPIO60 */
+			linux,code = <BTN_0>;
+		};
+
+		hps_hkey0 {
+			label = "BTN_1";			/* DIS_PWR */
+			gpios = <&portc 19 GPIO_ACTIVE_LOW>;	/* HPS_GPIO61 */
+			linux,code = <BTN_1>;
+		};
+
+		hps_hkey1 {
+			label = "hps_hkey1";			/* POWER_DOWN */
+			gpios = <&portc 20 GPIO_ACTIVE_LOW>;	/* HPS_GPIO62 */
+			linux,code = <KEY_POWER>;
+		};
+	};
+
+	regulator-usb-nrst {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_nrst";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&portb 5 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <70000>;
+		enable-active-high;
+		regulator-always-on;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&phy1>;
+
+	snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <10000 10000 10000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy1: ethernet-phy@1 {
+			reg = <1>;
+			rxd0-skew-ps = <0>;
+			rxd1-skew-ps = <0>;
+			rxd2-skew-ps = <0>;
+			rxd3-skew-ps = <0>;
+			txen-skew-ps = <0>;
+			txc-skew-ps = <2600>;
+			rxdv-skew-ps = <0>;
+			rxc-skew-ps = <2000>;
+		};
+	};
+};
+
+&gpio0 {	/* GPIO 0..29 */
+	status = "okay";
+};
+
+&gpio1 {	/* GPIO 30..57 */
+	status = "okay";
+};
+
+&gpio2 {	/* GPIO 58..66 (HLGPI 0..13 at offset 13) */
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	gpio: pca9557@1f {
+		compatible = "nxp,pca9557";
+		reg = <0x1f>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	temp: lm75@48 {
+		compatible = "lm75";
+		reg = <0x48>;
+	};
+
+	at24@50 {
+		compatible = "at24,24c01";
+		pagesize = <8>;
+		reg = <0x50>;
+	};
+
+	i2cswitch@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			eeprom@51 {
+				compatible = "at,24c01";
+				pagesize = <8>;
+				reg = <0x51>;
+			};
+		};
+
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			eeprom@51 {
+				compatible = "at,24c01";
+				pagesize = <8>;
+				reg = <0x51>;
+			};
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			eeprom@51 {
+				compatible = "at,24c01";
+				pagesize = <8>;
+				reg = <0x51>;
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			eeprom@51 {
+				compatible = "at,24c01";
+				pagesize = <8>;
+				reg = <0x51>;
+			};
+		};
+
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+			eeprom@51 {
+				compatible = "at,24c01";
+				pagesize = <8>;
+				reg = <0x51>;
+			};
+		};
+
+		i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+			eeprom@51 {
+				compatible = "at,24c01";
+				pagesize = <8>;
+				reg = <0x51>;
+			};
+		};
+
+		i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			eeprom@51 {
+				compatible = "at,24c01";
+				pagesize = <8>;
+				reg = <0x51>;
+			};
+		};
+
+		i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+			eeprom@51 {
+				compatible = "at,24c01";
+				pagesize = <8>;
+				reg = <0x51>;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	at24@50 {
+		compatible = "at24,24c02";
+		pagesize = <8>;
+		reg = <0x50>;
+	};
+};
+
+&usb0 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/spear1310-evb.dts b/sys/gnu/dts/arm/spear1310-evb.dts
index e48857249ce7..84101e4eebbf 100644
--- a/sys/gnu/dts/arm/spear1310-evb.dts
+++ b/sys/gnu/dts/arm/spear1310-evb.dts
@@ -161,7 +161,7 @@
 				linux,code = <0x100>;
 				gpios = <&gpio0 7 0x4>;
 				debounce-interval = <20>;
-				gpio-key,wakeup = <1>;
+				wakeup-source;
 			};
 		};
 
diff --git a/sys/gnu/dts/arm/spear1340-evb.dts b/sys/gnu/dts/arm/spear1340-evb.dts
index c611f5606dfe..6565f3cb866f 100644
--- a/sys/gnu/dts/arm/spear1340-evb.dts
+++ b/sys/gnu/dts/arm/spear1340-evb.dts
@@ -223,7 +223,7 @@
 				linux,code = <0x100>;
 				gpios = <&gpio1 1 0x4>;
 				debounce-interval = <20>;
-				gpio-key,wakeup = <1>;
+				wakeup-source;
 			};
 		};
 
diff --git a/sys/gnu/dts/arm/spear13xx.dtsi b/sys/gnu/dts/arm/spear13xx.dtsi
index 14594ce8c18a..449acf0d8272 100644
--- a/sys/gnu/dts/arm/spear13xx.dtsi
+++ b/sys/gnu/dts/arm/spear13xx.dtsi
@@ -117,7 +117,7 @@
 			chan_priority = <1>;
 			block_size = <0xfff>;
 			dma-masters = <2>;
-			data_width = <3 3>;
+			data-width = <8 8>;
 		};
 
 		dma@eb000000 {
@@ -133,7 +133,7 @@
 			chan_allocation_order = <1>;
 			chan_priority = <1>;
 			block_size = <0xfff>;
-			data_width = <3 3>;
+			data-width = <8 8>;
 		};
 
 		fsmc: flash@b0000000 {
diff --git a/sys/gnu/dts/arm/spear320-hmi.dts b/sys/gnu/dts/arm/spear320-hmi.dts
index 0aa6fef5ce22..0d0da1f65f0e 100644
--- a/sys/gnu/dts/arm/spear320-hmi.dts
+++ b/sys/gnu/dts/arm/spear320-hmi.dts
@@ -141,7 +141,7 @@
 				linux,code = <0x100>;
 				gpios = <&stmpegpio 3 0x4>;
 				debounce-interval = <20>;
-				gpio-key,wakeup = <1>;
+				wakeup-source;
 			};
 
 			button@2 {
@@ -149,7 +149,7 @@
 				linux,code = <0x200>;
 				gpios = <&stmpegpio 2 0x4>;
 				debounce-interval = <20>;
-				gpio-key,wakeup = <1>;
+				wakeup-source;
 			};
 		};
 
diff --git a/sys/gnu/dts/arm/ste-ccu9540.dts b/sys/gnu/dts/arm/ste-ccu9540.dts
index c8b815819cfe..b3b9bb8e1aa8 100644
--- a/sys/gnu/dts/arm/ste-ccu9540.dts
+++ b/sys/gnu/dts/arm/ste-ccu9540.dts
@@ -49,7 +49,7 @@
 			cap-mmc-highspeed;
 			vmmc-supply = <&ab8500_ldo_aux3_reg>;
 
-			cd-gpios  = <&gpio7 6 0x4>; // 230
+			cd-gpios  = <&gpio7 6 GPIO_ACTIVE_HIGH>; // 230
 			cd-inverted;
 
 			status = "okay";
diff --git a/sys/gnu/dts/arm/ste-dbx5x0.dtsi b/sys/gnu/dts/arm/ste-dbx5x0.dtsi
index 341f5b7ed242..6ae56838bd3a 100644
--- a/sys/gnu/dts/arm/ste-dbx5x0.dtsi
+++ b/sys/gnu/dts/arm/ste-dbx5x0.dtsi
@@ -10,8 +10,10 @@
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mfd/dbx500-prcmu.h>
 #include <dt-bindings/arm/ux500_pm_domains.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "skeleton.dtsi"
 
 / {
@@ -203,14 +205,14 @@
 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
 			reg = <0xa0412000 0x1000>;
-			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 			cache-unified;
 			cache-level = <2>;
 		};
 
 		pmu {
 			compatible = "arm,cortex-a9-pmu";
-			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		pm_domains: pm_domains0 {
@@ -253,7 +255,7 @@
 			/* Nomadik System Timer */
 			compatible = "st,nomadik-mtu";
 			reg = <0xa03c6000 0x1000>;
-			interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 
 			clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 			clock-names = "timclk", "apb_pclk";
@@ -262,7 +264,7 @@
 		timer@a0410600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0xa0410600 0x20>;
-			interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 
 			clocks = <&smp_twd_clk>;
 		};
@@ -270,14 +272,14 @@
 		watchdog@a0410620 {
 			compatible = "arm,cortex-a9-twd-wdt";
 			reg = <0xa0410620 0x20>;
-			interrupts = <1 14 0x304>;
+			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
 			clocks = <&smp_twd_clk>;
 		};
 
 		rtc@80154000 {
 			compatible = "arm,rtc-pl031", "arm,primecell";
 			reg = <0x80154000 0x1000>;
-			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 
 			clocks = <&rtc_clk>;
 			clock-names = "apb_pclk";
@@ -287,7 +289,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8012e000 0x80>;
-			interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -302,7 +304,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8012e080 0x80>;
-			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -317,7 +319,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8000e000 0x80>;
-			interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -332,7 +334,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8000e080 0x80>;
-			interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -347,7 +349,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8000e100 0x80>;
-			interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -362,7 +364,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8000e180 0x80>;
-			interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -377,7 +379,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8011e000 0x80>;
-			interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -392,7 +394,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0x8011e080 0x80>;
-			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -407,7 +409,7 @@
 			compatible = "stericsson,db8500-gpio",
 				"st,nomadik-gpio";
 			reg =  <0xa03fe000 0x80>;
-			interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			st,supports-sleepmode;
@@ -429,7 +431,7 @@
 		usb_per5@a03e0000 {
 			compatible = "stericsson,db8500-musb";
 			reg = <0xa03e0000 0x10000>;
-			interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc";
 
 			dr_mode = "otg";
@@ -467,7 +469,7 @@
 			compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 			reg = <0x801C0000 0x1000 0x40010000 0x800>;
 			reg-names = "base", "lcpa";
-			interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 
 			#dma-cells = <3>;
 			memcpy-channels = <56 57 58 59 60>;
@@ -479,7 +481,7 @@
 			compatible = "stericsson,db8500-prcmu";
 			reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 			reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
-			interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			interrupt-controller;
@@ -597,7 +599,7 @@
 			ab8500 {
 				compatible = "stericsson,ab8500";
 				interrupt-parent = <&intc>;
-				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 
@@ -785,7 +787,7 @@
 		i2c@80004000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80004000 0x1000>;
-			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -800,7 +802,7 @@
 		i2c@80122000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80122000 0x1000>;
-			interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -816,7 +818,7 @@
 		i2c@80128000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80128000 0x1000>;
-			interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -832,7 +834,7 @@
 		i2c@80110000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x80110000 0x1000>;
-			interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -848,7 +850,7 @@
 		i2c@8012a000 {
 			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 			reg = <0x8012a000 0x1000>;
-			interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -864,7 +866,7 @@
 		ssp@80002000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x80002000 0x1000>;
-			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
@@ -878,7 +880,7 @@
 		ssp@80003000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x80003000 0x1000>;
-			interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
@@ -892,7 +894,7 @@
 		spi@8011a000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x8011a000 0x1000>;
-			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			/* Same clock wired to kernel and pclk */
@@ -907,7 +909,7 @@
 		spi@80112000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x80112000 0x1000>;
-			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			/* Same clock wired to kernel and pclk */
@@ -922,7 +924,7 @@
 		spi@80111000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x80111000 0x1000>;
-			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			/* Same clock wired to kernel and pclk */
@@ -937,7 +939,7 @@
 		spi@80129000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x80129000 0x1000>;
-			interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			/* Same clock wired to kernel and pclk */
@@ -952,7 +954,7 @@
 		ux500_serial0: uart@80120000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80120000 0x1000>;
-			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 			       <&dma 13 0 0x0>; /* Logical - MemToDev */
@@ -967,7 +969,7 @@
 		ux500_serial1: uart@80121000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80121000 0x1000>;
-			interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
 			       <&dma 12 0 0x0>; /* Logical - MemToDev */
@@ -982,7 +984,7 @@
 		ux500_serial2: uart@80007000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80007000 0x1000>;
-			interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
 			       <&dma 11 0 0x0>; /* Logical - MemToDev */
@@ -997,7 +999,7 @@
 		sdi0_per1@80126000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80126000 0x1000>;
-			interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
 			       <&dma 29 0 0x0>; /* Logical - MemToDev */
@@ -1013,7 +1015,7 @@
 		sdi1_per2@80118000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80118000 0x1000>;
-			interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
 			       <&dma 32 0 0x0>; /* Logical - MemToDev */
@@ -1029,7 +1031,7 @@
 		sdi2_per3@80005000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80005000 0x1000>;
-			interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
 			       <&dma 28 0 0x0>; /* Logical - MemToDev */
@@ -1045,7 +1047,7 @@
 		sdi3_per2@80119000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80119000 0x1000>;
-			interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
 			       <&dma 41 0 0x0>; /* Logical - MemToDev */
@@ -1061,7 +1063,7 @@
 		sdi4_per2@80114000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80114000 0x1000>;
-			interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
 			       <&dma 42 0 0x0>; /* Logical - MemToDev */
@@ -1077,7 +1079,7 @@
 		sdi5_per3@80008000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80008000 0x1000>;
-			interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 
 			dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
 			       <&dma 43 0 0x0>; /* Logical - MemToDev */
@@ -1093,7 +1095,7 @@
 		msp0: msp@80123000 {
 			compatible = "stericsson,ux500-msp-i2s";
 			reg = <0x80123000 0x1000>;
-			interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			v-ape-supply = <&db8500_vape_reg>;
 
 			dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
@@ -1109,7 +1111,7 @@
 		msp1: msp@80124000 {
 			compatible = "stericsson,ux500-msp-i2s";
 			reg = <0x80124000 0x1000>;
-			interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			v-ape-supply = <&db8500_vape_reg>;
 
 			/* This DMA channel only exist on DB8500 v1 */
@@ -1126,7 +1128,7 @@
 		msp2: msp@80117000 {
 			compatible = "stericsson,ux500-msp-i2s";
 			reg = <0x80117000 0x1000>;
-			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 			v-ape-supply = <&db8500_vape_reg>;
 
 			dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
@@ -1143,7 +1145,7 @@
 		msp3: msp@80125000 {
 			compatible = "stericsson,ux500-msp-i2s";
 			reg = <0x80125000 0x1000>;
-			interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			v-ape-supply = <&db8500_vape_reg>;
 
 			/* This DMA channel only exist on DB8500 v2 */
@@ -1176,7 +1178,7 @@
 			      <0xa0351000 0x1000>, /* DSI link 1 */
 			      <0xa0352000 0x1000>, /* DSI link 2 */
 			      <0xa0353000 0x1000>; /* DSI link 3 */
-			interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
 				 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
 				 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
@@ -1190,7 +1192,7 @@
 		cryp@a03cb000 {
 			compatible = "stericsson,ux500-cryp";
 			reg = <0xa03cb000 0x1000>;
-			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 
 			v-ape-supply = <&db8500_vape_reg>;
 			clocks = <&prcc_pclk 6 1>;
diff --git a/sys/gnu/dts/arm/ste-href-stuib.dtsi b/sys/gnu/dts/arm/ste-href-stuib.dtsi
index c3987ad06d79..6f720756057d 100644
--- a/sys/gnu/dts/arm/ste-href-stuib.dtsi
+++ b/sys/gnu/dts/arm/ste-href-stuib.dtsi
@@ -22,13 +22,13 @@
 
 		button@139 {
 			/* Proximity sensor */
-			gpios = <&gpio6 25 0x4>;
+			gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>;
 			linux,code = <11>; /* SW_FRONT_PROXIMITY */
 			label = "SFH7741 Proximity Sensor";
 		};
 		button@145 {
 			/* Hall sensor */
-			gpios = <&gpio4 17 0x4>;
+			gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
 			linux,code = <0>; /* SW_LID */
 			label = "HED54XXU11 Hall Effect Sensor";
 		};
diff --git a/sys/gnu/dts/arm/ste-href-tvk1281618.dtsi b/sys/gnu/dts/arm/ste-href-tvk1281618.dtsi
index b7b4211c5353..fc5e8ce700c3 100644
--- a/sys/gnu/dts/arm/ste-href-tvk1281618.dtsi
+++ b/sys/gnu/dts/arm/ste-href-tvk1281618.dtsi
@@ -24,20 +24,19 @@
 
 		button@139 {
 			/* Proximity sensor */
-			gpios = <&gpio6 25 0x4>;
+			gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>;
 			linux,code = <11>; /* SW_FRONT_PROXIMITY */
 			label = "SFH7741 Proximity Sensor";
 		};
 		button@145 {
 			/* Hall sensor */
-			gpios = <&gpio4 17 0x4>;
+			gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
 			linux,code = <0>; /* SW_LID */
 			label = "HED54XXU11 Hall Effect Sensor";
 		};
 	};
 
 	soc {
-		/* Add Synaptics touch screen, TC35893 keypad etc here */
 		i2c@80004000 {
 			tc35893@44 {
 				compatible = "toshiba,tc35893";
@@ -94,14 +93,15 @@
 				/* Accelerometer */
 				compatible = "st,lsm303dlh-accel";
 				st,drdy-int-pin = <1>;
+				drive-open-drain;
 				reg = <0x18>;
 				vdd-supply = <&ab8500_ldo_aux1_reg>;
 				vddio-supply = <&db8500_vsmps2_reg>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&accel_tvk_mode>;
 				interrupt-parent = <&gpio2>;
-				interrupts = <18 IRQ_TYPE_EDGE_RISING>,
-					     <19 IRQ_TYPE_EDGE_RISING>;
+				interrupts = <18 IRQ_TYPE_EDGE_FALLING>,
+					     <19 IRQ_TYPE_EDGE_FALLING>;
 			};
 			lsm303dlh@1e {
 				/*
@@ -119,14 +119,15 @@
 				/* Accelerometer */
 				compatible = "st,lis331dl-accel";
 				st,drdy-int-pin = <1>;
+				drive-open-drain;
 				reg = <0x1c>;
 				vdd-supply = <&ab8500_ldo_aux1_reg>;
 				vddio-supply = <&db8500_vsmps2_reg>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&accel_tvk_mode>;
 				interrupt-parent = <&gpio2>;
-				interrupts = <18 IRQ_TYPE_EDGE_RISING>,
-					     <19 IRQ_TYPE_EDGE_RISING>;
+				interrupts = <18 IRQ_TYPE_EDGE_FALLING>,
+					     <19 IRQ_TYPE_EDGE_FALLING>;
 			};
 			ak8974@0f {
 				/* Magnetometer */
@@ -159,6 +160,33 @@
 				vddio-supply = <&db8500_vsmps2_reg>;
 			};
 		};
+
+		i2c@80110000 {
+			synaptics@4b {
+				/* Synaptics RMI4 TM1217 touchscreen */
+				compatible = "syna,rmi4-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x4b>;
+				vdd-supply = <&ab8500_ldo_aux1_reg>;
+				vddio-supply = <&db8500_vsmps2_reg>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&synaptics_tvk_mode>;
+				interrupt-parent = <&gpio2>;
+				interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
+
+				rmi-f01@1 {
+					reg = <0x1>;
+					syna,nosleep = <1>;
+				};
+				rmi-f11@11 {
+					reg = <0x11>;
+					touchscreen-inverted-x;
+					syna,sensor-type = <1>;
+				};
+			};
+		};
+
 		pinctrl {
 			/* Pull up this GPIO pin */
 			tc35893 {
@@ -190,7 +218,7 @@
 					/* Accelerometer interrupt lines 1 & 2 */
 					tvk_cfg {
 						pins = "GPIO82_C1", "GPIO83_D3";
-						ste,config = <&gpio_in_pd>;
+						ste,config = <&gpio_in_pu>;
 					};
 				};
 			};
@@ -212,6 +240,15 @@
 					};
 				};
 			};
+			synaptics {
+				synaptics_tvk_mode: synaptics_tvk {
+					/* Touchscreen uses GPIO 84 */
+					tvk_cfg1 {
+						pins = "GPIO84_C2";
+						ste,config = <&gpio_in_pu>;
+					};
+				};
+			};
 		};
 	};
 };
diff --git a/sys/gnu/dts/arm/ste-hrefprev60.dtsi b/sys/gnu/dts/arm/ste-hrefprev60.dtsi
index b0278f4c486c..ece222d51717 100644
--- a/sys/gnu/dts/arm/ste-hrefprev60.dtsi
+++ b/sys/gnu/dts/arm/ste-hrefprev60.dtsi
@@ -18,7 +18,7 @@
 / {
 	gpio_keys {
 		button@1 {
-			gpios = <&tc3589x_gpio 7 0x4>;
+			gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -68,12 +68,12 @@
 
 		// External Micro SD slot
 		sdi0_per1@80126000 {
-			cd-gpios  = <&tc3589x_gpio 3 0x4>;
+			cd-gpios  = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>;
 		};
 
 		vmmci: regulator-gpio {
-			gpios = <&tc3589x_gpio 18 0x4>;
-			enable-gpio = <&tc3589x_gpio 17 0x4>;
+			gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>;
+			enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>;
 		};
 
 		pinctrl {
diff --git a/sys/gnu/dts/arm/ste-hrefv60plus.dtsi b/sys/gnu/dts/arm/ste-hrefv60plus.dtsi
index 149a72e7e37a..45d7af326718 100644
--- a/sys/gnu/dts/arm/ste-hrefv60plus.dtsi
+++ b/sys/gnu/dts/arm/ste-hrefv60plus.dtsi
@@ -20,12 +20,12 @@
 	soc {
 		// External Micro SD slot
 		sdi0_per1@80126000 {
-			cd-gpios  = <&gpio2 31 0x4>; // 95
+			cd-gpios  = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95
 		};
 
 		vmmci: regulator-gpio {
-			gpios = <&gpio0 5 0x4>;
-			enable-gpio = <&gpio5 9 0x4>;
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 		};
 
 		pinctrl {
diff --git a/sys/gnu/dts/arm/ste-nomadik-nhk15.dts b/sys/gnu/dts/arm/ste-nomadik-nhk15.dts
index 4a21c6492dbb..d35aa88791ad 100644
--- a/sys/gnu/dts/arm/ste-nomadik-nhk15.dts
+++ b/sys/gnu/dts/arm/ste-nomadik-nhk15.dts
@@ -57,8 +57,15 @@
 				};
 			};
 		};
+		lis3lv02dl {
+			lis3lv02dl_nhk_mode: lis3lv02dl_nhk {
+				nhk_cfg1 {
+					pins = "GPIO82_C10"; // IRQ line
+					ste,input = <0>;
+				};
+			};
+		};
 	};
-
 	src@101e0000 {
 		/* These chrystal outputs are not used on this board */
 		disable-sxtalo;
@@ -86,6 +93,10 @@
 		lis3lv02dl@1d {
 			/* Accelerometer */
 			compatible = "st,lis3lv02dl-accel";
+			interrupt-parent = <&gpio2>;
+			interrupts = <18 IRQ_TYPE_EDGE_RISING>; // GPIO 82
+			pinctrl-0 = <&lis3lv02dl_nhk_mode>;
+			pinctrl-names = "default";
 			reg = <0x1d>;
 		};
 		stmpe0: stmpe2401@43 {
diff --git a/sys/gnu/dts/arm/ste-nomadik-stn8815.dtsi b/sys/gnu/dts/arm/ste-nomadik-stn8815.dtsi
index d0c743853318..d2d532a9d783 100644
--- a/sys/gnu/dts/arm/ste-nomadik-stn8815.dtsi
+++ b/sys/gnu/dts/arm/ste-nomadik-stn8815.dtsi
@@ -127,22 +127,14 @@
 			};
 			mmcsd_default_mode: mmcsd_default {
 				mmcsd_default_cfg1 {
-					/* MCCLK */
-					pins = "GPIO8_B10";
-					ste,output = <0>;
-				};
-				mmcsd_default_cfg2 {
-					/* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */
-					pins = "GPIO10_C11", "GPIO15_A12",
-					"GPIO16_C13", "GPIO23_D15";
-					ste,output = <1>;
-				};
-				mmcsd_default_cfg3 {
-					/* MCCMD, MCDAT3-0, MCMSFBCLK */
-					pins = "GPIO9_A10", "GPIO11_B11",
-					"GPIO12_A11", "GPIO13_C12",
-					"GPIO14_B12", "GPIO24_C15";
-					ste,input = <1>;
+					/*
+					 * MCCLK, MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2
+					 * MCCMD, MCDAT3-0, MCMSFBCLK
+					 */
+					pins = "GPIO8_B10", "GPIO9_A10", "GPIO10_C11", "GPIO11_B11",
+					       "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO15_A12",
+					       "GPIO16_C13", "GPIO23_D15", "GPIO24_C15";
+					ste,output = <2>;
 				};
 			};
 		};
@@ -729,7 +721,7 @@
 	};
 
 	amba {
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
@@ -756,6 +748,9 @@
 			clocks = <&uart0clk>, <&pclkuart0>;
 			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
+			dmas = <&dmac0 14 1>,
+			       <&dmac0 15 1>;
+			dma-names = "rx", "tx";
 		};
 
 		uart1: uart@101fb000 {
@@ -767,6 +762,9 @@
 			clock-names = "uartclk", "apb_pclk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart1_default_mux>;
+			dmas = <&dmac1 22 1>,
+			       <&dmac1 23 1>;
+			dma-names = "rx", "tx";
 		};
 
 		uart2: uart@101f2000 {
@@ -777,6 +775,9 @@
 			clocks = <&uart2clk>, <&pclkuart2>;
 			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
+			dmas = <&dmac1 30 1>,
+			       <&dmac1 31 1>;
+			dma-names = "rx", "tx";
 		};
 
 		rng: rng@101b0000 {
@@ -802,13 +803,53 @@
 			clock-names = "mclk", "apb_pclk";
 			interrupt-parent = <&vica>;
 			interrupts = <22>;
-			max-frequency = <48000000>;
+			max-frequency = <400000>;
 			bus-width = <4>;
 			cap-mmc-highspeed;
 			cap-sd-highspeed;
+			full-pwr-cycle;
+			/*
+			 * The STw4811 circuit used with the Nomadik strictly
+			 * requires that all of these signal direction pins be
+			 * routed and used for its 4-bit levelshifter.
+			 */
+			st,sig-dir-dat0;
+			st,sig-dir-dat2;
+			st,sig-dir-dat31;
+			st,sig-dir-cmd;
+			st,sig-pin-fbclk;
 			pinctrl-names = "default";
 			pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
 			vmmc-supply = <&vmmc_regulator>;
 		};
+
+		dmac0: dma-controller@10130000 {
+			compatible = "arm,pl080", "arm,primecell";
+			reg = <0x10130000 0x1000>;
+			interrupt-parent = <&vica>;
+			interrupts = <15>;
+			clocks = <&hclkdma0>;
+			clock-names = "apb_pclk";
+			lli-bus-interface-ahb1;
+			lli-bus-interface-ahb2;
+			mem-bus-interface-ahb2;
+			memcpy-burst-size = <256>;
+			memcpy-bus-width = <32>;
+			#dma-cells = <2>;
+		};
+		dmac1: dma-controller@10150000 {
+			compatible = "arm,pl080", "arm,primecell";
+			reg = <0x10150000 0x1000>;
+			interrupt-parent = <&vica>;
+			interrupts = <13>;
+			clocks = <&hclkdma1>;
+			clock-names = "apb_pclk";
+			lli-bus-interface-ahb1;
+			lli-bus-interface-ahb2;
+			mem-bus-interface-ahb2;
+			memcpy-burst-size = <256>;
+			memcpy-bus-width = <32>;
+			#dma-cells = <2>;
+		};
 	};
 };
diff --git a/sys/gnu/dts/arm/ste-snowball.dts b/sys/gnu/dts/arm/ste-snowball.dts
index 08f82077b64d..36e84efc401c 100644
--- a/sys/gnu/dts/arm/ste-snowball.dts
+++ b/sys/gnu/dts/arm/ste-snowball.dts
@@ -50,35 +50,35 @@
 			wakeup-source;
 			linux,code = <2>;
 			label = "userpb";
-			gpios = <&gpio1 0 0x4>;
+			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 		};
 		button@2 {
 			debounce_interval = <50>;
 			wakeup-source;
 			linux,code = <3>;
 			label = "extkb1";
-			gpios = <&gpio4 23 0x4>;
+			gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
 		};
 		button@3 {
 			debounce_interval = <50>;
 			wakeup-source;
 			linux,code = <4>;
 			label = "extkb2";
-			gpios = <&gpio4 24 0x4>;
+			gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
 		};
 		button@4 {
 			debounce_interval = <50>;
 			wakeup-source;
 			linux,code = <5>;
 			label = "extkb3";
-			gpios = <&gpio5 1 0x4>;
+			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 		};
 		button@5 {
 			debounce_interval = <50>;
 			wakeup-source;
 			linux,code = <6>;
 			label = "extkb4";
-			gpios = <&gpio5 2 0x4>;
+			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -88,7 +88,7 @@
 		pinctrl-0 = <&gpioled_snowball_mode>;
 		used-led {
 			label = "user_led";
-			gpios = <&gpio4 14 0x4>;
+			gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 			linux,default-trigger = "heartbeat";
 		};
@@ -155,8 +155,8 @@
 		vmmci: regulator-gpio {
 			compatible = "regulator-gpio";
 
-			gpios = <&gpio7 4 0x4>;
-			enable-gpio = <&gpio6 25 0x4>;
+			gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
+			enable-gpio = <&gpio6 25 GPIO_ACTIVE_HIGH>;
 
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <2900000>;
@@ -182,8 +182,7 @@
 			pinctrl-0 = <&sdi0_default_mode>;
 			pinctrl-1 = <&sdi0_sleep_mode>;
 
-			cd-gpios  = <&gpio6 26 0x4>; // 218
-			cd-inverted;
+			cd-gpios  = <&gpio6 26 GPIO_ACTIVE_LOW>; // 218
 
 			status = "okay";
 		};
diff --git a/sys/gnu/dts/arm/ste-u300.dts b/sys/gnu/dts/arm/ste-u300.dts
index 9c73ac2842ad..2f5107ffeef0 100644
--- a/sys/gnu/dts/arm/ste-u300.dts
+++ b/sys/gnu/dts/arm/ste-u300.dts
@@ -384,7 +384,7 @@
 	};
 
 	amba {
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
diff --git a/sys/gnu/dts/arm/stih407-family.dtsi b/sys/gnu/dts/arm/stih407-family.dtsi
index 81f81214cdf9..d294e82447a2 100644
--- a/sys/gnu/dts/arm/stih407-family.dtsi
+++ b/sys/gnu/dts/arm/stih407-family.dtsi
@@ -15,6 +15,39 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gp0_reserved: rproc@40000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x40000000 0x01000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		gp1_reserved: rproc@41000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x41000000 0x01000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		audio_reserved: rproc@42000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x42000000 0x01000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		dmu_reserved: rproc@43000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x43000000 0x01000000>;
+			no-map;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -22,15 +55,35 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+
 			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
 			cpu-release-addr = <0x94100A4>;
+
+					 /* kHz     uV   */
+			operating-points = <1500000 0
+					    1200000 0
+					    800000  0
+					    500000  0>;
+
+			clocks = <&clk_m_a9>;
+			clock-names = "cpu";
+			clock-latency = <100000>;
+			cpu0-supply = <&pwm_regulator>;
+			st,syscfg = <&syscfg_core 0x8e0>;
 		};
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+
 			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
 			cpu-release-addr = <0x94100A4>;
+
+					 /* kHz     uV   */
+			operating-points = <1500000 0
+					    1200000 0
+					    800000  0
+					    500000  0>;
 		};
 	};
 
@@ -534,7 +587,7 @@
 			reg = <0x8788000 0x1000>;
 			interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
 			clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
-			st,lpc-mode = <ST_LPC_MODE_RTC>;
+			st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
 		};
 
 		sata0: sata@9b20000 {
@@ -694,5 +747,79 @@
 			clocks          = <&clk_sysin>;
 			status		= "okay";
 		};
+
+		mailbox0: mailbox@8f00000  {
+			compatible	= "st,stih407-mailbox";
+			reg		= <0x8f00000 0x1000>;
+			interrupts	= <GIC_SPI 1 IRQ_TYPE_NONE>;
+			#mbox-cells	= <2>;
+			mbox-name	= "a9";
+			status		= "okay";
+		};
+
+		mailbox1: mailbox@8f01000 {
+			compatible	= "st,stih407-mailbox";
+			reg		= <0x8f01000 0x1000>;
+			#mbox-cells	= <2>;
+			mbox-name	= "st231_gp_1";
+			status		= "okay";
+		};
+
+		mailbox2: mailbox@8f02000 {
+			compatible	= "st,stih407-mailbox";
+			reg		= <0x8f02000 0x1000>;
+			#mbox-cells	= <2>;
+			mbox-name	= "st231_gp_0";
+			status		= "okay";
+		};
+
+		mailbox3: mailbox@8f03000 {
+			compatible	= "st,stih407-mailbox";
+			reg		= <0x8f03000 0x1000>;
+			#mbox-cells	= <2>;
+			mbox-name	= "st231_audio_video";
+			status		= "okay";
+		};
+
+		st231_gp0: remote-processor {
+			compatible	= "st,st231-rproc";
+			memory-region	= <&gp0_reserved>;
+			resets		= <&softreset STIH407_ST231_GP0_SOFTRESET>;
+			reset-names	= "sw_reset";
+			clocks		= <&clk_s_c0_flexgen CLK_ST231_GP_0>;
+			clock-frequency	= <600000000>;
+			st,syscfg	= <&syscfg_core 0x22c>;
+		};
+
+
+		st231_gp1: remote-processor {
+			compatible	= "st,st231-rproc";
+			memory-region	= <&gp1_reserved>;
+			resets		= <&softreset STIH407_ST231_GP1_SOFTRESET>;
+			reset-names	= "sw_reset";
+			clocks		= <&clk_s_c0_flexgen CLK_ST231_GP_1>;
+			clock-frequency = <600000000>;
+			st,syscfg	= <&syscfg_core 0x220>;
+		};
+
+		st231_audio: remote-processor {
+			compatible	= "st,st231-rproc";
+			memory-region	= <&audio_reserved>;
+			resets		= <&softreset STIH407_ST231_AUD_SOFTRESET>;
+			reset-names	= "sw_reset";
+			clocks		= <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
+			clock-frequency	= <600000000>;
+			st,syscfg	= <&syscfg_core 0x228>;
+		};
+
+		st231_dmu: remote-processor {
+			compatible	= "st,st231-rproc";
+			memory-region	= <&dmu_reserved>;
+			resets		= <&softreset STIH407_ST231_DMU_SOFTRESET>;
+			reset-names	= "sw_reset";
+			clocks		= <&clk_s_c0_flexgen CLK_ST231_DMU>;
+			clock-frequency	= <600000000>;
+			st,syscfg	= <&syscfg_core 0x224>;
+		};
 	};
 };
diff --git a/sys/gnu/dts/arm/stm32429i-eval.dts b/sys/gnu/dts/arm/stm32429i-eval.dts
index 6964fc9e97cf..6bfc5959dac3 100644
--- a/sys/gnu/dts/arm/stm32429i-eval.dts
+++ b/sys/gnu/dts/arm/stm32429i-eval.dts
@@ -58,18 +58,68 @@
 	};
 
 	memory {
-		reg = <0xc0000000 0x2000000>;
+		reg = <0x00000000 0x2000000>;
 	};
 
 	aliases {
 		serial0 = &usart1;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+		green {
+			gpios = <&gpiog 6 1>;
+			linux,default-trigger = "heartbeat";
+		};
+		orange {
+			gpios = <&gpiog 7 1>;
+		};
+		red {
+			gpios = <&gpiog 10 1>;
+		};
+		blue {
+			gpios = <&gpiog 12 1>;
+		};
+	};
+
+	usbotg_hs_phy: usbphy {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+		clocks = <&rcc 0 30>;
+		clock-names = "main_clk";
+	};
 };
 
 &clk_hse {
 	clock-frequency = <25000000>;
 };
 
+&ethernet0 {
+	status = "okay";
+	pinctrl-0	= <&ethernet0_mii>;
+	pinctrl-names	= "default";
+	phy-mode	= "mii-id";
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy1: ethernet-phy@1 {
+			reg = <1>;
+		};
+	};
+};
+
 &usart1 {
+	pinctrl-0 = <&usart1_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usbotg_hs {
+	dr_mode = "host";
+	phys = <&usbotg_hs_phy>;
+	phy-names = "usb2-phy";
+	pinctrl-0 = <&usbotg_hs_pins_a>;
+	pinctrl-names = "default";
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/stm32f429-disco.dts b/sys/gnu/dts/arm/stm32f429-disco.dts
index f0b731db6f53..01408073dd53 100644
--- a/sys/gnu/dts/arm/stm32f429-disco.dts
+++ b/sys/gnu/dts/arm/stm32f429-disco.dts
@@ -64,6 +64,17 @@
 	aliases {
 		serial0 = &usart1;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+		red {
+			gpios = <&gpiog 14 0>;
+		};
+		green {
+			gpios = <&gpiog 13 0>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
 };
 
 &clk_hse {
@@ -71,5 +82,7 @@
 };
 
 &usart1 {
+	pinctrl-0 = <&usart1_pins_a>;
+	pinctrl-names = "default";
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/stm32f429.dtsi b/sys/gnu/dts/arm/stm32f429.dtsi
index 5e1e234e8c0a..35df462559ca 100644
--- a/sys/gnu/dts/arm/stm32f429.dtsi
+++ b/sys/gnu/dts/arm/stm32f429.dtsi
@@ -46,6 +46,7 @@
  */
 
 #include "armv7-m.dtsi"
+#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
 
 / {
 	clocks {
@@ -57,6 +58,8 @@
 	};
 
 	soc {
+		dma-ranges = <0xc0000000 0x0 0x10000000>;
+
 		timer2: timer@40000000 {
 			compatible = "st,stm32-timer";
 			reg = <0x40000000 0x400>;
@@ -168,6 +171,160 @@
 			status = "disabled";
 		};
 
+		syscfg: system-config@40013800 {
+			compatible = "syscon";
+			reg = <0x40013800 0x400>;
+		};
+
+		pin-controller {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "st,stm32f429-pinctrl";
+			ranges = <0 0x40020000 0x3000>;
+			pins-are-numbered;
+
+			gpioa: gpio@40020000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x0 0x400>;
+				clocks = <&rcc 0 0>;
+				st,bank-name = "GPIOA";
+			};
+
+			gpiob: gpio@40020400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x400 0x400>;
+				clocks = <&rcc 0 1>;
+				st,bank-name = "GPIOB";
+			};
+
+			gpioc: gpio@40020800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x800 0x400>;
+				clocks = <&rcc 0 2>;
+				st,bank-name = "GPIOC";
+			};
+
+			gpiod: gpio@40020c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0xc00 0x400>;
+				clocks = <&rcc 0 3>;
+				st,bank-name = "GPIOD";
+			};
+
+			gpioe: gpio@40021000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1000 0x400>;
+				clocks = <&rcc 0 4>;
+				st,bank-name = "GPIOE";
+			};
+
+			gpiof: gpio@40021400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1400 0x400>;
+				clocks = <&rcc 0 5>;
+				st,bank-name = "GPIOF";
+			};
+
+			gpiog: gpio@40021800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1800 0x400>;
+				clocks = <&rcc 0 6>;
+				st,bank-name = "GPIOG";
+			};
+
+			gpioh: gpio@40021c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x1c00 0x400>;
+				clocks = <&rcc 0 7>;
+				st,bank-name = "GPIOH";
+			};
+
+			gpioi: gpio@40022000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x2000 0x400>;
+				clocks = <&rcc 0 8>;
+				st,bank-name = "GPIOI";
+			};
+
+			gpioj: gpio@40022400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x2400 0x400>;
+				clocks = <&rcc 0 9>;
+				st,bank-name = "GPIOJ";
+			};
+
+			gpiok: gpio@40022800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x2800 0x400>;
+				clocks = <&rcc 0 10>;
+				st,bank-name = "GPIOK";
+			};
+
+			usart1_pins_a: usart1@0 {
+				pins1 {
+					pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
+					bias-disable;
+				};
+			};
+
+			usbotg_hs_pins_a: usbotg_hs@0 {
+				pins {
+					pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
+						 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
+						 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
+						 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
+						 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
+						 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
+						 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
+						 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
+						 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
+						 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
+						 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
+						 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			ethernet0_mii: mii@0 {
+				pins {
+					pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+						 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+						 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
+						 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
+						 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
+						 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+						 <STM32F429_PA2_FUNC_ETH_MDIO>,
+						 <STM32F429_PC1_FUNC_ETH_MDC>,
+						 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+						 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+						 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+						 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
+						 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
+						 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
+					slew-rate = <2>;
+				};
+			};
+		};
+
 		rcc: rcc@40023810 {
 			#clock-cells = <2>;
 			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
@@ -175,6 +332,62 @@
 			clocks = <&clk_hse>;
 		};
 
+		dma1: dma-controller@40026000 {
+			compatible = "st,stm32-dma";
+			reg = <0x40026000 0x400>;
+			interrupts = <11>,
+				     <12>,
+				     <13>,
+				     <14>,
+				     <15>,
+				     <16>,
+				     <17>,
+				     <47>;
+			clocks = <&rcc 0 21>;
+			#dma-cells = <4>;
+		};
+
+		dma2: dma-controller@40026400 {
+			compatible = "st,stm32-dma";
+			reg = <0x40026400 0x400>;
+			interrupts = <56>,
+				     <57>,
+				     <58>,
+				     <59>,
+				     <60>,
+				     <68>,
+				     <69>,
+				     <70>;
+			clocks = <&rcc 0 22>;
+			#dma-cells = <4>;
+			st,mem2mem;
+		};
+
+		ethernet0: dwmac@40028000 {
+			compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+			reg = <0x40028000 0x8000>;
+			reg-names = "stmmaceth";
+			interrupts = <61>, <62>;
+			interrupt-names = "macirq", "eth_wake_irq";
+			clock-names = "stmmaceth", "tx-clk", "rx-clk";
+			clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
+			st,syscon = <&syscfg 0x4>;
+			snps,pbl = <8>;
+			snps,mixed-burst;
+			dma-ranges;
+			status = "disabled";
+		};
+
+		usbotg_hs: usb@40040000 {
+			compatible = "snps,dwc2";
+			dma-ranges;
+			reg = <0x40040000 0x40000>;
+			interrupts = <77>;
+			clocks = <&rcc 0 29>;
+			clock-names = "otg";
+			status = "disabled";
+		};
+
 		rng: rng@50060800 {
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
diff --git a/sys/gnu/dts/arm/stm32f469-disco.dts b/sys/gnu/dts/arm/stm32f469-disco.dts
new file mode 100644
index 000000000000..e911af836471
--- /dev/null
+++ b/sys/gnu/dts/arm/stm32f469-disco.dts
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f429.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32F469i-DISCO board";
+	compatible = "st,stm32f469i-disco", "st,stm32f469";
+
+	chosen {
+		bootargs = "root=/dev/ram rdinit=/linuxrc";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x00000000 0x800000>;
+	};
+
+	aliases {
+		serial0 = &usart3;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <8000000>;
+};
+
+&usart3 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun4i-a10-a1000.dts b/sys/gnu/dts/arm/sun4i-a10-a1000.dts
index 97570cb7f2fc..c92a1ae33a1e 100644
--- a/sys/gnu/dts/arm/sun4i-a10-a1000.dts
+++ b/sys/gnu/dts/arm/sun4i-a10-a1000.dts
@@ -87,6 +87,24 @@
 		enable-active-high;
 		gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>;
 	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "On-board SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+		#sound-dai-cells = <0>;
+		compatible = "linux,spdif-dit";
+	};
 };
 
 &ahci {
@@ -188,6 +206,12 @@
 	status = "okay";
 };
 
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spdif_tx_pins_a>;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
diff --git a/sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts b/sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts
index 53660894ea95..023b03efa5ff 100644
--- a/sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts
+++ b/sys/gnu/dts/arm/sun4i-a10-chuwi-v7-cw0825.dts
@@ -45,6 +45,7 @@
 #include "sunxi-common-regulators.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "Chuwi V7 CW0825";
@@ -88,6 +89,15 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
+
+	ft5306de4: touchscreen@38 {
+		compatible = "edt,edt-ft5406";
+		reg = <0x38>;
+		interrupt-parent = <&pio>;
+		interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <1024>;
+		touchscreen-size-y = <768>;
+	};
 };
 
 &lradc {
diff --git a/sys/gnu/dts/arm/sun4i-a10-dserve-dsrv9703c.dts b/sys/gnu/dts/arm/sun4i-a10-dserve-dsrv9703c.dts
new file mode 100644
index 000000000000..893497e397da
--- /dev/null
+++ b/sys/gnu/dts/arm/sun4i-a10-dserve-dsrv9703c.dts
@@ -0,0 +1,281 @@
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Dserve DSRV9703C";
+	compatible = "dserve,dsrv9703c", "allwinner,sun4i-a10";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bl_en_pin_dsrv9703c>;
+		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <8>;
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	haptics {
+		compatible = "regulator-haptic";
+		haptic-supply = <&reg_motor>;
+		min-microvolt = <3000000>;
+		max-microvolt = <3000000>;
+	};
+
+	reg_motor: reg_motor {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&motor_pins>;
+		regulator-name = "vcc-motor";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		enable-active-high;
+		gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+	};
+};
+
+&codec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&codec_pa_pin>;
+	allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+
+	axp209: pmic@34 {
+		reg = <0x34>;
+		interrupts = <0>;
+	};
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	/* pull-ups and devices require AXP209 LDO3 */
+	status = "failed";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins_a>;
+	status = "okay";
+
+	ft5406ee8: touchscreen@38 {
+		compatible = "edt,edt-ft5406";
+		reg = <0x38>;
+		interrupt-parent = <&pio>;
+		interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+		reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>;
+		touchscreen-size-x = <1024>;
+		touchscreen-size-y = <768>;
+	};
+};
+
+&lradc {
+	vref-supply = <&reg_ldo2>;
+	status = "okay";
+
+	button@400 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <400000>;
+	};
+
+	button@800 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <800000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+	cd-inverted;
+	status = "okay";
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&pio {
+	bl_en_pin_dsrv9703c: bl_en_pin@0 {
+		allwinner,pins = "PH7";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	codec_pa_pin: codec_pa_pin@0 {
+		allwinner,pins = "PH15";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	motor_pins: motor_pins@0 {
+		allwinner,pins = "PB3";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	touchscreen_pins: touchscreen_pins@0 {
+		allwinner,pins = "PB13";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+		allwinner,pins = "PH5";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins_a>;
+	status = "okay";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1250000>;
+	regulator-max-microvolt = <1250000>;
+	regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+	regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_usb0_vbus {
+	status = "okay";
+};
+
+&reg_usb2_vbus {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
+	usb2_vbus-supply = <&reg_usb2_vbus>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts b/sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts
index 43f58fbe161c..9103864fef90 100644
--- a/sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts
+++ b/sys/gnu/dts/arm/sun4i-a10-hyundai-a7hd.dts
@@ -87,6 +87,30 @@
 	status = "okay";
 };
 
+&otg_sram {
+	status = "okay";
+};
+
+&pio {
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+		allwinner,pins = "PH5";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+	};
+};
+
+&reg_usb0_vbus {
+	status = "okay";
+};
+
 &reg_usb2_vbus {
 	gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
 	status = "okay";
@@ -102,7 +126,17 @@
 	allwinner,pins = "PH6";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/sun4i-a10-inet97fv2.dts b/sys/gnu/dts/arm/sun4i-a10-inet97fv2.dts
index 77c31dab86b1..04b0d2d1ae6c 100644
--- a/sys/gnu/dts/arm/sun4i-a10-inet97fv2.dts
+++ b/sys/gnu/dts/arm/sun4i-a10-inet97fv2.dts
@@ -48,6 +48,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "INet-97F Rev 02";
@@ -93,6 +94,15 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
+
+	ft5406ee8: touchscreen@38 {
+		compatible = "edt,edt-ft5406";
+		reg = <0x38>;
+		interrupt-parent = <&pio>;
+		interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+	};
 };
 
 &lradc {
diff --git a/sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts b/sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts
index ca49b0d0ce1e..bba4f9cf9bf5 100644
--- a/sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts
+++ b/sys/gnu/dts/arm/sun4i-a10-inet9f-rev03.dts
@@ -253,6 +253,15 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
+
+	ft5406ee8: touchscreen@38 {
+		compatible = "edt,edt-ft5406";
+		reg = <0x38>;
+		interrupt-parent = <&pio>;
+		interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+	};
 };
 
 &lradc {
diff --git a/sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts b/sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts
index 985e15503378..4e798f014c99 100644
--- a/sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts
+++ b/sys/gnu/dts/arm/sun4i-a10-itead-iteaduino-plus.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright 2015 Josef Gajdusek <atx@atx.name>
+ * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -42,22 +43,11 @@
 
 /dts-v1/;
 #include "sun4i-a10.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sunxi-itead-core-common.dtsi"
 
 / {
 	model = "Iteaduino Plus A10";
 	compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
 };
 
 &ahci {
@@ -65,18 +55,6 @@
 	status = "okay";
 };
 
-&cpu0 {
-	cpu-supply = <&reg_dcdc2>;
-};
-
-&ehci0 {
-	status = "okay";
-};
-
-&ehci1 {
-	status = "okay";
-};
-
 &emac {
 	pinctrl-names = "default";
 	pinctrl-0 = <&emac_pins_a>;
@@ -89,12 +67,7 @@
 };
 
 &i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins_a>;
-	status = "okay";
-
 	axp209: pmic@34 {
-		reg = <0x34>;
 		interrupts = <0>;
 	};
 };
@@ -135,68 +108,13 @@
 	status = "okay";
 };
 
-&ohci0 {
-	status = "okay";
-};
-
-&ohci1 {
-	status = "okay";
-};
-
 &reg_ahci_5v {
 	status = "okay";
 };
 
-#include "axp209.dtsi"
-
-&reg_dcdc2 {
-	regulator-always-on;
-	regulator-min-microvolt = <1000000>;
-	regulator-max-microvolt = <1450000>;
-	regulator-name = "vdd-cpu";
-};
-
-&reg_dcdc3 {
-	regulator-always-on;
-	regulator-min-microvolt = <1000000>;
-	regulator-max-microvolt = <1400000>;
-	regulator-name = "vdd-int-dll";
-};
-
-&reg_ldo1 {
-	regulator-name = "vdd-rtc";
-};
-
-&reg_ldo2 {
-	regulator-always-on;
-	regulator-min-microvolt = <3000000>;
-	regulator-max-microvolt = <3000000>;
-	regulator-name = "avcc";
-};
-
-&reg_usb1_vbus {
-	status = "okay";
-};
-
-&reg_usb2_vbus {
-	status = "okay";
-};
-
 &spi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi0_pins_a>,
 		    <&spi0_cs0_pins_a>;
 	status = "okay";
 };
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
-	status = "okay";
-};
-
-&usbphy {
-	usb1_vbus-supply = <&reg_usb1_vbus>;
-	usb2_vbus-supply = <&reg_usb2_vbus>;
-	status = "okay";
-};
diff --git a/sys/gnu/dts/arm/sun4i-a10-mk802.dts b/sys/gnu/dts/arm/sun4i-a10-mk802.dts
index ddf0683cbc6a..ee46ea854832 100644
--- a/sys/gnu/dts/arm/sun4i-a10-mk802.dts
+++ b/sys/gnu/dts/arm/sun4i-a10-mk802.dts
@@ -44,6 +44,7 @@
 #include "sun4i-a10.dtsi"
 #include "sunxi-common-regulators.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
 	model = "MK802";
@@ -84,7 +85,25 @@
 	status = "okay";
 };
 
+&otg_sram {
+	status = "okay";
+};
+
 &pio {
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+		allwinner,pins = "PH5";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
 	usb2_vbus_pin_mk802: usb2_vbus_pin@0 {
 		allwinner,pins = "PH12";
 		allwinner,function = "gpio_out";
@@ -93,6 +112,10 @@
 	};
 };
 
+&reg_usb0_vbus {
+	status = "okay";
+};
+
 &reg_usb1_vbus {
 	status = "okay";
 };
@@ -109,7 +132,17 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";
diff --git a/sys/gnu/dts/arm/sun4i-a10.dtsi b/sys/gnu/dts/arm/sun4i-a10.dtsi
index 2c8f5e6ad905..ca58eb279d55 100644
--- a/sys/gnu/dts/arm/sun4i-a10.dtsi
+++ b/sys/gnu/dts/arm/sun4i-a10.dtsi
@@ -65,8 +65,9 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-hdmi";
-			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
-				 <&ahb_gates 44>, <&dram_gates 26>;
+			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
+				 <&ahb_gates 43>, <&ahb_gates 44>,
+				 <&dram_gates 26>;
 			status = "disabled";
 		};
 
@@ -74,8 +75,9 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
-			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
-				 <&ahb_gates 44>, <&ahb_gates 46>,
+			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
+				 <&ahb_gates 43>, <&ahb_gates 44>,
+				 <&ahb_gates 46>,
 				 <&dram_gates 25>, <&dram_gates 26>;
 			status = "disabled";
 		};
@@ -84,9 +86,9 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_fe0-de_be0-lcd0";
-			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
-				 <&ahb_gates 46>, <&dram_gates 25>,
-				 <&dram_gates 26>;
+			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
+				 <&ahb_gates 44>, <&ahb_gates 46>,
+				 <&dram_gates 25>, <&dram_gates 26>;
 			status = "disabled";
 		};
 
@@ -94,9 +96,10 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
-			clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
-				 <&ahb_gates 44>, <&ahb_gates 46>,
-				 <&dram_gates 25>, <&dram_gates 26>;
+			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
+				 <&ahb_gates 36>, <&ahb_gates 44>,
+				 <&ahb_gates 46>,
+				 <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;
 			status = "disabled";
 		};
 	};
@@ -184,6 +187,15 @@
 			clock-output-names = "osc24M";
 		};
 
+		osc3M: osc3M_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+			clock-output-names = "osc3M";
+		};
+
 		osc32k: clk@0 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -208,6 +220,23 @@
 					     "pll2-4x", "pll2-8x";
 		};
 
+		pll3: clk@01c20010 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll3-clk";
+			reg = <0x01c20010 0x4>;
+			clocks = <&osc3M>;
+			clock-output-names = "pll3";
+		};
+
+		pll3x2: pll3x2_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <2>;
+			clocks = <&pll3>;
+			clock-output-names = "pll3-2x";
+		};
+
 		pll4: clk@01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -232,6 +261,23 @@
 			clock-output-names = "pll6_sata", "pll6_other", "pll6";
 		};
 
+		pll7: clk@01c20030 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll3-clk";
+			reg = <0x01c20030 0x4>;
+			clocks = <&osc3M>;
+			clock-output-names = "pll7";
+		};
+
+		pll7x2: pll7x2_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <2>;
+			clocks = <&pll7>;
+			clock-output-names = "pll7-2x";
+		};
+
 		/* dummy is 200M */
 		cpu: cpu@01c20054 {
 			#clock-cells = <0>;
@@ -477,6 +523,17 @@
 			clock-output-names = "ir1";
 		};
 
+		spdif_clk: clk@01c200c0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200c0 0x4>;
+			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+				 <&pll2 SUN4I_A10_PLL2_4X>,
+				 <&pll2 SUN4I_A10_PLL2_2X>,
+				 <&pll2 SUN4I_A10_PLL2_1X>;
+			clock-output-names = "spdif";
+		};
+
 		usb_clk: clk@01c200cc {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -1006,6 +1063,13 @@
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
+
+			spdif_tx_pins_a: spdif@0 {
+				allwinner,pins = "PB13";
+				allwinner,function = "spdif";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+			};
 		};
 
 		timer@01c20c00 {
@@ -1034,6 +1098,19 @@
 			status = "disabled";
 		};
 
+		spdif: spdif@01c21000 {
+			#sound-dai-cells = <0>;
+			compatible = "allwinner,sun4i-a10-spdif";
+			reg = <0x01c21000 0x400>;
+			interrupts = <13>;
+			clocks = <&apb0_gates 1>, <&spdif_clk>;
+			clock-names = "apb", "spdif";
+			dmas = <&dma SUN4I_DMA_NORMAL 2>,
+			       <&dma SUN4I_DMA_NORMAL 2>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
 		ir0: ir@01c21800 {
 			compatible = "allwinner,sun4i-a10-ir";
 			clocks = <&apb0_gates 6>, <&ir0_clk>;
diff --git a/sys/gnu/dts/arm/sun5i-a10s.dtsi b/sys/gnu/dts/arm/sun5i-a10s.dtsi
index bddd0de88af6..367f33012493 100644
--- a/sys/gnu/dts/arm/sun5i-a10s.dtsi
+++ b/sys/gnu/dts/arm/sun5i-a10s.dtsi
@@ -65,8 +65,8 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-hdmi";
-			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
-				 <&ahb_gates 44>;
+			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
+				 <&ahb_gates 43>, <&ahb_gates 44>;
 			status = "disabled";
 		};
 
@@ -74,7 +74,8 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0";
-			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
+				 <&ahb_gates 44>;
 			status = "disabled";
 		};
 
@@ -82,8 +83,8 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-tve0";
-			clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
-				 <&ahb_gates 44>;
+			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
+				 <&ahb_gates 36>, <&ahb_gates 44>;
 			status = "disabled";
 		};
 	};
diff --git a/sys/gnu/dts/arm/sun5i-a13-difrnce-dit4350.dts b/sys/gnu/dts/arm/sun5i-a13-difrnce-dit4350.dts
new file mode 100644
index 000000000000..6546fa02901d
--- /dev/null
+++ b/sys/gnu/dts/arm/sun5i-a13-difrnce-dit4350.dts
@@ -0,0 +1,226 @@
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Difrnce DIT4350";
+	compatible = "difrnce,dit4350", "allwinner,sun5i-a13";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <8>;
+		/* TODO: backlight uses axp gpio1 as enable pin */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+
+	axp209: pmic@34 {
+		reg = <0x34>;
+		interrupts = <0>;
+	};
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "okay";
+
+	pcf8563: rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+};
+
+&lradc {
+	vref-supply = <&reg_ldo2>;
+	status = "okay";
+
+	button@200 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <200000>;
+	};
+
+	button@400 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <400000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+	cd-inverted;
+	status = "okay";
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&pio {
+	mmc0_cd_pin_d709: mmc0_cd_pin@0 {
+		allwinner,pins = "PG0";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+		allwinner,pins = "PG1";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+	};
+
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PG2";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins>;
+	status = "okay";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1250000>;
+	regulator-max-microvolt = <1250000>;
+	regulator-name = "vdd-int-pll";
+};
+
+&reg_ldo1 {
+	regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_ldo3 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_usb0_vbus {
+	gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins_b>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb0_vbus_pin_a {
+	allwinner,pins = "PG12";
+};
+
+&usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+	usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
+	usb1_vbus-supply = <&reg_ldo3>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts b/sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts
index 7fbb0b0558a9..6efbba6d40a9 100644
--- a/sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts
+++ b/sys/gnu/dts/arm/sun5i-a13-empire-electronix-d709.dts
@@ -123,7 +123,7 @@
 
 &mmc0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>;
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
@@ -131,27 +131,12 @@
 	status = "okay";
 };
 
-&mmc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins_a>;
-	vmmc-supply = <&reg_vcc3v3>;
-	bus-width = <8>;
-	non-removable;
-	status = "okay";
-
-	mmccard: mmccard@0 {
-		reg = <0>;
-		compatible = "mmc-card";
-		broken-hpi;
-	};
-};
-
 &otg_sram {
 	status = "okay";
 };
 
 &pio {
-	mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 {
+	mmc0_cd_pin_d709: mmc0_cd_pin@0 {
 		allwinner,pins = "PG0";
 		allwinner,function = "gpio_in";
 		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
diff --git a/sys/gnu/dts/arm/sun5i-a13-inet-98v-rev2.dts b/sys/gnu/dts/arm/sun5i-a13-inet-98v-rev2.dts
index 6fa54b661423..1b11ec95ae53 100644
--- a/sys/gnu/dts/arm/sun5i-a13-inet-98v-rev2.dts
+++ b/sys/gnu/dts/arm/sun5i-a13-inet-98v-rev2.dts
@@ -123,21 +123,6 @@
 	status = "okay";
 };
 
-&mmc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins_a>;
-	vmmc-supply = <&reg_vcc3v3>;
-	bus-width = <8>;
-	non-removable;
-	status = "okay";
-
-	mmccard: mmccard@0 {
-		reg = <0>;
-		compatible = "mmc-card";
-		broken-hpi;
-	};
-};
-
 &otg_sram {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts b/sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts
index ad84fe4276c9..081329e2b80b 100644
--- a/sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts
+++ b/sys/gnu/dts/arm/sun5i-a13-olinuxino-micro.dts
@@ -109,6 +109,10 @@
 	status = "okay";
 };
 
+&otg_sram {
+	status = "okay";
+};
+
 &pio {
 	mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
 		allwinner,pins = "PG0";
@@ -124,6 +128,27 @@
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
 
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PG2";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+		allwinner,pins = "PG1";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+	};
+
+	usb0_vbus_pin_olinuxinom: usb0_vbus_pin@0 {
+		allwinner,pins = "PG12";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
 	usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 {
 		allwinner,pins = "PG11";
 		allwinner,function = "gpio_out";
@@ -132,6 +157,12 @@
 	};
 };
 
+&reg_usb0_vbus {
+	pinctrl-0 = <&usb0_vbus_pin_olinuxinom>;
+	gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
 &reg_usb1_vbus {
 	pinctrl-0 = <&usb1_vbus_pin_olinuxinom>;
 	gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
@@ -144,7 +175,17 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+	usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/sun5i-a13.dtsi b/sys/gnu/dts/arm/sun5i-a13.dtsi
index d910d3a6c41c..263d46dbc7e6 100644
--- a/sys/gnu/dts/arm/sun5i-a13.dtsi
+++ b/sys/gnu/dts/arm/sun5i-a13.dtsi
@@ -61,7 +61,8 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0";
-			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+			clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
+				 <&tcon_ch0_clk>, <&dram_gates 26>;
 			status = "disabled";
 		};
 	};
@@ -110,8 +111,8 @@
 					<10>, <13>,
 					<14>, <20>,
 					<21>, <22>,
-				        <28>, <32>, <36>,
-				        <40>, <44>,
+					<28>, <32>, <34>,
+					<36>, <40>, <44>,
 					<46>, <51>,
 					<52>;
 			clock-output-names = "ahb_usbotg", "ahb_ehci",
@@ -120,8 +121,8 @@
 					     "ahb_mmc2", "ahb_nand",
 					     "ahb_sdram", "ahb_spi0",
 					     "ahb_spi1", "ahb_spi2",
-					     "ahb_stimer", "ahb_ve", "ahb_lcd",
-					     "ahb_csi", "ahb_de_be",
+					     "ahb_stimer", "ahb_ve", "ahb_tve",
+					     "ahb_lcd", "ahb_csi", "ahb_de_be",
 					     "ahb_de_fe", "ahb_iep",
 					     "ahb_mali400";
 		};
@@ -149,6 +150,61 @@
 					     "apb1_i2c2", "apb1_uart1",
 					     "apb1_uart3";
 		};
+
+		dram_gates: clk@01c20100 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun5i-a13-dram-gates-clk",
+				     "allwinner,sun4i-a10-gates-clk";
+			reg = <0x01c20100 0x4>;
+			clocks = <&pll5 0>;
+			clock-indices = <0>,
+					<1>,
+					<25>,
+					<26>,
+					<29>,
+					<31>;
+			clock-output-names = "dram_ve",
+					     "dram_csi",
+					     "dram_de_fe",
+					     "dram_de_be",
+					     "dram_ace",
+					     "dram_iep";
+		};
+
+		de_be_clk: clk@01c20104 {
+			#clock-cells = <0>;
+			#reset-cells = <0>;
+			compatible = "allwinner,sun4i-a10-display-clk";
+			reg = <0x01c20104 0x4>;
+			clocks = <&pll3>, <&pll7>, <&pll5 1>;
+			clock-output-names = "de-be";
+		};
+
+		de_fe_clk: clk@01c2010c {
+			#clock-cells = <0>;
+			#reset-cells = <0>;
+			compatible = "allwinner,sun4i-a10-display-clk";
+			reg = <0x01c2010c 0x4>;
+			clocks = <&pll3>, <&pll7>, <&pll5 1>;
+			clock-output-names = "de-fe";
+		};
+
+		tcon_ch0_clk: clk@01c20118 {
+			#clock-cells = <0>;
+			#reset-cells = <1>;
+			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+			reg = <0x01c20118 0x4>;
+			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+			clock-output-names = "tcon-ch0-sclk";
+		};
+
+		tcon_ch1_clk: clk@01c2012c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+			reg = <0x01c2012c 0x4>;
+			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+			clock-output-names = "tcon-ch1-sclk";
+		};
 	};
 
 	soc@01c00000 {
diff --git a/sys/gnu/dts/arm/sun5i-r8-chip.dts b/sys/gnu/dts/arm/sun5i-r8-chip.dts
index 530ab28e9ca2..f694482bdeb6 100644
--- a/sys/gnu/dts/arm/sun5i-r8-chip.dts
+++ b/sys/gnu/dts/arm/sun5i-r8-chip.dts
@@ -52,7 +52,7 @@
 
 / {
 	model = "NextThing C.H.I.P.";
-	compatible = "nextthing,chip", "allwinner,sun5i-r8";
+	compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13";
 
 	aliases {
 		i2c0 = &i2c0;
@@ -66,10 +66,18 @@
 	};
 };
 
+&be0 {
+	status = "okay";
+};
+
 &codec {
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -184,6 +192,14 @@
 	status = "okay";
 };
 
+&tcon0 {
+	status = "okay";
+};
+
+&tve0 {
+	status = "okay";
+};
+
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart1_pins_b>;
diff --git a/sys/gnu/dts/arm/sun5i-r8.dtsi b/sys/gnu/dts/arm/sun5i-r8.dtsi
index 0ef865601ac9..c04cf690b858 100644
--- a/sys/gnu/dts/arm/sun5i-r8.dtsi
+++ b/sys/gnu/dts/arm/sun5i-r8.dtsi
@@ -51,9 +51,147 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-tve0";
-			clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
-				 <&ahb_gates 44>;
+			clocks = <&ahb_gates 34>, <&ahb_gates 36>,
+				 <&ahb_gates 44>, <&de_be_clk>,
+				 <&tcon_ch1_clk>, <&dram_gates 26>;
 			status = "disabled";
 		};
 	};
+
+	soc@01c00000 {
+		tve0: tv-encoder@01c0a000 {
+			compatible = "allwinner,sun4i-a10-tv-encoder";
+			reg = <0x01c0a000 0x1000>;
+			clocks = <&ahb_gates 34>;
+			resets = <&tcon_ch0_clk 0>;
+			status = "disabled";
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tve0_in_tcon0: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&tcon0_out_tve0>;
+				};
+			};
+		};
+
+		tcon0: lcd-controller@01c0c000 {
+			compatible = "allwinner,sun5i-a13-tcon";
+			reg = <0x01c0c000 0x1000>;
+			interrupts = <44>;
+			resets = <&tcon_ch0_clk 1>;
+			reset-names = "lcd";
+			clocks = <&ahb_gates 36>,
+				 <&tcon_ch0_clk>,
+				 <&tcon_ch1_clk>;
+			clock-names = "ahb",
+				      "tcon-ch0",
+				      "tcon-ch1";
+			clock-output-names = "tcon-pixel-clock";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				tcon0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					tcon0_in_be0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&be0_out_tcon0>;
+					};
+				};
+
+				tcon0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					tcon0_out_tve0: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&tve0_in_tcon0>;
+					};
+				};
+			};
+		};
+
+		fe0: display-frontend@01e00000 {
+			compatible = "allwinner,sun5i-a13-display-frontend";
+			reg = <0x01e00000 0x20000>;
+			interrupts = <47>;
+			clocks = <&ahb_gates 46>, <&de_fe_clk>,
+				 <&dram_gates 25>;
+			clock-names = "ahb", "mod",
+				      "ram";
+			resets = <&de_fe_clk>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				fe0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					fe0_out_be0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&be0_in_fe0>;
+					};
+				};
+			};
+		};
+
+		be0: display-backend@01e60000 {
+			compatible = "allwinner,sun5i-a13-display-backend";
+			reg = <0x01e60000 0x10000>;
+			clocks = <&ahb_gates 44>, <&de_be_clk>,
+				 <&dram_gates 26>;
+			clock-names = "ahb", "mod",
+				      "ram";
+			resets = <&de_be_clk>;
+			status = "disabled";
+
+			assigned-clocks = <&de_be_clk>;
+			assigned-clock-rates = <300000000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				be0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					be0_in_fe0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&fe0_out_be0>;
+					};
+				};
+
+				be0_out: port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+
+					be0_out_tcon0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon0_in_be0>;
+					};
+				};
+			};
+		};
+	};
+
+	display-engine {
+		compatible = "allwinner,sun5i-a13-display-engine";
+		allwinner,pipelines = <&fe0>;
+	};
 };
diff --git a/sys/gnu/dts/arm/sun5i.dtsi b/sys/gnu/dts/arm/sun5i.dtsi
index 59a9426e3bd4..0840612b5ed6 100644
--- a/sys/gnu/dts/arm/sun5i.dtsi
+++ b/sys/gnu/dts/arm/sun5i.dtsi
@@ -88,6 +88,15 @@
 			clock-output-names = "osc24M";
 		};
 
+		osc3M: osc3M_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+			clock-output-names = "osc3M";
+		};
+
 		osc32k: clk@0 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -112,6 +121,23 @@
 					     "pll2-4x", "pll2-8x";
 		};
 
+		pll3: clk@01c20010 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll3-clk";
+			reg = <0x01c20010 0x4>;
+			clocks = <&osc3M>;
+			clock-output-names = "pll3";
+		};
+
+		pll3x2: pll3x2_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <2>;
+			clocks = <&pll3>;
+			clock-output-names = "pll3-2x";
+		};
+
 		pll4: clk@01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -136,6 +162,23 @@
 			clock-output-names = "pll6_sata", "pll6_other", "pll6";
 		};
 
+		pll7: clk@01c20030 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll3-clk";
+			reg = <0x01c20030 0x4>;
+			clocks = <&osc3M>;
+			clock-output-names = "pll7";
+		};
+
+		pll7x2: pll7x2_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <2>;
+			clocks = <&pll7>;
+			clock-output-names = "pll7-2x";
+		};
+
 		/* dummy is 200M */
 		cpu: cpu@01c20054 {
 			#clock-cells = <0>;
diff --git a/sys/gnu/dts/arm/sun6i-a31.dtsi b/sys/gnu/dts/arm/sun6i-a31.dtsi
index b6ad7850fac6..1867af24ff52 100644
--- a/sys/gnu/dts/arm/sun6i-a31.dtsi
+++ b/sys/gnu/dts/arm/sun6i-a31.dtsi
@@ -709,6 +709,16 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			mmc3_8bit_emmc_pins: mmc3@1 {
+				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+						 "PC10", "PC11", "PC12",
+						 "PC13", "PC14", "PC15",
+						 "PC24";
+				allwinner,function = "mmc3";
+				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			gmac_pins_mii_a: gmac_mii@0 {
 				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 						"PA8", "PA9", "PA11",
diff --git a/sys/gnu/dts/arm/sun6i-a31s-colorfly-e708-q1.dts b/sys/gnu/dts/arm/sun6i-a31s-colorfly-e708-q1.dts
new file mode 100644
index 000000000000..e182eec6d878
--- /dev/null
+++ b/sys/gnu/dts/arm/sun6i-a31s-colorfly-e708-q1.dts
@@ -0,0 +1,208 @@
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Colorfly E708 Q1 tablet";
+	compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&reg_dcdc3>;
+};
+
+&ehci0 {
+	/* rtl8188etv wifi is connected here */
+	status = "okay";
+};
+
+&lradc {
+	vref-supply = <&reg_aldo3>;
+	status = "okay";
+
+	button@1000 {
+		label = "Home";
+		linux,code = <KEY_HOMEPAGE>;
+		channel = <0>;
+		voltage = <1000000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
+	cd-inverted;
+	status = "okay";
+};
+
+&pio {
+	mma8452_int_e708_q1: mma8452_int_pin@0 {
+		allwinner,pins = "PA9";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 {
+		allwinner,pins = "PA8";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&p2wi {
+	status = "okay";
+
+	axp22x: pmic@68 {
+		compatible = "x-powers,axp221";
+		reg = <0x68>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <700000>;
+	regulator-max-microvolt = <1320000>;
+	regulator-name = "vdd-cpus"; /* This is an educated guess */
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-min-microvolt = <700000>;
+	regulator-max-microvolt = <1320000>;
+	regulator-name = "vdd-gpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <700000>;
+	regulator-max-microvolt = <1320000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc4 {
+	regulator-always-on;
+	regulator-min-microvolt = <700000>;
+	regulator-max-microvolt = <1320000>;
+	regulator-name = "vdd-sys-dll";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-name = "vcc-pg";
+};
+
+&simplefb_lcd {
+	vcc-lcd-supply = <&reg_dc1sw>;
+	vcc-pg-supply = <&reg_dldo2>;
+};
+
+/*
+ * FIXME for now we only support host mode and rely on u-boot to have
+ * turned on Vbus which is controlled by the axp221 pmic on the board.
+ *
+ * Once we have axp221 power-supply and vbus-usb support we should switch
+ * to fully supporting otg.
+ */
+&usb_otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_dldo1>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun6i-a31s-primo81.dts b/sys/gnu/dts/arm/sun6i-a31s-primo81.dts
index 68b479b8772c..73c133f5e79c 100644
--- a/sys/gnu/dts/arm/sun6i-a31s-primo81.dts
+++ b/sys/gnu/dts/arm/sun6i-a31s-primo81.dts
@@ -176,8 +176,6 @@
 };
 
 &reg_dc1sw {
-	regulator-min-microvolt = <3000000>;
-	regulator-max-microvolt = <3000000>;
 	regulator-name = "vcc-lcd";
 };
 
diff --git a/sys/gnu/dts/arm/sun6i-a31s-sina31s-core.dtsi b/sys/gnu/dts/arm/sun6i-a31s-sina31s-core.dtsi
index ea69fb8ad4d8..4ec0c8679b2e 100644
--- a/sys/gnu/dts/arm/sun6i-a31s-sina31s-core.dtsi
+++ b/sys/gnu/dts/arm/sun6i-a31s-sina31s-core.dtsi
@@ -61,12 +61,14 @@
 };
 
 /* eMMC on core board */
-&mmc2 {
+&mmc3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+	pinctrl-0 = <&mmc3_8bit_emmc_pins>;
 	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_dcdc1>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
diff --git a/sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts b/sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts
index 360adfb1e9ca..d6ad6196a768 100644
--- a/sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts
+++ b/sys/gnu/dts/arm/sun6i-a31s-yones-toptech-bs1078-v2.dts
@@ -135,8 +135,6 @@
 
 &reg_dc1sw {
 	regulator-name = "vcc-lcd-usb2";
-	regulator-min-microvolt = <3000000>;
-	regulator-max-microvolt = <3000000>;
 };
 
 &reg_dc5ldo {
diff --git a/sys/gnu/dts/arm/sun7i-a20-cubietruck.dts b/sys/gnu/dts/arm/sun7i-a20-cubietruck.dts
index 8da939ab8350..83f39b0362cb 100644
--- a/sys/gnu/dts/arm/sun7i-a20-cubietruck.dts
+++ b/sys/gnu/dts/arm/sun7i-a20-cubietruck.dts
@@ -94,6 +94,24 @@
 		pinctrl-0 = <&mmc3_pwrseq_pin_cubietruck>;
 		reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
 	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "On-board SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+		#sound-dai-cells = <0>;
+		compatible = "linux,spdif-dit";
+	};
 };
 
 &ahci {
@@ -301,6 +319,12 @@
 	status = "okay";
 };
 
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spdif_tx_pins_a>;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
diff --git a/sys/gnu/dts/arm/sun7i-a20-itead-ibox.dts b/sys/gnu/dts/arm/sun7i-a20-itead-ibox.dts
new file mode 100644
index 000000000000..10d48cbf81ff
--- /dev/null
+++ b/sys/gnu/dts/arm/sun7i-a20-itead-ibox.dts
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-itead-core-common.dtsi"
+
+/ {
+	model = "Itead Ibox A20";
+	compatible = "itead,itead-ibox-a20", "allwinner,sun7i-a20";
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins_itead_core>;
+
+		green {
+			label = "itead_core:green:usr";
+			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		blue {
+			label = "itead_core:blue:usr";
+			gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "On-board SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	spdif_out: spdif-out {
+		#sound-dai-cells = <0>;
+		compatible = "linux,spdif-dit";
+	};
+};
+
+&ahci {
+	target-supply = <&reg_ahci_5v>;
+	status = "okay";
+};
+
+&codec {
+	status = "okay";
+};
+
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_pins_mii_a>;
+	phy = <&phy1>;
+	phy-mode = "mii";
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&i2c0 {
+	axp209: pmic@34 {
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&ir0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ir0_rx_pins_a>;
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+	cd-inverted;
+	status = "okay";
+};
+
+&pio {
+	led_pins_itead_core: led_pins@0 {
+		allwinner,pins = "PH20","PH21";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&reg_ahci_5v {
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spdif_tx_pins_a>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun7i-a20-lamobo-r1.dts b/sys/gnu/dts/arm/sun7i-a20-lamobo-r1.dts
new file mode 100644
index 000000000000..5ee43d8bf174
--- /dev/null
+++ b/sys/gnu/dts/arm/sun7i-a20-lamobo-r1.dts
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2015 Jelle de Jong <jelledejong@powercraft.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Lamobo R1";
+	compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart3;
+		serial2 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins_lamobo_r1>;
+
+		green {
+			label = "lamobo_r1:green:usr";
+			gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	reg_gmac_3v3: gmac-3v3 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gmac_power_pin_lamobo_r1>;
+		regulator-name = "gmac-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		enable-active-high;
+		gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+	};
+};
+
+&ahci_pwr_pin_a {
+	allwinner,pins = "PB3";
+};
+
+&ahci {
+	target-supply = <&reg_ahci_5v>;
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&gmac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_pins_rgmii_a>;
+	phy = <&phy1>;
+	phy-mode = "rgmii";
+	phy-supply = <&reg_gmac_3v3>;
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+
+	axp209: pmic@34 {
+		reg = <0x34>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins_a>;
+	status = "okay";
+};
+
+&ir0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ir0_rx_pins_a>;
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+	cd-inverted;
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&pio {
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 {
+		allwinner,pins = "PH10";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+
+	gmac_power_pin_lamobo_r1: gmac_power_pin@0 {
+		allwinner,pins = "PH23";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	led_pins_lamobo_r1: led_pins@0 {
+		allwinner,pins = "PH24";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+#include "axp209.dtsi"
+
+&reg_ahci_5v {
+	gpio = <&pio 1 3 0>; /* PB3 */
+	status = "okay";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+	regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_usb0_vbus {
+	status = "okay";
+};
+
+&reg_usb1_vbus {
+	status = "okay";
+};
+
+&reg_usb2_vbus {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins_a>,
+		    <&spi0_cs0_pins_a>,
+		    <&spi0_cs1_pins_a>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins_b>;
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart7_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>;
+	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_vbus_power-supply = <&usb_power_supply>;
+	usb0_vbus-supply = <&reg_usb0_vbus>;
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	usb2_vbus-supply = <&reg_usb2_vbus>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun7i-a20-mk808c.dts b/sys/gnu/dts/arm/sun7i-a20-mk808c.dts
index c9e648d17a1e..90ff4a267025 100644
--- a/sys/gnu/dts/arm/sun7i-a20-mk808c.dts
+++ b/sys/gnu/dts/arm/sun7i-a20-mk808c.dts
@@ -53,6 +53,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
 	model = "mk808c";
@@ -125,6 +126,30 @@
 	status = "okay";
 };
 
+&otg_sram {
+	status = "okay";
+};
+
+&pio {
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+		allwinner,pins = "PH5";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&reg_usb0_vbus {
+	status = "okay";
+};
+
 &reg_usb1_vbus {
 	status = "okay";
 };
@@ -145,7 +170,17 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";
diff --git a/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts b/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts
index c3c626b2cfa2..23aacce4d6c7 100644
--- a/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts
+++ b/sys/gnu/dts/arm/sun7i-a20-olimex-som-evb.dts
@@ -198,6 +198,10 @@
 	status = "okay";
 };
 
+&otg_sram {
+	status = "okay";
+};
+
 &pio {
 	ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin@1 {
 		allwinner,pins = "PC3";
@@ -219,6 +223,20 @@
 		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 	};
+
+	usb0_id_detect_pin: usb0_id_detect_pin@0 {
+		allwinner,pins = "PH4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+		allwinner,pins = "PH5";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
 };
 
 &reg_ahci_5v {
@@ -254,6 +272,10 @@
 	regulator-name = "avcc";
 };
 
+&reg_usb0_vbus {
+	status = "okay";
+};
+
 &reg_usb1_vbus {
 	status = "okay";
 };
@@ -268,7 +290,17 @@
 	status = "okay";
 };
 
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &usbphy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */
+	usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";
diff --git a/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2-emmc.dts b/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2-emmc.dts
new file mode 100644
index 000000000000..5ea4915f6d75
--- /dev/null
+++ b/sys/gnu/dts/arm/sun7i-a20-olinuxino-lime2-emmc.dts
@@ -0,0 +1,82 @@
+ /*
+ * Copyright 2015 - Ultimaker B.V.
+ * Author Olliver Schinagl <oliver@schinagl.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun7i-a20-olinuxino-lime2.dts"
+
+/ {
+	model = "Olimex A20-OLinuXino-LIME2-eMMC";
+	compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20";
+
+	mmc2_pwrseq: pwrseq {
+		pinctrl-0 = <&mmc2_pins_nrst>;
+		pinctrl-names = "default";
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pio {
+	mmc2_pins_nrst: mmc2@0 {
+		allwinner,pins = "PC16";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins_a>;
+	vmmc-supply = <&reg_vcc3v3>;
+	vqmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	non-removable;
+	mmc-pwrseq = <&mmc2_pwrseq>;
+	status = "okay";
+
+	emmc: emmc@0 {
+		reg = <0>;
+		compatible = "mmc-card";
+		broken-hpi;
+	};
+};
diff --git a/sys/gnu/dts/arm/sun7i-a20.dtsi b/sys/gnu/dts/arm/sun7i-a20.dtsi
index 0940a788f824..2c34bbbb9570 100644
--- a/sys/gnu/dts/arm/sun7i-a20.dtsi
+++ b/sys/gnu/dts/arm/sun7i-a20.dtsi
@@ -67,8 +67,9 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-hdmi";
-			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
-				 <&ahb_gates 44>, <&dram_gates 26>;
+			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
+				 <&ahb_gates 43>, <&ahb_gates 44>,
+				 <&dram_gates 26>;
 			status = "disabled";
 		};
 
@@ -76,8 +77,8 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0";
-			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
-				 <&dram_gates 26>;
+			clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
+				 <&ahb_gates 44>, <&dram_gates 26>;
 			status = "disabled";
 		};
 
@@ -85,8 +86,9 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-tve0";
-			clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
-				 <&ahb_gates 44>, <&dram_gates 26>;
+			clocks = <&pll3>, <&pll5 1>,
+				 <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>,
+				 <&dram_gates 5>, <&dram_gates 26>;
 			status = "disabled";
 		};
 	};
@@ -186,6 +188,15 @@
 			clock-output-names = "osc24M";
 		};
 
+		osc3M: osc3M_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <8>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+			clock-output-names = "osc3M";
+		};
+
 		osc32k: clk@0 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -210,6 +221,23 @@
 					     "pll2-4x", "pll2-8x";
 		};
 
+		pll3: clk@01c20010 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll3-clk";
+			reg = <0x01c20010 0x4>;
+			clocks = <&osc3M>;
+			clock-output-names = "pll3";
+		};
+
+		pll3x2: pll3x2_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&pll3>;
+			clock-div = <1>;
+			clock-mult = <2>;
+			clock-output-names = "pll3-2x";
+		};
+
 		pll4: clk@01c20018 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun7i-a20-pll4-clk";
@@ -235,6 +263,23 @@
 					     "pll6_div_4";
 		};
 
+		pll7: clk@01c20030 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-pll3-clk";
+			reg = <0x01c20030 0x4>;
+			clocks = <&osc3M>;
+			clock-output-names = "pll7";
+		};
+
+		pll7x2: pll7x2_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&pll7>;
+			clock-div = <1>;
+			clock-mult = <2>;
+			clock-output-names = "pll7-2x";
+		};
+
 		pll8: clk@01c20040 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun7i-a20-pll4-clk";
@@ -476,6 +521,17 @@
 			clock-output-names = "ir1";
 		};
 
+		spdif_clk: clk@01c200c0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod1-clk";
+			reg = <0x01c200c0 0x4>;
+			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+				 <&pll2 SUN4I_A10_PLL2_4X>,
+				 <&pll2 SUN4I_A10_PLL2_2X>,
+				 <&pll2 SUN4I_A10_PLL2_1X>;
+			clock-output-names = "spdif";
+		};
+
 		keypad_clk: clk@01c200c4 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -1193,6 +1249,13 @@
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
+
+			spdif_tx_pins_a: spdif@0 {
+				allwinner,pins = "PB13";
+				allwinner,function = "spdif";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+			};
 		};
 
 		timer@01c20c00 {
@@ -1226,6 +1289,19 @@
 			status = "disabled";
 		};
 
+		spdif: spdif@01c21000 {
+			#sound-dai-cells = <0>;
+			compatible = "allwinner,sun4i-a10-spdif";
+			reg = <0x01c21000 0x400>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb0_gates 1>, <&spdif_clk>;
+			clock-names = "apb", "spdif";
+			dmas = <&dma SUN4I_DMA_NORMAL 2>,
+			       <&dma SUN4I_DMA_NORMAL 2>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
 		ir0: ir@01c21800 {
 			compatible = "allwinner,sun4i-a10-ir";
 			clocks = <&apb0_gates 6>, <&ir0_clk>;
diff --git a/sys/gnu/dts/arm/sun8i-a23-a33.dtsi b/sys/gnu/dts/arm/sun8i-a23-a33.dtsi
index 6f88fb0ddbc7..7e05e09e61c7 100644
--- a/sys/gnu/dts/arm/sun8i-a23-a33.dtsi
+++ b/sys/gnu/dts/arm/sun8i-a23-a33.dtsi
@@ -381,7 +381,7 @@
 				allwinner,pins = "PC5", "PC6", "PC8",
 						 "PC9", "PC10", "PC11",
 						 "PC12", "PC13", "PC14",
-						 "PC15";
+						 "PC15", "PC16";
 				allwinner,function = "mmc2";
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
diff --git a/sys/gnu/dts/arm/sun8i-a23-gt90h-v4.dts b/sys/gnu/dts/arm/sun8i-a23-gt90h-v4.dts
index 1aeb06c649b9..b2ce284a65a2 100644
--- a/sys/gnu/dts/arm/sun8i-a23-gt90h-v4.dts
+++ b/sys/gnu/dts/arm/sun8i-a23-gt90h-v4.dts
@@ -47,15 +47,26 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
 
 / {
-	model = "Allwinner GT90H Quad Core Tablet (v4)";
-	compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a33";
+	model = "Allwinner GT90H Dual Core Tablet (v4)";
+	compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23";
 
 	aliases {
 		serial0 = &r_uart;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bl_en_pin_gt90h>;
+		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <8>;
+		enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+	};
+
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
@@ -106,8 +117,7 @@
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gt90h>;
-	/* FIXME this really is aldo1, correct once we've pmic support */
-	vmmc-supply = <&reg_vcc3v0>;
+	vmmc-supply = <&reg_aldo1>;
 	bus-width = <4>;
 	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
 	cd-inverted;
@@ -115,6 +125,13 @@
 };
 
 &pio {
+	bl_en_pin_gt90h: bl_en_pin@0 {
+		allwinner,pins = "PH6";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
 	mmc0_cd_pin_gt90h: mmc0_cd_pin@0 {
 		allwinner,pins = "PB4";
 		allwinner,function = "gpio_in";
@@ -123,12 +140,106 @@
 	};
 };
 
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins>;
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		eldoin-supply = <&reg_dcdc1>;
+	};
+};
+
 &r_uart {
 	pinctrl-names = "default";
 	pinctrl-0 = <&r_uart_pins_a>;
 	status = "okay";
 };
 
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2350000>;
+	regulator-max-microvolt = <2650000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&simplefb_lcd {
+	vcc-lcd-supply = <&reg_dc1sw>;
+};
+
 /*
  * FIXME for now we only support host mode and rely on u-boot to have
  * turned on Vbus which is controlled by the axp223 pmic on the board.
@@ -141,5 +252,6 @@
 };
 
 &usbphy {
+	usb1_vbus-supply = <&reg_dldo1>;
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/sun8i-a23-polaroid-mid2809pxe04.dts b/sys/gnu/dts/arm/sun8i-a23-polaroid-mid2809pxe04.dts
new file mode 100644
index 000000000000..cb5daafcb7c2
--- /dev/null
+++ b/sys/gnu/dts/arm/sun8i-a23-polaroid-mid2809pxe04.dts
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Polaroid MID2809PXE04 tablet";
+	compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23";
+
+	aliases {
+		serial0 = &r_uart;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bl_en_pin_mid2809>;
+		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <8>;
+		enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "okay";
+};
+
+&lradc {
+	vref-supply = <&reg_vcc3v0>;
+	status = "okay";
+
+	button@200 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <200000>;
+	};
+
+	button@400 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <400000>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mid2809>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+	cd-inverted;
+	status = "okay";
+};
+
+&pio {
+	bl_en_pin_mid2809: bl_en_pin@0 {
+		allwinner,pins = "PH6";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	mmc0_cd_pin_mid2809: mmc0_cd_pin@0 {
+		allwinner,pins = "PB4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins>;
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		eldoin-supply = <&reg_dcdc1>;
+	};
+};
+
+&r_uart {
+	pinctrl-names = "default";
+	pinctrl-0 = <&r_uart_pins_a>;
+	status = "okay";
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2350000>;
+	regulator-max-microvolt = <2650000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&simplefb_lcd {
+	vcc-lcd-supply = <&reg_dc1sw>;
+};
+
+/*
+ * FIXME for now we only support host mode and rely on u-boot to have
+ * turned on Vbus which is controlled by the axp223 pmic on the board.
+ *
+ * Once we have axp223 support we should switch to fully supporting otg.
+ */
+&usb_otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts b/sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts
index 13ce68f06dd6..fef6abc0a703 100644
--- a/sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts
+++ b/sys/gnu/dts/arm/sun8i-a33-sinlinx-sina33.dts
@@ -68,7 +68,7 @@
 };
 
 &lradc {
-	vref-supply = <&reg_vcc3v0>;
+	vref-supply = <&reg_dcdc1>;
 	status = "okay";
 
 	button@200 {
@@ -96,7 +96,7 @@
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
-	vmmc-supply = <&reg_vcc3v0>;
+	vmmc-supply = <&reg_dcdc1>;
 	bus-width = <4>;
 	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
 	cd-inverted;
@@ -106,13 +106,16 @@
 &mmc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc2_8bit_pins>;
-	vmmc-supply = <&reg_vcc3v0>;
+	vmmc-supply = <&reg_dcdc1>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
 &mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 	/* eMMC is missing pull-ups */
 	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 };
@@ -132,6 +135,76 @@
 
 &r_rsb {
 	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		eldoin-supply = <&reg_dcdc1>;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2350000>;
+	regulator-max-microvolt = <2650000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
 };
 
 &uart0 {
diff --git a/sys/gnu/dts/arm/sun8i-a83t-allwinner-h8homlet-v2.dts b/sys/gnu/dts/arm/sun8i-a83t-allwinner-h8homlet-v2.dts
new file mode 100644
index 000000000000..342e1d33fa1c
--- /dev/null
+++ b/sys/gnu/dts/arm/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+	model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
+	compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun8i-a83t-cubietruck-plus.dts b/sys/gnu/dts/arm/sun8i-a83t-cubietruck-plus.dts
new file mode 100644
index 000000000000..88b1e0970b8d
--- /dev/null
+++ b/sys/gnu/dts/arm/sun8i-a83t-cubietruck-plus.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+	model = "Cubietech Cubietruck Plus";
+	compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun8i-a83t.dtsi b/sys/gnu/dts/arm/sun8i-a83t.dtsi
new file mode 100644
index 000000000000..d3473f81b12f
--- /dev/null
+++ b/sys/gnu/dts/arm/sun8i-a83t.dtsi
@@ -0,0 +1,228 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ *
+ * Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <3>;
+		};
+
+		cpu@100 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0x100>;
+		};
+
+		cpu@101 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0x101>;
+		};
+
+		cpu@102 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0x102>;
+		};
+
+		cpu@103 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0x103>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* TODO: PRCM block has a mux for this. */
+		osc24M: osc24M_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		/*
+		 * This is called "internal OSC" in some places.
+		 * It is an internal RC-based oscillator.
+		 * TODO: Its controls are in the PRCM block.
+		 */
+		osc16M: osc16M_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <16000000>;
+			clock-output-names = "osc16M";
+		};
+
+		osc16Md512: osc16Md512_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <512>;
+			clock-mult = <1>;
+			clocks = <&osc16M>;
+			clock-output-names = "osc16M-d512";
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		pio: pinctrl@01c20800 {
+			compatible = "allwinner,sun8i-a83t-pinctrl";
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x01c20800 0x400>;
+			clocks = <&osc24M>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#gpio-cells = <3>;
+
+			mmc0_pins_a: mmc0@0 {
+				allwinner,pins = "PF0", "PF1", "PF2",
+						 "PF3", "PF4", "PF5";
+				allwinner,function = "mmc0";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart0_pins_a: uart0@0 {
+				allwinner,pins = "PF2", "PF4";
+				allwinner,function = "uart0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart0_pins_b: uart0@1 {
+				allwinner,pins = "PB9", "PB10";
+				allwinner,function = "uart0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+		};
+
+		timer@01c20c00 {
+			compatible = "allwinner,sun4i-a10-timer";
+			reg = <0x01c20c00 0xa0>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
+		watchdog@01c20ca0 {
+			compatible = "allwinner,sun6i-a31-wdt";
+			reg = <0x01c20ca0 0x20>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
+		uart0: serial@01c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&osc24M>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@01c81000 {
+			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x1000>,
+			      <0x01c84000 0x2000>,
+			      <0x01c86000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-2.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-2.dts
new file mode 100644
index 000000000000..f93f5d1695c4
--- /dev/null
+++ b/sys/gnu/dts/arm/sun8i-h3-orangepi-2.dts
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Xunlong Orange Pi 2";
+	compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+		status_led {
+			label = "orangepi:red:status";
+			gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+		};
+
+		pwr_led {
+			label = "orangepi:green:pwr";
+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	r_gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sw_r_opc>;
+
+		sw2 {
+			label = "sw2";
+			linux,code = <BTN_1>;
+			gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
+		};
+
+		sw4 {
+			label = "sw4";
+			linux,code = <BTN_0>;
+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_pwrseq_pin_orangepi>;
+		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&ir {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ir_pins_a>;
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_a>;
+	vmmc-supply = <&reg_vcc3v3>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&pio {
+	leds_opc: led_pins@0 {
+		allwinner,pins = "PA15";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_pio {
+	leds_r_opc: led_pins@0 {
+		allwinner,pins = "PL10";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	sw_r_opc: key_pins@0 {
+		allwinner,pins = "PL3", "PL4";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 {
+		allwinner,pins = "PL7";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&reg_usb1_vbus {
+	gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb1_vbus_pin_a {
+	allwinner,pins = "PG13";
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-one.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-one.dts
new file mode 100644
index 000000000000..0adf932fd923
--- /dev/null
+++ b/sys/gnu/dts/arm/sun8i-h3-orangepi-one.dts
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Xunlong Orange Pi One";
+	compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+		pwr_led {
+			label = "orangepi:green:pwr";
+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		status_led {
+			label = "orangepi:red:status";
+			gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	r_gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sw_r_opc>;
+
+		sw4 {
+			label = "sw4";
+			linux,code = <BTN_0>;
+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	cd-inverted;
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pio {
+	leds_opc: led_pins@0 {
+		allwinner,pins = "PA15";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_pio {
+	leds_r_opc: led_pins@0 {
+		allwinner,pins = "PL10";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	sw_r_opc: key_pins@0 {
+		allwinner,pins = "PL3";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	/* USB VBUS is always on */
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts
new file mode 100644
index 000000000000..daf50b9a6657
--- /dev/null
+++ b/sys/gnu/dts/arm/sun8i-h3-orangepi-pc.dts
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2015 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Xunlong Orange Pi PC";
+	compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
+
+		pwr_led {
+			label = "orangepi:green:pwr";
+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		status_led {
+			label = "orangepi:red:status";
+			gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	r_gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&sw_r_opc>;
+
+		sw4 {
+			label = "sw4";
+			linux,code = <BTN_0>;
+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&ehci2 {
+	status = "okay";
+};
+
+&ehci3 {
+	status = "okay";
+};
+
+&ir {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ir_pins_a>;
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	cd-inverted;
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&ohci2 {
+	status = "okay";
+};
+
+&ohci3 {
+	status = "okay";
+};
+
+&pio {
+	leds_opc: led_pins@0 {
+		allwinner,pins = "PA15";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&r_pio {
+	leds_r_opc: led_pins@0 {
+		allwinner,pins = "PL10";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
+	sw_r_opc: key_pins@0 {
+		allwinner,pins = "PL3";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	/* USB VBUS is always on */
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/sun8i-h3-orangepi-plus.dts b/sys/gnu/dts/arm/sun8i-h3-orangepi-plus.dts
index e67df590535f..b0cb41787e09 100644
--- a/sys/gnu/dts/arm/sun8i-h3-orangepi-plus.dts
+++ b/sys/gnu/dts/arm/sun8i-h3-orangepi-plus.dts
@@ -40,38 +40,56 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/dts-v1/;
-#include "sun8i-h3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+/* The Orange Pi Plus is an extended version of the Orange Pi 2 */
+#include "sun8i-h3-orangepi-2.dts"
 
 / {
 	model = "Xunlong Orange Pi Plus";
 	compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
 
-	aliases {
-		serial0 = &uart0;
+	reg_usb3_vbus: usb3-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3_vbus_pin_a>;
+		regulator-name = "usb3-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
 	};
+};
 
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
+&ehci3 {
+	status = "okay";
 };
 
-&mmc0 {
+&mmc2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	pinctrl-0 = <&mmc2_8bit_pins>;
 	vmmc-supply = <&reg_vcc3v3>;
-	bus-width = <4>;
-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-	cd-inverted;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins_a>;
-	status = "okay";
+&mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+	/* eMMC is missing pull-ups */
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&pio {
+	usb3_vbus_pin_a: usb3_vbus_pin@0 {
+		allwinner,pins = "PG11";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+};
+
+&usbphy {
+	usb3_vbus-supply = <&reg_usb3_vbus>;
 };
diff --git a/sys/gnu/dts/arm/sun8i-h3.dtsi b/sys/gnu/dts/arm/sun8i-h3.dtsi
index 1524130e43c9..4a4926b0b0ed 100644
--- a/sys/gnu/dts/arm/sun8i-h3.dtsi
+++ b/sys/gnu/dts/arm/sun8i-h3.dtsi
@@ -269,6 +269,18 @@
 					     "mmc2_sample";
 		};
 
+		usb_clk: clk@01c200cc {
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			compatible = "allwinner,sun8i-h3-usb-clk";
+			reg = <0x01c200cc 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "usb_phy0", "usb_phy1",
+					     "usb_phy2", "usb_phy3",
+					     "usb_ohci0", "usb_ohci1",
+					     "usb_ohci2", "usb_ohci3";
+		};
+
 		mbus_clk: clk@01c2015c {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun8i-a23-mbus-clk";
@@ -276,6 +288,33 @@
 			clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 			clock-output-names = "mbus";
 		};
+
+		apb0: apb0_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+			clock-output-names = "apb0";
+		};
+
+		apb0_gates: clk@01f01428 {
+			compatible = "allwinner,sun8i-h3-apb0-gates-clk",
+				     "allwinner,sun4i-a10-gates-clk";
+			reg = <0x01f01428 0x4>;
+			#clock-cells = <1>;
+			clocks = <&apb0>;
+			clock-indices = <0>, <1>;
+			clock-output-names = "apb0_pio", "apb0_ir";
+		};
+
+		ir_clk: ir_clk@01f01454 {
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01f01454 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc32k>, <&osc24M>;
+			clock-output-names = "ir";
+		};
 	};
 
 	soc {
@@ -350,6 +389,107 @@
 			#size-cells = <0>;
 		};
 
+		usbphy: phy@01c19400 {
+			compatible = "allwinner,sun8i-h3-usb-phy";
+			reg = <0x01c19400 0x2c>,
+			      <0x01c1a800 0x4>,
+			      <0x01c1b800 0x4>,
+			      <0x01c1c800 0x4>,
+			      <0x01c1d800 0x4>;
+			reg-names = "phy_ctrl",
+				    "pmu0",
+				    "pmu1",
+				    "pmu2",
+				    "pmu3";
+			clocks = <&usb_clk 8>,
+				 <&usb_clk 9>,
+				 <&usb_clk 10>,
+				 <&usb_clk 11>;
+			clock-names = "usb0_phy",
+				      "usb1_phy",
+				      "usb2_phy",
+				      "usb3_phy";
+			resets = <&usb_clk 0>,
+				 <&usb_clk 1>,
+				 <&usb_clk 2>,
+				 <&usb_clk 3>;
+			reset-names = "usb0_reset",
+				      "usb1_reset",
+				      "usb2_reset",
+				      "usb3_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
+		ehci1: usb@01c1b000 {
+			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+			reg = <0x01c1b000 0x100>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 25>, <&bus_gates 29>;
+			resets = <&ahb_rst 25>, <&ahb_rst 29>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci1: usb@01c1b400 {
+			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+			reg = <0x01c1b400 0x100>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 29>, <&bus_gates 25>,
+				 <&usb_clk 17>;
+			resets = <&ahb_rst 29>, <&ahb_rst 25>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ehci2: usb@01c1c000 {
+			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+			reg = <0x01c1c000 0x100>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 26>, <&bus_gates 30>;
+			resets = <&ahb_rst 26>, <&ahb_rst 30>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci2: usb@01c1c400 {
+			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+			reg = <0x01c1c400 0x100>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 30>, <&bus_gates 26>,
+				 <&usb_clk 18>;
+			resets = <&ahb_rst 30>, <&ahb_rst 26>;
+			phys = <&usbphy 2>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ehci3: usb@01c1d000 {
+			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+			reg = <0x01c1d000 0x100>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 27>, <&bus_gates 31>;
+			resets = <&ahb_rst 27>, <&ahb_rst 31>;
+			phys = <&usbphy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci3: usb@01c1d400 {
+			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+			reg = <0x01c1d400 0x100>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 31>, <&bus_gates 27>,
+				 <&usb_clk 19>;
+			resets = <&ahb_rst 31>, <&ahb_rst 27>;
+			phys = <&usbphy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
 		pio: pinctrl@01c20800 {
 			compatible = "allwinner,sun8i-h3-pinctrl";
 			reg = <0x01c20800 0x400>;
@@ -359,7 +499,7 @@
 			gpio-controller;
 			#gpio-cells = <3>;
 			interrupt-controller;
-			#interrupt-cells = <2>;
+			#interrupt-cells = <3>;
 
 			uart0_pins_a: uart0@0 {
 				allwinner,pins = "PA4", "PA5";
@@ -390,6 +530,16 @@
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
+
+			mmc2_8bit_pins: mmc2_8bit {
+				allwinner,pins = "PC5", "PC6", "PC8",
+						 "PC9", "PC10", "PC11",
+						 "PC12", "PC13", "PC14",
+						 "PC15", "PC16";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
 		};
 
 		ahb_rst: reset@01c202c0 {
@@ -493,5 +643,40 @@
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		apb0_reset: reset@01f014b0 {
+			reg = <0x01f014b0 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
+
+		ir: ir@01f02000 {
+			compatible = "allwinner,sun5i-a13-ir";
+			clocks = <&apb0_gates 1>, <&ir_clk>;
+			clock-names = "apb", "ir";
+			resets = <&apb0_reset 1>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x01f02000 0x40>;
+			status = "disabled";
+		};
+
+		r_pio: pinctrl@01f02c00 {
+			compatible = "allwinner,sun8i-h3-r-pinctrl";
+			reg = <0x01f02c00 0x400>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb0_gates 0>;
+			resets = <&apb0_reset 0>;
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			ir_pins_a: ir@0 {
+				allwinner,pins = "PL11";
+				allwinner,function = "s_cir_rx";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+		};
 	};
 };
diff --git a/sys/gnu/dts/arm/sun8i-q8-common.dtsi b/sys/gnu/dts/arm/sun8i-q8-common.dtsi
index 1a69231d2da5..346a49d805a7 100644
--- a/sys/gnu/dts/arm/sun8i-q8-common.dtsi
+++ b/sys/gnu/dts/arm/sun8i-q8-common.dtsi
@@ -56,7 +56,6 @@
 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 		default-brightness-level = <8>;
 		enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
-		/* backlight is powered by AXP223 DC1SW */
 	};
 
 	chosen {
@@ -67,7 +66,7 @@
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
-	vmmc-supply = <&reg_vcc3v0>;
+	vmmc-supply = <&reg_dcdc1>;
 	bus-width = <4>;
 	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
 	cd-inverted;
@@ -92,6 +91,80 @@
 
 &r_rsb {
 	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		eldoin-supply = <&reg_dcdc1>;
+	};
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2350000>;
+	regulator-max-microvolt = <2650000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
 };
 
 &r_uart {
@@ -99,3 +172,7 @@
 	pinctrl-0 = <&r_uart_pins_a>;
 	status = "okay";
 };
+
+&simplefb_lcd {
+	vcc-lcd-supply = <&reg_dc1sw>;
+};
diff --git a/sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts b/sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts
index 382bd9fc5647..eb2ccd0a3bd5 100644
--- a/sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts
+++ b/sys/gnu/dts/arm/sun9i-a80-cubieboard4.dts
@@ -111,9 +111,15 @@
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
+&mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
 &r_ir {
 	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/sun9i-a80-optimus.dts b/sys/gnu/dts/arm/sun9i-a80-optimus.dts
index c0060e4f7379..d7a20d92b114 100644
--- a/sys/gnu/dts/arm/sun9i-a80-optimus.dts
+++ b/sys/gnu/dts/arm/sun9i-a80-optimus.dts
@@ -109,17 +109,6 @@
 	status = "okay";
 };
 
-&i2c3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c3_pins_a>;
-	status = "okay";
-};
-
-&i2c3_pins_a {
-	/* Enable internal pull-up */
-	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-};
-
 &ohci0 {
 	status = "okay";
 };
@@ -174,9 +163,15 @@
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
+&mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
 &reg_usb1_vbus {
 	pinctrl-0 = <&usb1_vbus_pin_optimus>;
 	gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
@@ -206,17 +201,6 @@
 	status = "okay";
 };
 
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins_a>;
-	status = "okay";
-};
-
-&uart4_pins_a {
-	/* Enable internal pull-up */
-	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-};
-
 &usbphy1 {
 	phy-supply = <&reg_usb1_vbus>;
 	status = "okay";
diff --git a/sys/gnu/dts/arm/sun9i-a80.dtsi b/sys/gnu/dts/arm/sun9i-a80.dtsi
index e838f206f2a0..f68b3242b33a 100644
--- a/sys/gnu/dts/arm/sun9i-a80.dtsi
+++ b/sys/gnu/dts/arm/sun9i-a80.dtsi
@@ -543,7 +543,7 @@
 		};
 
 		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
 				 <&mmc0_clk 1>, <&mmc0_clk 2>;
@@ -557,7 +557,7 @@
 		};
 
 		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
 				 <&mmc1_clk 1>, <&mmc1_clk 2>;
@@ -571,7 +571,7 @@
 		};
 
 		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
 				 <&mmc2_clk 1>, <&mmc2_clk 2>;
@@ -585,7 +585,7 @@
 		};
 
 		mmc3: mmc@01c12000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c12000 0x1000>;
 			clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
 				 <&mmc3_clk 1>, <&mmc3_clk 2>;
@@ -704,7 +704,8 @@
 			mmc2_8bit_pins: mmc2_8bit {
 				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 						 "PC10", "PC11", "PC12",
-						 "PC13", "PC14", "PC15";
+						 "PC13", "PC14", "PC15",
+						 "PC16";
 				allwinner,function = "mmc2";
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
diff --git a/sys/gnu/dts/arm/sunxi-itead-core-common.dtsi b/sys/gnu/dts/arm/sunxi-itead-core-common.dtsi
new file mode 100644
index 000000000000..2565d5137a17
--- /dev/null
+++ b/sys/gnu/dts/arm/sunxi-itead-core-common.dtsi
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+
+	axp209: pmic@34 {
+		reg = <0x34>;
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+#include "axp209.dtsi"
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+	regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_usb1_vbus {
+	status = "okay";
+};
+
+&reg_usb2_vbus {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	usb2_vbus-supply = <&reg_usb2_vbus>;
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/tango4-common.dtsi b/sys/gnu/dts/arm/tango4-common.dtsi
index ef665d21d317..dd7eb5f624d9 100644
--- a/sys/gnu/dts/arm/tango4-common.dtsi
+++ b/sys/gnu/dts/arm/tango4-common.dtsi
@@ -3,11 +3,13 @@
  * https://github.com/mansr/linux-tangox
  */
 
-#define CPU_CLK 0
-#define SYS_CLK 1
-
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
+#define  CPU_CLK	0
+#define  SYS_CLK	1
+#define  USB_CLK	2
+#define SDIO_CLK	3
+
 / {
 	interrupt-parent = <&gic>;
 	#address-cells = <1>;
@@ -70,7 +72,7 @@
 
 		clkgen: clkgen@10000 {
 			compatible = "sigma,tango4-clkgen";
-			reg = <0x10000 0x40>;
+			reg = <0x10000 0x100>;
 			clocks = <&xtal>;
 			#clock-cells = <1>;
 		};
@@ -89,6 +91,12 @@
 			reg-shift = <2>;
 		};
 
+		watchdog@1fd00 {
+			compatible = "sigma,smp8759-wdt";
+			reg = <0x1fd00 8>;
+			clocks = <&xtal>;
+		};
+
 		eth0: ethernet@26000 {
 			compatible = "sigma,smp8734-ethernet";
 			reg = <0x26000 0x800>;
diff --git a/sys/gnu/dts/arm/tango4-smp8758.dtsi b/sys/gnu/dts/arm/tango4-smp8758.dtsi
index 7ed88ee629fb..d2e65c46bcc7 100644
--- a/sys/gnu/dts/arm/tango4-smp8758.dtsi
+++ b/sys/gnu/dts/arm/tango4-smp8758.dtsi
@@ -1,4 +1,4 @@
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "tango4-common.dtsi"
 
 / {
 	cpus {
@@ -11,6 +11,9 @@
 			next-level-cache = <&l2cc>;
 			device_type = "cpu";
 			reg = <0>;
+			clocks = <&clkgen CPU_CLK>;
+			clock-latency = <1>;
+			operating-points = <1215000 0 607500 0 405000 0 243000 0 135000 0>;
 		};
 
 		cpu1: cpu@1 {
@@ -28,4 +31,27 @@
 			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 			<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 	};
+
+	soc {
+		cpu_temp: thermal@920100 {
+			#thermal-sensor-cells = <0>;
+			compatible = "sigma,smp8758-thermal";
+			reg = <0x920100 12>;
+		};
+	};
+
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay = <997>;		/* milliseconds */
+			polling-delay-passive = <499>;	/* milliseconds */
+			thermal-sensors = <&cpu_temp>;
+			trips {
+				cpu_critical {
+					temperature = <120000>;
+					hysteresis = <2500>;
+					type = "critical";
+				};
+			};
+		};
+	};
 };
diff --git a/sys/gnu/dts/arm/tango4-vantage-1172.dts b/sys/gnu/dts/arm/tango4-vantage-1172.dts
index 3e5b9c81a51c..4cab64cb581e 100644
--- a/sys/gnu/dts/arm/tango4-vantage-1172.dts
+++ b/sys/gnu/dts/arm/tango4-vantage-1172.dts
@@ -1,7 +1,6 @@
 /dts-v1/;
 
 #include "tango4-smp8758.dtsi"
-#include "tango4-common.dtsi"
 
 / {
 	model = "Sigma Designs SMP8758 Vantage-1172 Rev E1";
diff --git a/sys/gnu/dts/arm/tegra114-dalmore.dts b/sys/gnu/dts/arm/tegra114-dalmore.dts
index 8b7aa0dcdc6e..c970bf65c74c 100644
--- a/sys/gnu/dts/arm/tegra114-dalmore.dts
+++ b/sys/gnu/dts/arm/tegra114-dalmore.dts
@@ -18,6 +18,10 @@
 		serial0 = &uartd;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x80000000 0x40000000>;
 	};
@@ -1164,7 +1168,7 @@
 			label = "Power";
 			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		volume_down {
diff --git a/sys/gnu/dts/arm/tegra114-roth.dts b/sys/gnu/dts/arm/tegra114-roth.dts
index 38acf78d7815..9d868af97b8e 100644
--- a/sys/gnu/dts/arm/tegra114-roth.dts
+++ b/sys/gnu/dts/arm/tegra114-roth.dts
@@ -1047,7 +1047,7 @@
 			label = "Power";
 			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra114-tn7.dts b/sys/gnu/dts/arm/tegra114-tn7.dts
index f91c2c9b2f94..89047edb5c5f 100644
--- a/sys/gnu/dts/arm/tegra114-tn7.dts
+++ b/sys/gnu/dts/arm/tegra114-tn7.dts
@@ -292,7 +292,7 @@
 			label = "Power";
 			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		volume_down {
diff --git a/sys/gnu/dts/arm/tegra114.dtsi b/sys/gnu/dts/arm/tegra114.dtsi
index d845bd1448b5..cb9393a53422 100644
--- a/sys/gnu/dts/arm/tegra114.dtsi
+++ b/sys/gnu/dts/arm/tegra114.dtsi
@@ -150,7 +150,7 @@
 	};
 
 	timer@60005000 {
-		compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
+		compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 		reg = <0x60005000 0x400>;
 		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@@ -256,7 +256,7 @@
 	 * driver and APB DMA based serial driver for higher baudrate
 	 * and performace. To enable the 8250 based driver, the compatible
 	 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
-	 * the APB DMA based serial driver, the comptible is
+	 * the APB DMA based serial driver, the compatible is
 	 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 	 */
 	uarta: serial@70006000 {
diff --git a/sys/gnu/dts/arm/tegra124-jetson-tk1.dts b/sys/gnu/dts/arm/tegra124-jetson-tk1.dts
index 66b4451eb2ca..941f36263c8f 100644
--- a/sys/gnu/dts/arm/tegra124-jetson-tk1.dts
+++ b/sys/gnu/dts/arm/tegra124-jetson-tk1.dts
@@ -12,7 +12,15 @@
 	aliases {
 		rtc0 = "/i2c@0,7000d000/pmic@40";
 		rtc1 = "/rtc@0,7000e000";
+
+		/* This order keeps the mapping DB9 connector <-> ttyS0 */
 		serial0 = &uartd;
+		serial1 = &uarta;
+		serial2 = &uartb;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
 	};
 
 	memory {
@@ -30,11 +38,17 @@
 		vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
 		avdd-pll-erefe-supply = <&avdd_1v05_run>;
 
+		/* Mini PCIe */
 		pci@1,0 {
+			phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-4}>;
+			phy-names = "pcie-0";
 			status = "okay";
 		};
 
+		/* Gigabit Ethernet */
 		pci@2,0 {
+			phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-2}>;
+			phy-names = "pcie-0";
 			status = "okay";
 		};
 	};
@@ -1367,6 +1381,28 @@
 		};
 	};
 
+	/*
+	 * First high speed UART, exposed on the expansion connector J3A2
+	 *   Pin 41: BR_UART1_TXD
+	 *   Pin 44: BR_UART1_RXD
+	 */
+	serial@70006000 {
+		compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
+		status = "okay";
+	};
+
+	/*
+	 * Second high speed UART, exposed on the expansion connector J3A2
+	 *   Pin 65: UART2_RXD
+	 *   Pin 68: UART2_TXD
+	 *   Pin 71: UART2_CTS_L
+	 *   Pin 74: UART2_RTS_L
+	 */
+	serial@70006040 {
+		compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
+		status = "okay";
+	};
+
 	/* DB9 serial port */
 	serial@0,70006300 {
 		status = "okay";
@@ -1647,6 +1683,9 @@
 	sata@0,70020000 {
 		status = "okay";
 
+		phys = <&{/padctl@0,7009f000/pads/sata/lanes/sata-0}>;
+		phy-names = "sata-0";
+
 		hvdd-supply = <&vdd_3v3_lp0>;
 		vddio-supply = <&vdd_1v05_run>;
 		avdd-supply = <&vdd_1v05_run>;
@@ -1659,28 +1698,107 @@
 		status = "okay";
 	};
 
+	usb@0,70090000 {
+		phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
+		       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
+		       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
+		       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
+		phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
+
+		avddio-pex-supply = <&vdd_1v05_run>;
+		dvddio-pex-supply = <&vdd_1v05_run>;
+		avdd-usb-supply = <&vdd_3v3_lp0>;
+		avdd-pll-utmip-supply = <&vddio_1v8>;
+		avdd-pll-erefe-supply = <&avdd_1v05_run>;
+		avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
+		hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
+		hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
+
+		status = "okay";
+	};
+
 	padctl@0,7009f000 {
-		pinctrl-0 = <&padctl_default>;
-		pinctrl-names = "default";
+		status = "okay";
 
-		padctl_default: pinmux {
-			usb3 {
-				nvidia,lanes = "pcie-0", "pcie-1";
-				nvidia,function = "usb3";
-				nvidia,iddq = <0>;
+		pads {
+			usb2 {
+				status = "okay";
+
+				lanes {
+					usb2-0 {
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+
+					usb2-1 {
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+
+					usb2-2 {
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+				};
 			};
 
 			pcie {
-				nvidia,lanes = "pcie-2", "pcie-3",
-					       "pcie-4";
-				nvidia,function = "pcie";
-				nvidia,iddq = <0>;
+				status = "okay";
+
+				lanes {
+					pcie-0 {
+						nvidia,function = "usb3-ss";
+						status = "okay";
+					};
+
+					pcie-2 {
+						nvidia,function = "pcie";
+						status = "okay";
+					};
+
+					pcie-4 {
+						nvidia,function = "pcie";
+						status = "okay";
+					};
+				};
 			};
 
 			sata {
-				nvidia,lanes = "sata-0";
-				nvidia,function = "sata";
-				nvidia,iddq = <0>;
+				status = "okay";
+
+				lanes {
+					sata-0 {
+						nvidia,function = "sata";
+						status = "okay";
+					};
+				};
+			};
+		};
+
+		ports {
+			/* Micro A/B */
+			usb2-0 {
+				status = "okay";
+				mode = "otg";
+			};
+
+			/* Mini PCIe */
+			usb2-1 {
+				status = "okay";
+				mode = "host";
+			};
+
+			/* USB3 */
+			usb2-2 {
+				status = "okay";
+				mode = "host";
+
+				vbus-supply = <&vdd_usb3_vbus>;
+			};
+
+			usb3-0 {
+				nvidia,usb2-companion = <2>;
+				status = "okay";
 			};
 		};
 	};
@@ -1761,7 +1879,7 @@
 			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra124-nyan.dtsi b/sys/gnu/dts/arm/tegra124-nyan.dtsi
index ec1aa64ded68..0710a600cc69 100644
--- a/sys/gnu/dts/arm/tegra124-nyan.dtsi
+++ b/sys/gnu/dts/arm/tegra124-nyan.dtsi
@@ -8,6 +8,10 @@
 		serial0 = &uarta;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
@@ -220,7 +224,7 @@
 					regulator-always-on;
 				};
 
-				ldo0 {
+				avdd_1v05_run: ldo0 {
 					regulator-name = "+1.05V_RUN_AVDD";
 					regulator-min-microvolt = <1050000>;
 					regulator-max-microvolt = <1050000>;
@@ -364,6 +368,99 @@
 		status = "okay";
 	};
 
+	usb@0,70090000 {
+		phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
+		       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
+		       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
+		       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
+		       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
+		phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
+
+		avddio-pex-supply = <&vdd_1v05_run>;
+		dvddio-pex-supply = <&vdd_1v05_run>;
+		avdd-usb-supply = <&vdd_3v3_lp0>;
+		avdd-pll-utmip-supply = <&vddio_1v8>;
+		avdd-pll-erefe-supply = <&avdd_1v05_run>;
+		avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
+		hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
+		hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
+
+		status = "okay";
+	};
+
+	padctl@0,7009f000 {
+		status = "okay";
+
+		pads {
+			usb2 {
+				status = "okay";
+
+				lanes {
+					usb2-0 {
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+
+					usb2-1 {
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+
+					usb2-2 {
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+				};
+			};
+
+			pcie {
+				status = "okay";
+
+				lanes {
+					pcie-0 {
+						nvidia,function = "usb3-ss";
+						status = "okay";
+					};
+
+					pcie-1 {
+						nvidia,function = "usb3-ss";
+						status = "okay";
+					};
+				};
+			};
+		};
+
+		ports {
+			usb2-0 {
+				vbus-supply = <&vdd_usb1_vbus>;
+				status = "okay";
+				mode = "otg";
+			};
+
+			usb2-1 {
+				vbus-supply = <&vdd_run_cam>;
+				status = "okay";
+				mode = "host";
+			};
+
+			usb2-2 {
+				vbus-supply = <&vdd_usb3_vbus>;
+				status = "okay";
+				mode = "host";
+			};
+
+			usb3-0 {
+				nvidia,usb2-companion = <0>;
+				status = "okay";
+			};
+
+			usb3-1 {
+				nvidia,usb2-companion = <1>;
+				status = "okay";
+			};
+		};
+	};
+
 	sdhci0_pwrseq: sdhci0_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 
@@ -410,33 +507,6 @@
 		};
 	};
 
-	usb@0,7d000000 { /* Rear external USB port. */
-		status = "okay";
-	};
-
-	usb-phy@0,7d000000 {
-		status = "okay";
-		vbus-supply = <&vdd_usb1_vbus>;
-	};
-
-	usb@0,7d004000 { /* Internal webcam. */
-		status = "okay";
-	};
-
-	usb-phy@0,7d004000 {
-		status = "okay";
-		vbus-supply = <&vdd_run_cam>;
-	};
-
-	usb@0,7d008000 { /* Left external USB port. */
-		status = "okay";
-	};
-
-	usb-phy@0,7d008000 {
-		status = "okay";
-		vbus-supply = <&vdd_usb3_vbus>;
-	};
-
 	backlight: backlight {
 		compatible = "pwm-backlight";
 
@@ -509,7 +579,7 @@
 			linux,input-type = <5>;
 			linux,code = <KEY_RESERVED>;
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		power {
@@ -517,7 +587,7 @@
 			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			debounce-interval = <30>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra124-venice2.dts b/sys/gnu/dts/arm/tegra124-venice2.dts
index cfbdf429b45d..973446d07182 100644
--- a/sys/gnu/dts/arm/tegra124-venice2.dts
+++ b/sys/gnu/dts/arm/tegra124-venice2.dts
@@ -13,6 +13,10 @@
 		serial0 = &uarta;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
@@ -753,7 +757,7 @@
 					regulator-always-on;
 				};
 
-				ldo0 {
+				avdd_1v05_run: ldo0 {
 					regulator-name = "+1.05V_RUN_AVDD";
 					regulator-min-microvolt = <1050000>;
 					regulator-max-microvolt = <1050000>;
@@ -895,6 +899,105 @@
 		status = "okay";
 	};
 
+	usb@0,70090000 {
+		phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
+		       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
+		       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
+		       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
+		       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
+		phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
+
+		avddio-pex-supply = <&vdd_1v05_run>;
+		dvddio-pex-supply = <&vdd_1v05_run>;
+		avdd-usb-supply = <&vdd_3v3_lp0>;
+		avdd-pll-utmip-supply = <&vddio_1v8>;
+		avdd-pll-erefe-supply = <&avdd_1v05_run>;
+		avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
+		hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
+		hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
+
+		status = "okay";
+	};
+
+	padctl@0,7009f000 {
+		pads {
+			usb2 {
+				status = "okay";
+
+				lanes {
+					usb2-0 {
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+
+					usb2-1 {
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+
+					usb2-2 {
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+				};
+			};
+
+			pcie {
+				status = "okay";
+
+				lanes {
+					pcie-0 {
+						nvidia,function = "usb3-ss";
+						status = "okay";
+					};
+
+					pcie-1 {
+						nvidia,function = "usb3-ss";
+						status = "okay";
+					};
+
+					pcie-1 {
+						nvidia,function = "usb3-ss";
+						status = "okay";
+					};
+				};
+			};
+		};
+
+		ports {
+			usb2-0 {
+				status = "okay";
+				mode = "otg";
+
+				vbus-supply = <&vdd_usb1_vbus>;
+			};
+
+			usb2-1 {
+				status = "okay";
+				mode = "host";
+
+				vbus-supply = <&vdd_run_cam>;
+			};
+
+			usb2-2 {
+				status = "okay";
+				mode = "host";
+
+				vbus-supply = <&vdd_usb3_vbus>;
+			};
+
+			usb3-0 {
+				nvidia,usb2-companion = <0>;
+				status = "okay";
+			};
+
+			usb3-1 {
+				nvidia,usb2-companion = <2>;
+				status = "okay";
+			};
+		};
+	};
+
 	sdhci@0,700b0400 {
 		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
@@ -975,7 +1078,7 @@
 			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra124.dtsi b/sys/gnu/dts/arm/tegra124.dtsi
index 68669f791c8b..ea4811870de2 100644
--- a/sys/gnu/dts/arm/tegra124.dtsi
+++ b/sys/gnu/dts/arm/tegra124.dtsi
@@ -2,7 +2,6 @@
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/memory/tegra124-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
-#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/tegra124-car.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
@@ -51,9 +50,6 @@
 		reset-names = "pex", "afi", "pcie_x";
 		status = "disabled";
 
-		phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
-		phy-names = "pcie";
-
 		pci@1,0 {
 			device_type = "pci";
 			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
@@ -208,7 +204,7 @@
 	};
 
 	timer@0,60005000 {
-		compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
+		compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 		reg = <0x0 0x60005000 0x0 0x400>;
 		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@@ -322,7 +318,7 @@
 	 * driver and APB DMA based serial driver for higher baudrate
 	 * and performace. To enable the 8250 based driver, the compatible
 	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
-	 * the APB DMA based serial driver, the comptible is
+	 * the APB DMA based serial driver, the compatible is
 	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 	 */
 	uarta: serial@0,70006000 {
@@ -622,8 +618,6 @@
 			 <&tegra_car 123>,
 			 <&tegra_car 129>;
 		reset-names = "sata", "sata-oob", "sata-cold";
-		phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
-		phy-names = "sata-phy";
 		status = "disabled";
 	};
 
@@ -642,13 +636,172 @@
 		status = "disabled";
 	};
 
+	usb@0,70090000 {
+		compatible = "nvidia,tegra124-xusb";
+		reg = <0x0 0x70090000 0x0 0x8000>,
+		      <0x0 0x70098000 0x0 0x1000>,
+		      <0x0 0x70099000 0x0 0x1000>;
+		reg-names = "hcd", "fpci", "ipfs";
+
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+
+		clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
+			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
+			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
+			 <&tegra_car TEGRA124_CLK_XUSB_SS>,
+			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
+			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
+			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
+			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
+			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
+			 <&tegra_car TEGRA124_CLK_CLK_M>,
+			 <&tegra_car TEGRA124_CLK_PLL_E>;
+		clock-names = "xusb_host", "xusb_host_src",
+			      "xusb_falcon_src", "xusb_ss",
+			      "xusb_ss_div2", "xusb_ss_src",
+			      "xusb_hs_src", "xusb_fs_src",
+			      "pll_u_480m", "clk_m", "pll_e";
+		resets = <&tegra_car 89>, <&tegra_car 156>,
+			 <&tegra_car 143>;
+		reset-names = "xusb_host", "xusb_ss", "xusb_src";
+
+		nvidia,xusb-padctl = <&padctl>;
+
+		status = "disabled";
+	};
+
 	padctl: padctl@0,7009f000 {
 		compatible = "nvidia,tegra124-xusb-padctl";
 		reg = <0x0 0x7009f000 0x0 0x1000>;
 		resets = <&tegra_car 142>;
 		reset-names = "padctl";
 
-		#phy-cells = <1>;
+		pads {
+			usb2 {
+				status = "disabled";
+
+				lanes {
+					usb2-0 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+
+					usb2-1 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+
+					usb2-2 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+				};
+			};
+
+			ulpi {
+				status = "disabled";
+
+				lanes {
+					ulpi-0 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+				};
+			};
+
+			hsic {
+				status = "disabled";
+
+				lanes {
+					hsic-0 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+
+					hsic-1 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+				};
+			};
+
+			pcie {
+				status = "disabled";
+
+				lanes {
+					pcie-0 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+
+					pcie-1 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+
+					pcie-2 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+
+					pcie-3 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+
+					pcie-4 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+				};
+			};
+
+			sata {
+				status = "disabled";
+
+				lanes {
+					sata-0 {
+						status = "disabled";
+						#phy-cells = <0>;
+					};
+				};
+			};
+		};
+
+		ports {
+			usb2-0 {
+				status = "disabled";
+			};
+
+			usb2-1 {
+				status = "disabled";
+			};
+
+			usb2-2 {
+				status = "disabled";
+			};
+
+			ulpi-0 {
+				status = "disabled";
+			};
+
+			hsic-0 {
+				status = "disabled";
+			};
+
+			hsic-1 {
+				status = "disabled";
+			};
+
+			usb3-0 {
+				status = "disabled";
+			};
+
+			usb3-1 {
+				status = "disabled";
+			};
+		};
 	};
 
 	sdhci@0,700b0000 {
diff --git a/sys/gnu/dts/arm/tegra20-harmony.dts b/sys/gnu/dts/arm/tegra20-harmony.dts
index b926a07b9443..d2e960cbc001 100644
--- a/sys/gnu/dts/arm/tegra20-harmony.dts
+++ b/sys/gnu/dts/arm/tegra20-harmony.dts
@@ -13,6 +13,10 @@
 		serial0 = &uartd;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x00000000 0x40000000>;
 	};
@@ -655,7 +659,7 @@
 			label = "Power";
 			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra20-iris-512.dts b/sys/gnu/dts/arm/tegra20-iris-512.dts
index 1dd7d7bfdfcc..bb56dfe9e10c 100644
--- a/sys/gnu/dts/arm/tegra20-iris-512.dts
+++ b/sys/gnu/dts/arm/tegra20-iris-512.dts
@@ -11,6 +11,10 @@
 		serial1 = &uartd;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	host1x@50000000 {
 		hdmi@54280000 {
 			status = "okay";
diff --git a/sys/gnu/dts/arm/tegra20-medcom-wide.dts b/sys/gnu/dts/arm/tegra20-medcom-wide.dts
index 9b87526ab0b7..34c6588e92ef 100644
--- a/sys/gnu/dts/arm/tegra20-medcom-wide.dts
+++ b/sys/gnu/dts/arm/tegra20-medcom-wide.dts
@@ -10,6 +10,10 @@
 		serial0 = &uartd;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	pwm@7000a000 {
 		status = "okay";
 	};
diff --git a/sys/gnu/dts/arm/tegra20-paz00.dts b/sys/gnu/dts/arm/tegra20-paz00.dts
index ed7e1009326c..33ed2b23026b 100644
--- a/sys/gnu/dts/arm/tegra20-paz00.dts
+++ b/sys/gnu/dts/arm/tegra20-paz00.dts
@@ -14,6 +14,10 @@
 		serial1 = &uartc;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x00000000 0x20000000>;
 	};
@@ -521,7 +525,7 @@
 			label = "Power";
 			gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra20-seaboard.dts b/sys/gnu/dts/arm/tegra20-seaboard.dts
index aea8994b35f2..94b60a710dd8 100644
--- a/sys/gnu/dts/arm/tegra20-seaboard.dts
+++ b/sys/gnu/dts/arm/tegra20-seaboard.dts
@@ -13,6 +13,10 @@
 		serial0 = &uartd;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x00000000 0x40000000>;
 	};
@@ -807,7 +811,7 @@
 			label = "Power";
 			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		lid {
@@ -816,7 +820,7 @@
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0>; /* SW_LID */
 			debounce-interval = <1>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra20-tamonten.dtsi b/sys/gnu/dts/arm/tegra20-tamonten.dtsi
index 13d4e6185275..025e9e8037da 100644
--- a/sys/gnu/dts/arm/tegra20-tamonten.dtsi
+++ b/sys/gnu/dts/arm/tegra20-tamonten.dtsi
@@ -10,6 +10,10 @@
 		serial0 = &uartd;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x00000000 0x20000000>;
 	};
diff --git a/sys/gnu/dts/arm/tegra20-trimslice.dts b/sys/gnu/dts/arm/tegra20-trimslice.dts
index d99af4ef9c64..4a035f74043a 100644
--- a/sys/gnu/dts/arm/tegra20-trimslice.dts
+++ b/sys/gnu/dts/arm/tegra20-trimslice.dts
@@ -13,6 +13,10 @@
 		serial0 = &uarta;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x00000000 0x40000000>;
 	};
@@ -392,7 +396,7 @@
 			label = "Power";
 			gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra20-ventana.dts b/sys/gnu/dts/arm/tegra20-ventana.dts
index 04c58e9ca490..a28c060a839b 100644
--- a/sys/gnu/dts/arm/tegra20-ventana.dts
+++ b/sys/gnu/dts/arm/tegra20-ventana.dts
@@ -13,6 +13,10 @@
 		serial0 = &uartd;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x00000000 0x40000000>;
 	};
@@ -601,7 +605,7 @@
 			label = "Power";
 			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra20-whistler.dts b/sys/gnu/dts/arm/tegra20-whistler.dts
index 340d81108df1..073806d07b2b 100644
--- a/sys/gnu/dts/arm/tegra20-whistler.dts
+++ b/sys/gnu/dts/arm/tegra20-whistler.dts
@@ -13,6 +13,10 @@
 		serial0 = &uarta;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x00000000 0x20000000>;
 	};
@@ -508,7 +512,7 @@
 		nvidia,repeat-delay-ms = <160>;
 		nvidia,kbc-row-pins = <0 1 2>;
 		nvidia,kbc-col-pins = <16 17>;
-		nvidia,wakeup-source;
+		wakeup-source;
 		linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
 				MATRIX_KEY(0x01, 0x00, KEY_HOME)
 				MATRIX_KEY(0x01, 0x01, KEY_BACK)
diff --git a/sys/gnu/dts/arm/tegra20.dtsi b/sys/gnu/dts/arm/tegra20.dtsi
index 33173e1bace9..2207c08e3fa3 100644
--- a/sys/gnu/dts/arm/tegra20.dtsi
+++ b/sys/gnu/dts/arm/tegra20.dtsi
@@ -145,7 +145,7 @@
 		interrupt-parent = <&intc>;
 		reg = <0x50040600 0x20>;
 		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 		clocks = <&tegra_car TEGRA20_CLK_TWD>;
 	};
 
@@ -309,7 +309,7 @@
 	 * driver and APB DMA based serial driver for higher baudrate
 	 * and performace. To enable the 8250 based driver, the compatible
 	 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
-	 * driver, the comptible is "nvidia,tegra20-hsuart".
+	 * driver, the compatible is "nvidia,tegra20-hsuart".
 	 */
 	uarta: serial@70006000 {
 		compatible = "nvidia,tegra20-uart";
diff --git a/sys/gnu/dts/arm/tegra30-apalis-eval.dts b/sys/gnu/dts/arm/tegra30-apalis-eval.dts
index f2879cfcca62..99a69457dbf5 100644
--- a/sys/gnu/dts/arm/tegra30-apalis-eval.dts
+++ b/sys/gnu/dts/arm/tegra30-apalis-eval.dts
@@ -17,6 +17,10 @@
 		serial3 = &uartd;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	pcie-controller@00003000 {
 		status = "okay";
 
@@ -196,7 +200,7 @@
 			gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_WAKEUP>;
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra30-beaver.dts b/sys/gnu/dts/arm/tegra30-beaver.dts
index 3dede3934446..b6da15d823a6 100644
--- a/sys/gnu/dts/arm/tegra30-beaver.dts
+++ b/sys/gnu/dts/arm/tegra30-beaver.dts
@@ -12,6 +12,10 @@
 		serial0 = &uarta;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x80000000 0x7ff00000>;
 	};
@@ -1839,7 +1843,7 @@
 
 				ldo5_reg: ldo5 {
 					regulator-name = "vddio_sdmmc,avdd_vdac";
-					regulator-min-microvolt = <3300000>;
+					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <3300000>;
 					regulator-always-on;
 				};
@@ -1910,6 +1914,7 @@
 
 	sdhci@78000000 {
 		status = "okay";
+		vqmmc-supply = <&ldo5_reg>;
 		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
 		wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
 		power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
diff --git a/sys/gnu/dts/arm/tegra30-cardhu.dtsi b/sys/gnu/dts/arm/tegra30-cardhu.dtsi
index bb1ca158273c..4721c1c9c780 100644
--- a/sys/gnu/dts/arm/tegra30-cardhu.dtsi
+++ b/sys/gnu/dts/arm/tegra30-cardhu.dtsi
@@ -35,6 +35,10 @@
 		serial1 = &uartc;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	memory {
 		reg = <0x80000000 0x40000000>;
 	};
@@ -626,7 +630,7 @@
 			interrupts = <2 0>;
 			linux,code = <KEY_POWER>;
 			debounce-interval = <100>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 
 		volume-down {
diff --git a/sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts b/sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts
index 3ff019f47d00..76875c3160fe 100644
--- a/sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts
+++ b/sys/gnu/dts/arm/tegra30-colibri-eval-v3.dts
@@ -15,6 +15,10 @@
 		serial2 = &uartd;
 	};
 
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
 	host1x@50000000 {
 		dc@54200000 {
 			rgb {
@@ -142,7 +146,7 @@
 			gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_WAKEUP>;
 			debounce-interval = <10>;
-			gpio-key,wakeup;
+			wakeup-source;
 		};
 	};
 
diff --git a/sys/gnu/dts/arm/tegra30.dtsi b/sys/gnu/dts/arm/tegra30.dtsi
index 313e260529a3..5030065cbdfe 100644
--- a/sys/gnu/dts/arm/tegra30.dtsi
+++ b/sys/gnu/dts/arm/tegra30.dtsi
@@ -230,7 +230,7 @@
 		reg = <0x50040600 0x20>;
 		interrupt-parent = <&intc>;
 		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 		clocks = <&tegra_car TEGRA30_CLK_TWD>;
 	};
 
@@ -371,7 +371,7 @@
 	 * driver and APB DMA based serial driver for higher baudrate
 	 * and performace. To enable the 8250 based driver, the compatible
 	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
-	 * the APB DMA based serial driver, the comptible is
+	 * the APB DMA based serial driver, the compatible is
 	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 	 */
 	uarta: serial@70006000 {
diff --git a/sys/gnu/dts/arm/tps65217.dtsi b/sys/gnu/dts/arm/tps65217.dtsi
new file mode 100644
index 000000000000..a63272422d76
--- /dev/null
+++ b/sys/gnu/dts/arm/tps65217.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+
+&tps {
+	compatible = "ti,tps65217";
+
+	regulators {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dcdc1_reg: regulator@0 {
+			reg = <0>;
+			regulator-compatible = "dcdc1";
+		};
+
+		dcdc2_reg: regulator@1 {
+			reg = <1>;
+			regulator-compatible = "dcdc2";
+		};
+
+		dcdc3_reg: regulator@2 {
+			reg = <2>;
+			regulator-compatible = "dcdc3";
+		};
+
+		ldo1_reg: regulator@3 {
+			reg = <3>;
+			regulator-compatible = "ldo1";
+		};
+
+		ldo2_reg: regulator@4 {
+			reg = <4>;
+			regulator-compatible = "ldo2";
+		};
+
+		ldo3_reg: regulator@5 {
+			reg = <5>;
+			regulator-compatible = "ldo3";
+		};
+
+		ldo4_reg: regulator@6 {
+			reg = <6>;
+			regulator-compatible = "ldo4";
+		};
+	};
+};
diff --git a/sys/gnu/dts/arm/twl6030.dtsi b/sys/gnu/dts/arm/twl6030.dtsi
index 55eb35f068fb..c45f97f37563 100644
--- a/sys/gnu/dts/arm/twl6030.dtsi
+++ b/sys/gnu/dts/arm/twl6030.dtsi
@@ -99,4 +99,10 @@
 		compatible = "ti,twl6030-pwmled";
 		#pwm-cells = <2>;
 	};
+
+	gpadc {
+		compatible = "ti,twl6030-gpadc";
+		interrupts = <3>;
+		#io-channel-cells = <1>;
+	};
 };
diff --git a/sys/gnu/dts/arm/uniphier-common32.dtsi b/sys/gnu/dts/arm/uniphier-common32.dtsi
index ea9301aaa461..61a095598206 100644
--- a/sys/gnu/dts/arm/uniphier-common32.dtsi
+++ b/sys/gnu/dts/arm/uniphier-common32.dtsi
@@ -45,6 +45,13 @@
 /include/ "skeleton.dtsi"
 
 / {
+	clocks {
+		refclk: ref {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+		};
+	};
+
 	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -52,12 +59,6 @@
 		ranges;
 		interrupt-parent = <&intc>;
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
-
 		serial0: serial@54006800 {
 			compatible = "socionext,uniphier-uart";
 			status = "disabled";
@@ -98,9 +99,17 @@
 			clocks = <&uart_clk>;
 		};
 
-		system-bus-controller@58c00000 {
-			compatible = "socionext,uniphier-system-bus-controller";
-			reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
+
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
 		};
 
 		timer@60000200 {
diff --git a/sys/gnu/dts/arm/uniphier-ph1-ld4-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-ld4-ref.dts
index f1e9d40149ab..ec94b7a661f2 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-ld4-ref.dts
+++ b/sys/gnu/dts/arm/uniphier-ph1-ld4-ref.dts
@@ -72,14 +72,6 @@
 	};
 };
 
-&extbus {
-	ranges = <1 0x00000000 0x42000000 0x02000000>;
-};
-
-&support_card {
-	ranges = <0x00000000 1 0x01f00000 0x00100000>;
-};
-
 &ethsc {
 	interrupts = <0 49 4>;
 };
diff --git a/sys/gnu/dts/arm/uniphier-ph1-ld4.dtsi b/sys/gnu/dts/arm/uniphier-ph1-ld4.dtsi
index 34f0d8dcd814..dadd86070c98 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-ld4.dtsi
+++ b/sys/gnu/dts/arm/uniphier-ph1-ld4.dtsi
@@ -173,6 +173,10 @@
 
 };
 
+&refclk {
+	clock-frequency = <24576000>;
+};
+
 &serial3 {
 	interrupts = <0 29 4>;
 };
diff --git a/sys/gnu/dts/arm/uniphier-ph1-ld6b-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-ld6b-ref.dts
index 5baa9fc9c888..b8134c6e094b 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-ld6b-ref.dts
+++ b/sys/gnu/dts/arm/uniphier-ph1-ld6b-ref.dts
@@ -74,14 +74,6 @@
 	};
 };
 
-&extbus {
-	ranges = <1 0x00000000 0x42000000 0x02000000>;
-};
-
-&support_card {
-	ranges = <0x00000000 1 0x01f00000 0x00100000>;
-};
-
 &ethsc {
 	interrupts = <0 52 4>;
 };
diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro4-ace.dts b/sys/gnu/dts/arm/uniphier-ph1-pro4-ace.dts
new file mode 100644
index 000000000000..d34358632bec
--- /dev/null
+++ b/sys/gnu/dts/arm/uniphier-ph1-pro4-ace.dts
@@ -0,0 +1,113 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 Ace Board
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro4.dtsi"
+
+/ {
+	model = "UniPhier PH1-Pro4 Ace Board";
+	compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&serial2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	eeprom@54 {
+		compatible = "st,24c64";
+		reg = <0x54>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro4-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-pro4-ref.dts
index 24626687d4df..95f631a3de35 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-pro4-ref.dts
+++ b/sys/gnu/dts/arm/uniphier-ph1-pro4-ref.dts
@@ -74,14 +74,6 @@
 	};
 };
 
-&extbus {
-	ranges = <1 0x00000000 0x42000000 0x02000000>;
-};
-
-&support_card {
-	ranges = <0x00000000 1 0x01f00000 0x00100000>;
-};
-
 &ethsc {
 	interrupts = <0 50 4>;
 };
diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro4-sanji.dts b/sys/gnu/dts/arm/uniphier-ph1-pro4-sanji.dts
new file mode 100644
index 000000000000..7c3a1fcc9f3c
--- /dev/null
+++ b/sys/gnu/dts/arm/uniphier-ph1-pro4-sanji.dts
@@ -0,0 +1,108 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 Sanji Board
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro4.dtsi"
+
+/ {
+	model = "UniPhier PH1-Pro4 Sanji Board";
+	compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	eeprom@54 {
+		compatible = "st,24c64";
+		reg = <0x54>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro4.dtsi b/sys/gnu/dts/arm/uniphier-ph1-pro4.dtsi
index d78142fb35c4..20f3f2ae7fa4 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-pro4.dtsi
+++ b/sys/gnu/dts/arm/uniphier-ph1-pro4.dtsi
@@ -195,6 +195,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-pro4-pinctrl", "syscon";
 };
diff --git a/sys/gnu/dts/arm/uniphier-ph1-pro5.dtsi b/sys/gnu/dts/arm/uniphier-ph1-pro5.dtsi
index 2f389ea75e01..24f6f664b269 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-pro5.dtsi
+++ b/sys/gnu/dts/arm/uniphier-ph1-pro5.dtsi
@@ -189,6 +189,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <20000000>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
 };
diff --git a/sys/gnu/dts/arm/uniphier-ph1-sld3-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-sld3-ref.dts
index b7a032156789..acb420492b36 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-sld3-ref.dts
+++ b/sys/gnu/dts/arm/uniphier-ph1-sld3-ref.dts
@@ -73,14 +73,6 @@
 	};
 };
 
-&extbus {
-	ranges = <1 0x00000000 0x42000000 0x02000000>;
-};
-
-&support_card {
-	ranges = <0x00000000 1 0x01f00000 0x00100000>;
-};
-
 &ethsc {
 	interrupts = <0 49 4>;
 };
diff --git a/sys/gnu/dts/arm/uniphier-ph1-sld3.dtsi b/sys/gnu/dts/arm/uniphier-ph1-sld3.dtsi
index 691a17d765c2..03292f443305 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-sld3.dtsi
+++ b/sys/gnu/dts/arm/uniphier-ph1-sld3.dtsi
@@ -68,6 +68,12 @@
 	};
 
 	clocks {
+		refclk: ref {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24576000>;
+		};
+
 		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -94,12 +100,6 @@
 		ranges;
 		interrupt-parent = <&intc>;
 
-		extbus: extbus {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
-
 		timer@20000200 {
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0x20000200 0x20>;
@@ -216,9 +216,17 @@
 			clock-frequency = <400000>;
 		};
 
-		system-bus-controller@58c00000 {
-			compatible = "socionext,uniphier-system-bus-controller";
-			reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
+		system_bus: system-bus@58c00000 {
+			compatible = "socionext,uniphier-system-bus";
+			status = "disabled";
+			reg = <0x58c00000 0x400>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+		};
+
+		smpctrl@59800000 {
+			compatible = "socionext,uniphier-smpctrl";
+			reg = <0x59801000 0x400>;
 		};
 
 		usb0: usb@5a800100 {
diff --git a/sys/gnu/dts/arm/uniphier-ph1-sld8-ref.dts b/sys/gnu/dts/arm/uniphier-ph1-sld8-ref.dts
index fc7250c61674..d594f40e7f76 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-sld8-ref.dts
+++ b/sys/gnu/dts/arm/uniphier-ph1-sld8-ref.dts
@@ -72,14 +72,6 @@
 	};
 };
 
-&extbus {
-	ranges = <1 0x00000000 0x42000000 0x02000000>;
-};
-
-&support_card {
-	ranges = <0x00000000 1 0x01f00000 0x00100000>;
-};
-
 &ethsc {
 	interrupts = <0 48 4>;
 };
diff --git a/sys/gnu/dts/arm/uniphier-ph1-sld8.dtsi b/sys/gnu/dts/arm/uniphier-ph1-sld8.dtsi
index 7d06a1c487d8..6bfd29a05575 100644
--- a/sys/gnu/dts/arm/uniphier-ph1-sld8.dtsi
+++ b/sys/gnu/dts/arm/uniphier-ph1-sld8.dtsi
@@ -172,6 +172,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &serial3 {
 	interrupts = <0 29 4>;
 };
diff --git a/sys/gnu/dts/arm/uniphier-pinctrl.dtsi b/sys/gnu/dts/arm/uniphier-pinctrl.dtsi
index f67445f4f10d..f2f3fbe2d517 100644
--- a/sys/gnu/dts/arm/uniphier-pinctrl.dtsi
+++ b/sys/gnu/dts/arm/uniphier-pinctrl.dtsi
@@ -63,6 +63,21 @@
 		function = "i2c3";
 	};
 
+	pinctrl_i2c4: i2c4_grp {
+		groups = "i2c4";
+		function = "i2c4";
+	};
+
+	pinctrl_nand: nand_grp {
+		groups = "nand";
+		function = "nand";
+	};
+
+	pinctrl_nand2cs: nand2cs_grp {
+		groups = "nand", "nand_cs1";
+		function = "nand";
+	};
+
 	pinctrl_uart0: uart0_grp {
 		groups = "uart0";
 		function = "uart0";
diff --git a/sys/gnu/dts/arm/uniphier-proxstream2-gentil.dts b/sys/gnu/dts/arm/uniphier-proxstream2-gentil.dts
index 9d7ec5c204dd..bf2619e4d489 100644
--- a/sys/gnu/dts/arm/uniphier-proxstream2-gentil.dts
+++ b/sys/gnu/dts/arm/uniphier-proxstream2-gentil.dts
@@ -63,6 +63,7 @@
 		serial1 = &serial1;
 		serial2 = &serial2;
 		i2c0 = &i2c0;
+		i2c2 = &i2c2;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
 		i2c6 = &i2c6;
@@ -75,4 +76,13 @@
 
 &i2c0 {
 	status = "okay";
+
+	eeprom@54 {
+		compatible = "st,24c64";
+		reg = <0x54>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
 };
diff --git a/sys/gnu/dts/arm/uniphier-proxstream2.dtsi b/sys/gnu/dts/arm/uniphier-proxstream2.dtsi
index 6bd353f2d77e..4ac484c6ce4e 100644
--- a/sys/gnu/dts/arm/uniphier-proxstream2.dtsi
+++ b/sys/gnu/dts/arm/uniphier-proxstream2.dtsi
@@ -200,6 +200,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &pinctrl {
 	compatible = "socionext,proxstream2-pinctrl", "syscon";
 };
diff --git a/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi b/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi
index 3d29d2806cc0..f7df0881c5e0 100644
--- a/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi
+++ b/sys/gnu/dts/arm/uniphier-ref-daughter.dtsi
@@ -43,7 +43,7 @@
  */
 
 &i2c0 {
-	eeprom {
+	eeprom@50 {
 		compatible = "microchip,24lc128";
 		reg = <0x50>;
 	};
diff --git a/sys/gnu/dts/arm/uniphier-support-card.dtsi b/sys/gnu/dts/arm/uniphier-support-card.dtsi
index da271e3b922a..51ecc9b9c0ce 100644
--- a/sys/gnu/dts/arm/uniphier-support-card.dtsi
+++ b/sys/gnu/dts/arm/uniphier-support-card.dtsi
@@ -42,11 +42,15 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-&extbus {
+&system_bus {
+	status = "okay";
+	ranges = <1 0x00000000 0x42000000 0x02000000>;
+
 	support_card: support_card {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
+		ranges = <0x00000000 1 0x01f00000 0x00100000>;
 
 		ethsc: ethernet@00000000 {
 			compatible = "smsc,lan9118", "smsc,lan9115";
diff --git a/sys/gnu/dts/arm/versatile-ab.dts b/sys/gnu/dts/arm/versatile-ab.dts
index 6fd7efbead34..409e069b3a84 100644
--- a/sys/gnu/dts/arm/versatile-ab.dts
+++ b/sys/gnu/dts/arm/versatile-ab.dts
@@ -119,8 +119,9 @@
 	};
 
 	flash@34000000 {
-		compatible = "arm,versatile-flash";
-		reg = <0x34000000 0x4000000>;
+		/* 64 MiB NOR flash in non-interleaved chips */
+		compatible = "arm,versatile-flash", "cfi-flash";
+		reg = <0x34000000 0x04000000>;
 		bank-width = <4>;
 	};
 
@@ -148,7 +149,7 @@
 	};
 
 	amba {
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
diff --git a/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi b/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi
index 21b02874bea3..3086efacd00e 100644
--- a/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi
+++ b/sys/gnu/dts/arm/vexpress-v2m-rs1.dtsi
@@ -66,7 +66,7 @@
 		};
 
 		iofpga@3,00000000 {
-			compatible = "arm,amba-bus", "simple-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0 3 0 0x200000>;
@@ -75,19 +75,19 @@
 				compatible = "arm,vexpress-sysreg";
 				reg = <0x010000 0x1000>;
 
-				v2m_led_gpios: sys_led@08 {
+				v2m_led_gpios: sys_led {
 					compatible = "arm,vexpress-sysreg,sys_led";
 					gpio-controller;
 					#gpio-cells = <2>;
 				};
 
-				v2m_mmc_gpios: sys_mci@48 {
+				v2m_mmc_gpios: sys_mci {
 					compatible = "arm,vexpress-sysreg,sys_mci";
 					gpio-controller;
 					#gpio-cells = <2>;
 				};
 
-				v2m_flash_gpios: sys_flash@4c {
+				v2m_flash_gpios: sys_flash {
 					compatible = "arm,vexpress-sysreg,sys_flash";
 					gpio-controller;
 					#gpio-cells = <2>;
@@ -286,7 +286,7 @@
 			};
 		};
 
-		v2m_fixed_3v3: fixedregulator@0 {
+		v2m_fixed_3v3: fixed-regulator-0 {
 			compatible = "regulator-fixed";
 			regulator-name = "3V3";
 			regulator-min-microvolt = <3300000>;
@@ -318,49 +318,49 @@
 		leds {
 			compatible = "gpio-leds";
 
-			user@1 {
+			user1 {
 				label = "v2m:green:user1";
 				gpios = <&v2m_led_gpios 0 0>;
 				linux,default-trigger = "heartbeat";
 			};
 
-			user@2 {
+			user2 {
 				label = "v2m:green:user2";
 				gpios = <&v2m_led_gpios 1 0>;
 				linux,default-trigger = "mmc0";
 			};
 
-			user@3 {
+			user3 {
 				label = "v2m:green:user3";
 				gpios = <&v2m_led_gpios 2 0>;
 				linux,default-trigger = "cpu0";
 			};
 
-			user@4 {
+			user4 {
 				label = "v2m:green:user4";
 				gpios = <&v2m_led_gpios 3 0>;
 				linux,default-trigger = "cpu1";
 			};
 
-			user@5 {
+			user5 {
 				label = "v2m:green:user5";
 				gpios = <&v2m_led_gpios 4 0>;
 				linux,default-trigger = "cpu2";
 			};
 
-			user@6 {
+			user6 {
 				label = "v2m:green:user6";
 				gpios = <&v2m_led_gpios 5 0>;
 				linux,default-trigger = "cpu3";
 			};
 
-			user@7 {
+			user7 {
 				label = "v2m:green:user7";
 				gpios = <&v2m_led_gpios 6 0>;
 				linux,default-trigger = "cpu4";
 			};
 
-			user@8 {
+			user8 {
 				label = "v2m:green:user8";
 				gpios = <&v2m_led_gpios 7 0>;
 				linux,default-trigger = "cpu5";
@@ -371,7 +371,7 @@
 			compatible = "arm,vexpress,config-bus";
 			arm,vexpress,config-bridge = <&v2m_sysreg>;
 
-			osc@0 {
+			oscclk0 {
 				/* MCC static memory clock */
 				compatible = "arm,vexpress-osc";
 				arm,vexpress-sysreg,func = <1 0>;
@@ -380,7 +380,7 @@
 				clock-output-names = "v2m:oscclk0";
 			};
 
-			v2m_oscclk1: osc@1 {
+			v2m_oscclk1: oscclk1 {
 				/* CLCD clock */
 				compatible = "arm,vexpress-osc";
 				arm,vexpress-sysreg,func = <1 1>;
@@ -389,7 +389,7 @@
 				clock-output-names = "v2m:oscclk1";
 			};
 
-			v2m_oscclk2: osc@2 {
+			v2m_oscclk2: oscclk2 {
 				/* IO FPGA peripheral clock */
 				compatible = "arm,vexpress-osc";
 				arm,vexpress-sysreg,func = <1 2>;
@@ -398,7 +398,7 @@
 				clock-output-names = "v2m:oscclk2";
 			};
 
-			volt@0 {
+			volt-vio {
 				/* Logic level voltage */
 				compatible = "arm,vexpress-volt";
 				arm,vexpress-sysreg,func = <2 0>;
@@ -407,34 +407,34 @@
 				label = "VIO";
 			};
 
-			temp@0 {
+			temp-mcc {
 				/* MCC internal operating temperature */
 				compatible = "arm,vexpress-temp";
 				arm,vexpress-sysreg,func = <4 0>;
 				label = "MCC";
 			};
 
-			reset@0 {
+			reset {
 				compatible = "arm,vexpress-reset";
 				arm,vexpress-sysreg,func = <5 0>;
 			};
 
-			muxfpga@0 {
+			muxfpga {
 				compatible = "arm,vexpress-muxfpga";
 				arm,vexpress-sysreg,func = <7 0>;
 			};
 
-			shutdown@0 {
+			shutdown {
 				compatible = "arm,vexpress-shutdown";
 				arm,vexpress-sysreg,func = <8 0>;
 			};
 
-			reboot@0 {
+			reboot {
 				compatible = "arm,vexpress-reboot";
 				arm,vexpress-sysreg,func = <9 0>;
 			};
 
-			dvimode@0 {
+			dvimode {
 				compatible = "arm,vexpress-dvimode";
 				arm,vexpress-sysreg,func = <11 0>;
 			};
diff --git a/sys/gnu/dts/arm/vexpress-v2m.dtsi b/sys/gnu/dts/arm/vexpress-v2m.dtsi
index e712c0af149b..c6393d3f1719 100644
--- a/sys/gnu/dts/arm/vexpress-v2m.dtsi
+++ b/sys/gnu/dts/arm/vexpress-v2m.dtsi
@@ -65,7 +65,7 @@
 		};
 
 		iofpga@7,00000000 {
-			compatible = "arm,amba-bus", "simple-bus";
+			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0 7 0 0x20000>;
@@ -74,19 +74,19 @@
 				compatible = "arm,vexpress-sysreg";
 				reg = <0x00000 0x1000>;
 
-				v2m_led_gpios: sys_led@08 {
+				v2m_led_gpios: sys_led {
 					compatible = "arm,vexpress-sysreg,sys_led";
 					gpio-controller;
 					#gpio-cells = <2>;
 				};
 
-				v2m_mmc_gpios: sys_mci@48 {
+				v2m_mmc_gpios: sys_mci {
 					compatible = "arm,vexpress-sysreg,sys_mci";
 					gpio-controller;
 					#gpio-cells = <2>;
 				};
 
-				v2m_flash_gpios: sys_flash@4c {
+				v2m_flash_gpios: sys_flash {
 					compatible = "arm,vexpress-sysreg,sys_flash";
 					gpio-controller;
 					#gpio-cells = <2>;
@@ -285,7 +285,7 @@
 			};
 		};
 
-		v2m_fixed_3v3: fixedregulator@0 {
+		v2m_fixed_3v3: fixed-regulator-0 {
 			compatible = "regulator-fixed";
 			regulator-name = "3V3";
 			regulator-min-microvolt = <3300000>;
@@ -317,49 +317,49 @@
 		leds {
 			compatible = "gpio-leds";
 
-			user@1 {
+			user1 {
 				label = "v2m:green:user1";
 				gpios = <&v2m_led_gpios 0 0>;
 				linux,default-trigger = "heartbeat";
 			};
 
-			user@2 {
+			user2 {
 				label = "v2m:green:user2";
 				gpios = <&v2m_led_gpios 1 0>;
 				linux,default-trigger = "mmc0";
 			};
 
-			user@3 {
+			user3 {
 				label = "v2m:green:user3";
 				gpios = <&v2m_led_gpios 2 0>;
 				linux,default-trigger = "cpu0";
 			};
 
-			user@4 {
+			user4 {
 				label = "v2m:green:user4";
 				gpios = <&v2m_led_gpios 3 0>;
 				linux,default-trigger = "cpu1";
 			};
 
-			user@5 {
+			user5 {
 				label = "v2m:green:user5";
 				gpios = <&v2m_led_gpios 4 0>;
 				linux,default-trigger = "cpu2";
 			};
 
-			user@6 {
+			user6 {
 				label = "v2m:green:user6";
 				gpios = <&v2m_led_gpios 5 0>;
 				linux,default-trigger = "cpu3";
 			};
 
-			user@7 {
+			user7 {
 				label = "v2m:green:user7";
 				gpios = <&v2m_led_gpios 6 0>;
 				linux,default-trigger = "cpu4";
 			};
 
-			user@8 {
+			user8 {
 				label = "v2m:green:user8";
 				gpios = <&v2m_led_gpios 7 0>;
 				linux,default-trigger = "cpu5";
@@ -370,7 +370,7 @@
 			compatible = "arm,vexpress,config-bus";
 			arm,vexpress,config-bridge = <&v2m_sysreg>;
 
-			osc@0 {
+			oscclk0 {
 				/* MCC static memory clock */
 				compatible = "arm,vexpress-osc";
 				arm,vexpress-sysreg,func = <1 0>;
@@ -379,7 +379,7 @@
 				clock-output-names = "v2m:oscclk0";
 			};
 
-			v2m_oscclk1: osc@1 {
+			v2m_oscclk1: oscclk1 {
 				/* CLCD clock */
 				compatible = "arm,vexpress-osc";
 				arm,vexpress-sysreg,func = <1 1>;
@@ -388,7 +388,7 @@
 				clock-output-names = "v2m:oscclk1";
 			};
 
-			v2m_oscclk2: osc@2 {
+			v2m_oscclk2: oscclk2 {
 				/* IO FPGA peripheral clock */
 				compatible = "arm,vexpress-osc";
 				arm,vexpress-sysreg,func = <1 2>;
@@ -397,7 +397,7 @@
 				clock-output-names = "v2m:oscclk2";
 			};
 
-			volt@0 {
+			volt-vio {
 				/* Logic level voltage */
 				compatible = "arm,vexpress-volt";
 				arm,vexpress-sysreg,func = <2 0>;
@@ -406,34 +406,34 @@
 				label = "VIO";
 			};
 
-			temp@0 {
+			temp-mcc {
 				/* MCC internal operating temperature */
 				compatible = "arm,vexpress-temp";
 				arm,vexpress-sysreg,func = <4 0>;
 				label = "MCC";
 			};
 
-			reset@0 {
+			reset {
 				compatible = "arm,vexpress-reset";
 				arm,vexpress-sysreg,func = <5 0>;
 			};
 
-			muxfpga@0 {
+			muxfpga {
 				compatible = "arm,vexpress-muxfpga";
 				arm,vexpress-sysreg,func = <7 0>;
 			};
 
-			shutdown@0 {
+			shutdown {
 				compatible = "arm,vexpress-shutdown";
 				arm,vexpress-sysreg,func = <8 0>;
 			};
 
-			reboot@0 {
+			reboot {
 				compatible = "arm,vexpress-reboot";
 				arm,vexpress-sysreg,func = <9 0>;
 			};
 
-			dvimode@0 {
+			dvimode {
 				compatible = "arm,vexpress-dvimode";
 				arm,vexpress-sysreg,func = <11 0>;
 			};
diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts b/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts
index 9420053acc14..102838fcc588 100644
--- a/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts
+++ b/sys/gnu/dts/arm/vexpress-v2p-ca15-tc1.dts
@@ -55,14 +55,14 @@
 		compatible = "arm,hdlcd";
 		reg = <0 0x2b000000 0 0x1000>;
 		interrupts = <0 85 4>;
-		clocks = <&oscclk5>;
+		clocks = <&hdlcd_clk>;
 		clock-names = "pxlclk";
 	};
 
 	memory-controller@2b0a0000 {
 		compatible = "arm,pl341", "arm,primecell";
 		reg = <0 0x2b0a0000 0 0x1000>;
-		clocks = <&oscclk7>;
+		clocks = <&sys_pll>;
 		clock-names = "apb_pclk";
 	};
 
@@ -71,7 +71,7 @@
 		status = "disabled";
 		reg = <0 0x2b060000 0 0x1000>;
 		interrupts = <0 98 4>;
-		clocks = <&oscclk7>;
+		clocks = <&sys_pll>;
 		clock-names = "apb_pclk";
 	};
 
@@ -92,7 +92,7 @@
 		reg = <0 0x7ffd0000 0 0x1000>;
 		interrupts = <0 86 4>,
 			     <0 87 4>;
-		clocks = <&oscclk7>;
+		clocks = <&sys_pll>;
 		clock-names = "apb_pclk";
 	};
 
@@ -104,7 +104,7 @@
 			     <0 89 4>,
 			     <0 90 4>,
 			     <0 91 4>;
-		clocks = <&oscclk7>;
+		clocks = <&sys_pll>;
 		clock-names = "apb_pclk";
 	};
 
@@ -126,7 +126,7 @@
 		compatible = "arm,vexpress,config-bus";
 		arm,vexpress,config-bridge = <&v2m_sysreg>;
 
-		osc@0 {
+		oscclk0 {
 			/* CPU PLL reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 0>;
@@ -135,7 +135,7 @@
 			clock-output-names = "oscclk0";
 		};
 
-		osc@4 {
+		oscclk4 {
 			/* Multiplexed AXI master clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 4>;
@@ -144,7 +144,7 @@
 			clock-output-names = "oscclk4";
 		};
 
-		oscclk5: osc@5 {
+		hdlcd_clk: oscclk5 {
 			/* HDLCD PLL reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 5>;
@@ -153,7 +153,7 @@
 			clock-output-names = "oscclk5";
 		};
 
-		smbclk: osc@6 {
+		smbclk: oscclk6 {
 			/* SMB clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 6>;
@@ -162,7 +162,7 @@
 			clock-output-names = "oscclk6";
 		};
 
-		oscclk7: osc@7 {
+		sys_pll: oscclk7 {
 			/* SYS PLL reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 7>;
@@ -171,7 +171,7 @@
 			clock-output-names = "oscclk7";
 		};
 
-		osc@8 {
+		oscclk8 {
 			/* DDR2 PLL reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 8>;
@@ -180,7 +180,7 @@
 			clock-output-names = "oscclk8";
 		};
 
-		volt@0 {
+		volt-cores {
 			/* CPU core voltage */
 			compatible = "arm,vexpress-volt";
 			arm,vexpress-sysreg,func = <2 0>;
@@ -191,28 +191,28 @@
 			label = "Cores";
 		};
 
-		amp@0 {
+		amp-cores {
 			/* Total current for the two cores */
 			compatible = "arm,vexpress-amp";
 			arm,vexpress-sysreg,func = <3 0>;
 			label = "Cores";
 		};
 
-		temp@0 {
+		temp-dcc {
 			/* DCC internal temperature */
 			compatible = "arm,vexpress-temp";
 			arm,vexpress-sysreg,func = <4 0>;
 			label = "DCC";
 		};
 
-		power@0 {
+		power-cores {
 			/* Total power */
 			compatible = "arm,vexpress-power";
 			arm,vexpress-sysreg,func = <12 0>;
 			label = "Cores";
 		};
 
-		energy@0 {
+		energy {
 			/* Total energy */
 			compatible = "arm,vexpress-energy";
 			arm,vexpress-sysreg,func = <13 0>;
@@ -220,7 +220,7 @@
 		};
 	};
 
-	smb {
+	smb@08000000 {
 		compatible = "simple-bus";
 
 		#address-cells = <2>;
@@ -280,4 +280,17 @@
 
 		/include/ "vexpress-v2m-rs1.dtsi"
 	};
+
+	site2: hsb@40000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x40000000 0x3fef0000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 3>;
+		interrupt-map = <0 0 &gic 0 36 4>,
+				<0 1 &gic 0 37 4>,
+				<0 2 &gic 0 38 4>,
+				<0 3 &gic 0 39 4>;
+	};
 };
diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts b/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts
index 17f63f7dfd9e..0205c97efdef 100644
--- a/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts
+++ b/sys/gnu/dts/arm/vexpress-v2p-ca15_a7.dts
@@ -109,7 +109,7 @@
 		compatible = "arm,hdlcd";
 		reg = <0 0x2b000000 0 0x1000>;
 		interrupts = <0 85 4>;
-		clocks = <&oscclk5>;
+		clocks = <&hdlcd_clk>;
 		clock-names = "pxlclk";
 	};
 
@@ -227,7 +227,7 @@
 		compatible = "arm,vexpress,config-bus";
 		arm,vexpress,config-bridge = <&v2m_sysreg>;
 
-		osc@0 {
+		oscclk0 {
 			/* A15 PLL 0 reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 0>;
@@ -236,7 +236,7 @@
 			clock-output-names = "oscclk0";
 		};
 
-		osc@1 {
+		oscclk1 {
 			/* A15 PLL 1 reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 1>;
@@ -245,7 +245,7 @@
 			clock-output-names = "oscclk1";
 		};
 
-		osc@2 {
+		oscclk2 {
 			/* A7 PLL 0 reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 2>;
@@ -254,7 +254,7 @@
 			clock-output-names = "oscclk2";
 		};
 
-		osc@3 {
+		oscclk3 {
 			/* A7 PLL 1 reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 3>;
@@ -263,7 +263,7 @@
 			clock-output-names = "oscclk3";
 		};
 
-		osc@4 {
+		oscclk4 {
 			/* External AXI master clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 4>;
@@ -272,7 +272,7 @@
 			clock-output-names = "oscclk4";
 		};
 
-		oscclk5: osc@5 {
+		hdlcd_clk: oscclk5 {
 			/* HDLCD PLL reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 5>;
@@ -281,7 +281,7 @@
 			clock-output-names = "oscclk5";
 		};
 
-		smbclk: osc@6 {
+		smbclk: oscclk6 {
 			/* Static memory controller clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 6>;
@@ -290,7 +290,7 @@
 			clock-output-names = "oscclk6";
 		};
 
-		osc@7 {
+		oscclk7 {
 			/* SYS PLL reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 7>;
@@ -299,7 +299,7 @@
 			clock-output-names = "oscclk7";
 		};
 
-		osc@8 {
+		oscclk8 {
 			/* DDR2 PLL reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 8>;
@@ -308,7 +308,7 @@
 			clock-output-names = "oscclk8";
 		};
 
-		volt@0 {
+		volt-a15 {
 			/* A15 CPU core voltage */
 			compatible = "arm,vexpress-volt";
 			arm,vexpress-sysreg,func = <2 0>;
@@ -319,7 +319,7 @@
 			label = "A15 Vcore";
 		};
 
-		volt@1 {
+		volt-a7 {
 			/* A7 CPU core voltage */
 			compatible = "arm,vexpress-volt";
 			arm,vexpress-sysreg,func = <2 1>;
@@ -330,49 +330,49 @@
 			label = "A7 Vcore";
 		};
 
-		amp@0 {
+		amp-a15 {
 			/* Total current for the two A15 cores */
 			compatible = "arm,vexpress-amp";
 			arm,vexpress-sysreg,func = <3 0>;
 			label = "A15 Icore";
 		};
 
-		amp@1 {
+		amp-a7 {
 			/* Total current for the three A7 cores */
 			compatible = "arm,vexpress-amp";
 			arm,vexpress-sysreg,func = <3 1>;
 			label = "A7 Icore";
 		};
 
-		temp@0 {
+		temp-dcc {
 			/* DCC internal temperature */
 			compatible = "arm,vexpress-temp";
 			arm,vexpress-sysreg,func = <4 0>;
 			label = "DCC";
 		};
 
-		power@0 {
+		power-a15 {
 			/* Total power for the two A15 cores */
 			compatible = "arm,vexpress-power";
 			arm,vexpress-sysreg,func = <12 0>;
 			label = "A15 Pcore";
 		};
 
-		power@1 {
+		power-a7 {
 			/* Total power for the three A7 cores */
 			compatible = "arm,vexpress-power";
 			arm,vexpress-sysreg,func = <12 1>;
 			label = "A7 Pcore";
 		};
 
-		energy@0 {
+		energy-a15 {
 			/* Total energy for the two A15 cores */
 			compatible = "arm,vexpress-energy";
 			arm,vexpress-sysreg,func = <13 0>, <13 1>;
 			label = "A15 Jcore";
 		};
 
-		energy@2 {
+		energy-a7 {
 			/* Total energy for the three A7 cores */
 			compatible = "arm,vexpress-energy";
 			arm,vexpress-sysreg,func = <13 2>, <13 3>;
@@ -387,7 +387,7 @@
 		clocks = <&oscclk6a>;
 		clock-names = "apb_pclk";
 		port {
-			etb_in_port: endpoint@0 {
+			etb_in_port: endpoint {
 				slave-mode;
 				remote-endpoint = <&replicator_out_port0>;
 			};
@@ -401,7 +401,7 @@
 		clocks = <&oscclk6a>;
 		clock-names = "apb_pclk";
 		port {
-			tpiu_in_port: endpoint@0 {
+			tpiu_in_port: endpoint {
 				slave-mode;
 				remote-endpoint = <&replicator_out_port1>;
 			};
@@ -578,7 +578,7 @@
 		};
 	};
 
-	smb {
+	smb@08000000 {
 		compatible = "simple-bus";
 
 		#address-cells = <2>;
@@ -638,4 +638,17 @@
 
 		/include/ "vexpress-v2m-rs1.dtsi"
 	};
+
+	site2: hsb@40000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x40000000 0x3fef0000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 3>;
+		interrupt-map = <0 0 &gic 0 36 4>,
+				<0 1 &gic 0 37 4>,
+				<0 2 &gic 0 38 4>,
+				<0 3 &gic 0 39 4>;
+	};
 };
diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts b/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts
index d2709b73316b..1acecaf4b13d 100644
--- a/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts
+++ b/sys/gnu/dts/arm/vexpress-v2p-ca5s.dts
@@ -57,14 +57,14 @@
 		compatible = "arm,hdlcd";
 		reg = <0x2a110000 0x1000>;
 		interrupts = <0 85 4>;
-		clocks = <&oscclk3>;
+		clocks = <&hdlcd_clk>;
 		clock-names = "pxlclk";
 	};
 
 	memory-controller@2a150000 {
 		compatible = "arm,pl341", "arm,primecell";
 		reg = <0x2a150000 0x1000>;
-		clocks = <&oscclk1>;
+		clocks = <&axi_clk>;
 		clock-names = "apb_pclk";
 	};
 
@@ -73,7 +73,7 @@
 		reg = <0x2a190000 0x1000>;
 		interrupts = <0 86 4>,
 			     <0 87 4>;
-		clocks = <&oscclk1>;
+		clocks = <&axi_clk>;
 		clock-names = "apb_pclk";
 	};
 
@@ -93,7 +93,7 @@
 		             "arm,cortex-a9-global-timer";
 		reg = <0x2c000200 0x20>;
 		interrupts = <1 11 0x304>;
-		clocks = <&oscclk0>;
+		clocks = <&cpu_clk>;
 	};
 
 	watchdog@2c000620 {
@@ -128,7 +128,7 @@
 		compatible = "arm,vexpress,config-bus";
 		arm,vexpress,config-bridge = <&v2m_sysreg>;
 
-		oscclk0: osc@0 {
+		cpu_clk: oscclk0 {
 			/* CPU and internal AXI reference clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 0>;
@@ -137,7 +137,7 @@
 			clock-output-names = "oscclk0";
 		};
 
-		oscclk1: osc@1 {
+		axi_clk: oscclk1 {
 			/* Multiplexed AXI master clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 1>;
@@ -146,7 +146,7 @@
 			clock-output-names = "oscclk1";
 		};
 
-		osc@2 {
+		oscclk2 {
 			/* DDR2 */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 2>;
@@ -155,7 +155,7 @@
 			clock-output-names = "oscclk2";
 		};
 
-		oscclk3: osc@3 {
+		hdlcd_clk: oscclk3 {
 			/* HDLCD */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 3>;
@@ -164,7 +164,7 @@
 			clock-output-names = "oscclk3";
 		};
 
-		osc@4 {
+		oscclk4 {
 			/* Test chip gate configuration */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 4>;
@@ -173,7 +173,7 @@
 			clock-output-names = "oscclk4";
 		};
 
-		smbclk: osc@5 {
+		smbclk: oscclk5 {
 			/* SMB clock */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 5>;
@@ -182,7 +182,7 @@
 			clock-output-names = "oscclk5";
 		};
 
-		temp@0 {
+		temp-dcc {
 			/* DCC internal operating temperature */
 			compatible = "arm,vexpress-temp";
 			arm,vexpress-sysreg,func = <4 0>;
@@ -190,7 +190,7 @@
 		};
 	};
 
-	smb {
+	smb@08000000 {
 		compatible = "simple-bus";
 
 		#address-cells = <2>;
@@ -250,4 +250,17 @@
 
 		/include/ "vexpress-v2m-rs1.dtsi"
 	};
+
+	site2: hsb@40000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x40000000 0x40000000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 3>;
+		interrupt-map = <0 0 &gic 0 36 4>,
+				<0 1 &gic 0 37 4>,
+				<0 2 &gic 0 38 4>,
+				<0 3 &gic 0 39 4>;
+	};
 };
diff --git a/sys/gnu/dts/arm/vexpress-v2p-ca9.dts b/sys/gnu/dts/arm/vexpress-v2p-ca9.dts
index d949facba376..b608a03ee02f 100644
--- a/sys/gnu/dts/arm/vexpress-v2p-ca9.dts
+++ b/sys/gnu/dts/arm/vexpress-v2p-ca9.dts
@@ -190,7 +190,7 @@
 		compatible = "arm,vexpress,config-bus";
 		arm,vexpress,config-bridge = <&v2m_sysreg>;
 
-		osc@0 {
+		oscclk0: extsaxiclk {
 			/* ACLK clock to the AXI master port on the test chip */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 0>;
@@ -199,7 +199,7 @@
 			clock-output-names = "extsaxiclk";
 		};
 
-		oscclk1: osc@1 {
+		oscclk1: clcdclk {
 			/* Reference clock for the CLCD */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 1>;
@@ -208,7 +208,7 @@
 			clock-output-names = "clcdclk";
 		};
 
-		smbclk: oscclk2: osc@2 {
+		smbclk: oscclk2: tcrefclk {
 			/* Reference clock for the test chip internal PLLs */
 			compatible = "arm,vexpress-osc";
 			arm,vexpress-sysreg,func = <1 2>;
@@ -217,7 +217,7 @@
 			clock-output-names = "tcrefclk";
 		};
 
-		volt@0 {
+		volt-vd10 {
 			/* Test Chip internal logic voltage */
 			compatible = "arm,vexpress-volt";
 			arm,vexpress-sysreg,func = <2 0>;
@@ -226,7 +226,7 @@
 			label = "VD10";
 		};
 
-		volt@1 {
+		volt-vd10-s2 {
 			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
 			compatible = "arm,vexpress-volt";
 			arm,vexpress-sysreg,func = <2 1>;
@@ -235,7 +235,7 @@
 			label = "VD10_S2";
 		};
 
-		volt@2 {
+		volt-vd10-s3 {
 			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
 			compatible = "arm,vexpress-volt";
 			arm,vexpress-sysreg,func = <2 2>;
@@ -244,7 +244,7 @@
 			label = "VD10_S3";
 		};
 
-		volt@3 {
+		volt-vcc1v8 {
 			/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
 			compatible = "arm,vexpress-volt";
 			arm,vexpress-sysreg,func = <2 3>;
@@ -253,7 +253,7 @@
 			label = "VCC1V8";
 		};
 
-		volt@4 {
+		volt-ddr2vtt {
 			/* DDR2 SDRAM VTT termination voltage */
 			compatible = "arm,vexpress-volt";
 			arm,vexpress-sysreg,func = <2 4>;
@@ -262,7 +262,7 @@
 			label = "DDR2VTT";
 		};
 
-		volt@5 {
+		volt-vcc3v3 {
 			/* Local board supply for miscellaneous logic external to the Test Chip */
 			arm,vexpress-sysreg,func = <2 5>;
 			compatible = "arm,vexpress-volt";
@@ -271,28 +271,28 @@
 			label = "VCC3V3";
 		};
 
-		amp@0 {
+		amp-vd10-s2 {
 			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
 			compatible = "arm,vexpress-amp";
 			arm,vexpress-sysreg,func = <3 0>;
 			label = "VD10_S2";
 		};
 
-		amp@1 {
+		amp-vd10-s3 {
 			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
 			compatible = "arm,vexpress-amp";
 			arm,vexpress-sysreg,func = <3 1>;
 			label = "VD10_S3";
 		};
 
-		power@0 {
+		power-vd10-s2 {
 			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
 			compatible = "arm,vexpress-power";
 			arm,vexpress-sysreg,func = <12 0>;
 			label = "PVD10_S2";
 		};
 
-		power@1 {
+		power-vd10-s3 {
 			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
 			compatible = "arm,vexpress-power";
 			arm,vexpress-sysreg,func = <12 1>;
@@ -300,7 +300,7 @@
 		};
 	};
 
-	smb {
+	smb@04000000 {
 		compatible = "simple-bus";
 
 		#address-cells = <2>;
@@ -359,4 +359,17 @@
 
 		/include/ "vexpress-v2m.dtsi"
 	};
+
+	site2: hsb@e0000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xe0000000 0x20000000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 3>;
+		interrupt-map = <0 0 &gic 0 36 4>,
+				<0 1 &gic 0 37 4>,
+				<0 2 &gic 0 38 4>,
+				<0 3 &gic 0 39 4>;
+	};
 };
diff --git a/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi b/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi
index ed65e0f7dfc0..a8a8e434fb27 100644
--- a/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi
+++ b/sys/gnu/dts/arm/vf-colibri-eval-v3.dtsi
@@ -1,10 +1,42 @@
 /*
  * Copyright 2014 Toradex AG
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 / {
@@ -18,41 +50,51 @@
 		clock-frequency = <16000000>;
 	};
 
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		sys_5v0_reg: regulator@0 {
-			compatible = "regulator-fixed";
-			reg = <0>;
-			regulator-name = "5v0";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			regulator-always-on;
-		};
+	panel: panel {
+		compatible = "edt,et057090dhu";
+		backlight = <&bl>;
+	};
 
-		/* USBH_PEN */
-		usbh_vbus_reg: regulator@1 {
-			compatible = "regulator-fixed";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usbh1_reg>;
-			reg = <1>;
-			regulator-name = "usbh_vbus";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
-			vin-supply = <&sys_5v0_reg>;
-		};
+	reg_3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_5v0: regulator-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_usbh_vbus: regulator-usbh-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usbh1_reg>;
+		regulator-name = "VCC_USB[1-4]";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */
+		vin-supply = <&reg_5v0>;
 	};
 };
 
 &bl {
 	brightness-levels = <0 4 8 16 32 64 128 255>;
 	default-brightness-level = <6>;
+	power-supply = <&reg_3v3>;
 	status  = "okay";
 };
 
+&dcu0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dcu0_1>;
+	fsl,panel = <&panel>;
+	status = "okay";
+};
+
 &dspi1 {
 	status = "okay";
 
@@ -100,6 +142,14 @@
 	status = "okay";
 };
 
+&reg_module_3v3 {
+	vin-supply = <&reg_3v3>;
+};
+
+&tcon0 {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
@@ -113,7 +163,7 @@
 };
 
 &usbh1 {
-	vbus-supply = <&usbh_vbus_reg>;
+	vbus-supply = <&reg_usbh_vbus>;
 };
 
 &iomuxc {
diff --git a/sys/gnu/dts/arm/vf-colibri.dtsi b/sys/gnu/dts/arm/vf-colibri.dtsi
index 6e556be42ccd..b7417094dc11 100644
--- a/sys/gnu/dts/arm/vf-colibri.dtsi
+++ b/sys/gnu/dts/arm/vf-colibri.dtsi
@@ -1,26 +1,82 @@
 /*
  * Copyright 2014 Toradex AG
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 / {
+	aliases {
+		ethernet0 = &fec1;
+		ethernet1 = &fec0;
+	};
+
 	bl: backlight {
 		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_bl_on>;
 		pwms = <&pwm0 0 5000000 0>;
+		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
 		status = "disabled";
 	};
+
+	reg_module_3v3: regulator-module-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	reg_module_3v3_avdd: regulator-module-3v3-avdd {
+		compatible = "regulator-fixed";
+		regulator-name = "+V3.3_AVDD_AUDIO";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
 };
 
 &adc0 {
 	status = "okay";
+	vref-supply = <&reg_module_3v3_avdd>;
 };
 
 &adc1 {
 	status = "okay";
+	vref-supply = <&reg_module_3v3_avdd>;
 };
 
 &can0 {
@@ -35,6 +91,13 @@
 	status = "disabled";
 };
 
+&clks {
+	assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
+			  <&clks VF610_CLK_ENET_TS_SEL>;
+	assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
+				 <&clks VF610_CLK_ENET_50M>;
+};
+
 &dspi1 {
 	bus-num = <1>;
 	pinctrl-names = "default";
@@ -50,10 +113,12 @@
 	pinctrl-0 = <&pinctrl_esdhc1>;
 	bus-width = <4>;
 	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+	disable-wp;
 };
 
 &fec1 {
 	phy-mode = "rmii";
+	phy-supply = <&reg_module_3v3>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
 };
@@ -65,8 +130,6 @@
 };
 
 &nfc {
-	assigned-clocks = <&clks VF610_CLK_NFC>;
-	assigned-clock-rates = <33000000>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_nfc>;
 	status = "okay";
@@ -159,6 +222,39 @@
 			>;
 		};
 
+		pinctrl_dcu0_1: dcu0grp_1 {
+			fsl,pins = <
+				VF610_PAD_PTE0__DCU0_HSYNC	0x1902
+				VF610_PAD_PTE1__DCU0_VSYNC	0x1902
+				VF610_PAD_PTE2__DCU0_PCLK	0x1902
+				VF610_PAD_PTE4__DCU0_DE		0x1902
+				VF610_PAD_PTE5__DCU0_R0		0x1902
+				VF610_PAD_PTE6__DCU0_R1		0x1902
+				VF610_PAD_PTE7__DCU0_R2		0x1902
+				VF610_PAD_PTE8__DCU0_R3		0x1902
+				VF610_PAD_PTE9__DCU0_R4		0x1902
+				VF610_PAD_PTE10__DCU0_R5	0x1902
+				VF610_PAD_PTE11__DCU0_R6	0x1902
+				VF610_PAD_PTE12__DCU0_R7	0x1902
+				VF610_PAD_PTE13__DCU0_G0	0x1902
+				VF610_PAD_PTE14__DCU0_G1	0x1902
+				VF610_PAD_PTE15__DCU0_G2	0x1902
+				VF610_PAD_PTE16__DCU0_G3	0x1902
+				VF610_PAD_PTE17__DCU0_G4	0x1902
+				VF610_PAD_PTE18__DCU0_G5	0x1902
+				VF610_PAD_PTE19__DCU0_G6	0x1902
+				VF610_PAD_PTE20__DCU0_G7	0x1902
+				VF610_PAD_PTE21__DCU0_B0	0x1902
+				VF610_PAD_PTE22__DCU0_B1	0x1902
+				VF610_PAD_PTE23__DCU0_B2	0x1902
+				VF610_PAD_PTE24__DCU0_B3	0x1902
+				VF610_PAD_PTE25__DCU0_B4	0x1902
+				VF610_PAD_PTE26__DCU0_B5	0x1902
+				VF610_PAD_PTE27__DCU0_B6	0x1902
+				VF610_PAD_PTE28__DCU0_B7	0x1902
+			>;
+		};
+
 		pinctrl_dspi1: dspi1grp {
 			fsl,pins = <
 				VF610_PAD_PTD5__DSPI1_CS0		0x33e2
@@ -195,6 +291,12 @@
 			>;
 		};
 
+		pinctrl_gpio_bl_on: gpio_bl_on {
+			fsl,pins = <
+				VF610_PAD_PTC0__GPIO_45		0x22ef
+			>;
+		};
+
 		pinctrl_i2c0: i2c0grp {
 			fsl,pins = <
 				VF610_PAD_PTB14__I2C0_SCL		0x37ff
@@ -239,6 +341,8 @@
 			fsl,pins = <
 				VF610_PAD_PTB10__UART0_TX		0x21a2
 				VF610_PAD_PTB11__UART0_RX		0x21a1
+				VF610_PAD_PTB12__UART0_RTS		0x21a2
+				VF610_PAD_PTB13__UART0_CTS		0x21a1
 			>;
 		};
 
diff --git a/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts b/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts
index c3173fc9e833..b3aeab58f718 100644
--- a/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts
+++ b/sys/gnu/dts/arm/vf500-colibri-eval-v3.dts
@@ -1,10 +1,42 @@
 /*
  * Copyright 2014 Toradex AG
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/sys/gnu/dts/arm/vf500-colibri.dtsi b/sys/gnu/dts/arm/vf500-colibri.dtsi
index 84f091d1fcf2..1a8a0efa19a6 100644
--- a/sys/gnu/dts/arm/vf500-colibri.dtsi
+++ b/sys/gnu/dts/arm/vf500-colibri.dtsi
@@ -1,10 +1,42 @@
 /*
  * Copyright 2014 Toradex AG
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "vf500.dtsi"
@@ -37,6 +69,11 @@
 	};
 };
 
+&nfc {
+	assigned-clocks = <&clks VF610_CLK_NFC>;
+	assigned-clock-rates = <33000000>;
+};
+
 &iomuxc {
 	vf610-colibri {
 		pinctrl_touchctrl_idle: touchctrl_idle {
diff --git a/sys/gnu/dts/arm/vf500.dtsi b/sys/gnu/dts/arm/vf500.dtsi
index e976d2fa1527..a3824e61bd72 100644
--- a/sys/gnu/dts/arm/vf500.dtsi
+++ b/sys/gnu/dts/arm/vf500.dtsi
@@ -1,10 +1,42 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "skeleton.dtsi"
@@ -43,6 +75,16 @@
 				clocks = <&clks VF610_CLK_PLATFORM_BUS>;
 			};
 		};
+
+		aips-bus@40080000 {
+			pmu@40089000 {
+				compatible = "arm,cortex-a5-pmu";
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-affinity = <&a5_cpu>;
+				reg = <0x40089000 0x1000>;
+			};
+		};
+
 	};
 };
 
diff --git a/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts b/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts
index 10ebe99e2751..dbca4f86fdbb 100644
--- a/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts
+++ b/sys/gnu/dts/arm/vf610-colibri-eval-v3.dts
@@ -1,10 +1,42 @@
 /*
  * Copyright 2014 Toradex AG
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -14,4 +46,4 @@
 / {
 	model = "Toradex Colibri VF61 on Colibri Evaluation Board";
 	compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
-};
\ No newline at end of file
+};
diff --git a/sys/gnu/dts/arm/vf610-colibri.dtsi b/sys/gnu/dts/arm/vf610-colibri.dtsi
index 2d7eab755210..9ec9e337f5a8 100644
--- a/sys/gnu/dts/arm/vf610-colibri.dtsi
+++ b/sys/gnu/dts/arm/vf610-colibri.dtsi
@@ -1,10 +1,42 @@
 /*
  * Copyright 2014 Toradex AG
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "vf610.dtsi"
@@ -18,3 +50,8 @@
 		reg = <0x80000000 0x10000000>;
 	};
 };
+
+&nfc {
+	assigned-clocks = <&clks VF610_CLK_NFC>;
+	assigned-clock-rates = <50000000>;
+};
diff --git a/sys/gnu/dts/arm/vf610-twr.dts b/sys/gnu/dts/arm/vf610-twr.dts
index 5438ee4be2ec..cdc100732514 100644
--- a/sys/gnu/dts/arm/vf610-twr.dts
+++ b/sys/gnu/dts/arm/vf610-twr.dts
@@ -1,10 +1,42 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -96,6 +128,10 @@
 &clks {
 	clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
 	clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
+	assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
+			  <&clks VF610_CLK_ENET_TS_SEL>;
+	assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>,
+				 <&clks VF610_CLK_ENET_EXT>;
 };
 
 &dspi0 {
diff --git a/sys/gnu/dts/arm/vf610-zii-dev-rev-b.dts b/sys/gnu/dts/arm/vf610-zii-dev-rev-b.dts
new file mode 100644
index 000000000000..6c60b7f91104
--- /dev/null
+++ b/sys/gnu/dts/arm/vf610-zii-dev-rev-b.dts
@@ -0,0 +1,734 @@
+/*
+ * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
+ *
+ * Based on an original 'vf610-twr.dts' which is Copyright 2015,
+ * Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "vf610.dtsi"
+
+/ {
+	model = "ZII VF610 Development Board, Rev B";
+	compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pinctrl_leds_debug>;
+		pinctrl-names = "default";
+
+		debug {
+			label = "zii:green:debug1";
+			gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	mdio-mux {
+		compatible = "mdio-mux-gpio";
+		pinctrl-0 = <&pinctrl_mdio_mux>;
+		pinctrl-names = "default";
+		gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
+			 &gpio0 9  GPIO_ACTIVE_HIGH
+			 &gpio0 24 GPIO_ACTIVE_HIGH
+			 &gpio0 25 GPIO_ACTIVE_HIGH>;
+		mdio-parent-bus = <&mdio1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mdio_mux_1: mdio@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mdio_mux_2: mdio@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mdio_mux_4: mdio@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mdio_mux_8: mdio@8 {
+			reg = <8>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	dsa {
+		compatible = "marvell,dsa";
+		#address-cells = <2>;
+		#size-cells = <0>;
+		dsa,ethernet = <&fec1>;
+		dsa,mii-bus = <&mdio_mux_1>;
+
+		/* 6352 - Primary - 7 ports */
+		switch0: switch@0-0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x00 0>;
+			eeprom-length = <512>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan0";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan1";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+			};
+
+			switch0port5: port@5 {
+				reg = <5>;
+				label = "dsa";
+				phy-mode = "rgmii-txid";
+				link = <&switch1port6
+					&switch2port9>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				label = "cpu";
+
+				fixed-link {
+					speed = <100>;
+					full-duplex;
+				};
+			};
+
+		};
+
+		/* 6352 - Secondary - 7 ports */
+		switch1: switch@0-1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x00 1>;
+			eeprom-length = <512>;
+			mii-bus = <&mdio_mux_2>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan3";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan4";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan5";
+			};
+
+			switch1port5: port@5 {
+				reg = <5>;
+				label = "dsa";
+				link = <&switch2port9>;
+				phy-mode = "rgmii-txid";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			switch1port6: port@6 {
+				reg = <6>;
+				label = "dsa";
+				phy-mode = "rgmii-txid";
+				link = <&switch0port5>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+
+		/* 6185 - 10 ports */
+		switch2: switch@0-2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x00 2>;
+			mii-bus = <&mdio_mux_4>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan6";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan7";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan8";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "optical3";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+					link-gpios = <&gpio6 2
+						      GPIO_ACTIVE_HIGH>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "optical4";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+					link-gpios = <&gpio6 3
+						      GPIO_ACTIVE_HIGH>;
+				};
+			};
+
+			switch2port9: port@9 {
+				reg = <9>;
+				label = "dsa";
+				phy-mode = "rgmii-txid";
+				link = <&switch1port5
+					&switch0port5>;
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+
+	reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_mcu";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	usb0_vbus: regulator-usb0-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-0 = <&pinctrl_usb_vbus>;
+		regulator-name = "usb_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+		gpio = <&gpio0 6 0>;
+	};
+
+	spi0 {
+		compatible = "spi-gpio";
+		pinctrl-0 = <&pinctrl_gpio_spi0>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+		gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
+			     &gpio1  8 GPIO_ACTIVE_HIGH>;
+		num-chipselects = <2>;
+
+		m25p128@0 {
+			compatible = "m25p128", "jedec,spi-nor";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0>;
+			spi-max-frequency = <1000000>;
+		};
+
+		at93c46d@1 {
+			compatible = "atmel,at93c46d";
+			pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
+			pinctrl-names = "default";
+			#address-cells = <0>;
+			#size-cells = <0>;
+			reg = <1>;
+			spi-max-frequency = <500000>;
+			spi-cs-high;
+			data-size = <16>;
+			select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&adc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc0_ad5>;
+	vref-supply = <&reg_vcc_3v3_mcu>;
+	status = "okay";
+};
+
+&edma0 {
+	status = "okay";
+};
+
+&esdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esdhc1>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&fec0 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec0>;
+	status = "okay";
+};
+
+&fec1 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	status = "okay";
+
+	fixed-link {
+		   speed = <100>;
+		   full-duplex;
+	};
+
+	mdio1: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+	};
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>;
+	status = "okay";
+
+	gpio5: pca9554@20 {
+		compatible = "nxp,pca9554";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+	};
+
+	gpio6: pca9554@22 {
+		compatible = "nxp,pca9554";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pca9554_22>;
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	lm75@48 {
+		compatible = "national,lm75";
+		reg = <0x48>;
+	};
+
+	at24c04@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+	};
+
+	at24c04@52 {
+		compatible = "atmel,24c04";
+		reg = <0x52>;
+	};
+
+	ds1682@6b {
+		compatible = "dallas,ds1682";
+		reg = <0x6b>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	tca9548@70 {
+		compatible = "nxp,pca9548";
+		pinctrl-0 = <&pinctrl_i2c_mux_reset>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			sfp1: at24c04@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			sfp2: at24c04@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			sfp3: at24c04@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			sfp4: at24c04@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart0>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usbdev0 {
+	disable-over-current;
+	vbus-supply = <&usb0_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbh1 {
+	disable-over-current;
+	status = "okay";
+};
+
+&usbmisc0 {
+	status = "okay";
+};
+
+&usbmisc1 {
+	status = "okay";
+};
+
+&usbphy0 {
+	status = "okay";
+};
+
+&usbphy1 {
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_adc0_ad5: adc0ad5grp {
+		fsl,pins = <
+			VF610_PAD_PTC30__ADC0_SE5	0x00a1
+		>;
+	};
+
+	pinctrl_dspi0: dspi0grp {
+		fsl,pins = <
+			VF610_PAD_PTB18__DSPI0_CS1	0x1182
+			VF610_PAD_PTB19__DSPI0_CS0	0x1182
+			VF610_PAD_PTB20__DSPI0_SIN	0x1181
+			VF610_PAD_PTB21__DSPI0_SOUT	0x1182
+			VF610_PAD_PTB22__DSPI0_SCK	0x1182
+		>;
+	};
+
+	pinctrl_dspi2: dspi2grp {
+		fsl,pins = <
+			VF610_PAD_PTD31__DSPI2_CS1	0x1182
+			VF610_PAD_PTD30__DSPI2_CS0	0x1182
+			VF610_PAD_PTD29__DSPI2_SIN	0x1181
+			VF610_PAD_PTD28__DSPI2_SOUT	0x1182
+			VF610_PAD_PTD27__DSPI2_SCK	0x1182
+		>;
+	};
+
+	pinctrl_esdhc1: esdhc1grp {
+		fsl,pins = <
+			VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
+			VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
+			VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
+			VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
+			VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
+			VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
+			VF610_PAD_PTA7__GPIO_134	0x219d
+		>;
+	};
+
+	pinctrl_fec0: fec0grp {
+		fsl,pins = <
+			VF610_PAD_PTC0__ENET_RMII0_MDC	0x30d2
+			VF610_PAD_PTC1__ENET_RMII0_MDIO	0x30d3
+			VF610_PAD_PTC2__ENET_RMII0_CRS	0x30d1
+			VF610_PAD_PTC3__ENET_RMII0_RXD1	0x30d1
+			VF610_PAD_PTC4__ENET_RMII0_RXD0	0x30d1
+			VF610_PAD_PTC5__ENET_RMII0_RXER	0x30d1
+			VF610_PAD_PTC6__ENET_RMII0_TXD1	0x30d2
+			VF610_PAD_PTC7__ENET_RMII0_TXD0	0x30d2
+			VF610_PAD_PTC8__ENET_RMII0_TXEN	0x30d2
+		>;
+	};
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			VF610_PAD_PTA6__RMII_CLKIN		0x30d1
+			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
+			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
+			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
+			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
+			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
+			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
+			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
+			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
+			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
+		>;
+	};
+
+	pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
+		fsl,pins = <
+			VF610_PAD_PTE27__GPIO_132	0x33e2
+		>;
+	};
+
+	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
+		fsl,pins = <
+			VF610_PAD_PTB22__GPIO_44	0x33e2
+			VF610_PAD_PTB21__GPIO_43	0x33e2
+			VF610_PAD_PTB20__GPIO_42	0x33e1
+			VF610_PAD_PTB19__GPIO_41	0x33e2
+			VF610_PAD_PTB18__GPIO_40	0x33e2
+		>;
+	};
+
+	pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
+		fsl,pins = <
+			 VF610_PAD_PTE14__GPIO_119	0x31c2
+			 >;
+	};
+
+	pinctrl_i2c0: i2c0grp {
+		fsl,pins = <
+			VF610_PAD_PTB14__I2C0_SCL	0x37ff
+			VF610_PAD_PTB15__I2C0_SDA	0x37ff
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			VF610_PAD_PTB16__I2C1_SCL	0x37ff
+			VF610_PAD_PTB17__I2C1_SDA	0x37ff
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			VF610_PAD_PTA22__I2C2_SCL	0x37ff
+			VF610_PAD_PTA23__I2C2_SDA	0x37ff
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			VF610_PAD_PTA30__I2C3_SCL	0x37ff
+			VF610_PAD_PTA31__I2C3_SDA	0x37ff
+		>;
+	};
+
+	pinctrl_leds_debug: pinctrl-leds-debug {
+		fsl,pins = <
+			 VF610_PAD_PTD20__GPIO_74	0x31c2
+			 >;
+	};
+
+	pinctrl_mdio_mux: pinctrl-mdio-mux {
+		fsl,pins = <
+			VF610_PAD_PTA18__GPIO_8		0x31c2
+			VF610_PAD_PTA19__GPIO_9		0x31c2
+			VF610_PAD_PTB2__GPIO_24		0x31c2
+			VF610_PAD_PTB3__GPIO_25		0x31c2
+		>;
+	};
+
+	pinctrl_pca9554_22: pinctrl-pca95540-22 {
+		fsl,pins = <
+			VF610_PAD_PTB28__GPIO_98	0x219d
+		>;
+	};
+
+	pinctrl_pwm0: pwm0grp {
+		fsl,pins = <
+			VF610_PAD_PTB0__FTM0_CH0	0x1582
+			VF610_PAD_PTB1__FTM0_CH1	0x1582
+			VF610_PAD_PTB2__FTM0_CH2	0x1582
+			VF610_PAD_PTB3__FTM0_CH3	0x1582
+		>;
+	};
+
+	pinctrl_qspi0: qspi0grp {
+		fsl,pins = <
+			VF610_PAD_PTD7__QSPI0_B_QSCK	0x31c3
+			VF610_PAD_PTD8__QSPI0_B_CS0	0x31ff
+			VF610_PAD_PTD9__QSPI0_B_DATA3	0x31c3
+			VF610_PAD_PTD10__QSPI0_B_DATA2	0x31c3
+			VF610_PAD_PTD11__QSPI0_B_DATA1	0x31c3
+			VF610_PAD_PTD12__QSPI0_B_DATA0	0x31c3
+		>;
+	};
+
+	pinctrl_uart0: uart0grp {
+		fsl,pins = <
+			VF610_PAD_PTB10__UART0_TX	0x21a2
+			VF610_PAD_PTB11__UART0_RX	0x21a1
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			VF610_PAD_PTB23__UART1_TX	0x21a2
+			VF610_PAD_PTB24__UART1_RX	0x21a1
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			VF610_PAD_PTD0__UART2_TX	0x21a2
+			VF610_PAD_PTD1__UART2_RX	0x21a1
+		>;
+	};
+
+	pinctrl_usb_vbus: pinctrl-usb-vbus {
+		fsl,pins = <
+			VF610_PAD_PTA16__GPIO_6	0x31c2
+		>;
+	};
+
+	pinctrl_usb0_host: usb0-host-grp {
+		fsl,pins = <
+			VF610_PAD_PTD6__GPIO_85		0x0062
+		>;
+	};
+};
diff --git a/sys/gnu/dts/arm/vf610.dtsi b/sys/gnu/dts/arm/vf610.dtsi
index 58bc6e448be5..0cfc060f94d7 100644
--- a/sys/gnu/dts/arm/vf610.dtsi
+++ b/sys/gnu/dts/arm/vf610.dtsi
@@ -1,10 +1,42 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "vf500.dtsi"
diff --git a/sys/gnu/dts/arm/vfxxx.dtsi b/sys/gnu/dts/arm/vfxxx.dtsi
index a9ceb5bac40e..2c13ec696ac5 100644
--- a/sys/gnu/dts/arm/vfxxx.dtsi
+++ b/sys/gnu/dts/arm/vfxxx.dtsi
@@ -1,10 +1,42 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "vf610-pinfunc.h"
@@ -16,6 +48,8 @@
 	aliases {
 		can0 = &can0;
 		can1 = &can1;
+		ethernet0 = &fec0;
+		ethernet1 = &fec1;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		serial2 = &uart2;
@@ -61,6 +95,7 @@
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
+			reg = <0x40000000 0x00070000>;
 			ranges;
 
 			mscm_cpucfg: cpucfg@40001000 {
@@ -174,6 +209,34 @@
 				status = "disabled";
 			};
 
+			sai0: sai@4002f000 {
+				compatible = "fsl,vf610-sai";
+				reg = <0x4002f000 0x1000>;
+				interrupts = <84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks VF610_CLK_SAI0>,
+					<&clks VF610_CLK_SAI0_DIV>,
+					<&clks 0>, <&clks 0>;
+				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				dma-names = "tx", "rx";
+				dmas = <&edma0 0 17>,
+					<&edma0 0 16>;
+				status = "disabled";
+			};
+
+			sai1: sai@40030000 {
+				compatible = "fsl,vf610-sai";
+				reg = <0x40030000 0x1000>;
+				interrupts = <85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks VF610_CLK_SAI1>,
+					<&clks VF610_CLK_SAI1_DIV>,
+					<&clks 0>, <&clks 0>;
+				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				dma-names = "tx", "rx";
+				dmas = <&edma0 0 19>,
+					<&edma0 0 18>;
+				status = "disabled";
+			};
+
 			sai2: sai@40031000 {
 				compatible = "fsl,vf610-sai";
 				reg = <0x40031000 0x1000>;
@@ -188,6 +251,20 @@
 				status = "disabled";
 			};
 
+			sai3: sai@40032000 {
+				compatible = "fsl,vf610-sai";
+				reg = <0x40032000 0x1000>;
+				interrupts = <87 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks VF610_CLK_SAI3>,
+					<&clks VF610_CLK_SAI3_DIV>,
+					<&clks 0>, <&clks 0>;
+				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				dma-names = "tx", "rx";
+				dmas = <&edma0 1 9>,
+					<&edma0 1 8>;
+				status = "disabled";
+			};
+
 			pit: pit@40037000 {
 				compatible = "fsl,vf610-pit";
 				reg = <0x40037000 0x1000>;
@@ -234,6 +311,14 @@
 							<20000000>;
 			};
 
+			tcon0: timing-controller@4003d000 {
+				compatible = "fsl,vf610-tcon";
+				reg = <0x4003d000 0x1000>;
+				clocks = <&clks VF610_CLK_TCON0>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
 			wdoga5: wdog@4003e000 {
 				compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
 				reg = <0x4003e000 0x1000>;
@@ -339,6 +424,17 @@
 				status = "disabled";
 			};
 
+			dcu0: dcu@40058000 {
+				compatible = "fsl,vf610-dcu";
+				reg = <0x40058000 0x1200>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks VF610_CLK_DCU0>,
+					<&clks VF610_CLK_DCU0_DIV>;
+				clock-names = "dcu", "pix";
+				fsl,tcon = <&tcon0>;
+				status = "disabled";
+			};
+
 			i2c0: i2c@40066000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -405,6 +501,7 @@
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
+			reg = <0x40080000 0x0007f000>;
 			ranges;
 
 			edma1: dma-controller@40098000 {
@@ -558,6 +655,24 @@
 				status = "disabled";
 			};
 
+			dac0: dac@400cc000 {
+				compatible = "fsl,vf610-dac";
+				reg = <0x400cc000 1000>;
+				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "dac";
+				clocks = <&clks VF610_CLK_DAC0>;
+				status = "disabled";
+			};
+
+			dac1: dac@400cd000 {
+				compatible = "fsl,vf610-dac";
+				reg = <0x400cd000 1000>;
+				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "dac";
+				clocks = <&clks VF610_CLK_DAC1>;
+				status = "disabled";
+			};
+
 			fec0: ethernet@400d0000 {
 				compatible = "fsl,mvf600-fec";
 				reg = <0x400d0000 0x1000>;
@@ -629,5 +744,10 @@
 				status = "disabled";
 			};
 		};
+
+		iio-hwmon {
+			compatible = "iio-hwmon";
+			io-channels = <&adc0 16>, <&adc1 16>;
+		};
 	};
 };
diff --git a/sys/gnu/dts/arm/wd-mbwe.dts b/sys/gnu/dts/arm/wd-mbwe.dts
new file mode 100644
index 000000000000..ac3250ae8fc4
--- /dev/null
+++ b/sys/gnu/dts/arm/wd-mbwe.dts
@@ -0,0 +1,112 @@
+/*
+ * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+#include "ox810se.dtsi"
+
+/ {
+	model = "Western Digital My Book World Edition";
+
+	compatible = "wd,mbwe", "oxsemi,ox810se";
+
+	chosen {
+		bootargs = "console=ttyS1,115200n8 earlyprintk=serial";
+	};
+
+	memory {
+		/* 128Mbytes DDR */
+		reg = <0x48000000 0x8000000>;
+	};
+
+	aliases {
+		serial1 = &uart1;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		power {
+			label = "power";
+			gpios = <&gpio0 0 1>;
+			linux,code = <0x198>;
+		};
+
+		recovery {
+			label = "recovery";
+			gpios = <&gpio0 4 1>;
+			linux,code = <0xab>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		a0 {
+			label = "activity0";
+			gpios = <&gpio0 25 0>;
+			default-state = "keep";
+		};
+
+		a1 {
+			label = "activity1";
+			gpios = <&gpio0 26 0>;
+			default-state = "keep";
+		};
+
+		a2 {
+			label = "activity2";
+			gpios = <&gpio0 5 0>;
+			default-state = "keep";
+		};
+
+		a3 {
+			label = "activity3";
+			gpios = <&gpio0 6 0>;
+			default-state = "keep";
+		};
+
+		a4 {
+			label = "activity4";
+			gpios = <&gpio0 7 0>;
+			default-state = "keep";
+		};
+
+		a5 {
+			label = "activity5";
+			gpios = <&gpio1 2 0>;
+			default-state = "keep";
+		};
+	};
+
+	i2c-gpio {
+		compatible = "i2c-gpio";
+		gpios = <&gpio0 3 0 /* sda */
+			 &gpio0 2 0 /* scl */
+			 >;
+		i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rtc0: rtc@48 {
+			compatible = "st,m41t00";
+			reg = <0x68>;
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+};
diff --git a/sys/gnu/dts/arm/zynq-parallella.dts b/sys/gnu/dts/arm/zynq-parallella.dts
index 9efd16cb2859..307ed201d658 100644
--- a/sys/gnu/dts/arm/zynq-parallella.dts
+++ b/sys/gnu/dts/arm/zynq-parallella.dts
@@ -34,7 +34,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
+		bootargs = "earlycon root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
 		stdout-path = "serial0:115200n8";
 	};
 };
diff --git a/sys/gnu/dts/arm/zynq-zc702.dts b/sys/gnu/dts/arm/zynq-zc702.dts
index cb64209bca08..e96959b2e67a 100644
--- a/sys/gnu/dts/arm/zynq-zc702.dts
+++ b/sys/gnu/dts/arm/zynq-zc702.dts
@@ -30,7 +30,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/sys/gnu/dts/arm/zynq-zc706.dts b/sys/gnu/dts/arm/zynq-zc706.dts
index abf5d238ae04..be6a986bbbd8 100644
--- a/sys/gnu/dts/arm/zynq-zc706.dts
+++ b/sys/gnu/dts/arm/zynq-zc706.dts
@@ -30,7 +30,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/sys/gnu/dts/arm/zynq-zed.dts b/sys/gnu/dts/arm/zynq-zed.dts
index b9f2522012e8..7250c1eac7f9 100644
--- a/sys/gnu/dts/arm/zynq-zed.dts
+++ b/sys/gnu/dts/arm/zynq-zed.dts
@@ -29,7 +29,7 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
 	};
 
diff --git a/sys/gnu/dts/arm/zynq-zybo.dts b/sys/gnu/dts/arm/zynq-zybo.dts
index 16c9cacd668d..d9e0f3e70671 100644
--- a/sys/gnu/dts/arm/zynq-zybo.dts
+++ b/sys/gnu/dts/arm/zynq-zybo.dts
@@ -29,10 +29,15 @@
 	};
 
 	chosen {
-		bootargs = "earlyprintk";
+		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
 	};
 
+	usb_phy0: phy0 {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio0 46 1>;
+	};
 };
 
 &clkc {
@@ -56,3 +61,9 @@
 &uart1 {
 	status = "okay";
 };
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};
diff --git a/sys/gnu/dts/include/dt-bindings/clock/ath79-clk.h b/sys/gnu/dts/include/dt-bindings/clock/ath79-clk.h
new file mode 100644
index 000000000000..27359ad83904
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/clock/ath79-clk.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_ATH79_CLK_H
+#define __DT_BINDINGS_ATH79_CLK_H
+
+#define ATH79_CLK_CPU		0
+#define ATH79_CLK_DDR		1
+#define ATH79_CLK_AHB		2
+
+#define ATH79_CLK_END		3
+
+#endif /* __DT_BINDINGS_ATH79_CLK_H */
diff --git a/sys/gnu/dts/include/dt-bindings/clock/axis,artpec6-clkctrl.h b/sys/gnu/dts/include/dt-bindings/clock/axis,artpec6-clkctrl.h
new file mode 100644
index 000000000000..f9f04dccc996
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/clock/axis,artpec6-clkctrl.h
@@ -0,0 +1,38 @@
+/*
+ * ARTPEC-6 clock controller indexes
+ *
+ * Copyright 2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+
+#define ARTPEC6_CLK_CPU			0
+#define ARTPEC6_CLK_CPU_PERIPH		1
+#define ARTPEC6_CLK_NAND_CLKA		2
+#define ARTPEC6_CLK_NAND_CLKB		3
+#define ARTPEC6_CLK_ETH_ACLK		4
+#define ARTPEC6_CLK_DMA_ACLK		5
+#define ARTPEC6_CLK_PTP_REF		6
+#define ARTPEC6_CLK_SD_PCLK		7
+#define ARTPEC6_CLK_SD_IMCLK		8
+#define ARTPEC6_CLK_I2S_HST		9
+#define ARTPEC6_CLK_I2S0_CLK		10
+#define ARTPEC6_CLK_I2S1_CLK		11
+#define ARTPEC6_CLK_UART_PCLK		12
+#define ARTPEC6_CLK_UART_REFCLK		13
+#define ARTPEC6_CLK_I2C			14
+#define ARTPEC6_CLK_SPI_PCLK		15
+#define ARTPEC6_CLK_SPI_SSPCLK		16
+#define ARTPEC6_CLK_SYS_TIMER		17
+#define ARTPEC6_CLK_FRACDIV_IN		18
+#define ARTPEC6_CLK_DBG_PCLK		19
+
+/* This must be the highest clock index plus one. */
+#define ARTPEC6_CLK_NUMCLOCKS		20
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm-cygnus.h b/sys/gnu/dts/include/dt-bindings/clock/bcm-cygnus.h
index 32fbc475087a..62ac5d782a00 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/bcm-cygnus.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/bcm-cygnus.h
@@ -65,4 +65,10 @@
 #define BCM_CYGNUS_ASIU_ADC_CLK       1
 #define BCM_CYGNUS_ASIU_PWM_CLK       2
 
+/* AUDIO clock ID */
+#define BCM_CYGNUS_AUDIOPLL           0
+#define BCM_CYGNUS_AUDIOPLL_CH0       1
+#define BCM_CYGNUS_AUDIOPLL_CH1       2
+#define BCM_CYGNUS_AUDIOPLL_CH2       3
+
 #endif /* _CLOCK_BCM_CYGNUS_H */
diff --git a/sys/gnu/dts/include/dt-bindings/clock/bcm2835.h b/sys/gnu/dts/include/dt-bindings/clock/bcm2835.h
index 61f1d20c2a67..360e00cefd35 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/bcm2835.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/bcm2835.h
@@ -44,5 +44,23 @@
 #define BCM2835_CLOCK_EMMC		28
 #define BCM2835_CLOCK_PERI_IMAGE	29
 #define BCM2835_CLOCK_PWM		30
+#define BCM2835_CLOCK_PCM		31
 
-#define BCM2835_CLOCK_COUNT		31
+#define BCM2835_PLLA_DSI0		32
+#define BCM2835_PLLA_CCP2		33
+#define BCM2835_PLLD_DSI0		34
+#define BCM2835_PLLD_DSI1		35
+
+#define BCM2835_CLOCK_AVEO		36
+#define BCM2835_CLOCK_DFT		37
+#define BCM2835_CLOCK_GP0		38
+#define BCM2835_CLOCK_GP1		39
+#define BCM2835_CLOCK_GP2		40
+#define BCM2835_CLOCK_SLIM		41
+#define BCM2835_CLOCK_SMI		42
+#define BCM2835_CLOCK_TEC		43
+#define BCM2835_CLOCK_DPI		44
+#define BCM2835_CLOCK_CAM0		45
+#define BCM2835_CLOCK_CAM1		46
+#define BCM2835_CLOCK_DSI0E		47
+#define BCM2835_CLOCK_DSI1E		48
diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h b/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h
index 63d01c15d2b3..c796ff02ceeb 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/exynos3250.h
@@ -79,6 +79,8 @@
 #define CLK_MOUT_CORE			58
 #define CLK_MOUT_APLL			59
 #define CLK_MOUT_ACLK_266_SUB		60
+#define CLK_MOUT_UART2			61
+#define CLK_MOUT_MMC2			62
 
 /* Dividers */
 #define CLK_DIV_GPL			64
@@ -127,6 +129,9 @@
 #define CLK_DIV_CORE			107
 #define CLK_DIV_HPM			108
 #define CLK_DIV_COPY			109
+#define CLK_DIV_UART2			110
+#define CLK_DIV_MMC2_PRE		111
+#define CLK_DIV_MMC2			112
 
 /* Gates */
 #define CLK_ASYNC_G3D			128
@@ -223,6 +228,8 @@
 #define CLK_BLOCK_MFC			219
 #define CLK_BLOCK_CAM			220
 #define CLK_SMIES			221
+#define CLK_UART2			222
+#define CLK_SDMMC2			223
 
 /* Special clocks */
 #define CLK_SCLK_JPEG			224
@@ -249,12 +256,14 @@
 #define CLK_SCLK_SPI0			245
 #define CLK_SCLK_UART1			246
 #define CLK_SCLK_UART0			247
+#define CLK_SCLK_UART2			248
+#define CLK_SCLK_MMC2			249
 
 /*
  * Total number of clocks of main CMU.
  * NOTE: Must be equal to last clock ID increased by one.
  */
-#define CLK_NR_CLKS			248
+#define CLK_NR_CLKS			250
 
 /*
  * CMU DMC
diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h
index 7699ee9c16c0..17ab8394bec7 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/exynos5420.h
@@ -217,8 +217,30 @@
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
+#define CLK_DOUT_ACLK400_WCORE	769
+#define CLK_DOUT_ACLK400_ISP	770
+#define CLK_DOUT_ACLK400_MSCL	771
+#define CLK_DOUT_ACLK200	772
+#define CLK_DOUT_ACLK200_FSYS2	773
+#define CLK_DOUT_ACLK100_NOC	774
+#define CLK_DOUT_PCLK200_FSYS	775
+#define CLK_DOUT_ACLK200_FSYS	776
+#define CLK_DOUT_ACLK333_432_GSCL	777
+#define CLK_DOUT_ACLK333_432_ISP	778
+#define CLK_DOUT_ACLK66		779
+#define CLK_DOUT_ACLK333_432_ISP0	780
+#define CLK_DOUT_ACLK266	781
+#define CLK_DOUT_ACLK166	782
+#define CLK_DOUT_ACLK333	783
+#define CLK_DOUT_ACLK333_G2D	784
+#define CLK_DOUT_ACLK266_G2D	785
+#define CLK_DOUT_ACLK_G3D	786
+#define CLK_DOUT_ACLK300_JPEG	787
+#define CLK_DOUT_ACLK300_DISP1	788
+#define CLK_DOUT_ACLK300_GSCL	789
+#define CLK_DOUT_ACLK400_DISP1	790
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS		769
+#define CLK_NR_CLKS		791
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
diff --git a/sys/gnu/dts/include/dt-bindings/clock/exynos5433.h b/sys/gnu/dts/include/dt-bindings/clock/exynos5433.h
index 5bd80d5ecd0f..8e024fea26e7 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/exynos5433.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/exynos5433.h
@@ -765,7 +765,12 @@
 #define CLK_SCLK_RGB_VCLK				109
 #define CLK_SCLK_RGB_TV_VCLK				110
 
-#define DISP_NR_CLK					111
+#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY		111
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY		112
+
+#define CLK_PCLK_DECON					113
+
+#define DISP_NR_CLK					114
 
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER				1
@@ -1298,7 +1303,7 @@
 #define CLK_MOUT_ACLK_LITE_C_B				13
 #define CLK_MOUT_ACLK_LITE_C_A				14
 
-#define CLK_DIV_SCLK_ISP_WPWM				15
+#define CLK_DIV_SCLK_ISP_MPWM				15
 #define CLK_DIV_PCLK_CAM1_83				16
 #define CLK_DIV_PCLK_CAM1_166				17
 #define CLK_DIV_PCLK_DBG_CAM1				18
diff --git a/sys/gnu/dts/include/dt-bindings/clock/hi3519-clock.h b/sys/gnu/dts/include/dt-bindings/clock/hi3519-clock.h
new file mode 100644
index 000000000000..14f4d2184e5a
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/clock/hi3519-clock.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FMC_CLK			1
+#define HI3519_SPI0_CLK			2
+#define HI3519_SPI1_CLK			3
+#define HI3519_SPI2_CLK			4
+#define HI3519_UART0_CLK		5
+#define HI3519_UART1_CLK		6
+#define HI3519_UART2_CLK		7
+#define HI3519_UART3_CLK		8
+#define HI3519_UART4_CLK		9
+#define HI3519_PWM_CLK			10
+#define HI3519_DMA_CLK			11
+#define HI3519_IR_CLK			12
+#define HI3519_ETH_PHY_CLK		13
+#define HI3519_ETH_MAC_CLK		14
+#define HI3519_ETH_MACIF_CLK		15
+#define HI3519_USB2_BUS_CLK		16
+#define HI3519_USB2_PORT_CLK		17
+#define HI3519_USB3_CLK			18
+
+#endif	/* __DTS_HI3519_CLOCK_H */
diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h
index 77985cc43316..29050337d9d5 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/imx6qdl-clock.h
@@ -255,6 +255,20 @@
 #define IMX6QDL_CLK_CAAM_ACLK			242
 #define IMX6QDL_CLK_CAAM_IPG			243
 #define IMX6QDL_CLK_SPDIF_GCLK			244
-#define IMX6QDL_CLK_END				245
+#define IMX6QDL_CLK_UART_SEL			245
+#define IMX6QDL_CLK_IPG_PER_SEL			246
+#define IMX6QDL_CLK_ECSPI_SEL			247
+#define IMX6QDL_CLK_CAN_SEL			248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
+#define IMX6QDL_CLK_PRE0			250
+#define IMX6QDL_CLK_PRE1			251
+#define IMX6QDL_CLK_PRE2			252
+#define IMX6QDL_CLK_PRE3			253
+#define IMX6QDL_CLK_PRG0_AXI			254
+#define IMX6QDL_CLK_PRG1_AXI			255
+#define IMX6QDL_CLK_PRG0_APB			256
+#define IMX6QDL_CLK_PRG1_APB			257
+#define IMX6QDL_CLK_PRE_AXI			258
+#define IMX6QDL_CLK_END				259
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h
index c343894ce603..fd8aee8f64ae 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h
@@ -21,13 +21,13 @@
 #define IMX6UL_PLL5_BYPASS_SRC		8
 #define IMX6UL_PLL6_BYPASS_SRC		9
 #define IMX6UL_PLL7_BYPASS_SRC		10
-#define IMX6UL_CLK_PLL1 		11
-#define IMX6UL_CLK_PLL2 		12
-#define IMX6UL_CLK_PLL3 		13
-#define IMX6UL_CLK_PLL4 		14
-#define IMX6UL_CLK_PLL5 		15
-#define IMX6UL_CLK_PLL6 		16
-#define IMX6UL_CLK_PLL7 		17
+#define IMX6UL_CLK_PLL1			11
+#define IMX6UL_CLK_PLL2			12
+#define IMX6UL_CLK_PLL3			13
+#define IMX6UL_CLK_PLL4			14
+#define IMX6UL_CLK_PLL5			15
+#define IMX6UL_CLK_PLL6			16
+#define IMX6UL_CLK_PLL7			17
 #define IMX6UL_PLL1_BYPASS		18
 #define IMX6UL_PLL2_BYPASS		19
 #define IMX6UL_PLL3_BYPASS		20
@@ -37,7 +37,7 @@
 #define IMX6UL_PLL7_BYPASS		24
 #define IMX6UL_CLK_PLL1_SYS		25
 #define IMX6UL_CLK_PLL2_BUS		26
-#define IMX6UL_CLK_PLL3_USB_OTG 	27
+#define IMX6UL_CLK_PLL3_USB_OTG		27
 #define IMX6UL_CLK_PLL4_AUDIO		28
 #define IMX6UL_CLK_PLL5_VIDEO		29
 #define IMX6UL_CLK_PLL6_ENET		30
@@ -66,7 +66,7 @@
 #define IMX6UL_CLK_PLL2_198M		53
 #define IMX6UL_CLK_PLL3_80M		54
 #define IMX6UL_CLK_PLL3_60M		55
-#define IMX6UL_CLK_STEP 		56
+#define IMX6UL_CLK_STEP			56
 #define IMX6UL_CLK_PLL1_SW		57
 #define IMX6UL_CLK_AXI_ALT_SEL		58
 #define IMX6UL_CLK_AXI_SEL		59
@@ -78,7 +78,7 @@
 #define IMX6UL_CLK_USDHC2_SEL		65
 #define IMX6UL_CLK_BCH_SEL		66
 #define IMX6UL_CLK_GPMI_SEL		67
-#define IMX6UL_CLK_EIM_SLOW_SEL 	68
+#define IMX6UL_CLK_EIM_SLOW_SEL		68
 #define IMX6UL_CLK_SPDIF_SEL		69
 #define IMX6UL_CLK_SAI1_SEL		70
 #define IMX6UL_CLK_SAI2_SEL		71
@@ -105,9 +105,9 @@
 #define IMX6UL_CLK_LDB_DI1_DIV_SEL	92
 #define IMX6UL_CLK_ARM			93
 #define IMX6UL_CLK_PERIPH_CLK2		94
-#define IMX6UL_CLK_PERIPH2_CLK2 	95
+#define IMX6UL_CLK_PERIPH2_CLK2		95
 #define IMX6UL_CLK_AHB			96
-#define IMX6UL_CLK_MMDC_PODF 		97
+#define IMX6UL_CLK_MMDC_PODF		97
 #define IMX6UL_CLK_AXI_PODF		98
 #define IMX6UL_CLK_PERCLK		99
 #define IMX6UL_CLK_IPG			100
@@ -133,16 +133,16 @@
 #define IMX6UL_CLK_CAN_PODF		120
 #define IMX6UL_CLK_ECSPI_PODF		121
 #define IMX6UL_CLK_UART_PODF		122
-#define IMX6UL_CLK_ADC1 		123
-#define IMX6UL_CLK_ADC2 		124
+#define IMX6UL_CLK_ADC1			123
+#define IMX6UL_CLK_ADC2			124
 #define IMX6UL_CLK_AIPSTZ1		125
 #define IMX6UL_CLK_AIPSTZ2		126
 #define IMX6UL_CLK_AIPSTZ3		127
 #define IMX6UL_CLK_APBHDMA		128
 #define IMX6UL_CLK_ASRC_IPG		129
 #define IMX6UL_CLK_ASRC_MEM		130
-#define IMX6UL_CLK_GPMI_BCH_APB  	131
-#define IMX6UL_CLK_GPMI_BCH 		132
+#define IMX6UL_CLK_GPMI_BCH_APB		131
+#define IMX6UL_CLK_GPMI_BCH		132
 #define IMX6UL_CLK_GPMI_IO		133
 #define IMX6UL_CLK_GPMI_APB		134
 #define IMX6UL_CLK_CAAM_MEM		135
@@ -154,7 +154,7 @@
 #define IMX6UL_CLK_ECSPI3		141
 #define IMX6UL_CLK_ECSPI4		142
 #define IMX6UL_CLK_EIM			143
-#define IMX6UL_CLK_ENET  		144
+#define IMX6UL_CLK_ENET			144
 #define IMX6UL_CLK_ENET_AHB		145
 #define IMX6UL_CLK_EPIT1		146
 #define IMX6UL_CLK_EPIT2		147
@@ -166,63 +166,63 @@
 #define IMX6UL_CLK_GPT1_SERIAL		153
 #define IMX6UL_CLK_GPT2_BUS		154
 #define IMX6UL_CLK_GPT2_SERIAL		155
-#define IMX6UL_CLK_I2C1 		156
-#define IMX6UL_CLK_I2C2 		157
-#define IMX6UL_CLK_I2C3 		158
-#define IMX6UL_CLK_I2C4 		159
-#define IMX6UL_CLK_IOMUXC 		160
-#define IMX6UL_CLK_LCDIF_APB 		161
-#define IMX6UL_CLK_LCDIF_PIX 		162
-#define IMX6UL_CLK_MMDC_P0_FAST 	163
-#define IMX6UL_CLK_MMDC_P0_IPG  	164
-#define IMX6UL_CLK_OCOTP 		165
-#define IMX6UL_CLK_OCRAM 		166
-#define IMX6UL_CLK_PWM1 		167
-#define IMX6UL_CLK_PWM2 		168
-#define IMX6UL_CLK_PWM3 		169
-#define IMX6UL_CLK_PWM4 		170
-#define IMX6UL_CLK_PWM5 		171
-#define IMX6UL_CLK_PWM6 		172
-#define IMX6UL_CLK_PWM7 		173
-#define IMX6UL_CLK_PWM8 		174
-#define IMX6UL_CLK_PXP  		175
-#define IMX6UL_CLK_QSPI 		176
-#define IMX6UL_CLK_ROM  		177
-#define IMX6UL_CLK_SAI1 		178
-#define IMX6UL_CLK_SAI1_IPG 		179
-#define IMX6UL_CLK_SAI2 		180
-#define IMX6UL_CLK_SAI2_IPG 		181
-#define IMX6UL_CLK_SAI3 		182
-#define IMX6UL_CLK_SAI3_IPG 		183
-#define IMX6UL_CLK_SDMA 		184
-#define IMX6UL_CLK_SIM  		185
-#define IMX6UL_CLK_SIM_S 		186
-#define IMX6UL_CLK_SPBA 		187
-#define IMX6UL_CLK_SPDIF 		188
-#define IMX6UL_CLK_UART1_IPG 		189
-#define IMX6UL_CLK_UART1_SERIAL 	190
-#define IMX6UL_CLK_UART2_IPG 		191
-#define IMX6UL_CLK_UART2_SERIAL 	192
-#define IMX6UL_CLK_UART3_IPG 		193
-#define IMX6UL_CLK_UART3_SERIAL 	194
-#define IMX6UL_CLK_UART4_IPG 		195
-#define IMX6UL_CLK_UART4_SERIAL 	196
-#define IMX6UL_CLK_UART5_IPG 		197
-#define IMX6UL_CLK_UART5_SERIAL 	198
-#define IMX6UL_CLK_UART6_IPG 		199
-#define IMX6UL_CLK_UART6_SERIAL 	200
-#define IMX6UL_CLK_UART7_IPG 		201
-#define IMX6UL_CLK_UART7_SERIAL 	202
-#define IMX6UL_CLK_UART8_IPG 		203
-#define IMX6UL_CLK_UART8_SERIAL 	204
-#define IMX6UL_CLK_USBOH3 		205
-#define IMX6UL_CLK_USDHC1 		206
-#define IMX6UL_CLK_USDHC2 		207
-#define IMX6UL_CLK_WDOG1 		208
-#define IMX6UL_CLK_WDOG2 		209
-#define IMX6UL_CLK_WDOG3 		210
+#define IMX6UL_CLK_I2C1			156
+#define IMX6UL_CLK_I2C2			157
+#define IMX6UL_CLK_I2C3			158
+#define IMX6UL_CLK_I2C4			159
+#define IMX6UL_CLK_IOMUXC		160
+#define IMX6UL_CLK_LCDIF_APB		161
+#define IMX6UL_CLK_LCDIF_PIX		162
+#define IMX6UL_CLK_MMDC_P0_FAST		163
+#define IMX6UL_CLK_MMDC_P0_IPG		164
+#define IMX6UL_CLK_OCOTP		165
+#define IMX6UL_CLK_OCRAM		166
+#define IMX6UL_CLK_PWM1			167
+#define IMX6UL_CLK_PWM2			168
+#define IMX6UL_CLK_PWM3			169
+#define IMX6UL_CLK_PWM4			170
+#define IMX6UL_CLK_PWM5			171
+#define IMX6UL_CLK_PWM6			172
+#define IMX6UL_CLK_PWM7			173
+#define IMX6UL_CLK_PWM8			174
+#define IMX6UL_CLK_PXP			175
+#define IMX6UL_CLK_QSPI			176
+#define IMX6UL_CLK_ROM			177
+#define IMX6UL_CLK_SAI1			178
+#define IMX6UL_CLK_SAI1_IPG		179
+#define IMX6UL_CLK_SAI2			180
+#define IMX6UL_CLK_SAI2_IPG		181
+#define IMX6UL_CLK_SAI3			182
+#define IMX6UL_CLK_SAI3_IPG		183
+#define IMX6UL_CLK_SDMA			184
+#define IMX6UL_CLK_SIM			185
+#define IMX6UL_CLK_SIM_S		186
+#define IMX6UL_CLK_SPBA			187
+#define IMX6UL_CLK_SPDIF		188
+#define IMX6UL_CLK_UART1_IPG		189
+#define IMX6UL_CLK_UART1_SERIAL		190
+#define IMX6UL_CLK_UART2_IPG		191
+#define IMX6UL_CLK_UART2_SERIAL		192
+#define IMX6UL_CLK_UART3_IPG		193
+#define IMX6UL_CLK_UART3_SERIAL		194
+#define IMX6UL_CLK_UART4_IPG		195
+#define IMX6UL_CLK_UART4_SERIAL		196
+#define IMX6UL_CLK_UART5_IPG		197
+#define IMX6UL_CLK_UART5_SERIAL		198
+#define IMX6UL_CLK_UART6_IPG		199
+#define IMX6UL_CLK_UART6_SERIAL		200
+#define IMX6UL_CLK_UART7_IPG		201
+#define IMX6UL_CLK_UART7_SERIAL		202
+#define IMX6UL_CLK_UART8_IPG		203
+#define IMX6UL_CLK_UART8_SERIAL		204
+#define IMX6UL_CLK_USBOH3		205
+#define IMX6UL_CLK_USDHC1		206
+#define IMX6UL_CLK_USDHC2		207
+#define IMX6UL_CLK_WDOG1		208
+#define IMX6UL_CLK_WDOG2		209
+#define IMX6UL_CLK_WDOG3		210
 #define IMX6UL_CLK_LDB_DI0		211
-#define IMX6UL_CLK_AXI  		212
+#define IMX6UL_CLK_AXI			212
 #define IMX6UL_CLK_SPDIF_GCLK		213
 #define IMX6UL_CLK_GPT_3M		214
 #define IMX6UL_CLK_SIM2			215
@@ -234,7 +234,8 @@
 #define IMX6UL_CLK_CSI_SEL		221
 #define IMX6UL_CLK_CSI_PODF		222
 #define IMX6UL_CLK_PLL3_120M		223
+#define IMX6UL_CLK_KPP			224
 
-#define IMX6UL_CLK_END			224
+#define IMX6UL_CLK_END			225
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h b/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h
index edca8985c50e..1183347c383f 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/imx7d-clock.h
@@ -448,5 +448,6 @@
 #define IMX7D_PLL_DRAM_TEST_DIV		435
 #define IMX7D_ADC_ROOT_CLK		436
 #define IMX7D_CLK_ARM			437
-#define IMX7D_CLK_END			438
+#define IMX7D_CKIL			438
+#define IMX7D_CLK_END			439
 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/sys/gnu/dts/include/dt-bindings/clock/lpc32xx-clock.h b/sys/gnu/dts/include/dt-bindings/clock/lpc32xx-clock.h
index bcb1c9a73519..d41b6fea1450 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/lpc32xx-clock.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/lpc32xx-clock.h
@@ -47,6 +47,7 @@
 #define LPC32XX_CLK_PWM1	32
 #define LPC32XX_CLK_PWM2	33
 #define LPC32XX_CLK_ADC		34
+#define LPC32XX_CLK_HCLK_PLL	35
 
 /* LPC32XX USB clocks */
 #define LPC32XX_USB_CLK_I2C	1
diff --git a/sys/gnu/dts/include/dt-bindings/clock/microchip,pic32-clock.h b/sys/gnu/dts/include/dt-bindings/clock/microchip,pic32-clock.h
new file mode 100644
index 000000000000..184647a6a8de
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/clock/microchip,pic32-clock.h
@@ -0,0 +1,42 @@
+/*
+ * Purna Chandra Mandal,<purna.mandal@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+
+/* clock output indices */
+#define POSCCLK		0
+#define FRCCLK		1
+#define BFRCCLK		2
+#define LPRCCLK		3
+#define SOSCCLK		4
+#define FRCDIVCLK	5
+#define PLLCLK		6
+#define SCLK		7
+#define PB1CLK		8
+#define PB2CLK		9
+#define PB3CLK		10
+#define PB4CLK		11
+#define PB5CLK		12
+#define PB6CLK		13
+#define PB7CLK		14
+#define REF1CLK		15
+#define REF2CLK		16
+#define REF3CLK		17
+#define REF4CLK		18
+#define REF5CLK		19
+#define UPLLCLK		20
+#define MAXCLKS		21
+
+#endif	/* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */
diff --git a/sys/gnu/dts/include/dt-bindings/clock/mt8173-clk.h b/sys/gnu/dts/include/dt-bindings/clock/mt8173-clk.h
index 7956ba1bc974..6094bf7e50ab 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/mt8173-clk.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/mt8173-clk.h
@@ -176,7 +176,8 @@
 #define CLK_APMIXED_LVDSPLL		13
 #define CLK_APMIXED_MSDCPLL2		14
 #define CLK_APMIXED_REF2USB_TX		15
-#define CLK_APMIXED_NR_CLK		16
+#define CLK_APMIXED_HDMI_REF		16
+#define CLK_APMIXED_NR_CLK		17
 
 /* INFRA_SYS */
 
diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq4019.h
new file mode 100644
index 000000000000..6240e5b0e900
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -0,0 +1,158 @@
+/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#ifndef __QCOM_CLK_IPQ4019_H__
+#define __QCOM_CLK_IPQ4019_H__
+
+#define GCC_DUMMY_CLK					0
+#define AUDIO_CLK_SRC					1
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			2
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			3
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			4
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			5
+#define BLSP1_UART1_APPS_CLK_SRC			6
+#define BLSP1_UART2_APPS_CLK_SRC			7
+#define GCC_USB3_MOCK_UTMI_CLK_SRC			8
+#define GCC_APPS_CLK_SRC				9
+#define GCC_APPS_AHB_CLK_SRC				10
+#define GP1_CLK_SRC					11
+#define GP2_CLK_SRC					12
+#define GP3_CLK_SRC					13
+#define SDCC1_APPS_CLK_SRC				14
+#define FEPHY_125M_DLY_CLK_SRC				15
+#define WCSS2G_CLK_SRC					16
+#define WCSS5G_CLK_SRC					17
+#define GCC_APSS_AHB_CLK				18
+#define GCC_AUDIO_AHB_CLK				19
+#define GCC_AUDIO_PWM_CLK				20
+#define GCC_BLSP1_AHB_CLK				21
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			22
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			23
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			24
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			25
+#define GCC_BLSP1_UART1_APPS_CLK			26
+#define GCC_BLSP1_UART2_APPS_CLK			27
+#define GCC_DCD_XO_CLK					28
+#define GCC_GP1_CLK					29
+#define GCC_GP2_CLK					30
+#define GCC_GP3_CLK					31
+#define GCC_BOOT_ROM_AHB_CLK				32
+#define GCC_CRYPTO_AHB_CLK				33
+#define GCC_CRYPTO_AXI_CLK				34
+#define GCC_CRYPTO_CLK					35
+#define GCC_ESS_CLK					36
+#define GCC_IMEM_AXI_CLK				37
+#define GCC_IMEM_CFG_AHB_CLK				38
+#define GCC_PCIE_AHB_CLK				39
+#define GCC_PCIE_AXI_M_CLK				40
+#define GCC_PCIE_AXI_S_CLK				41
+#define GCC_PCNOC_AHB_CLK				42
+#define GCC_PRNG_AHB_CLK				43
+#define GCC_QPIC_AHB_CLK				44
+#define GCC_QPIC_CLK					45
+#define GCC_SDCC1_AHB_CLK				46
+#define GCC_SDCC1_APPS_CLK				47
+#define GCC_SNOC_PCNOC_AHB_CLK				48
+#define GCC_SYS_NOC_125M_CLK				49
+#define GCC_SYS_NOC_AXI_CLK				50
+#define GCC_TCSR_AHB_CLK				51
+#define GCC_TLMM_AHB_CLK				52
+#define GCC_USB2_MASTER_CLK				53
+#define GCC_USB2_SLEEP_CLK				54
+#define GCC_USB2_MOCK_UTMI_CLK				55
+#define GCC_USB3_MASTER_CLK				56
+#define GCC_USB3_SLEEP_CLK				57
+#define GCC_USB3_MOCK_UTMI_CLK				58
+#define GCC_WCSS2G_CLK					59
+#define GCC_WCSS2G_REF_CLK				60
+#define GCC_WCSS2G_RTC_CLK				61
+#define GCC_WCSS5G_CLK					62
+#define GCC_WCSS5G_REF_CLK				63
+#define GCC_WCSS5G_RTC_CLK				64
+
+#define WIFI0_CPU_INIT_RESET				0
+#define WIFI0_RADIO_SRIF_RESET				1
+#define WIFI0_RADIO_WARM_RESET				2
+#define WIFI0_RADIO_COLD_RESET				3
+#define WIFI0_CORE_WARM_RESET				4
+#define WIFI0_CORE_COLD_RESET				5
+#define WIFI1_CPU_INIT_RESET				6
+#define WIFI1_RADIO_SRIF_RESET				7
+#define WIFI1_RADIO_WARM_RESET				8
+#define WIFI1_RADIO_COLD_RESET				9
+#define WIFI1_CORE_WARM_RESET				10
+#define WIFI1_CORE_COLD_RESET				11
+#define USB3_UNIPHY_PHY_ARES				12
+#define USB3_HSPHY_POR_ARES				13
+#define USB3_HSPHY_S_ARES				14
+#define USB2_HSPHY_POR_ARES				15
+#define USB2_HSPHY_S_ARES				16
+#define PCIE_PHY_AHB_ARES				17
+#define PCIE_AHB_ARES					18
+#define PCIE_PWR_ARES					19
+#define PCIE_PIPE_STICKY_ARES				20
+#define PCIE_AXI_M_STICKY_ARES				21
+#define PCIE_PHY_ARES					22
+#define PCIE_PARF_XPU_ARES				23
+#define PCIE_AXI_S_XPU_ARES				24
+#define PCIE_AXI_M_VMIDMT_ARES				25
+#define PCIE_PIPE_ARES					26
+#define PCIE_AXI_S_ARES					27
+#define PCIE_AXI_M_ARES					28
+#define ESS_RESET					29
+#define GCC_BLSP1_BCR					30
+#define GCC_BLSP1_QUP1_BCR				31
+#define GCC_BLSP1_UART1_BCR				32
+#define GCC_BLSP1_QUP2_BCR				33
+#define GCC_BLSP1_UART2_BCR				34
+#define GCC_BIMC_BCR					35
+#define GCC_TLMM_BCR					36
+#define GCC_IMEM_BCR					37
+#define GCC_ESS_BCR					38
+#define GCC_PRNG_BCR					39
+#define GCC_BOOT_ROM_BCR				40
+#define GCC_CRYPTO_BCR					41
+#define GCC_SDCC1_BCR					42
+#define GCC_SEC_CTRL_BCR				43
+#define GCC_AUDIO_BCR					44
+#define GCC_QPIC_BCR					45
+#define GCC_PCIE_BCR					46
+#define GCC_USB2_BCR					47
+#define GCC_USB2_PHY_BCR				48
+#define GCC_USB3_BCR					49
+#define GCC_USB3_PHY_BCR				50
+#define GCC_SYSTEM_NOC_BCR				51
+#define GCC_PCNOC_BCR					52
+#define GCC_DCD_BCR					53
+#define GCC_SNOC_BUS_TIMEOUT0_BCR			54
+#define GCC_SNOC_BUS_TIMEOUT1_BCR			55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR			56
+#define GCC_SNOC_BUS_TIMEOUT3_BCR			57
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR			58
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR			59
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR			60
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR			61
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR			62
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR			63
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR			64
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR			65
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR			66
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR			67
+#define GCC_TCSR_BCR					68
+#define GCC_QDSS_BCR					69
+#define GCC_MPM_BCR					70
+#define GCC_SPDM_BCR					71
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8916.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8916.h
index 257e2fbedd94..28a27a4ed3c3 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -174,6 +174,7 @@
 #define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK		157
 #define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK		158
 #define GCC_CODEC_DIGCODEC_CLK			159
+#define GCC_MSS_Q6_BIMC_AXI_CLK			160
 
 /* Indexes for GDSCs */
 #define BIMC_GDSC				0
diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 888e75ce8fec..6f814db11c7e 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -336,4 +336,15 @@
 #define GCC_MSS_Q6_BCR						99
 #define GCC_QREFS_VBG_CAL_BCR					100
 
+/* Indexes for GDSCs */
+#define AGGRE0_NOC_GDSC			0
+#define HLOS1_VOTE_AGGRE0_NOC_GDSC	1
+#define HLOS1_VOTE_LPASS_ADSP_GDSC	2
+#define HLOS1_VOTE_LPASS_CORE_GDSC	3
+#define USB30_GDSC			4
+#define PCIE0_GDSC			5
+#define PCIE1_GDSC			6
+#define PCIE2_GDSC			7
+#define UFS_GDSC			8
+
 #endif
diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8996.h
index 9b81ca65fcec..7d3a7fa1a1bd 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8996.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8996.h
@@ -282,4 +282,21 @@
 #define FD_BCR						58
 #define MMSS_SPDM_RM_BCR				59
 
+/* Indexes for GDSCs */
+#define MMAGIC_VIDEO_GDSC	0
+#define MMAGIC_MDSS_GDSC	1
+#define MMAGIC_CAMSS_GDSC	2
+#define GPU_GDSC		3
+#define VENUS_GDSC		4
+#define VENUS_CORE0_GDSC	5
+#define VENUS_CORE1_GDSC	6
+#define CAMSS_GDSC		7
+#define VFE0_GDSC		8
+#define VFE1_GDSC		9
+#define JPEG_GDSC		10
+#define CPP_GDSC		11
+#define FD_GDSC			12
+#define MDSS_GDSC		13
+#define GPU_GX_GDSC		14
+
 #endif
diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h
index 7b1ad8922eec..fa5e8da809f2 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/r8a7790-clock.h
@@ -66,6 +66,7 @@
 #define R8A7790_CLK_IIC2		0
 #define R8A7790_CLK_TPU0		4
 #define R8A7790_CLK_MMCIF1		5
+#define R8A7790_CLK_SCIF2		10
 #define R8A7790_CLK_SDHI3		11
 #define R8A7790_CLK_SDHI2		12
 #define R8A7790_CLK_SDHI1		13
diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7793-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7793-clock.h
index 1579e07f96a3..efcbc594fe82 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/r8a7793-clock.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/r8a7793-clock.h
@@ -145,6 +145,8 @@
 #define R8A7793_CLK_SCU_ALL		17
 #define R8A7793_CLK_SCU_DVC1		18
 #define R8A7793_CLK_SCU_DVC0		19
+#define R8A7793_CLK_SCU_CTU1_MIX1	20
+#define R8A7793_CLK_SCU_CTU0_MIX0	21
 #define R8A7793_CLK_SCU_SRC9		22
 #define R8A7793_CLK_SCU_SRC8		23
 #define R8A7793_CLK_SCU_SRC7		24
diff --git a/sys/gnu/dts/include/dt-bindings/clock/r8a7794-clock.h b/sys/gnu/dts/include/dt-bindings/clock/r8a7794-clock.h
index a7a7e0370968..4d3ecd626c1f 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/r8a7794-clock.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/r8a7794-clock.h
@@ -21,6 +21,7 @@
 #define R8A7794_CLK_SDH			6
 #define R8A7794_CLK_SD0			7
 #define R8A7794_CLK_Z			8
+#define R8A7794_CLK_RCAN		9
 
 /* MSTP0 */
 #define R8A7794_CLK_MSIOF0		0
@@ -56,6 +57,8 @@
 #define R8A7794_CLK_SDHI1		12
 #define R8A7794_CLK_SDHI0		14
 #define R8A7794_CLK_MMCIF0		15
+#define R8A7794_CLK_IIC0		18
+#define R8A7794_CLK_IIC1		23
 #define R8A7794_CLK_CMT1		29
 #define R8A7794_CLK_USBDMAC0		30
 #define R8A7794_CLK_USBDMAC1		31
@@ -84,6 +87,7 @@
 /* MSTP8 */
 #define R8A7794_CLK_VIN1		10
 #define R8A7794_CLK_VIN0		11
+#define R8A7794_CLK_ETHERAVB		12
 #define R8A7794_CLK_ETHER		13
 
 /* MSTP9 */
@@ -94,6 +98,8 @@
 #define R8A7794_CLK_GPIO2		10
 #define R8A7794_CLK_GPIO1		11
 #define R8A7794_CLK_GPIO0		12
+#define R8A7794_CLK_RCAN1		15
+#define R8A7794_CLK_RCAN0		16
 #define R8A7794_CLK_QSPI_MOD		17
 #define R8A7794_CLK_I2C5		25
 #define R8A7794_CLK_I2C4		27
diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3036-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3036-cru.h
index ebc7a7b43f52..de44109a3a04 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/rk3036-cru.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/rk3036-cru.h
@@ -54,6 +54,7 @@
 #define SCLK_PVTM_VIDEO		125
 #define SCLK_MAC		151
 #define SCLK_MACREF		152
+#define SCLK_MACPLL		153
 #define SCLK_SFC		160
 
 /* aclk gates */
@@ -92,6 +93,7 @@
 #define HCLK_SDMMC		456
 #define HCLK_SDIO		457
 #define HCLK_EMMC		459
+#define HCLK_MAC		460
 #define HCLK_I2S		462
 #define HCLK_LCDC		465
 #define HCLK_ROM		467
diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h b/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h
index 8df77a7c030b..4f53e70f68ee 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/rk3188-cru-common.h
@@ -55,6 +55,7 @@
 #define SCLK_TIMER6		90
 #define SCLK_JTAG		91
 #define SCLK_SMC		92
+#define SCLK_TSADC		93
 
 #define DCLK_LCDC0		190
 #define DCLK_LCDC1		191
diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3228-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3228-cru.h
index a78dd891e24a..5d43ed9b05ad 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/rk3228-cru.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/rk3228-cru.h
@@ -29,6 +29,7 @@
 #define SCLK_SDMMC		68
 #define SCLK_SDIO		69
 #define SCLK_EMMC		71
+#define SCLK_TSADC		72
 #define SCLK_UART0		77
 #define SCLK_UART1		78
 #define SCLK_UART2		79
@@ -49,10 +50,17 @@
 #define SCLK_SDMMC_SAMPLE	118
 #define SCLK_SDIO_SAMPLE	119
 #define SCLK_EMMC_SAMPLE	121
+#define SCLK_VOP		122
+#define SCLK_HDMI_HDCP		123
+
+/* dclk gates */
+#define DCLK_VOP		190
+#define DCLK_HDMI_PHY		191
 
 /* aclk gates */
 #define ACLK_DMAC		194
 #define ACLK_PERI		210
+#define ACLK_VOP		211
 
 /* pclk gates */
 #define PCLK_GPIO0		320
@@ -68,11 +76,15 @@
 #define PCLK_UART0		341
 #define PCLK_UART1		342
 #define PCLK_UART2		343
+#define PCLK_TSADC		344
 #define PCLK_PWM		350
 #define PCLK_TIMER		353
 #define PCLK_PERI		363
+#define PCLK_HDMI_CTRL		364
+#define PCLK_HDMI_PHY		365
 
 /* hclk gates */
+#define HCLK_VOP		452
 #define HCLK_NANDC		453
 #define HCLK_SDMMC		456
 #define HCLK_SDIO		457
diff --git a/sys/gnu/dts/include/dt-bindings/clock/rk3399-cru.h b/sys/gnu/dts/include/dt-bindings/clock/rk3399-cru.h
new file mode 100644
index 000000000000..50a44cffb070
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/clock/rk3399-cru.h
@@ -0,0 +1,755 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng <zhengxing@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+
+/* core clocks */
+#define PLL_APLLL			1
+#define PLL_APLLB			2
+#define PLL_DPLL			3
+#define PLL_CPLL			4
+#define PLL_GPLL			5
+#define PLL_NPLL			6
+#define PLL_VPLL			7
+#define ARMCLKL				8
+#define ARMCLKB				9
+
+/* sclk gates (special clocks) */
+#define SCLK_I2C1			65
+#define SCLK_I2C2			66
+#define SCLK_I2C3			67
+#define SCLK_I2C5			68
+#define SCLK_I2C6			69
+#define SCLK_I2C7			70
+#define SCLK_SPI0			71
+#define SCLK_SPI1			72
+#define SCLK_SPI2			73
+#define SCLK_SPI4			74
+#define SCLK_SPI5			75
+#define SCLK_SDMMC			76
+#define SCLK_SDIO			77
+#define SCLK_EMMC			78
+#define SCLK_TSADC			79
+#define SCLK_SARADC			80
+#define SCLK_UART0			81
+#define SCLK_UART1			82
+#define SCLK_UART2			83
+#define SCLK_UART3			84
+#define SCLK_SPDIF_8CH			85
+#define SCLK_I2S0_8CH			86
+#define SCLK_I2S1_8CH			87
+#define SCLK_I2S2_8CH			88
+#define SCLK_I2S_8CH_OUT		89
+#define SCLK_TIMER00			90
+#define SCLK_TIMER01			91
+#define SCLK_TIMER02			92
+#define SCLK_TIMER03			93
+#define SCLK_TIMER04			94
+#define SCLK_TIMER05			95
+#define SCLK_TIMER06			96
+#define SCLK_TIMER07			97
+#define SCLK_TIMER08			98
+#define SCLK_TIMER09			99
+#define SCLK_TIMER10			100
+#define SCLK_TIMER11			101
+#define SCLK_MACREF			102
+#define SCLK_MAC_RX			103
+#define SCLK_MAC_TX			104
+#define SCLK_MAC			105
+#define SCLK_MACREF_OUT			106
+#define SCLK_VOP0_PWM			107
+#define SCLK_VOP1_PWM			108
+#define SCLK_RGA_CORE			109
+#define SCLK_ISP0			110
+#define SCLK_ISP1			111
+#define SCLK_HDMI_CEC			112
+#define SCLK_HDMI_SFR			113
+#define SCLK_DP_CORE			114
+#define SCLK_PVTM_CORE_L		115
+#define SCLK_PVTM_CORE_B		116
+#define SCLK_PVTM_GPU			117
+#define SCLK_PVTM_DDR			118
+#define SCLK_MIPIDPHY_REF		119
+#define SCLK_MIPIDPHY_CFG		120
+#define SCLK_HSICPHY			121
+#define SCLK_USBPHY480M			122
+#define SCLK_USB2PHY0_REF		123
+#define SCLK_USB2PHY1_REF		124
+#define SCLK_UPHY0_TCPDPHY_REF		125
+#define SCLK_UPHY0_TCPDCORE		126
+#define SCLK_UPHY1_TCPDPHY_REF		127
+#define SCLK_UPHY1_TCPDCORE		128
+#define SCLK_USB3OTG0_REF		129
+#define SCLK_USB3OTG1_REF		130
+#define SCLK_USB3OTG0_SUSPEND		131
+#define SCLK_USB3OTG1_SUSPEND		132
+#define SCLK_CRYPTO0			133
+#define SCLK_CRYPTO1			134
+#define SCLK_CCI_TRACE			135
+#define SCLK_CS				136
+#define SCLK_CIF_OUT			137
+#define SCLK_PCIEPHY_REF		138
+#define SCLK_PCIE_CORE			139
+#define SCLK_M0_PERILP			140
+#define SCLK_M0_PERILP_DEC		141
+#define SCLK_CM0S			142
+#define SCLK_DBG_NOC			143
+#define SCLK_DBG_PD_CORE_B		144
+#define SCLK_DBG_PD_CORE_L		145
+#define SCLK_DFIMON0_TIMER		146
+#define SCLK_DFIMON1_TIMER		147
+#define SCLK_INTMEM0			148
+#define SCLK_INTMEM1			149
+#define SCLK_INTMEM2			150
+#define SCLK_INTMEM3			151
+#define SCLK_INTMEM4			152
+#define SCLK_INTMEM5			153
+#define SCLK_SDMMC_DRV			154
+#define SCLK_SDMMC_SAMPLE		155
+#define SCLK_SDIO_DRV			156
+#define SCLK_SDIO_SAMPLE		157
+#define SCLK_VDU_CORE			158
+#define SCLK_VDU_CA			159
+#define SCLK_PCIE_PM			160
+#define SCLK_SPDIF_REC_DPTX		161
+#define SCLK_DPHY_PLL			162
+#define SCLK_DPHY_TX0_CFG		163
+#define SCLK_DPHY_TX1RX1_CFG		164
+#define SCLK_DPHY_RX0_CFG		165
+#define SCLK_RMII_SRC			166
+#define SCLK_PCIEPHY_REF100M		167
+
+#define DCLK_VOP0			180
+#define DCLK_VOP1			181
+#define DCLK_VOP0_DIV			182
+#define DCLK_VOP1_DIV			183
+#define DCLK_M0_PERILP			184
+
+#define FCLK_CM0S			190
+
+/* aclk gates */
+#define ACLK_PERIHP			192
+#define ACLK_PERIHP_NOC			193
+#define ACLK_PERILP0			194
+#define ACLK_PERILP0_NOC		195
+#define ACLK_PERF_PCIE			196
+#define ACLK_PCIE			197
+#define ACLK_INTMEM			198
+#define ACLK_TZMA			199
+#define ACLK_DCF			200
+#define ACLK_CCI			201
+#define ACLK_CCI_NOC0			202
+#define ACLK_CCI_NOC1			203
+#define ACLK_CCI_GRF			204
+#define ACLK_CENTER			205
+#define ACLK_CENTER_MAIN_NOC		206
+#define ACLK_CENTER_PERI_NOC		207
+#define ACLK_GPU			208
+#define ACLK_PERF_GPU			209
+#define ACLK_GPU_GRF			210
+#define ACLK_DMAC0_PERILP		211
+#define ACLK_DMAC1_PERILP		212
+#define ACLK_GMAC			213
+#define ACLK_GMAC_NOC			214
+#define ACLK_PERF_GMAC			215
+#define ACLK_VOP0_NOC			216
+#define ACLK_VOP0			217
+#define ACLK_VOP1_NOC			218
+#define ACLK_VOP1			219
+#define ACLK_RGA			220
+#define ACLK_RGA_NOC			221
+#define ACLK_HDCP			222
+#define ACLK_HDCP_NOC			223
+#define ACLK_HDCP22			224
+#define ACLK_IEP			225
+#define ACLK_IEP_NOC			226
+#define ACLK_VIO			227
+#define ACLK_VIO_NOC			228
+#define ACLK_ISP0			229
+#define ACLK_ISP1			230
+#define ACLK_ISP0_NOC			231
+#define ACLK_ISP1_NOC			232
+#define ACLK_ISP0_WRAPPER		233
+#define ACLK_ISP1_WRAPPER		234
+#define ACLK_VCODEC			235
+#define ACLK_VCODEC_NOC			236
+#define ACLK_VDU			237
+#define ACLK_VDU_NOC			238
+#define ACLK_PERI			239
+#define ACLK_EMMC			240
+#define ACLK_EMMC_CORE			241
+#define ACLK_EMMC_NOC			242
+#define ACLK_EMMC_GRF			243
+#define ACLK_USB3			244
+#define ACLK_USB3_NOC			245
+#define ACLK_USB3OTG0			246
+#define ACLK_USB3OTG1			247
+#define ACLK_USB3_RKSOC_AXI_PERF	248
+#define ACLK_USB3_GRF			249
+#define ACLK_GIC			250
+#define ACLK_GIC_NOC			251
+#define ACLK_GIC_ADB400_CORE_L_2_GIC	252
+#define ACLK_GIC_ADB400_CORE_B_2_GIC	253
+#define ACLK_GIC_ADB400_GIC_2_CORE_L	254
+#define ACLK_GIC_ADB400_GIC_2_CORE_B	255
+#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
+#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
+#define ACLK_ADB400M_PD_CORE_L		258
+#define ACLK_ADB400M_PD_CORE_B		259
+#define ACLK_PERF_CORE_L		260
+#define ACLK_PERF_CORE_B		261
+#define ACLK_GIC_PRE			262
+#define ACLK_VOP0_PRE			263
+#define ACLK_VOP1_PRE			264
+
+/* pclk gates */
+#define PCLK_PERIHP			320
+#define PCLK_PERIHP_NOC			321
+#define PCLK_PERILP0			322
+#define PCLK_PERILP1			323
+#define PCLK_PERILP1_NOC		324
+#define PCLK_PERILP_SGRF		325
+#define PCLK_PERIHP_GRF			326
+#define PCLK_PCIE			327
+#define PCLK_SGRF			328
+#define PCLK_INTR_ARB			329
+#define PCLK_CENTER_MAIN_NOC		330
+#define PCLK_CIC			331
+#define PCLK_COREDBG_B			332
+#define PCLK_COREDBG_L			333
+#define PCLK_DBG_CXCS_PD_CORE_B		334
+#define PCLK_DCF			335
+#define PCLK_GPIO2			336
+#define PCLK_GPIO3			337
+#define PCLK_GPIO4			338
+#define PCLK_GRF			339
+#define PCLK_HSICPHY			340
+#define PCLK_I2C1			341
+#define PCLK_I2C2			342
+#define PCLK_I2C3			343
+#define PCLK_I2C5			344
+#define PCLK_I2C6			345
+#define PCLK_I2C7			346
+#define PCLK_SPI0			347
+#define PCLK_SPI1			348
+#define PCLK_SPI2			349
+#define PCLK_SPI4			350
+#define PCLK_SPI5			351
+#define PCLK_UART0			352
+#define PCLK_UART1			353
+#define PCLK_UART2			354
+#define PCLK_UART3			355
+#define PCLK_TSADC			356
+#define PCLK_SARADC			357
+#define PCLK_GMAC			358
+#define PCLK_GMAC_NOC			359
+#define PCLK_TIMER0			360
+#define PCLK_TIMER1			361
+#define PCLK_EDP			362
+#define PCLK_EDP_NOC			363
+#define PCLK_EDP_CTRL			364
+#define PCLK_VIO			365
+#define PCLK_VIO_NOC			366
+#define PCLK_VIO_GRF			367
+#define PCLK_MIPI_DSI0			368
+#define PCLK_MIPI_DSI1			369
+#define PCLK_HDCP			370
+#define PCLK_HDCP_NOC			371
+#define PCLK_HDMI_CTRL			372
+#define PCLK_DP_CTRL			373
+#define PCLK_HDCP22			374
+#define PCLK_GASKET			375
+#define PCLK_DDR			376
+#define PCLK_DDR_MON			377
+#define PCLK_DDR_SGRF			378
+#define PCLK_ISP1_WRAPPER		379
+#define PCLK_WDT			380
+#define PCLK_EFUSE1024NS		381
+#define PCLK_EFUSE1024S			382
+#define PCLK_PMU_INTR_ARB		383
+#define PCLK_MAILBOX0			384
+#define PCLK_USBPHY_MUX_G		385
+#define PCLK_UPHY0_TCPHY_G		386
+#define PCLK_UPHY0_TCPD_G		387
+#define PCLK_UPHY1_TCPHY_G		388
+#define PCLK_UPHY1_TCPD_G		389
+#define PCLK_ALIVE			390
+
+/* hclk gates */
+#define HCLK_PERIHP			448
+#define HCLK_PERILP0			449
+#define HCLK_PERILP1			450
+#define HCLK_PERILP0_NOC		451
+#define HCLK_PERILP1_NOC		452
+#define HCLK_M0_PERILP			453
+#define HCLK_M0_PERILP_NOC		454
+#define HCLK_AHB1TOM			455
+#define HCLK_HOST0			456
+#define HCLK_HOST0_ARB			457
+#define HCLK_HOST1			458
+#define HCLK_HOST1_ARB			459
+#define HCLK_HSIC			460
+#define HCLK_SD				461
+#define HCLK_SDMMC			462
+#define HCLK_SDMMC_NOC			463
+#define HCLK_M_CRYPTO0			464
+#define HCLK_M_CRYPTO1			465
+#define HCLK_S_CRYPTO0			466
+#define HCLK_S_CRYPTO1			467
+#define HCLK_I2S0_8CH			468
+#define HCLK_I2S1_8CH			469
+#define HCLK_I2S2_8CH			470
+#define HCLK_SPDIF			471
+#define HCLK_VOP0_NOC			472
+#define HCLK_VOP0			473
+#define HCLK_VOP1_NOC			474
+#define HCLK_VOP1			475
+#define HCLK_ROM			476
+#define HCLK_IEP			477
+#define HCLK_IEP_NOC			478
+#define HCLK_ISP0			479
+#define HCLK_ISP1			480
+#define HCLK_ISP0_NOC			481
+#define HCLK_ISP1_NOC			482
+#define HCLK_ISP0_WRAPPER		483
+#define HCLK_ISP1_WRAPPER		484
+#define HCLK_RGA			485
+#define HCLK_RGA_NOC			486
+#define HCLK_HDCP			487
+#define HCLK_HDCP_NOC			488
+#define HCLK_HDCP22			489
+#define HCLK_VCODEC			490
+#define HCLK_VCODEC_NOC			491
+#define HCLK_VDU			492
+#define HCLK_VDU_NOC			493
+#define HCLK_SDIO			494
+#define HCLK_SDIO_NOC			495
+#define HCLK_SDIOAUDIO_NOC		496
+
+#define CLK_NR_CLKS			(HCLK_SDIOAUDIO_NOC + 1)
+
+/* pmu-clocks indices */
+
+#define PLL_PPLL			1
+
+#define SCLK_32K_SUSPEND_PMU		2
+#define SCLK_SPI3_PMU			3
+#define SCLK_TIMER12_PMU		4
+#define SCLK_TIMER13_PMU		5
+#define SCLK_UART4_PMU			6
+#define SCLK_PVTM_PMU			7
+#define SCLK_WIFI_PMU			8
+#define SCLK_I2C0_PMU			9
+#define SCLK_I2C4_PMU			10
+#define SCLK_I2C8_PMU			11
+
+#define PCLK_SRC_PMU			19
+#define PCLK_PMU			20
+#define PCLK_PMUGRF_PMU			21
+#define PCLK_INTMEM1_PMU		22
+#define PCLK_GPIO0_PMU			23
+#define PCLK_GPIO1_PMU			24
+#define PCLK_SGRF_PMU			25
+#define PCLK_NOC_PMU			26
+#define PCLK_I2C0_PMU			27
+#define PCLK_I2C4_PMU			28
+#define PCLK_I2C8_PMU			29
+#define PCLK_RKPWM_PMU			30
+#define PCLK_SPI3_PMU			31
+#define PCLK_TIMER_PMU			32
+#define PCLK_MAILBOX_PMU		33
+#define PCLK_UART4_PMU			34
+#define PCLK_WDT_M0_PMU			35
+
+#define FCLK_CM0S_SRC_PMU		44
+#define FCLK_CM0S_PMU			45
+#define SCLK_CM0S_PMU			46
+#define HCLK_CM0S_PMU			47
+#define DCLK_CM0S_PMU			48
+#define PCLK_INTR_ARB_PMU		49
+#define HCLK_NOC_PMU			50
+
+#define CLKPMU_NR_CLKS			(HCLK_NOC_PMU + 1)
+
+/* soft-reset indices */
+
+/* cru_softrst_con0 */
+#define SRST_CORE_L0			0
+#define SRST_CORE_B0			1
+#define SRST_CORE_PO_L0			2
+#define SRST_CORE_PO_B0			3
+#define SRST_L2_L			4
+#define SRST_L2_B			5
+#define SRST_ADB_L			6
+#define SRST_ADB_B			7
+#define SRST_A_CCI			8
+#define SRST_A_CCIM0_NOC		9
+#define SRST_A_CCIM1_NOC		10
+#define SRST_DBG_NOC			11
+
+/* cru_softrst_con1 */
+#define SRST_CORE_L0_T			16
+#define SRST_CORE_L1			17
+#define SRST_CORE_L2			18
+#define SRST_CORE_L3			19
+#define SRST_CORE_PO_L0_T		20
+#define SRST_CORE_PO_L1			21
+#define SRST_CORE_PO_L2			22
+#define SRST_CORE_PO_L3			23
+#define SRST_A_ADB400_GIC2COREL		24
+#define SRST_A_ADB400_COREL2GIC		25
+#define SRST_P_DBG_L			26
+#define SRST_L2_L_T			28
+#define SRST_ADB_L_T			29
+#define SRST_A_RKPERF_L			30
+#define SRST_PVTM_CORE_L		31
+
+/* cru_softrst_con2 */
+#define SRST_CORE_B0_T			32
+#define SRST_CORE_B1			33
+#define SRST_CORE_PO_B0_T		36
+#define SRST_CORE_PO_B1			37
+#define SRST_A_ADB400_GIC2COREB		40
+#define SRST_A_ADB400_COREB2GIC		41
+#define SRST_P_DBG_B			42
+#define SRST_L2_B_T			43
+#define SRST_ADB_B_T			45
+#define SRST_A_RKPERF_B			46
+#define SRST_PVTM_CORE_B		47
+
+/* cru_softrst_con3 */
+#define SRST_A_CCI_T			50
+#define SRST_A_CCIM0_NOC_T		51
+#define SRST_A_CCIM1_NOC_T		52
+#define SRST_A_ADB400M_PD_CORE_B_T	53
+#define SRST_A_ADB400M_PD_CORE_L_T	54
+#define SRST_DBG_NOC_T			55
+#define SRST_DBG_CXCS			56
+#define SRST_CCI_TRACE			57
+#define SRST_P_CCI_GRF			58
+
+/* cru_softrst_con4 */
+#define SRST_A_CENTER_MAIN_NOC		64
+#define SRST_A_CENTER_PERI_NOC		65
+#define SRST_P_CENTER_MAIN		66
+#define SRST_P_DDRMON			67
+#define SRST_P_CIC			68
+#define SRST_P_CENTER_SGRF		69
+#define SRST_DDR0_MSCH			70
+#define SRST_DDRCFG0_MSCH		71
+#define SRST_DDR0			72
+#define SRST_DDRPHY0			73
+#define SRST_DDR1_MSCH			74
+#define SRST_DDRCFG1_MSCH		75
+#define SRST_DDR1			76
+#define SRST_DDRPHY1			77
+#define SRST_DDR_CIC			78
+#define SRST_PVTM_DDR			79
+
+/* cru_softrst_con5 */
+#define SRST_A_VCODEC_NOC		80
+#define SRST_A_VCODEC			81
+#define SRST_H_VCODEC_NOC		82
+#define SRST_H_VCODEC			83
+#define SRST_A_VDU_NOC			88
+#define SRST_A_VDU			89
+#define SRST_H_VDU_NOC			90
+#define SRST_H_VDU			91
+#define SRST_VDU_CORE			92
+#define SRST_VDU_CA			93
+
+/* cru_softrst_con6 */
+#define SRST_A_IEP_NOC			96
+#define SRST_A_VOP_IEP			97
+#define SRST_A_IEP			98
+#define SRST_H_IEP_NOC			99
+#define SRST_H_IEP			100
+#define SRST_A_RGA_NOC			102
+#define SRST_A_RGA			103
+#define SRST_H_RGA_NOC			104
+#define SRST_H_RGA			105
+#define SRST_RGA_CORE			106
+#define SRST_EMMC_NOC			108
+#define SRST_EMMC			109
+#define SRST_EMMC_GRF			110
+
+/* cru_softrst_con7 */
+#define SRST_A_PERIHP_NOC		112
+#define SRST_P_PERIHP_GRF		113
+#define SRST_H_PERIHP_NOC		114
+#define SRST_USBHOST0			115
+#define SRST_HOSTC0_AUX			116
+#define SRST_HOST0_ARB			117
+#define SRST_USBHOST1			118
+#define SRST_HOSTC1_AUX			119
+#define SRST_HOST1_ARB			120
+#define SRST_SDIO0			121
+#define SRST_SDMMC			122
+#define SRST_HSIC			123
+#define SRST_HSIC_AUX			124
+#define SRST_AHB1TOM			125
+#define SRST_P_PERIHP_NOC		126
+#define SRST_HSICPHY			127
+
+/* cru_softrst_con8 */
+#define SRST_A_PCIE			128
+#define SRST_P_PCIE			129
+#define SRST_PCIE_CORE			130
+#define SRST_PCIE_MGMT			131
+#define SRST_PCIE_MGMT_STICKY		132
+#define SRST_PCIE_PIPE			133
+#define SRST_PCIE_PM			134
+#define SRST_PCIEPHY			135
+#define SRST_A_GMAC_NOC			136
+#define SRST_A_GMAC			137
+#define SRST_P_GMAC_NOC			138
+#define SRST_P_GMAC_GRF			140
+#define SRST_HSICPHY_POR		142
+#define SRST_HSICPHY_UTMI		143
+
+/* cru_softrst_con9 */
+#define SRST_USB2PHY0_POR		144
+#define SRST_USB2PHY0_UTMI_PORT0	145
+#define SRST_USB2PHY0_UTMI_PORT1	146
+#define SRST_USB2PHY0_EHCIPHY		147
+#define SRST_UPHY0_PIPE_L00		148
+#define SRST_UPHY0			149
+#define SRST_UPHY0_TCPDPWRUP		150
+#define SRST_USB2PHY1_POR		152
+#define SRST_USB2PHY1_UTMI_PORT0	153
+#define SRST_USB2PHY1_UTMI_PORT1	154
+#define SRST_USB2PHY1_EHCIPHY		155
+#define SRST_UPHY1_PIPE_L00		156
+#define SRST_UPHY1			157
+#define SRST_UPHY1_TCPDPWRUP		158
+
+/* cru_softrst_con10 */
+#define SRST_A_PERILP0_NOC		160
+#define SRST_A_DCF			161
+#define SRST_GIC500			162
+#define SRST_DMAC0_PERILP0		163
+#define SRST_DMAC1_PERILP0		164
+#define SRST_TZMA			165
+#define SRST_INTMEM			166
+#define SRST_ADB400_MST0		167
+#define SRST_ADB400_MST1		168
+#define SRST_ADB400_SLV0		169
+#define SRST_ADB400_SLV1		170
+#define SRST_H_PERILP0			171
+#define SRST_H_PERILP0_NOC		172
+#define SRST_ROM			173
+#define SRST_CRYPTO_S			174
+#define SRST_CRYPTO_M			175
+
+/* cru_softrst_con11 */
+#define SRST_P_DCF			176
+#define SRST_CM0S_NOC			177
+#define SRST_CM0S			178
+#define SRST_CM0S_DBG			179
+#define SRST_CM0S_PO			180
+#define SRST_CRYPTO			181
+#define SRST_P_PERILP1_SGRF		182
+#define SRST_P_PERILP1_GRF		183
+#define SRST_CRYPTO1_S			184
+#define SRST_CRYPTO1_M			185
+#define SRST_CRYPTO1			186
+#define SRST_GIC_NOC			188
+#define SRST_SD_NOC			189
+#define SRST_SDIOAUDIO_BRG		190
+
+/* cru_softrst_con12 */
+#define SRST_H_PERILP1			192
+#define SRST_H_PERILP1_NOC		193
+#define SRST_H_I2S0_8CH			194
+#define SRST_H_I2S1_8CH			195
+#define SRST_H_I2S2_8CH			196
+#define SRST_H_SPDIF_8CH		197
+#define SRST_P_PERILP1_NOC		198
+#define SRST_P_EFUSE_1024		199
+#define SRST_P_EFUSE_1024S		200
+#define SRST_P_I2C0			201
+#define SRST_P_I2C1			202
+#define SRST_P_I2C2			203
+#define SRST_P_I2C3			204
+#define SRST_P_I2C4			205
+#define SRST_P_I2C5			206
+#define SRST_P_MAILBOX0			207
+
+/* cru_softrst_con13 */
+#define SRST_P_UART0			208
+#define SRST_P_UART1			209
+#define SRST_P_UART2			210
+#define SRST_P_UART3			211
+#define SRST_P_SARADC			212
+#define SRST_P_TSADC			213
+#define SRST_P_SPI0			214
+#define SRST_P_SPI1			215
+#define SRST_P_SPI2			216
+#define SRST_P_SPI3			217
+#define SRST_P_SPI4			218
+#define SRST_SPI0			219
+#define SRST_SPI1			220
+#define SRST_SPI2			221
+#define SRST_SPI3			222
+#define SRST_SPI4			223
+
+/* cru_softrst_con14 */
+#define SRST_I2S0_8CH			224
+#define SRST_I2S1_8CH			225
+#define SRST_I2S2_8CH			226
+#define SRST_SPDIF_8CH			227
+#define SRST_UART0			228
+#define SRST_UART1			229
+#define SRST_UART2			230
+#define SRST_UART3			231
+#define SRST_TSADC			232
+#define SRST_I2C0			233
+#define SRST_I2C1			234
+#define SRST_I2C2			235
+#define SRST_I2C3			236
+#define SRST_I2C4			237
+#define SRST_I2C5			238
+#define SRST_SDIOAUDIO_NOC		239
+
+/* cru_softrst_con15 */
+#define SRST_A_VIO_NOC			240
+#define SRST_A_HDCP_NOC			241
+#define SRST_A_HDCP			242
+#define SRST_H_HDCP_NOC			243
+#define SRST_H_HDCP			244
+#define SRST_P_HDCP_NOC			245
+#define SRST_P_HDCP			246
+#define SRST_P_HDMI_CTRL		247
+#define SRST_P_DP_CTRL			248
+#define SRST_S_DP_CTRL			249
+#define SRST_C_DP_CTRL			250
+#define SRST_P_MIPI_DSI0		251
+#define SRST_P_MIPI_DSI1		252
+#define SRST_DP_CORE			253
+#define SRST_DP_I2S			254
+
+/* cru_softrst_con16 */
+#define SRST_GASKET			256
+#define SRST_VIO_GRF			258
+#define SRST_DPTX_SPDIF_REC		259
+#define SRST_HDMI_CTRL			260
+#define SRST_HDCP_CTRL			261
+#define SRST_A_ISP0_NOC			262
+#define SRST_A_ISP1_NOC			263
+#define SRST_H_ISP0_NOC			266
+#define SRST_H_ISP1_NOC			267
+#define SRST_H_ISP0			268
+#define SRST_H_ISP1			269
+#define SRST_ISP0			270
+#define SRST_ISP1			271
+
+/* cru_softrst_con17 */
+#define SRST_A_VOP0_NOC			272
+#define SRST_A_VOP1_NOC			273
+#define SRST_A_VOP0			274
+#define SRST_A_VOP1			275
+#define SRST_H_VOP0_NOC			276
+#define SRST_H_VOP1_NOC			277
+#define SRST_H_VOP0			278
+#define SRST_H_VOP1			279
+#define SRST_D_VOP0			280
+#define SRST_D_VOP1			281
+#define SRST_VOP0_PWM			282
+#define SRST_VOP1_PWM			283
+#define SRST_P_EDP_NOC			284
+#define SRST_P_EDP_CTRL			285
+
+/* cru_softrst_con18 */
+#define SRST_A_GPU			288
+#define SRST_A_GPU_NOC			289
+#define SRST_A_GPU_GRF			290
+#define SRST_PVTM_GPU			291
+#define SRST_A_USB3_NOC			292
+#define SRST_A_USB3_OTG0		293
+#define SRST_A_USB3_OTG1		294
+#define SRST_A_USB3_GRF			295
+#define SRST_PMU			296
+
+/* cru_softrst_con19 */
+#define SRST_P_TIMER0_5			304
+#define SRST_TIMER0			305
+#define SRST_TIMER1			306
+#define SRST_TIMER2			307
+#define SRST_TIMER3			308
+#define SRST_TIMER4			309
+#define SRST_TIMER5			310
+#define SRST_P_TIMER6_11		311
+#define SRST_TIMER6			312
+#define SRST_TIMER7			313
+#define SRST_TIMER8			314
+#define SRST_TIMER9			315
+#define SRST_TIMER10			316
+#define SRST_TIMER11			317
+#define SRST_P_INTR_ARB_PMU		318
+#define SRST_P_ALIVE_SGRF		319
+
+/* cru_softrst_con20 */
+#define SRST_P_GPIO2			320
+#define SRST_P_GPIO3			321
+#define SRST_P_GPIO4			322
+#define SRST_P_GRF			323
+#define SRST_P_ALIVE_NOC		324
+#define SRST_P_WDT0			325
+#define SRST_P_WDT1			326
+#define SRST_P_INTR_ARB			327
+#define SRST_P_UPHY0_DPTX		328
+#define SRST_P_UPHY0_APB		330
+#define SRST_P_UPHY0_TCPHY		332
+#define SRST_P_UPHY1_TCPHY		333
+#define SRST_P_UPHY0_TCPDCTRL		334
+#define SRST_P_UPHY1_TCPDCTRL		335
+
+/* pmu soft-reset indices */
+
+/* pmu_cru_softrst_con0 */
+#define SRST_P_NOC			0
+#define SRST_P_INTMEM			1
+#define SRST_H_CM0S			2
+#define SRST_H_CM0S_NOC			3
+#define SRST_DBG_CM0S			4
+#define SRST_PO_CM0S			5
+#define SRST_P_SPI6			6
+#define SRST_SPI6			7
+#define SRST_P_TIMER_0_1		8
+#define SRST_P_TIMER_0			9
+#define SRST_P_TIMER_1			10
+#define SRST_P_UART4			11
+#define SRST_UART4			12
+#define SRST_P_WDT			13
+
+/* pmu_cru_softrst_con1 */
+#define SRST_P_I2C6			16
+#define SRST_P_I2C7			17
+#define SRST_P_I2C8			18
+#define SRST_P_MAILBOX			19
+#define SRST_P_RKPWM			20
+#define SRST_P_PMUGRF			21
+#define SRST_P_SGRF			22
+#define SRST_P_GPIO0			23
+#define SRST_P_GPIO1			24
+#define SRST_P_CRU			25
+#define SRST_P_INTR			26
+#define SRST_PVTM			27
+#define SRST_I2C6			28
+#define SRST_I2C7			29
+#define SRST_I2C8			30
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h b/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h
index 6f45aea49e4f..bd3530e56d46 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/tegra210-car.h
@@ -126,7 +126,7 @@
 /* 104 */
 /* 105 */
 #define TEGRA210_CLK_D_AUDIO 106
-/* 107 ( affects abp -> ape) */
+#define TEGRA210_CLK_APB2APE 107
 /* 108 */
 /* 109 */
 /* 110 */
@@ -346,7 +346,7 @@
 #define TEGRA210_CLK_PLL_P_OUT_HSIO 316
 #define TEGRA210_CLK_PLL_P_OUT_XUSB 317
 #define TEGRA210_CLK_XUSB_SSP_SRC 318
-/* 319 */
+#define TEGRA210_CLK_PLL_RE_OUT1 319
 /* 320 */
 /* 321 */
 /* 322 */
diff --git a/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h b/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h
index 56c16aaea112..45997750c8a0 100644
--- a/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h
+++ b/sys/gnu/dts/include/dt-bindings/clock/vf610-clock.h
@@ -194,7 +194,11 @@
 #define VF610_PLL7_BYPASS		181
 #define VF610_CLK_SNVS			182
 #define VF610_CLK_DAP			183
-#define VF610_CLK_OCOTP         184
-#define VF610_CLK_END			185
+#define VF610_CLK_OCOTP			184
+#define VF610_CLK_DDRMC			185
+#define VF610_CLK_WKPU			186
+#define VF610_CLK_TCON0			187
+#define VF610_CLK_TCON1			188
+#define VF610_CLK_END			189
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/sys/gnu/dts/include/dt-bindings/gpio/meson-gxbb-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/meson-gxbb-gpio.h
new file mode 100644
index 000000000000..58654fd7aa1e
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/gpio/meson-gxbb-gpio.h
@@ -0,0 +1,154 @@
+/*
+ * GPIO definitions for Amlogic Meson GXBB SoCs
+ *
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H
+#define _DT_BINDINGS_MESON_GXBB_GPIO_H
+
+#define	GPIOAO_0	0
+#define	GPIOAO_1	1
+#define	GPIOAO_2	2
+#define	GPIOAO_3	3
+#define	GPIOAO_4	4
+#define	GPIOAO_5	5
+#define	GPIOAO_6	6
+#define	GPIOAO_7	7
+#define	GPIOAO_8	8
+#define	GPIOAO_9	9
+#define	GPIOAO_10	10
+#define	GPIOAO_11	11
+#define	GPIOAO_12	12
+#define	GPIOAO_13	13
+
+#define	GPIOZ_0		0
+#define	GPIOZ_1		1
+#define	GPIOZ_2		2
+#define	GPIOZ_3		3
+#define	GPIOZ_4		4
+#define	GPIOZ_5		5
+#define	GPIOZ_6		6
+#define	GPIOZ_7		7
+#define	GPIOZ_8		8
+#define	GPIOZ_9		9
+#define	GPIOZ_10	10
+#define	GPIOZ_11	11
+#define	GPIOZ_12	12
+#define	GPIOZ_13	13
+#define	GPIOZ_14	14
+#define	GPIOZ_15	15
+#define	GPIOH_0		16
+#define	GPIOH_1		17
+#define	GPIOH_2		18
+#define	GPIOH_3		19
+#define	BOOT_0		20
+#define	BOOT_1		21
+#define	BOOT_2		22
+#define	BOOT_3		23
+#define	BOOT_4		24
+#define	BOOT_5		25
+#define	BOOT_6		26
+#define	BOOT_7		27
+#define	BOOT_8		28
+#define	BOOT_9		29
+#define	BOOT_10		30
+#define	BOOT_11		31
+#define	BOOT_12		32
+#define	BOOT_13		33
+#define	BOOT_14		34
+#define	BOOT_15		35
+#define	BOOT_16		36
+#define	BOOT_17		37
+#define	CARD_0		38
+#define	CARD_1		39
+#define	CARD_2		40
+#define	CARD_3		41
+#define	CARD_4		42
+#define	CARD_5		43
+#define	CARD_6		44
+#define	GPIODV_0	45
+#define	GPIODV_1	46
+#define	GPIODV_2	47
+#define	GPIODV_3	48
+#define	GPIODV_4	49
+#define	GPIODV_5	50
+#define	GPIODV_6	51
+#define	GPIODV_7	52
+#define	GPIODV_8	53
+#define	GPIODV_9	54
+#define	GPIODV_10	55
+#define	GPIODV_11	56
+#define	GPIODV_12	57
+#define	GPIODV_13	58
+#define	GPIODV_14	59
+#define	GPIODV_15	60
+#define	GPIODV_16	61
+#define	GPIODV_17	62
+#define	GPIODV_18	63
+#define	GPIODV_19	64
+#define	GPIODV_20	65
+#define	GPIODV_21	66
+#define	GPIODV_22	67
+#define	GPIODV_23	68
+#define	GPIODV_24	69
+#define	GPIODV_25	70
+#define	GPIODV_26	71
+#define	GPIODV_27	72
+#define	GPIODV_28	73
+#define	GPIODV_29	74
+#define	GPIOY_0		75
+#define	GPIOY_1		76
+#define	GPIOY_2		77
+#define	GPIOY_3		78
+#define	GPIOY_4		79
+#define	GPIOY_5		80
+#define	GPIOY_6		81
+#define	GPIOY_7		82
+#define	GPIOY_8		83
+#define	GPIOY_9		84
+#define	GPIOY_10	85
+#define	GPIOY_11	86
+#define	GPIOY_12	87
+#define	GPIOY_13	88
+#define	GPIOY_14	89
+#define	GPIOY_15	90
+#define	GPIOY_16	91
+#define	GPIOX_0		92
+#define	GPIOX_1		93
+#define	GPIOX_2		94
+#define	GPIOX_3		95
+#define	GPIOX_4		96
+#define	GPIOX_5		97
+#define	GPIOX_6		98
+#define	GPIOX_7		99
+#define	GPIOX_8		100
+#define	GPIOX_9		101
+#define	GPIOX_10	102
+#define	GPIOX_11	103
+#define	GPIOX_12	104
+#define	GPIOX_13	105
+#define	GPIOX_14	106
+#define	GPIOX_15	107
+#define	GPIOX_16	108
+#define	GPIOX_17	109
+#define	GPIOX_18	110
+#define	GPIOX_19	111
+#define	GPIOX_20	112
+#define	GPIOX_21	113
+#define	GPIOX_22	114
+#define	GPIOCLK_0	115
+#define	GPIOCLK_1	116
+#define	GPIOCLK_2	117
+#define	GPIOCLK_3	118
+#define	GPIO_TEST_N	119
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/gpio/tegra-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/tegra-gpio.h
index 197dc28b676e..a1c09e88e80b 100644
--- a/sys/gnu/dts/include/dt-bindings/gpio/tegra-gpio.h
+++ b/sys/gnu/dts/include/dt-bindings/gpio/tegra-gpio.h
@@ -12,40 +12,40 @@
 
 #include <dt-bindings/gpio/gpio.h>
 
-#define TEGRA_GPIO_BANK_ID_A 0
-#define TEGRA_GPIO_BANK_ID_B 1
-#define TEGRA_GPIO_BANK_ID_C 2
-#define TEGRA_GPIO_BANK_ID_D 3
-#define TEGRA_GPIO_BANK_ID_E 4
-#define TEGRA_GPIO_BANK_ID_F 5
-#define TEGRA_GPIO_BANK_ID_G 6
-#define TEGRA_GPIO_BANK_ID_H 7
-#define TEGRA_GPIO_BANK_ID_I 8
-#define TEGRA_GPIO_BANK_ID_J 9
-#define TEGRA_GPIO_BANK_ID_K 10
-#define TEGRA_GPIO_BANK_ID_L 11
-#define TEGRA_GPIO_BANK_ID_M 12
-#define TEGRA_GPIO_BANK_ID_N 13
-#define TEGRA_GPIO_BANK_ID_O 14
-#define TEGRA_GPIO_BANK_ID_P 15
-#define TEGRA_GPIO_BANK_ID_Q 16
-#define TEGRA_GPIO_BANK_ID_R 17
-#define TEGRA_GPIO_BANK_ID_S 18
-#define TEGRA_GPIO_BANK_ID_T 19
-#define TEGRA_GPIO_BANK_ID_U 20
-#define TEGRA_GPIO_BANK_ID_V 21
-#define TEGRA_GPIO_BANK_ID_W 22
-#define TEGRA_GPIO_BANK_ID_X 23
-#define TEGRA_GPIO_BANK_ID_Y 24
-#define TEGRA_GPIO_BANK_ID_Z 25
-#define TEGRA_GPIO_BANK_ID_AA 26
-#define TEGRA_GPIO_BANK_ID_BB 27
-#define TEGRA_GPIO_BANK_ID_CC 28
-#define TEGRA_GPIO_BANK_ID_DD 29
-#define TEGRA_GPIO_BANK_ID_EE 30
-#define TEGRA_GPIO_BANK_ID_FF 31
+#define TEGRA_GPIO_PORT_A 0
+#define TEGRA_GPIO_PORT_B 1
+#define TEGRA_GPIO_PORT_C 2
+#define TEGRA_GPIO_PORT_D 3
+#define TEGRA_GPIO_PORT_E 4
+#define TEGRA_GPIO_PORT_F 5
+#define TEGRA_GPIO_PORT_G 6
+#define TEGRA_GPIO_PORT_H 7
+#define TEGRA_GPIO_PORT_I 8
+#define TEGRA_GPIO_PORT_J 9
+#define TEGRA_GPIO_PORT_K 10
+#define TEGRA_GPIO_PORT_L 11
+#define TEGRA_GPIO_PORT_M 12
+#define TEGRA_GPIO_PORT_N 13
+#define TEGRA_GPIO_PORT_O 14
+#define TEGRA_GPIO_PORT_P 15
+#define TEGRA_GPIO_PORT_Q 16
+#define TEGRA_GPIO_PORT_R 17
+#define TEGRA_GPIO_PORT_S 18
+#define TEGRA_GPIO_PORT_T 19
+#define TEGRA_GPIO_PORT_U 20
+#define TEGRA_GPIO_PORT_V 21
+#define TEGRA_GPIO_PORT_W 22
+#define TEGRA_GPIO_PORT_X 23
+#define TEGRA_GPIO_PORT_Y 24
+#define TEGRA_GPIO_PORT_Z 25
+#define TEGRA_GPIO_PORT_AA 26
+#define TEGRA_GPIO_PORT_BB 27
+#define TEGRA_GPIO_PORT_CC 28
+#define TEGRA_GPIO_PORT_DD 29
+#define TEGRA_GPIO_PORT_EE 30
+#define TEGRA_GPIO_PORT_FF 31
 
-#define TEGRA_GPIO(bank, offset) \
-	((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+#define TEGRA_GPIO(port, offset) \
+	((TEGRA_GPIO_PORT_##port * 8) + offset)
 
 #endif
diff --git a/sys/gnu/dts/include/dt-bindings/gpio/tegra186-gpio.h b/sys/gnu/dts/include/dt-bindings/gpio/tegra186-gpio.h
new file mode 100644
index 000000000000..38001c7023f1
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/gpio/tegra186-gpio.h
@@ -0,0 +1,56 @@
+/*
+ * This header provides constants for binding nvidia,tegra186-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_MAIN_GPIO_PORT_A 0
+#define TEGRA_MAIN_GPIO_PORT_B 1
+#define TEGRA_MAIN_GPIO_PORT_C 2
+#define TEGRA_MAIN_GPIO_PORT_D 3
+#define TEGRA_MAIN_GPIO_PORT_E 4
+#define TEGRA_MAIN_GPIO_PORT_F 5
+#define TEGRA_MAIN_GPIO_PORT_G 6
+#define TEGRA_MAIN_GPIO_PORT_H 7
+#define TEGRA_MAIN_GPIO_PORT_I 8
+#define TEGRA_MAIN_GPIO_PORT_J 9
+#define TEGRA_MAIN_GPIO_PORT_K 10
+#define TEGRA_MAIN_GPIO_PORT_L 11
+#define TEGRA_MAIN_GPIO_PORT_M 12
+#define TEGRA_MAIN_GPIO_PORT_N 13
+#define TEGRA_MAIN_GPIO_PORT_O 14
+#define TEGRA_MAIN_GPIO_PORT_P 15
+#define TEGRA_MAIN_GPIO_PORT_Q 16
+#define TEGRA_MAIN_GPIO_PORT_R 17
+#define TEGRA_MAIN_GPIO_PORT_T 18
+#define TEGRA_MAIN_GPIO_PORT_X 19
+#define TEGRA_MAIN_GPIO_PORT_Y 20
+#define TEGRA_MAIN_GPIO_PORT_BB 21
+#define TEGRA_MAIN_GPIO_PORT_CC 22
+
+#define TEGRA_MAIN_GPIO(port, offset) \
+	((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_AON_GPIO_PORT_S 0
+#define TEGRA_AON_GPIO_PORT_U 1
+#define TEGRA_AON_GPIO_PORT_V 2
+#define TEGRA_AON_GPIO_PORT_W 3
+#define TEGRA_AON_GPIO_PORT_Z 4
+#define TEGRA_AON_GPIO_PORT_AA 5
+#define TEGRA_AON_GPIO_PORT_EE 6
+#define TEGRA_AON_GPIO_PORT_FF 7
+
+#define TEGRA_AON_GPIO(port, offset) \
+	((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/iio/adc/fsl-imx25-gcq.h b/sys/gnu/dts/include/dt-bindings/iio/adc/fsl-imx25-gcq.h
new file mode 100644
index 000000000000..87abdd4a7674
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/iio/adc/fsl-imx25-gcq.h
@@ -0,0 +1,18 @@
+/*
+ * This header provides constants for configuring the I.MX25 ADC
+ */
+
+#ifndef _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H
+#define _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H
+
+#define MX25_ADC_REFP_YP	0 /* YP voltage reference */
+#define MX25_ADC_REFP_XP	1 /* XP voltage reference */
+#define MX25_ADC_REFP_EXT	2 /* External voltage reference */
+#define MX25_ADC_REFP_INT	3 /* Internal voltage reference */
+
+#define MX25_ADC_REFN_XN	0 /* XN ground reference */
+#define MX25_ADC_REFN_YN	1 /* YN ground reference */
+#define MX25_ADC_REFN_NGND	2 /* Internal ground reference */
+#define MX25_ADC_REFN_NGND2	3 /* External ground reference */
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/iio/adi,ad5592r.h b/sys/gnu/dts/include/dt-bindings/iio/adi,ad5592r.h
new file mode 100644
index 000000000000..c48aca1dcade
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/iio/adi,ad5592r.h
@@ -0,0 +1,16 @@
+
+#ifndef _DT_BINDINGS_ADI_AD5592R_H
+#define _DT_BINDINGS_ADI_AD5592R_H
+
+#define CH_MODE_UNUSED			0
+#define CH_MODE_ADC			1
+#define CH_MODE_DAC			2
+#define CH_MODE_DAC_AND_ADC		3
+#define CH_MODE_GPIO			8
+
+#define CH_OFFSTATE_PULLDOWN		0
+#define CH_OFFSTATE_OUT_LOW		1
+#define CH_OFFSTATE_OUT_HIGH		2
+#define CH_OFFSTATE_OUT_TRISTATE	3
+
+#endif /* _DT_BINDINGS_ADI_AD5592R_H */
diff --git a/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h b/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h
index 87cf351bab03..d6d071fc3c56 100644
--- a/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h
+++ b/sys/gnu/dts/include/dt-bindings/input/linux-event-codes.h
@@ -611,6 +611,37 @@
 #define KEY_KBDINPUTASSIST_ACCEPT		0x264
 #define KEY_KBDINPUTASSIST_CANCEL		0x265
 
+/* Diagonal movement keys */
+#define KEY_RIGHT_UP			0x266
+#define KEY_RIGHT_DOWN			0x267
+#define KEY_LEFT_UP			0x268
+#define KEY_LEFT_DOWN			0x269
+
+#define KEY_ROOT_MENU			0x26a /* Show Device's Root Menu */
+/* Show Top Menu of the Media (e.g. DVD) */
+#define KEY_MEDIA_TOP_MENU		0x26b
+#define KEY_NUMERIC_11			0x26c
+#define KEY_NUMERIC_12			0x26d
+/*
+ * Toggle Audio Description: refers to an audio service that helps blind and
+ * visually impaired consumers understand the action in a program. Note: in
+ * some countries this is referred to as "Video Description".
+ */
+#define KEY_AUDIO_DESC			0x26e
+#define KEY_3D_MODE			0x26f
+#define KEY_NEXT_FAVORITE		0x270
+#define KEY_STOP_RECORD			0x271
+#define KEY_PAUSE_RECORD		0x272
+#define KEY_VOD				0x273 /* Video on Demand */
+#define KEY_UNMUTE			0x274
+#define KEY_FASTREVERSE			0x275
+#define KEY_SLOWREVERSE			0x276
+/*
+ * Control a data application associated with the currently viewed channel,
+ * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
+ */
+#define KEY_DATA			0x275
+
 #define BTN_TRIGGER_HAPPY		0x2c0
 #define BTN_TRIGGER_HAPPY1		0x2c0
 #define BTN_TRIGGER_HAPPY2		0x2c1
@@ -749,6 +780,7 @@
 #define SW_ROTATE_LOCK		0x0c  /* set = rotate locked/disabled */
 #define SW_LINEIN_INSERT	0x0d  /* set = inserted */
 #define SW_MUTE_DEVICE		0x0e  /* set = device disabled */
+#define SW_PEN_INSERTED		0x0f  /* set = pen inserted */
 #define SW_MAX			0x0f
 #define SW_CNT			(SW_MAX+1)
 
diff --git a/sys/gnu/dts/include/dt-bindings/media/tvp5150.h b/sys/gnu/dts/include/dt-bindings/media/tvp5150.h
new file mode 100644
index 000000000000..c852a35e916e
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/media/tvp5150.h
@@ -0,0 +1,35 @@
+/*
+    tvp5150.h - definition for tvp5150 inputs
+
+    Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef _DT_BINDINGS_MEDIA_TVP5150_H
+#define _DT_BINDINGS_MEDIA_TVP5150_H
+
+/* TVP5150 HW inputs */
+#define TVP5150_COMPOSITE0 0
+#define TVP5150_COMPOSITE1 1
+#define TVP5150_SVIDEO     2
+
+#define TVP5150_INPUT_NUM  3
+
+/* TVP5150 HW outputs */
+#define TVP5150_NORMAL       0
+#define TVP5150_BLACK_SCREEN 1
+
+#endif /* _DT_BINDINGS_MEDIA_TVP5150_H */
diff --git a/sys/gnu/dts/include/dt-bindings/memory/mt8173-larb-port.h b/sys/gnu/dts/include/dt-bindings/memory/mt8173-larb-port.h
new file mode 100644
index 000000000000..5fef5d1f8f82
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/memory/mt8173-larb-port.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2015-2016 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DTS_IOMMU_PORT_MT8173_H
+#define __DTS_IOMMU_PORT_MT8173_H
+
+#define MTK_M4U_ID(larb, port)		(((larb) << 5) | (port))
+/* Local arbiter ID */
+#define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x7)
+/* PortID within the local arbiter */
+#define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
+
+#define M4U_LARB0_ID			0
+#define M4U_LARB1_ID			1
+#define M4U_LARB2_ID			2
+#define M4U_LARB3_ID			3
+#define M4U_LARB4_ID			4
+#define M4U_LARB5_ID			5
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0		MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_WDMA0		MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_OD_R		MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_OD_W		MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WDMA		MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0		MTK_M4U_ID(M4U_LARB0_ID, 7)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT		MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT		MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_UFO_EXT	MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_VLD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_VLD2_EXT	MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_HW_VDEC_TILE		MTK_M4U_ID(M4U_LARB1_ID, 9)
+
+/* larb2 */
+#define M4U_PORT_IMGO			MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_RRZO			MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_AAO			MTK_M4U_ID(M4U_LARB2_ID, 2)
+#define M4U_PORT_LCSO			MTK_M4U_ID(M4U_LARB2_ID, 3)
+#define M4U_PORT_ESFKO			MTK_M4U_ID(M4U_LARB2_ID, 4)
+#define M4U_PORT_IMGO_D			MTK_M4U_ID(M4U_LARB2_ID, 5)
+#define M4U_PORT_LSCI			MTK_M4U_ID(M4U_LARB2_ID, 6)
+#define M4U_PORT_LSCI_D			MTK_M4U_ID(M4U_LARB2_ID, 7)
+#define M4U_PORT_BPCI			MTK_M4U_ID(M4U_LARB2_ID, 8)
+#define M4U_PORT_BPCI_D			MTK_M4U_ID(M4U_LARB2_ID, 9)
+#define M4U_PORT_UFDI			MTK_M4U_ID(M4U_LARB2_ID, 10)
+#define M4U_PORT_IMGI			MTK_M4U_ID(M4U_LARB2_ID, 11)
+#define M4U_PORT_IMG2O			MTK_M4U_ID(M4U_LARB2_ID, 12)
+#define M4U_PORT_IMG3O			MTK_M4U_ID(M4U_LARB2_ID, 13)
+#define M4U_PORT_VIPI			MTK_M4U_ID(M4U_LARB2_ID, 14)
+#define M4U_PORT_VIP2I			MTK_M4U_ID(M4U_LARB2_ID, 15)
+#define M4U_PORT_VIP3I			MTK_M4U_ID(M4U_LARB2_ID, 16)
+#define M4U_PORT_LCEI			MTK_M4U_ID(M4U_LARB2_ID, 17)
+#define M4U_PORT_RB			MTK_M4U_ID(M4U_LARB2_ID, 18)
+#define M4U_PORT_RP			MTK_M4U_ID(M4U_LARB2_ID, 19)
+#define M4U_PORT_WR			MTK_M4U_ID(M4U_LARB2_ID, 20)
+
+/* larb3 */
+#define M4U_PORT_VENC_RCPU		MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_VENC_REC		MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_VENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_VENC_SV_COMV		MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_VENC_RD_COMV		MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_JPGENC_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_JPGENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_JPGDEC_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_JPGDEC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 8)
+#define M4U_PORT_VENC_CUR_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 9)
+#define M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 10)
+#define M4U_PORT_VENC_REF_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 11)
+#define M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 12)
+#define M4U_PORT_VENC_NBM_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 13)
+#define M4U_PORT_VENC_NBM_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 14)
+
+/* larb4 */
+#define M4U_PORT_DISP_OVL1		MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_DISP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_DISP_RDMA2		MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_DISP_WDMA1		MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_MDP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_MDP_WROT1		MTK_M4U_ID(M4U_LARB4_ID, 5)
+
+/* larb5 */
+#define M4U_PORT_VENC_RCPU_SET2		MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_VENC_REC_FRM_SET2	MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_VENC_REF_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_VENC_REC_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define M4U_PORT_VENC_BSDMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define M4U_PORT_VENC_CUR_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define M4U_PORT_VENC_CUR_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define M4U_PORT_VENC_RD_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define M4U_PORT_VENC_SV_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 8)
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/mfd/arizona.h b/sys/gnu/dts/include/dt-bindings/mfd/arizona.h
index c40f665e2712..dedf46ffdb53 100644
--- a/sys/gnu/dts/include/dt-bindings/mfd/arizona.h
+++ b/sys/gnu/dts/include/dt-bindings/mfd/arizona.h
@@ -110,4 +110,9 @@
 #define ARIZONA_ACCDET_MODE_HPM 4
 #define ARIZONA_ACCDET_MODE_ADC 7
 
+#define ARIZONA_GPSW_OPEN           0
+#define ARIZONA_GPSW_CLOSED         1
+#define ARIZONA_GPSW_CLAMP_ENABLED  2
+#define ARIZONA_GPSW_CLAMP_DISABLED 3
+
 #endif
diff --git a/sys/gnu/dts/include/dt-bindings/mfd/max77620.h b/sys/gnu/dts/include/dt-bindings/mfd/max77620.h
new file mode 100644
index 000000000000..b911a0720ccd
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/mfd/max77620.h
@@ -0,0 +1,39 @@
+/*
+ * This header provides macros for MAXIM MAX77620 device bindings.
+ *
+ * Copyright (c) 2016, NVIDIA Corporation.
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ */
+
+#ifndef _DT_BINDINGS_MFD_MAX77620_H
+#define _DT_BINDINGS_MFD_MAX77620_H
+
+/* MAX77620 interrupts */
+#define MAX77620_IRQ_TOP_GLBL		0 /* Low-Battery */
+#define MAX77620_IRQ_TOP_SD		1 /* SD power fail */
+#define MAX77620_IRQ_TOP_LDO		2 /* LDO power fail */
+#define MAX77620_IRQ_TOP_GPIO		3 /* GPIO internal int to MAX77620 */
+#define MAX77620_IRQ_TOP_RTC		4 /* RTC */
+#define MAX77620_IRQ_TOP_32K		5 /* 32kHz oscillator */
+#define MAX77620_IRQ_TOP_ONOFF		6 /* ON/OFF oscillator */
+#define MAX77620_IRQ_LBT_MBATLOW	7 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM1	8 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM2	9 /* Thermal alarm status, > 140C */
+
+/* FPS event source */
+#define MAX77620_FPS_EVENT_SRC_EN0		0
+#define MAX77620_FPS_EVENT_SRC_EN1		1
+#define MAX77620_FPS_EVENT_SRC_SW		2
+
+/* Device state when FPS event LOW  */
+#define MAX77620_FPS_INACTIVE_STATE_SLEEP	0
+#define MAX77620_FPS_INACTIVE_STATE_LOW_POWER	1
+
+/* FPS source */
+#define MAX77620_FPS_SRC_0			0
+#define MAX77620_FPS_SRC_1			1
+#define MAX77620_FPS_SRC_2			2
+#define MAX77620_FPS_SRC_NONE			3
+#define MAX77620_FPS_SRC_DEF			4
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/hisi.h b/sys/gnu/dts/include/dt-bindings/pinctrl/hisi.h
new file mode 100644
index 000000000000..38f1ea879ea1
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/pinctrl/hisi.h
@@ -0,0 +1,59 @@
+/*
+ * This header provides constants for hisilicon pinctrl bindings.
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ * Copyright (c) 2015 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_HISI_H
+#define _DT_BINDINGS_PINCTRL_HISI_H
+
+/* iomg bit definition */
+#define MUX_M0		0
+#define MUX_M1		1
+#define MUX_M2		2
+#define MUX_M3		3
+#define MUX_M4		4
+#define MUX_M5		5
+#define MUX_M6		6
+#define MUX_M7		7
+
+/* iocg bit definition */
+#define PULL_MASK	(3)
+#define PULL_DIS	(0)
+#define PULL_UP		(1 << 0)
+#define PULL_DOWN	(1 << 1)
+
+/* drive strength definition */
+#define DRIVE_MASK	(7 << 4)
+#define DRIVE1_02MA	(0 << 4)
+#define DRIVE1_04MA	(1 << 4)
+#define DRIVE1_08MA	(2 << 4)
+#define DRIVE1_10MA	(3 << 4)
+#define DRIVE2_02MA	(0 << 4)
+#define DRIVE2_04MA	(1 << 4)
+#define DRIVE2_08MA	(2 << 4)
+#define DRIVE2_10MA	(3 << 4)
+#define DRIVE3_04MA	(0 << 4)
+#define DRIVE3_08MA	(1 << 4)
+#define DRIVE3_12MA	(2 << 4)
+#define DRIVE3_16MA	(3 << 4)
+#define DRIVE3_20MA	(4 << 4)
+#define DRIVE3_24MA	(5 << 4)
+#define DRIVE3_32MA	(6 << 4)
+#define DRIVE3_40MA	(7 << 4)
+#define DRIVE4_02MA	(0 << 4)
+#define DRIVE4_04MA	(2 << 4)
+#define DRIVE4_08MA	(4 << 4)
+#define DRIVE4_10MA	(6 << 4)
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/sys/gnu/dts/include/dt-bindings/pinctrl/mt7623-pinfunc.h
new file mode 100644
index 000000000000..2f00bdc42442
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/pinctrl/mt7623-pinfunc.h
@@ -0,0 +1,520 @@
+#ifndef __DTS_MT7623_PINFUNC_H
+#define __DTS_MT7623_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
+
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
+
+#define MT7623_PIN_2_PWRAP_INT_FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT7623_PIN_2_PWRAP_INT_FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
+
+#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
+
+#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
+
+#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
+
+#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
+
+#define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
+
+#define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
+#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
+
+#define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
+#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
+
+#define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
+
+#define MT7623_PIN_11_WATCHDOG_FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT7623_PIN_11_WATCHDOG_FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
+
+#define MT7623_PIN_12_SRCLKENA_FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT7623_PIN_12_SRCLKENA_FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
+
+#define MT7623_PIN_13_SRCLKENAI_FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT7623_PIN_13_SRCLKENAI_FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
+
+#define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1)
+#define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
+
+#define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
+#define MT7623_PIN_15_GPIO15_FUNC_URXD2 (MTK_PIN_NO(15) | 2)
+
+#define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
+#define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6)
+
+#define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
+#define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6)
+
+#define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
+#define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
+#define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6)
+
+#define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
+#define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
+#define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6)
+
+#define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
+#define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2)
+
+#define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1)
+#define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2)
+
+#define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
+#define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2)
+
+#define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1)
+
+#define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
+#define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
+
+#define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1)
+#define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
+
+#define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
+#define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
+
+#define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1)
+#define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
+#define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6)
+
+#define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6)
+
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6)
+
+#define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6)
+
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6)
+
+#define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
+
+#define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1)
+
+#define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1)
+
+#define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1)
+
+#define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1)
+
+#define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1)
+#define MT7623_PIN_43_NCLE_FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
+
+#define MT7623_PIN_44_NCEB1_FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT7623_PIN_44_NCEB1_FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
+#define MT7623_PIN_44_NCEB1_FUNC_IDDIG (MTK_PIN_NO(44) | 2)
+
+#define MT7623_PIN_45_NCEB0_FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT7623_PIN_45_NCEB0_FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
+#define MT7623_PIN_45_NCEB0_FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
+
+#define MT7623_PIN_46_IR_FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT7623_PIN_46_IR_FUNC_IR (MTK_PIN_NO(46) | 1)
+
+#define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1)
+
+#define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1)
+
+#define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6)
+
+#define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
+#define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5)
+
+#define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
+
+#define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
+#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
+#define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
+#define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5)
+
+#define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
+#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+
+#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1)
+
+#define MT7623_PIN_61_GPIO61_FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT7623_PIN_61_GPIO61_FUNC_TEST_FD (MTK_PIN_NO(61) | 1)
+
+#define MT7623_PIN_62_GPIO62_FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT7623_PIN_62_GPIO62_FUNC_TEST_FC (MTK_PIN_NO(62) | 1)
+
+#define MT7623_PIN_63_WB_SCLK_FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT7623_PIN_63_WB_SCLK_FUNC_WB_SCLK (MTK_PIN_NO(63) | 1)
+
+#define MT7623_PIN_64_WB_SDATA_FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT7623_PIN_64_WB_SDATA_FUNC_WB_SDATA (MTK_PIN_NO(64) | 1)
+
+#define MT7623_PIN_65_WB_SEN_FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT7623_PIN_65_WB_SEN_FUNC_WB_SEN (MTK_PIN_NO(65) | 1)
+
+#define MT7623_PIN_66_WB_CRTL0_FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT7623_PIN_66_WB_CRTL0_FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1)
+
+#define MT7623_PIN_67_WB_CRTL1_FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT7623_PIN_67_WB_CRTL1_FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1)
+
+#define MT7623_PIN_68_WB_CRTL2_FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT7623_PIN_68_WB_CRTL2_FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1)
+
+#define MT7623_PIN_69_WB_CRTL3_FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT7623_PIN_69_WB_CRTL3_FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1)
+
+#define MT7623_PIN_70_WB_CRTL4_FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT7623_PIN_70_WB_CRTL4_FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1)
+
+#define MT7623_PIN_71_WB_CRTL5_FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT7623_PIN_71_WB_CRTL5_FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1)
+
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PWM0 (MTK_PIN_NO(72) | 4)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_AP_I2S_DI (MTK_PIN_NO(72) | 6)
+
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_AP_I2S_LRCK (MTK_PIN_NO(73) | 6)
+
+#define MT7623_PIN_74_I2S0_BCK_FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_AP_I2S_BCK (MTK_PIN_NO(74) | 6)
+
+#define MT7623_PIN_75_SDA0_FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT7623_PIN_75_SDA0_FUNC_SDA0 (MTK_PIN_NO(75) | 1)
+
+#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+
+#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
+
+#define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
+
+#define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1)
+
+#define MT7623_PIN_96_MIPI_TCP_FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT7623_PIN_96_MIPI_TCP_FUNC_TCP (MTK_PIN_NO(96) | 1)
+
+#define MT7623_PIN_97_MIPI_TDN1_FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1 (MTK_PIN_NO(97) | 1)
+
+#define MT7623_PIN_98_MIPI_TDP1_FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1 (MTK_PIN_NO(98) | 1)
+
+#define MT7623_PIN_99_MIPI_TDN0_FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0 (MTK_PIN_NO(99) | 1)
+
+#define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1)
+
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
+
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_SCL1 (MTK_PIN_NO(106) | 3)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
+
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
+
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM0 (MTK_PIN_NO(108) | 3)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_URXD0 (MTK_PIN_NO(108) | 5)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM1 (MTK_PIN_NO(108) | 6)
+
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_SDA2 (MTK_PIN_NO(109) | 3)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_PWM2 (MTK_PIN_NO(109) | 6)
+
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_SCL2 (MTK_PIN_NO(110) | 3)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_URXD1 (MTK_PIN_NO(110) | 5)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_PWM3 (MTK_PIN_NO(110) | 6)
+
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7 (MTK_PIN_NO(111) | 4)
+
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6 (MTK_PIN_NO(112) | 4)
+
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5 (MTK_PIN_NO(113) | 4)
+
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4 (MTK_PIN_NO(114) | 4)
+
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8 (MTK_PIN_NO(115) | 4)
+
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_NALE (MTK_PIN_NO(116) | 4)
+
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB (MTK_PIN_NO(117) | 4)
+
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3 (MTK_PIN_NO(118) | 4)
+
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2 (MTK_PIN_NO(119) | 4)
+
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1 (MTK_PIN_NO(120) | 4)
+
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0 (MTK_PIN_NO(121) | 4)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
+
+#define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT7623_PIN_122_GPIO122_FUNC_TEST (MTK_PIN_NO(122) | 1)
+#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4)
+#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5)
+
+#define MT7623_PIN_123_GPIO123_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT7623_PIN_123_GPIO123_FUNC_TEST (MTK_PIN_NO(123) | 1)
+#define MT7623_PIN_123_GPIO123_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT7623_PIN_123_GPIO123_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+
+#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1)
+#define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4)
+#define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5)
+
+#define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT7623_PIN_125_GPIO125_FUNC_TEST (MTK_PIN_NO(125) | 1)
+#define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4)
+#define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5)
+
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_AP_I2S_MCLK (MTK_PIN_NO(126) | 6)
+
+#define MT7623_PIN_199_SPI1_CK_FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
+
+#define MT7623_PIN_200_URXD2_FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT7623_PIN_200_URXD2_FUNC_URXD2 (MTK_PIN_NO(200) | 6)
+
+#define MT7623_PIN_201_UTXD2_FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT7623_PIN_201_UTXD2_FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
+
+#define MT7623_PIN_203_PWM0_FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define MT7623_PIN_203_PWM0_FUNC_PWM0 (MTK_PIN_NO(203) | 1)
+#define MT7623_PIN_203_PWM0_FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
+
+#define MT7623_PIN_204_PWM1_FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define MT7623_PIN_204_PWM1_FUNC_PWM1 (MTK_PIN_NO(204) | 1)
+
+#define MT7623_PIN_205_PWM2_FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define MT7623_PIN_205_PWM2_FUNC_PWM2 (MTK_PIN_NO(205) | 1)
+
+#define MT7623_PIN_206_PWM3_FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define MT7623_PIN_206_PWM3_FUNC_PWM3 (MTK_PIN_NO(206) | 1)
+
+#define MT7623_PIN_207_PWM4_FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define MT7623_PIN_207_PWM4_FUNC_PWM4 (MTK_PIN_NO(207) | 1)
+
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PWM0 (MTK_PIN_NO(208) | 2)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 3)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
+
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 3)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PWM1 (MTK_PIN_NO(209) | 5)
+
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_IDDIG (MTK_PIN_NO(236) | 2)
+
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
+
+#define MT7623_PIN_238_EXT_SDIO1_FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
+#define MT7623_PIN_238_EXT_SDIO1_FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
+
+#define MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
+#define MT7623_PIN_239_EXT_SDIO0_FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
+
+#define MT7623_PIN_240_EXT_XCS_FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
+#define MT7623_PIN_240_EXT_XCS_FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
+
+#define MT7623_PIN_241_EXT_SCK_FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
+#define MT7623_PIN_241_EXT_SCK_FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
+
+#define MT7623_PIN_242_URTS2_FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
+#define MT7623_PIN_242_URTS2_FUNC_URTS2 (MTK_PIN_NO(242) | 1)
+#define MT7623_PIN_242_URTS2_FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
+#define MT7623_PIN_242_URTS2_FUNC_URXD3 (MTK_PIN_NO(242) | 3)
+#define MT7623_PIN_242_URTS2_FUNC_SCL1 (MTK_PIN_NO(242) | 4)
+
+#define MT7623_PIN_243_UCTS2_FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
+#define MT7623_PIN_243_UCTS2_FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
+#define MT7623_PIN_243_UCTS2_FUNC_URXD3 (MTK_PIN_NO(243) | 2)
+#define MT7623_PIN_243_UCTS2_FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
+#define MT7623_PIN_243_UCTS2_FUNC_SDA1 (MTK_PIN_NO(243) | 4)
+
+#define MT7623_PIN_250_GPIO250_FUNC_GPIO250 (MTK_PIN_NO(250) | 0)
+#define MT7623_PIN_250_GPIO250_FUNC_TEST_MD7 (MTK_PIN_NO(250) | 1)
+#define MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 6)
+
+#define MT7623_PIN_251_GPIO251_FUNC_GPIO251 (MTK_PIN_NO(251) | 0)
+#define MT7623_PIN_251_GPIO251_FUNC_TEST_MD6 (MTK_PIN_NO(251) | 1)
+#define MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 6)
+
+#define MT7623_PIN_252_GPIO252_FUNC_GPIO252 (MTK_PIN_NO(252) | 0)
+#define MT7623_PIN_252_GPIO252_FUNC_TEST_MD5 (MTK_PIN_NO(252) | 1)
+#define MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 6)
+
+#define MT7623_PIN_253_GPIO253_FUNC_GPIO253 (MTK_PIN_NO(253) | 0)
+#define MT7623_PIN_253_GPIO253_FUNC_TEST_MD4 (MTK_PIN_NO(253) | 1)
+#define MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 6)
+
+#define MT7623_PIN_254_GPIO254_FUNC_GPIO254 (MTK_PIN_NO(254) | 0)
+#define MT7623_PIN_254_GPIO254_FUNC_TEST_MD3 (MTK_PIN_NO(254) | 1)
+#define MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 6)
+
+#define MT7623_PIN_255_GPIO255_FUNC_GPIO255 (MTK_PIN_NO(255) | 0)
+#define MT7623_PIN_255_GPIO255_FUNC_TEST_MD2 (MTK_PIN_NO(255) | 1)
+#define MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 6)
+
+#define MT7623_PIN_256_GPIO256_FUNC_GPIO256 (MTK_PIN_NO(256) | 0)
+#define MT7623_PIN_256_GPIO256_FUNC_TEST_MD1 (MTK_PIN_NO(256) | 1)
+
+#define MT7623_PIN_257_GPIO257_FUNC_GPIO257 (MTK_PIN_NO(257) | 0)
+#define MT7623_PIN_257_GPIO257_FUNC_TEST_MD0 (MTK_PIN_NO(257) | 1)
+
+#define MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
+#define MT7623_PIN_261_MSDC1_INS_FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
+
+#define MT7623_PIN_262_G2_TXEN_FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
+#define MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
+
+#define MT7623_PIN_263_G2_TXD3_FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
+#define MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
+
+#define MT7623_PIN_264_G2_TXD2_FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
+#define MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
+
+#define MT7623_PIN_265_G2_TXD1_FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
+#define MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
+
+#define MT7623_PIN_266_G2_TXD0_FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
+#define MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
+
+#define MT7623_PIN_267_G2_TXCLK_FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
+#define MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
+
+#define MT7623_PIN_268_G2_RXCLK_FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
+#define MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
+
+#define MT7623_PIN_269_G2_RXD0_FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
+#define MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
+
+#define MT7623_PIN_270_G2_RXD1_FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
+#define MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
+
+#define MT7623_PIN_271_G2_RXD2_FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
+#define MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
+
+#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
+#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
+
+#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
+#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
+
+#define MT7623_PIN_275_G2_MDC_FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
+#define MT7623_PIN_275_G2_MDC_FUNC_MDC (MTK_PIN_NO(275) | 1)
+
+#define MT7623_PIN_276_G2_MDIO_FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
+#define MT7623_PIN_276_G2_MDIO_FUNC_MDIO (MTK_PIN_NO(276) | 1)
+
+#define MT7623_PIN_278_JTAG_RESET_FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
+#define MT7623_PIN_278_JTAG_RESET_FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
+
+#endif /* __DTS_MT7623_PINFUNC_H */
diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/stm32f429-pinfunc.h b/sys/gnu/dts/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
new file mode 100644
index 000000000000..26f18798d949
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
@@ -0,0 +1,1239 @@
+#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H
+#define _DT_BINDINGS_STM32F429_PINFUNC_H
+
+#define STM32F429_PA0_FUNC_GPIO 0x0
+#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
+#define STM32F429_PA0_FUNC_TIM5_CH1 0x3
+#define STM32F429_PA0_FUNC_TIM8_ETR 0x4
+#define STM32F429_PA0_FUNC_USART2_CTS 0x8
+#define STM32F429_PA0_FUNC_UART4_TX 0x9
+#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc
+#define STM32F429_PA0_FUNC_EVENTOUT 0x10
+#define STM32F429_PA0_FUNC_ANALOG 0x11
+
+#define STM32F429_PA1_FUNC_GPIO 0x100
+#define STM32F429_PA1_FUNC_TIM2_CH2 0x102
+#define STM32F429_PA1_FUNC_TIM5_CH2 0x103
+#define STM32F429_PA1_FUNC_USART2_RTS 0x108
+#define STM32F429_PA1_FUNC_UART4_RX 0x109
+#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c
+#define STM32F429_PA1_FUNC_EVENTOUT 0x110
+#define STM32F429_PA1_FUNC_ANALOG 0x111
+
+#define STM32F429_PA2_FUNC_GPIO 0x200
+#define STM32F429_PA2_FUNC_TIM2_CH3 0x202
+#define STM32F429_PA2_FUNC_TIM5_CH3 0x203
+#define STM32F429_PA2_FUNC_TIM9_CH1 0x204
+#define STM32F429_PA2_FUNC_USART2_TX 0x208
+#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c
+#define STM32F429_PA2_FUNC_EVENTOUT 0x210
+#define STM32F429_PA2_FUNC_ANALOG 0x211
+
+#define STM32F429_PA3_FUNC_GPIO 0x300
+#define STM32F429_PA3_FUNC_TIM2_CH4 0x302
+#define STM32F429_PA3_FUNC_TIM5_CH4 0x303
+#define STM32F429_PA3_FUNC_TIM9_CH2 0x304
+#define STM32F429_PA3_FUNC_USART2_RX 0x308
+#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b
+#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c
+#define STM32F429_PA3_FUNC_LCD_B5 0x30f
+#define STM32F429_PA3_FUNC_EVENTOUT 0x310
+#define STM32F429_PA3_FUNC_ANALOG 0x311
+
+#define STM32F429_PA4_FUNC_GPIO 0x400
+#define STM32F429_PA4_FUNC_SPI1_NSS 0x406
+#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407
+#define STM32F429_PA4_FUNC_USART2_CK 0x408
+#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d
+#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e
+#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f
+#define STM32F429_PA4_FUNC_EVENTOUT 0x410
+#define STM32F429_PA4_FUNC_ANALOG 0x411
+
+#define STM32F429_PA5_FUNC_GPIO 0x500
+#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502
+#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504
+#define STM32F429_PA5_FUNC_SPI1_SCK 0x506
+#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b
+#define STM32F429_PA5_FUNC_EVENTOUT 0x510
+#define STM32F429_PA5_FUNC_ANALOG 0x511
+
+#define STM32F429_PA6_FUNC_GPIO 0x600
+#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602
+#define STM32F429_PA6_FUNC_TIM3_CH1 0x603
+#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604
+#define STM32F429_PA6_FUNC_SPI1_MISO 0x606
+#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a
+#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e
+#define STM32F429_PA6_FUNC_LCD_G2 0x60f
+#define STM32F429_PA6_FUNC_EVENTOUT 0x610
+#define STM32F429_PA6_FUNC_ANALOG 0x611
+
+#define STM32F429_PA7_FUNC_GPIO 0x700
+#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702
+#define STM32F429_PA7_FUNC_TIM3_CH2 0x703
+#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704
+#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706
+#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a
+#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c
+#define STM32F429_PA7_FUNC_EVENTOUT 0x710
+#define STM32F429_PA7_FUNC_ANALOG 0x711
+
+#define STM32F429_PA8_FUNC_GPIO 0x800
+#define STM32F429_PA8_FUNC_MCO1 0x801
+#define STM32F429_PA8_FUNC_TIM1_CH1 0x802
+#define STM32F429_PA8_FUNC_I2C3_SCL 0x805
+#define STM32F429_PA8_FUNC_USART1_CK 0x808
+#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b
+#define STM32F429_PA8_FUNC_LCD_R6 0x80f
+#define STM32F429_PA8_FUNC_EVENTOUT 0x810
+#define STM32F429_PA8_FUNC_ANALOG 0x811
+
+#define STM32F429_PA9_FUNC_GPIO 0x900
+#define STM32F429_PA9_FUNC_TIM1_CH2 0x902
+#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905
+#define STM32F429_PA9_FUNC_USART1_TX 0x908
+#define STM32F429_PA9_FUNC_DCMI_D0 0x90e
+#define STM32F429_PA9_FUNC_EVENTOUT 0x910
+#define STM32F429_PA9_FUNC_ANALOG 0x911
+
+#define STM32F429_PA10_FUNC_GPIO 0xa00
+#define STM32F429_PA10_FUNC_TIM1_CH3 0xa02
+#define STM32F429_PA10_FUNC_USART1_RX 0xa08
+#define STM32F429_PA10_FUNC_OTG_FS_ID 0xa0b
+#define STM32F429_PA10_FUNC_DCMI_D1 0xa0e
+#define STM32F429_PA10_FUNC_EVENTOUT 0xa10
+#define STM32F429_PA10_FUNC_ANALOG 0xa11
+
+#define STM32F429_PA11_FUNC_GPIO 0xb00
+#define STM32F429_PA11_FUNC_TIM1_CH4 0xb02
+#define STM32F429_PA11_FUNC_USART1_CTS 0xb08
+#define STM32F429_PA11_FUNC_CAN1_RX 0xb0a
+#define STM32F429_PA11_FUNC_OTG_FS_DM 0xb0b
+#define STM32F429_PA11_FUNC_LCD_R4 0xb0f
+#define STM32F429_PA11_FUNC_EVENTOUT 0xb10
+#define STM32F429_PA11_FUNC_ANALOG 0xb11
+
+#define STM32F429_PA12_FUNC_GPIO 0xc00
+#define STM32F429_PA12_FUNC_TIM1_ETR 0xc02
+#define STM32F429_PA12_FUNC_USART1_RTS 0xc08
+#define STM32F429_PA12_FUNC_CAN1_TX 0xc0a
+#define STM32F429_PA12_FUNC_OTG_FS_DP 0xc0b
+#define STM32F429_PA12_FUNC_LCD_R5 0xc0f
+#define STM32F429_PA12_FUNC_EVENTOUT 0xc10
+#define STM32F429_PA12_FUNC_ANALOG 0xc11
+
+#define STM32F429_PA13_FUNC_GPIO 0xd00
+#define STM32F429_PA13_FUNC_JTMS_SWDIO 0xd01
+#define STM32F429_PA13_FUNC_EVENTOUT 0xd10
+#define STM32F429_PA13_FUNC_ANALOG 0xd11
+
+#define STM32F429_PA14_FUNC_GPIO 0xe00
+#define STM32F429_PA14_FUNC_JTCK_SWCLK 0xe01
+#define STM32F429_PA14_FUNC_EVENTOUT 0xe10
+#define STM32F429_PA14_FUNC_ANALOG 0xe11
+
+#define STM32F429_PA15_FUNC_GPIO 0xf00
+#define STM32F429_PA15_FUNC_JTDI 0xf01
+#define STM32F429_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02
+#define STM32F429_PA15_FUNC_SPI1_NSS 0xf06
+#define STM32F429_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07
+#define STM32F429_PA15_FUNC_EVENTOUT 0xf10
+#define STM32F429_PA15_FUNC_ANALOG 0xf11
+
+
+
+#define STM32F429_PB0_FUNC_GPIO 0x1000
+#define STM32F429_PB0_FUNC_TIM1_CH2N 0x1002
+#define STM32F429_PB0_FUNC_TIM3_CH3 0x1003
+#define STM32F429_PB0_FUNC_TIM8_CH2N 0x1004
+#define STM32F429_PB0_FUNC_LCD_R3 0x100a
+#define STM32F429_PB0_FUNC_OTG_HS_ULPI_D1 0x100b
+#define STM32F429_PB0_FUNC_ETH_MII_RXD2 0x100c
+#define STM32F429_PB0_FUNC_EVENTOUT 0x1010
+#define STM32F429_PB0_FUNC_ANALOG 0x1011
+
+#define STM32F429_PB1_FUNC_GPIO 0x1100
+#define STM32F429_PB1_FUNC_TIM1_CH3N 0x1102
+#define STM32F429_PB1_FUNC_TIM3_CH4 0x1103
+#define STM32F429_PB1_FUNC_TIM8_CH3N 0x1104
+#define STM32F429_PB1_FUNC_LCD_R6 0x110a
+#define STM32F429_PB1_FUNC_OTG_HS_ULPI_D2 0x110b
+#define STM32F429_PB1_FUNC_ETH_MII_RXD3 0x110c
+#define STM32F429_PB1_FUNC_EVENTOUT 0x1110
+#define STM32F429_PB1_FUNC_ANALOG 0x1111
+
+#define STM32F429_PB2_FUNC_GPIO 0x1200
+#define STM32F429_PB2_FUNC_EVENTOUT 0x1210
+#define STM32F429_PB2_FUNC_ANALOG 0x1211
+
+#define STM32F429_PB3_FUNC_GPIO 0x1300
+#define STM32F429_PB3_FUNC_JTDO_TRACESWO 0x1301
+#define STM32F429_PB3_FUNC_TIM2_CH2 0x1302
+#define STM32F429_PB3_FUNC_SPI1_SCK 0x1306
+#define STM32F429_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
+#define STM32F429_PB3_FUNC_EVENTOUT 0x1310
+#define STM32F429_PB3_FUNC_ANALOG 0x1311
+
+#define STM32F429_PB4_FUNC_GPIO 0x1400
+#define STM32F429_PB4_FUNC_NJTRST 0x1401
+#define STM32F429_PB4_FUNC_TIM3_CH1 0x1403
+#define STM32F429_PB4_FUNC_SPI1_MISO 0x1406
+#define STM32F429_PB4_FUNC_SPI3_MISO 0x1407
+#define STM32F429_PB4_FUNC_I2S3EXT_SD 0x1408
+#define STM32F429_PB4_FUNC_EVENTOUT 0x1410
+#define STM32F429_PB4_FUNC_ANALOG 0x1411
+
+#define STM32F429_PB5_FUNC_GPIO 0x1500
+#define STM32F429_PB5_FUNC_TIM3_CH2 0x1503
+#define STM32F429_PB5_FUNC_I2C1_SMBA 0x1505
+#define STM32F429_PB5_FUNC_SPI1_MOSI 0x1506
+#define STM32F429_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507
+#define STM32F429_PB5_FUNC_CAN2_RX 0x150a
+#define STM32F429_PB5_FUNC_OTG_HS_ULPI_D7 0x150b
+#define STM32F429_PB5_FUNC_ETH_PPS_OUT 0x150c
+#define STM32F429_PB5_FUNC_FMC_SDCKE1 0x150d
+#define STM32F429_PB5_FUNC_DCMI_D10 0x150e
+#define STM32F429_PB5_FUNC_EVENTOUT 0x1510
+#define STM32F429_PB5_FUNC_ANALOG 0x1511
+
+#define STM32F429_PB6_FUNC_GPIO 0x1600
+#define STM32F429_PB6_FUNC_TIM4_CH1 0x1603
+#define STM32F429_PB6_FUNC_I2C1_SCL 0x1605
+#define STM32F429_PB6_FUNC_USART1_TX 0x1608
+#define STM32F429_PB6_FUNC_CAN2_TX 0x160a
+#define STM32F429_PB6_FUNC_FMC_SDNE1 0x160d
+#define STM32F429_PB6_FUNC_DCMI_D5 0x160e
+#define STM32F429_PB6_FUNC_EVENTOUT 0x1610
+#define STM32F429_PB6_FUNC_ANALOG 0x1611
+
+#define STM32F429_PB7_FUNC_GPIO 0x1700
+#define STM32F429_PB7_FUNC_TIM4_CH2 0x1703
+#define STM32F429_PB7_FUNC_I2C1_SDA 0x1705
+#define STM32F429_PB7_FUNC_USART1_RX 0x1708
+#define STM32F429_PB7_FUNC_FMC_NL 0x170d
+#define STM32F429_PB7_FUNC_DCMI_VSYNC 0x170e
+#define STM32F429_PB7_FUNC_EVENTOUT 0x1710
+#define STM32F429_PB7_FUNC_ANALOG 0x1711
+
+#define STM32F429_PB8_FUNC_GPIO 0x1800
+#define STM32F429_PB8_FUNC_TIM4_CH3 0x1803
+#define STM32F429_PB8_FUNC_TIM10_CH1 0x1804
+#define STM32F429_PB8_FUNC_I2C1_SCL 0x1805
+#define STM32F429_PB8_FUNC_CAN1_RX 0x180a
+#define STM32F429_PB8_FUNC_ETH_MII_TXD3 0x180c
+#define STM32F429_PB8_FUNC_SDIO_D4 0x180d
+#define STM32F429_PB8_FUNC_DCMI_D6 0x180e
+#define STM32F429_PB8_FUNC_LCD_B6 0x180f
+#define STM32F429_PB8_FUNC_EVENTOUT 0x1810
+#define STM32F429_PB8_FUNC_ANALOG 0x1811
+
+#define STM32F429_PB9_FUNC_GPIO 0x1900
+#define STM32F429_PB9_FUNC_TIM4_CH4 0x1903
+#define STM32F429_PB9_FUNC_TIM11_CH1 0x1904
+#define STM32F429_PB9_FUNC_I2C1_SDA 0x1905
+#define STM32F429_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906
+#define STM32F429_PB9_FUNC_CAN1_TX 0x190a
+#define STM32F429_PB9_FUNC_SDIO_D5 0x190d
+#define STM32F429_PB9_FUNC_DCMI_D7 0x190e
+#define STM32F429_PB9_FUNC_LCD_B7 0x190f
+#define STM32F429_PB9_FUNC_EVENTOUT 0x1910
+#define STM32F429_PB9_FUNC_ANALOG 0x1911
+
+#define STM32F429_PB10_FUNC_GPIO 0x1a00
+#define STM32F429_PB10_FUNC_TIM2_CH3 0x1a02
+#define STM32F429_PB10_FUNC_I2C2_SCL 0x1a05
+#define STM32F429_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06
+#define STM32F429_PB10_FUNC_USART3_TX 0x1a08
+#define STM32F429_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b
+#define STM32F429_PB10_FUNC_ETH_MII_RX_ER 0x1a0c
+#define STM32F429_PB10_FUNC_LCD_G4 0x1a0f
+#define STM32F429_PB10_FUNC_EVENTOUT 0x1a10
+#define STM32F429_PB10_FUNC_ANALOG 0x1a11
+
+#define STM32F429_PB11_FUNC_GPIO 0x1b00
+#define STM32F429_PB11_FUNC_TIM2_CH4 0x1b02
+#define STM32F429_PB11_FUNC_I2C2_SDA 0x1b05
+#define STM32F429_PB11_FUNC_USART3_RX 0x1b08
+#define STM32F429_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b
+#define STM32F429_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c
+#define STM32F429_PB11_FUNC_LCD_G5 0x1b0f
+#define STM32F429_PB11_FUNC_EVENTOUT 0x1b10
+#define STM32F429_PB11_FUNC_ANALOG 0x1b11
+
+#define STM32F429_PB12_FUNC_GPIO 0x1c00
+#define STM32F429_PB12_FUNC_TIM1_BKIN 0x1c02
+#define STM32F429_PB12_FUNC_I2C2_SMBA 0x1c05
+#define STM32F429_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06
+#define STM32F429_PB12_FUNC_USART3_CK 0x1c08
+#define STM32F429_PB12_FUNC_CAN2_RX 0x1c0a
+#define STM32F429_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b
+#define STM32F429_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c
+#define STM32F429_PB12_FUNC_OTG_HS_ID 0x1c0d
+#define STM32F429_PB12_FUNC_EVENTOUT 0x1c10
+#define STM32F429_PB12_FUNC_ANALOG 0x1c11
+
+#define STM32F429_PB13_FUNC_GPIO 0x1d00
+#define STM32F429_PB13_FUNC_TIM1_CH1N 0x1d02
+#define STM32F429_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06
+#define STM32F429_PB13_FUNC_USART3_CTS 0x1d08
+#define STM32F429_PB13_FUNC_CAN2_TX 0x1d0a
+#define STM32F429_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b
+#define STM32F429_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c
+#define STM32F429_PB13_FUNC_EVENTOUT 0x1d10
+#define STM32F429_PB13_FUNC_ANALOG 0x1d11
+
+#define STM32F429_PB14_FUNC_GPIO 0x1e00
+#define STM32F429_PB14_FUNC_TIM1_CH2N 0x1e02
+#define STM32F429_PB14_FUNC_TIM8_CH2N 0x1e04
+#define STM32F429_PB14_FUNC_SPI2_MISO 0x1e06
+#define STM32F429_PB14_FUNC_I2S2EXT_SD 0x1e07
+#define STM32F429_PB14_FUNC_USART3_RTS 0x1e08
+#define STM32F429_PB14_FUNC_TIM12_CH1 0x1e0a
+#define STM32F429_PB14_FUNC_OTG_HS_DM 0x1e0d
+#define STM32F429_PB14_FUNC_EVENTOUT 0x1e10
+#define STM32F429_PB14_FUNC_ANALOG 0x1e11
+
+#define STM32F429_PB15_FUNC_GPIO 0x1f00
+#define STM32F429_PB15_FUNC_RTC_REFIN 0x1f01
+#define STM32F429_PB15_FUNC_TIM1_CH3N 0x1f02
+#define STM32F429_PB15_FUNC_TIM8_CH3N 0x1f04
+#define STM32F429_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06
+#define STM32F429_PB15_FUNC_TIM12_CH2 0x1f0a
+#define STM32F429_PB15_FUNC_OTG_HS_DP 0x1f0d
+#define STM32F429_PB15_FUNC_EVENTOUT 0x1f10
+#define STM32F429_PB15_FUNC_ANALOG 0x1f11
+
+
+
+#define STM32F429_PC0_FUNC_GPIO 0x2000
+#define STM32F429_PC0_FUNC_OTG_HS_ULPI_STP 0x200b
+#define STM32F429_PC0_FUNC_FMC_SDNWE 0x200d
+#define STM32F429_PC0_FUNC_EVENTOUT 0x2010
+#define STM32F429_PC0_FUNC_ANALOG 0x2011
+
+#define STM32F429_PC1_FUNC_GPIO 0x2100
+#define STM32F429_PC1_FUNC_ETH_MDC 0x210c
+#define STM32F429_PC1_FUNC_EVENTOUT 0x2110
+#define STM32F429_PC1_FUNC_ANALOG 0x2111
+
+#define STM32F429_PC2_FUNC_GPIO 0x2200
+#define STM32F429_PC2_FUNC_SPI2_MISO 0x2206
+#define STM32F429_PC2_FUNC_I2S2EXT_SD 0x2207
+#define STM32F429_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b
+#define STM32F429_PC2_FUNC_ETH_MII_TXD2 0x220c
+#define STM32F429_PC2_FUNC_FMC_SDNE0 0x220d
+#define STM32F429_PC2_FUNC_EVENTOUT 0x2210
+#define STM32F429_PC2_FUNC_ANALOG 0x2211
+
+#define STM32F429_PC3_FUNC_GPIO 0x2300
+#define STM32F429_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306
+#define STM32F429_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b
+#define STM32F429_PC3_FUNC_ETH_MII_TX_CLK 0x230c
+#define STM32F429_PC3_FUNC_FMC_SDCKE0 0x230d
+#define STM32F429_PC3_FUNC_EVENTOUT 0x2310
+#define STM32F429_PC3_FUNC_ANALOG 0x2311
+
+#define STM32F429_PC4_FUNC_GPIO 0x2400
+#define STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c
+#define STM32F429_PC4_FUNC_EVENTOUT 0x2410
+#define STM32F429_PC4_FUNC_ANALOG 0x2411
+
+#define STM32F429_PC5_FUNC_GPIO 0x2500
+#define STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c
+#define STM32F429_PC5_FUNC_EVENTOUT 0x2510
+#define STM32F429_PC5_FUNC_ANALOG 0x2511
+
+#define STM32F429_PC6_FUNC_GPIO 0x2600
+#define STM32F429_PC6_FUNC_TIM3_CH1 0x2603
+#define STM32F429_PC6_FUNC_TIM8_CH1 0x2604
+#define STM32F429_PC6_FUNC_I2S2_MCK 0x2606
+#define STM32F429_PC6_FUNC_USART6_TX 0x2609
+#define STM32F429_PC6_FUNC_SDIO_D6 0x260d
+#define STM32F429_PC6_FUNC_DCMI_D0 0x260e
+#define STM32F429_PC6_FUNC_LCD_HSYNC 0x260f
+#define STM32F429_PC6_FUNC_EVENTOUT 0x2610
+#define STM32F429_PC6_FUNC_ANALOG 0x2611
+
+#define STM32F429_PC7_FUNC_GPIO 0x2700
+#define STM32F429_PC7_FUNC_TIM3_CH2 0x2703
+#define STM32F429_PC7_FUNC_TIM8_CH2 0x2704
+#define STM32F429_PC7_FUNC_I2S3_MCK 0x2707
+#define STM32F429_PC7_FUNC_USART6_RX 0x2709
+#define STM32F429_PC7_FUNC_SDIO_D7 0x270d
+#define STM32F429_PC7_FUNC_DCMI_D1 0x270e
+#define STM32F429_PC7_FUNC_LCD_G6 0x270f
+#define STM32F429_PC7_FUNC_EVENTOUT 0x2710
+#define STM32F429_PC7_FUNC_ANALOG 0x2711
+
+#define STM32F429_PC8_FUNC_GPIO 0x2800
+#define STM32F429_PC8_FUNC_TIM3_CH3 0x2803
+#define STM32F429_PC8_FUNC_TIM8_CH3 0x2804
+#define STM32F429_PC8_FUNC_USART6_CK 0x2809
+#define STM32F429_PC8_FUNC_SDIO_D0 0x280d
+#define STM32F429_PC8_FUNC_DCMI_D2 0x280e
+#define STM32F429_PC8_FUNC_EVENTOUT 0x2810
+#define STM32F429_PC8_FUNC_ANALOG 0x2811
+
+#define STM32F429_PC9_FUNC_GPIO 0x2900
+#define STM32F429_PC9_FUNC_MCO2 0x2901
+#define STM32F429_PC9_FUNC_TIM3_CH4 0x2903
+#define STM32F429_PC9_FUNC_TIM8_CH4 0x2904
+#define STM32F429_PC9_FUNC_I2C3_SDA 0x2905
+#define STM32F429_PC9_FUNC_I2S_CKIN 0x2906
+#define STM32F429_PC9_FUNC_SDIO_D1 0x290d
+#define STM32F429_PC9_FUNC_DCMI_D3 0x290e
+#define STM32F429_PC9_FUNC_EVENTOUT 0x2910
+#define STM32F429_PC9_FUNC_ANALOG 0x2911
+
+#define STM32F429_PC10_FUNC_GPIO 0x2a00
+#define STM32F429_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07
+#define STM32F429_PC10_FUNC_USART3_TX 0x2a08
+#define STM32F429_PC10_FUNC_UART4_TX 0x2a09
+#define STM32F429_PC10_FUNC_SDIO_D2 0x2a0d
+#define STM32F429_PC10_FUNC_DCMI_D8 0x2a0e
+#define STM32F429_PC10_FUNC_LCD_R2 0x2a0f
+#define STM32F429_PC10_FUNC_EVENTOUT 0x2a10
+#define STM32F429_PC10_FUNC_ANALOG 0x2a11
+
+#define STM32F429_PC11_FUNC_GPIO 0x2b00
+#define STM32F429_PC11_FUNC_I2S3EXT_SD 0x2b06
+#define STM32F429_PC11_FUNC_SPI3_MISO 0x2b07
+#define STM32F429_PC11_FUNC_USART3_RX 0x2b08
+#define STM32F429_PC11_FUNC_UART4_RX 0x2b09
+#define STM32F429_PC11_FUNC_SDIO_D3 0x2b0d
+#define STM32F429_PC11_FUNC_DCMI_D4 0x2b0e
+#define STM32F429_PC11_FUNC_EVENTOUT 0x2b10
+#define STM32F429_PC11_FUNC_ANALOG 0x2b11
+
+#define STM32F429_PC12_FUNC_GPIO 0x2c00
+#define STM32F429_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07
+#define STM32F429_PC12_FUNC_USART3_CK 0x2c08
+#define STM32F429_PC12_FUNC_UART5_TX 0x2c09
+#define STM32F429_PC12_FUNC_SDIO_CK 0x2c0d
+#define STM32F429_PC12_FUNC_DCMI_D9 0x2c0e
+#define STM32F429_PC12_FUNC_EVENTOUT 0x2c10
+#define STM32F429_PC12_FUNC_ANALOG 0x2c11
+
+#define STM32F429_PC13_FUNC_GPIO 0x2d00
+#define STM32F429_PC13_FUNC_EVENTOUT 0x2d10
+#define STM32F429_PC13_FUNC_ANALOG 0x2d11
+
+#define STM32F429_PC14_FUNC_GPIO 0x2e00
+#define STM32F429_PC14_FUNC_EVENTOUT 0x2e10
+#define STM32F429_PC14_FUNC_ANALOG 0x2e11
+
+#define STM32F429_PC15_FUNC_GPIO 0x2f00
+#define STM32F429_PC15_FUNC_EVENTOUT 0x2f10
+#define STM32F429_PC15_FUNC_ANALOG 0x2f11
+
+
+
+#define STM32F429_PD0_FUNC_GPIO 0x3000
+#define STM32F429_PD0_FUNC_CAN1_RX 0x300a
+#define STM32F429_PD0_FUNC_FMC_D2 0x300d
+#define STM32F429_PD0_FUNC_EVENTOUT 0x3010
+#define STM32F429_PD0_FUNC_ANALOG 0x3011
+
+#define STM32F429_PD1_FUNC_GPIO 0x3100
+#define STM32F429_PD1_FUNC_CAN1_TX 0x310a
+#define STM32F429_PD1_FUNC_FMC_D3 0x310d
+#define STM32F429_PD1_FUNC_EVENTOUT 0x3110
+#define STM32F429_PD1_FUNC_ANALOG 0x3111
+
+#define STM32F429_PD2_FUNC_GPIO 0x3200
+#define STM32F429_PD2_FUNC_TIM3_ETR 0x3203
+#define STM32F429_PD2_FUNC_UART5_RX 0x3209
+#define STM32F429_PD2_FUNC_SDIO_CMD 0x320d
+#define STM32F429_PD2_FUNC_DCMI_D11 0x320e
+#define STM32F429_PD2_FUNC_EVENTOUT 0x3210
+#define STM32F429_PD2_FUNC_ANALOG 0x3211
+
+#define STM32F429_PD3_FUNC_GPIO 0x3300
+#define STM32F429_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306
+#define STM32F429_PD3_FUNC_USART2_CTS 0x3308
+#define STM32F429_PD3_FUNC_FMC_CLK 0x330d
+#define STM32F429_PD3_FUNC_DCMI_D5 0x330e
+#define STM32F429_PD3_FUNC_LCD_G7 0x330f
+#define STM32F429_PD3_FUNC_EVENTOUT 0x3310
+#define STM32F429_PD3_FUNC_ANALOG 0x3311
+
+#define STM32F429_PD4_FUNC_GPIO 0x3400
+#define STM32F429_PD4_FUNC_USART2_RTS 0x3408
+#define STM32F429_PD4_FUNC_FMC_NOE 0x340d
+#define STM32F429_PD4_FUNC_EVENTOUT 0x3410
+#define STM32F429_PD4_FUNC_ANALOG 0x3411
+
+#define STM32F429_PD5_FUNC_GPIO 0x3500
+#define STM32F429_PD5_FUNC_USART2_TX 0x3508
+#define STM32F429_PD5_FUNC_FMC_NWE 0x350d
+#define STM32F429_PD5_FUNC_EVENTOUT 0x3510
+#define STM32F429_PD5_FUNC_ANALOG 0x3511
+
+#define STM32F429_PD6_FUNC_GPIO 0x3600
+#define STM32F429_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606
+#define STM32F429_PD6_FUNC_SAI1_SD_A 0x3607
+#define STM32F429_PD6_FUNC_USART2_RX 0x3608
+#define STM32F429_PD6_FUNC_FMC_NWAIT 0x360d
+#define STM32F429_PD6_FUNC_DCMI_D10 0x360e
+#define STM32F429_PD6_FUNC_LCD_B2 0x360f
+#define STM32F429_PD6_FUNC_EVENTOUT 0x3610
+#define STM32F429_PD6_FUNC_ANALOG 0x3611
+
+#define STM32F429_PD7_FUNC_GPIO 0x3700
+#define STM32F429_PD7_FUNC_USART2_CK 0x3708
+#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d
+#define STM32F429_PD7_FUNC_EVENTOUT 0x3710
+#define STM32F429_PD7_FUNC_ANALOG 0x3711
+
+#define STM32F429_PD8_FUNC_GPIO 0x3800
+#define STM32F429_PD8_FUNC_USART3_TX 0x3808
+#define STM32F429_PD8_FUNC_FMC_D13 0x380d
+#define STM32F429_PD8_FUNC_EVENTOUT 0x3810
+#define STM32F429_PD8_FUNC_ANALOG 0x3811
+
+#define STM32F429_PD9_FUNC_GPIO 0x3900
+#define STM32F429_PD9_FUNC_USART3_RX 0x3908
+#define STM32F429_PD9_FUNC_FMC_D14 0x390d
+#define STM32F429_PD9_FUNC_EVENTOUT 0x3910
+#define STM32F429_PD9_FUNC_ANALOG 0x3911
+
+#define STM32F429_PD10_FUNC_GPIO 0x3a00
+#define STM32F429_PD10_FUNC_USART3_CK 0x3a08
+#define STM32F429_PD10_FUNC_FMC_D15 0x3a0d
+#define STM32F429_PD10_FUNC_LCD_B3 0x3a0f
+#define STM32F429_PD10_FUNC_EVENTOUT 0x3a10
+#define STM32F429_PD10_FUNC_ANALOG 0x3a11
+
+#define STM32F429_PD11_FUNC_GPIO 0x3b00
+#define STM32F429_PD11_FUNC_USART3_CTS 0x3b08
+#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d
+#define STM32F429_PD11_FUNC_EVENTOUT 0x3b10
+#define STM32F429_PD11_FUNC_ANALOG 0x3b11
+
+#define STM32F429_PD12_FUNC_GPIO 0x3c00
+#define STM32F429_PD12_FUNC_TIM4_CH1 0x3c03
+#define STM32F429_PD12_FUNC_USART3_RTS 0x3c08
+#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d
+#define STM32F429_PD12_FUNC_EVENTOUT 0x3c10
+#define STM32F429_PD12_FUNC_ANALOG 0x3c11
+
+#define STM32F429_PD13_FUNC_GPIO 0x3d00
+#define STM32F429_PD13_FUNC_TIM4_CH2 0x3d03
+#define STM32F429_PD13_FUNC_FMC_A18 0x3d0d
+#define STM32F429_PD13_FUNC_EVENTOUT 0x3d10
+#define STM32F429_PD13_FUNC_ANALOG 0x3d11
+
+#define STM32F429_PD14_FUNC_GPIO 0x3e00
+#define STM32F429_PD14_FUNC_TIM4_CH3 0x3e03
+#define STM32F429_PD14_FUNC_FMC_D0 0x3e0d
+#define STM32F429_PD14_FUNC_EVENTOUT 0x3e10
+#define STM32F429_PD14_FUNC_ANALOG 0x3e11
+
+#define STM32F429_PD15_FUNC_GPIO 0x3f00
+#define STM32F429_PD15_FUNC_TIM4_CH4 0x3f03
+#define STM32F429_PD15_FUNC_FMC_D1 0x3f0d
+#define STM32F429_PD15_FUNC_EVENTOUT 0x3f10
+#define STM32F429_PD15_FUNC_ANALOG 0x3f11
+
+
+
+#define STM32F429_PE0_FUNC_GPIO 0x4000
+#define STM32F429_PE0_FUNC_TIM4_ETR 0x4003
+#define STM32F429_PE0_FUNC_UART8_RX 0x4009
+#define STM32F429_PE0_FUNC_FMC_NBL0 0x400d
+#define STM32F429_PE0_FUNC_DCMI_D2 0x400e
+#define STM32F429_PE0_FUNC_EVENTOUT 0x4010
+#define STM32F429_PE0_FUNC_ANALOG 0x4011
+
+#define STM32F429_PE1_FUNC_GPIO 0x4100
+#define STM32F429_PE1_FUNC_UART8_TX 0x4109
+#define STM32F429_PE1_FUNC_FMC_NBL1 0x410d
+#define STM32F429_PE1_FUNC_DCMI_D3 0x410e
+#define STM32F429_PE1_FUNC_EVENTOUT 0x4110
+#define STM32F429_PE1_FUNC_ANALOG 0x4111
+
+#define STM32F429_PE2_FUNC_GPIO 0x4200
+#define STM32F429_PE2_FUNC_TRACECLK 0x4201
+#define STM32F429_PE2_FUNC_SPI4_SCK 0x4206
+#define STM32F429_PE2_FUNC_SAI1_MCLK_A 0x4207
+#define STM32F429_PE2_FUNC_ETH_MII_TXD3 0x420c
+#define STM32F429_PE2_FUNC_FMC_A23 0x420d
+#define STM32F429_PE2_FUNC_EVENTOUT 0x4210
+#define STM32F429_PE2_FUNC_ANALOG 0x4211
+
+#define STM32F429_PE3_FUNC_GPIO 0x4300
+#define STM32F429_PE3_FUNC_TRACED0 0x4301
+#define STM32F429_PE3_FUNC_SAI1_SD_B 0x4307
+#define STM32F429_PE3_FUNC_FMC_A19 0x430d
+#define STM32F429_PE3_FUNC_EVENTOUT 0x4310
+#define STM32F429_PE3_FUNC_ANALOG 0x4311
+
+#define STM32F429_PE4_FUNC_GPIO 0x4400
+#define STM32F429_PE4_FUNC_TRACED1 0x4401
+#define STM32F429_PE4_FUNC_SPI4_NSS 0x4406
+#define STM32F429_PE4_FUNC_SAI1_FS_A 0x4407
+#define STM32F429_PE4_FUNC_FMC_A20 0x440d
+#define STM32F429_PE4_FUNC_DCMI_D4 0x440e
+#define STM32F429_PE4_FUNC_LCD_B0 0x440f
+#define STM32F429_PE4_FUNC_EVENTOUT 0x4410
+#define STM32F429_PE4_FUNC_ANALOG 0x4411
+
+#define STM32F429_PE5_FUNC_GPIO 0x4500
+#define STM32F429_PE5_FUNC_TRACED2 0x4501
+#define STM32F429_PE5_FUNC_TIM9_CH1 0x4504
+#define STM32F429_PE5_FUNC_SPI4_MISO 0x4506
+#define STM32F429_PE5_FUNC_SAI1_SCK_A 0x4507
+#define STM32F429_PE5_FUNC_FMC_A21 0x450d
+#define STM32F429_PE5_FUNC_DCMI_D6 0x450e
+#define STM32F429_PE5_FUNC_LCD_G0 0x450f
+#define STM32F429_PE5_FUNC_EVENTOUT 0x4510
+#define STM32F429_PE5_FUNC_ANALOG 0x4511
+
+#define STM32F429_PE6_FUNC_GPIO 0x4600
+#define STM32F429_PE6_FUNC_TRACED3 0x4601
+#define STM32F429_PE6_FUNC_TIM9_CH2 0x4604
+#define STM32F429_PE6_FUNC_SPI4_MOSI 0x4606
+#define STM32F429_PE6_FUNC_SAI1_SD_A 0x4607
+#define STM32F429_PE6_FUNC_FMC_A22 0x460d
+#define STM32F429_PE6_FUNC_DCMI_D7 0x460e
+#define STM32F429_PE6_FUNC_LCD_G1 0x460f
+#define STM32F429_PE6_FUNC_EVENTOUT 0x4610
+#define STM32F429_PE6_FUNC_ANALOG 0x4611
+
+#define STM32F429_PE7_FUNC_GPIO 0x4700
+#define STM32F429_PE7_FUNC_TIM1_ETR 0x4702
+#define STM32F429_PE7_FUNC_UART7_RX 0x4709
+#define STM32F429_PE7_FUNC_FMC_D4 0x470d
+#define STM32F429_PE7_FUNC_EVENTOUT 0x4710
+#define STM32F429_PE7_FUNC_ANALOG 0x4711
+
+#define STM32F429_PE8_FUNC_GPIO 0x4800
+#define STM32F429_PE8_FUNC_TIM1_CH1N 0x4802
+#define STM32F429_PE8_FUNC_UART7_TX 0x4809
+#define STM32F429_PE8_FUNC_FMC_D5 0x480d
+#define STM32F429_PE8_FUNC_EVENTOUT 0x4810
+#define STM32F429_PE8_FUNC_ANALOG 0x4811
+
+#define STM32F429_PE9_FUNC_GPIO 0x4900
+#define STM32F429_PE9_FUNC_TIM1_CH1 0x4902
+#define STM32F429_PE9_FUNC_FMC_D6 0x490d
+#define STM32F429_PE9_FUNC_EVENTOUT 0x4910
+#define STM32F429_PE9_FUNC_ANALOG 0x4911
+
+#define STM32F429_PE10_FUNC_GPIO 0x4a00
+#define STM32F429_PE10_FUNC_TIM1_CH2N 0x4a02
+#define STM32F429_PE10_FUNC_FMC_D7 0x4a0d
+#define STM32F429_PE10_FUNC_EVENTOUT 0x4a10
+#define STM32F429_PE10_FUNC_ANALOG 0x4a11
+
+#define STM32F429_PE11_FUNC_GPIO 0x4b00
+#define STM32F429_PE11_FUNC_TIM1_CH2 0x4b02
+#define STM32F429_PE11_FUNC_SPI4_NSS 0x4b06
+#define STM32F429_PE11_FUNC_FMC_D8 0x4b0d
+#define STM32F429_PE11_FUNC_LCD_G3 0x4b0f
+#define STM32F429_PE11_FUNC_EVENTOUT 0x4b10
+#define STM32F429_PE11_FUNC_ANALOG 0x4b11
+
+#define STM32F429_PE12_FUNC_GPIO 0x4c00
+#define STM32F429_PE12_FUNC_TIM1_CH3N 0x4c02
+#define STM32F429_PE12_FUNC_SPI4_SCK 0x4c06
+#define STM32F429_PE12_FUNC_FMC_D9 0x4c0d
+#define STM32F429_PE12_FUNC_LCD_B4 0x4c0f
+#define STM32F429_PE12_FUNC_EVENTOUT 0x4c10
+#define STM32F429_PE12_FUNC_ANALOG 0x4c11
+
+#define STM32F429_PE13_FUNC_GPIO 0x4d00
+#define STM32F429_PE13_FUNC_TIM1_CH3 0x4d02
+#define STM32F429_PE13_FUNC_SPI4_MISO 0x4d06
+#define STM32F429_PE13_FUNC_FMC_D10 0x4d0d
+#define STM32F429_PE13_FUNC_LCD_DE 0x4d0f
+#define STM32F429_PE13_FUNC_EVENTOUT 0x4d10
+#define STM32F429_PE13_FUNC_ANALOG 0x4d11
+
+#define STM32F429_PE14_FUNC_GPIO 0x4e00
+#define STM32F429_PE14_FUNC_TIM1_CH4 0x4e02
+#define STM32F429_PE14_FUNC_SPI4_MOSI 0x4e06
+#define STM32F429_PE14_FUNC_FMC_D11 0x4e0d
+#define STM32F429_PE14_FUNC_LCD_CLK 0x4e0f
+#define STM32F429_PE14_FUNC_EVENTOUT 0x4e10
+#define STM32F429_PE14_FUNC_ANALOG 0x4e11
+
+#define STM32F429_PE15_FUNC_GPIO 0x4f00
+#define STM32F429_PE15_FUNC_TIM1_BKIN 0x4f02
+#define STM32F429_PE15_FUNC_FMC_D12 0x4f0d
+#define STM32F429_PE15_FUNC_LCD_R7 0x4f0f
+#define STM32F429_PE15_FUNC_EVENTOUT 0x4f10
+#define STM32F429_PE15_FUNC_ANALOG 0x4f11
+
+
+
+#define STM32F429_PF0_FUNC_GPIO 0x5000
+#define STM32F429_PF0_FUNC_I2C2_SDA 0x5005
+#define STM32F429_PF0_FUNC_FMC_A0 0x500d
+#define STM32F429_PF0_FUNC_EVENTOUT 0x5010
+#define STM32F429_PF0_FUNC_ANALOG 0x5011
+
+#define STM32F429_PF1_FUNC_GPIO 0x5100
+#define STM32F429_PF1_FUNC_I2C2_SCL 0x5105
+#define STM32F429_PF1_FUNC_FMC_A1 0x510d
+#define STM32F429_PF1_FUNC_EVENTOUT 0x5110
+#define STM32F429_PF1_FUNC_ANALOG 0x5111
+
+#define STM32F429_PF2_FUNC_GPIO 0x5200
+#define STM32F429_PF2_FUNC_I2C2_SMBA 0x5205
+#define STM32F429_PF2_FUNC_FMC_A2 0x520d
+#define STM32F429_PF2_FUNC_EVENTOUT 0x5210
+#define STM32F429_PF2_FUNC_ANALOG 0x5211
+
+#define STM32F429_PF3_FUNC_GPIO 0x5300
+#define STM32F429_PF3_FUNC_FMC_A3 0x530d
+#define STM32F429_PF3_FUNC_EVENTOUT 0x5310
+#define STM32F429_PF3_FUNC_ANALOG 0x5311
+
+#define STM32F429_PF4_FUNC_GPIO 0x5400
+#define STM32F429_PF4_FUNC_FMC_A4 0x540d
+#define STM32F429_PF4_FUNC_EVENTOUT 0x5410
+#define STM32F429_PF4_FUNC_ANALOG 0x5411
+
+#define STM32F429_PF5_FUNC_GPIO 0x5500
+#define STM32F429_PF5_FUNC_FMC_A5 0x550d
+#define STM32F429_PF5_FUNC_EVENTOUT 0x5510
+#define STM32F429_PF5_FUNC_ANALOG 0x5511
+
+#define STM32F429_PF6_FUNC_GPIO 0x5600
+#define STM32F429_PF6_FUNC_TIM10_CH1 0x5604
+#define STM32F429_PF6_FUNC_SPI5_NSS 0x5606
+#define STM32F429_PF6_FUNC_SAI1_SD_B 0x5607
+#define STM32F429_PF6_FUNC_UART7_RX 0x5609
+#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d
+#define STM32F429_PF6_FUNC_EVENTOUT 0x5610
+#define STM32F429_PF6_FUNC_ANALOG 0x5611
+
+#define STM32F429_PF7_FUNC_GPIO 0x5700
+#define STM32F429_PF7_FUNC_TIM11_CH1 0x5704
+#define STM32F429_PF7_FUNC_SPI5_SCK 0x5706
+#define STM32F429_PF7_FUNC_SAI1_MCLK_B 0x5707
+#define STM32F429_PF7_FUNC_UART7_TX 0x5709
+#define STM32F429_PF7_FUNC_FMC_NREG 0x570d
+#define STM32F429_PF7_FUNC_EVENTOUT 0x5710
+#define STM32F429_PF7_FUNC_ANALOG 0x5711
+
+#define STM32F429_PF8_FUNC_GPIO 0x5800
+#define STM32F429_PF8_FUNC_SPI5_MISO 0x5806
+#define STM32F429_PF8_FUNC_SAI1_SCK_B 0x5807
+#define STM32F429_PF8_FUNC_TIM13_CH1 0x580a
+#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d
+#define STM32F429_PF8_FUNC_EVENTOUT 0x5810
+#define STM32F429_PF8_FUNC_ANALOG 0x5811
+
+#define STM32F429_PF9_FUNC_GPIO 0x5900
+#define STM32F429_PF9_FUNC_SPI5_MOSI 0x5906
+#define STM32F429_PF9_FUNC_SAI1_FS_B 0x5907
+#define STM32F429_PF9_FUNC_TIM14_CH1 0x590a
+#define STM32F429_PF9_FUNC_FMC_CD 0x590d
+#define STM32F429_PF9_FUNC_EVENTOUT 0x5910
+#define STM32F429_PF9_FUNC_ANALOG 0x5911
+
+#define STM32F429_PF10_FUNC_GPIO 0x5a00
+#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d
+#define STM32F429_PF10_FUNC_DCMI_D11 0x5a0e
+#define STM32F429_PF10_FUNC_LCD_DE 0x5a0f
+#define STM32F429_PF10_FUNC_EVENTOUT 0x5a10
+#define STM32F429_PF10_FUNC_ANALOG 0x5a11
+
+#define STM32F429_PF11_FUNC_GPIO 0x5b00
+#define STM32F429_PF11_FUNC_SPI5_MOSI 0x5b06
+#define STM32F429_PF11_FUNC_FMC_SDNRAS 0x5b0d
+#define STM32F429_PF11_FUNC_DCMI_D12 0x5b0e
+#define STM32F429_PF11_FUNC_EVENTOUT 0x5b10
+#define STM32F429_PF11_FUNC_ANALOG 0x5b11
+
+#define STM32F429_PF12_FUNC_GPIO 0x5c00
+#define STM32F429_PF12_FUNC_FMC_A6 0x5c0d
+#define STM32F429_PF12_FUNC_EVENTOUT 0x5c10
+#define STM32F429_PF12_FUNC_ANALOG 0x5c11
+
+#define STM32F429_PF13_FUNC_GPIO 0x5d00
+#define STM32F429_PF13_FUNC_FMC_A7 0x5d0d
+#define STM32F429_PF13_FUNC_EVENTOUT 0x5d10
+#define STM32F429_PF13_FUNC_ANALOG 0x5d11
+
+#define STM32F429_PF14_FUNC_GPIO 0x5e00
+#define STM32F429_PF14_FUNC_FMC_A8 0x5e0d
+#define STM32F429_PF14_FUNC_EVENTOUT 0x5e10
+#define STM32F429_PF14_FUNC_ANALOG 0x5e11
+
+#define STM32F429_PF15_FUNC_GPIO 0x5f00
+#define STM32F429_PF15_FUNC_FMC_A9 0x5f0d
+#define STM32F429_PF15_FUNC_EVENTOUT 0x5f10
+#define STM32F429_PF15_FUNC_ANALOG 0x5f11
+
+
+
+#define STM32F429_PG0_FUNC_GPIO 0x6000
+#define STM32F429_PG0_FUNC_FMC_A10 0x600d
+#define STM32F429_PG0_FUNC_EVENTOUT 0x6010
+#define STM32F429_PG0_FUNC_ANALOG 0x6011
+
+#define STM32F429_PG1_FUNC_GPIO 0x6100
+#define STM32F429_PG1_FUNC_FMC_A11 0x610d
+#define STM32F429_PG1_FUNC_EVENTOUT 0x6110
+#define STM32F429_PG1_FUNC_ANALOG 0x6111
+
+#define STM32F429_PG2_FUNC_GPIO 0x6200
+#define STM32F429_PG2_FUNC_FMC_A12 0x620d
+#define STM32F429_PG2_FUNC_EVENTOUT 0x6210
+#define STM32F429_PG2_FUNC_ANALOG 0x6211
+
+#define STM32F429_PG3_FUNC_GPIO 0x6300
+#define STM32F429_PG3_FUNC_FMC_A13 0x630d
+#define STM32F429_PG3_FUNC_EVENTOUT 0x6310
+#define STM32F429_PG3_FUNC_ANALOG 0x6311
+
+#define STM32F429_PG4_FUNC_GPIO 0x6400
+#define STM32F429_PG4_FUNC_FMC_A14_FMC_BA0 0x640d
+#define STM32F429_PG4_FUNC_EVENTOUT 0x6410
+#define STM32F429_PG4_FUNC_ANALOG 0x6411
+
+#define STM32F429_PG5_FUNC_GPIO 0x6500
+#define STM32F429_PG5_FUNC_FMC_A15_FMC_BA1 0x650d
+#define STM32F429_PG5_FUNC_EVENTOUT 0x6510
+#define STM32F429_PG5_FUNC_ANALOG 0x6511
+
+#define STM32F429_PG6_FUNC_GPIO 0x6600
+#define STM32F429_PG6_FUNC_FMC_INT2 0x660d
+#define STM32F429_PG6_FUNC_DCMI_D12 0x660e
+#define STM32F429_PG6_FUNC_LCD_R7 0x660f
+#define STM32F429_PG6_FUNC_EVENTOUT 0x6610
+#define STM32F429_PG6_FUNC_ANALOG 0x6611
+
+#define STM32F429_PG7_FUNC_GPIO 0x6700
+#define STM32F429_PG7_FUNC_USART6_CK 0x6709
+#define STM32F429_PG7_FUNC_FMC_INT3 0x670d
+#define STM32F429_PG7_FUNC_DCMI_D13 0x670e
+#define STM32F429_PG7_FUNC_LCD_CLK 0x670f
+#define STM32F429_PG7_FUNC_EVENTOUT 0x6710
+#define STM32F429_PG7_FUNC_ANALOG 0x6711
+
+#define STM32F429_PG8_FUNC_GPIO 0x6800
+#define STM32F429_PG8_FUNC_SPI6_NSS 0x6806
+#define STM32F429_PG8_FUNC_USART6_RTS 0x6809
+#define STM32F429_PG8_FUNC_ETH_PPS_OUT 0x680c
+#define STM32F429_PG8_FUNC_FMC_SDCLK 0x680d
+#define STM32F429_PG8_FUNC_EVENTOUT 0x6810
+#define STM32F429_PG8_FUNC_ANALOG 0x6811
+
+#define STM32F429_PG9_FUNC_GPIO 0x6900
+#define STM32F429_PG9_FUNC_USART6_RX 0x6909
+#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d
+#define STM32F429_PG9_FUNC_DCMI_VSYNC 0x690e
+#define STM32F429_PG9_FUNC_EVENTOUT 0x6910
+#define STM32F429_PG9_FUNC_ANALOG 0x6911
+
+#define STM32F429_PG10_FUNC_GPIO 0x6a00
+#define STM32F429_PG10_FUNC_LCD_G3 0x6a0a
+#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d
+#define STM32F429_PG10_FUNC_DCMI_D2 0x6a0e
+#define STM32F429_PG10_FUNC_LCD_B2 0x6a0f
+#define STM32F429_PG10_FUNC_EVENTOUT 0x6a10
+#define STM32F429_PG10_FUNC_ANALOG 0x6a11
+
+#define STM32F429_PG11_FUNC_GPIO 0x6b00
+#define STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c
+#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d
+#define STM32F429_PG11_FUNC_DCMI_D3 0x6b0e
+#define STM32F429_PG11_FUNC_LCD_B3 0x6b0f
+#define STM32F429_PG11_FUNC_EVENTOUT 0x6b10
+#define STM32F429_PG11_FUNC_ANALOG 0x6b11
+
+#define STM32F429_PG12_FUNC_GPIO 0x6c00
+#define STM32F429_PG12_FUNC_SPI6_MISO 0x6c06
+#define STM32F429_PG12_FUNC_USART6_RTS 0x6c09
+#define STM32F429_PG12_FUNC_LCD_B4 0x6c0a
+#define STM32F429_PG12_FUNC_FMC_NE4 0x6c0d
+#define STM32F429_PG12_FUNC_LCD_B1 0x6c0f
+#define STM32F429_PG12_FUNC_EVENTOUT 0x6c10
+#define STM32F429_PG12_FUNC_ANALOG 0x6c11
+
+#define STM32F429_PG13_FUNC_GPIO 0x6d00
+#define STM32F429_PG13_FUNC_SPI6_SCK 0x6d06
+#define STM32F429_PG13_FUNC_USART6_CTS 0x6d09
+#define STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c
+#define STM32F429_PG13_FUNC_FMC_A24 0x6d0d
+#define STM32F429_PG13_FUNC_EVENTOUT 0x6d10
+#define STM32F429_PG13_FUNC_ANALOG 0x6d11
+
+#define STM32F429_PG14_FUNC_GPIO 0x6e00
+#define STM32F429_PG14_FUNC_SPI6_MOSI 0x6e06
+#define STM32F429_PG14_FUNC_USART6_TX 0x6e09
+#define STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c
+#define STM32F429_PG14_FUNC_FMC_A25 0x6e0d
+#define STM32F429_PG14_FUNC_EVENTOUT 0x6e10
+#define STM32F429_PG14_FUNC_ANALOG 0x6e11
+
+#define STM32F429_PG15_FUNC_GPIO 0x6f00
+#define STM32F429_PG15_FUNC_USART6_CTS 0x6f09
+#define STM32F429_PG15_FUNC_FMC_SDNCAS 0x6f0d
+#define STM32F429_PG15_FUNC_DCMI_D13 0x6f0e
+#define STM32F429_PG15_FUNC_EVENTOUT 0x6f10
+#define STM32F429_PG15_FUNC_ANALOG 0x6f11
+
+
+
+#define STM32F429_PH0_FUNC_GPIO 0x7000
+#define STM32F429_PH0_FUNC_EVENTOUT 0x7010
+#define STM32F429_PH0_FUNC_ANALOG 0x7011
+
+#define STM32F429_PH1_FUNC_GPIO 0x7100
+#define STM32F429_PH1_FUNC_EVENTOUT 0x7110
+#define STM32F429_PH1_FUNC_ANALOG 0x7111
+
+#define STM32F429_PH2_FUNC_GPIO 0x7200
+#define STM32F429_PH2_FUNC_ETH_MII_CRS 0x720c
+#define STM32F429_PH2_FUNC_FMC_SDCKE0 0x720d
+#define STM32F429_PH2_FUNC_LCD_R0 0x720f
+#define STM32F429_PH2_FUNC_EVENTOUT 0x7210
+#define STM32F429_PH2_FUNC_ANALOG 0x7211
+
+#define STM32F429_PH3_FUNC_GPIO 0x7300
+#define STM32F429_PH3_FUNC_ETH_MII_COL 0x730c
+#define STM32F429_PH3_FUNC_FMC_SDNE0 0x730d
+#define STM32F429_PH3_FUNC_LCD_R1 0x730f
+#define STM32F429_PH3_FUNC_EVENTOUT 0x7310
+#define STM32F429_PH3_FUNC_ANALOG 0x7311
+
+#define STM32F429_PH4_FUNC_GPIO 0x7400
+#define STM32F429_PH4_FUNC_I2C2_SCL 0x7405
+#define STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b
+#define STM32F429_PH4_FUNC_EVENTOUT 0x7410
+#define STM32F429_PH4_FUNC_ANALOG 0x7411
+
+#define STM32F429_PH5_FUNC_GPIO 0x7500
+#define STM32F429_PH5_FUNC_I2C2_SDA 0x7505
+#define STM32F429_PH5_FUNC_SPI5_NSS 0x7506
+#define STM32F429_PH5_FUNC_FMC_SDNWE 0x750d
+#define STM32F429_PH5_FUNC_EVENTOUT 0x7510
+#define STM32F429_PH5_FUNC_ANALOG 0x7511
+
+#define STM32F429_PH6_FUNC_GPIO 0x7600
+#define STM32F429_PH6_FUNC_I2C2_SMBA 0x7605
+#define STM32F429_PH6_FUNC_SPI5_SCK 0x7606
+#define STM32F429_PH6_FUNC_TIM12_CH1 0x760a
+#define STM32F429_PH6_FUNC_ETH_MII_RXD2 0x760c
+#define STM32F429_PH6_FUNC_FMC_SDNE1 0x760d
+#define STM32F429_PH6_FUNC_DCMI_D8 0x760e
+#define STM32F429_PH6_FUNC_EVENTOUT 0x7610
+#define STM32F429_PH6_FUNC_ANALOG 0x7611
+
+#define STM32F429_PH7_FUNC_GPIO 0x7700
+#define STM32F429_PH7_FUNC_I2C3_SCL 0x7705
+#define STM32F429_PH7_FUNC_SPI5_MISO 0x7706
+#define STM32F429_PH7_FUNC_ETH_MII_RXD3 0x770c
+#define STM32F429_PH7_FUNC_FMC_SDCKE1 0x770d
+#define STM32F429_PH7_FUNC_DCMI_D9 0x770e
+#define STM32F429_PH7_FUNC_EVENTOUT 0x7710
+#define STM32F429_PH7_FUNC_ANALOG 0x7711
+
+#define STM32F429_PH8_FUNC_GPIO 0x7800
+#define STM32F429_PH8_FUNC_I2C3_SDA 0x7805
+#define STM32F429_PH8_FUNC_FMC_D16 0x780d
+#define STM32F429_PH8_FUNC_DCMI_HSYNC 0x780e
+#define STM32F429_PH8_FUNC_LCD_R2 0x780f
+#define STM32F429_PH8_FUNC_EVENTOUT 0x7810
+#define STM32F429_PH8_FUNC_ANALOG 0x7811
+
+#define STM32F429_PH9_FUNC_GPIO 0x7900
+#define STM32F429_PH9_FUNC_I2C3_SMBA 0x7905
+#define STM32F429_PH9_FUNC_TIM12_CH2 0x790a
+#define STM32F429_PH9_FUNC_FMC_D17 0x790d
+#define STM32F429_PH9_FUNC_DCMI_D0 0x790e
+#define STM32F429_PH9_FUNC_LCD_R3 0x790f
+#define STM32F429_PH9_FUNC_EVENTOUT 0x7910
+#define STM32F429_PH9_FUNC_ANALOG 0x7911
+
+#define STM32F429_PH10_FUNC_GPIO 0x7a00
+#define STM32F429_PH10_FUNC_TIM5_CH1 0x7a03
+#define STM32F429_PH10_FUNC_FMC_D18 0x7a0d
+#define STM32F429_PH10_FUNC_DCMI_D1 0x7a0e
+#define STM32F429_PH10_FUNC_LCD_R4 0x7a0f
+#define STM32F429_PH10_FUNC_EVENTOUT 0x7a10
+#define STM32F429_PH10_FUNC_ANALOG 0x7a11
+
+#define STM32F429_PH11_FUNC_GPIO 0x7b00
+#define STM32F429_PH11_FUNC_TIM5_CH2 0x7b03
+#define STM32F429_PH11_FUNC_FMC_D19 0x7b0d
+#define STM32F429_PH11_FUNC_DCMI_D2 0x7b0e
+#define STM32F429_PH11_FUNC_LCD_R5 0x7b0f
+#define STM32F429_PH11_FUNC_EVENTOUT 0x7b10
+#define STM32F429_PH11_FUNC_ANALOG 0x7b11
+
+#define STM32F429_PH12_FUNC_GPIO 0x7c00
+#define STM32F429_PH12_FUNC_TIM5_CH3 0x7c03
+#define STM32F429_PH12_FUNC_FMC_D20 0x7c0d
+#define STM32F429_PH12_FUNC_DCMI_D3 0x7c0e
+#define STM32F429_PH12_FUNC_LCD_R6 0x7c0f
+#define STM32F429_PH12_FUNC_EVENTOUT 0x7c10
+#define STM32F429_PH12_FUNC_ANALOG 0x7c11
+
+#define STM32F429_PH13_FUNC_GPIO 0x7d00
+#define STM32F429_PH13_FUNC_TIM8_CH1N 0x7d04
+#define STM32F429_PH13_FUNC_CAN1_TX 0x7d0a
+#define STM32F429_PH13_FUNC_FMC_D21 0x7d0d
+#define STM32F429_PH13_FUNC_LCD_G2 0x7d0f
+#define STM32F429_PH13_FUNC_EVENTOUT 0x7d10
+#define STM32F429_PH13_FUNC_ANALOG 0x7d11
+
+#define STM32F429_PH14_FUNC_GPIO 0x7e00
+#define STM32F429_PH14_FUNC_TIM8_CH2N 0x7e04
+#define STM32F429_PH14_FUNC_FMC_D22 0x7e0d
+#define STM32F429_PH14_FUNC_DCMI_D4 0x7e0e
+#define STM32F429_PH14_FUNC_LCD_G3 0x7e0f
+#define STM32F429_PH14_FUNC_EVENTOUT 0x7e10
+#define STM32F429_PH14_FUNC_ANALOG 0x7e11
+
+#define STM32F429_PH15_FUNC_GPIO 0x7f00
+#define STM32F429_PH15_FUNC_TIM8_CH3N 0x7f04
+#define STM32F429_PH15_FUNC_FMC_D23 0x7f0d
+#define STM32F429_PH15_FUNC_DCMI_D11 0x7f0e
+#define STM32F429_PH15_FUNC_LCD_G4 0x7f0f
+#define STM32F429_PH15_FUNC_EVENTOUT 0x7f10
+#define STM32F429_PH15_FUNC_ANALOG 0x7f11
+
+
+
+#define STM32F429_PI0_FUNC_GPIO 0x8000
+#define STM32F429_PI0_FUNC_TIM5_CH4 0x8003
+#define STM32F429_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006
+#define STM32F429_PI0_FUNC_FMC_D24 0x800d
+#define STM32F429_PI0_FUNC_DCMI_D13 0x800e
+#define STM32F429_PI0_FUNC_LCD_G5 0x800f
+#define STM32F429_PI0_FUNC_EVENTOUT 0x8010
+#define STM32F429_PI0_FUNC_ANALOG 0x8011
+
+#define STM32F429_PI1_FUNC_GPIO 0x8100
+#define STM32F429_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106
+#define STM32F429_PI1_FUNC_FMC_D25 0x810d
+#define STM32F429_PI1_FUNC_DCMI_D8 0x810e
+#define STM32F429_PI1_FUNC_LCD_G6 0x810f
+#define STM32F429_PI1_FUNC_EVENTOUT 0x8110
+#define STM32F429_PI1_FUNC_ANALOG 0x8111
+
+#define STM32F429_PI2_FUNC_GPIO 0x8200
+#define STM32F429_PI2_FUNC_TIM8_CH4 0x8204
+#define STM32F429_PI2_FUNC_SPI2_MISO 0x8206
+#define STM32F429_PI2_FUNC_I2S2EXT_SD 0x8207
+#define STM32F429_PI2_FUNC_FMC_D26 0x820d
+#define STM32F429_PI2_FUNC_DCMI_D9 0x820e
+#define STM32F429_PI2_FUNC_LCD_G7 0x820f
+#define STM32F429_PI2_FUNC_EVENTOUT 0x8210
+#define STM32F429_PI2_FUNC_ANALOG 0x8211
+
+#define STM32F429_PI3_FUNC_GPIO 0x8300
+#define STM32F429_PI3_FUNC_TIM8_ETR 0x8304
+#define STM32F429_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306
+#define STM32F429_PI3_FUNC_FMC_D27 0x830d
+#define STM32F429_PI3_FUNC_DCMI_D10 0x830e
+#define STM32F429_PI3_FUNC_EVENTOUT 0x8310
+#define STM32F429_PI3_FUNC_ANALOG 0x8311
+
+#define STM32F429_PI4_FUNC_GPIO 0x8400
+#define STM32F429_PI4_FUNC_TIM8_BKIN 0x8404
+#define STM32F429_PI4_FUNC_FMC_NBL2 0x840d
+#define STM32F429_PI4_FUNC_DCMI_D5 0x840e
+#define STM32F429_PI4_FUNC_LCD_B4 0x840f
+#define STM32F429_PI4_FUNC_EVENTOUT 0x8410
+#define STM32F429_PI4_FUNC_ANALOG 0x8411
+
+#define STM32F429_PI5_FUNC_GPIO 0x8500
+#define STM32F429_PI5_FUNC_TIM8_CH1 0x8504
+#define STM32F429_PI5_FUNC_FMC_NBL3 0x850d
+#define STM32F429_PI5_FUNC_DCMI_VSYNC 0x850e
+#define STM32F429_PI5_FUNC_LCD_B5 0x850f
+#define STM32F429_PI5_FUNC_EVENTOUT 0x8510
+#define STM32F429_PI5_FUNC_ANALOG 0x8511
+
+#define STM32F429_PI6_FUNC_GPIO 0x8600
+#define STM32F429_PI6_FUNC_TIM8_CH2 0x8604
+#define STM32F429_PI6_FUNC_FMC_D28 0x860d
+#define STM32F429_PI6_FUNC_DCMI_D6 0x860e
+#define STM32F429_PI6_FUNC_LCD_B6 0x860f
+#define STM32F429_PI6_FUNC_EVENTOUT 0x8610
+#define STM32F429_PI6_FUNC_ANALOG 0x8611
+
+#define STM32F429_PI7_FUNC_GPIO 0x8700
+#define STM32F429_PI7_FUNC_TIM8_CH3 0x8704
+#define STM32F429_PI7_FUNC_FMC_D29 0x870d
+#define STM32F429_PI7_FUNC_DCMI_D7 0x870e
+#define STM32F429_PI7_FUNC_LCD_B7 0x870f
+#define STM32F429_PI7_FUNC_EVENTOUT 0x8710
+#define STM32F429_PI7_FUNC_ANALOG 0x8711
+
+#define STM32F429_PI8_FUNC_GPIO 0x8800
+#define STM32F429_PI8_FUNC_EVENTOUT 0x8810
+#define STM32F429_PI8_FUNC_ANALOG 0x8811
+
+#define STM32F429_PI9_FUNC_GPIO 0x8900
+#define STM32F429_PI9_FUNC_CAN1_RX 0x890a
+#define STM32F429_PI9_FUNC_FMC_D30 0x890d
+#define STM32F429_PI9_FUNC_LCD_VSYNC 0x890f
+#define STM32F429_PI9_FUNC_EVENTOUT 0x8910
+#define STM32F429_PI9_FUNC_ANALOG 0x8911
+
+#define STM32F429_PI10_FUNC_GPIO 0x8a00
+#define STM32F429_PI10_FUNC_ETH_MII_RX_ER 0x8a0c
+#define STM32F429_PI10_FUNC_FMC_D31 0x8a0d
+#define STM32F429_PI10_FUNC_LCD_HSYNC 0x8a0f
+#define STM32F429_PI10_FUNC_EVENTOUT 0x8a10
+#define STM32F429_PI10_FUNC_ANALOG 0x8a11
+
+#define STM32F429_PI11_FUNC_GPIO 0x8b00
+#define STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b
+#define STM32F429_PI11_FUNC_EVENTOUT 0x8b10
+#define STM32F429_PI11_FUNC_ANALOG 0x8b11
+
+#define STM32F429_PI12_FUNC_GPIO 0x8c00
+#define STM32F429_PI12_FUNC_LCD_HSYNC 0x8c0f
+#define STM32F429_PI12_FUNC_EVENTOUT 0x8c10
+#define STM32F429_PI12_FUNC_ANALOG 0x8c11
+
+#define STM32F429_PI13_FUNC_GPIO 0x8d00
+#define STM32F429_PI13_FUNC_LCD_VSYNC 0x8d0f
+#define STM32F429_PI13_FUNC_EVENTOUT 0x8d10
+#define STM32F429_PI13_FUNC_ANALOG 0x8d11
+
+#define STM32F429_PI14_FUNC_GPIO 0x8e00
+#define STM32F429_PI14_FUNC_LCD_CLK 0x8e0f
+#define STM32F429_PI14_FUNC_EVENTOUT 0x8e10
+#define STM32F429_PI14_FUNC_ANALOG 0x8e11
+
+#define STM32F429_PI15_FUNC_GPIO 0x8f00
+#define STM32F429_PI15_FUNC_LCD_R0 0x8f0f
+#define STM32F429_PI15_FUNC_EVENTOUT 0x8f10
+#define STM32F429_PI15_FUNC_ANALOG 0x8f11
+
+
+
+#define STM32F429_PJ0_FUNC_GPIO 0x9000
+#define STM32F429_PJ0_FUNC_LCD_R1 0x900f
+#define STM32F429_PJ0_FUNC_EVENTOUT 0x9010
+#define STM32F429_PJ0_FUNC_ANALOG 0x9011
+
+#define STM32F429_PJ1_FUNC_GPIO 0x9100
+#define STM32F429_PJ1_FUNC_LCD_R2 0x910f
+#define STM32F429_PJ1_FUNC_EVENTOUT 0x9110
+#define STM32F429_PJ1_FUNC_ANALOG 0x9111
+
+#define STM32F429_PJ2_FUNC_GPIO 0x9200
+#define STM32F429_PJ2_FUNC_LCD_R3 0x920f
+#define STM32F429_PJ2_FUNC_EVENTOUT 0x9210
+#define STM32F429_PJ2_FUNC_ANALOG 0x9211
+
+#define STM32F429_PJ3_FUNC_GPIO 0x9300
+#define STM32F429_PJ3_FUNC_LCD_R4 0x930f
+#define STM32F429_PJ3_FUNC_EVENTOUT 0x9310
+#define STM32F429_PJ3_FUNC_ANALOG 0x9311
+
+#define STM32F429_PJ4_FUNC_GPIO 0x9400
+#define STM32F429_PJ4_FUNC_LCD_R5 0x940f
+#define STM32F429_PJ4_FUNC_EVENTOUT 0x9410
+#define STM32F429_PJ4_FUNC_ANALOG 0x9411
+
+#define STM32F429_PJ5_FUNC_GPIO 0x9500
+#define STM32F429_PJ5_FUNC_LCD_R6 0x950f
+#define STM32F429_PJ5_FUNC_EVENTOUT 0x9510
+#define STM32F429_PJ5_FUNC_ANALOG 0x9511
+
+#define STM32F429_PJ6_FUNC_GPIO 0x9600
+#define STM32F429_PJ6_FUNC_LCD_R7 0x960f
+#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610
+#define STM32F429_PJ6_FUNC_ANALOG 0x9611
+
+#define STM32F429_PJ7_FUNC_GPIO 0x9700
+#define STM32F429_PJ7_FUNC_LCD_G0 0x970f
+#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710
+#define STM32F429_PJ7_FUNC_ANALOG 0x9711
+
+#define STM32F429_PJ8_FUNC_GPIO 0x9800
+#define STM32F429_PJ8_FUNC_LCD_G1 0x980f
+#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810
+#define STM32F429_PJ8_FUNC_ANALOG 0x9811
+
+#define STM32F429_PJ9_FUNC_GPIO 0x9900
+#define STM32F429_PJ9_FUNC_LCD_G2 0x990f
+#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910
+#define STM32F429_PJ9_FUNC_ANALOG 0x9911
+
+#define STM32F429_PJ10_FUNC_GPIO 0x9a00
+#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f
+#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10
+#define STM32F429_PJ10_FUNC_ANALOG 0x9a11
+
+#define STM32F429_PJ11_FUNC_GPIO 0x9b00
+#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f
+#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10
+#define STM32F429_PJ11_FUNC_ANALOG 0x9b11
+
+#define STM32F429_PJ12_FUNC_GPIO 0x9c00
+#define STM32F429_PJ12_FUNC_LCD_B0 0x9c0f
+#define STM32F429_PJ12_FUNC_EVENTOUT 0x9c10
+#define STM32F429_PJ12_FUNC_ANALOG 0x9c11
+
+#define STM32F429_PJ13_FUNC_GPIO 0x9d00
+#define STM32F429_PJ13_FUNC_LCD_B1 0x9d0f
+#define STM32F429_PJ13_FUNC_EVENTOUT 0x9d10
+#define STM32F429_PJ13_FUNC_ANALOG 0x9d11
+
+#define STM32F429_PJ14_FUNC_GPIO 0x9e00
+#define STM32F429_PJ14_FUNC_LCD_B2 0x9e0f
+#define STM32F429_PJ14_FUNC_EVENTOUT 0x9e10
+#define STM32F429_PJ14_FUNC_ANALOG 0x9e11
+
+#define STM32F429_PJ15_FUNC_GPIO 0x9f00
+#define STM32F429_PJ15_FUNC_LCD_B3 0x9f0f
+#define STM32F429_PJ15_FUNC_EVENTOUT 0x9f10
+#define STM32F429_PJ15_FUNC_ANALOG 0x9f11
+
+
+
+#define STM32F429_PK0_FUNC_GPIO 0xa000
+#define STM32F429_PK0_FUNC_LCD_G5 0xa00f
+#define STM32F429_PK0_FUNC_EVENTOUT 0xa010
+#define STM32F429_PK0_FUNC_ANALOG 0xa011
+
+#define STM32F429_PK1_FUNC_GPIO 0xa100
+#define STM32F429_PK1_FUNC_LCD_G6 0xa10f
+#define STM32F429_PK1_FUNC_EVENTOUT 0xa110
+#define STM32F429_PK1_FUNC_ANALOG 0xa111
+
+#define STM32F429_PK2_FUNC_GPIO 0xa200
+#define STM32F429_PK2_FUNC_LCD_G7 0xa20f
+#define STM32F429_PK2_FUNC_EVENTOUT 0xa210
+#define STM32F429_PK2_FUNC_ANALOG 0xa211
+
+#define STM32F429_PK3_FUNC_GPIO 0xa300
+#define STM32F429_PK3_FUNC_LCD_B4 0xa30f
+#define STM32F429_PK3_FUNC_EVENTOUT 0xa310
+#define STM32F429_PK3_FUNC_ANALOG 0xa311
+
+#define STM32F429_PK4_FUNC_GPIO 0xa400
+#define STM32F429_PK4_FUNC_LCD_B5 0xa40f
+#define STM32F429_PK4_FUNC_EVENTOUT 0xa410
+#define STM32F429_PK4_FUNC_ANALOG 0xa411
+
+#define STM32F429_PK5_FUNC_GPIO 0xa500
+#define STM32F429_PK5_FUNC_LCD_B6 0xa50f
+#define STM32F429_PK5_FUNC_EVENTOUT 0xa510
+#define STM32F429_PK5_FUNC_ANALOG 0xa511
+
+#define STM32F429_PK6_FUNC_GPIO 0xa600
+#define STM32F429_PK6_FUNC_LCD_B7 0xa60f
+#define STM32F429_PK6_FUNC_EVENTOUT 0xa610
+#define STM32F429_PK6_FUNC_ANALOG 0xa611
+
+#define STM32F429_PK7_FUNC_GPIO 0xa700
+#define STM32F429_PK7_FUNC_LCD_DE 0xa70f
+#define STM32F429_PK7_FUNC_EVENTOUT 0xa710
+#define STM32F429_PK7_FUNC_ANALOG 0xa711
+
+#endif /* _DT_BINDINGS_STM32F429_PINFUNC_H */
diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7779-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7779-sysc.h
new file mode 100644
index 000000000000..183571da507e
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/power/r8a7779-sysc.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7779_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7779_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7779_PD_ARM1			 1
+#define R8A7779_PD_ARM2			 2
+#define R8A7779_PD_ARM3			 3
+#define R8A7779_PD_SGX			20
+#define R8A7779_PD_VDP			21
+#define R8A7779_PD_IMP			24
+
+/* Always-on power area */
+#define R8A7779_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7779_SYSC_H__ */
diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7790-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7790-sysc.h
new file mode 100644
index 000000000000..6af4e9929bd0
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/power/r8a7790-sysc.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7790_PD_CA15_CPU0		 0
+#define R8A7790_PD_CA15_CPU1		 1
+#define R8A7790_PD_CA15_CPU2		 2
+#define R8A7790_PD_CA15_CPU3		 3
+#define R8A7790_PD_CA7_CPU0		 5
+#define R8A7790_PD_CA7_CPU1		 6
+#define R8A7790_PD_CA7_CPU2		 7
+#define R8A7790_PD_CA7_CPU3		 8
+#define R8A7790_PD_CA15_SCU		12
+#define R8A7790_PD_SH_4A		16
+#define R8A7790_PD_RGX			20
+#define R8A7790_PD_CA7_SCU		21
+#define R8A7790_PD_IMP			24
+
+/* Always-on power area */
+#define R8A7790_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7791-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7791-sysc.h
new file mode 100644
index 000000000000..1403baa0514f
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/power/r8a7791-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7791_PD_CA15_CPU0		 0
+#define R8A7791_PD_CA15_CPU1		 1
+#define R8A7791_PD_CA15_SCU		12
+#define R8A7791_PD_SH_4A		16
+#define R8A7791_PD_SGX			20
+
+/* Always-on power area */
+#define R8A7791_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7793-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7793-sysc.h
new file mode 100644
index 000000000000..b5693df3d830
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/power/r8a7793-sysc.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ *
+ * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
+ */
+
+#define R8A7793_PD_CA15_CPU0		 0
+#define R8A7793_PD_CA15_CPU1		 1
+#define R8A7793_PD_CA15_SCU		12
+#define R8A7793_PD_SH_4A		16
+#define R8A7793_PD_SGX			20
+
+/* Always-on power area */
+#define R8A7793_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7794-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7794-sysc.h
new file mode 100644
index 000000000000..862241c2d27b
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/power/r8a7794-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7794_PD_CA7_CPU0		 5
+#define R8A7794_PD_CA7_CPU1		 6
+#define R8A7794_PD_SH_4A		16
+#define R8A7794_PD_SGX			20
+#define R8A7794_PD_CA7_SCU		21
+
+/* Always-on power area */
+#define R8A7794_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
diff --git a/sys/gnu/dts/include/dt-bindings/power/r8a7795-sysc.h b/sys/gnu/dts/include/dt-bindings/power/r8a7795-sysc.h
new file mode 100644
index 000000000000..ee2e26ba605e
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/power/r8a7795-sysc.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7795_PD_CA57_CPU0		 0
+#define R8A7795_PD_CA57_CPU1		 1
+#define R8A7795_PD_CA57_CPU2		 2
+#define R8A7795_PD_CA57_CPU3		 3
+#define R8A7795_PD_CA53_CPU0		 5
+#define R8A7795_PD_CA53_CPU1		 6
+#define R8A7795_PD_CA53_CPU2		 7
+#define R8A7795_PD_CA53_CPU3		 8
+#define R8A7795_PD_A3VP			 9
+#define R8A7795_PD_CA57_SCU		12
+#define R8A7795_PD_CR7			13
+#define R8A7795_PD_A3VC			14
+#define R8A7795_PD_3DG_A		17
+#define R8A7795_PD_3DG_B		18
+#define R8A7795_PD_3DG_C		19
+#define R8A7795_PD_3DG_D		20
+#define R8A7795_PD_CA53_SCU		21
+#define R8A7795_PD_3DG_E		22
+#define R8A7795_PD_A3IR			24
+#define R8A7795_PD_A2VC0		25
+#define R8A7795_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A7795_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3368-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3368-power.h
new file mode 100644
index 000000000000..93633d57ed84
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/power/rk3368-power.h
@@ -0,0 +1,28 @@
+#ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__
+#define __DT_BINDINGS_POWER_RK3368_POWER_H__
+
+/* VD_CORE */
+#define RK3368_PD_A53_L0	0
+#define RK3368_PD_A53_L1	1
+#define RK3368_PD_A53_L2	2
+#define RK3368_PD_A53_L3	3
+#define RK3368_PD_SCU_L		4
+#define RK3368_PD_A53_B0	5
+#define RK3368_PD_A53_B1	6
+#define RK3368_PD_A53_B2	7
+#define RK3368_PD_A53_B3	8
+#define RK3368_PD_SCU_B		9
+
+/* VD_LOGIC */
+#define RK3368_PD_BUS		10
+#define RK3368_PD_PERI		11
+#define RK3368_PD_VIO		12
+#define RK3368_PD_ALIVE		13
+#define RK3368_PD_VIDEO		14
+#define RK3368_PD_GPU_0		15
+#define RK3368_PD_GPU_1		16
+
+/* VD_PMU */
+#define RK3368_PD_PMU		17
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/power/rk3399-power.h b/sys/gnu/dts/include/dt-bindings/power/rk3399-power.h
new file mode 100644
index 000000000000..168b3bfbd6f5
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/power/rk3399-power.h
@@ -0,0 +1,53 @@
+#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
+#define __DT_BINDINGS_POWER_RK3399_POWER_H__
+
+/* VD_CORE_L */
+#define RK3399_PD_A53_L0	0
+#define RK3399_PD_A53_L1	1
+#define RK3399_PD_A53_L2	2
+#define RK3399_PD_A53_L3	3
+#define RK3399_PD_SCU_L		4
+
+/* VD_CORE_B */
+#define RK3399_PD_A72_B0	5
+#define RK3399_PD_A72_B1	6
+#define RK3399_PD_SCU_B		7
+
+/* VD_LOGIC */
+#define RK3399_PD_TCPD0		8
+#define RK3399_PD_TCPD1		9
+#define RK3399_PD_CCI		10
+#define RK3399_PD_CCI0		11
+#define RK3399_PD_CCI1		12
+#define RK3399_PD_PERILP	13
+#define RK3399_PD_PERIHP	14
+#define RK3399_PD_VIO		15
+#define RK3399_PD_VO		16
+#define RK3399_PD_VOPB		17
+#define RK3399_PD_VOPL		18
+#define RK3399_PD_ISP0		19
+#define RK3399_PD_ISP1		20
+#define RK3399_PD_HDCP		21
+#define RK3399_PD_GMAC		22
+#define RK3399_PD_EMMC		23
+#define RK3399_PD_USB3		24
+#define RK3399_PD_EDP		25
+#define RK3399_PD_GIC		26
+#define RK3399_PD_SD		27
+#define RK3399_PD_SDIOAUDIO	28
+#define RK3399_PD_ALIVE		29
+
+/* VD_CENTER */
+#define RK3399_PD_CENTER	30
+#define RK3399_PD_VCODEC	31
+#define RK3399_PD_VDU		32
+#define RK3399_PD_RGA		33
+#define RK3399_PD_IEP		34
+
+/* VD_GPU */
+#define RK3399_PD_GPU		35
+
+/* VD_PMU */
+#define RK3399_PD_PMU		36
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/reset/pistachio-resets.h b/sys/gnu/dts/include/dt-bindings/reset/pistachio-resets.h
new file mode 100644
index 000000000000..60a189b1faef
--- /dev/null
+++ b/sys/gnu/dts/include/dt-bindings/reset/pistachio-resets.h
@@ -0,0 +1,36 @@
+/*
+ * This header provides constants for the reset controller
+ * present in the Pistachio SoC
+ */
+
+#ifndef _PISTACHIO_RESETS_H
+#define _PISTACHIO_RESETS_H
+
+#define PISTACHIO_RESET_I2C0		0
+#define PISTACHIO_RESET_I2C1		1
+#define PISTACHIO_RESET_I2C2		2
+#define PISTACHIO_RESET_I2C3		3
+#define PISTACHIO_RESET_I2S_IN		4
+#define PISTACHIO_RESET_PRL_OUT		5
+#define PISTACHIO_RESET_SPDIF_OUT	6
+#define PISTACHIO_RESET_SPI		7
+#define PISTACHIO_RESET_PWM_PDM		8
+#define PISTACHIO_RESET_UART0		9
+#define PISTACHIO_RESET_UART1		10
+#define PISTACHIO_RESET_QSPI		11
+#define PISTACHIO_RESET_MDC		12
+#define PISTACHIO_RESET_SDHOST		13
+#define PISTACHIO_RESET_ETHERNET	14
+#define PISTACHIO_RESET_IR		15
+#define PISTACHIO_RESET_HASH		16
+#define PISTACHIO_RESET_TIMER		17
+#define PISTACHIO_RESET_I2S_OUT		18
+#define PISTACHIO_RESET_SPDIF_IN	19
+#define PISTACHIO_RESET_EVT		20
+#define PISTACHIO_RESET_USB_H		21
+#define PISTACHIO_RESET_USB_PR		22
+#define PISTACHIO_RESET_USB_PHY_PR	23
+#define PISTACHIO_RESET_USB_PHY_PON	24
+#define PISTACHIO_RESET_MAX		24
+
+#endif
diff --git a/sys/gnu/dts/include/dt-bindings/thermal/tegra124-soctherm.h b/sys/gnu/dts/include/dt-bindings/thermal/tegra124-soctherm.h
index 85aaf66690f9..729ab9fc325e 100644
--- a/sys/gnu/dts/include/dt-bindings/thermal/tegra124-soctherm.h
+++ b/sys/gnu/dts/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -9,5 +9,6 @@
 #define TEGRA124_SOCTHERM_SENSOR_MEM 1
 #define TEGRA124_SOCTHERM_SENSOR_GPU 2
 #define TEGRA124_SOCTHERM_SENSOR_PLLX 3
+#define TEGRA124_SOCTHERM_SENSOR_NUM 4
 
 #endif
diff --git a/sys/i386/i386/genassym.c b/sys/i386/i386/genassym.c
index 30878344dc8e..a0e4d242cfa2 100644
--- a/sys/i386/i386/genassym.c
+++ b/sys/i386/i386/genassym.c
@@ -143,7 +143,6 @@ ASSYM(PCB_DR2, offsetof(struct pcb, pcb_dr2));
 ASSYM(PCB_DR3, offsetof(struct pcb, pcb_dr3));
 ASSYM(PCB_DR6, offsetof(struct pcb, pcb_dr6));
 ASSYM(PCB_DR7, offsetof(struct pcb, pcb_dr7));
-ASSYM(PCB_PSL, offsetof(struct pcb, pcb_psl));
 ASSYM(PCB_DBREGS, PCB_DBREGS);
 ASSYM(PCB_EXT, offsetof(struct pcb, pcb_ext));
 
diff --git a/sys/i386/i386/swtch.s b/sys/i386/i386/swtch.s
index 6bedb48c3647..a270b4845125 100644
--- a/sys/i386/i386/swtch.s
+++ b/sys/i386/i386/swtch.s
@@ -131,8 +131,6 @@ ENTRY(cpu_switch)
 	movl	%esi,PCB_ESI(%edx)
 	movl	%edi,PCB_EDI(%edx)
 	mov	%gs,PCB_GS(%edx)
-	pushfl					/* PSL */
-	popl	PCB_PSL(%edx)
 	/* Test if debug registers should be saved. */
 	testl	$PCB_DBREGS,PCB_FLAGS(%edx)
 	jz      1f                              /* no, skip over */
@@ -261,8 +259,6 @@ sw1:
 	movl	PCB_EDI(%edx),%edi
 	movl	PCB_EIP(%edx),%eax
 	movl	%eax,(%esp)
-	pushl	PCB_PSL(%edx)
-	popfl
 
 	movl	%edx, PCPU(CURPCB)
 	movl	TD_TID(%ecx),%eax
@@ -365,8 +361,6 @@ ENTRY(savectx)
 	movl	%esi,PCB_ESI(%ecx)
 	movl	%edi,PCB_EDI(%ecx)
 	mov	%gs,PCB_GS(%ecx)
-	pushfl
-	popl	PCB_PSL(%ecx)
 
 	movl	%cr0,%eax
 	movl	%eax,PCB_CR0(%ecx)
diff --git a/sys/i386/i386/vm_machdep.c b/sys/i386/i386/vm_machdep.c
index a73b60d1b5dc..b051179b7c25 100644
--- a/sys/i386/i386/vm_machdep.c
+++ b/sys/i386/i386/vm_machdep.c
@@ -273,7 +273,6 @@ cpu_fork(td1, p2, td2, flags)
 	pcb2->pcb_esp = (int)td2->td_frame - sizeof(void *);
 	pcb2->pcb_ebx = (int)td2;		/* fork_trampoline argument */
 	pcb2->pcb_eip = (int)fork_trampoline;
-	pcb2->pcb_psl = PSL_KERNEL;		/* ints disabled */
 	/*-
 	 * pcb2->pcb_dr*:	cloned above.
 	 * pcb2->pcb_savefpu:	cloned above.
@@ -504,7 +503,6 @@ cpu_copy_thread(struct thread *td, struct thread *td0)
 	pcb2->pcb_esp = (int)td->td_frame - sizeof(void *); /* trampoline arg */
 	pcb2->pcb_ebx = (int)td;			    /* trampoline arg */
 	pcb2->pcb_eip = (int)fork_trampoline;
-	pcb2->pcb_psl &= ~(PSL_I);	/* interrupts must be disabled */
 	pcb2->pcb_gs = rgs();
 	/*
 	 * If we didn't copy the pcb, we'd need to do the following registers:
diff --git a/sys/i386/include/pcb.h b/sys/i386/include/pcb.h
index 558565b872cb..dc9dcb252e4c 100644
--- a/sys/i386/include/pcb.h
+++ b/sys/i386/include/pcb.h
@@ -89,7 +89,7 @@ struct pcb {
 
 	caddr_t	pcb_onfault;	/* copyin/out fault recovery */
 	struct	pcb_ext	*pcb_ext;	/* optional pcb extension */
-	int	pcb_psl;	/* process status long */
+	int	pcb_waspsl;	/* unused padding for ABI and API compat */
 	u_long	pcb_vm86[2];	/* vm86bios scratch space */
 	union	savefpu *pcb_save;
 
diff --git a/sys/i386/linux/linux_systrace_args.c b/sys/i386/linux/linux_systrace_args.c
index 0a0bf42dbd40..72e2fa2f5592 100644
--- a/sys/i386/linux/linux_systrace_args.c
+++ b/sys/i386/linux/linux_systrace_args.c
@@ -2466,7 +2466,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "u_int";
@@ -2482,7 +2482,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "u_int";
@@ -2495,7 +2495,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 5:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2524,7 +2524,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		case 2:
 			p = "l_int";
@@ -2537,7 +2537,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 8:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2550,10 +2550,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 9:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2563,7 +2563,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 10:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2573,13 +2573,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 11:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char **";
+			p = "userland char **";
 			break;
 		case 2:
-			p = "char **";
+			p = "userland char **";
 			break;
 		default:
 			break;
@@ -2589,7 +2589,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 12:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2599,7 +2599,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 13:
 		switch(ndx) {
 		case 0:
-			p = "l_time_t *";
+			p = "userland l_time_t *";
 			break;
 		default:
 			break;
@@ -2609,7 +2609,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 14:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2625,7 +2625,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 15:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_mode_t";
@@ -2638,7 +2638,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 16:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid16_t";
@@ -2654,10 +2654,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 18:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct linux_stat *";
+			p = "userland struct linux_stat *";
 			break;
 		default:
 			break;
@@ -2686,19 +2686,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 21:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "l_ulong";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -2708,7 +2708,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 22:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2766,7 +2766,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct linux_stat *";
+			p = "userland struct linux_stat *";
 			break;
 		default:
 			break;
@@ -2779,10 +2779,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 30:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_utimbuf *";
+			p = "userland struct l_utimbuf *";
 			break;
 		default:
 			break;
@@ -2792,7 +2792,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 33:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2831,10 +2831,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 38:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2844,7 +2844,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 39:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -2857,7 +2857,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 40:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2877,7 +2877,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 42:
 		switch(ndx) {
 		case 0:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		default:
 			break;
@@ -2887,7 +2887,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 43:
 		switch(ndx) {
 		case 0:
-			p = "struct l_times_argv *";
+			p = "userland struct l_times_argv *";
 			break;
 		default:
 			break;
@@ -2923,7 +2923,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -2939,7 +2939,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 51:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -2949,7 +2949,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 52:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_int";
@@ -3020,7 +3020,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 61:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3033,7 +3033,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_dev_t";
 			break;
 		case 1:
-			p = "struct l_ustat *";
+			p = "userland struct l_ustat *";
 			break;
 		default:
 			break;
@@ -3068,10 +3068,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_osigaction_t *";
+			p = "userland l_osigaction_t *";
 			break;
 		case 2:
-			p = "l_osigaction_t *";
+			p = "userland l_osigaction_t *";
 			break;
 		default:
 			break;
@@ -3136,7 +3136,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 73:
 		switch(ndx) {
 		case 0:
-			p = "l_osigset_t *";
+			p = "userland l_osigset_t *";
 			break;
 		default:
 			break;
@@ -3146,7 +3146,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 74:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "u_int";
@@ -3162,7 +3162,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_rlimit *";
+			p = "userland struct l_rlimit *";
 			break;
 		default:
 			break;
@@ -3175,7 +3175,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_rlimit *";
+			p = "userland struct l_rlimit *";
 			break;
 		default:
 			break;
@@ -3188,7 +3188,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct rusage *";
+			p = "userland struct rusage *";
 			break;
 		default:
 			break;
@@ -3198,10 +3198,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 78:
 		switch(ndx) {
 		case 0:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -3211,10 +3211,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 79:
 		switch(ndx) {
 		case 0:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -3227,7 +3227,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		default:
 			break;
@@ -3240,7 +3240,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		default:
 			break;
@@ -3250,7 +3250,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 82:
 		switch(ndx) {
 		case 0:
-			p = "struct l_old_select_argv *";
+			p = "userland struct l_old_select_argv *";
 			break;
 		default:
 			break;
@@ -3260,10 +3260,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 83:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3273,10 +3273,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 84:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_stat *";
+			p = "userland struct l_stat *";
 			break;
 		default:
 			break;
@@ -3286,10 +3286,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 85:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -3302,7 +3302,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 86:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3312,7 +3312,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 87:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3331,7 +3331,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -3344,7 +3344,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_dirent *";
+			p = "userland struct l_dirent *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -3357,7 +3357,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 90:
 		switch(ndx) {
 		case 0:
-			p = "struct l_mmap_argv *";
+			p = "userland struct l_mmap_argv *";
 			break;
 		default:
 			break;
@@ -3380,7 +3380,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 92:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_ulong";
@@ -3464,10 +3464,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 99:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_statfs_buf *";
+			p = "userland struct l_statfs_buf *";
 			break;
 		default:
 			break;
@@ -3480,7 +3480,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_statfs_buf *";
+			p = "userland struct l_statfs_buf *";
 			break;
 		default:
 			break;
@@ -3522,7 +3522,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -3538,10 +3538,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_itimerval *";
+			p = "userland struct l_itimerval *";
 			break;
 		case 2:
-			p = "struct l_itimerval *";
+			p = "userland struct l_itimerval *";
 			break;
 		default:
 			break;
@@ -3554,7 +3554,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_itimerval *";
+			p = "userland struct l_itimerval *";
 			break;
 		default:
 			break;
@@ -3564,10 +3564,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 106:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_newstat *";
+			p = "userland struct l_newstat *";
 			break;
 		default:
 			break;
@@ -3577,10 +3577,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 107:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_newstat *";
+			p = "userland struct l_newstat *";
 			break;
 		default:
 			break;
@@ -3593,7 +3593,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_newstat *";
+			p = "userland struct l_newstat *";
 			break;
 		default:
 			break;
@@ -3625,13 +3625,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		case 2:
 			p = "l_int";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -3644,7 +3644,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 116:
 		switch(ndx) {
 		case 0:
-			p = "struct l_sysinfo *";
+			p = "userland struct l_sysinfo *";
 			break;
 		default:
 			break;
@@ -3666,7 +3666,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 5:
 			p = "l_long";
@@ -3689,7 +3689,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 119:
 		switch(ndx) {
 		case 0:
-			p = "struct l_sigframe *";
+			p = "userland struct l_sigframe *";
 			break;
 		default:
 			break;
@@ -3702,16 +3702,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -3721,7 +3721,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 121:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3734,7 +3734,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 122:
 		switch(ndx) {
 		case 0:
-			p = "struct l_new_utsname *";
+			p = "userland struct l_new_utsname *";
 			break;
 		default:
 			break;
@@ -3747,7 +3747,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "l_ulong";
@@ -3782,10 +3782,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_osigset_t *";
+			p = "userland l_osigset_t *";
 			break;
 		case 2:
-			p = "l_osigset_t *";
+			p = "userland l_osigset_t *";
 			break;
 		default:
 			break;
@@ -3888,7 +3888,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_ulong";
 			break;
 		case 3:
-			p = "l_loff_t *";
+			p = "userland l_loff_t *";
 			break;
 		case 4:
 			p = "l_uint";
@@ -3904,7 +3904,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -3920,16 +3920,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 2:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 3:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 4:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		default:
 			break;
@@ -3971,7 +3971,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "u_int";
@@ -3987,7 +3987,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "u_int";
@@ -4020,7 +4020,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 149:
 		switch(ndx) {
 		case 0:
-			p = "struct l___sysctl_args *";
+			p = "userland struct l___sysctl_args *";
 			break;
 		default:
 			break;
@@ -4030,7 +4030,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 150:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4043,7 +4043,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 151:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4072,7 +4072,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -4085,7 +4085,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -4101,7 +4101,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -4147,7 +4147,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -4157,10 +4157,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 162:
 		switch(ndx) {
 		case 0:
-			p = "const struct l_timespec *";
+			p = "userland const struct l_timespec *";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -4208,13 +4208,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 165:
 		switch(ndx) {
 		case 0:
-			p = "l_uid16_t *";
+			p = "userland l_uid16_t *";
 			break;
 		case 1:
-			p = "l_uid16_t *";
+			p = "userland l_uid16_t *";
 			break;
 		case 2:
-			p = "l_uid16_t *";
+			p = "userland l_uid16_t *";
 			break;
 		default:
 			break;
@@ -4230,7 +4230,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 168:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -4265,13 +4265,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 171:
 		switch(ndx) {
 		case 0:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		case 1:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		case 2:
-			p = "l_gid16_t *";
+			p = "userland l_gid16_t *";
 			break;
 		default:
 			break;
@@ -4303,7 +4303,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 173:
 		switch(ndx) {
 		case 0:
-			p = "struct l_ucontext *";
+			p = "userland struct l_ucontext *";
 			break;
 		default:
 			break;
@@ -4316,10 +4316,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_sigaction_t *";
+			p = "userland l_sigaction_t *";
 			break;
 		case 2:
-			p = "l_sigaction_t *";
+			p = "userland l_sigaction_t *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -4335,10 +4335,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 2:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -4351,7 +4351,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 176:
 		switch(ndx) {
 		case 0:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 1:
 			p = "l_size_t";
@@ -4364,13 +4364,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 177:
 		switch(ndx) {
 		case 0:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 1:
-			p = "l_siginfo_t *";
+			p = "userland l_siginfo_t *";
 			break;
 		case 2:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		case 3:
 			p = "l_size_t";
@@ -4389,7 +4389,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "l_siginfo_t *";
+			p = "userland l_siginfo_t *";
 			break;
 		default:
 			break;
@@ -4399,7 +4399,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 179:
 		switch(ndx) {
 		case 0:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 1:
 			p = "l_size_t";
@@ -4415,7 +4415,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_size_t";
@@ -4434,7 +4434,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "l_size_t";
@@ -4450,7 +4450,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 182:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid16_t";
@@ -4466,7 +4466,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 183:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_ulong";
@@ -4479,10 +4479,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 184:
 		switch(ndx) {
 		case 0:
-			p = "struct l_user_cap_header *";
+			p = "userland struct l_user_cap_header *";
 			break;
 		case 1:
-			p = "struct l_user_cap_data *";
+			p = "userland struct l_user_cap_data *";
 			break;
 		default:
 			break;
@@ -4492,10 +4492,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 185:
 		switch(ndx) {
 		case 0:
-			p = "struct l_user_cap_header *";
+			p = "userland struct l_user_cap_header *";
 			break;
 		case 1:
-			p = "struct l_user_cap_data *";
+			p = "userland struct l_user_cap_data *";
 			break;
 		default:
 			break;
@@ -4505,10 +4505,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 186:
 		switch(ndx) {
 		case 0:
-			p = "l_stack_t *";
+			p = "userland l_stack_t *";
 			break;
 		case 1:
-			p = "l_stack_t *";
+			p = "userland l_stack_t *";
 			break;
 		default:
 			break;
@@ -4527,7 +4527,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "struct l_rlimit *";
+			p = "userland struct l_rlimit *";
 			break;
 		default:
 			break;
@@ -4562,7 +4562,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 193:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_loff_t";
@@ -4588,10 +4588,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 195:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
-			p = "struct l_stat64 *";
+			p = "userland struct l_stat64 *";
 			break;
 		default:
 			break;
@@ -4601,10 +4601,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 196:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
-			p = "struct l_stat64 *";
+			p = "userland struct l_stat64 *";
 			break;
 		default:
 			break;
@@ -4617,7 +4617,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_stat64 *";
+			p = "userland struct l_stat64 *";
 			break;
 		default:
 			break;
@@ -4627,7 +4627,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 198:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid_t";
@@ -4684,7 +4684,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_gid_t *";
+			p = "userland l_gid_t *";
 			break;
 		default:
 			break;
@@ -4697,7 +4697,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_gid_t *";
+			p = "userland l_gid_t *";
 			break;
 		default:
 			break;
@@ -4726,13 +4726,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 209:
 		switch(ndx) {
 		case 0:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 1:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 2:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		default:
 			break;
@@ -4758,13 +4758,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 211:
 		switch(ndx) {
 		case 0:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 1:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 2:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		default:
 			break;
@@ -4774,7 +4774,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 212:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "l_uid_t";
@@ -4830,10 +4830,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 217:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4849,7 +4849,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_size_t";
 			break;
 		case 2:
-			p = "u_char *";
+			p = "userland u_char *";
 			break;
 		default:
 			break;
@@ -4859,7 +4859,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 219:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4878,7 +4878,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -4959,7 +4959,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 240:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "int";
@@ -4968,10 +4968,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "uint32_t";
 			break;
 		case 3:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 4:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		case 5:
 			p = "uint32_t";
@@ -4990,7 +4990,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 2:
-			p = "l_ulong *";
+			p = "userland l_ulong *";
 			break;
 		default:
 			break;
@@ -5006,7 +5006,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 2:
-			p = "l_ulong *";
+			p = "userland l_ulong *";
 			break;
 		default:
 			break;
@@ -5016,7 +5016,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 243:
 		switch(ndx) {
 		case 0:
-			p = "struct l_user_desc *";
+			p = "userland struct l_user_desc *";
 			break;
 		default:
 			break;
@@ -5026,7 +5026,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 244:
 		switch(ndx) {
 		case 0:
-			p = "struct l_user_desc *";
+			p = "userland struct l_user_desc *";
 			break;
 		default:
 			break;
@@ -5087,7 +5087,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 3:
-			p = "struct epoll_event *";
+			p = "userland struct epoll_event *";
 			break;
 		default:
 			break;
@@ -5100,7 +5100,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct epoll_event *";
+			p = "userland struct epoll_event *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5119,7 +5119,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 258:
 		switch(ndx) {
 		case 0:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -5132,10 +5132,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct sigevent *";
+			p = "userland struct sigevent *";
 			break;
 		case 2:
-			p = "l_timer_t *";
+			p = "userland l_timer_t *";
 			break;
 		default:
 			break;
@@ -5151,10 +5151,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 2:
-			p = "const struct itimerspec *";
+			p = "userland const struct itimerspec *";
 			break;
 		case 3:
-			p = "struct itimerspec *";
+			p = "userland struct itimerspec *";
 			break;
 		default:
 			break;
@@ -5167,7 +5167,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_timer_t";
 			break;
 		case 1:
-			p = "struct itimerspec *";
+			p = "userland struct itimerspec *";
 			break;
 		default:
 			break;
@@ -5200,7 +5200,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5213,7 +5213,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5226,7 +5226,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5242,10 +5242,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 3:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5255,13 +5255,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 268:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "struct l_statfs64_buf *";
+			p = "userland struct l_statfs64_buf *";
 			break;
 		default:
 			break;
@@ -5277,7 +5277,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "size_t";
 			break;
 		case 2:
-			p = "struct l_statfs64_buf *";
+			p = "userland struct l_statfs64_buf *";
 			break;
 		default:
 			break;
@@ -5303,10 +5303,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 271:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		default:
 			break;
@@ -5344,7 +5344,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 277:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
@@ -5353,7 +5353,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "mode_t";
 			break;
 		case 3:
-			p = "struct mq_attr *";
+			p = "userland struct mq_attr *";
 			break;
 		default:
 			break;
@@ -5363,7 +5363,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 278:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5376,7 +5376,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_mqd_t";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -5385,7 +5385,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "unsigned int";
 			break;
 		case 4:
-			p = "const struct l_timespec *";
+			p = "userland const struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5398,7 +5398,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_mqd_t";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -5407,7 +5407,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "unsigned int";
 			break;
 		case 4:
-			p = "const struct l_timespec *";
+			p = "userland const struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5420,7 +5420,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_mqd_t";
 			break;
 		case 1:
-			p = "const struct l_timespec *";
+			p = "userland const struct l_timespec *";
 			break;
 		default:
 			break;
@@ -5433,10 +5433,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_mqd_t";
 			break;
 		case 1:
-			p = "const struct mq_attr *";
+			p = "userland const struct mq_attr *";
 			break;
 		case 2:
-			p = "struct mq_attr *";
+			p = "userland struct mq_attr *";
 			break;
 		default:
 			break;
@@ -5455,13 +5455,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_pid_t";
 			break;
 		case 2:
-			p = "l_siginfo_t *";
+			p = "userland l_siginfo_t *";
 			break;
 		case 3:
 			p = "int";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -5501,7 +5501,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5520,7 +5520,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5536,7 +5536,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5555,7 +5555,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_uid16_t";
@@ -5577,10 +5577,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct l_timeval *";
+			p = "userland struct l_timeval *";
 			break;
 		default:
 			break;
@@ -5593,10 +5593,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct l_stat64 *";
+			p = "userland struct l_stat64 *";
 			break;
 		case 3:
 			p = "l_int";
@@ -5612,7 +5612,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5628,13 +5628,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
 			break;
 		case 3:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5647,13 +5647,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
 			break;
 		case 3:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 4:
 			p = "l_int";
@@ -5666,13 +5666,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 304:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "l_int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5685,10 +5685,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "l_int";
@@ -5704,7 +5704,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_mode_t";
@@ -5720,7 +5720,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5736,19 +5736,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 2:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 3:
-			p = "l_fd_set *";
+			p = "userland l_fd_set *";
 			break;
 		case 4:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 5:
-			p = "l_uintptr_t *";
+			p = "userland l_uintptr_t *";
 			break;
 		default:
 			break;
@@ -5758,16 +5758,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 309:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "uint32_t";
 			break;
 		case 2:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		case 3:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		case 4:
 			p = "l_size_t";
@@ -5783,7 +5783,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 311:
 		switch(ndx) {
 		case 0:
-			p = "struct linux_robust_list_head *";
+			p = "userland struct linux_robust_list_head *";
 			break;
 		case 1:
 			p = "l_size_t";
@@ -5799,10 +5799,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct linux_robust_list_head **";
+			p = "userland struct linux_robust_list_head **";
 			break;
 		case 2:
-			p = "l_size_t *";
+			p = "userland l_size_t *";
 			break;
 		default:
 			break;
@@ -5833,7 +5833,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct epoll_event *";
+			p = "userland struct epoll_event *";
 			break;
 		case 2:
 			p = "l_int";
@@ -5842,7 +5842,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 4:
-			p = "l_sigset_t *";
+			p = "userland l_sigset_t *";
 			break;
 		default:
 			break;
@@ -5855,10 +5855,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
-			p = "const struct l_timespec *";
+			p = "userland const struct l_timespec *";
 			break;
 		case 3:
 			p = "l_int";
@@ -5954,7 +5954,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 331:
 		switch(ndx) {
 		case 0:
-			p = "l_int *";
+			p = "userland l_int *";
 			break;
 		case 1:
 			p = "l_int";
@@ -5985,7 +5985,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_mmsghdr *";
+			p = "userland struct l_mmsghdr *";
 			break;
 		case 2:
 			p = "l_uint";
@@ -5994,7 +5994,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 4:
-			p = "struct l_timespec *";
+			p = "userland struct l_timespec *";
 			break;
 		default:
 			break;
@@ -6016,10 +6016,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_uint";
 			break;
 		case 2:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		case 3:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		default:
 			break;
@@ -6051,7 +6051,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "l_int";
 			break;
 		case 1:
-			p = "struct l_mmsghdr *";
+			p = "userland struct l_mmsghdr *";
 			break;
 		case 2:
 			p = "l_uint";
diff --git a/sys/kern/kern_descrip.c b/sys/kern/kern_descrip.c
index 5272597021e2..55d5e441f483 100644
--- a/sys/kern/kern_descrip.c
+++ b/sys/kern/kern_descrip.c
@@ -2469,7 +2469,6 @@ fget_cap_locked(struct filedesc *fdp, int fd, cap_rights_t *needrightsp,
 	if (havecapsp != NULL)
 		filecaps_copy(&fde->fde_caps, havecapsp, true);
 
-	fhold(fde->fde_file);
 	*fpp = fde->fde_file;
 
 	error = 0;
@@ -2481,12 +2480,16 @@ int
 fget_cap(struct thread *td, int fd, cap_rights_t *needrightsp,
     struct file **fpp, struct filecaps *havecapsp)
 {
-	struct filedesc *fdp;
-	struct file *fp;
+	struct filedesc *fdp = td->td_proc->p_fd;
 	int error;
+#ifndef CAPABILITIES
+	error = fget_unlocked(fdp, fd, needrightsp, fpp, NULL);
+	if (error == 0 && havecapsp != NULL)
+		filecaps_fill(havecapsp);
+#else
+	struct file *fp;
 	seq_t seq;
 
-	fdp = td->td_proc->p_fd;
 	for (;;) {
 		error = fget_unlocked(fdp, fd, needrightsp, &fp, &seq);
 		if (error != 0)
@@ -2511,8 +2514,10 @@ fget_cap(struct thread *td, int fd, cap_rights_t *needrightsp,
 get_locked:
 	FILEDESC_SLOCK(fdp);
 	error = fget_cap_locked(fdp, fd, needrightsp, fpp, havecapsp);
+	if (error == 0)
+		fhold(*fpp);
 	FILEDESC_SUNLOCK(fdp);
-
+#endif
 	return (error);
 }
 
@@ -2781,30 +2786,31 @@ fgetvp_rights(struct thread *td, int fd, cap_rights_t *needrightsp,
     struct filecaps *havecaps, struct vnode **vpp)
 {
 	struct filedesc *fdp;
+	struct filecaps caps;
 	struct file *fp;
-#ifdef CAPABILITIES
 	int error;
-#endif
 
 	fdp = td->td_proc->p_fd;
-	fp = fget_locked(fdp, fd);
-	if (fp == NULL || fp->f_ops == &badfileops)
-		return (EBADF);
-
-#ifdef CAPABILITIES
-	error = cap_check(cap_rights(fdp, fd), needrightsp);
+	error = fget_cap_locked(fdp, fd, needrightsp, &fp, &caps);
 	if (error != 0)
 		return (error);
-#endif
-
-	if (fp->f_vnode == NULL)
-		return (EINVAL);
+	if (fp->f_ops == &badfileops) {
+		error = EBADF;
+		goto out;
+	}
+	if (fp->f_vnode == NULL) {
+		error = EINVAL;
+		goto out;
+	}
 
+	*havecaps = caps;
 	*vpp = fp->f_vnode;
 	vref(*vpp);
-	filecaps_copy(&fdp->fd_ofiles[fd].fde_caps, havecaps, true);
 
 	return (0);
+out:
+	filecaps_free(&caps);
+	return (error);
 }
 
 int
diff --git a/sys/kern/kern_fork.c b/sys/kern/kern_fork.c
index 557193e08c47..4f8baf8d5a62 100644
--- a/sys/kern/kern_fork.c
+++ b/sys/kern/kern_fork.c
@@ -497,7 +497,7 @@ do_fork(struct thread *td, struct fork_req *fr, struct proc *p2, struct thread *
 	 * Increase reference counts on shared objects.
 	 */
 	p2->p_flag = P_INMEM;
-	p2->p_flag2 = p1->p_flag2 & (P2_NOTRACE | P2_NOTRACE_EXEC);
+	p2->p_flag2 = p1->p_flag2 & (P2_NOTRACE | P2_NOTRACE_EXEC | P2_TRAPCAP);
 	p2->p_swtick = ticks;
 	if (p1->p_flag & P_PROFIL)
 		startprofclock(p2);
diff --git a/sys/kern/kern_lockf.c b/sys/kern/kern_lockf.c
index 6fc8f89cce59..1972b8270900 100644
--- a/sys/kern/kern_lockf.c
+++ b/sys/kern/kern_lockf.c
@@ -83,7 +83,9 @@ __FBSDID("$FreeBSD$");
 #ifdef LOCKF_DEBUG
 #include <sys/sysctl.h>
 
+#include <ufs/ufs/extattr.h>
 #include <ufs/ufs/quota.h>
+#include <ufs/ufs/ufsmount.h>
 #include <ufs/ufs/inode.h>
 
 static int	lockf_debug = 0; /* control debug output */
@@ -2500,7 +2502,7 @@ lf_print(char *tag, struct lockf_entry *lock)
 	if (lock->lf_inode != (struct inode *)0)
 		printf(" in ino %ju on dev <%s>,",
 		    (uintmax_t)lock->lf_inode->i_number,
-		    devtoname(lock->lf_inode->i_dev));
+		    devtoname(ITODEV(lock->lf_inode)));
 	printf(" %s, start %jd, end ",
 	    lock->lf_type == F_RDLCK ? "shared" :
 	    lock->lf_type == F_WRLCK ? "exclusive" :
@@ -2528,7 +2530,7 @@ lf_printlist(char *tag, struct lockf_entry *lock)
 
 	printf("%s: Lock list for ino %ju on dev <%s>:\n",
 	    tag, (uintmax_t)lock->lf_inode->i_number,
-	    devtoname(lock->lf_inode->i_dev));
+	    devtoname(ITODEV(lock->lf_inode)));
 	LIST_FOREACH(lf, &lock->lf_vnode->v_lockf->ls_active, lf_link) {
 		printf("\tlock %p for ",(void *)lf);
 		lf_print_owner(lock->lf_owner);
diff --git a/sys/kern/kern_procctl.c b/sys/kern/kern_procctl.c
index 8ef72901632e..c3d290ae9849 100644
--- a/sys/kern/kern_procctl.c
+++ b/sys/kern/kern_procctl.c
@@ -1,6 +1,6 @@
 /*-
  * Copyright (c) 2014 John Baldwin
- * Copyright (c) 2014 The FreeBSD Foundation
+ * Copyright (c) 2014, 2016 The FreeBSD Foundation
  *
  * Portions of this software were developed by Konstantin Belousov
  * under sponsorship from the FreeBSD Foundation.
@@ -336,6 +336,34 @@ trace_status(struct thread *td, struct proc *p, int *data)
 	return (0);
 }
 
+static int
+trapcap_ctl(struct thread *td, struct proc *p, int state)
+{
+
+	PROC_LOCK_ASSERT(p, MA_OWNED);
+
+	switch (state) {
+	case PROC_TRAPCAP_CTL_ENABLE:
+		p->p_flag2 |= P2_TRAPCAP;
+		break;
+	case PROC_TRAPCAP_CTL_DISABLE:
+		p->p_flag2 &= ~P2_TRAPCAP;
+		break;
+	default:
+		return (EINVAL);
+	}
+	return (0);
+}
+
+static int
+trapcap_status(struct thread *td, struct proc *p, int *data)
+{
+
+	*data = (p->p_flag2 & P2_TRAPCAP) != 0 ? PROC_TRAPCAP_CTL_ENABLE :
+	    PROC_TRAPCAP_CTL_DISABLE;
+	return (0);
+}
+
 #ifndef _SYS_SYSPROTO_H_
 struct procctl_args {
 	idtype_t idtype;
@@ -359,6 +387,7 @@ sys_procctl(struct thread *td, struct procctl_args *uap)
 	switch (uap->com) {
 	case PROC_SPROTECT:
 	case PROC_TRACE_CTL:
+	case PROC_TRAPCAP_CTL:
 		error = copyin(uap->data, &flags, sizeof(flags));
 		if (error != 0)
 			return (error);
@@ -386,6 +415,7 @@ sys_procctl(struct thread *td, struct procctl_args *uap)
 		data = &x.rk;
 		break;
 	case PROC_TRACE_STATUS:
+	case PROC_TRAPCAP_STATUS:
 		data = &flags;
 		break;
 	default:
@@ -403,6 +433,7 @@ sys_procctl(struct thread *td, struct procctl_args *uap)
 			error = error1;
 		break;
 	case PROC_TRACE_STATUS:
+	case PROC_TRAPCAP_STATUS:
 		if (error == 0)
 			error = copyout(&flags, uap->data, sizeof(flags));
 		break;
@@ -432,6 +463,10 @@ kern_procctl_single(struct thread *td, struct proc *p, int com, void *data)
 		return (trace_ctl(td, p, *(int *)data));
 	case PROC_TRACE_STATUS:
 		return (trace_status(td, p, data));
+	case PROC_TRAPCAP_CTL:
+		return (trapcap_ctl(td, p, *(int *)data));
+	case PROC_TRAPCAP_STATUS:
+		return (trapcap_status(td, p, data));
 	default:
 		return (EINVAL);
 	}
@@ -452,6 +487,7 @@ kern_procctl(struct thread *td, idtype_t idtype, id_t id, int com, void *data)
 	case PROC_REAP_GETPIDS:
 	case PROC_REAP_KILL:
 	case PROC_TRACE_STATUS:
+	case PROC_TRAPCAP_STATUS:
 		if (idtype != P_PID)
 			return (EINVAL);
 	}
@@ -462,6 +498,7 @@ kern_procctl(struct thread *td, idtype_t idtype, id_t id, int com, void *data)
 	case PROC_REAP_GETPIDS:
 	case PROC_REAP_KILL:
 	case PROC_TRACE_CTL:
+	case PROC_TRAPCAP_CTL:
 		sx_slock(&proctree_lock);
 		tree_locked = true;
 		break;
@@ -471,6 +508,7 @@ kern_procctl(struct thread *td, idtype_t idtype, id_t id, int com, void *data)
 		tree_locked = true;
 		break;
 	case PROC_TRACE_STATUS:
+	case PROC_TRAPCAP_STATUS:
 		tree_locked = false;
 		break;
 	default:
diff --git a/sys/kern/kern_sendfile.c b/sys/kern/kern_sendfile.c
index c8484b24a196..cac4d3649e64 100644
--- a/sys/kern/kern_sendfile.c
+++ b/sys/kern/kern_sendfile.c
@@ -502,7 +502,7 @@ sendfile_getsock(struct thread *td, int s, struct file **sock_fp,
 	 * The socket must be a stream socket and connected.
 	 */
 	error = getsock_cap(td, s, cap_rights_init(&rights, CAP_SEND),
-	    sock_fp, NULL);
+	    sock_fp, NULL, NULL);
 	if (error != 0)
 		return (error);
 	*so = (*sock_fp)->f_data;
@@ -656,10 +656,18 @@ retry_space:
 		if (hdr_uio != NULL && hdr_uio->uio_resid > 0) {
 			hdr_uio->uio_td = td;
 			hdr_uio->uio_rw = UIO_WRITE;
-			hdr_uio->uio_resid = min(hdr_uio->uio_resid, space);
-			mh = m_uiotombuf(hdr_uio, M_WAITOK, 0, 0, 0);
+			mh = m_uiotombuf(hdr_uio, M_WAITOK, space, 0, 0);
 			hdrlen = m_length(mh, &mhtail);
 			space -= hdrlen;
+			/*
+			 * If header consumed all the socket buffer space,
+			 * don't waste CPU cycles and jump to the end.
+			 */
+			if (space == 0) {
+				sfio = NULL;
+				nios = 0;
+				goto prepend_header;
+			}
 			hdr_uio = NULL;
 		}
 
@@ -806,6 +814,7 @@ retry_space:
 
 		/* Prepend header, if any. */
 		if (hdrlen) {
+prepend_header:
 			mhtail->m_next = m;
 			m = mh;
 			mh = NULL;
diff --git a/sys/kern/makesyscalls.sh b/sys/kern/makesyscalls.sh
index b5215bdbc8d4..896eb04753ca 100644
--- a/sys/kern/makesyscalls.sh
+++ b/sys/kern/makesyscalls.sh
@@ -418,7 +418,10 @@ s/\$//g
 			for (i = 1; i <= argc; i++) {
 				arg = argtype[i]
 				sub("__restrict$", "", arg)
-				printf("\t\tcase %d:\n\t\t\tp = \"%s\";\n\t\t\tbreak;\n", i - 1, arg) > systracetmp
+				if (index(arg, "*") > 0)
+					printf("\t\tcase %d:\n\t\t\tp = \"userland %s\";\n\t\t\tbreak;\n", i - 1, arg) > systracetmp
+				else
+					printf("\t\tcase %d:\n\t\t\tp = \"%s\";\n\t\t\tbreak;\n", i - 1, arg) > systracetmp
 				if (index(arg, "*") > 0 || arg == "caddr_t")
 					printf("\t\tuarg[%d] = (intptr_t) p->%s; /* %s */\n", \
 					     i - 1, \
diff --git a/sys/kern/subr_rtc.c b/sys/kern/subr_rtc.c
index 063c5bbddc3b..538708c5a314 100644
--- a/sys/kern/subr_rtc.c
+++ b/sys/kern/subr_rtc.c
@@ -75,7 +75,7 @@ __FBSDID("$FreeBSD$");
 static device_t clock_dev = NULL;
 static long clock_res;
 static struct timespec clock_adj;
-static struct mtx resettodr_lock;
+struct mtx resettodr_lock;
 MTX_SYSINIT(resettodr_init, &resettodr_lock, "tod2rl", MTX_DEF);
 
 /* XXX: should be kern. now, it's no longer machdep.  */
@@ -132,7 +132,9 @@ inittodr(time_t base)
 		goto wrong_time;
 	}
 	/* XXX: We should poll all registered RTCs in case of failure */
+	mtx_lock(&resettodr_lock);
 	error = CLOCK_GETTIME(clock_dev, &ts);
+	mtx_unlock(&resettodr_lock);
 	if (error != 0 && error != EINVAL) {
 		printf("warning: clock_gettime failed (%d), the system time "
 		    "will not be set accurately\n", error);
diff --git a/sys/kern/subr_syscall.c b/sys/kern/subr_syscall.c
index 3e2a3b3b748e..822976edf392 100644
--- a/sys/kern/subr_syscall.c
+++ b/sys/kern/subr_syscall.c
@@ -165,12 +165,25 @@ static inline void
 syscallret(struct thread *td, int error, struct syscall_args *sa)
 {
 	struct proc *p, *p2;
-	int traced;
+	ksiginfo_t ksi;
+	int traced, error1;
 
 	KASSERT((td->td_pflags & TDP_FORKING) == 0,
 	    ("fork() did not clear TDP_FORKING upon completion"));
 
 	p = td->td_proc;
+	if ((trap_enotcap || (p->p_flag2 & P2_TRAPCAP) != 0) &&
+	    IN_CAPABILITY_MODE(td)) {
+		error1 = (td->td_pflags & TDP_NERRNO) == 0 ? error :
+		    td->td_errno;
+		if (error1 == ENOTCAPABLE || error1 == ECAPMODE) {
+			ksiginfo_init_trap(&ksi);
+			ksi.ksi_signo = SIGTRAP;
+			ksi.ksi_errno = error1;
+			ksi.ksi_code = TRAP_CAP;
+			trapsignal(td, &ksi);
+		}
+	}
 
 	/*
 	 * Handle reschedule and other end-of-syscall issues
diff --git a/sys/kern/subr_witness.c b/sys/kern/subr_witness.c
index ed1203578c2c..a916bdd4be8e 100644
--- a/sys/kern/subr_witness.c
+++ b/sys/kern/subr_witness.c
@@ -625,7 +625,7 @@ static struct witness_order_list_entry order_lists[] = {
 	/*
 	 * VFS namecache
 	 */
-	{ "ncglobal", &lock_class_rw },
+	{ "ncvn", &lock_class_mtx_sleep },
 	{ "ncbuc", &lock_class_rw },
 	{ "vnode interlock", &lock_class_mtx_sleep },
 	{ "ncneg", &lock_class_mtx_sleep },
diff --git a/sys/kern/sys_capability.c b/sys/kern/sys_capability.c
index b8ac5dd315d9..65fc9ab514eb 100644
--- a/sys/kern/sys_capability.c
+++ b/sys/kern/sys_capability.c
@@ -83,6 +83,10 @@ __FBSDID("$FreeBSD$");
 #include <vm/uma.h>
 #include <vm/vm.h>
 
+int trap_enotcap;
+SYSCTL_INT(_kern, OID_AUTO, trap_enotcap, CTLFLAG_RW, &trap_enotcap, 0,
+    "Deliver SIGTRAP on ENOTCAPABLE");
+
 #ifdef CAPABILITY_MODE
 
 FEATURE(security_capability_mode, "Capsicum Capability Mode");
diff --git a/sys/kern/systrace_args.c b/sys/kern/systrace_args.c
index c6fe8e5a44d9..174430c0fd53 100644
--- a/sys/kern/systrace_args.c
+++ b/sys/kern/systrace_args.c
@@ -3357,7 +3357,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -3373,7 +3373,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -3386,7 +3386,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 5:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3415,13 +3415,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "struct rusage *";
+			p = "userland struct rusage *";
 			break;
 		default:
 			break;
@@ -3431,10 +3431,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 9:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3444,7 +3444,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 10:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3454,7 +3454,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 12:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3474,7 +3474,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 14:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3490,7 +3490,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 15:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3503,7 +3503,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 16:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3519,7 +3519,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 17:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3532,10 +3532,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 21:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
@@ -3551,7 +3551,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 22:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3602,7 +3602,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct msghdr *";
+			p = "userland struct msghdr *";
 			break;
 		case 2:
 			p = "int";
@@ -3618,7 +3618,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct msghdr *";
+			p = "userland struct msghdr *";
 			break;
 		case 2:
 			p = "int";
@@ -3643,10 +3643,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 4:
-			p = "struct sockaddr *";
+			p = "userland struct sockaddr *";
 			break;
 		case 5:
-			p = "__socklen_t *";
+			p = "userland __socklen_t *";
 			break;
 		default:
 			break;
@@ -3659,10 +3659,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct sockaddr *";
+			p = "userland struct sockaddr *";
 			break;
 		case 2:
-			p = "__socklen_t *";
+			p = "userland __socklen_t *";
 			break;
 		default:
 			break;
@@ -3675,10 +3675,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct sockaddr *";
+			p = "userland struct sockaddr *";
 			break;
 		case 2:
-			p = "__socklen_t *";
+			p = "userland __socklen_t *";
 			break;
 		default:
 			break;
@@ -3691,10 +3691,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct sockaddr *";
+			p = "userland struct sockaddr *";
 			break;
 		case 2:
-			p = "__socklen_t *";
+			p = "userland __socklen_t *";
 			break;
 		default:
 			break;
@@ -3704,7 +3704,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 33:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -3717,7 +3717,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 34:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "u_long";
@@ -3794,7 +3794,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 45:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
@@ -3816,7 +3816,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 49:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "u_int";
@@ -3829,7 +3829,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 50:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3839,7 +3839,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 51:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3849,10 +3849,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 53:
 		switch(ndx) {
 		case 0:
-			p = "stack_t *";
+			p = "userland stack_t *";
 			break;
 		case 1:
-			p = "stack_t *";
+			p = "userland stack_t *";
 			break;
 		default:
 			break;
@@ -3888,7 +3888,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 56:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3898,10 +3898,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 57:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3911,10 +3911,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 58:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -3927,13 +3927,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 59:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char **";
+			p = "userland char **";
 			break;
 		case 2:
-			p = "char **";
+			p = "userland char **";
 			break;
 		default:
 			break;
@@ -3953,7 +3953,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 61:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -3963,7 +3963,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 65:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4012,7 +4012,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 73:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4025,7 +4025,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 74:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4041,7 +4041,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 75:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4057,13 +4057,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 78:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4076,7 +4076,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		default:
 			break;
@@ -4089,7 +4089,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		default:
 			break;
@@ -4118,10 +4118,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "struct itimerval *";
+			p = "userland struct itimerval *";
 			break;
 		case 2:
-			p = "struct itimerval *";
+			p = "userland struct itimerval *";
 			break;
 		default:
 			break;
@@ -4131,7 +4131,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 85:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4144,7 +4144,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "struct itimerval *";
+			p = "userland struct itimerval *";
 			break;
 		default:
 			break;
@@ -4189,16 +4189,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 2:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 3:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 4:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		default:
 			break;
@@ -4330,10 +4330,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 116:
 		switch(ndx) {
 		case 0:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -4346,7 +4346,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct rusage *";
+			p = "userland struct rusage *";
 			break;
 		default:
 			break;
@@ -4368,7 +4368,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "caddr_t";
 			break;
 		case 4:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -4381,7 +4381,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "u_int";
@@ -4397,7 +4397,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "u_int";
@@ -4410,10 +4410,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 122:
 		switch(ndx) {
 		case 0:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		case 1:
-			p = "struct timezone *";
+			p = "userland struct timezone *";
 			break;
 		default:
 			break;
@@ -4478,10 +4478,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 128:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4504,7 +4504,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 132:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -4564,7 +4564,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 3:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -4574,7 +4574,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 136:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -4587,7 +4587,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 137:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4597,10 +4597,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 138:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		default:
 			break;
@@ -4610,10 +4610,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 140:
 		switch(ndx) {
 		case 0:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		case 1:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		default:
 			break;
@@ -4626,7 +4626,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 148:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -4654,7 +4654,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 3:
-			p = "char **";
+			p = "userland char **";
 			break;
 		default:
 			break;
@@ -4677,10 +4677,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 160:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct fhandle *";
+			p = "userland struct fhandle *";
 			break;
 		default:
 			break;
@@ -4690,10 +4690,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 161:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct fhandle *";
+			p = "userland struct fhandle *";
 			break;
 		default:
 			break;
@@ -4706,7 +4706,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -4722,7 +4722,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "pid_t";
 			break;
 		case 2:
-			p = "struct rtprio *";
+			p = "userland struct rtprio *";
 			break;
 		default:
 			break;
@@ -4808,7 +4808,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 176:
 		switch(ndx) {
 		case 0:
-			p = "struct timex *";
+			p = "userland struct timex *";
 			break;
 		default:
 			break;
@@ -4848,10 +4848,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 188:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct stat *";
+			p = "userland struct stat *";
 			break;
 		default:
 			break;
@@ -4864,7 +4864,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct stat *";
+			p = "userland struct stat *";
 			break;
 		default:
 			break;
@@ -4874,10 +4874,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 190:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct stat *";
+			p = "userland struct stat *";
 			break;
 		default:
 			break;
@@ -4887,7 +4887,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 191:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -4916,7 +4916,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		default:
 			break;
@@ -4929,7 +4929,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_int";
 			break;
 		case 1:
-			p = "struct rlimit *";
+			p = "userland struct rlimit *";
 			break;
 		default:
 			break;
@@ -4942,13 +4942,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "u_int";
 			break;
 		case 3:
-			p = "long *";
+			p = "userland long *";
 			break;
 		default:
 			break;
@@ -4961,19 +4961,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 202:
 		switch(ndx) {
 		case 0:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 1:
 			p = "u_int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
-			p = "size_t *";
+			p = "userland size_t *";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 5:
 			p = "size_t";
@@ -4986,7 +4986,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 203:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -4999,7 +4999,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 204:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -5012,7 +5012,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 205:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -5025,7 +5025,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		default:
 			break;
@@ -5045,7 +5045,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 209:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "u_int";
@@ -5110,7 +5110,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct sembuf *";
+			p = "userland struct sembuf *";
 			break;
 		case 2:
 			p = "size_t";
@@ -5139,7 +5139,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -5158,7 +5158,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -5180,7 +5180,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 2:
 			p = "int";
@@ -5193,7 +5193,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 230:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		default:
 			break;
@@ -5222,7 +5222,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		default:
 			break;
@@ -5235,7 +5235,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		default:
 			break;
@@ -5248,7 +5248,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		default:
 			break;
@@ -5261,10 +5261,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "clockid_t";
 			break;
 		case 1:
-			p = "struct sigevent *";
+			p = "userland struct sigevent *";
 			break;
 		case 2:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -5290,10 +5290,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const struct itimerspec *";
+			p = "userland const struct itimerspec *";
 			break;
 		case 3:
-			p = "struct itimerspec *";
+			p = "userland struct itimerspec *";
 			break;
 		default:
 			break;
@@ -5306,7 +5306,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct itimerspec *";
+			p = "userland struct itimerspec *";
 			break;
 		default:
 			break;
@@ -5326,10 +5326,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 240:
 		switch(ndx) {
 		case 0:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		case 1:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		default:
 			break;
@@ -5339,7 +5339,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 241:
 		switch(ndx) {
 		case 0:
-			p = "ffcounter *";
+			p = "userland ffcounter *";
 			break;
 		default:
 			break;
@@ -5349,7 +5349,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 242:
 		switch(ndx) {
 		case 0:
-			p = "struct ffclock_estimate *";
+			p = "userland struct ffclock_estimate *";
 			break;
 		default:
 			break;
@@ -5359,7 +5359,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 243:
 		switch(ndx) {
 		case 0:
-			p = "struct ffclock_estimate *";
+			p = "userland struct ffclock_estimate *";
 			break;
 		default:
 			break;
@@ -5375,7 +5375,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "clockid_t *";
+			p = "userland clockid_t *";
 			break;
 		default:
 			break;
@@ -5385,7 +5385,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 248:
 		switch(ndx) {
 		case 0:
-			p = "struct ntptimeval *";
+			p = "userland struct ntptimeval *";
 			break;
 		default:
 			break;
@@ -5395,7 +5395,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 250:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -5424,7 +5424,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 254:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -5440,7 +5440,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 255:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb *";
+			p = "userland struct aiocb *";
 			break;
 		default:
 			break;
@@ -5450,7 +5450,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 256:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb *";
+			p = "userland struct aiocb *";
 			break;
 		default:
 			break;
@@ -5463,13 +5463,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct aiocb *const *";
+			p = "userland struct aiocb *const *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "struct sigevent *";
+			p = "userland struct sigevent *";
 			break;
 		default:
 			break;
@@ -5482,7 +5482,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -5495,7 +5495,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 274:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "mode_t";
@@ -5508,7 +5508,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 275:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "uid_t";
@@ -5524,10 +5524,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 276:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		default:
 			break;
@@ -5537,7 +5537,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 277:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -5553,10 +5553,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 278:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct nstat *";
+			p = "userland struct nstat *";
 			break;
 		default:
 			break;
@@ -5569,7 +5569,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct nstat *";
+			p = "userland struct nstat *";
 			break;
 		default:
 			break;
@@ -5579,10 +5579,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 280:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct nstat *";
+			p = "userland struct nstat *";
 			break;
 		default:
 			break;
@@ -5595,7 +5595,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "u_int";
@@ -5614,7 +5614,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "u_int";
@@ -5630,7 +5630,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 298:
 		switch(ndx) {
 		case 0:
-			p = "const struct fhandle *";
+			p = "userland const struct fhandle *";
 			break;
 		case 1:
 			p = "int";
@@ -5643,10 +5643,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 299:
 		switch(ndx) {
 		case 0:
-			p = "const struct fhandle *";
+			p = "userland const struct fhandle *";
 			break;
 		case 1:
-			p = "struct stat *";
+			p = "userland struct stat *";
 			break;
 		default:
 			break;
@@ -5669,7 +5669,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct module_stat *";
+			p = "userland struct module_stat *";
 			break;
 		default:
 			break;
@@ -5689,7 +5689,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 303:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5699,7 +5699,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 304:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5719,7 +5719,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 306:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -5742,7 +5742,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct kld_file_stat *";
+			p = "userland struct kld_file_stat *";
 			break;
 		default:
 			break;
@@ -5804,7 +5804,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 314:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb *";
+			p = "userland struct aiocb *";
 			break;
 		default:
 			break;
@@ -5814,13 +5814,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 315:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb *const *";
+			p = "userland struct aiocb *const *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		default:
 			break;
@@ -5833,7 +5833,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct aiocb *";
+			p = "userland struct aiocb *";
 			break;
 		default:
 			break;
@@ -5843,7 +5843,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 317:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb *";
+			p = "userland struct aiocb *";
 			break;
 		default:
 			break;
@@ -5869,7 +5869,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 326:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "u_int";
@@ -5885,7 +5885,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "pid_t";
 			break;
 		case 1:
-			p = "const struct sched_param *";
+			p = "userland const struct sched_param *";
 			break;
 		default:
 			break;
@@ -5898,7 +5898,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "pid_t";
 			break;
 		case 1:
-			p = "struct sched_param *";
+			p = "userland struct sched_param *";
 			break;
 		default:
 			break;
@@ -5914,7 +5914,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const struct sched_param *";
+			p = "userland const struct sched_param *";
 			break;
 		default:
 			break;
@@ -5960,7 +5960,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "pid_t";
 			break;
 		case 1:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		default:
 			break;
@@ -5970,7 +5970,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 335:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
@@ -5989,7 +5989,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -5999,7 +5999,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 338:
 		switch(ndx) {
 		case 0:
-			p = "struct jail *";
+			p = "userland struct jail *";
 			break;
 		default:
 			break;
@@ -6012,13 +6012,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "int";
@@ -6034,10 +6034,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		case 2:
-			p = "sigset_t *";
+			p = "userland sigset_t *";
 			break;
 		default:
 			break;
@@ -6047,7 +6047,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 341:
 		switch(ndx) {
 		case 0:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		default:
 			break;
@@ -6057,7 +6057,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 343:
 		switch(ndx) {
 		case 0:
-			p = "sigset_t *";
+			p = "userland sigset_t *";
 			break;
 		default:
 			break;
@@ -6067,13 +6067,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 345:
 		switch(ndx) {
 		case 0:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		case 1:
-			p = "siginfo_t *";
+			p = "userland siginfo_t *";
 			break;
 		case 2:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		default:
 			break;
@@ -6083,10 +6083,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 346:
 		switch(ndx) {
 		case 0:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		case 1:
-			p = "siginfo_t *";
+			p = "userland siginfo_t *";
 			break;
 		default:
 			break;
@@ -6096,13 +6096,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 347:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6112,13 +6112,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 348:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6134,7 +6134,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6150,7 +6150,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6160,7 +6160,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 351:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
@@ -6186,13 +6186,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 353:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6208,7 +6208,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -6218,19 +6218,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 355:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
 			p = "int";
 			break;
 		case 4:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6240,16 +6240,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 356:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6262,16 +6262,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 357:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6284,13 +6284,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 358:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6300,10 +6300,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 359:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb **";
+			p = "userland struct aiocb **";
 			break;
 		case 1:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		default:
 			break;
@@ -6313,13 +6313,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 360:
 		switch(ndx) {
 		case 0:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 1:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		case 2:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		default:
 			break;
@@ -6329,13 +6329,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 361:
 		switch(ndx) {
 		case 0:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 1:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		case 2:
-			p = "gid_t *";
+			p = "userland gid_t *";
 			break;
 		default:
 			break;
@@ -6351,19 +6351,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct kevent *";
+			p = "userland struct kevent *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "struct kevent *";
+			p = "userland struct kevent *";
 			break;
 		case 4:
 			p = "int";
 			break;
 		case 5:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		default:
 			break;
@@ -6379,10 +6379,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6401,10 +6401,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6423,7 +6423,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6443,7 +6443,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 376:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -6484,7 +6484,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 378:
 		switch(ndx) {
 		case 0:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -6500,7 +6500,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 384:
 		switch(ndx) {
 		case 0:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6510,7 +6510,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 385:
 		switch(ndx) {
 		case 0:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6523,7 +6523,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6533,10 +6533,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 387:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6549,7 +6549,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6559,10 +6559,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 389:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6575,10 +6575,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "int";
@@ -6591,7 +6591,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 391:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "u_long";
@@ -6604,7 +6604,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 392:
 		switch(ndx) {
 		case 0:
-			p = "struct uuid *";
+			p = "userland struct uuid *";
 			break;
 		case 1:
 			p = "int";
@@ -6629,10 +6629,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "size_t";
 			break;
 		case 4:
-			p = "struct sf_hdtr *";
+			p = "userland struct sf_hdtr *";
 			break;
 		case 5:
-			p = "off_t *";
+			p = "userland off_t *";
 			break;
 		case 6:
 			p = "int";
@@ -6645,13 +6645,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 394:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -6661,7 +6661,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 395:
 		switch(ndx) {
 		case 0:
-			p = "struct statfs *";
+			p = "userland struct statfs *";
 			break;
 		case 1:
 			p = "long";
@@ -6677,10 +6677,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 396:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "struct statfs *";
+			p = "userland struct statfs *";
 			break;
 		default:
 			break;
@@ -6693,7 +6693,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct statfs *";
+			p = "userland struct statfs *";
 			break;
 		default:
 			break;
@@ -6703,10 +6703,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 398:
 		switch(ndx) {
 		case 0:
-			p = "const struct fhandle *";
+			p = "userland const struct fhandle *";
 			break;
 		case 1:
-			p = "struct statfs *";
+			p = "userland struct statfs *";
 			break;
 		default:
 			break;
@@ -6756,7 +6756,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 404:
 		switch(ndx) {
 		case 0:
-			p = "semid_t *";
+			p = "userland semid_t *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -6769,10 +6769,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 405:
 		switch(ndx) {
 		case 0:
-			p = "semid_t *";
+			p = "userland semid_t *";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "int";
@@ -6791,7 +6791,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 406:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6804,7 +6804,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "semid_t";
 			break;
 		case 1:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -6827,7 +6827,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "pid_t";
 			break;
 		case 1:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6837,10 +6837,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 410:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6850,10 +6850,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 411:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6863,16 +6863,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 412:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6885,16 +6885,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 413:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
 			p = "size_t";
@@ -6907,13 +6907,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 414:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -6923,16 +6923,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 415:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
-			p = "char **";
+			p = "userland char **";
 			break;
 		case 2:
-			p = "char **";
+			p = "userland char **";
 			break;
 		case 3:
-			p = "struct mac *";
+			p = "userland struct mac *";
 			break;
 		default:
 			break;
@@ -6945,10 +6945,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const struct sigaction *";
+			p = "userland const struct sigaction *";
 			break;
 		case 2:
-			p = "struct sigaction *";
+			p = "userland struct sigaction *";
 			break;
 		default:
 			break;
@@ -6958,7 +6958,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 417:
 		switch(ndx) {
 		case 0:
-			p = "const struct __ucontext *";
+			p = "userland const struct __ucontext *";
 			break;
 		default:
 			break;
@@ -6968,7 +6968,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 421:
 		switch(ndx) {
 		case 0:
-			p = "struct __ucontext *";
+			p = "userland struct __ucontext *";
 			break;
 		default:
 			break;
@@ -6978,7 +6978,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 422:
 		switch(ndx) {
 		case 0:
-			p = "const struct __ucontext *";
+			p = "userland const struct __ucontext *";
 			break;
 		default:
 			break;
@@ -6988,10 +6988,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 423:
 		switch(ndx) {
 		case 0:
-			p = "struct __ucontext *";
+			p = "userland struct __ucontext *";
 			break;
 		case 1:
-			p = "const struct __ucontext *";
+			p = "userland const struct __ucontext *";
 			break;
 		default:
 			break;
@@ -7001,7 +7001,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 424:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -7011,13 +7011,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 425:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -7027,13 +7027,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 426:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -7043,7 +7043,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 427:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
@@ -7056,13 +7056,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 428:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "acl_type_t";
 			break;
 		case 2:
-			p = "struct acl *";
+			p = "userland struct acl *";
 			break;
 		default:
 			break;
@@ -7072,10 +7072,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 429:
 		switch(ndx) {
 		case 0:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		case 1:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -7085,10 +7085,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 430:
 		switch(ndx) {
 		case 0:
-			p = "ucontext_t *";
+			p = "userland ucontext_t *";
 			break;
 		case 1:
-			p = "long *";
+			p = "userland long *";
 			break;
 		case 2:
 			p = "int";
@@ -7101,7 +7101,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 431:
 		switch(ndx) {
 		case 0:
-			p = "long *";
+			p = "userland long *";
 			break;
 		default:
 			break;
@@ -7111,7 +7111,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 432:
 		switch(ndx) {
 		case 0:
-			p = "long *";
+			p = "userland long *";
 			break;
 		default:
 			break;
@@ -7150,7 +7150,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -7163,13 +7163,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 438:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -7182,13 +7182,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 439:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -7204,7 +7204,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "semid_t";
 			break;
 		case 1:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		default:
 			break;
@@ -7214,7 +7214,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 442:
 		switch(ndx) {
 		case 0:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		default:
 			break;
@@ -7247,7 +7247,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 445:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "u_int";
@@ -7263,7 +7263,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "u_int";
@@ -7276,7 +7276,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 447:
 		switch(ndx) {
 		case 0:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		default:
 			break;
@@ -7286,7 +7286,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 448:
 		switch(ndx) {
 		case 0:
-			p = "uid_t *";
+			p = "userland uid_t *";
 			break;
 		default:
 			break;
@@ -7296,7 +7296,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 449:
 		switch(ndx) {
 		case 0:
-			p = "struct auditinfo *";
+			p = "userland struct auditinfo *";
 			break;
 		default:
 			break;
@@ -7306,7 +7306,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 450:
 		switch(ndx) {
 		case 0:
-			p = "struct auditinfo *";
+			p = "userland struct auditinfo *";
 			break;
 		default:
 			break;
@@ -7316,7 +7316,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 451:
 		switch(ndx) {
 		case 0:
-			p = "struct auditinfo_addr *";
+			p = "userland struct auditinfo_addr *";
 			break;
 		case 1:
 			p = "u_int";
@@ -7329,7 +7329,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 452:
 		switch(ndx) {
 		case 0:
-			p = "struct auditinfo_addr *";
+			p = "userland struct auditinfo_addr *";
 			break;
 		case 1:
 			p = "u_int";
@@ -7342,7 +7342,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 453:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -7352,7 +7352,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 454:
 		switch(ndx) {
 		case 0:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 1:
 			p = "int";
@@ -7361,10 +7361,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "u_long";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 4:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -7374,7 +7374,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 455:
 		switch(ndx) {
 		case 0:
-			p = "struct thr_param *";
+			p = "userland struct thr_param *";
 			break;
 		case 1:
 			p = "int";
@@ -7393,7 +7393,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -7403,7 +7403,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 457:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
@@ -7412,7 +7412,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "mode_t";
 			break;
 		case 3:
-			p = "const struct mq_attr *";
+			p = "userland const struct mq_attr *";
 			break;
 		default:
 			break;
@@ -7425,10 +7425,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const struct mq_attr *";
+			p = "userland const struct mq_attr *";
 			break;
 		case 2:
-			p = "struct mq_attr *";
+			p = "userland struct mq_attr *";
 			break;
 		default:
 			break;
@@ -7441,16 +7441,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "size_t";
 			break;
 		case 3:
-			p = "unsigned *";
+			p = "userland unsigned *";
 			break;
 		case 4:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		default:
 			break;
@@ -7463,7 +7463,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "size_t";
@@ -7472,7 +7472,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "unsigned";
 			break;
 		case 4:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		default:
 			break;
@@ -7485,7 +7485,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const struct sigevent *";
+			p = "userland const struct sigevent *";
 			break;
 		default:
 			break;
@@ -7495,7 +7495,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 462:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -7505,13 +7505,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 463:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "void **";
+			p = "userland void **";
 			break;
 		default:
 			break;
@@ -7524,7 +7524,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "long";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -7537,7 +7537,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct aiocb *";
+			p = "userland struct aiocb *";
 			break;
 		default:
 			break;
@@ -7553,7 +7553,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "lwpid_t";
 			break;
 		case 2:
-			p = "struct rtprio *";
+			p = "userland struct rtprio *";
 			break;
 		default:
 			break;
@@ -7591,7 +7591,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "__socklen_t";
 			break;
 		case 5:
-			p = "struct sctp_sndrcvinfo *";
+			p = "userland struct sctp_sndrcvinfo *";
 			break;
 		case 6:
 			p = "int";
@@ -7607,7 +7607,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "int";
@@ -7619,7 +7619,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "__socklen_t";
 			break;
 		case 5:
-			p = "struct sctp_sndrcvinfo *";
+			p = "userland struct sctp_sndrcvinfo *";
 			break;
 		case 6:
 			p = "int";
@@ -7635,22 +7635,22 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "struct sockaddr *";
+			p = "userland struct sockaddr *";
 			break;
 		case 4:
-			p = "__socklen_t *";
+			p = "userland __socklen_t *";
 			break;
 		case 5:
-			p = "struct sctp_sndrcvinfo *";
+			p = "userland struct sctp_sndrcvinfo *";
 			break;
 		case 6:
-			p = "int *";
+			p = "userland int *";
 			break;
 		default:
 			break;
@@ -7663,7 +7663,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -7682,7 +7682,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 2:
 			p = "size_t";
@@ -7739,7 +7739,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 479:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "off_t";
@@ -7781,7 +7781,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 482:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 1:
 			p = "int";
@@ -7797,7 +7797,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 483:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -7807,7 +7807,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 484:
 		switch(ndx) {
 		case 0:
-			p = "cpusetid_t *";
+			p = "userland cpusetid_t *";
 			break;
 		default:
 			break;
@@ -7842,7 +7842,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "id_t";
 			break;
 		case 3:
-			p = "cpusetid_t *";
+			p = "userland cpusetid_t *";
 			break;
 		default:
 			break;
@@ -7864,7 +7864,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "size_t";
 			break;
 		case 4:
-			p = "cpuset_t *";
+			p = "userland cpuset_t *";
 			break;
 		default:
 			break;
@@ -7886,7 +7886,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "size_t";
 			break;
 		case 4:
-			p = "const cpuset_t *";
+			p = "userland const cpuset_t *";
 			break;
 		default:
 			break;
@@ -7899,7 +7899,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
@@ -7918,7 +7918,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "mode_t";
@@ -7937,7 +7937,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "uid_t";
@@ -7959,10 +7959,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char **";
+			p = "userland char **";
 			break;
 		case 2:
-			p = "char **";
+			p = "userland char **";
 			break;
 		default:
 			break;
@@ -7975,10 +7975,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct stat *";
+			p = "userland struct stat *";
 			break;
 		case 3:
 			p = "int";
@@ -7994,10 +7994,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct timeval *";
+			p = "userland struct timeval *";
 			break;
 		default:
 			break;
@@ -8010,13 +8010,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 4:
 			p = "int";
@@ -8032,7 +8032,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "mode_t";
@@ -8048,7 +8048,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "mode_t";
@@ -8064,7 +8064,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "mode_t";
@@ -8083,7 +8083,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
@@ -8102,10 +8102,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8121,13 +8121,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
 			break;
 		case 3:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -8137,13 +8137,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 502:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
 			break;
 		case 2:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -8156,7 +8156,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
 			p = "int";
@@ -8179,7 +8179,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 505:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		default:
 			break;
@@ -8189,7 +8189,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 506:
 		switch(ndx) {
 		case 0:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -8205,7 +8205,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 507:
 		switch(ndx) {
 		case 0:
-			p = "struct iovec *";
+			p = "userland struct iovec *";
 			break;
 		case 1:
 			p = "unsigned int";
@@ -8250,7 +8250,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 3:
-			p = "union semun *";
+			p = "userland union semun *";
 			break;
 		default:
 			break;
@@ -8266,7 +8266,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "struct msqid_ds *";
+			p = "userland struct msqid_ds *";
 			break;
 		default:
 			break;
@@ -8282,7 +8282,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "struct shmid_ds *";
+			p = "userland struct shmid_ds *";
 			break;
 		default:
 			break;
@@ -8292,7 +8292,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 513:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "int";
@@ -8311,7 +8311,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 2:
-			p = "cap_rights_t *";
+			p = "userland cap_rights_t *";
 			break;
 		default:
 			break;
@@ -8324,7 +8324,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 517:
 		switch(ndx) {
 		case 0:
-			p = "u_int *";
+			p = "userland u_int *";
 			break;
 		default:
 			break;
@@ -8334,7 +8334,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 518:
 		switch(ndx) {
 		case 0:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 1:
 			p = "int";
@@ -8363,7 +8363,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "pid_t *";
+			p = "userland pid_t *";
 			break;
 		default:
 			break;
@@ -8376,19 +8376,19 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 2:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 3:
-			p = "fd_set *";
+			p = "userland fd_set *";
 			break;
 		case 4:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		case 5:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		default:
 			break;
@@ -8398,7 +8398,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 523:
 		switch(ndx) {
 		case 0:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 1:
 			p = "size_t";
@@ -8411,7 +8411,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 524:
 		switch(ndx) {
 		case 0:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		default:
 			break;
@@ -8421,13 +8421,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 525:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8440,13 +8440,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 526:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8459,13 +8459,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 527:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8478,13 +8478,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 528:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8497,13 +8497,13 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 529:
 		switch(ndx) {
 		case 0:
-			p = "const void *";
+			p = "userland const void *";
 			break;
 		case 1:
 			p = "size_t";
 			break;
 		case 2:
-			p = "void *";
+			p = "userland void *";
 			break;
 		case 3:
 			p = "size_t";
@@ -8557,16 +8557,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "id_t";
 			break;
 		case 2:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 3:
 			p = "int";
 			break;
 		case 4:
-			p = "struct __wrusage *";
+			p = "userland struct __wrusage *";
 			break;
 		case 5:
-			p = "siginfo_t *";
+			p = "userland siginfo_t *";
 			break;
 		default:
 			break;
@@ -8579,7 +8579,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "cap_rights_t *";
+			p = "userland cap_rights_t *";
 			break;
 		default:
 			break;
@@ -8592,7 +8592,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const u_long *";
+			p = "userland const u_long *";
 			break;
 		case 2:
 			p = "size_t";
@@ -8608,7 +8608,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "u_long *";
+			p = "userland u_long *";
 			break;
 		case 2:
 			p = "size_t";
@@ -8637,7 +8637,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "uint32_t *";
+			p = "userland uint32_t *";
 			break;
 		default:
 			break;
@@ -8688,7 +8688,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "const char *";
+			p = "userland const char *";
 			break;
 		case 2:
 			p = "u_long";
@@ -8707,10 +8707,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct sockaddr *";
+			p = "userland struct sockaddr *";
 			break;
 		case 2:
-			p = "__socklen_t *";
+			p = "userland __socklen_t *";
 			break;
 		case 3:
 			p = "int";
@@ -8723,7 +8723,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 542:
 		switch(ndx) {
 		case 0:
-			p = "int *";
+			p = "userland int *";
 			break;
 		case 1:
 			p = "int";
@@ -8736,7 +8736,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 543:
 		switch(ndx) {
 		case 0:
-			p = "struct aiocb *";
+			p = "userland struct aiocb *";
 			break;
 		default:
 			break;
@@ -8755,7 +8755,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 3:
-			p = "void *";
+			p = "userland void *";
 			break;
 		default:
 			break;
@@ -8765,16 +8765,16 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 	case 545:
 		switch(ndx) {
 		case 0:
-			p = "struct pollfd *";
+			p = "userland struct pollfd *";
 			break;
 		case 1:
 			p = "u_int";
 			break;
 		case 2:
-			p = "const struct timespec *";
+			p = "userland const struct timespec *";
 			break;
 		case 3:
-			p = "const sigset_t *";
+			p = "userland const sigset_t *";
 			break;
 		default:
 			break;
@@ -8787,7 +8787,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		default:
 			break;
@@ -8800,10 +8800,10 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "int";
 			break;
 		case 1:
-			p = "char *";
+			p = "userland char *";
 			break;
 		case 2:
-			p = "struct timespec *";
+			p = "userland struct timespec *";
 			break;
 		case 3:
 			p = "int";
@@ -8822,7 +8822,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "id_t";
 			break;
 		case 2:
-			p = "struct vm_domain_policy_entry *";
+			p = "userland struct vm_domain_policy_entry *";
 			break;
 		default:
 			break;
@@ -8838,7 +8838,7 @@ systrace_entry_setargdesc(int sysnum, int ndx, char *desc, size_t descsz)
 			p = "id_t";
 			break;
 		case 2:
-			p = "const struct vm_domain_policy_entry *";
+			p = "userland const struct vm_domain_policy_entry *";
 			break;
 		default:
 			break;
diff --git a/sys/kern/uipc_socket.c b/sys/kern/uipc_socket.c
index 7cd2a75ff688..d74430460a65 100644
--- a/sys/kern/uipc_socket.c
+++ b/sys/kern/uipc_socket.c
@@ -2455,8 +2455,12 @@ sooptcopyin(struct sockopt *sopt, void *buf, size_t len, size_t minlen)
 	 */
 	if ((valsize = sopt->sopt_valsize) < minlen)
 		return EINVAL;
-	if (valsize > len)
+	if (valsize > len) {
+#if _BYTE_ORDER == _BIG_ENDIAN
+		sopt->sopt_val = (void *)((uintptr_t)sopt->sopt_val + (valsize - len));
+#endif
 		sopt->sopt_valsize = valsize = len;
+	}
 
 	if (sopt->sopt_td != NULL)
 		return (copyin(sopt->sopt_val, buf, valsize));
diff --git a/sys/kern/uipc_syscalls.c b/sys/kern/uipc_syscalls.c
index d1cd93d5ea82..e282665f75e5 100644
--- a/sys/kern/uipc_syscalls.c
+++ b/sys/kern/uipc_syscalls.c
@@ -89,20 +89,23 @@ static int sockargs(struct mbuf **, char *, socklen_t, int);
 /*
  * Convert a user file descriptor to a kernel file entry and check if required
  * capability rights are present.
+ * If required copy of current set of capability rights is returned.
  * A reference on the file entry is held upon returning.
  */
 int
 getsock_cap(struct thread *td, int fd, cap_rights_t *rightsp,
-    struct file **fpp, u_int *fflagp)
+    struct file **fpp, u_int *fflagp, struct filecaps *havecapsp)
 {
 	struct file *fp;
 	int error;
 
-	error = fget_unlocked(td->td_proc->p_fd, fd, rightsp, &fp, NULL);
+	error = fget_cap(td, fd, rightsp, &fp, havecapsp);
 	if (error != 0)
 		return (error);
 	if (fp->f_type != DTYPE_SOCKET) {
 		fdrop(fp, td);
+		if (havecapsp != NULL)
+			filecaps_free(havecapsp);
 		return (ENOTSOCK);
 	}
 	if (fflagp != NULL)
@@ -188,7 +191,7 @@ kern_bindat(struct thread *td, int dirfd, int fd, struct sockaddr *sa)
 	AUDIT_ARG_FD(fd);
 	AUDIT_ARG_SOCKADDR(td, dirfd, sa);
 	error = getsock_cap(td, fd, cap_rights_init(&rights, CAP_BIND),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error != 0)
 		return (error);
 	so = fp->f_data;
@@ -235,7 +238,7 @@ sys_listen(struct thread *td, struct listen_args *uap)
 
 	AUDIT_ARG_FD(uap->s);
 	error = getsock_cap(td, uap->s, cap_rights_init(&rights, CAP_LISTEN),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error == 0) {
 		so = fp->f_data;
 #ifdef MAC
@@ -308,6 +311,7 @@ kern_accept4(struct thread *td, int s, struct sockaddr **name,
 	struct file *headfp, *nfp = NULL;
 	struct sockaddr *sa = NULL;
 	struct socket *head, *so;
+	struct filecaps fcaps;
 	cap_rights_t rights;
 	u_int fflag;
 	pid_t pgid;
@@ -318,7 +322,7 @@ kern_accept4(struct thread *td, int s, struct sockaddr **name,
 
 	AUDIT_ARG_FD(s);
 	error = getsock_cap(td, s, cap_rights_init(&rights, CAP_ACCEPT),
-	    &headfp, &fflag);
+	    &headfp, &fflag, &fcaps);
 	if (error != 0)
 		return (error);
 	head = headfp->f_data;
@@ -331,7 +335,8 @@ kern_accept4(struct thread *td, int s, struct sockaddr **name,
 	if (error != 0)
 		goto done;
 #endif
-	error = falloc(td, &nfp, &fd, (flags & SOCK_CLOEXEC) ? O_CLOEXEC : 0);
+	error = falloc_caps(td, &nfp, &fd,
+	    (flags & SOCK_CLOEXEC) ? O_CLOEXEC : 0, &fcaps);
 	if (error != 0)
 		goto done;
 	ACCEPT_LOCK();
@@ -440,6 +445,8 @@ noconnection:
 	 * a reference on nfp to the caller on success if they request it.
 	 */
 done:
+	if (nfp == NULL)
+		filecaps_free(&fcaps);
 	if (fp != NULL) {
 		if (error == 0) {
 			*fp = nfp;
@@ -511,7 +518,7 @@ kern_connectat(struct thread *td, int dirfd, int fd, struct sockaddr *sa)
 	AUDIT_ARG_FD(fd);
 	AUDIT_ARG_SOCKADDR(td, dirfd, sa);
 	error = getsock_cap(td, fd, cap_rights_init(&rights, CAP_CONNECT),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error != 0)
 		return (error);
 	so = fp->f_data;
@@ -754,7 +761,7 @@ kern_sendit(struct thread *td, int s, struct msghdr *mp, int flags,
 		AUDIT_ARG_SOCKADDR(td, AT_FDCWD, mp->msg_name);
 		cap_rights_set(&rights, CAP_CONNECT);
 	}
-	error = getsock_cap(td, s, &rights, &fp, NULL);
+	error = getsock_cap(td, s, &rights, &fp, NULL, NULL);
 	if (error != 0)
 		return (error);
 	so = (struct socket *)fp->f_data;
@@ -923,7 +930,7 @@ kern_recvit(struct thread *td, int s, struct msghdr *mp, enum uio_seg fromseg,
 
 	AUDIT_ARG_FD(s);
 	error = getsock_cap(td, s, cap_rights_init(&rights, CAP_RECV),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error != 0)
 		return (error);
 	so = fp->f_data;
@@ -1198,7 +1205,7 @@ sys_shutdown(struct thread *td, struct shutdown_args *uap)
 
 	AUDIT_ARG_FD(uap->s);
 	error = getsock_cap(td, uap->s, cap_rights_init(&rights, CAP_SHUTDOWN),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error == 0) {
 		so = fp->f_data;
 		error = soshutdown(so, uap->how);
@@ -1257,7 +1264,7 @@ kern_setsockopt(struct thread *td, int s, int level, int name, void *val,
 
 	AUDIT_ARG_FD(s);
 	error = getsock_cap(td, s, cap_rights_init(&rights, CAP_SETSOCKOPT),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error == 0) {
 		so = fp->f_data;
 		error = sosetopt(so, &sopt);
@@ -1323,7 +1330,7 @@ kern_getsockopt(struct thread *td, int s, int level, int name, void *val,
 
 	AUDIT_ARG_FD(s);
 	error = getsock_cap(td, s, cap_rights_init(&rights, CAP_GETSOCKOPT),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error == 0) {
 		so = fp->f_data;
 		error = sogetopt(so, &sopt);
@@ -1376,7 +1383,7 @@ kern_getsockname(struct thread *td, int fd, struct sockaddr **sa,
 
 	AUDIT_ARG_FD(fd);
 	error = getsock_cap(td, fd, cap_rights_init(&rights, CAP_GETSOCKNAME),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error != 0)
 		return (error);
 	so = fp->f_data;
@@ -1463,7 +1470,7 @@ kern_getpeername(struct thread *td, int fd, struct sockaddr **sa,
 
 	AUDIT_ARG_FD(fd);
 	error = getsock_cap(td, fd, cap_rights_init(&rights, CAP_GETPEERNAME),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error != 0)
 		return (error);
 	so = fp->f_data;
diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c
index 42ad0ac0ae07..2734c259dd92 100644
--- a/sys/kern/vfs_cache.c
+++ b/sys/kern/vfs_cache.c
@@ -151,21 +151,35 @@ struct	namecache_ts {
  * name is located in the cache, it will be dropped.
  *
  * These locks are used (in the order in which they can be taken):
- * NAME         TYPE    ROLE
- * cache_lock   rwlock  global, needed for all modifications
- * bucketlock   rwlock  for access to given hash bucket
- * ncneg_mtx    mtx     negative entry LRU management
+ * NAME		TYPE	ROLE
+ * vnodelock	mtx	vnode lists and v_cache_dd field protection
+ * bucketlock	rwlock	for access to given set of hash buckets
+ * ncneg_mtx	mtx	negative entry LRU management
  *
- * A name -> vnode lookup can be safely performed by either locking cache_lock
- * or the relevant hash bucket.
+ * Additionally, ncneg_shrink_lock mtx is used to have at most one thread
+ * shrinking the LRU list.
  *
- * ".." and vnode -> name lookups require cache_lock.
+ * It is legal to take multiple vnodelock and bucketlock locks. The locking
+ * order is lower address first. Both are recursive.
  *
- * Modifications require both cache_lock and relevant bucketlock taken for
- * writing.
+ * "." lookups are lockless.
  *
- * Negative entry LRU management requires ncneg_mtx taken on top of either
- * cache_lock or bucketlock.
+ * ".." and vnode -> name lookups require vnodelock.
+ *
+ * name -> vnode lookup requires the relevant bucketlock to be held for reading.
+ *
+ * Insertions and removals of entries require involved vnodes and bucketlocks
+ * to be write-locked to prevent other threads from seeing the entry.
+ *
+ * Some lookups result in removal of the found entry (e.g. getting rid of a
+ * negative entry with the intent to create a positive one), which poses a
+ * problem when multiple threads reach the state. Similarly, two different
+ * threads can purge two different vnodes and try to remove the same name.
+ *
+ * If the already held vnode lock is lower than the second required lock, we
+ * can just take the other lock. However, in the opposite case, this could
+ * deadlock. As such, this is resolved by trylocking and if that fails unlocking
+ * the first node, locking everything in order and revalidating the state.
  */
 
 /*
@@ -196,15 +210,9 @@ SYSCTL_UINT(_vfs, OID_AUTO, ncsizefactor, CTLFLAG_RW, &ncsizefactor, 0,
 
 struct nchstats	nchstats;		/* cache effectiveness statistics */
 
-static struct rwlock cache_lock;
-RW_SYSINIT(vfscache, &cache_lock, "ncglobal");
-
-#define	CACHE_TRY_WLOCK()	rw_try_wlock(&cache_lock)
-#define	CACHE_UPGRADE_LOCK()	rw_try_upgrade(&cache_lock)
-#define	CACHE_RLOCK()		rw_rlock(&cache_lock)
-#define	CACHE_RUNLOCK()		rw_runlock(&cache_lock)
-#define	CACHE_WLOCK()		rw_wlock(&cache_lock)
-#define	CACHE_WUNLOCK()		rw_wunlock(&cache_lock)
+static struct mtx       ncneg_shrink_lock;
+MTX_SYSINIT(vfscache_shrink_neg, &ncneg_shrink_lock, "Name Cache shrink neg",
+    MTX_DEF);
 
 static struct mtx_padalign ncneg_mtx;
 MTX_SYSINIT(vfscache_neg, &ncneg_mtx, "ncneg", MTX_DEF);
@@ -214,6 +222,19 @@ static struct rwlock_padalign  *bucketlocks;
 #define	HASH2BUCKETLOCK(hash) \
 	((struct rwlock *)(&bucketlocks[((hash) % numbucketlocks)]))
 
+static u_int   numvnodelocks;
+static struct mtx *vnodelocks;
+static inline struct mtx *
+VP2VNODELOCK(struct vnode *vp)
+{
+	struct mtx *vlp;
+
+	if (vp == NULL)
+		return (NULL);
+	vlp = &vnodelocks[(((uintptr_t)(vp) >> 8) % numvnodelocks)];
+	return (vlp);
+}
+
 /*
  * UMA zones for the VFS cache.
  *
@@ -329,19 +350,49 @@ STATNODE_COUNTER(numfullpathfail2,
     "Number of fullpath search errors (VOP_VPTOCNP failures)");
 STATNODE_COUNTER(numfullpathfail4, "Number of fullpath search errors (ENOMEM)");
 STATNODE_COUNTER(numfullpathfound, "Number of successful fullpath calls");
-static long numupgrades; STATNODE_ULONG(numupgrades,
-    "Number of updates of the cache after lookup (write lock + retry)");
 static long zap_and_exit_bucket_fail; STATNODE_ULONG(zap_and_exit_bucket_fail,
-    "Number of times bucketlocked zap_and_exit case failed to writelock");
+    "Number of times zap_and_exit failed to lock");
+static long cache_lock_vnodes_cel_3_failures;
+STATNODE_ULONG(cache_lock_vnodes_cel_3_failures,
+    "Number of times 3-way vnode locking failed");
 
-static void cache_zap(struct namecache *ncp);
-static int vn_vptocnp_locked(struct vnode **vp, struct ucred *cred, char *buf,
-    u_int *buflen);
+static void cache_zap_locked(struct namecache *ncp, bool neg_locked);
 static int vn_fullpath1(struct thread *td, struct vnode *vp, struct vnode *rdir,
     char *buf, char **retbuf, u_int buflen);
 
 static MALLOC_DEFINE(M_VFSCACHE, "vfscache", "VFS name cache entries");
 
+static int cache_yield;
+SYSCTL_INT(_vfs_cache, OID_AUTO, yield, CTLFLAG_RD, &cache_yield, 0,
+    "Number of times cache called yield");
+
+static void
+cache_maybe_yield(void)
+{
+
+	if (should_yield()) {
+		cache_yield++;
+		kern_yield(PRI_USER);
+	}
+}
+
+static inline void
+cache_assert_vlp_locked(struct mtx *vlp)
+{
+
+	if (vlp != NULL)
+		mtx_assert(vlp, MA_OWNED);
+}
+
+static inline void
+cache_assert_vnode_locked(struct vnode *vp)
+{
+	struct mtx *vlp;
+
+	vlp = VP2VNODELOCK(vp);
+	cache_assert_vlp_locked(vlp);
+}
+
 static uint32_t
 cache_get_hash(char *name, u_char len, struct vnode *dvp)
 {
@@ -352,21 +403,41 @@ cache_get_hash(char *name, u_char len, struct vnode *dvp)
 	return (hash);
 }
 
+static inline struct rwlock *
+NCP2BUCKETLOCK(struct namecache *ncp)
+{
+	uint32_t hash;
+
+	hash = cache_get_hash(nc_get_name(ncp), ncp->nc_nlen, ncp->nc_dvp);
+	return (HASH2BUCKETLOCK(hash));
+}
+
 #ifdef INVARIANTS
 static void
 cache_assert_bucket_locked(struct namecache *ncp, int mode)
 {
-	struct rwlock *bucketlock;
-	uint32_t hash;
+	struct rwlock *blp;
 
-	hash = cache_get_hash(nc_get_name(ncp), ncp->nc_nlen, ncp->nc_dvp);
-	bucketlock = HASH2BUCKETLOCK(hash);
-	rw_assert(bucketlock, mode);
+	blp = NCP2BUCKETLOCK(ncp);
+	rw_assert(blp, mode);
 }
 #else
 #define cache_assert_bucket_locked(x, y) do { } while (0)
 #endif
 
+#define cache_sort(x, y)	_cache_sort((void **)(x), (void **)(y))
+static void
+_cache_sort(void **p1, void **p2)
+{
+	void *tmp;
+
+	if (*p1 > *p2) {
+		tmp = *p2;
+		*p2 = *p1;
+		*p1 = tmp;
+	}
+}
+
 static void
 cache_lock_all_buckets(void)
 {
@@ -385,6 +456,56 @@ cache_unlock_all_buckets(void)
 		rw_wunlock(&bucketlocks[i]);
 }
 
+static void
+cache_lock_all_vnodes(void)
+{
+	u_int i;
+
+	for (i = 0; i < numvnodelocks; i++)
+		mtx_lock(&vnodelocks[i]);
+}
+
+static void
+cache_unlock_all_vnodes(void)
+{
+	u_int i;
+
+	for (i = 0; i < numvnodelocks; i++)
+		mtx_unlock(&vnodelocks[i]);
+}
+
+static int
+cache_trylock_vnodes(struct mtx *vlp1, struct mtx *vlp2)
+{
+
+	cache_sort(&vlp1, &vlp2);
+	MPASS(vlp2 != NULL);
+
+	if (vlp1 != NULL) {
+		if (!mtx_trylock(vlp1))
+			return (EAGAIN);
+	}
+	if (!mtx_trylock(vlp2)) {
+		if (vlp1 != NULL)
+			mtx_unlock(vlp1);
+		return (EAGAIN);
+	}
+
+	return (0);
+}
+
+static void
+cache_unlock_vnodes(struct mtx *vlp1, struct mtx *vlp2)
+{
+
+	MPASS(vlp1 != NULL || vlp2 != NULL);
+
+	if (vlp1 != NULL)
+		mtx_unlock(vlp1);
+	if (vlp2 != NULL)
+		mtx_unlock(vlp2);
+}
+
 static int
 sysctl_nchstats(SYSCTL_HANDLER_ARGS)
 {
@@ -426,9 +547,9 @@ retry:
 	if (req->oldptr == NULL)
 		return SYSCTL_OUT(req, 0, n_nchash * sizeof(int));
 	cntbuf = malloc(n_nchash * sizeof(int), M_TEMP, M_ZERO | M_WAITOK);
-	CACHE_RLOCK();
+	cache_lock_all_buckets();
 	if (n_nchash != nchash + 1) {
-		CACHE_RUNLOCK();
+		cache_unlock_all_buckets();
 		free(cntbuf, M_TEMP);
 		goto retry;
 	}
@@ -436,7 +557,7 @@ retry:
 	for (ncpp = nchashtbl, i = 0; i < n_nchash; ncpp++, i++)
 		LIST_FOREACH(ncp, ncpp, nc_hash)
 			cntbuf[i]++;
-	CACHE_RUNLOCK();
+	cache_unlock_all_buckets();
 	for (error = 0, i = 0; i < n_nchash; i++)
 		if ((error = SYSCTL_OUT(req, &cntbuf[i], sizeof(int))) != 0)
 			break;
@@ -459,7 +580,7 @@ sysctl_debug_hashstat_nchash(SYSCTL_HANDLER_ARGS)
 	if (!req->oldptr)
 		return SYSCTL_OUT(req, 0, 4 * sizeof(int));
 
-	CACHE_RLOCK();
+	cache_lock_all_buckets();
 	n_nchash = nchash + 1;	/* nchash is max index, not count */
 	used = 0;
 	maxlength = 0;
@@ -476,7 +597,7 @@ sysctl_debug_hashstat_nchash(SYSCTL_HANDLER_ARGS)
 			maxlength = count;
 	}
 	n_nchash = nchash + 1;
-	CACHE_RUNLOCK();
+	cache_unlock_all_buckets();
 	pct = (used * 100) / (n_nchash / 100);
 	error = SYSCTL_OUT(req, &n_nchash, sizeof(n_nchash));
 	if (error)
@@ -504,6 +625,7 @@ static void
 cache_negative_hit(struct namecache *ncp)
 {
 
+	MPASS(ncp->nc_vp == NULL);
 	mtx_lock(&ncneg_mtx);
 	TAILQ_REMOVE(&ncneg, ncp, nc_dst);
 	TAILQ_INSERT_TAIL(&ncneg, ncp, nc_dst);
@@ -514,9 +636,8 @@ static void
 cache_negative_insert(struct namecache *ncp)
 {
 
-	rw_assert(&cache_lock, RA_WLOCKED);
-	cache_assert_bucket_locked(ncp, RA_WLOCKED);
 	MPASS(ncp->nc_vp == NULL);
+	cache_assert_bucket_locked(ncp, RA_WLOCKED);
 	mtx_lock(&ncneg_mtx);
 	TAILQ_INSERT_TAIL(&ncneg, ncp, nc_dst);
 	numneg++;
@@ -524,43 +645,74 @@ cache_negative_insert(struct namecache *ncp)
 }
 
 static void
-cache_negative_remove(struct namecache *ncp)
+cache_negative_remove(struct namecache *ncp, bool neg_locked)
 {
 
-	rw_assert(&cache_lock, RA_WLOCKED);
-	cache_assert_bucket_locked(ncp, RA_WLOCKED);
 	MPASS(ncp->nc_vp == NULL);
-	mtx_lock(&ncneg_mtx);
+	cache_assert_bucket_locked(ncp, RA_WLOCKED);
+	if (!neg_locked)
+		mtx_lock(&ncneg_mtx);
+	else
+		mtx_assert(&ncneg_mtx, MA_OWNED);
 	TAILQ_REMOVE(&ncneg, ncp, nc_dst);
 	numneg--;
-	mtx_unlock(&ncneg_mtx);
+	if (!neg_locked)
+		mtx_unlock(&ncneg_mtx);
 }
 
-static struct namecache *
+static void
 cache_negative_zap_one(void)
 {
-	struct namecache *ncp;
+	struct namecache *ncp, *ncp2;
+	struct mtx *dvlp;
+	struct rwlock *blp;
 
-	rw_assert(&cache_lock, RA_WLOCKED);
+	if (!mtx_trylock(&ncneg_shrink_lock))
+		return;
+
+	mtx_lock(&ncneg_mtx);
 	ncp = TAILQ_FIRST(&ncneg);
-	KASSERT(ncp->nc_vp == NULL, ("ncp %p vp %p on ncneg",
-	    ncp, ncp->nc_vp));
-	cache_zap(ncp);
-	return (ncp);
+	if (ncp == NULL) {
+		mtx_unlock(&ncneg_mtx);
+		goto out;
+	}
+	MPASS(ncp->nc_vp == NULL);
+	dvlp = VP2VNODELOCK(ncp->nc_dvp);
+	blp = NCP2BUCKETLOCK(ncp);
+	mtx_unlock(&ncneg_mtx);
+	mtx_lock(dvlp);
+	rw_wlock(blp);
+	mtx_lock(&ncneg_mtx);
+	ncp2 = TAILQ_FIRST(&ncneg);
+	if (ncp != ncp2 || dvlp != VP2VNODELOCK(ncp2->nc_dvp) ||
+	    blp != NCP2BUCKETLOCK(ncp2) || ncp2->nc_vp != NULL) {
+		ncp = NULL;
+		goto out_unlock_all;
+	}
+	cache_zap_locked(ncp, true);
+out_unlock_all:
+	mtx_unlock(&ncneg_mtx);
+	rw_wunlock(blp);
+	mtx_unlock(dvlp);
+out:
+	mtx_unlock(&ncneg_shrink_lock);
+	cache_free(ncp);
 }
 
 /*
- * cache_zap():
+ * cache_zap_locked():
  *
  *   Removes a namecache entry from cache, whether it contains an actual
  *   pointer to a vnode or if it is just a negative cache entry.
  */
 static void
-cache_zap_locked(struct namecache *ncp)
+cache_zap_locked(struct namecache *ncp, bool neg_locked)
 {
 
-	rw_assert(&cache_lock, RA_WLOCKED);
+	cache_assert_vnode_locked(ncp->nc_vp);
+	cache_assert_vnode_locked(ncp->nc_dvp);
 	cache_assert_bucket_locked(ncp, RA_WLOCKED);
+
 	CTR2(KTR_VFS, "cache_zap(%p) vp %p", ncp, ncp->nc_vp);
 	if (ncp->nc_vp != NULL) {
 		SDT_PROBE3(vfs, namecache, zap, done, ncp->nc_dvp,
@@ -577,7 +729,7 @@ cache_zap_locked(struct namecache *ncp)
 		LIST_REMOVE(ncp, nc_src);
 		if (LIST_EMPTY(&ncp->nc_dvp->v_cache_src)) {
 			ncp->nc_flag |= NCF_DVDROP;
-			numcachehv--;
+			atomic_subtract_rel_long(&numcachehv, 1);
 		}
 	}
 	if (ncp->nc_vp) {
@@ -585,24 +737,198 @@ cache_zap_locked(struct namecache *ncp)
 		if (ncp == ncp->nc_vp->v_cache_dd)
 			ncp->nc_vp->v_cache_dd = NULL;
 	} else {
-		cache_negative_remove(ncp);
+		cache_negative_remove(ncp, neg_locked);
 	}
-	numcache--;
+	atomic_subtract_rel_long(&numcache, 1);
 }
 
 static void
-cache_zap(struct namecache *ncp)
+cache_zap_negative_locked_vnode_kl(struct namecache *ncp, struct vnode *vp)
 {
-	struct rwlock *bucketlock;
-	uint32_t hash;
+	struct rwlock *blp;
 
-	rw_assert(&cache_lock, RA_WLOCKED);
+	MPASS(ncp->nc_dvp == vp);
+	MPASS(ncp->nc_vp == NULL);
+	cache_assert_vnode_locked(vp);
 
-	hash = cache_get_hash(nc_get_name(ncp), ncp->nc_nlen, ncp->nc_dvp);
-	bucketlock = HASH2BUCKETLOCK(hash);
-	rw_wlock(bucketlock);
-	cache_zap_locked(ncp);
-	rw_wunlock(bucketlock);
+	blp = NCP2BUCKETLOCK(ncp);
+	rw_wlock(blp);
+	cache_zap_locked(ncp, false);
+	rw_wunlock(blp);
+}
+
+static bool
+cache_zap_locked_vnode_kl2(struct namecache *ncp, struct vnode *vp,
+    struct mtx **vlpp)
+{
+	struct mtx *pvlp, *vlp1, *vlp2, *to_unlock;
+	struct rwlock *blp;
+
+	MPASS(vp == ncp->nc_dvp || vp == ncp->nc_vp);
+	cache_assert_vnode_locked(vp);
+
+	if (ncp->nc_vp == NULL) {
+		if (*vlpp != NULL) {
+			mtx_unlock(*vlpp);
+			*vlpp = NULL;
+		}
+		cache_zap_negative_locked_vnode_kl(ncp, vp);
+		return (true);
+	}
+
+	pvlp = VP2VNODELOCK(vp);
+	blp = NCP2BUCKETLOCK(ncp);
+	vlp1 = VP2VNODELOCK(ncp->nc_dvp);
+	vlp2 = VP2VNODELOCK(ncp->nc_vp);
+
+	if (*vlpp == vlp1 || *vlpp == vlp2) {
+		to_unlock = *vlpp;
+		*vlpp = NULL;
+	} else {
+		if (*vlpp != NULL) {
+			mtx_unlock(*vlpp);
+			*vlpp = NULL;
+		}
+		cache_sort(&vlp1, &vlp2);
+		if (vlp1 == pvlp) {
+			mtx_lock(vlp2);
+			to_unlock = vlp2;
+		} else {
+			if (!mtx_trylock(vlp1))
+				goto out_relock;
+			to_unlock = vlp1;
+		}
+	}
+	rw_wlock(blp);
+	cache_zap_locked(ncp, false);
+	rw_wunlock(blp);
+	if (to_unlock != NULL)
+		mtx_unlock(to_unlock);
+	return (true);
+
+out_relock:
+	mtx_unlock(vlp2);
+	mtx_lock(vlp1);
+	mtx_lock(vlp2);
+	MPASS(*vlpp == NULL);
+	*vlpp = vlp1;
+	return (false);
+}
+
+static int
+cache_zap_locked_vnode(struct namecache *ncp, struct vnode *vp)
+{
+	struct mtx *pvlp, *vlp1, *vlp2, *to_unlock;
+	struct rwlock *blp;
+	int error = 0;
+
+	MPASS(vp == ncp->nc_dvp || vp == ncp->nc_vp);
+	cache_assert_vnode_locked(vp);
+
+	pvlp = VP2VNODELOCK(vp);
+	if (ncp->nc_vp == NULL) {
+		cache_zap_negative_locked_vnode_kl(ncp, vp);
+		goto out;
+	}
+
+	blp = NCP2BUCKETLOCK(ncp);
+	vlp1 = VP2VNODELOCK(ncp->nc_dvp);
+	vlp2 = VP2VNODELOCK(ncp->nc_vp);
+	cache_sort(&vlp1, &vlp2);
+	if (vlp1 == pvlp) {
+		mtx_lock(vlp2);
+		to_unlock = vlp2;
+	} else {
+		if (!mtx_trylock(vlp1)) {
+			error = EAGAIN;
+			goto out;
+		}
+		to_unlock = vlp1;
+	}
+	rw_wlock(blp);
+	cache_zap_locked(ncp, false);
+	rw_wunlock(blp);
+	mtx_unlock(to_unlock);
+out:
+	mtx_unlock(pvlp);
+	return (error);
+}
+
+static int
+cache_zap_rlocked_bucket(struct namecache *ncp, struct rwlock *blp)
+{
+	struct mtx *dvlp, *vlp;
+
+	cache_assert_bucket_locked(ncp, RA_RLOCKED);
+
+	dvlp = VP2VNODELOCK(ncp->nc_dvp);
+	vlp = VP2VNODELOCK(ncp->nc_vp);
+	if (cache_trylock_vnodes(dvlp, vlp) == 0) {
+		rw_runlock(blp);
+		rw_wlock(blp);
+		cache_zap_locked(ncp, false);
+		rw_wunlock(blp);
+		cache_unlock_vnodes(dvlp, vlp);
+		return (0);
+	}
+
+	rw_runlock(blp);
+	return (EAGAIN);
+}
+
+static int
+cache_zap_wlocked_bucket_kl(struct namecache *ncp, struct rwlock *blp,
+    struct mtx **vlpp1, struct mtx **vlpp2)
+{
+	struct mtx *dvlp, *vlp;
+
+	cache_assert_bucket_locked(ncp, RA_WLOCKED);
+
+	dvlp = VP2VNODELOCK(ncp->nc_dvp);
+	vlp = VP2VNODELOCK(ncp->nc_vp);
+	cache_sort(&dvlp, &vlp);
+
+	if (*vlpp1 == dvlp && *vlpp2 == vlp) {
+		cache_zap_locked(ncp, false);
+		cache_unlock_vnodes(dvlp, vlp);
+		*vlpp1 = NULL;
+		*vlpp2 = NULL;
+		return (0);
+	}
+
+	if (*vlpp1 != NULL)
+		mtx_unlock(*vlpp1);
+	if (*vlpp2 != NULL)
+		mtx_unlock(*vlpp2);
+	*vlpp1 = NULL;
+	*vlpp2 = NULL;
+
+	if (cache_trylock_vnodes(dvlp, vlp) == 0) {
+		cache_zap_locked(ncp, false);
+		cache_unlock_vnodes(dvlp, vlp);
+		return (0);
+	}
+
+	rw_wunlock(blp);
+	*vlpp1 = dvlp;
+	*vlpp2 = vlp;
+	if (*vlpp1 != NULL)
+		mtx_lock(*vlpp1);
+	mtx_lock(*vlpp2);
+	rw_wlock(blp);
+	return (EAGAIN);
+}
+
+static void
+cache_lookup_unlock(struct rwlock *blp, struct mtx *vlp)
+{
+
+	if (blp != NULL) {
+		rw_runlock(blp);
+		mtx_assert(vlp, MA_NOTOWNED);
+	} else {
+		mtx_unlock(vlp);
+	}
 }
 
 /*
@@ -622,44 +948,26 @@ cache_zap(struct namecache *ncp)
  * not recursively acquired.
  */
 
-enum { UNLOCKED, WLOCKED, RLOCKED };
-
-static void
-cache_unlock(int cache_locked)
-{
-
-	switch (cache_locked) {
-	case UNLOCKED:
-		break;
-	case WLOCKED:
-		CACHE_WUNLOCK();
-		break;
-	case RLOCKED:
-		CACHE_RUNLOCK();
-		break;
-	}
-}
-
 int
 cache_lookup(struct vnode *dvp, struct vnode **vpp, struct componentname *cnp,
     struct timespec *tsp, int *ticksp)
 {
-	struct rwlock *bucketlock;
 	struct namecache *ncp;
+	struct rwlock *blp;
+	struct mtx *dvlp, *dvlp2;
 	uint32_t hash;
-	int error, ltype, cache_locked;
+	int error, ltype;
 
 	if (!doingcache) {
 		cnp->cn_flags &= ~MAKEENTRY;
 		return (0);
 	}
 retry:
-	bucketlock = NULL;
-	cache_locked = UNLOCKED;
+	blp = NULL;
+	dvlp = VP2VNODELOCK(dvp);
 	error = 0;
 	counter_u64_add(numcalls, 1);
 
-retry_wlocked:
 	if (cnp->cn_nameptr[0] == '.') {
 		if (cnp->cn_namelen == 1) {
 			*vpp = dvp;
@@ -693,32 +1001,37 @@ retry_wlocked:
 		}
 		if (cnp->cn_namelen == 2 && cnp->cn_nameptr[1] == '.') {
 			counter_u64_add(dotdothits, 1);
-			if (cache_locked == UNLOCKED) {
-				CACHE_RLOCK();
-				cache_locked = RLOCKED;
-			}
-
-			if (dvp->v_cache_dd == NULL) {
+			dvlp2 = NULL;
+			mtx_lock(dvlp);
+retry_dotdot:
+			ncp = dvp->v_cache_dd;
+			if (ncp == NULL) {
 				SDT_PROBE3(vfs, namecache, lookup, miss, dvp,
 				    "..", NULL);
-				goto unlock;
+				mtx_unlock(dvlp);
+				return (0);
 			}
 			if ((cnp->cn_flags & MAKEENTRY) == 0) {
-				if (cache_locked != WLOCKED &&
-				    !CACHE_UPGRADE_LOCK())
-					goto wlock;
-				ncp = NULL;
-				if (dvp->v_cache_dd->nc_flag & NCF_ISDOTDOT) {
-					ncp = dvp->v_cache_dd;
-					cache_zap(ncp);
+				if ((ncp->nc_flag & NCF_ISDOTDOT) != 0) {
+					if (ncp->nc_dvp != dvp)
+						panic("dvp %p v_cache_dd %p\n", dvp, ncp);
+					if (!cache_zap_locked_vnode_kl2(ncp,
+					    dvp, &dvlp2))
+						goto retry_dotdot;
+					MPASS(dvp->v_cache_dd == NULL);
+					mtx_unlock(dvlp);
+					if (dvlp2 != NULL)
+						mtx_unlock(dvlp2);
+					cache_free(ncp);
+				} else {
+					dvp->v_cache_dd = NULL;
+					mtx_unlock(dvlp);
+					if (dvlp2 != NULL)
+						mtx_unlock(dvlp2);
 				}
-				dvp->v_cache_dd = NULL;
-				CACHE_WUNLOCK();
-				cache_free(ncp);
 				return (0);
 			}
-			ncp = dvp->v_cache_dd;
-			if (ncp->nc_flag & NCF_ISDOTDOT)
+			if ((ncp->nc_flag & NCF_ISDOTDOT) != 0)
 				*vpp = ncp->nc_vp;
 			else
 				*vpp = ncp->nc_dvp;
@@ -739,10 +1052,8 @@ retry_wlocked:
 	}
 
 	hash = cache_get_hash(cnp->cn_nameptr, cnp->cn_namelen, dvp);
-	if (cache_locked == UNLOCKED) {
-		bucketlock = HASH2BUCKETLOCK(hash);
-		rw_rlock(bucketlock);
-	}
+	blp = HASH2BUCKETLOCK(hash);
+	rw_rlock(blp);
 
 	LIST_FOREACH(ncp, (NCHHASH(hash)), nc_hash) {
 		counter_u64_add(numchecks, 1);
@@ -795,24 +1106,9 @@ negative_success:
 	SDT_PROBE2(vfs, namecache, lookup, hit__negative, dvp,
 	    nc_get_name(ncp));
 	cache_out_ts(ncp, tsp, ticksp);
-	MPASS(bucketlock != NULL || cache_locked != UNLOCKED);
-	if (bucketlock != NULL)
-		rw_runlock(bucketlock);
-	cache_unlock(cache_locked);
+	cache_lookup_unlock(blp, dvlp);
 	return (ENOENT);
 
-wlock:
-	/*
-	 * We need to update the cache after our lookup, so upgrade to
-	 * a write lock and retry the operation.
-	 */
-	CACHE_RUNLOCK();
-wlock_unlocked:
-	CACHE_WLOCK();
-	numupgrades++;
-	cache_locked = WLOCKED;
-	goto retry_wlocked;
-
 success:
 	/*
 	 * On success we return a locked and ref'd vnode as per the lookup
@@ -825,10 +1121,7 @@ success:
 		VOP_UNLOCK(dvp, 0);
 	}
 	vhold(*vpp);
-	MPASS(bucketlock != NULL || cache_locked != UNLOCKED);
-	if (bucketlock != NULL)
-		rw_runlock(bucketlock);
-	cache_unlock(cache_locked);
+	cache_lookup_unlock(blp, dvlp);
 	error = vget(*vpp, cnp->cn_lkflags | LK_VNHELD, cnp->cn_thread);
 	if (cnp->cn_flags & ISDOTDOT) {
 		vn_lock(dvp, ltype | LK_RETRY);
@@ -850,32 +1143,232 @@ success:
 	return (-1);
 
 unlock:
-	MPASS(bucketlock != NULL || cache_locked != UNLOCKED);
-	if (bucketlock != NULL)
-		rw_runlock(bucketlock);
-	cache_unlock(cache_locked);
+	cache_lookup_unlock(blp, dvlp);
 	return (0);
 
 zap_and_exit:
-	if (bucketlock != NULL) {
-		rw_assert(&cache_lock, RA_UNLOCKED);
-		if (!CACHE_TRY_WLOCK()) {
-			rw_runlock(bucketlock);
-			bucketlock = NULL;
-			zap_and_exit_bucket_fail++;
-			goto wlock_unlocked;
-		}
-		cache_locked = WLOCKED;
-		rw_runlock(bucketlock);
-		bucketlock = NULL;
-	} else if (cache_locked != WLOCKED && !CACHE_UPGRADE_LOCK())
-		goto wlock;
-	cache_zap(ncp);
-	CACHE_WUNLOCK();
+	if (blp != NULL)
+		error = cache_zap_rlocked_bucket(ncp, blp);
+	else
+		error = cache_zap_locked_vnode(ncp, dvp);
+	if (error != 0) {
+		zap_and_exit_bucket_fail++;
+		cache_maybe_yield();
+		goto retry;
+	}
 	cache_free(ncp);
 	return (0);
 }
 
+struct celockstate {
+	struct mtx *vlp[3];
+	struct rwlock *blp[2];
+};
+CTASSERT((nitems(((struct celockstate *)0)->vlp) == 3));
+CTASSERT((nitems(((struct celockstate *)0)->blp) == 2));
+
+static inline void
+cache_celockstate_init(struct celockstate *cel)
+{
+
+	bzero(cel, sizeof(*cel));
+}
+
+static void
+cache_lock_vnodes_cel(struct celockstate *cel, struct vnode *vp,
+    struct vnode *dvp)
+{
+	struct mtx *vlp1, *vlp2;
+
+	MPASS(cel->vlp[0] == NULL);
+	MPASS(cel->vlp[1] == NULL);
+	MPASS(cel->vlp[2] == NULL);
+
+	MPASS(vp != NULL || dvp != NULL);
+
+	vlp1 = VP2VNODELOCK(vp);
+	vlp2 = VP2VNODELOCK(dvp);
+	cache_sort(&vlp1, &vlp2);
+
+	if (vlp1 != NULL) {
+		mtx_lock(vlp1);
+		cel->vlp[0] = vlp1;
+	}
+	mtx_lock(vlp2);
+	cel->vlp[1] = vlp2;
+}
+
+static void
+cache_unlock_vnodes_cel(struct celockstate *cel)
+{
+
+	MPASS(cel->vlp[0] != NULL || cel->vlp[1] != NULL);
+
+	if (cel->vlp[0] != NULL)
+		mtx_unlock(cel->vlp[0]);
+	if (cel->vlp[1] != NULL)
+		mtx_unlock(cel->vlp[1]);
+	if (cel->vlp[2] != NULL)
+		mtx_unlock(cel->vlp[2]);
+}
+
+static bool
+cache_lock_vnodes_cel_3(struct celockstate *cel, struct vnode *vp)
+{
+	struct mtx *vlp;
+	bool ret;
+
+	cache_assert_vlp_locked(cel->vlp[0]);
+	cache_assert_vlp_locked(cel->vlp[1]);
+	MPASS(cel->vlp[2] == NULL);
+
+	vlp = VP2VNODELOCK(vp);
+	if (vlp == NULL)
+		return (true);
+
+	ret = true;
+	if (vlp >= cel->vlp[1]) {
+		mtx_lock(vlp);
+	} else {
+		if (mtx_trylock(vlp))
+			goto out;
+		cache_lock_vnodes_cel_3_failures++;
+		cache_unlock_vnodes_cel(cel);
+		if (vlp < cel->vlp[0]) {
+			mtx_lock(vlp);
+			mtx_lock(cel->vlp[0]);
+			mtx_lock(cel->vlp[1]);
+		} else {
+			if (cel->vlp[0] != NULL)
+				mtx_lock(cel->vlp[0]);
+			mtx_lock(vlp);
+			mtx_lock(cel->vlp[1]);
+		}
+		ret = false;
+	}
+out:
+	cel->vlp[2] = vlp;
+	return (ret);
+}
+
+static void
+cache_lock_buckets_cel(struct celockstate *cel, struct rwlock *blp1,
+    struct rwlock *blp2)
+{
+
+	MPASS(cel->blp[0] == NULL);
+	MPASS(cel->blp[1] == NULL);
+
+	cache_sort(&blp1, &blp2);
+
+	if (blp1 != NULL) {
+		rw_wlock(blp1);
+		cel->blp[0] = blp1;
+	}
+	rw_wlock(blp2);
+	cel->blp[1] = blp2;
+}
+
+static void
+cache_unlock_buckets_cel(struct celockstate *cel)
+{
+
+	if (cel->blp[0] != NULL)
+		rw_wunlock(cel->blp[0]);
+	rw_wunlock(cel->blp[1]);
+}
+
+/*
+ * Lock part of the cache affected by the insertion.
+ *
+ * This means vnodelocks for dvp, vp and the relevant bucketlock.
+ * However, insertion can result in removal of an old entry. In this
+ * case we have an additional vnode and bucketlock pair to lock. If the
+ * entry is negative, ncelock is locked instead of the vnode.
+ *
+ * That is, in the worst case we have to lock 3 vnodes and 2 bucketlocks, while
+ * preserving the locking order (smaller address first).
+ */
+static void
+cache_enter_lock(struct celockstate *cel, struct vnode *dvp, struct vnode *vp,
+    uint32_t hash)
+{
+	struct namecache *ncp;
+	struct rwlock *blps[2];
+
+	blps[0] = HASH2BUCKETLOCK(hash);
+	for (;;) {
+		blps[1] = NULL;
+		cache_lock_vnodes_cel(cel, dvp, vp);
+		if (vp == NULL || vp->v_type != VDIR)
+			break;
+		ncp = vp->v_cache_dd;
+		if (ncp == NULL)
+			break;
+		if ((ncp->nc_flag & NCF_ISDOTDOT) == 0)
+			break;
+		MPASS(ncp->nc_dvp == vp);
+		blps[1] = NCP2BUCKETLOCK(ncp);
+		if (cache_lock_vnodes_cel_3(cel, ncp->nc_vp))
+			break;
+		/*
+		 * All vnodes got re-locked. Re-validate the state and if
+		 * nothing changed we are done. Otherwise restart.
+		 */
+		if (ncp == vp->v_cache_dd &&
+		    (ncp->nc_flag & NCF_ISDOTDOT) != 0 &&
+		    blps[1] == NCP2BUCKETLOCK(ncp) &&
+		    VP2VNODELOCK(ncp->nc_vp) == cel->vlp[2])
+			break;
+		cache_unlock_vnodes_cel(cel);
+		cel->vlp[0] = NULL;
+		cel->vlp[1] = NULL;
+		cel->vlp[2] = NULL;
+	}
+	cache_lock_buckets_cel(cel, blps[0], blps[1]);
+}
+
+static void
+cache_enter_lock_dd(struct celockstate *cel, struct vnode *dvp, struct vnode *vp,
+    uint32_t hash)
+{
+	struct namecache *ncp;
+	struct rwlock *blps[2];
+
+	blps[0] = HASH2BUCKETLOCK(hash);
+	for (;;) {
+		blps[1] = NULL;
+		cache_lock_vnodes_cel(cel, dvp, vp);
+		ncp = dvp->v_cache_dd;
+		if (ncp == NULL)
+			break;
+		if ((ncp->nc_flag & NCF_ISDOTDOT) == 0)
+			break;
+		MPASS(ncp->nc_dvp == dvp);
+		blps[1] = NCP2BUCKETLOCK(ncp);
+		if (cache_lock_vnodes_cel_3(cel, ncp->nc_vp))
+			break;
+		if (ncp == dvp->v_cache_dd &&
+		    (ncp->nc_flag & NCF_ISDOTDOT) != 0 &&
+		    blps[1] == NCP2BUCKETLOCK(ncp) &&
+		    VP2VNODELOCK(ncp->nc_vp) == cel->vlp[2])
+			break;
+		cache_unlock_vnodes_cel(cel);
+		cel->vlp[0] = NULL;
+		cel->vlp[1] = NULL;
+		cel->vlp[2] = NULL;
+	}
+	cache_lock_buckets_cel(cel, blps[0], blps[1]);
+}
+
+static void
+cache_enter_unlock(struct celockstate *cel)
+{
+
+	cache_unlock_buckets_cel(cel);
+	cache_unlock_vnodes_cel(cel);
+}
+
 /*
  * Add an entry to the cache.
  */
@@ -883,8 +1376,8 @@ void
 cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
     struct timespec *tsp, struct timespec *dtsp)
 {
-	struct rwlock *bucketlock;
-	struct namecache *ncp, *n2, *ndd, *nneg;
+	struct celockstate cel;
+	struct namecache *ncp, *n2, *ndd;
 	struct namecache_ts *n3;
 	struct nchashhead *ncpp;
 	uint32_t hash;
@@ -906,13 +1399,16 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
 	if (numcache >= desiredvnodes * ncsizefactor)
 		return;
 
-	ndd = nneg = NULL;
+	cache_celockstate_init(&cel);
+	ndd = NULL;
 	flag = 0;
 	if (cnp->cn_nameptr[0] == '.') {
 		if (cnp->cn_namelen == 1)
 			return;
 		if (cnp->cn_namelen == 2 && cnp->cn_nameptr[1] == '.') {
-			CACHE_WLOCK();
+			len = cnp->cn_namelen;
+			hash = cache_get_hash(cnp->cn_nameptr, len, dvp);
+			cache_enter_lock_dd(&cel, dvp, vp, hash);
 			/*
 			 * If dotdot entry already exists, just retarget it
 			 * to new parent vnode, otherwise continue with new
@@ -926,7 +1422,7 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
 					TAILQ_REMOVE(&ncp->nc_vp->v_cache_dst,
 					    ncp, nc_dst);
 				} else {
-					cache_negative_remove(ncp);
+					cache_negative_remove(ncp, false);
 				}
 				if (vp != NULL) {
 					TAILQ_INSERT_HEAD(&vp->v_cache_dst,
@@ -935,12 +1431,13 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
 					cache_negative_insert(ncp);
 				}
 				ncp->nc_vp = vp;
-				CACHE_WUNLOCK();
+				cache_enter_unlock(&cel);
 				return;
 			}
 			dvp->v_cache_dd = NULL;
+			cache_enter_unlock(&cel);
+			cache_celockstate_init(&cel);
 			SDT_PROBE3(vfs, namecache, enter, done, dvp, "..", vp);
-			CACHE_WUNLOCK();
 			flag = NCF_ISDOTDOT;
 		}
 	}
@@ -966,7 +1463,7 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
 	len = ncp->nc_nlen = cnp->cn_namelen;
 	hash = cache_get_hash(cnp->cn_nameptr, len, dvp);
 	strlcpy(nc_get_name(ncp), cnp->cn_nameptr, len + 1);
-	CACHE_WLOCK();
+	cache_enter_lock(&cel, dvp, vp, hash);
 
 	/*
 	 * See if this vnode or negative entry is already in the cache
@@ -993,9 +1490,7 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
 					n3->nc_flag |= NCF_DTS;
 				}
 			}
-			CACHE_WUNLOCK();
-			cache_free(ncp);
-			return;
+			goto out_unlock_free;
 		}
 	}
 
@@ -1004,17 +1499,14 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
 		 * See if we are trying to add .. entry, but some other lookup
 		 * has populated v_cache_dd pointer already.
 		 */
-		if (dvp->v_cache_dd != NULL) {
-			CACHE_WUNLOCK();
-			cache_free(ncp);
-			return;
-		}
+		if (dvp->v_cache_dd != NULL)
+			goto out_unlock_free;
 		KASSERT(vp == NULL || vp->v_type == VDIR,
 		    ("wrong vnode type %p", vp));
 		dvp->v_cache_dd = ncp;
 	}
 
-	numcache++;
+	atomic_add_rel_long(&numcache, 1);
 	if (vp != NULL) {
 		if (vp->v_type == VDIR) {
 			if (flag != NCF_ISDOTDOT) {
@@ -1025,7 +1517,7 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
 				 */
 				if ((ndd = vp->v_cache_dd) != NULL) {
 					if ((ndd->nc_flag & NCF_ISDOTDOT) != 0)
-						cache_zap(ndd);
+						cache_zap_locked(ndd, false);
 					else
 						ndd = NULL;
 				}
@@ -1039,14 +1531,11 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
 	if (flag != NCF_ISDOTDOT) {
 		if (LIST_EMPTY(&dvp->v_cache_src)) {
 			vhold(dvp);
-			numcachehv++;
+			atomic_add_rel_long(&numcachehv, 1);
 		}
 		LIST_INSERT_HEAD(&dvp->v_cache_src, ncp, nc_src);
 	}
 
-	bucketlock = HASH2BUCKETLOCK(hash);
-	rw_wlock(bucketlock);
-
 	/*
 	 * Insert the new namecache entry into the appropriate chain
 	 * within the cache entries table.
@@ -1069,12 +1558,15 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp,
 		SDT_PROBE2(vfs, namecache, enter_negative, done, dvp,
 		    nc_get_name(ncp));
 	}
-	rw_wunlock(bucketlock);
+	cache_enter_unlock(&cel);
 	if (numneg * ncnegfactor > numcache)
-		nneg = cache_negative_zap_one();
-	CACHE_WUNLOCK();
+		cache_negative_zap_one();
 	cache_free(ndd);
-	cache_free(nneg);
+	return;
+out_unlock_free:
+	cache_enter_unlock(&cel);
+	cache_free(ncp);
+	return;
 }
 
 static u_int
@@ -1112,13 +1604,16 @@ nchinit(void *dummy __unused)
 	    NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_ZINIT);
 
 	nchashtbl = hashinit(desiredvnodes * 2, M_VFSCACHE, &nchash);
-	numbucketlocks = cache_roundup_2(mp_ncpus * 16);
-	if (numbucketlocks > nchash)
-		numbucketlocks = nchash;
+	numbucketlocks = cache_roundup_2(mp_ncpus * 64);
 	bucketlocks = malloc(sizeof(*bucketlocks) * numbucketlocks, M_VFSCACHE,
 	    M_WAITOK | M_ZERO);
 	for (i = 0; i < numbucketlocks; i++)
-		rw_init_flags(&bucketlocks[i], "ncbuc", RW_DUPOK);
+		rw_init_flags(&bucketlocks[i], "ncbuc", RW_DUPOK | RW_RECURSE);
+	numvnodelocks = cache_roundup_2(mp_ncpus * 64);
+	vnodelocks = malloc(sizeof(*vnodelocks) * numvnodelocks, M_VFSCACHE,
+	    M_WAITOK | M_ZERO);
+	for (i = 0; i < numvnodelocks; i++)
+		mtx_init(&vnodelocks[i], "ncvn", NULL, MTX_DUPOK | MTX_RECURSE);
 
 	numcalls = counter_u64_alloc(M_WAITOK);
 	dothits = counter_u64_alloc(M_WAITOK);
@@ -1158,7 +1653,7 @@ cache_changesize(int newmaxvnodes)
 	 * None of the namecache entries in the table can be removed
 	 * because to do so, they have to be removed from the hash table.
 	 */
-	CACHE_WLOCK();
+	cache_lock_all_vnodes();
 	cache_lock_all_buckets();
 	old_nchashtbl = nchashtbl;
 	old_nchash = nchash;
@@ -1173,7 +1668,7 @@ cache_changesize(int newmaxvnodes)
 		}
 	}
 	cache_unlock_all_buckets();
-	CACHE_WUNLOCK();
+	cache_unlock_all_vnodes();
 	free(old_nchashtbl, M_VFSCACHE);
 }
 
@@ -1185,30 +1680,42 @@ cache_purge(struct vnode *vp)
 {
 	TAILQ_HEAD(, namecache) ncps;
 	struct namecache *ncp, *nnp;
+	struct mtx *vlp, *vlp2;
 
 	CTR1(KTR_VFS, "cache_purge(%p)", vp);
 	SDT_PROBE1(vfs, namecache, purge, done, vp);
+	if (LIST_EMPTY(&vp->v_cache_src) && TAILQ_EMPTY(&vp->v_cache_dst) &&
+	    vp->v_cache_dd == NULL)
+		return;
 	TAILQ_INIT(&ncps);
-	CACHE_WLOCK();
+	vlp = VP2VNODELOCK(vp);
+	vlp2 = NULL;
+	mtx_lock(vlp);
+retry:
 	while (!LIST_EMPTY(&vp->v_cache_src)) {
 		ncp = LIST_FIRST(&vp->v_cache_src);
-		cache_zap(ncp);
+		if (!cache_zap_locked_vnode_kl2(ncp, vp, &vlp2))
+			goto retry;
 		TAILQ_INSERT_TAIL(&ncps, ncp, nc_dst);
 	}
 	while (!TAILQ_EMPTY(&vp->v_cache_dst)) {
 		ncp = TAILQ_FIRST(&vp->v_cache_dst);
-		cache_zap(ncp);
+		if (!cache_zap_locked_vnode_kl2(ncp, vp, &vlp2))
+			goto retry;
 		TAILQ_INSERT_TAIL(&ncps, ncp, nc_dst);
 	}
-	if (vp->v_cache_dd != NULL) {
-		ncp = vp->v_cache_dd;
+	ncp = vp->v_cache_dd;
+	if (ncp != NULL) {
 		KASSERT(ncp->nc_flag & NCF_ISDOTDOT,
 		   ("lost dotdot link"));
-		cache_zap(ncp);
+		if (!cache_zap_locked_vnode_kl2(ncp, vp, &vlp2))
+			goto retry;
 		TAILQ_INSERT_TAIL(&ncps, ncp, nc_dst);
 	}
 	KASSERT(vp->v_cache_dd == NULL, ("incomplete purge"));
-	CACHE_WUNLOCK();
+	mtx_unlock(vlp);
+	if (vlp2 != NULL)
+		mtx_unlock(vlp2);
 	TAILQ_FOREACH_SAFE(ncp, &ncps, nc_dst, nnp) {
 		cache_free(ncp);
 	}
@@ -1222,18 +1729,20 @@ cache_purge_negative(struct vnode *vp)
 {
 	TAILQ_HEAD(, namecache) ncps;
 	struct namecache *ncp, *nnp;
+	struct mtx *vlp;
 
 	CTR1(KTR_VFS, "cache_purge_negative(%p)", vp);
 	SDT_PROBE1(vfs, namecache, purge_negative, done, vp);
 	TAILQ_INIT(&ncps);
-	CACHE_WLOCK();
+	vlp = VP2VNODELOCK(vp);
+	mtx_lock(vlp);
 	LIST_FOREACH_SAFE(ncp, &vp->v_cache_src, nc_src, nnp) {
 		if (ncp->nc_vp != NULL)
 			continue;
-		cache_zap(ncp);
+		cache_zap_negative_locked_vnode_kl(ncp, vp);
 		TAILQ_INSERT_TAIL(&ncps, ncp, nc_dst);
 	}
-	CACHE_WUNLOCK();
+	mtx_unlock(vlp);
 	TAILQ_FOREACH_SAFE(ncp, &ncps, nc_dst, nnp) {
 		cache_free(ncp);
 	}
@@ -1246,32 +1755,44 @@ void
 cache_purgevfs(struct mount *mp)
 {
 	TAILQ_HEAD(, namecache) ncps;
-	struct rwlock *bucketlock;
+	struct mtx *vlp1, *vlp2;
+	struct rwlock *blp;
 	struct nchashhead *bucket;
 	struct namecache *ncp, *nnp;
 	u_long i, j, n_nchash;
+	int error;
 
 	/* Scan hash tables for applicable entries */
 	SDT_PROBE1(vfs, namecache, purgevfs, done, mp);
 	TAILQ_INIT(&ncps);
-	CACHE_WLOCK();
 	n_nchash = nchash + 1;
+	vlp1 = vlp2 = NULL;
 	for (i = 0; i < numbucketlocks; i++) {
-		bucketlock = (struct rwlock *)&bucketlocks[i];
-		rw_wlock(bucketlock);
+		blp = (struct rwlock *)&bucketlocks[i];
+		rw_wlock(blp);
 		for (j = i; j < n_nchash; j += numbucketlocks) {
+retry:
 			bucket = &nchashtbl[j];
 			LIST_FOREACH_SAFE(ncp, bucket, nc_hash, nnp) {
 				cache_assert_bucket_locked(ncp, RA_WLOCKED);
 				if (ncp->nc_dvp->v_mount != mp)
 					continue;
-				cache_zap_locked(ncp);
+				error = cache_zap_wlocked_bucket_kl(ncp, blp,
+				    &vlp1, &vlp2);
+				if (error != 0)
+					goto retry;
 				TAILQ_INSERT_HEAD(&ncps, ncp, nc_dst);
 			}
 		}
-		rw_wunlock(bucketlock);
+		rw_wunlock(blp);
+		if (vlp1 == NULL && vlp2 == NULL)
+			cache_maybe_yield();
 	}
-	CACHE_WUNLOCK();
+	if (vlp1 != NULL)
+		mtx_unlock(vlp1);
+	if (vlp2 != NULL)
+		mtx_unlock(vlp2);
+
 	TAILQ_FOREACH_SAFE(ncp, &ncps, nc_dst, nnp) {
 		cache_free(ncp);
 	}
@@ -1443,30 +1964,20 @@ vn_fullpath_global(struct thread *td, struct vnode *vn,
 int
 vn_vptocnp(struct vnode **vp, struct ucred *cred, char *buf, u_int *buflen)
 {
-	int error;
-
-	CACHE_RLOCK();
-	error = vn_vptocnp_locked(vp, cred, buf, buflen);
-	if (error == 0)
-		CACHE_RUNLOCK();
-	return (error);
-}
-
-static int
-vn_vptocnp_locked(struct vnode **vp, struct ucred *cred, char *buf,
-    u_int *buflen)
-{
 	struct vnode *dvp;
 	struct namecache *ncp;
+	struct mtx *vlp;
 	int error;
 
+	vlp = VP2VNODELOCK(*vp);
+	mtx_lock(vlp);
 	TAILQ_FOREACH(ncp, &((*vp)->v_cache_dst), nc_dst) {
 		if ((ncp->nc_flag & NCF_ISDOTDOT) == 0)
 			break;
 	}
 	if (ncp != NULL) {
 		if (*buflen < ncp->nc_nlen) {
-			CACHE_RUNLOCK();
+			mtx_unlock(vlp);
 			vrele(*vp);
 			counter_u64_add(numfullpathfail4, 1);
 			error = ENOMEM;
@@ -1481,14 +1992,13 @@ vn_vptocnp_locked(struct vnode **vp, struct ucred *cred, char *buf,
 		dvp = *vp;
 		*vp = ncp->nc_dvp;
 		vref(*vp);
-		CACHE_RUNLOCK();
+		mtx_unlock(vlp);
 		vrele(dvp);
-		CACHE_RLOCK();
 		return (0);
 	}
 	SDT_PROBE1(vfs, namecache, fullpath, miss, vp);
 
-	CACHE_RUNLOCK();
+	mtx_unlock(vlp);
 	vn_lock(*vp, LK_SHARED | LK_RETRY);
 	error = VOP_VPTOCNP(*vp, &dvp, cred, buf, buflen);
 	vput(*vp);
@@ -1499,10 +2009,8 @@ vn_vptocnp_locked(struct vnode **vp, struct ucred *cred, char *buf,
 	}
 
 	*vp = dvp;
-	CACHE_RLOCK();
 	if (dvp->v_iflag & VI_DOOMED) {
 		/* forced unmount */
-		CACHE_RUNLOCK();
 		vrele(dvp);
 		error = ENOENT;
 		SDT_PROBE3(vfs, namecache, fullpath, return, error, vp, NULL);
@@ -1536,13 +2044,11 @@ vn_fullpath1(struct thread *td, struct vnode *vp, struct vnode *rdir,
 	SDT_PROBE1(vfs, namecache, fullpath, entry, vp);
 	counter_u64_add(numfullpathcalls, 1);
 	vref(vp);
-	CACHE_RLOCK();
 	if (vp->v_type != VDIR) {
-		error = vn_vptocnp_locked(&vp, td->td_ucred, buf, &buflen);
+		error = vn_vptocnp(&vp, td->td_ucred, buf, &buflen);
 		if (error)
 			return (error);
 		if (buflen == 0) {
-			CACHE_RUNLOCK();
 			vrele(vp);
 			return (ENOMEM);
 		}
@@ -1552,7 +2058,6 @@ vn_fullpath1(struct thread *td, struct vnode *vp, struct vnode *rdir,
 	while (vp != rdir && vp != rootvnode) {
 		if (vp->v_vflag & VV_ROOT) {
 			if (vp->v_iflag & VI_DOOMED) {	/* forced unmount */
-				CACHE_RUNLOCK();
 				vrele(vp);
 				error = ENOENT;
 				SDT_PROBE3(vfs, namecache, fullpath, return,
@@ -1561,14 +2066,11 @@ vn_fullpath1(struct thread *td, struct vnode *vp, struct vnode *rdir,
 			}
 			vp1 = vp->v_mount->mnt_vnodecovered;
 			vref(vp1);
-			CACHE_RUNLOCK();
 			vrele(vp);
 			vp = vp1;
-			CACHE_RLOCK();
 			continue;
 		}
 		if (vp->v_type != VDIR) {
-			CACHE_RUNLOCK();
 			vrele(vp);
 			counter_u64_add(numfullpathfail1, 1);
 			error = ENOTDIR;
@@ -1576,11 +2078,10 @@ vn_fullpath1(struct thread *td, struct vnode *vp, struct vnode *rdir,
 			    error, vp, NULL);
 			break;
 		}
-		error = vn_vptocnp_locked(&vp, td->td_ucred, buf, &buflen);
+		error = vn_vptocnp(&vp, td->td_ucred, buf, &buflen);
 		if (error)
 			break;
 		if (buflen == 0) {
-			CACHE_RUNLOCK();
 			vrele(vp);
 			error = ENOMEM;
 			SDT_PROBE3(vfs, namecache, fullpath, return, error,
@@ -1594,7 +2095,6 @@ vn_fullpath1(struct thread *td, struct vnode *vp, struct vnode *rdir,
 		return (error);
 	if (!slash_prefixed) {
 		if (buflen == 0) {
-			CACHE_RUNLOCK();
 			vrele(vp);
 			counter_u64_add(numfullpathfail4, 1);
 			SDT_PROBE3(vfs, namecache, fullpath, return, ENOMEM,
@@ -1604,7 +2104,6 @@ vn_fullpath1(struct thread *td, struct vnode *vp, struct vnode *rdir,
 		buf[--buflen] = '/';
 	}
 	counter_u64_add(numfullpathfound, 1);
-	CACHE_RUNLOCK();
 	vrele(vp);
 
 	SDT_PROBE3(vfs, namecache, fullpath, return, 0, startvp, buf + buflen);
@@ -1617,20 +2116,22 @@ vn_dir_dd_ino(struct vnode *vp)
 {
 	struct namecache *ncp;
 	struct vnode *ddvp;
+	struct mtx *vlp;
 
 	ASSERT_VOP_LOCKED(vp, "vn_dir_dd_ino");
-	CACHE_RLOCK();
+	vlp = VP2VNODELOCK(vp);
+	mtx_lock(vlp);
 	TAILQ_FOREACH(ncp, &(vp->v_cache_dst), nc_dst) {
 		if ((ncp->nc_flag & NCF_ISDOTDOT) != 0)
 			continue;
 		ddvp = ncp->nc_dvp;
 		vhold(ddvp);
-		CACHE_RUNLOCK();
+		mtx_unlock(vlp);
 		if (vget(ddvp, LK_SHARED | LK_NOWAIT | LK_VNHELD, curthread))
 			return (NULL);
 		return (ddvp);
 	}
-	CACHE_RUNLOCK();
+	mtx_unlock(vlp);
 	return (NULL);
 }
 
@@ -1638,19 +2139,21 @@ int
 vn_commname(struct vnode *vp, char *buf, u_int buflen)
 {
 	struct namecache *ncp;
+	struct mtx *vlp;
 	int l;
 
-	CACHE_RLOCK();
+	vlp = VP2VNODELOCK(vp);
+	mtx_lock(vlp);
 	TAILQ_FOREACH(ncp, &vp->v_cache_dst, nc_dst)
 		if ((ncp->nc_flag & NCF_ISDOTDOT) == 0)
 			break;
 	if (ncp == NULL) {
-		CACHE_RUNLOCK();
+		mtx_unlock(vlp);
 		return (ENOENT);
 	}
 	l = min(ncp->nc_nlen, buflen - 1);
 	memcpy(buf, nc_get_name(ncp), l);
-	CACHE_RUNLOCK();
+	mtx_unlock(vlp);
 	buf[l] = '\0';
 	return (0);
 }
diff --git a/sys/kern/vfs_mount.c b/sys/kern/vfs_mount.c
index f5177b1eeb8d..c09b1fad6c8c 100644
--- a/sys/kern/vfs_mount.c
+++ b/sys/kern/vfs_mount.c
@@ -1207,6 +1207,9 @@ sys_unmount(struct thread *td, struct unmount_args *uap)
 /*
  * Return error if any of the vnodes, ignoring the root vnode
  * and the syncer vnode, have non-zero usecount.
+ *
+ * This function is purely advisory - it can return false positives
+ * and negatives.
  */
 static int
 vfs_check_usecounts(struct mount *mp)
@@ -1288,6 +1291,10 @@ dounmount(struct mount *mp, int flags, struct thread *td)
 		MNT_ILOCK(mp);
 		if (error != 0) {
 			mp->mnt_kern_flag &= ~(MNTK_UNMOUNT | MNTK_NOINSMNTQ);
+			if (mp->mnt_kern_flag & MNTK_MWAIT) {
+				mp->mnt_kern_flag &= ~MNTK_MWAIT;
+				wakeup(mp);
+			}
 			MNT_IUNLOCK(mp);
 			if (coveredvp != NULL) {
 				VOP_UNLOCK(coveredvp, 0);
diff --git a/sys/mips/broadcom/bcm_bmips.c b/sys/mips/broadcom/bcm_bmips.c
new file mode 100644
index 000000000000..b69abd99228e
--- /dev/null
+++ b/sys/mips/broadcom/bcm_bmips.c
@@ -0,0 +1,123 @@
+/*-
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/bhnd/bhnd.h>
+
+#include "bcm_bmipsreg.h"
+
+/*
+ * BMIPS32 and BMIPS3300 core driver.
+ *
+ * These cores are only found on siba(4) chipsets, allowing
+ * us to assume the availability of siba interrupt registers.
+ */
+
+static const struct bhnd_device bcm_bmips_devs[] = {
+	BHND_DEVICE(BCM, MIPS33, NULL, NULL, BHND_DF_SOC),
+	BHND_DEVICE_END
+};
+
+struct bcm_bmips_softc {
+	device_t		 dev;
+	struct resource		*mem_res;
+	int			 mem_rid;
+};
+
+static int
+bcm_bmips_probe(device_t dev)
+{
+	const struct bhnd_device	*id;
+
+	id = bhnd_device_lookup(dev, bcm_bmips_devs,
+	    sizeof(bcm_bmips_devs[0]));
+	if (id == NULL)
+		return (ENXIO);
+
+	bhnd_set_default_core_desc(dev);
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+bcm_bmips_attach(device_t dev)
+{
+	struct bcm_bmips_softc *sc;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	/* Allocate bus resources */
+	sc->mem_rid = 0;
+	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
+	    RF_ACTIVE);
+	if (sc->mem_res == NULL)
+		return (ENXIO);
+
+	return (0);
+}
+
+static int
+bcm_bmips_detach(device_t dev)
+{
+	struct bcm_bmips_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
+
+	return (0);
+}
+
+static device_method_t bcm_bmips_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,			bcm_bmips_probe),
+	DEVMETHOD(device_attach,		bcm_bmips_attach),
+	DEVMETHOD(device_detach,		bcm_bmips_detach),
+	
+	DEVMETHOD_END
+};
+
+static devclass_t bcm_mips_devclass;
+
+DEFINE_CLASS_0(bcm_mips, bcm_bmips_driver, bcm_bmips_methods, sizeof(struct bcm_bmips_softc));
+EARLY_DRIVER_MODULE(bcm_bmips, bhnd, bcm_bmips_driver, bcm_mips_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
+
+MODULE_VERSION(bcm_bmips, 1);
+MODULE_DEPEND(bcm_bmips, bhnd, 1, 1, 1);
diff --git a/sys/mips/broadcom/bcm_mips_exts.h b/sys/mips/broadcom/bcm_bmips_exts.h
index 582fb8b3068f..1ced180b7763 100644
--- a/sys/mips/broadcom/bcm_mips_exts.h
+++ b/sys/mips/broadcom/bcm_bmips_exts.h
@@ -52,8 +52,8 @@
     *
     *********************************************************************/
 
-#ifndef _MIPS_BROADCOM_BCM_MIPS_EXTS_H_
-#define _MIPS_BROADCOM_BCM_MIPS_EXTS_H_
+#ifndef _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
+#define _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
 
 #include <machine/cpufunc.h>
 
@@ -62,15 +62,15 @@
  * BMIPS330x MIPS32 core.
  */
 
-#define	MIPS_COP_0_BCMCFG	22
+#define	BMIPS_COP_0_BCMCFG	22
 
 /*
  * Custom CP0 Accessors
  */
 
-#define	BCM_MIPS_RW32_COP0_SEL(n,r,s)				\
+#define	BCM_BMIPS_RW32_COP0_SEL(n,r,s)				\
 static __inline uint32_t					\
-bcm_mips_rd_ ## n(void)						\
+bcm_bmips_rd_ ## n(void)					\
 {								\
 	int v0;							\
 	__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"	\
@@ -79,7 +79,7 @@ bcm_mips_rd_ ## n(void)						\
 	return (v0);						\
 }								\
 static __inline void						\
-bcm_mips_wr_ ## n(uint32_t a0)					\
+bcm_bmips_wr_ ## n(uint32_t a0)					\
 {								\
 	__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";"	\
 			 __XSTRING(COP0_SYNC)";"		\
@@ -90,101 +90,101 @@ bcm_mips_wr_ ## n(uint32_t a0)					\
 	mips_barrier();						\
 } struct __hack
 
-BCM_MIPS_RW32_COP0_SEL(pllcfg1,	MIPS_COP_0_CONFIG,	1);
-BCM_MIPS_RW32_COP0_SEL(pllcfg2,	MIPS_COP_0_CONFIG,	2);
-BCM_MIPS_RW32_COP0_SEL(clksync,	MIPS_COP_0_CONFIG,	3);
-BCM_MIPS_RW32_COP0_SEL(pllcfg3,	MIPS_COP_0_CONFIG,	4);
-BCM_MIPS_RW32_COP0_SEL(rstcfg,	MIPS_COP_0_CONFIG,	5);
+BCM_BMIPS_RW32_COP0_SEL(pllcfg1,	MIPS_COP_0_CONFIG,	1);
+BCM_BMIPS_RW32_COP0_SEL(pllcfg2,	MIPS_COP_0_CONFIG,	2);
+BCM_BMIPS_RW32_COP0_SEL(clksync,	MIPS_COP_0_CONFIG,	3);
+BCM_BMIPS_RW32_COP0_SEL(pllcfg3,	MIPS_COP_0_CONFIG,	4);
+BCM_BMIPS_RW32_COP0_SEL(rstcfg,		MIPS_COP_0_CONFIG,	5);
 
 /*
  * Broadcom PLLConfig1 Register (22, select 1)
  */
 
 /* SoftMIPSPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG1_MC_SHIFT	10
-#define	MIPS_BCMCFG_PLLCFG1_MC_MASK	0xFFFFFC00
+#define	BMIPS_BCMCFG_PLLCFG1_MC_SHIFT	10
+#define	BMIPS_BCMCFG_PLLCFG1_MC_MASK	0xFFFFFC00
 
 /* SoftISBPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG1_BC_SHIFT	5
-#define	MIPS_BCMCFG_PLLCFG1_BC_MASK	0x000003E0
+#define	BMIPS_BCMCFG_PLLCFG1_BC_SHIFT	5
+#define	BMIPS_BCMCFG_PLLCFG1_BC_MASK	0x000003E0
 
 /* SoftRefPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG1_PC_SHIFT	0
-#define	MIPS_BCMCFG_PLLCFG1_PC_MASK	0x0000001F
+#define	BMIPS_BCMCFG_PLLCFG1_PC_SHIFT	0
+#define	BMIPS_BCMCFG_PLLCFG1_PC_MASK	0x0000001F
 
 /*
  * Broadcom PLLConfig2 Register (22, select 2)
  */
 
 /* Soft1to1ClkRatio */
-#define	MIPS_BCMCFG_PLLCFG2_CR		(1<<23)
+#define	BMIPS_BCMCFG_PLLCFG2_CR		(1<<23)
 
 /* SoftUSBxPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG2_UC_SHIFT	15
-#define	MIPS_BCMCFG_PLLCFG2_UC_MASK	0x007F8000
+#define	BMIPS_BCMCFG_PLLCFG2_UC_SHIFT	15
+#define	BMIPS_BCMCFG_PLLCFG2_UC_MASK	0x007F8000
 
 /* SoftIDExPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG2_IC_SHIFT	7
-#define	MIPS_BCMCFG_PLLCFG2_IC_MASK	0x00007F80
+#define	BMIPS_BCMCFG_PLLCFG2_IC_SHIFT	7
+#define	BMIPS_BCMCFG_PLLCFG2_IC_MASK	0x00007F80
 
-#define	MIPS_BCMCFG_PLLCFG2_BE		(1<<6)	/* ISBxSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_UE		(1<<5)	/* USBxSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_IE		(1<<4)	/* IDExSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_CA		(1<<3)	/* CfgActive */
-#define	MIPS_BCMCFG_PLLCFG2_CF		(1<<2)	/* RefSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_CI		(1<<1)	/* ISBSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_CC		(1<<0)	/* MIPSSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_BE		(1<<6)	/* ISBxSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_UE		(1<<5)	/* USBxSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_IE		(1<<4)	/* IDExSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_CA		(1<<3)	/* CfgActive */
+#define	BMIPS_BCMCFG_PLLCFG2_CF		(1<<2)	/* RefSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_CI		(1<<1)	/* ISBSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_CC		(1<<0)	/* MIPSSoftCfgEnable */
 
 /*
  * Broadcom ClkSync Register (22, select 3)
  */
 /* SoftClkCfgHigh */
-#define	MIPS_BCMCFG_CLKSYNC_CH_SHIFT	16
-#define	MIPS_BCMCFG_CLKSYNC_CH_MASK	0xFFFF0000
+#define	BMIPS_BCMCFG_CLKSYNC_CH_SHIFT	16
+#define	BMIPS_BCMCFG_CLKSYNC_CH_MASK	0xFFFF0000
 
 /* SoftClkCfgLow */
-#define	MIPS_BCMCFG_CLKSYNC_CL_SHIFT	0
-#define	MIPS_BCMCFG_CLKSYNC_CL_MASK	0x0000FFFF
+#define	BMIPS_BCMCFG_CLKSYNC_CL_SHIFT	0
+#define	BMIPS_BCMCFG_CLKSYNC_CL_MASK	0x0000FFFF
 
 /*
  * Broadcom ISBxPLLConfig3 Register (22, select 4)
  */
 
 /* AsyncClkRatio */
-#define	MIPS_BCMCFG_PLLCFG3_AR_SHIFT	23
-#define	MIPS_BCMCFG_PLLCFG3_AR_MASK	0x01800000
+#define	BMIPS_BCMCFG_PLLCFG3_AR_SHIFT	23
+#define	BMIPS_BCMCFG_PLLCFG3_AR_MASK	0x01800000
 
-#define	MIPS_BCMCFG_PLLCFG3_SM		(1<<22)	/* SyncMode */
+#define	BMIPS_BCMCFG_PLLCFG3_SM		(1<<22)	/* SyncMode */
 
 /* SoftISBxPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG3_IC_SHIFT	0
-#define	MIPS_BCMCFG_PLLCFG3_IC_MASK	0x003FFFFF
+#define	BMIPS_BCMCFG_PLLCFG3_IC_SHIFT	0
+#define	BMIPS_BCMCFG_PLLCFG3_IC_MASK	0x003FFFFF
 
 /*
  * Broadcom BRCMRstConfig Register (22, select 5)
  */
 
-#define	MIPS_BCMCFG_RSTCFG_SR		(1<<18)	/* SSMR */
-#define	MIPS_BCMCFG_RSTCFG_DT		(1<<16)	/* BHTD */
+#define	BMIPS_BCMCFG_RSTCFG_SR		(1<<18)	/* SSMR */
+#define	BMIPS_BCMCFG_RSTCFG_DT		(1<<16)	/* BHTD */
 
 /* RStSt */
-#define	MIPS_BCMCFG_RSTCFG_RS_SHIFT	8
-#define	MIPS_BCMCFG_RSTCFG_RS_MASK	0x00001F00
-#define	  MIPS_BCMCFG_RST_OTHER		0x00
-#define	  MIPS_BCMCFG_RST_SH		0x01
-#define	  MIPS_BCMCFG_RST_SS		0x02
-#define	  MIPS_BCMCFG_RST_EJTAG		0x04
-#define	  MIPS_BCMCFG_RST_WDOG		0x08
-#define	  MIPS_BCMCFG_RST_CRC		0x10
+#define	BMIPS_BCMCFG_RSTCFG_RS_SHIFT	8
+#define	BMIPS_BCMCFG_RSTCFG_RS_MASK	0x00001F00
+#define	  BMIPS_BCMCFG_RST_OTHER	0x00
+#define	  BMIPS_BCMCFG_RST_SH		0x01
+#define	  BMIPS_BCMCFG_RST_SS		0x02
+#define	  BMIPS_BCMCFG_RST_EJTAG	0x04
+#define	  BMIPS_BCMCFG_RST_WDOG		0x08
+#define	  BMIPS_BCMCFG_RST_CRC		0x10
 
-#define	MIPS_BCMCFG_RSTCFG_CR		(1<<7)	/* RStCr */
+#define	BMIPS_BCMCFG_RSTCFG_CR		(1<<7)	/* RStCr */
 
 /* WBMD */
-#define	MIPS_BCMCFG_RSTCFG_WD_SHIFT	3
-#define	MIPS_BCMCFG_RSTCFG_WD_MASK	0x00000078
+#define	BMIPS_BCMCFG_RSTCFG_WD_SHIFT	3
+#define	BMIPS_BCMCFG_RSTCFG_WD_MASK	0x00000078
 
-#define	MIPS_BCMCFG_RSTCFG_SS		(1<<2)	/* SSR */
-#define	MIPS_BCMCFG_RSTCFG_SH		(1<<1)	/* SHR */
-#define	MIPS_BCMCFG_RSTCFG_BR		(1<<0)	/* BdR */
+#define	BMIPS_BCMCFG_RSTCFG_SS		(1<<2)	/* SSR */
+#define	BMIPS_BCMCFG_RSTCFG_SH		(1<<1)	/* SHR */
+#define	BMIPS_BCMCFG_RSTCFG_BR		(1<<0)	/* BdR */
 
-#endif /* _MIPS_BROADCOM_BCM_MIPS_EXTS_H_ */
+#endif /* _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_ */
diff --git a/sys/mips/broadcom/bcm_bmipsreg.h b/sys/mips/broadcom/bcm_bmipsreg.h
new file mode 100644
index 000000000000..ff77a20e667e
--- /dev/null
+++ b/sys/mips/broadcom/bcm_bmipsreg.h
@@ -0,0 +1,73 @@
+/*-
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ * 
+ * $FreeBSD$
+ */
+
+#ifndef	_MIPS_BROADCOM_BMIPSREG_H_
+#define	_MIPS_BROADCOM_BMIPSREG_H_
+
+/*
+ * Common BMIPS32/BMIPS3300 Registers
+ */
+#define	BCM_BMIPS_CORECTL		0x00	/**< core control */
+#define	  BCM_BMIPS_CORECTL_FORCE_RST	0x01	/**< force reset */
+#define	  BCM_BMIPS_CORECTL_NO_FLSH_EXC	0x02	/**< flash exception disable */
+#define	BCM_BMIPS_INTR_STATUS		0x20	/**< interrupt status */
+#define	BCM_BMIPS_INTR_MASK		0x24	/**< interrupt mask */
+#define	  BCM_BMIPS_TIMER_INTMASK	0x01	/**< timer interrupt mask */
+#define	BCM_BMIPS_TIMER_CTRL		0x28	/**< timer interval (?) */
+
+/*
+ * Broadcom BMIPS32 (BHND_COREID_MIPS)
+ */
+
+#define	BCM_BMIPS32_CORECTL		BCM_BMIPS_CORECTL
+#define	BCM_BMIPS32_BIST_STATUS		0x04	/**< built-in self-test status */
+#define	BCM_BMIPS32_INTR_STATUS		BCM_BMIPS_INTR_STATUS
+#define	BCM_BMIPS32_INTR_MASK		BCM_BMIPS_INTR_MASK
+#define	BCM_BMIPS32_TIMER_CTRL		BCM_BMIPS_TIMER_CTRL
+
+/*
+ * Broadcom BMIPS3300+ (BHND_COREID_MIPS33)
+ */
+
+#define	BCM_BMIPS33_CORECTL		BCM_BMIPS_CORECTL
+#define	BCM_BMIPS33_BIST_CTRL		0x04	/**< build-in self-test control */
+#define	  BCM_BMIPS33_BIST_CTRL_DUMP	0x01	/**< BIST dump */
+#define	  BCM_BMIPS33_BIST_CTRL_DEBUG	0x02	/**< BIST debug */
+#define	  BCM_BMIPS33_BIST_CTRL_HOLD	0x04	/**< BIST hold */
+#define	BCM_BMIPS33_BIST_STATUS		0x08	/**< built-in self-test status */
+#define	BCM_BMIPS33_INTR_STATUS		BCM_BMIPS_INTR_STATUS
+#define	BCM_BMIPS33_INTR_MASK		BCM_BMIPS_INTR_MASK
+#define	BCM_BMIPS33_TIMER_CTRL		BCM_BMIPS_TIMER_CTRL
+#define	BCM_BMIPS33_TEST_MUX_SEL	0x30	/**< test multiplexer select (?) */
+#define	BCM_BMIPS33_TEST_MUX_EN		0x34	/**< test multiplexer enable (?) */
+#define	BCM_BMIPS33_EJTAG_GPIO_EN	0x2C	/**< ejtag gpio enable */
+
+#endif /* _MIPS_BROADCOM_BMIPSREG_H_ */
diff --git a/sys/mips/broadcom/bcm_machdep.c b/sys/mips/broadcom/bcm_machdep.c
index e9cf5060953d..40fa466ce274 100644
--- a/sys/mips/broadcom/bcm_machdep.c
+++ b/sys/mips/broadcom/bcm_machdep.c
@@ -84,7 +84,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/bhnd/cores/pmu/bhnd_pmureg.h>
 
 #include "bcm_machdep.h"
-#include "bcm_mips_exts.h"
+#include "bcm_bmips_exts.h"
 
 #ifdef CFE
 #include <dev/cfe/cfe_api.h>
@@ -436,7 +436,7 @@ platform_reset(void)
 		bcm4785war = true;
 
 		/* Switch to async mode */
-		bcm_mips_wr_pllcfg3(MIPS_BCMCFG_PLLCFG3_SM);
+		bcm_bmips_wr_pllcfg3(BMIPS_BCMCFG_PLLCFG3_SM);
 	}
 
 	/* Set watchdog (PMU or ChipCommon) */
diff --git a/sys/mips/broadcom/bcm_mipscore.c b/sys/mips/broadcom/bcm_mips74k.c
index e48a68f23df8..66ccadd96e2f 100644
--- a/sys/mips/broadcom/bcm_mipscore.c
+++ b/sys/mips/broadcom/bcm_mips74k.c
@@ -1,5 +1,6 @@
 /*-
  * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,41 +35,40 @@ __FBSDID("$FreeBSD$");
 #include <sys/kernel.h>
 #include <sys/bus.h>
 #include <sys/module.h>
-#include <sys/systm.h>
-#include <sys/errno.h>
-#include <sys/rman.h>
-#include <sys/stddef.h>
 
 #include <machine/bus.h>
+#include <sys/rman.h>
 #include <machine/resource.h>
 
 #include <dev/bhnd/bhnd.h>
-#include <dev/bhnd/bhndvar.h>
-#include <dev/bhnd/bhnd_ids.h>
 
-#include "bcm_mipscore.h"
+#include "bcm_mips74kreg.h"
 
-static const struct resource_spec mipscore_rspec[MIPSCORE_MAX_RSPEC] = {
-	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
-	{ -1, -1, 0 }
-};
-
-#define	MIPSCORE_DEV(_vendor, _core)	\
-	BHND_DEVICE(_vendor, _core, NULL, NULL, BHND_DF_SOC)
+/*
+ * Broadcom MIPS74K Core
+ *
+ * These cores are only found on bcma(4) chipsets, allowing
+ * us to assume the availability of bcma interrupt registers.
+ */
 
-struct bhnd_device mipscore_match[] = {
-	MIPSCORE_DEV(BCM, MIPS),
-	MIPSCORE_DEV(BCM, MIPS33),
-	MIPSCORE_DEV(MIPS, MIPS74K),
+static const struct bhnd_device bcm_mips74k_devs[] = {
+	BHND_DEVICE(MIPS, MIPS74K, NULL, NULL, BHND_DF_SOC),
 	BHND_DEVICE_END
 };
 
+struct bcm_mips74k_softc {
+	device_t		 dev;
+	struct resource		*mem_res;
+	int			 mem_rid;
+};
+
 static int
-mipscore_probe(device_t dev)
+bcm_mips74k_probe(device_t dev)
 {
-	const struct bhnd_device *id;
+	const struct bhnd_device	*id;
 
-	id = bhnd_device_lookup(dev, mipscore_match, sizeof(mipscore_match[0]));
+	id = bhnd_device_lookup(dev, bcm_mips74k_devs,
+	    sizeof(bcm_mips74k_devs[0]));
 	if (id == NULL)
 		return (ENXIO);
 
@@ -77,50 +77,51 @@ mipscore_probe(device_t dev)
 }
 
 static int
-mipscore_attach(device_t dev)
+bcm_mips74k_attach(device_t dev)
 {
-	struct mipscore_softc 	*sc;
-	struct resource 	*res;
-	uint32_t		 intmask;
-	uint16_t		 devid;
-	int			 error;
+	struct bcm_mips74k_softc *sc;
 
 	sc = device_get_softc(dev);
-	devid = bhnd_get_device(dev);
-
-	sc->devid = devid;
 	sc->dev = dev;
 
 	/* Allocate bus resources */
-	memcpy(sc->rspec, mipscore_rspec, sizeof(sc->rspec));
-	error = bhnd_alloc_resources(dev, sc->rspec, sc->res);
-	if (error)
-		return (error);
-
-	res = sc->res[0]->res;
-	if (res == NULL)
+	sc->mem_rid = 0;
+	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
+	    RF_ACTIVE);
+	if (sc->mem_res == NULL)
 		return (ENXIO);
 
-	if (devid == BHND_COREID_MIPS74K) {
-		intmask = (1 << 31);
-		/* Use intmask5 register to route the timer interrupt */
-		bus_write_4(res, offsetof(struct mipscore_regs, intmask[5]),
-				intmask);
-	}
+	/* Route MIPS timer to IRQ5 */
+	bus_write_4(sc->mem_res, BCM_MIPS74K_INTR5_SEL,
+	    (1<<BCM_MIPS74K_TIMER_IVEC));
+
+	return (0);
+}
+
+static int
+bcm_mips74k_detach(device_t dev)
+{
+	struct bcm_mips74k_softc	*sc;
+
+	sc = device_get_softc(dev);
+
+	bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
 
 	return (0);
 }
 
-static device_method_t mipscore_methods[] = {
-		DEVMETHOD(device_probe, 	mipscore_probe),
-		DEVMETHOD(device_attach,	mipscore_attach),
-		DEVMETHOD_END
+static device_method_t bcm_mips74k_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,			bcm_mips74k_probe),
+	DEVMETHOD(device_attach,		bcm_mips74k_attach),
+	DEVMETHOD(device_detach,		bcm_mips74k_detach),
+	
+	DEVMETHOD_END
 };
 
-devclass_t bhnd_mipscore_devclass;
+static devclass_t bcm_mips_devclass;
 
-DEFINE_CLASS_0(bhnd_mips, mipscore_driver, mipscore_methods,
-    sizeof(struct mipscore_softc));
-EARLY_DRIVER_MODULE(bhnd_mips, bhnd, mipscore_driver,
-    bhnd_mipscore_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
-MODULE_VERSION(bhnd_mips, 1);
+DEFINE_CLASS_0(bcm_mips, bcm_mips74k_driver, bcm_mips74k_methods, sizeof(struct bcm_mips74k_softc));
+EARLY_DRIVER_MODULE(bcm_mips74k, bhnd, bcm_mips74k_driver, bcm_mips_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
+MODULE_VERSION(bcm_mips74k, 1);
+MODULE_DEPEND(bcm_mips74k, bhnd, 1, 1, 1);
diff --git a/sys/mips/broadcom/bcm_mipscore.h b/sys/mips/broadcom/bcm_mips74kreg.h
index fd5b5a856081..fb1f516125e8 100644
--- a/sys/mips/broadcom/bcm_mipscore.h
+++ b/sys/mips/broadcom/bcm_mips74kreg.h
@@ -1,5 +1,5 @@
 /*-
- * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,36 +25,38 @@
  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGES.
- *
- *  $FreeBSD$
+ * 
+ * $FreeBSD$
  */
 
-#ifndef _BHND_CORES_MIPS_MIPSCOREVAR_H_
-#define _BHND_CORES_MIPS_MIPSCOREVAR_H_
-
-#define	MIPSCORE_MAX_RSPEC 2
-
-struct mipscore_softc {
-	device_t		dev;	/* CPU device */
-	uint32_t		devid;
-	struct resource_spec	rspec[MIPSCORE_MAX_RSPEC];
-	struct bhnd_resource	*res[MIPSCORE_MAX_RSPEC];
-};
-
-struct mipscore_regs {
-        uint32_t	corecontrol;
-        uint32_t	exceptionbase;
-        uint32_t	PAD1[1];	/* unmapped address */
-        uint32_t	biststatus;
-        uint32_t	intstatus;
-        uint32_t	intmask[6];
-        uint32_t	nmimask;
-        uint32_t	PAD2[4];	/* unmapped addresses */
-        uint32_t	gpioselect;
-        uint32_t	gpiooutput;
-        uint32_t	gpioenable;
-        uint32_t	PAD3[101];	/* unmapped addresses */
-        uint32_t	clkcontrolstatus;
-};
-
-#endif /* _BHND_CORES_MIPS_MIPSCOREVAR_H_ */
+#ifndef	_MIPS_BROADCOM_MIPS74KREG_H_
+#define	_MIPS_BROADCOM_MIPS74KREG_H_
+
+#define	BCM_MIPS74K_CORECTL		0x00	/**< core control */
+#define	BCM_MIPS74K_EXCBASE		0x04	/**< exception base */
+
+#define	BCM_MIPS74K_BIST_STATUS		0x0C	/**< built-in self-test status */
+#define	BCM_MIPS74K_INTR_STATUS		0x10	/**< interrupt status */
+
+/* INTR(0-5)_MASK map bcma(4) OOB interrupt bus lines to MIPS hardware
+ * interrupts. */
+#define	BCM_MIPS74K_INTR0_SEL		0x14	/**< IRQ0 OOBSEL mask */
+#define	BCM_MIPS74K_INTR1_SEL		0x18	/**< IRQ1 OOBSEL mask */
+#define	BCM_MIPS74K_INTR2_SEL		0x1C	/**< IRQ2 OOBSEL mask */
+#define	BCM_MIPS74K_INTR3_SEL		0x20	/**< IRQ3 OOBSEL mask */
+#define	BCM_MIPS74K_INTR4_SEL		0x24	/**< IRQ4 OOBSEL mask */
+#define	BCM_MIPS74K_INTR5_SEL		0x28	/**< IRQ5 OOBSEL mask */
+
+#define	BCM_MIPS74K_INTR_SEL(_intr)	\
+	(BCM_MIPS74K_INTR0_SEL + ((_intr) * 4))
+
+#define	BCM_MIPS74K_NMI_MASK		0x2C	/**< nmi mask */
+
+#define	BCM_MIPS74K_GPIO_SEL		0x40	/**< gpio select */
+#define	BCM_MIPS74K_GPIO_OUT		0x44	/**< gpio output enable */
+#define	BCM_MIPS74K_GPIO_EN		0x48	/**< gpio enable */
+
+
+#define	BCM_MIPS74K_TIMER_IVEC		31	/**< MIPS timer OOBSEL value */
+
+#endif /* _MIPS_BROADCOM_MIPS74KREG_H_ */
diff --git a/sys/mips/broadcom/files.broadcom b/sys/mips/broadcom/files.broadcom
index 77436f154c9e..ab534eca1606 100644
--- a/sys/mips/broadcom/files.broadcom
+++ b/sys/mips/broadcom/files.broadcom
@@ -5,6 +5,8 @@
 # which are believed to be devices we have drivers for
 # which just need to be tweaked for attachment to an BHND system bus.
 mips/broadcom/bcm_machdep.c		standard
+mips/broadcom/bcm_bmips.c		optional siba_nexus siba
+mips/broadcom/bcm_mips74k.c		optional bcma_nexus bcma
 mips/broadcom/bcm_pmu.c			standard
 mips/mips/tick.c			standard
 mips/mips/mips_pic.c			standard
@@ -15,7 +17,6 @@ kern/msi_if.m				optional intrng
 
 mips/broadcom/uart_cpu_chipc.c		optional uart
 mips/broadcom/uart_bus_chipc.c		optional uart
-mips/broadcom/bcm_mipscore.c		standard
 
 # TODO: Replace with BCM47xx/57xx/etc-aware geom_map
 geom/geom_flashmap.c			standard
@@ -23,4 +24,4 @@ geom/geom_flashmap.c			standard
 # USB bits
 dev/bhnd/cores/usb/bhnd_usb.c		optional usb
 dev/bhnd/cores/usb/bhnd_ehci.c		optional ehci
-dev/bhnd/cores/usb/bhnd_ohci.c		optional ohci
\ No newline at end of file
+dev/bhnd/cores/usb/bhnd_ohci.c		optional ohci
diff --git a/sys/mips/mips/elf_machdep.c b/sys/mips/mips/elf_machdep.c
index 5f4161b259c1..c58a3f33017e 100644
--- a/sys/mips/mips/elf_machdep.c
+++ b/sys/mips/mips/elf_machdep.c
@@ -92,7 +92,8 @@ static Elf64_Brandinfo freebsd_brand_info = {
 	.interp_path	= "/libexec/ld-elf.so.1",
 	.sysvec		= &elf64_freebsd_sysvec,
 	.interp_newpath	= NULL,
-	.flags		= 0
+	.brand_note	= &elf64_freebsd_brandnote,
+	.flags		= BI_BRAND_NOTE
 };
 
 SYSINIT(elf64, SI_SUB_EXEC, SI_ORDER_ANY,
@@ -147,7 +148,8 @@ static Elf32_Brandinfo freebsd_brand_info = {
 	.interp_path	= "/libexec/ld-elf.so.1",
 	.sysvec		= &elf32_freebsd_sysvec,
 	.interp_newpath	= NULL,
-	.flags		= 0
+	.brand_note	= &elf32_freebsd_brandnote,
+	.flags		= BI_BRAND_NOTE
 };
 
 SYSINIT(elf32, SI_SUB_EXEC, SI_ORDER_FIRST,
diff --git a/sys/mips/mips/freebsd32_machdep.c b/sys/mips/mips/freebsd32_machdep.c
index 8ce15b460be8..cb72891f23d2 100644
--- a/sys/mips/mips/freebsd32_machdep.c
+++ b/sys/mips/mips/freebsd32_machdep.c
@@ -117,7 +117,8 @@ static Elf32_Brandinfo freebsd_brand_info = {
 	.interp_path	= "/libexec/ld-elf.so.1",
 	.sysvec		= &elf32_freebsd_sysvec,
 	.interp_newpath	= "/libexec/ld-elf32.so.1",
-	.flags		= 0
+	.brand_note	= &elf32_freebsd_brandnote,
+	.flags		= BI_BRAND_NOTE
 };
 
 SYSINIT(elf32, SI_SUB_EXEC, SI_ORDER_FIRST,
diff --git a/sys/modules/Makefile b/sys/modules/Makefile
index 6a616764a734..bd6326175d5b 100644
--- a/sys/modules/Makefile
+++ b/sys/modules/Makefile
@@ -103,6 +103,7 @@ SUBDIR=	\
 	${_drm2} \
 	dummynet \
 	${_ed} \
+	${_efirt} \
 	${_elink} \
 	${_em} \
 	en \
@@ -669,6 +670,7 @@ _x86bios=	x86bios
 .endif
 
 .if ${MACHINE_CPUARCH} == "amd64"
+_efirt=		efirt
 _ioat=		ioat
 _ixl=		ixl
 _ixlv=		ixlv
@@ -766,7 +768,8 @@ _epic=		epic
 _igb=		igb
 .endif
 
-.if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386"
+.if (${MACHINE_CPUARCH} == "amd64" || ${MACHINE_ARCH} == "armv6" || \
+     ${MACHINE_CPUARCH} == "i386")
 _cloudabi32=	cloudabi32
 .endif
 .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64"
diff --git a/sys/modules/bhnd/bcma/Makefile b/sys/modules/bhnd/bcma/Makefile
index 59d1eb5f1413..8b86c3e6500e 100644
--- a/sys/modules/bhnd/bcma/Makefile
+++ b/sys/modules/bhnd/bcma/Makefile
@@ -6,6 +6,6 @@ KMOD=	bcma
 SRCS=	bcma.c bcma_subr.c bcma_erom.c
 
 SRCS+=	device_if.h bus_if.h
-SRCS+=	bhnd_bus_if.h bhnd_erom_if.h
+SRCS+=	bhnd_bus_if.h bhnd_erom_if.h bhnd_pmu_if.h
 
 .include <bsd.kmod.mk>
diff --git a/sys/modules/bhnd/siba/Makefile b/sys/modules/bhnd/siba/Makefile
index 0bf58e80a7c2..7c6a69272ae0 100644
--- a/sys/modules/bhnd/siba/Makefile
+++ b/sys/modules/bhnd/siba/Makefile
@@ -7,6 +7,6 @@ SRCS=	siba.c siba_subr.c \
 	siba_erom.c
 
 SRCS+=	device_if.h bus_if.h
-SRCS+=	bhnd_bus_if.h bhnd_erom_if.h
+SRCS+=	bhnd_bus_if.h bhnd_erom_if.h bhnd_pmu_if.h
 
 .include <bsd.kmod.mk>
diff --git a/sys/modules/cloudabi32/Makefile b/sys/modules/cloudabi32/Makefile
index 10851bdba26d..61e5142824e7 100644
--- a/sys/modules/cloudabi32/Makefile
+++ b/sys/modules/cloudabi32/Makefile
@@ -14,14 +14,18 @@ SRCS=	cloudabi32_fd.c cloudabi32_module.c cloudabi32_poll.c \
 OBJS=	cloudabi32_vdso_blob.o
 CLEANFILES=cloudabi32_vdso.o
 
-.if ${MACHINE_CPUARCH} == "i386"
-VDSO_SRCS=${SYSDIR}/contrib/cloudabi/cloudabi_vdso_i686.S
-OUTPUT_TARGET=elf32-i386-freebsd
-BINARY_ARCHITECTURE=aarch32
-.elif ${MACHINE_CPUARCH} == "amd64"
+.if ${MACHINE_CPUARCH} == "amd64"
 VDSO_SRCS=${SYSDIR}/contrib/cloudabi/cloudabi_vdso_i686_on_64bit.S
 OUTPUT_TARGET=elf64-x86-64-freebsd
 BINARY_ARCHITECTURE=i386
+.elif ${MACHINE_ARCH} == "armv6"
+VDSO_SRCS=${SYSDIR}/contrib/cloudabi/cloudabi_vdso_armv6.S
+OUTPUT_TARGET=elf32-littlearm
+BINARY_ARCHITECTURE=arm
+.elif ${MACHINE_CPUARCH} == "i386"
+VDSO_SRCS=${SYSDIR}/contrib/cloudabi/cloudabi_vdso_i686.S
+OUTPUT_TARGET=elf32-i386-freebsd
+BINARY_ARCHITECTURE=i386
 .endif
 
 cloudabi32_vdso.o: ${VDSO_SRCS}
diff --git a/sys/modules/efirt/Makefile b/sys/modules/efirt/Makefile
new file mode 100644
index 000000000000..2dff20d73804
--- /dev/null
+++ b/sys/modules/efirt/Makefile
@@ -0,0 +1,9 @@
+# $FreeBSD$
+
+.PATH: ${.CURDIR}/../../${MACHINE}/${MACHINE}
+
+KMOD=	efirt
+SRCS=	efirt.c
+SRCS+=  device_if.h bus_if.h
+
+.include <bsd.kmod.mk>
diff --git a/sys/modules/usb/ukbd/Makefile b/sys/modules/usb/ukbd/Makefile
index e9861916acb1..3db978a486ce 100644
--- a/sys/modules/usb/ukbd/Makefile
+++ b/sys/modules/usb/ukbd/Makefile
@@ -30,7 +30,7 @@ S=     ${.CURDIR}/../../..
 .PATH: $S/dev/usb/input
 
 KMOD=	ukbd
-SRCS=	opt_bus.h opt_compat.h opt_kbd.h opt_ukbd.h opt_usb.h \
+SRCS=	opt_bus.h opt_compat.h opt_evdev.h opt_kbd.h opt_ukbd.h opt_usb.h \
 	device_if.h bus_if.h usb_if.h usbdevs.h \
 	ukbd.c
 
diff --git a/sys/modules/usb/ums/Makefile b/sys/modules/usb/ums/Makefile
index fb24f0dbb7be..197415f6e2f2 100644
--- a/sys/modules/usb/ums/Makefile
+++ b/sys/modules/usb/ums/Makefile
@@ -30,7 +30,7 @@ S=     ${.CURDIR}/../../..
 .PATH: $S/dev/usb/input
 
 KMOD=	ums
-SRCS=	opt_bus.h opt_usb.h device_if.h bus_if.h usb_if.h vnode_if.h usbdevs.h \
-	ums.c
+SRCS=	opt_bus.h opt_evdev.h opt_usb.h device_if.h bus_if.h usb_if.h \
+	vnode_if.h usbdevs.h ums.c
 
 .include <bsd.kmod.mk>
diff --git a/sys/net/if_bridge.c b/sys/net/if_bridge.c
index ed2176cf9f03..986639da9ccf 100644
--- a/sys/net/if_bridge.c
+++ b/sys/net/if_bridge.c
@@ -333,7 +333,7 @@ static int	bridge_ip_checkbasic(struct mbuf **mp);
 #ifdef INET6
 static int	bridge_ip6_checkbasic(struct mbuf **mp);
 #endif /* INET6 */
-static int	bridge_fragment(struct ifnet *, struct mbuf *,
+static int	bridge_fragment(struct ifnet *, struct mbuf **mp,
 		    struct ether_header *, int, struct llc *);
 static void	bridge_linkstate(struct ifnet *ifp);
 static void	bridge_linkcheck(struct bridge_softc *sc);
@@ -1917,6 +1917,7 @@ bridge_enqueue(struct bridge_softc *sc, struct ifnet *dst_ifp, struct mbuf *m)
 			m->m_flags &= ~M_VLANTAG;
 		}
 
+		M_ASSERTPKTHDR(m); /* We shouldn't transmit mbuf without pkthdr */
 		if ((err = dst_ifp->if_transmit(dst_ifp, m))) {
 			m_freem(m0);
 			if_inc_counter(sc->sc_ifp, IFCOUNTER_OERRORS, 1);
@@ -3234,10 +3235,12 @@ bridge_pfil(struct mbuf **mp, struct ifnet *bifp, struct ifnet *ifp, int dir)
 			break;
 
 		/* check if we need to fragment the packet */
+		/* bridge_fragment generates a mbuf chain of packets */
+		/* that already include eth headers */
 		if (V_pfil_member && ifp != NULL && dir == PFIL_OUT) {
 			i = (*mp)->m_pkthdr.len;
 			if (i > ifp->if_mtu) {
-				error = bridge_fragment(ifp, *mp, &eh2, snap,
+				error = bridge_fragment(ifp, mp, &eh2, snap,
 					    &llc1);
 				return (error);
 			}
@@ -3476,56 +3479,77 @@ bad:
 /*
  * bridge_fragment:
  *
- *	Return a fragmented mbuf chain.
+ *	Fragment mbuf chain in multiple packets and prepend ethernet header.
  */
 static int
-bridge_fragment(struct ifnet *ifp, struct mbuf *m, struct ether_header *eh,
+bridge_fragment(struct ifnet *ifp, struct mbuf **mp, struct ether_header *eh,
     int snap, struct llc *llc)
 {
-	struct mbuf *m0;
+	struct mbuf *m = *mp, *nextpkt = NULL, *mprev = NULL, *mcur = NULL;
 	struct ip *ip;
 	int error = -1;
 
 	if (m->m_len < sizeof(struct ip) &&
 	    (m = m_pullup(m, sizeof(struct ip))) == NULL)
-		goto out;
+		goto dropit;
 	ip = mtod(m, struct ip *);
 
 	m->m_pkthdr.csum_flags |= CSUM_IP;
 	error = ip_fragment(ip, &m, ifp->if_mtu, ifp->if_hwassist);
 	if (error)
-		goto out;
+		goto dropit;
 
-	/* walk the chain and re-add the Ethernet header */
-	for (m0 = m; m0; m0 = m0->m_nextpkt) {
-		if (error == 0) {
-			if (snap) {
-				M_PREPEND(m0, sizeof(struct llc), M_NOWAIT);
-				if (m0 == NULL) {
-					error = ENOBUFS;
-					continue;
-				}
-				bcopy(llc, mtod(m0, caddr_t),
-				    sizeof(struct llc));
-			}
-			M_PREPEND(m0, ETHER_HDR_LEN, M_NOWAIT);
-			if (m0 == NULL) {
+	/*
+	 * Walk the chain and re-add the Ethernet header for
+	 * each mbuf packet.
+	 */
+	for (mcur = m; mcur; mcur = mcur->m_nextpkt) {
+		nextpkt = mcur->m_nextpkt;
+		mcur->m_nextpkt = NULL;
+		if (snap) {
+			M_PREPEND(mcur, sizeof(struct llc), M_NOWAIT);
+			if (mcur == NULL) {
 				error = ENOBUFS;
-				continue;
+				if (mprev != NULL)
+					mprev->m_nextpkt = nextpkt;
+				goto dropit;
 			}
-			bcopy(eh, mtod(m0, caddr_t), ETHER_HDR_LEN);
-		} else
-			m_freem(m);
-	}
+			bcopy(llc, mtod(mcur, caddr_t),sizeof(struct llc));
+		}
+
+		M_PREPEND(mcur, ETHER_HDR_LEN, M_NOWAIT);
+		if (mcur == NULL) {
+			error = ENOBUFS;
+			if (mprev != NULL)
+				mprev->m_nextpkt = nextpkt;
+			goto dropit;
+		}
+		bcopy(eh, mtod(mcur, caddr_t), ETHER_HDR_LEN);
 
-	if (error == 0)
-		KMOD_IPSTAT_INC(ips_fragmented);
+		/*
+		 * The previous two M_PREPEND could have inserted one or two
+		 * mbufs in front so we have to update the previous packet's
+		 * m_nextpkt.
+		 */
+		mcur->m_nextpkt = nextpkt;
+		if (mprev != NULL)
+			mprev->m_nextpkt = mcur;
+		else {
+			/* The first mbuf in the original chain needs to be
+			 * updated. */
+			*mp = mcur;
+		}
+		mprev = mcur;
+	}
 
+	KMOD_IPSTAT_INC(ips_fragmented);
 	return (error);
 
-out:
-	if (m != NULL)
-		m_freem(m);
+dropit:
+	for (mcur = *mp; mcur; mcur = m) { /* droping the full packet chain */
+		m = mcur->m_nextpkt;
+		m_freem(mcur);
+	}
 	return (error);
 }
 
diff --git a/sys/net80211/ieee80211_adhoc.c b/sys/net80211/ieee80211_adhoc.c
index 8d62292c577f..8362f54bf1a7 100644
--- a/sys/net80211/ieee80211_adhoc.c
+++ b/sys/net80211/ieee80211_adhoc.c
@@ -747,8 +747,20 @@ adhoc_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m0,
 			if (!IEEE80211_ADDR_EQ(wh->i_addr2, ni->ni_macaddr)) {
 				/*
 				 * Create a new entry in the neighbor table.
+				 *
+				 * XXX TODO:
+				 *
+				 * Here we're not scanning; so if we have an
+				 * SSID then make sure it matches our SSID.
+				 * Otherwise this code will match on all IBSS
+				 * beacons/probe requests for all SSIDs,
+				 * filling the node table with nodes that
+				 * aren't ours.
 				 */
-				ni = ieee80211_add_neighbor(vap, wh, &scan);
+				if (ieee80211_ibss_node_check_new(ni, &scan))
+					ni = ieee80211_add_neighbor(vap, wh, &scan);
+				else
+					ni = NULL;
 			} else if (ni->ni_capinfo == 0) {
 				/*
 				 * Update faked node created on transmit.
diff --git a/sys/net80211/ieee80211_ht.c b/sys/net80211/ieee80211_ht.c
index 7e3616d3791c..0943f9b09dc0 100644
--- a/sys/net80211/ieee80211_ht.c
+++ b/sys/net80211/ieee80211_ht.c
@@ -2846,6 +2846,96 @@ ieee80211_add_htcap(uint8_t *frm, struct ieee80211_node *ni)
 }
 
 /*
+ * Non-associated probe request - add HT capabilities based on
+ * the current channel configuration.
+ */
+static uint8_t *
+ieee80211_add_htcap_body_ch(uint8_t *frm, struct ieee80211vap *vap,
+    struct ieee80211_channel *c)
+{
+#define	ADDSHORT(frm, v) do {			\
+	frm[0] = (v) & 0xff;			\
+	frm[1] = (v) >> 8;			\
+	frm += 2;				\
+} while (0)
+	struct ieee80211com *ic = vap->iv_ic;
+	uint16_t caps, extcaps;
+	int rxmax, density;
+
+	/* HT capabilities */
+	caps = vap->iv_htcaps & 0xffff;
+
+	/*
+	 * We don't use this in STA mode; only in IBSS mode.
+	 * So in IBSS mode we base our HTCAP flags on the
+	 * given channel.
+	 */
+
+	/* override 20/40 use based on current channel */
+	if (IEEE80211_IS_CHAN_HT40(c))
+		caps |= IEEE80211_HTCAP_CHWIDTH40;
+	else
+		caps &= ~IEEE80211_HTCAP_CHWIDTH40;
+
+	/* Use the currently configured values */
+	rxmax = vap->iv_ampdu_rxmax;
+	density = vap->iv_ampdu_density;
+
+	/* adjust short GI based on channel and config */
+	if ((vap->iv_flags_ht & IEEE80211_FHT_SHORTGI20) == 0)
+		caps &= ~IEEE80211_HTCAP_SHORTGI20;
+	if ((vap->iv_flags_ht & IEEE80211_FHT_SHORTGI40) == 0 ||
+	    (caps & IEEE80211_HTCAP_CHWIDTH40) == 0)
+		caps &= ~IEEE80211_HTCAP_SHORTGI40;
+	ADDSHORT(frm, caps);
+
+	/* HT parameters */
+	*frm = SM(rxmax, IEEE80211_HTCAP_MAXRXAMPDU)
+	     | SM(density, IEEE80211_HTCAP_MPDUDENSITY)
+	     ;
+	frm++;
+
+	/* pre-zero remainder of ie */
+	memset(frm, 0, sizeof(struct ieee80211_ie_htcap) - 
+		__offsetof(struct ieee80211_ie_htcap, hc_mcsset));
+
+	/* supported MCS set */
+	/*
+	 * XXX: For sta mode the rate set should be restricted based
+	 * on the AP's capabilities, but ni_htrates isn't setup when
+	 * we're called to form an AssocReq frame so for now we're
+	 * restricted to the device capabilities.
+	 */
+	ieee80211_set_mcsset(ic, frm);
+
+	frm += __offsetof(struct ieee80211_ie_htcap, hc_extcap) -
+		__offsetof(struct ieee80211_ie_htcap, hc_mcsset);
+
+	/* HT extended capabilities */
+	extcaps = vap->iv_htextcaps & 0xffff;
+
+	ADDSHORT(frm, extcaps);
+
+	frm += sizeof(struct ieee80211_ie_htcap) -
+		__offsetof(struct ieee80211_ie_htcap, hc_txbf);
+
+	return frm;
+#undef ADDSHORT
+}
+
+/*
+ * Add 802.11n HT capabilities information element
+ */
+uint8_t *
+ieee80211_add_htcap_ch(uint8_t *frm, struct ieee80211vap *vap,
+    struct ieee80211_channel *c)
+{
+	frm[0] = IEEE80211_ELEMID_HTCAP;
+	frm[1] = sizeof(struct ieee80211_ie_htcap) - 2;
+	return ieee80211_add_htcap_body_ch(frm + 2, vap, c);
+}
+
+/*
  * Add Broadcom OUI wrapped standard HTCAP ie; this is
  * used for compatibility w/ pre-draft implementations.
  */
diff --git a/sys/net80211/ieee80211_ht.h b/sys/net80211/ieee80211_ht.h
index c0464119aa7c..1ad2d2616860 100644
--- a/sys/net80211/ieee80211_ht.h
+++ b/sys/net80211/ieee80211_ht.h
@@ -210,6 +210,8 @@ void	ieee80211_ampdu_stop(struct ieee80211_node *,
 int	ieee80211_send_bar(struct ieee80211_node *, struct ieee80211_tx_ampdu *,
 		ieee80211_seq);
 uint8_t	*ieee80211_add_htcap(uint8_t *, struct ieee80211_node *);
+uint8_t	*ieee80211_add_htcap_ch(uint8_t *, struct ieee80211vap *,
+	    struct ieee80211_channel *);
 uint8_t	*ieee80211_add_htcap_vendor(uint8_t *, struct ieee80211_node *);
 uint8_t	*ieee80211_add_htinfo(uint8_t *, struct ieee80211_node *);
 uint8_t	*ieee80211_add_htinfo_vendor(uint8_t *, struct ieee80211_node *);
diff --git a/sys/net80211/ieee80211_node.c b/sys/net80211/ieee80211_node.c
index c5b5cc417a16..c375f1cb0b77 100644
--- a/sys/net80211/ieee80211_node.c
+++ b/sys/net80211/ieee80211_node.c
@@ -579,6 +579,62 @@ ieee80211_ibss_merge_check(struct ieee80211_node *ni)
 }
 
 /*
+ * Check if the given node should populate the node table.
+ *
+ * We need to be in "see all beacons for all ssids" mode in order
+ * to do IBSS merges, however this means we will populate nodes for
+ * /all/ IBSS SSIDs, versus just the one we care about.
+ *
+ * So this check ensures the node can actually belong to our IBSS
+ * configuration.  For now it simply checks the SSID.
+ */
+int
+ieee80211_ibss_node_check_new(struct ieee80211_node *ni,
+    const struct ieee80211_scanparams *scan)
+{
+	struct ieee80211vap *vap = ni->ni_vap;
+	int i;
+
+	/*
+	 * If we have no SSID and no scan SSID, return OK.
+	 */
+	if (vap->iv_des_nssid == 0 && scan->ssid == NULL)
+		goto ok;
+
+	/*
+	 * If we have one of (SSID, scan SSID) then return error.
+	 */
+	if (!! (vap->iv_des_nssid == 0) != !! (scan->ssid == NULL))
+		goto mismatch;
+
+	/*
+	 * Double-check - we need scan SSID.
+	 */
+	if (scan->ssid == NULL)
+		goto mismatch;
+
+	/*
+	 * Check if the scan SSID matches the SSID list for the VAP.
+	 */
+	for (i = 0; i < vap->iv_des_nssid; i++) {
+
+		/* Sanity length check */
+		if (vap->iv_des_ssid[i].len != scan->ssid[1])
+			continue;
+
+		/* Note: SSID in the scan entry is the IE format */
+		if (memcmp(vap->iv_des_ssid[i].ssid, scan->ssid + 2,
+		    vap->iv_des_ssid[i].len) == 0)
+			goto ok;
+	}
+
+mismatch:
+	return (0);
+ok:
+	return (1);
+}
+
+/*
  * Handle 802.11 ad hoc network merge.  The
  * convention, set by the Wireless Ethernet Compatibility Alliance
  * (WECA), is that an 802.11 station will change its BSSID to match
diff --git a/sys/net80211/ieee80211_node.h b/sys/net80211/ieee80211_node.h
index 7df0053983f3..a7a0bbd29446 100644
--- a/sys/net80211/ieee80211_node.h
+++ b/sys/net80211/ieee80211_node.h
@@ -65,6 +65,7 @@
 struct ieee80211_node_table;
 struct ieee80211com;
 struct ieee80211vap;
+struct ieee80211_scanparams;
 
 /*
  * Information element ``blob''.  We use this structure
@@ -330,6 +331,8 @@ void	ieee80211_setupcurchan(struct ieee80211com *,
 void	ieee80211_setcurchan(struct ieee80211com *, struct ieee80211_channel *);
 void	ieee80211_update_chw(struct ieee80211com *);
 int	ieee80211_ibss_merge_check(struct ieee80211_node *);
+int	ieee80211_ibss_node_check_new(struct ieee80211_node *ni,
+	    const struct ieee80211_scanparams *);
 int	ieee80211_ibss_merge(struct ieee80211_node *);
 struct ieee80211_scan_entry;
 int	ieee80211_sta_join(struct ieee80211vap *, struct ieee80211_channel *,
diff --git a/sys/netinet/sctp_indata.c b/sys/netinet/sctp_indata.c
index 40112530f4fc..cfdcfe7d0ffb 100644
--- a/sys/netinet/sctp_indata.c
+++ b/sys/netinet/sctp_indata.c
@@ -809,6 +809,8 @@ restart:
 					tchk = TAILQ_FIRST(&control->reasm);
 					if (tchk->rec.data.rcv_flags & SCTP_DATA_FIRST_FRAG) {
 						TAILQ_REMOVE(&control->reasm, tchk, sctp_next);
+						asoc->size_on_reasm_queue -= tchk->send_size;
+						sctp_ucount_decr(asoc->cnt_on_reasm_queue);
 						nc->first_frag_seen = 1;
 						nc->fsn_included = tchk->rec.data.fsn_num;
 						nc->data = tchk->data;
@@ -5322,6 +5324,9 @@ sctp_flush_reassm_for_str_seq(struct sctp_tcb *stcb,
 		/* Not found */
 		return;
 	}
+	if (old && !ordered && SCTP_TSN_GT(control->fsn_included, cumtsn)) {
+		return;
+	}
 	TAILQ_FOREACH_SAFE(chk, &control->reasm, sctp_next, nchk) {
 		/* Purge hanging chunks */
 		if (old && (ordered == 0)) {
diff --git a/sys/netinet/sctp_syscalls.c b/sys/netinet/sctp_syscalls.c
index 5c16e8d3555e..eea70e23d208 100644
--- a/sys/netinet/sctp_syscalls.c
+++ b/sys/netinet/sctp_syscalls.c
@@ -248,7 +248,7 @@ sys_sctp_generic_sendmsg (td, uap)
 	}
 
 	AUDIT_ARG_FD(uap->sd);
-	error = getsock_cap(td, uap->sd, &rights, &fp, NULL);
+	error = getsock_cap(td, uap->sd, &rights, &fp, NULL, NULL);
 	if (error != 0)
 		goto sctp_bad;
 #ifdef KTRACE
@@ -361,7 +361,7 @@ sys_sctp_generic_sendmsg_iov(td, uap)
 	}
 
 	AUDIT_ARG_FD(uap->sd);
-	error = getsock_cap(td, uap->sd, &rights, &fp, NULL);
+	error = getsock_cap(td, uap->sd, &rights, &fp, NULL, NULL);
 	if (error != 0)
 		goto sctp_bad1;
 
@@ -477,7 +477,7 @@ sys_sctp_generic_recvmsg(td, uap)
 
 	AUDIT_ARG_FD(uap->sd);
 	error = getsock_cap(td, uap->sd, cap_rights_init(&rights, CAP_RECV),
-	    &fp, NULL);
+	    &fp, NULL, NULL);
 	if (error != 0)
 		return (error);
 #ifdef COMPAT_FREEBSD32
diff --git a/sys/netinet6/icmp6.c b/sys/netinet6/icmp6.c
index 0d040e4b0f7c..54f0e9205b4c 100644
--- a/sys/netinet6/icmp6.c
+++ b/sys/netinet6/icmp6.c
@@ -734,36 +734,19 @@ icmp6_input(struct mbuf **mp, int *offp, int proto)
 			goto badcode;
 		if (icmp6len < sizeof(struct nd_router_solicit))
 			goto badlen;
-		if ((n = m_copym(m, 0, M_COPYALL, M_NOWAIT)) == NULL) {
-			/* give up local */
-
-			/* Send incoming SeND packet to user space. */
-			if (send_sendso_input_hook != NULL) {
-				IP6_EXTHDR_CHECK(m, off,
-				    icmp6len, IPPROTO_DONE);
-				error = send_sendso_input_hook(m, ifp,
-				    SND_IN, ip6len);
-				/* -1 == no app on SEND socket */
-				if (error == 0)
-					return (IPPROTO_DONE);
-				nd6_rs_input(m, off, icmp6len);
-			} else
-				nd6_rs_input(m, off, icmp6len);
-			m = NULL;
-			goto freeit;
-		}
 		if (send_sendso_input_hook != NULL) {
-			IP6_EXTHDR_CHECK(n, off,
-			    icmp6len, IPPROTO_DONE);
-                        error = send_sendso_input_hook(n, ifp,
-			    SND_IN, ip6len);
-			if (error == 0)
+			IP6_EXTHDR_CHECK(m, off, icmp6len, IPPROTO_DONE);
+			error = send_sendso_input_hook(m, ifp, SND_IN, ip6len);
+			if (error == 0) {
+				m = NULL;
 				goto freeit;
-			/* -1 == no app on SEND socket */
-			nd6_rs_input(n, off, icmp6len);
-		} else
-			nd6_rs_input(n, off, icmp6len);
-		/* m stays. */
+			}
+		}
+		n = m_copym(m, 0, M_COPYALL, M_NOWAIT);
+		nd6_rs_input(m, off, icmp6len);
+		m = n;
+		if (m == NULL)
+			goto freeit;
 		break;
 
 	case ND_ROUTER_ADVERT:
@@ -772,29 +755,18 @@ icmp6_input(struct mbuf **mp, int *offp, int proto)
 			goto badcode;
 		if (icmp6len < sizeof(struct nd_router_advert))
 			goto badlen;
-		if ((n = m_copym(m, 0, M_COPYALL, M_NOWAIT)) == NULL) {
-
-			/* Send incoming SeND-protected/ND packet to user space. */
-			if (send_sendso_input_hook != NULL) {
-				error = send_sendso_input_hook(m, ifp,
-				    SND_IN, ip6len);
-				if (error == 0)
-					return (IPPROTO_DONE);
-				nd6_ra_input(m, off, icmp6len);
-			} else
-				nd6_ra_input(m, off, icmp6len);
-			m = NULL;
-			goto freeit;
-		}
 		if (send_sendso_input_hook != NULL) {
-			error = send_sendso_input_hook(n, ifp,
-			    SND_IN, ip6len);
-			if (error == 0)
+			error = send_sendso_input_hook(m, ifp, SND_IN, ip6len);
+			if (error == 0) {
+				m = NULL;
 				goto freeit;
-			nd6_ra_input(n, off, icmp6len);
-		} else
-			nd6_ra_input(n, off, icmp6len);
-		/* m stays. */
+			}
+		}
+		n = m_copym(m, 0, M_COPYALL, M_NOWAIT);
+		nd6_ra_input(m, off, icmp6len);
+		m = n;
+		if (m == NULL)
+			goto freeit;
 		break;
 
 	case ND_NEIGHBOR_SOLICIT:
@@ -803,27 +775,18 @@ icmp6_input(struct mbuf **mp, int *offp, int proto)
 			goto badcode;
 		if (icmp6len < sizeof(struct nd_neighbor_solicit))
 			goto badlen;
-		if ((n = m_copym(m, 0, M_COPYALL, M_NOWAIT)) == NULL) {
-			if (send_sendso_input_hook != NULL) {
-				error = send_sendso_input_hook(m, ifp,
-				    SND_IN, ip6len);
-				if (error == 0)
-					return (IPPROTO_DONE);
-				nd6_ns_input(m, off, icmp6len);
-			} else
-				nd6_ns_input(m, off, icmp6len);
-			m = NULL;
-			goto freeit;
-		}
 		if (send_sendso_input_hook != NULL) {
-			error = send_sendso_input_hook(n, ifp,
-			    SND_IN, ip6len);
-			if (error == 0)
+			error = send_sendso_input_hook(m, ifp, SND_IN, ip6len);
+			if (error == 0) {
+				m = NULL;
 				goto freeit;
-			nd6_ns_input(n, off, icmp6len);
-		} else
-			nd6_ns_input(n, off, icmp6len);
-		/* m stays. */
+			}
+		}
+		n = m_copym(m, 0, M_COPYALL, M_NOWAIT);
+		nd6_ns_input(m, off, icmp6len);
+		m = n;
+		if (m == NULL)
+			goto freeit;
 		break;
 
 	case ND_NEIGHBOR_ADVERT:
@@ -832,29 +795,18 @@ icmp6_input(struct mbuf **mp, int *offp, int proto)
 			goto badcode;
 		if (icmp6len < sizeof(struct nd_neighbor_advert))
 			goto badlen;
-		if ((n = m_copym(m, 0, M_COPYALL, M_NOWAIT)) == NULL) {
-
-			/* Send incoming SeND-protected/ND packet to user space. */
-			if (send_sendso_input_hook != NULL) {
-				error = send_sendso_input_hook(m, ifp,
-				    SND_IN, ip6len);
-				if (error == 0)
-					return (IPPROTO_DONE);
-				nd6_na_input(m, off, icmp6len);
-			} else
-				nd6_na_input(m, off, icmp6len);
-			m = NULL;
-			goto freeit;
-		}
 		if (send_sendso_input_hook != NULL) {
-			error = send_sendso_input_hook(n, ifp,
-			    SND_IN, ip6len);
-			if (error == 0)
+			error = send_sendso_input_hook(m, ifp, SND_IN, ip6len);
+			if (error == 0) {
+				m = NULL;
 				goto freeit;
-			nd6_na_input(n, off, icmp6len);
-		} else
-			nd6_na_input(n, off, icmp6len);
-		/* m stays. */
+			}
+		}
+		n = m_copym(m, 0, M_COPYALL, M_NOWAIT);
+		nd6_na_input(m, off, icmp6len);
+		m = n;
+		if (m == NULL)
+			goto freeit;
 		break;
 
 	case ND_REDIRECT:
@@ -863,27 +815,18 @@ icmp6_input(struct mbuf **mp, int *offp, int proto)
 			goto badcode;
 		if (icmp6len < sizeof(struct nd_redirect))
 			goto badlen;
-		if ((n = m_copym(m, 0, M_COPYALL, M_NOWAIT)) == NULL) {
-			if (send_sendso_input_hook != NULL) {
-				error = send_sendso_input_hook(m, ifp,
-				    SND_IN, ip6len);
-		 		if (error == 0)
-					return (IPPROTO_DONE);
-			    icmp6_redirect_input(m, off);
-			} else
-				icmp6_redirect_input(m, off);
-			m = NULL;
-			goto freeit;
-		}
 		if (send_sendso_input_hook != NULL) {
-			error = send_sendso_input_hook(n, ifp,
-			    SND_IN, ip6len);
-			if (error == 0)
+			error = send_sendso_input_hook(m, ifp, SND_IN, ip6len);
+			if (error == 0) {
+				m = NULL;
 				goto freeit;
-			icmp6_redirect_input(n, off);
-		} else
-			icmp6_redirect_input(n, off);
-		/* m stays. */
+			}
+		}
+		n = m_copym(m, 0, M_COPYALL, M_NOWAIT);
+		icmp6_redirect_input(m, off);
+		m = n;
+		if (m == NULL)
+			goto freeit;
 		break;
 
 	case ICMP6_ROUTER_RENUMBERING:
diff --git a/sys/netinet6/in6.c b/sys/netinet6/in6.c
index 419178243e38..2075db696ff0 100644
--- a/sys/netinet6/in6.c
+++ b/sys/netinet6/in6.c
@@ -630,7 +630,7 @@ in6_control(struct socket *so, u_long cmd, caddr_t data,
 		/* relate the address to the prefix */
 		if (ia->ia6_ndpr == NULL) {
 			ia->ia6_ndpr = pr;
-			pr->ndpr_refcnt++;
+			pr->ndpr_addrcnt++;
 
 			/*
 			 * If this is the first autoconf address from the
@@ -638,7 +638,7 @@ in6_control(struct socket *so, u_long cmd, caddr_t data,
 			 * (when required).
 			 */
 			if ((ia->ia6_flags & IN6_IFF_AUTOCONF) &&
-			    V_ip6_use_tempaddr && pr->ndpr_refcnt == 1) {
+			    V_ip6_use_tempaddr && pr->ndpr_addrcnt == 1) {
 				int e;
 				if ((e = in6_tmpifadd(ia, 1, 0)) != 0) {
 					log(LOG_NOTICE, "in6_control: failed "
@@ -690,11 +690,11 @@ aifaddr_out:
 		 * and the prefix management.  We do this, however, to provide
 		 * as much backward compatibility as possible in terms of
 		 * the ioctl operation.
-		 * Note that in6_purgeaddr() will decrement ndpr_refcnt.
+		 * Note that in6_purgeaddr() will decrement ndpr_addrcnt.
 		 */
 		pr = ia->ia6_ndpr;
 		in6_purgeaddr(&ia->ia_ifa);
-		if (pr && pr->ndpr_refcnt == 0)
+		if (pr && pr->ndpr_addrcnt == 0)
 			prelist_remove(pr);
 		EVENTHANDLER_INVOKE(ifaddr_event, ifp);
 		break;
@@ -1305,9 +1305,9 @@ in6_unlink_ifa(struct in6_ifaddr *ia, struct ifnet *ifp)
 		    "in6_unlink_ifa: autoconf'ed address "
 		    "%s has no prefix\n", ip6_sprintf(ip6buf, IA6_IN6(ia))));
 	} else {
-		ia->ia6_ndpr->ndpr_refcnt--;
+		ia->ia6_ndpr->ndpr_addrcnt--;
 		/* Do not delete lles within prefix if refcont != 0 */
-		if (ia->ia6_ndpr->ndpr_refcnt == 0)
+		if (ia->ia6_ndpr->ndpr_addrcnt == 0)
 			remove_lle = 1;
 		ia->ia6_ndpr = NULL;
 	}
diff --git a/sys/netinet6/nd6.c b/sys/netinet6/nd6.c
index 3decb70a1788..ef9e37480c98 100644
--- a/sys/netinet6/nd6.c
+++ b/sys/netinet6/nd6.c
@@ -1159,7 +1159,7 @@ nd6_purge(struct ifnet *ifp)
 			 * still be above zero. We therefore reset it to
 			 * make sure that the prefix really gets purged.
 			 */
-			pr->ndpr_refcnt = 0;
+			pr->ndpr_addrcnt = 0;
 
 			prelist_remove(pr);
 		}
@@ -2674,7 +2674,7 @@ nd6_sysctl_prlist(SYSCTL_HANDLER_ARGS)
 			else
 				p.expire = maxexpire;
 		}
-		p.refcnt = pr->ndpr_refcnt;
+		p.refcnt = pr->ndpr_addrcnt;
 		p.flags = pr->ndpr_stateflags;
 		p.advrtrs = 0;
 		LIST_FOREACH(pfr, &pr->ndpr_advrtrs, pfr_entry)
diff --git a/sys/netinet6/nd6.h b/sys/netinet6/nd6.h
index 33ac4386b419..24dbef5c6fbb 100644
--- a/sys/netinet6/nd6.h
+++ b/sys/netinet6/nd6.h
@@ -275,7 +275,7 @@ struct nd_prefix {
 	/* list of routers that advertise the prefix: */
 	LIST_HEAD(pr_rtrhead, nd_pfxrouter) ndpr_advrtrs;
 	u_char	ndpr_plen;
-	int	ndpr_refcnt;	/* reference couter from addresses */
+	int	ndpr_addrcnt;	/* count of derived addresses */
 };
 
 #define ndpr_raf		ndpr_flags
diff --git a/sys/netinet6/nd6_rtr.c b/sys/netinet6/nd6_rtr.c
index 8f194061e4be..c9c7056aa77c 100644
--- a/sys/netinet6/nd6_rtr.c
+++ b/sys/netinet6/nd6_rtr.c
@@ -1053,7 +1053,7 @@ prelist_remove(struct nd_prefix *pr)
 		/* what should we do? */
 	}
 
-	if (pr->ndpr_refcnt > 0)
+	if (pr->ndpr_addrcnt > 0)
 		return;		/* notice here? */
 
 	/* unlink ndpr_entry from nd_prefix list */
@@ -1356,7 +1356,7 @@ prelist_update(struct nd_prefixctl *new, struct nd_defrouter *dr,
 			/*
 			 * note that we should use pr (not new) for reference.
 			 */
-			pr->ndpr_refcnt++;
+			pr->ndpr_addrcnt++;
 			ia6->ia6_ndpr = pr;
 
 			/*
@@ -2114,7 +2114,7 @@ in6_tmpifadd(const struct in6_ifaddr *ia0, int forcegen, int delay)
 		return (EINVAL); /* XXX */
 	}
 	newia->ia6_ndpr = ia0->ia6_ndpr;
-	newia->ia6_ndpr->ndpr_refcnt++;
+	newia->ia6_ndpr->ndpr_addrcnt++;
 	ifa_free(&newia->ia_ifa);
 
 	/*
diff --git a/sys/netpfil/ipfw/ip_fw2.c b/sys/netpfil/ipfw/ip_fw2.c
index 5e5c46cf0504..ecdb2f896673 100644
--- a/sys/netpfil/ipfw/ip_fw2.c
+++ b/sys/netpfil/ipfw/ip_fw2.c
@@ -2710,6 +2710,7 @@ ipfw_init(void)
 	  default_fw_tables = IPFW_TABLES_MAX;
 
 	ipfw_init_sopt_handler();
+	ipfw_init_obj_rewriter();
 	ipfw_iface_init();
 	return (error);
 }
@@ -2723,6 +2724,7 @@ ipfw_destroy(void)
 
 	ipfw_iface_destroy();
 	ipfw_destroy_sopt_handler();
+	ipfw_destroy_obj_rewriter();
 	printf("IP firewall unloaded\n");
 }
 
@@ -2757,7 +2759,6 @@ vnet_ipfw_init(const void *unused)
 	/* Init shared services hash table */
 	ipfw_init_srv(chain);
 
-	ipfw_init_obj_rewriter();
 	ipfw_init_counters();
 	/* insert the default rule and create the initial map */
 	chain->n_rules = 1;
@@ -2862,7 +2863,6 @@ vnet_ipfw_uninit(const void *unused)
 	IPFW_LOCK_DESTROY(chain);
 	ipfw_dyn_uninit(1);	/* free the remaining parts */
 	ipfw_destroy_counters();
-	ipfw_destroy_obj_rewriter();
 	ipfw_bpf_uninit(last);
 	return (0);
 }
diff --git a/sys/powerpc/mpc85xx/qoriq_gpio.c b/sys/powerpc/mpc85xx/qoriq_gpio.c
index 2838548dd7ae..d09719cc3875 100644
--- a/sys/powerpc/mpc85xx/qoriq_gpio.c
+++ b/sys/powerpc/mpc85xx/qoriq_gpio.c
@@ -220,6 +220,7 @@ qoriq_gpio_probe(device_t dev)
 {
 
 	if (!ofw_bus_is_compatible(dev, "fsl,qoriq-gpio") &&
+	    !ofw_bus_is_compatible(dev, "fsl,pq3-gpio") &&
 	    !ofw_bus_is_compatible(dev, "fsl,mpc8572-gpio"))
 		return (ENXIO);
 
diff --git a/sys/powerpc/powerpc/machdep.c b/sys/powerpc/powerpc/machdep.c
index 24bc052a78f8..cec335d29eaf 100644
--- a/sys/powerpc/powerpc/machdep.c
+++ b/sys/powerpc/powerpc/machdep.c
@@ -128,6 +128,7 @@ __FBSDID("$FreeBSD$");
 #include <ddb/ddb.h>
 
 #include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_subr.h>
 
 int cold = 1;
 #ifdef __powerpc64__
@@ -140,6 +141,7 @@ int hw_direct_map = 1;
 extern void *ap_pcpu;
 
 struct pcpu __pcpu[MAXCPU];
+static char init_kenv[2048];
 
 static struct trapframe frame0;
 
@@ -292,7 +294,7 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
 		bzero(__sbss_start, __sbss_end - __sbss_start);
 		bzero(__bss_start, _end - __bss_start);
 #endif
-		init_static_kenv(NULL, 0);
+		init_static_kenv(init_kenv, sizeof(init_kenv));
 	}
 	/* Store boot environment state */
 	OF_initial_setup((void *)fdt, NULL, (int (*)(void *))ofentry);
@@ -335,6 +337,8 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
 
 	OF_bootstrap();
 
+	ofw_parse_bootargs();
+
 	/*
 	 * Initialize the console before printing anything.
 	 */
diff --git a/sys/sys/bio.h b/sys/sys/bio.h
index 01149dd64df9..8821fef59bb3 100644
--- a/sys/sys/bio.h
+++ b/sys/sys/bio.h
@@ -151,8 +151,6 @@ void bioq_insert_head(struct bio_queue_head *head, struct bio *bp);
 void bioq_insert_tail(struct bio_queue_head *head, struct bio *bp);
 void bioq_remove(struct bio_queue_head *head, struct bio *bp);
 
-void bio_taskqueue(struct bio *bp, bio_task_t *fund, void *arg);
-
 int	physio(struct cdev *dev, struct uio *uio, int ioflag);
 #define physread physio
 #define physwrite physio
diff --git a/sys/sys/capsicum.h b/sys/sys/capsicum.h
index 8720166ac836..0675100460f6 100644
--- a/sys/sys/capsicum.h
+++ b/sys/sys/capsicum.h
@@ -368,6 +368,8 @@ int	cap_ioctl_check(struct filedesc *fdp, int fd, u_long cmd);
 int	cap_fcntl_check_fde(struct filedescent *fde, int cmd);
 int	cap_fcntl_check(struct filedesc *fdp, int fd, int cmd);
 
+extern int trap_enotcap;
+
 #else /* !_KERNEL */
 
 __BEGIN_DECLS
diff --git a/sys/sys/clock.h b/sys/sys/clock.h
index b484bc8c2587..f1809dbb9527 100644
--- a/sys/sys/clock.h
+++ b/sys/sys/clock.h
@@ -54,6 +54,7 @@
  */
 extern int tz_minuteswest;
 extern int tz_dsttime;
+extern struct mtx resettodr_lock;
 
 int utc_offset(void);
 
diff --git a/sys/sys/efi.h b/sys/sys/efi.h
index 3bdcdc384dbe..68fc2816e494 100644
--- a/sys/sys/efi.h
+++ b/sys/sys/efi.h
@@ -30,6 +30,7 @@
 #define _SYS_EFI_H_
 
 #include <sys/uuid.h>
+#include <machine/efi.h>
 
 #define	EFI_PAGE_SHIFT		12
 #define	EFI_PAGE_SIZE		(1 << EFI_PAGE_SHIFT)
@@ -90,6 +91,9 @@ struct efi_md {
 #define	EFI_MD_ATTR_RT		0x8000000000000000UL
 };
 
+#define efi_next_descriptor(ptr, size) \
+    ((struct efi_md *)(((uint8_t *)(ptr)) + (size)))
+
 struct efi_tm {
 	uint16_t	tm_year;		/* 1998 - 20XX */
 	uint8_t		tm_mon;			/* 1 - 12 */
@@ -120,22 +124,25 @@ struct efi_tblhdr {
 
 struct efi_rt {
 	struct efi_tblhdr rt_hdr;
-	efi_status	(*rt_gettime)(struct efi_tm *, struct efi_tmcap *);
-	efi_status	(*rt_settime)(struct efi_tm *);
+	efi_status	(*rt_gettime)(struct efi_tm *, struct efi_tmcap *)
+	    EFIABI_ATTR;
+	efi_status	(*rt_settime)(struct efi_tm *) EFIABI_ATTR;
 	efi_status	(*rt_getwaketime)(uint8_t *, uint8_t *,
-	    struct efi_tm *);
-	efi_status	(*rt_setwaketime)(uint8_t, struct efi_tm *);
+	    struct efi_tm *) EFIABI_ATTR;
+	efi_status	(*rt_setwaketime)(uint8_t, struct efi_tm *)
+	    EFIABI_ATTR;
 	efi_status	(*rt_setvirtual)(u_long, u_long, uint32_t,
-	    struct efi_md *);
-	efi_status	(*rt_cvtptr)(u_long, void **);
+	    struct efi_md *) EFIABI_ATTR;
+	efi_status	(*rt_cvtptr)(u_long, void **) EFIABI_ATTR;
 	efi_status	(*rt_getvar)(efi_char *, struct uuid *, uint32_t *,
-	    u_long *, void *);
-	efi_status	(*rt_scanvar)(u_long *, efi_char *, struct uuid *);
+	    u_long *, void *) EFIABI_ATTR;
+	efi_status	(*rt_scanvar)(u_long *, efi_char *, struct uuid *)
+	    EFIABI_ATTR;
 	efi_status	(*rt_setvar)(efi_char *, struct uuid *, uint32_t,
-	    u_long, void *);
-	efi_status	(*rt_gethicnt)(uint32_t *);
+	    u_long, void *) EFIABI_ATTR;
+	efi_status	(*rt_gethicnt)(uint32_t *) EFIABI_ATTR;
 	efi_status	(*rt_reset)(enum efi_reset, efi_status, u_long,
-	    efi_char *);
+	    efi_char *) EFIABI_ATTR;
 };
 
 struct efi_systbl {
@@ -156,5 +163,8 @@ struct efi_systbl {
 	uint64_t	st_cfgtbl;
 };
 
-extern vm_paddr_t efi_systbl;
+#ifdef _KERNEL
+extern vm_paddr_t efi_systbl_phys;
+#endif	/* _KERNEL */
+
 #endif /* _SYS_EFI_H_ */
diff --git a/sys/sys/filedesc.h b/sys/sys/filedesc.h
index d6ed2edb051f..eb0ad4b254db 100644
--- a/sys/sys/filedesc.h
+++ b/sys/sys/filedesc.h
@@ -229,12 +229,14 @@ fdeget_locked(struct filedesc *fdp, int fd)
 	return (fde);
 }
 
+#ifdef CAPABILITIES
 static __inline bool
 fd_modified(struct filedesc *fdp, int fd, seq_t seq)
 {
 
 	return (!seq_consistent(fd_seq(fdp->fd_files, fd), seq));
 }
+#endif
 
 /* cdir/rdir/jdir manipulation functions. */
 void	pwd_chdir(struct thread *td, struct vnode *vp);
diff --git a/sys/sys/param.h b/sys/sys/param.h
index 467dc5275a4e..bafa596ea719 100644
--- a/sys/sys/param.h
+++ b/sys/sys/param.h
@@ -58,7 +58,7 @@
  *		in the range 5 to 9.
  */
 #undef __FreeBSD_version
-#define __FreeBSD_version 1200008	/* Master, propagated to newvers */
+#define __FreeBSD_version 1200010	/* Master, propagated to newvers */
 
 /*
  * __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD,
diff --git a/sys/sys/proc.h b/sys/sys/proc.h
index d20657dab4ea..e7f3f2f49738 100644
--- a/sys/sys/proc.h
+++ b/sys/sys/proc.h
@@ -716,6 +716,7 @@ struct proc {
 #define	P2_NOTRACE_EXEC 0x00000004	/* Keep P2_NOPTRACE on exec(2). */
 #define	P2_AST_SU	0x00000008	/* Handles SU ast for kthreads. */
 #define	P2_PTRACE_FSTP	0x00000010 /* SIGSTOP from PT_ATTACH not yet handled. */
+#define	P2_TRAPCAP	0x00000020	/* SIGTRAP on ENOTCAPABLE */
 
 /* Flags protected by proctree_lock, kept in p_treeflags. */
 #define	P_TREE_ORPHANED		0x00000001	/* Reparented, on orphan list */
diff --git a/sys/sys/procctl.h b/sys/sys/procctl.h
index c6f1e94eb5b7..53bb6caa66f2 100644
--- a/sys/sys/procctl.h
+++ b/sys/sys/procctl.h
@@ -1,8 +1,12 @@
 /*-
  * Copyright (c) 2013 Hudson River Trading LLC
+ * Copyright (c) 2014, 2016 The FreeBSD Foundation
  * Written by: John H. Baldwin <jhb@FreeBSD.org>
  * All rights reserved.
  *
+ * Portions of this software were developed by Konstantin Belousov
+ * under sponsorship from the FreeBSD Foundation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -43,6 +47,8 @@
 #define	PROC_REAP_KILL		6	/* kill descendants */
 #define	PROC_TRACE_CTL		7	/* en/dis ptrace and coredumps */
 #define	PROC_TRACE_STATUS	8	/* query tracing status */
+#define	PROC_TRAPCAP_CTL	9	/* trap capability errors */
+#define	PROC_TRAPCAP_STATUS	10	/* query trap capability status */
 
 /* Operations for PROC_SPROTECT (passed in integer arg). */
 #define	PPROT_OP(x)	((x) & 0xf)
@@ -102,6 +108,9 @@ struct procctl_reaper_kill {
 #define	PROC_TRACE_CTL_DISABLE		2
 #define	PROC_TRACE_CTL_DISABLE_EXEC	3
 
+#define	PROC_TRAPCAP_CTL_ENABLE		1
+#define	PROC_TRAPCAP_CTL_DISABLE	2
+
 #ifndef _KERNEL
 __BEGIN_DECLS
 int	procctl(idtype_t, id_t, int, void *);
diff --git a/sys/sys/signal.h b/sys/sys/signal.h
index 86a07e167c86..a8444658971f 100644
--- a/sys/sys/signal.h
+++ b/sys/sys/signal.h
@@ -291,6 +291,7 @@ typedef	struct __siginfo {
 #define TRAP_BRKPT	1	/* Process breakpoint.			*/
 #define TRAP_TRACE	2	/* Process trace trap.			*/
 #define	TRAP_DTRACE	3	/* DTrace induced trap.			*/
+#define	TRAP_CAP	4	/* Capabilities protective trap.	*/
 
 /* codes for SIGCHLD */
 #define CLD_EXITED	1	/* Child has exited			*/
diff --git a/sys/sys/socketvar.h b/sys/sys/socketvar.h
index 3bc2bae2be69..7decd6318b00 100644
--- a/sys/sys/socketvar.h
+++ b/sys/sys/socketvar.h
@@ -321,6 +321,7 @@ extern u_long	sb_max;
 extern so_gen_t so_gencnt;
 
 struct file;
+struct filecaps;
 struct filedesc;
 struct mbuf;
 struct sockaddr;
@@ -340,7 +341,7 @@ struct uio;
  */
 int	getsockaddr(struct sockaddr **namp, caddr_t uaddr, size_t len);
 int	getsock_cap(struct thread *td, int fd, cap_rights_t *rightsp,
-	    struct file **fpp, u_int *fflagp);
+	    struct file **fpp, u_int *fflagp, struct filecaps *havecaps);
 void	soabort(struct socket *so);
 int	soaccept(struct socket *so, struct sockaddr **nam);
 void	soaio_enqueue(struct task *task);
diff --git a/sys/ufs/ffs/ffs_alloc.c b/sys/ufs/ffs/ffs_alloc.c
index 0e4dc0316064..fb719cfb20ac 100644
--- a/sys/ufs/ffs/ffs_alloc.c
+++ b/sys/ufs/ffs/ffs_alloc.c
@@ -163,13 +163,13 @@ ffs_alloc(ip, lbn, bpref, size, flags, cred, bnp)
 #endif
 
 	*bnp = 0;
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	mtx_assert(UFS_MTX(ump), MA_OWNED);
 #ifdef INVARIANTS
 	if ((u_int)size > fs->fs_bsize || fragoff(fs, size) != 0) {
 		printf("dev = %s, bsize = %ld, size = %d, fs = %s\n",
-		    devtoname(ip->i_dev), (long)fs->fs_bsize, size,
+		    devtoname(ump->um_dev), (long)fs->fs_bsize, size,
 		    fs->fs_fsmnt);
 		panic("ffs_alloc: bad size");
 	}
@@ -260,9 +260,9 @@ ffs_realloccg(ip, lbprev, bprev, bpref, osize, nsize, flags, cred, bpp)
 	int64_t delta;
 
 	vp = ITOV(ip);
-	fs = ip->i_fs;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	bp = NULL;
-	ump = ip->i_ump;
 	gbflags = (flags & BA_UNMAPPED) != 0 ? GB_UNMAPPED : 0;
 
 	mtx_assert(UFS_MTX(ump), MA_OWNED);
@@ -273,7 +273,7 @@ ffs_realloccg(ip, lbprev, bprev, bpref, osize, nsize, flags, cred, bpp)
 	    (u_int)nsize > fs->fs_bsize || fragoff(fs, nsize) != 0) {
 		printf(
 		"dev = %s, bsize = %ld, osize = %d, nsize = %d, fs = %s\n",
-		    devtoname(ip->i_dev), (long)fs->fs_bsize, osize,
+		    devtoname(ump->um_dev), (long)fs->fs_bsize, osize,
 		    nsize, fs->fs_fsmnt);
 		panic("ffs_realloccg: bad size");
 	}
@@ -288,7 +288,7 @@ retry:
 	}
 	if (bprev == 0) {
 		printf("dev = %s, bsize = %ld, bprev = %jd, fs = %s\n",
-		    devtoname(ip->i_dev), (long)fs->fs_bsize, (intmax_t)bprev,
+		    devtoname(ump->um_dev), (long)fs->fs_bsize, (intmax_t)bprev,
 		    fs->fs_fsmnt);
 		panic("ffs_realloccg: bad bprev");
 	}
@@ -383,7 +383,7 @@ retry:
 		break;
 	default:
 		printf("dev = %s, optim = %ld, fs = %s\n",
-		    devtoname(ip->i_dev), (long)fs->fs_optim, fs->fs_fsmnt);
+		    devtoname(ump->um_dev), (long)fs->fs_optim, fs->fs_fsmnt);
 		panic("ffs_realloccg: bad optim");
 		/* NOTREACHED */
 	}
@@ -391,7 +391,7 @@ retry:
 	if (bno > 0) {
 		bp->b_blkno = fsbtodb(fs, bno);
 		if (!DOINGSOFTDEP(vp))
-			ffs_blkfree(ump, fs, ip->i_devvp, bprev, (long)osize,
+			ffs_blkfree(ump, fs, ump->um_devvp, bprev, (long)osize,
 			    ip->i_number, vp->v_type, NULL);
 		delta = btodb(nsize - osize);
 		DIP_SET(ip, i_blocks, DIP(ip, i_blocks) + delta);
@@ -490,7 +490,7 @@ ffs_reallocblks(ap)
 	 * These devices are flash and therefore work less well with this
 	 * optimization. Also skip if reallocblks has been disabled globally.
 	 */
-	ump = VTOI(ap->a_vp)->i_ump;
+	ump = ap->a_vp->v_mount->mnt_data;
 	if (ump->um_candelete || doreallocblks == 0)
 		return (ENOSPC);
 
@@ -529,8 +529,8 @@ ffs_reallocblks_ufs1(ap)
 
 	vp = ap->a_vp;
 	ip = VTOI(vp);
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	/*
 	 * If we are not tracking block clusters or if we have less than 4%
 	 * free blocks left, then do not attempt to cluster. Running with
@@ -727,7 +727,7 @@ ffs_reallocblks_ufs1(ap)
 #endif
 	for (blkno = newblk, i = 0; i < len; i++, blkno += fs->fs_frag) {
 		if (!DOINGSOFTDEP(vp))
-			ffs_blkfree(ump, fs, ip->i_devvp,
+			ffs_blkfree(ump, fs, ump->um_devvp,
 			    dbtofsb(fs, buflist->bs_children[i]->b_blkno),
 			    fs->fs_bsize, ip->i_number, vp->v_type, NULL);
 		buflist->bs_children[i]->b_blkno = fsbtodb(fs, blkno);
@@ -778,8 +778,8 @@ ffs_reallocblks_ufs2(ap)
 
 	vp = ap->a_vp;
 	ip = VTOI(vp);
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	/*
 	 * If we are not tracking block clusters or if we have less than 4%
 	 * free blocks left, then do not attempt to cluster. Running with
@@ -975,7 +975,7 @@ ffs_reallocblks_ufs2(ap)
 #endif
 	for (blkno = newblk, i = 0; i < len; i++, blkno += fs->fs_frag) {
 		if (!DOINGSOFTDEP(vp))
-			ffs_blkfree(ump, fs, ip->i_devvp,
+			ffs_blkfree(ump, fs, ump->um_devvp,
 			    dbtofsb(fs, buflist->bs_children[i]->b_blkno),
 			    fs->fs_bsize, ip->i_number, vp->v_type, NULL);
 		buflist->bs_children[i]->b_blkno = fsbtodb(fs, blkno);
@@ -1040,8 +1040,8 @@ ffs_valloc(pvp, mode, cred, vpp)
 
 	*vpp = NULL;
 	pip = VTOI(pvp);
-	fs = pip->i_fs;
-	ump = pip->i_ump;
+	ump = ITOUMP(pip);
+	fs = ump->um_fs;
 
 	UFS_LOCK(ump);
 	reclaimed = 0;
@@ -1114,10 +1114,12 @@ dup_alloc:
 	ip->i_flag = 0;
 	(*vpp)->v_vflag = 0;
 	(*vpp)->v_type = VNON;
-	if (fs->fs_magic == FS_UFS2_MAGIC)
+	if (fs->fs_magic == FS_UFS2_MAGIC) {
 		(*vpp)->v_op = &ffs_vnodeops2;
-	else
+		ip->i_flag |= IN_UFS2;
+	} else {
 		(*vpp)->v_op = &ffs_vnodeops1;
+	}
 	return (0);
 noinodes:
 	if (reclaimed == 0) {
@@ -1158,8 +1160,8 @@ ffs_dirpref(pip)
 	u_int mincg, minndir;
 	u_int maxcontigdirs;
 
-	mtx_assert(UFS_MTX(pip->i_ump), MA_OWNED);
-	fs = pip->i_fs;
+	mtx_assert(UFS_MTX(ITOUMP(pip)), MA_OWNED);
+	fs = ITOFS(pip);
 
 	avgifree = fs->fs_cstotal.cs_nifree / fs->fs_ncg;
 	avgbfree = fs->fs_cstotal.cs_nbfree / fs->fs_ncg;
@@ -1307,8 +1309,8 @@ ffs_blkpref_ufs1(ip, lbn, indx, bap)
 	ufs2_daddr_t pref;
 
 	KASSERT(indx <= 0 || bap != NULL, ("need non-NULL bap"));
-	mtx_assert(UFS_MTX(ip->i_ump), MA_OWNED);
-	fs = ip->i_fs;
+	mtx_assert(UFS_MTX(ITOUMP(ip)), MA_OWNED);
+	fs = ITOFS(ip);
 	/*
 	 * Allocation of indirect blocks is indicated by passing negative
 	 * values in indx: -1 for single indirect, -2 for double indirect,
@@ -1412,8 +1414,8 @@ ffs_blkpref_ufs2(ip, lbn, indx, bap)
 	ufs2_daddr_t pref;
 
 	KASSERT(indx <= 0 || bap != NULL, ("need non-NULL bap"));
-	mtx_assert(UFS_MTX(ip->i_ump), MA_OWNED);
-	fs = ip->i_fs;
+	mtx_assert(UFS_MTX(ITOUMP(ip)), MA_OWNED);
+	fs = ITOFS(ip);
 	/*
 	 * Allocation of indirect blocks is indicated by passing negative
 	 * values in indx: -1 for single indirect, -2 for double indirect,
@@ -1526,12 +1528,12 @@ ffs_hashalloc(ip, cg, pref, size, rsize, allocator)
 	ufs2_daddr_t result;
 	u_int i, icg = cg;
 
-	mtx_assert(UFS_MTX(ip->i_ump), MA_OWNED);
+	mtx_assert(UFS_MTX(ITOUMP(ip)), MA_OWNED);
 #ifdef INVARIANTS
 	if (ITOV(ip)->v_mount->mnt_kern_flag & MNTK_SUSPENDED)
 		panic("ffs_hashalloc: allocation on suspended filesystem");
 #endif
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	/*
 	 * 1: preferred cylinder group
 	 */
@@ -1589,8 +1591,8 @@ ffs_fragextend(ip, cg, bprev, osize, nsize)
 	int i, error;
 	u_int8_t *blksfree;
 
-	ump = ip->i_ump;
-	fs = ip->i_fs;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	if (fs->fs_cs(fs, cg).cs_nffree < numfrags(fs, nsize - osize))
 		return (0);
 	frags = numfrags(fs, nsize);
@@ -1600,8 +1602,8 @@ ffs_fragextend(ip, cg, bprev, osize, nsize)
 		return (0);
 	}
 	UFS_UNLOCK(ump);
-	error = bread(ip->i_devvp, fsbtodb(fs, cgtod(fs, cg)),
-		(int)fs->fs_cgsize, NOCRED, &bp);
+	error = bread(ump->um_devvp, fsbtodb(fs, cgtod(fs, cg)),
+	    (int)fs->fs_cgsize, NOCRED, &bp);
 	if (error)
 		goto fail;
 	cgp = (struct cg *)bp->b_data;
@@ -1673,13 +1675,13 @@ ffs_alloccg(ip, cg, bpref, size, rsize)
 	int i, allocsiz, error, frags;
 	u_int8_t *blksfree;
 
-	ump = ip->i_ump;
-	fs = ip->i_fs;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	if (fs->fs_cs(fs, cg).cs_nbfree == 0 && size == fs->fs_bsize)
 		return (0);
 	UFS_UNLOCK(ump);
-	error = bread(ip->i_devvp, fsbtodb(fs, cgtod(fs, cg)),
-		(int)fs->fs_cgsize, NOCRED, &bp);
+	error = bread(ump->um_devvp, fsbtodb(fs, cgtod(fs, cg)),
+	    (int)fs->fs_cgsize, NOCRED, &bp);
 	if (error)
 		goto fail;
 	cgp = (struct cg *)bp->b_data;
@@ -1775,8 +1777,8 @@ ffs_alloccgblk(ip, bp, bpref, size)
 	u_int8_t *blksfree;
 	int i, cgbpref;
 
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	mtx_assert(UFS_MTX(ump), MA_OWNED);
 	cgp = (struct cg *)bp->b_data;
 	blksfree = cg_blksfree(cgp);
@@ -1861,12 +1863,12 @@ ffs_clusteralloc(ip, cg, bpref, len)
 	int32_t *lp;
 	u_int8_t *blksfree;
 
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	if (fs->fs_maxcluster[cg] < len)
 		return (0);
 	UFS_UNLOCK(ump);
-	if (bread(ip->i_devvp, fsbtodb(fs, cgtod(fs, cg)), (int)fs->fs_cgsize,
+	if (bread(ump->um_devvp, fsbtodb(fs, cgtod(fs, cg)), (int)fs->fs_cgsize,
 	    NOCRED, &bp))
 		goto fail_lock;
 	cgp = (struct cg *)bp->b_data;
@@ -1965,8 +1967,8 @@ getinobuf(struct inode *ip, u_int cg, u_int32_t cginoblk, int gbflags)
 {
 	struct fs *fs;
 
-	fs = ip->i_fs;
-	return (getblk(ip->i_devvp, fsbtodb(fs, ino_to_fsba(fs,
+	fs = ITOFS(ip);
+	return (getblk(ITODEVVP(ip), fsbtodb(fs, ino_to_fsba(fs,
 	    cg * fs->fs_ipg + cginoblk)), (int)fs->fs_bsize, 0, 0,
 	    gbflags));
 }
@@ -1997,13 +1999,13 @@ ffs_nodealloccg(ip, cg, ipref, mode, unused)
 	int error, start, len, i;
 	u_int32_t old_initediblk;
 
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 check_nifree:
 	if (fs->fs_cs(fs, cg).cs_nifree == 0)
 		return (0);
 	UFS_UNLOCK(ump);
-	error = bread(ip->i_devvp, fsbtodb(fs, cgtod(fs, cg)),
+	error = bread(ump->um_devvp, fsbtodb(fs, cgtod(fs, cg)),
 		(int)fs->fs_cgsize, NOCRED, &bp);
 	if (error) {
 		brelse(bp);
@@ -2101,7 +2103,7 @@ gotit:
 		 * to it, then leave it unchanged as the other thread
 		 * has already set it correctly.
 		 */
-		error = bread(ip->i_devvp, fsbtodb(fs, cgtod(fs, cg)),
+		error = bread(ump->um_devvp, fsbtodb(fs, cgtod(fs, cg)),
 		    (int)fs->fs_cgsize, NOCRED, &bp);
 		UFS_LOCK(ump);
 		ACTIVECLEAR(fs, cg);
@@ -2166,14 +2168,16 @@ ffs_blkfree_cg(ump, fs, devvp, bno, size, inum, dephd)
 	cg = dtog(fs, bno);
 	if (devvp->v_type == VREG) {
 		/* devvp is a snapshot */
-		dev = VTOI(devvp)->i_devvp->v_rdev;
+		MPASS(devvp->v_mount->mnt_data == ump);
+		dev = ump->um_devvp->v_rdev;
 		cgblkno = fragstoblks(fs, cgtod(fs, cg));
-	} else {
+	} else if (devvp->v_type == VCHR) {
 		/* devvp is a normal disk device */
 		dev = devvp->v_rdev;
 		cgblkno = fsbtodb(fs, cgtod(fs, cg));
 		ASSERT_VOP_LOCKED(devvp, "ffs_blkfree_cg");
-	}
+	} else
+		return;
 #ifdef INVARIANTS
 	if ((u_int)size > fs->fs_bsize || fragoff(fs, size) != 0 ||
 	    fragnum(fs, bno) + numfrags(fs, size) > fs->fs_frag) {
@@ -2267,7 +2271,7 @@ ffs_blkfree_cg(ump, fs, devvp, bno, size, inum, dephd)
 	ACTIVECLEAR(fs, cg);
 	UFS_UNLOCK(ump);
 	mp = UFSTOVFS(ump);
-	if (MOUNTEDSOFTDEP(mp) && devvp->v_type != VREG)
+	if (MOUNTEDSOFTDEP(mp) && devvp->v_type == VCHR)
 		softdep_setup_blkfree(UFSTOVFS(ump), bp, bno,
 		    numfrags(fs, size), dephd);
 	bdwrite(bp);
@@ -2332,7 +2336,7 @@ ffs_blkfree(ump, fs, devvp, bno, size, inum, vtype, dephd)
 	 * it has a snapshot(s) associated with it, and one of the
 	 * snapshots wants to claim the block.
 	 */
-	if (devvp->v_type != VREG &&
+	if (devvp->v_type == VCHR &&
 	    (devvp->v_vflag & VV_COPYONWRITE) &&
 	    ffs_snapblkfree(fs, devvp, bno, size, inum, vtype, dephd)) {
 		return;
@@ -2396,7 +2400,7 @@ ffs_checkblk(ip, bno, size)
 	int i, error, frags, free;
 	u_int8_t *blksfree;
 
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	if ((u_int)size > fs->fs_bsize || fragoff(fs, size) != 0) {
 		printf("bsize = %ld, size = %ld, fs = %s\n",
 		    (long)fs->fs_bsize, size, fs->fs_fsmnt);
@@ -2404,7 +2408,7 @@ ffs_checkblk(ip, bno, size)
 	}
 	if ((u_int)bno >= fs->fs_size)
 		panic("ffs_checkblk: bad block %jd", (intmax_t)bno);
-	error = bread(ip->i_devvp, fsbtodb(fs, cgtod(fs, dtog(fs, bno))),
+	error = bread(ITODEVVP(ip), fsbtodb(fs, cgtod(fs, dtog(fs, bno))),
 		(int)fs->fs_cgsize, NOCRED, &bp);
 	if (error)
 		panic("ffs_checkblk: cg bread failed");
@@ -2438,6 +2442,7 @@ ffs_vfree(pvp, ino, mode)
 	ino_t ino;
 	int mode;
 {
+	struct ufsmount *ump;
 	struct inode *ip;
 
 	if (DOINGSOFTDEP(pvp)) {
@@ -2445,8 +2450,8 @@ ffs_vfree(pvp, ino, mode)
 		return (0);
 	}
 	ip = VTOI(pvp);
-	return (ffs_freefile(ip->i_ump, ip->i_fs, ip->i_devvp, ino, mode,
-	    NULL));
+	ump = VFSTOUFS(pvp->v_mount);
+	return (ffs_freefile(ump, ump->um_fs, ump->um_devvp, ino, mode, NULL));
 }
 
 /*
@@ -2473,12 +2478,16 @@ ffs_freefile(ump, fs, devvp, ino, mode, wkhd)
 	cg = ino_to_cg(fs, ino);
 	if (devvp->v_type == VREG) {
 		/* devvp is a snapshot */
-		dev = VTOI(devvp)->i_devvp->v_rdev;
+		MPASS(devvp->v_mount->mnt_data == ump);
+		dev = ump->um_devvp->v_rdev;
 		cgbno = fragstoblks(fs, cgtod(fs, cg));
-	} else {
+	} else if (devvp->v_type == VCHR) {
 		/* devvp is a normal disk device */
 		dev = devvp->v_rdev;
 		cgbno = fsbtodb(fs, cgtod(fs, cg));
+	} else {
+		bp = NULL;
+		return (0);
 	}
 	if (ino >= fs->fs_ipg * fs->fs_ncg)
 		panic("ffs_freefile: range: dev = %s, ino = %ju, fs = %s",
@@ -2517,7 +2526,7 @@ ffs_freefile(ump, fs, devvp, ino, mode, wkhd)
 	fs->fs_fmod = 1;
 	ACTIVECLEAR(fs, cg);
 	UFS_UNLOCK(ump);
-	if (MOUNTEDSOFTDEP(UFSTOVFS(ump)) && devvp->v_type != VREG)
+	if (MOUNTEDSOFTDEP(UFSTOVFS(ump)) && devvp->v_type == VCHR)
 		softdep_setup_inofree(UFSTOVFS(ump), bp,
 		    ino + cg * fs->fs_ipg, wkhd);
 	bdwrite(bp);
@@ -2544,9 +2553,11 @@ ffs_checkfreefile(fs, devvp, ino)
 	if (devvp->v_type == VREG) {
 		/* devvp is a snapshot */
 		cgbno = fragstoblks(fs, cgtod(fs, cg));
-	} else {
+	} else if (devvp->v_type == VCHR) {
 		/* devvp is a normal disk device */
 		cgbno = fsbtodb(fs, cgtod(fs, cg));
+	} else {
+		return (1);
 	}
 	if (ino >= fs->fs_ipg * fs->fs_ncg)
 		return (1);
@@ -3056,7 +3067,7 @@ sysctl_ffs_fsck(SYSCTL_HANDLER_ARGS)
 			break;
 		AUDIT_ARG_VNODE1(vp);
 		ip = VTOI(vp);
-		if (ip->i_ump->um_fstype == UFS1)
+		if (I_IS_UFS1(ip))
 			error = copyin((void *)(intptr_t)cmd.size, ip->i_din1,
 			    sizeof(struct ufs1_dinode));
 		else
@@ -3076,7 +3087,7 @@ sysctl_ffs_fsck(SYSCTL_HANDLER_ARGS)
 			error = EPERM;
 			break;
 		}
-		if (VTOI(vp)->i_ump != ump) {
+		if (ITOUMP(VTOI(vp)) != ump) {
 			error = EINVAL;
 			break;
 		}
@@ -3173,11 +3184,11 @@ buffered_write(fp, uio, active_cred, flags, td)
 		return (EINVAL);
 	}
 	ip = VTOI(vp);
-	if (ip->i_devvp != devvp) {
+	if (ITODEVVP(ip) != devvp) {
 		vput(vp);
 		return (EINVAL);
 	}
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	vput(vp);
 	foffset_lock_uio(fp, uio, flags);
 	vn_lock(devvp, LK_EXCLUSIVE | LK_RETRY);
diff --git a/sys/ufs/ffs/ffs_balloc.c b/sys/ufs/ffs/ffs_balloc.c
index 676dcb4e4d4c..0471fd6938f6 100644
--- a/sys/ufs/ffs/ffs_balloc.c
+++ b/sys/ufs/ffs/ffs_balloc.c
@@ -111,8 +111,8 @@ ffs_balloc_ufs1(struct vnode *vp, off_t startoffset, int size,
 
 	ip = VTOI(vp);
 	dp = ip->i_din1;
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	fs = ITOFS(ip);
+	ump = ITOUMP(ip);
 	lbn = lblkno(fs, startoffset);
 	size = blkoff(fs, startoffset) + size;
 	reclaimed = 0;
@@ -548,7 +548,7 @@ fail:
 		}
 		lbns_remfree++;
 #endif
-		ffs_blkfree(ump, fs, ip->i_devvp, *blkp, fs->fs_bsize,
+		ffs_blkfree(ump, fs, ump->um_devvp, *blkp, fs->fs_bsize,
 		    ip->i_number, vp->v_type, NULL);
 	}
 	return (error);
@@ -584,8 +584,8 @@ ffs_balloc_ufs2(struct vnode *vp, off_t startoffset, int size,
 
 	ip = VTOI(vp);
 	dp = ip->i_din2;
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	fs = ITOFS(ip);
+	ump = ITOUMP(ip);
 	lbn = lblkno(fs, startoffset);
 	size = blkoff(fs, startoffset) + size;
 	reclaimed = 0;
@@ -1141,7 +1141,7 @@ fail:
 		}
 		lbns_remfree++;
 #endif
-		ffs_blkfree(ump, fs, ip->i_devvp, *blkp, fs->fs_bsize,
+		ffs_blkfree(ump, fs, ump->um_devvp, *blkp, fs->fs_bsize,
 		    ip->i_number, vp->v_type, NULL);
 	}
 	return (error);
diff --git a/sys/ufs/ffs/ffs_inode.c b/sys/ufs/ffs/ffs_inode.c
index 4bd38d58692f..0982ddab98ac 100644
--- a/sys/ufs/ffs/ffs_inode.c
+++ b/sys/ufs/ffs/ffs_inode.c
@@ -92,8 +92,8 @@ ffs_update(vp, waitfor)
 	if ((ip->i_flag & IN_MODIFIED) == 0 && waitfor == 0)
 		return (0);
 	ip->i_flag &= ~(IN_LAZYACCESS | IN_LAZYMOD | IN_MODIFIED);
-	fs = ip->i_fs;
-	if (fs->fs_ronly && ip->i_ump->um_fsckpid == 0)
+	fs = ITOFS(ip);
+	if (fs->fs_ronly && ITOUMP(ip)->um_fsckpid == 0)
 		return (0);
 	/*
 	 * If we are updating a snapshot and another process is currently
@@ -110,7 +110,7 @@ ffs_update(vp, waitfor)
 	if (IS_SNAPSHOT(ip))
 		flags = GB_LOCK_NOWAIT;
 loop:
-	error = breadn_flags(ip->i_devvp,
+	error = breadn_flags(ITODEVVP(ip),
 	     fsbtodb(fs, ino_to_fsba(fs, ip->i_number)),
 	     (int) fs->fs_bsize, 0, 0, 0, NOCRED, flags, &bp);
 	if (error != 0) {
@@ -143,7 +143,7 @@ loop:
 		softdep_update_inodeblock(ip, bp, waitfor);
 	else if (ip->i_effnlink != ip->i_nlink)
 		panic("ffs_update: bad link cnt");
-	if (ip->i_ump->um_fstype == UFS1) {
+	if (I_IS_UFS1(ip)) {
 		*((struct ufs1_dinode *)bp->b_data +
 		    ino_to_fsbo(fs, ip->i_number)) = *ip->i_din1;
 		/* XXX: FIX? The entropy here is desirable, but the harvesting may be expensive */
@@ -197,8 +197,8 @@ ffs_truncate(vp, length, flags, cred)
 	off_t osize;
 
 	ip = VTOI(vp);
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	ump = VFSTOUFS(vp->v_mount);
+	fs = ump->um_fs;
 	bo = &vp->v_bufobj;
 
 	ASSERT_VOP_LOCKED(vp, "ffs_truncate");
@@ -270,7 +270,7 @@ ffs_truncate(vp, length, flags, cred)
 			for (i = 0; i < NXADDR; i++) {
 				if (oldblks[i] == 0)
 					continue;
-				ffs_blkfree(ump, fs, ip->i_devvp, oldblks[i],
+				ffs_blkfree(ump, fs, ITODEVVP(ip), oldblks[i],
 				    sblksize(fs, osize, i), ip->i_number,
 				    vp->v_type, NULL);
 			}
@@ -346,7 +346,7 @@ ffs_truncate(vp, length, flags, cred)
 		if (error)
 			return (error);
 		indiroff = (lbn - NDADDR) % NINDIR(fs);
-		if (ip->i_ump->um_fstype == UFS1)
+		if (I_IS_UFS1(ip))
 			blkno = ((ufs1_daddr_t *)(bp->b_data))[indiroff];
 		else
 			blkno = ((ufs2_daddr_t *)(bp->b_data))[indiroff];
@@ -518,7 +518,7 @@ ffs_truncate(vp, length, flags, cred)
 			blocksreleased += count;
 			if (lastiblock[level] < 0) {
 				DIP_SET(ip, i_ib[level], 0);
-				ffs_blkfree(ump, fs, ip->i_devvp, bn,
+				ffs_blkfree(ump, fs, ump->um_devvp, bn,
 				    fs->fs_bsize, ip->i_number,
 				    vp->v_type, NULL);
 				blocksreleased += nblocks;
@@ -539,7 +539,7 @@ ffs_truncate(vp, length, flags, cred)
 			continue;
 		DIP_SET(ip, i_db[i], 0);
 		bsize = blksize(fs, ip, i);
-		ffs_blkfree(ump, fs, ip->i_devvp, bn, bsize, ip->i_number,
+		ffs_blkfree(ump, fs, ump->um_devvp, bn, bsize, ip->i_number,
 		    vp->v_type, NULL);
 		blocksreleased += btodb(bsize);
 	}
@@ -571,7 +571,7 @@ ffs_truncate(vp, length, flags, cred)
 			 * required for the storage we're keeping.
 			 */
 			bn += numfrags(fs, newspace);
-			ffs_blkfree(ump, fs, ip->i_devvp, bn,
+			ffs_blkfree(ump, fs, ump->um_devvp, bn,
 			   oldspace - newspace, ip->i_number, vp->v_type, NULL);
 			blocksreleased += btodb(oldspace - newspace);
 		}
@@ -630,7 +630,7 @@ ffs_indirtrunc(ip, lbn, dbn, lastbn, level, countp)
 	ufs2_daddr_t *countp;
 {
 	struct buf *bp;
-	struct fs *fs = ip->i_fs;
+	struct fs *fs;
 	struct vnode *vp;
 	caddr_t copy = NULL;
 	int i, nblocks, error = 0, allerror = 0;
@@ -638,7 +638,9 @@ ffs_indirtrunc(ip, lbn, dbn, lastbn, level, countp)
 	ufs2_daddr_t blkcount, factor, blocksreleased = 0;
 	ufs1_daddr_t *bap1 = NULL;
 	ufs2_daddr_t *bap2 = NULL;
-#	define BAP(ip, i) (((ip)->i_ump->um_fstype == UFS1) ? bap1[i] : bap2[i])
+#define BAP(ip, i) (I_IS_UFS1(ip) ? bap1[i] : bap2[i])
+
+	fs = ITOFS(ip);
 
 	/*
 	 * Calculate index in current block of last
@@ -686,7 +688,7 @@ ffs_indirtrunc(ip, lbn, dbn, lastbn, level, countp)
 		return (error);
 	}
 
-	if (ip->i_ump->um_fstype == UFS1)
+	if (I_IS_UFS1(ip))
 		bap1 = (ufs1_daddr_t *)bp->b_data;
 	else
 		bap2 = (ufs2_daddr_t *)bp->b_data;
@@ -694,7 +696,7 @@ ffs_indirtrunc(ip, lbn, dbn, lastbn, level, countp)
 		copy = malloc(fs->fs_bsize, M_TEMP, M_WAITOK);
 		bcopy((caddr_t)bp->b_data, copy, (u_int)fs->fs_bsize);
 		for (i = last + 1; i < NINDIR(fs); i++)
-			if (ip->i_ump->um_fstype == UFS1)
+			if (I_IS_UFS1(ip))
 				bap1[i] = 0;
 			else
 				bap2[i] = 0;
@@ -705,7 +707,7 @@ ffs_indirtrunc(ip, lbn, dbn, lastbn, level, countp)
 			if (error)
 				allerror = error;
 		}
-		if (ip->i_ump->um_fstype == UFS1)
+		if (I_IS_UFS1(ip))
 			bap1 = (ufs1_daddr_t *)copy;
 		else
 			bap2 = (ufs2_daddr_t *)copy;
@@ -725,7 +727,7 @@ ffs_indirtrunc(ip, lbn, dbn, lastbn, level, countp)
 				allerror = error;
 			blocksreleased += blkcount;
 		}
-		ffs_blkfree(ip->i_ump, fs, ip->i_devvp, nb, fs->fs_bsize,
+		ffs_blkfree(ITOUMP(ip), fs, ITODEVVP(ip), nb, fs->fs_bsize,
 		    ip->i_number, vp->v_type, NULL);
 		blocksreleased += nblocks;
 	}
@@ -759,6 +761,6 @@ int
 ffs_rdonly(struct inode *ip)
 {
 
-	return (ip->i_ump->um_fs->fs_ronly != 0);
+	return (ITOFS(ip)->fs_ronly != 0);
 }
 
diff --git a/sys/ufs/ffs/ffs_rawread.c b/sys/ufs/ffs/ffs_rawread.c
index 84fa0db9c6b0..e1fc3465525e 100644
--- a/sys/ufs/ffs/ffs_rawread.c
+++ b/sys/ufs/ffs/ffs_rawread.c
@@ -204,7 +204,7 @@ ffs_rawread_readahead(struct vnode *vp,
 	bsize = vp->v_mount->mnt_stat.f_iosize;
 	
 	ip = VTOI(vp);
-	dp = ip->i_devvp;
+	dp = ITODEVVP(ip);
 
 	iolen = ((vm_offset_t) udata) & PAGE_MASK;
 	bp->b_bcount = len;
@@ -440,7 +440,7 @@ ffs_rawread(struct vnode *vp,
 
 		/* Only handle sector aligned reads */
 		ip = VTOI(vp);
-		secsize = ip->i_devvp->v_bufobj.bo_bsize;
+		secsize = ITODEVVP(ip)->v_bufobj.bo_bsize;
 		if ((uio->uio_offset & (secsize - 1)) == 0 &&
 		    (uio->uio_resid & (secsize - 1)) == 0) {
 			
@@ -460,7 +460,7 @@ ffs_rawread(struct vnode *vp,
 				}
 				
 				partialbytes = ((unsigned int) ip->i_size) %
-					ip->i_fs->fs_bsize;
+				    ITOFS(ip)->fs_bsize;
 				blockbytes = (int) filebytes - partialbytes;
 				if (blockbytes > 0) {
 					skipbytes = uio->uio_resid -
diff --git a/sys/ufs/ffs/ffs_snapshot.c b/sys/ufs/ffs/ffs_snapshot.c
index 5ef439f6a1a8..a303c8d0f9fd 100644
--- a/sys/ufs/ffs/ffs_snapshot.c
+++ b/sys/ufs/ffs/ffs_snapshot.c
@@ -302,7 +302,7 @@ restart:
 	vp = nd.ni_vp;
 	vp->v_vflag |= VV_SYSTEM;
 	ip = VTOI(vp);
-	devvp = ip->i_devvp;
+	devvp = ITODEVVP(ip);
 	/*
 	 * Allocate and copy the last block contents so as to be able
 	 * to set size to that of the filesystem.
@@ -587,7 +587,7 @@ loop:
 			}
 		}
 		snaplistsize += 1;
-		if (xp->i_ump->um_fstype == UFS1)
+		if (I_IS_UFS1(xp))
 			error = expunge_ufs1(vp, xp, copy_fs, fullacct_ufs1,
 			    BLK_NOCOPY, 1);
 		else
@@ -620,7 +620,7 @@ loop:
 			goto out1;
 		}
 		xp = VTOI(xvp);
-		if (xp->i_ump->um_fstype == UFS1)
+		if (I_IS_UFS1(xp))
 			error = expunge_ufs1(vp, xp, copy_fs, fullacct_ufs1,
 			    BLK_NOCOPY, 0);
 		else
@@ -706,7 +706,7 @@ out1:
 	TAILQ_FOREACH(xp, &sn->sn_head, i_nextsnap) {
 		if (xp == ip)
 			break;
-		if (xp->i_ump->um_fstype == UFS1)
+		if (I_IS_UFS1(xp))
 			error = expunge_ufs1(vp, xp, fs, snapacct_ufs1,
 			    BLK_SNAP, 0);
 		else
@@ -735,7 +735,7 @@ out1:
 	 * blocks marked as used in the snapshot bitmaps. Also, collect
 	 * the list of allocated blocks in i_snapblklist.
 	 */
-	if (ip->i_ump->um_fstype == UFS1)
+	if (I_IS_UFS1(ip))
 		error = expunge_ufs1(vp, ip, copy_fs, mapacct_ufs1,
 		    BLK_SNAP, 0);
 	else
@@ -887,9 +887,9 @@ cgaccount(cg, vp, nbp, passno)
 	int error, len, loc, indiroff;
 
 	ip = VTOI(vp);
-	fs = ip->i_fs;
-	error = bread(ip->i_devvp, fsbtodb(fs, cgtod(fs, cg)),
-		(int)fs->fs_cgsize, KERNCRED, &bp);
+	fs = ITOFS(ip);
+	error = bread(ITODEVVP(ip), fsbtodb(fs, cgtod(fs, cg)),
+	    (int)fs->fs_cgsize, KERNCRED, &bp);
 	if (error) {
 		brelse(bp);
 		return (error);
@@ -899,7 +899,7 @@ cgaccount(cg, vp, nbp, passno)
 		brelse(bp);
 		return (EIO);
 	}
-	UFS_LOCK(ip->i_ump);
+	UFS_LOCK(ITOUMP(ip));
 	ACTIVESET(fs, cg);
 	/*
 	 * Recomputation of summary information might not have been performed
@@ -908,7 +908,7 @@ cgaccount(cg, vp, nbp, passno)
 	 * fsck is slightly more consistent.
 	 */
 	fs->fs_cs(fs, cg) = cgp->cg_cs;
-	UFS_UNLOCK(ip->i_ump);
+	UFS_UNLOCK(ITOUMP(ip));
 	bcopy(bp->b_data, nbp->b_data, fs->fs_cgsize);
 	if (fs->fs_cgsize < fs->fs_bsize)
 		bzero(&nbp->b_data[fs->fs_cgsize],
@@ -952,7 +952,7 @@ cgaccount(cg, vp, nbp, passno)
 			}
 			indiroff = 0;
 		}
-		if (ip->i_ump->um_fstype == UFS1) {
+		if (I_IS_UFS1(ip)) {
 			if (ffs_isblock(fs, cg_blksfree(cgp), loc))
 				((ufs1_daddr_t *)(ibp->b_data))[indiroff] =
 				    BLK_NOCOPY;
@@ -1257,7 +1257,7 @@ mapacct_ufs1(vp, oldblkp, lastblkp, fs, lblkno, expungetype)
 			*ip->i_snapblklist++ = lblkno;
 		if (blkno == BLK_SNAP)
 			blkno = blkstofrags(fs, lblkno);
-		ffs_blkfree(ip->i_ump, fs, vp, blkno, fs->fs_bsize, inum,
+		ffs_blkfree(ITOUMP(ip), fs, vp, blkno, fs->fs_bsize, inum,
 		    vp->v_type, NULL);
 	}
 	return (0);
@@ -1541,7 +1541,7 @@ mapacct_ufs2(vp, oldblkp, lastblkp, fs, lblkno, expungetype)
 			*ip->i_snapblklist++ = lblkno;
 		if (blkno == BLK_SNAP)
 			blkno = blkstofrags(fs, lblkno);
-		ffs_blkfree(ip->i_ump, fs, vp, blkno, fs->fs_bsize, inum,
+		ffs_blkfree(ITOUMP(ip), fs, vp, blkno, fs->fs_bsize, inum,
 		    vp->v_type, NULL);
 	}
 	return (0);
@@ -1565,7 +1565,7 @@ ffs_snapgone(ip)
 	 * Find snapshot in incore list.
 	 */
 	xp = NULL;
-	sn = ip->i_devvp->v_rdev->si_snapdata;
+	sn = ITODEVVP(ip)->v_rdev->si_snapdata;
 	if (sn != NULL)
 		TAILQ_FOREACH(xp, &sn->sn_head, i_nextsnap)
 			if (xp == ip)
@@ -1578,8 +1578,8 @@ ffs_snapgone(ip)
 	/*
 	 * Delete snapshot inode from superblock. Keep list dense.
 	 */
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	UFS_LOCK(ump);
 	for (snaploc = 0; snaploc < FSMAXSNAP; snaploc++)
 		if (fs->fs_snapinum[snaploc] == ip->i_number)
@@ -1611,8 +1611,8 @@ ffs_snapremove(vp)
 	struct snapdata *sn;
 
 	ip = VTOI(vp);
-	fs = ip->i_fs;
-	devvp = ip->i_devvp;
+	fs = ITOFS(ip);
+	devvp = ITODEVVP(ip);
 	/*
 	 * If active, delete from incore list (this snapshot may
 	 * already have been in the process of being deleted, so
@@ -1646,7 +1646,7 @@ ffs_snapremove(vp)
 		if (dblk == BLK_NOCOPY || dblk == BLK_SNAP)
 			DIP_SET(ip, i_db[blkno], 0);
 		else if ((dblk == blkstofrags(fs, blkno) &&
-		     ffs_snapblkfree(fs, ip->i_devvp, dblk, fs->fs_bsize,
+		     ffs_snapblkfree(fs, ITODEVVP(ip), dblk, fs->fs_bsize,
 		     ip->i_number, vp->v_type, NULL))) {
 			DIP_SET(ip, i_blocks, DIP(ip, i_blocks) -
 			    btodb(fs->fs_bsize));
@@ -1664,14 +1664,14 @@ ffs_snapremove(vp)
 		else
 			last = fs->fs_size - blkno;
 		for (loc = 0; loc < last; loc++) {
-			if (ip->i_ump->um_fstype == UFS1) {
+			if (I_IS_UFS1(ip)) {
 				dblk = ((ufs1_daddr_t *)(ibp->b_data))[loc];
 				if (dblk == 0)
 					continue;
 				if (dblk == BLK_NOCOPY || dblk == BLK_SNAP)
 					((ufs1_daddr_t *)(ibp->b_data))[loc]= 0;
 				else if ((dblk == blkstofrags(fs, blkno) &&
-				     ffs_snapblkfree(fs, ip->i_devvp, dblk,
+				     ffs_snapblkfree(fs, ITODEVVP(ip), dblk,
 				     fs->fs_bsize, ip->i_number, vp->v_type,
 				     NULL))) {
 					ip->i_din1->di_blocks -=
@@ -1686,7 +1686,7 @@ ffs_snapremove(vp)
 			if (dblk == BLK_NOCOPY || dblk == BLK_SNAP)
 				((ufs2_daddr_t *)(ibp->b_data))[loc] = 0;
 			else if ((dblk == blkstofrags(fs, blkno) &&
-			     ffs_snapblkfree(fs, ip->i_devvp, dblk,
+			     ffs_snapblkfree(fs, ITODEVVP(ip), dblk,
 			     fs->fs_bsize, ip->i_number, vp->v_type, NULL))) {
 				ip->i_din2->di_blocks -= btodb(fs->fs_bsize);
 				((ufs2_daddr_t *)(ibp->b_data))[loc] = 0;
@@ -1781,7 +1781,7 @@ retry:
 			if (error)
 				break;
 			indiroff = (lbn - NDADDR) % NINDIR(fs);
-			if (ip->i_ump->um_fstype == UFS1)
+			if (I_IS_UFS1(ip))
 				blkno=((ufs1_daddr_t *)(ibp->b_data))[indiroff];
 			else
 				blkno=((ufs2_daddr_t *)(ibp->b_data))[indiroff];
@@ -1806,7 +1806,7 @@ retry:
 			if (lbn < NDADDR) {
 				DIP_SET(ip, i_db[lbn], BLK_NOCOPY);
 				ip->i_flag |= IN_CHANGE | IN_UPDATE;
-			} else if (ip->i_ump->um_fstype == UFS1) {
+			} else if (I_IS_UFS1(ip)) {
 				((ufs1_daddr_t *)(ibp->b_data))[indiroff] =
 				    BLK_NOCOPY;
 				bdwrite(ibp);
@@ -1854,7 +1854,7 @@ retry:
 			}
 			if (lbn < NDADDR) {
 				DIP_SET(ip, i_db[lbn], bno);
-			} else if (ip->i_ump->um_fstype == UFS1) {
+			} else if (I_IS_UFS1(ip)) {
 				((ufs1_daddr_t *)(ibp->b_data))[indiroff] = bno;
 				bdwrite(ibp);
 			} else {
@@ -2136,7 +2136,7 @@ ffs_bp_snapblk(devvp, bp)
 	sn = devvp->v_rdev->si_snapdata;
 	if (sn == NULL || TAILQ_FIRST(&sn->sn_head) == NULL)
 		return (0);
-	fs = TAILQ_FIRST(&sn->sn_head)->i_fs;
+	fs = ITOFS(TAILQ_FIRST(&sn->sn_head));
 	lbn = fragstoblks(fs, dbtofsb(fs, bp->b_blkno));
 	snapblklist = sn->sn_blklist;
 	upper = sn->sn_listsize - 1;
@@ -2263,7 +2263,7 @@ ffs_copyonwrite(devvp, bp)
 		return (0);		/* No snapshot */
 	}
 	ip = TAILQ_FIRST(&sn->sn_head);
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	lbn = fragstoblks(fs, dbtofsb(fs, bp->b_blkno));
 	snapblklist = sn->sn_blklist;
 	upper = sn->sn_listsize - 1;
@@ -2337,7 +2337,7 @@ ffs_copyonwrite(devvp, bp)
 			if (error)
 				break;
 			indiroff = (lbn - NDADDR) % NINDIR(fs);
-			if (ip->i_ump->um_fstype == UFS1)
+			if (I_IS_UFS1(ip))
 				blkno=((ufs1_daddr_t *)(ibp->b_data))[indiroff];
 			else
 				blkno=((ufs2_daddr_t *)(ibp->b_data))[indiroff];
@@ -2493,15 +2493,19 @@ readblock(vp, bp, lbn)
 {
 	struct inode *ip = VTOI(vp);
 	struct bio *bip;
+	struct fs *fs;
+
+	ip = VTOI(vp);
+	fs = ITOFS(ip);
 
 	bip = g_alloc_bio();
 	bip->bio_cmd = BIO_READ;
-	bip->bio_offset = dbtob(fsbtodb(ip->i_fs, blkstofrags(ip->i_fs, lbn)));
+	bip->bio_offset = dbtob(fsbtodb(fs, blkstofrags(fs, lbn)));
 	bip->bio_data = bp->b_data;
 	bip->bio_length = bp->b_bcount;
 	bip->bio_done = NULL;
 
-	g_io_request(bip, ip->i_devvp->v_bufobj.bo_private);
+	g_io_request(bip, ITODEVVP(ip)->v_bufobj.bo_private);
 	bp->b_error = biowait(bip, "snaprdb");
 	g_destroy_bio(bip);
 	return (bp->b_error);
diff --git a/sys/ufs/ffs/ffs_softdep.c b/sys/ufs/ffs/ffs_softdep.c
index 7434974ce9c6..812cc56517b7 100644
--- a/sys/ufs/ffs/ffs_softdep.c
+++ b/sys/ufs/ffs/ffs_softdep.c
@@ -3998,7 +3998,7 @@ newjmvref(dp, ino, oldoff, newoff)
 	struct jmvref *jmvref;
 
 	jmvref = malloc(sizeof(*jmvref), M_JMVREF, M_SOFTDEP_FLAGS);
-	workitem_alloc(&jmvref->jm_list, D_JMVREF, UFSTOVFS(dp->i_ump));
+	workitem_alloc(&jmvref->jm_list, D_JMVREF, ITOVFS(dp));
 	jmvref->jm_list.wk_state = ATTACHED | DEPCOMPLETE;
 	jmvref->jm_parent = dp->i_number;
 	jmvref->jm_ino = ino;
@@ -4025,7 +4025,7 @@ newjremref(struct dirrem *dirrem, struct inode *dp, struct inode *ip,
 	struct jremref *jremref;
 
 	jremref = malloc(sizeof(*jremref), M_JREMREF, M_SOFTDEP_FLAGS);
-	workitem_alloc(&jremref->jr_list, D_JREMREF, UFSTOVFS(dp->i_ump));
+	workitem_alloc(&jremref->jr_list, D_JREMREF, ITOVFS(dp));
 	jremref->jr_state = ATTACHED;
 	newinoref(&jremref->jr_ref, ip->i_number, dp->i_number, diroff,
 	   nlink, ip->i_mode);
@@ -4061,7 +4061,7 @@ newjaddref(struct inode *dp, ino_t ino, off_t diroff, int16_t nlink,
 	struct jaddref *jaddref;
 
 	jaddref = malloc(sizeof(*jaddref), M_JADDREF, M_SOFTDEP_FLAGS);
-	workitem_alloc(&jaddref->ja_list, D_JADDREF, UFSTOVFS(dp->i_ump));
+	workitem_alloc(&jaddref->ja_list, D_JADDREF, ITOVFS(dp));
 	jaddref->ja_state = ATTACHED;
 	jaddref->ja_mkdir = NULL;
 	newinoref(&jaddref->ja_ref, ino, dp->i_number, diroff, nlink, mode);
@@ -4649,7 +4649,7 @@ inodedep_lookup_ip(ip)
 
 	KASSERT(ip->i_nlink >= ip->i_effnlink,
 	    ("inodedep_lookup_ip: bad delta"));
-	(void) inodedep_lookup(UFSTOVFS(ip->i_ump), ip->i_number, DEPALLOC,
+	(void) inodedep_lookup(ITOVFS(ip), ip->i_number, DEPALLOC,
 	    &inodedep);
 	inodedep->id_nlinkdelta = ip->i_nlink - ip->i_effnlink;
 	KASSERT((inodedep->id_state & UNLINKED) == 0, ("inode unlinked"));
@@ -4672,12 +4672,12 @@ softdep_setup_create(dp, ip)
 	struct jaddref *jaddref;
 	struct vnode *dvp;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS(dp)) != 0,
 	    ("softdep_setup_create called on non-softdep filesystem"));
 	KASSERT(ip->i_nlink == 1,
 	    ("softdep_setup_create: Invalid link count."));
 	dvp = ITOV(dp);
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	inodedep = inodedep_lookup_ip(ip);
 	if (DOINGSUJ(dvp)) {
 		jaddref = (struct jaddref *)TAILQ_LAST(&inodedep->id_inoreflst,
@@ -4686,7 +4686,7 @@ softdep_setup_create(dp, ip)
 		    ("softdep_setup_create: No addref structure present."));
 	}
 	softdep_prelink(dvp, NULL);
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /*
@@ -4704,7 +4704,7 @@ softdep_setup_dotdot_link(dp, ip)
 	struct jaddref *jaddref;
 	struct vnode *dvp;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS(dp)) != 0,
 	    ("softdep_setup_dotdot_link called on non-softdep filesystem"));
 	dvp = ITOV(dp);
 	jaddref = NULL;
@@ -4715,13 +4715,13 @@ softdep_setup_dotdot_link(dp, ip)
 	if (DOINGSUJ(dvp))
 		jaddref = newjaddref(ip, dp->i_number, DOTDOT_OFFSET,
 		    dp->i_effnlink - 1, dp->i_mode);
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	inodedep = inodedep_lookup_ip(dp);
 	if (jaddref)
 		TAILQ_INSERT_TAIL(&inodedep->id_inoreflst, &jaddref->ja_ref,
 		    if_deps);
 	softdep_prelink(dvp, ITOV(ip));
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /*
@@ -4739,20 +4739,20 @@ softdep_setup_link(dp, ip)
 	struct jaddref *jaddref;
 	struct vnode *dvp;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS(dp)) != 0,
 	    ("softdep_setup_link called on non-softdep filesystem"));
 	dvp = ITOV(dp);
 	jaddref = NULL;
 	if (DOINGSUJ(dvp))
 		jaddref = newjaddref(dp, ip->i_number, 0, ip->i_effnlink - 1,
 		    ip->i_mode);
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	inodedep = inodedep_lookup_ip(ip);
 	if (jaddref)
 		TAILQ_INSERT_TAIL(&inodedep->id_inoreflst, &jaddref->ja_ref,
 		    if_deps);
 	softdep_prelink(dvp, ITOV(ip));
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /*
@@ -4772,7 +4772,7 @@ softdep_setup_mkdir(dp, ip)
 	struct jaddref *jaddref;
 	struct vnode *dvp;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS(dp)) != 0,
 	    ("softdep_setup_mkdir called on non-softdep filesystem"));
 	dvp = ITOV(dp);
 	dotaddref = dotdotaddref = NULL;
@@ -4784,7 +4784,7 @@ softdep_setup_mkdir(dp, ip)
 		    dp->i_effnlink - 1, dp->i_mode);
 		dotdotaddref->ja_state |= MKDIR_PARENT;
 	}
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	inodedep = inodedep_lookup_ip(ip);
 	if (DOINGSUJ(dvp)) {
 		jaddref = (struct jaddref *)TAILQ_LAST(&inodedep->id_inoreflst,
@@ -4802,7 +4802,7 @@ softdep_setup_mkdir(dp, ip)
 		TAILQ_INSERT_TAIL(&inodedep->id_inoreflst,
 		    &dotdotaddref->ja_ref, if_deps);
 	softdep_prelink(ITOV(dp), NULL);
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /*
@@ -4816,14 +4816,14 @@ softdep_setup_rmdir(dp, ip)
 {
 	struct vnode *dvp;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS(dp)) != 0,
 	    ("softdep_setup_rmdir called on non-softdep filesystem"));
 	dvp = ITOV(dp);
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	(void) inodedep_lookup_ip(ip);
 	(void) inodedep_lookup_ip(dp);
 	softdep_prelink(dvp, ITOV(ip));
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /*
@@ -4837,14 +4837,14 @@ softdep_setup_unlink(dp, ip)
 {
 	struct vnode *dvp;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS(dp)) != 0,
 	    ("softdep_setup_unlink called on non-softdep filesystem"));
 	dvp = ITOV(dp);
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	(void) inodedep_lookup_ip(ip);
 	(void) inodedep_lookup_ip(dp);
 	softdep_prelink(dvp, ITOV(ip));
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /*
@@ -4860,10 +4860,10 @@ softdep_revert_create(dp, ip)
 	struct jaddref *jaddref;
 	struct vnode *dvp;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS((dp))) != 0,
 	    ("softdep_revert_create called on non-softdep filesystem"));
 	dvp = ITOV(dp);
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	inodedep = inodedep_lookup_ip(ip);
 	if (DOINGSUJ(dvp)) {
 		jaddref = (struct jaddref *)TAILQ_LAST(&inodedep->id_inoreflst,
@@ -4872,7 +4872,7 @@ softdep_revert_create(dp, ip)
 		    ("softdep_revert_create: addref parent mismatch"));
 		cancel_jaddref(jaddref, inodedep, &inodedep->id_inowait);
 	}
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /*
@@ -4888,10 +4888,10 @@ softdep_revert_link(dp, ip)
 	struct jaddref *jaddref;
 	struct vnode *dvp;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS(dp)) != 0,
 	    ("softdep_revert_link called on non-softdep filesystem"));
 	dvp = ITOV(dp);
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	inodedep = inodedep_lookup_ip(ip);
 	if (DOINGSUJ(dvp)) {
 		jaddref = (struct jaddref *)TAILQ_LAST(&inodedep->id_inoreflst,
@@ -4900,7 +4900,7 @@ softdep_revert_link(dp, ip)
 		    ("softdep_revert_link: addref parent mismatch"));
 		cancel_jaddref(jaddref, inodedep, &inodedep->id_inowait);
 	}
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /*
@@ -4917,11 +4917,11 @@ softdep_revert_mkdir(dp, ip)
 	struct jaddref *dotaddref;
 	struct vnode *dvp;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS(dp)) != 0,
 	    ("softdep_revert_mkdir called on non-softdep filesystem"));
 	dvp = ITOV(dp);
 
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	inodedep = inodedep_lookup_ip(dp);
 	if (DOINGSUJ(dvp)) {
 		jaddref = (struct jaddref *)TAILQ_LAST(&inodedep->id_inoreflst,
@@ -4943,7 +4943,7 @@ softdep_revert_mkdir(dp, ip)
 		    ("softdep_revert_mkdir: dot addref parent mismatch"));
 		cancel_jaddref(dotaddref, inodedep, &inodedep->id_inowait);
 	}
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /* 
@@ -4955,12 +4955,12 @@ softdep_revert_rmdir(dp, ip)
 	struct inode *ip;
 {
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(dp->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(ITOVFS(dp)) != 0,
 	    ("softdep_revert_rmdir called on non-softdep filesystem"));
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ITOUMP(dp));
 	(void) inodedep_lookup_ip(ip);
 	(void) inodedep_lookup_ip(dp);
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ITOUMP(dp));
 }
 
 /*
@@ -5011,10 +5011,10 @@ softdep_setup_inomapdep(bp, ip, newinum, mode)
 	struct mount *mp;
 	struct fs *fs;
 
-	mp = UFSTOVFS(ip->i_ump);
+	mp = ITOVFS(ip);
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	    ("softdep_setup_inomapdep called on non-softdep filesystem"));
-	fs = ip->i_ump->um_fs;
+	fs = VFSTOUFS(mp)->um_fs;
 	jaddref = NULL;
 
 	/*
@@ -5046,7 +5046,7 @@ softdep_setup_inomapdep(bp, ip, newinum, mode)
 	bmsafemap = malloc(sizeof(struct bmsafemap),
 	    M_BMSAFEMAP, M_SOFTDEP_FLAGS);
 	workitem_alloc(&bmsafemap->sm_list, D_BMSAFEMAP, mp);
-	ACQUIRE_LOCK(ip->i_ump);
+	ACQUIRE_LOCK(ITOUMP(ip));
 	if ((inodedep_lookup(mp, newinum, DEPALLOC, &inodedep)))
 		panic("softdep_setup_inomapdep: dependency %p for new"
 		    "inode already exists", inodedep);
@@ -5061,7 +5061,7 @@ softdep_setup_inomapdep(bp, ip, newinum, mode)
 	}
 	inodedep->id_bmsafemap = bmsafemap;
 	inodedep->id_state &= ~DEPCOMPLETE;
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(ITOUMP(ip));
 }
 
 /*
@@ -5283,7 +5283,7 @@ softdep_setup_allocdirect(ip, off, newblkno, oldblkno, newsize, oldsize, bp)
 	ufs_lbn_t lbn;
 
 	lbn = bp->b_lblkno;
-	mp = UFSTOVFS(ip->i_ump);
+	mp = ITOVFS(ip);
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	    ("softdep_setup_allocdirect called on non-softdep filesystem"));
 	if (oldblkno && oldblkno != newblkno)
@@ -5295,7 +5295,7 @@ softdep_setup_allocdirect(ip, off, newblkno, oldblkno, newsize, oldsize, bp)
 	    "softdep_setup_allocdirect: ino %d blkno %jd oldblkno %jd "
 	    "off %jd newsize %ld oldsize %d",
 	    ip->i_number, newblkno, oldblkno, off, newsize, oldsize);
-	ACQUIRE_LOCK(ip->i_ump);
+	ACQUIRE_LOCK(ITOUMP(ip));
 	if (off >= NDADDR) {
 		if (lbn > 0)
 			panic("softdep_setup_allocdirect: bad lbn %jd, off %jd",
@@ -5367,7 +5367,7 @@ softdep_setup_allocdirect(ip, off, newblkno, oldblkno, newsize, oldsize, bp)
 		TAILQ_INSERT_TAIL(adphead, adp, ad_next);
 		if (oldadp != NULL && oldadp->ad_offset == off)
 			allocdirect_merge(adphead, adp, oldadp);
-		FREE_LOCK(ip->i_ump);
+		FREE_LOCK(ITOUMP(ip));
 		return;
 	}
 	TAILQ_FOREACH(oldadp, adphead, ad_next) {
@@ -5381,7 +5381,7 @@ softdep_setup_allocdirect(ip, off, newblkno, oldblkno, newsize, oldsize, bp)
 	if (oldadp->ad_offset == off)
 		allocdirect_merge(adphead, adp, oldadp);
 
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(ITOUMP(ip));
 }
 
 /*
@@ -5545,10 +5545,10 @@ newjfreefrag(freefrag, ip, blkno, size, lbn)
 	struct jfreefrag *jfreefrag;
 	struct fs *fs;
 
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	jfreefrag = malloc(sizeof(struct jfreefrag), M_JFREEFRAG,
 	    M_SOFTDEP_FLAGS);
-	workitem_alloc(&jfreefrag->fr_list, D_JFREEFRAG, UFSTOVFS(ip->i_ump));
+	workitem_alloc(&jfreefrag->fr_list, D_JFREEFRAG, ITOVFS(ip));
 	jfreefrag->fr_jsegdep = newjsegdep(&jfreefrag->fr_list);
 	jfreefrag->fr_state = ATTACHED | DEPCOMPLETE;
 	jfreefrag->fr_ino = ip->i_number;
@@ -5571,16 +5571,18 @@ newfreefrag(ip, blkno, size, lbn)
 	ufs_lbn_t lbn;
 {
 	struct freefrag *freefrag;
+	struct ufsmount *ump;
 	struct fs *fs;
 
 	CTR4(KTR_SUJ, "newfreefrag: ino %d blkno %jd size %ld lbn %jd",
 	    ip->i_number, blkno, size, lbn);
-	fs = ip->i_fs;
+	ump = ITOUMP(ip);
+	fs = ump->um_fs;
 	if (fragnum(fs, blkno) + numfrags(fs, size) > fs->fs_frag)
 		panic("newfreefrag: frag size");
 	freefrag = malloc(sizeof(struct freefrag),
 	    M_FREEFRAG, M_SOFTDEP_FLAGS);
-	workitem_alloc(&freefrag->ff_list, D_FREEFRAG, UFSTOVFS(ip->i_ump));
+	workitem_alloc(&freefrag->ff_list, D_FREEFRAG, UFSTOVFS(ump));
 	freefrag->ff_state = ATTACHED;
 	LIST_INIT(&freefrag->ff_jwork);
 	freefrag->ff_inum = ip->i_number;
@@ -5588,7 +5590,7 @@ newfreefrag(ip, blkno, size, lbn)
 	freefrag->ff_blkno = blkno;
 	freefrag->ff_fragsize = size;
 
-	if (MOUNTEDSUJ(UFSTOVFS(ip->i_ump))) {
+	if (MOUNTEDSUJ(UFSTOVFS(ump))) {
 		freefrag->ff_jdep = (struct worklist *)
 		    newjfreefrag(freefrag, ip, blkno, size, lbn);
 	} else {
@@ -5660,9 +5662,11 @@ softdep_setup_allocext(ip, off, newblkno, oldblkno, newsize, oldsize, bp)
 	struct jnewblk *jnewblk;
 	struct newblk *newblk;
 	struct mount *mp;
+	struct ufsmount *ump;
 	ufs_lbn_t lbn;
 
-	mp = UFSTOVFS(ip->i_ump);
+	mp = ITOVFS(ip);
+	ump = VFSTOUFS(mp);
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	    ("softdep_setup_allocext called on non-softdep filesystem"));
 	KASSERT(off < NXADDR, ("softdep_setup_allocext: lbn %lld > NXADDR",
@@ -5674,7 +5678,7 @@ softdep_setup_allocext(ip, off, newblkno, oldblkno, newsize, oldsize, bp)
 	else
 		freefrag = NULL;
 
-	ACQUIRE_LOCK(ip->i_ump);
+	ACQUIRE_LOCK(ump);
 	if (newblk_lookup(mp, newblkno, 0, &newblk) == 0)
 		panic("softdep_setup_allocext: lost block");
 	KASSERT(newblk->nb_list.wk_type == D_NEWBLK,
@@ -5725,7 +5729,7 @@ softdep_setup_allocext(ip, off, newblkno, oldblkno, newsize, oldsize, bp)
 		TAILQ_INSERT_TAIL(adphead, adp, ad_next);
 		if (oldadp != NULL && oldadp->ad_offset == off)
 			allocdirect_merge(adphead, adp, oldadp);
-		FREE_LOCK(ip->i_ump);
+		FREE_LOCK(ump);
 		return;
 	}
 	TAILQ_FOREACH(oldadp, adphead, ad_next) {
@@ -5738,7 +5742,7 @@ softdep_setup_allocext(ip, off, newblkno, oldblkno, newsize, oldsize, bp)
 	TAILQ_INSERT_BEFORE(oldadp, adp, ad_next);
 	if (oldadp->ad_offset == off)
 		allocdirect_merge(adphead, adp, oldadp);
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(ump);
 }
 
 /*
@@ -5783,11 +5787,11 @@ newallocindir(ip, ptrno, newblkno, oldblkno, lbn)
 	struct jnewblk *jnewblk;
 
 	if (oldblkno)
-		freefrag = newfreefrag(ip, oldblkno, ip->i_fs->fs_bsize, lbn);
+		freefrag = newfreefrag(ip, oldblkno, ITOFS(ip)->fs_bsize, lbn);
 	else
 		freefrag = NULL;
-	ACQUIRE_LOCK(ip->i_ump);
-	if (newblk_lookup(UFSTOVFS(ip->i_ump), newblkno, 0, &newblk) == 0)
+	ACQUIRE_LOCK(ITOUMP(ip));
+	if (newblk_lookup(ITOVFS(ip), newblkno, 0, &newblk) == 0)
 		panic("new_allocindir: lost block");
 	KASSERT(newblk->nb_list.wk_type == D_NEWBLK,
 	    ("newallocindir: newblk already initialized"));
@@ -5827,8 +5831,10 @@ softdep_setup_allocindir_page(ip, lbn, bp, ptrno, newblkno, oldblkno, nbp)
 	struct allocindir *aip;
 	struct pagedep *pagedep;
 	struct mount *mp;
+	struct ufsmount *ump;
 
-	mp = UFSTOVFS(ip->i_ump);
+	mp = ITOVFS(ip);
+	ump = VFSTOUFS(mp);
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	    ("softdep_setup_allocindir_page called on non-softdep filesystem"));
 	KASSERT(lbn == nbp->b_lblkno,
@@ -5849,7 +5855,7 @@ softdep_setup_allocindir_page(ip, lbn, bp, ptrno, newblkno, oldblkno, nbp)
 		pagedep_lookup(mp, nbp, ip->i_number, lbn, DEPALLOC, &pagedep);
 	WORKLIST_INSERT(&nbp->b_dep, &aip->ai_block.nb_list);
 	freefrag = setup_allocindir_phase2(bp, ip, inodedep, aip, lbn);
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(ump);
 	if (freefrag)
 		handle_workitem_freefrag(freefrag);
 }
@@ -5868,9 +5874,11 @@ softdep_setup_allocindir_meta(nbp, ip, bp, ptrno, newblkno)
 {
 	struct inodedep *inodedep;
 	struct allocindir *aip;
+	struct ufsmount *ump;
 	ufs_lbn_t lbn;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ip->i_ump)) != 0,
+	ump = ITOUMP(ip);
+	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ump)) != 0,
 	    ("softdep_setup_allocindir_meta called on non-softdep filesystem"));
 	CTR3(KTR_SUJ,
 	    "softdep_setup_allocindir_meta: ino %d blkno %jd ptrno %d",
@@ -5878,12 +5886,11 @@ softdep_setup_allocindir_meta(nbp, ip, bp, ptrno, newblkno)
 	lbn = nbp->b_lblkno;
 	ASSERT_VOP_LOCKED(ITOV(ip), "softdep_setup_allocindir_meta");
 	aip = newallocindir(ip, ptrno, newblkno, 0, lbn);
-	inodedep_lookup(UFSTOVFS(ip->i_ump), ip->i_number, DEPALLOC,
-	    &inodedep);
+	inodedep_lookup(UFSTOVFS(ump), ip->i_number, DEPALLOC, &inodedep);
 	WORKLIST_INSERT(&nbp->b_dep, &aip->ai_block.nb_list);
 	if (setup_allocindir_phase2(bp, ip, inodedep, aip, lbn))
 		panic("softdep_setup_allocindir_meta: Block already existed");
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(ump);
 }
 
 static void
@@ -5925,7 +5932,7 @@ indirdep_lookup(mp, ip, bp)
 	LOCK_OWNED(ump);
 	indirdep = NULL;
 	newindirdep = NULL;
-	fs = ip->i_fs;
+	fs = ump->um_fs;
 	for (;;) {
 		LIST_FOREACH(wk, &bp->b_dep, wk_list) {
 			if (wk->wk_type != D_INDIRDEP)
@@ -5947,7 +5954,7 @@ indirdep_lookup(mp, ip, bp)
 		    M_INDIRDEP, M_SOFTDEP_FLAGS);
 		workitem_alloc(&newindirdep->ir_list, D_INDIRDEP, mp);
 		newindirdep->ir_state = ATTACHED;
-		if (ip->i_ump->um_fstype == UFS1)
+		if (I_IS_UFS1(ip))
 			newindirdep->ir_state |= UFS1FMT;
 		TAILQ_INIT(&newindirdep->ir_trunc);
 		newindirdep->ir_saveddata = NULL;
@@ -5962,7 +5969,7 @@ indirdep_lookup(mp, ip, bp)
 		}
 		newindirdep->ir_freeblks = NULL;
 		newindirdep->ir_savebp =
-		    getblk(ip->i_devvp, bp->b_blkno, bp->b_bcount, 0, 0, 0);
+		    getblk(ump->um_devvp, bp->b_blkno, bp->b_bcount, 0, 0, 0);
 		newindirdep->ir_bp = bp;
 		BUF_KERNPROC(newindirdep->ir_savebp);
 		bcopy(bp->b_data, newindirdep->ir_savebp->b_data, bp->b_bcount);
@@ -6000,10 +6007,12 @@ setup_allocindir_phase2(bp, ip, inodedep, aip, lbn)
 	struct allocindir *oldaip;
 	struct freefrag *freefrag;
 	struct mount *mp;
+	struct ufsmount *ump;
 
-	LOCK_OWNED(ip->i_ump);
-	mp = UFSTOVFS(ip->i_ump);
-	fs = ip->i_fs;
+	mp = ITOVFS(ip);
+	ump = VFSTOUFS(mp);
+	LOCK_OWNED(ump);
+	fs = ump->um_fs;
 	if (bp->b_lblkno >= 0)
 		panic("setup_allocindir_phase2: not indir blk");
 	KASSERT(aip->ai_offset >= 0 && aip->ai_offset < NINDIR(fs),
@@ -6088,6 +6097,7 @@ setup_freedirect(freeblks, ip, i, needj)
 	int i;
 	int needj;
 {
+	struct ufsmount *ump;
 	ufs2_daddr_t blkno;
 	int frags;
 
@@ -6095,9 +6105,10 @@ setup_freedirect(freeblks, ip, i, needj)
 	if (blkno == 0)
 		return;
 	DIP_SET(ip, i_db[i], 0);
-	frags = sblksize(ip->i_fs, ip->i_size, i);
-	frags = numfrags(ip->i_fs, frags);
-	newfreework(ip->i_ump, freeblks, NULL, i, blkno, frags, 0, needj);
+	ump = ITOUMP(ip);
+	frags = sblksize(ump->um_fs, ip->i_size, i);
+	frags = numfrags(ump->um_fs, frags);
+	newfreework(ump, freeblks, NULL, i, blkno, frags, 0, needj);
 }
 
 static inline void
@@ -6107,6 +6118,7 @@ setup_freeext(freeblks, ip, i, needj)
 	int i;
 	int needj;
 {
+	struct ufsmount *ump;
 	ufs2_daddr_t blkno;
 	int frags;
 
@@ -6114,9 +6126,10 @@ setup_freeext(freeblks, ip, i, needj)
 	if (blkno == 0)
 		return;
 	ip->i_din2->di_extb[i] = 0;
-	frags = sblksize(ip->i_fs, ip->i_din2->di_extsize, i);
-	frags = numfrags(ip->i_fs, frags);
-	newfreework(ip->i_ump, freeblks, NULL, -1 - i, blkno, frags, 0, needj);
+	ump = ITOUMP(ip);
+	frags = sblksize(ump->um_fs, ip->i_din2->di_extsize, i);
+	frags = numfrags(ump->um_fs, frags);
+	newfreework(ump, freeblks, NULL, -1 - i, blkno, frags, 0, needj);
 }
 
 static inline void
@@ -6127,13 +6140,15 @@ setup_freeindir(freeblks, ip, i, lbn, needj)
 	ufs_lbn_t lbn;
 	int needj;
 {
+	struct ufsmount *ump;
 	ufs2_daddr_t blkno;
 
 	blkno = DIP(ip, i_ib[i]);
 	if (blkno == 0)
 		return;
 	DIP_SET(ip, i_ib[i], 0);
-	newfreework(ip->i_ump, freeblks, NULL, lbn, blkno, ip->i_fs->fs_frag,
+	ump = ITOUMP(ip);
+	newfreework(ump, freeblks, NULL, lbn, blkno, ump->um_fs->fs_frag,
 	    0, needj);
 }
 
@@ -6156,7 +6171,7 @@ newfreeblks(mp, ip)
 	freeblks->fb_inum = ip->i_number;
 	freeblks->fb_vtype = ITOV(ip)->v_type;
 	freeblks->fb_modrev = DIP(ip, i_modrev);
-	freeblks->fb_devvp = ip->i_devvp;
+	freeblks->fb_devvp = ITODEVVP(ip);
 	freeblks->fb_chkcnt = 0;
 	freeblks->fb_len = 0;
 
@@ -6211,6 +6226,7 @@ setup_trunc_indir(freeblks, ip, lbn, lastlbn, blkno)
 	struct freework *freework;
 	struct newblk *newblk;
 	struct mount *mp;
+	struct ufsmount *ump;
 	struct buf *bp;
 	uint8_t *start;
 	uint8_t *end;
@@ -6224,6 +6240,7 @@ setup_trunc_indir(freeblks, ip, lbn, lastlbn, blkno)
 	if (blkno == 0)
 		return (0);
 	mp = freeblks->fb_list.wk_mp;
+	ump = VFSTOUFS(mp);
 	bp = getblk(ITOV(ip), lbn, mp->mnt_stat.f_iosize, 0, 0, 0);
 	if ((bp->b_flags & B_CACHE) == 0) {
 		bp->b_blkno = blkptrtodb(VFSTOUFS(mp), blkno);
@@ -6248,22 +6265,21 @@ setup_trunc_indir(freeblks, ip, lbn, lastlbn, blkno)
 		}
 	}
 	level = lbn_level(lbn);
-	lbnadd = lbn_offset(ip->i_fs, level);
+	lbnadd = lbn_offset(ump->um_fs, level);
 	/*
 	 * Compute the offset of the last block we want to keep.  Store
 	 * in the freework the first block we want to completely free.
 	 */
 	off = (lastlbn - -(lbn + level)) / lbnadd;
-	if (off + 1 == NINDIR(ip->i_fs))
+	if (off + 1 == NINDIR(ump->um_fs))
 		goto nowork;
-	freework = newfreework(ip->i_ump, freeblks, NULL, lbn, blkno, 0, off+1,
-	    0);
+	freework = newfreework(ump, freeblks, NULL, lbn, blkno, 0, off + 1, 0);
 	/*
 	 * Link the freework into the indirdep.  This will prevent any new
 	 * allocations from proceeding until we are finished with the
 	 * truncate and the block is written.
 	 */
-	ACQUIRE_LOCK(ip->i_ump);
+	ACQUIRE_LOCK(ump);
 	indirdep = indirdep_lookup(mp, ip, bp);
 	if (indirdep->ir_freeblks)
 		panic("setup_trunc_indir: indirdep already truncated.");
@@ -6275,12 +6291,12 @@ setup_trunc_indir(freeblks, ip, lbn, lastlbn, blkno)
 	 * live on this newblk.
 	 */
 	if ((indirdep->ir_state & DEPCOMPLETE) == 0) {
-		newblk_lookup(mp, dbtofsb(ip->i_fs, bp->b_blkno), 0, &newblk);
+		newblk_lookup(mp, dbtofsb(ump->um_fs, bp->b_blkno), 0, &newblk);
 		LIST_FOREACH(indirn, &newblk->nb_indirdeps, ir_next)
 			trunc_indirdep(indirn, freeblks, bp, off);
 	} else
 		trunc_indirdep(indirdep, freeblks, bp, off);
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(ump);
 	/*
 	 * Creation is protected by the buf lock. The saveddata is only
 	 * needed if a full truncation follows a partial truncation but it
@@ -6291,7 +6307,7 @@ setup_trunc_indir(freeblks, ip, lbn, lastlbn, blkno)
 		    M_SOFTDEP_FLAGS);
 nowork:
 	/* Fetch the blkno of the child and the zero start offset. */
-	if (ip->i_ump->um_fstype == UFS1) {
+	if (I_IS_UFS1(ip)) {
 		blkno = ((ufs1_daddr_t *)bp->b_data)[off];
 		start = (uint8_t *)&((ufs1_daddr_t *)bp->b_data)[off+1];
 	} else {
@@ -6501,9 +6517,9 @@ softdep_journal_freeblocks(ip, cred, length, flags)
 	ufs_lbn_t tmpval, lbn, lastlbn;
 	int frags, lastoff, iboff, allocblock, needj, error, i;
 
-	fs = ip->i_fs;
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
 	mp = UFSTOVFS(ump);
+	fs = ump->um_fs;
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	    ("softdep_journal_freeblocks called on non-softdep filesystem"));
 	vp = ITOV(ip);
@@ -6583,13 +6599,13 @@ softdep_journal_freeblocks(ip, cred, length, flags)
 			blkno = DIP(ip, i_db[lastlbn]);
 			if (blkno && oldfrags != frags) {
 				oldfrags -= frags;
-				oldfrags = numfrags(ip->i_fs, oldfrags);
-				blkno += numfrags(ip->i_fs, frags);
+				oldfrags = numfrags(fs, oldfrags);
+				blkno += numfrags(fs, frags);
 				newfreework(ump, freeblks, NULL, lastlbn,
 				    blkno, oldfrags, 0, needj);
 				if (needj)
 					adjust_newfreework(freeblks,
-					    numfrags(ip->i_fs, frags));
+					    numfrags(fs, frags));
 			} else if (blkno == 0)
 				allocblock = 1;
 		}
@@ -6606,7 +6622,7 @@ softdep_journal_freeblocks(ip, cred, length, flags)
 		DIP_SET(ip, i_size, ip->i_size);
 		datablocks = DIP(ip, i_blocks) - extblocks;
 		if (length != 0)
-			datablocks = blkcount(ip->i_fs, datablocks, length);
+			datablocks = blkcount(fs, datablocks, length);
 		freeblks->fb_len = length;
 	}
 	if ((flags & IO_EXT) != 0) {
@@ -6633,7 +6649,7 @@ softdep_journal_freeblocks(ip, cred, length, flags)
 	 */
 	ufs_itimes(vp);
 	ip->i_flag &= ~(IN_LAZYACCESS | IN_LAZYMOD | IN_MODIFIED);
-	error = bread(ip->i_devvp, fsbtodb(fs, ino_to_fsba(fs, ip->i_number)),
+	error = bread(ump->um_devvp, fsbtodb(fs, ino_to_fsba(fs, ip->i_number)),
 	    (int)fs->fs_bsize, cred, &bp);
 	if (error) {
 		brelse(bp);
@@ -6773,20 +6789,22 @@ softdep_journal_fsync(ip)
 	struct inode *ip;
 {
 	struct jfsync *jfsync;
+	struct ufsmount *ump;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ip->i_ump)) != 0,
+	ump = ITOUMP(ip);
+	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ump)) != 0,
 	    ("softdep_journal_fsync called on non-softdep filesystem"));
 	if ((ip->i_flag & IN_TRUNCATED) == 0)
 		return;
 	ip->i_flag &= ~IN_TRUNCATED;
 	jfsync = malloc(sizeof(*jfsync), M_JFSYNC, M_SOFTDEP_FLAGS | M_ZERO);
-	workitem_alloc(&jfsync->jfs_list, D_JFSYNC, UFSTOVFS(ip->i_ump));
+	workitem_alloc(&jfsync->jfs_list, D_JFSYNC, UFSTOVFS(ump));
 	jfsync->jfs_size = ip->i_size;
 	jfsync->jfs_ino = ip->i_number;
-	ACQUIRE_LOCK(ip->i_ump);
+	ACQUIRE_LOCK(ump);
 	add_to_journal(&jfsync->jfs_list);
 	jwait(&jfsync->jfs_list, MNT_WAIT);
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(ump);
 }
 
 /*
@@ -6838,15 +6856,15 @@ softdep_setup_freeblocks(ip, length, flags)
 	ufs_lbn_t tmpval;
 	ufs_lbn_t lbn;
 
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
 	mp = UFSTOVFS(ump);
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	    ("softdep_setup_freeblocks called on non-softdep filesystem"));
 	CTR2(KTR_SUJ, "softdep_setup_freeblks: ip %d length %ld",
 	    ip->i_number, length);
 	KASSERT(length == 0, ("softdep_setup_freeblocks: non-zero length"));
-	fs = ip->i_fs;
-	if ((error = bread(ip->i_devvp,
+	fs = ump->um_fs;
+	if ((error = bread(ump->um_devvp,
 	    fsbtodb(fs, ino_to_fsba(fs, ip->i_number)),
 	    (int)fs->fs_bsize, NOCRED, &bp)) != 0) {
 		brelse(bp);
@@ -6981,7 +6999,7 @@ trunc_pages(ip, length, extblocks, flags)
 	off_t end, extend;
 
 	vp = ITOV(ip);
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	extend = OFF_TO_IDX(lblktosize(fs, -extblocks));
 	if ((flags & IO_EXT) != 0)
 		vn_pages_remove(vp, extend, 0);
@@ -7517,7 +7535,7 @@ softdep_freefile(pvp, ino, mode)
 	struct freeblks *freeblks;
 	struct ufsmount *ump;
 
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
 	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ump)) != 0,
 	    ("softdep_freefile called on non-softdep filesystem"));
 	/*
@@ -7528,10 +7546,10 @@ softdep_freefile(pvp, ino, mode)
 	workitem_alloc(&freefile->fx_list, D_FREEFILE, pvp->v_mount);
 	freefile->fx_mode = mode;
 	freefile->fx_oldinum = ino;
-	freefile->fx_devvp = ip->i_devvp;
+	freefile->fx_devvp = ump->um_devvp;
 	LIST_INIT(&freefile->fx_jwork);
 	UFS_LOCK(ump);
-	ip->i_fs->fs_pendinginodes += 1;
+	ump->um_fs->fs_pendinginodes += 1;
 	UFS_UNLOCK(ump);
 
 	/*
@@ -8451,8 +8469,8 @@ softdep_setup_directory_add(bp, dp, diroffset, newinum, newdirbp, isnewblk)
 	struct mount *mp;
 	int isindir;
 
-	ump = dp->i_ump;
-	mp = UFSTOVFS(ump);
+	mp = ITOVFS(dp);
+	ump = VFSTOUFS(mp);
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	    ("softdep_setup_directory_add called on non-softdep filesystem"));
 	/*
@@ -8465,7 +8483,7 @@ softdep_setup_directory_add(bp, dp, diroffset, newinum, newdirbp, isnewblk)
 	}
 	jaddref = NULL;
 	mkdir1 = mkdir2 = NULL;
-	fs = dp->i_fs;
+	fs = ump->um_fs;
 	lbn = lblkno(fs, diroffset);
 	offset = blkoff(fs, diroffset);
 	dap = malloc(sizeof(struct diradd), M_DIRADD,
@@ -8618,10 +8636,12 @@ softdep_change_directoryentry_offset(bp, dp, base, oldloc, newloc, entrysize)
 	struct diradd *dap;
 	struct direct *de;
 	struct mount *mp;
+	struct ufsmount *ump;
 	ufs_lbn_t lbn;
 	int flags;
 
-	mp = UFSTOVFS(dp->i_ump);
+	mp = ITOVFS(dp);
+	ump = VFSTOUFS(mp);
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	    ("softdep_change_directoryentry_offset called on "
 	     "non-softdep filesystem"));
@@ -8639,11 +8659,11 @@ softdep_change_directoryentry_offset(bp, dp, base, oldloc, newloc, entrysize)
 		    dp->i_offset + (oldloc - base),
 		    dp->i_offset + (newloc - base));
 	}
-	lbn = lblkno(dp->i_fs, dp->i_offset);
-	offset = blkoff(dp->i_fs, dp->i_offset);
+	lbn = lblkno(ump->um_fs, dp->i_offset);
+	offset = blkoff(ump->um_fs, dp->i_offset);
 	oldoffset = offset + (oldloc - base);
 	newoffset = offset + (newloc - base);
-	ACQUIRE_LOCK(dp->i_ump);
+	ACQUIRE_LOCK(ump);
 	if (pagedep_lookup(mp, bp, dp->i_number, lbn, flags, &pagedep) == 0)
 		goto done;
 	dap = diradd_lookup(pagedep, oldoffset);
@@ -8665,7 +8685,7 @@ done:
 		add_to_journal(&jmvref->jm_list);
 	}
 	bcopy(oldloc, newloc, entrysize);
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ump);
 }
 
 /*
@@ -8908,9 +8928,11 @@ softdep_setup_remove(bp, dp, ip, isrmdir)
 {
 	struct dirrem *dirrem, *prevdirrem;
 	struct inodedep *inodedep;
+	struct ufsmount *ump;
 	int direct;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ip->i_ump)) != 0,
+	ump = ITOUMP(ip);
+	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ump)) != 0,
 	    ("softdep_setup_remove called on non-softdep filesystem"));
 	/*
 	 * Allocate a new dirrem if appropriate and ACQUIRE_LOCK.  We want
@@ -8922,8 +8944,7 @@ softdep_setup_remove(bp, dp, ip, isrmdir)
 	 * Add the dirrem to the inodedep's pending remove list for quick
 	 * discovery later.
 	 */
-	if (inodedep_lookup(UFSTOVFS(ip->i_ump), ip->i_number, 0,
-	    &inodedep) == 0)
+	if (inodedep_lookup(UFSTOVFS(ump), ip->i_number, 0, &inodedep) == 0)
 		panic("softdep_setup_remove: Lost inodedep.");
 	KASSERT((inodedep->id_state & UNLINKED) == 0, ("inode unlinked"));
 	dirrem->dm_state |= ONDEPLIST;
@@ -8943,14 +8964,14 @@ softdep_setup_remove(bp, dp, ip, isrmdir)
 	if ((dirrem->dm_state & COMPLETE) == 0) {
 		LIST_INSERT_HEAD(&dirrem->dm_pagedep->pd_dirremhd, dirrem,
 		    dm_next);
-		FREE_LOCK(ip->i_ump);
+		FREE_LOCK(ump);
 	} else {
 		if (prevdirrem != NULL)
 			LIST_INSERT_HEAD(&dirrem->dm_pagedep->pd_dirremhd,
 			    prevdirrem, dm_next);
 		dirrem->dm_dirinum = dirrem->dm_pagedep->pd_ino;
 		direct = LIST_EMPTY(&dirrem->dm_jremrefhd);
-		FREE_LOCK(ip->i_ump);
+		FREE_LOCK(ump);
 		if (direct)
 			handle_workitem_remove(dirrem, 0);
 	}
@@ -8992,8 +9013,7 @@ cancel_diradd_dotdot(ip, dirrem, jremref)
 	struct diradd *dap;
 	struct worklist *wk;
 
-	if (pagedep_lookup(UFSTOVFS(ip->i_ump), NULL, ip->i_number, 0, 0,
-	    &pagedep) == 0)
+	if (pagedep_lookup(ITOVFS(ip), NULL, ip->i_number, 0, 0, &pagedep) == 0)
 		return (jremref);
 	dap = diradd_lookup(pagedep, DOTDOT_OFFSET);
 	if (dap == NULL)
@@ -9025,9 +9045,10 @@ cancel_mkdir_dotdot(ip, dirrem, jremref)
 	struct ufsmount *ump;
 	struct mkdir *mkdir;
 	struct diradd *dap;
+	struct mount *mp;
 
-	if (inodedep_lookup(UFSTOVFS(ip->i_ump), ip->i_number, 0,
-	    &inodedep) == 0)
+	mp = ITOVFS(ip);
+	if (inodedep_lookup(mp, ip->i_number, 0, &inodedep) == 0)
 		return (jremref);
 	dap = inodedep->id_mkdiradd;
 	if (dap == NULL || (dap->da_state & MKDIR_PARENT) == 0)
@@ -9042,8 +9063,7 @@ cancel_mkdir_dotdot(ip, dirrem, jremref)
 	if ((jaddref = mkdir->md_jaddref) != NULL) {
 		mkdir->md_jaddref = NULL;
 		jaddref->ja_state &= ~MKDIR_PARENT;
-		if (inodedep_lookup(UFSTOVFS(ip->i_ump), jaddref->ja_ino, 0,
-		    &inodedep) == 0)
+		if (inodedep_lookup(mp, jaddref->ja_ino, 0, &inodedep) == 0)
 			panic("cancel_mkdir_dotdot: Lost parent inodedep");
 		if (cancel_jaddref(jaddref, inodedep, &dirrem->dm_jwork)) {
 			journal_jremref(dirrem, jremref, inodedep);
@@ -9114,6 +9134,7 @@ newdirrem(bp, dp, ip, isrmdir, prevdirremp)
 	struct jremref *dotremref;
 	struct jremref *dotdotremref;
 	struct vnode *dvp;
+	struct ufsmount *ump;
 
 	/*
 	 * Whiteouts have no deletion dependencies.
@@ -9121,6 +9142,8 @@ newdirrem(bp, dp, ip, isrmdir, prevdirremp)
 	if (ip == NULL)
 		panic("newdirrem: whiteout");
 	dvp = ITOV(dp);
+	ump = ITOUMP(dp);
+
 	/*
 	 * If the system is over its limit and our filesystem is
 	 * responsible for more than our share of that usage and
@@ -9128,11 +9151,11 @@ newdirrem(bp, dp, ip, isrmdir, prevdirremp)
 	 * Limiting the number of dirrem structures will also limit
 	 * the number of freefile and freeblks structures.
 	 */
-	ACQUIRE_LOCK(ip->i_ump);
-	if (!IS_SNAPSHOT(ip) && softdep_excess_items(ip->i_ump, D_DIRREM))
-		schedule_cleanup(ITOV(dp)->v_mount);
+	ACQUIRE_LOCK(ump);
+	if (!IS_SNAPSHOT(ip) && softdep_excess_items(ump, D_DIRREM))
+		schedule_cleanup(UFSTOVFS(ump));
 	else
-		FREE_LOCK(ip->i_ump);
+		FREE_LOCK(ump);
 	dirrem = malloc(sizeof(struct dirrem), M_DIRREM, M_SOFTDEP_FLAGS |
 	    M_ZERO);
 	workitem_alloc(&dirrem->dm_list, D_DIRREM, dvp->v_mount);
@@ -9162,10 +9185,10 @@ newdirrem(bp, dp, ip, isrmdir, prevdirremp)
 			jremref = newjremref(dirrem, dp, ip, dp->i_offset,
 			    ip->i_effnlink + 1);
 	}
-	ACQUIRE_LOCK(ip->i_ump);
-	lbn = lblkno(dp->i_fs, dp->i_offset);
-	offset = blkoff(dp->i_fs, dp->i_offset);
-	pagedep_lookup(UFSTOVFS(dp->i_ump), bp, dp->i_number, lbn, DEPALLOC,
+	ACQUIRE_LOCK(ump);
+	lbn = lblkno(ump->um_fs, dp->i_offset);
+	offset = blkoff(ump->um_fs, dp->i_offset);
+	pagedep_lookup(UFSTOVFS(ump), bp, dp->i_number, lbn, DEPALLOC,
 	    &pagedep);
 	dirrem->dm_pagedep = pagedep;
 	dirrem->dm_offset = offset;
@@ -9272,9 +9295,11 @@ softdep_setup_directory_change(bp, dp, ip, newinum, isrmdir)
 	struct inodedep *inodedep;
 	struct jaddref *jaddref;
 	struct mount *mp;
+	struct ufsmount *ump;
 
-	offset = blkoff(dp->i_fs, dp->i_offset);
-	mp = UFSTOVFS(dp->i_ump);
+	mp = ITOVFS(dp);
+	ump = VFSTOUFS(mp);
+	offset = blkoff(ump->um_fs, dp->i_offset);
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	   ("softdep_setup_directory_change called on non-softdep filesystem"));
 
@@ -9324,7 +9349,7 @@ softdep_setup_directory_change(bp, dp, ip, newinum, isrmdir)
 			if (LIST_EMPTY(&dirrem->dm_jremrefhd))
 				add_to_worklist(&dirrem->dm_list, 0);
 		}
-		FREE_LOCK(dp->i_ump);
+		FREE_LOCK(ump);
 		return;
 	}
 	/*
@@ -9398,7 +9423,7 @@ softdep_setup_directory_change(bp, dp, ip, newinum, isrmdir)
 	 */
 	if (inodedep->id_mkdiradd && dp->i_offset != DOTDOT_OFFSET)
 		merge_diradd(inodedep, dap);
-	FREE_LOCK(dp->i_ump);
+	FREE_LOCK(ump);
 }
 
 /*
@@ -9412,16 +9437,17 @@ softdep_change_linkcnt(ip)
 	struct inode *ip;	/* the inode with the increased link count */
 {
 	struct inodedep *inodedep;
+	struct ufsmount *ump;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ip->i_ump)) != 0,
+	ump = ITOUMP(ip);
+	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ump)) != 0,
 	    ("softdep_change_linkcnt called on non-softdep filesystem"));
-	ACQUIRE_LOCK(ip->i_ump);
-	inodedep_lookup(UFSTOVFS(ip->i_ump), ip->i_number, DEPALLOC,
-	    &inodedep);
+	ACQUIRE_LOCK(ump);
+	inodedep_lookup(UFSTOVFS(ump), ip->i_number, DEPALLOC, &inodedep);
 	if (ip->i_nlink < ip->i_effnlink)
 		panic("softdep_change_linkcnt: bad delta");
 	inodedep->id_nlinkdelta = ip->i_nlink - ip->i_effnlink;
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(ump);
 }
 
 /*
@@ -12116,21 +12142,22 @@ softdep_load_inodeblock(ip)
 	struct inode *ip;	/* the "in_core" copy of the inode */
 {
 	struct inodedep *inodedep;
+	struct ufsmount *ump;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ip->i_ump)) != 0,
+	ump = ITOUMP(ip);
+	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ump)) != 0,
 	    ("softdep_load_inodeblock called on non-softdep filesystem"));
 	/*
 	 * Check for alternate nlink count.
 	 */
 	ip->i_effnlink = ip->i_nlink;
-	ACQUIRE_LOCK(ip->i_ump);
-	if (inodedep_lookup(UFSTOVFS(ip->i_ump), ip->i_number, 0,
-	    &inodedep) == 0) {
-		FREE_LOCK(ip->i_ump);
+	ACQUIRE_LOCK(ump);
+	if (inodedep_lookup(UFSTOVFS(ump), ip->i_number, 0, &inodedep) == 0) {
+		FREE_LOCK(ump);
 		return;
 	}
 	ip->i_effnlink -= inodedep->id_nlinkdelta;
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(ump);
 }
 
 /*
@@ -12158,11 +12185,11 @@ softdep_update_inodeblock(ip, bp, waitfor)
 	struct fs *fs;
 	int error;
 
-	ump = ip->i_ump;
+	ump = ITOUMP(ip);
 	mp = UFSTOVFS(ump);
 	KASSERT(MOUNTEDSOFTDEP(mp) != 0,
 	    ("softdep_update_inodeblock called on non-softdep filesystem"));
-	fs = ip->i_fs;
+	fs = ump->um_fs;
 	/*
 	 * Preserve the freelink that is on disk.  clear_unlinked_inodedep()
 	 * does not have access to the in-core ip so must write directly into
@@ -12327,9 +12354,9 @@ softdep_fsync(vp)
 	ufs_lbn_t lbn;
 
 	ip = VTOI(vp);
-	fs = ip->i_fs;
-	ump = ip->i_ump;
 	mp = vp->v_mount;
+	ump = VFSTOUFS(mp);
+	fs = ump->um_fs;
 	if (MOUNTEDSOFTDEP(mp) == 0)
 		return (0);
 	ACQUIRE_LOCK(ump);
@@ -12602,13 +12629,13 @@ softdep_sync_metadata(struct vnode *vp)
 	int error;
 
 	ip = VTOI(vp);
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ip->i_ump)) != 0,
+	KASSERT(MOUNTEDSOFTDEP(vp->v_mount) != 0,
 	    ("softdep_sync_metadata called on non-softdep filesystem"));
 	/*
 	 * Ensure that any direct block dependencies have been cleared,
 	 * truncations are started, and inode references are journaled.
 	 */
-	ACQUIRE_LOCK(ip->i_ump);
+	ACQUIRE_LOCK(VFSTOUFS(vp->v_mount));
 	/*
 	 * Write all journal records to prevent rollbacks on devvp.
 	 */
@@ -12620,7 +12647,7 @@ softdep_sync_metadata(struct vnode *vp)
 	 * indirect blocks.
 	 */
 	process_truncates(vp);
-	FREE_LOCK(ip->i_ump);
+	FREE_LOCK(VFSTOUFS(vp->v_mount));
 
 	return (error);
 }
@@ -12655,7 +12682,7 @@ softdep_sync_buf(struct vnode *vp, struct buf *bp, int waitfor)
 			return (EBUSY);
 		return (0);
 	}
-	ump = VTOI(vp)->i_ump;
+	ump = VFSTOUFS(vp->v_mount);
 	ACQUIRE_LOCK(ump);
 	/*
 	 * As we hold the buffer locked, none of its dependencies
@@ -13776,12 +13803,14 @@ softdep_inode_append(ip, cred, wkhd)
 {
 	struct buf *bp;
 	struct fs *fs;
+	struct ufsmount *ump;
 	int error;
 
-	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ip->i_ump)) != 0,
+	ump = ITOUMP(ip);
+	KASSERT(MOUNTEDSOFTDEP(UFSTOVFS(ump)) != 0,
 	    ("softdep_inode_append called on non-softdep filesystem"));
-	fs = ip->i_fs;
-	error = bread(ip->i_devvp, fsbtodb(fs, ino_to_fsba(fs, ip->i_number)),
+	fs = ump->um_fs;
+	error = bread(ump->um_devvp, fsbtodb(fs, ino_to_fsba(fs, ip->i_number)),
 	    (int)fs->fs_bsize, cred, &bp);
 	if (error) {
 		bqrelse(bp);
diff --git a/sys/ufs/ffs/ffs_subr.c b/sys/ufs/ffs/ffs_subr.c
index 67f7e5ceebc2..cabed2baea16 100644
--- a/sys/ufs/ffs/ffs_subr.c
+++ b/sys/ufs/ffs/ffs_subr.c
@@ -74,7 +74,7 @@ ffs_blkatoff(vp, offset, res, bpp)
 	int bsize, error;
 
 	ip = VTOI(vp);
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	lbn = lblkno(fs, offset);
 	bsize = blksize(fs, ip, lbn);
 
@@ -102,7 +102,7 @@ ffs_load_inode(bp, ip, fs, ino)
 	ino_t ino;
 {
 
-	if (ip->i_ump->um_fstype == UFS1) {
+	if (I_IS_UFS1(ip)) {
 		*ip->i_din1 =
 		    *((struct ufs1_dinode *)bp->b_data + ino_to_fsbo(fs, ino));
 		ip->i_mode = ip->i_din1->di_mode;
diff --git a/sys/ufs/ffs/ffs_vfsops.c b/sys/ufs/ffs/ffs_vfsops.c
index b28b742934b7..d8790d177523 100644
--- a/sys/ufs/ffs/ffs_vfsops.c
+++ b/sys/ufs/ffs/ffs_vfsops.c
@@ -1652,7 +1652,6 @@ ffs_vgetf(mp, ino, flags, vpp, ffs_flags)
 	struct ufsmount *ump;
 	struct buf *bp;
 	struct vnode *vp;
-	struct cdev *dev;
 	int error;
 
 	error = vfs_hash_get(mp, ino, flags, curthread, vpp, NULL, NULL);
@@ -1676,7 +1675,6 @@ ffs_vgetf(mp, ino, flags, vpp, ffs_flags)
 	 */
 
 	ump = VFSTOUFS(mp);
-	dev = ump->um_dev;
 	fs = ump->um_fs;
 	ip = uma_zalloc(uma_inode, M_WAITOK | M_ZERO);
 
@@ -1697,11 +1695,10 @@ ffs_vgetf(mp, ino, flags, vpp, ffs_flags)
 	vp->v_bufobj.bo_bsize = fs->fs_bsize;
 	ip->i_vnode = vp;
 	ip->i_ump = ump;
-	ip->i_fs = fs;
-	ip->i_dev = dev;
 	ip->i_number = ino;
 	ip->i_ea_refs = 0;
 	ip->i_nextclustercg = -1;
+	ip->i_flag = fs->fs_magic == FS_UFS1_MAGIC ? 0 : IN_UFS2;
 #ifdef QUOTA
 	{
 		int i;
@@ -1738,7 +1735,7 @@ ffs_vgetf(mp, ino, flags, vpp, ffs_flags)
 		*vpp = NULL;
 		return (error);
 	}
-	if (ip->i_ump->um_fstype == UFS1)
+	if (I_IS_UFS1(ip))
 		ip->i_din1 = uma_zalloc(uma_ufs1, M_WAITOK);
 	else
 		ip->i_din2 = uma_zalloc(uma_ufs2, M_WAITOK);
@@ -1753,10 +1750,8 @@ ffs_vgetf(mp, ino, flags, vpp, ffs_flags)
 	 * Initialize the vnode from the inode, check for aliases.
 	 * Note that the underlying vnode may have changed.
 	 */
-	if (ip->i_ump->um_fstype == UFS1)
-		error = ufs_vinit(mp, &ffs_fifoops1, &vp);
-	else
-		error = ufs_vinit(mp, &ffs_fifoops2, &vp);
+	error = ufs_vinit(mp, I_IS_UFS1(ip) ? &ffs_fifoops1 : &ffs_fifoops2,
+	    &vp);
 	if (error) {
 		vput(vp);
 		*vpp = NULL;
diff --git a/sys/ufs/ffs/ffs_vnops.c b/sys/ufs/ffs/ffs_vnops.c
index 0ed7c5923986..2af53832d1e9 100644
--- a/sys/ufs/ffs/ffs_vnops.c
+++ b/sys/ufs/ffs/ffs_vnops.c
@@ -244,7 +244,7 @@ ffs_syncvnode(struct vnode *vp, int waitfor, int flags)
 	error = 0;
 	passes = 0;
 	wait = false;	/* Always do an async pass first. */
-	lbn = lblkno(ip->i_fs, (ip->i_size + ip->i_fs->fs_bsize - 1));
+	lbn = lblkno(ITOFS(ip), (ip->i_size + ITOFS(ip)->fs_bsize - 1));
 	BO_LOCK(bo);
 loop:
 	TAILQ_FOREACH(bp, &bo->bo_dirty.bv_hd, b_bobufs)
@@ -518,7 +518,7 @@ ffs_read(ap)
 	if (orig_resid == 0)
 		return (0);
 	KASSERT(uio->uio_offset >= 0, ("ffs_read: uio->uio_offset < 0"));
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	if (uio->uio_offset < ip->i_size &&
 	    uio->uio_offset >= fs->fs_maxfilesize)
 		return (EOVERFLOW);
@@ -741,7 +741,7 @@ ffs_write(ap)
 
 	KASSERT(uio->uio_resid >= 0, ("ffs_write: uio->uio_resid < 0"));
 	KASSERT(uio->uio_offset >= 0, ("ffs_write: uio->uio_offset < 0"));
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	if ((uoff_t)uio->uio_offset + uio->uio_resid > fs->fs_maxfilesize)
 		return (EFBIG);
 	/*
@@ -905,7 +905,7 @@ ffs_extread(struct vnode *vp, struct uio *uio, int ioflag)
 	int error;
 
 	ip = VTOI(vp);
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	dp = ip->i_din2;
 
 #ifdef INVARIANTS
@@ -1059,7 +1059,7 @@ ffs_extwrite(struct vnode *vp, struct uio *uio, int ioflag, struct ucred *ucred)
 	int blkoffset, error, flags, size, xfersize;
 
 	ip = VTOI(vp);
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	dp = ip->i_din2;
 
 #ifdef INVARIANTS
@@ -1231,7 +1231,7 @@ ffs_rdextattr(u_char **p, struct vnode *vp, struct thread *td, int extra)
 	u_char *eae;
 
 	ip = VTOI(vp);
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 	dp = ip->i_din2;
 	easize = dp->di_extsize;
 	if ((uoff_t)easize + extra > NXADDR * fs->fs_bsize)
@@ -1385,8 +1385,7 @@ struct vop_strategy_args {
 
 	vp = ap->a_vp;
 	lbn = ap->a_bp->b_lblkno;
-	if (VTOI(vp)->i_fs->fs_magic == FS_UFS2_MAGIC &&
-	    lbn < 0 && lbn >= -NXADDR)
+	if (I_IS_UFS2(VTOI(vp)) && lbn < 0 && lbn >= -NXADDR)
 		return (VOP_STRATEGY_APV(&ufs_vnodeops, ap));
 	if (vp->v_type == VFIFO)
 		return (VOP_STRATEGY_APV(&ufs_fifoops, ap));
@@ -1462,7 +1461,7 @@ vop_deleteextattr {
 	u_char *eae, *p;
 
 	ip = VTOI(ap->a_vp);
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 
 	if (ap->a_vp->v_type == VCHR || ap->a_vp->v_type == VBLK)
 		return (EOPNOTSUPP);
@@ -1665,7 +1664,7 @@ vop_setextattr {
 	u_char *eae, *p;
 
 	ip = VTOI(ap->a_vp);
-	fs = ip->i_fs;
+	fs = ITOFS(ip);
 
 	if (ap->a_vp->v_type == VCHR || ap->a_vp->v_type == VBLK)
 		return (EOPNOTSUPP);
diff --git a/sys/ufs/ufs/extattr.h b/sys/ufs/ufs/extattr.h
index 1e5152c28a0e..6b4987cc2b69 100644
--- a/sys/ufs/ufs/extattr.h
+++ b/sys/ufs/ufs/extattr.h
@@ -133,6 +133,10 @@ struct ufs_extattr_per_mount {
 	int	uepm_flags;
 };
 
+struct vop_getextattr_args;
+struct vop_deleteextattr_args;
+struct vop_setextattr_args;
+
 void	ufs_extattr_uepm_init(struct ufs_extattr_per_mount *uepm);
 void	ufs_extattr_uepm_destroy(struct ufs_extattr_per_mount *uepm);
 int	ufs_extattr_start(struct mount *mp, struct thread *td);
diff --git a/sys/ufs/ufs/inode.h b/sys/ufs/ufs/inode.h
index cd7c47261534..e44cae59ee45 100644
--- a/sys/ufs/ufs/inode.h
+++ b/sys/ufs/ufs/inode.h
@@ -66,14 +66,25 @@
 struct inode {
 	TAILQ_ENTRY(inode) i_nextsnap; /* snapshot file list. */
 	struct	vnode  *i_vnode;/* Vnode associated with this inode. */
-	struct	ufsmount *i_ump;/* Ufsmount point associated with this inode. */
-	u_int32_t i_flag;	/* flags, see below */
-	struct cdev *i_dev;	/* Device associated with the inode. */
+	struct 	ufsmount *i_ump;/* Ufsmount point associated with this inode. */
+	struct	 dquot *i_dquot[MAXQUOTAS]; /* Dquot structures. */
+	union {
+		struct dirhash *dirhash; /* Hashing for large directories. */
+		daddr_t *snapblklist;    /* Collect expunged snapshot blocks. */
+	} i_un;
+	/*
+	 * The real copy of the on-disk inode.
+	 */
+	union {
+		struct ufs1_dinode *din1;	/* UFS1 on-disk dinode. */
+		struct ufs2_dinode *din2;	/* UFS2 on-disk dinode. */
+	} dinode_u;
+
 	ino_t	  i_number;	/* The identity of the inode. */
+	u_int32_t i_flag;	/* flags, see below */
 	int	  i_effnlink;	/* i_nlink when I/O completes */
 
-	struct	 fs *i_fs;	/* Associated filesystem superblock. */
-	struct	 dquot *i_dquot[MAXQUOTAS]; /* Dquot structures. */
+
 	/*
 	 * Side effects; used during directory lookup.
 	 */
@@ -82,11 +93,6 @@ struct inode {
 	doff_t	  i_diroff;	/* Offset in dir, where we found last entry. */
 	doff_t	  i_offset;	/* Offset of free space in directory. */
 
-	union {
-		struct dirhash *dirhash; /* Hashing for large directories. */
-		daddr_t *snapblklist;    /* Collect expunged snapshot blocks. */
-	} i_un;
-
 	int	i_nextclustercg; /* last cg searched for cluster */
 
 	/*
@@ -100,20 +106,13 @@ struct inode {
 	/*
 	 * Copies from the on-disk dinode itself.
 	 */
-	u_int16_t i_mode;	/* IFMT, permissions; see below. */
-	int16_t	  i_nlink;	/* File link count. */
 	u_int64_t i_size;	/* File byte count. */
-	u_int32_t i_flags;	/* Status flags (chflags). */
 	u_int64_t i_gen;	/* Generation number. */
+	u_int32_t i_flags;	/* Status flags (chflags). */
 	u_int32_t i_uid;	/* File owner. */
 	u_int32_t i_gid;	/* File group. */
-	/*
-	 * The real copy of the on-disk inode.
-	 */
-	union {
-		struct ufs1_dinode *din1;	/* UFS1 on-disk dinode. */
-		struct ufs2_dinode *din2;	/* UFS2 on-disk dinode. */
-	} dinode_u;
+	u_int16_t i_mode;	/* IFMT, permissions; see below. */
+	int16_t	  i_nlink;	/* File link count. */
 };
 /*
  * These flags are kept in i_flag.
@@ -123,39 +122,58 @@ struct inode {
 #define	IN_UPDATE	0x0004		/* Modification time update request. */
 #define	IN_MODIFIED	0x0008		/* Inode has been modified. */
 #define	IN_NEEDSYNC	0x0010		/* Inode requires fsync. */
-#define	IN_LAZYMOD	0x0040		/* Modified, but don't write yet. */
-#define	IN_LAZYACCESS	0x0100		/* Process IN_ACCESS after the
+#define	IN_LAZYMOD	0x0020		/* Modified, but don't write yet. */
+#define	IN_LAZYACCESS	0x0040		/* Process IN_ACCESS after the
 					   suspension finished */
-#define	IN_EA_LOCKED	0x0200
-#define	IN_EA_LOCKWAIT	0x0400
+#define	IN_EA_LOCKED	0x0080
+#define	IN_EA_LOCKWAIT	0x0100
 
-#define	IN_TRUNCATED	0x0800		/* Journaled truncation pending. */
+#define	IN_TRUNCATED	0x0200		/* Journaled truncation pending. */
+
+#define	IN_UFS2		0x0400		/* UFS2 vs UFS1 */
 
-#define	i_devvp i_ump->um_devvp
-#define	i_umbufobj i_ump->um_bo
 #define	i_dirhash i_un.dirhash
 #define	i_snapblklist i_un.snapblklist
 #define	i_din1 dinode_u.din1
 #define	i_din2 dinode_u.din2
 
 #ifdef _KERNEL
+
+#define	ITOUMP(ip)	((ip)->i_ump)
+#define	ITODEV(ip)	(ITOUMP(ip)->um_dev)
+#define	ITODEVVP(ip)	(ITOUMP(ip)->um_devvp)
+#define	ITOFS(ip)	(ITOUMP(ip)->um_fs)
+#define	ITOVFS(ip)	((ip)->i_vnode->v_mount)
+
+static inline _Bool
+I_IS_UFS1(const struct inode *ip)
+{
+
+	return ((ip->i_flag & IN_UFS2) == 0);
+}
+
+static inline _Bool
+I_IS_UFS2(const struct inode *ip)
+{
+
+	return ((ip->i_flag & IN_UFS2) != 0);
+}
+
 /*
  * The DIP macro is used to access fields in the dinode that are
  * not cached in the inode itself.
  */
-#define	DIP(ip, field) \
-	(((ip)->i_ump->um_fstype == UFS1) ? \
-	(ip)->i_din1->d##field : (ip)->i_din2->d##field)
-#define	DIP_SET(ip, field, val) do { \
-	if ((ip)->i_ump->um_fstype == UFS1) \
-		(ip)->i_din1->d##field = (val); \
-	else \
-		(ip)->i_din2->d##field = (val); \
+#define	DIP(ip, field)	(I_IS_UFS1(ip) ? (ip)->i_din1->d##field : \
+    (ip)->i_din2->d##field)
+#define	DIP_SET(ip, field, val) do {				\
+	if (I_IS_UFS1(ip))					\
+		(ip)->i_din1->d##field = (val); 		\
+	else							\
+		(ip)->i_din2->d##field = (val); 		\
 	} while (0)
 
-#define	SHORTLINK(ip) \
-	(((ip)->i_ump->um_fstype == UFS1) ? \
-	(caddr_t)(ip)->i_din1->di_db : (caddr_t)(ip)->i_din2->di_db)
+#define	SHORTLINK(ip)	(I_IS_UFS1(ip) ?			\
+    (caddr_t)(ip)->i_din1->di_db : (caddr_t)(ip)->i_din2->di_db)
 #define	IS_SNAPSHOT(ip)		((ip)->i_flags & SF_SNAPSHOT)
 
 /*
diff --git a/sys/ufs/ufs/ufs_acl.c b/sys/ufs/ufs/ufs_acl.c
index 836b2c08a869..86f4270248e0 100644
--- a/sys/ufs/ufs/ufs_acl.c
+++ b/sys/ufs/ufs/ufs_acl.c
@@ -184,7 +184,7 @@ ufs_getacl_nfs4_internal(struct vnode *vp, struct acl *aclp, struct thread *td)
 		 */
 		printf("ufs_getacl_nfs4(): Loaded invalid ACL ("
 		    "%d bytes), inumber %ju on %s\n", len,
-		    (uintmax_t)ip->i_number, ip->i_fs->fs_fsmnt);
+		    (uintmax_t)ip->i_number, ITOFS(ip)->fs_fsmnt);
 
 		return (EPERM);
 	}
@@ -193,7 +193,7 @@ ufs_getacl_nfs4_internal(struct vnode *vp, struct acl *aclp, struct thread *td)
 	if (error) {
 		printf("ufs_getacl_nfs4(): Loaded invalid ACL "
 		    "(failed acl_nfs4_check), inumber %ju on %s\n",
-		    (uintmax_t)ip->i_number, ip->i_fs->fs_fsmnt);
+		    (uintmax_t)ip->i_number, ITOFS(ip)->fs_fsmnt);
 
 		return (EPERM);
 	}
@@ -261,7 +261,7 @@ ufs_get_oldacl(acl_type_t type, struct oldacl *old, struct vnode *vp,
 		 */
 		printf("ufs_get_oldacl(): Loaded invalid ACL "
 		    "(len = %d), inumber %ju on %s\n", len,
-		    (uintmax_t)ip->i_number, ip->i_fs->fs_fsmnt);
+		    (uintmax_t)ip->i_number, ITOFS(ip)->fs_fsmnt);
 		return (EPERM);
 	}
 
diff --git a/sys/ufs/ufs/ufs_bmap.c b/sys/ufs/ufs/ufs_bmap.c
index 768298f61a5a..f6a774a89fc4 100644
--- a/sys/ufs/ufs/ufs_bmap.c
+++ b/sys/ufs/ufs/ufs_bmap.c
@@ -78,7 +78,7 @@ ufs_bmap(ap)
 	 * to physical mapping is requested.
 	 */
 	if (ap->a_bop != NULL)
-		*ap->a_bop = &VTOI(ap->a_vp)->i_devvp->v_bufobj;
+		*ap->a_bop = &VFSTOUFS(ap->a_vp->v_mount)->um_devvp->v_bufobj;
 	if (ap->a_bnp == NULL)
 		return (0);
 
@@ -239,7 +239,7 @@ ufs_bmaparray(vp, bn, bnp, nbp, runp, runb)
 			}
 		}
 
-		if (ip->i_ump->um_fstype == UFS1) {
+		if (I_IS_UFS1(ip)) {
 			daddr = ((ufs1_daddr_t *)bp->b_data)[ap->in_off];
 			if (num == 1 && daddr && runp) {
 				for (bn = ap->in_off + 1;
diff --git a/sys/ufs/ufs/ufs_gjournal.c b/sys/ufs/ufs/ufs_gjournal.c
index 4d6fb0ebdc6e..807393dcb44f 100644
--- a/sys/ufs/ufs/ufs_gjournal.c
+++ b/sys/ufs/ufs/ufs_gjournal.c
@@ -65,20 +65,23 @@ ufs_gjournal_modref(struct vnode *vp, int count)
 	ino_t ino;
 
 	ip = VTOI(vp);
-	ump = ip->i_ump;
-	fs = ip->i_fs;
-	devvp = ip->i_devvp;
+	ump = VFSTOUFS(vp->v_mount);
+	fs = ump->um_fs;
+	devvp = ump->um_devvp;
 	ino = ip->i_number;
 
 	cg = ino_to_cg(fs, ino);
-	if (devvp->v_type != VCHR) {
+	if (devvp->v_type == VREG) {
 		/* devvp is a snapshot */
-		dev = VTOI(devvp)->i_devvp->v_rdev;
+		dev = VFSTOUFS(devvp->v_mount)->um_devvp->v_rdev;
 		cgbno = fragstoblks(fs, cgtod(fs, cg));
-	} else {
+	} else if (devvp->v_type == VCHR) {
 		/* devvp is a normal disk device */
 		dev = devvp->v_rdev;
 		cgbno = fsbtodb(fs, cgtod(fs, cg));
+	} else {
+		bp = NULL;
+		return (EIO);
 	}
 	if ((u_int)ino >= fs->fs_ipg * fs->fs_ncg)
 		panic("ufs_gjournal_modref: range: dev = %s, ino = %lu, fs = %s",
diff --git a/sys/ufs/ufs/ufs_inode.c b/sys/ufs/ufs/ufs_inode.c
index e2825b5a74d9..aeaa7c83267d 100644
--- a/sys/ufs/ufs/ufs_inode.c
+++ b/sys/ufs/ufs/ufs_inode.c
@@ -125,7 +125,7 @@ ufs_inactive(ap)
 		}
 	}
 	isize = ip->i_size;
-	if (ip->i_ump->um_fstype == UFS2)
+	if (I_IS_UFS2(ip))
 		isize += ip->i_din2->di_extsize;
 	if (ip->i_effnlink <= 0 && isize && !UFS_RDONLY(ip))
 		error = UFS_TRUNCATE(vp, (off_t)0, IO_EXT | IO_NORMAL, NOCRED);
@@ -214,7 +214,6 @@ ufs_reclaim(ap)
 {
 	struct vnode *vp = ap->a_vp;
 	struct inode *ip = VTOI(vp);
-	struct ufsmount *ump = ip->i_ump;
 
 	ufs_prepare_reclaim(vp);
 
@@ -233,6 +232,6 @@ ufs_reclaim(ap)
 	VI_LOCK(vp);
 	vp->v_data = 0;
 	VI_UNLOCK(vp);
-	UFS_IFREE(ump, ip);
+	UFS_IFREE(ITOUMP(ip), ip);
 	return (0);
 }
diff --git a/sys/ufs/ufs/ufs_quota.c b/sys/ufs/ufs/ufs_quota.c
index ccc496203ace..fe8a283c6661 100644
--- a/sys/ufs/ufs/ufs_quota.c
+++ b/sys/ufs/ufs/ufs_quota.c
@@ -232,13 +232,13 @@ chkdq(struct inode *ip, ufs2_daddr_t change, struct ucred *cred, int flags)
 		/* Reset timer when crossing soft limit */
 		if (dq->dq_curblocks + change >= dq->dq_bsoftlimit &&
 		    dq->dq_curblocks < dq->dq_bsoftlimit)
-			dq->dq_btime = time_second + ip->i_ump->um_btime[i];
+			dq->dq_btime = time_second + ITOUMP(ip)->um_btime[i];
 		dq->dq_curblocks += change;
 		dq->dq_flags |= DQ_MOD;
 		DQI_UNLOCK(dq);
 		if (warn)
 			uprintf("\n%s: warning, %s disk quota exceeded\n",
-			    ITOV(ip)->v_mount->mnt_stat.f_mntonname,
+			    ITOVFS(ip)->mnt_stat.f_mntonname,
 			    quotatypes[i]);
 	}
 	return (0);
@@ -264,7 +264,7 @@ chkdqchg(struct inode *ip, ufs2_daddr_t change, struct ucred *cred,
 			dq->dq_flags |= DQ_BLKS;
 			DQI_UNLOCK(dq);
 			uprintf("\n%s: write failed, %s disk limit reached\n",
-			    ITOV(ip)->v_mount->mnt_stat.f_mntonname,
+			    ITOVFS(ip)->mnt_stat.f_mntonname,
 			    quotatypes[type]);
 			return (EDQUOT);
 		}
@@ -277,7 +277,7 @@ chkdqchg(struct inode *ip, ufs2_daddr_t change, struct ucred *cred,
 	 */
 	if (ncurblocks >= dq->dq_bsoftlimit && dq->dq_bsoftlimit) {
 		if (dq->dq_curblocks < dq->dq_bsoftlimit) {
-			dq->dq_btime = time_second + ip->i_ump->um_btime[type];
+			dq->dq_btime = time_second + ITOUMP(ip)->um_btime[type];
 			if (ip->i_uid == cred->cr_uid)
 				*warn = 1;
 			return (0);
@@ -289,7 +289,7 @@ chkdqchg(struct inode *ip, ufs2_daddr_t change, struct ucred *cred,
 				DQI_UNLOCK(dq);
 				uprintf("\n%s: write failed, %s "
 				    "disk quota exceeded for too long\n",
-				    ITOV(ip)->v_mount->mnt_stat.f_mntonname,
+				    ITOVFS(ip)->mnt_stat.f_mntonname,
 				    quotatypes[type]);
 				return (EDQUOT);
 			}
@@ -370,13 +370,13 @@ chkiq(struct inode *ip, int change, struct ucred *cred, int flags)
 		/* Reset timer when crossing soft limit */
 		if (dq->dq_curinodes + change >= dq->dq_isoftlimit &&
 		    dq->dq_curinodes < dq->dq_isoftlimit)
-			dq->dq_itime = time_second + ip->i_ump->um_itime[i];
+			dq->dq_itime = time_second + ITOUMP(ip)->um_itime[i];
 		dq->dq_curinodes += change;
 		dq->dq_flags |= DQ_MOD;
 		DQI_UNLOCK(dq);
 		if (warn)
 			uprintf("\n%s: warning, %s inode quota exceeded\n",
-			    ITOV(ip)->v_mount->mnt_stat.f_mntonname,
+			    ITOVFS(ip)->mnt_stat.f_mntonname,
 			    quotatypes[i]);
 	}
 	return (0);
@@ -401,7 +401,7 @@ chkiqchg(struct inode *ip, int change, struct ucred *cred, int type, int *warn)
 			dq->dq_flags |= DQ_INODS;
 			DQI_UNLOCK(dq);
 			uprintf("\n%s: write failed, %s inode limit reached\n",
-			    ITOV(ip)->v_mount->mnt_stat.f_mntonname,
+			    ITOVFS(ip)->mnt_stat.f_mntonname,
 			    quotatypes[type]);
 			return (EDQUOT);
 		}
@@ -414,7 +414,7 @@ chkiqchg(struct inode *ip, int change, struct ucred *cred, int type, int *warn)
 	 */
 	if (ncurinodes >= dq->dq_isoftlimit && dq->dq_isoftlimit) {
 		if (dq->dq_curinodes < dq->dq_isoftlimit) {
-			dq->dq_itime = time_second + ip->i_ump->um_itime[type];
+			dq->dq_itime = time_second + ITOUMP(ip)->um_itime[type];
 			if (ip->i_uid == cred->cr_uid)
 				*warn = 1;
 			return (0);
@@ -426,7 +426,7 @@ chkiqchg(struct inode *ip, int change, struct ucred *cred, int type, int *warn)
 				DQI_UNLOCK(dq);
 				uprintf("\n%s: write failed, %s "
 				    "inode quota exceeded for too long\n",
-				    ITOV(ip)->v_mount->mnt_stat.f_mntonname,
+				    ITOVFS(ip)->mnt_stat.f_mntonname,
 				    quotatypes[type]);
 				return (EDQUOT);
 			}
@@ -445,10 +445,13 @@ chkiqchg(struct inode *ip, int change, struct ucred *cred, int type, int *warn)
 static void
 chkdquot(struct inode *ip)
 {
-	struct ufsmount *ump = ip->i_ump;
-	struct vnode *vp = ITOV(ip);
+	struct ufsmount *ump;
+	struct vnode *vp;
 	int i;
 
+	ump = ITOUMP(ip);
+	vp = ITOV(ip);
+
 	/*
 	 * Disk quotas must be turned off for system files.  Currently
 	 * these are snapshots and quota files.
diff --git a/sys/ufs/ufs/ufs_vnops.c b/sys/ufs/ufs/ufs_vnops.c
index 46e5b24a36f0..b6e3385b81c3 100644
--- a/sys/ufs/ufs/ufs_vnops.c
+++ b/sys/ufs/ufs/ufs_vnops.c
@@ -456,7 +456,7 @@ ufs_getattr(ap)
 
 	VI_LOCK(vp);
 	ufs_itimes_locked(vp);
-	if (ip->i_ump->um_fstype == UFS1) {
+	if (I_IS_UFS1(ip)) {
 		vap->va_atime.tv_sec = ip->i_din1->di_atime;
 		vap->va_atime.tv_nsec = ip->i_din1->di_atimensec;
 	} else {
@@ -467,13 +467,13 @@ ufs_getattr(ap)
 	/*
 	 * Copy from inode table
 	 */
-	vap->va_fsid = dev2udev(ip->i_dev);
+	vap->va_fsid = dev2udev(ITOUMP(ip)->um_dev);
 	vap->va_fileid = ip->i_number;
 	vap->va_mode = ip->i_mode & ~IFMT;
 	vap->va_nlink = ip->i_effnlink;
 	vap->va_uid = ip->i_uid;
 	vap->va_gid = ip->i_gid;
-	if (ip->i_ump->um_fstype == UFS1) {
+	if (I_IS_UFS1(ip)) {
 		vap->va_rdev = ip->i_din1->di_rdev;
 		vap->va_size = ip->i_din1->di_size;
 		vap->va_mtime.tv_sec = ip->i_din1->di_mtime;
@@ -651,8 +651,7 @@ ufs_setattr(ap)
 			DIP_SET(ip, i_mtime, vap->va_mtime.tv_sec);
 			DIP_SET(ip, i_mtimensec, vap->va_mtime.tv_nsec);
 		}
-		if (vap->va_birthtime.tv_sec != VNOVAL &&
-		    ip->i_ump->um_fstype == UFS2) {
+		if (vap->va_birthtime.tv_sec != VNOVAL && I_IS_UFS2(ip)) {
 			ip->i_din2->di_birthtime = vap->va_birthtime.tv_sec;
 			ip->i_din2->di_birthnsec = vap->va_birthtime.tv_nsec;
 		}
@@ -1347,7 +1346,7 @@ relock:
 	 *    expunge the original entry's existence.
 	 */
 	if (tip == NULL) {
-		if (tdp->i_dev != fip->i_dev)
+		if (ITODEV(tdp) != ITODEV(fip))
 			panic("ufs_rename: EXDEV");
 		if (doingdirectory && newparent) {
 			/*
@@ -1371,7 +1370,7 @@ relock:
 		    tdp->i_endoff < tdp->i_size)
 			endoff = tdp->i_endoff;
 	} else {
-		if (tip->i_dev != tdp->i_dev || tip->i_dev != fip->i_dev)
+		if (ITODEV(tip) != ITODEV(tdp) || ITODEV(tip) != ITODEV(fip))
 			panic("ufs_rename: EXDEV");
 		/*
 		 * Short circuit rename(foo, foo).
@@ -2301,12 +2300,9 @@ ufs_strategy(ap)
 {
 	struct buf *bp = ap->a_bp;
 	struct vnode *vp = ap->a_vp;
-	struct bufobj *bo;
-	struct inode *ip;
 	ufs2_daddr_t blkno;
 	int error;
 
-	ip = VTOI(vp);
 	if (bp->b_blkno == bp->b_lblkno) {
 		error = ufs_bmaparray(vp, bp->b_lblkno, &blkno, bp, NULL, NULL);
 		bp->b_blkno = blkno;
@@ -2324,8 +2320,7 @@ ufs_strategy(ap)
 		return (0);
 	}
 	bp->b_iooffset = dbtob(bp->b_blkno);
-	bo = ip->i_umbufobj;
-	BO_STRATEGY(bo, bp);
+	BO_STRATEGY(VFSTOUFS(vp->v_mount)->um_bo, bp);
 	return (0);
 }
 
@@ -2342,7 +2337,7 @@ ufs_print(ap)
 	struct inode *ip = VTOI(vp);
 
 	printf("\tino %lu, on dev %s", (u_long)ip->i_number,
-	    devtoname(ip->i_dev));
+	    devtoname(ITODEV(ip)));
 	if (vp->v_type == VFIFO)
 		fifo_printinfo(vp);
 	printf("\n");
diff --git a/sys/ufs/ufs/ufsmount.h b/sys/ufs/ufs/ufsmount.h
index 838c1e3b53f8..e0212e0159f3 100644
--- a/sys/ufs/ufs/ufsmount.h
+++ b/sys/ufs/ufs/ufsmount.h
@@ -108,8 +108,8 @@ struct ufsmount {
 #define	UFS_VALLOC(aa, bb, cc, dd) VFSTOUFS((aa)->v_mount)->um_valloc(aa, bb, cc, dd)
 #define	UFS_VFREE(aa, bb, cc) VFSTOUFS((aa)->v_mount)->um_vfree(aa, bb, cc)
 #define	UFS_IFREE(aa, bb) ((aa)->um_ifree(aa, bb))
-#define	UFS_RDONLY(aa) ((aa)->i_ump->um_rdonly(aa))
-#define	UFS_SNAPGONE(aa) ((aa)->i_ump->um_snapgone(aa))
+#define	UFS_RDONLY(aa) (ITOUMP(aa)->um_rdonly(aa))
+#define	UFS_SNAPGONE(aa) (ITOUMP(aa)->um_snapgone(aa))
 
 #define	UFS_LOCK(aa)	mtx_lock(&(aa)->um_lock)
 #define	UFS_UNLOCK(aa)	mtx_unlock(&(aa)->um_lock)
diff --git a/sys/x86/acpica/madt.c b/sys/x86/acpica/madt.c
index 241a7696f8a5..e884c867bf3f 100644
--- a/sys/x86/acpica/madt.c
+++ b/sys/x86/acpica/madt.c
@@ -135,10 +135,11 @@ madt_setup_local(void)
 	const char *reason;
 	char *hw_vendor;
 	u_int p[4];
+	int user_x2apic;
+	bool bios_x2apic;
 
 	madt = pmap_mapbios(madt_physaddr, madt_length);
 	if ((cpu_feature2 & CPUID2_X2APIC) != 0) {
-		x2apic_mode = 1;
 		reason = NULL;
 
 		/*
@@ -150,21 +151,17 @@ madt_setup_local(void)
 		if (dmartbl_physaddr != 0) {
 			dmartbl = acpi_map_table(dmartbl_physaddr,
 			    ACPI_SIG_DMAR);
-			if ((dmartbl->Flags & ACPI_DMAR_X2APIC_OPT_OUT) != 0) {
-				x2apic_mode = 0;
+			if ((dmartbl->Flags & ACPI_DMAR_X2APIC_OPT_OUT) != 0)
 				reason = "by DMAR table";
-			}
 			acpi_unmap_table(dmartbl);
 		}
 		if (vm_guest == VM_GUEST_VMWARE) {
 			vmware_hvcall(VMW_HVCMD_GETVCPU_INFO, p);
 			if ((p[0] & VMW_VCPUINFO_VCPU_RESERVED) != 0 ||
-			    (p[0] & VMW_VCPUINFO_LEGACY_X2APIC) == 0) {
-				x2apic_mode = 0;
-		reason = "inside VMWare without intr redirection";
-			}
+			    (p[0] & VMW_VCPUINFO_LEGACY_X2APIC) == 0)
+				reason =
+				    "inside VMWare without intr redirection";
 		} else if (vm_guest == VM_GUEST_XEN) {
-			x2apic_mode = 0;
 			reason = "due to running under XEN";
 		} else if (vm_guest == VM_GUEST_NO &&
 		    CPUID_TO_FAMILY(cpu_id) == 0x6 &&
@@ -184,16 +181,33 @@ madt_setup_local(void)
 				if (!strcmp(hw_vendor, "LENOVO") ||
 				    !strcmp(hw_vendor,
 				    "ASUSTeK Computer Inc.")) {
-					x2apic_mode = 0;
 					reason =
 				    "for a suspected SandyBridge BIOS bug";
 				}
 				freeenv(hw_vendor);
 			}
 		}
-		TUNABLE_INT_FETCH("hw.x2apic_enable", &x2apic_mode);
-		if (!x2apic_mode && reason != NULL && bootverbose)
+		bios_x2apic = lapic_is_x2apic();
+		if (reason != NULL && bios_x2apic) {
+			if (bootverbose)
+				printf("x2APIC should be disabled %s but "
+				    "already enabled by BIOS; enabling.\n",
+				     reason);
+			reason = NULL;
+		}
+		if (reason == NULL)
+			x2apic_mode = 1;
+		else if (bootverbose)
 			printf("x2APIC available but disabled %s\n", reason);
+		user_x2apic = x2apic_mode;
+		TUNABLE_INT_FETCH("hw.x2apic_enable", &user_x2apic);
+		if (user_x2apic != x2apic_mode) {
+			if (bios_x2apic && !user_x2apic)
+				printf("x2APIC disabled by tunable and "
+				    "enabled by BIOS; ignoring tunable.");
+			else
+				x2apic_mode = user_x2apic;
+		}
 	}
 
 	lapic_init(madt->Address);
diff --git a/sys/x86/include/apicvar.h b/sys/x86/include/apicvar.h
index 1ddb69e4938b..09c3a638df8f 100644
--- a/sys/x86/include/apicvar.h
+++ b/sys/x86/include/apicvar.h
@@ -206,6 +206,7 @@ struct apic_ops {
 	void	(*create)(u_int, int);
 	void	(*init)(vm_paddr_t);
 	void	(*xapic_mode)(void);
+	bool	(*is_x2apic)(void);
 	void	(*setup)(int);
 	void	(*dump)(const char *);
 	void	(*disable)(void);
@@ -268,6 +269,13 @@ lapic_xapic_mode(void)
 	apic_ops.xapic_mode();
 }
 
+static inline bool
+lapic_is_x2apic(void)
+{
+
+	return (apic_ops.is_x2apic());
+}
+
 static inline void
 lapic_setup(int boot)
 {
diff --git a/sys/x86/x86/local_apic.c b/sys/x86/x86/local_apic.c
index cd774df1422c..d9a3453037c1 100644
--- a/sys/x86/x86/local_apic.c
+++ b/sys/x86/x86/local_apic.c
@@ -269,6 +269,16 @@ native_lapic_enable_x2apic(void)
 	wrmsr(MSR_APICBASE, apic_base);
 }
 
+static bool
+native_lapic_is_x2apic(void)
+{
+	uint64_t apic_base;
+
+	apic_base = rdmsr(MSR_APICBASE);
+	return ((apic_base & (APICBASE_X2APIC | APICBASE_ENABLED)) ==
+	    (APICBASE_X2APIC | APICBASE_ENABLED));
+}
+
 static void	lapic_enable(void);
 static void	lapic_resume(struct pic *pic, bool suspend_cancelled);
 static void	lapic_timer_oneshot(struct lapic *);
@@ -329,6 +339,7 @@ struct apic_ops apic_ops = {
 	.create			= native_lapic_create,
 	.init			= native_lapic_init,
 	.xapic_mode		= native_lapic_xapic_mode,
+	.is_x2apic		= native_lapic_is_x2apic,
 	.setup			= native_lapic_setup,
 	.dump			= native_lapic_dump,
 	.disable		= native_lapic_disable,
diff --git a/sys/x86/xen/xen_apic.c b/sys/x86/xen/xen_apic.c
index 4d7a39ba5eed..45c3c18d8e6d 100644
--- a/sys/x86/xen/xen_apic.c
+++ b/sys/x86/xen/xen_apic.c
@@ -139,6 +139,13 @@ xen_pv_lapic_disable(void)
 
 }
 
+static bool
+xen_pv_lapic_is_x2apic(void)
+{
+
+	return (false);
+}
+
 static void
 xen_pv_lapic_eoi(void)
 {
@@ -351,6 +358,7 @@ struct apic_ops xen_apic_ops = {
 	.create			= xen_pv_lapic_create,
 	.init			= xen_pv_lapic_init,
 	.xapic_mode		= xen_pv_lapic_disable,
+	.is_x2apic		= xen_pv_lapic_is_x2apic,
 	.setup			= xen_pv_lapic_setup,
 	.dump			= xen_pv_lapic_dump,
 	.disable		= xen_pv_lapic_disable,
diff --git a/targets/pseudo/userland/Makefile.depend b/targets/pseudo/userland/Makefile.depend
index 6b9f83c009bb..700da508c2a0 100644
--- a/targets/pseudo/userland/Makefile.depend
+++ b/targets/pseudo/userland/Makefile.depend
@@ -325,6 +325,7 @@ DIRDEPS+= \
 	usr.bin/pr \
 	usr.bin/printenv \
 	usr.bin/printf \
+	usr.bin/proccontrol \
 	usr.bin/procstat \
 	usr.bin/protect \
 	usr.bin/quota \
diff --git a/tests/etc/rc.d/routing_test.sh b/tests/etc/rc.d/routing_test.sh
index 4fd6754192b0..f1510cbf1730 100755
--- a/tests/etc/rc.d/routing_test.sh
+++ b/tests/etc/rc.d/routing_test.sh
@@ -58,6 +58,10 @@ static_ipv6_loopback_route_for_each_fib_body()
 	local nfibs fib
 	nfibs=`sysctl -n net.fibs`
 
+	if [ "`sysctl -in kern.features.inet6`" != "1" ]; then
+		atf_skip "This test requires IPv6 support"
+	fi
+
 	# Check for an IPv6 loopback route
 	for fib in `seq 0 $((${nfibs} - 1))`; do
 		atf_check -o match:"interface: lo0" -s exit:0 \
diff --git a/tests/sys/Makefile b/tests/sys/Makefile
index 944e820ac1ae..682e21c00d37 100644
--- a/tests/sys/Makefile
+++ b/tests/sys/Makefile
@@ -1,6 +1,6 @@
 # $FreeBSD$
 
-TESTSDIR= ${TESTSBASE}/sys
+TESTSDIR=		${TESTSBASE}/sys
 
 TESTS_SUBDIRS+=		acl
 TESTS_SUBDIRS+=		aio
diff --git a/tests/sys/geom/class/eli/resize_test.sh b/tests/sys/geom/class/eli/resize_test.sh
index 67d62917bf2f..7a7cf635837b 100644
--- a/tests/sys/geom/class/eli/resize_test.sh
+++ b/tests/sys/geom/class/eli/resize_test.sh
@@ -18,7 +18,7 @@ setsize() {
     {
 	echo a: $(($partszMB * $BLKS_PER_MB)) 0 4.2BSD 1024 8192
 	echo c: $(($unitszMB * $BLKS_PER_MB)) 0 unused 0 0
-    } | disklabel -R $md /dev/stdin
+    } | bsdlabel -R $md /dev/stdin
 }
 
 # Initialise
diff --git a/tests/sys/mac/bsdextended/matches_test.sh b/tests/sys/mac/bsdextended/matches_test.sh
index 11cac81236e7..929bbca2fcca 100644
--- a/tests/sys/mac/bsdextended/matches_test.sh
+++ b/tests/sys/mac/bsdextended/matches_test.sh
@@ -36,6 +36,12 @@ if ! sysctl -N security.mac.bsdextended >/dev/null 2>&1; then
 	echo "1..0 # SKIP mac_bsdextended(4) support isn't available"
 	exit 0
 fi
+if [ "$TMPDIR" != "/tmp" ]; then
+	if ! chmod -Rf 0755 $TMPDIR; then
+		echo "1..0 # SKIP failed to chmod $TMPDIR"
+		exit 0
+	fi
+fi
 if ! playground=$(mktemp -d $TMPDIR/tmp.XXXXXXX); then
 	echo "1..0 # SKIP failed to create temporary directory"
 	exit 0
diff --git a/tools/build/options/WITHOUT_RCS b/tools/build/options/WITHOUT_RCS
deleted file mode 100644
index b4f89e162321..000000000000
--- a/tools/build/options/WITHOUT_RCS
+++ /dev/null
@@ -1,5 +0,0 @@
-.\" $FreeBSD$
-Set to not build
-.Xr rcs 1 ,
-.Xr etcupdate 8 ,
-and related utilities.
diff --git a/tools/build/options/WITH_META_MODE b/tools/build/options/WITH_META_MODE
index 9f7badee5961..5427cdfcf78c 100644
--- a/tools/build/options/WITH_META_MODE
+++ b/tools/build/options/WITH_META_MODE
@@ -49,6 +49,3 @@ The build operates as it normally would otherwise.
 This option originally invoked a different build system but that was renamed
 to
 .Va WITH_DIRDEPS_BUILD .
-.Pp
-Currently this also enforces
-.Va WITHOUT_SYSTEM_COMPILER .
diff --git a/tools/build/options/WITH_RCS b/tools/build/options/WITH_RCS
new file mode 100644
index 000000000000..0765b995717d
--- /dev/null
+++ b/tools/build/options/WITH_RCS
@@ -0,0 +1,4 @@
+.\" $FreeBSD$
+Set to build
+.Xr rcs 1
+and related utilities.
diff --git a/tools/tools/cxgbetool/cxgbetool.c b/tools/tools/cxgbetool/cxgbetool.c
index 3d4cbfbc0d1d..7d9a4c96ee1a 100644
--- a/tools/tools/cxgbetool/cxgbetool.c
+++ b/tools/tools/cxgbetool/cxgbetool.c
@@ -1360,7 +1360,7 @@ show_struct(const uint32_t *words, int nwords, const struct field_desc *fd)
 #define FIELD1(name, start) FIELD(name, start, start)
 
 static void
-show_t5_ctxt(const struct t4_sge_context *p)
+show_t5t6_ctxt(const struct t4_sge_context *p, int vers)
 {
 	static struct field_desc egress_t5[] = {
 		FIELD("DCA_ST:", 181, 191),
@@ -1400,6 +1400,44 @@ show_t5_ctxt(const struct t4_sge_context *p)
 		FIELD1("CachePriority:", 0),
 		{ NULL }
 	};
+	static struct field_desc egress_t6[] = {
+		FIELD("DCA_ST:", 181, 191),
+		FIELD1("StatusPgNS:", 180),
+		FIELD1("StatusPgRO:", 179),
+		FIELD1("FetchNS:", 178),
+		FIELD1("FetchRO:", 177),
+		FIELD1("Valid:", 176),
+		FIELD1("ReschedulePending_1:", 175),
+		FIELD1("PCIeDataChannel:", 174),
+		FIELD1("StatusPgTPHintEn:", 173),
+		FIELD("StatusPgTPHint:", 171, 172),
+		FIELD1("FetchTPHintEn:", 170),
+		FIELD("FetchTPHint:", 168, 169),
+		FIELD1("FCThreshOverride:", 167),
+		{ "WRLength:", 162, 166, 9, 0, 1 },
+		FIELD1("WRLengthKnown:", 161),
+		FIELD1("ReschedulePending:", 160),
+		FIELD("TimerIx:", 157, 159),
+		FIELD1("FetchBurstMin:", 156),
+		FIELD1("FLMPacking:", 155),
+		FIELD("FetchBurstMax:", 153, 154),
+		FIELD("uPToken:", 133, 152),
+		FIELD1("uPTokenEn:", 132),
+		FIELD1("UserModeIO:", 131),
+		FIELD("uPFLCredits:", 123, 130),
+		FIELD1("uPFLCreditEn:", 122),
+		FIELD("FID:", 111, 121),
+		FIELD("HostFCMode:", 109, 110),
+		FIELD1("HostFCOwner:", 108),
+		{ "CIDXFlushThresh:", 105, 107, 0, 0, 1 },
+		FIELD("CIDX:", 89, 104),
+		FIELD("PIDX:", 73, 88),
+		{ "BaseAddress:", 18, 72, 9, 1 },
+		FIELD("QueueSize:", 2, 17),
+		FIELD1("QueueType:", 1),
+		FIELD1("FetchSizeMode:", 0),
+		{ NULL }
+	};
 	static struct field_desc fl_t5[] = {
 		FIELD("DCA_ST:", 181, 191),
 		FIELD1("StatusPgNS:", 180),
@@ -1470,6 +1508,42 @@ show_t5_ctxt(const struct t4_sge_context *p)
 		FIELD1("CachePriority:", 0),
 		{ NULL }
 	};
+	static struct field_desc ingress_t6[] = {
+		FIELD1("SP_NS:", 158),
+		FIELD1("SP_RO:", 157),
+		FIELD1("SP_TPHintEn:", 156),
+		FIELD("SP_TPHint:", 154, 155),
+		FIELD("DCA_ST:", 143, 153),
+		FIELD1("ISCSICoalescing:", 142),
+		FIELD1("Queue_Valid:", 141),
+		FIELD1("TimerPending:", 140),
+		FIELD1("DropRSS:", 139),
+		FIELD("PCIeChannel:", 137, 138),
+		FIELD1("SEInterruptArmed:", 136),
+		FIELD1("CongestionMgtEnable:", 135),
+		FIELD1("NoSnoop:", 134),
+		FIELD1("RelaxedOrdering:", 133),
+		FIELD1("GTSmode:", 132),
+		FIELD1("TPHintEn:", 131),
+		FIELD("TPHint:", 129, 130),
+		FIELD1("UpdateScheduling:", 128),
+		FIELD("UpdateDelivery:", 126, 127),
+		FIELD1("InterruptSent:", 125),
+		FIELD("InterruptIDX:", 114, 124),
+		FIELD1("InterruptDestination:", 113),
+		FIELD1("InterruptArmed:", 112),
+		FIELD("RxIntCounter:", 106, 111),
+		FIELD("RxIntCounterThreshold:", 104, 105),
+		FIELD1("Generation:", 103),
+		{ "BaseAddress:", 48, 102, 9, 1 },
+		FIELD("PIDX:", 32, 47),
+		FIELD("CIDX:", 16, 31),
+		{ "QueueSize:", 4, 15, 4, 0 },
+		{ "QueueEntrySize:", 2, 3, 4, 0, 1 },
+		FIELD1("QueueEntryOverride:", 1),
+		FIELD1("CachePriority:", 0),
+		{ NULL }
+	};
 	static struct field_desc flm_t5[] = {
 		FIELD1("Valid:", 89),
 		FIELD("SplitLenMode:", 87, 88),
@@ -1489,6 +1563,28 @@ show_t5_ctxt(const struct t4_sge_context *p)
 		FIELD("PIDX:", 0, 7),
 		{ NULL }
 	};
+	static struct field_desc flm_t6[] = {
+		FIELD1("Valid:", 89),
+		FIELD("SplitLenMode:", 87, 88),
+		FIELD1("TPHintEn:", 86),
+		FIELD("TPHint:", 84, 85),
+		FIELD1("NoSnoop:", 83),
+		FIELD1("RelaxedOrdering:", 82),
+		FIELD("DCA_ST:", 71, 81),
+		FIELD("EQid:", 54, 70),
+		FIELD("SplitEn:", 52, 53),
+		FIELD1("PadEn:", 51),
+		FIELD1("PackEn:", 50),
+		FIELD1("Cache_Lock :", 49),
+		FIELD1("CongDrop:", 48),
+		FIELD1("Inflight:", 47),
+		FIELD1("CongEn:", 46),
+		FIELD1("CongMode:", 45),
+		FIELD("PackOffset:", 20, 39),
+		FIELD("CIDX:", 8, 15),
+		FIELD("PIDX:", 0, 7),
+		{ NULL }
+	};
 	static struct field_desc conm_t5[] = {
 		FIELD1("CngMPSEnable:", 21),
 		FIELD("CngTPMode:", 19, 20),
@@ -1499,12 +1595,17 @@ show_t5_ctxt(const struct t4_sge_context *p)
 		{ NULL }
 	};
 
-	if (p->mem_id == SGE_CONTEXT_EGRESS)
-		show_struct(p->data, 6, (p->data[0] & 2) ? fl_t5 : egress_t5);
-	else if (p->mem_id == SGE_CONTEXT_FLM)
-		show_struct(p->data, 3, flm_t5);
+	if (p->mem_id == SGE_CONTEXT_EGRESS) {
+		if (p->data[0] & 2)
+			show_struct(p->data, 6, fl_t5);
+		else if (vers == 5)
+			show_struct(p->data, 6, egress_t5);
+		else
+			show_struct(p->data, 6, egress_t6);
+	} else if (p->mem_id == SGE_CONTEXT_FLM)
+		show_struct(p->data, 3, vers == 5 ? flm_t5 : flm_t6);
 	else if (p->mem_id == SGE_CONTEXT_INGRESS)
-		show_struct(p->data, 5, ingress_t5);
+		show_struct(p->data, 5, vers == 5 ? ingress_t5 : ingress_t6);
 	else if (p->mem_id == SGE_CONTEXT_CNM)
 		show_struct(p->data, 1, conm_t5);
 }
@@ -1689,7 +1790,7 @@ get_sge_context(int argc, const char *argv[])
 	if (chip_id == 4)
 		show_t4_ctxt(&cntxt);
 	else
-		show_t5_ctxt(&cntxt);
+		show_t5t6_ctxt(&cntxt, chip_id);
 
 	return (0);
 }
diff --git a/usr.bin/Makefile b/usr.bin/Makefile
index 8084c708716d..5a6911d02dda 100644
--- a/usr.bin/Makefile
+++ b/usr.bin/Makefile
@@ -122,6 +122,7 @@ SUBDIR=	alias \
 	pr \
 	printenv \
 	printf \
+	proccontrol \
 	procstat \
 	protect \
 	rctl \
diff --git a/usr.bin/bsdiff/bspatch/bspatch.c b/usr.bin/bsdiff/bspatch/bspatch.c
index 185814639a20..fc7c07de7b72 100644
--- a/usr.bin/bsdiff/bspatch/bspatch.c
+++ b/usr.bin/bsdiff/bspatch/bspatch.c
@@ -29,12 +29,9 @@ __FBSDID("$FreeBSD$");
 
 #if defined(__FreeBSD__)
 #include <sys/param.h>
-#if __FreeBSD_version >= 1100014
+#if __FreeBSD_version >= 1001511
 #include <sys/capsicum.h>
 #define HAVE_CAPSICUM
-#elif __FreeBSD_version >= 1000000
-#include <sys/capability.h>
-#define HAVE_CAPSICUM
 #endif
 #endif
 
diff --git a/usr.bin/calendar/calendars/calendar.freebsd b/usr.bin/calendar/calendars/calendar.freebsd
index 6254f1a3a83b..841896eb1d81 100644
--- a/usr.bin/calendar/calendars/calendar.freebsd
+++ b/usr.bin/calendar/calendars/calendar.freebsd
@@ -342,6 +342,7 @@
 10/26	Philip M. Gollucci <pgollucci@FreeBSD.org> born in Silver Spring, Maryland, United States, 1979
 10/27	Takanori Watanabe <takawata@FreeBSD.org> born in Numazu, Shizuoka, Japan, 1972
 11/05	M. Warner Losh <imp@FreeBSD.org> born in Kansas City, Kansas, United States, 1966
+11/08	Joseph R. Mingrone <jrm@FreeBSD.org> born in Charlottetown, Prince Edward Island, Canada, 1976
 11/09	Coleman Kane <cokane@FreeBSD.org> born in Cincinnati, Ohio, United States, 1980
 11/09	Antoine Brodin <antoine@FreeBSD.org> born in Bagnolet, France, 1981
 11/10	Gregory Neil Shapiro <gshapiro@FreeBSD.org> born in Providence, Rhode Island, United States, 1970
diff --git a/usr.bin/cmp/cmp.c b/usr.bin/cmp/cmp.c
index f3ac7178ecad..b1e0c4cc9106 100644
--- a/usr.bin/cmp/cmp.c
+++ b/usr.bin/cmp/cmp.c
@@ -43,14 +43,17 @@ static char sccsid[] = "@(#)cmp.c	8.3 (Berkeley) 4/2/94";
 __FBSDID("$FreeBSD$");
 
 #include <sys/types.h>
+#include <sys/capsicum.h>
 #include <sys/stat.h>
 
 #include <err.h>
 #include <errno.h>
 #include <fcntl.h>
+#include <nl_types.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <termios.h>
 #include <unistd.h>
 
 #include "extern.h"
@@ -66,6 +69,9 @@ main(int argc, char *argv[])
 	off_t skip1, skip2;
 	int ch, fd1, fd2, oflag, special;
 	const char *file1, *file2;
+	cap_rights_t rights;
+	unsigned long cmd;
+	uint32_t fcntls;
 
 	oflag = O_RDONLY;
 	while ((ch = getopt(argc, argv, "hlsxz")) != -1)
@@ -146,6 +152,37 @@ main(int argc, char *argv[])
 			exit(ERR_EXIT);
 	}
 
+	cap_rights_init(&rights, CAP_FCNTL, CAP_FSTAT, CAP_MMAP_R);
+	if (cap_rights_limit(fd1, &rights) < 0 && errno != ENOSYS)
+		err(ERR_EXIT, "unable to limit rights for %s", file1);
+	if (cap_rights_limit(fd2, &rights) < 0 && errno != ENOSYS)
+		err(ERR_EXIT, "unable to limit rights for %s", file2);
+
+	/* Required for fdopen(3). */
+	fcntls = CAP_FCNTL_GETFL;
+	if (cap_fcntls_limit(fd1, fcntls) < 0 && errno != ENOSYS)
+		err(ERR_EXIT, "unable to limit fcntls for %s", file1);
+	if (cap_fcntls_limit(fd2, fcntls) < 0 && errno != ENOSYS)
+		err(ERR_EXIT, "unable to limit fcntls for %s", file2);
+
+	cap_rights_init(&rights, CAP_FSTAT, CAP_WRITE, CAP_IOCTL);
+	if (cap_rights_limit(STDOUT_FILENO, &rights) < 0 && errno != ENOSYS)
+		err(ERR_EXIT, "unable to limit rights for stdout");
+
+	/* Required for printf(3) via isatty(3). */
+	cmd = TIOCGETA;
+	if (cap_ioctls_limit(STDOUT_FILENO, &cmd, 1) < 0 && errno != ENOSYS)
+		err(ERR_EXIT, "unable to limit ioctls for stdout");
+
+	/*
+	 * Cache NLS data, for strerror, for err(3), before entering capability
+	 * mode.
+	 */
+	(void)catopen("libc", NL_CAT_LOCALE);
+
+	if (cap_enter() < 0 && errno != ENOSYS)
+		err(ERR_EXIT, "unable to enter capability mode");
+
 	if (!special) {
 		if (fstat(fd1, &sb1)) {
 			if (!sflag)
diff --git a/usr.bin/elfdump/elfdump.c b/usr.bin/elfdump/elfdump.c
index e42727a44f8c..3a70326270c8 100644
--- a/usr.bin/elfdump/elfdump.c
+++ b/usr.bin/elfdump/elfdump.c
@@ -44,6 +44,7 @@ __FBSDID("$FreeBSD$");
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <termios.h>
 #include <unistd.h>
 
 #define	ED_DYN		(1<<0)
@@ -504,6 +505,7 @@ main(int ac, char **av)
 	u_int64_t name;
 	u_int64_t type;
 	struct stat sb;
+	unsigned long cmd;
 	u_int flags;
 	Elf32_Ehdr *e;
 	void *p;
@@ -571,12 +573,14 @@ main(int ac, char **av)
 	cap_rights_init(&rights, CAP_MMAP_R);
 	if (cap_rights_limit(fd, &rights) < 0 && errno != ENOSYS)
 		err(1, "unable to limit rights for %s", *av);
-	close(STDIN_FILENO);
-	cap_rights_init(&rights, CAP_WRITE);
-	if (cap_rights_limit(STDOUT_FILENO, &rights) < 0 && errno != ENOSYS)
-		err(1, "unable to limit rights for stdout");
-	if (cap_rights_limit(STDERR_FILENO, &rights) < 0 && errno != ENOSYS)
-		err(1, "unable to limit rights for stderr");
+	cap_rights_limit(STDIN_FILENO, cap_rights_init(&rights));
+	cap_rights_init(&rights, CAP_FSTAT, CAP_IOCTL, CAP_WRITE);
+	cmd = TIOCGETA; /* required by isatty(3) in printf(3) */
+	if ((cap_rights_limit(STDOUT_FILENO, &rights) < 0 && errno != ENOSYS) ||
+	    (cap_ioctls_limit(STDOUT_FILENO, &cmd, 1) < 0 && errno != ENOSYS) ||
+	    (cap_rights_limit(STDERR_FILENO, &rights) < 0 && errno != ENOSYS) ||
+	    (cap_ioctls_limit(STDERR_FILENO, &cmd, 1) < 0 && errno != ENOSYS))
+		err(1, "unable to limit rights for stdout/stderr");
 	if (cap_enter() < 0 && errno != ENOSYS)
 		err(1, "unable to enter capability mode");
 	e = mmap(NULL, sb.st_size, PROT_READ, MAP_SHARED, fd, 0);
diff --git a/usr.bin/hexdump/parse.c b/usr.bin/hexdump/parse.c
index 1e0612028f86..8f433d18ff3a 100644
--- a/usr.bin/hexdump/parse.c
+++ b/usr.bin/hexdump/parse.c
@@ -208,7 +208,6 @@ rewrite(FS *fs)
 	unsigned char *p1, *p2, *fmtp;
 	char savech, cs[3];
 	int nconv, prec;
-	size_t len;
 
 	prec = 0;
 
@@ -389,10 +388,8 @@ isint2:					switch(fu->bcnt) {
 			 */
 			savech = *p2;
 			p1[0] = '\0';
-			len = strlen(fmtp) + strlen(cs) + 1;
-			if ((pr->fmt = calloc(1, len)) == NULL)
+			if (asprintf(&pr->fmt, "%s%s", fmtp, cs) == -1)
 				err(1, NULL);
-			snprintf(pr->fmt, len, "%s%s", fmtp, cs);
 			*p2 = savech;
 			pr->cchar = pr->fmt + (p1 - fmtp);
 			fmtp = p2;
diff --git a/usr.bin/indent/indent.c b/usr.bin/indent/indent.c
index d11270caba27..03e649facfb6 100644
--- a/usr.bin/indent/indent.c
+++ b/usr.bin/indent/indent.c
@@ -51,7 +51,9 @@ static char sccsid[] = "@(#)indent.c	5.17 (Berkeley) 6/7/93";
 __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
+#include <sys/capsicum.h>
 #include <err.h>
+#include <errno.h>
 #include <fcntl.h>
 #include <unistd.h>
 #include <stdio.h>
@@ -74,6 +76,7 @@ char        bakfile[MAXPATHLEN] = "";
 int
 main(int argc, char **argv)
 {
+    cap_rights_t rights;
 
     int         dec_ind;	/* current indentation for declarations */
     int         di_stack[20];	/* a stack of structure indentation levels */
@@ -234,6 +237,17 @@ main(int argc, char **argv)
 	    bakcopy();
 	}
     }
+
+    /* Restrict input/output descriptors and enter Capsicum sandbox. */
+    cap_rights_init(&rights, CAP_FSTAT, CAP_WRITE);
+    if (cap_rights_limit(fileno(output), &rights) < 0 && errno != ENOSYS)
+	err(EXIT_FAILURE, "unable to limit rights for %s", out_name);
+    cap_rights_init(&rights, CAP_FSTAT, CAP_READ);
+    if (cap_rights_limit(fileno(input), &rights) < 0 && errno != ENOSYS)
+	err(EXIT_FAILURE, "unable to limit rights for %s", in_name);
+    if (cap_enter() < 0 && errno != ENOSYS)
+	err(EXIT_FAILURE, "unable to enter capability mode");
+
     if (ps.com_ind <= 1)
 	ps.com_ind = 2;		/* dont put normal comments before column 2 */
     if (troff) {
diff --git a/usr.bin/mkimg/mkimg.1 b/usr.bin/mkimg/mkimg.1
index 246a39705bc2..856818a71e3b 100644
--- a/usr.bin/mkimg/mkimg.1
+++ b/usr.bin/mkimg/mkimg.1
@@ -328,4 +328,4 @@ utility first appeared in
 The
 .Nm
 utility and manpage were written by
-.An Marcel Moolenaar Aq Mt marcelm@juniper.net .
+.An Marcel Moolenaar Aq Mt marcel@FreeBSD.org .
diff --git a/usr.bin/mkimg/mkimg.c b/usr.bin/mkimg/mkimg.c
index 5a4b9f9b26fa..5d41e3bbd48b 100644
--- a/usr.bin/mkimg/mkimg.c
+++ b/usr.bin/mkimg/mkimg.c
@@ -463,13 +463,16 @@ mkimg(void)
 
 	block = scheme_metadata(SCHEME_META_IMG_END, block);
 	error = image_set_size(block);
-	if (!error)
+	if (!error) {
 		error = capacity_resize(block);
-	if (!error)
+		block = image_get_size();
+	}
+	if (!error) {
 		error = format_resize(block);
+		block = image_get_size();
+	}
 	if (error)
 		errc(EX_IOERR, error, "image sizing");
-	block = image_get_size();
 	ncyls = block / (nsecs * nheads);
 	error = scheme_write(block);
 	if (error)
diff --git a/usr.bin/proccontrol/Makefile b/usr.bin/proccontrol/Makefile
new file mode 100644
index 000000000000..c11c412ee08b
--- /dev/null
+++ b/usr.bin/proccontrol/Makefile
@@ -0,0 +1,7 @@
+# $FreeBSD$
+
+PROG=   proccontrol
+WARNS?=	6
+MK_MAN=no
+
+.include <bsd.prog.mk>
diff --git a/usr.bin/proccontrol/Makefile.depend b/usr.bin/proccontrol/Makefile.depend
new file mode 100644
index 000000000000..3646e2e2b1af
--- /dev/null
+++ b/usr.bin/proccontrol/Makefile.depend
@@ -0,0 +1,18 @@
+# $FreeBSD$
+# Autogenerated - do NOT edit!
+
+DIRDEPS = \
+	gnu/lib/csu \
+	gnu/lib/libgcc \
+	include \
+	include/xlocale \
+	lib/${CSU_DIR} \
+	lib/libc \
+	lib/libcompiler_rt \
+
+
+.include <dirdeps.mk>
+
+.if ${DEP_RELDIR} == ${_DEP_RELDIR}
+# local dependencies - needed for -jN in clean tree
+.endif
diff --git a/usr.bin/proccontrol/proccontrol.c b/usr.bin/proccontrol/proccontrol.c
new file mode 100644
index 000000000000..4cb37018c419
--- /dev/null
+++ b/usr.bin/proccontrol/proccontrol.c
@@ -0,0 +1,180 @@
+/*-
+ * Copyright (c) 2016 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
+ * under sponsorship from the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/procctl.h>
+#include <err.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+enum {
+	MODE_INVALID,
+	MODE_TRACE,
+	MODE_TRAPCAP,
+};
+
+static pid_t
+str2pid(const char *str)
+{
+	pid_t res;
+	char *tail;
+
+	res = strtol(str, &tail, 0);
+	if (*tail != '\0') {
+		warnx("non-numeric pid");
+		return (-1);
+	}
+	return (res);
+}
+
+static void __dead2
+usage(void)
+{
+
+	fprintf(stderr, "Usage: proccontrol -m (trace|trapcap) [-q] "
+	    "[-s (enable|disable)] [-p pid | command]\n");
+	exit(1);
+}
+
+int
+main(int argc, char *argv[])
+{
+	int arg, ch, error, mode;
+	pid_t pid;
+	bool enable, do_command, query;
+
+	mode = MODE_INVALID;
+	enable = true;
+	pid = -1;
+	query = false;
+	while ((ch = getopt(argc, argv, "m:qs:p:")) != -1) {
+		switch (ch) {
+		case 'm':
+			if (strcmp(optarg, "trace") == 0)
+				mode = MODE_TRACE;
+			else if (strcmp(optarg, "trapcap") == 0)
+				mode = MODE_TRAPCAP;
+			else
+				usage();
+			break;
+		case 's':
+			if (strcmp(optarg, "enable") == 0)
+				enable = true;
+			else if (strcmp(optarg, "disable") == 0)
+				enable = false;
+			else
+				usage();
+			break;
+		case 'p':
+			pid = str2pid(optarg);
+			break;
+		case 'q':
+			query = true;
+			break;
+		case '?':
+		default:
+			usage();
+			break;
+		}
+	}
+	argc -= optind;
+	argv += optind;
+	do_command = argc != 0;
+	if (do_command) {
+		if (pid != -1 || query)
+			usage();
+		pid = getpid();
+	} else if (pid == -1) {
+		pid = getpid();
+	}
+
+	if (query) {
+		switch (mode) {
+		case MODE_TRACE:
+			error = procctl(P_PID, pid, PROC_TRACE_STATUS, &arg);
+			break;
+		case MODE_TRAPCAP:
+			error = procctl(P_PID, pid, PROC_TRAPCAP_STATUS, &arg);
+			break;
+		default:
+			usage();
+			break;
+		}
+		if (error != 0)
+			err(1, "procctl status");
+		switch (mode) {
+		case MODE_TRACE:
+			if (arg == -1)
+				printf("disabled\n");
+			else if (arg == 0)
+				printf("enabled, no debugger\n");
+			else
+				printf("enabled, traced by %d\n", arg);
+			break;
+		case MODE_TRAPCAP:
+			switch (arg) {
+			case PROC_TRAPCAP_CTL_ENABLE:
+				printf("enabled\n");
+				break;
+			case PROC_TRAPCAP_CTL_DISABLE:
+				printf("disabled\n");
+				break;
+			}
+			break;
+		}
+	} else {
+		switch (mode) {
+		case MODE_TRACE:
+			arg = enable ? PROC_TRACE_CTL_ENABLE :
+			    PROC_TRACE_CTL_DISABLE;
+			error = procctl(P_PID, pid, PROC_TRACE_CTL, &arg);
+			break;
+		case MODE_TRAPCAP:
+			arg = enable ? PROC_TRAPCAP_CTL_ENABLE :
+			    PROC_TRAPCAP_CTL_DISABLE;
+			error = procctl(P_PID, pid, PROC_TRAPCAP_CTL, &arg);
+			break;
+		default:
+			usage();
+			break;
+		}
+		if (error != 0)
+			err(1, "procctl ctl");
+		if (do_command) {
+			error = execvp(argv[0], argv);
+			err(1, "exec");
+		}
+	}
+	exit(0);
+}
diff --git a/usr.bin/sdiff/sdiff.c b/usr.bin/sdiff/sdiff.c
index 76b6475fbc24..1b122d12eee7 100644
--- a/usr.bin/sdiff/sdiff.c
+++ b/usr.bin/sdiff/sdiff.c
@@ -477,8 +477,8 @@ main(int argc, char **argv)
 }
 
 /*
- * When sdiff/zsdiff detects a binary file as input, executes them with
- * diff/zdiff to maintain the same behavior as GNU sdiff with binary input.
+ * When sdiff detects a binary file as input, executes them with
+ * diff to maintain the same behavior as GNU sdiff with binary input.
  */
 static void
 binexec(char *diffprog, char *f1, char *f2)
diff --git a/usr.bin/tee/tee.c b/usr.bin/tee/tee.c
index 6b5c00c532fb..302bb97e32ca 100644
--- a/usr.bin/tee/tee.c
+++ b/usr.bin/tee/tee.c
@@ -41,14 +41,18 @@ static const char rcsid[] =
   "$FreeBSD$";
 #endif /* not lint */
 
-#include <sys/types.h>
+#include <sys/capsicum.h>
 #include <sys/stat.h>
+#include <sys/types.h>
+
 #include <err.h>
+#include <errno.h>
 #include <fcntl.h>
 #include <signal.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <termios.h>
 #include <unistd.h>
 
 typedef struct _list {
@@ -69,6 +73,8 @@ main(int argc, char *argv[])
 	char *bp;
 	int append, ch, exitval;
 	char *buf;
+	cap_rights_t rights;
+	unsigned long cmd;
 #define	BSIZE (8 * 1024)
 
 	append = 0;
@@ -90,6 +96,16 @@ main(int argc, char *argv[])
 	if ((buf = malloc(BSIZE)) == NULL)
 		err(1, "malloc");
 
+	cap_rights_init(&rights, CAP_READ, CAP_FSTAT);
+	if (cap_rights_limit(STDIN_FILENO, &rights) < 0 && errno != ENOSYS)
+		err(EXIT_FAILURE, "unable to limit rights for stdin");
+	cap_rights_init(&rights, CAP_WRITE, CAP_FSTAT, CAP_IOCTL);
+	if (cap_rights_limit(STDERR_FILENO, &rights) < 0 && errno != ENOSYS)
+		err(EXIT_FAILURE, "unable to limit rights for stderr");
+	cmd = TIOCGETA;
+	if (cap_ioctls_limit(STDERR_FILENO, &cmd, 1) < 0 && errno != ENOSYS)
+		err(EXIT_FAILURE, "unable to limit ioctls for stderr");
+
 	add(STDOUT_FILENO, "stdout");
 
 	for (exitval = 0; *argv; ++argv)
@@ -100,6 +116,8 @@ main(int argc, char *argv[])
 		} else
 			add(fd, *argv);
 
+	if (cap_enter() < 0 && errno != ENOSYS)
+		err(EXIT_FAILURE, "unable to enter capability mode");
 	while ((rval = read(STDIN_FILENO, buf, BSIZE)) > 0)
 		for (p = head; p; p = p->next) {
 			n = rval;
@@ -129,6 +147,21 @@ static void
 add(int fd, const char *name)
 {
 	LIST *p;
+	cap_rights_t rights;
+	unsigned long cmd;
+
+	if (fd == STDOUT_FILENO)
+		cap_rights_init(&rights, CAP_WRITE, CAP_FSTAT, CAP_IOCTL);
+	else
+		cap_rights_init(&rights, CAP_WRITE, CAP_FSTAT);
+	if (cap_rights_limit(fd, &rights) < 0 && errno != ENOSYS)
+		err(EXIT_FAILURE, "unable to limit rights");
+
+	if (fd == STDOUT_FILENO) {
+		cmd = TIOCGETA;
+		if (cap_ioctls_limit(fd, &cmd, 1) < 0 && errno != ENOSYS)
+			err(EXIT_FAILURE, "unable to limit ioctls for stdout");
+	}
 
 	if ((p = malloc(sizeof(LIST))) == NULL)
 		err(1, "malloc");
diff --git a/usr.bin/tr/tr.c b/usr.bin/tr/tr.c
index d54e74c19319..b22ae7d3e248 100644
--- a/usr.bin/tr/tr.c
+++ b/usr.bin/tr/tr.c
@@ -42,15 +42,18 @@ static const char sccsid[] = "@(#)tr.c	8.2 (Berkeley) 5/4/95";
 #endif
 
 #include <sys/types.h>
+#include <sys/capsicum.h>
 
 #include <ctype.h>
 #include <err.h>
+#include <errno.h>
 #include <limits.h>
 #include <locale.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <termios.h>
 #include <unistd.h>
 #include <wchar.h>
 #include <wctype.h>
@@ -69,6 +72,8 @@ int
 main(int argc, char **argv)
 {
 	static int carray[NCHARS_SB];
+	cap_rights_t rights;
+	unsigned long cmd;
 	struct cmap *map;
 	struct cset *delete, *squeeze;
 	int n, *p;
@@ -77,6 +82,27 @@ main(int argc, char **argv)
 
 	(void)setlocale(LC_ALL, "");
 
+	cap_rights_init(&rights, CAP_FSTAT, CAP_IOCTL, CAP_READ);
+	if (cap_rights_limit(STDIN_FILENO, &rights) < 0 && errno != ENOSYS)
+		err(1, "unable to limit rights for stdin");
+	cap_rights_init(&rights, CAP_FSTAT, CAP_IOCTL, CAP_WRITE);
+	if (cap_rights_limit(STDOUT_FILENO, &rights) < 0 && errno != ENOSYS)
+		err(1, "unable to limit rights for stdout");
+	if (cap_rights_limit(STDERR_FILENO, &rights) < 0 && errno != ENOSYS)
+		err(1, "unable to limit rights for stderr");
+
+	/* Required for isatty(3). */
+	cmd = TIOCGETA;
+	if (cap_ioctls_limit(STDIN_FILENO, &cmd, 1) < 0 && errno != ENOSYS)
+		err(1, "unable to limit ioctls for stdin");
+	if (cap_ioctls_limit(STDOUT_FILENO, &cmd, 1) < 0 && errno != ENOSYS)
+		err(1, "unable to limit ioctls for stdout");
+	if (cap_ioctls_limit(STDERR_FILENO, &cmd, 1) < 0 && errno != ENOSYS)
+		err(1, "unable to limit ioctls for stderr");
+
+	if (cap_enter() < 0 && errno != ENOSYS)
+		err(1, "unable to enter capability mode");
+
 	Cflag = cflag = dflag = sflag = 0;
 	while ((ch = getopt(argc, argv, "Ccdsu")) != -1)
 		switch((char)ch) {
diff --git a/usr.sbin/bhyve/Makefile b/usr.sbin/bhyve/Makefile
index 11273499582e..c4b1e37ca709 100644
--- a/usr.sbin/bhyve/Makefile
+++ b/usr.sbin/bhyve/Makefile
@@ -36,6 +36,7 @@ SRCS=	\
 	pci_lpc.c		\
 	pci_passthru.c		\
 	pci_virtio_block.c	\
+	pci_virtio_console.c	\
 	pci_virtio_net.c	\
 	pci_virtio_rnd.c	\
 	pci_uart.c		\
diff --git a/usr.sbin/bhyve/pci_virtio_console.c b/usr.sbin/bhyve/pci_virtio_console.c
new file mode 100644
index 000000000000..977e0efcfbc2
--- /dev/null
+++ b/usr.sbin/bhyve/pci_virtio_console.c
@@ -0,0 +1,641 @@
+/*-
+ * Copyright (c) 2016 iXsystems Inc.
+ * All rights reserved.
+ *
+ * This software was developed by Jakub Klama <jceel@FreeBSD.org>
+ * under sponsorship from iXsystems Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer
+ *    in this position and unchanged.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/linker_set.h>
+#include <sys/uio.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <sys/un.h>
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+#include <unistd.h>
+#include <assert.h>
+#include <pthread.h>
+#include <libgen.h>
+
+#include "bhyverun.h"
+#include "pci_emul.h"
+#include "virtio.h"
+#include "mevent.h"
+
+#define	VTCON_RINGSZ	64
+#define	VTCON_MAXPORTS	16
+#define	VTCON_MAXQ	(VTCON_MAXPORTS * 2 + 2)
+
+#define	VTCON_DEVICE_READY	0
+#define	VTCON_DEVICE_ADD	1
+#define	VTCON_DEVICE_REMOVE	2
+#define	VTCON_PORT_READY	3
+#define	VTCON_CONSOLE_PORT	4
+#define	VTCON_CONSOLE_RESIZE	5
+#define	VTCON_PORT_OPEN		6
+#define	VTCON_PORT_NAME		7
+
+#define	VTCON_F_SIZE		0
+#define	VTCON_F_MULTIPORT	1
+#define	VTCON_F_EMERG_WRITE	2
+#define	VTCON_S_HOSTCAPS	\
+    (VTCON_F_SIZE | VTCON_F_MULTIPORT | VTCON_F_EMERG_WRITE)
+
+static int pci_vtcon_debug;
+#define DPRINTF(params) if (pci_vtcon_debug) printf params
+#define WPRINTF(params) printf params
+
+struct pci_vtcon_softc;
+struct pci_vtcon_port;
+struct pci_vtcon_config;
+typedef void (pci_vtcon_cb_t)(struct pci_vtcon_port *, void *, struct iovec *,
+    int);
+
+struct pci_vtcon_port {
+	struct pci_vtcon_softc * vsp_sc;
+	int                      vsp_id;
+	const char *             vsp_name;
+	bool                     vsp_enabled;
+	bool                     vsp_console;
+	bool                     vsp_rx_ready;
+	int                      vsp_rxq;
+	int                      vsp_txq;
+	void *                   vsp_arg;
+	pci_vtcon_cb_t *         vsp_cb;
+};
+
+struct pci_vtcon_sock
+{
+	struct pci_vtcon_port *  vss_port;
+	const char *             vss_path;
+	struct mevent *          vss_server_evp;
+	struct mevent *          vss_conn_evp;
+	int                      vss_server_fd;
+	int                      vss_conn_fd;
+	bool                     vss_open;
+};
+
+struct pci_vtcon_softc {
+	struct virtio_softc      vsc_vs;
+	struct vqueue_info       vsc_queues[VTCON_MAXQ];
+	pthread_mutex_t          vsc_mtx;
+	uint64_t                 vsc_cfg;
+	uint64_t                 vsc_features;
+	char *                   vsc_rootdir;
+	int                      vsc_kq;
+	int                      vsc_nports;
+	struct pci_vtcon_port    vsc_control_port;
+ 	struct pci_vtcon_port    vsc_ports[VTCON_MAXPORTS];
+	struct pci_vtcon_config *vsc_config;
+};
+
+struct pci_vtcon_config {
+	uint16_t cols;
+	uint16_t rows;
+	uint32_t max_nr_ports;
+	uint32_t emerg_wr;
+} __attribute__((packed));
+
+struct pci_vtcon_control {
+	uint32_t id;
+	uint16_t event;
+	uint16_t value;
+} __attribute__((packed));
+
+struct pci_vtcon_console_resize {
+	uint16_t cols;
+	uint16_t rows;
+} __attribute__((packed));
+
+static void pci_vtcon_reset(void *);
+static void pci_vtcon_notify_rx(void *, struct vqueue_info *);
+static void pci_vtcon_notify_tx(void *, struct vqueue_info *);
+static int pci_vtcon_cfgread(void *, int, int, uint32_t *);
+static int pci_vtcon_cfgwrite(void *, int, int, uint32_t);
+static void pci_vtcon_neg_features(void *, uint64_t);
+static void pci_vtcon_sock_accept(int, enum ev_type,  void *);
+static void pci_vtcon_sock_rx(int, enum ev_type, void *);
+static void pci_vtcon_sock_tx(struct pci_vtcon_port *, void *, struct iovec *,
+    int);
+static void pci_vtcon_control_send(struct pci_vtcon_softc *,
+    struct pci_vtcon_control *, const void *, size_t);
+static void pci_vtcon_announce_port(struct pci_vtcon_port *);
+static void pci_vtcon_open_port(struct pci_vtcon_port *, bool);
+
+static struct virtio_consts vtcon_vi_consts = {
+	"vtcon",		/* our name */
+	VTCON_MAXQ,		/* we support VTCON_MAXQ virtqueues */
+	sizeof(struct pci_vtcon_config), /* config reg size */
+	pci_vtcon_reset,	/* reset */
+	NULL,			/* device-wide qnotify */
+	pci_vtcon_cfgread,	/* read virtio config */
+	pci_vtcon_cfgwrite,	/* write virtio config */
+	pci_vtcon_neg_features,	/* apply negotiated features */
+	VTCON_S_HOSTCAPS,	/* our capabilities */
+};
+
+
+static void
+pci_vtcon_reset(void *vsc)
+{
+	struct pci_vtcon_softc *sc;
+
+	sc = vsc;
+
+	DPRINTF(("vtcon: device reset requested!\n"));
+	vi_reset_dev(&sc->vsc_vs);
+}
+
+static void
+pci_vtcon_neg_features(void *vsc, uint64_t negotiated_features)
+{
+	struct pci_vtcon_softc *sc = vsc;
+
+	sc->vsc_features = negotiated_features;
+}
+
+static int
+pci_vtcon_cfgread(void *vsc, int offset, int size, uint32_t *retval)
+{
+	struct pci_vtcon_softc *sc = vsc;
+	void *ptr;
+
+	ptr = (uint8_t *)sc->vsc_config + offset;
+	memcpy(retval, ptr, size);
+	return (0);
+}
+
+static int
+pci_vtcon_cfgwrite(void *vsc, int offset, int size, uint32_t val)
+{
+
+	return (0);
+}
+
+static inline struct pci_vtcon_port *
+pci_vtcon_vq_to_port(struct pci_vtcon_softc *sc, struct vqueue_info *vq)
+{
+	uint16_t num = vq->vq_num;
+
+	if (num == 0 || num == 1)
+		return (&sc->vsc_ports[0]);
+
+	if (num == 2 || num == 3)
+		return (&sc->vsc_control_port);
+
+	return (&sc->vsc_ports[(num / 2) - 1]);
+}
+
+static inline struct vqueue_info *
+pci_vtcon_port_to_vq(struct pci_vtcon_port *port, bool tx_queue)
+{
+	int qnum;
+
+	qnum = tx_queue ? port->vsp_txq : port->vsp_rxq;
+	return (&port->vsp_sc->vsc_queues[qnum]);
+}
+
+static struct pci_vtcon_port *
+pci_vtcon_port_add(struct pci_vtcon_softc *sc, const char *name,
+    pci_vtcon_cb_t *cb, void *arg)
+{
+	struct pci_vtcon_port *port;
+
+	if (sc->vsc_nports == VTCON_MAXPORTS) {
+		errno = EBUSY;
+		return (NULL);
+	}
+
+	port = &sc->vsc_ports[sc->vsc_nports++];
+	port->vsp_id = sc->vsc_nports - 1;
+	port->vsp_sc = sc;
+	port->vsp_name = name;
+	port->vsp_cb = cb;
+	port->vsp_arg = arg;
+
+	if (port->vsp_id == 0) {
+		/* port0 */
+		port->vsp_txq = 0;
+		port->vsp_rxq = 1;
+	} else {
+		port->vsp_txq = sc->vsc_nports * 2;
+		port->vsp_rxq = port->vsp_txq + 1;
+	}
+
+	port->vsp_enabled = true;
+	return (port);
+}
+
+static int
+pci_vtcon_sock_add(struct pci_vtcon_softc *sc, const char *name,
+    const char *path)
+{
+	struct pci_vtcon_sock *sock;
+	struct sockaddr_un sun;
+	char *pathcopy;
+	int s = -1, fd = -1, error = 0;
+
+	sock = calloc(1, sizeof(struct pci_vtcon_sock));
+	if (sock == NULL) {
+		error = -1;
+		goto out;
+	}
+
+	s = socket(AF_UNIX, SOCK_STREAM, 0);
+	if (s < 0) {
+		error = -1;
+		goto out;
+	}
+
+	pathcopy = strdup(path);
+	if (pathcopy == NULL) {
+		error = -1;
+		goto out;
+	}
+
+	fd = open(dirname(pathcopy), O_RDONLY | O_DIRECTORY);
+	if (fd < 0) {
+		free(pathcopy);
+		error = -1;
+		goto out;
+	}
+
+	sun.sun_family = AF_UNIX;
+	sun.sun_len = sizeof(struct sockaddr_un);
+	strcpy(pathcopy, path);
+	strncpy(sun.sun_path, basename(pathcopy), sizeof(sun.sun_path));
+	free(pathcopy);
+
+	if (bindat(fd, s, (struct sockaddr *)&sun, sun.sun_len) < 0) {
+		error = -1;
+		goto out;
+	}
+
+	if (fcntl(s, F_SETFL, O_NONBLOCK) < 0) {
+		error = -1;
+		goto out;
+	}
+
+	if (listen(s, 1) < 0) {
+		error = -1;
+		goto out;
+	}
+
+
+	sock->vss_port = pci_vtcon_port_add(sc, name, pci_vtcon_sock_tx, sock);
+	if (sock->vss_port == NULL) {
+		error = -1;
+		goto out;
+	}
+
+	sock->vss_open = false;
+	sock->vss_conn_fd = -1;
+	sock->vss_server_fd = s;
+	sock->vss_server_evp = mevent_add(s, EVF_READ, pci_vtcon_sock_accept,
+	    sock);
+
+	if (sock->vss_server_evp == NULL) {
+		error = -1;
+		goto out;
+	}
+
+out:
+	if (fd != -1)
+		close(fd);
+
+	if (error != 0 && s != -1)
+		close(s);
+
+	return (error);
+}
+
+static void
+pci_vtcon_sock_accept(int fd __unused, enum ev_type t __unused, void *arg)
+{
+	struct pci_vtcon_sock *sock = (struct pci_vtcon_sock *)arg;
+	int s;
+
+	s = accept(sock->vss_server_fd, NULL, NULL);
+	if (s < 0)
+		return;
+
+	if (sock->vss_open) {
+		close(s);
+		return;
+	}
+
+	sock->vss_open = true;
+	sock->vss_conn_fd = s;
+	sock->vss_conn_evp = mevent_add(s, EVF_READ, pci_vtcon_sock_rx, sock);
+	pci_vtcon_open_port(sock->vss_port, true);
+}
+
+static void
+pci_vtcon_sock_rx(int fd __unused, enum ev_type t __unused, void *arg)
+{
+	struct pci_vtcon_port *port;
+	struct pci_vtcon_sock *sock = (struct pci_vtcon_sock *)arg;
+	struct vqueue_info *vq;
+	struct iovec iov;
+	static char dummybuf[2048];
+	int len, n;
+	uint16_t idx;
+
+	port = sock->vss_port;
+	vq = pci_vtcon_port_to_vq(port, true);
+
+	if (!sock->vss_open || !port->vsp_rx_ready) {
+		len = read(sock->vss_conn_fd, dummybuf, sizeof(dummybuf));
+		if (len == 0)
+			goto close;
+
+		return;
+	}
+
+	if (!vq_has_descs(vq)) {
+		len = read(sock->vss_conn_fd, dummybuf, sizeof(dummybuf));
+		vq_endchains(vq, 1);
+		if (len == 0)
+			goto close;
+
+		return;
+	}
+
+	do {
+		n = vq_getchain(vq, &idx, &iov, 1, NULL);
+		len = readv(sock->vss_conn_fd, &iov, n);
+
+		if (len == 0 || (len < 0 && errno == EWOULDBLOCK)) {
+			vq_retchain(vq);
+			vq_endchains(vq, 0);
+			if (len == 0)
+				goto close;
+
+			return;
+		}
+
+		vq_relchain(vq, idx, len);
+	} while (vq_has_descs(vq));
+
+	vq_endchains(vq, 1);
+
+close:
+	mevent_delete_close(sock->vss_conn_evp);
+	sock->vss_conn_fd = -1;
+	sock->vss_open = false;
+}
+
+static void
+pci_vtcon_sock_tx(struct pci_vtcon_port *port, void *arg, struct iovec *iov,
+    int niov)
+{
+	struct pci_vtcon_sock *sock;
+	int ret;
+
+	sock = (struct pci_vtcon_sock *)arg;
+
+	if (sock->vss_conn_fd == -1)
+		return;
+
+	ret = writev(sock->vss_conn_fd, iov, niov);
+
+	if (ret < 0 && errno != EWOULDBLOCK) {
+		mevent_delete_close(sock->vss_conn_evp);
+		sock->vss_conn_fd = -1;
+		sock->vss_open = false;
+	}
+}
+
+static void
+pci_vtcon_control_tx(struct pci_vtcon_port *port, void *arg, struct iovec *iov,
+    int niov)
+{
+	struct pci_vtcon_softc *sc;
+	struct pci_vtcon_port *tmp;
+	struct pci_vtcon_control resp, *ctrl;
+	int i;
+
+	assert(niov == 1);
+
+	sc = port->vsp_sc;
+	ctrl = (struct pci_vtcon_control *)iov->iov_base;
+
+	switch (ctrl->event) {
+	case VTCON_DEVICE_READY:
+		/* set port ready events for registered ports */
+		for (i = 0; i < VTCON_MAXPORTS; i++) {
+			tmp = &sc->vsc_ports[i];
+			if (tmp->vsp_enabled)
+				pci_vtcon_announce_port(tmp);
+		}
+		break;
+
+	case VTCON_PORT_READY:
+		if (ctrl->id >= sc->vsc_nports) {
+			WPRINTF(("VTCON_PORT_READY event for unknown port %d\n",
+			    ctrl->id));
+			return;
+		}
+
+		tmp = &sc->vsc_ports[ctrl->id];
+		if (tmp->vsp_console) {
+			resp.event = VTCON_CONSOLE_PORT;
+			resp.id = ctrl->id;
+			resp.value = 1;
+			pci_vtcon_control_send(sc, &resp, NULL, 0);
+		}
+		break;
+	}
+}
+
+static void
+pci_vtcon_announce_port(struct pci_vtcon_port *port)
+{
+	struct pci_vtcon_control event;
+
+	event.id = port->vsp_id;
+	event.event = VTCON_DEVICE_ADD;
+	event.value = 1;
+	pci_vtcon_control_send(port->vsp_sc, &event, NULL, 0);
+
+	event.event = VTCON_PORT_NAME;
+	pci_vtcon_control_send(port->vsp_sc, &event, port->vsp_name,
+	    strlen(port->vsp_name));
+}
+
+static void
+pci_vtcon_open_port(struct pci_vtcon_port *port, bool open)
+{
+	struct pci_vtcon_control event;
+
+	event.id = port->vsp_id;
+	event.event = VTCON_PORT_OPEN;
+	event.value = (int)open;
+	pci_vtcon_control_send(port->vsp_sc, &event, NULL, 0);
+}
+
+static void
+pci_vtcon_control_send(struct pci_vtcon_softc *sc,
+    struct pci_vtcon_control *ctrl, const void *payload, size_t len)
+{
+	struct vqueue_info *vq;
+	struct iovec iov;
+	uint16_t idx;
+	int n;
+
+	vq = pci_vtcon_port_to_vq(&sc->vsc_control_port, true);
+
+	if (!vq_has_descs(vq))
+		return;
+
+	n = vq_getchain(vq, &idx, &iov, 1, NULL);
+
+	assert(n == 1);
+
+	memcpy(iov.iov_base, ctrl, sizeof(struct pci_vtcon_control));
+	if (payload != NULL && len > 0)
+		memcpy(iov.iov_base + sizeof(struct pci_vtcon_control),
+		     payload, len);
+
+	vq_relchain(vq, idx, sizeof(struct pci_vtcon_control) + len);
+	vq_endchains(vq, 1);
+}
+    
+
+static void
+pci_vtcon_notify_tx(void *vsc, struct vqueue_info *vq)
+{
+	struct pci_vtcon_softc *sc;
+	struct pci_vtcon_port *port;
+	struct iovec iov[1];
+	uint16_t idx, n;
+	uint16_t flags[8];
+
+	sc = vsc;
+	port = pci_vtcon_vq_to_port(sc, vq);
+
+	while (vq_has_descs(vq)) {
+		n = vq_getchain(vq, &idx, iov, 1, flags);
+		if (port != NULL)
+			port->vsp_cb(port, port->vsp_arg, iov, 1);
+
+		/*
+		 * Release this chain and handle more
+		 */
+		vq_relchain(vq, idx, 0);
+	}
+	vq_endchains(vq, 1);	/* Generate interrupt if appropriate. */
+}
+
+static void
+pci_vtcon_notify_rx(void *vsc, struct vqueue_info *vq)
+{
+	struct pci_vtcon_softc *sc;
+	struct pci_vtcon_port *port;
+
+	sc = vsc;
+	port = pci_vtcon_vq_to_port(sc, vq);
+
+	if (!port->vsp_rx_ready) {
+		port->vsp_rx_ready = 1;
+		vq->vq_used->vu_flags |= VRING_USED_F_NO_NOTIFY;
+	}
+}
+
+static int
+pci_vtcon_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
+{
+	struct pci_vtcon_softc *sc;
+	char *portname = NULL;
+	char *portpath = NULL;
+	char *opt;
+	int i;	
+
+	sc = calloc(1, sizeof(struct pci_vtcon_softc));
+	sc->vsc_config = calloc(1, sizeof(struct pci_vtcon_config));
+	sc->vsc_config->max_nr_ports = VTCON_MAXPORTS;
+	sc->vsc_config->cols = 80;
+	sc->vsc_config->rows = 25; 
+
+	vi_softc_linkup(&sc->vsc_vs, &vtcon_vi_consts, sc, pi, sc->vsc_queues);
+	sc->vsc_vs.vs_mtx = &sc->vsc_mtx;
+
+	for (i = 0; i < VTCON_MAXQ; i++) {
+		sc->vsc_queues[i].vq_qsize = VTCON_RINGSZ;
+		sc->vsc_queues[i].vq_notify = i % 2 == 0
+		    ? pci_vtcon_notify_rx
+		    : pci_vtcon_notify_tx;
+	}
+
+	/* initialize config space */
+	pci_set_cfgdata16(pi, PCIR_DEVICE, VIRTIO_DEV_CONSOLE);
+	pci_set_cfgdata16(pi, PCIR_VENDOR, VIRTIO_VENDOR);
+	pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SIMPLECOMM);
+	pci_set_cfgdata16(pi, PCIR_SUBDEV_0, VIRTIO_TYPE_CONSOLE);
+	pci_set_cfgdata16(pi, PCIR_SUBVEND_0, VIRTIO_VENDOR);
+
+	if (vi_intr_init(&sc->vsc_vs, 1, fbsdrun_virtio_msix()))
+		return (1);
+	vi_set_io_bar(&sc->vsc_vs, 0);
+
+	/* create control port */
+	sc->vsc_control_port.vsp_sc = sc;
+	sc->vsc_control_port.vsp_txq = 2;
+	sc->vsc_control_port.vsp_rxq = 3;
+	sc->vsc_control_port.vsp_cb = pci_vtcon_control_tx;
+	sc->vsc_control_port.vsp_enabled = true;
+
+	while ((opt = strsep(&opts, ",")) != NULL) {
+		portname = strsep(&opt, "=");
+		portpath = strdup(opt);
+
+		/* create port */
+		if (pci_vtcon_sock_add(sc, portname, portpath) < 0) {
+			fprintf(stderr, "cannot create port %s: %s\n",
+			    portname, strerror(errno));
+			return (1);
+		}
+	}
+
+	return (0);
+}
+
+struct pci_devemu pci_de_vcon = {
+	.pe_emu =	"virtio-console",
+	.pe_init =	pci_vtcon_init,
+	.pe_barwrite =	vi_pci_write,
+	.pe_barread =	vi_pci_read
+};
+PCI_EMUL_SET(pci_de_vcon);
diff --git a/usr.sbin/bhyve/virtio.h b/usr.sbin/bhyve/virtio.h
index 0e96a1d3b0c8..efb11f7f7003 100644
--- a/usr.sbin/bhyve/virtio.h
+++ b/usr.sbin/bhyve/virtio.h
@@ -210,6 +210,7 @@ struct vring_used {
 #define	VIRTIO_DEV_NET		0x1000
 #define	VIRTIO_DEV_BLOCK	0x1001
 #define	VIRTIO_DEV_RANDOM	0x1002
+#define	VIRTIO_DEV_CONSOLE	0x1003
 
 /*
  * PCI config space constants.
diff --git a/usr.sbin/bsnmpd/modules/snmp_hostres/Makefile b/usr.sbin/bsnmpd/modules/snmp_hostres/Makefile
index 57f3eab0d5f5..80349ca0414f 100644
--- a/usr.sbin/bsnmpd/modules/snmp_hostres/Makefile
+++ b/usr.sbin/bsnmpd/modules/snmp_hostres/Makefile
@@ -73,7 +73,7 @@ LIBADD=	kvm devinfo m geom memstat
 
 .include <bsd.snmpmod.mk>
 
-printcap.So: printcap.c
+printcap.pico: printcap.c
 	${CC} ${PICFLAG} -DPIC ${CFLAGS:C/^-W.*//} -c ${.IMPSRC} -o ${.TARGET}
 
 smilint:
diff --git a/usr.sbin/diskinfo/diskinfo.8 b/usr.sbin/diskinfo/diskinfo.8
index f68d426e6b49..c58f9be5cf9e 100644
--- a/usr.sbin/diskinfo/diskinfo.8
+++ b/usr.sbin/diskinfo/diskinfo.8
@@ -28,7 +28,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd November 9, 2004
+.Dd September 22, 2016
 .Dt DISKINFO 8
 .Os
 .Sh NAME
@@ -36,7 +36,7 @@
 .Nd get information about disk device
 .Sh SYNOPSIS
 .Nm
-.Op Fl ctv
+.Op Fl citv
 .Ar disk ...
 .Sh DESCRIPTION
 The
@@ -44,31 +44,34 @@ The
 utility prints out information about a disk device,
 and optionally runs a naive performance test on the device.
 .Pp
+The following options are available:
+.Bl -tag -width ".Fl v"
+.It Fl v
+Print fields one per line with a descriptive comment.
+.It Fl c
+Perform a simple measurement of the I/O read command overhead.
+.It Fl i
+Perform a simple IOPS benchmark.
+.It Fl t
+Perform a simple and rather naive benchmark of the disks seek
+and transfer performance.
+.El
+.Pp
 If given no arguments, the output will be a single line per specified device
 with the following fields: device name, sectorsize, media size in bytes,
 media size in sectors, stripe size, stripe offset, firmware cylinders,
 firmware heads, and firmware sectors.
 The last three fields are only present if the information is available.
-.Pp
-If given the
-.Fl v
-option, the fields will be printed one per line with a descriptive comment.
-.Pp
-The
-.Fl c
-option triggers a simple measurement of the I/O read command overhead.
-.Pp
-The
-.Fl t
-option triggers a simple and rather naive benchmark of the disks seek
-and transfer performance.
 .Sh HISTORY
 The
 .Nm
 command appeared in
 .Fx 5.1 .
 .Sh AUTHORS
-.An Poul-Henning Kamp
+The
+.Nm
+utility was written by
+.An Poul-Henning Kamp Aq Mt phk@FreeBSD.org .
 .Sh BUGS
 There are in order of increasing severity: lies,
 damn lies, statistics, and computer benchmarks.
diff --git a/usr.sbin/diskinfo/diskinfo.c b/usr.sbin/diskinfo/diskinfo.c
index 373b3fe719e5..df51aac2691e 100644
--- a/usr.sbin/diskinfo/diskinfo.c
+++ b/usr.sbin/diskinfo/diskinfo.c
@@ -40,27 +40,33 @@
 #include <libutil.h>
 #include <paths.h>
 #include <err.h>
+#include <sys/aio.h>
 #include <sys/disk.h>
 #include <sys/param.h>
+#include <sys/stat.h>
 #include <sys/time.h>
 
+#define	NAIO	128
+
 static void
 usage(void)
 {
-	fprintf(stderr, "usage: diskinfo [-ctv] disk ...\n");
+	fprintf(stderr, "usage: diskinfo [-citv] disk ...\n");
 	exit (1);
 }
 
-static int opt_c, opt_t, opt_v;
+static int opt_c, opt_i, opt_t, opt_v;
 
 static void speeddisk(int fd, off_t mediasize, u_int sectorsize);
 static void commandtime(int fd, off_t mediasize, u_int sectorsize);
+static void iopsbench(int fd, off_t mediasize, u_int sectorsize);
 static int zonecheck(int fd, uint32_t *zone_mode, char *zone_str,
 		     size_t zone_str_len);
 
 int
 main(int argc, char **argv)
 {
+	struct stat sb;
 	int i, ch, fd, error, exitval = 0;
 	char buf[BUFSIZ], ident[DISK_IDENT_SIZE], physpath[MAXPATHLEN];
 	char zone_desc[64];
@@ -68,12 +74,16 @@ main(int argc, char **argv)
 	u_int	sectorsize, fwsectors, fwheads, zoned = 0;
 	uint32_t zone_mode;
 
-	while ((ch = getopt(argc, argv, "ctv")) != -1) {
+	while ((ch = getopt(argc, argv, "citv")) != -1) {
 		switch (ch) {
 		case 'c':
 			opt_c = 1;
 			opt_v = 1;
 			break;
+		case 'i':
+			opt_i = 1;
+			opt_v = 1;
+			break;
 		case 't':
 			opt_t = 1;
 			opt_v = 1;
@@ -92,7 +102,7 @@ main(int argc, char **argv)
 		usage();
 
 	for (i = 0; i < argc; i++) {
-		fd = open(argv[i], O_RDONLY);
+		fd = open(argv[i], O_RDONLY | O_DIRECT);
 		if (fd < 0 && errno == ENOENT && *argv[i] != '/') {
 			sprintf(buf, "%s%s", _PATH_DEV, argv[i]);
 			fd = open(buf, O_RDONLY);
@@ -102,33 +112,48 @@ main(int argc, char **argv)
 			exitval = 1;
 			goto out;
 		}
-		error = ioctl(fd, DIOCGMEDIASIZE, &mediasize);
-		if (error) {
-			warnx("%s: ioctl(DIOCGMEDIASIZE) failed, probably not a disk.", argv[i]);
+		error = fstat(fd, &sb);
+		if (error != 0) {
+			warn("cannot stat %s", argv[i]);
 			exitval = 1;
 			goto out;
 		}
-		error = ioctl(fd, DIOCGSECTORSIZE, &sectorsize);
-		if (error) {
-			warnx("%s: ioctl(DIOCGSECTORSIZE) failed, probably not a disk.", argv[i]);
-			exitval = 1;
-			goto out;
-		}
-		error = ioctl(fd, DIOCGFWSECTORS, &fwsectors);
-		if (error)
+		if (S_ISREG(sb.st_mode)) {
+			mediasize = sb.st_size;
+			sectorsize = S_BLKSIZE;
 			fwsectors = 0;
-		error = ioctl(fd, DIOCGFWHEADS, &fwheads);
-		if (error)
 			fwheads = 0;
-		error = ioctl(fd, DIOCGSTRIPESIZE, &stripesize);
-		if (error)
-			stripesize = 0;
-		error = ioctl(fd, DIOCGSTRIPEOFFSET, &stripeoffset);
-		if (error)
+			stripesize = sb.st_blksize;
 			stripeoffset = 0;
-		error = zonecheck(fd, &zone_mode, zone_desc, sizeof(zone_desc));
-		if (error == 0)
-			zoned = 1;
+		} else {
+			error = ioctl(fd, DIOCGMEDIASIZE, &mediasize);
+			if (error) {
+				warnx("%s: ioctl(DIOCGMEDIASIZE) failed, probably not a disk.", argv[i]);
+				exitval = 1;
+				goto out;
+			}
+			error = ioctl(fd, DIOCGSECTORSIZE, &sectorsize);
+			if (error) {
+				warnx("%s: ioctl(DIOCGSECTORSIZE) failed, probably not a disk.", argv[i]);
+				exitval = 1;
+				goto out;
+			}
+			error = ioctl(fd, DIOCGFWSECTORS, &fwsectors);
+			if (error)
+				fwsectors = 0;
+			error = ioctl(fd, DIOCGFWHEADS, &fwheads);
+			if (error)
+				fwheads = 0;
+			error = ioctl(fd, DIOCGSTRIPESIZE, &stripesize);
+			if (error)
+				stripesize = 0;
+			error = ioctl(fd, DIOCGSTRIPEOFFSET, &stripeoffset);
+			if (error)
+				stripeoffset = 0;
+			error = zonecheck(fd, &zone_mode, zone_desc, sizeof(zone_desc));
+			if (error == 0)
+				zoned = 1;
+		}
 		if (!opt_v) {
 			printf("%s", argv[i]);
 			printf("\t%u", sectorsize);
@@ -171,6 +196,8 @@ main(int argc, char **argv)
 			commandtime(fd, mediasize, sectorsize);
 		if (opt_t)
 			speeddisk(fd, mediasize, sectorsize);
+		if (opt_i)
+			iopsbench(fd, mediasize, sectorsize);
 out:
 		close(fd);
 	}
@@ -220,14 +247,24 @@ T0(void)
 	gettimeofday(&tv1, NULL);
 }
 
-static void
-TN(int count)
+static double
+delta_t(void)
 {
 	double dt;
 
 	gettimeofday(&tv2, NULL);
 	dt = (tv2.tv_usec - tv1.tv_usec) / 1e6;
 	dt += (tv2.tv_sec - tv1.tv_sec);
+
+	return (dt);
+}
+
+static void
+TN(int count)
+{
+	double dt;
+
+	dt = delta_t();
 	printf("%5d iter in %10.6f sec = %8.3f msec\n",
 		count, dt, dt * 1000.0 / count);
 }
@@ -237,14 +274,22 @@ TR(double count)
 {
 	double dt;
 
-	gettimeofday(&tv2, NULL);
-	dt = (tv2.tv_usec - tv1.tv_usec) / 1e6;
-	dt += (tv2.tv_sec - tv1.tv_sec);
+	dt = delta_t();
 	printf("%8.0f kbytes in %10.6f sec = %8.0f kbytes/sec\n",
 		count, dt, count / dt);
 }
 
 static void
+TI(double count)
+{
+	double dt;
+
+	dt = delta_t();
+	printf("%8.0f ops in  %10.6f sec = %8.0f IOPS\n",
+		count, dt, count / dt);
+}
+
+static void
 speeddisk(int fd, off_t mediasize, u_int sectorsize)
 {
 	int bulk, i;
@@ -330,7 +375,7 @@ speeddisk(int fd, off_t mediasize, u_int sectorsize)
 	}
 	TN(2048);
 
-	printf("Transfer rates:\n");
+	printf("\nTransfer rates:\n");
 	printf("\toutside:     ");
 	rdsect(fd, 0, sectorsize);
 	T0();
@@ -373,9 +418,7 @@ commandtime(int fd, off_t mediasize, u_int sectorsize)
 	T0();
 	for (i = 0; i < 10; i++)
 		rdmega(fd);
-	gettimeofday(&tv2, NULL);
-	dtmega = (tv2.tv_usec - tv1.tv_usec) / 1e6;
-	dtmega += (tv2.tv_sec - tv1.tv_sec);
+	dtmega = delta_t();
 
 	printf("\ttime to read 10MB block    %10.6f sec\t= %8.3f msec/sector\n",
 		dtmega, dtmega*100/2048);
@@ -384,9 +427,7 @@ commandtime(int fd, off_t mediasize, u_int sectorsize)
 	T0();
 	for (i = 0; i < 20480; i++)
 		rdsect(fd, 0, sectorsize);
-	gettimeofday(&tv2, NULL);
-	dtsector = (tv2.tv_usec - tv1.tv_usec) / 1e6;
-	dtsector += (tv2.tv_sec - tv1.tv_sec);
+	dtsector = delta_t();
 
 	printf("\ttime to read 20480 sectors %10.6f sec\t= %8.3f msec/sector\n",
 		dtsector, dtsector*100/2048);
@@ -397,6 +438,91 @@ commandtime(int fd, off_t mediasize, u_int sectorsize)
 	return;
 }
 
+static void
+iops(int fd, off_t mediasize, u_int sectorsize)
+{
+	struct aiocb aios[NAIO], *aiop;
+	ssize_t ret;
+	off_t sectorcount;
+	int error, i, queued, completed;
+
+	sectorcount = mediasize / sectorsize;
+
+	for (i = 0; i < NAIO; i++) {
+		aiop = &(aios[i]);
+		bzero(aiop, sizeof(*aiop));
+		aiop->aio_buf = malloc(sectorsize);
+		if (aiop->aio_buf == NULL)
+			err(1, "malloc");
+	}
+
+	T0();
+	for (i = 0; i < NAIO; i++) {
+		aiop = &(aios[i]);
+
+		aiop->aio_fildes = fd;
+		aiop->aio_offset = (random() % (sectorcount)) * sectorsize;
+		aiop->aio_nbytes = sectorsize;
+
+		error = aio_read(aiop);
+		if (error != 0)
+			err(1, "aio_read");
+	}
+
+	queued = i;
+	completed = 0;
+
+	for (;;) {
+		ret = aio_waitcomplete(&aiop, NULL);
+		if (ret < 0)
+			err(1, "aio_waitcomplete");
+		if (ret != (ssize_t)sectorsize)
+			errx(1, "short read");
+
+		completed++;
+
+		if (delta_t() < 3.0) {
+			aiop->aio_fildes = fd;
+			aiop->aio_offset = (random() % (sectorcount)) * sectorsize;
+			aiop->aio_nbytes = sectorsize;
+
+			error = aio_read(aiop);
+			if (error != 0)
+				err(1, "aio_read");
+
+			queued++;
+		} else if (completed == queued) {
+			break;
+		}
+	}
+
+	TI(completed);
+
+	return;
+}
+
+static void
+iopsbench(int fd, off_t mediasize, u_int sectorsize)
+{
+	printf("Asynchronous random reads:\n");
+
+	printf("\tsectorsize:  ");
+	iops(fd, mediasize, sectorsize);
+
+	if (sectorsize != 4096) {
+		printf("\t4 kbytes:    ");
+		iops(fd, mediasize, 4096);
+	}
+
+	printf("\t32 kbytes:   ");
+	iops(fd, mediasize, 32 * 1024);
+
+	printf("\t128 kbytes:  ");
+	iops(fd, mediasize, 128 * 1024);
+
+	printf("\n");
+}
+
 static int
 zonecheck(int fd, uint32_t *zone_mode, char *zone_str, size_t zone_str_len)
 {
diff --git a/usr.sbin/extattr/tests/extattr_test.sh b/usr.sbin/extattr/tests/extattr_test.sh
index 33d0a82f69b7..303abe190605 100755
--- a/usr.sbin/extattr/tests/extattr_test.sh
+++ b/usr.sbin/extattr/tests/extattr_test.sh
@@ -355,7 +355,11 @@ atf_init_test_cases() {
 
 check_fs() {
 	case `df -T . | tail -n 1 | cut -wf 2` in
-		"ufs") ;; # UFS is fine
+		"ufs")
+		case `dumpfs . | head -1 | awk -F'[()]' '{print $2}'` in
+			"UFS1") atf_skip "UFS1 is not supported by this test";;
+			"UFS2") ;; # UFS2 is fine
+		esac ;;
 		"zfs") ;; # ZFS is fine
 		"tmpfs") atf_skip "tmpfs does not support extended attributes";;
 	esac
diff --git a/usr.sbin/freebsd-update/freebsd-update.sh b/usr.sbin/freebsd-update/freebsd-update.sh
index 000c80e7b3c0..9537c3214690 100644
--- a/usr.sbin/freebsd-update/freebsd-update.sh
+++ b/usr.sbin/freebsd-update/freebsd-update.sh
@@ -2380,7 +2380,7 @@ upgrade_merge () {
 				cp merge/old/${F} merge/new/${F}
 				;;
 			*)
-				if ! merge -p -L "current version"	\
+				if ! diff3 -E -m -L "current version"	\
 				    -L "${OLDRELNUM}" -L "${RELNUM}"	\
 				    merge/old/${F}			\
 				    merge/${OLDRELNUM}/${F}		\
diff --git a/usr.sbin/iostat/iostat.c b/usr.sbin/iostat/iostat.c
index e9229e94aa3c..69882f15f5a6 100644
--- a/usr.sbin/iostat/iostat.c
+++ b/usr.sbin/iostat/iostat.c
@@ -807,7 +807,7 @@ devstats(int perf_select, long double etime, int havelast)
 			printf("           cpu ");
 		printf("\n");
 		if (Iflag == 0) {
-			printf("device     r/s   w/s     kr/s     kw/s "
+			printf("device       r/s     w/s     kr/s     kw/s "
 			    " ms/r  ms/w  ms/o  ms/t qlen  %%b  ");
 		} else {
 			printf("device           r/i         w/i         kr/i"
@@ -884,7 +884,7 @@ devstats(int perf_select, long double etime, int havelast)
 			    mb_per_second_write > ((long double).0005)/1024 ||
 			    busy_pct > 0.5) {
 				if (Iflag == 0)
-					printf("%-8.8s %5d %5d %8.1Lf "
+					printf("%-8.8s %7d %7d %8.1Lf "
 					    "%8.1Lf %5d %5d %5d %5d "
 					    "%4" PRIu64 " %3.0Lf ",
 					    devicename,
diff --git a/usr.sbin/uefisign/child.c b/usr.sbin/uefisign/child.c
index 7dfc21108e75..c8f5e4c277dc 100644
--- a/usr.sbin/uefisign/child.c
+++ b/usr.sbin/uefisign/child.c
@@ -32,11 +32,7 @@
 __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
-#if __FreeBSD_version >= 1100000
 #include <sys/capsicum.h>
-#else
-#include <sys/capability.h>
-#endif
 #include <sys/types.h>
 #include <sys/stat.h>
 #include <assert.h>