Remove arm1136 support. We don't have any configs that use it, and I don't

expect us to add support for any more arm11 SoCs.

6 files changed, 14 insertions, 109 deletions

diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index e629d2a131bc..9d9dc2d69c82 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -557,69 +557,6 @@ struct cpu_functions fa526_cpufuncs = {
 };
 #endif	/* CPU_FA526 || CPU_FA626TE */
 
-#if defined(CPU_ARM1136)
-struct cpu_functions arm1136_cpufuncs = {
-	/* CPU functions */
-	
-	cpufunc_id,                     /* id                   */
-	cpufunc_nullop,                 /* cpwait               */
-	
-	/* MMU functions */
-	
-	cpufunc_control,                /* control              */
-	cpufunc_domains,                /* Domain               */
-	arm11x6_setttb,                 /* Setttb               */
-	cpufunc_faultstatus,            /* Faultstatus          */
-	cpufunc_faultaddress,           /* Faultaddress         */
-	
-	/* TLB functions */
-	
-	arm11_tlb_flushID,              /* tlb_flushID          */
-	arm11_tlb_flushID_SE,           /* tlb_flushID_SE       */
-	arm11_tlb_flushI,               /* tlb_flushI           */
-	arm11_tlb_flushI_SE,            /* tlb_flushI_SE        */
-	arm11_tlb_flushD,               /* tlb_flushD           */
-	arm11_tlb_flushD_SE,            /* tlb_flushD_SE        */
-	
-	/* Cache operations */
-	
-	arm11x6_icache_sync_all,        /* icache_sync_all      */
-	arm11x6_icache_sync_range,      /* icache_sync_range    */
-	
-	arm11x6_dcache_wbinv_all,       /* dcache_wbinv_all     */
-	armv6_dcache_wbinv_range,       /* dcache_wbinv_range   */
-	armv6_dcache_inv_range,         /* dcache_inv_range     */
-	armv6_dcache_wb_range,          /* dcache_wb_range      */
-	
-	armv6_idcache_inv_all,		/* idcache_inv_all	*/
-	arm11x6_idcache_wbinv_all,      /* idcache_wbinv_all    */
-	arm11x6_idcache_wbinv_range,    /* idcache_wbinv_range  */
-	
-	(void *)cpufunc_nullop,         /* l2cache_wbinv_all    */
-	(void *)cpufunc_nullop,         /* l2cache_wbinv_range  */
-	(void *)cpufunc_nullop,         /* l2cache_inv_range    */
-	(void *)cpufunc_nullop,         /* l2cache_wb_range     */
-	(void *)cpufunc_nullop,         /* l2cache_drain_writebuf */
-	
-	/* Other functions */
-	
-	arm11x6_flush_prefetchbuf,      /* flush_prefetchbuf    */
-	arm11_drain_writebuf,           /* drain_writebuf       */
-	cpufunc_nullop,                 /* flush_brnchtgt_C     */
-	(void *)cpufunc_nullop,         /* flush_brnchtgt_E     */
-	
-	arm11_sleep,                  	/* sleep                */
-	
-	/* Soft functions */
-	
-	cpufunc_null_fixup,             /* dataabt_fixup        */
-	cpufunc_null_fixup,             /* prefetchabt_fixup    */
-	
-	arm11_context_switch,           /* context_switch       */
-	
-	arm11x6_setup                   /* cpu setup            */
-};
-#endif /* CPU_ARM1136 */
 #if defined(CPU_ARM1176)
 struct cpu_functions arm1176_cpufuncs = {
 	/* CPU functions */
@@ -765,7 +702,7 @@ u_int cputype;
 u_int cpu_reset_needs_v4_MMU_disable;	/* flag used in locore.s */
 
 #if defined(CPU_ARM9) ||	\
-  defined (CPU_ARM9E) || defined (CPU_ARM1136) ||	\
+  defined (CPU_ARM9E) ||	\
   defined(CPU_ARM1176) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
   defined(CPU_FA526) || defined(CPU_FA626TE) || defined(CPU_MV_PJ4B) ||			\
@@ -959,19 +896,8 @@ set_cpufuncs()
 		goto out;
 	}
 #endif /* CPU_ARM9E */
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
-	if (cputype == CPU_ID_ARM1136JS
-	    || cputype == CPU_ID_ARM1136JSR1
-	    || cputype == CPU_ID_ARM1176JZS) {
-#ifdef CPU_ARM1136
-		if (cputype == CPU_ID_ARM1136JS
-		    || cputype == CPU_ID_ARM1136JSR1)
-			cpufuncs = arm1136_cpufuncs;
-#endif
-#ifdef CPU_ARM1176
-		if (cputype == CPU_ID_ARM1176JZS)
-			cpufuncs = arm1176_cpufuncs;
-#endif
+#if defined(CPU_ARM1176)
+	if (cputype == CPU_ID_ARM1176JZS) {
 		cpu_reset_needs_v4_MMU_disable = 1;     /* V4 or higher */
 		get_cachetype_cp15();
 
@@ -979,7 +905,7 @@ set_cpufuncs()
 
 		goto out;
 	}
-#endif /* CPU_ARM1136 || CPU_ARM1176 */
+#endif /* CPU_ARM1176 */
 #if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
 	if (cputype == CPU_ID_CORTEXA5 ||
 	    cputype == CPU_ID_CORTEXA7 ||
@@ -1238,7 +1164,7 @@ arm10_setup(void)
 }
 #endif	/* CPU_ARM9E || CPU_ARM10 */
 
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \
+#if defined(CPU_ARM1176) \
  || defined(CPU_MV_PJ4B) \
  || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
 static __inline void
@@ -1250,7 +1176,7 @@ cpu_scc_setup_ccnt(void)
  * you want!
  */
 #ifdef _PMC_USER_READ_WRITE_
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+#if defined(CPU_ARM1176)
 	/* Use the Secure User and Non-secure Access Validation Control Register
 	 * to allow userland access
 	 */
@@ -1264,7 +1190,7 @@ cpu_scc_setup_ccnt(void)
 			: "r"(0x00000001));
 #endif
 #endif
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+#if defined(CPU_ARM1176)
 	/* Set PMCR[2,0] to enable counters and reset CCNT */
 	__asm volatile ("mcr	p15, 0, %0, c15, c12, 0\n\t"
 			:
@@ -1285,7 +1211,7 @@ cpu_scc_setup_ccnt(void)
 }
 #endif
 
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+#if defined(CPU_ARM1176)
 void
 arm11x6_setup(void)
 {
@@ -1331,20 +1257,6 @@ arm11x6_setup(void)
 
 	auxctrl = 0;
 	auxctrl_wax = ~0;
-	/*
-	 * This options enables the workaround for the 364296 ARM1136
-	 * r0pX errata (possible cache data corruption with
-	 * hit-under-miss enabled). It sets the undocumented bit 31 in
-	 * the auxiliary control register and the FI bit in the control
-	 * register, thus disabling hit-under-miss without putting the
-	 * processor into full low interrupt latency mode. ARM11MPCore
-	 * is not affected.
-	 */
-	if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1136JS) { /* ARM1136JSr0pX */
-		cpuctrl |= CPU_CONTROL_FI_ENABLE;
-		auxctrl = ARM1136_AUXCTL_PFI;
-		auxctrl_wax = ~ARM1136_AUXCTL_PFI;
-	}
 
 	/*
 	 * Enable an errata workaround
@@ -1380,7 +1292,7 @@ arm11x6_setup(void)
 
 	cpu_scc_setup_ccnt();
 }
-#endif  /* CPU_ARM1136 || CPU_ARM1176 */
+#endif  /* CPU_ARM1176 */
 
 #ifdef CPU_MV_PJ4B
 void
diff --git a/sys/arm/arm/elf_trampoline.c b/sys/arm/arm/elf_trampoline.c
index 9c7497c00a6e..a651ae08ff0d 100644
--- a/sys/arm/arm/elf_trampoline.c
+++ b/sys/arm/arm/elf_trampoline.c
@@ -65,7 +65,7 @@ extern void fa526_idcache_wbinv_all(void);
 #elif defined(CPU_ARM9E)
 #define cpu_idcache_wbinv_all	armv5_ec_idcache_wbinv_all
 extern void armv5_ec_idcache_wbinv_all(void);
-#elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
+#elif defined(CPU_ARM1176)
 #define cpu_idcache_wbinv_all	armv6_idcache_wbinv_all
 #elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
diff --git a/sys/arm/include/cpuconf.h b/sys/arm/include/cpuconf.h
index fb021539caed..2015e6efdab5 100644
--- a/sys/arm/include/cpuconf.h
+++ b/sys/arm/include/cpuconf.h
@@ -52,8 +52,6 @@
  */
 #define	CPU_NTYPES	(defined(CPU_ARM9) +				\
 			 defined(CPU_ARM9E) +				\
-			 defined(CPU_ARM10) +				\
-			 defined(CPU_ARM1136) +				\
 			 defined(CPU_ARM1176) +				\
 			 defined(CPU_XSCALE_80200) +			\
 			 defined(CPU_XSCALE_80321) +			\
@@ -85,7 +83,7 @@
 #endif
 
 #if !defined(ARM_ARCH_6)
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+#if defined(CPU_ARM1176)
 #define ARM_ARCH_6	1
 #else
 #define ARM_ARCH_6	0
@@ -158,7 +156,7 @@
 #define	ARM_MMU_GENERIC		0
 #endif
 
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+#if defined(CPU_ARM1176)
 #define ARM_MMU_V6		1
 #else
 #define ARM_MMU_V6		0
diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index 0ea26df953b9..1fe3661a56b4 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -386,7 +386,7 @@ void	armadaxp_idcache_wbinv_all	(void);
 void 	cortexa_setup			(void);
 #endif
 
-#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+#if defined(CPU_ARM1176)
 void	arm11_tlb_flushID	(void);
 void	arm11_tlb_flushID_SE	(u_int);
 void	arm11_tlb_flushI	(void);
@@ -414,10 +414,6 @@ void    arm11x6_idcache_wbinv_range     (vm_offset_t, vm_size_t);
 void    arm11x6_setup                   (void);
 void    arm11x6_sleep                   (int);  /* no ref. for errata */
 #endif
-#if defined(CPU_ARM1136)
-void	arm11_sleep		(int);
-void    arm1136_sleep_rev0              (int);  /* for errata 336501 */
-#endif
 
 #if defined(CPU_ARM9E)
 void	armv5_ec_setttb(u_int);
diff --git a/sys/arm/include/intr.h b/sys/arm/include/intr.h
index c58ee3e98b2e..7ab69d9405a0 100644
--- a/sys/arm/include/intr.h
+++ b/sys/arm/include/intr.h
@@ -58,7 +58,7 @@
 #define NIRQ		1020
 #elif defined(CPU_KRAIT)
 #define NIRQ		288
-#elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
+#elif defined(CPU_ARM1176)
 #define NIRQ		128
 #elif defined(SOC_MV_ARMADAXP)
 #define MAIN_IRQ_NUM		116
diff --git a/sys/conf/options.arm b/sys/conf/options.arm
index 58b0875fec90..93b140b2dc24 100644
--- a/sys/conf/options.arm
+++ b/sys/conf/options.arm
@@ -10,7 +10,6 @@ ARM_WANT_TP_ADDRESS	opt_global.h
 COUNTS_PER_SEC		opt_timer.h
 CPU_ARM9		opt_global.h
 CPU_ARM9E		opt_global.h
-CPU_ARM1136		opt_global.h
 CPU_ARM1176		opt_global.h
 CPU_CORTEXA		opt_global.h
 CPU_KRAIT		opt_global.h