diff options
| author | Marcin Wojtas <mw@FreeBSD.org> | 2021-01-26 10:49:35 +0000 |
|---|---|---|
| committer | Marcin Wojtas <mw@FreeBSD.org> | 2021-01-26 13:04:22 +0000 |
| commit | a86b0839d7bf3fc06b1ae9c50e055b53c50a9d0b (patch) | |
| tree | b2937f933fb3170b1c45cd455009ef9daa519d64 | |
| parent | 6943671b481e571f2f1ffbe407a4d75241d1174e (diff) | |
| download | src-a86b0839d7bf3fc06b1ae9c50e055b53c50a9d0b.tar.gz src-a86b0839d7bf3fc06b1ae9c50e055b53c50a9d0b.zip | |
marvell: ap806_clock: add missing frequency modes
In the driver init routine the CPU clock frequency
value is obtained from a dedicated register. Until now
only part of the values were handled by the mv_ap806_clock
driver. Fix that by adding missing cases.
Submitted by: Zyta Szpak <zr@semihalf.com>
MFC after: 1 week
Obtained from: Semihalf
Sponsored by: Marvell
| -rw-r--r-- | sys/arm/mv/mv_ap806_clock.c | 34 |
1 files changed, 30 insertions, 4 deletions
diff --git a/sys/arm/mv/mv_ap806_clock.c b/sys/arm/mv/mv_ap806_clock.c index 378640633c03..56041a48d312 100644 --- a/sys/arm/mv/mv_ap806_clock.c +++ b/sys/arm/mv/mv_ap806_clock.c @@ -136,25 +136,51 @@ mv_ap806_clock_attach(device_t dev) return (ENXIO); } - /* - * We might miss some combinations - * Those are the only possible ones on the mcbin - */ reg = RD4(sc, 0x400); switch (reg & 0x1f) { case 0x0: case 0x1: clock_freq = 2000000000; break; + case 0x4: + clock_freq = 1600000000; + break; case 0x6: clock_freq = 1800000000; break; + case 0x7: + clock_freq = 1800000000; + break; + case 0xb: + clock_freq = 1600000000; + break; case 0xd: clock_freq = 1600000000; break; + case 0x13: + clock_freq = 1000000000; + break; case 0x14: clock_freq = 1333000000; break; + case 0x17: + clock_freq = 1333000000; + break; + case 0x19: + clock_freq = 1200000000; + break; + case 0x1a: + clock_freq = 1400000000; + break; + case 0x1b: + clock_freq = 600000000; + break; + case 0x1c: + clock_freq = 800000000; + break; + case 0x1d: + clock_freq = 1000000000; + break; default: device_printf(dev, "Cannot guess clock freq with reg %x\n", reg & 0x1f); |