Revert 287914,287762.

Reports of breakage on igb(4) have been narrowed down to 287762 and 287914
is an dependant change.

Submitted by:	erj

26 files changed, 381 insertions, 1428 deletions

diff --git a/sys/dev/e1000/e1000_80003es2lan.c b/sys/dev/e1000/e1000_80003es2lan.c
index e7c42d5386eb..b948bb4e3198 100644
--- a/sys/dev/e1000/e1000_80003es2lan.c
+++ b/sys/dev/e1000/e1000_80003es2lan.c
@@ -851,17 +851,11 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 	e1000_release_phy_80003es2lan(hw);
 
 	/* Disable IBIST slave mode (far-end loopback) */
-	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
-				E1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data);
-	if (!ret_val) {
-		kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
-		ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-						 E1000_KMRNCTRLSTA_INBAND_PARAM,
-						 kum_reg_data);
-		if (ret_val)
-			DEBUGOUT("Error disabling far-end loopback\n");
-	} else
-		DEBUGOUT("Error disabling far-end loopback\n");
+	e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
+					&kum_reg_data);
+	kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
+	e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
+					kum_reg_data);
 
 	ret_val = e1000_get_auto_rd_done_generic(hw);
 	if (ret_val)
@@ -917,18 +911,11 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 		return ret_val;
 
 	/* Disable IBIST slave mode (far-end loopback) */
-	ret_val =
-	    e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
-					    &kum_reg_data);
-	if (!ret_val) {
-		kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
-		ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-						 E1000_KMRNCTRLSTA_INBAND_PARAM,
-						 kum_reg_data);
-		if (ret_val)
-			DEBUGOUT("Error disabling far-end loopback\n");
-	} else
-		DEBUGOUT("Error disabling far-end loopback\n");
+	e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
+					&kum_reg_data);
+	kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
+	e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
+					 kum_reg_data);
 
 	/* Set the transmit descriptor write-back policy */
 	reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
diff --git a/sys/dev/e1000/e1000_82540.c b/sys/dev/e1000/e1000_82540.c
index 2d03b8ff8e3f..68f92c619afe 100644
--- a/sys/dev/e1000/e1000_82540.c
+++ b/sys/dev/e1000/e1000_82540.c
@@ -66,7 +66,7 @@ static s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
 {
 	struct e1000_phy_info *phy = &hw->phy;
-	s32 ret_val;
+	s32 ret_val = E1000_SUCCESS;
 
 	phy->addr		= 1;
 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
@@ -329,7 +329,7 @@ static s32 e1000_init_hw_82540(struct e1000_hw *hw)
 {
 	struct e1000_mac_info *mac = &hw->mac;
 	u32 txdctl, ctrl_ext;
-	s32 ret_val;
+	s32 ret_val = E1000_SUCCESS;
 	u16 i;
 
 	DEBUGFUNC("e1000_init_hw_82540");
@@ -411,7 +411,7 @@ static s32 e1000_init_hw_82540(struct e1000_hw *hw)
 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
 {
 	u32 ctrl;
-	s32 ret_val;
+	s32 ret_val = E1000_SUCCESS;
 	u16 data;
 
 	DEBUGFUNC("e1000_setup_copper_link_82540");
@@ -498,7 +498,7 @@ out:
  **/
 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
 {
-	s32 ret_val;
+	s32 ret_val = E1000_SUCCESS;
 	u16 nvm_data;
 
 	DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
@@ -528,7 +528,7 @@ out:
  **/
 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
 {
-	s32  ret_val;
+	s32  ret_val = E1000_SUCCESS;
 	u16 default_page = 0;
 	u16 phy_data;
 
diff --git a/sys/dev/e1000/e1000_82541.c b/sys/dev/e1000/e1000_82541.c
index 55d51087b7b3..59615556fa32 100644
--- a/sys/dev/e1000/e1000_82541.c
+++ b/sys/dev/e1000/e1000_82541.c
@@ -85,7 +85,7 @@ static const u16 e1000_igp_cable_length_table[] = {
 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
 {
 	struct e1000_phy_info *phy = &hw->phy;
-	s32 ret_val;
+	s32 ret_val = E1000_SUCCESS;
 
 	DEBUGFUNC("e1000_init_phy_params_82541");
 
@@ -295,7 +295,7 @@ void e1000_init_function_pointers_82541(struct e1000_hw *hw)
  **/
 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 {
-	u32 ledctl, ctrl, manc;
+	u32 ledctl, ctrl, icr, manc;
 
 	DEBUGFUNC("e1000_reset_hw_82541");
 
@@ -317,7 +317,6 @@ static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 	/* Must reset the Phy before resetting the MAC */
 	if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
-		E1000_WRITE_FLUSH(hw);
 		msec_delay(5);
 	}
 
@@ -360,7 +359,7 @@ static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 
 	/* Clear any pending interrupt events. */
-	E1000_READ_REG(hw, E1000_ICR);
+	icr = E1000_READ_REG(hw, E1000_ICR);
 
 	return E1000_SUCCESS;
 }
diff --git a/sys/dev/e1000/e1000_82542.c b/sys/dev/e1000/e1000_82542.c
index 4cca9b2b2c61..b2d676eca8c5 100644
--- a/sys/dev/e1000/e1000_82542.c
+++ b/sys/dev/e1000/e1000_82542.c
@@ -317,7 +317,7 @@ static s32 e1000_init_hw_82542(struct e1000_hw *hw)
 static s32 e1000_setup_link_82542(struct e1000_hw *hw)
 {
 	struct e1000_mac_info *mac = &hw->mac;
-	s32 ret_val;
+	s32 ret_val = E1000_SUCCESS;
 
 	DEBUGFUNC("e1000_setup_link_82542");
 
@@ -565,7 +565,7 @@ static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
  *
  *  Reads the device MAC address from the EEPROM and stores the value.
  **/
-s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
+static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
 {
 	s32  ret_val = E1000_SUCCESS;
 	u16 offset, nvm_data, i;
diff --git a/sys/dev/e1000/e1000_82543.c b/sys/dev/e1000/e1000_82543.c
index 474387d2cb75..b9a53bd6081c 100644
--- a/sys/dev/e1000/e1000_82543.c
+++ b/sys/dev/e1000/e1000_82543.c
@@ -900,7 +900,7 @@ static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
  **/
 static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
 {
-	u32 ctrl;
+	u32 ctrl, icr;
 	s32 ret_val = E1000_SUCCESS;
 
 	DEBUGFUNC("e1000_reset_hw_82543");
@@ -942,7 +942,7 @@ static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
 
 	/* Masking off and clearing any pending interrupts */
 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
-	E1000_READ_REG(hw, E1000_ICR);
+	icr = E1000_READ_REG(hw, E1000_ICR);
 
 	return ret_val;
 }
diff --git a/sys/dev/e1000/e1000_82571.h b/sys/dev/e1000/e1000_82571.h
index 8e5ca56ae88c..1d7718eda12c 100644
--- a/sys/dev/e1000/e1000_82571.h
+++ b/sys/dev/e1000/e1000_82571.h
@@ -50,10 +50,9 @@
 #define E1000_EIAC_82574	0x000DC /* Ext. Interrupt Auto Clear - RW */
 #define E1000_EIAC_MASK_82574	0x01F00000
 
-#define E1000_IVAR_INT_ALLOC_VALID	0x8
+#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
 
-/* Manageability Operation Mode mask */
-#define E1000_NVM_INIT_CTRL2_MNGM	0x6000
+#define E1000_RXCFGL    0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */
 
 #define E1000_BASE1000T_STATUS		10
 #define E1000_IDLE_ERROR_COUNT_MASK	0xFF
diff --git a/sys/dev/e1000/e1000_82575.c b/sys/dev/e1000/e1000_82575.c
index 04afc7493e34..10653f8824c8 100644
--- a/sys/dev/e1000/e1000_82575.c
+++ b/sys/dev/e1000/e1000_82575.c
@@ -1235,7 +1235,7 @@ static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
 
 	DEBUGFUNC("e1000_check_for_link_media_swap");
 
-	/* Check for copper. */
+	/* Check the copper medium. */
 	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 	if (ret_val)
 		return ret_val;
@@ -1247,7 +1247,7 @@ static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
 	if (data & E1000_M88E1112_STATUS_LINK)
 		port = E1000_MEDIA_PORT_COPPER;
 
-	/* Check for other. */
+	/* Check the other medium. */
 	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
 	if (ret_val)
 		return ret_val;
@@ -1256,6 +1256,11 @@ static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
 	if (ret_val)
 		return ret_val;
 
+	/* reset page to 0 */
+	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
+	if (ret_val)
+		return ret_val;
+
 	if (data & E1000_M88E1112_STATUS_LINK)
 		port = E1000_MEDIA_PORT_OTHER;
 
@@ -1263,20 +1268,8 @@ static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
 	if (port && (hw->dev_spec._82575.media_port != port)) {
 		hw->dev_spec._82575.media_port = port;
 		hw->dev_spec._82575.media_changed = TRUE;
-	}
-
-	if (port == E1000_MEDIA_PORT_COPPER) {
-		/* reset page to 0 */
-		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
-		if (ret_val)
-			return ret_val;
-		e1000_check_for_link_82575(hw);
 	} else {
-		e1000_check_for_link_82575(hw);
-		/* reset page to 0 */
-		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
-		if (ret_val)
-			return ret_val;
+		ret_val = e1000_check_for_link_82575(hw);
 	}
 
 	return E1000_SUCCESS;
@@ -2143,13 +2136,7 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
 	u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
 	int i, ms_wait;
 
-	DEBUGFUNC("e1000_rx_fifo_flush_82575");
-
-	/* disable IPv6 options as per hardware errata */
-	rfctl = E1000_READ_REG(hw, E1000_RFCTL);
-	rfctl |= E1000_RFCTL_IPV6_EX_DIS;
-	E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
-
+	DEBUGFUNC("e1000_rx_fifo_workaround_82575");
 	if (hw->mac.type != e1000_82575 ||
 	    !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
 		return;
@@ -2177,6 +2164,7 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
 	 * incoming packets are rejected.  Set enable and wait 2ms so that
 	 * any packet that was coming in as RCTL.EN was set is flushed
 	 */
+	rfctl = E1000_READ_REG(hw, E1000_RFCTL);
 	E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
 
 	rlpml = E1000_READ_REG(hw, E1000_RLPML);
@@ -2906,13 +2894,11 @@ out:
 /**
  *  e1000_set_eee_i350 - Enable/disable EEE support
  *  @hw: pointer to the HW structure
- *  @adv1g: boolean flag enabling 1G EEE advertisement
- *  @adv100m: boolean flag enabling 100M EEE advertisement
  *
  *  Enable/disable EEE based on setting in dev_spec structure.
  *
  **/
-s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
+s32 e1000_set_eee_i350(struct e1000_hw *hw)
 {
 	u32 ipcnfg, eeer;
 
@@ -2928,16 +2914,7 @@ s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
 	if (!(hw->dev_spec._82575.eee_disable)) {
 		u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
 
-		if (adv100M)
-			ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
-		else
-			ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
-
-		if (adv1G)
-			ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
-		else
-			ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
-
+		ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
 		eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
 			 E1000_EEER_LPI_FC);
 
@@ -2961,13 +2938,11 @@ out:
 /**
  *  e1000_set_eee_i354 - Enable/disable EEE support
  *  @hw: pointer to the HW structure
- *  @adv1g: boolean flag enabling 1G EEE advertisement
- *  @adv100m: boolean flag enabling 100M EEE advertisement
  *
  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
  *
  **/
-s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
+s32 e1000_set_eee_i354(struct e1000_hw *hw)
 {
 	struct e1000_phy_info *phy = &hw->phy;
 	s32 ret_val = E1000_SUCCESS;
@@ -3009,16 +2984,8 @@ s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
 		if (ret_val)
 			goto out;
 
-		if (adv100M)
-			phy_data |= E1000_EEE_ADV_100_SUPPORTED;
-		else
-			phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
-
-		if (adv1G)
-			phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
-		else
-			phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
-
+		phy_data |= E1000_EEE_ADV_100_SUPPORTED |
+			    E1000_EEE_ADV_1000_SUPPORTED;
 		ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
 						E1000_EEE_ADV_DEV_I354,
 						phy_data);
diff --git a/sys/dev/e1000/e1000_82575.h b/sys/dev/e1000/e1000_82575.h
index ef2b074c0686..503fdce305d6 100644
--- a/sys/dev/e1000/e1000_82575.h
+++ b/sys/dev/e1000/e1000_82575.h
@@ -495,8 +495,8 @@ void e1000_rlpml_set_vf(struct e1000_hw *, u16);
 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type);
 u16 e1000_rxpbs_adjust_82580(u32 data);
 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data);
-s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M);
-s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M);
+s32 e1000_set_eee_i350(struct e1000_hw *);
+s32 e1000_set_eee_i354(struct e1000_hw *);
 s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *);
 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw);
 
diff --git a/sys/dev/e1000/e1000_api.c b/sys/dev/e1000/e1000_api.c
index 9cd0adf27772..5db22db16f0d 100644
--- a/sys/dev/e1000/e1000_api.c
+++ b/sys/dev/e1000/e1000_api.c
@@ -299,12 +299,6 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
 	case E1000_DEV_ID_PCH_I218_V3:
 		mac->type = e1000_pch_lpt;
 		break;
-	case E1000_DEV_ID_PCH_SPT_I219_LM:
-	case E1000_DEV_ID_PCH_SPT_I219_V:
-	case E1000_DEV_ID_PCH_SPT_I219_LM2:
-	case E1000_DEV_ID_PCH_SPT_I219_V2:
-		mac->type = e1000_pch_spt;
-		break;
 	case E1000_DEV_ID_82575EB_COPPER:
 	case E1000_DEV_ID_82575EB_FIBER_SERDES:
 	case E1000_DEV_ID_82575GB_QUAD_COPPER:
@@ -455,7 +449,6 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
 	case e1000_pchlan:
 	case e1000_pch2lan:
 	case e1000_pch_lpt:
-	case e1000_pch_spt:
 		e1000_init_function_pointers_ich8lan(hw);
 		break;
 	case e1000_82575:
@@ -936,6 +929,21 @@ s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
 }
 
 /**
+ *  e1000_set_obff_timer - Set Optimized Buffer Flush/Fill timer
+ *  @hw: pointer to the HW structure
+ *  @itr: u32 indicating itr value
+ *
+ *  Set the OBFF timer based on the given interrupt rate.
+ **/
+s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr)
+{
+	if (hw->mac.ops.set_obff_timer)
+		return hw->mac.ops.set_obff_timer(hw, itr);
+
+	return E1000_SUCCESS;
+}
+
+/**
  *  e1000_check_reset_block - Verifies PHY can be reset
  *  @hw: pointer to the HW structure
  *
@@ -1208,21 +1216,6 @@ s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size)
 }
 
 /**
- *  e1000_read_pba_num - Read device part number
- *  @hw: pointer to the HW structure
- *  @pba_num: pointer to device part number
- *
- *  Reads the product board assembly (PBA) number from the EEPROM and stores
- *  the value in pba_num.
- *  Currently no func pointer exists and all implementations are handled in the
- *  generic version of this function.
- **/
-s32 e1000_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
-{
-	return e1000_read_pba_num_generic(hw, pba_num);
-}
-
-/**
  *  e1000_validate_nvm_checksum - Verifies NVM (EEPROM) checksum
  *  @hw: pointer to the HW structure
  *
diff --git a/sys/dev/e1000/e1000_api.h b/sys/dev/e1000/e1000_api.h
index 86075f8e61b4..074197bfe851 100644
--- a/sys/dev/e1000/e1000_api.h
+++ b/sys/dev/e1000/e1000_api.h
@@ -97,7 +97,6 @@ s32 e1000_phy_commit(struct e1000_hw *hw);
 void e1000_power_up_phy(struct e1000_hw *hw);
 void e1000_power_down_phy(struct e1000_hw *hw);
 s32 e1000_read_mac_addr(struct e1000_hw *hw);
-s32 e1000_read_pba_num(struct e1000_hw *hw, u32 *part_num);
 s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size);
 s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);
 void e1000_reload_nvm(struct e1000_hw *hw);
diff --git a/sys/dev/e1000/e1000_defines.h b/sys/dev/e1000/e1000_defines.h
index eb6260481f65..9472ca4c4d4d 100644
--- a/sys/dev/e1000/e1000_defines.h
+++ b/sys/dev/e1000/e1000_defines.h
@@ -197,8 +197,6 @@
 #define E1000_RCTL_LBM_TCVR	0x000000C0 /* tcvr loopback mode */
 #define E1000_RCTL_DTYP_PS	0x00000400 /* Packet Split descriptor */
 #define E1000_RCTL_RDMTS_HALF	0x00000000 /* Rx desc min thresh size */
-#define E1000_RCTL_RDMTS_HEX	0x00010000
-#define E1000_RCTL_RDMTS1_HEX	E1000_RCTL_RDMTS_HEX
 #define E1000_RCTL_MO_SHIFT	12 /* multicast offset shift */
 #define E1000_RCTL_MO_3		0x00003000 /* multicast offset 15:4 */
 #define E1000_RCTL_BAM		0x00008000 /* broadcast enable */
@@ -567,6 +565,9 @@
 #define E1000_ICR_THS		0x00800000 /* ICR.THS: Thermal Sensor Event*/
 #define E1000_ICR_MDDET		0x10000000 /* Malicious Driver Detect */
 
+#define E1000_ITR_MASK		0x000FFFFF /* ITR value bitfield */
+#define E1000_ITR_MULT		256 /* ITR mulitplier in nsec */
+
 /* PBA ECC Register */
 #define E1000_PBA_ECC_COUNTER_MASK	0xFFF00000 /* ECC counter mask */
 #define E1000_PBA_ECC_COUNTER_SHIFT	20 /* ECC counter shift value */
@@ -752,12 +753,6 @@
 #define E1000_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
 #define E1000_TSYNCTXCTL_ENABLED	0x00000010 /* enable Tx timestamping */
 
-/* HH Time Sync */
-#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK	0x0000F000 /* max delay */
-#define E1000_TSYNCTXCTL_SYNC_COMP_ERR		0x20000000 /* sync err */
-#define E1000_TSYNCTXCTL_SYNC_COMP		0x40000000 /* sync complete */
-#define E1000_TSYNCTXCTL_START_SYNC		0x80000000 /* initiate sync */
-
 #define E1000_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
 #define E1000_TSYNCRXCTL_TYPE_MASK	0x0000000E /* Rx type mask */
 #define E1000_TSYNCRXCTL_TYPE_L2_V2	0x00
@@ -1025,7 +1020,9 @@
 /* NVM Addressing bits based on type 0=small, 1=large */
 #define E1000_EECD_ADDR_BITS	0x00000400
 #define E1000_EECD_TYPE		0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
+#ifndef E1000_NVM_GRANT_ATTEMPTS
 #define E1000_NVM_GRANT_ATTEMPTS	1000 /* NVM # attempts to gain grant */
+#endif
 #define E1000_EECD_AUTO_RD		0x00000200  /* NVM Auto Read done */
 #define E1000_EECD_SIZE_EX_MASK		0x00007800  /* NVM Size */
 #define E1000_EECD_SIZE_EX_SHIFT	11
@@ -1062,44 +1059,11 @@
 /* NVM Word Offsets */
 #define NVM_COMPAT			0x0003
 #define NVM_ID_LED_SETTINGS		0x0004
-#define NVM_VERSION			0x0005
 #define NVM_SERDES_AMPLITUDE		0x0006 /* SERDES output amplitude */
 #define NVM_PHY_CLASS_WORD		0x0007
 #define E1000_I210_NVM_FW_MODULE_PTR	0x0010
 #define E1000_I350_NVM_FW_MODULE_PTR	0x0051
 #define NVM_FUTURE_INIT_WORD1		0x0019
-#define NVM_ETRACK_WORD			0x0042
-#define NVM_ETRACK_HIWORD		0x0043
-#define NVM_COMB_VER_OFF		0x0083
-#define NVM_COMB_VER_PTR		0x003d
-
-/* NVM version defines */
-#define NVM_MAJOR_MASK			0xF000
-#define NVM_MINOR_MASK			0x0FF0
-#define NVM_IMAGE_ID_MASK		0x000F
-#define NVM_COMB_VER_MASK		0x00FF
-#define NVM_MAJOR_SHIFT			12
-#define NVM_MINOR_SHIFT			4
-#define NVM_COMB_VER_SHFT		8
-#define NVM_VER_INVALID			0xFFFF
-#define NVM_ETRACK_SHIFT		16
-#define NVM_ETRACK_VALID		0x8000
-#define NVM_NEW_DEC_MASK		0x0F00
-#define NVM_HEX_CONV			16
-#define NVM_HEX_TENS			10
-
-/* FW version defines */
-/* Offset of "Loader patch ptr" in Firmware Header */
-#define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET	0x01
-/* Patch generation hour & minutes */
-#define E1000_I350_NVM_FW_VER_WORD1_OFFSET		0x04
-/* Patch generation month & day */
-#define E1000_I350_NVM_FW_VER_WORD2_OFFSET		0x05
-/* Patch generation year */
-#define E1000_I350_NVM_FW_VER_WORD3_OFFSET		0x06
-/* Patch major & minor numbers */
-#define E1000_I350_NVM_FW_VER_WORD4_OFFSET		0x07
-
 #define NVM_MAC_ADDR			0x0000
 #define NVM_SUB_DEV_ID			0x000B
 #define NVM_SUB_VEN_ID			0x000C
@@ -1476,6 +1440,8 @@
 #define I210_RXPBSIZE_DEFAULT		0x000000A2 /* RXPBSIZE default */
 #define I210_TXPBSIZE_DEFAULT		0x04000014 /* TXPBSIZE default */
 
+#define E1000_DOBFFCTL_OBFFTHR_MASK	0x000000FF /* OBFF threshold */
+#define E1000_DOBFFCTL_EXIT_ACT_MASK	0x01000000 /* Exit active CB */
 
 /* Proxy Filter Control */
 #define E1000_PROXYFC_D0		0x00000001 /* Enable offload in D0 */
diff --git a/sys/dev/e1000/e1000_hw.h b/sys/dev/e1000/e1000_hw.h
index 8e945f663a62..8ae4b202fd1e 100644
--- a/sys/dev/e1000/e1000_hw.h
+++ b/sys/dev/e1000/e1000_hw.h
@@ -137,10 +137,6 @@ struct e1000_hw;
 #define E1000_DEV_ID_PCH_I218_V2		0x15A1
 #define E1000_DEV_ID_PCH_I218_LM3		0x15A2 /* Wildcat Point PCH */
 #define E1000_DEV_ID_PCH_I218_V3		0x15A3 /* Wildcat Point PCH */
-#define E1000_DEV_ID_PCH_SPT_I219_LM		0x156F /* Sunrise Point PCH */
-#define E1000_DEV_ID_PCH_SPT_I219_V		0x1570 /* Sunrise Point PCH */
-#define E1000_DEV_ID_PCH_SPT_I219_LM2		0x15B7 /* Sunrise Point-H PCH */
-#define E1000_DEV_ID_PCH_SPT_I219_V2		0x15B8 /* Sunrise Point-H PCH */
 #define E1000_DEV_ID_82576			0x10C9
 #define E1000_DEV_ID_82576_FIBER		0x10E6
 #define E1000_DEV_ID_82576_SERDES		0x10E7
@@ -226,7 +222,6 @@ enum e1000_mac_type {
 	e1000_pchlan,
 	e1000_pch2lan,
 	e1000_pch_lpt,
-	e1000_pch_spt,
 	e1000_82575,
 	e1000_82576,
 	e1000_82580,
@@ -708,6 +703,7 @@ struct e1000_mac_operations {
 	int  (*rar_set)(struct e1000_hw *, u8*, u32);
 	s32  (*read_mac_addr)(struct e1000_hw *);
 	s32  (*validate_mdi_setting)(struct e1000_hw *);
+	s32  (*set_obff_timer)(struct e1000_hw *, u32);
 	s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 	void (*release_swfw_sync)(struct e1000_hw *, u16);
 };
@@ -809,7 +805,7 @@ struct e1000_mac_info {
 	enum e1000_serdes_link_state serdes_link_state;
 	bool serdes_has_link;
 	bool tx_pkt_filtering;
-	u32  max_frame_size;
+	u32 max_frame_size;
 };
 
 struct e1000_phy_info {
diff --git a/sys/dev/e1000/e1000_i210.c b/sys/dev/e1000/e1000_i210.c
index 2c03660da76a..563f11a1d27e 100644
--- a/sys/dev/e1000/e1000_i210.c
+++ b/sys/dev/e1000/e1000_i210.c
@@ -489,105 +489,6 @@ static s32 e1000_read_invm_i210(struct e1000_hw *hw, u16 offset,
 }
 
 /**
- *  e1000_read_invm_version - Reads iNVM version and image type
- *  @hw: pointer to the HW structure
- *  @invm_ver: version structure for the version read
- *
- *  Reads iNVM version and image type.
- **/
-s32 e1000_read_invm_version(struct e1000_hw *hw,
-			    struct e1000_fw_version *invm_ver)
-{
-	u32 *record = NULL;
-	u32 *next_record = NULL;
-	u32 i = 0;
-	u32 invm_dword = 0;
-	u32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /
-					     E1000_INVM_RECORD_SIZE_IN_BYTES);
-	u32 buffer[E1000_INVM_SIZE];
-	s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
-	u16 version = 0;
-
-	DEBUGFUNC("e1000_read_invm_version");
-
-	/* Read iNVM memory */
-	for (i = 0; i < E1000_INVM_SIZE; i++) {
-		invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
-		buffer[i] = invm_dword;
-	}
-
-	/* Read version number */
-	for (i = 1; i < invm_blocks; i++) {
-		record = &buffer[invm_blocks - i];
-		next_record = &buffer[invm_blocks - i + 1];
-
-		/* Check if we have first version location used */
-		if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {
-			version = 0;
-			status = E1000_SUCCESS;
-			break;
-		}
-		/* Check if we have second version location used */
-		else if ((i == 1) &&
-			 ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {
-			version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
-			status = E1000_SUCCESS;
-			break;
-		}
-		/*
-		 * Check if we have odd version location
-		 * used and it is the last one used
-		 */
-		else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&
-			 ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&
-			 (i != 1))) {
-			version = (*next_record & E1000_INVM_VER_FIELD_TWO)
-				  >> 13;
-			status = E1000_SUCCESS;
-			break;
-		}
-		/*
-		 * Check if we have even version location
-		 * used and it is the last one used
-		 */
-		else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&
-			 ((*record & 0x3) == 0)) {
-			version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
-			status = E1000_SUCCESS;
-			break;
-		}
-	}
-
-	if (status == E1000_SUCCESS) {
-		invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)
-					>> E1000_INVM_MAJOR_SHIFT;
-		invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;
-	}
-	/* Read Image Type */
-	for (i = 1; i < invm_blocks; i++) {
-		record = &buffer[invm_blocks - i];
-		next_record = &buffer[invm_blocks - i + 1];
-
-		/* Check if we have image type in first location used */
-		if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {
-			invm_ver->invm_img_type = 0;
-			status = E1000_SUCCESS;
-			break;
-		}
-		/* Check if we have image type in first location used */
-		else if ((((*record & 0x3) == 0) &&
-			 ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) ||
-			 ((((*record & 0x3) != 0) && (i != 1)))) {
-			invm_ver->invm_img_type =
-				(*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;
-			status = E1000_SUCCESS;
-			break;
-		}
-	}
-	return status;
-}
-
-/**
  *  e1000_validate_nvm_checksum_i210 - Validate EEPROM checksum
  *  @hw: pointer to the HW structure
  *
diff --git a/sys/dev/e1000/e1000_i210.h b/sys/dev/e1000/e1000_i210.h
index b0f94baeea3f..f940915b0619 100644
--- a/sys/dev/e1000/e1000_i210.h
+++ b/sys/dev/e1000/e1000_i210.h
@@ -43,8 +43,6 @@ s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,
 			      u16 words, u16 *data);
 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
 			     u16 words, u16 *data);
-s32 e1000_read_invm_version(struct e1000_hw *hw,
-			    struct e1000_fw_version *invm_ver);
 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
diff --git a/sys/dev/e1000/e1000_ich8lan.c b/sys/dev/e1000/e1000_ich8lan.c
index 5b60d1914677..75fcade3703b 100644
--- a/sys/dev/e1000/e1000_ich8lan.c
+++ b/sys/dev/e1000/e1000_ich8lan.c
@@ -92,13 +92,10 @@ static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
 					    bool active);
 static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
 				   u16 words, u16 *data);
-static s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
-			       u16 *data);
 static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
 				    u16 words, u16 *data);
 static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
-static s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
 static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
 					    u16 *data);
 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
@@ -126,14 +123,6 @@ static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 					  u32 offset, u8 *data);
 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 					  u8 size, u16 *data);
-static s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
-					    u32 *data);
-static s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
-					   u32 offset, u32 *data);
-static s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
-					     u32 offset, u32 data);
-static s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
-						  u32 offset, u32 dword);
 static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 					  u32 offset, u16 *data);
 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
@@ -144,6 +133,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
+static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
 
 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 /* Offset 04h HSFSTS */
@@ -242,21 +232,16 @@ static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 	if (ret_val)
 		return FALSE;
 out:
-	if ((hw->mac.type == e1000_pch_lpt) ||
-	    (hw->mac.type == e1000_pch_spt)) {
-		/* Only unforce SMBus if ME is not active */
-		if (!(E1000_READ_REG(hw, E1000_FWSM) &
-		    E1000_ICH_FWSM_FW_VALID)) {
-			/* Unforce SMBus mode in PHY */
-			hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
-			phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
-			hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
+	if (hw->mac.type == e1000_pch_lpt) {
+		/* Unforce SMBus mode in PHY */
+		hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
+		phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
+		hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 
-			/* Unforce SMBus mode in MAC */
-			mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
-			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
-			E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
-		}
+		/* Unforce SMBus mode in MAC */
+		mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
+		mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
+		E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 	}
 
 	return TRUE;
@@ -343,7 +328,6 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 	 */
 	switch (hw->mac.type) {
 	case e1000_pch_lpt:
-	case e1000_pch_spt:
 		if (e1000_phy_is_accessible_pchlan(hw))
 			break;
 
@@ -491,7 +475,6 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 			/* fall-through */
 		case e1000_pch2lan:
 		case e1000_pch_lpt:
-		case e1000_pch_spt:
 			/* In case the PHY needs to be in mdio slow mode,
 			 * set slow mode and try to get the PHY id again.
 			 */
@@ -634,53 +617,36 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 	u32 gfpreg, sector_base_addr, sector_end_addr;
 	u16 i;
-	u32 nvm_size;
 
 	DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 
 	/* Can't read flash registers if the register set isn't mapped. */
 	nvm->type = e1000_nvm_flash_sw;
-	/* in SPT, gfpreg doesn't exist. NVM size is taken from the
-	 * STRAP register
-	 */
-	if (hw->mac.type == e1000_pch_spt) {
-		nvm->flash_base_addr = 0;
-		nvm_size =
-		    (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
-		    * NVM_SIZE_MULTIPLIER;
-		nvm->flash_bank_size = nvm_size / 2;
-		/* Adjust to word count */
-		nvm->flash_bank_size /= sizeof(u16);
-		/* Set the base address for flash register access */
-		hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
-	} else {
-		if (!hw->flash_address) {
-			DEBUGOUT("ERROR: Flash registers not mapped\n");
-			return -E1000_ERR_CONFIG;
-		}
+	if (!hw->flash_address) {
+		DEBUGOUT("ERROR: Flash registers not mapped\n");
+		return -E1000_ERR_CONFIG;
+	}
 
-		gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
+	gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 
-		/* sector_X_addr is a "sector"-aligned address (4096 bytes)
-		 * Add 1 to sector_end_addr since this sector is included in
-		 * the overall size.
-		 */
-		sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
-		sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
+	/* sector_X_addr is a "sector"-aligned address (4096 bytes)
+	 * Add 1 to sector_end_addr since this sector is included in
+	 * the overall size.
+	 */
+	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
+	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 
-		/* flash_base_addr is byte-aligned */
-		nvm->flash_base_addr = sector_base_addr
-				       << FLASH_SECTOR_ADDR_SHIFT;
+	/* flash_base_addr is byte-aligned */
+	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 
-		/* find total size of the NVM, then cut in half since the total
-		 * size represents two separate NVM banks.
-		 */
-		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
-					<< FLASH_SECTOR_ADDR_SHIFT);
-		nvm->flash_bank_size /= 2;
-		/* Adjust to word count */
-		nvm->flash_bank_size /= sizeof(u16);
-	}
+	/* find total size of the NVM, then cut in half since the total
+	 * size represents two separate NVM banks.
+	 */
+	nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
+				<< FLASH_SECTOR_ADDR_SHIFT);
+	nvm->flash_bank_size /= 2;
+	/* Adjust to word count */
+	nvm->flash_bank_size /= sizeof(u16);
 
 	nvm->word_size = E1000_SHADOW_RAM_WORDS;
 
@@ -696,13 +662,8 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 	/* Function Pointers */
 	nvm->ops.acquire	= e1000_acquire_nvm_ich8lan;
 	nvm->ops.release	= e1000_release_nvm_ich8lan;
-	if (hw->mac.type == e1000_pch_spt) {
-		nvm->ops.read	= e1000_read_nvm_spt;
-		nvm->ops.update	= e1000_update_nvm_checksum_spt;
-	} else {
-		nvm->ops.read	= e1000_read_nvm_ich8lan;
-		nvm->ops.update	= e1000_update_nvm_checksum_ich8lan;
-	}
+	nvm->ops.read		= e1000_read_nvm_ich8lan;
+	nvm->ops.update		= e1000_update_nvm_checksum_ich8lan;
 	nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 	nvm->ops.validate	= e1000_validate_nvm_checksum_ich8lan;
 	nvm->ops.write		= e1000_write_nvm_ich8lan;
@@ -720,7 +681,9 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 {
 	struct e1000_mac_info *mac = &hw->mac;
+#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 	u16 pci_cfg;
+#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 
 	DEBUGFUNC("e1000_init_mac_params_ich8lan");
 
@@ -789,21 +752,15 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 		mac->ops.rar_set = e1000_rar_set_pch2lan;
 		/* fall-through */
 	case e1000_pch_lpt:
-	case e1000_pch_spt:
 		/* multicast address update for pch2 */
 		mac->ops.update_mc_addr_list =
 			e1000_update_mc_addr_list_pch2lan;
-		/* fall-through */
 	case e1000_pchlan:
+#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 		/* save PCH revision_id */
 		e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
-		/* SPT uses full byte for revision ID,
-		 * as opposed to previous generations
-		 */
-		if (hw->mac.type >= e1000_pch_spt)
-			hw->revision_id = (u8)(pci_cfg &= 0x00FF);
-		else
-			hw->revision_id = (u8)(pci_cfg &= 0x000F);
+		hw->revision_id = (u8)(pci_cfg &= 0x000F);
+#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 		/* check management mode */
 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 		/* ID LED init */
@@ -820,11 +777,11 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 		break;
 	}
 
-	if ((mac->type == e1000_pch_lpt) ||
-	    (mac->type == e1000_pch_spt)) {
+	if (mac->type == e1000_pch_lpt) {
 		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 		mac->ops.rar_set = e1000_rar_set_pch_lpt;
 		mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
+		mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
 	}
 
 	/* Enable PCS Lock-loss workaround for ICH8 */
@@ -1050,9 +1007,8 @@ release:
 		/* clear FEXTNVM6 bit 8 on link down or 10/100 */
 		fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 
-		if ((hw->phy.revision > 5) || !link ||
-		    ((status & E1000_STATUS_SPEED_100) &&
-		     (status & E1000_STATUS_FD)))
+		if (!link || ((status & E1000_STATUS_SPEED_100) &&
+			      (status & E1000_STATUS_FD)))
 			goto update_fextnvm6;
 
 		ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
@@ -1088,6 +1044,168 @@ update_fextnvm6:
 	return ret_val;
 }
 
+static u64 e1000_ltr2ns(u16 ltr)
+{
+	u32 value, scale;
+
+	/* Determine the latency in nsec based on the LTR value & scale */
+	value = ltr & E1000_LTRV_VALUE_MASK;
+	scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
+
+	return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
+}
+
+/**
+ *  e1000_platform_pm_pch_lpt - Set platform power management values
+ *  @hw: pointer to the HW structure
+ *  @link: bool indicating link status
+ *
+ *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
+ *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
+ *  when link is up (which must not exceed the maximum latency supported
+ *  by the platform), otherwise specify there is no LTR requirement.
+ *  Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
+ *  latencies in the LTR Extended Capability Structure in the PCIe Extended
+ *  Capability register set, on this device LTR is set by writing the
+ *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
+ *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
+ *  message to the PMC.
+ *
+ *  Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
+ *  high-water mark.
+ **/
+static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
+{
+	u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
+		  link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
+	u16 lat_enc = 0;	/* latency encoded */
+	s32 obff_hwm = 0;
+
+	DEBUGFUNC("e1000_platform_pm_pch_lpt");
+
+	if (link) {
+		u16 speed, duplex, scale = 0;
+		u16 max_snoop, max_nosnoop;
+		u16 max_ltr_enc;	/* max LTR latency encoded */
+		s64 lat_ns;
+		s64 value;
+		u32 rxa;
+
+		if (!hw->mac.max_frame_size) {
+			DEBUGOUT("max_frame_size not set.\n");
+			return -E1000_ERR_CONFIG;
+		}
+
+		hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
+		if (!speed) {
+			DEBUGOUT("Speed not set.\n");
+			return -E1000_ERR_CONFIG;
+		}
+
+		/* Rx Packet Buffer Allocation size (KB) */
+		rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
+
+		/* Determine the maximum latency tolerated by the device.
+		 *
+		 * Per the PCIe spec, the tolerated latencies are encoded as
+		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
+		 * a 10-bit value (0-1023) to provide a range from 1 ns to
+		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
+		 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
+		 */
+		lat_ns = ((s64)rxa * 1024 -
+			  (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
+		if (lat_ns < 0)
+			lat_ns = 0;
+		else
+			lat_ns /= speed;
+		value = lat_ns;
+
+		while (value > E1000_LTRV_VALUE_MASK) {
+			scale++;
+			value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
+		}
+		if (scale > E1000_LTRV_SCALE_MAX) {
+			DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
+			return -E1000_ERR_CONFIG;
+		}
+		lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
+
+		/* Determine the maximum latency tolerated by the platform */
+		e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
+		e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
+		max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
+
+		if (lat_enc > max_ltr_enc) {
+			lat_enc = max_ltr_enc;
+			lat_ns = e1000_ltr2ns(max_ltr_enc);
+		}
+
+		if (lat_ns) {
+			lat_ns *= speed * 1000;
+			lat_ns /= 8;
+			lat_ns /= 1000000000;
+			obff_hwm = (s32)(rxa - lat_ns);
+		}
+		if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
+			DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
+			return -E1000_ERR_CONFIG;
+		}
+	}
+
+	/* Set Snoop and No-Snoop latencies the same */
+	reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
+	E1000_WRITE_REG(hw, E1000_LTRV, reg);
+
+	/* Set OBFF high water mark */
+	reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
+	reg |= obff_hwm;
+	E1000_WRITE_REG(hw, E1000_SVT, reg);
+
+	/* Enable OBFF */
+	reg = E1000_READ_REG(hw, E1000_SVCR);
+	reg |= E1000_SVCR_OFF_EN;
+	/* Always unblock interrupts to the CPU even when the system is
+	 * in OBFF mode. This ensures that small round-robin traffic
+	 * (like ping) does not get dropped or experience long latency.
+	 */
+	reg |= E1000_SVCR_OFF_MASKINT;
+	E1000_WRITE_REG(hw, E1000_SVCR, reg);
+
+	return E1000_SUCCESS;
+}
+
+/**
+ *  e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
+ *  @hw: pointer to the HW structure
+ *  @itr: interrupt throttling rate
+ *
+ *  Configure OBFF with the updated interrupt rate.
+ **/
+static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
+{
+	u32 svcr;
+	s32 timer;
+
+	DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
+
+	/* Convert ITR value into microseconds for OBFF timer */
+	timer = itr & E1000_ITR_MASK;
+	timer = (timer * E1000_ITR_MULT) / 1000;
+
+	if ((timer < 0) || (timer > E1000_ITR_MASK)) {
+		DEBUGOUT1("Invalid OBFF timer %d\n", timer);
+		return -E1000_ERR_CONFIG;
+	}
+
+	svcr = E1000_READ_REG(hw, E1000_SVCR);
+	svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
+	svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
+	E1000_WRITE_REG(hw, E1000_SVCR, svcr);
+
+	return E1000_SUCCESS;
+}
+
 /**
  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
  *  @hw: pointer to the HW structure
@@ -1103,7 +1221,6 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
 	u32 mac_reg;
 	s32 ret_val = E1000_SUCCESS;
 	u16 phy_reg;
-	u16 oem_reg = 0;
 
 	if ((hw->mac.type < e1000_pch_lpt) ||
 	    (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
@@ -1159,25 +1276,6 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
 	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 
-	/* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
-	 * LPLU and disable Gig speed when entering ULP
-	 */
-	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
-		ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
-						       &oem_reg);
-		if (ret_val)
-			goto release;
-
-		phy_reg = oem_reg;
-		phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
-
-		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
-							phy_reg);
-
-		if (ret_val)
-			goto release;
-	}
-
 	/* Set Inband ULP Exit, Reset to SMBus mode and
 	 * Disable SMBus Release on PERST# in PHY
 	 */
@@ -1189,15 +1287,10 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
 	if (to_sx) {
 		if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
 			phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
-		else
-			phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
 
 		phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
-		phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
 	} else {
 		phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
-		phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
-		phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
 	}
 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
 
@@ -1209,16 +1302,6 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
 	/* Commit ULP changes in PHY by starting auto ULP configuration */
 	phy_reg |= I218_ULP_CONFIG1_START;
 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
-
-	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
-	    to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
-
-		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
-							oem_reg);
-		if (ret_val)
-			goto release;
-	}
-
 release:
 	hw->phy.ops.release(hw);
 out:
@@ -1384,8 +1467,7 @@ out:
 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 {
 	struct e1000_mac_info *mac = &hw->mac;
-	s32 ret_val, tipg_reg = 0;
-	u16 emi_addr, emi_val = 0;
+	s32 ret_val;
 	bool link;
 	u16 phy_reg;
 
@@ -1418,92 +1500,35 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 	 * the IPG and reduce Rx latency in the PHY.
 	 */
 	if (((hw->mac.type == e1000_pch2lan) ||
-	     (hw->mac.type == e1000_pch_lpt) ||
-	     (hw->mac.type == e1000_pch_spt)) && link) {
-		u16 speed, duplex;
+	     (hw->mac.type == e1000_pch_lpt)) && link) {
+		u32 reg;
+		reg = E1000_READ_REG(hw, E1000_STATUS);
+		if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
+			u16 emi_addr;
 
-		e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
-		tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
-		tipg_reg &= ~E1000_TIPG_IPGT_MASK;
+			reg = E1000_READ_REG(hw, E1000_TIPG);
+			reg &= ~E1000_TIPG_IPGT_MASK;
+			reg |= 0xFF;
+			E1000_WRITE_REG(hw, E1000_TIPG, reg);
 
-		if (duplex == HALF_DUPLEX && speed == SPEED_10) {
-			tipg_reg |= 0xFF;
 			/* Reduce Rx latency in analog PHY */
-			emi_val = 0;
-		} else if (hw->mac.type == e1000_pch_spt &&
-			   duplex == FULL_DUPLEX && speed != SPEED_1000) {
-			tipg_reg |= 0xC;
-			emi_val = 1;
-		} else {
-			/* Roll back the default values */
-			tipg_reg |= 0x08;
-			emi_val = 1;
-		}
-
-		E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
-
-		ret_val = hw->phy.ops.acquire(hw);
-		if (ret_val)
-			return ret_val;
-
-		if (hw->mac.type == e1000_pch2lan)
-			emi_addr = I82579_RX_CONFIG;
-		else
-			emi_addr = I217_RX_CONFIG;
-		ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
+			ret_val = hw->phy.ops.acquire(hw);
+			if (ret_val)
+				return ret_val;
 
-		hw->phy.ops.release(hw);
+			if (hw->mac.type == e1000_pch2lan)
+				emi_addr = I82579_RX_CONFIG;
+			else
+				emi_addr = I217_RX_CONFIG;
+			ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
 
-		if (ret_val)
-			return ret_val;
+			hw->phy.ops.release(hw);
 
-		if (hw->mac.type == e1000_pch_spt) {
-			u16 data;
-			u16 ptr_gap;
-
-			if (speed == SPEED_1000) {
-				ret_val = hw->phy.ops.acquire(hw);
-				if (ret_val)
-					return ret_val;
-
-				ret_val = hw->phy.ops.read_reg_locked(hw,
-							      PHY_REG(776, 20),
-							      &data);
-				if (ret_val) {
-					hw->phy.ops.release(hw);
-					return ret_val;
-				}
-
-				ptr_gap = (data & (0x3FF << 2)) >> 2;
-				if (ptr_gap < 0x18) {
-					data &= ~(0x3FF << 2);
-					data |= (0x18 << 2);
-					ret_val =
-						hw->phy.ops.write_reg_locked(hw,
-							PHY_REG(776, 20), data);
-				}
-				hw->phy.ops.release(hw);
-				if (ret_val)
-					return ret_val;
-			}
+			if (ret_val)
+				return ret_val;
 		}
 	}
 
-	/* I217 Packet Loss issue:
-	 * ensure that FEXTNVM4 Beacon Duration is set correctly
-	 * on power up.
-	 * Set the Beacon Duration for I217 to 8 usec
-	 */
-	if ((hw->mac.type == e1000_pch_lpt) ||
-	    (hw->mac.type == e1000_pch_spt)) {
-		u32 mac_reg;
-
-		mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
-		mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
-		mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
-		E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
-	}
-
 	/* Work-around I218 hang issue */
 	if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
 	    (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
@@ -1513,22 +1538,19 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 		if (ret_val)
 			return ret_val;
 	}
+	if (hw->mac.type == e1000_pch_lpt) {
+		/* Set platform power management values for
+		 * Latency Tolerance Reporting (LTR)
+		 * Optimized Buffer Flush/Fill (OBFF)
+		 */
+		ret_val = e1000_platform_pm_pch_lpt(hw, link);
+		if (ret_val)
+			return ret_val;
+	}
+
 	/* Clear link partner's EEE ability */
 	hw->dev_spec.ich8lan.eee_lp_ability = 0;
 
-	/* FEXTNVM6 K1-off workaround */
-	if (hw->mac.type == e1000_pch_spt) {
-		u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
-		u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
-
-		if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
-			fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
-		else
-			fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
-
-		E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
-	}
-
 	if (!link)
 		return E1000_SUCCESS; /* No link detected */
 
@@ -1622,7 +1644,6 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
 	case e1000_pchlan:
 	case e1000_pch2lan:
 	case e1000_pch_lpt:
-	case e1000_pch_spt:
 		hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
 		break;
 	default:
@@ -2086,7 +2107,6 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 	case e1000_pchlan:
 	case e1000_pch2lan:
 	case e1000_pch_lpt:
-	case e1000_pch_spt:
 		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 		break;
 	default:
@@ -3202,20 +3222,6 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 	DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
 
 	switch (hw->mac.type) {
-	/* In SPT, read from the CTRL_EXT reg instead of
-	 * accessing the sector valid bits from the nvm
-	 */
-	case e1000_pch_spt:
-		*bank = E1000_READ_REG(hw, E1000_CTRL_EXT)
-			& E1000_CTRL_EXT_NVMVS;
-		if ((*bank == 0) || (*bank == 1)) {
-			DEBUGOUT("ERROR: No valid NVM bank present\n");
-			return -E1000_ERR_NVM;
-		} else {
-			*bank = *bank - 2;
-			return E1000_SUCCESS;
-		}
-		break;
 	case e1000_ich8lan:
 	case e1000_ich9lan:
 		eecd = E1000_READ_REG(hw, E1000_EECD);
@@ -3263,99 +3269,6 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 }
 
 /**
- *  e1000_read_nvm_spt - NVM access for SPT
- *  @hw: pointer to the HW structure
- *  @offset: The offset (in bytes) of the word(s) to read.
- *  @words: Size of data to read in words.
- *  @data: pointer to the word(s) to read at offset.
- *
- *  Reads a word(s) from the NVM
- **/
-static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
-			      u16 *data)
-{
-	struct e1000_nvm_info *nvm = &hw->nvm;
-	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
-	u32 act_offset;
-	s32 ret_val = E1000_SUCCESS;
-	u32 bank = 0;
-	u32 dword = 0;
-	u16 offset_to_read;
-	u16 i;
-
-	DEBUGFUNC("e1000_read_nvm_spt");
-
-	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
-	    (words == 0)) {
-		DEBUGOUT("nvm parameter(s) out of bounds\n");
-		ret_val = -E1000_ERR_NVM;
-		goto out;
-	}
-
-	nvm->ops.acquire(hw);
-
-	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
-	if (ret_val != E1000_SUCCESS) {
-		DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
-		bank = 0;
-	}
-
-	act_offset = (bank) ? nvm->flash_bank_size : 0;
-	act_offset += offset;
-
-	ret_val = E1000_SUCCESS;
-
-	for (i = 0; i < words; i += 2) {
-		if (words - i == 1) {
-			if (dev_spec->shadow_ram[offset+i].modified) {
-				data[i] = dev_spec->shadow_ram[offset+i].value;
-			} else {
-				offset_to_read = act_offset + i -
-						 ((act_offset + i) % 2);
-				ret_val =
-				   e1000_read_flash_dword_ich8lan(hw,
-								 offset_to_read,
-								 &dword);
-				if (ret_val)
-					break;
-				if ((act_offset + i) % 2 == 0)
-					data[i] = (u16)(dword & 0xFFFF);
-				else
-					data[i] = (u16)((dword >> 16) & 0xFFFF);
-			}
-		} else {
-			offset_to_read = act_offset + i;
-			if (!(dev_spec->shadow_ram[offset+i].modified) ||
-			    !(dev_spec->shadow_ram[offset+i+1].modified)) {
-				ret_val =
-				   e1000_read_flash_dword_ich8lan(hw,
-								 offset_to_read,
-								 &dword);
-				if (ret_val)
-					break;
-			}
-			if (dev_spec->shadow_ram[offset+i].modified)
-				data[i] = dev_spec->shadow_ram[offset+i].value;
-			else
-				data[i] = (u16) (dword & 0xFFFF);
-			if (dev_spec->shadow_ram[offset+i].modified)
-				data[i+1] =
-				   dev_spec->shadow_ram[offset+i+1].value;
-			else
-				data[i+1] = (u16) (dword >> 16 & 0xFFFF);
-		}
-	}
-
-	nvm->ops.release(hw);
-
-out:
-	if (ret_val)
-		DEBUGOUT1("NVM read error: %d\n", ret_val);
-
-	return ret_val;
-}
-
-/**
  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
  *  @hw: pointer to the HW structure
  *  @offset: The offset (in bytes) of the word(s) to read.
@@ -3442,11 +3355,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
 	/* Clear FCERR and DAEL in hw status by writing 1 */
 	hsfsts.hsf_status.flcerr = 1;
 	hsfsts.hsf_status.dael = 1;
-	if (hw->mac.type == e1000_pch_spt)
-		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
-				      hsfsts.regval & 0xFFFF);
-	else
-		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
+	E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
 
 	/* Either we should have a hardware SPI cycle in progress
 	 * bit to check against, in order to start a new cycle or
@@ -3462,12 +3371,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
 		 * Begin by setting Flash Cycle Done.
 		 */
 		hsfsts.hsf_status.flcdone = 1;
-		if (hw->mac.type == e1000_pch_spt)
-			E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
-					      hsfsts.regval & 0xFFFF);
-		else
-			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
-						hsfsts.regval);
+		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
 		ret_val = E1000_SUCCESS;
 	} else {
 		s32 i;
@@ -3489,12 +3393,8 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
 			 * now set the Flash Cycle Done.
 			 */
 			hsfsts.hsf_status.flcdone = 1;
-			if (hw->mac.type == e1000_pch_spt)
-				E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
-						      hsfsts.regval & 0xFFFF);
-			else
-				E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
-							hsfsts.regval);
+			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
+						hsfsts.regval);
 		} else {
 			DEBUGOUT("Flash controller busy, cannot get access\n");
 		}
@@ -3519,17 +3419,10 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
 	DEBUGFUNC("e1000_flash_cycle_ich8lan");
 
 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
-	if (hw->mac.type == e1000_pch_spt)
-		hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
-	else
-		hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
+	hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
 	hsflctl.hsf_ctrl.flcgo = 1;
 
-	if (hw->mac.type == e1000_pch_spt)
-		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
-				      hsflctl.regval << 16);
-	else
-		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
+	E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
 
 	/* wait till FDONE bit is set to 1 */
 	do {
@@ -3546,29 +3439,6 @@ static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
 }
 
 /**
- *  e1000_read_flash_dword_ich8lan - Read dword from flash
- *  @hw: pointer to the HW structure
- *  @offset: offset to data location
- *  @data: pointer to the location for storing the data
- *
- *  Reads the flash dword at offset into data.  Offset is converted
- *  to bytes before read.
- **/
-static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
-					  u32 *data)
-{
-	DEBUGFUNC("e1000_read_flash_dword_ich8lan");
-
-	if (!data)
-		return -E1000_ERR_NVM;
-
-	/* Must convert word offset into bytes. */
-	offset <<= 1;
-
-	return e1000_read_flash_data32_ich8lan(hw, offset, data);
-}
-
-/**
  *  e1000_read_flash_word_ich8lan - Read word from flash
  *  @hw: pointer to the HW structure
  *  @offset: offset to data location
@@ -3605,13 +3475,7 @@ static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 	s32 ret_val;
 	u16 word = 0;
 
-	/* In SPT, only 32 bits access is supported,
-	 * so this function should not be called.
-	 */
-	if (hw->mac.type == e1000_pch_spt)
-		return -E1000_ERR_NVM;
-	else
-		ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
+	ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
 
 	if (ret_val)
 		return ret_val;
@@ -3699,84 +3563,6 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 
 
 /**
- *  e1000_read_flash_data32_ich8lan - Read dword from NVM
- *  @hw: pointer to the HW structure
- *  @offset: The offset (in bytes) of the dword to read.
- *  @data: Pointer to the dword to store the value read.
- *
- *  Reads a byte or word from the NVM using the flash access registers.
- **/
-
-static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
-					   u32 *data)
-{
-	union ich8_hws_flash_status hsfsts;
-	union ich8_hws_flash_ctrl hsflctl;
-	u32 flash_linear_addr;
-	s32 ret_val = -E1000_ERR_NVM;
-	u8 count = 0;
-
-	DEBUGFUNC("e1000_read_flash_data_ich8lan");
-
-		if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
-		    hw->mac.type != e1000_pch_spt)
-			return -E1000_ERR_NVM;
-	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
-			     hw->nvm.flash_base_addr);
-
-	do {
-		usec_delay(1);
-		/* Steps */
-		ret_val = e1000_flash_cycle_init_ich8lan(hw);
-		if (ret_val != E1000_SUCCESS)
-			break;
-		/* In SPT, This register is in Lan memory space, not flash.
-		 * Therefore, only 32 bit access is supported
-		 */
-		hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
-
-		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
-		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
-		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
-		/* In SPT, This register is in Lan memory space, not flash.
-		 * Therefore, only 32 bit access is supported
-		 */
-		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
-				      (u32)hsflctl.regval << 16);
-		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
-
-		ret_val = e1000_flash_cycle_ich8lan(hw,
-						ICH_FLASH_READ_COMMAND_TIMEOUT);
-
-		/* Check if FCERR is set to 1, if set to 1, clear it
-		 * and try the whole sequence a few more times, else
-		 * read in (shift in) the Flash Data0, the order is
-		 * least significant byte first msb to lsb
-		 */
-		if (ret_val == E1000_SUCCESS) {
-			*data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
-			break;
-		} else {
-			/* If we've gotten here, then things are probably
-			 * completely hosed, but if the error condition is
-			 * detected, it won't hurt to give it another try...
-			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
-			 */
-			hsfsts.regval = E1000_READ_FLASH_REG16(hw,
-							      ICH_FLASH_HSFSTS);
-			if (hsfsts.hsf_status.flcerr) {
-				/* Repeat for some time before giving up. */
-				continue;
-			} else if (!hsfsts.hsf_status.flcdone) {
-				DEBUGOUT("Timeout error - flash cycle did not complete.\n");
-				break;
-			}
-		}
-	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
-
-	return ret_val;
-}
-/**
  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
  *  @hw: pointer to the HW structure
  *  @offset: The offset (in bytes) of the word(s) to write.
@@ -3813,175 +3599,6 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
 }
 
 /**
- *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
- *  @hw: pointer to the HW structure
- *
- *  The NVM checksum is updated by calling the generic update_nvm_checksum,
- *  which writes the checksum to the shadow ram.  The changes in the shadow
- *  ram are then committed to the EEPROM by processing each bank at a time
- *  checking for the modified bit and writing only the pending changes.
- *  After a successful commit, the shadow ram is cleared and is ready for
- *  future writes.
- **/
-static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
-{
-	struct e1000_nvm_info *nvm = &hw->nvm;
-	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
-	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
-	s32 ret_val;
-	u32 dword = 0;
-
-	DEBUGFUNC("e1000_update_nvm_checksum_spt");
-
-	ret_val = e1000_update_nvm_checksum_generic(hw);
-	if (ret_val)
-		goto out;
-
-	if (nvm->type != e1000_nvm_flash_sw)
-		goto out;
-
-	nvm->ops.acquire(hw);
-
-	/* We're writing to the opposite bank so if we're on bank 1,
-	 * write to bank 0 etc.  We also need to erase the segment that
-	 * is going to be written
-	 */
-	ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
-	if (ret_val != E1000_SUCCESS) {
-		DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
-		bank = 0;
-	}
-
-	if (bank == 0) {
-		new_bank_offset = nvm->flash_bank_size;
-		old_bank_offset = 0;
-		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
-		if (ret_val)
-			goto release;
-	} else {
-		old_bank_offset = nvm->flash_bank_size;
-		new_bank_offset = 0;
-		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
-		if (ret_val)
-			goto release;
-	}
-	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
-		/* Determine whether to write the value stored
-		 * in the other NVM bank or a modified value stored
-		 * in the shadow RAM
-		 */
-		ret_val = e1000_read_flash_dword_ich8lan(hw,
-							 i + old_bank_offset,
-							 &dword);
-
-		if (dev_spec->shadow_ram[i].modified) {
-			dword &= 0xffff0000;
-			dword |= (dev_spec->shadow_ram[i].value & 0xffff);
-		}
-		if (dev_spec->shadow_ram[i + 1].modified) {
-			dword &= 0x0000ffff;
-			dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
-				  << 16);
-		}
-		if (ret_val)
-			break;
-
-		/* If the word is 0x13, then make sure the signature bits
-		 * (15:14) are 11b until the commit has completed.
-		 * This will allow us to write 10b which indicates the
-		 * signature is valid.  We want to do this after the write
-		 * has completed so that we don't mark the segment valid
-		 * while the write is still in progress
-		 */
-		if (i == E1000_ICH_NVM_SIG_WORD - 1)
-			dword |= E1000_ICH_NVM_SIG_MASK << 16;
-
-		/* Convert offset to bytes. */
-		act_offset = (i + new_bank_offset) << 1;
-
-		usec_delay(100);
-
-		/* Write the data to the new bank. Offset in words*/
-		act_offset = i + new_bank_offset;
-		ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
-								dword);
-		if (ret_val)
-			break;
-	 }
-
-	/* Don't bother writing the segment valid bits if sector
-	 * programming failed.
-	 */
-	if (ret_val) {
-		DEBUGOUT("Flash commit failed.\n");
-		goto release;
-	}
-
-	/* Finally validate the new segment by setting bit 15:14
-	 * to 10b in word 0x13 , this can be done without an
-	 * erase as well since these bits are 11 to start with
-	 * and we need to change bit 14 to 0b
-	 */
-	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
-
-	/*offset in words but we read dword*/
-	--act_offset;
-	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
-
-	if (ret_val)
-		goto release;
-
-	dword &= 0xBFFFFFFF;
-	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
-
-	if (ret_val)
-		goto release;
-
-	/* And invalidate the previously valid segment by setting
-	 * its signature word (0x13) high_byte to 0b. This can be
-	 * done without an erase because flash erase sets all bits
-	 * to 1's. We can write 1's to 0's without an erase
-	 */
-	act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
-
-	/* offset in words but we read dword*/
-	act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
-	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
-
-	if (ret_val)
-		goto release;
-
-	dword &= 0x00FFFFFF;
-	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
-
-	if (ret_val)
-		goto release;
-
-	/* Great!  Everything worked, we can now clear the cached entries. */
-	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
-		dev_spec->shadow_ram[i].modified = FALSE;
-		dev_spec->shadow_ram[i].value = 0xFFFF;
-	}
-
-release:
-	nvm->ops.release(hw);
-
-	/* Reload the EEPROM, or else modifications will not appear
-	 * until after the next adapter reset.
-	 */
-	if (!ret_val) {
-		nvm->ops.reload(hw);
-		msec_delay(10);
-	}
-
-out:
-	if (ret_val)
-		DEBUGOUT1("NVM update error: %d\n", ret_val);
-
-	return ret_val;
-}
-
-/**
  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
  *  @hw: pointer to the HW structure
  *
@@ -4158,7 +3775,6 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
 	 */
 	switch (hw->mac.type) {
 	case e1000_pch_lpt:
-	case e1000_pch_spt:
 		word = NVM_COMPAT;
 		valid_csum_mask = NVM_COMPAT_VALID_CSUM;
 		break;
@@ -4206,13 +3822,8 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 
 	DEBUGFUNC("e1000_write_ich8_data");
 
-	if (hw->mac.type == e1000_pch_spt) {
-		if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
-			return -E1000_ERR_NVM;
-	} else {
-		if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
-			return -E1000_ERR_NVM;
-	}
+	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
+		return -E1000_ERR_NVM;
 
 	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
 			     hw->nvm.flash_base_addr);
@@ -4223,29 +3834,12 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 		ret_val = e1000_flash_cycle_init_ich8lan(hw);
 		if (ret_val != E1000_SUCCESS)
 			break;
-		/* In SPT, This register is in Lan memory space, not
-		 * flash.  Therefore, only 32 bit access is supported
-		 */
-		if (hw->mac.type == e1000_pch_spt)
-			hsflctl.regval =
-			    E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
-		else
-			hsflctl.regval =
-			    E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
+		hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
 
 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
 		hsflctl.hsf_ctrl.fldbcount = size - 1;
 		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
-		/* In SPT, This register is in Lan memory space,
-		 * not flash.  Therefore, only 32 bit access is
-		 * supported
-		 */
-		if (hw->mac.type == e1000_pch_spt)
-			E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
-					      hsflctl.regval << 16);
-		else
-			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
-						hsflctl.regval);
+		E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
 
 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
 
@@ -4283,94 +3877,6 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 	return ret_val;
 }
 
-/**
-*  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
-*  @hw: pointer to the HW structure
-*  @offset: The offset (in bytes) of the dwords to read.
-*  @data: The 4 bytes to write to the NVM.
-*
-*  Writes one/two/four bytes to the NVM using the flash access registers.
-**/
-static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
-					    u32 data)
-{
-	union ich8_hws_flash_status hsfsts;
-	union ich8_hws_flash_ctrl hsflctl;
-	u32 flash_linear_addr;
-	s32 ret_val;
-	u8 count = 0;
-
-	DEBUGFUNC("e1000_write_flash_data32_ich8lan");
-
-	if (hw->mac.type == e1000_pch_spt) {
-		if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
-			return -E1000_ERR_NVM;
-	}
-	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
-			     hw->nvm.flash_base_addr);
-	do {
-		usec_delay(1);
-		/* Steps */
-		ret_val = e1000_flash_cycle_init_ich8lan(hw);
-		if (ret_val != E1000_SUCCESS)
-			break;
-
-		/* In SPT, This register is in Lan memory space, not
-		 * flash.  Therefore, only 32 bit access is supported
-		 */
-		if (hw->mac.type == e1000_pch_spt)
-			hsflctl.regval = E1000_READ_FLASH_REG(hw,
-							      ICH_FLASH_HSFSTS)
-					 >> 16;
-		else
-			hsflctl.regval = E1000_READ_FLASH_REG16(hw,
-							      ICH_FLASH_HSFCTL);
-
-		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
-		hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
-
-		/* In SPT, This register is in Lan memory space,
-		 * not flash.  Therefore, only 32 bit access is
-		 * supported
-		 */
-		if (hw->mac.type == e1000_pch_spt)
-			E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
-					      hsflctl.regval << 16);
-		else
-			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
-						hsflctl.regval);
-
-		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
-
-		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
-
-		/* check if FCERR is set to 1 , if set to 1, clear it
-		 * and try the whole sequence a few more times else done
-		 */
-		ret_val = e1000_flash_cycle_ich8lan(hw,
-					       ICH_FLASH_WRITE_COMMAND_TIMEOUT);
-
-		if (ret_val == E1000_SUCCESS)
-			break;
-
-		/* If we're here, then things are most likely
-		 * completely hosed, but if the error condition
-		 * is detected, it won't hurt to give it another
-		 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
-		 */
-		hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
-
-		if (hsfsts.hsf_status.flcerr)
-			/* Repeat for some time before giving up. */
-			continue;
-		if (!hsfsts.hsf_status.flcdone) {
-			DEBUGOUT("Timeout error - flash cycle did not complete.\n");
-			break;
-		}
-	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
-
-	return ret_val;
-}
 
 /**
  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
@@ -4393,44 +3899,6 @@ static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 
 
 /**
-*  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
-*  @hw: pointer to the HW structure
-*  @offset: The offset of the word to write.
-*  @dword: The dword to write to the NVM.
-*
-*  Writes a single dword to the NVM using the flash access registers.
-*  Goes through a retry algorithm before giving up.
-**/
-static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
-						 u32 offset, u32 dword)
-{
-	s32 ret_val;
-	u16 program_retries;
-
-	DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
-
-	/* Must convert word offset into bytes. */
-	offset <<= 1;
-
-	ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
-
-	if (!ret_val)
-		return ret_val;
-	for (program_retries = 0; program_retries < 100; program_retries++) {
-		DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
-		usec_delay(100);
-		ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
-		if (ret_val == E1000_SUCCESS)
-			break;
-	}
-	if (program_retries == 100)
-		return -E1000_ERR_NVM;
-
-	return E1000_SUCCESS;
-}
-
-
-/**
  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
  *  @hw: pointer to the HW structure
  *  @offset: The offset of the byte to write.
@@ -4538,22 +4006,12 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
 			/* Write a value 11 (block Erase) in Flash
 			 * Cycle field in hw flash control
 			 */
-			if (hw->mac.type == e1000_pch_spt)
-				hsflctl.regval =
-				    E1000_READ_FLASH_REG(hw,
-							 ICH_FLASH_HSFSTS)>>16;
-			else
-				hsflctl.regval =
-				    E1000_READ_FLASH_REG16(hw,
-							   ICH_FLASH_HSFCTL);
+			hsflctl.regval =
+			    E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
 
 			hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
-			if (hw->mac.type == e1000_pch_spt)
-				E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
-						      hsflctl.regval << 16);
-			else
-				E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
-							hsflctl.regval);
+			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
+						hsflctl.regval);
 
 			/* Write the last 24 bits of an index within the
 			 * block into Flash Linear address field in Flash
@@ -4986,8 +4444,7 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
 	E1000_WRITE_REG(hw, E1000_RFCTL, reg);
 
 	/* Enable ECC on Lynxpoint */
-	if ((hw->mac.type == e1000_pch_lpt) ||
-	    (hw->mac.type == e1000_pch_spt)) {
+	if (hw->mac.type == e1000_pch_lpt) {
 		reg = E1000_READ_REG(hw, E1000_PBECCSTS);
 		reg |= E1000_PBECCSTS_ECC_ENABLE;
 		E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
@@ -5419,8 +4876,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
 		if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
 		    (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
 		    (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
-		    (device_id == E1000_DEV_ID_PCH_I218_V3) ||
-		    (hw->mac.type == e1000_pch_spt)) {
+		    (device_id == E1000_DEV_ID_PCH_I218_V3)) {
 			u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
 
 			E1000_WRITE_REG(hw, E1000_FEXTNVM6,
@@ -5536,18 +4992,18 @@ out:
  *  the PHY.
  *  On i217, setup Intel Rapid Start Technology.
  **/
-u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
+void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
 {
 	s32 ret_val;
 
 	DEBUGFUNC("e1000_resume_workarounds_pchlan");
 	if (hw->mac.type < e1000_pch2lan)
-		return E1000_SUCCESS;
+		return;
 
 	ret_val = e1000_init_phy_workarounds_pchlan(hw);
 	if (ret_val) {
 		DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
-		return ret_val;
+		return;
 	}
 
 	/* For i217 Intel Rapid Start Technology support when the system
@@ -5561,7 +5017,7 @@ u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
 		ret_val = hw->phy.ops.acquire(hw);
 		if (ret_val) {
 			DEBUGOUT("Failed to setup iRST\n");
-			return ret_val;
+			return;
 		}
 
 		/* Clear Auto Enable LPI after link up */
@@ -5595,9 +5051,7 @@ release:
 		if (ret_val)
 			DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
 		hw->phy.ops.release(hw);
-		return ret_val;
 	}
-	return E1000_SUCCESS;
 }
 
 /**
diff --git a/sys/dev/e1000/e1000_ich8lan.h b/sys/dev/e1000/e1000_ich8lan.h
index b2d099150d75..9cb79c0b0c99 100644
--- a/sys/dev/e1000/e1000_ich8lan.h
+++ b/sys/dev/e1000/e1000_ich8lan.h
@@ -107,25 +107,9 @@
 
 #define E1000_FEXTNVM6_REQ_PLL_CLK	0x00000100
 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION	0x00000200
-#define E1000_FEXTNVM6_K1_OFF_ENABLE	0x80000000
-/* bit for disabling packet buffer read */
-#define E1000_FEXTNVM7_DISABLE_PB_READ	0x00040000
-#define E1000_FEXTNVM7_SIDE_CLK_UNGATE	0x00000004
+
 #define E1000_FEXTNVM7_DISABLE_SMB_PERST	0x00000020
-#define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS	0x00000800
-#define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS	0x00001000
-#define E1000_FEXTNVM11_DISABLE_PB_READ		0x00000200
-#define E1000_FEXTNVM11_DISABLE_MULR_FIX	0x00002000
-
-/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
-#define E1000_RXDCTL_THRESH_UNIT_DESC	0x01000000
-
-#define NVM_SIZE_MULTIPLIER 4096  /*multiplier for NVMS field*/
-#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/
-#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
-#define E1000_SPT_B_STEP_REV	0x10 /*SPT B step Rev ID*/
-#define E1000_TARC0_CB_MULTIQ_2_REQ	(1 << 29)
-#define E1000_TARC0_CB_MULTIQ_3_REQ	(1 << 28 | 1 << 29)
+
 #define PCIE_ICH8_SNOOP_ALL	PCIE_NO_SNOOP_ALL
 
 #define E1000_ICH_RAR_ENTRIES	7
@@ -187,8 +171,6 @@
 
 #define E1000_NVM_K1_CONFIG	0x1B /* NVM K1 Config Word */
 #define E1000_NVM_K1_ENABLE	0x1  /* NVM Enable K1 bit */
-#define K1_ENTRY_LATENCY	0
-#define K1_MIN_TIME		1
 
 /* SMBus Control Phy Register */
 #define CV_SMB_CTRL		PHY_REG(769, 23)
@@ -299,13 +281,36 @@
 /* Receive Address Initial CRC Calculation */
 #define E1000_PCH_RAICC(_n)	(0x05F50 + ((_n) * 4))
 
+/* Latency Tolerance Reporting */
+#define E1000_LTRV			0x000F8
+#define E1000_LTRV_VALUE_MASK		0x000003FF
+#define E1000_LTRV_SCALE_MAX		5
+#define E1000_LTRV_SCALE_FACTOR		5
+#define E1000_LTRV_SCALE_SHIFT		10
+#define E1000_LTRV_SCALE_MASK		0x00001C00
+#define E1000_LTRV_REQ_SHIFT		15
+#define E1000_LTRV_NOSNOOP_SHIFT	16
+#define E1000_LTRV_SEND			(1 << 30)
+
+/* Proprietary Latency Tolerance Reporting PCI Capability */
+#define E1000_PCI_LTR_CAP_LPT		0xA8
+
+/* OBFF Control & Threshold Defines */
+#define E1000_SVCR_OFF_EN		0x00000001
+#define E1000_SVCR_OFF_MASKINT		0x00001000
+#define E1000_SVCR_OFF_TIMER_MASK	0xFFFF0000
+#define E1000_SVCR_OFF_TIMER_SHIFT	16
+#define E1000_SVT_OFF_HWM_MASK		0x0000001F
+
+#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 #define E1000_PCI_REVISION_ID_REG	0x08
+#endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */
 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
 						 bool state);
 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
-u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
+void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
diff --git a/sys/dev/e1000/e1000_mac.c b/sys/dev/e1000/e1000_mac.c
index 58137b1bb904..1c863073f082 100644
--- a/sys/dev/e1000/e1000_mac.c
+++ b/sys/dev/e1000/e1000_mac.c
@@ -70,6 +70,7 @@ void e1000_init_mac_ops_generic(struct e1000_hw *hw)
 	mac->ops.setup_link = e1000_null_ops_generic;
 	mac->ops.get_link_up_info = e1000_null_link_info;
 	mac->ops.check_for_link = e1000_null_ops_generic;
+	mac->ops.set_obff_timer = e1000_null_set_obff_timer;
 	/* Management */
 	mac->ops.check_mng_mode = e1000_null_mng_mode;
 	/* VLAN, MC, etc. */
@@ -155,6 +156,17 @@ int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
 }
 
 /**
+ *  e1000_null_set_obff_timer - No-op function, return 0
+ *  @hw: pointer to the HW structure
+ **/
+s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw,
+			      u32 E1000_UNUSEDARG a)
+{
+	DEBUGFUNC("e1000_null_set_obff_timer");
+	return E1000_SUCCESS;
+}
+
+/**
  *  e1000_get_bus_info_pci_generic - Get PCI(x) bus information
  *  @hw: pointer to the HW structure
  *
diff --git a/sys/dev/e1000/e1000_mac.h b/sys/dev/e1000/e1000_mac.h
index 2445f4652535..1daed9bc9472 100644
--- a/sys/dev/e1000/e1000_mac.h
+++ b/sys/dev/e1000/e1000_mac.h
@@ -36,7 +36,9 @@
 #define _E1000_MAC_H_
 
 void e1000_init_mac_ops_generic(struct e1000_hw *hw);
+#ifndef E1000_REMOVED
 #define E1000_REMOVED(a) (0)
+#endif /* E1000_REMOVED */
 void e1000_null_mac_generic(struct e1000_hw *hw);
 s32  e1000_null_ops_generic(struct e1000_hw *hw);
 s32  e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d);
@@ -44,6 +46,7 @@ bool e1000_null_mng_mode(struct e1000_hw *hw);
 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a);
 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b);
 int  e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a);
+s32  e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a);
 s32  e1000_blink_led_generic(struct e1000_hw *hw);
 s32  e1000_check_for_copper_link_generic(struct e1000_hw *hw);
 s32  e1000_check_for_fiber_link_generic(struct e1000_hw *hw);
diff --git a/sys/dev/e1000/e1000_nvm.c b/sys/dev/e1000/e1000_nvm.c
index 6eafbb2e6dd3..0a1a18d4a973 100644
--- a/sys/dev/e1000/e1000_nvm.c
+++ b/sys/dev/e1000/e1000_nvm.c
@@ -930,41 +930,6 @@ s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
 	return E1000_SUCCESS;
 }
 
-/**
- *  e1000_read_pba_num_generic - Read device part number
- *  @hw: pointer to the HW structure
- *  @pba_num: pointer to device part number
- *
- *  Reads the product board assembly (PBA) number from the EEPROM and stores
- *  the value in pba_num.
- **/
-s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
-{
-	s32 ret_val;
-	u16 nvm_data;
-
-	DEBUGFUNC("e1000_read_pba_num_generic");
-
-	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
-	if (ret_val) {
-		DEBUGOUT("NVM Read Error\n");
-		return ret_val;
-	} else if (nvm_data == NVM_PBA_PTR_GUARD) {
-		DEBUGOUT("NVM Not Supported\n");
-		return -E1000_NOT_IMPLEMENTED;
-	}
-	*pba_num = (u32)(nvm_data << 16);
-
-	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
-	if (ret_val) {
-		DEBUGOUT("NVM Read Error\n");
-		return ret_val;
-	}
-	*pba_num |= nvm_data;
-
-	return E1000_SUCCESS;
-}
-
 
 /**
  *  e1000_read_pba_raw
@@ -1267,115 +1232,4 @@ static void e1000_reload_nvm_generic(struct e1000_hw *hw)
 	E1000_WRITE_FLUSH(hw);
 }
 
-/**
- *  e1000_get_fw_version - Get firmware version information
- *  @hw: pointer to the HW structure
- *  @fw_vers: pointer to output version structure
- *
- *  unsupported/not present features return 0 in version structure
- **/
-void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
-{
-	u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
-	u8 q, hval, rem, result;
-	u16 comb_verh, comb_verl, comb_offset;
-
-	memset(fw_vers, 0, sizeof(struct e1000_fw_version));
-
-	/* basic eeprom version numbers, bits used vary by part and by tool
-	 * used to create the nvm images */
-	/* Check which data format we have */
-	switch (hw->mac.type) {
-	case e1000_i211:
-		e1000_read_invm_version(hw, fw_vers);
-		return;
-	case e1000_82575:
-	case e1000_82576:
-	case e1000_82580:
-		hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
-		/* Use this format, unless EETRACK ID exists,
-		 * then use alternate format
-		 */
-		if ((etrack_test &  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
-			hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
-			fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
-					      >> NVM_MAJOR_SHIFT;
-			fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
-					      >> NVM_MINOR_SHIFT;
-			fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
-			goto etrack_id;
-		}
-		break;
-	case e1000_i210:
-		if (!(e1000_get_flash_presence_i210(hw))) {
-			e1000_read_invm_version(hw, fw_vers);
-			return;
-		}
-		/* fall through */
-	case e1000_i350:
-		hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
-		/* find combo image version */
-		hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
-		if ((comb_offset != 0x0) &&
-		    (comb_offset != NVM_VER_INVALID)) {
-
-			hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
-					 + 1), 1, &comb_verh);
-			hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
-					 1, &comb_verl);
-
-			/* get Option Rom version if it exists and is valid */
-			if ((comb_verh && comb_verl) &&
-			    ((comb_verh != NVM_VER_INVALID) &&
-			     (comb_verl != NVM_VER_INVALID))) {
-
-				fw_vers->or_valid = TRUE;
-				fw_vers->or_major =
-					comb_verl >> NVM_COMB_VER_SHFT;
-				fw_vers->or_build =
-					(comb_verl << NVM_COMB_VER_SHFT)
-					| (comb_verh >> NVM_COMB_VER_SHFT);
-				fw_vers->or_patch =
-					comb_verh & NVM_COMB_VER_MASK;
-			}
-		}
-		break;
-	default:
-		hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
-		return;
-	}
-	hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
-	fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
-			      >> NVM_MAJOR_SHIFT;
-
-	/* check for old style version format in newer images*/
-	if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
-		eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
-	} else {
-		eeprom_verl = (fw_version & NVM_MINOR_MASK)
-				>> NVM_MINOR_SHIFT;
-	}
-	/* Convert minor value to hex before assigning to output struct
-	 * Val to be converted will not be higher than 99, per tool output
-	 */
-	q = eeprom_verl / NVM_HEX_CONV;
-	hval = q * NVM_HEX_TENS;
-	rem = eeprom_verl % NVM_HEX_CONV;
-	result = hval + rem;
-	fw_vers->eep_minor = result;
-
-etrack_id:
-	if ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
-		hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
-		hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
-		fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
-			| eeprom_verl;
-	} else if ((etrack_test & NVM_ETRACK_VALID) == 0) {
-		hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
-		hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
-		fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |
-				     eeprom_verl;
-	}
-}
-
 
diff --git a/sys/dev/e1000/e1000_nvm.h b/sys/dev/e1000/e1000_nvm.h
index 66461c70848a..31f2180a0b6b 100644
--- a/sys/dev/e1000/e1000_nvm.h
+++ b/sys/dev/e1000/e1000_nvm.h
@@ -35,26 +35,12 @@
 #ifndef _E1000_NVM_H_
 #define _E1000_NVM_H_
 
+#if !defined(NO_READ_PBA_RAW) || !defined(NO_WRITE_PBA_RAW)
 struct e1000_pba {
 	u16 word[2];
 	u16 *pba_block;
 };
-
-struct e1000_fw_version {
-	u32 etrack_id;
-	u16 eep_major;
-	u16 eep_minor;
-	u16 eep_build;
-
-	u8 invm_major;
-	u8 invm_minor;
-	u8 invm_img_type;
-
-	bool or_valid;
-	u16 or_major;
-	u16 or_build;
-	u16 or_patch;
-};
+#endif
 
 
 void e1000_init_nvm_ops_generic(struct e1000_hw *hw);
@@ -66,7 +52,6 @@ s32  e1000_acquire_nvm_generic(struct e1000_hw *hw);
 
 s32  e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
 s32  e1000_read_mac_addr_generic(struct e1000_hw *hw);
-s32  e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num);
 s32  e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 				   u32 pba_num_size);
 s32  e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size);
@@ -91,8 +76,6 @@ s32  e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
 s32  e1000_update_nvm_checksum_generic(struct e1000_hw *hw);
 void e1000_stop_nvm(struct e1000_hw *hw);
 void e1000_release_nvm_generic(struct e1000_hw *hw);
-void e1000_get_fw_version(struct e1000_hw *hw,
-			  struct e1000_fw_version *fw_vers);
 
 #define E1000_STM_OPCODE	0xDB00
 
diff --git a/sys/dev/e1000/e1000_osdep.h b/sys/dev/e1000/e1000_osdep.h
index 1664ef0ff363..fc46f48df6cc 100644
--- a/sys/dev/e1000/e1000_osdep.h
+++ b/sys/dev/e1000/e1000_osdep.h
@@ -74,6 +74,10 @@
 #define STATIC			static
 #define FALSE			0
 #define TRUE			1
+#ifndef __bool_true_false_are_defined
+#define false			FALSE 
+#define true			TRUE
+#endif
 #define CMD_MEM_WRT_INVALIDATE	0x0010  /* BIT_4 */
 #define PCI_COMMAND_REGISTER	PCIR_COMMAND
 
@@ -95,6 +99,9 @@ typedef int64_t		s64;
 typedef int32_t		s32;
 typedef int16_t		s16;
 typedef int8_t		s8;
+#ifndef __bool_true_false_are_defined
+typedef boolean_t	bool;
+#endif
 
 #define __le16		u16
 #define __le32		u32
diff --git a/sys/dev/e1000/e1000_phy.c b/sys/dev/e1000/e1000_phy.c
index 49cdec3a143c..0c8ccd2ba627 100644
--- a/sys/dev/e1000/e1000_phy.c
+++ b/sys/dev/e1000/e1000_phy.c
@@ -1827,10 +1827,10 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
 					     phy_data);
 		if (ret_val)
 			return ret_val;
-
-		DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
 	}
 
+	DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
+
 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
 	if (ret_val)
 		return ret_val;
diff --git a/sys/dev/e1000/e1000_regs.h b/sys/dev/e1000/e1000_regs.h
index e07ec0592ef5..7c81a8988243 100644
--- a/sys/dev/e1000/e1000_regs.h
+++ b/sys/dev/e1000/e1000_regs.h
@@ -65,9 +65,6 @@
 #define E1000_FEXTNVM4	0x00024  /* Future Extended NVM 4 - RW */
 #define E1000_FEXTNVM6	0x00010  /* Future Extended NVM 6 - RW */
 #define E1000_FEXTNVM7	0x000E4  /* Future Extended NVM 7 - RW */
-#define E1000_FEXTNVM9	0x5BB4  /* Future Extended NVM 9 - RW */
-#define E1000_FEXTNVM11	0x5BBC  /* Future Extended NVM 11 - RW */
-#define E1000_PCIEANACFG	0x00F18 /* PCIE Analog Config */
 #define E1000_FCT	0x00030  /* Flow Control Type - RW */
 #define E1000_CONNSW	0x00034  /* Copper/Fiber switch control - RW */
 #define E1000_VET	0x00038  /* VLAN Ether Type - RW */
@@ -110,8 +107,6 @@
 #define E1000_PBA	0x01000  /* Packet Buffer Allocation - RW */
 #define E1000_PBS	0x01008  /* Packet Buffer Size */
 #define E1000_PBECCSTS	0x0100C  /* Packet Buffer ECC Status - RW */
-#define E1000_IOSFPC	0x00F28  /* TX corrupted data  */
-#define E1000_IOSFPC	0x00F28  /* TX corrupted data  */
 #define E1000_EEMNGCTL	0x01010  /* MNG EEprom Control */
 #define E1000_EEARBC	0x01024  /* EEPROM Auto Read Bus Control */
 #define E1000_EEARBC_I210	0x12024 /* EEPROM Auto Read Bus Control */
@@ -593,10 +588,6 @@
 #define E1000_TIMADJL	0x0B60C /* Time sync time adjustment offset Low - RW */
 #define E1000_TIMADJH	0x0B610 /* Time sync time adjustment offset High - RW */
 #define E1000_TSAUXC	0x0B640 /* Timesync Auxiliary Control register */
-#define	E1000_SYSSTMPL	0x0B648 /* HH Timesync system stamp low register */
-#define	E1000_SYSSTMPH	0x0B64C /* HH Timesync system stamp hi register */
-#define	E1000_PLTSTMPL	0x0B640 /* HH Timesync platform stamp low register */
-#define	E1000_PLTSTMPH	0x0B644 /* HH Timesync platform stamp hi register */
 #define E1000_SYSTIMR	0x0B6F8 /* System time register Residue */
 #define E1000_TSICR	0x0B66C /* Interrupt Cause Register */
 #define E1000_TSIM	0x0B674 /* Interrupt Mask Register */
@@ -689,6 +680,7 @@
 #define E1000_O2BGPTC	0x08FE4 /* OS2BMC packets received by BMC */
 #define E1000_O2BSPC	0x0415C /* OS2BMC packets transmitted by host */
 
+#define E1000_DOBFFCTL	0x3F24 /* DMA OBFF Control Register */
 
 
 #endif
diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c
index bece7ec3f3b3..d9b3ca559d6e 100644
--- a/sys/dev/e1000/if_em.c
+++ b/sys/dev/e1000/if_em.c
@@ -103,7 +103,7 @@ int	em_display_debug_stats = 0;
 /*********************************************************************
  *  Driver version:
  *********************************************************************/
-char em_driver_version[] = "7.5.2";
+char em_driver_version[] = "7.4.2";
 
 /*********************************************************************
  *  PCI Device ID Table
@@ -191,11 +191,6 @@ static em_vendor_info_t em_vendor_info_array[] =
 	{ 0x8086, E1000_DEV_ID_PCH_I218_V2,	PCI_ANY_ID, PCI_ANY_ID, 0},
 	{ 0x8086, E1000_DEV_ID_PCH_I218_LM3,	PCI_ANY_ID, PCI_ANY_ID, 0},
 	{ 0x8086, E1000_DEV_ID_PCH_I218_V3,	PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_PCH_SPT_I219_V,  PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2,
-                                                PCI_ANY_ID, PCI_ANY_ID, 0},
-	{ 0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, PCI_ANY_ID, PCI_ANY_ID, 0},
 	/* required last entry */
 	{ 0, 0, 0, 0, 0}
 };
@@ -243,7 +238,6 @@ static void	em_free_pci_resources(struct adapter *);
 static void	em_local_timer(void *);
 static void	em_reset(struct adapter *);
 static int	em_setup_interface(device_t, struct adapter *);
-static void	em_flush_desc_rings(struct adapter *);
 
 static void	em_setup_transmit_structures(struct adapter *);
 static void	em_initialize_transmit_unit(struct adapter *);
@@ -590,20 +584,6 @@ em_attach(device_t dev)
 	}
 
 	/*
-	** In the new SPT device flash is not  a
-	** separate BAR, rather it is also in BAR0,
-	** so use the same tag and handle for the
-	** FLASH read/write macros in the shared
-	** code.
-	*/
-	if (hw->mac.type == e1000_pch_spt) {
-		adapter->osdep.flash_bus_space_tag =
-		    adapter->osdep.mem_bus_space_tag;
-		adapter->osdep.flash_bus_space_handle =
-		    adapter->osdep.mem_bus_space_handle;
-	}
-
-	/*
 	 * Setup MSI/X or MSI if PCI Express
 	 */
 	adapter->msix = em_setup_msix(adapter);
@@ -1188,7 +1168,6 @@ em_ioctl(if_t ifp, u_long command, caddr_t data)
 		case e1000_ich10lan:
 		case e1000_pch2lan:
 		case e1000_pch_lpt:
-		case e1000_pch_spt:
 		case e1000_82574:
 		case e1000_82583:
 		case e1000_80003es2lan:	/* 9K Jumbo Frame size */
@@ -1390,15 +1369,8 @@ em_init_locked(struct adapter *adapter)
 	if_clearhwassist(ifp);
 	if (if_getcapenable(ifp) & IFCAP_TXCSUM)
 		if_sethwassistbits(ifp, CSUM_TCP | CSUM_UDP, 0);
-	/* 
-	** There have proven to be problems with TSO when not
-	** at full gigabit speed, so disable the assist automatically
-	** when at lower speeds.  -jfv
-	*/
-	if (if_getcapenable(ifp) & IFCAP_TSO4) {
-		if (adapter->link_speed == SPEED_1000)
-			if_sethwassistbits(ifp, CSUM_TSO, 0);
-	}
+	if (if_getcapenable(ifp) & IFCAP_TSO4)
+		if_sethwassistbits(ifp, CSUM_TSO, 0);
 
 	/* Configure for OS presence */
 	em_init_manageability(adapter);
@@ -2378,8 +2350,6 @@ em_update_link_status(struct adapter *adapter)
 	switch (hw->phy.media_type) {
 	case e1000_media_type_copper:
 		if (hw->mac.get_link_status) {
-			if (hw->mac.type == e1000_pch_spt)
-				msec_delay(50);
 			/* Do the work to read phy */
 			e1000_check_for_link(hw);
 			link_check = !hw->mac.get_link_status;
@@ -2471,10 +2441,6 @@ em_stop(void *arg)
 		EM_TX_UNLOCK(txr);
 	}
 
-	/* I219 needs some special flushing to avoid hangs */
-	if (adapter->hw.mac.type == e1000_pch_spt)
-		em_flush_desc_rings(adapter);
-
 	e1000_reset_hw(&adapter->hw);
 	E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
 
@@ -2894,116 +2860,6 @@ msi:
 }
 
 
-/*
-** The 3 following flush routines are used as a workaround in the
-** I219 client parts and only for them.
-**
-** em_flush_tx_ring - remove all descriptors from the tx_ring
-**
-** We want to clear all pending descriptors from the TX ring.
-** zeroing happens when the HW reads the regs. We  assign the ring itself as
-** the data of the next descriptor. We don't care about the data we are about
-** to reset the HW.
-*/
-static void
-em_flush_tx_ring(struct adapter *adapter)
-{
-	struct e1000_hw		*hw = &adapter->hw;
-	struct tx_ring		*txr = adapter->tx_rings;
-	struct e1000_tx_desc	*txd;
-	u32			tctl, txd_lower = E1000_TXD_CMD_IFCS;
-	u16			size = 512;
-
-	tctl = E1000_READ_REG(hw, E1000_TCTL);
-	E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
-
-	txd = &txr->tx_base[txr->next_avail_desc++];
-	if (txr->next_avail_desc == adapter->num_tx_desc)
-		txr->next_avail_desc = 0;
-
-	/* Just use the ring as a dummy buffer addr */
-	txd->buffer_addr = txr->txdma.dma_paddr;
-	txd->lower.data = htole32(txd_lower | size);
-	txd->upper.data = 0;
-
-	/* flush descriptors to memory before notifying the HW */
-	wmb();
-
-	E1000_WRITE_REG(hw, E1000_TDT(0), txr->next_avail_desc);
-	mb();
-	usec_delay(250);
-}
-
-/*
-** em_flush_rx_ring - remove all descriptors from the rx_ring
-**
-** Mark all descriptors in the RX ring as consumed and disable the rx ring
-*/
-static void
-em_flush_rx_ring(struct adapter *adapter)
-{
-	struct e1000_hw	*hw = &adapter->hw;
-	u32		rctl, rxdctl;
-
-	rctl = E1000_READ_REG(hw, E1000_RCTL);
-	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
-	E1000_WRITE_FLUSH(hw);
-	usec_delay(150);
-
-	rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
-	/* zero the lower 14 bits (prefetch and host thresholds) */
-	rxdctl &= 0xffffc000;
-	/*
-	 * update thresholds: prefetch threshold to 31, host threshold to 1
-	 * and make sure the granularity is "descriptors" and not "cache lines"
-	 */
-	rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
-	E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl);
-
-	/* momentarily enable the RX ring for the changes to take effect */
-	E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);
-	E1000_WRITE_FLUSH(hw);
-	usec_delay(150);
-	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
-}
-
-/*
-** em_flush_desc_rings - remove all descriptors from the descriptor rings
-**
-** In i219, the descriptor rings must be emptied before resetting the HW
-** or before changing the device state to D3 during runtime (runtime PM).
-**
-** Failure to do this will cause the HW to enter a unit hang state which can
-** only be released by PCI reset on the device
-**
-*/
-static void
-em_flush_desc_rings(struct adapter *adapter)
-{
-	struct e1000_hw	*hw = &adapter->hw;
-	device_t	dev = adapter->dev;
-	u16		hang_state;
-	u32		fext_nvm11, tdlen;
- 
-	/* First, disable MULR fix in FEXTNVM11 */
-	fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
-	fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
-	E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11);
-        
-	/* do nothing if we're not in faulty state, or if the queue is empty */
-	tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
-	hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2);
-	if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
-		return;
-	em_flush_tx_ring(adapter);
-
-	/* recheck, maybe the fault is caused by the rx ring */
-	hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2);
-	if (hang_state & FLUSH_DESC_REQUIRED)
-		em_flush_rx_ring(adapter);
-}
-
-
 /*********************************************************************
  *
  *  Initialize the hardware to a configuration
@@ -3065,7 +2921,6 @@ em_reset(struct adapter *adapter)
 	case e1000_pchlan:
 	case e1000_pch2lan:
 	case e1000_pch_lpt:
-	case e1000_pch_spt:
 		pba = E1000_PBA_26K;
 		break;
 	default:
@@ -3124,7 +2979,6 @@ em_reset(struct adapter *adapter)
 		break;
 	case e1000_pch2lan:
 	case e1000_pch_lpt:
-	case e1000_pch_spt:
 		hw->fc.high_water = 0x5C20;
 		hw->fc.low_water = 0x5048;
 		hw->fc.pause_time = 0x0650;
@@ -3149,10 +3003,6 @@ em_reset(struct adapter *adapter)
 		break;
 	}
 
-	/* I219 needs some special flushing to avoid hangs */
-	if (hw->mac.type == e1000_pch_spt)
-		em_flush_desc_rings(adapter);
-
 	/* Issue a global reset */
 	e1000_reset_hw(hw);
 	E1000_WRITE_REG(hw, E1000_WUC, 0);
@@ -3749,15 +3599,6 @@ em_initialize_transmit_unit(struct adapter *adapter)
 	/* This write will effectively turn on the transmit unit. */
 	E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
 
-	if (hw->mac.type == e1000_pch_spt) {
-		u32 reg;
-		reg = E1000_READ_REG(hw, E1000_IOSFPC);
-		reg |= E1000_RCTL_RDMTS_HEX;
-		E1000_WRITE_REG(hw, E1000_IOSFPC, reg);
-		reg = E1000_READ_REG(hw, E1000_TARC(0));
-		reg |= E1000_TARC0_CB_MULTIQ_3_REQ;
-		E1000_WRITE_REG(hw, E1000_TARC(0), reg);
-	}
 }
 
 
diff --git a/sys/dev/e1000/if_em.h b/sys/dev/e1000/if_em.h
index 0aee4f4f7db1..8725de35e81d 100644
--- a/sys/dev/e1000/if_em.h
+++ b/sys/dev/e1000/if_em.h
@@ -218,9 +218,6 @@
 #define EM_TX_HUNG			0x80000000
 #define EM_TX_MAXTRIES			10
 
-#define PCICFG_DESC_RING_STATUS		0xe4
-#define FLUSH_DESC_REQUIRED		0x100
-
 /*
  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
diff --git a/sys/dev/e1000/if_igb.c b/sys/dev/e1000/if_igb.c
index beb42f1a43fc..696fec41a264 100644
--- a/sys/dev/e1000/if_igb.c
+++ b/sys/dev/e1000/if_igb.c
@@ -541,9 +541,9 @@ igb_attach(device_t dev)
 		    "Disable Energy Efficient Ethernet");
 		if (adapter->hw.phy.media_type == e1000_media_type_copper) {
 			if (adapter->hw.mac.type == e1000_i354)
-				e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
+				e1000_set_eee_i354(&adapter->hw);
 			else
-				e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
+				e1000_set_eee_i350(&adapter->hw);
 		}
 	}
 
@@ -1330,9 +1330,9 @@ igb_init_locked(struct adapter *adapter)
 	/* Set Energy Efficient Ethernet */
 	if (adapter->hw.phy.media_type == e1000_media_type_copper) {
 		if (adapter->hw.mac.type == e1000_i354)
-			e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
+			e1000_set_eee_i354(&adapter->hw);
 		else
-			e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
+			e1000_set_eee_i350(&adapter->hw);
 	}
 }