Add support for newer XLS chips/boards in the GMAC driver.

Improved processor id code in board.h, remove unnecessary macros.

Approved by:	rrs(mentor)

3 files changed, 106 insertions, 199 deletions

diff --git a/sys/mips/rmi/board.c b/sys/mips/rmi/board.c
index ae7b43fb9a9a..f3575d7c1754 100644
--- a/sys/mips/rmi/board.c
+++ b/sys/mips/rmi/board.c
@@ -100,6 +100,7 @@ xlr_board_info_setup()
 		xlr_board_info.is_xls = 1;
 		xlr_board_info.nr_cpus = 8;
 		xlr_board_info.usb = 1;
+		/* Board version 8 has NAND flash */
 		xlr_board_info.cfi =
 		    (xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII);
 		xlr_board_info.pci_irq = 0;
@@ -114,7 +115,9 @@ xlr_board_info_setup()
 		xlr_board_info.gmac_block[0].credit_config = &xls_cc_table_gmac0;
 		xlr_board_info.gmac_block[0].station_txbase = MSGRNG_STNID_GMACTX0;
 		xlr_board_info.gmac_block[0].station_rfr = MSGRNG_STNID_GMACRFR_0;
-		if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI)
+		if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI ||
+		    xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI ||
+		    xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XII)
 			xlr_board_info.gmac_block[0].mode = XLR_PORT0_RGMII;
 		else
 			xlr_board_info.gmac_block[0].mode = XLR_SGMII;
@@ -125,12 +128,12 @@ xlr_board_info_setup()
 		/* network block 1 */
 		xlr_board_info.gmac_block[1].type = XLR_GMAC;
 		xlr_board_info.gmac_block[1].enabled = 0xf;
-		if (xlr_is_xls4xx()) {
+		if (xlr_is_xls4xx_lite()) {
 			xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
 			uint32_t tmp;
 
-			/* some ports are not enabled on 4xx, figure this out
-			   from the GPIO fuse bank */
+			/* some ports are not enabled on the condor 4xx, figure this
+			   out from the GPIO fuse bank */
 			tmp = xlr_read_reg(mmio, 35);
 			if (tmp & (1<<28))
 				xlr_board_info.gmac_block[1].enabled &= ~0x8;
diff --git a/sys/mips/rmi/board.h b/sys/mips/rmi/board.h
index f47654e2a6cf..1b8cb14bdd9d 100644
--- a/sys/mips/rmi/board.h
+++ b/sys/mips/rmi/board.h
@@ -26,10 +26,16 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * RMI_BSD */
+ * RMI_BSD
+ * $FreeBSD$
+ */
 #ifndef _RMI_BOARD_H_
 #define _RMI_BOARD_H_
 
+/*
+ * Engineering boards have a major/minor number in their EEPROM to 
+ * identify their configuration
+ */
 #define RMI_XLR_BOARD_ARIZONA_I        1
 #define RMI_XLR_BOARD_ARIZONA_II       2
 #define RMI_XLR_BOARD_ARIZONA_III      3
@@ -38,95 +44,34 @@
 #define RMI_XLR_BOARD_ARIZONA_VI       6
 #define RMI_XLR_BOARD_ARIZONA_VII      7
 #define RMI_XLR_BOARD_ARIZONA_VIII     8
-
-#define RMI_CHIP_XLR308_A0 0x0c0600
-#define RMI_CHIP_XLR508_A0 0x0c0700
-#define RMI_CHIP_XLR516_A0 0x0c0800
-#define RMI_CHIP_XLR532_A0 0x0c0900
-#define RMI_CHIP_XLR716_A0 0x0c0a00
-#define RMI_CHIP_XLR732_A0 0x0c0b00
-
-#define RMI_CHIP_XLR308_A1 0x0c0601
-#define RMI_CHIP_XLR508_A1 0x0c0701
-#define RMI_CHIP_XLR516_A1 0x0c0801
-#define RMI_CHIP_XLR532_A1 0x0c0901
-#define RMI_CHIP_XLR716_A1 0x0c0a01
-#define RMI_CHIP_XLR732_A1 0x0c0b01
-
-#define RMI_CHIP_XLR308_B0 0x0c0602
-#define RMI_CHIP_XLR508_B0 0x0c0702
-#define RMI_CHIP_XLR516_B0 0x0c0802
-#define RMI_CHIP_XLR532_B0 0x0c0902
-#define RMI_CHIP_XLR716_B0 0x0c0a02
-#define RMI_CHIP_XLR732_B0 0x0c0b02
-
-#define RMI_CHIP_XLR308_B1 0x0c0603
-#define RMI_CHIP_XLR508_B1 0x0c0703
-#define RMI_CHIP_XLR516_B1 0x0c0803
-#define RMI_CHIP_XLR532_B1 0x0c0903
-#define RMI_CHIP_XLR716_B1 0x0c0a03
-#define RMI_CHIP_XLR732_B1 0x0c0b03
-
-#define RMI_CHIP_XLR308_B2 0x0c0604
-#define RMI_CHIP_XLR508_B2 0x0c0704
-#define RMI_CHIP_XLR516_B2 0x0c0804
-#define RMI_CHIP_XLR532_B2 0x0c0904
-#define RMI_CHIP_XLR716_B2 0x0c0a04
-#define RMI_CHIP_XLR732_B2 0x0c0b04
-
-#define RMI_CHIP_XLR308_C0 0x0c0705
-#define RMI_CHIP_XLR508_C0 0x0c0b05
-#define RMI_CHIP_XLR516_C0 0x0c0a05
-#define RMI_CHIP_XLR532_C0 0x0c0805
-#define RMI_CHIP_XLR716_C0 0x0c0205
-#define RMI_CHIP_XLR732_C0 0x0c0005
-
-#define RMI_CHIP_XLR308_C1 0x0c0706
-#define RMI_CHIP_XLR508_C1 0x0c0b06
-#define RMI_CHIP_XLR516_C1 0x0c0a06
-#define RMI_CHIP_XLR532_C1 0x0c0806
-#define RMI_CHIP_XLR716_C1 0x0c0206
-#define RMI_CHIP_XLR732_C1 0x0c0006
-
-#define RMI_CHIP_XLR308_C2 0x0c0707
-#define RMI_CHIP_XLR508_C2 0x0c0b07
-#define RMI_CHIP_XLR516_C2 0x0c0a07
-#define RMI_CHIP_XLR532_C2 0x0c0807
-#define RMI_CHIP_XLR716_C2 0x0c0207
-#define RMI_CHIP_XLR732_C2 0x0c0007
-
-#define RMI_CHIP_XLR308_C3 0x0c0708
-#define RMI_CHIP_XLR508_C3 0x0c0b08
-#define RMI_CHIP_XLR516_C3 0x0c0a08
-#define RMI_CHIP_XLR532_C3 0x0c0808
-#define RMI_CHIP_XLR716_C3 0x0c0208
-#define RMI_CHIP_XLR732_C3 0x0c0008
-
-#define RMI_CHIP_XLR308_C4 0x0c0709
-#define RMI_CHIP_XLR508_C4 0x0c0b09
-#define RMI_CHIP_XLR516_C4 0x0c0a09
-#define RMI_CHIP_XLR532_C4 0x0c0809
-#define RMI_CHIP_XLR716_C4 0x0c0209
-#define RMI_CHIP_XLR732_C4 0x0c0009
-
-#define RMI_CHIP_XLS608_A0 0x0c8000
-#define RMI_CHIP_XLS408_A0 0x0c8800
-#define RMI_CHIP_XLS404_A0 0x0c8c00
-#define RMI_CHIP_XLS208_A0 0x0c8e00
-#define RMI_CHIP_XLS204_A0 0x0c8f00
-
-#define RMI_CHIP_XLS608_A1 0x0c8001
-#define RMI_CHIP_XLS408_A1 0x0c8801
-#define RMI_CHIP_XLS404_A1 0x0c8c01
-#define RMI_CHIP_XLS208_A1 0x0c8e01
-#define RMI_CHIP_XLS204_A1 0x0c8f01
-
-static __inline__ unsigned int
-xlr_revision(void)
-{
-	return mips_rd_prid() & 0xff00ff;
-}
-
+#define RMI_XLR_BOARD_ARIZONA_XI      11
+#define RMI_XLR_BOARD_ARIZONA_XII     12
+
+/*
+ * RMI Chips - Values in Processor ID field
+ */
+#define	RMI_CHIP_XLR732		0x00
+#define	RMI_CHIP_XLR716		0x02
+#define	RMI_CHIP_XLR308		0x06
+#define	RMI_CHIP_XLR532		0x09
+
+#define RMI_CHIP_XLS616_B0      0x40
+#define RMI_CHIP_XLS608_B0      0x4a
+#define RMI_CHIP_XLS608         0x80  /* Internal */
+#define RMI_CHIP_XLS416_B0      0x44
+#define RMI_CHIP_XLS412_B0      0x4c
+#define RMI_CHIP_XLS408_B0      0x4e
+#define RMI_CHIP_XLS408         0x88  /* Lite "Condor" */
+#define RMI_CHIP_XLS404_B0      0x4f
+#define RMI_CHIP_XLS404         0x8c  /* Lite "Condor" */
+#define RMI_CHIP_XLS208         0x8e
+#define RMI_CHIP_XLS204         0x8f
+#define RMI_CHIP_XLS108         0xce
+#define RMI_CHIP_XLS104         0xcf
+
+/* 
+ * The XLS product line has chip versions 0x4x and 0x8x
+ */
 static __inline__ unsigned int
 xlr_is_xls(void)
 {
@@ -135,122 +80,60 @@ xlr_is_xls(void)
 	return (prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000;
 }
 
-static __inline__ int
-xlr_revision_a0(void)
-{
-	return xlr_revision() == 0x0c0000;
-}
-
-static __inline__ int
-xlr_revision_b0(void)
-{
-	return xlr_revision() == 0x0c0002;
-}
-
-static __inline__ int
-xlr_revision_b1(void)
-{
-	return xlr_revision() == 0x0c0003;
-}
-
-static __inline__ int
-xlr_board_atx_i(void)
-{
-	return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_I;
-}
-
-static __inline__ int
-xlr_board_atx_ii(void)
-{
-	return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_II;
-}
-
-static __inline__ int
-xlr_board_atx_ii_b(void)
-{
-	return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_II)
-	&& (xlr_boot1_info.board_minor_version == 1);
-}
-
-static __inline__ int
-xlr_board_atx_iii(void)
-{
-	return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_III;
-}
-
-static __inline__ int
-xlr_board_atx_iv(void)
-{
-	return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_IV)
-	&& (xlr_boot1_info.board_minor_version == 0);
-}
-static __inline__ int
-xlr_board_atx_iv_b(void)
-{
-	return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_IV)
-	&& (xlr_boot1_info.board_minor_version == 1);
-}
-static __inline__ int
-xlr_board_atx_v(void)
-{
-	return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_V;
-}
-static __inline__ int
-xlr_board_atx_vi(void)
-{
-	return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI;
-}
-
-static __inline__ int
-xlr_board_atx_iii_256(void)
-{
-	return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_III)
-	&& (xlr_boot1_info.board_minor_version == 0);
-}
-
-static __inline__ int
-xlr_board_atx_iii_512(void)
+/*
+ * The last byte of the processor id field is revision
+ */
+static __inline__ unsigned int
+xlr_revision(void)
 {
-	return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_III)
-	&& (xlr_boot1_info.board_minor_version == 1);
+	return mips_rd_prid() & 0xff;
 }
 
-static __inline__ int
-xlr_board_atx_v_512(void)
+/*
+ * The 15:8 byte of the PR Id register is the Processor ID
+ */
+static __inline__ unsigned int
+xlr_processor_id(void)
 {
-	return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_V)
-	&& (xlr_boot1_info.board_minor_version == 1);
+	return ((mips_rd_prid() & 0xff00) >> 8);
 }
 
+/*
+ * RMI Engineering boards which are PCI cards
+ * These should come up in PCI device mode (not yet)
+ */
 static __inline__ int
 xlr_board_pci(void)
 {
-	return (xlr_board_atx_iii_256() || xlr_board_atx_iii_512()
-	    || xlr_board_atx_v_512());
+	return ((xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_III) ||
+		(xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_V));
 }
+
 static __inline__ int
 xlr_is_xls2xx(void)
 {
-	uint32_t chipid = mips_rd_prid() & 0xffffff00U;
+	uint32_t chipid = xlr_processor_id();
 
-	return chipid == 0x0c8e00 || chipid == 0x0c8f00;
+	return (chipid == 0x8e || chipid == 0x8f);
 }
 
 static __inline__ int
-xlr_is_xls4xx(void)
+xlr_is_xls4xx_lite(void)
 {
-	uint32_t chipid = mips_rd_prid() & 0xffffff00U;
+	uint32_t chipid = xlr_processor_id();
 
-	return chipid == 0x0c8800 || chipid == 0x0c8c00;
+	return (chipid == 0x88 || chipid == 0x8c);
 }
 
 /* all our knowledge of chip and board that cannot be detected run-time goes here */
 enum gmac_block_types {
 	XLR_GMAC, XLR_XGMAC, XLR_SPI4
 };
+
 enum gmac_block_modes {
 	XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII
 };
+
 struct xlr_board_info {
 	int is_xls;
 	int nr_cpus;
@@ -273,7 +156,7 @@ struct xlr_board_info {
 		int baseirq;	/* first irq for this block, the rest are in
 				 * sequence */
 		int baseinst;	/* the first rge unit for this block */
-	}                gmac_block[3];
+	}  gmac_block[3];
 };
 
 extern struct xlr_board_info xlr_board_info;
diff --git a/sys/mips/rmi/dev/xlr/rge.c b/sys/mips/rmi/dev/xlr/rge.c
index 609edf908292..457877050efb 100644
--- a/sys/mips/rmi/dev/xlr/rge.c
+++ b/sys/mips/rmi/dev/xlr/rge.c
@@ -899,7 +899,6 @@ static void
 serdes_regs_init(struct driver_data *priv)
 {
 	xlr_reg_t *mmio_gpio = (xlr_reg_t *) (xlr_io_base + XLR_IO_GPIO_OFFSET);
-	int i;
 
 	/* Initialize SERDES CONTROL Registers */
 	rge_mii_write_internal(priv->serdes_mmio, 26, 0, 0x6DB0);
@@ -915,14 +914,27 @@ serdes_regs_init(struct driver_data *priv)
 	rge_mii_write_internal(priv->serdes_mmio, 26, 10, 0x0000);
 
 	/*
-	 * For loop delay and GPIO programming crud from Linux driver,
+	 * GPIO setting which affect the serdes - needs figuring out
 	 */
-	for (i = 0; i < 10000000; i++) {
-	}
-	mmio_gpio[0x20] = 0x7e6802;
-	mmio_gpio[0x10] = 0x7104;
-	for (i = 0; i < 100000000; i++) {
+	DELAY(100);
+	xlr_write_reg(mmio_gpio, 0x20, 0x7e6802);
+	xlr_write_reg(mmio_gpio, 0x10, 0x7104);
+	DELAY(100);
+	
+	/* 
+	 * This kludge is needed to setup serdes (?) clock correctly on some
+	 * XLS boards
+	 */
+	if ((xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI ||
+	    xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XII) &&
+	    xlr_boot1_info.board_minor_version == 4) {
+		/* use 125 Mhz instead of 156.25Mhz ref clock */
+		DELAY(100);
+		xlr_write_reg(mmio_gpio, 0x10, 0x7103);
+		xlr_write_reg(mmio_gpio, 0x21, 0x7103);
+		DELAY(100);
 	}
+
 	return;
 }
 
@@ -1085,7 +1097,7 @@ rmi_xlr_gmac_config_speed(struct driver_data *priv)
 	if (priv->speed == xlr_mac_speed_10) {
 		if (priv->mode != XLR_RGMII)
 			xlr_write_reg(mmio, R_INTERFACE_CONTROL, SGMII_SPEED_10);
-		xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7137);
+		xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7117);
 		xlr_write_reg(mmio, R_CORECONTROL, 0x02);
 		printf("%s: [10Mbps]\n", device_get_nameunit(sc->rge_dev));
 		sc->rge_mii.mii_media.ifm_media = IFM_ETHER | IFM_AUTO | IFM_10_T | IFM_FDX;
@@ -1094,7 +1106,7 @@ rmi_xlr_gmac_config_speed(struct driver_data *priv)
 	} else if (priv->speed == xlr_mac_speed_100) {
 		if (priv->mode != XLR_RGMII)
 			xlr_write_reg(mmio, R_INTERFACE_CONTROL, SGMII_SPEED_100);
-		xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7137);
+		xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7117);
 		xlr_write_reg(mmio, R_CORECONTROL, 0x01);
 		printf("%s: [100Mbps]\n", device_get_nameunit(sc->rge_dev));
 		sc->rge_mii.mii_media.ifm_media = IFM_ETHER | IFM_AUTO | IFM_100_TX | IFM_FDX;
@@ -1105,7 +1117,7 @@ rmi_xlr_gmac_config_speed(struct driver_data *priv)
 			if (priv->mode != XLR_RGMII)
 				xlr_write_reg(mmio, R_INTERFACE_CONTROL, SGMII_SPEED_100);
 			printf("PHY reported unknown MAC speed, defaulting to 100Mbps\n");
-			xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7137);
+			xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7117);
 			xlr_write_reg(mmio, R_CORECONTROL, 0x01);
 			sc->rge_mii.mii_media.ifm_media = IFM_ETHER | IFM_AUTO | IFM_100_TX | IFM_FDX;
 			sc->rge_mii.mii_media.ifm_cur->ifm_media = IFM_ETHER | IFM_AUTO | IFM_100_TX | IFM_FDX;
@@ -1113,7 +1125,7 @@ rmi_xlr_gmac_config_speed(struct driver_data *priv)
 		} else {
 			if (priv->mode != XLR_RGMII)
 				xlr_write_reg(mmio, R_INTERFACE_CONTROL, SGMII_SPEED_1000);
-			xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7237);
+			xlr_write_reg(mmio, R_MAC_CONFIG_2, 0x7217);
 			xlr_write_reg(mmio, R_CORECONTROL, 0x00);
 			printf("%s: [1000Mbps]\n", device_get_nameunit(sc->rge_dev));
 			sc->rge_mii.mii_media.ifm_media = IFM_ETHER | IFM_AUTO | IFM_1000_T | IFM_FDX;
@@ -1788,7 +1800,9 @@ rge_attach(device_t dev)
 		priv->instance = priv->id - xlr_board_info.gmacports;
 		priv->mmio = (xlr_reg_t *) (xlr_io_base + gmac_conf->baseaddr);
 	}
-	if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI) {
+	if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI ||
+	    (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI &&
+	     priv->instance >=4)) {
 		dbg_msg("Arizona board - offset 4 \n");
 		priv->mii_mmio = (xlr_reg_t *) (xlr_io_base + XLR_IO_GMAC_4_OFFSET);
 	} else
@@ -1812,7 +1826,9 @@ rge_attach(device_t dev)
 
 	priv->mode = gmac_conf->mode;
 	if (xlr_board_info.is_xls == 0) {
-		if (xlr_board_atx_ii() && !xlr_board_atx_ii_b())
+		/* TODO - check II and IIB boards */
+		if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_II &&
+		    xlr_boot1_info.board_minor_version != 1)
 			priv->phy_addr = priv->instance - 2;
 		else
 			priv->phy_addr = priv->instance;
@@ -1824,7 +1840,12 @@ rge_attach(device_t dev)
 			priv->phy_addr = 0;
 		} else {
 			priv->mode = XLR_SGMII;
-			priv->phy_addr = priv->instance + 16;
+			/* Board 11 has SGMII daughter cards with the XLS chips, in this case
+			   the phy number is 0-3 for both GMAC blocks */
+			if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI)
+				priv->phy_addr = priv->instance % 4 + 16;
+			else
+				priv->phy_addr = priv->instance + 16;
 		}
 	}
 
@@ -2088,8 +2109,8 @@ rge_intr(void *arg)
 	/* clear all interrupts and hope to make progress */
 	xlr_write_reg(mmio, R_INTREG, 0xffffffff);
 
-	/* on A0 and B0, xgmac interrupts are routed only to xgs_1 irq */
-	if ((xlr_revision_b0()) && (priv->type == XLR_XGMAC)) {
+	/* (not yet) on A0 and B0, xgmac interrupts are routed only to xgs_1 irq */
+	if ((xlr_revision() < 2) && (priv->type == XLR_XGMAC)) {
 		struct rge_softc *xgs0_dev = dev_mac[dev_mac_xgs0];
 		struct driver_data *xgs0_priv = &xgs0_dev->priv;
 		xlr_reg_t *xgs0_mmio = xgs0_priv->mmio;