e1000: Recover from igb(4) controller DEV_RSTHEADmain

CTRL.DEV_RST resets every port on an 82580 and newer igb device.
Hardware reports the event to each affected function through ICR.DRSTA
and requires software to reinitialize the port registers and descriptor
rings.  The driver neither enabled nor handled this cause, so a reset
initiated by another function could leave a running interface using
stale state.

In FreeBSD, we do not currently send this, but other OSes including
Linux do, so a PF passed through to such a guest or FreeBSD as a guest
running with a passthrough PF on the same controller can be wedged.

Enable DRSTA for 82580 and newer PFs in both MSI-X and shared MSI/legacy
modes.  Bit 30 is reserved on 82575 and is the TCP timer on 82576, so
leave it masked on those parts.  Latch the event without programming
port registers from the interrupt filter.  Defer the iflib reset request
to admin-task context because the request takes STATE_LOCK.  Use IAM to
auto-mask shared interrupts on the first ICR read.  Keep admin,
queue-vector, and interrupt-rearm work quiesced until initialization
succeeds.

Follow the device reset handshake before the first CTX-owned register
programming: wait for GCR to report that the device reset and pending
PCIe transactions have completed, then acknowledge STATUS.DEV_RST_SET.
Also verify EEPROM autoload and PF reset completion on I350 and newer
parts.  This follows the Intel 82580 Datasheet, section 4.3.2, and the
Intel I350 Datasheet, section 4.3.4.  Detect a completed reset from
STATUS even when the interface was down.  A bounded timeout falls back
to the requested port reset.

Retain staged reset state through the complete initialization.  Check
ICR.DRSTA, GCR, and STATUS.DEV_RST_SET after all registers and rings
have been rebuilt.  If another reset arrived while interrupts were
masked, reject the incomplete initialization and repeat the handshake.
If both MMIO and PCI configuration space have disappeared, leave the
interface stopped rather than queueing an endless recovery loop.

Validated on an I210 with INVARIANTS and WITNESS.  Injecting
CTRL.DEV_RST while igb0 was running recovered through a full iflib
initialization in both MSI-X and MSI modes without a panic.
STATUS.DEV_RST_SET and GCR.DEV_RST_IN_PROGRESS cleared, enabled DMA
coalescing was restored.  Injecting the reset while igb0 was down left
DEV_RST_SET latched; the first ifconfig up consumed it.

On a dual-port 82580, synthetic DRSTA injection produced one complete
reinitialization in four-queue MSI-X and shared-MSI modes.  Five
repeated events produced five clean reinitializations without a panic
or watchdog.  A raw CTRL.DEV_RST test is not counted because Intel's
shared code deliberately avoids that unreliable operation on 82580.

On an I350, a real device-wide reset initiated by a sibling function
produced one reinitialization while igb0 was running and restored its
carrier and enabled state.  With igb0 down, STATUS.DEV_RST_SET remained
latched until the first up, which consumed it and restored the correct
state.  The host remained healthy in both cases.

MFC after:	2 weeks
Sponsored by:	BBOX.io

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