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| author | Dimitry Andric <dim@FreeBSD.org> | 2021-06-13 19:31:46 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2021-06-13 19:37:19 +0000 |
| commit | e8d8bef961a50d4dc22501cde4fb9fb0be1b2532 (patch) | |
| tree | 94f04805f47bb7c59ae29690d8952b6074fff602 /contrib/llvm-project/llvm/lib/Target/ARM/ARM.td | |
| parent | bb130ff39747b94592cb26d71b7cb097b9a4ea6b (diff) | |
| parent | b60736ec1405bb0a8dd40989f67ef4c93da068ab (diff) | |
| download | src-e8d8bef961a50d4dc22501cde4fb9fb0be1b2532.tar.gz src-e8d8bef961a50d4dc22501cde4fb9fb0be1b2532.zip | |
Merge llvm-project main llvmorg-12-init-17869-g8e464dd76bef
This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and
openmp to llvmorg-12-init-17869-g8e464dd76bef, the last commit before the
upstream release/12.x branch was created.
PR: 255570
MFC after: 6 weeks
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/ARM/ARM.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/ARM/ARM.td | 109 |
1 files changed, 90 insertions, 19 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/ARM/ARM.td b/contrib/llvm-project/llvm/lib/Target/ARM/ARM.td index 0468f7f1cf8e..3d0a0bf7f8c3 100644 --- a/contrib/llvm-project/llvm/lib/Target/ARM/ARM.td +++ b/contrib/llvm-project/llvm/lib/Target/ARM/ARM.td @@ -535,6 +535,10 @@ def HasV8_6aOps : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true", [HasV8_5aOps, FeatureBF16, FeatureMatMulInt8]>; +def HasV8_7aOps : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true", + "Support ARM v8.7a instructions", + [HasV8_6aOps]>; + def HasV8_1MMainlineOps : SubtargetFeature< "v8.1m.main", "HasV8_1MMainlineOps", "true", "Support ARM v8-1M Mainline instructions", @@ -559,6 +563,20 @@ foreach i = {0-7} in [HasCDEOps]>; //===----------------------------------------------------------------------===// +// Control codegen mitigation against Straight Line Speculation vulnerability. +//===----------------------------------------------------------------------===// + +def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", + "HardenSlsRetBr", "true", + "Harden against straight line speculation across RETurn and BranchRegister " + "instructions">; +def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", + "HardenSlsBlr", "true", + "Harden against straight line speculation across indirect calls">; + + + +//===----------------------------------------------------------------------===// // ARM Processor subtarget features. // @@ -598,9 +616,14 @@ def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", "Cortex-A77 ARM processors", []>; def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78", "Cortex-A78 ARM processors", []>; +def ProcA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C", + "Cortex-A78C ARM processors", []>; def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", "Cortex-X1 ARM processors", []>; +def ProcV1 : SubtargetFeature<"neoverse-v1", "ARMProcFamily", + "NeoverseV1", "Neoverse-V1 ARM processors", []>; + def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", "Qualcomm Krait processors", []>; def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", @@ -639,7 +662,8 @@ def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", "Cortex-M3 ARM processors", []>; - +def ProcM7 : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7", + "Cortex-M7 ARM processors", []>; //===----------------------------------------------------------------------===// // ARM Helper classes. @@ -828,6 +852,19 @@ def ARMv86a : Architecture<"armv8.6-a", "ARMv86a", [HasV8_6aOps, FeatureCRC, FeatureRAS, FeatureDotProd]>; +def ARMv87a : Architecture<"armv8.7-a", "ARMv86a", [HasV8_7aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCrypto, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, @@ -882,6 +919,13 @@ def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; +//===----------------------------------------------------------------------===// +// Register File Description +//===----------------------------------------------------------------------===// + +include "ARMRegisterInfo.td" +include "ARMRegisterBanks.td" +include "ARMCallingConv.td" //===----------------------------------------------------------------------===// // ARM schedules. @@ -891,9 +935,27 @@ include "ARMPredicates.td" include "ARMSchedule.td" //===----------------------------------------------------------------------===// -// ARM processors +// Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "ARMInstrInfo.td" +def ARMInstrInfo : InstrInfo; + +//===----------------------------------------------------------------------===// +// ARM schedules // +include "ARMScheduleV6.td" +include "ARMScheduleA8.td" +include "ARMScheduleA9.td" +include "ARMScheduleSwift.td" +include "ARMScheduleR52.td" +include "ARMScheduleA57.td" +include "ARMScheduleM4.td" +include "ARMScheduleM7.td" +//===----------------------------------------------------------------------===// +// ARM processors +// // Dummy CPU, used to target architectures def : ProcessorModel<"generic", CortexA8Model, []>; @@ -1131,8 +1193,10 @@ def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, FeatureUseMISched, FeatureHasNoBranchPredictor]>; -def : ProcNoItin<"cortex-m7", [ARMv7em, - FeatureFPARMv8_D16]>; +def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em, + ProcM7, + FeatureFPARMv8_D16, + FeatureUseMISched]>; def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, FeatureNoMovt]>; @@ -1246,6 +1310,14 @@ def : ProcNoItin<"cortex-a78", [ARMv82a, ProcA78, FeatureFullFP16, FeatureDotProd]>; +def : ProcNoItin<"cortex-a78c", [ARMv82a, ProcA78C, + FeatureHWDivThumb, + FeatureHWDivARM, + FeatureCrypto, + FeatureCRC, + FeatureDotProd, + FeatureFullFP16]>; + def : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1, FeatureHWDivThumb, FeatureHWDivARM, @@ -1254,6 +1326,15 @@ def : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1, FeatureFullFP16, FeatureDotProd]>; +def : ProcNoItin<"neoverse-v1", [ARMv84a, + FeatureHWDivThumb, + FeatureHWDivARM, + FeatureCrypto, + FeatureCRC, + FeatureFullFP16, + FeatureBF16, + FeatureMatMulInt8]>; + def : ProcNoItin<"neoverse-n1", [ARMv82a, FeatureHWDivThumb, FeatureHWDivARM, @@ -1261,6 +1342,11 @@ def : ProcNoItin<"neoverse-n1", [ARMv82a, FeatureCRC, FeatureDotProd]>; +def : ProcNoItin<"neoverse-n2", [ARMv85a, + FeatureBF16, + FeatureMatMulInt8, + FeaturePerfMon]>; + def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, @@ -1296,21 +1382,6 @@ def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, FeatureFPAO]>; //===----------------------------------------------------------------------===// -// Register File Description -//===----------------------------------------------------------------------===// - -include "ARMRegisterInfo.td" -include "ARMRegisterBanks.td" -include "ARMCallingConv.td" - -//===----------------------------------------------------------------------===// -// Instruction Descriptions -//===----------------------------------------------------------------------===// - -include "ARMInstrInfo.td" -def ARMInstrInfo : InstrInfo; - -//===----------------------------------------------------------------------===// // Declare the target which we are implementing //===----------------------------------------------------------------------===// |