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| author | Dimitry Andric <dim@FreeBSD.org> | 2022-02-05 20:07:43 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2022-05-14 11:44:47 +0000 |
| commit | 1fd87a682ad7442327078e1eeb63edc4258f9815 (patch) | |
| tree | 83b42223e987ef7df2e1036937bc1bb627fa2779 /contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td | |
| parent | 04eeddc0aa8e0a417a16eaf9d7d095207f4a8623 (diff) | |
| parent | ecbca9f5fb7d7613d2b94982c4825eb0d33d6842 (diff) | |
| download | src-1fd87a682ad7442327078e1eeb63edc4258f9815.tar.gz src-1fd87a682ad7442327078e1eeb63edc4258f9815.zip | |
Merge llvm-project main llvmorg-14-init-18294-gdb01b123d012
This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and
openmp to llvmorg-14-init-18294-gdb01b123d012, the last commit before
the upstream release/14.x branch was created.
PR: 261742
MFC after: 2 weeks
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 964f0fa54512..e71c498fd5f4 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -228,6 +228,7 @@ def SDT_RISCVVWBinOp_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisVT<4, XLenVT>]>; def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; +def riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWBinOp_VL>; def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; def SDTRVVVecReduce : SDTypeProfile<1, 5, [ @@ -832,7 +833,7 @@ foreach vti = AllIntegerVectors in { defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT, - SplatPat_simm5_plus1>; + SplatPat_simm5_plus1_nonzero>; defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT, SplatPat_simm5_plus1_nonzero>; defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGT", SETGE, @@ -861,6 +862,7 @@ defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; // 12.12. Vector Widening Integer Multiply Instructions defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; +defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">; // 12.13 Vector Single-Width Integer Multiply-Add Instructions foreach vti = AllIntegerVectors in { |