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| author | Dimitry Andric <dim@FreeBSD.org> | 2023-11-16 21:58:12 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2023-12-08 17:35:50 +0000 |
| commit | b121cb0095c8c1a060f66a8c4b118a54ebaa2551 (patch) | |
| tree | b29c02b9abbfc698522a09ad77b56a3440f5e215 /contrib/llvm-project/llvm/lib/Target/RISCV | |
| parent | bdb86d1a853a919764f65fdedcea76d76e4d619b (diff) | |
| parent | fc0a8108a55ae5db3aa0e71a9877bd56f0581728 (diff) | |
| download | src-b121cb0095c8c1a060f66a8c4b118a54ebaa2551.tar.gz src-b121cb0095c8c1a060f66a8c4b118a54ebaa2551.zip | |
Merge llvm-project release/17.x llvmorg-17.0.5-0-g98bfdac5ce82
This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and
openmp to llvmorg-17.0.5-0-g98bfdac5ce82.
PR: 273753
MFC after: 1 month
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/RISCV')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index e0cbca6dc1c2..c1065f73000f 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -299,11 +299,6 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MCRegister SrcReg, bool KillSrc) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - if (RISCV::GPRPF64RegClass.contains(DstReg)) - DstReg = TRI->getSubReg(DstReg, RISCV::sub_32); - if (RISCV::GPRPF64RegClass.contains(SrcReg)) - SrcReg = TRI->getSubReg(SrcReg, RISCV::sub_32); - if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) { BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) .addReg(SrcReg, getKillRegState(KillSrc)) @@ -311,6 +306,20 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, return; } + if (RISCV::GPRPF64RegClass.contains(DstReg, SrcReg)) { + // Emit an ADDI for both parts of GPRPF64. + BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), + TRI->getSubReg(DstReg, RISCV::sub_32)) + .addReg(TRI->getSubReg(SrcReg, RISCV::sub_32), getKillRegState(KillSrc)) + .addImm(0); + BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), + TRI->getSubReg(DstReg, RISCV::sub_32_hi)) + .addReg(TRI->getSubReg(SrcReg, RISCV::sub_32_hi), + getKillRegState(KillSrc)) + .addImm(0); + return; + } + // Handle copy from csr if (RISCV::VCSRRegClass.contains(SrcReg) && RISCV::GPRRegClass.contains(DstReg)) { |