Add support for RDMA from userspace with T6 cards.

Submitted by:	Krishnamraju Eraparaju @ Chelsio
Sponsored by:	Chelsio Communications

7 files changed, 20653 insertions, 64 deletions

diff --git a/contrib/ofed/libcxgb4/src/dev.c b/contrib/ofed/libcxgb4/src/dev.c
index 33c10de237e5..2d8471901945 100644
--- a/contrib/ofed/libcxgb4/src/dev.c
+++ b/contrib/ofed/libcxgb4/src/dev.c
@@ -145,10 +145,10 @@ static struct ibv_context *c4iw_alloc_context(struct ibv_device *ibdev,
 	context->ibv_ctx.ops = c4iw_ctx_ops;
 
 	switch (rhp->chip_version) {
+	case CHELSIO_T6:
 	case CHELSIO_T5:
-		PDBG("%s T5/T4 device\n", __FUNCTION__);
 	case CHELSIO_T4:
-		PDBG("%s T4 device\n", __FUNCTION__);
+		PDBG("%s T%d device\n", __FUNCTION__, rhp->chip_version);
 		context->ibv_ctx.ops.async_event = c4iw_async_event;
 		context->ibv_ctx.ops.post_send = c4iw_post_send;
 		context->ibv_ctx.ops.post_recv = c4iw_post_receive;
@@ -390,29 +390,26 @@ static struct ibv_device *cxgb4_driver_init(const char *uverbs_sys_path,
 					    int abi_version)
 {
 	char devstr[IBV_SYSFS_PATH_MAX], ibdev[16], value[128], *cp;
-	char t5nexstr[IBV_SYSFS_PATH_MAX];
+	char dev_str[IBV_SYSFS_PATH_MAX];
 	struct c4iw_dev *dev;
 	unsigned vendor, device, fw_maj, fw_min;
 	int i;
-	char devnum=0;
+	char devnum;
         char ib_param[16];
 
 #ifndef __linux__
 	if (ibv_read_sysfs_file(uverbs_sys_path, "ibdev",
 				ibdev, sizeof ibdev) < 0)
 		return NULL;
-	/* 
-	 * Extract the non-numeric part of ibdev
-	 * say "t5nex0" -> devname=="t5nex", devnum=0
-	 */
-	if (strstr(ibdev,"t5nex")) {
-		devnum = atoi(ibdev+strlen("t5nex"));
-		sprintf(t5nexstr, "/dev/t5nex/%d", devnum);
+
+	if (ibdev[0] == 't' && ibdev[1] >= '4' && ibdev[1] <= '6' &&
+	    strstr(&ibdev[2], "nex") && (devnum = atoi(&ibdev[5])) >= 0) {
+		snprintf(dev_str, sizeof(dev_str), "/dev/t%cnex/%d", ibdev[1],
+		    devnum);
 	} else
 		return NULL;
 
-	if (ibv_read_sysfs_file(t5nexstr, "\%pnpinfo",
-				value, sizeof value) < 0)
+	if (ibv_read_sysfs_file(dev_str, "\%pnpinfo", value, sizeof value) < 0)
 		return NULL;
 	else {
 		if (strstr(value,"vendor=")) {
@@ -449,7 +446,7 @@ found:
 
 
 #ifndef __linux__
-	if (ibv_read_sysfs_file(t5nexstr, "firmware_version",
+	if (ibv_read_sysfs_file(dev_str, "firmware_version",
 				value, sizeof value) < 0)
 		return NULL;
 #else
diff --git a/contrib/ofed/libcxgb4/src/qp.c b/contrib/ofed/libcxgb4/src/qp.c
index b0e3def5006c..7f36637c6aea 100644
--- a/contrib/ofed/libcxgb4/src/qp.c
+++ b/contrib/ofed/libcxgb4/src/qp.c
@@ -393,7 +393,7 @@ int c4iw_post_send(struct ibv_qp *ibqp, struct ibv_send_wr *wr,
 		idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 	}
 
-	t4_ring_sq_db(&qhp->wq, idx, dev_is_t5(qhp->rhp),
+	t4_ring_sq_db(&qhp->wq, idx, dev_is_t4(qhp->rhp),
 			len16, wqe);
 	qhp->wq.sq.queue[qhp->wq.sq.size].status.host_wq_pidx = \
 			(qhp->wq.sq.wq_pidx);
@@ -457,7 +457,7 @@ int c4iw_post_receive(struct ibv_qp *ibqp, struct ibv_recv_wr *wr,
 		num_wrs--;
 	}
 
-	t4_ring_rq_db(&qhp->wq, idx, dev_is_t5(qhp->rhp),
+	t4_ring_rq_db(&qhp->wq, idx, dev_is_t4(qhp->rhp),
 			len16, wqe);
 	qhp->wq.rq.queue[qhp->wq.rq.size].status.host_wq_pidx = \
 			(qhp->wq.rq.wq_pidx);
diff --git a/contrib/ofed/libcxgb4/src/t4.h b/contrib/ofed/libcxgb4/src/t4.h
index c5120a6a61b3..d93e9b68126c 100644
--- a/contrib/ofed/libcxgb4/src/t4.h
+++ b/contrib/ofed/libcxgb4/src/t4.h
@@ -484,11 +484,11 @@ static void copy_wqe_to_udb(volatile u32 *udb_offset, void *wqe)
 extern int ma_wr;
 extern int t5_en_wc;
 
-static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
+static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t4, u8 len16,
 				 union t4_wr *wqe)
 {
 	wc_wmb();
-	if (t5) {
+	if (!t4) {
 		if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {
 			PDBG("%s: WC wq->sq.pidx = %d; len16=%d\n",
 			     __func__, wq->sq.pidx, len16);
@@ -517,11 +517,11 @@ static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
 	writel(V_QID(wq->sq.qid & wq->qid_mask) | V_PIDX(inc), wq->sq.udb);
 }
 
-static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
+static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t4, u8 len16,
 				 union t4_recv_wr *wqe)
 {
 	wc_wmb();
-	if (t5) {
+	if (!t4) {
 		if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {
 			PDBG("%s: WC wq->rq.pidx = %d; len16=%d\n",
 			     __func__, wq->rq.pidx, len16);
diff --git a/contrib/ofed/libcxgb4/src/t4_chip_type.h b/contrib/ofed/libcxgb4/src/t4_chip_type.h
index b4f164c2ce9f..59c4a240fcd7 100644
--- a/contrib/ofed/libcxgb4/src/t4_chip_type.h
+++ b/contrib/ofed/libcxgb4/src/t4_chip_type.h
@@ -1,7 +1,7 @@
 /*
- * This file is part of the Chelsio T4 Ethernet driver.
+ * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
  *
- * Copyright (C) 2003-2014 Chelsio Communications.  All rights reserved.
+ * Copyright (C) 2003-2016 Chelsio Communications.  All rights reserved.
  *
  * This program is distributed in the hope that it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@@ -30,6 +30,8 @@
 #define CHELSIO_T4_FPGA		0xa
 #define CHELSIO_T5		0x5
 #define CHELSIO_T5_FPGA		0xb
+#define CHELSIO_T6		0x6
+#define CHELSIO_T6_FPGA		0xc
 
 /*
  * Translate a PCI Device ID to a base Chelsio Chip Version -- CHELSIO_T4,
@@ -43,11 +45,25 @@
  * Finally: This will of course need to be expanded as future chips are
  * developed.
  */
-#define CHELSIO_PCI_ID_CHIP_VERSION(__DeviceID) \
-	(CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4 || \
-	 CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4_FPGA \
-	 ? CHELSIO_T4 \
-	 : CHELSIO_T5)
+static inline unsigned int
+CHELSIO_PCI_ID_CHIP_VERSION(unsigned int DeviceID)
+{
+	switch (CHELSIO_PCI_ID_VER(DeviceID)) {
+	case CHELSIO_T4:
+	case CHELSIO_T4_FPGA:
+	return CHELSIO_T4;
+
+	case CHELSIO_T5:
+	case CHELSIO_T5_FPGA:
+	return CHELSIO_T5;
+
+	case CHELSIO_T6:
+	case CHELSIO_T6_FPGA:
+	return CHELSIO_T6;
+	}
+
+	return 0;
+}
 
 /*
  * Internally we code the Chelsio T4 Family "Chip Code" as a tuple:
@@ -72,9 +88,13 @@ enum chip_type {
 	T4_LAST_REV	= T4_A2,
 
 	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
-	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
+	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
 	T5_FIRST_REV	= T5_A0,
 	T5_LAST_REV	= T5_A1,
+
+	T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
+	T6_FIRST_REV	= T6_A0,
+	T6_LAST_REV	= T6_A0,
 };
 
 static inline int is_t4(enum chip_type chip)
@@ -88,6 +108,11 @@ static inline int is_t5(enum chip_type chip)
 	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
 }
 
+static inline int is_t6(enum chip_type chip)
+{
+	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
+}
+
 static inline int is_fpga(enum chip_type chip)
 {
 	 return chip & CHELSIO_CHIP_FPGA;
diff --git a/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h b/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h
index fbc2fd49dc98..9a7c91ba9d79 100644
--- a/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h
+++ b/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h
@@ -1,7 +1,7 @@
 /*
- * This file is part of the Chelsio T4 Ethernet driver.
+ * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
  *
- * Copyright (C) 2003-2014 Chelsio Communications.  All rights reserved.
+ * Copyright (C) 2003-2017 Chelsio Communications.  All rights reserved.
  *
  * This program is distributed in the hope that it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@@ -44,7 +44,6 @@
  *   -- If defined, indicates that the OS Driver has support for Bypass
  *   -- Adapters.
  */
-#ifdef CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
 
 /*
  * Some sanity checks ...
@@ -96,10 +95,13 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
 	CH_PCI_ID_TABLE_ENTRY(0xa000),	/* PE10K FPGA */
 	CH_PCI_ID_TABLE_ENTRY(0xb000),	/* PF0 T5 PE10K5 FPGA */
 	CH_PCI_ID_TABLE_ENTRY(0xb001),	/* PF0 T5 PE10K FPGA */
+	CH_PCI_ID_TABLE_ENTRY(0xc006),  /* PF0 T6 PE10K6 FPGA */
 #else
 	CH_PCI_ID_TABLE_FENTRY(0xa000),	/* PE10K FPGA */
 	CH_PCI_ID_TABLE_FENTRY(0xb000),	/* PF0 T5 PE10K5 FPGA */
 	CH_PCI_ID_TABLE_FENTRY(0xb001),	/* PF0 T5 PE10K FPGA */
+	CH_PCI_ID_TABLE_FENTRY(0xc006), /* PF0 T6 PE10K6 FPGA */
+	CH_PCI_ID_TABLE_FENTRY(0xc106),  /* PF1 T6 PE10K6 FPGA */
 #endif
 
 	/*
@@ -108,6 +110,7 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
 #if ((CH_PCI_DEVICE_ID_FUNCTION == 5) || (CH_PCI_DEVICE_ID_FUNCTION == 6))
 	CH_PCI_ID_TABLE_ENTRY(0xa001),	/* PF1 PE10K FPGA FCOE */
 	CH_PCI_ID_TABLE_ENTRY(0xa002),	/* PE10K FPGA iSCSI */
+	CH_PCI_ID_TABLE_ENTRY(0xc106),  /* PF1 T6 PE10K6 FPGA */
 #endif
 
 	/*
@@ -166,10 +169,50 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
 	CH_PCI_ID_TABLE_FENTRY(0x5013),	/* T580-chr */
 	CH_PCI_ID_TABLE_FENTRY(0x5014),	/* T580-so */
 	CH_PCI_ID_TABLE_FENTRY(0x5015),	/* T502-bt */
+	CH_PCI_ID_TABLE_FENTRY(0x5016),	/* T580-OCP-SO */
+	CH_PCI_ID_TABLE_FENTRY(0x5017),	/* T520-OCP-SO */
+	CH_PCI_ID_TABLE_FENTRY(0x5018),	/* T540-BT */
 	CH_PCI_ID_TABLE_FENTRY(0x5080),	/* Custom T540-cr */
 	CH_PCI_ID_TABLE_FENTRY(0x5081),	/* Custom T540-LL-cr */
-CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
+	CH_PCI_ID_TABLE_FENTRY(0x5082),	/* Custom T504-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5083),	/* Custom T540-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5084),	/* Custom T580-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5085),	/* Custom 3x T580-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5086),	/* Custom 2x T580-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5087),	/* Custom T580-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5088),	/* Custom T570-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5089),	/* Custom T520-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5090),	/* Custom T540-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5091),	/* Custom T522-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5092),	/* Custom T520-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5093),	/* Custom SECA */
+	CH_PCI_ID_TABLE_FENTRY(0x5094),	/* Custom T540-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5095),	/* Custom T540-CR-SO */
+	CH_PCI_ID_TABLE_FENTRY(0x5096), /* Custom T580-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x5097), /* Custom T520-KR */
+	CH_PCI_ID_TABLE_FENTRY(0x5098), /* Custom 2x40G QSFP */
+	CH_PCI_ID_TABLE_FENTRY(0x5099), /* Custom 2x40G QSFP */
+	CH_PCI_ID_TABLE_FENTRY(0x509A), /* Custom T520-CR */
+	CH_PCI_ID_TABLE_FENTRY(0x509B), /* Custom T540-CR LOM */
+	CH_PCI_ID_TABLE_FENTRY(0x509c), /* Custom T520-CR SFP+ LOM */
+	CH_PCI_ID_TABLE_FENTRY(0x509d), /* Custom T540-CR SFP+ */
 
-#endif /* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN */
+	/* T6 adapter */
+	CH_PCI_ID_TABLE_FENTRY(0x6000),
+	CH_PCI_ID_TABLE_FENTRY(0x6001),
+	CH_PCI_ID_TABLE_FENTRY(0x6002),
+	CH_PCI_ID_TABLE_FENTRY(0x6003),
+	CH_PCI_ID_TABLE_FENTRY(0x6004),
+	CH_PCI_ID_TABLE_FENTRY(0x6005),
+	CH_PCI_ID_TABLE_FENTRY(0x6006),
+	CH_PCI_ID_TABLE_FENTRY(0x6007),
+	CH_PCI_ID_TABLE_FENTRY(0x6008),
+	CH_PCI_ID_TABLE_FENTRY(0x6009),
+	CH_PCI_ID_TABLE_FENTRY(0x600d),
+	CH_PCI_ID_TABLE_FENTRY(0x6010),
+	CH_PCI_ID_TABLE_FENTRY(0x6011),
+	CH_PCI_ID_TABLE_FENTRY(0x6014),
+	CH_PCI_ID_TABLE_FENTRY(0x6015),
+CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
 
 #endif /* __T4_PCI_ID_TBL_H__ */
diff --git a/contrib/ofed/libcxgb4/src/t4_regs.h b/contrib/ofed/libcxgb4/src/t4_regs.h
index 266f773edb9c..d001d8ca9b8b 100644
--- a/contrib/ofed/libcxgb4/src/t4_regs.h
+++ b/contrib/ofed/libcxgb4/src/t4_regs.h
@@ -1,4 +1,8 @@
 /* This file is automatically generated --- changes will be lost */
+/* Generation Date : Fri Oct 28 19:22:40 IST 2016 */
+/* Directory name: t4_reg.txt, Changeset:  */
+/* Directory name: t5_reg.txt, Changeset: 6938:9111c5bdce6e */
+/* Directory name: t6_reg.txt, Changeset: 4252:437fb8972e44 */
 
 #define MYPF_BASE 0x1b000
 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
@@ -339,9 +343,141 @@
 #define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
 #define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
 
+#define SGE_DEBUG1_DBP_THREAD(idx) (A_SGE_DEBUG1_DBP_THREAD + (idx) * 4)
+#define NUM_SGE_DEBUG1_DBP_THREAD_INSTANCES 4
+
+#define SGE_DEBUG0_DBP_THREAD(idx) (A_SGE_DEBUG0_DBP_THREAD + (idx) * 4)
+#define NUM_SGE_DEBUG0_DBP_THREAD_INSTANCES 5
+
+#define SGE_WC_EGRS_BAR2_OFF_PF(idx) (A_SGE_WC_EGRS_BAR2_OFF_PF + (idx) * 4)
+#define NUM_SGE_WC_EGRS_BAR2_OFF_PF_INSTANCES 8
+
+#define SGE_WC_EGRS_BAR2_OFF_VF(idx) (A_SGE_WC_EGRS_BAR2_OFF_VF + (idx) * 4)
+#define NUM_SGE_WC_EGRS_BAR2_OFF_VF_INSTANCES 8
+
+#define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T6_DMA_INSTANCES 2
+
+#define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T6_CMD_INSTANCES 1
+
+#define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_PCIE_VF_256_INT_INSTANCES 128
+
+#define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_L_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_H_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_L_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_H_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_PORT_VLAN_INSTANCES 8
+
+#define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32)
+#define NUM_MPS_CLS_REQUEST_TRACE_ENCAP_INSTANCES 8
+
+#define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4)
+#define NUM_MPS_CLS_RESULT_TRACE_INSTANCES 8
+
+#define MPS_CLS_DIPIPV4_ID_TABLE(idx) (A_MPS_CLS_DIPIPV4_ID_TABLE + (idx) * 8)
+#define NUM_MPS_CLS_DIPIPV4_ID_TABLE_INSTANCES 4
+
+#define MPS_CLS_DIPIPV4_MASK_TABLE(idx) (A_MPS_CLS_DIPIPV4_MASK_TABLE + (idx) * 8)
+#define NUM_MPS_CLS_DIPIPV4_MASK_TABLE_INSTANCES 4
+
+#define MPS_CLS_DIPIPV6ID_0_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_0_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6ID_0_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6ID_1_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_1_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6ID_1_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6ID_2_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_2_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6ID_2_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6ID_3_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_3_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6ID_3_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6MASK_0_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_0_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6MASK_0_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6MASK_1_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_1_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6MASK_1_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6MASK_2_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_2_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6MASK_2_TABLE_INSTANCES 2
+
+#define MPS_CLS_DIPIPV6MASK_3_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_3_TABLE + (idx) * 32)
+#define NUM_MPS_CLS_DIPIPV6MASK_3_TABLE_INSTANCES 2
+
+#define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4)
+#define NUM_MPS_RX_HASH_LKP_TABLE_INSTANCES 4
+
+#define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4)
+#define NUM_LE_DB_DBG_MATCH_DATA_MASK_INSTANCES 8
+
+#define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4)
+#define NUM_LE_DB_DBG_MATCH_DATA_INSTANCES 8
+
+#define LE_DB_DBGI_REQ_DATA_T6(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
+#define NUM_LE_DB_DBGI_REQ_DATA_T6_INSTANCES 11
+
+#define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
+#define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11
+
+#define LE_DB_DBGI_RSP_DATA_T6(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
+#define NUM_LE_DB_DBGI_RSP_DATA_T6_INSTANCES 11
+
+#define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
+#define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8
+
+#define LE_HASH_MASK_GEN_IPV4T6(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_GEN_IPV4T6_INSTANCES 8
+
+#define T6_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T6_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
+#define NUM_T6_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8
+
+#define LE_DB_PSV_FILTER_MASK_TUP_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 + (idx) * 4)
+#define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV4_INSTANCES 3
+
+#define LE_DB_PSV_FILTER_MASK_FLT_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 + (idx) * 4)
+#define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV4_INSTANCES 2
+
+#define LE_DB_PSV_FILTER_MASK_TUP_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 + (idx) * 4)
+#define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV6_INSTANCES 9
+
+#define LE_DB_PSV_FILTER_MASK_FLT_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 + (idx) * 4)
+#define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV6_INSTANCES 2
+
+#define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6_INSTANCES 8
+
+#define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
+#define NUM_MC_DDRPHY_DP18_T6_INSTANCES 9
+
+#define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_CE_ERR_DATA_T6_INSTANCES 16
+
+#define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_UE_ERR_DATA_T6_INSTANCES 16
+
+#define CIM_CTL_MAILBOX_VF_STATUS_T6(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
+#define NUM_CIM_CTL_MAILBOX_VF_STATUS_T6_INSTANCES 8
+
+#define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
+#define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256
+
 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
 
+#define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
+#define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
+
 /* registers for module SGE */
 #define SGE_BASE_ADDR 0x1000
 
@@ -372,6 +508,10 @@
 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
 
+#define S_SYNC_T6    14
+#define V_SYNC_T6(x) ((x) << S_SYNC_T6)
+#define F_SYNC_T6    V_SYNC_T6(1U)
+
 #define A_SGE_PF_GTS 0x4
 
 #define S_INGRESSQID    16
@@ -764,6 +904,14 @@
 #define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
 #define F_PERR_PC_CHPI_RSP2    V_PERR_PC_CHPI_RSP2(1U)
 
+#define S_PERR_PC_RSP    23
+#define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP)
+#define F_PERR_PC_RSP    V_PERR_PC_RSP(1U)
+
+#define S_PERR_PC_REQ    22
+#define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
+#define F_PERR_PC_REQ    V_PERR_PC_REQ(1U)
+
 #define A_SGE_INT_ENABLE1 0x1028
 #define A_SGE_PERR_ENABLE1 0x102c
 #define A_SGE_INT_CAUSE2 0x1030
@@ -908,6 +1056,26 @@
 #define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
 #define F_PERR_PC_DBP2    V_PERR_PC_DBP2(1U)
 
+#define S_DEQ_LL_PERR    21
+#define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR)
+#define F_DEQ_LL_PERR    V_DEQ_LL_PERR(1U)
+
+#define S_ENQ_PERR    20
+#define V_ENQ_PERR(x) ((x) << S_ENQ_PERR)
+#define F_ENQ_PERR    V_ENQ_PERR(1U)
+
+#define S_DEQ_OUT_PERR    19
+#define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR)
+#define F_DEQ_OUT_PERR    V_DEQ_OUT_PERR(1U)
+
+#define S_BUF_PERR    18
+#define V_BUF_PERR(x) ((x) << S_BUF_PERR)
+#define F_BUF_PERR    V_BUF_PERR(1U)
+
+#define S_PERR_DB_FIFO    3
+#define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
+#define F_PERR_DB_FIFO    V_PERR_DB_FIFO(1U)
+
 #define A_SGE_INT_ENABLE2 0x1034
 #define A_SGE_PERR_ENABLE2 0x1038
 #define A_SGE_INT_CAUSE3 0x103c
@@ -1040,6 +1208,14 @@
 #define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
 #define F_ERR_INV_CTXT0    V_ERR_INV_CTXT0(1U)
 
+#define S_DBP_TBUF_FULL    8
+#define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL)
+#define F_DBP_TBUF_FULL    V_DBP_TBUF_FULL(1U)
+
+#define S_FATAL_WRE_LEN    7
+#define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN)
+#define F_FATAL_WRE_LEN    V_FATAL_WRE_LEN(1U)
+
 #define A_SGE_INT_ENABLE3 0x1040
 #define A_SGE_FL_BUFFER_SIZE0 0x1044
 
@@ -1048,21 +1224,116 @@
 #define V_SIZE(x) ((x) << S_SIZE)
 #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
 
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE1 0x1048
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE2 0x104c
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE3 0x1050
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE4 0x1054
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE5 0x1058
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE6 0x105c
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE7 0x1060
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE8 0x1064
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE9 0x1068
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE10 0x106c
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE11 0x1070
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE12 0x1074
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE13 0x1078
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE14 0x107c
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_FL_BUFFER_SIZE15 0x1080
+
+#define S_T6_SIZE    4
+#define M_T6_SIZE    0xfffffU
+#define V_T6_SIZE(x) ((x) << S_T6_SIZE)
+#define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
+
 #define A_SGE_DBQ_CTXT_BADDR 0x1084
 
 #define S_BASEADDR    3
@@ -1117,6 +1388,15 @@
 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
 
+#define S_NULLPTR    20
+#define M_NULLPTR    0xfU
+#define V_NULLPTR(x) ((x) << S_NULLPTR)
+#define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR)
+
+#define S_NULLPTREN    19
+#define V_NULLPTREN(x) ((x) << S_NULLPTREN)
+#define F_NULLPTREN    V_NULLPTREN(1U)
+
 #define A_SGE_CONM_CTRL 0x1094
 
 #define S_EGRTHRESHOLD    8
@@ -1142,6 +1422,16 @@
 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
 
+#define S_T6_EGRTHRESHOLDPACKING    16
+#define M_T6_EGRTHRESHOLDPACKING    0xffU
+#define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING)
+#define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING)
+
+#define S_T6_EGRTHRESHOLD    8
+#define M_T6_EGRTHRESHOLD    0xffU
+#define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD)
+#define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD)
+
 #define A_SGE_TIMESTAMP_LO 0x1098
 #define A_SGE_TIMESTAMP_HI 0x109c
 
@@ -1217,6 +1507,21 @@
 #define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
 
+#define S_VFIFO_CNT    15
+#define M_VFIFO_CNT    0x1ffffU
+#define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT)
+#define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT)
+
+#define S_COAL_CTL_FIFO_CNT    8
+#define M_COAL_CTL_FIFO_CNT    0x3fU
+#define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT)
+#define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT)
+
+#define S_MERGE_FIFO_CNT    0
+#define M_MERGE_FIFO_CNT    0x3fU
+#define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT)
+#define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT)
+
 #define A_SGE_DOORBELL_CONTROL 0x10a8
 
 #define S_HINTDEPTHCTL    27
@@ -1286,6 +1591,32 @@
 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
 #define F_DROPPED_DB    V_DROPPED_DB(1U)
 
+#define S_T6_DROP_TIMEOUT    7
+#define M_T6_DROP_TIMEOUT    0x3fU
+#define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT)
+#define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT)
+
+#define S_INVONDBSYNC    6
+#define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC)
+#define F_INVONDBSYNC    V_INVONDBSYNC(1U)
+
+#define S_INVONGTSSYNC    5
+#define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC)
+#define F_INVONGTSSYNC    V_INVONGTSSYNC(1U)
+
+#define S_DB_DBG_EN    4
+#define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN)
+#define F_DB_DBG_EN    V_DB_DBG_EN(1U)
+
+#define S_GTS_DBG_TIMER_REG    1
+#define M_GTS_DBG_TIMER_REG    0x7U
+#define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG)
+#define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG)
+
+#define S_GTS_DBG_EN    0
+#define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN)
+#define F_GTS_DBG_EN    V_GTS_DBG_EN(1U)
+
 #define A_SGE_DROPPED_DOORBELL 0x10ac
 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
 
@@ -1331,6 +1662,11 @@
 #define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
 #define F_LL_READ_WAIT_DISABLE    V_LL_READ_WAIT_DISABLE(1U)
 
+#define S_TSCALE    28
+#define M_TSCALE    0xfU
+#define V_TSCALE(x) ((x) << S_TSCALE)
+#define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE)
+
 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
 
 #define S_TIMERVALUE0    16
@@ -1397,6 +1733,39 @@
 #define V_MAXRSPCNT1(x) ((x) << S_MAXRSPCNT1)
 #define G_MAXRSPCNT1(x) (((x) >> S_MAXRSPCNT1) & M_MAXRSPCNT1)
 
+#define A_SGE_GK_CONTROL 0x10c4
+
+#define S_EN_FLM_FIFTH    29
+#define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH)
+#define F_EN_FLM_FIFTH    V_EN_FLM_FIFTH(1U)
+
+#define S_FL_PROG_THRESH    20
+#define M_FL_PROG_THRESH    0x1ffU
+#define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH)
+#define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH)
+
+#define S_COAL_ALL_THREAD    19
+#define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD)
+#define F_COAL_ALL_THREAD    V_COAL_ALL_THREAD(1U)
+
+#define S_EN_PSHB    18
+#define V_EN_PSHB(x) ((x) << S_EN_PSHB)
+#define F_EN_PSHB    V_EN_PSHB(1U)
+
+#define S_EN_DB_FIFTH    17
+#define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH)
+#define F_EN_DB_FIFTH    V_EN_DB_FIFTH(1U)
+
+#define S_DB_PROG_THRESH    8
+#define M_DB_PROG_THRESH    0x1ffU
+#define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH)
+#define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH)
+
+#define S_100NS_TIMER    0
+#define M_100NS_TIMER    0xffU
+#define V_100NS_TIMER(x) ((x) << S_100NS_TIMER)
+#define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER)
+
 #define A_SGE_PD_RSP_CREDIT23 0x10c8
 
 #define S_RSPCREDITEN2    31
@@ -1427,6 +1796,23 @@
 #define V_MAXRSPCNT3(x) ((x) << S_MAXRSPCNT3)
 #define G_MAXRSPCNT3(x) (((x) >> S_MAXRSPCNT3) & M_MAXRSPCNT3)
 
+#define A_SGE_GK_CONTROL2 0x10c8
+
+#define S_DBQ_TIMER_TICK    16
+#define M_DBQ_TIMER_TICK    0xffffU
+#define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK)
+#define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK)
+
+#define S_FL_MERGE_CNT_THRESH    8
+#define M_FL_MERGE_CNT_THRESH    0xfU
+#define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH)
+#define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH)
+
+#define S_MERGE_CNT_THRESH    0
+#define M_MERGE_CNT_THRESH    0x3fU
+#define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH)
+#define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH)
+
 #define A_SGE_DEBUG_INDEX 0x10cc
 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
 #define A_SGE_DEBUG_DATA_LOW 0x10d4
@@ -1553,6 +1939,30 @@
 #define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
 #define F_ERR_RX_CPL_PACKET_SIZE0    V_ERR_RX_CPL_PACKET_SIZE0(1U)
 
+#define S_ERR_ISHIFT_UR1    31
+#define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1)
+#define F_ERR_ISHIFT_UR1    V_ERR_ISHIFT_UR1(1U)
+
+#define S_ERR_ISHIFT_UR0    30
+#define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0)
+#define F_ERR_ISHIFT_UR0    V_ERR_ISHIFT_UR0(1U)
+
+#define S_ERR_TH3_MAX_FETCH    14
+#define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH)
+#define F_ERR_TH3_MAX_FETCH    V_ERR_TH3_MAX_FETCH(1U)
+
+#define S_ERR_TH2_MAX_FETCH    13
+#define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH)
+#define F_ERR_TH2_MAX_FETCH    V_ERR_TH2_MAX_FETCH(1U)
+
+#define S_ERR_TH1_MAX_FETCH    12
+#define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH)
+#define F_ERR_TH1_MAX_FETCH    V_ERR_TH1_MAX_FETCH(1U)
+
+#define S_ERR_TH0_MAX_FETCH    11
+#define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH)
+#define F_ERR_TH0_MAX_FETCH    V_ERR_TH0_MAX_FETCH(1U)
+
 #define A_SGE_INT_ENABLE4 0x10e0
 #define A_SGE_STAT_TOTAL 0x10e4
 #define A_SGE_STAT_MATCH 0x10e8
@@ -1587,6 +1997,11 @@
 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
 
+#define S_T6_STATMODE    0
+#define M_T6_STATMODE    0xfU
+#define V_T6_STATMODE(x) ((x) << S_T6_STATMODE)
+#define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE)
+
 #define A_SGE_HINT_CFG 0x10f0
 
 #define S_HINTSALLOWEDNOHDR    6
@@ -1660,6 +2075,7 @@
 #define V_MINTAG0(x) ((x) << S_MINTAG0)
 #define G_MINTAG0(x) (((x) >> S_MINTAG0) & M_MINTAG0)
 
+#define A_SGE_IDMA0_DROP_CNT 0x1104
 #define A_SGE_SHARED_TAG_POOL_CFG 0x1108
 
 #define S_TAGPOOLTOTAL    0
@@ -1667,6 +2083,7 @@
 #define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
 #define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
 
+#define A_SGE_IDMA1_DROP_CNT 0x1108
 #define A_SGE_INT_CAUSE5 0x110c
 
 #define S_ERR_T_RXCRC    31
@@ -1963,6 +2380,90 @@
 #define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ)
 #define F_EDMA0_SLEEP_REQ    V_EDMA0_SLEEP_REQ(1U)
 
+#define A_SGE_INT_CAUSE6 0x1128
+
+#define S_ERR_DB_SYNC    21
+#define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC)
+#define F_ERR_DB_SYNC    V_ERR_DB_SYNC(1U)
+
+#define S_ERR_GTS_SYNC    20
+#define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC)
+#define F_ERR_GTS_SYNC    V_ERR_GTS_SYNC(1U)
+
+#define S_FATAL_LARGE_COAL    19
+#define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL)
+#define F_FATAL_LARGE_COAL    V_FATAL_LARGE_COAL(1U)
+
+#define S_PL_BAR2_FRM_ERR    18
+#define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR)
+#define F_PL_BAR2_FRM_ERR    V_PL_BAR2_FRM_ERR(1U)
+
+#define S_SILENT_DROP_TX_COAL    17
+#define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL)
+#define F_SILENT_DROP_TX_COAL    V_SILENT_DROP_TX_COAL(1U)
+
+#define S_ERR_INV_CTXT4    16
+#define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4)
+#define F_ERR_INV_CTXT4    V_ERR_INV_CTXT4(1U)
+
+#define S_ERR_BAD_DB_PIDX4    15
+#define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4)
+#define F_ERR_BAD_DB_PIDX4    V_ERR_BAD_DB_PIDX4(1U)
+
+#define S_ERR_BAD_UPFL_INC_CREDIT4    14
+#define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4)
+#define F_ERR_BAD_UPFL_INC_CREDIT4    V_ERR_BAD_UPFL_INC_CREDIT4(1U)
+
+#define S_FATAL_TAG_MISMATCH    13
+#define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH)
+#define F_FATAL_TAG_MISMATCH    V_FATAL_TAG_MISMATCH(1U)
+
+#define S_FATAL_ENQ_CTL_RDY    12
+#define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY)
+#define F_FATAL_ENQ_CTL_RDY    V_FATAL_ENQ_CTL_RDY(1U)
+
+#define S_ERR_PC_RSP_LEN3    11
+#define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3)
+#define F_ERR_PC_RSP_LEN3    V_ERR_PC_RSP_LEN3(1U)
+
+#define S_ERR_PC_RSP_LEN2    10
+#define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2)
+#define F_ERR_PC_RSP_LEN2    V_ERR_PC_RSP_LEN2(1U)
+
+#define S_ERR_PC_RSP_LEN1    9
+#define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1)
+#define F_ERR_PC_RSP_LEN1    V_ERR_PC_RSP_LEN1(1U)
+
+#define S_ERR_PC_RSP_LEN0    8
+#define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0)
+#define F_ERR_PC_RSP_LEN0    V_ERR_PC_RSP_LEN0(1U)
+
+#define S_FATAL_ENQ2LL_VLD    7
+#define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD)
+#define F_FATAL_ENQ2LL_VLD    V_FATAL_ENQ2LL_VLD(1U)
+
+#define S_FATAL_LL_EMPTY    6
+#define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY)
+#define F_FATAL_LL_EMPTY    V_FATAL_LL_EMPTY(1U)
+
+#define S_FATAL_OFF_WDENQ    5
+#define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ)
+#define F_FATAL_OFF_WDENQ    V_FATAL_OFF_WDENQ(1U)
+
+#define S_FATAL_DEQ_DRDY    3
+#define M_FATAL_DEQ_DRDY    0x3U
+#define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY)
+#define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY)
+
+#define S_FATAL_OUTP_DRDY    1
+#define M_FATAL_OUTP_DRDY    0x3U
+#define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY)
+#define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY)
+
+#define S_FATAL_DEQ    0
+#define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ)
+#define F_FATAL_DEQ    V_FATAL_DEQ(1U)
+
 #define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
 
 #define S_THROTTLE_THRESHOLD_FL    16
@@ -1980,6 +2481,7 @@
 #define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP)
 #define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP)
 
+#define A_SGE_INT_ENABLE6 0x112c
 #define A_SGE_DBP_FETCH_THRESHOLD 0x1130
 
 #define S_DBP_FETCH_THRESHOLD_FL    21
@@ -2037,6 +2539,11 @@
 #define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
 #define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
 
+#define S_T6_DBVFIFO_SIZE    0
+#define M_T6_DBVFIFO_SIZE    0x1fffU
+#define V_T6_DBVFIFO_SIZE(x) ((x) << S_T6_DBVFIFO_SIZE)
+#define G_T6_DBVFIFO_SIZE(x) (((x) >> S_T6_DBVFIFO_SIZE) & M_T6_DBVFIFO_SIZE)
+
 #define A_SGE_DBFIFO_STATUS3 0x1140
 
 #define S_LP_PTRS_EQUAL    21
@@ -2064,6 +2571,18 @@
 
 #define A_SGE_CHANGESET 0x1144
 #define A_SGE_PC_RSP_ERROR 0x1148
+#define A_SGE_TBUF_CONTROL 0x114c
+
+#define S_DBPTBUFRSV1    9
+#define M_DBPTBUFRSV1    0x1ffU
+#define V_DBPTBUFRSV1(x) ((x) << S_DBPTBUFRSV1)
+#define G_DBPTBUFRSV1(x) (((x) >> S_DBPTBUFRSV1) & M_DBPTBUFRSV1)
+
+#define S_DBPTBUFRSV0    0
+#define M_DBPTBUFRSV0    0x1ffU
+#define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0)
+#define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0)
+
 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
@@ -2109,6 +2628,115 @@
 #define A_SGE_CTXT_MASK5 0x1234
 #define A_SGE_CTXT_MASK6 0x1238
 #define A_SGE_CTXT_MASK7 0x123c
+#define A_SGE_QBASE_MAP0 0x1240
+
+#define S_EGRESS0_SIZE    24
+#define M_EGRESS0_SIZE    0x1fU
+#define V_EGRESS0_SIZE(x) ((x) << S_EGRESS0_SIZE)
+#define G_EGRESS0_SIZE(x) (((x) >> S_EGRESS0_SIZE) & M_EGRESS0_SIZE)
+
+#define S_EGRESS1_SIZE    16
+#define M_EGRESS1_SIZE    0x1fU
+#define V_EGRESS1_SIZE(x) ((x) << S_EGRESS1_SIZE)
+#define G_EGRESS1_SIZE(x) (((x) >> S_EGRESS1_SIZE) & M_EGRESS1_SIZE)
+
+#define S_INGRESS0_SIZE    8
+#define M_INGRESS0_SIZE    0x1fU
+#define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE)
+#define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE)
+
+#define A_SGE_QBASE_MAP1 0x1244
+
+#define S_EGRESS0_BASE    0
+#define M_EGRESS0_BASE    0x1ffffU
+#define V_EGRESS0_BASE(x) ((x) << S_EGRESS0_BASE)
+#define G_EGRESS0_BASE(x) (((x) >> S_EGRESS0_BASE) & M_EGRESS0_BASE)
+
+#define A_SGE_QBASE_MAP2 0x1248
+
+#define S_EGRESS1_BASE    0
+#define M_EGRESS1_BASE    0x1ffffU
+#define V_EGRESS1_BASE(x) ((x) << S_EGRESS1_BASE)
+#define G_EGRESS1_BASE(x) (((x) >> S_EGRESS1_BASE) & M_EGRESS1_BASE)
+
+#define A_SGE_QBASE_MAP3 0x124c
+
+#define S_INGRESS1_BASE_256VF    16
+#define M_INGRESS1_BASE_256VF    0xffffU
+#define V_INGRESS1_BASE_256VF(x) ((x) << S_INGRESS1_BASE_256VF)
+#define G_INGRESS1_BASE_256VF(x) (((x) >> S_INGRESS1_BASE_256VF) & M_INGRESS1_BASE_256VF)
+
+#define S_INGRESS0_BASE    0
+#define M_INGRESS0_BASE    0xffffU
+#define V_INGRESS0_BASE(x) ((x) << S_INGRESS0_BASE)
+#define G_INGRESS0_BASE(x) (((x) >> S_INGRESS0_BASE) & M_INGRESS0_BASE)
+
+#define A_SGE_QBASE_INDEX 0x1250
+
+#define S_QIDX    0
+#define M_QIDX    0x1ffU
+#define V_QIDX(x) ((x) << S_QIDX)
+#define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX)
+
+#define A_SGE_CONM_CTRL2 0x1254
+
+#define S_FLMTHRESHPACK    8
+#define M_FLMTHRESHPACK    0x7fU
+#define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK)
+#define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK)
+
+#define S_FLMTHRESH    0
+#define M_FLMTHRESH    0x7fU
+#define V_FLMTHRESH(x) ((x) << S_FLMTHRESH)
+#define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH)
+
+#define A_SGE_DEBUG_CONM 0x1258
+
+#define S_MPS_CH_CNG    16
+#define M_MPS_CH_CNG    0xffffU
+#define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG)
+#define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG)
+
+#define S_TP_CH_CNG    14
+#define M_TP_CH_CNG    0x3U
+#define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG)
+#define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG)
+
+#define S_ST_CONG    12
+#define M_ST_CONG    0x3U
+#define V_ST_CONG(x) ((x) << S_ST_CONG)
+#define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG)
+
+#define S_LAST_XOFF    10
+#define V_LAST_XOFF(x) ((x) << S_LAST_XOFF)
+#define F_LAST_XOFF    V_LAST_XOFF(1U)
+
+#define S_LAST_QID    0
+#define M_LAST_QID    0x3ffU
+#define V_LAST_QID(x) ((x) << S_LAST_QID)
+#define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID)
+
+#define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c
+
+#define S_IMSG_GTS_SEL    18
+#define V_IMSG_GTS_SEL(x) ((x) << S_IMSG_GTS_SEL)
+#define F_IMSG_GTS_SEL    V_IMSG_GTS_SEL(1U)
+
+#define S_MGT_SEL    17
+#define V_MGT_SEL(x) ((x) << S_MGT_SEL)
+#define F_MGT_SEL    V_MGT_SEL(1U)
+
+#define S_DB_GTS_QID    0
+#define M_DB_GTS_QID    0x1ffffU
+#define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID)
+#define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID)
+
+#define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260
+#define A_SGE_DBG_QUEUE_STAT0 0x1264
+#define A_SGE_DBG_QUEUE_STAT1 0x1268
+#define A_SGE_DBG_BAR2_PKT_CNT 0x126c
+#define A_SGE_DBG_DB_PKT_CNT 0x1270
+#define A_SGE_DBG_GTS_PKT_CNT 0x1274
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
 
 #define S_CIM_WM    24
@@ -2146,6 +2774,16 @@
 #define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
 #define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
 
+#define S_DEBUG_BAR2_SOP_CNT    28
+#define M_DEBUG_BAR2_SOP_CNT    0xfU
+#define V_DEBUG_BAR2_SOP_CNT(x) ((x) << S_DEBUG_BAR2_SOP_CNT)
+#define G_DEBUG_BAR2_SOP_CNT(x) (((x) >> S_DEBUG_BAR2_SOP_CNT) & M_DEBUG_BAR2_SOP_CNT)
+
+#define S_DEBUG_BAR2_EOP_CNT    24
+#define M_DEBUG_BAR2_EOP_CNT    0xfU
+#define V_DEBUG_BAR2_EOP_CNT(x) ((x) << S_DEBUG_BAR2_EOP_CNT)
+#define G_DEBUG_BAR2_EOP_CNT(x) (((x) >> S_DEBUG_BAR2_EOP_CNT) & M_DEBUG_BAR2_EOP_CNT)
+
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
 
 #define S_DEBUG_T_RX_SOP1_CNT    28
@@ -2230,6 +2868,16 @@
 #define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
 #define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
 
+#define S_DBG_TBUF_USED1    9
+#define M_DBG_TBUF_USED1    0x1ffU
+#define V_DBG_TBUF_USED1(x) ((x) << S_DBG_TBUF_USED1)
+#define G_DBG_TBUF_USED1(x) (((x) >> S_DBG_TBUF_USED1) & M_DBG_TBUF_USED1)
+
+#define S_DBG_TBUF_USED0    0
+#define M_DBG_TBUF_USED0    0x1ffU
+#define V_DBG_TBUF_USED0(x) ((x) << S_DBG_TBUF_USED0)
+#define G_DBG_TBUF_USED0(x) (((x) >> S_DBG_TBUF_USED0) & M_DBG_TBUF_USED0)
+
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
 
 #define S_DEBUG_U_TX_SOP3_CNT    28
@@ -2272,6 +2920,28 @@
 #define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
 #define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
 
+#define A_SGE_DEBUG1_DBP_THREAD 0x128c
+
+#define S_WR_DEQ_CNT    12
+#define M_WR_DEQ_CNT    0xfU
+#define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT)
+#define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT)
+
+#define S_WR_ENQ_CNT    8
+#define M_WR_ENQ_CNT    0xfU
+#define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT)
+#define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT)
+
+#define S_FL_DEQ_CNT    4
+#define M_FL_DEQ_CNT    0xfU
+#define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT)
+#define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT)
+
+#define S_FL_ENQ_CNT    0
+#define M_FL_ENQ_CNT    0xfU
+#define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT)
+#define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT)
+
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
 
 #define S_DEBUG_PC_RSP_SOP1_CNT    28
@@ -2440,6 +3110,26 @@
 #define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
 #define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
 
+#define S_DEBUG_PC_RSP_SOP_CNT    28
+#define M_DEBUG_PC_RSP_SOP_CNT    0xfU
+#define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT)
+#define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT)
+
+#define S_DEBUG_PC_RSP_EOP_CNT    24
+#define M_DEBUG_PC_RSP_EOP_CNT    0xfU
+#define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT)
+#define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT)
+
+#define S_DEBUG_PC_REQ_SOP_CNT    20
+#define M_DEBUG_PC_REQ_SOP_CNT    0xfU
+#define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT)
+#define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT)
+
+#define S_DEBUG_PC_REQ_EOP_CNT    16
+#define M_DEBUG_PC_REQ_EOP_CNT    0xfU
+#define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT)
+#define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT)
+
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
 
 #define S_GLOBALENABLE_OFF    29
@@ -2512,6 +3202,14 @@
 #define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
 #define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
 
+#define S_DEBUG_PL_BAR2_REQVLD    31
+#define V_DEBUG_PL_BAR2_REQVLD(x) ((x) << S_DEBUG_PL_BAR2_REQVLD)
+#define F_DEBUG_PL_BAR2_REQVLD    V_DEBUG_PL_BAR2_REQVLD(1U)
+
+#define S_DEBUG_PL_BAR2_REQFULL    30
+#define V_DEBUG_PL_BAR2_REQFULL(x) ((x) << S_DEBUG_PL_BAR2_REQFULL)
+#define F_DEBUG_PL_BAR2_REQFULL    V_DEBUG_PL_BAR2_REQFULL(1U)
+
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
 
 #define S_DEBUG_CPLSW_TP_RX_SOP1_CNT    28
@@ -2606,6 +3304,94 @@
 #define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
 #define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
 
+#define S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    28
+#define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    0xfU
+#define V_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
+#define G_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
+
+#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    27
+#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY)
+#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(1U)
+
+#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    26
+#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS)
+#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(1U)
+
+#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    25
+#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL)
+#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(1U)
+
+#define S_DEBUG_IDMA1_IDMA2IMSG_FULL    24
+#define V_DEBUG_IDMA1_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FULL)
+#define F_DEBUG_IDMA1_IDMA2IMSG_FULL    V_DEBUG_IDMA1_IDMA2IMSG_FULL(1U)
+
+#define S_DEBUG_IDMA1_IDMA2IMSG_EOP    23
+#define V_DEBUG_IDMA1_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_EOP)
+#define F_DEBUG_IDMA1_IDMA2IMSG_EOP    V_DEBUG_IDMA1_IDMA2IMSG_EOP(1U)
+
+#define S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    22
+#define V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY)
+#define F_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(1U)
+
+#define S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    21
+#define V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY)
+#define F_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(1U)
+
+#define S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    17
+#define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    0xfU
+#define V_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
+#define G_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
+
+#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    16
+#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY)
+#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(1U)
+
+#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    15
+#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS)
+#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(1U)
+
+#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    14
+#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL)
+#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(1U)
+
+#define S_DEBUG_IDMA0_IDMA2IMSG_FULL    13
+#define V_DEBUG_IDMA0_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FULL)
+#define F_DEBUG_IDMA0_IDMA2IMSG_FULL    V_DEBUG_IDMA0_IDMA2IMSG_FULL(1U)
+
+#define S_DEBUG_IDMA0_IDMA2IMSG_EOP    12
+#define V_DEBUG_IDMA0_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_EOP)
+#define F_DEBUG_IDMA0_IDMA2IMSG_EOP    V_DEBUG_IDMA0_IDMA2IMSG_EOP(1U)
+
+#define S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    11
+#define V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY)
+#define F_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(1U)
+
+#define S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    10
+#define V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY)
+#define F_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(1U)
+
+#define S_T6_DEBUG_T_RXAFULL_D    8
+#define M_T6_DEBUG_T_RXAFULL_D    0x3U
+#define V_T6_DEBUG_T_RXAFULL_D(x) ((x) << S_T6_DEBUG_T_RXAFULL_D)
+#define G_T6_DEBUG_T_RXAFULL_D(x) (((x) >> S_T6_DEBUG_T_RXAFULL_D) & M_T6_DEBUG_T_RXAFULL_D)
+
+#define S_T6_DEBUG_PD_WRREQAFULL_D    6
+#define M_T6_DEBUG_PD_WRREQAFULL_D    0x3U
+#define V_T6_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_T6_DEBUG_PD_WRREQAFULL_D)
+#define G_T6_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_T6_DEBUG_PD_WRREQAFULL_D) & M_T6_DEBUG_PD_WRREQAFULL_D)
+
+#define S_T6_DEBUG_PC_RSPAFULL_D    5
+#define V_T6_DEBUG_PC_RSPAFULL_D(x) ((x) << S_T6_DEBUG_PC_RSPAFULL_D)
+#define F_T6_DEBUG_PC_RSPAFULL_D    V_T6_DEBUG_PC_RSPAFULL_D(1U)
+
+#define S_T6_DEBUG_PC_REQAFULL_D    4
+#define V_T6_DEBUG_PC_REQAFULL_D(x) ((x) << S_T6_DEBUG_PC_REQAFULL_D)
+#define F_T6_DEBUG_PC_REQAFULL_D    V_T6_DEBUG_PC_REQAFULL_D(1U)
+
+#define S_T6_DEBUG_CIM_AFULL_D    0
+#define V_T6_DEBUG_CIM_AFULL_D(x) ((x) << S_T6_DEBUG_CIM_AFULL_D)
+#define F_T6_DEBUG_CIM_AFULL_D    V_T6_DEBUG_CIM_AFULL_D(1U)
+
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
 
 #define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    24
@@ -2702,6 +3488,16 @@
 #define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
 #define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
 
+#define S_DEBUG_IDMA1_ISHIFT_TX_SIZE    8
+#define M_DEBUG_IDMA1_ISHIFT_TX_SIZE    0x7fU
+#define V_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA1_ISHIFT_TX_SIZE)
+#define G_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA1_ISHIFT_TX_SIZE) & M_DEBUG_IDMA1_ISHIFT_TX_SIZE)
+
+#define S_DEBUG_IDMA0_ISHIFT_TX_SIZE    0
+#define M_DEBUG_IDMA0_ISHIFT_TX_SIZE    0x7fU
+#define V_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA0_ISHIFT_TX_SIZE)
+#define G_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA0_ISHIFT_TX_SIZE) & M_DEBUG_IDMA0_ISHIFT_TX_SIZE)
+
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
 #define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
@@ -2747,6 +3543,14 @@
 #define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
 #define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
 
+#define S_DEBUG_ST_IDMA1_IDMA2IMSG    15
+#define V_DEBUG_ST_IDMA1_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA1_IDMA2IMSG)
+#define F_DEBUG_ST_IDMA1_IDMA2IMSG    V_DEBUG_ST_IDMA1_IDMA2IMSG(1U)
+
+#define S_DEBUG_ST_IDMA0_IDMA2IMSG    6
+#define V_DEBUG_ST_IDMA0_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA0_IDMA2IMSG)
+#define F_DEBUG_ST_IDMA0_IDMA2IMSG    V_DEBUG_ST_IDMA0_IDMA2IMSG(1U)
+
 #define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
 
 #define S_DEBUG_ITP_EMPTY    12
@@ -2808,6 +3612,11 @@
 #define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
 #define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
 
+#define S_T6_DEBUG_ST_DBP_UPCP_MAIN    14
+#define M_T6_DEBUG_ST_DBP_UPCP_MAIN    0x7U
+#define V_T6_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_T6_DEBUG_ST_DBP_UPCP_MAIN)
+#define G_T6_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_T6_DEBUG_ST_DBP_UPCP_MAIN) & M_T6_DEBUG_ST_DBP_UPCP_MAIN)
+
 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
 
 #define S_DEBUG_ST_DBP_UPCP_MAIN    14
@@ -2927,6 +3736,28 @@
 #define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
 #define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)
 
+#define A_SGE_DEBUG0_DBP_THREAD 0x12d4
+
+#define S_THREAD_ST_MAIN    25
+#define M_THREAD_ST_MAIN    0x3fU
+#define V_THREAD_ST_MAIN(x) ((x) << S_THREAD_ST_MAIN)
+#define G_THREAD_ST_MAIN(x) (((x) >> S_THREAD_ST_MAIN) & M_THREAD_ST_MAIN)
+
+#define S_THREAD_ST_CIMFL    21
+#define M_THREAD_ST_CIMFL    0xfU
+#define V_THREAD_ST_CIMFL(x) ((x) << S_THREAD_ST_CIMFL)
+#define G_THREAD_ST_CIMFL(x) (((x) >> S_THREAD_ST_CIMFL) & M_THREAD_ST_CIMFL)
+
+#define S_THREAD_CMDOP    17
+#define M_THREAD_CMDOP    0xfU
+#define V_THREAD_CMDOP(x) ((x) << S_THREAD_CMDOP)
+#define G_THREAD_CMDOP(x) (((x) >> S_THREAD_CMDOP) & M_THREAD_CMDOP)
+
+#define S_THREAD_QID    0
+#define M_THREAD_QID    0x1ffffU
+#define V_THREAD_QID(x) ((x) << S_THREAD_QID)
+#define G_THREAD_QID(x) (((x) >> S_THREAD_QID) & M_THREAD_QID)
+
 #define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
 
 #define S_DEBUG_DBP_THREAD0_QID    0
@@ -3031,6 +3862,37 @@
 #define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
 #define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
 
+#define A_SGE_WC_EGRS_BAR2_OFF_PF 0x1300
+
+#define S_PFIQSPERPAGE    28
+#define M_PFIQSPERPAGE    0xfU
+#define V_PFIQSPERPAGE(x) ((x) << S_PFIQSPERPAGE)
+#define G_PFIQSPERPAGE(x) (((x) >> S_PFIQSPERPAGE) & M_PFIQSPERPAGE)
+
+#define S_PFEQSPERPAGE    24
+#define M_PFEQSPERPAGE    0xfU
+#define V_PFEQSPERPAGE(x) ((x) << S_PFEQSPERPAGE)
+#define G_PFEQSPERPAGE(x) (((x) >> S_PFEQSPERPAGE) & M_PFEQSPERPAGE)
+
+#define S_PFWCQSPERPAGE    20
+#define M_PFWCQSPERPAGE    0xfU
+#define V_PFWCQSPERPAGE(x) ((x) << S_PFWCQSPERPAGE)
+#define G_PFWCQSPERPAGE(x) (((x) >> S_PFWCQSPERPAGE) & M_PFWCQSPERPAGE)
+
+#define S_PFWCOFFEN    19
+#define V_PFWCOFFEN(x) ((x) << S_PFWCOFFEN)
+#define F_PFWCOFFEN    V_PFWCOFFEN(1U)
+
+#define S_PFMAXWCSIZE    17
+#define M_PFMAXWCSIZE    0x3U
+#define V_PFMAXWCSIZE(x) ((x) << S_PFMAXWCSIZE)
+#define G_PFMAXWCSIZE(x) (((x) >> S_PFMAXWCSIZE) & M_PFMAXWCSIZE)
+
+#define S_PFWCOFFSET    0
+#define M_PFWCOFFSET    0x1ffffU
+#define V_PFWCOFFSET(x) ((x) << S_PFWCOFFSET)
+#define G_PFWCOFFSET(x) (((x) >> S_PFWCOFFSET) & M_PFWCOFFSET)
+
 #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
 
 #define S_INGRESS2_BASE    16
@@ -3043,6 +3905,37 @@
 #define V_INGRESS1_BASE(x) ((x) << S_INGRESS1_BASE)
 #define G_INGRESS1_BASE(x) (((x) >> S_INGRESS1_BASE) & M_INGRESS1_BASE)
 
+#define A_SGE_WC_EGRS_BAR2_OFF_VF 0x1320
+
+#define S_VFIQSPERPAGE    28
+#define M_VFIQSPERPAGE    0xfU
+#define V_VFIQSPERPAGE(x) ((x) << S_VFIQSPERPAGE)
+#define G_VFIQSPERPAGE(x) (((x) >> S_VFIQSPERPAGE) & M_VFIQSPERPAGE)
+
+#define S_VFEQSPERPAGE    24
+#define M_VFEQSPERPAGE    0xfU
+#define V_VFEQSPERPAGE(x) ((x) << S_VFEQSPERPAGE)
+#define G_VFEQSPERPAGE(x) (((x) >> S_VFEQSPERPAGE) & M_VFEQSPERPAGE)
+
+#define S_VFWCQSPERPAGE    20
+#define M_VFWCQSPERPAGE    0xfU
+#define V_VFWCQSPERPAGE(x) ((x) << S_VFWCQSPERPAGE)
+#define G_VFWCQSPERPAGE(x) (((x) >> S_VFWCQSPERPAGE) & M_VFWCQSPERPAGE)
+
+#define S_VFWCOFFEN    19
+#define V_VFWCOFFEN(x) ((x) << S_VFWCOFFEN)
+#define F_VFWCOFFEN    V_VFWCOFFEN(1U)
+
+#define S_VFMAXWCSIZE    17
+#define M_VFMAXWCSIZE    0x3U
+#define V_VFMAXWCSIZE(x) ((x) << S_VFMAXWCSIZE)
+#define G_VFMAXWCSIZE(x) (((x) >> S_VFMAXWCSIZE) & M_VFMAXWCSIZE)
+
+#define S_VFWCOFFSET    0
+#define M_VFWCOFFSET    0x1ffffU
+#define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET)
+#define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET)
+
 #define A_SGE_LA_RDPTR_0 0x1800
 #define A_SGE_LA_RDDATA_0 0x1804
 #define A_SGE_LA_WRPTR_0 0x1808
@@ -3380,6 +4273,11 @@
 #define V_IDE(x) ((x) << S_IDE)
 #define F_IDE    V_IDE(1U)
 
+#define S_MEMSEL_PCIE    1
+#define M_MEMSEL_PCIE    0x1fU
+#define V_MEMSEL_PCIE(x) ((x) << S_MEMSEL_PCIE)
+#define G_MEMSEL_PCIE(x) (((x) >> S_MEMSEL_PCIE) & M_MEMSEL_PCIE)
+
 #define A_PCIE_NONFAT_ERR 0x3010
 
 #define S_RDRSPERR    9
@@ -3506,6 +4404,14 @@
 #define V_BAR2REQ(x) ((x) << S_BAR2REQ)
 #define F_BAR2REQ    V_BAR2REQ(1U)
 
+#define S_MARSPUE    30
+#define V_MARSPUE(x) ((x) << S_MARSPUE)
+#define F_MARSPUE    V_MARSPUE(1U)
+
+#define S_KDBEOPERR    7
+#define V_KDBEOPERR(x) ((x) << S_KDBEOPERR)
+#define F_KDBEOPERR    V_KDBEOPERR(1U)
+
 #define A_PCIE_CFG 0x3014
 
 #define S_CFGDMAXPYLDSZRX    26
@@ -3596,6 +4502,10 @@
 #define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN)
 #define F_LINKDNRSTEN    V_LINKDNRSTEN(1U)
 
+#define S_T5_PIOSTOPEN    31
+#define V_T5_PIOSTOPEN(x) ((x) << S_T5_PIOSTOPEN)
+#define F_T5_PIOSTOPEN    V_T5_PIOSTOPEN(1U)
+
 #define S_DIAGCTRLBUS    28
 #define M_DIAGCTRLBUS    0x7U
 #define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS)
@@ -3643,6 +4553,10 @@
 #define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE)
 #define F_LINKREQRSTPCIECRSTMODE    V_LINKREQRSTPCIECRSTMODE(1U)
 
+#define S_T6_PIOSTOPEN    31
+#define V_T6_PIOSTOPEN(x) ((x) << S_T6_PIOSTOPEN)
+#define F_T6_PIOSTOPEN    V_T6_PIOSTOPEN(1U)
+
 #define A_PCIE_DMA_CTRL 0x3018
 
 #define S_LITTLEENDIAN    7
@@ -3670,6 +4584,11 @@
 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
 #define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)
 
+#define S_T6_TOTMAXTAG    0
+#define M_T6_TOTMAXTAG    0x7U
+#define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
+#define G_T6_TOTMAXTAG(x) (((x) >> S_T6_TOTMAXTAG) & M_T6_TOTMAXTAG)
+
 #define A_PCIE_DMA_CFG 0x301c
 
 #define S_MAXPYLDSIZE    28
@@ -3799,6 +4718,7 @@
 #define V_PERSTTIMER(x) ((x) << S_PERSTTIMER)
 #define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER)
 
+#define A_PCIE_CFG7 0x302c
 #define A_PCIE_CMD_CTRL 0x303c
 #define A_PCIE_CMD_CFG 0x3040
 
@@ -3936,6 +4856,32 @@
 #define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
 #define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)
 
+#define S_T6_ENABLE    31
+#define V_T6_ENABLE(x) ((x) << S_T6_ENABLE)
+#define F_T6_ENABLE    V_T6_ENABLE(1U)
+
+#define S_T6_AI    30
+#define V_T6_AI(x) ((x) << S_T6_AI)
+#define F_T6_AI    V_T6_AI(1U)
+
+#define S_T6_CS2    29
+#define V_T6_CS2(x) ((x) << S_T6_CS2)
+#define F_T6_CS2    V_T6_CS2(1U)
+
+#define S_T6_WRBE    25
+#define M_T6_WRBE    0xfU
+#define V_T6_WRBE(x) ((x) << S_T6_WRBE)
+#define G_T6_WRBE(x) (((x) >> S_T6_WRBE) & M_T6_WRBE)
+
+#define S_T6_CFG_SPACE_VFVLD    24
+#define V_T6_CFG_SPACE_VFVLD(x) ((x) << S_T6_CFG_SPACE_VFVLD)
+#define F_T6_CFG_SPACE_VFVLD    V_T6_CFG_SPACE_VFVLD(1U)
+
+#define S_T6_CFG_SPACE_RVF    16
+#define M_T6_CFG_SPACE_RVF    0xffU
+#define V_T6_CFG_SPACE_RVF(x) ((x) << S_T6_CFG_SPACE_RVF)
+#define G_T6_CFG_SPACE_RVF(x) (((x) >> S_T6_CFG_SPACE_RVF) & M_T6_CFG_SPACE_RVF)
+
 #define A_PCIE_CFG_SPACE_DATA 0x3064
 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
 
@@ -4265,6 +5211,30 @@
 #define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF)
 #define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF)
 
+#define S_T6_FID_VFID_VFID    15
+#define M_T6_FID_VFID_VFID    0x1ffU
+#define V_T6_FID_VFID_VFID(x) ((x) << S_T6_FID_VFID_VFID)
+#define G_T6_FID_VFID_VFID(x) (((x) >> S_T6_FID_VFID_VFID) & M_T6_FID_VFID_VFID)
+
+#define S_T6_FID_VFID_TC    12
+#define M_T6_FID_VFID_TC    0x7U
+#define V_T6_FID_VFID_TC(x) ((x) << S_T6_FID_VFID_TC)
+#define G_T6_FID_VFID_TC(x) (((x) >> S_T6_FID_VFID_TC) & M_T6_FID_VFID_TC)
+
+#define S_T6_FID_VFID_VFVLD    11
+#define V_T6_FID_VFID_VFVLD(x) ((x) << S_T6_FID_VFID_VFVLD)
+#define F_T6_FID_VFID_VFVLD    V_T6_FID_VFID_VFVLD(1U)
+
+#define S_T6_FID_VFID_PF    8
+#define M_T6_FID_VFID_PF    0x7U
+#define V_T6_FID_VFID_PF(x) ((x) << S_T6_FID_VFID_PF)
+#define G_T6_FID_VFID_PF(x) (((x) >> S_T6_FID_VFID_PF) & M_T6_FID_VFID_PF)
+
+#define S_T6_FID_VFID_RVF    0
+#define M_T6_FID_VFID_RVF    0xffU
+#define V_T6_FID_VFID_RVF(x) ((x) << S_T6_FID_VFID_RVF)
+#define G_T6_FID_VFID_RVF(x) (((x) >> S_T6_FID_VFID_RVF) & M_T6_FID_VFID_RVF)
+
 #define A_PCIE_FID 0x3900
 
 #define S_PAD    11
@@ -4327,6 +5297,26 @@
 #define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE)
 #define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE)
 
+#define S_RCVDVDMRXCOOKIE    24
+#define M_RCVDVDMRXCOOKIE    0xffU
+#define V_RCVDVDMRXCOOKIE(x) ((x) << S_RCVDVDMRXCOOKIE)
+#define G_RCVDVDMRXCOOKIE(x) (((x) >> S_RCVDVDMRXCOOKIE) & M_RCVDVDMRXCOOKIE)
+
+#define S_RCVDVDMTXCOOKIE    16
+#define M_RCVDVDMTXCOOKIE    0xffU
+#define V_RCVDVDMTXCOOKIE(x) ((x) << S_RCVDVDMTXCOOKIE)
+#define G_RCVDVDMTXCOOKIE(x) (((x) >> S_RCVDVDMTXCOOKIE) & M_RCVDVDMTXCOOKIE)
+
+#define S_T6_RCVDMAREQCOOKIE    8
+#define M_T6_RCVDMAREQCOOKIE    0xffU
+#define V_T6_RCVDMAREQCOOKIE(x) ((x) << S_T6_RCVDMAREQCOOKIE)
+#define G_T6_RCVDMAREQCOOKIE(x) (((x) >> S_T6_RCVDMAREQCOOKIE) & M_T6_RCVDMAREQCOOKIE)
+
+#define S_T6_RCVDPIOREQCOOKIE    0
+#define M_T6_RCVDPIOREQCOOKIE    0xffU
+#define V_T6_RCVDPIOREQCOOKIE(x) ((x) << S_T6_RCVDPIOREQCOOKIE)
+#define G_T6_RCVDPIOREQCOOKIE(x) (((x) >> S_T6_RCVDPIOREQCOOKIE) & M_T6_RCVDPIOREQCOOKIE)
+
 #define A_PCIE_VC0_CDTS0 0x56cc
 
 #define S_CPLD0    20
@@ -4426,6 +5416,20 @@
 #define V_STATECFGINIT(x) ((x) << S_STATECFGINIT)
 #define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT)
 
+#define S_LTSSMENABLE_PCIE    12
+#define V_LTSSMENABLE_PCIE(x) ((x) << S_LTSSMENABLE_PCIE)
+#define F_LTSSMENABLE_PCIE    V_LTSSMENABLE_PCIE(1U)
+
+#define S_STATECFGINITF_PCIE    4
+#define M_STATECFGINITF_PCIE    0xffU
+#define V_STATECFGINITF_PCIE(x) ((x) << S_STATECFGINITF_PCIE)
+#define G_STATECFGINITF_PCIE(x) (((x) >> S_STATECFGINITF_PCIE) & M_STATECFGINITF_PCIE)
+
+#define S_STATECFGINIT_PCIE    0
+#define M_STATECFGINIT_PCIE    0xfU
+#define V_STATECFGINIT_PCIE(x) ((x) << S_STATECFGINIT_PCIE)
+#define G_STATECFGINIT_PCIE(x) (((x) >> S_STATECFGINIT_PCIE) & M_STATECFGINIT_PCIE)
+
 #define A_PCIE_CRS 0x56f8
 
 #define S_CRS_ENABLE    0
@@ -4438,6 +5442,10 @@
 #define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE)
 #define F_LTSSM_ENABLE    V_LTSSM_ENABLE(1U)
 
+#define S_LTSSM_STALL_DISABLE    1
+#define V_LTSSM_STALL_DISABLE(x) ((x) << S_LTSSM_STALL_DISABLE)
+#define F_LTSSM_STALL_DISABLE    V_LTSSM_STALL_DISABLE(1U)
+
 #define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700
 
 #define S_REPLAY_TIME_LIMIT    16
@@ -4838,6 +5846,15 @@
 #define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3)
 #define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3)
 
+#define S_AUTO_LANE_FLIP_CTRL_EN    16
+#define V_AUTO_LANE_FLIP_CTRL_EN(x) ((x) << S_AUTO_LANE_FLIP_CTRL_EN)
+#define F_AUTO_LANE_FLIP_CTRL_EN    V_AUTO_LANE_FLIP_CTRL_EN(1U)
+
+#define S_T6_NUM_LANES    8
+#define M_T6_NUM_LANES    0x1fU
+#define V_T6_NUM_LANES(x) ((x) << S_T6_NUM_LANES)
+#define G_T6_NUM_LANES(x) (((x) >> S_T6_NUM_LANES) & M_T6_NUM_LANES)
+
 #define A_PCIE_CORE_PHY_STATUS 0x5810
 #define A_PCIE_CORE_PHY_CONTROL 0x5814
 #define A_PCIE_CORE_GEN3_CONTROL 0x5890
@@ -4964,6 +5981,10 @@
 #define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN)
 #define F_PIPE_LOOPBACK_EN    V_PIPE_LOOPBACK_EN(1U)
 
+#define S_T6_PIPE_LOOPBACK_EN    31
+#define V_T6_PIPE_LOOPBACK_EN(x) ((x) << S_T6_PIPE_LOOPBACK_EN)
+#define F_T6_PIPE_LOOPBACK_EN    V_T6_PIPE_LOOPBACK_EN(1U)
+
 #define A_PCIE_CORE_DBI_RO_WE 0x58bc
 
 #define S_READONLY_WRITEEN    0
@@ -5215,6 +6236,25 @@
 #define V_MINTAG(x) ((x) << S_MINTAG)
 #define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG)
 
+#define S_T6_T5_DMA_MAXREQCNT    20
+#define M_T6_T5_DMA_MAXREQCNT    0x7fU
+#define V_T6_T5_DMA_MAXREQCNT(x) ((x) << S_T6_T5_DMA_MAXREQCNT)
+#define G_T6_T5_DMA_MAXREQCNT(x) (((x) >> S_T6_T5_DMA_MAXREQCNT) & M_T6_T5_DMA_MAXREQCNT)
+
+#define S_T6_T5_DMA_MAXRSPCNT    9
+#define M_T6_T5_DMA_MAXRSPCNT    0xffU
+#define V_T6_T5_DMA_MAXRSPCNT(x) ((x) << S_T6_T5_DMA_MAXRSPCNT)
+#define G_T6_T5_DMA_MAXRSPCNT(x) (((x) >> S_T6_T5_DMA_MAXRSPCNT) & M_T6_T5_DMA_MAXRSPCNT)
+
+#define S_T6_SEQCHKDIS    8
+#define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS)
+#define F_T6_SEQCHKDIS    V_T6_SEQCHKDIS(1U)
+
+#define S_T6_MINTAG    0
+#define M_T6_MINTAG    0xffU
+#define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
+#define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
+
 #define A_PCIE_T5_DMA_STAT 0x5944
 
 #define S_DMA_RESPCNT    20
@@ -5232,6 +6272,21 @@
 #define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT)
 #define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT)
 
+#define S_T6_DMA_RESPCNT    20
+#define M_T6_DMA_RESPCNT    0x3ffU
+#define V_T6_DMA_RESPCNT(x) ((x) << S_T6_DMA_RESPCNT)
+#define G_T6_DMA_RESPCNT(x) (((x) >> S_T6_DMA_RESPCNT) & M_T6_DMA_RESPCNT)
+
+#define S_T6_DMA_RDREQCNT    12
+#define M_T6_DMA_RDREQCNT    0x3fU
+#define V_T6_DMA_RDREQCNT(x) ((x) << S_T6_DMA_RDREQCNT)
+#define G_T6_DMA_RDREQCNT(x) (((x) >> S_T6_DMA_RDREQCNT) & M_T6_DMA_RDREQCNT)
+
+#define S_T6_DMA_WRREQCNT    0
+#define M_T6_DMA_WRREQCNT    0x1ffU
+#define V_T6_DMA_WRREQCNT(x) ((x) << S_T6_DMA_WRREQCNT)
+#define G_T6_DMA_WRREQCNT(x) (((x) >> S_T6_DMA_WRREQCNT) & M_T6_DMA_WRREQCNT)
+
 #define A_PCIE_T5_DMA_STAT2 0x5948
 
 #define S_COOKIECNT    24
@@ -5414,6 +6469,20 @@
 #define V_USECMDPOOL(x) ((x) << S_USECMDPOOL)
 #define F_USECMDPOOL    V_USECMDPOOL(1U)
 
+#define S_T6_T5_CMD_MAXRSPCNT    9
+#define M_T6_T5_CMD_MAXRSPCNT    0x3fU
+#define V_T6_T5_CMD_MAXRSPCNT(x) ((x) << S_T6_T5_CMD_MAXRSPCNT)
+#define G_T6_T5_CMD_MAXRSPCNT(x) (((x) >> S_T6_T5_CMD_MAXRSPCNT) & M_T6_T5_CMD_MAXRSPCNT)
+
+#define S_T6_USECMDPOOL    8
+#define V_T6_USECMDPOOL(x) ((x) << S_T6_USECMDPOOL)
+#define F_T6_USECMDPOOL    V_T6_USECMDPOOL(1U)
+
+#define S_T6_MINTAG    0
+#define M_T6_MINTAG    0xffU
+#define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
+#define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
+
 #define A_PCIE_T5_CMD_STAT 0x5984
 
 #define S_T5_STAT_RSPCNT    20
@@ -5426,6 +6495,16 @@
 #define V_RDREQCNT(x) ((x) << S_RDREQCNT)
 #define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT)
 
+#define S_T6_T5_STAT_RSPCNT    20
+#define M_T6_T5_STAT_RSPCNT    0xffU
+#define V_T6_T5_STAT_RSPCNT(x) ((x) << S_T6_T5_STAT_RSPCNT)
+#define G_T6_T5_STAT_RSPCNT(x) (((x) >> S_T6_T5_STAT_RSPCNT) & M_T6_T5_STAT_RSPCNT)
+
+#define S_T6_RDREQCNT    12
+#define M_T6_RDREQCNT    0xfU
+#define V_T6_RDREQCNT(x) ((x) << S_T6_RDREQCNT)
+#define G_T6_RDREQCNT(x) (((x) >> S_T6_RDREQCNT) & M_T6_RDREQCNT)
+
 #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
 
 #define S_IN0H    24
@@ -5750,6 +6829,25 @@
 #define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT)
 #define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT)
 
+#define S_T6_HMA_MAXREQCNT    20
+#define M_T6_HMA_MAXREQCNT    0x7fU
+#define V_T6_HMA_MAXREQCNT(x) ((x) << S_T6_HMA_MAXREQCNT)
+#define G_T6_HMA_MAXREQCNT(x) (((x) >> S_T6_HMA_MAXREQCNT) & M_T6_HMA_MAXREQCNT)
+
+#define S_T6_T5_HMA_MAXRSPCNT    9
+#define M_T6_T5_HMA_MAXRSPCNT    0xffU
+#define V_T6_T5_HMA_MAXRSPCNT(x) ((x) << S_T6_T5_HMA_MAXRSPCNT)
+#define G_T6_T5_HMA_MAXRSPCNT(x) (((x) >> S_T6_T5_HMA_MAXRSPCNT) & M_T6_T5_HMA_MAXRSPCNT)
+
+#define S_T6_SEQCHKDIS    8
+#define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS)
+#define F_T6_SEQCHKDIS    V_T6_SEQCHKDIS(1U)
+
+#define S_T6_MINTAG    0
+#define M_T6_MINTAG    0xffU
+#define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
+#define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
+
 #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
 
 #define S_RLCS    31
@@ -5813,6 +6911,11 @@
 #define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT)
 #define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT)
 
+#define S_T6_HMA_RESPCNT    20
+#define M_T6_HMA_RESPCNT    0x3ffU
+#define V_T6_HMA_RESPCNT(x) ((x) << S_T6_HMA_RESPCNT)
+#define G_T6_HMA_RESPCNT(x) (((x) >> S_T6_HMA_RESPCNT) & M_T6_HMA_RESPCNT)
+
 #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
 
 #define S_RLCI    31
@@ -6369,6 +7472,26 @@
 #define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR)
 #define F_PIOCPL_PLMRSPPERR    V_PIOCPL_PLMRSPPERR(1U)
 
+#define S_MA_RSPCTLPERR    26
+#define V_MA_RSPCTLPERR(x) ((x) << S_MA_RSPCTLPERR)
+#define F_MA_RSPCTLPERR    V_MA_RSPCTLPERR(1U)
+
+#define S_T6_IPRXDATA_VC0PERR    15
+#define V_T6_IPRXDATA_VC0PERR(x) ((x) << S_T6_IPRXDATA_VC0PERR)
+#define F_T6_IPRXDATA_VC0PERR    V_T6_IPRXDATA_VC0PERR(1U)
+
+#define S_T6_IPRXHDR_VC0PERR    14
+#define V_T6_IPRXHDR_VC0PERR(x) ((x) << S_T6_IPRXHDR_VC0PERR)
+#define F_T6_IPRXHDR_VC0PERR    V_T6_IPRXHDR_VC0PERR(1U)
+
+#define S_PIOCPL_VDMTXCTLPERR    13
+#define V_PIOCPL_VDMTXCTLPERR(x) ((x) << S_PIOCPL_VDMTXCTLPERR)
+#define F_PIOCPL_VDMTXCTLPERR    V_PIOCPL_VDMTXCTLPERR(1U)
+
+#define S_PIOCPL_VDMTXDATAPERR    12
+#define V_PIOCPL_VDMTXDATAPERR(x) ((x) << S_PIOCPL_VDMTXDATAPERR)
+#define F_PIOCPL_VDMTXDATAPERR    V_PIOCPL_VDMTXDATAPERR(1U)
+
 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
 #define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
 
@@ -6460,6 +7583,16 @@
 #define V_REQVFID(x) ((x) << S_REQVFID)
 #define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID)
 
+#define S_T6_ADDR10B    9
+#define M_T6_ADDR10B    0x3ffU
+#define V_T6_ADDR10B(x) ((x) << S_T6_ADDR10B)
+#define G_T6_ADDR10B(x) (((x) >> S_T6_ADDR10B) & M_T6_ADDR10B)
+
+#define S_T6_REQVFID    0
+#define M_T6_REQVFID    0x1ffU
+#define V_T6_REQVFID(x) ((x) << S_T6_REQVFID)
+#define G_T6_REQVFID(x) (((x) >> S_T6_REQVFID) & M_T6_REQVFID)
+
 #define A_PCIE_CHANGESET 0x59fc
 #define A_PCIE_REVISION 0x5a00
 #define A_PCIE_PDEBUG_INDEX 0x5a04
@@ -6474,6 +7607,16 @@
 #define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
 #define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)
 
+#define S_T6_PDEBUGSELH    16
+#define M_T6_PDEBUGSELH    0x7fU
+#define V_T6_PDEBUGSELH(x) ((x) << S_T6_PDEBUGSELH)
+#define G_T6_PDEBUGSELH(x) (((x) >> S_T6_PDEBUGSELH) & M_T6_PDEBUGSELH)
+
+#define S_T6_PDEBUGSELL    0
+#define M_T6_PDEBUGSELL    0x7fU
+#define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL)
+#define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL)
+
 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
 #define A_PCIE_CDEBUG_INDEX 0x5a10
@@ -6664,6 +7807,34 @@
 #define V_PL_TOVF(x) ((x) << S_PL_TOVF)
 #define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF)
 
+#define S_T6_SOURCE    17
+#define M_T6_SOURCE    0x3U
+#define V_T6_SOURCE(x) ((x) << S_T6_SOURCE)
+#define G_T6_SOURCE(x) (((x) >> S_T6_SOURCE) & M_T6_SOURCE)
+
+#define S_T6_DBI_WRITE    13
+#define M_T6_DBI_WRITE    0xfU
+#define V_T6_DBI_WRITE(x) ((x) << S_T6_DBI_WRITE)
+#define G_T6_DBI_WRITE(x) (((x) >> S_T6_DBI_WRITE) & M_T6_DBI_WRITE)
+
+#define S_T6_DBI_CS2    12
+#define V_T6_DBI_CS2(x) ((x) << S_T6_DBI_CS2)
+#define F_T6_DBI_CS2    V_T6_DBI_CS2(1U)
+
+#define S_T6_DBI_PF    9
+#define M_T6_DBI_PF    0x7U
+#define V_T6_DBI_PF(x) ((x) << S_T6_DBI_PF)
+#define G_T6_DBI_PF(x) (((x) >> S_T6_DBI_PF) & M_T6_DBI_PF)
+
+#define S_T6_PL_TOVFVLD    8
+#define V_T6_PL_TOVFVLD(x) ((x) << S_T6_PL_TOVFVLD)
+#define F_T6_PL_TOVFVLD    V_T6_PL_TOVFVLD(1U)
+
+#define S_T6_PL_TOVF    0
+#define M_T6_PL_TOVF    0xffU
+#define V_T6_PL_TOVF(x) ((x) << S_T6_PL_TOVF)
+#define G_T6_PL_TOVF(x) (((x) >> S_T6_PL_TOVF) & M_T6_PL_TOVF)
+
 #define A_PCIE_MSI_EN_0 0x5aa0
 #define A_PCIE_MSI_EN_1 0x5aa4
 #define A_PCIE_MSI_EN_2 0x5aa8
@@ -6869,7 +8040,192 @@
 #define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE)
 #define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE)
 
+#define S_REQ_LNH_RXSTATEDONE    31
+#define V_REQ_LNH_RXSTATEDONE(x) ((x) << S_REQ_LNH_RXSTATEDONE)
+#define F_REQ_LNH_RXSTATEDONE    V_REQ_LNH_RXSTATEDONE(1U)
+
+#define S_REQ_LNH_RXSTATEREQ    30
+#define V_REQ_LNH_RXSTATEREQ(x) ((x) << S_REQ_LNH_RXSTATEREQ)
+#define F_REQ_LNH_RXSTATEREQ    V_REQ_LNH_RXSTATEREQ(1U)
+
+#define S_REQ_LNH_RXPWRSTATE    28
+#define M_REQ_LNH_RXPWRSTATE    0x3U
+#define V_REQ_LNH_RXPWRSTATE(x) ((x) << S_REQ_LNH_RXPWRSTATE)
+#define G_REQ_LNH_RXPWRSTATE(x) (((x) >> S_REQ_LNH_RXPWRSTATE) & M_REQ_LNH_RXPWRSTATE)
+
+#define S_REQ_LNG_RXSTATEDONE    27
+#define V_REQ_LNG_RXSTATEDONE(x) ((x) << S_REQ_LNG_RXSTATEDONE)
+#define F_REQ_LNG_RXSTATEDONE    V_REQ_LNG_RXSTATEDONE(1U)
+
+#define S_REQ_LNG_RXSTATEREQ    26
+#define V_REQ_LNG_RXSTATEREQ(x) ((x) << S_REQ_LNG_RXSTATEREQ)
+#define F_REQ_LNG_RXSTATEREQ    V_REQ_LNG_RXSTATEREQ(1U)
+
+#define S_REQ_LNG_RXPWRSTATE    24
+#define M_REQ_LNG_RXPWRSTATE    0x3U
+#define V_REQ_LNG_RXPWRSTATE(x) ((x) << S_REQ_LNG_RXPWRSTATE)
+#define G_REQ_LNG_RXPWRSTATE(x) (((x) >> S_REQ_LNG_RXPWRSTATE) & M_REQ_LNG_RXPWRSTATE)
+
+#define S_REQ_LNF_RXSTATEDONE    23
+#define V_REQ_LNF_RXSTATEDONE(x) ((x) << S_REQ_LNF_RXSTATEDONE)
+#define F_REQ_LNF_RXSTATEDONE    V_REQ_LNF_RXSTATEDONE(1U)
+
+#define S_REQ_LNF_RXSTATEREQ    22
+#define V_REQ_LNF_RXSTATEREQ(x) ((x) << S_REQ_LNF_RXSTATEREQ)
+#define F_REQ_LNF_RXSTATEREQ    V_REQ_LNF_RXSTATEREQ(1U)
+
+#define S_REQ_LNF_RXPWRSTATE    20
+#define M_REQ_LNF_RXPWRSTATE    0x3U
+#define V_REQ_LNF_RXPWRSTATE(x) ((x) << S_REQ_LNF_RXPWRSTATE)
+#define G_REQ_LNF_RXPWRSTATE(x) (((x) >> S_REQ_LNF_RXPWRSTATE) & M_REQ_LNF_RXPWRSTATE)
+
+#define S_REQ_LNE_RXSTATEDONE    19
+#define V_REQ_LNE_RXSTATEDONE(x) ((x) << S_REQ_LNE_RXSTATEDONE)
+#define F_REQ_LNE_RXSTATEDONE    V_REQ_LNE_RXSTATEDONE(1U)
+
+#define S_REQ_LNE_RXSTATEREQ    18
+#define V_REQ_LNE_RXSTATEREQ(x) ((x) << S_REQ_LNE_RXSTATEREQ)
+#define F_REQ_LNE_RXSTATEREQ    V_REQ_LNE_RXSTATEREQ(1U)
+
+#define S_REQ_LNE_RXPWRSTATE    16
+#define M_REQ_LNE_RXPWRSTATE    0x3U
+#define V_REQ_LNE_RXPWRSTATE(x) ((x) << S_REQ_LNE_RXPWRSTATE)
+#define G_REQ_LNE_RXPWRSTATE(x) (((x) >> S_REQ_LNE_RXPWRSTATE) & M_REQ_LNE_RXPWRSTATE)
+
+#define S_REQ_LND_RXSTATEDONE    15
+#define V_REQ_LND_RXSTATEDONE(x) ((x) << S_REQ_LND_RXSTATEDONE)
+#define F_REQ_LND_RXSTATEDONE    V_REQ_LND_RXSTATEDONE(1U)
+
+#define S_REQ_LND_RXSTATEREQ    14
+#define V_REQ_LND_RXSTATEREQ(x) ((x) << S_REQ_LND_RXSTATEREQ)
+#define F_REQ_LND_RXSTATEREQ    V_REQ_LND_RXSTATEREQ(1U)
+
+#define S_REQ_LND_RXPWRSTATE    12
+#define M_REQ_LND_RXPWRSTATE    0x3U
+#define V_REQ_LND_RXPWRSTATE(x) ((x) << S_REQ_LND_RXPWRSTATE)
+#define G_REQ_LND_RXPWRSTATE(x) (((x) >> S_REQ_LND_RXPWRSTATE) & M_REQ_LND_RXPWRSTATE)
+
+#define S_REQ_LNC_RXSTATEDONE    11
+#define V_REQ_LNC_RXSTATEDONE(x) ((x) << S_REQ_LNC_RXSTATEDONE)
+#define F_REQ_LNC_RXSTATEDONE    V_REQ_LNC_RXSTATEDONE(1U)
+
+#define S_REQ_LNC_RXSTATEREQ    10
+#define V_REQ_LNC_RXSTATEREQ(x) ((x) << S_REQ_LNC_RXSTATEREQ)
+#define F_REQ_LNC_RXSTATEREQ    V_REQ_LNC_RXSTATEREQ(1U)
+
+#define S_REQ_LNC_RXPWRSTATE    8
+#define M_REQ_LNC_RXPWRSTATE    0x3U
+#define V_REQ_LNC_RXPWRSTATE(x) ((x) << S_REQ_LNC_RXPWRSTATE)
+#define G_REQ_LNC_RXPWRSTATE(x) (((x) >> S_REQ_LNC_RXPWRSTATE) & M_REQ_LNC_RXPWRSTATE)
+
+#define S_REQ_LNB_RXSTATEDONE    7
+#define V_REQ_LNB_RXSTATEDONE(x) ((x) << S_REQ_LNB_RXSTATEDONE)
+#define F_REQ_LNB_RXSTATEDONE    V_REQ_LNB_RXSTATEDONE(1U)
+
+#define S_REQ_LNB_RXSTATEREQ    6
+#define V_REQ_LNB_RXSTATEREQ(x) ((x) << S_REQ_LNB_RXSTATEREQ)
+#define F_REQ_LNB_RXSTATEREQ    V_REQ_LNB_RXSTATEREQ(1U)
+
+#define S_REQ_LNB_RXPWRSTATE    4
+#define M_REQ_LNB_RXPWRSTATE    0x3U
+#define V_REQ_LNB_RXPWRSTATE(x) ((x) << S_REQ_LNB_RXPWRSTATE)
+#define G_REQ_LNB_RXPWRSTATE(x) (((x) >> S_REQ_LNB_RXPWRSTATE) & M_REQ_LNB_RXPWRSTATE)
+
+#define S_REQ_LNA_RXSTATEDONE    3
+#define V_REQ_LNA_RXSTATEDONE(x) ((x) << S_REQ_LNA_RXSTATEDONE)
+#define F_REQ_LNA_RXSTATEDONE    V_REQ_LNA_RXSTATEDONE(1U)
+
+#define S_REQ_LNA_RXSTATEREQ    2
+#define V_REQ_LNA_RXSTATEREQ(x) ((x) << S_REQ_LNA_RXSTATEREQ)
+#define F_REQ_LNA_RXSTATEREQ    V_REQ_LNA_RXSTATEREQ(1U)
+
+#define S_REQ_LNA_RXPWRSTATE    0
+#define M_REQ_LNA_RXPWRSTATE    0x3U
+#define V_REQ_LNA_RXPWRSTATE(x) ((x) << S_REQ_LNA_RXPWRSTATE)
+#define G_REQ_LNA_RXPWRSTATE(x) (((x) >> S_REQ_LNA_RXPWRSTATE) & M_REQ_LNA_RXPWRSTATE)
+
 #define A_PCIE_PHY_CURRXPWR 0x5ba4
+
+#define S_T5_LNH_RXPWRSTATE    28
+#define M_T5_LNH_RXPWRSTATE    0x7U
+#define V_T5_LNH_RXPWRSTATE(x) ((x) << S_T5_LNH_RXPWRSTATE)
+#define G_T5_LNH_RXPWRSTATE(x) (((x) >> S_T5_LNH_RXPWRSTATE) & M_T5_LNH_RXPWRSTATE)
+
+#define S_T5_LNG_RXPWRSTATE    24
+#define M_T5_LNG_RXPWRSTATE    0x7U
+#define V_T5_LNG_RXPWRSTATE(x) ((x) << S_T5_LNG_RXPWRSTATE)
+#define G_T5_LNG_RXPWRSTATE(x) (((x) >> S_T5_LNG_RXPWRSTATE) & M_T5_LNG_RXPWRSTATE)
+
+#define S_T5_LNF_RXPWRSTATE    20
+#define M_T5_LNF_RXPWRSTATE    0x7U
+#define V_T5_LNF_RXPWRSTATE(x) ((x) << S_T5_LNF_RXPWRSTATE)
+#define G_T5_LNF_RXPWRSTATE(x) (((x) >> S_T5_LNF_RXPWRSTATE) & M_T5_LNF_RXPWRSTATE)
+
+#define S_T5_LNE_RXPWRSTATE    16
+#define M_T5_LNE_RXPWRSTATE    0x7U
+#define V_T5_LNE_RXPWRSTATE(x) ((x) << S_T5_LNE_RXPWRSTATE)
+#define G_T5_LNE_RXPWRSTATE(x) (((x) >> S_T5_LNE_RXPWRSTATE) & M_T5_LNE_RXPWRSTATE)
+
+#define S_T5_LND_RXPWRSTATE    12
+#define M_T5_LND_RXPWRSTATE    0x7U
+#define V_T5_LND_RXPWRSTATE(x) ((x) << S_T5_LND_RXPWRSTATE)
+#define G_T5_LND_RXPWRSTATE(x) (((x) >> S_T5_LND_RXPWRSTATE) & M_T5_LND_RXPWRSTATE)
+
+#define S_T5_LNC_RXPWRSTATE    8
+#define M_T5_LNC_RXPWRSTATE    0x7U
+#define V_T5_LNC_RXPWRSTATE(x) ((x) << S_T5_LNC_RXPWRSTATE)
+#define G_T5_LNC_RXPWRSTATE(x) (((x) >> S_T5_LNC_RXPWRSTATE) & M_T5_LNC_RXPWRSTATE)
+
+#define S_T5_LNB_RXPWRSTATE    4
+#define M_T5_LNB_RXPWRSTATE    0x7U
+#define V_T5_LNB_RXPWRSTATE(x) ((x) << S_T5_LNB_RXPWRSTATE)
+#define G_T5_LNB_RXPWRSTATE(x) (((x) >> S_T5_LNB_RXPWRSTATE) & M_T5_LNB_RXPWRSTATE)
+
+#define S_T5_LNA_RXPWRSTATE    0
+#define M_T5_LNA_RXPWRSTATE    0x7U
+#define V_T5_LNA_RXPWRSTATE(x) ((x) << S_T5_LNA_RXPWRSTATE)
+#define G_T5_LNA_RXPWRSTATE(x) (((x) >> S_T5_LNA_RXPWRSTATE) & M_T5_LNA_RXPWRSTATE)
+
+#define S_CUR_LNH_RXPWRSTATE    28
+#define M_CUR_LNH_RXPWRSTATE    0x7U
+#define V_CUR_LNH_RXPWRSTATE(x) ((x) << S_CUR_LNH_RXPWRSTATE)
+#define G_CUR_LNH_RXPWRSTATE(x) (((x) >> S_CUR_LNH_RXPWRSTATE) & M_CUR_LNH_RXPWRSTATE)
+
+#define S_CUR_LNG_RXPWRSTATE    24
+#define M_CUR_LNG_RXPWRSTATE    0x7U
+#define V_CUR_LNG_RXPWRSTATE(x) ((x) << S_CUR_LNG_RXPWRSTATE)
+#define G_CUR_LNG_RXPWRSTATE(x) (((x) >> S_CUR_LNG_RXPWRSTATE) & M_CUR_LNG_RXPWRSTATE)
+
+#define S_CUR_LNF_RXPWRSTATE    20
+#define M_CUR_LNF_RXPWRSTATE    0x7U
+#define V_CUR_LNF_RXPWRSTATE(x) ((x) << S_CUR_LNF_RXPWRSTATE)
+#define G_CUR_LNF_RXPWRSTATE(x) (((x) >> S_CUR_LNF_RXPWRSTATE) & M_CUR_LNF_RXPWRSTATE)
+
+#define S_CUR_LNE_RXPWRSTATE    16
+#define M_CUR_LNE_RXPWRSTATE    0x7U
+#define V_CUR_LNE_RXPWRSTATE(x) ((x) << S_CUR_LNE_RXPWRSTATE)
+#define G_CUR_LNE_RXPWRSTATE(x) (((x) >> S_CUR_LNE_RXPWRSTATE) & M_CUR_LNE_RXPWRSTATE)
+
+#define S_CUR_LND_RXPWRSTATE    12
+#define M_CUR_LND_RXPWRSTATE    0x7U
+#define V_CUR_LND_RXPWRSTATE(x) ((x) << S_CUR_LND_RXPWRSTATE)
+#define G_CUR_LND_RXPWRSTATE(x) (((x) >> S_CUR_LND_RXPWRSTATE) & M_CUR_LND_RXPWRSTATE)
+
+#define S_CUR_LNC_RXPWRSTATE    8
+#define M_CUR_LNC_RXPWRSTATE    0x7U
+#define V_CUR_LNC_RXPWRSTATE(x) ((x) << S_CUR_LNC_RXPWRSTATE)
+#define G_CUR_LNC_RXPWRSTATE(x) (((x) >> S_CUR_LNC_RXPWRSTATE) & M_CUR_LNC_RXPWRSTATE)
+
+#define S_CUR_LNB_RXPWRSTATE    4
+#define M_CUR_LNB_RXPWRSTATE    0x7U
+#define V_CUR_LNB_RXPWRSTATE(x) ((x) << S_CUR_LNB_RXPWRSTATE)
+#define G_CUR_LNB_RXPWRSTATE(x) (((x) >> S_CUR_LNB_RXPWRSTATE) & M_CUR_LNB_RXPWRSTATE)
+
+#define S_CUR_LNA_RXPWRSTATE    0
+#define M_CUR_LNA_RXPWRSTATE    0x7U
+#define V_CUR_LNA_RXPWRSTATE(x) ((x) << S_CUR_LNA_RXPWRSTATE)
+#define G_CUR_LNA_RXPWRSTATE(x) (((x) >> S_CUR_LNA_RXPWRSTATE) & M_CUR_LNA_RXPWRSTATE)
+
 #define A_PCIE_PHY_GEN3_AE0 0x5ba8
 
 #define S_LND_STAT    28
@@ -7057,6 +8413,11 @@
 #define V_COEFFSTART(x) ((x) << S_COEFFSTART)
 #define F_COEFFSTART    V_COEFFSTART(1U)
 
+#define S_T6_COEFFLANE    8
+#define M_T6_COEFFLANE    0xfU
+#define V_T6_COEFFLANE(x) ((x) << S_T6_COEFFLANE)
+#define G_T6_COEFFLANE(x) (((x) >> S_T6_COEFFLANE) & M_T6_COEFFLANE)
+
 #define A_PCIE_PHY_PRESET_COEFF 0x5bc4
 
 #define S_COEFF    0
@@ -7078,6 +8439,3026 @@
 #define A_PCIE_PHY_INDIR_DATA 0x5bf4
 #define A_PCIE_STATIC_SPARE1 0x5bf8
 #define A_PCIE_STATIC_SPARE2 0x5bfc
+#define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10
+
+#define S_KDB_PF_LEN    24
+#define M_KDB_PF_LEN    0x1fU
+#define V_KDB_PF_LEN(x) ((x) << S_KDB_PF_LEN)
+#define G_KDB_PF_LEN(x) (((x) >> S_KDB_PF_LEN) & M_KDB_PF_LEN)
+
+#define S_KDB_PF_BASEADDR    0
+#define M_KDB_PF_BASEADDR    0xfffffU
+#define V_KDB_PF_BASEADDR(x) ((x) << S_KDB_PF_BASEADDR)
+#define G_KDB_PF_BASEADDR(x) (((x) >> S_KDB_PF_BASEADDR) & M_KDB_PF_BASEADDR)
+
+#define A_PCIE_KDOORBELL_GTS_VF_BASE_LEN 0x5c14
+
+#define S_KDB_VF_LEN    24
+#define M_KDB_VF_LEN    0x1fU
+#define V_KDB_VF_LEN(x) ((x) << S_KDB_VF_LEN)
+#define G_KDB_VF_LEN(x) (((x) >> S_KDB_VF_LEN) & M_KDB_VF_LEN)
+
+#define S_KDB_VF_BASEADDR    0
+#define M_KDB_VF_BASEADDR    0xfffffU
+#define V_KDB_VF_BASEADDR(x) ((x) << S_KDB_VF_BASEADDR)
+#define G_KDB_VF_BASEADDR(x) (((x) >> S_KDB_VF_BASEADDR) & M_KDB_VF_BASEADDR)
+
+#define A_PCIE_KDOORBELL_GTS_VF_OFFSET 0x5c18
+
+#define S_KDB_VF_MODOFST    0
+#define M_KDB_VF_MODOFST    0xfffU
+#define V_KDB_VF_MODOFST(x) ((x) << S_KDB_VF_MODOFST)
+#define G_KDB_VF_MODOFST(x) (((x) >> S_KDB_VF_MODOFST) & M_KDB_VF_MODOFST)
+
+#define A_PCIE_PHY_REQRXPWR1 0x5c1c
+
+#define S_REQ_LNP_RXSTATEDONE    31
+#define V_REQ_LNP_RXSTATEDONE(x) ((x) << S_REQ_LNP_RXSTATEDONE)
+#define F_REQ_LNP_RXSTATEDONE    V_REQ_LNP_RXSTATEDONE(1U)
+
+#define S_REQ_LNP_RXSTATEREQ    30
+#define V_REQ_LNP_RXSTATEREQ(x) ((x) << S_REQ_LNP_RXSTATEREQ)
+#define F_REQ_LNP_RXSTATEREQ    V_REQ_LNP_RXSTATEREQ(1U)
+
+#define S_REQ_LNP_RXPWRSTATE    28
+#define M_REQ_LNP_RXPWRSTATE    0x3U
+#define V_REQ_LNP_RXPWRSTATE(x) ((x) << S_REQ_LNP_RXPWRSTATE)
+#define G_REQ_LNP_RXPWRSTATE(x) (((x) >> S_REQ_LNP_RXPWRSTATE) & M_REQ_LNP_RXPWRSTATE)
+
+#define S_REQ_LNO_RXSTATEDONE    27
+#define V_REQ_LNO_RXSTATEDONE(x) ((x) << S_REQ_LNO_RXSTATEDONE)
+#define F_REQ_LNO_RXSTATEDONE    V_REQ_LNO_RXSTATEDONE(1U)
+
+#define S_REQ_LNO_RXSTATEREQ    26
+#define V_REQ_LNO_RXSTATEREQ(x) ((x) << S_REQ_LNO_RXSTATEREQ)
+#define F_REQ_LNO_RXSTATEREQ    V_REQ_LNO_RXSTATEREQ(1U)
+
+#define S_REQ_LNO_RXPWRSTATE    24
+#define M_REQ_LNO_RXPWRSTATE    0x3U
+#define V_REQ_LNO_RXPWRSTATE(x) ((x) << S_REQ_LNO_RXPWRSTATE)
+#define G_REQ_LNO_RXPWRSTATE(x) (((x) >> S_REQ_LNO_RXPWRSTATE) & M_REQ_LNO_RXPWRSTATE)
+
+#define S_REQ_LNN_RXSTATEDONE    23
+#define V_REQ_LNN_RXSTATEDONE(x) ((x) << S_REQ_LNN_RXSTATEDONE)
+#define F_REQ_LNN_RXSTATEDONE    V_REQ_LNN_RXSTATEDONE(1U)
+
+#define S_REQ_LNN_RXSTATEREQ    22
+#define V_REQ_LNN_RXSTATEREQ(x) ((x) << S_REQ_LNN_RXSTATEREQ)
+#define F_REQ_LNN_RXSTATEREQ    V_REQ_LNN_RXSTATEREQ(1U)
+
+#define S_REQ_LNN_RXPWRSTATE    20
+#define M_REQ_LNN_RXPWRSTATE    0x3U
+#define V_REQ_LNN_RXPWRSTATE(x) ((x) << S_REQ_LNN_RXPWRSTATE)
+#define G_REQ_LNN_RXPWRSTATE(x) (((x) >> S_REQ_LNN_RXPWRSTATE) & M_REQ_LNN_RXPWRSTATE)
+
+#define S_REQ_LNM_RXSTATEDONE    19
+#define V_REQ_LNM_RXSTATEDONE(x) ((x) << S_REQ_LNM_RXSTATEDONE)
+#define F_REQ_LNM_RXSTATEDONE    V_REQ_LNM_RXSTATEDONE(1U)
+
+#define S_REQ_LNM_RXSTATEREQ    18
+#define V_REQ_LNM_RXSTATEREQ(x) ((x) << S_REQ_LNM_RXSTATEREQ)
+#define F_REQ_LNM_RXSTATEREQ    V_REQ_LNM_RXSTATEREQ(1U)
+
+#define S_REQ_LNM_RXPWRSTATE    16
+#define M_REQ_LNM_RXPWRSTATE    0x3U
+#define V_REQ_LNM_RXPWRSTATE(x) ((x) << S_REQ_LNM_RXPWRSTATE)
+#define G_REQ_LNM_RXPWRSTATE(x) (((x) >> S_REQ_LNM_RXPWRSTATE) & M_REQ_LNM_RXPWRSTATE)
+
+#define S_REQ_LNL_RXSTATEDONE    15
+#define V_REQ_LNL_RXSTATEDONE(x) ((x) << S_REQ_LNL_RXSTATEDONE)
+#define F_REQ_LNL_RXSTATEDONE    V_REQ_LNL_RXSTATEDONE(1U)
+
+#define S_REQ_LNL_RXSTATEREQ    14
+#define V_REQ_LNL_RXSTATEREQ(x) ((x) << S_REQ_LNL_RXSTATEREQ)
+#define F_REQ_LNL_RXSTATEREQ    V_REQ_LNL_RXSTATEREQ(1U)
+
+#define S_REQ_LNL_RXPWRSTATE    12
+#define M_REQ_LNL_RXPWRSTATE    0x3U
+#define V_REQ_LNL_RXPWRSTATE(x) ((x) << S_REQ_LNL_RXPWRSTATE)
+#define G_REQ_LNL_RXPWRSTATE(x) (((x) >> S_REQ_LNL_RXPWRSTATE) & M_REQ_LNL_RXPWRSTATE)
+
+#define S_REQ_LNK_RXSTATEDONE    11
+#define V_REQ_LNK_RXSTATEDONE(x) ((x) << S_REQ_LNK_RXSTATEDONE)
+#define F_REQ_LNK_RXSTATEDONE    V_REQ_LNK_RXSTATEDONE(1U)
+
+#define S_REQ_LNK_RXSTATEREQ    10
+#define V_REQ_LNK_RXSTATEREQ(x) ((x) << S_REQ_LNK_RXSTATEREQ)
+#define F_REQ_LNK_RXSTATEREQ    V_REQ_LNK_RXSTATEREQ(1U)
+
+#define S_REQ_LNK_RXPWRSTATE    8
+#define M_REQ_LNK_RXPWRSTATE    0x3U
+#define V_REQ_LNK_RXPWRSTATE(x) ((x) << S_REQ_LNK_RXPWRSTATE)
+#define G_REQ_LNK_RXPWRSTATE(x) (((x) >> S_REQ_LNK_RXPWRSTATE) & M_REQ_LNK_RXPWRSTATE)
+
+#define S_REQ_LNJ_RXSTATEDONE    7
+#define V_REQ_LNJ_RXSTATEDONE(x) ((x) << S_REQ_LNJ_RXSTATEDONE)
+#define F_REQ_LNJ_RXSTATEDONE    V_REQ_LNJ_RXSTATEDONE(1U)
+
+#define S_REQ_LNJ_RXSTATEREQ    6
+#define V_REQ_LNJ_RXSTATEREQ(x) ((x) << S_REQ_LNJ_RXSTATEREQ)
+#define F_REQ_LNJ_RXSTATEREQ    V_REQ_LNJ_RXSTATEREQ(1U)
+
+#define S_REQ_LNJ_RXPWRSTATE    4
+#define M_REQ_LNJ_RXPWRSTATE    0x3U
+#define V_REQ_LNJ_RXPWRSTATE(x) ((x) << S_REQ_LNJ_RXPWRSTATE)
+#define G_REQ_LNJ_RXPWRSTATE(x) (((x) >> S_REQ_LNJ_RXPWRSTATE) & M_REQ_LNJ_RXPWRSTATE)
+
+#define S_REQ_LNI_RXSTATEDONE    3
+#define V_REQ_LNI_RXSTATEDONE(x) ((x) << S_REQ_LNI_RXSTATEDONE)
+#define F_REQ_LNI_RXSTATEDONE    V_REQ_LNI_RXSTATEDONE(1U)
+
+#define S_REQ_LNI_RXSTATEREQ    2
+#define V_REQ_LNI_RXSTATEREQ(x) ((x) << S_REQ_LNI_RXSTATEREQ)
+#define F_REQ_LNI_RXSTATEREQ    V_REQ_LNI_RXSTATEREQ(1U)
+
+#define S_REQ_LNI_RXPWRSTATE    0
+#define M_REQ_LNI_RXPWRSTATE    0x3U
+#define V_REQ_LNI_RXPWRSTATE(x) ((x) << S_REQ_LNI_RXPWRSTATE)
+#define G_REQ_LNI_RXPWRSTATE(x) (((x) >> S_REQ_LNI_RXPWRSTATE) & M_REQ_LNI_RXPWRSTATE)
+
+#define A_PCIE_PHY_CURRXPWR1 0x5c20
+
+#define S_CUR_LNP_RXPWRSTATE    28
+#define M_CUR_LNP_RXPWRSTATE    0x7U
+#define V_CUR_LNP_RXPWRSTATE(x) ((x) << S_CUR_LNP_RXPWRSTATE)
+#define G_CUR_LNP_RXPWRSTATE(x) (((x) >> S_CUR_LNP_RXPWRSTATE) & M_CUR_LNP_RXPWRSTATE)
+
+#define S_CUR_LNO_RXPWRSTATE    24
+#define M_CUR_LNO_RXPWRSTATE    0x7U
+#define V_CUR_LNO_RXPWRSTATE(x) ((x) << S_CUR_LNO_RXPWRSTATE)
+#define G_CUR_LNO_RXPWRSTATE(x) (((x) >> S_CUR_LNO_RXPWRSTATE) & M_CUR_LNO_RXPWRSTATE)
+
+#define S_CUR_LNN_RXPWRSTATE    20
+#define M_CUR_LNN_RXPWRSTATE    0x7U
+#define V_CUR_LNN_RXPWRSTATE(x) ((x) << S_CUR_LNN_RXPWRSTATE)
+#define G_CUR_LNN_RXPWRSTATE(x) (((x) >> S_CUR_LNN_RXPWRSTATE) & M_CUR_LNN_RXPWRSTATE)
+
+#define S_CUR_LNM_RXPWRSTATE    16
+#define M_CUR_LNM_RXPWRSTATE    0x7U
+#define V_CUR_LNM_RXPWRSTATE(x) ((x) << S_CUR_LNM_RXPWRSTATE)
+#define G_CUR_LNM_RXPWRSTATE(x) (((x) >> S_CUR_LNM_RXPWRSTATE) & M_CUR_LNM_RXPWRSTATE)
+
+#define S_CUR_LNL_RXPWRSTATE    12
+#define M_CUR_LNL_RXPWRSTATE    0x7U
+#define V_CUR_LNL_RXPWRSTATE(x) ((x) << S_CUR_LNL_RXPWRSTATE)
+#define G_CUR_LNL_RXPWRSTATE(x) (((x) >> S_CUR_LNL_RXPWRSTATE) & M_CUR_LNL_RXPWRSTATE)
+
+#define S_CUR_LNK_RXPWRSTATE    8
+#define M_CUR_LNK_RXPWRSTATE    0x7U
+#define V_CUR_LNK_RXPWRSTATE(x) ((x) << S_CUR_LNK_RXPWRSTATE)
+#define G_CUR_LNK_RXPWRSTATE(x) (((x) >> S_CUR_LNK_RXPWRSTATE) & M_CUR_LNK_RXPWRSTATE)
+
+#define S_CUR_LNJ_RXPWRSTATE    4
+#define M_CUR_LNJ_RXPWRSTATE    0x7U
+#define V_CUR_LNJ_RXPWRSTATE(x) ((x) << S_CUR_LNJ_RXPWRSTATE)
+#define G_CUR_LNJ_RXPWRSTATE(x) (((x) >> S_CUR_LNJ_RXPWRSTATE) & M_CUR_LNJ_RXPWRSTATE)
+
+#define S_CUR_LNI_RXPWRSTATE    0
+#define M_CUR_LNI_RXPWRSTATE    0x7U
+#define V_CUR_LNI_RXPWRSTATE(x) ((x) << S_CUR_LNI_RXPWRSTATE)
+#define G_CUR_LNI_RXPWRSTATE(x) (((x) >> S_CUR_LNI_RXPWRSTATE) & M_CUR_LNI_RXPWRSTATE)
+
+#define A_PCIE_PHY_GEN3_AE2 0x5c24
+
+#define S_LNL_STAT    28
+#define M_LNL_STAT    0x7U
+#define V_LNL_STAT(x) ((x) << S_LNL_STAT)
+#define G_LNL_STAT(x) (((x) >> S_LNL_STAT) & M_LNL_STAT)
+
+#define S_LNL_CMD    24
+#define M_LNL_CMD    0x7U
+#define V_LNL_CMD(x) ((x) << S_LNL_CMD)
+#define G_LNL_CMD(x) (((x) >> S_LNL_CMD) & M_LNL_CMD)
+
+#define S_LNK_STAT    20
+#define M_LNK_STAT    0x7U
+#define V_LNK_STAT(x) ((x) << S_LNK_STAT)
+#define G_LNK_STAT(x) (((x) >> S_LNK_STAT) & M_LNK_STAT)
+
+#define S_LNK_CMD    16
+#define M_LNK_CMD    0x7U
+#define V_LNK_CMD(x) ((x) << S_LNK_CMD)
+#define G_LNK_CMD(x) (((x) >> S_LNK_CMD) & M_LNK_CMD)
+
+#define S_LNJ_STAT    12
+#define M_LNJ_STAT    0x7U
+#define V_LNJ_STAT(x) ((x) << S_LNJ_STAT)
+#define G_LNJ_STAT(x) (((x) >> S_LNJ_STAT) & M_LNJ_STAT)
+
+#define S_LNJ_CMD    8
+#define M_LNJ_CMD    0x7U
+#define V_LNJ_CMD(x) ((x) << S_LNJ_CMD)
+#define G_LNJ_CMD(x) (((x) >> S_LNJ_CMD) & M_LNJ_CMD)
+
+#define S_LNI_STAT    4
+#define M_LNI_STAT    0x7U
+#define V_LNI_STAT(x) ((x) << S_LNI_STAT)
+#define G_LNI_STAT(x) (((x) >> S_LNI_STAT) & M_LNI_STAT)
+
+#define S_LNI_CMD    0
+#define M_LNI_CMD    0x7U
+#define V_LNI_CMD(x) ((x) << S_LNI_CMD)
+#define G_LNI_CMD(x) (((x) >> S_LNI_CMD) & M_LNI_CMD)
+
+#define A_PCIE_PHY_GEN3_AE3 0x5c28
+
+#define S_LNP_STAT    28
+#define M_LNP_STAT    0x7U
+#define V_LNP_STAT(x) ((x) << S_LNP_STAT)
+#define G_LNP_STAT(x) (((x) >> S_LNP_STAT) & M_LNP_STAT)
+
+#define S_LNP_CMD    24
+#define M_LNP_CMD    0x7U
+#define V_LNP_CMD(x) ((x) << S_LNP_CMD)
+#define G_LNP_CMD(x) (((x) >> S_LNP_CMD) & M_LNP_CMD)
+
+#define S_LNO_STAT    20
+#define M_LNO_STAT    0x7U
+#define V_LNO_STAT(x) ((x) << S_LNO_STAT)
+#define G_LNO_STAT(x) (((x) >> S_LNO_STAT) & M_LNO_STAT)
+
+#define S_LNO_CMD    16
+#define M_LNO_CMD    0x7U
+#define V_LNO_CMD(x) ((x) << S_LNO_CMD)
+#define G_LNO_CMD(x) (((x) >> S_LNO_CMD) & M_LNO_CMD)
+
+#define S_LNN_STAT    12
+#define M_LNN_STAT    0x7U
+#define V_LNN_STAT(x) ((x) << S_LNN_STAT)
+#define G_LNN_STAT(x) (((x) >> S_LNN_STAT) & M_LNN_STAT)
+
+#define S_LNN_CMD    8
+#define M_LNN_CMD    0x7U
+#define V_LNN_CMD(x) ((x) << S_LNN_CMD)
+#define G_LNN_CMD(x) (((x) >> S_LNN_CMD) & M_LNN_CMD)
+
+#define S_LNM_STAT    4
+#define M_LNM_STAT    0x7U
+#define V_LNM_STAT(x) ((x) << S_LNM_STAT)
+#define G_LNM_STAT(x) (((x) >> S_LNM_STAT) & M_LNM_STAT)
+
+#define S_LNM_CMD    0
+#define M_LNM_CMD    0x7U
+#define V_LNM_CMD(x) ((x) << S_LNM_CMD)
+#define G_LNM_CMD(x) (((x) >> S_LNM_CMD) & M_LNM_CMD)
+
+#define A_PCIE_PHY_FS_LF4 0x5c2c
+
+#define S_LANE9LF    24
+#define M_LANE9LF    0x3fU
+#define V_LANE9LF(x) ((x) << S_LANE9LF)
+#define G_LANE9LF(x) (((x) >> S_LANE9LF) & M_LANE9LF)
+
+#define S_LANE9FS    16
+#define M_LANE9FS    0x3fU
+#define V_LANE9FS(x) ((x) << S_LANE9FS)
+#define G_LANE9FS(x) (((x) >> S_LANE9FS) & M_LANE9FS)
+
+#define S_LANE8LF    8
+#define M_LANE8LF    0x3fU
+#define V_LANE8LF(x) ((x) << S_LANE8LF)
+#define G_LANE8LF(x) (((x) >> S_LANE8LF) & M_LANE8LF)
+
+#define S_LANE8FS    0
+#define M_LANE8FS    0x3fU
+#define V_LANE8FS(x) ((x) << S_LANE8FS)
+#define G_LANE8FS(x) (((x) >> S_LANE8FS) & M_LANE8FS)
+
+#define A_PCIE_PHY_FS_LF5 0x5c30
+
+#define S_LANE11LF    24
+#define M_LANE11LF    0x3fU
+#define V_LANE11LF(x) ((x) << S_LANE11LF)
+#define G_LANE11LF(x) (((x) >> S_LANE11LF) & M_LANE11LF)
+
+#define S_LANE11FS    16
+#define M_LANE11FS    0x3fU
+#define V_LANE11FS(x) ((x) << S_LANE11FS)
+#define G_LANE11FS(x) (((x) >> S_LANE11FS) & M_LANE11FS)
+
+#define S_LANE10LF    8
+#define M_LANE10LF    0x3fU
+#define V_LANE10LF(x) ((x) << S_LANE10LF)
+#define G_LANE10LF(x) (((x) >> S_LANE10LF) & M_LANE10LF)
+
+#define S_LANE10FS    0
+#define M_LANE10FS    0x3fU
+#define V_LANE10FS(x) ((x) << S_LANE10FS)
+#define G_LANE10FS(x) (((x) >> S_LANE10FS) & M_LANE10FS)
+
+#define A_PCIE_PHY_FS_LF6 0x5c34
+
+#define S_LANE13LF    24
+#define M_LANE13LF    0x3fU
+#define V_LANE13LF(x) ((x) << S_LANE13LF)
+#define G_LANE13LF(x) (((x) >> S_LANE13LF) & M_LANE13LF)
+
+#define S_LANE13FS    16
+#define M_LANE13FS    0x3fU
+#define V_LANE13FS(x) ((x) << S_LANE13FS)
+#define G_LANE13FS(x) (((x) >> S_LANE13FS) & M_LANE13FS)
+
+#define S_LANE12LF    8
+#define M_LANE12LF    0x3fU
+#define V_LANE12LF(x) ((x) << S_LANE12LF)
+#define G_LANE12LF(x) (((x) >> S_LANE12LF) & M_LANE12LF)
+
+#define S_LANE12FS    0
+#define M_LANE12FS    0x3fU
+#define V_LANE12FS(x) ((x) << S_LANE12FS)
+#define G_LANE12FS(x) (((x) >> S_LANE12FS) & M_LANE12FS)
+
+#define A_PCIE_PHY_FS_LF7 0x5c38
+
+#define S_LANE15LF    24
+#define M_LANE15LF    0x3fU
+#define V_LANE15LF(x) ((x) << S_LANE15LF)
+#define G_LANE15LF(x) (((x) >> S_LANE15LF) & M_LANE15LF)
+
+#define S_LANE15FS    16
+#define M_LANE15FS    0x3fU
+#define V_LANE15FS(x) ((x) << S_LANE15FS)
+#define G_LANE15FS(x) (((x) >> S_LANE15FS) & M_LANE15FS)
+
+#define S_LANE14LF    8
+#define M_LANE14LF    0x3fU
+#define V_LANE14LF(x) ((x) << S_LANE14LF)
+#define G_LANE14LF(x) (((x) >> S_LANE14LF) & M_LANE14LF)
+
+#define S_LANE14FS    0
+#define M_LANE14FS    0x3fU
+#define V_LANE14FS(x) ((x) << S_LANE14FS)
+#define G_LANE14FS(x) (((x) >> S_LANE14FS) & M_LANE14FS)
+
+#define A_PCIE_MULTI_PHY_INDIR_REQ 0x5c3c
+
+#define S_PHY_REG_ENABLE    31
+#define V_PHY_REG_ENABLE(x) ((x) << S_PHY_REG_ENABLE)
+#define F_PHY_REG_ENABLE    V_PHY_REG_ENABLE(1U)
+
+#define S_PHY_REG_SELECT    22
+#define M_PHY_REG_SELECT    0x3U
+#define V_PHY_REG_SELECT(x) ((x) << S_PHY_REG_SELECT)
+#define G_PHY_REG_SELECT(x) (((x) >> S_PHY_REG_SELECT) & M_PHY_REG_SELECT)
+
+#define S_PHY_REG_REGADDR    0
+#define M_PHY_REG_REGADDR    0xffffU
+#define V_PHY_REG_REGADDR(x) ((x) << S_PHY_REG_REGADDR)
+#define G_PHY_REG_REGADDR(x) (((x) >> S_PHY_REG_REGADDR) & M_PHY_REG_REGADDR)
+
+#define A_PCIE_MULTI_PHY_INDIR_DATA 0x5c40
+
+#define S_PHY_REG_DATA    0
+#define M_PHY_REG_DATA    0xffffU
+#define V_PHY_REG_DATA(x) ((x) << S_PHY_REG_DATA)
+#define G_PHY_REG_DATA(x) (((x) >> S_PHY_REG_DATA) & M_PHY_REG_DATA)
+
+#define A_PCIE_VF_INT_INDIR_REQ 0x5c44
+
+#define S_ENABLE_VF    24
+#define V_ENABLE_VF(x) ((x) << S_ENABLE_VF)
+#define F_ENABLE_VF    V_ENABLE_VF(1U)
+
+#define S_AI_VF    23
+#define V_AI_VF(x) ((x) << S_AI_VF)
+#define F_AI_VF    V_AI_VF(1U)
+
+#define S_VFID_PCIE    0
+#define M_VFID_PCIE    0x3ffU
+#define V_VFID_PCIE(x) ((x) << S_VFID_PCIE)
+#define G_VFID_PCIE(x) (((x) >> S_VFID_PCIE) & M_VFID_PCIE)
+
+#define A_PCIE_VF_INT_INDIR_DATA 0x5c48
+#define A_PCIE_VF_256_INT_CFG2 0x5c4c
+#define A_PCIE_VF_MSI_EN_4 0x5e50
+#define A_PCIE_VF_MSI_EN_5 0x5e54
+#define A_PCIE_VF_MSI_EN_6 0x5e58
+#define A_PCIE_VF_MSI_EN_7 0x5e5c
+#define A_PCIE_VF_MSIX_EN_4 0x5e60
+#define A_PCIE_VF_MSIX_EN_5 0x5e64
+#define A_PCIE_VF_MSIX_EN_6 0x5e68
+#define A_PCIE_VF_MSIX_EN_7 0x5e6c
+#define A_PCIE_FLR_VF4_STATUS 0x5e70
+#define A_PCIE_FLR_VF5_STATUS 0x5e74
+#define A_PCIE_FLR_VF6_STATUS 0x5e78
+#define A_PCIE_FLR_VF7_STATUS 0x5e7c
+#define A_T6_PCIE_BUS_MST_STAT_4 0x5e80
+#define A_T6_PCIE_BUS_MST_STAT_5 0x5e84
+#define A_T6_PCIE_BUS_MST_STAT_6 0x5e88
+#define A_T6_PCIE_BUS_MST_STAT_7 0x5e8c
+#define A_PCIE_BUS_MST_STAT_8 0x5e90
+
+#define S_BUSMST_263_256    0
+#define M_BUSMST_263_256    0xffU
+#define V_BUSMST_263_256(x) ((x) << S_BUSMST_263_256)
+#define G_BUSMST_263_256(x) (((x) >> S_BUSMST_263_256) & M_BUSMST_263_256)
+
+#define A_PCIE_TGT_SKID_FIFO 0x5e94
+
+#define S_HDRFREECNT    16
+#define M_HDRFREECNT    0xfffU
+#define V_HDRFREECNT(x) ((x) << S_HDRFREECNT)
+#define G_HDRFREECNT(x) (((x) >> S_HDRFREECNT) & M_HDRFREECNT)
+
+#define S_DATAFREECNT    0
+#define M_DATAFREECNT    0xfffU
+#define V_DATAFREECNT(x) ((x) << S_DATAFREECNT)
+#define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT)
+
+#define A_T6_PCIE_RSP_ERR_STAT_4 0x5ea0
+#define A_T6_PCIE_RSP_ERR_STAT_5 0x5ea4
+#define A_T6_PCIE_RSP_ERR_STAT_6 0x5ea8
+#define A_T6_PCIE_RSP_ERR_STAT_7 0x5eac
+#define A_PCIE_RSP_ERR_STAT_8 0x5eb0
+
+#define S_RSPERR_263_256    0
+#define M_RSPERR_263_256    0xffU
+#define V_RSPERR_263_256(x) ((x) << S_RSPERR_263_256)
+#define G_RSPERR_263_256(x) (((x) >> S_RSPERR_263_256) & M_RSPERR_263_256)
+
+#define A_PCIE_PHY_STAT1 0x5ec0
+
+#define S_PHY0_RTUNE_ACK    31
+#define V_PHY0_RTUNE_ACK(x) ((x) << S_PHY0_RTUNE_ACK)
+#define F_PHY0_RTUNE_ACK    V_PHY0_RTUNE_ACK(1U)
+
+#define S_PHY1_RTUNE_ACK    30
+#define V_PHY1_RTUNE_ACK(x) ((x) << S_PHY1_RTUNE_ACK)
+#define F_PHY1_RTUNE_ACK    V_PHY1_RTUNE_ACK(1U)
+
+#define A_PCIE_PHY_CTRL1 0x5ec4
+
+#define S_PHY0_RTUNE_REQ    31
+#define V_PHY0_RTUNE_REQ(x) ((x) << S_PHY0_RTUNE_REQ)
+#define F_PHY0_RTUNE_REQ    V_PHY0_RTUNE_REQ(1U)
+
+#define S_PHY1_RTUNE_REQ    30
+#define V_PHY1_RTUNE_REQ(x) ((x) << S_PHY1_RTUNE_REQ)
+#define F_PHY1_RTUNE_REQ    V_PHY1_RTUNE_REQ(1U)
+
+#define S_TXDEEMPH_GEN1    16
+#define M_TXDEEMPH_GEN1    0xffU
+#define V_TXDEEMPH_GEN1(x) ((x) << S_TXDEEMPH_GEN1)
+#define G_TXDEEMPH_GEN1(x) (((x) >> S_TXDEEMPH_GEN1) & M_TXDEEMPH_GEN1)
+
+#define S_TXDEEMPH_GEN2_3P5DB    8
+#define M_TXDEEMPH_GEN2_3P5DB    0xffU
+#define V_TXDEEMPH_GEN2_3P5DB(x) ((x) << S_TXDEEMPH_GEN2_3P5DB)
+#define G_TXDEEMPH_GEN2_3P5DB(x) (((x) >> S_TXDEEMPH_GEN2_3P5DB) & M_TXDEEMPH_GEN2_3P5DB)
+
+#define S_TXDEEMPH_GEN2_6DB    0
+#define M_TXDEEMPH_GEN2_6DB    0xffU
+#define V_TXDEEMPH_GEN2_6DB(x) ((x) << S_TXDEEMPH_GEN2_6DB)
+#define G_TXDEEMPH_GEN2_6DB(x) (((x) >> S_TXDEEMPH_GEN2_6DB) & M_TXDEEMPH_GEN2_6DB)
+
+#define A_PCIE_PCIE_SPARE0 0x5ec8
+#define A_PCIE_RESET_STAT 0x5ecc
+
+#define S_PON_RST_STATE_FLAG    11
+#define V_PON_RST_STATE_FLAG(x) ((x) << S_PON_RST_STATE_FLAG)
+#define F_PON_RST_STATE_FLAG    V_PON_RST_STATE_FLAG(1U)
+
+#define S_BUS_RST_STATE_FLAG    10
+#define V_BUS_RST_STATE_FLAG(x) ((x) << S_BUS_RST_STATE_FLAG)
+#define F_BUS_RST_STATE_FLAG    V_BUS_RST_STATE_FLAG(1U)
+
+#define S_DL_DOWN_PCIECRST_MODE0_STATE_FLAG    9
+#define V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE0_STATE_FLAG)
+#define F_DL_DOWN_PCIECRST_MODE0_STATE_FLAG    V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(1U)
+
+#define S_DL_DOWN_PCIECRST_MODE1_STATE_FLAG    8
+#define V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE1_STATE_FLAG)
+#define F_DL_DOWN_PCIECRST_MODE1_STATE_FLAG    V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(1U)
+
+#define S_PCIE_WARM_RST_MODE0_STATE_FLAG    7
+#define V_PCIE_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE0_STATE_FLAG)
+#define F_PCIE_WARM_RST_MODE0_STATE_FLAG    V_PCIE_WARM_RST_MODE0_STATE_FLAG(1U)
+
+#define S_PCIE_WARM_RST_MODE1_STATE_FLAG    6
+#define V_PCIE_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE1_STATE_FLAG)
+#define F_PCIE_WARM_RST_MODE1_STATE_FLAG    V_PCIE_WARM_RST_MODE1_STATE_FLAG(1U)
+
+#define S_PIO_WARM_RST_MODE0_STATE_FLAG    5
+#define V_PIO_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE0_STATE_FLAG)
+#define F_PIO_WARM_RST_MODE0_STATE_FLAG    V_PIO_WARM_RST_MODE0_STATE_FLAG(1U)
+
+#define S_PIO_WARM_RST_MODE1_STATE_FLAG    4
+#define V_PIO_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE1_STATE_FLAG)
+#define F_PIO_WARM_RST_MODE1_STATE_FLAG    V_PIO_WARM_RST_MODE1_STATE_FLAG(1U)
+
+#define S_LASTRESETSTATE    0
+#define M_LASTRESETSTATE    0x7U
+#define V_LASTRESETSTATE(x) ((x) << S_LASTRESETSTATE)
+#define G_LASTRESETSTATE(x) (((x) >> S_LASTRESETSTATE) & M_LASTRESETSTATE)
+
+#define A_PCIE_FUNC_DSTATE 0x5ed0
+
+#define S_PF7_DSTATE    21
+#define M_PF7_DSTATE    0x7U
+#define V_PF7_DSTATE(x) ((x) << S_PF7_DSTATE)
+#define G_PF7_DSTATE(x) (((x) >> S_PF7_DSTATE) & M_PF7_DSTATE)
+
+#define S_PF6_DSTATE    18
+#define M_PF6_DSTATE    0x7U
+#define V_PF6_DSTATE(x) ((x) << S_PF6_DSTATE)
+#define G_PF6_DSTATE(x) (((x) >> S_PF6_DSTATE) & M_PF6_DSTATE)
+
+#define S_PF5_DSTATE    15
+#define M_PF5_DSTATE    0x7U
+#define V_PF5_DSTATE(x) ((x) << S_PF5_DSTATE)
+#define G_PF5_DSTATE(x) (((x) >> S_PF5_DSTATE) & M_PF5_DSTATE)
+
+#define S_PF4_DSTATE    12
+#define M_PF4_DSTATE    0x7U
+#define V_PF4_DSTATE(x) ((x) << S_PF4_DSTATE)
+#define G_PF4_DSTATE(x) (((x) >> S_PF4_DSTATE) & M_PF4_DSTATE)
+
+#define S_PF3_DSTATE    9
+#define M_PF3_DSTATE    0x7U
+#define V_PF3_DSTATE(x) ((x) << S_PF3_DSTATE)
+#define G_PF3_DSTATE(x) (((x) >> S_PF3_DSTATE) & M_PF3_DSTATE)
+
+#define S_PF2_DSTATE    6
+#define M_PF2_DSTATE    0x7U
+#define V_PF2_DSTATE(x) ((x) << S_PF2_DSTATE)
+#define G_PF2_DSTATE(x) (((x) >> S_PF2_DSTATE) & M_PF2_DSTATE)
+
+#define S_PF1_DSTATE    3
+#define M_PF1_DSTATE    0x7U
+#define V_PF1_DSTATE(x) ((x) << S_PF1_DSTATE)
+#define G_PF1_DSTATE(x) (((x) >> S_PF1_DSTATE) & M_PF1_DSTATE)
+
+#define S_PF0_DSTATE    0
+#define M_PF0_DSTATE    0x7U
+#define V_PF0_DSTATE(x) ((x) << S_PF0_DSTATE)
+#define G_PF0_DSTATE(x) (((x) >> S_PF0_DSTATE) & M_PF0_DSTATE)
+
+#define A_PCIE_DEBUG_ADDR_RANGE1 0x5ee0
+#define A_PCIE_DEBUG_ADDR_RANGE2 0x5ef0
+#define A_PCIE_DEBUG_ADDR_RANGE_CNT 0x5f00
+#define A_PCIE_PDEBUG_REG_0X0 0x0
+#define A_PCIE_PDEBUG_REG_0X1 0x1
+#define A_PCIE_PDEBUG_REG_0X2 0x2
+
+#define S_TAGQ_CH0_TAGS_USED    11
+#define M_TAGQ_CH0_TAGS_USED    0xffU
+#define V_TAGQ_CH0_TAGS_USED(x) ((x) << S_TAGQ_CH0_TAGS_USED)
+#define G_TAGQ_CH0_TAGS_USED(x) (((x) >> S_TAGQ_CH0_TAGS_USED) & M_TAGQ_CH0_TAGS_USED)
+
+#define S_REQ_CH0_DATA_EMPTY    10
+#define V_REQ_CH0_DATA_EMPTY(x) ((x) << S_REQ_CH0_DATA_EMPTY)
+#define F_REQ_CH0_DATA_EMPTY    V_REQ_CH0_DATA_EMPTY(1U)
+
+#define S_RDQ_CH0_REQ_EMPTY    9
+#define V_RDQ_CH0_REQ_EMPTY(x) ((x) << S_RDQ_CH0_REQ_EMPTY)
+#define F_RDQ_CH0_REQ_EMPTY    V_RDQ_CH0_REQ_EMPTY(1U)
+
+#define S_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ    8
+#define V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ)
+#define F_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(1U)
+
+#define S_REQ_CTL_RD_CH0_WAIT_FOR_CMD    7
+#define V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_CMD)
+#define F_REQ_CTL_RD_CH0_WAIT_FOR_CMD    V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(1U)
+
+#define S_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM    6
+#define V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM)
+#define F_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(1U)
+
+#define S_REQ_CTL_RD_CH0_WAIT_FOR_RDQ    5
+#define V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_RDQ)
+#define F_REQ_CTL_RD_CH0_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(1U)
+
+#define S_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO    4
+#define V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO)
+#define F_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(1U)
+
+#define S_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0X3 0x3
+
+#define S_TAGQ_CH1_TAGS_USED    11
+#define M_TAGQ_CH1_TAGS_USED    0xffU
+#define V_TAGQ_CH1_TAGS_USED(x) ((x) << S_TAGQ_CH1_TAGS_USED)
+#define G_TAGQ_CH1_TAGS_USED(x) (((x) >> S_TAGQ_CH1_TAGS_USED) & M_TAGQ_CH1_TAGS_USED)
+
+#define S_REQ_CH1_DATA_EMPTY    10
+#define V_REQ_CH1_DATA_EMPTY(x) ((x) << S_REQ_CH1_DATA_EMPTY)
+#define F_REQ_CH1_DATA_EMPTY    V_REQ_CH1_DATA_EMPTY(1U)
+
+#define S_RDQ_CH1_REQ_EMPTY    9
+#define V_RDQ_CH1_REQ_EMPTY(x) ((x) << S_RDQ_CH1_REQ_EMPTY)
+#define F_RDQ_CH1_REQ_EMPTY    V_RDQ_CH1_REQ_EMPTY(1U)
+
+#define S_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ    8
+#define V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ)
+#define F_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(1U)
+
+#define S_REQ_CTL_RD_CH1_WAIT_FOR_CMD    7
+#define V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_CMD)
+#define F_REQ_CTL_RD_CH1_WAIT_FOR_CMD    V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(1U)
+
+#define S_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM    6
+#define V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM)
+#define F_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(1U)
+
+#define S_REQ_CTL_RD_CH1_WAIT_FOR_RDQ    5
+#define V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_RDQ)
+#define F_REQ_CTL_RD_CH1_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(1U)
+
+#define S_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO    4
+#define V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO)
+#define F_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(1U)
+
+#define S_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0X4 0x4
+
+#define S_TAGQ_CH2_TAGS_USED    11
+#define M_TAGQ_CH2_TAGS_USED    0xffU
+#define V_TAGQ_CH2_TAGS_USED(x) ((x) << S_TAGQ_CH2_TAGS_USED)
+#define G_TAGQ_CH2_TAGS_USED(x) (((x) >> S_TAGQ_CH2_TAGS_USED) & M_TAGQ_CH2_TAGS_USED)
+
+#define S_REQ_CH2_DATA_EMPTY    10
+#define V_REQ_CH2_DATA_EMPTY(x) ((x) << S_REQ_CH2_DATA_EMPTY)
+#define F_REQ_CH2_DATA_EMPTY    V_REQ_CH2_DATA_EMPTY(1U)
+
+#define S_RDQ_CH2_REQ_EMPTY    9
+#define V_RDQ_CH2_REQ_EMPTY(x) ((x) << S_RDQ_CH2_REQ_EMPTY)
+#define F_RDQ_CH2_REQ_EMPTY    V_RDQ_CH2_REQ_EMPTY(1U)
+
+#define S_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ    8
+#define V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ)
+#define F_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(1U)
+
+#define S_REQ_CTL_RD_CH2_WAIT_FOR_CMD    7
+#define V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_CMD)
+#define F_REQ_CTL_RD_CH2_WAIT_FOR_CMD    V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(1U)
+
+#define S_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM    6
+#define V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM)
+#define F_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(1U)
+
+#define S_REQ_CTL_RD_CH2_WAIT_FOR_RDQ    5
+#define V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_RDQ)
+#define F_REQ_CTL_RD_CH2_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(1U)
+
+#define S_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO    4
+#define V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO)
+#define F_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(1U)
+
+#define S_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0X5 0x5
+
+#define S_TAGQ_CH3_TAGS_USED    11
+#define M_TAGQ_CH3_TAGS_USED    0xffU
+#define V_TAGQ_CH3_TAGS_USED(x) ((x) << S_TAGQ_CH3_TAGS_USED)
+#define G_TAGQ_CH3_TAGS_USED(x) (((x) >> S_TAGQ_CH3_TAGS_USED) & M_TAGQ_CH3_TAGS_USED)
+
+#define S_REQ_CH3_DATA_EMPTY    10
+#define V_REQ_CH3_DATA_EMPTY(x) ((x) << S_REQ_CH3_DATA_EMPTY)
+#define F_REQ_CH3_DATA_EMPTY    V_REQ_CH3_DATA_EMPTY(1U)
+
+#define S_RDQ_CH3_REQ_EMPTY    9
+#define V_RDQ_CH3_REQ_EMPTY(x) ((x) << S_RDQ_CH3_REQ_EMPTY)
+#define F_RDQ_CH3_REQ_EMPTY    V_RDQ_CH3_REQ_EMPTY(1U)
+
+#define S_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ    8
+#define V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ)
+#define F_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(1U)
+
+#define S_REQ_CTL_RD_CH3_WAIT_FOR_CMD    7
+#define V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_CMD)
+#define F_REQ_CTL_RD_CH3_WAIT_FOR_CMD    V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(1U)
+
+#define S_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM    6
+#define V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM)
+#define F_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(1U)
+
+#define S_REQ_CTL_RD_CH3_WAIT_FOR_RDQ    5
+#define V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_RDQ)
+#define F_REQ_CTL_RD_CH3_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(1U)
+
+#define S_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO    4
+#define V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO)
+#define F_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(1U)
+
+#define S_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0X6 0x6
+
+#define S_TAGQ_CH4_TAGS_USED    11
+#define M_TAGQ_CH4_TAGS_USED    0xffU
+#define V_TAGQ_CH4_TAGS_USED(x) ((x) << S_TAGQ_CH4_TAGS_USED)
+#define G_TAGQ_CH4_TAGS_USED(x) (((x) >> S_TAGQ_CH4_TAGS_USED) & M_TAGQ_CH4_TAGS_USED)
+
+#define S_REQ_CH4_DATA_EMPTY    10
+#define V_REQ_CH4_DATA_EMPTY(x) ((x) << S_REQ_CH4_DATA_EMPTY)
+#define F_REQ_CH4_DATA_EMPTY    V_REQ_CH4_DATA_EMPTY(1U)
+
+#define S_RDQ_CH4_REQ_EMPTY    9
+#define V_RDQ_CH4_REQ_EMPTY(x) ((x) << S_RDQ_CH4_REQ_EMPTY)
+#define F_RDQ_CH4_REQ_EMPTY    V_RDQ_CH4_REQ_EMPTY(1U)
+
+#define S_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ    8
+#define V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ)
+#define F_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(1U)
+
+#define S_REQ_CTL_RD_CH4_WAIT_FOR_CMD    7
+#define V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_CMD)
+#define F_REQ_CTL_RD_CH4_WAIT_FOR_CMD    V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(1U)
+
+#define S_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM    6
+#define V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM)
+#define F_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(1U)
+
+#define S_REQ_CTL_RD_CH4_WAIT_FOR_RDQ    5
+#define V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_RDQ)
+#define F_REQ_CTL_RD_CH4_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(1U)
+
+#define S_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO    4
+#define V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO)
+#define F_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(1U)
+
+#define S_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0X7 0x7
+
+#define S_TAGQ_CH5_TAGS_USED    11
+#define M_TAGQ_CH5_TAGS_USED    0xffU
+#define V_TAGQ_CH5_TAGS_USED(x) ((x) << S_TAGQ_CH5_TAGS_USED)
+#define G_TAGQ_CH5_TAGS_USED(x) (((x) >> S_TAGQ_CH5_TAGS_USED) & M_TAGQ_CH5_TAGS_USED)
+
+#define S_REQ_CH5_DATA_EMPTY    10
+#define V_REQ_CH5_DATA_EMPTY(x) ((x) << S_REQ_CH5_DATA_EMPTY)
+#define F_REQ_CH5_DATA_EMPTY    V_REQ_CH5_DATA_EMPTY(1U)
+
+#define S_RDQ_CH5_REQ_EMPTY    9
+#define V_RDQ_CH5_REQ_EMPTY(x) ((x) << S_RDQ_CH5_REQ_EMPTY)
+#define F_RDQ_CH5_REQ_EMPTY    V_RDQ_CH5_REQ_EMPTY(1U)
+
+#define S_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ    8
+#define V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ)
+#define F_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(1U)
+
+#define S_REQ_CTL_RD_CH5_WAIT_FOR_CMD    7
+#define V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_CMD)
+#define F_REQ_CTL_RD_CH5_WAIT_FOR_CMD    V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(1U)
+
+#define S_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM    6
+#define V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM)
+#define F_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(1U)
+
+#define S_REQ_CTL_RD_CH5_WAIT_FOR_RDQ    5
+#define V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_RDQ)
+#define F_REQ_CTL_RD_CH5_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(1U)
+
+#define S_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO    4
+#define V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO)
+#define F_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(1U)
+
+#define S_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0X8 0x8
+
+#define S_TAGQ_CH6_TAGS_USED    11
+#define M_TAGQ_CH6_TAGS_USED    0xffU
+#define V_TAGQ_CH6_TAGS_USED(x) ((x) << S_TAGQ_CH6_TAGS_USED)
+#define G_TAGQ_CH6_TAGS_USED(x) (((x) >> S_TAGQ_CH6_TAGS_USED) & M_TAGQ_CH6_TAGS_USED)
+
+#define S_REQ_CH6_DATA_EMPTY    10
+#define V_REQ_CH6_DATA_EMPTY(x) ((x) << S_REQ_CH6_DATA_EMPTY)
+#define F_REQ_CH6_DATA_EMPTY    V_REQ_CH6_DATA_EMPTY(1U)
+
+#define S_RDQ_CH6_REQ_EMPTY    9
+#define V_RDQ_CH6_REQ_EMPTY(x) ((x) << S_RDQ_CH6_REQ_EMPTY)
+#define F_RDQ_CH6_REQ_EMPTY    V_RDQ_CH6_REQ_EMPTY(1U)
+
+#define S_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ    8
+#define V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ)
+#define F_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(1U)
+
+#define S_REQ_CTL_RD_CH6_WAIT_FOR_CMD    7
+#define V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_CMD)
+#define F_REQ_CTL_RD_CH6_WAIT_FOR_CMD    V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(1U)
+
+#define S_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM    6
+#define V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM)
+#define F_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(1U)
+
+#define S_REQ_CTL_RD_CH6_WAIT_FOR_RDQ    5
+#define V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_RDQ)
+#define F_REQ_CTL_RD_CH6_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(1U)
+
+#define S_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO    4
+#define V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO)
+#define F_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(1U)
+
+#define S_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0X9 0x9
+
+#define S_TAGQ_CH7_TAGS_USED    11
+#define M_TAGQ_CH7_TAGS_USED    0xffU
+#define V_TAGQ_CH7_TAGS_USED(x) ((x) << S_TAGQ_CH7_TAGS_USED)
+#define G_TAGQ_CH7_TAGS_USED(x) (((x) >> S_TAGQ_CH7_TAGS_USED) & M_TAGQ_CH7_TAGS_USED)
+
+#define S_REQ_CH7_DATA_EMPTY    10
+#define V_REQ_CH7_DATA_EMPTY(x) ((x) << S_REQ_CH7_DATA_EMPTY)
+#define F_REQ_CH7_DATA_EMPTY    V_REQ_CH7_DATA_EMPTY(1U)
+
+#define S_RDQ_CH7_REQ_EMPTY    9
+#define V_RDQ_CH7_REQ_EMPTY(x) ((x) << S_RDQ_CH7_REQ_EMPTY)
+#define F_RDQ_CH7_REQ_EMPTY    V_RDQ_CH7_REQ_EMPTY(1U)
+
+#define S_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ    8
+#define V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ)
+#define F_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(1U)
+
+#define S_REQ_CTL_RD_CH7_WAIT_FOR_CMD    7
+#define V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_CMD)
+#define F_REQ_CTL_RD_CH7_WAIT_FOR_CMD    V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(1U)
+
+#define S_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM    6
+#define V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM)
+#define F_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(1U)
+
+#define S_REQ_CTL_RD_CH7_WAIT_FOR_RDQ    5
+#define V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_RDQ)
+#define F_REQ_CTL_RD_CH7_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(1U)
+
+#define S_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO    4
+#define V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO)
+#define F_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(1U)
+
+#define S_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0XA 0xa
+
+#define S_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM    27
+#define V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM)
+#define F_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(1U)
+
+#define S_REQ_CTL_WR_CH0_SEQNUM    19
+#define M_REQ_CTL_WR_CH0_SEQNUM    0xffU
+#define V_REQ_CTL_WR_CH0_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH0_SEQNUM)
+#define G_REQ_CTL_WR_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH0_SEQNUM) & M_REQ_CTL_WR_CH0_SEQNUM)
+
+#define S_REQ_CTL_RD_CH0_SEQNUM    11
+#define M_REQ_CTL_RD_CH0_SEQNUM    0xffU
+#define V_REQ_CTL_RD_CH0_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_SEQNUM)
+#define G_REQ_CTL_RD_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH0_SEQNUM) & M_REQ_CTL_RD_CH0_SEQNUM)
+
+#define S_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO    4
+#define V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO)
+#define F_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(1U)
+
+#define S_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0XB 0xb
+
+#define S_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM    27
+#define V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM)
+#define F_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(1U)
+
+#define S_REQ_CTL_WR_CH1_SEQNUM    19
+#define M_REQ_CTL_WR_CH1_SEQNUM    0xffU
+#define V_REQ_CTL_WR_CH1_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH1_SEQNUM)
+#define G_REQ_CTL_WR_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH1_SEQNUM) & M_REQ_CTL_WR_CH1_SEQNUM)
+
+#define S_REQ_CTL_RD_CH1_SEQNUM    11
+#define M_REQ_CTL_RD_CH1_SEQNUM    0xffU
+#define V_REQ_CTL_RD_CH1_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_SEQNUM)
+#define G_REQ_CTL_RD_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH1_SEQNUM) & M_REQ_CTL_RD_CH1_SEQNUM)
+
+#define S_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO    4
+#define V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO)
+#define F_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(1U)
+
+#define S_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0XC 0xc
+
+#define S_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM    27
+#define V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM)
+#define F_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(1U)
+
+#define S_REQ_CTL_WR_CH2_SEQNUM    19
+#define M_REQ_CTL_WR_CH2_SEQNUM    0xffU
+#define V_REQ_CTL_WR_CH2_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH2_SEQNUM)
+#define G_REQ_CTL_WR_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH2_SEQNUM) & M_REQ_CTL_WR_CH2_SEQNUM)
+
+#define S_REQ_CTL_RD_CH2_SEQNUM    11
+#define M_REQ_CTL_RD_CH2_SEQNUM    0xffU
+#define V_REQ_CTL_RD_CH2_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_SEQNUM)
+#define G_REQ_CTL_RD_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH2_SEQNUM) & M_REQ_CTL_RD_CH2_SEQNUM)
+
+#define S_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO    4
+#define V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO)
+#define F_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(1U)
+
+#define S_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0XD 0xd
+
+#define S_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM    27
+#define V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM)
+#define F_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(1U)
+
+#define S_REQ_CTL_WR_CH3_SEQNUM    19
+#define M_REQ_CTL_WR_CH3_SEQNUM    0xffU
+#define V_REQ_CTL_WR_CH3_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH3_SEQNUM)
+#define G_REQ_CTL_WR_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH3_SEQNUM) & M_REQ_CTL_WR_CH3_SEQNUM)
+
+#define S_REQ_CTL_RD_CH3_SEQNUM    11
+#define M_REQ_CTL_RD_CH3_SEQNUM    0xffU
+#define V_REQ_CTL_RD_CH3_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_SEQNUM)
+#define G_REQ_CTL_RD_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH3_SEQNUM) & M_REQ_CTL_RD_CH3_SEQNUM)
+
+#define S_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO    4
+#define V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO)
+#define F_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(1U)
+
+#define S_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0XE 0xe
+
+#define S_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM    27
+#define V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM)
+#define F_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(1U)
+
+#define S_REQ_CTL_WR_CH4_SEQNUM    19
+#define M_REQ_CTL_WR_CH4_SEQNUM    0xffU
+#define V_REQ_CTL_WR_CH4_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH4_SEQNUM)
+#define G_REQ_CTL_WR_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH4_SEQNUM) & M_REQ_CTL_WR_CH4_SEQNUM)
+
+#define S_REQ_CTL_RD_CH4_SEQNUM    11
+#define M_REQ_CTL_RD_CH4_SEQNUM    0xffU
+#define V_REQ_CTL_RD_CH4_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_SEQNUM)
+#define G_REQ_CTL_RD_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH4_SEQNUM) & M_REQ_CTL_RD_CH4_SEQNUM)
+
+#define S_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO    4
+#define V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO)
+#define F_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(1U)
+
+#define S_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED    3
+#define V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED)
+#define F_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED    2
+#define V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED)
+#define F_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(1U)
+
+#define S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE    1
+#define V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE)
+#define F_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(1U)
+
+#define S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA    0
+#define V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA)
+#define F_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(1U)
+
+#define A_PCIE_PDEBUG_REG_0XF 0xf
+#define A_PCIE_PDEBUG_REG_0X10 0x10
+
+#define S_PIPE0_TX3_DATAK_0    31
+#define V_PIPE0_TX3_DATAK_0(x) ((x) << S_PIPE0_TX3_DATAK_0)
+#define F_PIPE0_TX3_DATAK_0    V_PIPE0_TX3_DATAK_0(1U)
+
+#define S_PIPE0_TX3_DATA_6_0    24
+#define M_PIPE0_TX3_DATA_6_0    0x7fU
+#define V_PIPE0_TX3_DATA_6_0(x) ((x) << S_PIPE0_TX3_DATA_6_0)
+#define G_PIPE0_TX3_DATA_6_0(x) (((x) >> S_PIPE0_TX3_DATA_6_0) & M_PIPE0_TX3_DATA_6_0)
+
+#define S_PIPE0_TX2_DATA_7_0    16
+#define M_PIPE0_TX2_DATA_7_0    0xffU
+#define V_PIPE0_TX2_DATA_7_0(x) ((x) << S_PIPE0_TX2_DATA_7_0)
+#define G_PIPE0_TX2_DATA_7_0(x) (((x) >> S_PIPE0_TX2_DATA_7_0) & M_PIPE0_TX2_DATA_7_0)
+
+#define S_PIPE0_TX1_DATA_7_0    8
+#define M_PIPE0_TX1_DATA_7_0    0xffU
+#define V_PIPE0_TX1_DATA_7_0(x) ((x) << S_PIPE0_TX1_DATA_7_0)
+#define G_PIPE0_TX1_DATA_7_0(x) (((x) >> S_PIPE0_TX1_DATA_7_0) & M_PIPE0_TX1_DATA_7_0)
+
+#define S_PIPE0_TX0_DATAK_0    7
+#define V_PIPE0_TX0_DATAK_0(x) ((x) << S_PIPE0_TX0_DATAK_0)
+#define F_PIPE0_TX0_DATAK_0    V_PIPE0_TX0_DATAK_0(1U)
+
+#define S_PIPE0_TX0_DATA_6_0    0
+#define M_PIPE0_TX0_DATA_6_0    0x7fU
+#define V_PIPE0_TX0_DATA_6_0(x) ((x) << S_PIPE0_TX0_DATA_6_0)
+#define G_PIPE0_TX0_DATA_6_0(x) (((x) >> S_PIPE0_TX0_DATA_6_0) & M_PIPE0_TX0_DATA_6_0)
+
+#define A_PCIE_PDEBUG_REG_0X11 0x11
+
+#define S_PIPE0_TX3_DATAK_1    31
+#define V_PIPE0_TX3_DATAK_1(x) ((x) << S_PIPE0_TX3_DATAK_1)
+#define F_PIPE0_TX3_DATAK_1    V_PIPE0_TX3_DATAK_1(1U)
+
+#define S_PIPE0_TX3_DATA_14_8    24
+#define M_PIPE0_TX3_DATA_14_8    0x7fU
+#define V_PIPE0_TX3_DATA_14_8(x) ((x) << S_PIPE0_TX3_DATA_14_8)
+#define G_PIPE0_TX3_DATA_14_8(x) (((x) >> S_PIPE0_TX3_DATA_14_8) & M_PIPE0_TX3_DATA_14_8)
+
+#define S_PIPE0_TX2_DATA_15_8    16
+#define M_PIPE0_TX2_DATA_15_8    0xffU
+#define V_PIPE0_TX2_DATA_15_8(x) ((x) << S_PIPE0_TX2_DATA_15_8)
+#define G_PIPE0_TX2_DATA_15_8(x) (((x) >> S_PIPE0_TX2_DATA_15_8) & M_PIPE0_TX2_DATA_15_8)
+
+#define S_PIPE0_TX1_DATA_15_8    8
+#define M_PIPE0_TX1_DATA_15_8    0xffU
+#define V_PIPE0_TX1_DATA_15_8(x) ((x) << S_PIPE0_TX1_DATA_15_8)
+#define G_PIPE0_TX1_DATA_15_8(x) (((x) >> S_PIPE0_TX1_DATA_15_8) & M_PIPE0_TX1_DATA_15_8)
+
+#define S_PIPE0_TX0_DATAK_1    7
+#define V_PIPE0_TX0_DATAK_1(x) ((x) << S_PIPE0_TX0_DATAK_1)
+#define F_PIPE0_TX0_DATAK_1    V_PIPE0_TX0_DATAK_1(1U)
+
+#define S_PIPE0_TX0_DATA_14_8    0
+#define M_PIPE0_TX0_DATA_14_8    0x7fU
+#define V_PIPE0_TX0_DATA_14_8(x) ((x) << S_PIPE0_TX0_DATA_14_8)
+#define G_PIPE0_TX0_DATA_14_8(x) (((x) >> S_PIPE0_TX0_DATA_14_8) & M_PIPE0_TX0_DATA_14_8)
+
+#define A_PCIE_PDEBUG_REG_0X12 0x12
+
+#define S_PIPE0_TX7_DATAK_0    31
+#define V_PIPE0_TX7_DATAK_0(x) ((x) << S_PIPE0_TX7_DATAK_0)
+#define F_PIPE0_TX7_DATAK_0    V_PIPE0_TX7_DATAK_0(1U)
+
+#define S_PIPE0_TX7_DATA_6_0    24
+#define M_PIPE0_TX7_DATA_6_0    0x7fU
+#define V_PIPE0_TX7_DATA_6_0(x) ((x) << S_PIPE0_TX7_DATA_6_0)
+#define G_PIPE0_TX7_DATA_6_0(x) (((x) >> S_PIPE0_TX7_DATA_6_0) & M_PIPE0_TX7_DATA_6_0)
+
+#define S_PIPE0_TX6_DATA_7_0    16
+#define M_PIPE0_TX6_DATA_7_0    0xffU
+#define V_PIPE0_TX6_DATA_7_0(x) ((x) << S_PIPE0_TX6_DATA_7_0)
+#define G_PIPE0_TX6_DATA_7_0(x) (((x) >> S_PIPE0_TX6_DATA_7_0) & M_PIPE0_TX6_DATA_7_0)
+
+#define S_PIPE0_TX5_DATA_7_0    8
+#define M_PIPE0_TX5_DATA_7_0    0xffU
+#define V_PIPE0_TX5_DATA_7_0(x) ((x) << S_PIPE0_TX5_DATA_7_0)
+#define G_PIPE0_TX5_DATA_7_0(x) (((x) >> S_PIPE0_TX5_DATA_7_0) & M_PIPE0_TX5_DATA_7_0)
+
+#define S_PIPE0_TX4_DATAK_0    7
+#define V_PIPE0_TX4_DATAK_0(x) ((x) << S_PIPE0_TX4_DATAK_0)
+#define F_PIPE0_TX4_DATAK_0    V_PIPE0_TX4_DATAK_0(1U)
+
+#define S_PIPE0_TX4_DATA_6_0    0
+#define M_PIPE0_TX4_DATA_6_0    0x7fU
+#define V_PIPE0_TX4_DATA_6_0(x) ((x) << S_PIPE0_TX4_DATA_6_0)
+#define G_PIPE0_TX4_DATA_6_0(x) (((x) >> S_PIPE0_TX4_DATA_6_0) & M_PIPE0_TX4_DATA_6_0)
+
+#define A_PCIE_PDEBUG_REG_0X13 0x13
+
+#define S_PIPE0_TX7_DATAK_1    31
+#define V_PIPE0_TX7_DATAK_1(x) ((x) << S_PIPE0_TX7_DATAK_1)
+#define F_PIPE0_TX7_DATAK_1    V_PIPE0_TX7_DATAK_1(1U)
+
+#define S_PIPE0_TX7_DATA_14_8    24
+#define M_PIPE0_TX7_DATA_14_8    0x7fU
+#define V_PIPE0_TX7_DATA_14_8(x) ((x) << S_PIPE0_TX7_DATA_14_8)
+#define G_PIPE0_TX7_DATA_14_8(x) (((x) >> S_PIPE0_TX7_DATA_14_8) & M_PIPE0_TX7_DATA_14_8)
+
+#define S_PIPE0_TX6_DATA_15_8    16
+#define M_PIPE0_TX6_DATA_15_8    0xffU
+#define V_PIPE0_TX6_DATA_15_8(x) ((x) << S_PIPE0_TX6_DATA_15_8)
+#define G_PIPE0_TX6_DATA_15_8(x) (((x) >> S_PIPE0_TX6_DATA_15_8) & M_PIPE0_TX6_DATA_15_8)
+
+#define S_PIPE0_TX5_DATA_15_8    8
+#define M_PIPE0_TX5_DATA_15_8    0xffU
+#define V_PIPE0_TX5_DATA_15_8(x) ((x) << S_PIPE0_TX5_DATA_15_8)
+#define G_PIPE0_TX5_DATA_15_8(x) (((x) >> S_PIPE0_TX5_DATA_15_8) & M_PIPE0_TX5_DATA_15_8)
+
+#define S_PIPE0_TX4_DATAK_1    7
+#define V_PIPE0_TX4_DATAK_1(x) ((x) << S_PIPE0_TX4_DATAK_1)
+#define F_PIPE0_TX4_DATAK_1    V_PIPE0_TX4_DATAK_1(1U)
+
+#define S_PIPE0_TX4_DATA_14_8    0
+#define M_PIPE0_TX4_DATA_14_8    0x7fU
+#define V_PIPE0_TX4_DATA_14_8(x) ((x) << S_PIPE0_TX4_DATA_14_8)
+#define G_PIPE0_TX4_DATA_14_8(x) (((x) >> S_PIPE0_TX4_DATA_14_8) & M_PIPE0_TX4_DATA_14_8)
+
+#define A_PCIE_PDEBUG_REG_0X14 0x14
+
+#define S_PIPE0_RX3_VALID_14    31
+#define V_PIPE0_RX3_VALID_14(x) ((x) << S_PIPE0_RX3_VALID_14)
+#define F_PIPE0_RX3_VALID_14    V_PIPE0_RX3_VALID_14(1U)
+
+#define S_PIPE0_RX3_VALID2_14    24
+#define M_PIPE0_RX3_VALID2_14    0x7fU
+#define V_PIPE0_RX3_VALID2_14(x) ((x) << S_PIPE0_RX3_VALID2_14)
+#define G_PIPE0_RX3_VALID2_14(x) (((x) >> S_PIPE0_RX3_VALID2_14) & M_PIPE0_RX3_VALID2_14)
+
+#define S_PIPE0_RX2_VALID_14    16
+#define M_PIPE0_RX2_VALID_14    0xffU
+#define V_PIPE0_RX2_VALID_14(x) ((x) << S_PIPE0_RX2_VALID_14)
+#define G_PIPE0_RX2_VALID_14(x) (((x) >> S_PIPE0_RX2_VALID_14) & M_PIPE0_RX2_VALID_14)
+
+#define S_PIPE0_RX1_VALID_14    8
+#define M_PIPE0_RX1_VALID_14    0xffU
+#define V_PIPE0_RX1_VALID_14(x) ((x) << S_PIPE0_RX1_VALID_14)
+#define G_PIPE0_RX1_VALID_14(x) (((x) >> S_PIPE0_RX1_VALID_14) & M_PIPE0_RX1_VALID_14)
+
+#define S_PIPE0_RX0_VALID_14    7
+#define V_PIPE0_RX0_VALID_14(x) ((x) << S_PIPE0_RX0_VALID_14)
+#define F_PIPE0_RX0_VALID_14    V_PIPE0_RX0_VALID_14(1U)
+
+#define S_PIPE0_RX0_VALID2_14    0
+#define M_PIPE0_RX0_VALID2_14    0x7fU
+#define V_PIPE0_RX0_VALID2_14(x) ((x) << S_PIPE0_RX0_VALID2_14)
+#define G_PIPE0_RX0_VALID2_14(x) (((x) >> S_PIPE0_RX0_VALID2_14) & M_PIPE0_RX0_VALID2_14)
+
+#define A_PCIE_PDEBUG_REG_0X15 0x15
+
+#define S_PIPE0_RX3_VALID_15    31
+#define V_PIPE0_RX3_VALID_15(x) ((x) << S_PIPE0_RX3_VALID_15)
+#define F_PIPE0_RX3_VALID_15    V_PIPE0_RX3_VALID_15(1U)
+
+#define S_PIPE0_RX3_VALID2_15    24
+#define M_PIPE0_RX3_VALID2_15    0x7fU
+#define V_PIPE0_RX3_VALID2_15(x) ((x) << S_PIPE0_RX3_VALID2_15)
+#define G_PIPE0_RX3_VALID2_15(x) (((x) >> S_PIPE0_RX3_VALID2_15) & M_PIPE0_RX3_VALID2_15)
+
+#define S_PIPE0_RX2_VALID_15    16
+#define M_PIPE0_RX2_VALID_15    0xffU
+#define V_PIPE0_RX2_VALID_15(x) ((x) << S_PIPE0_RX2_VALID_15)
+#define G_PIPE0_RX2_VALID_15(x) (((x) >> S_PIPE0_RX2_VALID_15) & M_PIPE0_RX2_VALID_15)
+
+#define S_PIPE0_RX1_VALID_15    8
+#define M_PIPE0_RX1_VALID_15    0xffU
+#define V_PIPE0_RX1_VALID_15(x) ((x) << S_PIPE0_RX1_VALID_15)
+#define G_PIPE0_RX1_VALID_15(x) (((x) >> S_PIPE0_RX1_VALID_15) & M_PIPE0_RX1_VALID_15)
+
+#define S_PIPE0_RX0_VALID_15    7
+#define V_PIPE0_RX0_VALID_15(x) ((x) << S_PIPE0_RX0_VALID_15)
+#define F_PIPE0_RX0_VALID_15    V_PIPE0_RX0_VALID_15(1U)
+
+#define S_PIPE0_RX0_VALID2_15    0
+#define M_PIPE0_RX0_VALID2_15    0x7fU
+#define V_PIPE0_RX0_VALID2_15(x) ((x) << S_PIPE0_RX0_VALID2_15)
+#define G_PIPE0_RX0_VALID2_15(x) (((x) >> S_PIPE0_RX0_VALID2_15) & M_PIPE0_RX0_VALID2_15)
+
+#define A_PCIE_PDEBUG_REG_0X16 0x16
+
+#define S_PIPE0_RX7_VALID_16    31
+#define V_PIPE0_RX7_VALID_16(x) ((x) << S_PIPE0_RX7_VALID_16)
+#define F_PIPE0_RX7_VALID_16    V_PIPE0_RX7_VALID_16(1U)
+
+#define S_PIPE0_RX7_VALID2_16    24
+#define M_PIPE0_RX7_VALID2_16    0x7fU
+#define V_PIPE0_RX7_VALID2_16(x) ((x) << S_PIPE0_RX7_VALID2_16)
+#define G_PIPE0_RX7_VALID2_16(x) (((x) >> S_PIPE0_RX7_VALID2_16) & M_PIPE0_RX7_VALID2_16)
+
+#define S_PIPE0_RX6_VALID_16    16
+#define M_PIPE0_RX6_VALID_16    0xffU
+#define V_PIPE0_RX6_VALID_16(x) ((x) << S_PIPE0_RX6_VALID_16)
+#define G_PIPE0_RX6_VALID_16(x) (((x) >> S_PIPE0_RX6_VALID_16) & M_PIPE0_RX6_VALID_16)
+
+#define S_PIPE0_RX5_VALID_16    8
+#define M_PIPE0_RX5_VALID_16    0xffU
+#define V_PIPE0_RX5_VALID_16(x) ((x) << S_PIPE0_RX5_VALID_16)
+#define G_PIPE0_RX5_VALID_16(x) (((x) >> S_PIPE0_RX5_VALID_16) & M_PIPE0_RX5_VALID_16)
+
+#define S_PIPE0_RX4_VALID_16    7
+#define V_PIPE0_RX4_VALID_16(x) ((x) << S_PIPE0_RX4_VALID_16)
+#define F_PIPE0_RX4_VALID_16    V_PIPE0_RX4_VALID_16(1U)
+
+#define S_PIPE0_RX4_VALID2_16    0
+#define M_PIPE0_RX4_VALID2_16    0x7fU
+#define V_PIPE0_RX4_VALID2_16(x) ((x) << S_PIPE0_RX4_VALID2_16)
+#define G_PIPE0_RX4_VALID2_16(x) (((x) >> S_PIPE0_RX4_VALID2_16) & M_PIPE0_RX4_VALID2_16)
+
+#define A_PCIE_PDEBUG_REG_0X17 0x17
+
+#define S_PIPE0_RX7_VALID_17    31
+#define V_PIPE0_RX7_VALID_17(x) ((x) << S_PIPE0_RX7_VALID_17)
+#define F_PIPE0_RX7_VALID_17    V_PIPE0_RX7_VALID_17(1U)
+
+#define S_PIPE0_RX7_VALID2_17    24
+#define M_PIPE0_RX7_VALID2_17    0x7fU
+#define V_PIPE0_RX7_VALID2_17(x) ((x) << S_PIPE0_RX7_VALID2_17)
+#define G_PIPE0_RX7_VALID2_17(x) (((x) >> S_PIPE0_RX7_VALID2_17) & M_PIPE0_RX7_VALID2_17)
+
+#define S_PIPE0_RX6_VALID_17    16
+#define M_PIPE0_RX6_VALID_17    0xffU
+#define V_PIPE0_RX6_VALID_17(x) ((x) << S_PIPE0_RX6_VALID_17)
+#define G_PIPE0_RX6_VALID_17(x) (((x) >> S_PIPE0_RX6_VALID_17) & M_PIPE0_RX6_VALID_17)
+
+#define S_PIPE0_RX5_VALID_17    8
+#define M_PIPE0_RX5_VALID_17    0xffU
+#define V_PIPE0_RX5_VALID_17(x) ((x) << S_PIPE0_RX5_VALID_17)
+#define G_PIPE0_RX5_VALID_17(x) (((x) >> S_PIPE0_RX5_VALID_17) & M_PIPE0_RX5_VALID_17)
+
+#define S_PIPE0_RX4_VALID_17    7
+#define V_PIPE0_RX4_VALID_17(x) ((x) << S_PIPE0_RX4_VALID_17)
+#define F_PIPE0_RX4_VALID_17    V_PIPE0_RX4_VALID_17(1U)
+
+#define S_PIPE0_RX4_VALID2_17    0
+#define M_PIPE0_RX4_VALID2_17    0x7fU
+#define V_PIPE0_RX4_VALID2_17(x) ((x) << S_PIPE0_RX4_VALID2_17)
+#define G_PIPE0_RX4_VALID2_17(x) (((x) >> S_PIPE0_RX4_VALID2_17) & M_PIPE0_RX4_VALID2_17)
+
+#define A_PCIE_PDEBUG_REG_0X18 0x18
+
+#define S_PIPE0_RX7_POLARITY    31
+#define V_PIPE0_RX7_POLARITY(x) ((x) << S_PIPE0_RX7_POLARITY)
+#define F_PIPE0_RX7_POLARITY    V_PIPE0_RX7_POLARITY(1U)
+
+#define S_PIPE0_RX7_STATUS    28
+#define M_PIPE0_RX7_STATUS    0x7U
+#define V_PIPE0_RX7_STATUS(x) ((x) << S_PIPE0_RX7_STATUS)
+#define G_PIPE0_RX7_STATUS(x) (((x) >> S_PIPE0_RX7_STATUS) & M_PIPE0_RX7_STATUS)
+
+#define S_PIPE0_RX6_POLARITY    27
+#define V_PIPE0_RX6_POLARITY(x) ((x) << S_PIPE0_RX6_POLARITY)
+#define F_PIPE0_RX6_POLARITY    V_PIPE0_RX6_POLARITY(1U)
+
+#define S_PIPE0_RX6_STATUS    24
+#define M_PIPE0_RX6_STATUS    0x7U
+#define V_PIPE0_RX6_STATUS(x) ((x) << S_PIPE0_RX6_STATUS)
+#define G_PIPE0_RX6_STATUS(x) (((x) >> S_PIPE0_RX6_STATUS) & M_PIPE0_RX6_STATUS)
+
+#define S_PIPE0_RX5_POLARITY    23
+#define V_PIPE0_RX5_POLARITY(x) ((x) << S_PIPE0_RX5_POLARITY)
+#define F_PIPE0_RX5_POLARITY    V_PIPE0_RX5_POLARITY(1U)
+
+#define S_PIPE0_RX5_STATUS    20
+#define M_PIPE0_RX5_STATUS    0x7U
+#define V_PIPE0_RX5_STATUS(x) ((x) << S_PIPE0_RX5_STATUS)
+#define G_PIPE0_RX5_STATUS(x) (((x) >> S_PIPE0_RX5_STATUS) & M_PIPE0_RX5_STATUS)
+
+#define S_PIPE0_RX4_POLARITY    19
+#define V_PIPE0_RX4_POLARITY(x) ((x) << S_PIPE0_RX4_POLARITY)
+#define F_PIPE0_RX4_POLARITY    V_PIPE0_RX4_POLARITY(1U)
+
+#define S_PIPE0_RX4_STATUS    16
+#define M_PIPE0_RX4_STATUS    0x7U
+#define V_PIPE0_RX4_STATUS(x) ((x) << S_PIPE0_RX4_STATUS)
+#define G_PIPE0_RX4_STATUS(x) (((x) >> S_PIPE0_RX4_STATUS) & M_PIPE0_RX4_STATUS)
+
+#define S_PIPE0_RX3_POLARITY    15
+#define V_PIPE0_RX3_POLARITY(x) ((x) << S_PIPE0_RX3_POLARITY)
+#define F_PIPE0_RX3_POLARITY    V_PIPE0_RX3_POLARITY(1U)
+
+#define S_PIPE0_RX3_STATUS    12
+#define M_PIPE0_RX3_STATUS    0x7U
+#define V_PIPE0_RX3_STATUS(x) ((x) << S_PIPE0_RX3_STATUS)
+#define G_PIPE0_RX3_STATUS(x) (((x) >> S_PIPE0_RX3_STATUS) & M_PIPE0_RX3_STATUS)
+
+#define S_PIPE0_RX2_POLARITY    11
+#define V_PIPE0_RX2_POLARITY(x) ((x) << S_PIPE0_RX2_POLARITY)
+#define F_PIPE0_RX2_POLARITY    V_PIPE0_RX2_POLARITY(1U)
+
+#define S_PIPE0_RX2_STATUS    8
+#define M_PIPE0_RX2_STATUS    0x7U
+#define V_PIPE0_RX2_STATUS(x) ((x) << S_PIPE0_RX2_STATUS)
+#define G_PIPE0_RX2_STATUS(x) (((x) >> S_PIPE0_RX2_STATUS) & M_PIPE0_RX2_STATUS)
+
+#define S_PIPE0_RX1_POLARITY    7
+#define V_PIPE0_RX1_POLARITY(x) ((x) << S_PIPE0_RX1_POLARITY)
+#define F_PIPE0_RX1_POLARITY    V_PIPE0_RX1_POLARITY(1U)
+
+#define S_PIPE0_RX1_STATUS    4
+#define M_PIPE0_RX1_STATUS    0x7U
+#define V_PIPE0_RX1_STATUS(x) ((x) << S_PIPE0_RX1_STATUS)
+#define G_PIPE0_RX1_STATUS(x) (((x) >> S_PIPE0_RX1_STATUS) & M_PIPE0_RX1_STATUS)
+
+#define S_PIPE0_RX0_POLARITY    3
+#define V_PIPE0_RX0_POLARITY(x) ((x) << S_PIPE0_RX0_POLARITY)
+#define F_PIPE0_RX0_POLARITY    V_PIPE0_RX0_POLARITY(1U)
+
+#define S_PIPE0_RX0_STATUS    0
+#define M_PIPE0_RX0_STATUS    0x7U
+#define V_PIPE0_RX0_STATUS(x) ((x) << S_PIPE0_RX0_STATUS)
+#define G_PIPE0_RX0_STATUS(x) (((x) >> S_PIPE0_RX0_STATUS) & M_PIPE0_RX0_STATUS)
+
+#define A_PCIE_PDEBUG_REG_0X19 0x19
+
+#define S_PIPE0_TX7_COMPLIANCE    31
+#define V_PIPE0_TX7_COMPLIANCE(x) ((x) << S_PIPE0_TX7_COMPLIANCE)
+#define F_PIPE0_TX7_COMPLIANCE    V_PIPE0_TX7_COMPLIANCE(1U)
+
+#define S_PIPE0_TX6_COMPLIANCE    30
+#define V_PIPE0_TX6_COMPLIANCE(x) ((x) << S_PIPE0_TX6_COMPLIANCE)
+#define F_PIPE0_TX6_COMPLIANCE    V_PIPE0_TX6_COMPLIANCE(1U)
+
+#define S_PIPE0_TX5_COMPLIANCE    29
+#define V_PIPE0_TX5_COMPLIANCE(x) ((x) << S_PIPE0_TX5_COMPLIANCE)
+#define F_PIPE0_TX5_COMPLIANCE    V_PIPE0_TX5_COMPLIANCE(1U)
+
+#define S_PIPE0_TX4_COMPLIANCE    28
+#define V_PIPE0_TX4_COMPLIANCE(x) ((x) << S_PIPE0_TX4_COMPLIANCE)
+#define F_PIPE0_TX4_COMPLIANCE    V_PIPE0_TX4_COMPLIANCE(1U)
+
+#define S_PIPE0_TX3_COMPLIANCE    27
+#define V_PIPE0_TX3_COMPLIANCE(x) ((x) << S_PIPE0_TX3_COMPLIANCE)
+#define F_PIPE0_TX3_COMPLIANCE    V_PIPE0_TX3_COMPLIANCE(1U)
+
+#define S_PIPE0_TX2_COMPLIANCE    26
+#define V_PIPE0_TX2_COMPLIANCE(x) ((x) << S_PIPE0_TX2_COMPLIANCE)
+#define F_PIPE0_TX2_COMPLIANCE    V_PIPE0_TX2_COMPLIANCE(1U)
+
+#define S_PIPE0_TX1_COMPLIANCE    25
+#define V_PIPE0_TX1_COMPLIANCE(x) ((x) << S_PIPE0_TX1_COMPLIANCE)
+#define F_PIPE0_TX1_COMPLIANCE    V_PIPE0_TX1_COMPLIANCE(1U)
+
+#define S_PIPE0_TX0_COMPLIANCE    24
+#define V_PIPE0_TX0_COMPLIANCE(x) ((x) << S_PIPE0_TX0_COMPLIANCE)
+#define F_PIPE0_TX0_COMPLIANCE    V_PIPE0_TX0_COMPLIANCE(1U)
+
+#define S_PIPE0_TX7_ELECIDLE    23
+#define V_PIPE0_TX7_ELECIDLE(x) ((x) << S_PIPE0_TX7_ELECIDLE)
+#define F_PIPE0_TX7_ELECIDLE    V_PIPE0_TX7_ELECIDLE(1U)
+
+#define S_PIPE0_TX6_ELECIDLE    22
+#define V_PIPE0_TX6_ELECIDLE(x) ((x) << S_PIPE0_TX6_ELECIDLE)
+#define F_PIPE0_TX6_ELECIDLE    V_PIPE0_TX6_ELECIDLE(1U)
+
+#define S_PIPE0_TX5_ELECIDLE    21
+#define V_PIPE0_TX5_ELECIDLE(x) ((x) << S_PIPE0_TX5_ELECIDLE)
+#define F_PIPE0_TX5_ELECIDLE    V_PIPE0_TX5_ELECIDLE(1U)
+
+#define S_PIPE0_TX4_ELECIDLE    20
+#define V_PIPE0_TX4_ELECIDLE(x) ((x) << S_PIPE0_TX4_ELECIDLE)
+#define F_PIPE0_TX4_ELECIDLE    V_PIPE0_TX4_ELECIDLE(1U)
+
+#define S_PIPE0_TX3_ELECIDLE    19
+#define V_PIPE0_TX3_ELECIDLE(x) ((x) << S_PIPE0_TX3_ELECIDLE)
+#define F_PIPE0_TX3_ELECIDLE    V_PIPE0_TX3_ELECIDLE(1U)
+
+#define S_PIPE0_TX2_ELECIDLE    18
+#define V_PIPE0_TX2_ELECIDLE(x) ((x) << S_PIPE0_TX2_ELECIDLE)
+#define F_PIPE0_TX2_ELECIDLE    V_PIPE0_TX2_ELECIDLE(1U)
+
+#define S_PIPE0_TX1_ELECIDLE    17
+#define V_PIPE0_TX1_ELECIDLE(x) ((x) << S_PIPE0_TX1_ELECIDLE)
+#define F_PIPE0_TX1_ELECIDLE    V_PIPE0_TX1_ELECIDLE(1U)
+
+#define S_PIPE0_TX0_ELECIDLE    16
+#define V_PIPE0_TX0_ELECIDLE(x) ((x) << S_PIPE0_TX0_ELECIDLE)
+#define F_PIPE0_TX0_ELECIDLE    V_PIPE0_TX0_ELECIDLE(1U)
+
+#define S_PIPE0_RX7_POLARITY_19    15
+#define V_PIPE0_RX7_POLARITY_19(x) ((x) << S_PIPE0_RX7_POLARITY_19)
+#define F_PIPE0_RX7_POLARITY_19    V_PIPE0_RX7_POLARITY_19(1U)
+
+#define S_PIPE0_RX6_POLARITY_19    14
+#define V_PIPE0_RX6_POLARITY_19(x) ((x) << S_PIPE0_RX6_POLARITY_19)
+#define F_PIPE0_RX6_POLARITY_19    V_PIPE0_RX6_POLARITY_19(1U)
+
+#define S_PIPE0_RX5_POLARITY_19    13
+#define V_PIPE0_RX5_POLARITY_19(x) ((x) << S_PIPE0_RX5_POLARITY_19)
+#define F_PIPE0_RX5_POLARITY_19    V_PIPE0_RX5_POLARITY_19(1U)
+
+#define S_PIPE0_RX4_POLARITY_19    12
+#define V_PIPE0_RX4_POLARITY_19(x) ((x) << S_PIPE0_RX4_POLARITY_19)
+#define F_PIPE0_RX4_POLARITY_19    V_PIPE0_RX4_POLARITY_19(1U)
+
+#define S_PIPE0_RX3_POLARITY_19    11
+#define V_PIPE0_RX3_POLARITY_19(x) ((x) << S_PIPE0_RX3_POLARITY_19)
+#define F_PIPE0_RX3_POLARITY_19    V_PIPE0_RX3_POLARITY_19(1U)
+
+#define S_PIPE0_RX2_POLARITY_19    10
+#define V_PIPE0_RX2_POLARITY_19(x) ((x) << S_PIPE0_RX2_POLARITY_19)
+#define F_PIPE0_RX2_POLARITY_19    V_PIPE0_RX2_POLARITY_19(1U)
+
+#define S_PIPE0_RX1_POLARITY_19    9
+#define V_PIPE0_RX1_POLARITY_19(x) ((x) << S_PIPE0_RX1_POLARITY_19)
+#define F_PIPE0_RX1_POLARITY_19    V_PIPE0_RX1_POLARITY_19(1U)
+
+#define S_PIPE0_RX0_POLARITY_19    8
+#define V_PIPE0_RX0_POLARITY_19(x) ((x) << S_PIPE0_RX0_POLARITY_19)
+#define F_PIPE0_RX0_POLARITY_19    V_PIPE0_RX0_POLARITY_19(1U)
+
+#define S_PIPE0_RX7_ELECIDLE    7
+#define V_PIPE0_RX7_ELECIDLE(x) ((x) << S_PIPE0_RX7_ELECIDLE)
+#define F_PIPE0_RX7_ELECIDLE    V_PIPE0_RX7_ELECIDLE(1U)
+
+#define S_PIPE0_RX6_ELECIDLE    6
+#define V_PIPE0_RX6_ELECIDLE(x) ((x) << S_PIPE0_RX6_ELECIDLE)
+#define F_PIPE0_RX6_ELECIDLE    V_PIPE0_RX6_ELECIDLE(1U)
+
+#define S_PIPE0_RX5_ELECIDLE    5
+#define V_PIPE0_RX5_ELECIDLE(x) ((x) << S_PIPE0_RX5_ELECIDLE)
+#define F_PIPE0_RX5_ELECIDLE    V_PIPE0_RX5_ELECIDLE(1U)
+
+#define S_PIPE0_RX4_ELECIDLE    4
+#define V_PIPE0_RX4_ELECIDLE(x) ((x) << S_PIPE0_RX4_ELECIDLE)
+#define F_PIPE0_RX4_ELECIDLE    V_PIPE0_RX4_ELECIDLE(1U)
+
+#define S_PIPE0_RX3_ELECIDLE    3
+#define V_PIPE0_RX3_ELECIDLE(x) ((x) << S_PIPE0_RX3_ELECIDLE)
+#define F_PIPE0_RX3_ELECIDLE    V_PIPE0_RX3_ELECIDLE(1U)
+
+#define S_PIPE0_RX2_ELECIDLE    2
+#define V_PIPE0_RX2_ELECIDLE(x) ((x) << S_PIPE0_RX2_ELECIDLE)
+#define F_PIPE0_RX2_ELECIDLE    V_PIPE0_RX2_ELECIDLE(1U)
+
+#define S_PIPE0_RX1_ELECIDLE    1
+#define V_PIPE0_RX1_ELECIDLE(x) ((x) << S_PIPE0_RX1_ELECIDLE)
+#define F_PIPE0_RX1_ELECIDLE    V_PIPE0_RX1_ELECIDLE(1U)
+
+#define S_PIPE0_RX0_ELECIDLE    0
+#define V_PIPE0_RX0_ELECIDLE(x) ((x) << S_PIPE0_RX0_ELECIDLE)
+#define F_PIPE0_RX0_ELECIDLE    V_PIPE0_RX0_ELECIDLE(1U)
+
+#define A_PCIE_PDEBUG_REG_0X1A 0x1a
+
+#define S_PIPE0_RESET_N    21
+#define V_PIPE0_RESET_N(x) ((x) << S_PIPE0_RESET_N)
+#define F_PIPE0_RESET_N    V_PIPE0_RESET_N(1U)
+
+#define S_PCS_COMMON_CLOCKS    20
+#define V_PCS_COMMON_CLOCKS(x) ((x) << S_PCS_COMMON_CLOCKS)
+#define F_PCS_COMMON_CLOCKS    V_PCS_COMMON_CLOCKS(1U)
+
+#define S_PCS_CLK_REQ    19
+#define V_PCS_CLK_REQ(x) ((x) << S_PCS_CLK_REQ)
+#define F_PCS_CLK_REQ    V_PCS_CLK_REQ(1U)
+
+#define S_PIPE_CLKREQ_N    18
+#define V_PIPE_CLKREQ_N(x) ((x) << S_PIPE_CLKREQ_N)
+#define F_PIPE_CLKREQ_N    V_PIPE_CLKREQ_N(1U)
+
+#define S_MAC_CLKREQ_N_TO_MUX    17
+#define V_MAC_CLKREQ_N_TO_MUX(x) ((x) << S_MAC_CLKREQ_N_TO_MUX)
+#define F_MAC_CLKREQ_N_TO_MUX    V_MAC_CLKREQ_N_TO_MUX(1U)
+
+#define S_PIPE0_TX2RX_LOOPBK    16
+#define V_PIPE0_TX2RX_LOOPBK(x) ((x) << S_PIPE0_TX2RX_LOOPBK)
+#define F_PIPE0_TX2RX_LOOPBK    V_PIPE0_TX2RX_LOOPBK(1U)
+
+#define S_PIPE0_TX_SWING    15
+#define V_PIPE0_TX_SWING(x) ((x) << S_PIPE0_TX_SWING)
+#define F_PIPE0_TX_SWING    V_PIPE0_TX_SWING(1U)
+
+#define S_PIPE0_TX_MARGIN    12
+#define M_PIPE0_TX_MARGIN    0x7U
+#define V_PIPE0_TX_MARGIN(x) ((x) << S_PIPE0_TX_MARGIN)
+#define G_PIPE0_TX_MARGIN(x) (((x) >> S_PIPE0_TX_MARGIN) & M_PIPE0_TX_MARGIN)
+
+#define S_PIPE0_TX_DEEMPH    11
+#define V_PIPE0_TX_DEEMPH(x) ((x) << S_PIPE0_TX_DEEMPH)
+#define F_PIPE0_TX_DEEMPH    V_PIPE0_TX_DEEMPH(1U)
+
+#define S_PIPE0_TX_DETECTRX    10
+#define V_PIPE0_TX_DETECTRX(x) ((x) << S_PIPE0_TX_DETECTRX)
+#define F_PIPE0_TX_DETECTRX    V_PIPE0_TX_DETECTRX(1U)
+
+#define S_PIPE0_POWERDOWN    8
+#define M_PIPE0_POWERDOWN    0x3U
+#define V_PIPE0_POWERDOWN(x) ((x) << S_PIPE0_POWERDOWN)
+#define G_PIPE0_POWERDOWN(x) (((x) >> S_PIPE0_POWERDOWN) & M_PIPE0_POWERDOWN)
+
+#define S_PHY_MAC_PHYSTATUS    0
+#define M_PHY_MAC_PHYSTATUS    0xffU
+#define V_PHY_MAC_PHYSTATUS(x) ((x) << S_PHY_MAC_PHYSTATUS)
+#define G_PHY_MAC_PHYSTATUS(x) (((x) >> S_PHY_MAC_PHYSTATUS) & M_PHY_MAC_PHYSTATUS)
+
+#define A_PCIE_PDEBUG_REG_0X1B 0x1b
+
+#define S_PIPE0_RX7_EQ_IN_PROG    31
+#define V_PIPE0_RX7_EQ_IN_PROG(x) ((x) << S_PIPE0_RX7_EQ_IN_PROG)
+#define F_PIPE0_RX7_EQ_IN_PROG    V_PIPE0_RX7_EQ_IN_PROG(1U)
+
+#define S_PIPE0_RX7_EQ_INVLD_REQ    30
+#define V_PIPE0_RX7_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX7_EQ_INVLD_REQ)
+#define F_PIPE0_RX7_EQ_INVLD_REQ    V_PIPE0_RX7_EQ_INVLD_REQ(1U)
+
+#define S_PIPE0_RX7_SYNCHEADER    28
+#define M_PIPE0_RX7_SYNCHEADER    0x3U
+#define V_PIPE0_RX7_SYNCHEADER(x) ((x) << S_PIPE0_RX7_SYNCHEADER)
+#define G_PIPE0_RX7_SYNCHEADER(x) (((x) >> S_PIPE0_RX7_SYNCHEADER) & M_PIPE0_RX7_SYNCHEADER)
+
+#define S_PIPE0_RX6_EQ_IN_PROG    27
+#define V_PIPE0_RX6_EQ_IN_PROG(x) ((x) << S_PIPE0_RX6_EQ_IN_PROG)
+#define F_PIPE0_RX6_EQ_IN_PROG    V_PIPE0_RX6_EQ_IN_PROG(1U)
+
+#define S_PIPE0_RX6_EQ_INVLD_REQ    26
+#define V_PIPE0_RX6_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX6_EQ_INVLD_REQ)
+#define F_PIPE0_RX6_EQ_INVLD_REQ    V_PIPE0_RX6_EQ_INVLD_REQ(1U)
+
+#define S_PIPE0_RX6_SYNCHEADER    24
+#define M_PIPE0_RX6_SYNCHEADER    0x3U
+#define V_PIPE0_RX6_SYNCHEADER(x) ((x) << S_PIPE0_RX6_SYNCHEADER)
+#define G_PIPE0_RX6_SYNCHEADER(x) (((x) >> S_PIPE0_RX6_SYNCHEADER) & M_PIPE0_RX6_SYNCHEADER)
+
+#define S_PIPE0_RX5_EQ_IN_PROG    23
+#define V_PIPE0_RX5_EQ_IN_PROG(x) ((x) << S_PIPE0_RX5_EQ_IN_PROG)
+#define F_PIPE0_RX5_EQ_IN_PROG    V_PIPE0_RX5_EQ_IN_PROG(1U)
+
+#define S_PIPE0_RX5_EQ_INVLD_REQ    22
+#define V_PIPE0_RX5_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX5_EQ_INVLD_REQ)
+#define F_PIPE0_RX5_EQ_INVLD_REQ    V_PIPE0_RX5_EQ_INVLD_REQ(1U)
+
+#define S_PIPE0_RX5_SYNCHEADER    20
+#define M_PIPE0_RX5_SYNCHEADER    0x3U
+#define V_PIPE0_RX5_SYNCHEADER(x) ((x) << S_PIPE0_RX5_SYNCHEADER)
+#define G_PIPE0_RX5_SYNCHEADER(x) (((x) >> S_PIPE0_RX5_SYNCHEADER) & M_PIPE0_RX5_SYNCHEADER)
+
+#define S_PIPE0_RX4_EQ_IN_PROG    19
+#define V_PIPE0_RX4_EQ_IN_PROG(x) ((x) << S_PIPE0_RX4_EQ_IN_PROG)
+#define F_PIPE0_RX4_EQ_IN_PROG    V_PIPE0_RX4_EQ_IN_PROG(1U)
+
+#define S_PIPE0_RX4_EQ_INVLD_REQ    18
+#define V_PIPE0_RX4_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX4_EQ_INVLD_REQ)
+#define F_PIPE0_RX4_EQ_INVLD_REQ    V_PIPE0_RX4_EQ_INVLD_REQ(1U)
+
+#define S_PIPE0_RX4_SYNCHEADER    16
+#define M_PIPE0_RX4_SYNCHEADER    0x3U
+#define V_PIPE0_RX4_SYNCHEADER(x) ((x) << S_PIPE0_RX4_SYNCHEADER)
+#define G_PIPE0_RX4_SYNCHEADER(x) (((x) >> S_PIPE0_RX4_SYNCHEADER) & M_PIPE0_RX4_SYNCHEADER)
+
+#define S_PIPE0_RX3_EQ_IN_PROG    15
+#define V_PIPE0_RX3_EQ_IN_PROG(x) ((x) << S_PIPE0_RX3_EQ_IN_PROG)
+#define F_PIPE0_RX3_EQ_IN_PROG    V_PIPE0_RX3_EQ_IN_PROG(1U)
+
+#define S_PIPE0_RX3_EQ_INVLD_REQ    14
+#define V_PIPE0_RX3_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX3_EQ_INVLD_REQ)
+#define F_PIPE0_RX3_EQ_INVLD_REQ    V_PIPE0_RX3_EQ_INVLD_REQ(1U)
+
+#define S_PIPE0_RX3_SYNCHEADER    12
+#define M_PIPE0_RX3_SYNCHEADER    0x3U
+#define V_PIPE0_RX3_SYNCHEADER(x) ((x) << S_PIPE0_RX3_SYNCHEADER)
+#define G_PIPE0_RX3_SYNCHEADER(x) (((x) >> S_PIPE0_RX3_SYNCHEADER) & M_PIPE0_RX3_SYNCHEADER)
+
+#define S_PIPE0_RX2_EQ_IN_PROG    11
+#define V_PIPE0_RX2_EQ_IN_PROG(x) ((x) << S_PIPE0_RX2_EQ_IN_PROG)
+#define F_PIPE0_RX2_EQ_IN_PROG    V_PIPE0_RX2_EQ_IN_PROG(1U)
+
+#define S_PIPE0_RX2_EQ_INVLD_REQ    10
+#define V_PIPE0_RX2_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX2_EQ_INVLD_REQ)
+#define F_PIPE0_RX2_EQ_INVLD_REQ    V_PIPE0_RX2_EQ_INVLD_REQ(1U)
+
+#define S_PIPE0_RX2_SYNCHEADER    8
+#define M_PIPE0_RX2_SYNCHEADER    0x3U
+#define V_PIPE0_RX2_SYNCHEADER(x) ((x) << S_PIPE0_RX2_SYNCHEADER)
+#define G_PIPE0_RX2_SYNCHEADER(x) (((x) >> S_PIPE0_RX2_SYNCHEADER) & M_PIPE0_RX2_SYNCHEADER)
+
+#define S_PIPE0_RX1_EQ_IN_PROG    7
+#define V_PIPE0_RX1_EQ_IN_PROG(x) ((x) << S_PIPE0_RX1_EQ_IN_PROG)
+#define F_PIPE0_RX1_EQ_IN_PROG    V_PIPE0_RX1_EQ_IN_PROG(1U)
+
+#define S_PIPE0_RX1_EQ_INVLD_REQ    6
+#define V_PIPE0_RX1_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX1_EQ_INVLD_REQ)
+#define F_PIPE0_RX1_EQ_INVLD_REQ    V_PIPE0_RX1_EQ_INVLD_REQ(1U)
+
+#define S_PIPE0_RX1_SYNCHEADER    4
+#define M_PIPE0_RX1_SYNCHEADER    0x3U
+#define V_PIPE0_RX1_SYNCHEADER(x) ((x) << S_PIPE0_RX1_SYNCHEADER)
+#define G_PIPE0_RX1_SYNCHEADER(x) (((x) >> S_PIPE0_RX1_SYNCHEADER) & M_PIPE0_RX1_SYNCHEADER)
+
+#define S_PIPE0_RX0_EQ_IN_PROG    3
+#define V_PIPE0_RX0_EQ_IN_PROG(x) ((x) << S_PIPE0_RX0_EQ_IN_PROG)
+#define F_PIPE0_RX0_EQ_IN_PROG    V_PIPE0_RX0_EQ_IN_PROG(1U)
+
+#define S_PIPE0_RX0_EQ_INVLD_REQ    2
+#define V_PIPE0_RX0_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX0_EQ_INVLD_REQ)
+#define F_PIPE0_RX0_EQ_INVLD_REQ    V_PIPE0_RX0_EQ_INVLD_REQ(1U)
+
+#define S_PIPE0_RX0_SYNCHEADER    0
+#define M_PIPE0_RX0_SYNCHEADER    0x3U
+#define V_PIPE0_RX0_SYNCHEADER(x) ((x) << S_PIPE0_RX0_SYNCHEADER)
+#define G_PIPE0_RX0_SYNCHEADER(x) (((x) >> S_PIPE0_RX0_SYNCHEADER) & M_PIPE0_RX0_SYNCHEADER)
+
+#define A_PCIE_PDEBUG_REG_0X1C 0x1c
+
+#define S_SI_REQVFID    24
+#define M_SI_REQVFID    0xffU
+#define V_SI_REQVFID(x) ((x) << S_SI_REQVFID)
+#define G_SI_REQVFID(x) (((x) >> S_SI_REQVFID) & M_SI_REQVFID)
+
+#define S_SI_REQVEC    13
+#define M_SI_REQVEC    0x7ffU
+#define V_SI_REQVEC(x) ((x) << S_SI_REQVEC)
+#define G_SI_REQVEC(x) (((x) >> S_SI_REQVEC) & M_SI_REQVEC)
+
+#define S_SI_REQTCVAL    10
+#define M_SI_REQTCVAL    0x7U
+#define V_SI_REQTCVAL(x) ((x) << S_SI_REQTCVAL)
+#define G_SI_REQTCVAL(x) (((x) >> S_SI_REQTCVAL) & M_SI_REQTCVAL)
+
+#define S_SI_REQRDY    9
+#define V_SI_REQRDY(x) ((x) << S_SI_REQRDY)
+#define F_SI_REQRDY    V_SI_REQRDY(1U)
+
+#define S_SI_REQVLD    8
+#define V_SI_REQVLD(x) ((x) << S_SI_REQVLD)
+#define F_SI_REQVLD    V_SI_REQVLD(1U)
+
+#define S_T5_AI    0
+#define M_T5_AI    0xffU
+#define V_T5_AI(x) ((x) << S_T5_AI)
+#define G_T5_AI(x) (((x) >> S_T5_AI) & M_T5_AI)
+
+#define A_PCIE_PDEBUG_REG_0X1D 0x1d
+
+#define S_GNTSI    31
+#define V_GNTSI(x) ((x) << S_GNTSI)
+#define F_GNTSI    V_GNTSI(1U)
+
+#define S_DROPINTFORFLR    30
+#define V_DROPINTFORFLR(x) ((x) << S_DROPINTFORFLR)
+#define F_DROPINTFORFLR    V_DROPINTFORFLR(1U)
+
+#define S_SMARB    27
+#define M_SMARB    0x7U
+#define V_SMARB(x) ((x) << S_SMARB)
+#define G_SMARB(x) (((x) >> S_SMARB) & M_SMARB)
+
+#define S_SMDEFR    24
+#define M_SMDEFR    0x7U
+#define V_SMDEFR(x) ((x) << S_SMDEFR)
+#define G_SMDEFR(x) (((x) >> S_SMDEFR) & M_SMDEFR)
+
+#define S_SYS_INT    16
+#define M_SYS_INT    0xffU
+#define V_SYS_INT(x) ((x) << S_SYS_INT)
+#define G_SYS_INT(x) (((x) >> S_SYS_INT) & M_SYS_INT)
+
+#define S_CFG_INTXCLR    8
+#define M_CFG_INTXCLR    0xffU
+#define V_CFG_INTXCLR(x) ((x) << S_CFG_INTXCLR)
+#define G_CFG_INTXCLR(x) (((x) >> S_CFG_INTXCLR) & M_CFG_INTXCLR)
+
+#define S_PIO_INTXCLR    0
+#define M_PIO_INTXCLR    0xffU
+#define V_PIO_INTXCLR(x) ((x) << S_PIO_INTXCLR)
+#define G_PIO_INTXCLR(x) (((x) >> S_PIO_INTXCLR) & M_PIO_INTXCLR)
+
+#define A_PCIE_PDEBUG_REG_0X1E 0x1e
+
+#define S_PLI_TABDATWREN    31
+#define V_PLI_TABDATWREN(x) ((x) << S_PLI_TABDATWREN)
+#define F_PLI_TABDATWREN    V_PLI_TABDATWREN(1U)
+
+#define S_TAB_RDENA    30
+#define V_TAB_RDENA(x) ((x) << S_TAB_RDENA)
+#define F_TAB_RDENA    V_TAB_RDENA(1U)
+
+#define S_TAB_RDENA2    19
+#define M_TAB_RDENA2    0x7ffU
+#define V_TAB_RDENA2(x) ((x) << S_TAB_RDENA2)
+#define G_TAB_RDENA2(x) (((x) >> S_TAB_RDENA2) & M_TAB_RDENA2)
+
+#define S_PLI_REQADDR    10
+#define M_PLI_REQADDR    0x1ffU
+#define V_PLI_REQADDR(x) ((x) << S_PLI_REQADDR)
+#define G_PLI_REQADDR(x) (((x) >> S_PLI_REQADDR) & M_PLI_REQADDR)
+
+#define S_PLI_REQVFID    2
+#define M_PLI_REQVFID    0xffU
+#define V_PLI_REQVFID(x) ((x) << S_PLI_REQVFID)
+#define G_PLI_REQVFID(x) (((x) >> S_PLI_REQVFID) & M_PLI_REQVFID)
+
+#define S_PLI_REQTABHIT    1
+#define V_PLI_REQTABHIT(x) ((x) << S_PLI_REQTABHIT)
+#define F_PLI_REQTABHIT    V_PLI_REQTABHIT(1U)
+
+#define S_PLI_REQRDVLD    0
+#define V_PLI_REQRDVLD(x) ((x) << S_PLI_REQRDVLD)
+#define F_PLI_REQRDVLD    V_PLI_REQRDVLD(1U)
+
+#define A_PCIE_PDEBUG_REG_0X1F 0x1f
+#define A_PCIE_PDEBUG_REG_0X20 0x20
+#define A_PCIE_PDEBUG_REG_0X21 0x21
+
+#define S_PLI_REQPBASTART    20
+#define M_PLI_REQPBASTART    0xfffU
+#define V_PLI_REQPBASTART(x) ((x) << S_PLI_REQPBASTART)
+#define G_PLI_REQPBASTART(x) (((x) >> S_PLI_REQPBASTART) & M_PLI_REQPBASTART)
+
+#define S_PLI_REQPBAEND    9
+#define M_PLI_REQPBAEND    0x7ffU
+#define V_PLI_REQPBAEND(x) ((x) << S_PLI_REQPBAEND)
+#define G_PLI_REQPBAEND(x) (((x) >> S_PLI_REQPBAEND) & M_PLI_REQPBAEND)
+
+#define S_T5_PLI_REQVFID    2
+#define M_T5_PLI_REQVFID    0x7fU
+#define V_T5_PLI_REQVFID(x) ((x) << S_T5_PLI_REQVFID)
+#define G_T5_PLI_REQVFID(x) (((x) >> S_T5_PLI_REQVFID) & M_T5_PLI_REQVFID)
+
+#define S_PLI_REQPBAHIT    1
+#define V_PLI_REQPBAHIT(x) ((x) << S_PLI_REQPBAHIT)
+#define F_PLI_REQPBAHIT    V_PLI_REQPBAHIT(1U)
+
+#define A_PCIE_PDEBUG_REG_0X22 0x22
+
+#define S_GNTSI1    31
+#define V_GNTSI1(x) ((x) << S_GNTSI1)
+#define F_GNTSI1    V_GNTSI1(1U)
+
+#define S_GNTSI2    30
+#define V_GNTSI2(x) ((x) << S_GNTSI2)
+#define F_GNTSI2    V_GNTSI2(1U)
+
+#define S_GNTSI3    27
+#define M_GNTSI3    0x7U
+#define V_GNTSI3(x) ((x) << S_GNTSI3)
+#define G_GNTSI3(x) (((x) >> S_GNTSI3) & M_GNTSI3)
+
+#define S_GNTSI4    16
+#define M_GNTSI4    0x7ffU
+#define V_GNTSI4(x) ((x) << S_GNTSI4)
+#define G_GNTSI4(x) (((x) >> S_GNTSI4) & M_GNTSI4)
+
+#define S_GNTSI5    8
+#define M_GNTSI5    0xffU
+#define V_GNTSI5(x) ((x) << S_GNTSI5)
+#define G_GNTSI5(x) (((x) >> S_GNTSI5) & M_GNTSI5)
+
+#define S_GNTSI6    7
+#define V_GNTSI6(x) ((x) << S_GNTSI6)
+#define F_GNTSI6    V_GNTSI6(1U)
+
+#define S_GNTSI7    6
+#define V_GNTSI7(x) ((x) << S_GNTSI7)
+#define F_GNTSI7    V_GNTSI7(1U)
+
+#define S_GNTSI8    5
+#define V_GNTSI8(x) ((x) << S_GNTSI8)
+#define F_GNTSI8    V_GNTSI8(1U)
+
+#define S_GNTSI9    4
+#define V_GNTSI9(x) ((x) << S_GNTSI9)
+#define F_GNTSI9    V_GNTSI9(1U)
+
+#define S_GNTSIA    3
+#define V_GNTSIA(x) ((x) << S_GNTSIA)
+#define F_GNTSIA    V_GNTSIA(1U)
+
+#define S_GNTAI    2
+#define V_GNTAI(x) ((x) << S_GNTAI)
+#define F_GNTAI    V_GNTAI(1U)
+
+#define S_GNTDB    1
+#define V_GNTDB(x) ((x) << S_GNTDB)
+#define F_GNTDB    V_GNTDB(1U)
+
+#define S_GNTDI    0
+#define V_GNTDI(x) ((x) << S_GNTDI)
+#define F_GNTDI    V_GNTDI(1U)
+
+#define A_PCIE_PDEBUG_REG_0X23 0x23
+
+#define S_DI_REQVLD    31
+#define V_DI_REQVLD(x) ((x) << S_DI_REQVLD)
+#define F_DI_REQVLD    V_DI_REQVLD(1U)
+
+#define S_DI_REQRDY    30
+#define V_DI_REQRDY(x) ((x) << S_DI_REQRDY)
+#define F_DI_REQRDY    V_DI_REQRDY(1U)
+
+#define S_DI_REQWREN    19
+#define M_DI_REQWREN    0x7ffU
+#define V_DI_REQWREN(x) ((x) << S_DI_REQWREN)
+#define G_DI_REQWREN(x) (((x) >> S_DI_REQWREN) & M_DI_REQWREN)
+
+#define S_DI_REQMSIEN    18
+#define V_DI_REQMSIEN(x) ((x) << S_DI_REQMSIEN)
+#define F_DI_REQMSIEN    V_DI_REQMSIEN(1U)
+
+#define S_DI_REQMSXEN    17
+#define V_DI_REQMSXEN(x) ((x) << S_DI_REQMSXEN)
+#define F_DI_REQMSXEN    V_DI_REQMSXEN(1U)
+
+#define S_DI_REQMSXVFIDMSK    16
+#define V_DI_REQMSXVFIDMSK(x) ((x) << S_DI_REQMSXVFIDMSK)
+#define F_DI_REQMSXVFIDMSK    V_DI_REQMSXVFIDMSK(1U)
+
+#define S_DI_REQWREN2    2
+#define M_DI_REQWREN2    0x3fffU
+#define V_DI_REQWREN2(x) ((x) << S_DI_REQWREN2)
+#define G_DI_REQWREN2(x) (((x) >> S_DI_REQWREN2) & M_DI_REQWREN2)
+
+#define S_DI_REQRDEN    1
+#define V_DI_REQRDEN(x) ((x) << S_DI_REQRDEN)
+#define F_DI_REQRDEN    V_DI_REQRDEN(1U)
+
+#define S_DI_REQWREN3    0
+#define V_DI_REQWREN3(x) ((x) << S_DI_REQWREN3)
+#define F_DI_REQWREN3    V_DI_REQWREN3(1U)
+
+#define A_PCIE_PDEBUG_REG_0X24 0x24
+#define A_PCIE_PDEBUG_REG_0X25 0x25
+#define A_PCIE_PDEBUG_REG_0X26 0x26
+#define A_PCIE_PDEBUG_REG_0X27 0x27
+
+#define S_FID_STI_RSPVLD    31
+#define V_FID_STI_RSPVLD(x) ((x) << S_FID_STI_RSPVLD)
+#define F_FID_STI_RSPVLD    V_FID_STI_RSPVLD(1U)
+
+#define S_TAB_STIRDENA    30
+#define V_TAB_STIRDENA(x) ((x) << S_TAB_STIRDENA)
+#define F_TAB_STIRDENA    V_TAB_STIRDENA(1U)
+
+#define S_TAB_STIWRENA    29
+#define V_TAB_STIWRENA(x) ((x) << S_TAB_STIWRENA)
+#define F_TAB_STIWRENA    V_TAB_STIWRENA(1U)
+
+#define S_TAB_STIRDENA2    18
+#define M_TAB_STIRDENA2    0x7ffU
+#define V_TAB_STIRDENA2(x) ((x) << S_TAB_STIRDENA2)
+#define G_TAB_STIRDENA2(x) (((x) >> S_TAB_STIRDENA2) & M_TAB_STIRDENA2)
+
+#define S_T5_PLI_REQTABHIT    7
+#define M_T5_PLI_REQTABHIT    0x7ffU
+#define V_T5_PLI_REQTABHIT(x) ((x) << S_T5_PLI_REQTABHIT)
+#define G_T5_PLI_REQTABHIT(x) (((x) >> S_T5_PLI_REQTABHIT) & M_T5_PLI_REQTABHIT)
+
+#define S_T5_GNTSI    0
+#define M_T5_GNTSI    0x7fU
+#define V_T5_GNTSI(x) ((x) << S_T5_GNTSI)
+#define G_T5_GNTSI(x) (((x) >> S_T5_GNTSI) & M_T5_GNTSI)
+
+#define A_PCIE_PDEBUG_REG_0X28 0x28
+
+#define S_PLI_REQWRVLD    31
+#define V_PLI_REQWRVLD(x) ((x) << S_PLI_REQWRVLD)
+#define F_PLI_REQWRVLD    V_PLI_REQWRVLD(1U)
+
+#define S_T5_PLI_REQPBAHIT    30
+#define V_T5_PLI_REQPBAHIT(x) ((x) << S_T5_PLI_REQPBAHIT)
+#define F_T5_PLI_REQPBAHIT    V_T5_PLI_REQPBAHIT(1U)
+
+#define S_PLI_TABADDRLWREN    29
+#define V_PLI_TABADDRLWREN(x) ((x) << S_PLI_TABADDRLWREN)
+#define F_PLI_TABADDRLWREN    V_PLI_TABADDRLWREN(1U)
+
+#define S_PLI_TABADDRHWREN    28
+#define V_PLI_TABADDRHWREN(x) ((x) << S_PLI_TABADDRHWREN)
+#define F_PLI_TABADDRHWREN    V_PLI_TABADDRHWREN(1U)
+
+#define S_T5_PLI_TABDATWREN    27
+#define V_T5_PLI_TABDATWREN(x) ((x) << S_T5_PLI_TABDATWREN)
+#define F_T5_PLI_TABDATWREN    V_T5_PLI_TABDATWREN(1U)
+
+#define S_PLI_TABMSKWREN    26
+#define V_PLI_TABMSKWREN(x) ((x) << S_PLI_TABMSKWREN)
+#define F_PLI_TABMSKWREN    V_PLI_TABMSKWREN(1U)
+
+#define S_AI_REQVLD    23
+#define M_AI_REQVLD    0x7U
+#define V_AI_REQVLD(x) ((x) << S_AI_REQVLD)
+#define G_AI_REQVLD(x) (((x) >> S_AI_REQVLD) & M_AI_REQVLD)
+
+#define S_AI_REQVLD2    22
+#define V_AI_REQVLD2(x) ((x) << S_AI_REQVLD2)
+#define F_AI_REQVLD2    V_AI_REQVLD2(1U)
+
+#define S_AI_REQRDY    21
+#define V_AI_REQRDY(x) ((x) << S_AI_REQRDY)
+#define F_AI_REQRDY    V_AI_REQRDY(1U)
+
+#define S_VEN_MSI_REQ_28    18
+#define M_VEN_MSI_REQ_28    0x7U
+#define V_VEN_MSI_REQ_28(x) ((x) << S_VEN_MSI_REQ_28)
+#define G_VEN_MSI_REQ_28(x) (((x) >> S_VEN_MSI_REQ_28) & M_VEN_MSI_REQ_28)
+
+#define S_VEN_MSI_REQ2    11
+#define M_VEN_MSI_REQ2    0x7fU
+#define V_VEN_MSI_REQ2(x) ((x) << S_VEN_MSI_REQ2)
+#define G_VEN_MSI_REQ2(x) (((x) >> S_VEN_MSI_REQ2) & M_VEN_MSI_REQ2)
+
+#define S_VEN_MSI_REQ3    6
+#define M_VEN_MSI_REQ3    0x1fU
+#define V_VEN_MSI_REQ3(x) ((x) << S_VEN_MSI_REQ3)
+#define G_VEN_MSI_REQ3(x) (((x) >> S_VEN_MSI_REQ3) & M_VEN_MSI_REQ3)
+
+#define S_VEN_MSI_REQ4    3
+#define M_VEN_MSI_REQ4    0x7U
+#define V_VEN_MSI_REQ4(x) ((x) << S_VEN_MSI_REQ4)
+#define G_VEN_MSI_REQ4(x) (((x) >> S_VEN_MSI_REQ4) & M_VEN_MSI_REQ4)
+
+#define S_VEN_MSI_REQ5    2
+#define V_VEN_MSI_REQ5(x) ((x) << S_VEN_MSI_REQ5)
+#define F_VEN_MSI_REQ5    V_VEN_MSI_REQ5(1U)
+
+#define S_VEN_MSI_GRANT    1
+#define V_VEN_MSI_GRANT(x) ((x) << S_VEN_MSI_GRANT)
+#define F_VEN_MSI_GRANT    V_VEN_MSI_GRANT(1U)
+
+#define S_VEN_MSI_REQ6    0
+#define V_VEN_MSI_REQ6(x) ((x) << S_VEN_MSI_REQ6)
+#define F_VEN_MSI_REQ6    V_VEN_MSI_REQ6(1U)
+
+#define A_PCIE_PDEBUG_REG_0X29 0x29
+
+#define S_TRGT1_REQDATAVLD    16
+#define M_TRGT1_REQDATAVLD    0xffffU
+#define V_TRGT1_REQDATAVLD(x) ((x) << S_TRGT1_REQDATAVLD)
+#define G_TRGT1_REQDATAVLD(x) (((x) >> S_TRGT1_REQDATAVLD) & M_TRGT1_REQDATAVLD)
+
+#define S_TRGT1_REQDATAVLD2    12
+#define M_TRGT1_REQDATAVLD2    0xfU
+#define V_TRGT1_REQDATAVLD2(x) ((x) << S_TRGT1_REQDATAVLD2)
+#define G_TRGT1_REQDATAVLD2(x) (((x) >> S_TRGT1_REQDATAVLD2) & M_TRGT1_REQDATAVLD2)
+
+#define S_TRGT1_REQDATAVLD3    11
+#define V_TRGT1_REQDATAVLD3(x) ((x) << S_TRGT1_REQDATAVLD3)
+#define F_TRGT1_REQDATAVLD3    V_TRGT1_REQDATAVLD3(1U)
+
+#define S_TRGT1_REQDATAVLD4    10
+#define V_TRGT1_REQDATAVLD4(x) ((x) << S_TRGT1_REQDATAVLD4)
+#define F_TRGT1_REQDATAVLD4    V_TRGT1_REQDATAVLD4(1U)
+
+#define S_TRGT1_REQDATAVLD5    9
+#define V_TRGT1_REQDATAVLD5(x) ((x) << S_TRGT1_REQDATAVLD5)
+#define F_TRGT1_REQDATAVLD5    V_TRGT1_REQDATAVLD5(1U)
+
+#define S_TRGT1_REQDATAVLD6    8
+#define V_TRGT1_REQDATAVLD6(x) ((x) << S_TRGT1_REQDATAVLD6)
+#define F_TRGT1_REQDATAVLD6    V_TRGT1_REQDATAVLD6(1U)
+
+#define S_TRGT1_REQDATAVLD7    4
+#define M_TRGT1_REQDATAVLD7    0xfU
+#define V_TRGT1_REQDATAVLD7(x) ((x) << S_TRGT1_REQDATAVLD7)
+#define G_TRGT1_REQDATAVLD7(x) (((x) >> S_TRGT1_REQDATAVLD7) & M_TRGT1_REQDATAVLD7)
+
+#define S_TRGT1_REQDATAVLD8    2
+#define M_TRGT1_REQDATAVLD8    0x3U
+#define V_TRGT1_REQDATAVLD8(x) ((x) << S_TRGT1_REQDATAVLD8)
+#define G_TRGT1_REQDATAVLD8(x) (((x) >> S_TRGT1_REQDATAVLD8) & M_TRGT1_REQDATAVLD8)
+
+#define S_TRGT1_REQDATARDY    1
+#define V_TRGT1_REQDATARDY(x) ((x) << S_TRGT1_REQDATARDY)
+#define F_TRGT1_REQDATARDY    V_TRGT1_REQDATARDY(1U)
+
+#define S_TRGT1_REQDATAVLD0    0
+#define V_TRGT1_REQDATAVLD0(x) ((x) << S_TRGT1_REQDATAVLD0)
+#define F_TRGT1_REQDATAVLD0    V_TRGT1_REQDATAVLD0(1U)
+
+#define A_PCIE_PDEBUG_REG_0X2A 0x2a
+#define A_PCIE_PDEBUG_REG_0X2B 0x2b
+
+#define S_RADM_TRGT1_ADDR    20
+#define M_RADM_TRGT1_ADDR    0xfffU
+#define V_RADM_TRGT1_ADDR(x) ((x) << S_RADM_TRGT1_ADDR)
+#define G_RADM_TRGT1_ADDR(x) (((x) >> S_RADM_TRGT1_ADDR) & M_RADM_TRGT1_ADDR)
+
+#define S_RADM_TRGT1_DWEN    16
+#define M_RADM_TRGT1_DWEN    0xfU
+#define V_RADM_TRGT1_DWEN(x) ((x) << S_RADM_TRGT1_DWEN)
+#define G_RADM_TRGT1_DWEN(x) (((x) >> S_RADM_TRGT1_DWEN) & M_RADM_TRGT1_DWEN)
+
+#define S_RADM_TRGT1_FMT    14
+#define M_RADM_TRGT1_FMT    0x3U
+#define V_RADM_TRGT1_FMT(x) ((x) << S_RADM_TRGT1_FMT)
+#define G_RADM_TRGT1_FMT(x) (((x) >> S_RADM_TRGT1_FMT) & M_RADM_TRGT1_FMT)
+
+#define S_RADM_TRGT1_TYPE    9
+#define M_RADM_TRGT1_TYPE    0x1fU
+#define V_RADM_TRGT1_TYPE(x) ((x) << S_RADM_TRGT1_TYPE)
+#define G_RADM_TRGT1_TYPE(x) (((x) >> S_RADM_TRGT1_TYPE) & M_RADM_TRGT1_TYPE)
+
+#define S_RADM_TRGT1_IN_MEMBAR_RANGE    6
+#define M_RADM_TRGT1_IN_MEMBAR_RANGE    0x7U
+#define V_RADM_TRGT1_IN_MEMBAR_RANGE(x) ((x) << S_RADM_TRGT1_IN_MEMBAR_RANGE)
+#define G_RADM_TRGT1_IN_MEMBAR_RANGE(x) (((x) >> S_RADM_TRGT1_IN_MEMBAR_RANGE) & M_RADM_TRGT1_IN_MEMBAR_RANGE)
+
+#define S_RADM_TRGT1_ECRC_ERR    5
+#define V_RADM_TRGT1_ECRC_ERR(x) ((x) << S_RADM_TRGT1_ECRC_ERR)
+#define F_RADM_TRGT1_ECRC_ERR    V_RADM_TRGT1_ECRC_ERR(1U)
+
+#define S_RADM_TRGT1_DLLP_ABORT    4
+#define V_RADM_TRGT1_DLLP_ABORT(x) ((x) << S_RADM_TRGT1_DLLP_ABORT)
+#define F_RADM_TRGT1_DLLP_ABORT    V_RADM_TRGT1_DLLP_ABORT(1U)
+
+#define S_RADM_TRGT1_TLP_ABORT    3
+#define V_RADM_TRGT1_TLP_ABORT(x) ((x) << S_RADM_TRGT1_TLP_ABORT)
+#define F_RADM_TRGT1_TLP_ABORT    V_RADM_TRGT1_TLP_ABORT(1U)
+
+#define S_RADM_TRGT1_EOT    2
+#define V_RADM_TRGT1_EOT(x) ((x) << S_RADM_TRGT1_EOT)
+#define F_RADM_TRGT1_EOT    V_RADM_TRGT1_EOT(1U)
+
+#define S_RADM_TRGT1_DV_2B    1
+#define V_RADM_TRGT1_DV_2B(x) ((x) << S_RADM_TRGT1_DV_2B)
+#define F_RADM_TRGT1_DV_2B    V_RADM_TRGT1_DV_2B(1U)
+
+#define S_RADM_TRGT1_HV_2B    0
+#define V_RADM_TRGT1_HV_2B(x) ((x) << S_RADM_TRGT1_HV_2B)
+#define F_RADM_TRGT1_HV_2B    V_RADM_TRGT1_HV_2B(1U)
+
+#define A_PCIE_PDEBUG_REG_0X2C 0x2c
+
+#define S_STATEMPIO    29
+#define M_STATEMPIO    0x7U
+#define V_STATEMPIO(x) ((x) << S_STATEMPIO)
+#define G_STATEMPIO(x) (((x) >> S_STATEMPIO) & M_STATEMPIO)
+
+#define S_STATECPL    25
+#define M_STATECPL    0xfU
+#define V_STATECPL(x) ((x) << S_STATECPL)
+#define G_STATECPL(x) (((x) >> S_STATECPL) & M_STATECPL)
+
+#define S_STATEALIN    22
+#define M_STATEALIN    0x7U
+#define V_STATEALIN(x) ((x) << S_STATEALIN)
+#define G_STATEALIN(x) (((x) >> S_STATEALIN) & M_STATEALIN)
+
+#define S_STATEPL    19
+#define M_STATEPL    0x7U
+#define V_STATEPL(x) ((x) << S_STATEPL)
+#define G_STATEPL(x) (((x) >> S_STATEPL) & M_STATEPL)
+
+#define S_STATEMARSP    18
+#define V_STATEMARSP(x) ((x) << S_STATEMARSP)
+#define F_STATEMARSP    V_STATEMARSP(1U)
+
+#define S_MA_TAGSINUSE    11
+#define M_MA_TAGSINUSE    0x7fU
+#define V_MA_TAGSINUSE(x) ((x) << S_MA_TAGSINUSE)
+#define G_MA_TAGSINUSE(x) (((x) >> S_MA_TAGSINUSE) & M_MA_TAGSINUSE)
+
+#define S_RADM_TRGT1_HSRDY    10
+#define V_RADM_TRGT1_HSRDY(x) ((x) << S_RADM_TRGT1_HSRDY)
+#define F_RADM_TRGT1_HSRDY    V_RADM_TRGT1_HSRDY(1U)
+
+#define S_RADM_TRGT1_DSRDY    9
+#define V_RADM_TRGT1_DSRDY(x) ((x) << S_RADM_TRGT1_DSRDY)
+#define F_RADM_TRGT1_DSRDY    V_RADM_TRGT1_DSRDY(1U)
+
+#define S_ALIND_REQWRDATAVLD    8
+#define V_ALIND_REQWRDATAVLD(x) ((x) << S_ALIND_REQWRDATAVLD)
+#define F_ALIND_REQWRDATAVLD    V_ALIND_REQWRDATAVLD(1U)
+
+#define S_FID_LKUPWRHDRVLD    7
+#define V_FID_LKUPWRHDRVLD(x) ((x) << S_FID_LKUPWRHDRVLD)
+#define F_FID_LKUPWRHDRVLD    V_FID_LKUPWRHDRVLD(1U)
+
+#define S_MPIO_WRVLD    6
+#define V_MPIO_WRVLD(x) ((x) << S_MPIO_WRVLD)
+#define F_MPIO_WRVLD    V_MPIO_WRVLD(1U)
+
+#define S_TRGT1_RADM_HALT    5
+#define V_TRGT1_RADM_HALT(x) ((x) << S_TRGT1_RADM_HALT)
+#define F_TRGT1_RADM_HALT    V_TRGT1_RADM_HALT(1U)
+
+#define S_RADM_TRGT1_DV_2C    4
+#define V_RADM_TRGT1_DV_2C(x) ((x) << S_RADM_TRGT1_DV_2C)
+#define F_RADM_TRGT1_DV_2C    V_RADM_TRGT1_DV_2C(1U)
+
+#define S_RADM_TRGT1_DV_2C_2    3
+#define V_RADM_TRGT1_DV_2C_2(x) ((x) << S_RADM_TRGT1_DV_2C_2)
+#define F_RADM_TRGT1_DV_2C_2    V_RADM_TRGT1_DV_2C_2(1U)
+
+#define S_RADM_TRGT1_TLP_ABORT_2C    2
+#define V_RADM_TRGT1_TLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_TLP_ABORT_2C)
+#define F_RADM_TRGT1_TLP_ABORT_2C    V_RADM_TRGT1_TLP_ABORT_2C(1U)
+
+#define S_RADM_TRGT1_DLLP_ABORT_2C    1
+#define V_RADM_TRGT1_DLLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_DLLP_ABORT_2C)
+#define F_RADM_TRGT1_DLLP_ABORT_2C    V_RADM_TRGT1_DLLP_ABORT_2C(1U)
+
+#define S_RADM_TRGT1_ECRC_ERR_2C    0
+#define V_RADM_TRGT1_ECRC_ERR_2C(x) ((x) << S_RADM_TRGT1_ECRC_ERR_2C)
+#define F_RADM_TRGT1_ECRC_ERR_2C    V_RADM_TRGT1_ECRC_ERR_2C(1U)
+
+#define A_PCIE_PDEBUG_REG_0X2D 0x2d
+
+#define S_RADM_TRGT1_HV_2D    31
+#define V_RADM_TRGT1_HV_2D(x) ((x) << S_RADM_TRGT1_HV_2D)
+#define F_RADM_TRGT1_HV_2D    V_RADM_TRGT1_HV_2D(1U)
+
+#define S_RADM_TRGT1_DV_2D    30
+#define V_RADM_TRGT1_DV_2D(x) ((x) << S_RADM_TRGT1_DV_2D)
+#define F_RADM_TRGT1_DV_2D    V_RADM_TRGT1_DV_2D(1U)
+
+#define S_RADM_TRGT1_HV2    23
+#define M_RADM_TRGT1_HV2    0x7fU
+#define V_RADM_TRGT1_HV2(x) ((x) << S_RADM_TRGT1_HV2)
+#define G_RADM_TRGT1_HV2(x) (((x) >> S_RADM_TRGT1_HV2) & M_RADM_TRGT1_HV2)
+
+#define S_RADM_TRGT1_HV3    20
+#define M_RADM_TRGT1_HV3    0x7U
+#define V_RADM_TRGT1_HV3(x) ((x) << S_RADM_TRGT1_HV3)
+#define G_RADM_TRGT1_HV3(x) (((x) >> S_RADM_TRGT1_HV3) & M_RADM_TRGT1_HV3)
+
+#define S_RADM_TRGT1_HV4    16
+#define M_RADM_TRGT1_HV4    0xfU
+#define V_RADM_TRGT1_HV4(x) ((x) << S_RADM_TRGT1_HV4)
+#define G_RADM_TRGT1_HV4(x) (((x) >> S_RADM_TRGT1_HV4) & M_RADM_TRGT1_HV4)
+
+#define S_RADM_TRGT1_HV5    12
+#define M_RADM_TRGT1_HV5    0xfU
+#define V_RADM_TRGT1_HV5(x) ((x) << S_RADM_TRGT1_HV5)
+#define G_RADM_TRGT1_HV5(x) (((x) >> S_RADM_TRGT1_HV5) & M_RADM_TRGT1_HV5)
+
+#define S_RADM_TRGT1_HV6    11
+#define V_RADM_TRGT1_HV6(x) ((x) << S_RADM_TRGT1_HV6)
+#define F_RADM_TRGT1_HV6    V_RADM_TRGT1_HV6(1U)
+
+#define S_RADM_TRGT1_HV7    10
+#define V_RADM_TRGT1_HV7(x) ((x) << S_RADM_TRGT1_HV7)
+#define F_RADM_TRGT1_HV7    V_RADM_TRGT1_HV7(1U)
+
+#define S_RADM_TRGT1_HV8    7
+#define M_RADM_TRGT1_HV8    0x7U
+#define V_RADM_TRGT1_HV8(x) ((x) << S_RADM_TRGT1_HV8)
+#define G_RADM_TRGT1_HV8(x) (((x) >> S_RADM_TRGT1_HV8) & M_RADM_TRGT1_HV8)
+
+#define S_RADM_TRGT1_HV9    6
+#define V_RADM_TRGT1_HV9(x) ((x) << S_RADM_TRGT1_HV9)
+#define F_RADM_TRGT1_HV9    V_RADM_TRGT1_HV9(1U)
+
+#define S_RADM_TRGT1_HVA    5
+#define V_RADM_TRGT1_HVA(x) ((x) << S_RADM_TRGT1_HVA)
+#define F_RADM_TRGT1_HVA    V_RADM_TRGT1_HVA(1U)
+
+#define S_RADM_TRGT1_DSRDY_2D    4
+#define V_RADM_TRGT1_DSRDY_2D(x) ((x) << S_RADM_TRGT1_DSRDY_2D)
+#define F_RADM_TRGT1_DSRDY_2D    V_RADM_TRGT1_DSRDY_2D(1U)
+
+#define S_RADM_TRGT1_WRCNT    0
+#define M_RADM_TRGT1_WRCNT    0xfU
+#define V_RADM_TRGT1_WRCNT(x) ((x) << S_RADM_TRGT1_WRCNT)
+#define G_RADM_TRGT1_WRCNT(x) (((x) >> S_RADM_TRGT1_WRCNT) & M_RADM_TRGT1_WRCNT)
+
+#define A_PCIE_PDEBUG_REG_0X2E 0x2e
+
+#define S_RADM_TRGT1_HV_2E    30
+#define M_RADM_TRGT1_HV_2E    0x3U
+#define V_RADM_TRGT1_HV_2E(x) ((x) << S_RADM_TRGT1_HV_2E)
+#define G_RADM_TRGT1_HV_2E(x) (((x) >> S_RADM_TRGT1_HV_2E) & M_RADM_TRGT1_HV_2E)
+
+#define S_RADM_TRGT1_HV_2E_2    20
+#define M_RADM_TRGT1_HV_2E_2    0x3ffU
+#define V_RADM_TRGT1_HV_2E_2(x) ((x) << S_RADM_TRGT1_HV_2E_2)
+#define G_RADM_TRGT1_HV_2E_2(x) (((x) >> S_RADM_TRGT1_HV_2E_2) & M_RADM_TRGT1_HV_2E_2)
+
+#define S_RADM_TRGT1_HV_WE_3    12
+#define M_RADM_TRGT1_HV_WE_3    0xffU
+#define V_RADM_TRGT1_HV_WE_3(x) ((x) << S_RADM_TRGT1_HV_WE_3)
+#define G_RADM_TRGT1_HV_WE_3(x) (((x) >> S_RADM_TRGT1_HV_WE_3) & M_RADM_TRGT1_HV_WE_3)
+
+#define S_ALIN_REQDATAVLD4    8
+#define M_ALIN_REQDATAVLD4    0xfU
+#define V_ALIN_REQDATAVLD4(x) ((x) << S_ALIN_REQDATAVLD4)
+#define G_ALIN_REQDATAVLD4(x) (((x) >> S_ALIN_REQDATAVLD4) & M_ALIN_REQDATAVLD4)
+
+#define S_ALIN_REQDATAVLD5    7
+#define V_ALIN_REQDATAVLD5(x) ((x) << S_ALIN_REQDATAVLD5)
+#define F_ALIN_REQDATAVLD5    V_ALIN_REQDATAVLD5(1U)
+
+#define S_ALIN_REQDATAVLD6    6
+#define V_ALIN_REQDATAVLD6(x) ((x) << S_ALIN_REQDATAVLD6)
+#define F_ALIN_REQDATAVLD6    V_ALIN_REQDATAVLD6(1U)
+
+#define S_ALIN_REQDATAVLD7    4
+#define M_ALIN_REQDATAVLD7    0x3U
+#define V_ALIN_REQDATAVLD7(x) ((x) << S_ALIN_REQDATAVLD7)
+#define G_ALIN_REQDATAVLD7(x) (((x) >> S_ALIN_REQDATAVLD7) & M_ALIN_REQDATAVLD7)
+
+#define S_ALIN_REQDATAVLD8    3
+#define V_ALIN_REQDATAVLD8(x) ((x) << S_ALIN_REQDATAVLD8)
+#define F_ALIN_REQDATAVLD8    V_ALIN_REQDATAVLD8(1U)
+
+#define S_ALIN_REQDATAVLD9    2
+#define V_ALIN_REQDATAVLD9(x) ((x) << S_ALIN_REQDATAVLD9)
+#define F_ALIN_REQDATAVLD9    V_ALIN_REQDATAVLD9(1U)
+
+#define S_ALIN_REQDATARDY    1
+#define V_ALIN_REQDATARDY(x) ((x) << S_ALIN_REQDATARDY)
+#define F_ALIN_REQDATARDY    V_ALIN_REQDATARDY(1U)
+
+#define S_ALIN_REQDATAVLDA    0
+#define V_ALIN_REQDATAVLDA(x) ((x) << S_ALIN_REQDATAVLDA)
+#define F_ALIN_REQDATAVLDA    V_ALIN_REQDATAVLDA(1U)
+
+#define A_PCIE_PDEBUG_REG_0X2F 0x2f
+#define A_PCIE_PDEBUG_REG_0X30 0x30
+
+#define S_RADM_TRGT1_HV_30    25
+#define M_RADM_TRGT1_HV_30    0x7fU
+#define V_RADM_TRGT1_HV_30(x) ((x) << S_RADM_TRGT1_HV_30)
+#define G_RADM_TRGT1_HV_30(x) (((x) >> S_RADM_TRGT1_HV_30) & M_RADM_TRGT1_HV_30)
+
+#define S_PIO_WRCNT    15
+#define M_PIO_WRCNT    0x3ffU
+#define V_PIO_WRCNT(x) ((x) << S_PIO_WRCNT)
+#define G_PIO_WRCNT(x) (((x) >> S_PIO_WRCNT) & M_PIO_WRCNT)
+
+#define S_ALIND_REQWRCNT    12
+#define M_ALIND_REQWRCNT    0x7U
+#define V_ALIND_REQWRCNT(x) ((x) << S_ALIND_REQWRCNT)
+#define G_ALIND_REQWRCNT(x) (((x) >> S_ALIND_REQWRCNT) & M_ALIND_REQWRCNT)
+
+#define S_FID_LKUPWRCNT    9
+#define M_FID_LKUPWRCNT    0x7U
+#define V_FID_LKUPWRCNT(x) ((x) << S_FID_LKUPWRCNT)
+#define G_FID_LKUPWRCNT(x) (((x) >> S_FID_LKUPWRCNT) & M_FID_LKUPWRCNT)
+
+#define S_ALIND_REQRDDATAVLD    8
+#define V_ALIND_REQRDDATAVLD(x) ((x) << S_ALIND_REQRDDATAVLD)
+#define F_ALIND_REQRDDATAVLD    V_ALIND_REQRDDATAVLD(1U)
+
+#define S_ALIND_REQRDDATARDY    7
+#define V_ALIND_REQRDDATARDY(x) ((x) << S_ALIND_REQRDDATARDY)
+#define F_ALIND_REQRDDATARDY    V_ALIND_REQRDDATARDY(1U)
+
+#define S_ALIND_REQRDDATAVLD2    6
+#define V_ALIND_REQRDDATAVLD2(x) ((x) << S_ALIND_REQRDDATAVLD2)
+#define F_ALIND_REQRDDATAVLD2    V_ALIND_REQRDDATAVLD2(1U)
+
+#define S_ALIND_REQWRDATAVLD3    3
+#define M_ALIND_REQWRDATAVLD3    0x7U
+#define V_ALIND_REQWRDATAVLD3(x) ((x) << S_ALIND_REQWRDATAVLD3)
+#define G_ALIND_REQWRDATAVLD3(x) (((x) >> S_ALIND_REQWRDATAVLD3) & M_ALIND_REQWRDATAVLD3)
+
+#define S_ALIND_REQWRDATAVLD4    2
+#define V_ALIND_REQWRDATAVLD4(x) ((x) << S_ALIND_REQWRDATAVLD4)
+#define F_ALIND_REQWRDATAVLD4    V_ALIND_REQWRDATAVLD4(1U)
+
+#define S_ALIND_REQWRDATARDYOPEN    1
+#define V_ALIND_REQWRDATARDYOPEN(x) ((x) << S_ALIND_REQWRDATARDYOPEN)
+#define F_ALIND_REQWRDATARDYOPEN    V_ALIND_REQWRDATARDYOPEN(1U)
+
+#define S_ALIND_REQWRDATAVLD5    0
+#define V_ALIND_REQWRDATAVLD5(x) ((x) << S_ALIND_REQWRDATAVLD5)
+#define F_ALIND_REQWRDATAVLD5    V_ALIND_REQWRDATAVLD5(1U)
+
+#define A_PCIE_PDEBUG_REG_0X31 0x31
+#define A_PCIE_PDEBUG_REG_0X32 0x32
+#define A_PCIE_PDEBUG_REG_0X33 0x33
+#define A_PCIE_PDEBUG_REG_0X34 0x34
+#define A_PCIE_PDEBUG_REG_0X35 0x35
+
+#define S_T5_MPIO_WRVLD    19
+#define M_T5_MPIO_WRVLD    0x1fffU
+#define V_T5_MPIO_WRVLD(x) ((x) << S_T5_MPIO_WRVLD)
+#define G_T5_MPIO_WRVLD(x) (((x) >> S_T5_MPIO_WRVLD) & M_T5_MPIO_WRVLD)
+
+#define S_FID_LKUPRDHDRVLD    18
+#define V_FID_LKUPRDHDRVLD(x) ((x) << S_FID_LKUPRDHDRVLD)
+#define F_FID_LKUPRDHDRVLD    V_FID_LKUPRDHDRVLD(1U)
+
+#define S_FID_LKUPRDHDRVLD2    17
+#define V_FID_LKUPRDHDRVLD2(x) ((x) << S_FID_LKUPRDHDRVLD2)
+#define F_FID_LKUPRDHDRVLD2    V_FID_LKUPRDHDRVLD2(1U)
+
+#define S_FID_LKUPRDHDRVLD3    16
+#define V_FID_LKUPRDHDRVLD3(x) ((x) << S_FID_LKUPRDHDRVLD3)
+#define F_FID_LKUPRDHDRVLD3    V_FID_LKUPRDHDRVLD3(1U)
+
+#define S_FID_LKUPRDHDRVLD4    15
+#define V_FID_LKUPRDHDRVLD4(x) ((x) << S_FID_LKUPRDHDRVLD4)
+#define F_FID_LKUPRDHDRVLD4    V_FID_LKUPRDHDRVLD4(1U)
+
+#define S_FID_LKUPRDHDRVLD5    14
+#define V_FID_LKUPRDHDRVLD5(x) ((x) << S_FID_LKUPRDHDRVLD5)
+#define F_FID_LKUPRDHDRVLD5    V_FID_LKUPRDHDRVLD5(1U)
+
+#define S_FID_LKUPRDHDRVLD6    13
+#define V_FID_LKUPRDHDRVLD6(x) ((x) << S_FID_LKUPRDHDRVLD6)
+#define F_FID_LKUPRDHDRVLD6    V_FID_LKUPRDHDRVLD6(1U)
+
+#define S_FID_LKUPRDHDRVLD7    12
+#define V_FID_LKUPRDHDRVLD7(x) ((x) << S_FID_LKUPRDHDRVLD7)
+#define F_FID_LKUPRDHDRVLD7    V_FID_LKUPRDHDRVLD7(1U)
+
+#define S_FID_LKUPRDHDRVLD8    11
+#define V_FID_LKUPRDHDRVLD8(x) ((x) << S_FID_LKUPRDHDRVLD8)
+#define F_FID_LKUPRDHDRVLD8    V_FID_LKUPRDHDRVLD8(1U)
+
+#define S_FID_LKUPRDHDRVLD9    10
+#define V_FID_LKUPRDHDRVLD9(x) ((x) << S_FID_LKUPRDHDRVLD9)
+#define F_FID_LKUPRDHDRVLD9    V_FID_LKUPRDHDRVLD9(1U)
+
+#define S_FID_LKUPRDHDRVLDA    9
+#define V_FID_LKUPRDHDRVLDA(x) ((x) << S_FID_LKUPRDHDRVLDA)
+#define F_FID_LKUPRDHDRVLDA    V_FID_LKUPRDHDRVLDA(1U)
+
+#define S_FID_LKUPRDHDRVLDB    8
+#define V_FID_LKUPRDHDRVLDB(x) ((x) << S_FID_LKUPRDHDRVLDB)
+#define F_FID_LKUPRDHDRVLDB    V_FID_LKUPRDHDRVLDB(1U)
+
+#define S_FID_LKUPRDHDRVLDC    7
+#define V_FID_LKUPRDHDRVLDC(x) ((x) << S_FID_LKUPRDHDRVLDC)
+#define F_FID_LKUPRDHDRVLDC    V_FID_LKUPRDHDRVLDC(1U)
+
+#define S_MPIO_WRVLD1    6
+#define V_MPIO_WRVLD1(x) ((x) << S_MPIO_WRVLD1)
+#define F_MPIO_WRVLD1    V_MPIO_WRVLD1(1U)
+
+#define S_MPIO_WRVLD2    5
+#define V_MPIO_WRVLD2(x) ((x) << S_MPIO_WRVLD2)
+#define F_MPIO_WRVLD2    V_MPIO_WRVLD2(1U)
+
+#define S_MPIO_WRVLD3    4
+#define V_MPIO_WRVLD3(x) ((x) << S_MPIO_WRVLD3)
+#define F_MPIO_WRVLD3    V_MPIO_WRVLD3(1U)
+
+#define S_MPIO_WRVLD4    0
+#define M_MPIO_WRVLD4    0xfU
+#define V_MPIO_WRVLD4(x) ((x) << S_MPIO_WRVLD4)
+#define G_MPIO_WRVLD4(x) (((x) >> S_MPIO_WRVLD4) & M_MPIO_WRVLD4)
+
+#define A_PCIE_PDEBUG_REG_0X36 0x36
+#define A_PCIE_PDEBUG_REG_0X37 0x37
+#define A_PCIE_PDEBUG_REG_0X38 0x38
+#define A_PCIE_PDEBUG_REG_0X39 0x39
+#define A_PCIE_PDEBUG_REG_0X3A 0x3a
+
+#define S_CLIENT0_TLP_VFUNC_ACTIVE    31
+#define V_CLIENT0_TLP_VFUNC_ACTIVE(x) ((x) << S_CLIENT0_TLP_VFUNC_ACTIVE)
+#define F_CLIENT0_TLP_VFUNC_ACTIVE    V_CLIENT0_TLP_VFUNC_ACTIVE(1U)
+
+#define S_CLIENT0_TLP_VFUNC_NUM    24
+#define M_CLIENT0_TLP_VFUNC_NUM    0x7fU
+#define V_CLIENT0_TLP_VFUNC_NUM(x) ((x) << S_CLIENT0_TLP_VFUNC_NUM)
+#define G_CLIENT0_TLP_VFUNC_NUM(x) (((x) >> S_CLIENT0_TLP_VFUNC_NUM) & M_CLIENT0_TLP_VFUNC_NUM)
+
+#define S_CLIENT0_TLP_FUNC_NUM    21
+#define M_CLIENT0_TLP_FUNC_NUM    0x7U
+#define V_CLIENT0_TLP_FUNC_NUM(x) ((x) << S_CLIENT0_TLP_FUNC_NUM)
+#define G_CLIENT0_TLP_FUNC_NUM(x) (((x) >> S_CLIENT0_TLP_FUNC_NUM) & M_CLIENT0_TLP_FUNC_NUM)
+
+#define S_CLIENT0_TLP_BYTE_EN    13
+#define M_CLIENT0_TLP_BYTE_EN    0xffU
+#define V_CLIENT0_TLP_BYTE_EN(x) ((x) << S_CLIENT0_TLP_BYTE_EN)
+#define G_CLIENT0_TLP_BYTE_EN(x) (((x) >> S_CLIENT0_TLP_BYTE_EN) & M_CLIENT0_TLP_BYTE_EN)
+
+#define S_CLIENT0_TLP_BYTE_LEN    0
+#define M_CLIENT0_TLP_BYTE_LEN    0x1fffU
+#define V_CLIENT0_TLP_BYTE_LEN(x) ((x) << S_CLIENT0_TLP_BYTE_LEN)
+#define G_CLIENT0_TLP_BYTE_LEN(x) (((x) >> S_CLIENT0_TLP_BYTE_LEN) & M_CLIENT0_TLP_BYTE_LEN)
+
+#define A_PCIE_PDEBUG_REG_0X3B 0x3b
+
+#define S_XADM_CLIENT0_HALT    31
+#define V_XADM_CLIENT0_HALT(x) ((x) << S_XADM_CLIENT0_HALT)
+#define F_XADM_CLIENT0_HALT    V_XADM_CLIENT0_HALT(1U)
+
+#define S_CLIENT0_TLP_DV    30
+#define V_CLIENT0_TLP_DV(x) ((x) << S_CLIENT0_TLP_DV)
+#define F_CLIENT0_TLP_DV    V_CLIENT0_TLP_DV(1U)
+
+#define S_CLIENT0_ADDR_ALIGN_EN    29
+#define V_CLIENT0_ADDR_ALIGN_EN(x) ((x) << S_CLIENT0_ADDR_ALIGN_EN)
+#define F_CLIENT0_ADDR_ALIGN_EN    V_CLIENT0_ADDR_ALIGN_EN(1U)
+
+#define S_CLIENT0_CPL_BCM    28
+#define V_CLIENT0_CPL_BCM(x) ((x) << S_CLIENT0_CPL_BCM)
+#define F_CLIENT0_CPL_BCM    V_CLIENT0_CPL_BCM(1U)
+
+#define S_CLIENT0_TLP_EP    27
+#define V_CLIENT0_TLP_EP(x) ((x) << S_CLIENT0_TLP_EP)
+#define F_CLIENT0_TLP_EP    V_CLIENT0_TLP_EP(1U)
+
+#define S_CLIENT0_CPL_STATUS    24
+#define M_CLIENT0_CPL_STATUS    0x7U
+#define V_CLIENT0_CPL_STATUS(x) ((x) << S_CLIENT0_CPL_STATUS)
+#define G_CLIENT0_CPL_STATUS(x) (((x) >> S_CLIENT0_CPL_STATUS) & M_CLIENT0_CPL_STATUS)
+
+#define S_CLIENT0_TLP_TD    23
+#define V_CLIENT0_TLP_TD(x) ((x) << S_CLIENT0_TLP_TD)
+#define F_CLIENT0_TLP_TD    V_CLIENT0_TLP_TD(1U)
+
+#define S_CLIENT0_TLP_TYPE    18
+#define M_CLIENT0_TLP_TYPE    0x1fU
+#define V_CLIENT0_TLP_TYPE(x) ((x) << S_CLIENT0_TLP_TYPE)
+#define G_CLIENT0_TLP_TYPE(x) (((x) >> S_CLIENT0_TLP_TYPE) & M_CLIENT0_TLP_TYPE)
+
+#define S_CLIENT0_TLP_FMT    16
+#define M_CLIENT0_TLP_FMT    0x3U
+#define V_CLIENT0_TLP_FMT(x) ((x) << S_CLIENT0_TLP_FMT)
+#define G_CLIENT0_TLP_FMT(x) (((x) >> S_CLIENT0_TLP_FMT) & M_CLIENT0_TLP_FMT)
+
+#define S_CLIENT0_TLP_BAD_EOT    15
+#define V_CLIENT0_TLP_BAD_EOT(x) ((x) << S_CLIENT0_TLP_BAD_EOT)
+#define F_CLIENT0_TLP_BAD_EOT    V_CLIENT0_TLP_BAD_EOT(1U)
+
+#define S_CLIENT0_TLP_EOT    14
+#define V_CLIENT0_TLP_EOT(x) ((x) << S_CLIENT0_TLP_EOT)
+#define F_CLIENT0_TLP_EOT    V_CLIENT0_TLP_EOT(1U)
+
+#define S_CLIENT0_TLP_ATTR    11
+#define M_CLIENT0_TLP_ATTR    0x7U
+#define V_CLIENT0_TLP_ATTR(x) ((x) << S_CLIENT0_TLP_ATTR)
+#define G_CLIENT0_TLP_ATTR(x) (((x) >> S_CLIENT0_TLP_ATTR) & M_CLIENT0_TLP_ATTR)
+
+#define S_CLIENT0_TLP_TC    8
+#define M_CLIENT0_TLP_TC    0x7U
+#define V_CLIENT0_TLP_TC(x) ((x) << S_CLIENT0_TLP_TC)
+#define G_CLIENT0_TLP_TC(x) (((x) >> S_CLIENT0_TLP_TC) & M_CLIENT0_TLP_TC)
+
+#define S_CLIENT0_TLP_TID    0
+#define M_CLIENT0_TLP_TID    0xffU
+#define V_CLIENT0_TLP_TID(x) ((x) << S_CLIENT0_TLP_TID)
+#define G_CLIENT0_TLP_TID(x) (((x) >> S_CLIENT0_TLP_TID) & M_CLIENT0_TLP_TID)
+
+#define A_PCIE_PDEBUG_REG_0X3C 0x3c
+
+#define S_MEM_RSPRRAVLD    31
+#define V_MEM_RSPRRAVLD(x) ((x) << S_MEM_RSPRRAVLD)
+#define F_MEM_RSPRRAVLD    V_MEM_RSPRRAVLD(1U)
+
+#define S_MEM_RSPRRARDY    30
+#define V_MEM_RSPRRARDY(x) ((x) << S_MEM_RSPRRARDY)
+#define F_MEM_RSPRRARDY    V_MEM_RSPRRARDY(1U)
+
+#define S_PIO_RSPRRAVLD    29
+#define V_PIO_RSPRRAVLD(x) ((x) << S_PIO_RSPRRAVLD)
+#define F_PIO_RSPRRAVLD    V_PIO_RSPRRAVLD(1U)
+
+#define S_PIO_RSPRRARDY    28
+#define V_PIO_RSPRRARDY(x) ((x) << S_PIO_RSPRRARDY)
+#define F_PIO_RSPRRARDY    V_PIO_RSPRRARDY(1U)
+
+#define S_MEM_RSPRDVLD    27
+#define V_MEM_RSPRDVLD(x) ((x) << S_MEM_RSPRDVLD)
+#define F_MEM_RSPRDVLD    V_MEM_RSPRDVLD(1U)
+
+#define S_MEM_RSPRDRRARDY    26
+#define V_MEM_RSPRDRRARDY(x) ((x) << S_MEM_RSPRDRRARDY)
+#define F_MEM_RSPRDRRARDY    V_MEM_RSPRDRRARDY(1U)
+
+#define S_PIO_RSPRDVLD    25
+#define V_PIO_RSPRDVLD(x) ((x) << S_PIO_RSPRDVLD)
+#define F_PIO_RSPRDVLD    V_PIO_RSPRDVLD(1U)
+
+#define S_PIO_RSPRDRRARDY    24
+#define V_PIO_RSPRDRRARDY(x) ((x) << S_PIO_RSPRDRRARDY)
+#define F_PIO_RSPRDRRARDY    V_PIO_RSPRDRRARDY(1U)
+
+#define S_TGT_TAGQ_RDVLD    16
+#define M_TGT_TAGQ_RDVLD    0xffU
+#define V_TGT_TAGQ_RDVLD(x) ((x) << S_TGT_TAGQ_RDVLD)
+#define G_TGT_TAGQ_RDVLD(x) (((x) >> S_TGT_TAGQ_RDVLD) & M_TGT_TAGQ_RDVLD)
+
+#define S_CPLTXNDISABLE    8
+#define M_CPLTXNDISABLE    0xffU
+#define V_CPLTXNDISABLE(x) ((x) << S_CPLTXNDISABLE)
+#define G_CPLTXNDISABLE(x) (((x) >> S_CPLTXNDISABLE) & M_CPLTXNDISABLE)
+
+#define S_CPLTXNDISABLE2    7
+#define V_CPLTXNDISABLE2(x) ((x) << S_CPLTXNDISABLE2)
+#define F_CPLTXNDISABLE2    V_CPLTXNDISABLE2(1U)
+
+#define S_CLIENT0_TLP_HV    0
+#define M_CLIENT0_TLP_HV    0x7fU
+#define V_CLIENT0_TLP_HV(x) ((x) << S_CLIENT0_TLP_HV)
+#define G_CLIENT0_TLP_HV(x) (((x) >> S_CLIENT0_TLP_HV) & M_CLIENT0_TLP_HV)
+
+#define A_PCIE_PDEBUG_REG_0X3D 0x3d
+#define A_PCIE_PDEBUG_REG_0X3E 0x3e
+#define A_PCIE_PDEBUG_REG_0X3F 0x3f
+#define A_PCIE_PDEBUG_REG_0X40 0x40
+#define A_PCIE_PDEBUG_REG_0X41 0x41
+#define A_PCIE_PDEBUG_REG_0X42 0x42
+#define A_PCIE_PDEBUG_REG_0X43 0x43
+#define A_PCIE_PDEBUG_REG_0X44 0x44
+#define A_PCIE_PDEBUG_REG_0X45 0x45
+#define A_PCIE_PDEBUG_REG_0X46 0x46
+#define A_PCIE_PDEBUG_REG_0X47 0x47
+#define A_PCIE_PDEBUG_REG_0X48 0x48
+#define A_PCIE_PDEBUG_REG_0X49 0x49
+#define A_PCIE_PDEBUG_REG_0X4A 0x4a
+#define A_PCIE_PDEBUG_REG_0X4B 0x4b
+#define A_PCIE_PDEBUG_REG_0X4C 0x4c
+#define A_PCIE_PDEBUG_REG_0X4D 0x4d
+#define A_PCIE_PDEBUG_REG_0X4E 0x4e
+#define A_PCIE_PDEBUG_REG_0X4F 0x4f
+#define A_PCIE_PDEBUG_REG_0X50 0x50
+#define A_PCIE_CDEBUG_REG_0X0 0x0
+#define A_PCIE_CDEBUG_REG_0X1 0x1
+#define A_PCIE_CDEBUG_REG_0X2 0x2
+
+#define S_FLR_REQVLD    31
+#define V_FLR_REQVLD(x) ((x) << S_FLR_REQVLD)
+#define F_FLR_REQVLD    V_FLR_REQVLD(1U)
+
+#define S_D_RSPVLD    28
+#define M_D_RSPVLD    0x7U
+#define V_D_RSPVLD(x) ((x) << S_D_RSPVLD)
+#define G_D_RSPVLD(x) (((x) >> S_D_RSPVLD) & M_D_RSPVLD)
+
+#define S_D_RSPVLD2    27
+#define V_D_RSPVLD2(x) ((x) << S_D_RSPVLD2)
+#define F_D_RSPVLD2    V_D_RSPVLD2(1U)
+
+#define S_D_RSPVLD3    26
+#define V_D_RSPVLD3(x) ((x) << S_D_RSPVLD3)
+#define F_D_RSPVLD3    V_D_RSPVLD3(1U)
+
+#define S_D_RSPVLD4    25
+#define V_D_RSPVLD4(x) ((x) << S_D_RSPVLD4)
+#define F_D_RSPVLD4    V_D_RSPVLD4(1U)
+
+#define S_D_RSPVLD5    24
+#define V_D_RSPVLD5(x) ((x) << S_D_RSPVLD5)
+#define F_D_RSPVLD5    V_D_RSPVLD5(1U)
+
+#define S_D_RSPVLD6    20
+#define M_D_RSPVLD6    0xfU
+#define V_D_RSPVLD6(x) ((x) << S_D_RSPVLD6)
+#define G_D_RSPVLD6(x) (((x) >> S_D_RSPVLD6) & M_D_RSPVLD6)
+
+#define S_D_RSPAFULL    16
+#define M_D_RSPAFULL    0xfU
+#define V_D_RSPAFULL(x) ((x) << S_D_RSPAFULL)
+#define G_D_RSPAFULL(x) (((x) >> S_D_RSPAFULL) & M_D_RSPAFULL)
+
+#define S_D_RDREQVLD    12
+#define M_D_RDREQVLD    0xfU
+#define V_D_RDREQVLD(x) ((x) << S_D_RDREQVLD)
+#define G_D_RDREQVLD(x) (((x) >> S_D_RDREQVLD) & M_D_RDREQVLD)
+
+#define S_D_RDREQAFULL    8
+#define M_D_RDREQAFULL    0xfU
+#define V_D_RDREQAFULL(x) ((x) << S_D_RDREQAFULL)
+#define G_D_RDREQAFULL(x) (((x) >> S_D_RDREQAFULL) & M_D_RDREQAFULL)
+
+#define S_D_WRREQVLD    4
+#define M_D_WRREQVLD    0xfU
+#define V_D_WRREQVLD(x) ((x) << S_D_WRREQVLD)
+#define G_D_WRREQVLD(x) (((x) >> S_D_WRREQVLD) & M_D_WRREQVLD)
+
+#define S_D_WRREQAFULL    0
+#define M_D_WRREQAFULL    0xfU
+#define V_D_WRREQAFULL(x) ((x) << S_D_WRREQAFULL)
+#define G_D_WRREQAFULL(x) (((x) >> S_D_WRREQAFULL) & M_D_WRREQAFULL)
+
+#define A_PCIE_CDEBUG_REG_0X3 0x3
+
+#define S_C_REQVLD    19
+#define M_C_REQVLD    0x1fffU
+#define V_C_REQVLD(x) ((x) << S_C_REQVLD)
+#define G_C_REQVLD(x) (((x) >> S_C_REQVLD) & M_C_REQVLD)
+
+#define S_C_RSPVLD2    16
+#define M_C_RSPVLD2    0x7U
+#define V_C_RSPVLD2(x) ((x) << S_C_RSPVLD2)
+#define G_C_RSPVLD2(x) (((x) >> S_C_RSPVLD2) & M_C_RSPVLD2)
+
+#define S_C_RSPVLD3    15
+#define V_C_RSPVLD3(x) ((x) << S_C_RSPVLD3)
+#define F_C_RSPVLD3    V_C_RSPVLD3(1U)
+
+#define S_C_RSPVLD4    14
+#define V_C_RSPVLD4(x) ((x) << S_C_RSPVLD4)
+#define F_C_RSPVLD4    V_C_RSPVLD4(1U)
+
+#define S_C_RSPVLD5    13
+#define V_C_RSPVLD5(x) ((x) << S_C_RSPVLD5)
+#define F_C_RSPVLD5    V_C_RSPVLD5(1U)
+
+#define S_C_RSPVLD6    12
+#define V_C_RSPVLD6(x) ((x) << S_C_RSPVLD6)
+#define F_C_RSPVLD6    V_C_RSPVLD6(1U)
+
+#define S_C_RSPVLD7    9
+#define M_C_RSPVLD7    0x7U
+#define V_C_RSPVLD7(x) ((x) << S_C_RSPVLD7)
+#define G_C_RSPVLD7(x) (((x) >> S_C_RSPVLD7) & M_C_RSPVLD7)
+
+#define S_C_RSPAFULL    6
+#define M_C_RSPAFULL    0x7U
+#define V_C_RSPAFULL(x) ((x) << S_C_RSPAFULL)
+#define G_C_RSPAFULL(x) (((x) >> S_C_RSPAFULL) & M_C_RSPAFULL)
+
+#define S_C_REQVLD8    3
+#define M_C_REQVLD8    0x7U
+#define V_C_REQVLD8(x) ((x) << S_C_REQVLD8)
+#define G_C_REQVLD8(x) (((x) >> S_C_REQVLD8) & M_C_REQVLD8)
+
+#define S_C_REQAFULL    0
+#define M_C_REQAFULL    0x7U
+#define V_C_REQAFULL(x) ((x) << S_C_REQAFULL)
+#define G_C_REQAFULL(x) (((x) >> S_C_REQAFULL) & M_C_REQAFULL)
+
+#define A_PCIE_CDEBUG_REG_0X4 0x4
+
+#define S_H_REQVLD    7
+#define M_H_REQVLD    0x1ffffffU
+#define V_H_REQVLD(x) ((x) << S_H_REQVLD)
+#define G_H_REQVLD(x) (((x) >> S_H_REQVLD) & M_H_REQVLD)
+
+#define S_H_RSPVLD    6
+#define V_H_RSPVLD(x) ((x) << S_H_RSPVLD)
+#define F_H_RSPVLD    V_H_RSPVLD(1U)
+
+#define S_H_RSPVLD2    5
+#define V_H_RSPVLD2(x) ((x) << S_H_RSPVLD2)
+#define F_H_RSPVLD2    V_H_RSPVLD2(1U)
+
+#define S_H_RSPVLD3    4
+#define V_H_RSPVLD3(x) ((x) << S_H_RSPVLD3)
+#define F_H_RSPVLD3    V_H_RSPVLD3(1U)
+
+#define S_H_RSPVLD4    3
+#define V_H_RSPVLD4(x) ((x) << S_H_RSPVLD4)
+#define F_H_RSPVLD4    V_H_RSPVLD4(1U)
+
+#define S_H_RSPAFULL    2
+#define V_H_RSPAFULL(x) ((x) << S_H_RSPAFULL)
+#define F_H_RSPAFULL    V_H_RSPAFULL(1U)
+
+#define S_H_REQVLD2    1
+#define V_H_REQVLD2(x) ((x) << S_H_REQVLD2)
+#define F_H_REQVLD2    V_H_REQVLD2(1U)
+
+#define S_H_REQAFULL    0
+#define V_H_REQAFULL(x) ((x) << S_H_REQAFULL)
+#define F_H_REQAFULL    V_H_REQAFULL(1U)
+
+#define A_PCIE_CDEBUG_REG_0X5 0x5
+
+#define S_ER_RSPVLD    16
+#define M_ER_RSPVLD    0xffffU
+#define V_ER_RSPVLD(x) ((x) << S_ER_RSPVLD)
+#define G_ER_RSPVLD(x) (((x) >> S_ER_RSPVLD) & M_ER_RSPVLD)
+
+#define S_ER_REQVLD2    5
+#define M_ER_REQVLD2    0x7ffU
+#define V_ER_REQVLD2(x) ((x) << S_ER_REQVLD2)
+#define G_ER_REQVLD2(x) (((x) >> S_ER_REQVLD2) & M_ER_REQVLD2)
+
+#define S_ER_REQVLD3    2
+#define M_ER_REQVLD3    0x7U
+#define V_ER_REQVLD3(x) ((x) << S_ER_REQVLD3)
+#define G_ER_REQVLD3(x) (((x) >> S_ER_REQVLD3) & M_ER_REQVLD3)
+
+#define S_ER_RSPVLD4    1
+#define V_ER_RSPVLD4(x) ((x) << S_ER_RSPVLD4)
+#define F_ER_RSPVLD4    V_ER_RSPVLD4(1U)
+
+#define S_ER_REQVLD5    0
+#define V_ER_REQVLD5(x) ((x) << S_ER_REQVLD5)
+#define F_ER_REQVLD5    V_ER_REQVLD5(1U)
+
+#define A_PCIE_CDEBUG_REG_0X6 0x6
+
+#define S_PL_BAR2_REQVLD    4
+#define M_PL_BAR2_REQVLD    0xfffffffU
+#define V_PL_BAR2_REQVLD(x) ((x) << S_PL_BAR2_REQVLD)
+#define G_PL_BAR2_REQVLD(x) (((x) >> S_PL_BAR2_REQVLD) & M_PL_BAR2_REQVLD)
+
+#define S_PL_BAR2_REQVLD2    3
+#define V_PL_BAR2_REQVLD2(x) ((x) << S_PL_BAR2_REQVLD2)
+#define F_PL_BAR2_REQVLD2    V_PL_BAR2_REQVLD2(1U)
+
+#define S_PL_BAR2_REQVLDE    2
+#define V_PL_BAR2_REQVLDE(x) ((x) << S_PL_BAR2_REQVLDE)
+#define F_PL_BAR2_REQVLDE    V_PL_BAR2_REQVLDE(1U)
+
+#define S_PL_BAR2_REQFULL    1
+#define V_PL_BAR2_REQFULL(x) ((x) << S_PL_BAR2_REQFULL)
+#define F_PL_BAR2_REQFULL    V_PL_BAR2_REQFULL(1U)
+
+#define S_PL_BAR2_REQVLD4    0
+#define V_PL_BAR2_REQVLD4(x) ((x) << S_PL_BAR2_REQVLD4)
+#define F_PL_BAR2_REQVLD4    V_PL_BAR2_REQVLD4(1U)
+
+#define A_PCIE_CDEBUG_REG_0X7 0x7
+#define A_PCIE_CDEBUG_REG_0X8 0x8
+#define A_PCIE_CDEBUG_REG_0X9 0x9
+#define A_PCIE_CDEBUG_REG_0XA 0xa
+
+#define S_VPD_RSPVLD    20
+#define M_VPD_RSPVLD    0xfffU
+#define V_VPD_RSPVLD(x) ((x) << S_VPD_RSPVLD)
+#define G_VPD_RSPVLD(x) (((x) >> S_VPD_RSPVLD) & M_VPD_RSPVLD)
+
+#define S_VPD_REQVLD2    9
+#define M_VPD_REQVLD2    0x7ffU
+#define V_VPD_REQVLD2(x) ((x) << S_VPD_REQVLD2)
+#define G_VPD_REQVLD2(x) (((x) >> S_VPD_REQVLD2) & M_VPD_REQVLD2)
+
+#define S_VPD_REQVLD3    6
+#define M_VPD_REQVLD3    0x7U
+#define V_VPD_REQVLD3(x) ((x) << S_VPD_REQVLD3)
+#define G_VPD_REQVLD3(x) (((x) >> S_VPD_REQVLD3) & M_VPD_REQVLD3)
+
+#define S_VPD_REQVLD4    5
+#define V_VPD_REQVLD4(x) ((x) << S_VPD_REQVLD4)
+#define F_VPD_REQVLD4    V_VPD_REQVLD4(1U)
+
+#define S_VPD_REQVLD5    3
+#define M_VPD_REQVLD5    0x3U
+#define V_VPD_REQVLD5(x) ((x) << S_VPD_REQVLD5)
+#define G_VPD_REQVLD5(x) (((x) >> S_VPD_REQVLD5) & M_VPD_REQVLD5)
+
+#define S_VPD_RSPVLD2    2
+#define V_VPD_RSPVLD2(x) ((x) << S_VPD_RSPVLD2)
+#define F_VPD_RSPVLD2    V_VPD_RSPVLD2(1U)
+
+#define S_VPD_RSPVLD3    1
+#define V_VPD_RSPVLD3(x) ((x) << S_VPD_RSPVLD3)
+#define F_VPD_RSPVLD3    V_VPD_RSPVLD3(1U)
+
+#define S_VPD_REQVLD6    0
+#define V_VPD_REQVLD6(x) ((x) << S_VPD_REQVLD6)
+#define F_VPD_REQVLD6    V_VPD_REQVLD6(1U)
+
+#define A_PCIE_CDEBUG_REG_0XB 0xb
+
+#define S_MA_REQDATAVLD    28
+#define M_MA_REQDATAVLD    0xfU
+#define V_MA_REQDATAVLD(x) ((x) << S_MA_REQDATAVLD)
+#define G_MA_REQDATAVLD(x) (((x) >> S_MA_REQDATAVLD) & M_MA_REQDATAVLD)
+
+#define S_MA_REQADDRVLD    27
+#define V_MA_REQADDRVLD(x) ((x) << S_MA_REQADDRVLD)
+#define F_MA_REQADDRVLD    V_MA_REQADDRVLD(1U)
+
+#define S_MA_REQADDRVLD2    26
+#define V_MA_REQADDRVLD2(x) ((x) << S_MA_REQADDRVLD2)
+#define F_MA_REQADDRVLD2    V_MA_REQADDRVLD2(1U)
+
+#define S_MA_RSPDATAVLD2    22
+#define M_MA_RSPDATAVLD2    0xfU
+#define V_MA_RSPDATAVLD2(x) ((x) << S_MA_RSPDATAVLD2)
+#define G_MA_RSPDATAVLD2(x) (((x) >> S_MA_RSPDATAVLD2) & M_MA_RSPDATAVLD2)
+
+#define S_MA_REQADDRVLD3    20
+#define M_MA_REQADDRVLD3    0x3U
+#define V_MA_REQADDRVLD3(x) ((x) << S_MA_REQADDRVLD3)
+#define G_MA_REQADDRVLD3(x) (((x) >> S_MA_REQADDRVLD3) & M_MA_REQADDRVLD3)
+
+#define S_MA_REQADDRVLD4    4
+#define M_MA_REQADDRVLD4    0xffffU
+#define V_MA_REQADDRVLD4(x) ((x) << S_MA_REQADDRVLD4)
+#define G_MA_REQADDRVLD4(x) (((x) >> S_MA_REQADDRVLD4) & M_MA_REQADDRVLD4)
+
+#define S_MA_REQADDRVLD5    3
+#define V_MA_REQADDRVLD5(x) ((x) << S_MA_REQADDRVLD5)
+#define F_MA_REQADDRVLD5    V_MA_REQADDRVLD5(1U)
+
+#define S_MA_REQADDRVLD6    2
+#define V_MA_REQADDRVLD6(x) ((x) << S_MA_REQADDRVLD6)
+#define F_MA_REQADDRVLD6    V_MA_REQADDRVLD6(1U)
+
+#define S_MA_REQADDRRDY    1
+#define V_MA_REQADDRRDY(x) ((x) << S_MA_REQADDRRDY)
+#define F_MA_REQADDRRDY    V_MA_REQADDRRDY(1U)
+
+#define S_MA_REQADDRVLD7    0
+#define V_MA_REQADDRVLD7(x) ((x) << S_MA_REQADDRVLD7)
+#define F_MA_REQADDRVLD7    V_MA_REQADDRVLD7(1U)
+
+#define A_PCIE_CDEBUG_REG_0XC 0xc
+#define A_PCIE_CDEBUG_REG_0XD 0xd
+#define A_PCIE_CDEBUG_REG_0XE 0xe
+#define A_PCIE_CDEBUG_REG_0XF 0xf
+#define A_PCIE_CDEBUG_REG_0X10 0x10
+#define A_PCIE_CDEBUG_REG_0X11 0x11
+#define A_PCIE_CDEBUG_REG_0X12 0x12
+#define A_PCIE_CDEBUG_REG_0X13 0x13
+#define A_PCIE_CDEBUG_REG_0X14 0x14
+#define A_PCIE_CDEBUG_REG_0X15 0x15
+
+#define S_PLM_REQVLD    19
+#define M_PLM_REQVLD    0x1fffU
+#define V_PLM_REQVLD(x) ((x) << S_PLM_REQVLD)
+#define G_PLM_REQVLD(x) (((x) >> S_PLM_REQVLD) & M_PLM_REQVLD)
+
+#define S_PLM_REQVLD2    18
+#define V_PLM_REQVLD2(x) ((x) << S_PLM_REQVLD2)
+#define F_PLM_REQVLD2    V_PLM_REQVLD2(1U)
+
+#define S_PLM_RSPVLD3    17
+#define V_PLM_RSPVLD3(x) ((x) << S_PLM_RSPVLD3)
+#define F_PLM_RSPVLD3    V_PLM_RSPVLD3(1U)
+
+#define S_PLM_REQVLD4    16
+#define V_PLM_REQVLD4(x) ((x) << S_PLM_REQVLD4)
+#define F_PLM_REQVLD4    V_PLM_REQVLD4(1U)
+
+#define S_PLM_REQVLD5    15
+#define V_PLM_REQVLD5(x) ((x) << S_PLM_REQVLD5)
+#define F_PLM_REQVLD5    V_PLM_REQVLD5(1U)
+
+#define S_PLM_REQVLD6    14
+#define V_PLM_REQVLD6(x) ((x) << S_PLM_REQVLD6)
+#define F_PLM_REQVLD6    V_PLM_REQVLD6(1U)
+
+#define S_PLM_REQVLD7    13
+#define V_PLM_REQVLD7(x) ((x) << S_PLM_REQVLD7)
+#define F_PLM_REQVLD7    V_PLM_REQVLD7(1U)
+
+#define S_PLM_REQVLD8    12
+#define V_PLM_REQVLD8(x) ((x) << S_PLM_REQVLD8)
+#define F_PLM_REQVLD8    V_PLM_REQVLD8(1U)
+
+#define S_PLM_REQVLD9    4
+#define M_PLM_REQVLD9    0xffU
+#define V_PLM_REQVLD9(x) ((x) << S_PLM_REQVLD9)
+#define G_PLM_REQVLD9(x) (((x) >> S_PLM_REQVLD9) & M_PLM_REQVLD9)
+
+#define S_PLM_REQVLDA    1
+#define M_PLM_REQVLDA    0x7U
+#define V_PLM_REQVLDA(x) ((x) << S_PLM_REQVLDA)
+#define G_PLM_REQVLDA(x) (((x) >> S_PLM_REQVLDA) & M_PLM_REQVLDA)
+
+#define S_PLM_REQVLDB    0
+#define V_PLM_REQVLDB(x) ((x) << S_PLM_REQVLDB)
+#define F_PLM_REQVLDB    V_PLM_REQVLDB(1U)
+
+#define A_PCIE_CDEBUG_REG_0X16 0x16
+#define A_PCIE_CDEBUG_REG_0X17 0x17
+#define A_PCIE_CDEBUG_REG_0X18 0x18
+#define A_PCIE_CDEBUG_REG_0X19 0x19
+#define A_PCIE_CDEBUG_REG_0X1A 0x1a
+#define A_PCIE_CDEBUG_REG_0X1B 0x1b
+#define A_PCIE_CDEBUG_REG_0X1C 0x1c
+#define A_PCIE_CDEBUG_REG_0X1D 0x1d
+#define A_PCIE_CDEBUG_REG_0X1E 0x1e
+#define A_PCIE_CDEBUG_REG_0X1F 0x1f
+#define A_PCIE_CDEBUG_REG_0X20 0x20
+#define A_PCIE_CDEBUG_REG_0X21 0x21
+#define A_PCIE_CDEBUG_REG_0X22 0x22
+#define A_PCIE_CDEBUG_REG_0X23 0x23
+#define A_PCIE_CDEBUG_REG_0X24 0x24
+#define A_PCIE_CDEBUG_REG_0X25 0x25
+#define A_PCIE_CDEBUG_REG_0X26 0x26
+#define A_PCIE_CDEBUG_REG_0X27 0x27
+#define A_PCIE_CDEBUG_REG_0X28 0x28
+#define A_PCIE_CDEBUG_REG_0X29 0x29
+#define A_PCIE_CDEBUG_REG_0X2A 0x2a
+#define A_PCIE_CDEBUG_REG_0X2B 0x2b
+#define A_PCIE_CDEBUG_REG_0X2C 0x2c
+#define A_PCIE_CDEBUG_REG_0X2D 0x2d
+#define A_PCIE_CDEBUG_REG_0X2E 0x2e
+#define A_PCIE_CDEBUG_REG_0X2F 0x2f
+#define A_PCIE_CDEBUG_REG_0X30 0x30
+#define A_PCIE_CDEBUG_REG_0X31 0x31
+#define A_PCIE_CDEBUG_REG_0X32 0x32
+#define A_PCIE_CDEBUG_REG_0X33 0x33
+#define A_PCIE_CDEBUG_REG_0X34 0x34
+#define A_PCIE_CDEBUG_REG_0X35 0x35
+#define A_PCIE_CDEBUG_REG_0X36 0x36
+#define A_PCIE_CDEBUG_REG_0X37 0x37
 
 /* registers for module DBG */
 #define DBG_BASE_ADDR 0x6000
@@ -7969,6 +12350,11 @@
 #define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL)
 #define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL)
 
+#define S_T6_P_OCLK_MUXSEL    13
+#define M_T6_P_OCLK_MUXSEL    0xfU
+#define V_T6_P_OCLK_MUXSEL(x) ((x) << S_T6_P_OCLK_MUXSEL)
+#define G_T6_P_OCLK_MUXSEL(x) (((x) >> S_T6_P_OCLK_MUXSEL) & M_T6_P_OCLK_MUXSEL)
+
 #define A_DBG_TRACE0_CONF_COMPREG0 0x6060
 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064
 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068
@@ -8042,6 +12428,26 @@
 #define V_RD_EN0(x) ((x) << S_RD_EN0)
 #define F_RD_EN0    V_RD_EN0(1U)
 
+#define S_T5_RD_ADDR1    11
+#define M_T5_RD_ADDR1    0x1ffU
+#define V_T5_RD_ADDR1(x) ((x) << S_T5_RD_ADDR1)
+#define G_T5_RD_ADDR1(x) (((x) >> S_T5_RD_ADDR1) & M_T5_RD_ADDR1)
+
+#define S_T5_RD_ADDR0    2
+#define M_T5_RD_ADDR0    0x1ffU
+#define V_T5_RD_ADDR0(x) ((x) << S_T5_RD_ADDR0)
+#define G_T5_RD_ADDR0(x) (((x) >> S_T5_RD_ADDR0) & M_T5_RD_ADDR0)
+
+#define S_T6_RD_ADDR1    11
+#define M_T6_RD_ADDR1    0x1ffU
+#define V_T6_RD_ADDR1(x) ((x) << S_T6_RD_ADDR1)
+#define G_T6_RD_ADDR1(x) (((x) >> S_T6_RD_ADDR1) & M_T6_RD_ADDR1)
+
+#define S_T6_RD_ADDR0    2
+#define M_T6_RD_ADDR0    0x1ffU
+#define V_T6_RD_ADDR0(x) ((x) << S_T6_RD_ADDR0)
+#define G_T6_RD_ADDR0(x) (((x) >> S_T6_RD_ADDR0) & M_T6_RD_ADDR0)
+
 #define A_DBG_TRACE_WRADDR 0x6090
 
 #define S_WR_POINTER_ADDR1    16
@@ -8054,6 +12460,26 @@
 #define V_WR_POINTER_ADDR0(x) ((x) << S_WR_POINTER_ADDR0)
 #define G_WR_POINTER_ADDR0(x) (((x) >> S_WR_POINTER_ADDR0) & M_WR_POINTER_ADDR0)
 
+#define S_T5_WR_POINTER_ADDR1    16
+#define M_T5_WR_POINTER_ADDR1    0x1ffU
+#define V_T5_WR_POINTER_ADDR1(x) ((x) << S_T5_WR_POINTER_ADDR1)
+#define G_T5_WR_POINTER_ADDR1(x) (((x) >> S_T5_WR_POINTER_ADDR1) & M_T5_WR_POINTER_ADDR1)
+
+#define S_T5_WR_POINTER_ADDR0    0
+#define M_T5_WR_POINTER_ADDR0    0x1ffU
+#define V_T5_WR_POINTER_ADDR0(x) ((x) << S_T5_WR_POINTER_ADDR0)
+#define G_T5_WR_POINTER_ADDR0(x) (((x) >> S_T5_WR_POINTER_ADDR0) & M_T5_WR_POINTER_ADDR0)
+
+#define S_T6_WR_POINTER_ADDR1    16
+#define M_T6_WR_POINTER_ADDR1    0x1ffU
+#define V_T6_WR_POINTER_ADDR1(x) ((x) << S_T6_WR_POINTER_ADDR1)
+#define G_T6_WR_POINTER_ADDR1(x) (((x) >> S_T6_WR_POINTER_ADDR1) & M_T6_WR_POINTER_ADDR1)
+
+#define S_T6_WR_POINTER_ADDR0    0
+#define M_T6_WR_POINTER_ADDR0    0x1ffU
+#define V_T6_WR_POINTER_ADDR0(x) ((x) << S_T6_WR_POINTER_ADDR0)
+#define G_T6_WR_POINTER_ADDR0(x) (((x) >> S_T6_WR_POINTER_ADDR0) & M_T6_WR_POINTER_ADDR0)
+
 #define A_DBG_TRACE0_DATA_OUT 0x6094
 #define A_DBG_TRACE1_DATA_OUT 0x6098
 #define A_DBG_FUSE_SENSE_DONE 0x609c
@@ -8108,6 +12534,18 @@
 #define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO)
 #define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO)
 
+#define S_T6_TVSENSE_SLEEP    11
+#define V_T6_TVSENSE_SLEEP(x) ((x) << S_T6_TVSENSE_SLEEP)
+#define F_T6_TVSENSE_SLEEP    V_T6_TVSENSE_SLEEP(1U)
+
+#define S_T6_TVSENSE_SENSV    10
+#define V_T6_TVSENSE_SENSV(x) ((x) << S_T6_TVSENSE_SENSV)
+#define F_T6_TVSENSE_SENSV    V_T6_TVSENSE_SENSV(1U)
+
+#define S_T6_TVSENSE_RST    9
+#define V_T6_TVSENSE_RST(x) ((x) << S_T6_TVSENSE_RST)
+#define F_T6_TVSENSE_RST    V_T6_TVSENSE_RST(1U)
+
 #define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
 #define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
 #define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
@@ -8159,6 +12597,18 @@
 #define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE)
 #define G_T5_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE)
 
+#define A_DBG_STATIC_M_PLL_CONF1 0x60b8
+
+#define S_STATIC_M_PLL_MULTFRAC    8
+#define M_STATIC_M_PLL_MULTFRAC    0xffffffU
+#define V_STATIC_M_PLL_MULTFRAC(x) ((x) << S_STATIC_M_PLL_MULTFRAC)
+#define G_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_STATIC_M_PLL_MULTFRAC) & M_STATIC_M_PLL_MULTFRAC)
+
+#define S_STATIC_M_PLL_FFSLEWRATE    0
+#define M_STATIC_M_PLL_FFSLEWRATE    0xffU
+#define V_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_STATIC_M_PLL_FFSLEWRATE)
+#define G_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_M_PLL_FFSLEWRATE) & M_STATIC_M_PLL_FFSLEWRATE)
+
 #define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
 
 #define S_T5_STATIC_M_PLL_DCO_BYPASS    23
@@ -8195,6 +12645,47 @@
 #define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE)
 #define G_T5_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE)
 
+#define A_DBG_STATIC_M_PLL_CONF2 0x60bc
+
+#define S_T6_STATIC_M_PLL_PREDIV    24
+#define M_T6_STATIC_M_PLL_PREDIV    0x3fU
+#define V_T6_STATIC_M_PLL_PREDIV(x) ((x) << S_T6_STATIC_M_PLL_PREDIV)
+#define G_T6_STATIC_M_PLL_PREDIV(x) (((x) >> S_T6_STATIC_M_PLL_PREDIV) & M_T6_STATIC_M_PLL_PREDIV)
+
+#define S_STATIC_M_PLL_DCO_BYPASS    23
+#define V_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_STATIC_M_PLL_DCO_BYPASS)
+#define F_STATIC_M_PLL_DCO_BYPASS    V_STATIC_M_PLL_DCO_BYPASS(1U)
+
+#define S_STATIC_M_PLL_SDORDER    21
+#define M_STATIC_M_PLL_SDORDER    0x3U
+#define V_STATIC_M_PLL_SDORDER(x) ((x) << S_STATIC_M_PLL_SDORDER)
+#define G_STATIC_M_PLL_SDORDER(x) (((x) >> S_STATIC_M_PLL_SDORDER) & M_STATIC_M_PLL_SDORDER)
+
+#define S_STATIC_M_PLL_FFENABLE    20
+#define V_STATIC_M_PLL_FFENABLE(x) ((x) << S_STATIC_M_PLL_FFENABLE)
+#define F_STATIC_M_PLL_FFENABLE    V_STATIC_M_PLL_FFENABLE(1U)
+
+#define S_STATIC_M_PLL_STOPCLKB    19
+#define V_STATIC_M_PLL_STOPCLKB(x) ((x) << S_STATIC_M_PLL_STOPCLKB)
+#define F_STATIC_M_PLL_STOPCLKB    V_STATIC_M_PLL_STOPCLKB(1U)
+
+#define S_STATIC_M_PLL_STOPCLKA    18
+#define V_STATIC_M_PLL_STOPCLKA(x) ((x) << S_STATIC_M_PLL_STOPCLKA)
+#define F_STATIC_M_PLL_STOPCLKA    V_STATIC_M_PLL_STOPCLKA(1U)
+
+#define S_T6_STATIC_M_PLL_SLEEP    17
+#define V_T6_STATIC_M_PLL_SLEEP(x) ((x) << S_T6_STATIC_M_PLL_SLEEP)
+#define F_T6_STATIC_M_PLL_SLEEP    V_T6_STATIC_M_PLL_SLEEP(1U)
+
+#define S_T6_STATIC_M_PLL_BYPASS    16
+#define V_T6_STATIC_M_PLL_BYPASS(x) ((x) << S_T6_STATIC_M_PLL_BYPASS)
+#define F_T6_STATIC_M_PLL_BYPASS    V_T6_STATIC_M_PLL_BYPASS(1U)
+
+#define S_STATIC_M_PLL_LOCKTUNE    0
+#define M_STATIC_M_PLL_LOCKTUNE    0x1fU
+#define V_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_STATIC_M_PLL_LOCKTUNE)
+#define G_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_STATIC_M_PLL_LOCKTUNE) & M_STATIC_M_PLL_LOCKTUNE)
+
 #define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
 
 #define S_T5_STATIC_M_PLL_MULTPRE    30
@@ -8227,7 +12718,39 @@
 #define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA)
 #define G_T5_STATIC_M_PLL_RANGEA(x) (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA)
 
+#define A_DBG_STATIC_M_PLL_CONF3 0x60c0
+
+#define S_STATIC_M_PLL_MULTPRE    30
+#define M_STATIC_M_PLL_MULTPRE    0x3U
+#define V_STATIC_M_PLL_MULTPRE(x) ((x) << S_STATIC_M_PLL_MULTPRE)
+#define G_STATIC_M_PLL_MULTPRE(x) (((x) >> S_STATIC_M_PLL_MULTPRE) & M_STATIC_M_PLL_MULTPRE)
+
+#define S_STATIC_M_PLL_LOCKSEL    28
+#define V_STATIC_M_PLL_LOCKSEL(x) ((x) << S_STATIC_M_PLL_LOCKSEL)
+#define F_STATIC_M_PLL_LOCKSEL    V_STATIC_M_PLL_LOCKSEL(1U)
+
+#define S_STATIC_M_PLL_FFTUNE    12
+#define M_STATIC_M_PLL_FFTUNE    0xffffU
+#define V_STATIC_M_PLL_FFTUNE(x) ((x) << S_STATIC_M_PLL_FFTUNE)
+#define G_STATIC_M_PLL_FFTUNE(x) (((x) >> S_STATIC_M_PLL_FFTUNE) & M_STATIC_M_PLL_FFTUNE)
+
+#define S_STATIC_M_PLL_RANGEPRE    10
+#define M_STATIC_M_PLL_RANGEPRE    0x3U
+#define V_STATIC_M_PLL_RANGEPRE(x) ((x) << S_STATIC_M_PLL_RANGEPRE)
+#define G_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_STATIC_M_PLL_RANGEPRE) & M_STATIC_M_PLL_RANGEPRE)
+
+#define S_T6_STATIC_M_PLL_RANGEB    5
+#define M_T6_STATIC_M_PLL_RANGEB    0x1fU
+#define V_T6_STATIC_M_PLL_RANGEB(x) ((x) << S_T6_STATIC_M_PLL_RANGEB)
+#define G_T6_STATIC_M_PLL_RANGEB(x) (((x) >> S_T6_STATIC_M_PLL_RANGEB) & M_T6_STATIC_M_PLL_RANGEB)
+
+#define S_T6_STATIC_M_PLL_RANGEA    0
+#define M_T6_STATIC_M_PLL_RANGEA    0x1fU
+#define V_T6_STATIC_M_PLL_RANGEA(x) ((x) << S_T6_STATIC_M_PLL_RANGEA)
+#define G_T6_STATIC_M_PLL_RANGEA(x) (((x) >> S_T6_STATIC_M_PLL_RANGEA) & M_T6_STATIC_M_PLL_RANGEA)
+
 #define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
+#define A_DBG_STATIC_M_PLL_CONF4 0x60c4
 #define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
 
 #define S_T5_STATIC_M_PLL_VCVTUNE    24
@@ -8258,6 +12781,31 @@
 #define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT)
 #define G_T5_STATIC_M_PLL_MULT(x) (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT)
 
+#define A_DBG_STATIC_M_PLL_CONF5 0x60c8
+
+#define S_STATIC_M_PLL_VCVTUNE    24
+#define M_STATIC_M_PLL_VCVTUNE    0x7U
+#define V_STATIC_M_PLL_VCVTUNE(x) ((x) << S_STATIC_M_PLL_VCVTUNE)
+#define G_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_STATIC_M_PLL_VCVTUNE) & M_STATIC_M_PLL_VCVTUNE)
+
+#define S_T6_STATIC_M_PLL_RESET    23
+#define V_T6_STATIC_M_PLL_RESET(x) ((x) << S_T6_STATIC_M_PLL_RESET)
+#define F_T6_STATIC_M_PLL_RESET    V_T6_STATIC_M_PLL_RESET(1U)
+
+#define S_STATIC_MPLL_REFCLK_SEL    22
+#define V_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_STATIC_MPLL_REFCLK_SEL)
+#define F_STATIC_MPLL_REFCLK_SEL    V_STATIC_MPLL_REFCLK_SEL(1U)
+
+#define S_STATIC_M_PLL_LFTUNE_32_40    13
+#define M_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
+#define V_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_M_PLL_LFTUNE_32_40)
+#define G_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_M_PLL_LFTUNE_32_40) & M_STATIC_M_PLL_LFTUNE_32_40)
+
+#define S_T6_STATIC_M_PLL_MULT    0
+#define M_T6_STATIC_M_PLL_MULT    0xffU
+#define V_T6_STATIC_M_PLL_MULT(x) ((x) << S_T6_STATIC_M_PLL_MULT)
+#define G_T6_STATIC_M_PLL_MULT(x) (((x) >> S_T6_STATIC_M_PLL_MULT) & M_T6_STATIC_M_PLL_MULT)
+
 #define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
 
 #define S_T5_STATIC_PHY0RECRST_    5
@@ -8284,6 +12832,58 @@
 #define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_)
 #define F_T5_STATIC_SWMC1CFGRST_    V_T5_STATIC_SWMC1CFGRST_(1U)
 
+#define A_DBG_STATIC_M_PLL_CONF6 0x60cc
+
+#define S_STATIC_M_PLL_DIVCHANGE    30
+#define V_STATIC_M_PLL_DIVCHANGE(x) ((x) << S_STATIC_M_PLL_DIVCHANGE)
+#define F_STATIC_M_PLL_DIVCHANGE    V_STATIC_M_PLL_DIVCHANGE(1U)
+
+#define S_STATIC_M_PLL_FRAMESTOP    29
+#define V_STATIC_M_PLL_FRAMESTOP(x) ((x) << S_STATIC_M_PLL_FRAMESTOP)
+#define F_STATIC_M_PLL_FRAMESTOP    V_STATIC_M_PLL_FRAMESTOP(1U)
+
+#define S_STATIC_M_PLL_FASTSTOP    28
+#define V_STATIC_M_PLL_FASTSTOP(x) ((x) << S_STATIC_M_PLL_FASTSTOP)
+#define F_STATIC_M_PLL_FASTSTOP    V_STATIC_M_PLL_FASTSTOP(1U)
+
+#define S_STATIC_M_PLL_FFBYPASS    27
+#define V_STATIC_M_PLL_FFBYPASS(x) ((x) << S_STATIC_M_PLL_FFBYPASS)
+#define F_STATIC_M_PLL_FFBYPASS    V_STATIC_M_PLL_FFBYPASS(1U)
+
+#define S_STATIC_M_PLL_STARTUP    25
+#define M_STATIC_M_PLL_STARTUP    0x3U
+#define V_STATIC_M_PLL_STARTUP(x) ((x) << S_STATIC_M_PLL_STARTUP)
+#define G_STATIC_M_PLL_STARTUP(x) (((x) >> S_STATIC_M_PLL_STARTUP) & M_STATIC_M_PLL_STARTUP)
+
+#define S_STATIC_M_PLL_VREGTUNE    6
+#define M_STATIC_M_PLL_VREGTUNE    0x7ffffU
+#define V_STATIC_M_PLL_VREGTUNE(x) ((x) << S_STATIC_M_PLL_VREGTUNE)
+#define G_STATIC_M_PLL_VREGTUNE(x) (((x) >> S_STATIC_M_PLL_VREGTUNE) & M_STATIC_M_PLL_VREGTUNE)
+
+#define S_STATIC_PHY0RECRST_    5
+#define V_STATIC_PHY0RECRST_(x) ((x) << S_STATIC_PHY0RECRST_)
+#define F_STATIC_PHY0RECRST_    V_STATIC_PHY0RECRST_(1U)
+
+#define S_STATIC_PHY1RECRST_    4
+#define V_STATIC_PHY1RECRST_(x) ((x) << S_STATIC_PHY1RECRST_)
+#define F_STATIC_PHY1RECRST_    V_STATIC_PHY1RECRST_(1U)
+
+#define S_STATIC_SWMC0RST_    3
+#define V_STATIC_SWMC0RST_(x) ((x) << S_STATIC_SWMC0RST_)
+#define F_STATIC_SWMC0RST_    V_STATIC_SWMC0RST_(1U)
+
+#define S_STATIC_SWMC0CFGRST_    2
+#define V_STATIC_SWMC0CFGRST_(x) ((x) << S_STATIC_SWMC0CFGRST_)
+#define F_STATIC_SWMC0CFGRST_    V_STATIC_SWMC0CFGRST_(1U)
+
+#define S_STATIC_SWMC1RST_    1
+#define V_STATIC_SWMC1RST_(x) ((x) << S_STATIC_SWMC1RST_)
+#define F_STATIC_SWMC1RST_    V_STATIC_SWMC1RST_(1U)
+
+#define S_STATIC_SWMC1CFGRST_    0
+#define V_STATIC_SWMC1CFGRST_(x) ((x) << S_STATIC_SWMC1CFGRST_)
+#define F_STATIC_SWMC1CFGRST_    V_STATIC_SWMC1CFGRST_(1U)
+
 #define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
 
 #define S_T5_STATIC_C_PLL_MULTFRAC    8
@@ -8296,6 +12896,18 @@
 #define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE)
 #define G_T5_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE)
 
+#define A_DBG_STATIC_C_PLL_CONF1 0x60d0
+
+#define S_STATIC_C_PLL_MULTFRAC    8
+#define M_STATIC_C_PLL_MULTFRAC    0xffffffU
+#define V_STATIC_C_PLL_MULTFRAC(x) ((x) << S_STATIC_C_PLL_MULTFRAC)
+#define G_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_STATIC_C_PLL_MULTFRAC) & M_STATIC_C_PLL_MULTFRAC)
+
+#define S_STATIC_C_PLL_FFSLEWRATE    0
+#define M_STATIC_C_PLL_FFSLEWRATE    0xffU
+#define V_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_STATIC_C_PLL_FFSLEWRATE)
+#define G_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_C_PLL_FFSLEWRATE) & M_STATIC_C_PLL_FFSLEWRATE)
+
 #define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
 
 #define S_T5_STATIC_C_PLL_DCO_BYPASS    23
@@ -8332,6 +12944,52 @@
 #define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE)
 #define G_T5_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE)
 
+#define A_DBG_STATIC_C_PLL_CONF2 0x60d4
+
+#define S_T6_STATIC_C_PLL_PREDIV    26
+#define M_T6_STATIC_C_PLL_PREDIV    0x3fU
+#define V_T6_STATIC_C_PLL_PREDIV(x) ((x) << S_T6_STATIC_C_PLL_PREDIV)
+#define G_T6_STATIC_C_PLL_PREDIV(x) (((x) >> S_T6_STATIC_C_PLL_PREDIV) & M_T6_STATIC_C_PLL_PREDIV)
+
+#define S_STATIC_C_PLL_STARTUP    24
+#define M_STATIC_C_PLL_STARTUP    0x3U
+#define V_STATIC_C_PLL_STARTUP(x) ((x) << S_STATIC_C_PLL_STARTUP)
+#define G_STATIC_C_PLL_STARTUP(x) (((x) >> S_STATIC_C_PLL_STARTUP) & M_STATIC_C_PLL_STARTUP)
+
+#define S_STATIC_C_PLL_DCO_BYPASS    23
+#define V_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_STATIC_C_PLL_DCO_BYPASS)
+#define F_STATIC_C_PLL_DCO_BYPASS    V_STATIC_C_PLL_DCO_BYPASS(1U)
+
+#define S_STATIC_C_PLL_SDORDER    21
+#define M_STATIC_C_PLL_SDORDER    0x3U
+#define V_STATIC_C_PLL_SDORDER(x) ((x) << S_STATIC_C_PLL_SDORDER)
+#define G_STATIC_C_PLL_SDORDER(x) (((x) >> S_STATIC_C_PLL_SDORDER) & M_STATIC_C_PLL_SDORDER)
+
+#define S_STATIC_C_PLL_DIVCHANGE    20
+#define V_STATIC_C_PLL_DIVCHANGE(x) ((x) << S_STATIC_C_PLL_DIVCHANGE)
+#define F_STATIC_C_PLL_DIVCHANGE    V_STATIC_C_PLL_DIVCHANGE(1U)
+
+#define S_STATIC_C_PLL_STOPCLKB    19
+#define V_STATIC_C_PLL_STOPCLKB(x) ((x) << S_STATIC_C_PLL_STOPCLKB)
+#define F_STATIC_C_PLL_STOPCLKB    V_STATIC_C_PLL_STOPCLKB(1U)
+
+#define S_STATIC_C_PLL_STOPCLKA    18
+#define V_STATIC_C_PLL_STOPCLKA(x) ((x) << S_STATIC_C_PLL_STOPCLKA)
+#define F_STATIC_C_PLL_STOPCLKA    V_STATIC_C_PLL_STOPCLKA(1U)
+
+#define S_T6_STATIC_C_PLL_SLEEP    17
+#define V_T6_STATIC_C_PLL_SLEEP(x) ((x) << S_T6_STATIC_C_PLL_SLEEP)
+#define F_T6_STATIC_C_PLL_SLEEP    V_T6_STATIC_C_PLL_SLEEP(1U)
+
+#define S_T6_STATIC_C_PLL_BYPASS    16
+#define V_T6_STATIC_C_PLL_BYPASS(x) ((x) << S_T6_STATIC_C_PLL_BYPASS)
+#define F_T6_STATIC_C_PLL_BYPASS    V_T6_STATIC_C_PLL_BYPASS(1U)
+
+#define S_STATIC_C_PLL_LOCKTUNE    0
+#define M_STATIC_C_PLL_LOCKTUNE    0x1fU
+#define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE)
+#define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE)
+
 #define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
 
 #define S_T5_STATIC_C_PLL_MULTPRE    30
@@ -8364,7 +13022,39 @@
 #define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA)
 #define G_T5_STATIC_C_PLL_RANGEA(x) (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA)
 
+#define A_DBG_STATIC_C_PLL_CONF3 0x60d8
+
+#define S_STATIC_C_PLL_MULTPRE    30
+#define M_STATIC_C_PLL_MULTPRE    0x3U
+#define V_STATIC_C_PLL_MULTPRE(x) ((x) << S_STATIC_C_PLL_MULTPRE)
+#define G_STATIC_C_PLL_MULTPRE(x) (((x) >> S_STATIC_C_PLL_MULTPRE) & M_STATIC_C_PLL_MULTPRE)
+
+#define S_STATIC_C_PLL_LOCKSEL    28
+#define V_STATIC_C_PLL_LOCKSEL(x) ((x) << S_STATIC_C_PLL_LOCKSEL)
+#define F_STATIC_C_PLL_LOCKSEL    V_STATIC_C_PLL_LOCKSEL(1U)
+
+#define S_STATIC_C_PLL_FFTUNE    12
+#define M_STATIC_C_PLL_FFTUNE    0xffffU
+#define V_STATIC_C_PLL_FFTUNE(x) ((x) << S_STATIC_C_PLL_FFTUNE)
+#define G_STATIC_C_PLL_FFTUNE(x) (((x) >> S_STATIC_C_PLL_FFTUNE) & M_STATIC_C_PLL_FFTUNE)
+
+#define S_STATIC_C_PLL_RANGEPRE    10
+#define M_STATIC_C_PLL_RANGEPRE    0x3U
+#define V_STATIC_C_PLL_RANGEPRE(x) ((x) << S_STATIC_C_PLL_RANGEPRE)
+#define G_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_STATIC_C_PLL_RANGEPRE) & M_STATIC_C_PLL_RANGEPRE)
+
+#define S_T6_STATIC_C_PLL_RANGEB    5
+#define M_T6_STATIC_C_PLL_RANGEB    0x1fU
+#define V_T6_STATIC_C_PLL_RANGEB(x) ((x) << S_T6_STATIC_C_PLL_RANGEB)
+#define G_T6_STATIC_C_PLL_RANGEB(x) (((x) >> S_T6_STATIC_C_PLL_RANGEB) & M_T6_STATIC_C_PLL_RANGEB)
+
+#define S_T6_STATIC_C_PLL_RANGEA    0
+#define M_T6_STATIC_C_PLL_RANGEA    0x1fU
+#define V_T6_STATIC_C_PLL_RANGEA(x) ((x) << S_T6_STATIC_C_PLL_RANGEA)
+#define G_T6_STATIC_C_PLL_RANGEA(x) (((x) >> S_T6_STATIC_C_PLL_RANGEA) & M_T6_STATIC_C_PLL_RANGEA)
+
 #define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
+#define A_DBG_STATIC_C_PLL_CONF4 0x60dc
 #define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
 
 #define S_T5_STATIC_C_PLL_VCVTUNE    22
@@ -8387,6 +13077,40 @@
 #define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT)
 #define G_T5_STATIC_C_PLL_MULT(x) (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT)
 
+#define A_DBG_STATIC_C_PLL_CONF5 0x60e0
+
+#define S_STATIC_C_PLL_FFBYPASS    27
+#define V_STATIC_C_PLL_FFBYPASS(x) ((x) << S_STATIC_C_PLL_FFBYPASS)
+#define F_STATIC_C_PLL_FFBYPASS    V_STATIC_C_PLL_FFBYPASS(1U)
+
+#define S_STATIC_C_PLL_FASTSTOP    26
+#define V_STATIC_C_PLL_FASTSTOP(x) ((x) << S_STATIC_C_PLL_FASTSTOP)
+#define F_STATIC_C_PLL_FASTSTOP    V_STATIC_C_PLL_FASTSTOP(1U)
+
+#define S_STATIC_C_PLL_FRAMESTOP    25
+#define V_STATIC_C_PLL_FRAMESTOP(x) ((x) << S_STATIC_C_PLL_FRAMESTOP)
+#define F_STATIC_C_PLL_FRAMESTOP    V_STATIC_C_PLL_FRAMESTOP(1U)
+
+#define S_STATIC_C_PLL_VCVTUNE    22
+#define M_STATIC_C_PLL_VCVTUNE    0x7U
+#define V_STATIC_C_PLL_VCVTUNE(x) ((x) << S_STATIC_C_PLL_VCVTUNE)
+#define G_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_STATIC_C_PLL_VCVTUNE) & M_STATIC_C_PLL_VCVTUNE)
+
+#define S_STATIC_C_PLL_LFTUNE_32_40    13
+#define M_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
+#define V_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_C_PLL_LFTUNE_32_40)
+#define G_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_C_PLL_LFTUNE_32_40) & M_STATIC_C_PLL_LFTUNE_32_40)
+
+#define S_STATIC_C_PLL_PREDIV_CNF5    8
+#define M_STATIC_C_PLL_PREDIV_CNF5    0x1fU
+#define V_STATIC_C_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_C_PLL_PREDIV_CNF5)
+#define G_STATIC_C_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_C_PLL_PREDIV_CNF5) & M_STATIC_C_PLL_PREDIV_CNF5)
+
+#define S_T6_STATIC_C_PLL_MULT    0
+#define M_T6_STATIC_C_PLL_MULT    0xffU
+#define V_T6_STATIC_C_PLL_MULT(x) ((x) << S_T6_STATIC_C_PLL_MULT)
+#define G_T6_STATIC_C_PLL_MULT(x) (((x) >> S_T6_STATIC_C_PLL_MULT) & M_T6_STATIC_C_PLL_MULT)
+
 #define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
 
 #define S_T5_STATIC_U_PLL_MULTFRAC    8
@@ -8399,6 +13123,18 @@
 #define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE)
 #define G_T5_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE)
 
+#define A_DBG_STATIC_U_PLL_CONF1 0x60e4
+
+#define S_STATIC_U_PLL_MULTFRAC    8
+#define M_STATIC_U_PLL_MULTFRAC    0xffffffU
+#define V_STATIC_U_PLL_MULTFRAC(x) ((x) << S_STATIC_U_PLL_MULTFRAC)
+#define G_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_STATIC_U_PLL_MULTFRAC) & M_STATIC_U_PLL_MULTFRAC)
+
+#define S_STATIC_U_PLL_FFSLEWRATE    0
+#define M_STATIC_U_PLL_FFSLEWRATE    0xffU
+#define V_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_STATIC_U_PLL_FFSLEWRATE)
+#define G_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_U_PLL_FFSLEWRATE) & M_STATIC_U_PLL_FFSLEWRATE)
+
 #define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
 
 #define S_T5_STATIC_U_PLL_DCO_BYPASS    23
@@ -8435,6 +13171,52 @@
 #define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE)
 #define G_T5_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE)
 
+#define A_DBG_STATIC_U_PLL_CONF2 0x60e8
+
+#define S_T6_STATIC_U_PLL_PREDIV    26
+#define M_T6_STATIC_U_PLL_PREDIV    0x3fU
+#define V_T6_STATIC_U_PLL_PREDIV(x) ((x) << S_T6_STATIC_U_PLL_PREDIV)
+#define G_T6_STATIC_U_PLL_PREDIV(x) (((x) >> S_T6_STATIC_U_PLL_PREDIV) & M_T6_STATIC_U_PLL_PREDIV)
+
+#define S_STATIC_U_PLL_STARTUP    24
+#define M_STATIC_U_PLL_STARTUP    0x3U
+#define V_STATIC_U_PLL_STARTUP(x) ((x) << S_STATIC_U_PLL_STARTUP)
+#define G_STATIC_U_PLL_STARTUP(x) (((x) >> S_STATIC_U_PLL_STARTUP) & M_STATIC_U_PLL_STARTUP)
+
+#define S_STATIC_U_PLL_DCO_BYPASS    23
+#define V_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_STATIC_U_PLL_DCO_BYPASS)
+#define F_STATIC_U_PLL_DCO_BYPASS    V_STATIC_U_PLL_DCO_BYPASS(1U)
+
+#define S_STATIC_U_PLL_SDORDER    21
+#define M_STATIC_U_PLL_SDORDER    0x3U
+#define V_STATIC_U_PLL_SDORDER(x) ((x) << S_STATIC_U_PLL_SDORDER)
+#define G_STATIC_U_PLL_SDORDER(x) (((x) >> S_STATIC_U_PLL_SDORDER) & M_STATIC_U_PLL_SDORDER)
+
+#define S_STATIC_U_PLL_DIVCHANGE    20
+#define V_STATIC_U_PLL_DIVCHANGE(x) ((x) << S_STATIC_U_PLL_DIVCHANGE)
+#define F_STATIC_U_PLL_DIVCHANGE    V_STATIC_U_PLL_DIVCHANGE(1U)
+
+#define S_STATIC_U_PLL_STOPCLKB    19
+#define V_STATIC_U_PLL_STOPCLKB(x) ((x) << S_STATIC_U_PLL_STOPCLKB)
+#define F_STATIC_U_PLL_STOPCLKB    V_STATIC_U_PLL_STOPCLKB(1U)
+
+#define S_STATIC_U_PLL_STOPCLKA    18
+#define V_STATIC_U_PLL_STOPCLKA(x) ((x) << S_STATIC_U_PLL_STOPCLKA)
+#define F_STATIC_U_PLL_STOPCLKA    V_STATIC_U_PLL_STOPCLKA(1U)
+
+#define S_T6_STATIC_U_PLL_SLEEP    17
+#define V_T6_STATIC_U_PLL_SLEEP(x) ((x) << S_T6_STATIC_U_PLL_SLEEP)
+#define F_T6_STATIC_U_PLL_SLEEP    V_T6_STATIC_U_PLL_SLEEP(1U)
+
+#define S_T6_STATIC_U_PLL_BYPASS    16
+#define V_T6_STATIC_U_PLL_BYPASS(x) ((x) << S_T6_STATIC_U_PLL_BYPASS)
+#define F_T6_STATIC_U_PLL_BYPASS    V_T6_STATIC_U_PLL_BYPASS(1U)
+
+#define S_STATIC_U_PLL_LOCKTUNE    0
+#define M_STATIC_U_PLL_LOCKTUNE    0x1fU
+#define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE)
+#define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE)
+
 #define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
 
 #define S_T5_STATIC_U_PLL_MULTPRE    30
@@ -8467,7 +13249,39 @@
 #define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA)
 #define G_T5_STATIC_U_PLL_RANGEA(x) (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA)
 
+#define A_DBG_STATIC_U_PLL_CONF3 0x60ec
+
+#define S_STATIC_U_PLL_MULTPRE    30
+#define M_STATIC_U_PLL_MULTPRE    0x3U
+#define V_STATIC_U_PLL_MULTPRE(x) ((x) << S_STATIC_U_PLL_MULTPRE)
+#define G_STATIC_U_PLL_MULTPRE(x) (((x) >> S_STATIC_U_PLL_MULTPRE) & M_STATIC_U_PLL_MULTPRE)
+
+#define S_STATIC_U_PLL_LOCKSEL    28
+#define V_STATIC_U_PLL_LOCKSEL(x) ((x) << S_STATIC_U_PLL_LOCKSEL)
+#define F_STATIC_U_PLL_LOCKSEL    V_STATIC_U_PLL_LOCKSEL(1U)
+
+#define S_STATIC_U_PLL_FFTUNE    12
+#define M_STATIC_U_PLL_FFTUNE    0xffffU
+#define V_STATIC_U_PLL_FFTUNE(x) ((x) << S_STATIC_U_PLL_FFTUNE)
+#define G_STATIC_U_PLL_FFTUNE(x) (((x) >> S_STATIC_U_PLL_FFTUNE) & M_STATIC_U_PLL_FFTUNE)
+
+#define S_STATIC_U_PLL_RANGEPRE    10
+#define M_STATIC_U_PLL_RANGEPRE    0x3U
+#define V_STATIC_U_PLL_RANGEPRE(x) ((x) << S_STATIC_U_PLL_RANGEPRE)
+#define G_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_STATIC_U_PLL_RANGEPRE) & M_STATIC_U_PLL_RANGEPRE)
+
+#define S_T6_STATIC_U_PLL_RANGEB    5
+#define M_T6_STATIC_U_PLL_RANGEB    0x1fU
+#define V_T6_STATIC_U_PLL_RANGEB(x) ((x) << S_T6_STATIC_U_PLL_RANGEB)
+#define G_T6_STATIC_U_PLL_RANGEB(x) (((x) >> S_T6_STATIC_U_PLL_RANGEB) & M_T6_STATIC_U_PLL_RANGEB)
+
+#define S_T6_STATIC_U_PLL_RANGEA    0
+#define M_T6_STATIC_U_PLL_RANGEA    0x1fU
+#define V_T6_STATIC_U_PLL_RANGEA(x) ((x) << S_T6_STATIC_U_PLL_RANGEA)
+#define G_T6_STATIC_U_PLL_RANGEA(x) (((x) >> S_T6_STATIC_U_PLL_RANGEA) & M_T6_STATIC_U_PLL_RANGEA)
+
 #define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
+#define A_DBG_STATIC_U_PLL_CONF4 0x60f0
 #define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
 
 #define S_T5_STATIC_U_PLL_VCVTUNE    22
@@ -8490,6 +13304,40 @@
 #define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT)
 #define G_T5_STATIC_U_PLL_MULT(x) (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT)
 
+#define A_DBG_STATIC_U_PLL_CONF5 0x60f4
+
+#define S_STATIC_U_PLL_FFBYPASS    27
+#define V_STATIC_U_PLL_FFBYPASS(x) ((x) << S_STATIC_U_PLL_FFBYPASS)
+#define F_STATIC_U_PLL_FFBYPASS    V_STATIC_U_PLL_FFBYPASS(1U)
+
+#define S_STATIC_U_PLL_FASTSTOP    26
+#define V_STATIC_U_PLL_FASTSTOP(x) ((x) << S_STATIC_U_PLL_FASTSTOP)
+#define F_STATIC_U_PLL_FASTSTOP    V_STATIC_U_PLL_FASTSTOP(1U)
+
+#define S_STATIC_U_PLL_FRAMESTOP    25
+#define V_STATIC_U_PLL_FRAMESTOP(x) ((x) << S_STATIC_U_PLL_FRAMESTOP)
+#define F_STATIC_U_PLL_FRAMESTOP    V_STATIC_U_PLL_FRAMESTOP(1U)
+
+#define S_STATIC_U_PLL_VCVTUNE    22
+#define M_STATIC_U_PLL_VCVTUNE    0x7U
+#define V_STATIC_U_PLL_VCVTUNE(x) ((x) << S_STATIC_U_PLL_VCVTUNE)
+#define G_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_STATIC_U_PLL_VCVTUNE) & M_STATIC_U_PLL_VCVTUNE)
+
+#define S_STATIC_U_PLL_LFTUNE_32_40    13
+#define M_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
+#define V_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_U_PLL_LFTUNE_32_40)
+#define G_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_U_PLL_LFTUNE_32_40) & M_STATIC_U_PLL_LFTUNE_32_40)
+
+#define S_STATIC_U_PLL_PREDIV_CNF5    8
+#define M_STATIC_U_PLL_PREDIV_CNF5    0x1fU
+#define V_STATIC_U_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_U_PLL_PREDIV_CNF5)
+#define G_STATIC_U_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_U_PLL_PREDIV_CNF5) & M_STATIC_U_PLL_PREDIV_CNF5)
+
+#define S_T6_STATIC_U_PLL_MULT    0
+#define M_T6_STATIC_U_PLL_MULT    0xffU
+#define V_T6_STATIC_U_PLL_MULT(x) ((x) << S_T6_STATIC_U_PLL_MULT)
+#define G_T6_STATIC_U_PLL_MULT(x) (((x) >> S_T6_STATIC_U_PLL_MULT) & M_T6_STATIC_U_PLL_MULT)
+
 #define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8
 
 #define S_T5_STATIC_KR_PLL_BYPASS    30
@@ -8551,6 +13399,67 @@
 #define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1)
 #define G_T5_STATIC_KR_PLL_N1(x) (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1)
 
+#define A_DBG_STATIC_KR_PLL_CONF1 0x60f8
+
+#define S_T6_STATIC_KR_PLL_BYPASS    30
+#define V_T6_STATIC_KR_PLL_BYPASS(x) ((x) << S_T6_STATIC_KR_PLL_BYPASS)
+#define F_T6_STATIC_KR_PLL_BYPASS    V_T6_STATIC_KR_PLL_BYPASS(1U)
+
+#define S_STATIC_KR_PLL_VBOOSTDIV    27
+#define M_STATIC_KR_PLL_VBOOSTDIV    0x7U
+#define V_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KR_PLL_VBOOSTDIV)
+#define G_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KR_PLL_VBOOSTDIV) & M_STATIC_KR_PLL_VBOOSTDIV)
+
+#define S_STATIC_KR_PLL_CPISEL    24
+#define M_STATIC_KR_PLL_CPISEL    0x7U
+#define V_STATIC_KR_PLL_CPISEL(x) ((x) << S_STATIC_KR_PLL_CPISEL)
+#define G_STATIC_KR_PLL_CPISEL(x) (((x) >> S_STATIC_KR_PLL_CPISEL) & M_STATIC_KR_PLL_CPISEL)
+
+#define S_STATIC_KR_PLL_CCALMETHOD    23
+#define V_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_STATIC_KR_PLL_CCALMETHOD)
+#define F_STATIC_KR_PLL_CCALMETHOD    V_STATIC_KR_PLL_CCALMETHOD(1U)
+
+#define S_STATIC_KR_PLL_CCALLOAD    22
+#define V_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_STATIC_KR_PLL_CCALLOAD)
+#define F_STATIC_KR_PLL_CCALLOAD    V_STATIC_KR_PLL_CCALLOAD(1U)
+
+#define S_STATIC_KR_PLL_CCALFMIN    21
+#define V_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_STATIC_KR_PLL_CCALFMIN)
+#define F_STATIC_KR_PLL_CCALFMIN    V_STATIC_KR_PLL_CCALFMIN(1U)
+
+#define S_STATIC_KR_PLL_CCALFMAX    20
+#define V_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_STATIC_KR_PLL_CCALFMAX)
+#define F_STATIC_KR_PLL_CCALFMAX    V_STATIC_KR_PLL_CCALFMAX(1U)
+
+#define S_STATIC_KR_PLL_CCALCVHOLD    19
+#define V_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KR_PLL_CCALCVHOLD)
+#define F_STATIC_KR_PLL_CCALCVHOLD    V_STATIC_KR_PLL_CCALCVHOLD(1U)
+
+#define S_STATIC_KR_PLL_CCALBANDSEL    15
+#define M_STATIC_KR_PLL_CCALBANDSEL    0xfU
+#define V_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KR_PLL_CCALBANDSEL)
+#define G_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KR_PLL_CCALBANDSEL) & M_STATIC_KR_PLL_CCALBANDSEL)
+
+#define S_STATIC_KR_PLL_BGOFFSET    11
+#define M_STATIC_KR_PLL_BGOFFSET    0xfU
+#define V_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_STATIC_KR_PLL_BGOFFSET)
+#define G_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_STATIC_KR_PLL_BGOFFSET) & M_STATIC_KR_PLL_BGOFFSET)
+
+#define S_T6_STATIC_KR_PLL_P    8
+#define M_T6_STATIC_KR_PLL_P    0x7U
+#define V_T6_STATIC_KR_PLL_P(x) ((x) << S_T6_STATIC_KR_PLL_P)
+#define G_T6_STATIC_KR_PLL_P(x) (((x) >> S_T6_STATIC_KR_PLL_P) & M_T6_STATIC_KR_PLL_P)
+
+#define S_T6_STATIC_KR_PLL_N2    4
+#define M_T6_STATIC_KR_PLL_N2    0xfU
+#define V_T6_STATIC_KR_PLL_N2(x) ((x) << S_T6_STATIC_KR_PLL_N2)
+#define G_T6_STATIC_KR_PLL_N2(x) (((x) >> S_T6_STATIC_KR_PLL_N2) & M_T6_STATIC_KR_PLL_N2)
+
+#define S_T6_STATIC_KR_PLL_N1    0
+#define M_T6_STATIC_KR_PLL_N1    0xfU
+#define V_T6_STATIC_KR_PLL_N1(x) ((x) << S_T6_STATIC_KR_PLL_N1)
+#define G_T6_STATIC_KR_PLL_N1(x) (((x) >> S_T6_STATIC_KR_PLL_N1) & M_T6_STATIC_KR_PLL_N1)
+
 #define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc
 
 #define S_T5_STATIC_KR_PLL_M    11
@@ -8563,6 +13472,18 @@
 #define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE)
 #define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE)
 
+#define A_DBG_STATIC_KR_PLL_CONF2 0x60fc
+
+#define S_T6_STATIC_KR_PLL_M    11
+#define M_T6_STATIC_KR_PLL_M    0x1ffU
+#define V_T6_STATIC_KR_PLL_M(x) ((x) << S_T6_STATIC_KR_PLL_M)
+#define G_T6_STATIC_KR_PLL_M(x) (((x) >> S_T6_STATIC_KR_PLL_M) & M_T6_STATIC_KR_PLL_M)
+
+#define S_STATIC_KR_PLL_ANALOGTUNE    0
+#define M_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
+#define V_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KR_PLL_ANALOGTUNE)
+#define G_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KR_PLL_ANALOGTUNE) & M_STATIC_KR_PLL_ANALOGTUNE)
+
 #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
 
 #define S_HALT_CALIBRATE    1
@@ -8639,21 +13560,21 @@
 #define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET)
 #define F_GPIO19_CHG_DET    V_GPIO19_CHG_DET(1U)
 
-#define S_GPIO16_IN    3
-#define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
-#define F_GPIO16_IN    V_GPIO16_IN(1U)
-
-#define S_GPIO17_IN    2
-#define V_GPIO17_IN(x) ((x) << S_GPIO17_IN)
-#define F_GPIO17_IN    V_GPIO17_IN(1U)
+#define S_GPIO19_IN    3
+#define V_GPIO19_IN(x) ((x) << S_GPIO19_IN)
+#define F_GPIO19_IN    V_GPIO19_IN(1U)
 
-#define S_GPIO18_IN    1
+#define S_GPIO18_IN    2
 #define V_GPIO18_IN(x) ((x) << S_GPIO18_IN)
 #define F_GPIO18_IN    V_GPIO18_IN(1U)
 
-#define S_GPIO19_IN    0
-#define V_GPIO19_IN(x) ((x) << S_GPIO19_IN)
-#define F_GPIO19_IN    V_GPIO19_IN(1U)
+#define S_GPIO17_IN    1
+#define V_GPIO17_IN(x) ((x) << S_GPIO17_IN)
+#define F_GPIO17_IN    V_GPIO17_IN(1U)
+
+#define S_GPIO16_IN    0
+#define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
+#define F_GPIO16_IN    V_GPIO16_IN(1U)
 
 #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
 
@@ -8733,6 +13654,67 @@
 #define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1)
 #define G_T5_STATIC_KX_PLL_N1(x) (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1)
 
+#define A_DBG_STATIC_KX_PLL_CONF1 0x6108
+
+#define S_T6_STATIC_KX_PLL_BYPASS    30
+#define V_T6_STATIC_KX_PLL_BYPASS(x) ((x) << S_T6_STATIC_KX_PLL_BYPASS)
+#define F_T6_STATIC_KX_PLL_BYPASS    V_T6_STATIC_KX_PLL_BYPASS(1U)
+
+#define S_STATIC_KX_PLL_VBOOSTDIV    27
+#define M_STATIC_KX_PLL_VBOOSTDIV    0x7U
+#define V_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KX_PLL_VBOOSTDIV)
+#define G_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KX_PLL_VBOOSTDIV) & M_STATIC_KX_PLL_VBOOSTDIV)
+
+#define S_STATIC_KX_PLL_CPISEL    24
+#define M_STATIC_KX_PLL_CPISEL    0x7U
+#define V_STATIC_KX_PLL_CPISEL(x) ((x) << S_STATIC_KX_PLL_CPISEL)
+#define G_STATIC_KX_PLL_CPISEL(x) (((x) >> S_STATIC_KX_PLL_CPISEL) & M_STATIC_KX_PLL_CPISEL)
+
+#define S_STATIC_KX_PLL_CCALMETHOD    23
+#define V_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_STATIC_KX_PLL_CCALMETHOD)
+#define F_STATIC_KX_PLL_CCALMETHOD    V_STATIC_KX_PLL_CCALMETHOD(1U)
+
+#define S_STATIC_KX_PLL_CCALLOAD    22
+#define V_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_STATIC_KX_PLL_CCALLOAD)
+#define F_STATIC_KX_PLL_CCALLOAD    V_STATIC_KX_PLL_CCALLOAD(1U)
+
+#define S_STATIC_KX_PLL_CCALFMIN    21
+#define V_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_STATIC_KX_PLL_CCALFMIN)
+#define F_STATIC_KX_PLL_CCALFMIN    V_STATIC_KX_PLL_CCALFMIN(1U)
+
+#define S_STATIC_KX_PLL_CCALFMAX    20
+#define V_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_STATIC_KX_PLL_CCALFMAX)
+#define F_STATIC_KX_PLL_CCALFMAX    V_STATIC_KX_PLL_CCALFMAX(1U)
+
+#define S_STATIC_KX_PLL_CCALCVHOLD    19
+#define V_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KX_PLL_CCALCVHOLD)
+#define F_STATIC_KX_PLL_CCALCVHOLD    V_STATIC_KX_PLL_CCALCVHOLD(1U)
+
+#define S_STATIC_KX_PLL_CCALBANDSEL    15
+#define M_STATIC_KX_PLL_CCALBANDSEL    0xfU
+#define V_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KX_PLL_CCALBANDSEL)
+#define G_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KX_PLL_CCALBANDSEL) & M_STATIC_KX_PLL_CCALBANDSEL)
+
+#define S_STATIC_KX_PLL_BGOFFSET    11
+#define M_STATIC_KX_PLL_BGOFFSET    0xfU
+#define V_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_STATIC_KX_PLL_BGOFFSET)
+#define G_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_STATIC_KX_PLL_BGOFFSET) & M_STATIC_KX_PLL_BGOFFSET)
+
+#define S_T6_STATIC_KX_PLL_P    8
+#define M_T6_STATIC_KX_PLL_P    0x7U
+#define V_T6_STATIC_KX_PLL_P(x) ((x) << S_T6_STATIC_KX_PLL_P)
+#define G_T6_STATIC_KX_PLL_P(x) (((x) >> S_T6_STATIC_KX_PLL_P) & M_T6_STATIC_KX_PLL_P)
+
+#define S_T6_STATIC_KX_PLL_N2    4
+#define M_T6_STATIC_KX_PLL_N2    0xfU
+#define V_T6_STATIC_KX_PLL_N2(x) ((x) << S_T6_STATIC_KX_PLL_N2)
+#define G_T6_STATIC_KX_PLL_N2(x) (((x) >> S_T6_STATIC_KX_PLL_N2) & M_T6_STATIC_KX_PLL_N2)
+
+#define S_T6_STATIC_KX_PLL_N1    0
+#define M_T6_STATIC_KX_PLL_N1    0xfU
+#define V_T6_STATIC_KX_PLL_N1(x) ((x) << S_T6_STATIC_KX_PLL_N1)
+#define G_T6_STATIC_KX_PLL_N1(x) (((x) >> S_T6_STATIC_KX_PLL_N1) & M_T6_STATIC_KX_PLL_N1)
+
 #define A_DBG_PVT_REG_DRVN 0x610c
 
 #define S_PVT_REG_DRVN_EN    8
@@ -8761,6 +13743,18 @@
 #define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE)
 #define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE)
 
+#define A_DBG_STATIC_KX_PLL_CONF2 0x610c
+
+#define S_T6_STATIC_KX_PLL_M    11
+#define M_T6_STATIC_KX_PLL_M    0x1ffU
+#define V_T6_STATIC_KX_PLL_M(x) ((x) << S_T6_STATIC_KX_PLL_M)
+#define G_T6_STATIC_KX_PLL_M(x) (((x) >> S_T6_STATIC_KX_PLL_M) & M_T6_STATIC_KX_PLL_M)
+
+#define S_STATIC_KX_PLL_ANALOGTUNE    0
+#define M_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
+#define V_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KX_PLL_ANALOGTUNE)
+#define G_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KX_PLL_ANALOGTUNE) & M_STATIC_KX_PLL_ANALOGTUNE)
+
 #define A_DBG_PVT_REG_DRVP 0x6110
 
 #define S_PVT_REG_DRVP_EN    8
@@ -8801,6 +13795,7 @@
 #define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE)
 #define F_STATIC_C_DFS_ENABLE    V_STATIC_C_DFS_ENABLE(1U)
 
+#define A_DBG_STATIC_C_DFS_CONF 0x6110
 #define A_DBG_PVT_REG_TERMN 0x6114
 
 #define S_PVT_REG_TERMN_EN    8
@@ -8841,6 +13836,7 @@
 #define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE)
 #define F_STATIC_U_DFS_ENABLE    V_STATIC_U_DFS_ENABLE(1U)
 
+#define A_DBG_STATIC_U_DFS_CONF 0x6114
 #define A_DBG_PVT_REG_TERMP 0x6118
 
 #define S_PVT_REG_TERMP_EN    8
@@ -9222,6 +14218,70 @@
 #define V_SAMPLE_WAIT_CLKS(x) ((x) << S_SAMPLE_WAIT_CLKS)
 #define G_SAMPLE_WAIT_CLKS(x) (((x) >> S_SAMPLE_WAIT_CLKS) & M_SAMPLE_WAIT_CLKS)
 
+#define A_DBG_STATIC_U_PLL_CONF6 0x6150
+
+#define S_STATIC_U_PLL_VREGTUNE    0
+#define M_STATIC_U_PLL_VREGTUNE    0x7ffffU
+#define V_STATIC_U_PLL_VREGTUNE(x) ((x) << S_STATIC_U_PLL_VREGTUNE)
+#define G_STATIC_U_PLL_VREGTUNE(x) (((x) >> S_STATIC_U_PLL_VREGTUNE) & M_STATIC_U_PLL_VREGTUNE)
+
+#define A_DBG_STATIC_C_PLL_CONF6 0x6154
+
+#define S_STATIC_C_PLL_VREGTUNE    0
+#define M_STATIC_C_PLL_VREGTUNE    0x7ffffU
+#define V_STATIC_C_PLL_VREGTUNE(x) ((x) << S_STATIC_C_PLL_VREGTUNE)
+#define G_STATIC_C_PLL_VREGTUNE(x) (((x) >> S_STATIC_C_PLL_VREGTUNE) & M_STATIC_C_PLL_VREGTUNE)
+
+#define A_DBG_CUST_EFUSE_PROGRAM 0x6158
+
+#define S_EFUSE_PROG_PERIOD    16
+#define M_EFUSE_PROG_PERIOD    0xffffU
+#define V_EFUSE_PROG_PERIOD(x) ((x) << S_EFUSE_PROG_PERIOD)
+#define G_EFUSE_PROG_PERIOD(x) (((x) >> S_EFUSE_PROG_PERIOD) & M_EFUSE_PROG_PERIOD)
+
+#define S_EFUSE_OPER_TYP    14
+#define M_EFUSE_OPER_TYP    0x3U
+#define V_EFUSE_OPER_TYP(x) ((x) << S_EFUSE_OPER_TYP)
+#define G_EFUSE_OPER_TYP(x) (((x) >> S_EFUSE_OPER_TYP) & M_EFUSE_OPER_TYP)
+
+#define S_EFUSE_ADDR    8
+#define M_EFUSE_ADDR    0x3fU
+#define V_EFUSE_ADDR(x) ((x) << S_EFUSE_ADDR)
+#define G_EFUSE_ADDR(x) (((x) >> S_EFUSE_ADDR) & M_EFUSE_ADDR)
+
+#define S_EFUSE_DIN    0
+#define M_EFUSE_DIN    0xffU
+#define V_EFUSE_DIN(x) ((x) << S_EFUSE_DIN)
+#define G_EFUSE_DIN(x) (((x) >> S_EFUSE_DIN) & M_EFUSE_DIN)
+
+#define A_DBG_CUST_EFUSE_OUT 0x615c
+
+#define S_EFUSE_OPER_DONE    8
+#define V_EFUSE_OPER_DONE(x) ((x) << S_EFUSE_OPER_DONE)
+#define F_EFUSE_OPER_DONE    V_EFUSE_OPER_DONE(1U)
+
+#define S_EFUSE_DOUT    0
+#define M_EFUSE_DOUT    0xffU
+#define V_EFUSE_DOUT(x) ((x) << S_EFUSE_DOUT)
+#define G_EFUSE_DOUT(x) (((x) >> S_EFUSE_DOUT) & M_EFUSE_DOUT)
+
+#define A_DBG_CUST_EFUSE_BYTE0_3 0x6160
+#define A_DBG_CUST_EFUSE_BYTE4_7 0x6164
+#define A_DBG_CUST_EFUSE_BYTE8_11 0x6168
+#define A_DBG_CUST_EFUSE_BYTE12_15 0x616c
+#define A_DBG_CUST_EFUSE_BYTE16_19 0x6170
+#define A_DBG_CUST_EFUSE_BYTE20_23 0x6174
+#define A_DBG_CUST_EFUSE_BYTE24_27 0x6178
+#define A_DBG_CUST_EFUSE_BYTE28_31 0x617c
+#define A_DBG_CUST_EFUSE_BYTE32_35 0x6180
+#define A_DBG_CUST_EFUSE_BYTE36_39 0x6184
+#define A_DBG_CUST_EFUSE_BYTE40_43 0x6188
+#define A_DBG_CUST_EFUSE_BYTE44_47 0x618c
+#define A_DBG_CUST_EFUSE_BYTE48_51 0x6190
+#define A_DBG_CUST_EFUSE_BYTE52_55 0x6194
+#define A_DBG_CUST_EFUSE_BYTE56_59 0x6198
+#define A_DBG_CUST_EFUSE_BYTE60_63 0x619c
+
 /* registers for module MC */
 #define MC_BASE_ADDR 0x6200
 
@@ -11098,6 +16158,19 @@
 #define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1)
 #define G_EXT_MEM_PAGE_SIZE1(x) (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1)
 
+#define S_BRBC_MODE    4
+#define V_BRBC_MODE(x) ((x) << S_BRBC_MODE)
+#define F_BRBC_MODE    V_BRBC_MODE(1U)
+
+#define S_T6_BRC_MODE    3
+#define V_T6_BRC_MODE(x) ((x) << S_T6_BRC_MODE)
+#define F_T6_BRC_MODE    V_T6_BRC_MODE(1U)
+
+#define S_T6_EXT_MEM_PAGE_SIZE    0
+#define M_T6_EXT_MEM_PAGE_SIZE    0x7U
+#define V_T6_EXT_MEM_PAGE_SIZE(x) ((x) << S_T6_EXT_MEM_PAGE_SIZE)
+#define G_T6_EXT_MEM_PAGE_SIZE(x) (((x) >> S_T6_EXT_MEM_PAGE_SIZE) & M_T6_EXT_MEM_PAGE_SIZE)
+
 #define A_MA_ARB_CTRL 0x77d4
 
 #define S_DIS_PAGE_HINT    1
@@ -11112,6 +16185,48 @@
 #define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR)
 #define F_DIS_BANK_FAIR    V_DIS_BANK_FAIR(1U)
 
+#define S_HMA_WRT_EN    26
+#define V_HMA_WRT_EN(x) ((x) << S_HMA_WRT_EN)
+#define F_HMA_WRT_EN    V_HMA_WRT_EN(1U)
+
+#define S_HMA_NUM_PG_128B_FDBK    21
+#define M_HMA_NUM_PG_128B_FDBK    0x1fU
+#define V_HMA_NUM_PG_128B_FDBK(x) ((x) << S_HMA_NUM_PG_128B_FDBK)
+#define G_HMA_NUM_PG_128B_FDBK(x) (((x) >> S_HMA_NUM_PG_128B_FDBK) & M_HMA_NUM_PG_128B_FDBK)
+
+#define S_HMA_DIS_128B_PG_CNT_FDBK    20
+#define V_HMA_DIS_128B_PG_CNT_FDBK(x) ((x) << S_HMA_DIS_128B_PG_CNT_FDBK)
+#define F_HMA_DIS_128B_PG_CNT_FDBK    V_HMA_DIS_128B_PG_CNT_FDBK(1U)
+
+#define S_HMA_DIS_BG_ARB    19
+#define V_HMA_DIS_BG_ARB(x) ((x) << S_HMA_DIS_BG_ARB)
+#define F_HMA_DIS_BG_ARB    V_HMA_DIS_BG_ARB(1U)
+
+#define S_HMA_DIS_BANK_FAIR    18
+#define V_HMA_DIS_BANK_FAIR(x) ((x) << S_HMA_DIS_BANK_FAIR)
+#define F_HMA_DIS_BANK_FAIR    V_HMA_DIS_BANK_FAIR(1U)
+
+#define S_HMA_DIS_PAGE_HINT    17
+#define V_HMA_DIS_PAGE_HINT(x) ((x) << S_HMA_DIS_PAGE_HINT)
+#define F_HMA_DIS_PAGE_HINT    V_HMA_DIS_PAGE_HINT(1U)
+
+#define S_HMA_DIS_ADV_ARB    16
+#define V_HMA_DIS_ADV_ARB(x) ((x) << S_HMA_DIS_ADV_ARB)
+#define F_HMA_DIS_ADV_ARB    V_HMA_DIS_ADV_ARB(1U)
+
+#define S_NUM_PG_128B_FDBK    5
+#define M_NUM_PG_128B_FDBK    0x1fU
+#define V_NUM_PG_128B_FDBK(x) ((x) << S_NUM_PG_128B_FDBK)
+#define G_NUM_PG_128B_FDBK(x) (((x) >> S_NUM_PG_128B_FDBK) & M_NUM_PG_128B_FDBK)
+
+#define S_DIS_128B_PG_CNT_FDBK    4
+#define V_DIS_128B_PG_CNT_FDBK(x) ((x) << S_DIS_128B_PG_CNT_FDBK)
+#define F_DIS_128B_PG_CNT_FDBK    V_DIS_128B_PG_CNT_FDBK(1U)
+
+#define S_DIS_BG_ARB    3
+#define V_DIS_BG_ARB(x) ((x) << S_DIS_BG_ARB)
+#define F_DIS_BG_ARB    V_DIS_BG_ARB(1U)
+
 #define A_MA_TARGET_MEM_ENABLE 0x77d8
 
 #define S_HMA_ENABLE    3
@@ -11142,6 +16257,10 @@
 #define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
 #define F_EXT_MEM0_ENABLE    V_EXT_MEM0_ENABLE(1U)
 
+#define S_MC_SPLIT    6
+#define V_MC_SPLIT(x) ((x) << S_MC_SPLIT)
+#define F_MC_SPLIT    V_MC_SPLIT(1U)
+
 #define A_MA_INT_ENABLE 0x77dc
 
 #define S_MEM_PERR_INT_ENABLE    1
@@ -11490,6 +16609,11 @@
 #define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION)
 #define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION)
 
+#define S_FUTURE_EXPANSION_EE    1
+#define M_FUTURE_EXPANSION_EE    0x7fffffffU
+#define V_FUTURE_EXPANSION_EE(x) ((x) << S_FUTURE_EXPANSION_EE)
+#define G_FUTURE_EXPANSION_EE(x) (((x) >> S_FUTURE_EXPANSION_EE) & M_FUTURE_EXPANSION_EE)
+
 #define A_MA_PARITY_ERROR_ENABLE2 0x7800
 
 #define S_ARB4_PAR_WRQUEUE_ERROR_EN    1
@@ -11561,7 +16685,24 @@
 #define A_MA_PMRX_RDDATA_CNT 0x7874
 #define A_MA_HMA_RDDATA_CNT 0x7878
 #define A_MA_EDRAM0_WRDATA_CNT1 0x787c
+#define A_MA_EXIT_ADDR_FAULT 0x787c
+
+#define S_EXIT_ADDR_FAULT    0
+#define V_EXIT_ADDR_FAULT(x) ((x) << S_EXIT_ADDR_FAULT)
+#define F_EXIT_ADDR_FAULT    V_EXIT_ADDR_FAULT(1U)
+
 #define A_MA_EDRAM0_WRDATA_CNT0 0x7880
+#define A_MA_DDR_DEVICE_CFG 0x7880
+
+#define S_MEM_WIDTH    1
+#define M_MEM_WIDTH    0x7U
+#define V_MEM_WIDTH(x) ((x) << S_MEM_WIDTH)
+#define G_MEM_WIDTH(x) (((x) >> S_MEM_WIDTH) & M_MEM_WIDTH)
+
+#define S_DDR_MODE    0
+#define V_DDR_MODE(x) ((x) << S_DDR_MODE)
+#define F_DDR_MODE    V_DDR_MODE(1U)
+
 #define A_MA_EDRAM1_WRDATA_CNT1 0x7884
 #define A_MA_EDRAM1_WRDATA_CNT0 0x7888
 #define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
@@ -11735,6 +16876,16 @@
 #define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN)
 #define F_CL0_WR_DATA_TO_EN    V_CL0_WR_DATA_TO_EN(1U)
 
+#define S_FUTURE_CEXPANSION_WTE    29
+#define M_FUTURE_CEXPANSION_WTE    0x7U
+#define V_FUTURE_CEXPANSION_WTE(x) ((x) << S_FUTURE_CEXPANSION_WTE)
+#define G_FUTURE_CEXPANSION_WTE(x) (((x) >> S_FUTURE_CEXPANSION_WTE) & M_FUTURE_CEXPANSION_WTE)
+
+#define S_FUTURE_DEXPANSION_WTE    13
+#define M_FUTURE_DEXPANSION_WTE    0x7U
+#define V_FUTURE_DEXPANSION_WTE(x) ((x) << S_FUTURE_DEXPANSION_WTE)
+#define G_FUTURE_DEXPANSION_WTE(x) (((x) >> S_FUTURE_DEXPANSION_WTE) & M_FUTURE_DEXPANSION_WTE)
+
 #define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
 
 #define S_CL12_WR_CMD_TO_ERROR    28
@@ -11841,6 +16992,16 @@
 #define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR)
 #define F_CL0_WR_DATA_TO_ERROR    V_CL0_WR_DATA_TO_ERROR(1U)
 
+#define S_FUTURE_CEXPANSION_WTS    29
+#define M_FUTURE_CEXPANSION_WTS    0x7U
+#define V_FUTURE_CEXPANSION_WTS(x) ((x) << S_FUTURE_CEXPANSION_WTS)
+#define G_FUTURE_CEXPANSION_WTS(x) (((x) >> S_FUTURE_CEXPANSION_WTS) & M_FUTURE_CEXPANSION_WTS)
+
+#define S_FUTURE_DEXPANSION_WTS    13
+#define M_FUTURE_DEXPANSION_WTS    0x7U
+#define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS)
+#define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS)
+
 #define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
 
 #define S_CL12_RD_CMD_TO_EN    28
@@ -11947,6 +17108,16 @@
 #define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN)
 #define F_CL0_RD_DATA_TO_EN    V_CL0_RD_DATA_TO_EN(1U)
 
+#define S_FUTURE_CEXPANSION_RTE    29
+#define M_FUTURE_CEXPANSION_RTE    0x7U
+#define V_FUTURE_CEXPANSION_RTE(x) ((x) << S_FUTURE_CEXPANSION_RTE)
+#define G_FUTURE_CEXPANSION_RTE(x) (((x) >> S_FUTURE_CEXPANSION_RTE) & M_FUTURE_CEXPANSION_RTE)
+
+#define S_FUTURE_DEXPANSION_RTE    13
+#define M_FUTURE_DEXPANSION_RTE    0x7U
+#define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE)
+#define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE)
+
 #define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
 
 #define S_CL12_RD_CMD_TO_ERROR    28
@@ -12053,6 +17224,16 @@
 #define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR)
 #define F_CL0_RD_DATA_TO_ERROR    V_CL0_RD_DATA_TO_ERROR(1U)
 
+#define S_FUTURE_CEXPANSION_RTS    29
+#define M_FUTURE_CEXPANSION_RTS    0x7U
+#define V_FUTURE_CEXPANSION_RTS(x) ((x) << S_FUTURE_CEXPANSION_RTS)
+#define G_FUTURE_CEXPANSION_RTS(x) (((x) >> S_FUTURE_CEXPANSION_RTS) & M_FUTURE_CEXPANSION_RTS)
+
+#define S_FUTURE_DEXPANSION_RTS    13
+#define M_FUTURE_DEXPANSION_RTS    0x7U
+#define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS)
+#define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS)
+
 #define A_MA_BKP_CNT_SEL 0x78e4
 
 #define S_BKP_CNT_TYPE    30
@@ -12089,6 +17270,11 @@
 
 #define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0
 
+#define S_T5_FUTURE_DEXPANSION    13
+#define M_T5_FUTURE_DEXPANSION    0x7ffffU
+#define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION)
+#define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION)
+
 #define S_CL12_IF_PAR_EN    12
 #define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN)
 #define F_CL12_IF_PAR_EN    V_CL12_IF_PAR_EN(1U)
@@ -12141,8 +17327,18 @@
 #define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN)
 #define F_CL0_IF_PAR_EN    V_CL0_IF_PAR_EN(1U)
 
+#define S_FUTURE_DEXPANSION_IPE    13
+#define M_FUTURE_DEXPANSION_IPE    0x7ffffU
+#define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE)
+#define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE)
+
 #define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
 
+#define S_T5_FUTURE_DEXPANSION    13
+#define M_T5_FUTURE_DEXPANSION    0x7ffffU
+#define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION)
+#define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION)
+
 #define S_CL12_IF_PAR_ERROR    12
 #define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR)
 #define F_CL12_IF_PAR_ERROR    V_CL12_IF_PAR_ERROR(1U)
@@ -12195,6 +17391,11 @@
 #define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR)
 #define F_CL0_IF_PAR_ERROR    V_CL0_IF_PAR_ERROR(1U)
 
+#define S_FUTURE_DEXPANSION_IPS    13
+#define M_FUTURE_DEXPANSION_IPS    0x7ffffU
+#define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS)
+#define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS)
+
 #define A_MA_LOCAL_DEBUG_CFG 0x78f8
 
 #define S_DEBUG_OR    15
@@ -12215,6 +17416,2823 @@
 #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
 
 #define A_MA_LOCAL_DEBUG_RPT 0x78fc
+#define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa000
+
+#define S_CMDVLD0    31
+#define V_CMDVLD0(x) ((x) << S_CMDVLD0)
+#define F_CMDVLD0    V_CMDVLD0(1U)
+
+#define S_CMDRDY0    30
+#define V_CMDRDY0(x) ((x) << S_CMDRDY0)
+#define F_CMDRDY0    V_CMDRDY0(1U)
+
+#define S_CMDTYPE0    29
+#define V_CMDTYPE0(x) ((x) << S_CMDTYPE0)
+#define F_CMDTYPE0    V_CMDTYPE0(1U)
+
+#define S_CMDLEN0    21
+#define M_CMDLEN0    0xffU
+#define V_CMDLEN0(x) ((x) << S_CMDLEN0)
+#define G_CMDLEN0(x) (((x) >> S_CMDLEN0) & M_CMDLEN0)
+
+#define S_CMDADDR0    8
+#define M_CMDADDR0    0x1fffU
+#define V_CMDADDR0(x) ((x) << S_CMDADDR0)
+#define G_CMDADDR0(x) (((x) >> S_CMDADDR0) & M_CMDADDR0)
+
+#define S_WRDATAVLD0    7
+#define V_WRDATAVLD0(x) ((x) << S_WRDATAVLD0)
+#define F_WRDATAVLD0    V_WRDATAVLD0(1U)
+
+#define S_WRDATARDY0    6
+#define V_WRDATARDY0(x) ((x) << S_WRDATARDY0)
+#define F_WRDATARDY0    V_WRDATARDY0(1U)
+
+#define S_RDDATARDY0    5
+#define V_RDDATARDY0(x) ((x) << S_RDDATARDY0)
+#define F_RDDATARDY0    V_RDDATARDY0(1U)
+
+#define S_RDDATAVLD0    4
+#define V_RDDATAVLD0(x) ((x) << S_RDDATAVLD0)
+#define F_RDDATAVLD0    V_RDDATAVLD0(1U)
+
+#define S_RDDATA0    0
+#define M_RDDATA0    0xfU
+#define V_RDDATA0(x) ((x) << S_RDDATA0)
+#define G_RDDATA0(x) (((x) >> S_RDDATA0) & M_RDDATA0)
+
+#define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa001
+
+#define S_CMDVLD1    31
+#define V_CMDVLD1(x) ((x) << S_CMDVLD1)
+#define F_CMDVLD1    V_CMDVLD1(1U)
+
+#define S_CMDRDY1    30
+#define V_CMDRDY1(x) ((x) << S_CMDRDY1)
+#define F_CMDRDY1    V_CMDRDY1(1U)
+
+#define S_CMDTYPE1    29
+#define V_CMDTYPE1(x) ((x) << S_CMDTYPE1)
+#define F_CMDTYPE1    V_CMDTYPE1(1U)
+
+#define S_CMDLEN1    21
+#define M_CMDLEN1    0xffU
+#define V_CMDLEN1(x) ((x) << S_CMDLEN1)
+#define G_CMDLEN1(x) (((x) >> S_CMDLEN1) & M_CMDLEN1)
+
+#define S_CMDADDR1    8
+#define M_CMDADDR1    0x1fffU
+#define V_CMDADDR1(x) ((x) << S_CMDADDR1)
+#define G_CMDADDR1(x) (((x) >> S_CMDADDR1) & M_CMDADDR1)
+
+#define S_WRDATAVLD1    7
+#define V_WRDATAVLD1(x) ((x) << S_WRDATAVLD1)
+#define F_WRDATAVLD1    V_WRDATAVLD1(1U)
+
+#define S_WRDATARDY1    6
+#define V_WRDATARDY1(x) ((x) << S_WRDATARDY1)
+#define F_WRDATARDY1    V_WRDATARDY1(1U)
+
+#define S_RDDATARDY1    5
+#define V_RDDATARDY1(x) ((x) << S_RDDATARDY1)
+#define F_RDDATARDY1    V_RDDATARDY1(1U)
+
+#define S_RDDATAVLD1    4
+#define V_RDDATAVLD1(x) ((x) << S_RDDATAVLD1)
+#define F_RDDATAVLD1    V_RDDATAVLD1(1U)
+
+#define S_RDDATA1    0
+#define M_RDDATA1    0xfU
+#define V_RDDATA1(x) ((x) << S_RDDATA1)
+#define G_RDDATA1(x) (((x) >> S_RDDATA1) & M_RDDATA1)
+
+#define A_MA_ULP_TX_CLIENT_INTERFACE_EXTERNAL 0xa002
+
+#define S_CMDVLD2    31
+#define V_CMDVLD2(x) ((x) << S_CMDVLD2)
+#define F_CMDVLD2    V_CMDVLD2(1U)
+
+#define S_CMDRDY2    30
+#define V_CMDRDY2(x) ((x) << S_CMDRDY2)
+#define F_CMDRDY2    V_CMDRDY2(1U)
+
+#define S_CMDTYPE2    29
+#define V_CMDTYPE2(x) ((x) << S_CMDTYPE2)
+#define F_CMDTYPE2    V_CMDTYPE2(1U)
+
+#define S_CMDLEN2    21
+#define M_CMDLEN2    0xffU
+#define V_CMDLEN2(x) ((x) << S_CMDLEN2)
+#define G_CMDLEN2(x) (((x) >> S_CMDLEN2) & M_CMDLEN2)
+
+#define S_CMDADDR2    8
+#define M_CMDADDR2    0x1fffU
+#define V_CMDADDR2(x) ((x) << S_CMDADDR2)
+#define G_CMDADDR2(x) (((x) >> S_CMDADDR2) & M_CMDADDR2)
+
+#define S_WRDATAVLD2    7
+#define V_WRDATAVLD2(x) ((x) << S_WRDATAVLD2)
+#define F_WRDATAVLD2    V_WRDATAVLD2(1U)
+
+#define S_WRDATARDY2    6
+#define V_WRDATARDY2(x) ((x) << S_WRDATARDY2)
+#define F_WRDATARDY2    V_WRDATARDY2(1U)
+
+#define S_RDDATARDY2    5
+#define V_RDDATARDY2(x) ((x) << S_RDDATARDY2)
+#define F_RDDATARDY2    V_RDDATARDY2(1U)
+
+#define S_RDDATAVLD2    4
+#define V_RDDATAVLD2(x) ((x) << S_RDDATAVLD2)
+#define F_RDDATAVLD2    V_RDDATAVLD2(1U)
+
+#define S_RDDATA2    0
+#define M_RDDATA2    0xfU
+#define V_RDDATA2(x) ((x) << S_RDDATA2)
+#define G_RDDATA2(x) (((x) >> S_RDDATA2) & M_RDDATA2)
+
+#define A_MA_ULP_RX_CLIENT_INTERFACE_EXTERNAL 0xa003
+
+#define S_CMDVLD3    31
+#define V_CMDVLD3(x) ((x) << S_CMDVLD3)
+#define F_CMDVLD3    V_CMDVLD3(1U)
+
+#define S_CMDRDY3    30
+#define V_CMDRDY3(x) ((x) << S_CMDRDY3)
+#define F_CMDRDY3    V_CMDRDY3(1U)
+
+#define S_CMDTYPE3    29
+#define V_CMDTYPE3(x) ((x) << S_CMDTYPE3)
+#define F_CMDTYPE3    V_CMDTYPE3(1U)
+
+#define S_CMDLEN3    21
+#define M_CMDLEN3    0xffU
+#define V_CMDLEN3(x) ((x) << S_CMDLEN3)
+#define G_CMDLEN3(x) (((x) >> S_CMDLEN3) & M_CMDLEN3)
+
+#define S_CMDADDR3    8
+#define M_CMDADDR3    0x1fffU
+#define V_CMDADDR3(x) ((x) << S_CMDADDR3)
+#define G_CMDADDR3(x) (((x) >> S_CMDADDR3) & M_CMDADDR3)
+
+#define S_WRDATAVLD3    7
+#define V_WRDATAVLD3(x) ((x) << S_WRDATAVLD3)
+#define F_WRDATAVLD3    V_WRDATAVLD3(1U)
+
+#define S_WRDATARDY3    6
+#define V_WRDATARDY3(x) ((x) << S_WRDATARDY3)
+#define F_WRDATARDY3    V_WRDATARDY3(1U)
+
+#define S_RDDATARDY3    5
+#define V_RDDATARDY3(x) ((x) << S_RDDATARDY3)
+#define F_RDDATARDY3    V_RDDATARDY3(1U)
+
+#define S_RDDATAVLD3    4
+#define V_RDDATAVLD3(x) ((x) << S_RDDATAVLD3)
+#define F_RDDATAVLD3    V_RDDATAVLD3(1U)
+
+#define S_RDDATA3    0
+#define M_RDDATA3    0xfU
+#define V_RDDATA3(x) ((x) << S_RDDATA3)
+#define G_RDDATA3(x) (((x) >> S_RDDATA3) & M_RDDATA3)
+
+#define A_MA_ULP_TX_RX_CLIENT_INTERFACE_EXTERNAL 0xa004
+
+#define S_CMDVLD4    31
+#define V_CMDVLD4(x) ((x) << S_CMDVLD4)
+#define F_CMDVLD4    V_CMDVLD4(1U)
+
+#define S_CMDRDY4    30
+#define V_CMDRDY4(x) ((x) << S_CMDRDY4)
+#define F_CMDRDY4    V_CMDRDY4(1U)
+
+#define S_CMDTYPE4    29
+#define V_CMDTYPE4(x) ((x) << S_CMDTYPE4)
+#define F_CMDTYPE4    V_CMDTYPE4(1U)
+
+#define S_CMDLEN4    21
+#define M_CMDLEN4    0xffU
+#define V_CMDLEN4(x) ((x) << S_CMDLEN4)
+#define G_CMDLEN4(x) (((x) >> S_CMDLEN4) & M_CMDLEN4)
+
+#define S_CMDADDR4    8
+#define M_CMDADDR4    0x1fffU
+#define V_CMDADDR4(x) ((x) << S_CMDADDR4)
+#define G_CMDADDR4(x) (((x) >> S_CMDADDR4) & M_CMDADDR4)
+
+#define S_WRDATAVLD4    7
+#define V_WRDATAVLD4(x) ((x) << S_WRDATAVLD4)
+#define F_WRDATAVLD4    V_WRDATAVLD4(1U)
+
+#define S_WRDATARDY4    6
+#define V_WRDATARDY4(x) ((x) << S_WRDATARDY4)
+#define F_WRDATARDY4    V_WRDATARDY4(1U)
+
+#define S_RDDATARDY4    5
+#define V_RDDATARDY4(x) ((x) << S_RDDATARDY4)
+#define F_RDDATARDY4    V_RDDATARDY4(1U)
+
+#define S_RDDATAVLD4    4
+#define V_RDDATAVLD4(x) ((x) << S_RDDATAVLD4)
+#define F_RDDATAVLD4    V_RDDATAVLD4(1U)
+
+#define S_RDDATA4    0
+#define M_RDDATA4    0xfU
+#define V_RDDATA4(x) ((x) << S_RDDATA4)
+#define G_RDDATA4(x) (((x) >> S_RDDATA4) & M_RDDATA4)
+
+#define A_MA_TP_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa005
+
+#define S_CMDVLD5    31
+#define V_CMDVLD5(x) ((x) << S_CMDVLD5)
+#define F_CMDVLD5    V_CMDVLD5(1U)
+
+#define S_CMDRDY5    30
+#define V_CMDRDY5(x) ((x) << S_CMDRDY5)
+#define F_CMDRDY5    V_CMDRDY5(1U)
+
+#define S_CMDTYPE5    29
+#define V_CMDTYPE5(x) ((x) << S_CMDTYPE5)
+#define F_CMDTYPE5    V_CMDTYPE5(1U)
+
+#define S_CMDLEN5    21
+#define M_CMDLEN5    0xffU
+#define V_CMDLEN5(x) ((x) << S_CMDLEN5)
+#define G_CMDLEN5(x) (((x) >> S_CMDLEN5) & M_CMDLEN5)
+
+#define S_CMDADDR5    8
+#define M_CMDADDR5    0x1fffU
+#define V_CMDADDR5(x) ((x) << S_CMDADDR5)
+#define G_CMDADDR5(x) (((x) >> S_CMDADDR5) & M_CMDADDR5)
+
+#define S_WRDATAVLD5    7
+#define V_WRDATAVLD5(x) ((x) << S_WRDATAVLD5)
+#define F_WRDATAVLD5    V_WRDATAVLD5(1U)
+
+#define S_WRDATARDY5    6
+#define V_WRDATARDY5(x) ((x) << S_WRDATARDY5)
+#define F_WRDATARDY5    V_WRDATARDY5(1U)
+
+#define S_RDDATARDY5    5
+#define V_RDDATARDY5(x) ((x) << S_RDDATARDY5)
+#define F_RDDATARDY5    V_RDDATARDY5(1U)
+
+#define S_RDDATAVLD5    4
+#define V_RDDATAVLD5(x) ((x) << S_RDDATAVLD5)
+#define F_RDDATAVLD5    V_RDDATAVLD5(1U)
+
+#define S_RDDATA5    0
+#define M_RDDATA5    0xfU
+#define V_RDDATA5(x) ((x) << S_RDDATA5)
+#define G_RDDATA5(x) (((x) >> S_RDDATA5) & M_RDDATA5)
+
+#define A_MA_TP_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa006
+
+#define S_CMDVLD6    31
+#define V_CMDVLD6(x) ((x) << S_CMDVLD6)
+#define F_CMDVLD6    V_CMDVLD6(1U)
+
+#define S_CMDRDY6    30
+#define V_CMDRDY6(x) ((x) << S_CMDRDY6)
+#define F_CMDRDY6    V_CMDRDY6(1U)
+
+#define S_CMDTYPE6    29
+#define V_CMDTYPE6(x) ((x) << S_CMDTYPE6)
+#define F_CMDTYPE6    V_CMDTYPE6(1U)
+
+#define S_CMDLEN6    21
+#define M_CMDLEN6    0xffU
+#define V_CMDLEN6(x) ((x) << S_CMDLEN6)
+#define G_CMDLEN6(x) (((x) >> S_CMDLEN6) & M_CMDLEN6)
+
+#define S_CMDADDR6    8
+#define M_CMDADDR6    0x1fffU
+#define V_CMDADDR6(x) ((x) << S_CMDADDR6)
+#define G_CMDADDR6(x) (((x) >> S_CMDADDR6) & M_CMDADDR6)
+
+#define S_WRDATAVLD6    7
+#define V_WRDATAVLD6(x) ((x) << S_WRDATAVLD6)
+#define F_WRDATAVLD6    V_WRDATAVLD6(1U)
+
+#define S_WRDATARDY6    6
+#define V_WRDATARDY6(x) ((x) << S_WRDATARDY6)
+#define F_WRDATARDY6    V_WRDATARDY6(1U)
+
+#define S_RDDATARDY6    5
+#define V_RDDATARDY6(x) ((x) << S_RDDATARDY6)
+#define F_RDDATARDY6    V_RDDATARDY6(1U)
+
+#define S_RDDATAVLD6    4
+#define V_RDDATAVLD6(x) ((x) << S_RDDATAVLD6)
+#define F_RDDATAVLD6    V_RDDATAVLD6(1U)
+
+#define S_RDDATA6    0
+#define M_RDDATA6    0xfU
+#define V_RDDATA6(x) ((x) << S_RDDATA6)
+#define G_RDDATA6(x) (((x) >> S_RDDATA6) & M_RDDATA6)
+
+#define A_MA_LE_CLIENT_INTERFACE_EXTERNAL 0xa007
+
+#define S_CMDVLD7    31
+#define V_CMDVLD7(x) ((x) << S_CMDVLD7)
+#define F_CMDVLD7    V_CMDVLD7(1U)
+
+#define S_CMDRDY7    30
+#define V_CMDRDY7(x) ((x) << S_CMDRDY7)
+#define F_CMDRDY7    V_CMDRDY7(1U)
+
+#define S_CMDTYPE7    29
+#define V_CMDTYPE7(x) ((x) << S_CMDTYPE7)
+#define F_CMDTYPE7    V_CMDTYPE7(1U)
+
+#define S_CMDLEN7    21
+#define M_CMDLEN7    0xffU
+#define V_CMDLEN7(x) ((x) << S_CMDLEN7)
+#define G_CMDLEN7(x) (((x) >> S_CMDLEN7) & M_CMDLEN7)
+
+#define S_CMDADDR7    8
+#define M_CMDADDR7    0x1fffU
+#define V_CMDADDR7(x) ((x) << S_CMDADDR7)
+#define G_CMDADDR7(x) (((x) >> S_CMDADDR7) & M_CMDADDR7)
+
+#define S_WRDATAVLD7    7
+#define V_WRDATAVLD7(x) ((x) << S_WRDATAVLD7)
+#define F_WRDATAVLD7    V_WRDATAVLD7(1U)
+
+#define S_WRDATARDY7    6
+#define V_WRDATARDY7(x) ((x) << S_WRDATARDY7)
+#define F_WRDATARDY7    V_WRDATARDY7(1U)
+
+#define S_RDDATARDY7    5
+#define V_RDDATARDY7(x) ((x) << S_RDDATARDY7)
+#define F_RDDATARDY7    V_RDDATARDY7(1U)
+
+#define S_RDDATAVLD7    4
+#define V_RDDATAVLD7(x) ((x) << S_RDDATAVLD7)
+#define F_RDDATAVLD7    V_RDDATAVLD7(1U)
+
+#define S_RDDATA7    0
+#define M_RDDATA7    0xfU
+#define V_RDDATA7(x) ((x) << S_RDDATA7)
+#define G_RDDATA7(x) (((x) >> S_RDDATA7) & M_RDDATA7)
+
+#define A_MA_CIM_CLIENT_INTERFACE_EXTERNAL 0xa008
+
+#define S_CMDVLD8    31
+#define V_CMDVLD8(x) ((x) << S_CMDVLD8)
+#define F_CMDVLD8    V_CMDVLD8(1U)
+
+#define S_CMDRDY8    30
+#define V_CMDRDY8(x) ((x) << S_CMDRDY8)
+#define F_CMDRDY8    V_CMDRDY8(1U)
+
+#define S_CMDTYPE8    29
+#define V_CMDTYPE8(x) ((x) << S_CMDTYPE8)
+#define F_CMDTYPE8    V_CMDTYPE8(1U)
+
+#define S_CMDLEN8    21
+#define M_CMDLEN8    0xffU
+#define V_CMDLEN8(x) ((x) << S_CMDLEN8)
+#define G_CMDLEN8(x) (((x) >> S_CMDLEN8) & M_CMDLEN8)
+
+#define S_CMDADDR8    8
+#define M_CMDADDR8    0x1fffU
+#define V_CMDADDR8(x) ((x) << S_CMDADDR8)
+#define G_CMDADDR8(x) (((x) >> S_CMDADDR8) & M_CMDADDR8)
+
+#define S_WRDATAVLD8    7
+#define V_WRDATAVLD8(x) ((x) << S_WRDATAVLD8)
+#define F_WRDATAVLD8    V_WRDATAVLD8(1U)
+
+#define S_WRDATARDY8    6
+#define V_WRDATARDY8(x) ((x) << S_WRDATARDY8)
+#define F_WRDATARDY8    V_WRDATARDY8(1U)
+
+#define S_RDDATARDY8    5
+#define V_RDDATARDY8(x) ((x) << S_RDDATARDY8)
+#define F_RDDATARDY8    V_RDDATARDY8(1U)
+
+#define S_RDDATAVLD8    4
+#define V_RDDATAVLD8(x) ((x) << S_RDDATAVLD8)
+#define F_RDDATAVLD8    V_RDDATAVLD8(1U)
+
+#define S_RDDATA8    0
+#define M_RDDATA8    0xfU
+#define V_RDDATA8(x) ((x) << S_RDDATA8)
+#define G_RDDATA8(x) (((x) >> S_RDDATA8) & M_RDDATA8)
+
+#define A_MA_PCIE_CLIENT_INTERFACE_EXTERNAL 0xa009
+
+#define S_CMDVLD9    31
+#define V_CMDVLD9(x) ((x) << S_CMDVLD9)
+#define F_CMDVLD9    V_CMDVLD9(1U)
+
+#define S_CMDRDY9    30
+#define V_CMDRDY9(x) ((x) << S_CMDRDY9)
+#define F_CMDRDY9    V_CMDRDY9(1U)
+
+#define S_CMDTYPE9    29
+#define V_CMDTYPE9(x) ((x) << S_CMDTYPE9)
+#define F_CMDTYPE9    V_CMDTYPE9(1U)
+
+#define S_CMDLEN9    21
+#define M_CMDLEN9    0xffU
+#define V_CMDLEN9(x) ((x) << S_CMDLEN9)
+#define G_CMDLEN9(x) (((x) >> S_CMDLEN9) & M_CMDLEN9)
+
+#define S_CMDADDR9    8
+#define M_CMDADDR9    0x1fffU
+#define V_CMDADDR9(x) ((x) << S_CMDADDR9)
+#define G_CMDADDR9(x) (((x) >> S_CMDADDR9) & M_CMDADDR9)
+
+#define S_WRDATAVLD9    7
+#define V_WRDATAVLD9(x) ((x) << S_WRDATAVLD9)
+#define F_WRDATAVLD9    V_WRDATAVLD9(1U)
+
+#define S_WRDATARDY9    6
+#define V_WRDATARDY9(x) ((x) << S_WRDATARDY9)
+#define F_WRDATARDY9    V_WRDATARDY9(1U)
+
+#define S_RDDATARDY9    5
+#define V_RDDATARDY9(x) ((x) << S_RDDATARDY9)
+#define F_RDDATARDY9    V_RDDATARDY9(1U)
+
+#define S_RDDATAVLD9    4
+#define V_RDDATAVLD9(x) ((x) << S_RDDATAVLD9)
+#define F_RDDATAVLD9    V_RDDATAVLD9(1U)
+
+#define S_RDDATA9    0
+#define M_RDDATA9    0xfU
+#define V_RDDATA9(x) ((x) << S_RDDATA9)
+#define G_RDDATA9(x) (((x) >> S_RDDATA9) & M_RDDATA9)
+
+#define A_MA_PM_TX_CLIENT_INTERFACE_EXTERNAL 0xa00a
+
+#define S_CMDVLD10    31
+#define V_CMDVLD10(x) ((x) << S_CMDVLD10)
+#define F_CMDVLD10    V_CMDVLD10(1U)
+
+#define S_CMDRDY10    30
+#define V_CMDRDY10(x) ((x) << S_CMDRDY10)
+#define F_CMDRDY10    V_CMDRDY10(1U)
+
+#define S_CMDTYPE10    29
+#define V_CMDTYPE10(x) ((x) << S_CMDTYPE10)
+#define F_CMDTYPE10    V_CMDTYPE10(1U)
+
+#define S_CMDLEN10    21
+#define M_CMDLEN10    0xffU
+#define V_CMDLEN10(x) ((x) << S_CMDLEN10)
+#define G_CMDLEN10(x) (((x) >> S_CMDLEN10) & M_CMDLEN10)
+
+#define S_CMDADDR10    8
+#define M_CMDADDR10    0x1fffU
+#define V_CMDADDR10(x) ((x) << S_CMDADDR10)
+#define G_CMDADDR10(x) (((x) >> S_CMDADDR10) & M_CMDADDR10)
+
+#define S_WRDATAVLD10    7
+#define V_WRDATAVLD10(x) ((x) << S_WRDATAVLD10)
+#define F_WRDATAVLD10    V_WRDATAVLD10(1U)
+
+#define S_WRDATARDY10    6
+#define V_WRDATARDY10(x) ((x) << S_WRDATARDY10)
+#define F_WRDATARDY10    V_WRDATARDY10(1U)
+
+#define S_RDDATARDY10    5
+#define V_RDDATARDY10(x) ((x) << S_RDDATARDY10)
+#define F_RDDATARDY10    V_RDDATARDY10(1U)
+
+#define S_RDDATAVLD10    4
+#define V_RDDATAVLD10(x) ((x) << S_RDDATAVLD10)
+#define F_RDDATAVLD10    V_RDDATAVLD10(1U)
+
+#define S_RDDATA10    0
+#define M_RDDATA10    0xfU
+#define V_RDDATA10(x) ((x) << S_RDDATA10)
+#define G_RDDATA10(x) (((x) >> S_RDDATA10) & M_RDDATA10)
+
+#define A_MA_PM_RX_CLIENT_INTERFACE_EXTERNAL 0xa00b
+
+#define S_CMDVLD11    31
+#define V_CMDVLD11(x) ((x) << S_CMDVLD11)
+#define F_CMDVLD11    V_CMDVLD11(1U)
+
+#define S_CMDRDY11    30
+#define V_CMDRDY11(x) ((x) << S_CMDRDY11)
+#define F_CMDRDY11    V_CMDRDY11(1U)
+
+#define S_CMDTYPE11    29
+#define V_CMDTYPE11(x) ((x) << S_CMDTYPE11)
+#define F_CMDTYPE11    V_CMDTYPE11(1U)
+
+#define S_CMDLEN11    21
+#define M_CMDLEN11    0xffU
+#define V_CMDLEN11(x) ((x) << S_CMDLEN11)
+#define G_CMDLEN11(x) (((x) >> S_CMDLEN11) & M_CMDLEN11)
+
+#define S_CMDADDR11    8
+#define M_CMDADDR11    0x1fffU
+#define V_CMDADDR11(x) ((x) << S_CMDADDR11)
+#define G_CMDADDR11(x) (((x) >> S_CMDADDR11) & M_CMDADDR11)
+
+#define S_WRDATAVLD11    7
+#define V_WRDATAVLD11(x) ((x) << S_WRDATAVLD11)
+#define F_WRDATAVLD11    V_WRDATAVLD11(1U)
+
+#define S_WRDATARDY11    6
+#define V_WRDATARDY11(x) ((x) << S_WRDATARDY11)
+#define F_WRDATARDY11    V_WRDATARDY11(1U)
+
+#define S_RDDATARDY11    5
+#define V_RDDATARDY11(x) ((x) << S_RDDATARDY11)
+#define F_RDDATARDY11    V_RDDATARDY11(1U)
+
+#define S_RDDATAVLD11    4
+#define V_RDDATAVLD11(x) ((x) << S_RDDATAVLD11)
+#define F_RDDATAVLD11    V_RDDATAVLD11(1U)
+
+#define S_RDDATA11    0
+#define M_RDDATA11    0xfU
+#define V_RDDATA11(x) ((x) << S_RDDATA11)
+#define G_RDDATA11(x) (((x) >> S_RDDATA11) & M_RDDATA11)
+
+#define A_MA_HMA_CLIENT_INTERFACE_EXTERNAL 0xa00c
+
+#define S_CMDVLD12    31
+#define V_CMDVLD12(x) ((x) << S_CMDVLD12)
+#define F_CMDVLD12    V_CMDVLD12(1U)
+
+#define S_CMDRDY12    30
+#define V_CMDRDY12(x) ((x) << S_CMDRDY12)
+#define F_CMDRDY12    V_CMDRDY12(1U)
+
+#define S_CMDTYPE12    29
+#define V_CMDTYPE12(x) ((x) << S_CMDTYPE12)
+#define F_CMDTYPE12    V_CMDTYPE12(1U)
+
+#define S_CMDLEN12    21
+#define M_CMDLEN12    0xffU
+#define V_CMDLEN12(x) ((x) << S_CMDLEN12)
+#define G_CMDLEN12(x) (((x) >> S_CMDLEN12) & M_CMDLEN12)
+
+#define S_CMDADDR12    8
+#define M_CMDADDR12    0x1fffU
+#define V_CMDADDR12(x) ((x) << S_CMDADDR12)
+#define G_CMDADDR12(x) (((x) >> S_CMDADDR12) & M_CMDADDR12)
+
+#define S_WRDATAVLD12    7
+#define V_WRDATAVLD12(x) ((x) << S_WRDATAVLD12)
+#define F_WRDATAVLD12    V_WRDATAVLD12(1U)
+
+#define S_WRDATARDY12    6
+#define V_WRDATARDY12(x) ((x) << S_WRDATARDY12)
+#define F_WRDATARDY12    V_WRDATARDY12(1U)
+
+#define S_RDDATARDY12    5
+#define V_RDDATARDY12(x) ((x) << S_RDDATARDY12)
+#define F_RDDATARDY12    V_RDDATARDY12(1U)
+
+#define S_RDDATAVLD12    4
+#define V_RDDATAVLD12(x) ((x) << S_RDDATAVLD12)
+#define F_RDDATAVLD12    V_RDDATAVLD12(1U)
+
+#define S_RDDATA12    0
+#define M_RDDATA12    0xfU
+#define V_RDDATA12(x) ((x) << S_RDDATA12)
+#define G_RDDATA12(x) (((x) >> S_RDDATA12) & M_RDDATA12)
+
+#define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00d
+
+#define S_CI0_ARB0_REQ    31
+#define V_CI0_ARB0_REQ(x) ((x) << S_CI0_ARB0_REQ)
+#define F_CI0_ARB0_REQ    V_CI0_ARB0_REQ(1U)
+
+#define S_ARB0_CI0_GNT    30
+#define V_ARB0_CI0_GNT(x) ((x) << S_ARB0_CI0_GNT)
+#define F_ARB0_CI0_GNT    V_ARB0_CI0_GNT(1U)
+
+#define S_CI0_DM0_WDATA_VLD    29
+#define V_CI0_DM0_WDATA_VLD(x) ((x) << S_CI0_DM0_WDATA_VLD)
+#define F_CI0_DM0_WDATA_VLD    V_CI0_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI0_RDATA_VLD    28
+#define V_DM0_CI0_RDATA_VLD(x) ((x) << S_DM0_CI0_RDATA_VLD)
+#define F_DM0_CI0_RDATA_VLD    V_DM0_CI0_RDATA_VLD(1U)
+
+#define S_CI1_ARB0_REQ    27
+#define V_CI1_ARB0_REQ(x) ((x) << S_CI1_ARB0_REQ)
+#define F_CI1_ARB0_REQ    V_CI1_ARB0_REQ(1U)
+
+#define S_ARB0_CI1_GNT    26
+#define V_ARB0_CI1_GNT(x) ((x) << S_ARB0_CI1_GNT)
+#define F_ARB0_CI1_GNT    V_ARB0_CI1_GNT(1U)
+
+#define S_CI1_DM0_WDATA_VLD    25
+#define V_CI1_DM0_WDATA_VLD(x) ((x) << S_CI1_DM0_WDATA_VLD)
+#define F_CI1_DM0_WDATA_VLD    V_CI1_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI1_RDATA_VLD    24
+#define V_DM0_CI1_RDATA_VLD(x) ((x) << S_DM0_CI1_RDATA_VLD)
+#define F_DM0_CI1_RDATA_VLD    V_DM0_CI1_RDATA_VLD(1U)
+
+#define S_CI2_ARB0_REQ    23
+#define V_CI2_ARB0_REQ(x) ((x) << S_CI2_ARB0_REQ)
+#define F_CI2_ARB0_REQ    V_CI2_ARB0_REQ(1U)
+
+#define S_ARB0_CI2_GNT    22
+#define V_ARB0_CI2_GNT(x) ((x) << S_ARB0_CI2_GNT)
+#define F_ARB0_CI2_GNT    V_ARB0_CI2_GNT(1U)
+
+#define S_CI2_DM0_WDATA_VLD    21
+#define V_CI2_DM0_WDATA_VLD(x) ((x) << S_CI2_DM0_WDATA_VLD)
+#define F_CI2_DM0_WDATA_VLD    V_CI2_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI2_RDATA_VLD    20
+#define V_DM0_CI2_RDATA_VLD(x) ((x) << S_DM0_CI2_RDATA_VLD)
+#define F_DM0_CI2_RDATA_VLD    V_DM0_CI2_RDATA_VLD(1U)
+
+#define S_CI3_ARB0_REQ    19
+#define V_CI3_ARB0_REQ(x) ((x) << S_CI3_ARB0_REQ)
+#define F_CI3_ARB0_REQ    V_CI3_ARB0_REQ(1U)
+
+#define S_ARB0_CI3_GNT    18
+#define V_ARB0_CI3_GNT(x) ((x) << S_ARB0_CI3_GNT)
+#define F_ARB0_CI3_GNT    V_ARB0_CI3_GNT(1U)
+
+#define S_CI3_DM0_WDATA_VLD    17
+#define V_CI3_DM0_WDATA_VLD(x) ((x) << S_CI3_DM0_WDATA_VLD)
+#define F_CI3_DM0_WDATA_VLD    V_CI3_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI3_RDATA_VLD    16
+#define V_DM0_CI3_RDATA_VLD(x) ((x) << S_DM0_CI3_RDATA_VLD)
+#define F_DM0_CI3_RDATA_VLD    V_DM0_CI3_RDATA_VLD(1U)
+
+#define S_CI4_ARB0_REQ    15
+#define V_CI4_ARB0_REQ(x) ((x) << S_CI4_ARB0_REQ)
+#define F_CI4_ARB0_REQ    V_CI4_ARB0_REQ(1U)
+
+#define S_ARB0_CI4_GNT    14
+#define V_ARB0_CI4_GNT(x) ((x) << S_ARB0_CI4_GNT)
+#define F_ARB0_CI4_GNT    V_ARB0_CI4_GNT(1U)
+
+#define S_CI4_DM0_WDATA_VLD    13
+#define V_CI4_DM0_WDATA_VLD(x) ((x) << S_CI4_DM0_WDATA_VLD)
+#define F_CI4_DM0_WDATA_VLD    V_CI4_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI4_RDATA_VLD    12
+#define V_DM0_CI4_RDATA_VLD(x) ((x) << S_DM0_CI4_RDATA_VLD)
+#define F_DM0_CI4_RDATA_VLD    V_DM0_CI4_RDATA_VLD(1U)
+
+#define S_CI5_ARB0_REQ    11
+#define V_CI5_ARB0_REQ(x) ((x) << S_CI5_ARB0_REQ)
+#define F_CI5_ARB0_REQ    V_CI5_ARB0_REQ(1U)
+
+#define S_ARB0_CI5_GNT    10
+#define V_ARB0_CI5_GNT(x) ((x) << S_ARB0_CI5_GNT)
+#define F_ARB0_CI5_GNT    V_ARB0_CI5_GNT(1U)
+
+#define S_CI5_DM0_WDATA_VLD    9
+#define V_CI5_DM0_WDATA_VLD(x) ((x) << S_CI5_DM0_WDATA_VLD)
+#define F_CI5_DM0_WDATA_VLD    V_CI5_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI5_RDATA_VLD    8
+#define V_DM0_CI5_RDATA_VLD(x) ((x) << S_DM0_CI5_RDATA_VLD)
+#define F_DM0_CI5_RDATA_VLD    V_DM0_CI5_RDATA_VLD(1U)
+
+#define S_CI6_ARB0_REQ    7
+#define V_CI6_ARB0_REQ(x) ((x) << S_CI6_ARB0_REQ)
+#define F_CI6_ARB0_REQ    V_CI6_ARB0_REQ(1U)
+
+#define S_ARB0_CI6_GNT    6
+#define V_ARB0_CI6_GNT(x) ((x) << S_ARB0_CI6_GNT)
+#define F_ARB0_CI6_GNT    V_ARB0_CI6_GNT(1U)
+
+#define S_CI6_DM0_WDATA_VLD    5
+#define V_CI6_DM0_WDATA_VLD(x) ((x) << S_CI6_DM0_WDATA_VLD)
+#define F_CI6_DM0_WDATA_VLD    V_CI6_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI6_RDATA_VLD    4
+#define V_DM0_CI6_RDATA_VLD(x) ((x) << S_DM0_CI6_RDATA_VLD)
+#define F_DM0_CI6_RDATA_VLD    V_DM0_CI6_RDATA_VLD(1U)
+
+#define S_CI7_ARB0_REQ    3
+#define V_CI7_ARB0_REQ(x) ((x) << S_CI7_ARB0_REQ)
+#define F_CI7_ARB0_REQ    V_CI7_ARB0_REQ(1U)
+
+#define S_ARB0_CI7_GNT    2
+#define V_ARB0_CI7_GNT(x) ((x) << S_ARB0_CI7_GNT)
+#define F_ARB0_CI7_GNT    V_ARB0_CI7_GNT(1U)
+
+#define S_CI7_DM0_WDATA_VLD    1
+#define V_CI7_DM0_WDATA_VLD(x) ((x) << S_CI7_DM0_WDATA_VLD)
+#define F_CI7_DM0_WDATA_VLD    V_CI7_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI7_RDATA_VLD    0
+#define V_DM0_CI7_RDATA_VLD(x) ((x) << S_DM0_CI7_RDATA_VLD)
+#define F_DM0_CI7_RDATA_VLD    V_DM0_CI7_RDATA_VLD(1U)
+
+#define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00e
+
+#define S_CI0_ARB1_REQ    31
+#define V_CI0_ARB1_REQ(x) ((x) << S_CI0_ARB1_REQ)
+#define F_CI0_ARB1_REQ    V_CI0_ARB1_REQ(1U)
+
+#define S_ARB1_CI0_GNT    30
+#define V_ARB1_CI0_GNT(x) ((x) << S_ARB1_CI0_GNT)
+#define F_ARB1_CI0_GNT    V_ARB1_CI0_GNT(1U)
+
+#define S_CI0_DM1_WDATA_VLD    29
+#define V_CI0_DM1_WDATA_VLD(x) ((x) << S_CI0_DM1_WDATA_VLD)
+#define F_CI0_DM1_WDATA_VLD    V_CI0_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI0_RDATA_VLD    28
+#define V_DM1_CI0_RDATA_VLD(x) ((x) << S_DM1_CI0_RDATA_VLD)
+#define F_DM1_CI0_RDATA_VLD    V_DM1_CI0_RDATA_VLD(1U)
+
+#define S_CI1_ARB1_REQ    27
+#define V_CI1_ARB1_REQ(x) ((x) << S_CI1_ARB1_REQ)
+#define F_CI1_ARB1_REQ    V_CI1_ARB1_REQ(1U)
+
+#define S_ARB1_CI1_GNT    26
+#define V_ARB1_CI1_GNT(x) ((x) << S_ARB1_CI1_GNT)
+#define F_ARB1_CI1_GNT    V_ARB1_CI1_GNT(1U)
+
+#define S_CI1_DM1_WDATA_VLD    25
+#define V_CI1_DM1_WDATA_VLD(x) ((x) << S_CI1_DM1_WDATA_VLD)
+#define F_CI1_DM1_WDATA_VLD    V_CI1_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI1_RDATA_VLD    24
+#define V_DM1_CI1_RDATA_VLD(x) ((x) << S_DM1_CI1_RDATA_VLD)
+#define F_DM1_CI1_RDATA_VLD    V_DM1_CI1_RDATA_VLD(1U)
+
+#define S_CI2_ARB1_REQ    23
+#define V_CI2_ARB1_REQ(x) ((x) << S_CI2_ARB1_REQ)
+#define F_CI2_ARB1_REQ    V_CI2_ARB1_REQ(1U)
+
+#define S_ARB1_CI2_GNT    22
+#define V_ARB1_CI2_GNT(x) ((x) << S_ARB1_CI2_GNT)
+#define F_ARB1_CI2_GNT    V_ARB1_CI2_GNT(1U)
+
+#define S_CI2_DM1_WDATA_VLD    21
+#define V_CI2_DM1_WDATA_VLD(x) ((x) << S_CI2_DM1_WDATA_VLD)
+#define F_CI2_DM1_WDATA_VLD    V_CI2_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI2_RDATA_VLD    20
+#define V_DM1_CI2_RDATA_VLD(x) ((x) << S_DM1_CI2_RDATA_VLD)
+#define F_DM1_CI2_RDATA_VLD    V_DM1_CI2_RDATA_VLD(1U)
+
+#define S_CI3_ARB1_REQ    19
+#define V_CI3_ARB1_REQ(x) ((x) << S_CI3_ARB1_REQ)
+#define F_CI3_ARB1_REQ    V_CI3_ARB1_REQ(1U)
+
+#define S_ARB1_CI3_GNT    18
+#define V_ARB1_CI3_GNT(x) ((x) << S_ARB1_CI3_GNT)
+#define F_ARB1_CI3_GNT    V_ARB1_CI3_GNT(1U)
+
+#define S_CI3_DM1_WDATA_VLD    17
+#define V_CI3_DM1_WDATA_VLD(x) ((x) << S_CI3_DM1_WDATA_VLD)
+#define F_CI3_DM1_WDATA_VLD    V_CI3_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI3_RDATA_VLD    16
+#define V_DM1_CI3_RDATA_VLD(x) ((x) << S_DM1_CI3_RDATA_VLD)
+#define F_DM1_CI3_RDATA_VLD    V_DM1_CI3_RDATA_VLD(1U)
+
+#define S_CI4_ARB1_REQ    15
+#define V_CI4_ARB1_REQ(x) ((x) << S_CI4_ARB1_REQ)
+#define F_CI4_ARB1_REQ    V_CI4_ARB1_REQ(1U)
+
+#define S_ARB1_CI4_GNT    14
+#define V_ARB1_CI4_GNT(x) ((x) << S_ARB1_CI4_GNT)
+#define F_ARB1_CI4_GNT    V_ARB1_CI4_GNT(1U)
+
+#define S_CI4_DM1_WDATA_VLD    13
+#define V_CI4_DM1_WDATA_VLD(x) ((x) << S_CI4_DM1_WDATA_VLD)
+#define F_CI4_DM1_WDATA_VLD    V_CI4_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI4_RDATA_VLD    12
+#define V_DM1_CI4_RDATA_VLD(x) ((x) << S_DM1_CI4_RDATA_VLD)
+#define F_DM1_CI4_RDATA_VLD    V_DM1_CI4_RDATA_VLD(1U)
+
+#define S_CI5_ARB1_REQ    11
+#define V_CI5_ARB1_REQ(x) ((x) << S_CI5_ARB1_REQ)
+#define F_CI5_ARB1_REQ    V_CI5_ARB1_REQ(1U)
+
+#define S_ARB1_CI5_GNT    10
+#define V_ARB1_CI5_GNT(x) ((x) << S_ARB1_CI5_GNT)
+#define F_ARB1_CI5_GNT    V_ARB1_CI5_GNT(1U)
+
+#define S_CI5_DM1_WDATA_VLD    9
+#define V_CI5_DM1_WDATA_VLD(x) ((x) << S_CI5_DM1_WDATA_VLD)
+#define F_CI5_DM1_WDATA_VLD    V_CI5_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI5_RDATA_VLD    8
+#define V_DM1_CI5_RDATA_VLD(x) ((x) << S_DM1_CI5_RDATA_VLD)
+#define F_DM1_CI5_RDATA_VLD    V_DM1_CI5_RDATA_VLD(1U)
+
+#define S_CI6_ARB1_REQ    7
+#define V_CI6_ARB1_REQ(x) ((x) << S_CI6_ARB1_REQ)
+#define F_CI6_ARB1_REQ    V_CI6_ARB1_REQ(1U)
+
+#define S_ARB1_CI6_GNT    6
+#define V_ARB1_CI6_GNT(x) ((x) << S_ARB1_CI6_GNT)
+#define F_ARB1_CI6_GNT    V_ARB1_CI6_GNT(1U)
+
+#define S_CI6_DM1_WDATA_VLD    5
+#define V_CI6_DM1_WDATA_VLD(x) ((x) << S_CI6_DM1_WDATA_VLD)
+#define F_CI6_DM1_WDATA_VLD    V_CI6_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI6_RDATA_VLD    4
+#define V_DM1_CI6_RDATA_VLD(x) ((x) << S_DM1_CI6_RDATA_VLD)
+#define F_DM1_CI6_RDATA_VLD    V_DM1_CI6_RDATA_VLD(1U)
+
+#define S_CI7_ARB1_REQ    3
+#define V_CI7_ARB1_REQ(x) ((x) << S_CI7_ARB1_REQ)
+#define F_CI7_ARB1_REQ    V_CI7_ARB1_REQ(1U)
+
+#define S_ARB1_CI7_GNT    2
+#define V_ARB1_CI7_GNT(x) ((x) << S_ARB1_CI7_GNT)
+#define F_ARB1_CI7_GNT    V_ARB1_CI7_GNT(1U)
+
+#define S_CI7_DM1_WDATA_VLD    1
+#define V_CI7_DM1_WDATA_VLD(x) ((x) << S_CI7_DM1_WDATA_VLD)
+#define F_CI7_DM1_WDATA_VLD    V_CI7_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI7_RDATA_VLD    0
+#define V_DM1_CI7_RDATA_VLD(x) ((x) << S_DM1_CI7_RDATA_VLD)
+#define F_DM1_CI7_RDATA_VLD    V_DM1_CI7_RDATA_VLD(1U)
+
+#define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00f
+
+#define S_CI0_ARB2_REQ    31
+#define V_CI0_ARB2_REQ(x) ((x) << S_CI0_ARB2_REQ)
+#define F_CI0_ARB2_REQ    V_CI0_ARB2_REQ(1U)
+
+#define S_ARB2_CI0_GNT    30
+#define V_ARB2_CI0_GNT(x) ((x) << S_ARB2_CI0_GNT)
+#define F_ARB2_CI0_GNT    V_ARB2_CI0_GNT(1U)
+
+#define S_CI0_DM2_WDATA_VLD    29
+#define V_CI0_DM2_WDATA_VLD(x) ((x) << S_CI0_DM2_WDATA_VLD)
+#define F_CI0_DM2_WDATA_VLD    V_CI0_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI0_RDATA_VLD    28
+#define V_DM2_CI0_RDATA_VLD(x) ((x) << S_DM2_CI0_RDATA_VLD)
+#define F_DM2_CI0_RDATA_VLD    V_DM2_CI0_RDATA_VLD(1U)
+
+#define S_CI1_ARB2_REQ    27
+#define V_CI1_ARB2_REQ(x) ((x) << S_CI1_ARB2_REQ)
+#define F_CI1_ARB2_REQ    V_CI1_ARB2_REQ(1U)
+
+#define S_ARB2_CI1_GNT    26
+#define V_ARB2_CI1_GNT(x) ((x) << S_ARB2_CI1_GNT)
+#define F_ARB2_CI1_GNT    V_ARB2_CI1_GNT(1U)
+
+#define S_CI1_DM2_WDATA_VLD    25
+#define V_CI1_DM2_WDATA_VLD(x) ((x) << S_CI1_DM2_WDATA_VLD)
+#define F_CI1_DM2_WDATA_VLD    V_CI1_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI1_RDATA_VLD    24
+#define V_DM2_CI1_RDATA_VLD(x) ((x) << S_DM2_CI1_RDATA_VLD)
+#define F_DM2_CI1_RDATA_VLD    V_DM2_CI1_RDATA_VLD(1U)
+
+#define S_CI2_ARB2_REQ    23
+#define V_CI2_ARB2_REQ(x) ((x) << S_CI2_ARB2_REQ)
+#define F_CI2_ARB2_REQ    V_CI2_ARB2_REQ(1U)
+
+#define S_ARB2_CI2_GNT    22
+#define V_ARB2_CI2_GNT(x) ((x) << S_ARB2_CI2_GNT)
+#define F_ARB2_CI2_GNT    V_ARB2_CI2_GNT(1U)
+
+#define S_CI2_DM2_WDATA_VLD    21
+#define V_CI2_DM2_WDATA_VLD(x) ((x) << S_CI2_DM2_WDATA_VLD)
+#define F_CI2_DM2_WDATA_VLD    V_CI2_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI2_RDATA_VLD    20
+#define V_DM2_CI2_RDATA_VLD(x) ((x) << S_DM2_CI2_RDATA_VLD)
+#define F_DM2_CI2_RDATA_VLD    V_DM2_CI2_RDATA_VLD(1U)
+
+#define S_CI3_ARB2_REQ    19
+#define V_CI3_ARB2_REQ(x) ((x) << S_CI3_ARB2_REQ)
+#define F_CI3_ARB2_REQ    V_CI3_ARB2_REQ(1U)
+
+#define S_ARB2_CI3_GNT    18
+#define V_ARB2_CI3_GNT(x) ((x) << S_ARB2_CI3_GNT)
+#define F_ARB2_CI3_GNT    V_ARB2_CI3_GNT(1U)
+
+#define S_CI3_DM2_WDATA_VLD    17
+#define V_CI3_DM2_WDATA_VLD(x) ((x) << S_CI3_DM2_WDATA_VLD)
+#define F_CI3_DM2_WDATA_VLD    V_CI3_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI3_RDATA_VLD    16
+#define V_DM2_CI3_RDATA_VLD(x) ((x) << S_DM2_CI3_RDATA_VLD)
+#define F_DM2_CI3_RDATA_VLD    V_DM2_CI3_RDATA_VLD(1U)
+
+#define S_CI4_ARB2_REQ    15
+#define V_CI4_ARB2_REQ(x) ((x) << S_CI4_ARB2_REQ)
+#define F_CI4_ARB2_REQ    V_CI4_ARB2_REQ(1U)
+
+#define S_ARB2_CI4_GNT    14
+#define V_ARB2_CI4_GNT(x) ((x) << S_ARB2_CI4_GNT)
+#define F_ARB2_CI4_GNT    V_ARB2_CI4_GNT(1U)
+
+#define S_CI4_DM2_WDATA_VLD    13
+#define V_CI4_DM2_WDATA_VLD(x) ((x) << S_CI4_DM2_WDATA_VLD)
+#define F_CI4_DM2_WDATA_VLD    V_CI4_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI4_RDATA_VLD    12
+#define V_DM2_CI4_RDATA_VLD(x) ((x) << S_DM2_CI4_RDATA_VLD)
+#define F_DM2_CI4_RDATA_VLD    V_DM2_CI4_RDATA_VLD(1U)
+
+#define S_CI5_ARB2_REQ    11
+#define V_CI5_ARB2_REQ(x) ((x) << S_CI5_ARB2_REQ)
+#define F_CI5_ARB2_REQ    V_CI5_ARB2_REQ(1U)
+
+#define S_ARB2_CI5_GNT    10
+#define V_ARB2_CI5_GNT(x) ((x) << S_ARB2_CI5_GNT)
+#define F_ARB2_CI5_GNT    V_ARB2_CI5_GNT(1U)
+
+#define S_CI5_DM2_WDATA_VLD    9
+#define V_CI5_DM2_WDATA_VLD(x) ((x) << S_CI5_DM2_WDATA_VLD)
+#define F_CI5_DM2_WDATA_VLD    V_CI5_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI5_RDATA_VLD    8
+#define V_DM2_CI5_RDATA_VLD(x) ((x) << S_DM2_CI5_RDATA_VLD)
+#define F_DM2_CI5_RDATA_VLD    V_DM2_CI5_RDATA_VLD(1U)
+
+#define S_CI6_ARB2_REQ    7
+#define V_CI6_ARB2_REQ(x) ((x) << S_CI6_ARB2_REQ)
+#define F_CI6_ARB2_REQ    V_CI6_ARB2_REQ(1U)
+
+#define S_ARB2_CI6_GNT    6
+#define V_ARB2_CI6_GNT(x) ((x) << S_ARB2_CI6_GNT)
+#define F_ARB2_CI6_GNT    V_ARB2_CI6_GNT(1U)
+
+#define S_CI6_DM2_WDATA_VLD    5
+#define V_CI6_DM2_WDATA_VLD(x) ((x) << S_CI6_DM2_WDATA_VLD)
+#define F_CI6_DM2_WDATA_VLD    V_CI6_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI6_RDATA_VLD    4
+#define V_DM2_CI6_RDATA_VLD(x) ((x) << S_DM2_CI6_RDATA_VLD)
+#define F_DM2_CI6_RDATA_VLD    V_DM2_CI6_RDATA_VLD(1U)
+
+#define S_CI7_ARB2_REQ    3
+#define V_CI7_ARB2_REQ(x) ((x) << S_CI7_ARB2_REQ)
+#define F_CI7_ARB2_REQ    V_CI7_ARB2_REQ(1U)
+
+#define S_ARB2_CI7_GNT    2
+#define V_ARB2_CI7_GNT(x) ((x) << S_ARB2_CI7_GNT)
+#define F_ARB2_CI7_GNT    V_ARB2_CI7_GNT(1U)
+
+#define S_CI7_DM2_WDATA_VLD    1
+#define V_CI7_DM2_WDATA_VLD(x) ((x) << S_CI7_DM2_WDATA_VLD)
+#define F_CI7_DM2_WDATA_VLD    V_CI7_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI7_RDATA_VLD    0
+#define V_DM2_CI7_RDATA_VLD(x) ((x) << S_DM2_CI7_RDATA_VLD)
+#define F_DM2_CI7_RDATA_VLD    V_DM2_CI7_RDATA_VLD(1U)
+
+#define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG0 0xa010
+
+#define S_CI0_ARB3_REQ    31
+#define V_CI0_ARB3_REQ(x) ((x) << S_CI0_ARB3_REQ)
+#define F_CI0_ARB3_REQ    V_CI0_ARB3_REQ(1U)
+
+#define S_ARB3_CI0_GNT    30
+#define V_ARB3_CI0_GNT(x) ((x) << S_ARB3_CI0_GNT)
+#define F_ARB3_CI0_GNT    V_ARB3_CI0_GNT(1U)
+
+#define S_CI0_DM3_WDATA_VLD    29
+#define V_CI0_DM3_WDATA_VLD(x) ((x) << S_CI0_DM3_WDATA_VLD)
+#define F_CI0_DM3_WDATA_VLD    V_CI0_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI0_RDATA_VLD    28
+#define V_DM3_CI0_RDATA_VLD(x) ((x) << S_DM3_CI0_RDATA_VLD)
+#define F_DM3_CI0_RDATA_VLD    V_DM3_CI0_RDATA_VLD(1U)
+
+#define S_CI1_ARB3_REQ    27
+#define V_CI1_ARB3_REQ(x) ((x) << S_CI1_ARB3_REQ)
+#define F_CI1_ARB3_REQ    V_CI1_ARB3_REQ(1U)
+
+#define S_ARB3_CI1_GNT    26
+#define V_ARB3_CI1_GNT(x) ((x) << S_ARB3_CI1_GNT)
+#define F_ARB3_CI1_GNT    V_ARB3_CI1_GNT(1U)
+
+#define S_CI1_DM3_WDATA_VLD    25
+#define V_CI1_DM3_WDATA_VLD(x) ((x) << S_CI1_DM3_WDATA_VLD)
+#define F_CI1_DM3_WDATA_VLD    V_CI1_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI1_RDATA_VLD    24
+#define V_DM3_CI1_RDATA_VLD(x) ((x) << S_DM3_CI1_RDATA_VLD)
+#define F_DM3_CI1_RDATA_VLD    V_DM3_CI1_RDATA_VLD(1U)
+
+#define S_CI2_ARB3_REQ    23
+#define V_CI2_ARB3_REQ(x) ((x) << S_CI2_ARB3_REQ)
+#define F_CI2_ARB3_REQ    V_CI2_ARB3_REQ(1U)
+
+#define S_ARB3_CI2_GNT    22
+#define V_ARB3_CI2_GNT(x) ((x) << S_ARB3_CI2_GNT)
+#define F_ARB3_CI2_GNT    V_ARB3_CI2_GNT(1U)
+
+#define S_CI2_DM3_WDATA_VLD    21
+#define V_CI2_DM3_WDATA_VLD(x) ((x) << S_CI2_DM3_WDATA_VLD)
+#define F_CI2_DM3_WDATA_VLD    V_CI2_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI2_RDATA_VLD    20
+#define V_DM3_CI2_RDATA_VLD(x) ((x) << S_DM3_CI2_RDATA_VLD)
+#define F_DM3_CI2_RDATA_VLD    V_DM3_CI2_RDATA_VLD(1U)
+
+#define S_CI3_ARB3_REQ    19
+#define V_CI3_ARB3_REQ(x) ((x) << S_CI3_ARB3_REQ)
+#define F_CI3_ARB3_REQ    V_CI3_ARB3_REQ(1U)
+
+#define S_ARB3_CI3_GNT    18
+#define V_ARB3_CI3_GNT(x) ((x) << S_ARB3_CI3_GNT)
+#define F_ARB3_CI3_GNT    V_ARB3_CI3_GNT(1U)
+
+#define S_CI3_DM3_WDATA_VLD    17
+#define V_CI3_DM3_WDATA_VLD(x) ((x) << S_CI3_DM3_WDATA_VLD)
+#define F_CI3_DM3_WDATA_VLD    V_CI3_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI3_RDATA_VLD    16
+#define V_DM3_CI3_RDATA_VLD(x) ((x) << S_DM3_CI3_RDATA_VLD)
+#define F_DM3_CI3_RDATA_VLD    V_DM3_CI3_RDATA_VLD(1U)
+
+#define S_CI4_ARB3_REQ    15
+#define V_CI4_ARB3_REQ(x) ((x) << S_CI4_ARB3_REQ)
+#define F_CI4_ARB3_REQ    V_CI4_ARB3_REQ(1U)
+
+#define S_ARB3_CI4_GNT    14
+#define V_ARB3_CI4_GNT(x) ((x) << S_ARB3_CI4_GNT)
+#define F_ARB3_CI4_GNT    V_ARB3_CI4_GNT(1U)
+
+#define S_CI4_DM3_WDATA_VLD    13
+#define V_CI4_DM3_WDATA_VLD(x) ((x) << S_CI4_DM3_WDATA_VLD)
+#define F_CI4_DM3_WDATA_VLD    V_CI4_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI4_RDATA_VLD    12
+#define V_DM3_CI4_RDATA_VLD(x) ((x) << S_DM3_CI4_RDATA_VLD)
+#define F_DM3_CI4_RDATA_VLD    V_DM3_CI4_RDATA_VLD(1U)
+
+#define S_CI5_ARB3_REQ    11
+#define V_CI5_ARB3_REQ(x) ((x) << S_CI5_ARB3_REQ)
+#define F_CI5_ARB3_REQ    V_CI5_ARB3_REQ(1U)
+
+#define S_ARB3_CI5_GNT    10
+#define V_ARB3_CI5_GNT(x) ((x) << S_ARB3_CI5_GNT)
+#define F_ARB3_CI5_GNT    V_ARB3_CI5_GNT(1U)
+
+#define S_CI5_DM3_WDATA_VLD    9
+#define V_CI5_DM3_WDATA_VLD(x) ((x) << S_CI5_DM3_WDATA_VLD)
+#define F_CI5_DM3_WDATA_VLD    V_CI5_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI5_RDATA_VLD    8
+#define V_DM3_CI5_RDATA_VLD(x) ((x) << S_DM3_CI5_RDATA_VLD)
+#define F_DM3_CI5_RDATA_VLD    V_DM3_CI5_RDATA_VLD(1U)
+
+#define S_CI6_ARB3_REQ    7
+#define V_CI6_ARB3_REQ(x) ((x) << S_CI6_ARB3_REQ)
+#define F_CI6_ARB3_REQ    V_CI6_ARB3_REQ(1U)
+
+#define S_ARB3_CI6_GNT    6
+#define V_ARB3_CI6_GNT(x) ((x) << S_ARB3_CI6_GNT)
+#define F_ARB3_CI6_GNT    V_ARB3_CI6_GNT(1U)
+
+#define S_CI6_DM3_WDATA_VLD    5
+#define V_CI6_DM3_WDATA_VLD(x) ((x) << S_CI6_DM3_WDATA_VLD)
+#define F_CI6_DM3_WDATA_VLD    V_CI6_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI6_RDATA_VLD    4
+#define V_DM3_CI6_RDATA_VLD(x) ((x) << S_DM3_CI6_RDATA_VLD)
+#define F_DM3_CI6_RDATA_VLD    V_DM3_CI6_RDATA_VLD(1U)
+
+#define S_CI7_ARB3_REQ    3
+#define V_CI7_ARB3_REQ(x) ((x) << S_CI7_ARB3_REQ)
+#define F_CI7_ARB3_REQ    V_CI7_ARB3_REQ(1U)
+
+#define S_ARB3_CI7_GNT    2
+#define V_ARB3_CI7_GNT(x) ((x) << S_ARB3_CI7_GNT)
+#define F_ARB3_CI7_GNT    V_ARB3_CI7_GNT(1U)
+
+#define S_CI7_DM3_WDATA_VLD    1
+#define V_CI7_DM3_WDATA_VLD(x) ((x) << S_CI7_DM3_WDATA_VLD)
+#define F_CI7_DM3_WDATA_VLD    V_CI7_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI7_RDATA_VLD    0
+#define V_DM3_CI7_RDATA_VLD(x) ((x) << S_DM3_CI7_RDATA_VLD)
+#define F_DM3_CI7_RDATA_VLD    V_DM3_CI7_RDATA_VLD(1U)
+
+#define A_MA_MA_DEBUG_SIGNATURE_LTL_END 0xa011
+#define A_MA_MA_DEBUG_SIGNATURE_BIG_END_INVERSE 0xa012
+#define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG1 0xa013
+
+#define S_CI8_ARB0_REQ    31
+#define V_CI8_ARB0_REQ(x) ((x) << S_CI8_ARB0_REQ)
+#define F_CI8_ARB0_REQ    V_CI8_ARB0_REQ(1U)
+
+#define S_ARB0_CI8_GNT    30
+#define V_ARB0_CI8_GNT(x) ((x) << S_ARB0_CI8_GNT)
+#define F_ARB0_CI8_GNT    V_ARB0_CI8_GNT(1U)
+
+#define S_CI8_DM0_WDATA_VLD    29
+#define V_CI8_DM0_WDATA_VLD(x) ((x) << S_CI8_DM0_WDATA_VLD)
+#define F_CI8_DM0_WDATA_VLD    V_CI8_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI8_RDATA_VLD    28
+#define V_DM0_CI8_RDATA_VLD(x) ((x) << S_DM0_CI8_RDATA_VLD)
+#define F_DM0_CI8_RDATA_VLD    V_DM0_CI8_RDATA_VLD(1U)
+
+#define S_CI9_ARB0_REQ    27
+#define V_CI9_ARB0_REQ(x) ((x) << S_CI9_ARB0_REQ)
+#define F_CI9_ARB0_REQ    V_CI9_ARB0_REQ(1U)
+
+#define S_ARB0_CI9_GNT    26
+#define V_ARB0_CI9_GNT(x) ((x) << S_ARB0_CI9_GNT)
+#define F_ARB0_CI9_GNT    V_ARB0_CI9_GNT(1U)
+
+#define S_CI9_DM0_WDATA_VLD    25
+#define V_CI9_DM0_WDATA_VLD(x) ((x) << S_CI9_DM0_WDATA_VLD)
+#define F_CI9_DM0_WDATA_VLD    V_CI9_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI9_RDATA_VLD    24
+#define V_DM0_CI9_RDATA_VLD(x) ((x) << S_DM0_CI9_RDATA_VLD)
+#define F_DM0_CI9_RDATA_VLD    V_DM0_CI9_RDATA_VLD(1U)
+
+#define S_CI10_ARB0_REQ    23
+#define V_CI10_ARB0_REQ(x) ((x) << S_CI10_ARB0_REQ)
+#define F_CI10_ARB0_REQ    V_CI10_ARB0_REQ(1U)
+
+#define S_ARB0_CI10_GNT    22
+#define V_ARB0_CI10_GNT(x) ((x) << S_ARB0_CI10_GNT)
+#define F_ARB0_CI10_GNT    V_ARB0_CI10_GNT(1U)
+
+#define S_CI10_DM0_WDATA_VLD    21
+#define V_CI10_DM0_WDATA_VLD(x) ((x) << S_CI10_DM0_WDATA_VLD)
+#define F_CI10_DM0_WDATA_VLD    V_CI10_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI10_RDATA_VLD    20
+#define V_DM0_CI10_RDATA_VLD(x) ((x) << S_DM0_CI10_RDATA_VLD)
+#define F_DM0_CI10_RDATA_VLD    V_DM0_CI10_RDATA_VLD(1U)
+
+#define S_CI11_ARB0_REQ    19
+#define V_CI11_ARB0_REQ(x) ((x) << S_CI11_ARB0_REQ)
+#define F_CI11_ARB0_REQ    V_CI11_ARB0_REQ(1U)
+
+#define S_ARB0_CI11_GNT    18
+#define V_ARB0_CI11_GNT(x) ((x) << S_ARB0_CI11_GNT)
+#define F_ARB0_CI11_GNT    V_ARB0_CI11_GNT(1U)
+
+#define S_CI11_DM0_WDATA_VLD    17
+#define V_CI11_DM0_WDATA_VLD(x) ((x) << S_CI11_DM0_WDATA_VLD)
+#define F_CI11_DM0_WDATA_VLD    V_CI11_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI11_RDATA_VLD    16
+#define V_DM0_CI11_RDATA_VLD(x) ((x) << S_DM0_CI11_RDATA_VLD)
+#define F_DM0_CI11_RDATA_VLD    V_DM0_CI11_RDATA_VLD(1U)
+
+#define S_CI12_ARB0_REQ    15
+#define V_CI12_ARB0_REQ(x) ((x) << S_CI12_ARB0_REQ)
+#define F_CI12_ARB0_REQ    V_CI12_ARB0_REQ(1U)
+
+#define S_ARB0_CI12_GNT    14
+#define V_ARB0_CI12_GNT(x) ((x) << S_ARB0_CI12_GNT)
+#define F_ARB0_CI12_GNT    V_ARB0_CI12_GNT(1U)
+
+#define S_CI12_DM0_WDATA_VLD    13
+#define V_CI12_DM0_WDATA_VLD(x) ((x) << S_CI12_DM0_WDATA_VLD)
+#define F_CI12_DM0_WDATA_VLD    V_CI12_DM0_WDATA_VLD(1U)
+
+#define S_DM0_CI12_RDATA_VLD    12
+#define V_DM0_CI12_RDATA_VLD(x) ((x) << S_DM0_CI12_RDATA_VLD)
+#define F_DM0_CI12_RDATA_VLD    V_DM0_CI12_RDATA_VLD(1U)
+
+#define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG1 0xa014
+
+#define S_CI8_ARB1_REQ    31
+#define V_CI8_ARB1_REQ(x) ((x) << S_CI8_ARB1_REQ)
+#define F_CI8_ARB1_REQ    V_CI8_ARB1_REQ(1U)
+
+#define S_ARB1_CI8_GNT    30
+#define V_ARB1_CI8_GNT(x) ((x) << S_ARB1_CI8_GNT)
+#define F_ARB1_CI8_GNT    V_ARB1_CI8_GNT(1U)
+
+#define S_CI8_DM1_WDATA_VLD    29
+#define V_CI8_DM1_WDATA_VLD(x) ((x) << S_CI8_DM1_WDATA_VLD)
+#define F_CI8_DM1_WDATA_VLD    V_CI8_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI8_RDATA_VLD    28
+#define V_DM1_CI8_RDATA_VLD(x) ((x) << S_DM1_CI8_RDATA_VLD)
+#define F_DM1_CI8_RDATA_VLD    V_DM1_CI8_RDATA_VLD(1U)
+
+#define S_CI9_ARB1_REQ    27
+#define V_CI9_ARB1_REQ(x) ((x) << S_CI9_ARB1_REQ)
+#define F_CI9_ARB1_REQ    V_CI9_ARB1_REQ(1U)
+
+#define S_ARB1_CI9_GNT    26
+#define V_ARB1_CI9_GNT(x) ((x) << S_ARB1_CI9_GNT)
+#define F_ARB1_CI9_GNT    V_ARB1_CI9_GNT(1U)
+
+#define S_CI9_DM1_WDATA_VLD    25
+#define V_CI9_DM1_WDATA_VLD(x) ((x) << S_CI9_DM1_WDATA_VLD)
+#define F_CI9_DM1_WDATA_VLD    V_CI9_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI9_RDATA_VLD    24
+#define V_DM1_CI9_RDATA_VLD(x) ((x) << S_DM1_CI9_RDATA_VLD)
+#define F_DM1_CI9_RDATA_VLD    V_DM1_CI9_RDATA_VLD(1U)
+
+#define S_CI10_ARB1_REQ    23
+#define V_CI10_ARB1_REQ(x) ((x) << S_CI10_ARB1_REQ)
+#define F_CI10_ARB1_REQ    V_CI10_ARB1_REQ(1U)
+
+#define S_ARB1_CI10_GNT    22
+#define V_ARB1_CI10_GNT(x) ((x) << S_ARB1_CI10_GNT)
+#define F_ARB1_CI10_GNT    V_ARB1_CI10_GNT(1U)
+
+#define S_CI10_DM1_WDATA_VLD    21
+#define V_CI10_DM1_WDATA_VLD(x) ((x) << S_CI10_DM1_WDATA_VLD)
+#define F_CI10_DM1_WDATA_VLD    V_CI10_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI10_RDATA_VLD    20
+#define V_DM1_CI10_RDATA_VLD(x) ((x) << S_DM1_CI10_RDATA_VLD)
+#define F_DM1_CI10_RDATA_VLD    V_DM1_CI10_RDATA_VLD(1U)
+
+#define S_CI11_ARB1_REQ    19
+#define V_CI11_ARB1_REQ(x) ((x) << S_CI11_ARB1_REQ)
+#define F_CI11_ARB1_REQ    V_CI11_ARB1_REQ(1U)
+
+#define S_ARB1_CI11_GNT    18
+#define V_ARB1_CI11_GNT(x) ((x) << S_ARB1_CI11_GNT)
+#define F_ARB1_CI11_GNT    V_ARB1_CI11_GNT(1U)
+
+#define S_CI11_DM1_WDATA_VLD    17
+#define V_CI11_DM1_WDATA_VLD(x) ((x) << S_CI11_DM1_WDATA_VLD)
+#define F_CI11_DM1_WDATA_VLD    V_CI11_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI11_RDATA_VLD    16
+#define V_DM1_CI11_RDATA_VLD(x) ((x) << S_DM1_CI11_RDATA_VLD)
+#define F_DM1_CI11_RDATA_VLD    V_DM1_CI11_RDATA_VLD(1U)
+
+#define S_CI12_ARB1_REQ    15
+#define V_CI12_ARB1_REQ(x) ((x) << S_CI12_ARB1_REQ)
+#define F_CI12_ARB1_REQ    V_CI12_ARB1_REQ(1U)
+
+#define S_ARB1_CI12_GNT    14
+#define V_ARB1_CI12_GNT(x) ((x) << S_ARB1_CI12_GNT)
+#define F_ARB1_CI12_GNT    V_ARB1_CI12_GNT(1U)
+
+#define S_CI12_DM1_WDATA_VLD    13
+#define V_CI12_DM1_WDATA_VLD(x) ((x) << S_CI12_DM1_WDATA_VLD)
+#define F_CI12_DM1_WDATA_VLD    V_CI12_DM1_WDATA_VLD(1U)
+
+#define S_DM1_CI12_RDATA_VLD    12
+#define V_DM1_CI12_RDATA_VLD(x) ((x) << S_DM1_CI12_RDATA_VLD)
+#define F_DM1_CI12_RDATA_VLD    V_DM1_CI12_RDATA_VLD(1U)
+
+#define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG1 0xa015
+
+#define S_CI8_ARB2_REQ    31
+#define V_CI8_ARB2_REQ(x) ((x) << S_CI8_ARB2_REQ)
+#define F_CI8_ARB2_REQ    V_CI8_ARB2_REQ(1U)
+
+#define S_ARB2_CI8_GNT    30
+#define V_ARB2_CI8_GNT(x) ((x) << S_ARB2_CI8_GNT)
+#define F_ARB2_CI8_GNT    V_ARB2_CI8_GNT(1U)
+
+#define S_CI8_DM2_WDATA_VLD    29
+#define V_CI8_DM2_WDATA_VLD(x) ((x) << S_CI8_DM2_WDATA_VLD)
+#define F_CI8_DM2_WDATA_VLD    V_CI8_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI8_RDATA_VLD    28
+#define V_DM2_CI8_RDATA_VLD(x) ((x) << S_DM2_CI8_RDATA_VLD)
+#define F_DM2_CI8_RDATA_VLD    V_DM2_CI8_RDATA_VLD(1U)
+
+#define S_CI9_ARB2_REQ    27
+#define V_CI9_ARB2_REQ(x) ((x) << S_CI9_ARB2_REQ)
+#define F_CI9_ARB2_REQ    V_CI9_ARB2_REQ(1U)
+
+#define S_ARB2_CI9_GNT    26
+#define V_ARB2_CI9_GNT(x) ((x) << S_ARB2_CI9_GNT)
+#define F_ARB2_CI9_GNT    V_ARB2_CI9_GNT(1U)
+
+#define S_CI9_DM2_WDATA_VLD    25
+#define V_CI9_DM2_WDATA_VLD(x) ((x) << S_CI9_DM2_WDATA_VLD)
+#define F_CI9_DM2_WDATA_VLD    V_CI9_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI9_RDATA_VLD    24
+#define V_DM2_CI9_RDATA_VLD(x) ((x) << S_DM2_CI9_RDATA_VLD)
+#define F_DM2_CI9_RDATA_VLD    V_DM2_CI9_RDATA_VLD(1U)
+
+#define S_CI10_ARB2_REQ    23
+#define V_CI10_ARB2_REQ(x) ((x) << S_CI10_ARB2_REQ)
+#define F_CI10_ARB2_REQ    V_CI10_ARB2_REQ(1U)
+
+#define S_ARB2_CI10_GNT    22
+#define V_ARB2_CI10_GNT(x) ((x) << S_ARB2_CI10_GNT)
+#define F_ARB2_CI10_GNT    V_ARB2_CI10_GNT(1U)
+
+#define S_CI10_DM2_WDATA_VLD    21
+#define V_CI10_DM2_WDATA_VLD(x) ((x) << S_CI10_DM2_WDATA_VLD)
+#define F_CI10_DM2_WDATA_VLD    V_CI10_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI10_RDATA_VLD    20
+#define V_DM2_CI10_RDATA_VLD(x) ((x) << S_DM2_CI10_RDATA_VLD)
+#define F_DM2_CI10_RDATA_VLD    V_DM2_CI10_RDATA_VLD(1U)
+
+#define S_CI11_ARB2_REQ    19
+#define V_CI11_ARB2_REQ(x) ((x) << S_CI11_ARB2_REQ)
+#define F_CI11_ARB2_REQ    V_CI11_ARB2_REQ(1U)
+
+#define S_ARB2_CI11_GNT    18
+#define V_ARB2_CI11_GNT(x) ((x) << S_ARB2_CI11_GNT)
+#define F_ARB2_CI11_GNT    V_ARB2_CI11_GNT(1U)
+
+#define S_CI11_DM2_WDATA_VLD    17
+#define V_CI11_DM2_WDATA_VLD(x) ((x) << S_CI11_DM2_WDATA_VLD)
+#define F_CI11_DM2_WDATA_VLD    V_CI11_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI11_RDATA_VLD    16
+#define V_DM2_CI11_RDATA_VLD(x) ((x) << S_DM2_CI11_RDATA_VLD)
+#define F_DM2_CI11_RDATA_VLD    V_DM2_CI11_RDATA_VLD(1U)
+
+#define S_CI12_ARB2_REQ    15
+#define V_CI12_ARB2_REQ(x) ((x) << S_CI12_ARB2_REQ)
+#define F_CI12_ARB2_REQ    V_CI12_ARB2_REQ(1U)
+
+#define S_ARB2_CI12_GNT    14
+#define V_ARB2_CI12_GNT(x) ((x) << S_ARB2_CI12_GNT)
+#define F_ARB2_CI12_GNT    V_ARB2_CI12_GNT(1U)
+
+#define S_CI12_DM2_WDATA_VLD    13
+#define V_CI12_DM2_WDATA_VLD(x) ((x) << S_CI12_DM2_WDATA_VLD)
+#define F_CI12_DM2_WDATA_VLD    V_CI12_DM2_WDATA_VLD(1U)
+
+#define S_DM2_CI12_RDATA_VLD    12
+#define V_DM2_CI12_RDATA_VLD(x) ((x) << S_DM2_CI12_RDATA_VLD)
+#define F_DM2_CI12_RDATA_VLD    V_DM2_CI12_RDATA_VLD(1U)
+
+#define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG1 0xa016
+
+#define S_CI8_ARB3_REQ    31
+#define V_CI8_ARB3_REQ(x) ((x) << S_CI8_ARB3_REQ)
+#define F_CI8_ARB3_REQ    V_CI8_ARB3_REQ(1U)
+
+#define S_ARB3_CI8_GNT    30
+#define V_ARB3_CI8_GNT(x) ((x) << S_ARB3_CI8_GNT)
+#define F_ARB3_CI8_GNT    V_ARB3_CI8_GNT(1U)
+
+#define S_CI8_DM3_WDATA_VLD    29
+#define V_CI8_DM3_WDATA_VLD(x) ((x) << S_CI8_DM3_WDATA_VLD)
+#define F_CI8_DM3_WDATA_VLD    V_CI8_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI8_RDATA_VLD    28
+#define V_DM3_CI8_RDATA_VLD(x) ((x) << S_DM3_CI8_RDATA_VLD)
+#define F_DM3_CI8_RDATA_VLD    V_DM3_CI8_RDATA_VLD(1U)
+
+#define S_CI9_ARB3_REQ    27
+#define V_CI9_ARB3_REQ(x) ((x) << S_CI9_ARB3_REQ)
+#define F_CI9_ARB3_REQ    V_CI9_ARB3_REQ(1U)
+
+#define S_ARB3_CI9_GNT    26
+#define V_ARB3_CI9_GNT(x) ((x) << S_ARB3_CI9_GNT)
+#define F_ARB3_CI9_GNT    V_ARB3_CI9_GNT(1U)
+
+#define S_CI9_DM3_WDATA_VLD    25
+#define V_CI9_DM3_WDATA_VLD(x) ((x) << S_CI9_DM3_WDATA_VLD)
+#define F_CI9_DM3_WDATA_VLD    V_CI9_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI9_RDATA_VLD    24
+#define V_DM3_CI9_RDATA_VLD(x) ((x) << S_DM3_CI9_RDATA_VLD)
+#define F_DM3_CI9_RDATA_VLD    V_DM3_CI9_RDATA_VLD(1U)
+
+#define S_CI10_ARB3_REQ    23
+#define V_CI10_ARB3_REQ(x) ((x) << S_CI10_ARB3_REQ)
+#define F_CI10_ARB3_REQ    V_CI10_ARB3_REQ(1U)
+
+#define S_ARB3_CI10_GNT    22
+#define V_ARB3_CI10_GNT(x) ((x) << S_ARB3_CI10_GNT)
+#define F_ARB3_CI10_GNT    V_ARB3_CI10_GNT(1U)
+
+#define S_CI10_DM3_WDATA_VLD    21
+#define V_CI10_DM3_WDATA_VLD(x) ((x) << S_CI10_DM3_WDATA_VLD)
+#define F_CI10_DM3_WDATA_VLD    V_CI10_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI10_RDATA_VLD    20
+#define V_DM3_CI10_RDATA_VLD(x) ((x) << S_DM3_CI10_RDATA_VLD)
+#define F_DM3_CI10_RDATA_VLD    V_DM3_CI10_RDATA_VLD(1U)
+
+#define S_CI11_ARB3_REQ    19
+#define V_CI11_ARB3_REQ(x) ((x) << S_CI11_ARB3_REQ)
+#define F_CI11_ARB3_REQ    V_CI11_ARB3_REQ(1U)
+
+#define S_ARB3_CI11_GNT    18
+#define V_ARB3_CI11_GNT(x) ((x) << S_ARB3_CI11_GNT)
+#define F_ARB3_CI11_GNT    V_ARB3_CI11_GNT(1U)
+
+#define S_CI11_DM3_WDATA_VLD    17
+#define V_CI11_DM3_WDATA_VLD(x) ((x) << S_CI11_DM3_WDATA_VLD)
+#define F_CI11_DM3_WDATA_VLD    V_CI11_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI11_RDATA_VLD    16
+#define V_DM3_CI11_RDATA_VLD(x) ((x) << S_DM3_CI11_RDATA_VLD)
+#define F_DM3_CI11_RDATA_VLD    V_DM3_CI11_RDATA_VLD(1U)
+
+#define S_CI12_ARB3_REQ    15
+#define V_CI12_ARB3_REQ(x) ((x) << S_CI12_ARB3_REQ)
+#define F_CI12_ARB3_REQ    V_CI12_ARB3_REQ(1U)
+
+#define S_ARB3_CI12_GNT    14
+#define V_ARB3_CI12_GNT(x) ((x) << S_ARB3_CI12_GNT)
+#define F_ARB3_CI12_GNT    V_ARB3_CI12_GNT(1U)
+
+#define S_CI12_DM3_WDATA_VLD    13
+#define V_CI12_DM3_WDATA_VLD(x) ((x) << S_CI12_DM3_WDATA_VLD)
+#define F_CI12_DM3_WDATA_VLD    V_CI12_DM3_WDATA_VLD(1U)
+
+#define S_DM3_CI12_RDATA_VLD    12
+#define V_DM3_CI12_RDATA_VLD(x) ((x) << S_DM3_CI12_RDATA_VLD)
+#define F_DM3_CI12_RDATA_VLD    V_DM3_CI12_RDATA_VLD(1U)
+
+#define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa400
+
+#define S_CMD_IN_FIFO_CNT0    30
+#define M_CMD_IN_FIFO_CNT0    0x3U
+#define V_CMD_IN_FIFO_CNT0(x) ((x) << S_CMD_IN_FIFO_CNT0)
+#define G_CMD_IN_FIFO_CNT0(x) (((x) >> S_CMD_IN_FIFO_CNT0) & M_CMD_IN_FIFO_CNT0)
+
+#define S_CMD_SPLIT_FIFO_CNT0    28
+#define M_CMD_SPLIT_FIFO_CNT0    0x3U
+#define V_CMD_SPLIT_FIFO_CNT0(x) ((x) << S_CMD_SPLIT_FIFO_CNT0)
+#define G_CMD_SPLIT_FIFO_CNT0(x) (((x) >> S_CMD_SPLIT_FIFO_CNT0) & M_CMD_SPLIT_FIFO_CNT0)
+
+#define S_CMD_THROTTLE_FIFO_CNT0    22
+#define M_CMD_THROTTLE_FIFO_CNT0    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT0(x) ((x) << S_CMD_THROTTLE_FIFO_CNT0)
+#define G_CMD_THROTTLE_FIFO_CNT0(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT0) & M_CMD_THROTTLE_FIFO_CNT0)
+
+#define S_RD_CHNL_FIFO_CNT0    15
+#define M_RD_CHNL_FIFO_CNT0    0x7fU
+#define V_RD_CHNL_FIFO_CNT0(x) ((x) << S_RD_CHNL_FIFO_CNT0)
+#define G_RD_CHNL_FIFO_CNT0(x) (((x) >> S_RD_CHNL_FIFO_CNT0) & M_RD_CHNL_FIFO_CNT0)
+
+#define S_RD_DATA_EXT_FIFO_CNT0    13
+#define M_RD_DATA_EXT_FIFO_CNT0    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT0(x) ((x) << S_RD_DATA_EXT_FIFO_CNT0)
+#define G_RD_DATA_EXT_FIFO_CNT0(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT0) & M_RD_DATA_EXT_FIFO_CNT0)
+
+#define S_RD_DATA_512B_FIFO_CNT0    5
+#define M_RD_DATA_512B_FIFO_CNT0    0xffU
+#define V_RD_DATA_512B_FIFO_CNT0(x) ((x) << S_RD_DATA_512B_FIFO_CNT0)
+#define G_RD_DATA_512B_FIFO_CNT0(x) (((x) >> S_RD_DATA_512B_FIFO_CNT0) & M_RD_DATA_512B_FIFO_CNT0)
+
+#define S_RD_REQ_TAG_FIFO_CNT0    1
+#define M_RD_REQ_TAG_FIFO_CNT0    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT0(x) ((x) << S_RD_REQ_TAG_FIFO_CNT0)
+#define G_RD_REQ_TAG_FIFO_CNT0(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT0) & M_RD_REQ_TAG_FIFO_CNT0)
+
+#define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa401
+
+#define S_CMD_IN_FIFO_CNT1    30
+#define M_CMD_IN_FIFO_CNT1    0x3U
+#define V_CMD_IN_FIFO_CNT1(x) ((x) << S_CMD_IN_FIFO_CNT1)
+#define G_CMD_IN_FIFO_CNT1(x) (((x) >> S_CMD_IN_FIFO_CNT1) & M_CMD_IN_FIFO_CNT1)
+
+#define S_CMD_SPLIT_FIFO_CNT1    28
+#define M_CMD_SPLIT_FIFO_CNT1    0x3U
+#define V_CMD_SPLIT_FIFO_CNT1(x) ((x) << S_CMD_SPLIT_FIFO_CNT1)
+#define G_CMD_SPLIT_FIFO_CNT1(x) (((x) >> S_CMD_SPLIT_FIFO_CNT1) & M_CMD_SPLIT_FIFO_CNT1)
+
+#define S_CMD_THROTTLE_FIFO_CNT1    22
+#define M_CMD_THROTTLE_FIFO_CNT1    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT1(x) ((x) << S_CMD_THROTTLE_FIFO_CNT1)
+#define G_CMD_THROTTLE_FIFO_CNT1(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT1) & M_CMD_THROTTLE_FIFO_CNT1)
+
+#define S_RD_CHNL_FIFO_CNT1    15
+#define M_RD_CHNL_FIFO_CNT1    0x7fU
+#define V_RD_CHNL_FIFO_CNT1(x) ((x) << S_RD_CHNL_FIFO_CNT1)
+#define G_RD_CHNL_FIFO_CNT1(x) (((x) >> S_RD_CHNL_FIFO_CNT1) & M_RD_CHNL_FIFO_CNT1)
+
+#define S_RD_DATA_EXT_FIFO_CNT1    13
+#define M_RD_DATA_EXT_FIFO_CNT1    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT1(x) ((x) << S_RD_DATA_EXT_FIFO_CNT1)
+#define G_RD_DATA_EXT_FIFO_CNT1(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT1) & M_RD_DATA_EXT_FIFO_CNT1)
+
+#define S_RD_DATA_512B_FIFO_CNT1    5
+#define M_RD_DATA_512B_FIFO_CNT1    0xffU
+#define V_RD_DATA_512B_FIFO_CNT1(x) ((x) << S_RD_DATA_512B_FIFO_CNT1)
+#define G_RD_DATA_512B_FIFO_CNT1(x) (((x) >> S_RD_DATA_512B_FIFO_CNT1) & M_RD_DATA_512B_FIFO_CNT1)
+
+#define S_RD_REQ_TAG_FIFO_CNT1    1
+#define M_RD_REQ_TAG_FIFO_CNT1    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT1(x) ((x) << S_RD_REQ_TAG_FIFO_CNT1)
+#define G_RD_REQ_TAG_FIFO_CNT1(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT1) & M_RD_REQ_TAG_FIFO_CNT1)
+
+#define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa402
+
+#define S_CMD_IN_FIFO_CNT2    30
+#define M_CMD_IN_FIFO_CNT2    0x3U
+#define V_CMD_IN_FIFO_CNT2(x) ((x) << S_CMD_IN_FIFO_CNT2)
+#define G_CMD_IN_FIFO_CNT2(x) (((x) >> S_CMD_IN_FIFO_CNT2) & M_CMD_IN_FIFO_CNT2)
+
+#define S_CMD_SPLIT_FIFO_CNT2    28
+#define M_CMD_SPLIT_FIFO_CNT2    0x3U
+#define V_CMD_SPLIT_FIFO_CNT2(x) ((x) << S_CMD_SPLIT_FIFO_CNT2)
+#define G_CMD_SPLIT_FIFO_CNT2(x) (((x) >> S_CMD_SPLIT_FIFO_CNT2) & M_CMD_SPLIT_FIFO_CNT2)
+
+#define S_CMD_THROTTLE_FIFO_CNT2    22
+#define M_CMD_THROTTLE_FIFO_CNT2    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT2(x) ((x) << S_CMD_THROTTLE_FIFO_CNT2)
+#define G_CMD_THROTTLE_FIFO_CNT2(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT2) & M_CMD_THROTTLE_FIFO_CNT2)
+
+#define S_RD_CHNL_FIFO_CNT2    15
+#define M_RD_CHNL_FIFO_CNT2    0x7fU
+#define V_RD_CHNL_FIFO_CNT2(x) ((x) << S_RD_CHNL_FIFO_CNT2)
+#define G_RD_CHNL_FIFO_CNT2(x) (((x) >> S_RD_CHNL_FIFO_CNT2) & M_RD_CHNL_FIFO_CNT2)
+
+#define S_RD_DATA_EXT_FIFO_CNT2    13
+#define M_RD_DATA_EXT_FIFO_CNT2    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT2(x) ((x) << S_RD_DATA_EXT_FIFO_CNT2)
+#define G_RD_DATA_EXT_FIFO_CNT2(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT2) & M_RD_DATA_EXT_FIFO_CNT2)
+
+#define S_RD_DATA_512B_FIFO_CNT2    5
+#define M_RD_DATA_512B_FIFO_CNT2    0xffU
+#define V_RD_DATA_512B_FIFO_CNT2(x) ((x) << S_RD_DATA_512B_FIFO_CNT2)
+#define G_RD_DATA_512B_FIFO_CNT2(x) (((x) >> S_RD_DATA_512B_FIFO_CNT2) & M_RD_DATA_512B_FIFO_CNT2)
+
+#define S_RD_REQ_TAG_FIFO_CNT2    1
+#define M_RD_REQ_TAG_FIFO_CNT2    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT2(x) ((x) << S_RD_REQ_TAG_FIFO_CNT2)
+#define G_RD_REQ_TAG_FIFO_CNT2(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT2) & M_RD_REQ_TAG_FIFO_CNT2)
+
+#define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa403
+
+#define S_CMD_IN_FIFO_CNT3    30
+#define M_CMD_IN_FIFO_CNT3    0x3U
+#define V_CMD_IN_FIFO_CNT3(x) ((x) << S_CMD_IN_FIFO_CNT3)
+#define G_CMD_IN_FIFO_CNT3(x) (((x) >> S_CMD_IN_FIFO_CNT3) & M_CMD_IN_FIFO_CNT3)
+
+#define S_CMD_SPLIT_FIFO_CNT3    28
+#define M_CMD_SPLIT_FIFO_CNT3    0x3U
+#define V_CMD_SPLIT_FIFO_CNT3(x) ((x) << S_CMD_SPLIT_FIFO_CNT3)
+#define G_CMD_SPLIT_FIFO_CNT3(x) (((x) >> S_CMD_SPLIT_FIFO_CNT3) & M_CMD_SPLIT_FIFO_CNT3)
+
+#define S_CMD_THROTTLE_FIFO_CNT3    22
+#define M_CMD_THROTTLE_FIFO_CNT3    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT3(x) ((x) << S_CMD_THROTTLE_FIFO_CNT3)
+#define G_CMD_THROTTLE_FIFO_CNT3(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT3) & M_CMD_THROTTLE_FIFO_CNT3)
+
+#define S_RD_CHNL_FIFO_CNT3    15
+#define M_RD_CHNL_FIFO_CNT3    0x7fU
+#define V_RD_CHNL_FIFO_CNT3(x) ((x) << S_RD_CHNL_FIFO_CNT3)
+#define G_RD_CHNL_FIFO_CNT3(x) (((x) >> S_RD_CHNL_FIFO_CNT3) & M_RD_CHNL_FIFO_CNT3)
+
+#define S_RD_DATA_EXT_FIFO_CNT3    13
+#define M_RD_DATA_EXT_FIFO_CNT3    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT3(x) ((x) << S_RD_DATA_EXT_FIFO_CNT3)
+#define G_RD_DATA_EXT_FIFO_CNT3(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT3) & M_RD_DATA_EXT_FIFO_CNT3)
+
+#define S_RD_DATA_512B_FIFO_CNT3    5
+#define M_RD_DATA_512B_FIFO_CNT3    0xffU
+#define V_RD_DATA_512B_FIFO_CNT3(x) ((x) << S_RD_DATA_512B_FIFO_CNT3)
+#define G_RD_DATA_512B_FIFO_CNT3(x) (((x) >> S_RD_DATA_512B_FIFO_CNT3) & M_RD_DATA_512B_FIFO_CNT3)
+
+#define S_RD_REQ_TAG_FIFO_CNT3    1
+#define M_RD_REQ_TAG_FIFO_CNT3    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT3(x) ((x) << S_RD_REQ_TAG_FIFO_CNT3)
+#define G_RD_REQ_TAG_FIFO_CNT3(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT3) & M_RD_REQ_TAG_FIFO_CNT3)
+
+#define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa404
+
+#define S_CMD_IN_FIFO_CNT4    30
+#define M_CMD_IN_FIFO_CNT4    0x3U
+#define V_CMD_IN_FIFO_CNT4(x) ((x) << S_CMD_IN_FIFO_CNT4)
+#define G_CMD_IN_FIFO_CNT4(x) (((x) >> S_CMD_IN_FIFO_CNT4) & M_CMD_IN_FIFO_CNT4)
+
+#define S_CMD_SPLIT_FIFO_CNT4    28
+#define M_CMD_SPLIT_FIFO_CNT4    0x3U
+#define V_CMD_SPLIT_FIFO_CNT4(x) ((x) << S_CMD_SPLIT_FIFO_CNT4)
+#define G_CMD_SPLIT_FIFO_CNT4(x) (((x) >> S_CMD_SPLIT_FIFO_CNT4) & M_CMD_SPLIT_FIFO_CNT4)
+
+#define S_CMD_THROTTLE_FIFO_CNT4    22
+#define M_CMD_THROTTLE_FIFO_CNT4    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT4(x) ((x) << S_CMD_THROTTLE_FIFO_CNT4)
+#define G_CMD_THROTTLE_FIFO_CNT4(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT4) & M_CMD_THROTTLE_FIFO_CNT4)
+
+#define S_RD_CHNL_FIFO_CNT4    15
+#define M_RD_CHNL_FIFO_CNT4    0x7fU
+#define V_RD_CHNL_FIFO_CNT4(x) ((x) << S_RD_CHNL_FIFO_CNT4)
+#define G_RD_CHNL_FIFO_CNT4(x) (((x) >> S_RD_CHNL_FIFO_CNT4) & M_RD_CHNL_FIFO_CNT4)
+
+#define S_RD_DATA_EXT_FIFO_CNT4    13
+#define M_RD_DATA_EXT_FIFO_CNT4    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT4(x) ((x) << S_RD_DATA_EXT_FIFO_CNT4)
+#define G_RD_DATA_EXT_FIFO_CNT4(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT4) & M_RD_DATA_EXT_FIFO_CNT4)
+
+#define S_RD_DATA_512B_FIFO_CNT4    5
+#define M_RD_DATA_512B_FIFO_CNT4    0xffU
+#define V_RD_DATA_512B_FIFO_CNT4(x) ((x) << S_RD_DATA_512B_FIFO_CNT4)
+#define G_RD_DATA_512B_FIFO_CNT4(x) (((x) >> S_RD_DATA_512B_FIFO_CNT4) & M_RD_DATA_512B_FIFO_CNT4)
+
+#define S_RD_REQ_TAG_FIFO_CNT4    1
+#define M_RD_REQ_TAG_FIFO_CNT4    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT4(x) ((x) << S_RD_REQ_TAG_FIFO_CNT4)
+#define G_RD_REQ_TAG_FIFO_CNT4(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT4) & M_RD_REQ_TAG_FIFO_CNT4)
+
+#define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa405
+
+#define S_CMD_IN_FIFO_CNT5    30
+#define M_CMD_IN_FIFO_CNT5    0x3U
+#define V_CMD_IN_FIFO_CNT5(x) ((x) << S_CMD_IN_FIFO_CNT5)
+#define G_CMD_IN_FIFO_CNT5(x) (((x) >> S_CMD_IN_FIFO_CNT5) & M_CMD_IN_FIFO_CNT5)
+
+#define S_CMD_SPLIT_FIFO_CNT5    28
+#define M_CMD_SPLIT_FIFO_CNT5    0x3U
+#define V_CMD_SPLIT_FIFO_CNT5(x) ((x) << S_CMD_SPLIT_FIFO_CNT5)
+#define G_CMD_SPLIT_FIFO_CNT5(x) (((x) >> S_CMD_SPLIT_FIFO_CNT5) & M_CMD_SPLIT_FIFO_CNT5)
+
+#define S_CMD_THROTTLE_FIFO_CNT5    22
+#define M_CMD_THROTTLE_FIFO_CNT5    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT5(x) ((x) << S_CMD_THROTTLE_FIFO_CNT5)
+#define G_CMD_THROTTLE_FIFO_CNT5(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT5) & M_CMD_THROTTLE_FIFO_CNT5)
+
+#define S_RD_CHNL_FIFO_CNT5    15
+#define M_RD_CHNL_FIFO_CNT5    0x7fU
+#define V_RD_CHNL_FIFO_CNT5(x) ((x) << S_RD_CHNL_FIFO_CNT5)
+#define G_RD_CHNL_FIFO_CNT5(x) (((x) >> S_RD_CHNL_FIFO_CNT5) & M_RD_CHNL_FIFO_CNT5)
+
+#define S_RD_DATA_EXT_FIFO_CNT5    13
+#define M_RD_DATA_EXT_FIFO_CNT5    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT5(x) ((x) << S_RD_DATA_EXT_FIFO_CNT5)
+#define G_RD_DATA_EXT_FIFO_CNT5(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT5) & M_RD_DATA_EXT_FIFO_CNT5)
+
+#define S_RD_DATA_512B_FIFO_CNT5    5
+#define M_RD_DATA_512B_FIFO_CNT5    0xffU
+#define V_RD_DATA_512B_FIFO_CNT5(x) ((x) << S_RD_DATA_512B_FIFO_CNT5)
+#define G_RD_DATA_512B_FIFO_CNT5(x) (((x) >> S_RD_DATA_512B_FIFO_CNT5) & M_RD_DATA_512B_FIFO_CNT5)
+
+#define S_RD_REQ_TAG_FIFO_CNT5    1
+#define M_RD_REQ_TAG_FIFO_CNT5    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT5(x) ((x) << S_RD_REQ_TAG_FIFO_CNT5)
+#define G_RD_REQ_TAG_FIFO_CNT5(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT5) & M_RD_REQ_TAG_FIFO_CNT5)
+
+#define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa406
+
+#define S_CMD_IN_FIFO_CNT6    30
+#define M_CMD_IN_FIFO_CNT6    0x3U
+#define V_CMD_IN_FIFO_CNT6(x) ((x) << S_CMD_IN_FIFO_CNT6)
+#define G_CMD_IN_FIFO_CNT6(x) (((x) >> S_CMD_IN_FIFO_CNT6) & M_CMD_IN_FIFO_CNT6)
+
+#define S_CMD_SPLIT_FIFO_CNT6    28
+#define M_CMD_SPLIT_FIFO_CNT6    0x3U
+#define V_CMD_SPLIT_FIFO_CNT6(x) ((x) << S_CMD_SPLIT_FIFO_CNT6)
+#define G_CMD_SPLIT_FIFO_CNT6(x) (((x) >> S_CMD_SPLIT_FIFO_CNT6) & M_CMD_SPLIT_FIFO_CNT6)
+
+#define S_CMD_THROTTLE_FIFO_CNT6    22
+#define M_CMD_THROTTLE_FIFO_CNT6    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT6(x) ((x) << S_CMD_THROTTLE_FIFO_CNT6)
+#define G_CMD_THROTTLE_FIFO_CNT6(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT6) & M_CMD_THROTTLE_FIFO_CNT6)
+
+#define S_RD_CHNL_FIFO_CNT6    15
+#define M_RD_CHNL_FIFO_CNT6    0x7fU
+#define V_RD_CHNL_FIFO_CNT6(x) ((x) << S_RD_CHNL_FIFO_CNT6)
+#define G_RD_CHNL_FIFO_CNT6(x) (((x) >> S_RD_CHNL_FIFO_CNT6) & M_RD_CHNL_FIFO_CNT6)
+
+#define S_RD_DATA_EXT_FIFO_CNT6    13
+#define M_RD_DATA_EXT_FIFO_CNT6    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT6(x) ((x) << S_RD_DATA_EXT_FIFO_CNT6)
+#define G_RD_DATA_EXT_FIFO_CNT6(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT6) & M_RD_DATA_EXT_FIFO_CNT6)
+
+#define S_RD_DATA_512B_FIFO_CNT6    5
+#define M_RD_DATA_512B_FIFO_CNT6    0xffU
+#define V_RD_DATA_512B_FIFO_CNT6(x) ((x) << S_RD_DATA_512B_FIFO_CNT6)
+#define G_RD_DATA_512B_FIFO_CNT6(x) (((x) >> S_RD_DATA_512B_FIFO_CNT6) & M_RD_DATA_512B_FIFO_CNT6)
+
+#define S_RD_REQ_TAG_FIFO_CNT6    1
+#define M_RD_REQ_TAG_FIFO_CNT6    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT6(x) ((x) << S_RD_REQ_TAG_FIFO_CNT6)
+#define G_RD_REQ_TAG_FIFO_CNT6(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT6) & M_RD_REQ_TAG_FIFO_CNT6)
+
+#define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG0 0xa407
+
+#define S_CMD_IN_FIFO_CNT7    30
+#define M_CMD_IN_FIFO_CNT7    0x3U
+#define V_CMD_IN_FIFO_CNT7(x) ((x) << S_CMD_IN_FIFO_CNT7)
+#define G_CMD_IN_FIFO_CNT7(x) (((x) >> S_CMD_IN_FIFO_CNT7) & M_CMD_IN_FIFO_CNT7)
+
+#define S_CMD_SPLIT_FIFO_CNT7    28
+#define M_CMD_SPLIT_FIFO_CNT7    0x3U
+#define V_CMD_SPLIT_FIFO_CNT7(x) ((x) << S_CMD_SPLIT_FIFO_CNT7)
+#define G_CMD_SPLIT_FIFO_CNT7(x) (((x) >> S_CMD_SPLIT_FIFO_CNT7) & M_CMD_SPLIT_FIFO_CNT7)
+
+#define S_CMD_THROTTLE_FIFO_CNT7    22
+#define M_CMD_THROTTLE_FIFO_CNT7    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT7(x) ((x) << S_CMD_THROTTLE_FIFO_CNT7)
+#define G_CMD_THROTTLE_FIFO_CNT7(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT7) & M_CMD_THROTTLE_FIFO_CNT7)
+
+#define S_RD_CHNL_FIFO_CNT7    15
+#define M_RD_CHNL_FIFO_CNT7    0x7fU
+#define V_RD_CHNL_FIFO_CNT7(x) ((x) << S_RD_CHNL_FIFO_CNT7)
+#define G_RD_CHNL_FIFO_CNT7(x) (((x) >> S_RD_CHNL_FIFO_CNT7) & M_RD_CHNL_FIFO_CNT7)
+
+#define S_RD_DATA_EXT_FIFO_CNT7    13
+#define M_RD_DATA_EXT_FIFO_CNT7    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT7(x) ((x) << S_RD_DATA_EXT_FIFO_CNT7)
+#define G_RD_DATA_EXT_FIFO_CNT7(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT7) & M_RD_DATA_EXT_FIFO_CNT7)
+
+#define S_RD_DATA_512B_FIFO_CNT7    5
+#define M_RD_DATA_512B_FIFO_CNT7    0xffU
+#define V_RD_DATA_512B_FIFO_CNT7(x) ((x) << S_RD_DATA_512B_FIFO_CNT7)
+#define G_RD_DATA_512B_FIFO_CNT7(x) (((x) >> S_RD_DATA_512B_FIFO_CNT7) & M_RD_DATA_512B_FIFO_CNT7)
+
+#define S_RD_REQ_TAG_FIFO_CNT7    1
+#define M_RD_REQ_TAG_FIFO_CNT7    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT7(x) ((x) << S_RD_REQ_TAG_FIFO_CNT7)
+#define G_RD_REQ_TAG_FIFO_CNT7(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT7) & M_RD_REQ_TAG_FIFO_CNT7)
+
+#define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG0 0xa408
+
+#define S_CMD_IN_FIFO_CNT8    30
+#define M_CMD_IN_FIFO_CNT8    0x3U
+#define V_CMD_IN_FIFO_CNT8(x) ((x) << S_CMD_IN_FIFO_CNT8)
+#define G_CMD_IN_FIFO_CNT8(x) (((x) >> S_CMD_IN_FIFO_CNT8) & M_CMD_IN_FIFO_CNT8)
+
+#define S_CMD_SPLIT_FIFO_CNT8    28
+#define M_CMD_SPLIT_FIFO_CNT8    0x3U
+#define V_CMD_SPLIT_FIFO_CNT8(x) ((x) << S_CMD_SPLIT_FIFO_CNT8)
+#define G_CMD_SPLIT_FIFO_CNT8(x) (((x) >> S_CMD_SPLIT_FIFO_CNT8) & M_CMD_SPLIT_FIFO_CNT8)
+
+#define S_CMD_THROTTLE_FIFO_CNT8    22
+#define M_CMD_THROTTLE_FIFO_CNT8    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT8(x) ((x) << S_CMD_THROTTLE_FIFO_CNT8)
+#define G_CMD_THROTTLE_FIFO_CNT8(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT8) & M_CMD_THROTTLE_FIFO_CNT8)
+
+#define S_RD_CHNL_FIFO_CNT8    15
+#define M_RD_CHNL_FIFO_CNT8    0x7fU
+#define V_RD_CHNL_FIFO_CNT8(x) ((x) << S_RD_CHNL_FIFO_CNT8)
+#define G_RD_CHNL_FIFO_CNT8(x) (((x) >> S_RD_CHNL_FIFO_CNT8) & M_RD_CHNL_FIFO_CNT8)
+
+#define S_RD_DATA_EXT_FIFO_CNT8    13
+#define M_RD_DATA_EXT_FIFO_CNT8    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT8(x) ((x) << S_RD_DATA_EXT_FIFO_CNT8)
+#define G_RD_DATA_EXT_FIFO_CNT8(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT8) & M_RD_DATA_EXT_FIFO_CNT8)
+
+#define S_RD_DATA_512B_FIFO_CNT8    5
+#define M_RD_DATA_512B_FIFO_CNT8    0xffU
+#define V_RD_DATA_512B_FIFO_CNT8(x) ((x) << S_RD_DATA_512B_FIFO_CNT8)
+#define G_RD_DATA_512B_FIFO_CNT8(x) (((x) >> S_RD_DATA_512B_FIFO_CNT8) & M_RD_DATA_512B_FIFO_CNT8)
+
+#define S_RD_REQ_TAG_FIFO_CNT8    1
+#define M_RD_REQ_TAG_FIFO_CNT8    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT8(x) ((x) << S_RD_REQ_TAG_FIFO_CNT8)
+#define G_RD_REQ_TAG_FIFO_CNT8(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT8) & M_RD_REQ_TAG_FIFO_CNT8)
+
+#define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG0 0xa409
+
+#define S_CMD_IN_FIFO_CNT9    30
+#define M_CMD_IN_FIFO_CNT9    0x3U
+#define V_CMD_IN_FIFO_CNT9(x) ((x) << S_CMD_IN_FIFO_CNT9)
+#define G_CMD_IN_FIFO_CNT9(x) (((x) >> S_CMD_IN_FIFO_CNT9) & M_CMD_IN_FIFO_CNT9)
+
+#define S_CMD_SPLIT_FIFO_CNT9    28
+#define M_CMD_SPLIT_FIFO_CNT9    0x3U
+#define V_CMD_SPLIT_FIFO_CNT9(x) ((x) << S_CMD_SPLIT_FIFO_CNT9)
+#define G_CMD_SPLIT_FIFO_CNT9(x) (((x) >> S_CMD_SPLIT_FIFO_CNT9) & M_CMD_SPLIT_FIFO_CNT9)
+
+#define S_CMD_THROTTLE_FIFO_CNT9    22
+#define M_CMD_THROTTLE_FIFO_CNT9    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT9(x) ((x) << S_CMD_THROTTLE_FIFO_CNT9)
+#define G_CMD_THROTTLE_FIFO_CNT9(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT9) & M_CMD_THROTTLE_FIFO_CNT9)
+
+#define S_RD_CHNL_FIFO_CNT9    15
+#define M_RD_CHNL_FIFO_CNT9    0x7fU
+#define V_RD_CHNL_FIFO_CNT9(x) ((x) << S_RD_CHNL_FIFO_CNT9)
+#define G_RD_CHNL_FIFO_CNT9(x) (((x) >> S_RD_CHNL_FIFO_CNT9) & M_RD_CHNL_FIFO_CNT9)
+
+#define S_RD_DATA_EXT_FIFO_CNT9    13
+#define M_RD_DATA_EXT_FIFO_CNT9    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT9(x) ((x) << S_RD_DATA_EXT_FIFO_CNT9)
+#define G_RD_DATA_EXT_FIFO_CNT9(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT9) & M_RD_DATA_EXT_FIFO_CNT9)
+
+#define S_RD_DATA_512B_FIFO_CNT9    5
+#define M_RD_DATA_512B_FIFO_CNT9    0xffU
+#define V_RD_DATA_512B_FIFO_CNT9(x) ((x) << S_RD_DATA_512B_FIFO_CNT9)
+#define G_RD_DATA_512B_FIFO_CNT9(x) (((x) >> S_RD_DATA_512B_FIFO_CNT9) & M_RD_DATA_512B_FIFO_CNT9)
+
+#define S_RD_REQ_TAG_FIFO_CNT9    1
+#define M_RD_REQ_TAG_FIFO_CNT9    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT9(x) ((x) << S_RD_REQ_TAG_FIFO_CNT9)
+#define G_RD_REQ_TAG_FIFO_CNT9(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT9) & M_RD_REQ_TAG_FIFO_CNT9)
+
+#define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40a
+
+#define S_CMD_IN_FIFO_CNT10    30
+#define M_CMD_IN_FIFO_CNT10    0x3U
+#define V_CMD_IN_FIFO_CNT10(x) ((x) << S_CMD_IN_FIFO_CNT10)
+#define G_CMD_IN_FIFO_CNT10(x) (((x) >> S_CMD_IN_FIFO_CNT10) & M_CMD_IN_FIFO_CNT10)
+
+#define S_CMD_SPLIT_FIFO_CNT10    28
+#define M_CMD_SPLIT_FIFO_CNT10    0x3U
+#define V_CMD_SPLIT_FIFO_CNT10(x) ((x) << S_CMD_SPLIT_FIFO_CNT10)
+#define G_CMD_SPLIT_FIFO_CNT10(x) (((x) >> S_CMD_SPLIT_FIFO_CNT10) & M_CMD_SPLIT_FIFO_CNT10)
+
+#define S_CMD_THROTTLE_FIFO_CNT10    22
+#define M_CMD_THROTTLE_FIFO_CNT10    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT10(x) ((x) << S_CMD_THROTTLE_FIFO_CNT10)
+#define G_CMD_THROTTLE_FIFO_CNT10(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT10) & M_CMD_THROTTLE_FIFO_CNT10)
+
+#define S_RD_CHNL_FIFO_CNT10    15
+#define M_RD_CHNL_FIFO_CNT10    0x7fU
+#define V_RD_CHNL_FIFO_CNT10(x) ((x) << S_RD_CHNL_FIFO_CNT10)
+#define G_RD_CHNL_FIFO_CNT10(x) (((x) >> S_RD_CHNL_FIFO_CNT10) & M_RD_CHNL_FIFO_CNT10)
+
+#define S_RD_DATA_EXT_FIFO_CNT10    13
+#define M_RD_DATA_EXT_FIFO_CNT10    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT10(x) ((x) << S_RD_DATA_EXT_FIFO_CNT10)
+#define G_RD_DATA_EXT_FIFO_CNT10(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT10) & M_RD_DATA_EXT_FIFO_CNT10)
+
+#define S_RD_DATA_512B_FIFO_CNT10    5
+#define M_RD_DATA_512B_FIFO_CNT10    0xffU
+#define V_RD_DATA_512B_FIFO_CNT10(x) ((x) << S_RD_DATA_512B_FIFO_CNT10)
+#define G_RD_DATA_512B_FIFO_CNT10(x) (((x) >> S_RD_DATA_512B_FIFO_CNT10) & M_RD_DATA_512B_FIFO_CNT10)
+
+#define S_RD_REQ_TAG_FIFO_CNT10    1
+#define M_RD_REQ_TAG_FIFO_CNT10    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT10(x) ((x) << S_RD_REQ_TAG_FIFO_CNT10)
+#define G_RD_REQ_TAG_FIFO_CNT10(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT10) & M_RD_REQ_TAG_FIFO_CNT10)
+
+#define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40b
+
+#define S_CMD_IN_FIFO_CNT11    30
+#define M_CMD_IN_FIFO_CNT11    0x3U
+#define V_CMD_IN_FIFO_CNT11(x) ((x) << S_CMD_IN_FIFO_CNT11)
+#define G_CMD_IN_FIFO_CNT11(x) (((x) >> S_CMD_IN_FIFO_CNT11) & M_CMD_IN_FIFO_CNT11)
+
+#define S_CMD_SPLIT_FIFO_CNT11    28
+#define M_CMD_SPLIT_FIFO_CNT11    0x3U
+#define V_CMD_SPLIT_FIFO_CNT11(x) ((x) << S_CMD_SPLIT_FIFO_CNT11)
+#define G_CMD_SPLIT_FIFO_CNT11(x) (((x) >> S_CMD_SPLIT_FIFO_CNT11) & M_CMD_SPLIT_FIFO_CNT11)
+
+#define S_CMD_THROTTLE_FIFO_CNT11    22
+#define M_CMD_THROTTLE_FIFO_CNT11    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT11(x) ((x) << S_CMD_THROTTLE_FIFO_CNT11)
+#define G_CMD_THROTTLE_FIFO_CNT11(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT11) & M_CMD_THROTTLE_FIFO_CNT11)
+
+#define S_RD_CHNL_FIFO_CNT11    15
+#define M_RD_CHNL_FIFO_CNT11    0x7fU
+#define V_RD_CHNL_FIFO_CNT11(x) ((x) << S_RD_CHNL_FIFO_CNT11)
+#define G_RD_CHNL_FIFO_CNT11(x) (((x) >> S_RD_CHNL_FIFO_CNT11) & M_RD_CHNL_FIFO_CNT11)
+
+#define S_RD_DATA_EXT_FIFO_CNT11    13
+#define M_RD_DATA_EXT_FIFO_CNT11    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT11(x) ((x) << S_RD_DATA_EXT_FIFO_CNT11)
+#define G_RD_DATA_EXT_FIFO_CNT11(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT11) & M_RD_DATA_EXT_FIFO_CNT11)
+
+#define S_RD_DATA_512B_FIFO_CNT11    5
+#define M_RD_DATA_512B_FIFO_CNT11    0xffU
+#define V_RD_DATA_512B_FIFO_CNT11(x) ((x) << S_RD_DATA_512B_FIFO_CNT11)
+#define G_RD_DATA_512B_FIFO_CNT11(x) (((x) >> S_RD_DATA_512B_FIFO_CNT11) & M_RD_DATA_512B_FIFO_CNT11)
+
+#define S_RD_REQ_TAG_FIFO_CNT11    1
+#define M_RD_REQ_TAG_FIFO_CNT11    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT11(x) ((x) << S_RD_REQ_TAG_FIFO_CNT11)
+#define G_RD_REQ_TAG_FIFO_CNT11(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT11) & M_RD_REQ_TAG_FIFO_CNT11)
+
+#define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG0 0xa40c
+
+#define S_CMD_IN_FIFO_CNT12    30
+#define M_CMD_IN_FIFO_CNT12    0x3U
+#define V_CMD_IN_FIFO_CNT12(x) ((x) << S_CMD_IN_FIFO_CNT12)
+#define G_CMD_IN_FIFO_CNT12(x) (((x) >> S_CMD_IN_FIFO_CNT12) & M_CMD_IN_FIFO_CNT12)
+
+#define S_CMD_SPLIT_FIFO_CNT12    28
+#define M_CMD_SPLIT_FIFO_CNT12    0x3U
+#define V_CMD_SPLIT_FIFO_CNT12(x) ((x) << S_CMD_SPLIT_FIFO_CNT12)
+#define G_CMD_SPLIT_FIFO_CNT12(x) (((x) >> S_CMD_SPLIT_FIFO_CNT12) & M_CMD_SPLIT_FIFO_CNT12)
+
+#define S_CMD_THROTTLE_FIFO_CNT12    22
+#define M_CMD_THROTTLE_FIFO_CNT12    0x3fU
+#define V_CMD_THROTTLE_FIFO_CNT12(x) ((x) << S_CMD_THROTTLE_FIFO_CNT12)
+#define G_CMD_THROTTLE_FIFO_CNT12(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT12) & M_CMD_THROTTLE_FIFO_CNT12)
+
+#define S_RD_CHNL_FIFO_CNT12    15
+#define M_RD_CHNL_FIFO_CNT12    0x7fU
+#define V_RD_CHNL_FIFO_CNT12(x) ((x) << S_RD_CHNL_FIFO_CNT12)
+#define G_RD_CHNL_FIFO_CNT12(x) (((x) >> S_RD_CHNL_FIFO_CNT12) & M_RD_CHNL_FIFO_CNT12)
+
+#define S_RD_DATA_EXT_FIFO_CNT12    13
+#define M_RD_DATA_EXT_FIFO_CNT12    0x3U
+#define V_RD_DATA_EXT_FIFO_CNT12(x) ((x) << S_RD_DATA_EXT_FIFO_CNT12)
+#define G_RD_DATA_EXT_FIFO_CNT12(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT12) & M_RD_DATA_EXT_FIFO_CNT12)
+
+#define S_RD_DATA_512B_FIFO_CNT12    5
+#define M_RD_DATA_512B_FIFO_CNT12    0xffU
+#define V_RD_DATA_512B_FIFO_CNT12(x) ((x) << S_RD_DATA_512B_FIFO_CNT12)
+#define G_RD_DATA_512B_FIFO_CNT12(x) (((x) >> S_RD_DATA_512B_FIFO_CNT12) & M_RD_DATA_512B_FIFO_CNT12)
+
+#define S_RD_REQ_TAG_FIFO_CNT12    1
+#define M_RD_REQ_TAG_FIFO_CNT12    0xfU
+#define V_RD_REQ_TAG_FIFO_CNT12(x) ((x) << S_RD_REQ_TAG_FIFO_CNT12)
+#define G_RD_REQ_TAG_FIFO_CNT12(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT12) & M_RD_REQ_TAG_FIFO_CNT12)
+
+#define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG0 0xa40d
+
+#define S_WR_DATA_FSM0    23
+#define V_WR_DATA_FSM0(x) ((x) << S_WR_DATA_FSM0)
+#define F_WR_DATA_FSM0    V_WR_DATA_FSM0(1U)
+
+#define S_RD_DATA_FSM0    22
+#define V_RD_DATA_FSM0(x) ((x) << S_RD_DATA_FSM0)
+#define F_RD_DATA_FSM0    V_RD_DATA_FSM0(1U)
+
+#define S_TGT_CMD_FIFO_CNT0    19
+#define M_TGT_CMD_FIFO_CNT0    0x7U
+#define V_TGT_CMD_FIFO_CNT0(x) ((x) << S_TGT_CMD_FIFO_CNT0)
+#define G_TGT_CMD_FIFO_CNT0(x) (((x) >> S_TGT_CMD_FIFO_CNT0) & M_TGT_CMD_FIFO_CNT0)
+
+#define S_CLNT_NUM_FIFO_CNT0    16
+#define M_CLNT_NUM_FIFO_CNT0    0x7U
+#define V_CLNT_NUM_FIFO_CNT0(x) ((x) << S_CLNT_NUM_FIFO_CNT0)
+#define G_CLNT_NUM_FIFO_CNT0(x) (((x) >> S_CLNT_NUM_FIFO_CNT0) & M_CLNT_NUM_FIFO_CNT0)
+
+#define S_WR_CMD_TAG_FIFO_CNT_TGT0    8
+#define M_WR_CMD_TAG_FIFO_CNT_TGT0    0xffU
+#define V_WR_CMD_TAG_FIFO_CNT_TGT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT0)
+#define G_WR_CMD_TAG_FIFO_CNT_TGT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT0) & M_WR_CMD_TAG_FIFO_CNT_TGT0)
+
+#define S_WR_DATA_512B_FIFO_CNT_TGT0    0
+#define M_WR_DATA_512B_FIFO_CNT_TGT0    0xffU
+#define V_WR_DATA_512B_FIFO_CNT_TGT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT0)
+#define G_WR_DATA_512B_FIFO_CNT_TGT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT0) & M_WR_DATA_512B_FIFO_CNT_TGT0)
+
+#define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG0 0xa40e
+
+#define S_WR_DATA_FSM1    23
+#define V_WR_DATA_FSM1(x) ((x) << S_WR_DATA_FSM1)
+#define F_WR_DATA_FSM1    V_WR_DATA_FSM1(1U)
+
+#define S_RD_DATA_FSM1    22
+#define V_RD_DATA_FSM1(x) ((x) << S_RD_DATA_FSM1)
+#define F_RD_DATA_FSM1    V_RD_DATA_FSM1(1U)
+
+#define S_TGT_CMD_FIFO_CNT1    19
+#define M_TGT_CMD_FIFO_CNT1    0x7U
+#define V_TGT_CMD_FIFO_CNT1(x) ((x) << S_TGT_CMD_FIFO_CNT1)
+#define G_TGT_CMD_FIFO_CNT1(x) (((x) >> S_TGT_CMD_FIFO_CNT1) & M_TGT_CMD_FIFO_CNT1)
+
+#define S_CLNT_NUM_FIFO_CNT1    16
+#define M_CLNT_NUM_FIFO_CNT1    0x7U
+#define V_CLNT_NUM_FIFO_CNT1(x) ((x) << S_CLNT_NUM_FIFO_CNT1)
+#define G_CLNT_NUM_FIFO_CNT1(x) (((x) >> S_CLNT_NUM_FIFO_CNT1) & M_CLNT_NUM_FIFO_CNT1)
+
+#define S_WR_CMD_TAG_FIFO_CNT_TGT1    8
+#define M_WR_CMD_TAG_FIFO_CNT_TGT1    0xffU
+#define V_WR_CMD_TAG_FIFO_CNT_TGT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT1)
+#define G_WR_CMD_TAG_FIFO_CNT_TGT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT1) & M_WR_CMD_TAG_FIFO_CNT_TGT1)
+
+#define S_WR_DATA_512B_FIFO_CNT_TGT1    0
+#define M_WR_DATA_512B_FIFO_CNT_TGT1    0xffU
+#define V_WR_DATA_512B_FIFO_CNT_TGT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT1)
+#define G_WR_DATA_512B_FIFO_CNT_TGT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT1) & M_WR_DATA_512B_FIFO_CNT_TGT1)
+
+#define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG0 0xa40f
+
+#define S_WR_DATA_FSM2    23
+#define V_WR_DATA_FSM2(x) ((x) << S_WR_DATA_FSM2)
+#define F_WR_DATA_FSM2    V_WR_DATA_FSM2(1U)
+
+#define S_RD_DATA_FSM2    22
+#define V_RD_DATA_FSM2(x) ((x) << S_RD_DATA_FSM2)
+#define F_RD_DATA_FSM2    V_RD_DATA_FSM2(1U)
+
+#define S_TGT_CMD_FIFO_CNT2    19
+#define M_TGT_CMD_FIFO_CNT2    0x7U
+#define V_TGT_CMD_FIFO_CNT2(x) ((x) << S_TGT_CMD_FIFO_CNT2)
+#define G_TGT_CMD_FIFO_CNT2(x) (((x) >> S_TGT_CMD_FIFO_CNT2) & M_TGT_CMD_FIFO_CNT2)
+
+#define S_CLNT_NUM_FIFO_CNT2    16
+#define M_CLNT_NUM_FIFO_CNT2    0x7U
+#define V_CLNT_NUM_FIFO_CNT2(x) ((x) << S_CLNT_NUM_FIFO_CNT2)
+#define G_CLNT_NUM_FIFO_CNT2(x) (((x) >> S_CLNT_NUM_FIFO_CNT2) & M_CLNT_NUM_FIFO_CNT2)
+
+#define S_WR_CMD_TAG_FIFO_CNT_TGT2    8
+#define M_WR_CMD_TAG_FIFO_CNT_TGT2    0xffU
+#define V_WR_CMD_TAG_FIFO_CNT_TGT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT2)
+#define G_WR_CMD_TAG_FIFO_CNT_TGT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT2) & M_WR_CMD_TAG_FIFO_CNT_TGT2)
+
+#define S_WR_DATA_512B_FIFO_CNT_TGT2    0
+#define M_WR_DATA_512B_FIFO_CNT_TGT2    0xffU
+#define V_WR_DATA_512B_FIFO_CNT_TGT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT2)
+#define G_WR_DATA_512B_FIFO_CNT_TGT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT2) & M_WR_DATA_512B_FIFO_CNT_TGT2)
+
+#define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG0 0xa410
+
+#define S_WR_DATA_FSM3    23
+#define V_WR_DATA_FSM3(x) ((x) << S_WR_DATA_FSM3)
+#define F_WR_DATA_FSM3    V_WR_DATA_FSM3(1U)
+
+#define S_RD_DATA_FSM3    22
+#define V_RD_DATA_FSM3(x) ((x) << S_RD_DATA_FSM3)
+#define F_RD_DATA_FSM3    V_RD_DATA_FSM3(1U)
+
+#define S_TGT_CMD_FIFO_CNT3    19
+#define M_TGT_CMD_FIFO_CNT3    0x7U
+#define V_TGT_CMD_FIFO_CNT3(x) ((x) << S_TGT_CMD_FIFO_CNT3)
+#define G_TGT_CMD_FIFO_CNT3(x) (((x) >> S_TGT_CMD_FIFO_CNT3) & M_TGT_CMD_FIFO_CNT3)
+
+#define S_CLNT_NUM_FIFO_CNT3    16
+#define M_CLNT_NUM_FIFO_CNT3    0x7U
+#define V_CLNT_NUM_FIFO_CNT3(x) ((x) << S_CLNT_NUM_FIFO_CNT3)
+#define G_CLNT_NUM_FIFO_CNT3(x) (((x) >> S_CLNT_NUM_FIFO_CNT3) & M_CLNT_NUM_FIFO_CNT3)
+
+#define S_WR_CMD_TAG_FIFO_CNT_TGT3    8
+#define M_WR_CMD_TAG_FIFO_CNT_TGT3    0xffU
+#define V_WR_CMD_TAG_FIFO_CNT_TGT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT3)
+#define G_WR_CMD_TAG_FIFO_CNT_TGT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT3) & M_WR_CMD_TAG_FIFO_CNT_TGT3)
+
+#define S_WR_DATA_512B_FIFO_CNT_TGT    0
+#define M_WR_DATA_512B_FIFO_CNT_TGT    0xffU
+#define V_WR_DATA_512B_FIFO_CNT_TGT(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT)
+#define G_WR_DATA_512B_FIFO_CNT_TGT(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT) & M_WR_DATA_512B_FIFO_CNT_TGT)
+
+#define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa412
+#define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa413
+#define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa414
+#define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa415
+#define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa416
+#define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa417
+#define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa418
+#define A_MA_LE_CLNT_EXP_RD_CYC_CNT_LO 0xa419
+#define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_LO 0xa41a
+#define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_LO 0xa41b
+#define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa41c
+#define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa41d
+#define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_LO 0xa41e
+#define A_T6_MA_EDRAM0_WRDATA_CNT1 0xa800
+#define A_T6_MA_EDRAM0_WRDATA_CNT0 0xa801
+#define A_T6_MA_EDRAM1_WRDATA_CNT1 0xa802
+#define A_T6_MA_EDRAM1_WRDATA_CNT0 0xa803
+#define A_T6_MA_EXT_MEMORY0_WRDATA_CNT1 0xa804
+#define A_T6_MA_EXT_MEMORY0_WRDATA_CNT0 0xa805
+#define A_T6_MA_HOST_MEMORY_WRDATA_CNT1 0xa806
+#define A_T6_MA_HOST_MEMORY_WRDATA_CNT0 0xa807
+#define A_T6_MA_EXT_MEMORY1_WRDATA_CNT1 0xa808
+#define A_T6_MA_EXT_MEMORY1_WRDATA_CNT0 0xa809
+#define A_T6_MA_EDRAM0_RDDATA_CNT1 0xa80a
+#define A_T6_MA_EDRAM0_RDDATA_CNT0 0xa80b
+#define A_T6_MA_EDRAM1_RDDATA_CNT1 0xa80c
+#define A_T6_MA_EDRAM1_RDDATA_CNT0 0xa80d
+#define A_T6_MA_EXT_MEMORY0_RDDATA_CNT1 0xa80e
+#define A_T6_MA_EXT_MEMORY0_RDDATA_CNT0 0xa80f
+#define A_T6_MA_HOST_MEMORY_RDDATA_CNT1 0xa810
+#define A_T6_MA_HOST_MEMORY_RDDATA_CNT0 0xa811
+#define A_T6_MA_EXT_MEMORY1_RDDATA_CNT1 0xa812
+#define A_T6_MA_EXT_MEMORY1_RDDATA_CNT0 0xa813
+#define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac00
+#define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac01
+#define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac02
+#define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac03
+#define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac04
+#define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac05
+#define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac06
+#define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac07
+#define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac08
+#define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac09
+#define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac0a
+#define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac0b
+#define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac0c
+#define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac0d
+#define A_MA_LE_CLNT_ACT_WR_CYC_CNT_HI 0xac0e
+#define A_MA_LE_CLNT_ACT_WR_CYC_CNT_LO 0xac0f
+#define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_HI 0xac10
+#define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_LO 0xac11
+#define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_HI 0xac12
+#define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_LO 0xac13
+#define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac14
+#define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac15
+#define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac16
+#define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac17
+#define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_HI 0xac18
+#define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_LO 0xac19
+#define A_MA_SGE_THREAD_0_CLNT_WR_REQ_CNT 0xb000
+#define A_MA_SGE_THREAD_1_CLNT_WR_REQ_CNT 0xb001
+#define A_MA_ULP_TX_CLNT_WR_REQ_CNT 0xb002
+#define A_MA_ULP_RX_CLNT_WR_REQ_CNT 0xb003
+#define A_MA_ULP_TX_RX_CLNT_WR_REQ_CNT 0xb004
+#define A_MA_TP_THREAD_0_CLNT_WR_REQ_CNT 0xb005
+#define A_MA_TP_THREAD_1_CLNT_WR_REQ_CNT 0xb006
+#define A_MA_LE_CLNT_WR_REQ_CNT 0xb007
+#define A_MA_CIM_CLNT_WR_REQ_CNT 0xb008
+#define A_MA_PCIE_CLNT_WR_REQ_CNT 0xb009
+#define A_MA_PM_TX_CLNT_WR_REQ_CNT 0xb00a
+#define A_MA_PM_RX_CLNT_WR_REQ_CNT 0xb00b
+#define A_MA_HMA_CLNT_WR_REQ_CNT 0xb00c
+#define A_MA_SGE_THREAD_0_CLNT_RD_REQ_CNT 0xb00d
+#define A_MA_SGE_THREAD_1_CLNT_RD_REQ_CNT 0xb00e
+#define A_MA_ULP_TX_CLNT_RD_REQ_CNT 0xb00f
+#define A_MA_ULP_RX_CLNT_RD_REQ_CNT 0xb010
+#define A_MA_ULP_TX_RX_CLNT_RD_REQ_CNT 0xb011
+#define A_MA_TP_THREAD_0_CLNT_RD_REQ_CNT 0xb012
+#define A_MA_TP_THREAD_1_CLNT_RD_REQ_CNT 0xb013
+#define A_MA_LE_CLNT_RD_REQ_CNT 0xb014
+#define A_MA_CIM_CLNT_RD_REQ_CNT 0xb015
+#define A_MA_PCIE_CLNT_RD_REQ_CNT 0xb016
+#define A_MA_PM_TX_CLNT_RD_REQ_CNT 0xb017
+#define A_MA_PM_RX_CLNT_RD_REQ_CNT 0xb018
+#define A_MA_HMA_CLNT_RD_REQ_CNT 0xb019
+#define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb400
+#define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb401
+#define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb402
+#define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb403
+#define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb404
+#define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb405
+#define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb406
+#define A_MA_LE_CLNT_EXP_RD_CYC_CNT_HI 0xb407
+#define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_HI 0xb408
+#define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_HI 0xb409
+#define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb40a
+#define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb40b
+#define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_HI 0xb40c
+#define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb40d
+#define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb40e
+#define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb40f
+#define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb410
+#define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb411
+#define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb412
+#define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb413
+#define A_MA_LE_CLNT_EXP_WR_CYC_CNT_HI 0xb414
+#define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_HI 0xb415
+#define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_HI 0xb416
+#define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb417
+#define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb418
+#define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_HI 0xb419
+#define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe400
+
+#define S_WR_DATA_EXT_FIFO_CNT0    30
+#define M_WR_DATA_EXT_FIFO_CNT0    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT0(x) ((x) << S_WR_DATA_EXT_FIFO_CNT0)
+#define G_WR_DATA_EXT_FIFO_CNT0(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT0) & M_WR_DATA_EXT_FIFO_CNT0)
+
+#define S_WR_CMD_TAG_FIFO_CNT0    26
+#define M_WR_CMD_TAG_FIFO_CNT0    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT0)
+#define G_WR_CMD_TAG_FIFO_CNT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT0) & M_WR_CMD_TAG_FIFO_CNT0)
+
+#define S_WR_DATA_512B_FIFO_CNT0    18
+#define M_WR_DATA_512B_FIFO_CNT0    0xffU
+#define V_WR_DATA_512B_FIFO_CNT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT0)
+#define G_WR_DATA_512B_FIFO_CNT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT0) & M_WR_DATA_512B_FIFO_CNT0)
+
+#define S_RD_DATA_ALIGN_FSM0    17
+#define V_RD_DATA_ALIGN_FSM0(x) ((x) << S_RD_DATA_ALIGN_FSM0)
+#define F_RD_DATA_ALIGN_FSM0    V_RD_DATA_ALIGN_FSM0(1U)
+
+#define S_RD_DATA_FETCH_FSM0    16
+#define V_RD_DATA_FETCH_FSM0(x) ((x) << S_RD_DATA_FETCH_FSM0)
+#define F_RD_DATA_FETCH_FSM0    V_RD_DATA_FETCH_FSM0(1U)
+
+#define S_COHERENCY_TX_FSM0    15
+#define V_COHERENCY_TX_FSM0(x) ((x) << S_COHERENCY_TX_FSM0)
+#define F_COHERENCY_TX_FSM0    V_COHERENCY_TX_FSM0(1U)
+
+#define S_COHERENCY_RX_FSM0    14
+#define V_COHERENCY_RX_FSM0(x) ((x) << S_COHERENCY_RX_FSM0)
+#define F_COHERENCY_RX_FSM0    V_COHERENCY_RX_FSM0(1U)
+
+#define S_ARB_REQ_FSM0    13
+#define V_ARB_REQ_FSM0(x) ((x) << S_ARB_REQ_FSM0)
+#define F_ARB_REQ_FSM0    V_ARB_REQ_FSM0(1U)
+
+#define S_CMD_SPLIT_FSM0    10
+#define M_CMD_SPLIT_FSM0    0x7U
+#define V_CMD_SPLIT_FSM0(x) ((x) << S_CMD_SPLIT_FSM0)
+#define G_CMD_SPLIT_FSM0(x) (((x) >> S_CMD_SPLIT_FSM0) & M_CMD_SPLIT_FSM0)
+
+#define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe420
+
+#define S_WR_DATA_EXT_FIFO_CNT1    30
+#define M_WR_DATA_EXT_FIFO_CNT1    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT1(x) ((x) << S_WR_DATA_EXT_FIFO_CNT1)
+#define G_WR_DATA_EXT_FIFO_CNT1(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT1) & M_WR_DATA_EXT_FIFO_CNT1)
+
+#define S_WR_CMD_TAG_FIFO_CNT1    26
+#define M_WR_CMD_TAG_FIFO_CNT1    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT1)
+#define G_WR_CMD_TAG_FIFO_CNT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT1) & M_WR_CMD_TAG_FIFO_CNT1)
+
+#define S_WR_DATA_512B_FIFO_CNT1    18
+#define M_WR_DATA_512B_FIFO_CNT1    0xffU
+#define V_WR_DATA_512B_FIFO_CNT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT1)
+#define G_WR_DATA_512B_FIFO_CNT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT1) & M_WR_DATA_512B_FIFO_CNT1)
+
+#define S_RD_DATA_ALIGN_FSM1    17
+#define V_RD_DATA_ALIGN_FSM1(x) ((x) << S_RD_DATA_ALIGN_FSM1)
+#define F_RD_DATA_ALIGN_FSM1    V_RD_DATA_ALIGN_FSM1(1U)
+
+#define S_RD_DATA_FETCH_FSM1    16
+#define V_RD_DATA_FETCH_FSM1(x) ((x) << S_RD_DATA_FETCH_FSM1)
+#define F_RD_DATA_FETCH_FSM1    V_RD_DATA_FETCH_FSM1(1U)
+
+#define S_COHERENCY_TX_FSM1    15
+#define V_COHERENCY_TX_FSM1(x) ((x) << S_COHERENCY_TX_FSM1)
+#define F_COHERENCY_TX_FSM1    V_COHERENCY_TX_FSM1(1U)
+
+#define S_COHERENCY_RX_FSM1    14
+#define V_COHERENCY_RX_FSM1(x) ((x) << S_COHERENCY_RX_FSM1)
+#define F_COHERENCY_RX_FSM1    V_COHERENCY_RX_FSM1(1U)
+
+#define S_ARB_REQ_FSM1    13
+#define V_ARB_REQ_FSM1(x) ((x) << S_ARB_REQ_FSM1)
+#define F_ARB_REQ_FSM1    V_ARB_REQ_FSM1(1U)
+
+#define S_CMD_SPLIT_FSM1    10
+#define M_CMD_SPLIT_FSM1    0x7U
+#define V_CMD_SPLIT_FSM1(x) ((x) << S_CMD_SPLIT_FSM1)
+#define G_CMD_SPLIT_FSM1(x) (((x) >> S_CMD_SPLIT_FSM1) & M_CMD_SPLIT_FSM1)
+
+#define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe440
+
+#define S_WR_DATA_EXT_FIFO_CNT2    30
+#define M_WR_DATA_EXT_FIFO_CNT2    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT2(x) ((x) << S_WR_DATA_EXT_FIFO_CNT2)
+#define G_WR_DATA_EXT_FIFO_CNT2(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT2) & M_WR_DATA_EXT_FIFO_CNT2)
+
+#define S_WR_CMD_TAG_FIFO_CNT2    26
+#define M_WR_CMD_TAG_FIFO_CNT2    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT2)
+#define G_WR_CMD_TAG_FIFO_CNT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT2) & M_WR_CMD_TAG_FIFO_CNT2)
+
+#define S_WR_DATA_512B_FIFO_CNT2    18
+#define M_WR_DATA_512B_FIFO_CNT2    0xffU
+#define V_WR_DATA_512B_FIFO_CNT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT2)
+#define G_WR_DATA_512B_FIFO_CNT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT2) & M_WR_DATA_512B_FIFO_CNT2)
+
+#define S_RD_DATA_ALIGN_FSM2    17
+#define V_RD_DATA_ALIGN_FSM2(x) ((x) << S_RD_DATA_ALIGN_FSM2)
+#define F_RD_DATA_ALIGN_FSM2    V_RD_DATA_ALIGN_FSM2(1U)
+
+#define S_RD_DATA_FETCH_FSM2    16
+#define V_RD_DATA_FETCH_FSM2(x) ((x) << S_RD_DATA_FETCH_FSM2)
+#define F_RD_DATA_FETCH_FSM2    V_RD_DATA_FETCH_FSM2(1U)
+
+#define S_COHERENCY_TX_FSM2    15
+#define V_COHERENCY_TX_FSM2(x) ((x) << S_COHERENCY_TX_FSM2)
+#define F_COHERENCY_TX_FSM2    V_COHERENCY_TX_FSM2(1U)
+
+#define S_COHERENCY_RX_FSM2    14
+#define V_COHERENCY_RX_FSM2(x) ((x) << S_COHERENCY_RX_FSM2)
+#define F_COHERENCY_RX_FSM2    V_COHERENCY_RX_FSM2(1U)
+
+#define S_ARB_REQ_FSM2    13
+#define V_ARB_REQ_FSM2(x) ((x) << S_ARB_REQ_FSM2)
+#define F_ARB_REQ_FSM2    V_ARB_REQ_FSM2(1U)
+
+#define S_CMD_SPLIT_FSM2    10
+#define M_CMD_SPLIT_FSM2    0x7U
+#define V_CMD_SPLIT_FSM2(x) ((x) << S_CMD_SPLIT_FSM2)
+#define G_CMD_SPLIT_FSM2(x) (((x) >> S_CMD_SPLIT_FSM2) & M_CMD_SPLIT_FSM2)
+
+#define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe460
+
+#define S_WR_DATA_EXT_FIFO_CNT3    30
+#define M_WR_DATA_EXT_FIFO_CNT3    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT3(x) ((x) << S_WR_DATA_EXT_FIFO_CNT3)
+#define G_WR_DATA_EXT_FIFO_CNT3(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT3) & M_WR_DATA_EXT_FIFO_CNT3)
+
+#define S_WR_CMD_TAG_FIFO_CNT3    26
+#define M_WR_CMD_TAG_FIFO_CNT3    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT3)
+#define G_WR_CMD_TAG_FIFO_CNT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT3) & M_WR_CMD_TAG_FIFO_CNT3)
+
+#define S_WR_DATA_512B_FIFO_CNT3    18
+#define M_WR_DATA_512B_FIFO_CNT3    0xffU
+#define V_WR_DATA_512B_FIFO_CNT3(x) ((x) << S_WR_DATA_512B_FIFO_CNT3)
+#define G_WR_DATA_512B_FIFO_CNT3(x) (((x) >> S_WR_DATA_512B_FIFO_CNT3) & M_WR_DATA_512B_FIFO_CNT3)
+
+#define S_RD_DATA_ALIGN_FSM3    17
+#define V_RD_DATA_ALIGN_FSM3(x) ((x) << S_RD_DATA_ALIGN_FSM3)
+#define F_RD_DATA_ALIGN_FSM3    V_RD_DATA_ALIGN_FSM3(1U)
+
+#define S_RD_DATA_FETCH_FSM3    16
+#define V_RD_DATA_FETCH_FSM3(x) ((x) << S_RD_DATA_FETCH_FSM3)
+#define F_RD_DATA_FETCH_FSM3    V_RD_DATA_FETCH_FSM3(1U)
+
+#define S_COHERENCY_TX_FSM3    15
+#define V_COHERENCY_TX_FSM3(x) ((x) << S_COHERENCY_TX_FSM3)
+#define F_COHERENCY_TX_FSM3    V_COHERENCY_TX_FSM3(1U)
+
+#define S_COHERENCY_RX_FSM3    14
+#define V_COHERENCY_RX_FSM3(x) ((x) << S_COHERENCY_RX_FSM3)
+#define F_COHERENCY_RX_FSM3    V_COHERENCY_RX_FSM3(1U)
+
+#define S_ARB_REQ_FSM3    13
+#define V_ARB_REQ_FSM3(x) ((x) << S_ARB_REQ_FSM3)
+#define F_ARB_REQ_FSM3    V_ARB_REQ_FSM3(1U)
+
+#define S_CMD_SPLIT_FSM3    10
+#define M_CMD_SPLIT_FSM3    0x7U
+#define V_CMD_SPLIT_FSM3(x) ((x) << S_CMD_SPLIT_FSM3)
+#define G_CMD_SPLIT_FSM3(x) (((x) >> S_CMD_SPLIT_FSM3) & M_CMD_SPLIT_FSM3)
+
+#define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe480
+
+#define S_WR_DATA_EXT_FIFO_CNT4    30
+#define M_WR_DATA_EXT_FIFO_CNT4    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT4(x) ((x) << S_WR_DATA_EXT_FIFO_CNT4)
+#define G_WR_DATA_EXT_FIFO_CNT4(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT4) & M_WR_DATA_EXT_FIFO_CNT4)
+
+#define S_WR_CMD_TAG_FIFO_CNT4    26
+#define M_WR_CMD_TAG_FIFO_CNT4    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT4(x) ((x) << S_WR_CMD_TAG_FIFO_CNT4)
+#define G_WR_CMD_TAG_FIFO_CNT4(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT4) & M_WR_CMD_TAG_FIFO_CNT4)
+
+#define S_WR_DATA_512B_FIFO_CNT4    18
+#define M_WR_DATA_512B_FIFO_CNT4    0xffU
+#define V_WR_DATA_512B_FIFO_CNT4(x) ((x) << S_WR_DATA_512B_FIFO_CNT4)
+#define G_WR_DATA_512B_FIFO_CNT4(x) (((x) >> S_WR_DATA_512B_FIFO_CNT4) & M_WR_DATA_512B_FIFO_CNT4)
+
+#define S_RD_DATA_ALIGN_FSM4    17
+#define V_RD_DATA_ALIGN_FSM4(x) ((x) << S_RD_DATA_ALIGN_FSM4)
+#define F_RD_DATA_ALIGN_FSM4    V_RD_DATA_ALIGN_FSM4(1U)
+
+#define S_RD_DATA_FETCH_FSM4    16
+#define V_RD_DATA_FETCH_FSM4(x) ((x) << S_RD_DATA_FETCH_FSM4)
+#define F_RD_DATA_FETCH_FSM4    V_RD_DATA_FETCH_FSM4(1U)
+
+#define S_COHERENCY_TX_FSM4    15
+#define V_COHERENCY_TX_FSM4(x) ((x) << S_COHERENCY_TX_FSM4)
+#define F_COHERENCY_TX_FSM4    V_COHERENCY_TX_FSM4(1U)
+
+#define S_COHERENCY_RX_FSM4    14
+#define V_COHERENCY_RX_FSM4(x) ((x) << S_COHERENCY_RX_FSM4)
+#define F_COHERENCY_RX_FSM4    V_COHERENCY_RX_FSM4(1U)
+
+#define S_ARB_REQ_FSM4    13
+#define V_ARB_REQ_FSM4(x) ((x) << S_ARB_REQ_FSM4)
+#define F_ARB_REQ_FSM4    V_ARB_REQ_FSM4(1U)
+
+#define S_CMD_SPLIT_FSM4    10
+#define M_CMD_SPLIT_FSM4    0x7U
+#define V_CMD_SPLIT_FSM4(x) ((x) << S_CMD_SPLIT_FSM4)
+#define G_CMD_SPLIT_FSM4(x) (((x) >> S_CMD_SPLIT_FSM4) & M_CMD_SPLIT_FSM4)
+
+#define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe4a0
+
+#define S_WR_DATA_EXT_FIFO_CNT5    30
+#define M_WR_DATA_EXT_FIFO_CNT5    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT5(x) ((x) << S_WR_DATA_EXT_FIFO_CNT5)
+#define G_WR_DATA_EXT_FIFO_CNT5(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT5) & M_WR_DATA_EXT_FIFO_CNT5)
+
+#define S_WR_CMD_TAG_FIFO_CNT5    26
+#define M_WR_CMD_TAG_FIFO_CNT5    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT5(x) ((x) << S_WR_CMD_TAG_FIFO_CNT5)
+#define G_WR_CMD_TAG_FIFO_CNT5(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT5) & M_WR_CMD_TAG_FIFO_CNT5)
+
+#define S_WR_DATA_512B_FIFO_CNT5    18
+#define M_WR_DATA_512B_FIFO_CNT5    0xffU
+#define V_WR_DATA_512B_FIFO_CNT5(x) ((x) << S_WR_DATA_512B_FIFO_CNT5)
+#define G_WR_DATA_512B_FIFO_CNT5(x) (((x) >> S_WR_DATA_512B_FIFO_CNT5) & M_WR_DATA_512B_FIFO_CNT5)
+
+#define S_RD_DATA_ALIGN_FSM5    17
+#define V_RD_DATA_ALIGN_FSM5(x) ((x) << S_RD_DATA_ALIGN_FSM5)
+#define F_RD_DATA_ALIGN_FSM5    V_RD_DATA_ALIGN_FSM5(1U)
+
+#define S_RD_DATA_FETCH_FSM5    16
+#define V_RD_DATA_FETCH_FSM5(x) ((x) << S_RD_DATA_FETCH_FSM5)
+#define F_RD_DATA_FETCH_FSM5    V_RD_DATA_FETCH_FSM5(1U)
+
+#define S_COHERENCY_TX_FSM5    15
+#define V_COHERENCY_TX_FSM5(x) ((x) << S_COHERENCY_TX_FSM5)
+#define F_COHERENCY_TX_FSM5    V_COHERENCY_TX_FSM5(1U)
+
+#define S_COHERENCY_RX_FSM5    14
+#define V_COHERENCY_RX_FSM5(x) ((x) << S_COHERENCY_RX_FSM5)
+#define F_COHERENCY_RX_FSM5    V_COHERENCY_RX_FSM5(1U)
+
+#define S_ARB_REQ_FSM5    13
+#define V_ARB_REQ_FSM5(x) ((x) << S_ARB_REQ_FSM5)
+#define F_ARB_REQ_FSM5    V_ARB_REQ_FSM5(1U)
+
+#define S_CMD_SPLIT_FSM5    10
+#define M_CMD_SPLIT_FSM5    0x7U
+#define V_CMD_SPLIT_FSM5(x) ((x) << S_CMD_SPLIT_FSM5)
+#define G_CMD_SPLIT_FSM5(x) (((x) >> S_CMD_SPLIT_FSM5) & M_CMD_SPLIT_FSM5)
+
+#define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe4c0
+
+#define S_WR_DATA_EXT_FIFO_CNT6    30
+#define M_WR_DATA_EXT_FIFO_CNT6    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT6(x) ((x) << S_WR_DATA_EXT_FIFO_CNT6)
+#define G_WR_DATA_EXT_FIFO_CNT6(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT6) & M_WR_DATA_EXT_FIFO_CNT6)
+
+#define S_WR_CMD_TAG_FIFO_CNT6    26
+#define M_WR_CMD_TAG_FIFO_CNT6    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT6(x) ((x) << S_WR_CMD_TAG_FIFO_CNT6)
+#define G_WR_CMD_TAG_FIFO_CNT6(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT6) & M_WR_CMD_TAG_FIFO_CNT6)
+
+#define S_WR_DATA_512B_FIFO_CNT6    18
+#define M_WR_DATA_512B_FIFO_CNT6    0xffU
+#define V_WR_DATA_512B_FIFO_CNT6(x) ((x) << S_WR_DATA_512B_FIFO_CNT6)
+#define G_WR_DATA_512B_FIFO_CNT6(x) (((x) >> S_WR_DATA_512B_FIFO_CNT6) & M_WR_DATA_512B_FIFO_CNT6)
+
+#define S_RD_DATA_ALIGN_FSM6    17
+#define V_RD_DATA_ALIGN_FSM6(x) ((x) << S_RD_DATA_ALIGN_FSM6)
+#define F_RD_DATA_ALIGN_FSM6    V_RD_DATA_ALIGN_FSM6(1U)
+
+#define S_RD_DATA_FETCH_FSM6    16
+#define V_RD_DATA_FETCH_FSM6(x) ((x) << S_RD_DATA_FETCH_FSM6)
+#define F_RD_DATA_FETCH_FSM6    V_RD_DATA_FETCH_FSM6(1U)
+
+#define S_COHERENCY_TX_FSM6    15
+#define V_COHERENCY_TX_FSM6(x) ((x) << S_COHERENCY_TX_FSM6)
+#define F_COHERENCY_TX_FSM6    V_COHERENCY_TX_FSM6(1U)
+
+#define S_COHERENCY_RX_FSM6    14
+#define V_COHERENCY_RX_FSM6(x) ((x) << S_COHERENCY_RX_FSM6)
+#define F_COHERENCY_RX_FSM6    V_COHERENCY_RX_FSM6(1U)
+
+#define S_ARB_REQ_FSM6    13
+#define V_ARB_REQ_FSM6(x) ((x) << S_ARB_REQ_FSM6)
+#define F_ARB_REQ_FSM6    V_ARB_REQ_FSM6(1U)
+
+#define S_CMD_SPLIT_FSM6    10
+#define M_CMD_SPLIT_FSM6    0x7U
+#define V_CMD_SPLIT_FSM6(x) ((x) << S_CMD_SPLIT_FSM6)
+#define G_CMD_SPLIT_FSM6(x) (((x) >> S_CMD_SPLIT_FSM6) & M_CMD_SPLIT_FSM6)
+
+#define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG1 0xe4e0
+
+#define S_WR_DATA_EXT_FIFO_CNT7    30
+#define M_WR_DATA_EXT_FIFO_CNT7    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT7(x) ((x) << S_WR_DATA_EXT_FIFO_CNT7)
+#define G_WR_DATA_EXT_FIFO_CNT7(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT7) & M_WR_DATA_EXT_FIFO_CNT7)
+
+#define S_WR_CMD_TAG_FIFO_CNT7    26
+#define M_WR_CMD_TAG_FIFO_CNT7    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT7(x) ((x) << S_WR_CMD_TAG_FIFO_CNT7)
+#define G_WR_CMD_TAG_FIFO_CNT7(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT7) & M_WR_CMD_TAG_FIFO_CNT7)
+
+#define S_WR_DATA_512B_FIFO_CNT7    18
+#define M_WR_DATA_512B_FIFO_CNT7    0xffU
+#define V_WR_DATA_512B_FIFO_CNT7(x) ((x) << S_WR_DATA_512B_FIFO_CNT7)
+#define G_WR_DATA_512B_FIFO_CNT7(x) (((x) >> S_WR_DATA_512B_FIFO_CNT7) & M_WR_DATA_512B_FIFO_CNT7)
+
+#define S_RD_DATA_ALIGN_FSM7    17
+#define V_RD_DATA_ALIGN_FSM7(x) ((x) << S_RD_DATA_ALIGN_FSM7)
+#define F_RD_DATA_ALIGN_FSM7    V_RD_DATA_ALIGN_FSM7(1U)
+
+#define S_RD_DATA_FETCH_FSM7    16
+#define V_RD_DATA_FETCH_FSM7(x) ((x) << S_RD_DATA_FETCH_FSM7)
+#define F_RD_DATA_FETCH_FSM7    V_RD_DATA_FETCH_FSM7(1U)
+
+#define S_COHERENCY_TX_FSM7    15
+#define V_COHERENCY_TX_FSM7(x) ((x) << S_COHERENCY_TX_FSM7)
+#define F_COHERENCY_TX_FSM7    V_COHERENCY_TX_FSM7(1U)
+
+#define S_COHERENCY_RX_FSM7    14
+#define V_COHERENCY_RX_FSM7(x) ((x) << S_COHERENCY_RX_FSM7)
+#define F_COHERENCY_RX_FSM7    V_COHERENCY_RX_FSM7(1U)
+
+#define S_ARB_REQ_FSM7    13
+#define V_ARB_REQ_FSM7(x) ((x) << S_ARB_REQ_FSM7)
+#define F_ARB_REQ_FSM7    V_ARB_REQ_FSM7(1U)
+
+#define S_CMD_SPLIT_FSM7    10
+#define M_CMD_SPLIT_FSM7    0x7U
+#define V_CMD_SPLIT_FSM7(x) ((x) << S_CMD_SPLIT_FSM7)
+#define G_CMD_SPLIT_FSM7(x) (((x) >> S_CMD_SPLIT_FSM7) & M_CMD_SPLIT_FSM7)
+
+#define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG1 0xe500
+
+#define S_WR_DATA_EXT_FIFO_CNT8    30
+#define M_WR_DATA_EXT_FIFO_CNT8    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT8(x) ((x) << S_WR_DATA_EXT_FIFO_CNT8)
+#define G_WR_DATA_EXT_FIFO_CNT8(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT8) & M_WR_DATA_EXT_FIFO_CNT8)
+
+#define S_WR_CMD_TAG_FIFO_CNT8    26
+#define M_WR_CMD_TAG_FIFO_CNT8    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT8(x) ((x) << S_WR_CMD_TAG_FIFO_CNT8)
+#define G_WR_CMD_TAG_FIFO_CNT8(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT8) & M_WR_CMD_TAG_FIFO_CNT8)
+
+#define S_WR_DATA_512B_FIFO_CNT8    18
+#define M_WR_DATA_512B_FIFO_CNT8    0xffU
+#define V_WR_DATA_512B_FIFO_CNT8(x) ((x) << S_WR_DATA_512B_FIFO_CNT8)
+#define G_WR_DATA_512B_FIFO_CNT8(x) (((x) >> S_WR_DATA_512B_FIFO_CNT8) & M_WR_DATA_512B_FIFO_CNT8)
+
+#define S_RD_DATA_ALIGN_FSM8    17
+#define V_RD_DATA_ALIGN_FSM8(x) ((x) << S_RD_DATA_ALIGN_FSM8)
+#define F_RD_DATA_ALIGN_FSM8    V_RD_DATA_ALIGN_FSM8(1U)
+
+#define S_RD_DATA_FETCH_FSM8    16
+#define V_RD_DATA_FETCH_FSM8(x) ((x) << S_RD_DATA_FETCH_FSM8)
+#define F_RD_DATA_FETCH_FSM8    V_RD_DATA_FETCH_FSM8(1U)
+
+#define S_COHERENCY_TX_FSM8    15
+#define V_COHERENCY_TX_FSM8(x) ((x) << S_COHERENCY_TX_FSM8)
+#define F_COHERENCY_TX_FSM8    V_COHERENCY_TX_FSM8(1U)
+
+#define S_COHERENCY_RX_FSM8    14
+#define V_COHERENCY_RX_FSM8(x) ((x) << S_COHERENCY_RX_FSM8)
+#define F_COHERENCY_RX_FSM8    V_COHERENCY_RX_FSM8(1U)
+
+#define S_ARB_REQ_FSM8    13
+#define V_ARB_REQ_FSM8(x) ((x) << S_ARB_REQ_FSM8)
+#define F_ARB_REQ_FSM8    V_ARB_REQ_FSM8(1U)
+
+#define S_CMD_SPLIT_FSM8    10
+#define M_CMD_SPLIT_FSM8    0x7U
+#define V_CMD_SPLIT_FSM8(x) ((x) << S_CMD_SPLIT_FSM8)
+#define G_CMD_SPLIT_FSM8(x) (((x) >> S_CMD_SPLIT_FSM8) & M_CMD_SPLIT_FSM8)
+
+#define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG1 0xe520
+
+#define S_WR_DATA_EXT_FIFO_CNT9    30
+#define M_WR_DATA_EXT_FIFO_CNT9    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT9(x) ((x) << S_WR_DATA_EXT_FIFO_CNT9)
+#define G_WR_DATA_EXT_FIFO_CNT9(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT9) & M_WR_DATA_EXT_FIFO_CNT9)
+
+#define S_WR_CMD_TAG_FIFO_CNT9    26
+#define M_WR_CMD_TAG_FIFO_CNT9    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT9(x) ((x) << S_WR_CMD_TAG_FIFO_CNT9)
+#define G_WR_CMD_TAG_FIFO_CNT9(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT9) & M_WR_CMD_TAG_FIFO_CNT9)
+
+#define S_WR_DATA_512B_FIFO_CNT9    18
+#define M_WR_DATA_512B_FIFO_CNT9    0xffU
+#define V_WR_DATA_512B_FIFO_CNT9(x) ((x) << S_WR_DATA_512B_FIFO_CNT9)
+#define G_WR_DATA_512B_FIFO_CNT9(x) (((x) >> S_WR_DATA_512B_FIFO_CNT9) & M_WR_DATA_512B_FIFO_CNT9)
+
+#define S_RD_DATA_ALIGN_FSM9    17
+#define V_RD_DATA_ALIGN_FSM9(x) ((x) << S_RD_DATA_ALIGN_FSM9)
+#define F_RD_DATA_ALIGN_FSM9    V_RD_DATA_ALIGN_FSM9(1U)
+
+#define S_RD_DATA_FETCH_FSM9    16
+#define V_RD_DATA_FETCH_FSM9(x) ((x) << S_RD_DATA_FETCH_FSM9)
+#define F_RD_DATA_FETCH_FSM9    V_RD_DATA_FETCH_FSM9(1U)
+
+#define S_COHERENCY_TX_FSM9    15
+#define V_COHERENCY_TX_FSM9(x) ((x) << S_COHERENCY_TX_FSM9)
+#define F_COHERENCY_TX_FSM9    V_COHERENCY_TX_FSM9(1U)
+
+#define S_COHERENCY_RX_FSM9    14
+#define V_COHERENCY_RX_FSM9(x) ((x) << S_COHERENCY_RX_FSM9)
+#define F_COHERENCY_RX_FSM9    V_COHERENCY_RX_FSM9(1U)
+
+#define S_ARB_REQ_FSM9    13
+#define V_ARB_REQ_FSM9(x) ((x) << S_ARB_REQ_FSM9)
+#define F_ARB_REQ_FSM9    V_ARB_REQ_FSM9(1U)
+
+#define S_CMD_SPLIT_FSM9    10
+#define M_CMD_SPLIT_FSM9    0x7U
+#define V_CMD_SPLIT_FSM9(x) ((x) << S_CMD_SPLIT_FSM9)
+#define G_CMD_SPLIT_FSM9(x) (((x) >> S_CMD_SPLIT_FSM9) & M_CMD_SPLIT_FSM9)
+
+#define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe540
+
+#define S_WR_DATA_EXT_FIFO_CNT10    30
+#define M_WR_DATA_EXT_FIFO_CNT10    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT10(x) ((x) << S_WR_DATA_EXT_FIFO_CNT10)
+#define G_WR_DATA_EXT_FIFO_CNT10(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT10) & M_WR_DATA_EXT_FIFO_CNT10)
+
+#define S_WR_CMD_TAG_FIFO_CNT10    26
+#define M_WR_CMD_TAG_FIFO_CNT10    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT10(x) ((x) << S_WR_CMD_TAG_FIFO_CNT10)
+#define G_WR_CMD_TAG_FIFO_CNT10(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT10) & M_WR_CMD_TAG_FIFO_CNT10)
+
+#define S_WR_DATA_512B_FIFO_CNT10    18
+#define M_WR_DATA_512B_FIFO_CNT10    0xffU
+#define V_WR_DATA_512B_FIFO_CNT10(x) ((x) << S_WR_DATA_512B_FIFO_CNT10)
+#define G_WR_DATA_512B_FIFO_CNT10(x) (((x) >> S_WR_DATA_512B_FIFO_CNT10) & M_WR_DATA_512B_FIFO_CNT10)
+
+#define S_RD_DATA_ALIGN_FSM10    17
+#define V_RD_DATA_ALIGN_FSM10(x) ((x) << S_RD_DATA_ALIGN_FSM10)
+#define F_RD_DATA_ALIGN_FSM10    V_RD_DATA_ALIGN_FSM10(1U)
+
+#define S_RD_DATA_FETCH_FSM10    16
+#define V_RD_DATA_FETCH_FSM10(x) ((x) << S_RD_DATA_FETCH_FSM10)
+#define F_RD_DATA_FETCH_FSM10    V_RD_DATA_FETCH_FSM10(1U)
+
+#define S_COHERENCY_TX_FSM10    15
+#define V_COHERENCY_TX_FSM10(x) ((x) << S_COHERENCY_TX_FSM10)
+#define F_COHERENCY_TX_FSM10    V_COHERENCY_TX_FSM10(1U)
+
+#define S_COHERENCY_RX_FSM10    14
+#define V_COHERENCY_RX_FSM10(x) ((x) << S_COHERENCY_RX_FSM10)
+#define F_COHERENCY_RX_FSM10    V_COHERENCY_RX_FSM10(1U)
+
+#define S_ARB_REQ_FSM10    13
+#define V_ARB_REQ_FSM10(x) ((x) << S_ARB_REQ_FSM10)
+#define F_ARB_REQ_FSM10    V_ARB_REQ_FSM10(1U)
+
+#define S_CMD_SPLIT_FSM10    10
+#define M_CMD_SPLIT_FSM10    0x7U
+#define V_CMD_SPLIT_FSM10(x) ((x) << S_CMD_SPLIT_FSM10)
+#define G_CMD_SPLIT_FSM10(x) (((x) >> S_CMD_SPLIT_FSM10) & M_CMD_SPLIT_FSM10)
+
+#define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe560
+
+#define S_WR_DATA_EXT_FIFO_CNT11    30
+#define M_WR_DATA_EXT_FIFO_CNT11    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT11(x) ((x) << S_WR_DATA_EXT_FIFO_CNT11)
+#define G_WR_DATA_EXT_FIFO_CNT11(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT11) & M_WR_DATA_EXT_FIFO_CNT11)
+
+#define S_WR_CMD_TAG_FIFO_CNT11    26
+#define M_WR_CMD_TAG_FIFO_CNT11    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT11(x) ((x) << S_WR_CMD_TAG_FIFO_CNT11)
+#define G_WR_CMD_TAG_FIFO_CNT11(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT11) & M_WR_CMD_TAG_FIFO_CNT11)
+
+#define S_WR_DATA_512B_FIFO_CNT11    18
+#define M_WR_DATA_512B_FIFO_CNT11    0xffU
+#define V_WR_DATA_512B_FIFO_CNT11(x) ((x) << S_WR_DATA_512B_FIFO_CNT11)
+#define G_WR_DATA_512B_FIFO_CNT11(x) (((x) >> S_WR_DATA_512B_FIFO_CNT11) & M_WR_DATA_512B_FIFO_CNT11)
+
+#define S_RD_DATA_ALIGN_FSM11    17
+#define V_RD_DATA_ALIGN_FSM11(x) ((x) << S_RD_DATA_ALIGN_FSM11)
+#define F_RD_DATA_ALIGN_FSM11    V_RD_DATA_ALIGN_FSM11(1U)
+
+#define S_RD_DATA_FETCH_FSM11    16
+#define V_RD_DATA_FETCH_FSM11(x) ((x) << S_RD_DATA_FETCH_FSM11)
+#define F_RD_DATA_FETCH_FSM11    V_RD_DATA_FETCH_FSM11(1U)
+
+#define S_COHERENCY_TX_FSM11    15
+#define V_COHERENCY_TX_FSM11(x) ((x) << S_COHERENCY_TX_FSM11)
+#define F_COHERENCY_TX_FSM11    V_COHERENCY_TX_FSM11(1U)
+
+#define S_COHERENCY_RX_FSM11    14
+#define V_COHERENCY_RX_FSM11(x) ((x) << S_COHERENCY_RX_FSM11)
+#define F_COHERENCY_RX_FSM11    V_COHERENCY_RX_FSM11(1U)
+
+#define S_ARB_REQ_FSM11    13
+#define V_ARB_REQ_FSM11(x) ((x) << S_ARB_REQ_FSM11)
+#define F_ARB_REQ_FSM11    V_ARB_REQ_FSM11(1U)
+
+#define S_CMD_SPLIT_FSM11    10
+#define M_CMD_SPLIT_FSM11    0x7U
+#define V_CMD_SPLIT_FSM11(x) ((x) << S_CMD_SPLIT_FSM11)
+#define G_CMD_SPLIT_FSM11(x) (((x) >> S_CMD_SPLIT_FSM11) & M_CMD_SPLIT_FSM11)
+
+#define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG1 0xe580
+
+#define S_WR_DATA_EXT_FIFO_CNT12    30
+#define M_WR_DATA_EXT_FIFO_CNT12    0x3U
+#define V_WR_DATA_EXT_FIFO_CNT12(x) ((x) << S_WR_DATA_EXT_FIFO_CNT12)
+#define G_WR_DATA_EXT_FIFO_CNT12(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT12) & M_WR_DATA_EXT_FIFO_CNT12)
+
+#define S_WR_CMD_TAG_FIFO_CNT12    26
+#define M_WR_CMD_TAG_FIFO_CNT12    0xfU
+#define V_WR_CMD_TAG_FIFO_CNT12(x) ((x) << S_WR_CMD_TAG_FIFO_CNT12)
+#define G_WR_CMD_TAG_FIFO_CNT12(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT12) & M_WR_CMD_TAG_FIFO_CNT12)
+
+#define S_WR_DATA_512B_FIFO_CNT12    18
+#define M_WR_DATA_512B_FIFO_CNT12    0xffU
+#define V_WR_DATA_512B_FIFO_CNT12(x) ((x) << S_WR_DATA_512B_FIFO_CNT12)
+#define G_WR_DATA_512B_FIFO_CNT12(x) (((x) >> S_WR_DATA_512B_FIFO_CNT12) & M_WR_DATA_512B_FIFO_CNT12)
+
+#define S_RD_DATA_ALIGN_FSM12    17
+#define V_RD_DATA_ALIGN_FSM12(x) ((x) << S_RD_DATA_ALIGN_FSM12)
+#define F_RD_DATA_ALIGN_FSM12    V_RD_DATA_ALIGN_FSM12(1U)
+
+#define S_RD_DATA_FETCH_FSM12    16
+#define V_RD_DATA_FETCH_FSM12(x) ((x) << S_RD_DATA_FETCH_FSM12)
+#define F_RD_DATA_FETCH_FSM12    V_RD_DATA_FETCH_FSM12(1U)
+
+#define S_COHERENCY_TX_FSM12    15
+#define V_COHERENCY_TX_FSM12(x) ((x) << S_COHERENCY_TX_FSM12)
+#define F_COHERENCY_TX_FSM12    V_COHERENCY_TX_FSM12(1U)
+
+#define S_COHERENCY_RX_FSM12    14
+#define V_COHERENCY_RX_FSM12(x) ((x) << S_COHERENCY_RX_FSM12)
+#define F_COHERENCY_RX_FSM12    V_COHERENCY_RX_FSM12(1U)
+
+#define S_ARB_REQ_FSM12    13
+#define V_ARB_REQ_FSM12(x) ((x) << S_ARB_REQ_FSM12)
+#define F_ARB_REQ_FSM12    V_ARB_REQ_FSM12(1U)
+
+#define S_CMD_SPLIT_FSM12    10
+#define M_CMD_SPLIT_FSM12    0x7U
+#define V_CMD_SPLIT_FSM12(x) ((x) << S_CMD_SPLIT_FSM12)
+#define G_CMD_SPLIT_FSM12(x) (((x) >> S_CMD_SPLIT_FSM12) & M_CMD_SPLIT_FSM12)
+
+#define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG1 0xe5a0
+
+#define S_RD_CMD_TAG_FIFO_CNT0    8
+#define M_RD_CMD_TAG_FIFO_CNT0    0xffU
+#define V_RD_CMD_TAG_FIFO_CNT0(x) ((x) << S_RD_CMD_TAG_FIFO_CNT0)
+#define G_RD_CMD_TAG_FIFO_CNT0(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT0) & M_RD_CMD_TAG_FIFO_CNT0)
+
+#define S_RD_DATA_FIFO_CNT0    0
+#define M_RD_DATA_FIFO_CNT0    0xffU
+#define V_RD_DATA_FIFO_CNT0(x) ((x) << S_RD_DATA_FIFO_CNT0)
+#define G_RD_DATA_FIFO_CNT0(x) (((x) >> S_RD_DATA_FIFO_CNT0) & M_RD_DATA_FIFO_CNT0)
+
+#define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG1 0xe5c0
+
+#define S_RD_CMD_TAG_FIFO_CNT1    8
+#define M_RD_CMD_TAG_FIFO_CNT1    0xffU
+#define V_RD_CMD_TAG_FIFO_CNT1(x) ((x) << S_RD_CMD_TAG_FIFO_CNT1)
+#define G_RD_CMD_TAG_FIFO_CNT1(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT1) & M_RD_CMD_TAG_FIFO_CNT1)
+
+#define S_RD_DATA_FIFO_CNT1    0
+#define M_RD_DATA_FIFO_CNT1    0xffU
+#define V_RD_DATA_FIFO_CNT1(x) ((x) << S_RD_DATA_FIFO_CNT1)
+#define G_RD_DATA_FIFO_CNT1(x) (((x) >> S_RD_DATA_FIFO_CNT1) & M_RD_DATA_FIFO_CNT1)
+
+#define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG1 0xe5e0
+
+#define S_RD_CMD_TAG_FIFO_CNT2    8
+#define M_RD_CMD_TAG_FIFO_CNT2    0xffU
+#define V_RD_CMD_TAG_FIFO_CNT2(x) ((x) << S_RD_CMD_TAG_FIFO_CNT2)
+#define G_RD_CMD_TAG_FIFO_CNT2(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT2) & M_RD_CMD_TAG_FIFO_CNT2)
+
+#define S_RD_DATA_FIFO_CNT2    0
+#define M_RD_DATA_FIFO_CNT2    0xffU
+#define V_RD_DATA_FIFO_CNT2(x) ((x) << S_RD_DATA_FIFO_CNT2)
+#define G_RD_DATA_FIFO_CNT2(x) (((x) >> S_RD_DATA_FIFO_CNT2) & M_RD_DATA_FIFO_CNT2)
+
+#define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG1 0xe600
+
+#define S_RD_CMD_TAG_FIFO_CNT3    8
+#define M_RD_CMD_TAG_FIFO_CNT3    0xffU
+#define V_RD_CMD_TAG_FIFO_CNT3(x) ((x) << S_RD_CMD_TAG_FIFO_CNT3)
+#define G_RD_CMD_TAG_FIFO_CNT3(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT3) & M_RD_CMD_TAG_FIFO_CNT3)
+
+#define S_RD_DATA_FIFO_CNT3    0
+#define M_RD_DATA_FIFO_CNT3    0xffU
+#define V_RD_DATA_FIFO_CNT3(x) ((x) << S_RD_DATA_FIFO_CNT3)
+#define G_RD_DATA_FIFO_CNT3(x) (((x) >> S_RD_DATA_FIFO_CNT3) & M_RD_DATA_FIFO_CNT3)
+
+#define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe640
+#define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe660
+#define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe680
+#define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6a0
+#define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6c0
+#define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe6e0
+#define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe700
+#define A_MA_LE_CLNT_EXP_WR_CYC_CNT_LO 0xe720
+#define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_LO 0xe740
+#define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_LO 0xe760
+#define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe780
+#define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe7a0
+#define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_LO 0xe7c0
+#define A_MA_EDRAM0_WR_REQ_CNT_HI 0xe800
+#define A_MA_EDRAM0_WR_REQ_CNT_LO 0xe820
+#define A_MA_EDRAM1_WR_REQ_CNT_HI 0xe840
+#define A_MA_EDRAM1_WR_REQ_CNT_LO 0xe860
+#define A_MA_EXT_MEMORY0_WR_REQ_CNT_HI 0xe880
+#define A_MA_EXT_MEMORY0_WR_REQ_CNT_LO 0xe8a0
+#define A_MA_EXT_MEMORY1_WR_REQ_CNT_HI 0xe8c0
+#define A_MA_EXT_MEMORY1_WR_REQ_CNT_LO 0xe8e0
+#define A_MA_EDRAM0_RD_REQ_CNT_HI 0xe900
+#define A_MA_EDRAM0_RD_REQ_CNT_LO 0xe920
+#define A_MA_EDRAM1_RD_REQ_CNT_HI 0xe940
+#define A_MA_EDRAM1_RD_REQ_CNT_LO 0xe960
+#define A_MA_EXT_MEMORY0_RD_REQ_CNT_HI 0xe980
+#define A_MA_EXT_MEMORY0_RD_REQ_CNT_LO 0xe9a0
+#define A_MA_EXT_MEMORY1_RD_REQ_CNT_HI 0xe9c0
+#define A_MA_EXT_MEMORY1_RD_REQ_CNT_LO 0xe9e0
+#define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xec00
+#define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xec20
+#define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xec40
+#define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xec60
+#define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_HI 0xec80
+#define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeca0
+#define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_HI 0xecc0
+#define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_LO 0xece0
+#define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_HI 0xed00
+#define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_LO 0xed20
+#define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xed40
+#define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xed60
+#define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xed80
+#define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xeda0
+#define A_MA_LE_CLNT_ACT_RD_CYC_CNT_HI 0xedc0
+#define A_MA_LE_CLNT_ACT_RD_CYC_CNT_LO 0xede0
+#define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_HI 0xee00
+#define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_LO 0xee20
+#define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_HI 0xee40
+#define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_LO 0xee60
+#define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_HI 0xee80
+#define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeea0
+#define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_HI 0xeec0
+#define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_LO 0xeee0
+#define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_HI 0xef00
+#define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_LO 0xef20
+#define A_MA_PM_TX_RD_THROTTLE_STATUS 0xf000
+
+#define S_PTMAXTRANS    16
+#define V_PTMAXTRANS(x) ((x) << S_PTMAXTRANS)
+#define F_PTMAXTRANS    V_PTMAXTRANS(1U)
+
+#define S_PTFLITCNT    0
+#define M_PTFLITCNT    0xffU
+#define V_PTFLITCNT(x) ((x) << S_PTFLITCNT)
+#define G_PTFLITCNT(x) (((x) >> S_PTFLITCNT) & M_PTFLITCNT)
+
+#define A_MA_PM_RX_RD_THROTTLE_STATUS 0xf020
+
+#define S_PRMAXTRANS    16
+#define V_PRMAXTRANS(x) ((x) << S_PRMAXTRANS)
+#define F_PRMAXTRANS    V_PRMAXTRANS(1U)
+
+#define S_PRFLITCNT    0
+#define M_PRFLITCNT    0xffU
+#define V_PRFLITCNT(x) ((x) << S_PRFLITCNT)
+#define G_PRFLITCNT(x) (((x) >> S_PRFLITCNT) & M_PRFLITCNT)
 
 /* registers for module EDC_0 */
 #define EDC_0_BASE_ADDR 0x7900
@@ -12538,6 +20556,14 @@
 #define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
 #define F_OBQSGERX0PARERR    V_OBQSGERX0PARERR(1U)
 
+#define S_PCIE2CIMINTFPARERR    29
+#define V_PCIE2CIMINTFPARERR(x) ((x) << S_PCIE2CIMINTFPARERR)
+#define F_PCIE2CIMINTFPARERR    V_PCIE2CIMINTFPARERR(1U)
+
+#define S_IBQPCIEPARERR    12
+#define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR)
+#define F_IBQPCIEPARERR    V_IBQPCIEPARERR(1U)
+
 #define A_CIM_HOST_INT_CAUSE 0x7b2c
 
 #define S_TIEQOUTPARERRINT    20
@@ -12866,6 +20892,10 @@
 #define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
 #define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)
 
+#define S_CIMQ1KEN    30
+#define V_CIMQ1KEN(x) ((x) << S_CIMQ1KEN)
+#define F_CIMQ1KEN    V_CIMQ1KEN(1U)
+
 #define A_CIM_HOST_ACC_CTRL 0x7b50
 
 #define S_HOSTBUSY    17
@@ -13082,6 +21112,11 @@
 #define V_DADDRTIMEOUT(x) ((x) << S_DADDRTIMEOUT)
 #define G_DADDRTIMEOUT(x) (((x) >> S_DADDRTIMEOUT) & M_DADDRTIMEOUT)
 
+#define S_DADDRTIMEOUTTYPE    0
+#define M_DADDRTIMEOUTTYPE    0x3U
+#define V_DADDRTIMEOUTTYPE(x) ((x) << S_DADDRTIMEOUTTYPE)
+#define G_DADDRTIMEOUTTYPE(x) (((x) >> S_DADDRTIMEOUTTYPE) & M_DADDRTIMEOUTTYPE)
+
 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
 
 #define S_DADDRILLEGAL    2
@@ -13089,6 +21124,11 @@
 #define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
 #define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)
 
+#define S_DADDRILLEGALTYPE    0
+#define M_DADDRILLEGALTYPE    0x3U
+#define V_DADDRILLEGALTYPE(x) ((x) << S_DADDRILLEGALTYPE)
+#define G_DADDRILLEGALTYPE(x) (((x) >> S_DADDRILLEGALTYPE) & M_DADDRILLEGALTYPE)
+
 #define A_CIM_DEBUG_PIF_CAUSE_MASK 0x7c10
 
 #define S_DPIFHOSTMASK    0
@@ -13101,6 +21141,11 @@
 #define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK)
 #define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK)
 
+#define S_T6_T5_DPIFHOSTMASK    0
+#define M_T6_T5_DPIFHOSTMASK    0x3fffffffU
+#define V_T6_T5_DPIFHOSTMASK(x) ((x) << S_T6_T5_DPIFHOSTMASK)
+#define G_T6_T5_DPIFHOSTMASK(x) (((x) >> S_T6_T5_DPIFHOSTMASK) & M_T6_T5_DPIFHOSTMASK)
+
 #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
 
 #define S_DPIFHUPAMASK    0
@@ -13120,6 +21165,11 @@
 #define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK)
 #define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK)
 
+#define S_T6_T5_DUPMASK    0
+#define M_T6_T5_DUPMASK    0x3fffffffU
+#define V_T6_T5_DUPMASK(x) ((x) << S_T6_T5_DUPMASK)
+#define G_T6_T5_DUPMASK(x) (((x) >> S_T6_T5_DUPMASK) & M_T6_T5_DUPMASK)
+
 #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
 
 #define S_DUPUACCMASK    0
@@ -13140,6 +21190,11 @@
 #define V_T5_PERREN(x) ((x) << S_T5_PERREN)
 #define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN)
 
+#define S_T6_T5_PERREN    0
+#define M_T6_T5_PERREN    0x3fffffffU
+#define V_T6_T5_PERREN(x) ((x) << S_T6_T5_PERREN)
+#define G_T6_T5_PERREN(x) (((x) >> S_T6_T5_PERREN) & M_T6_T5_PERREN)
+
 #define A_CIM_EEPROM_BUSY_BIT 0x7c28
 
 #define S_EEPROMBUSY    0
@@ -13152,6 +21207,10 @@
 #define V_MA_TIMER_ENABLE(x) ((x) << S_MA_TIMER_ENABLE)
 #define F_MA_TIMER_ENABLE    V_MA_TIMER_ENABLE(1U)
 
+#define S_SLOW_TIMER_ENABLE    1
+#define V_SLOW_TIMER_ENABLE(x) ((x) << S_SLOW_TIMER_ENABLE)
+#define F_SLOW_TIMER_ENABLE    V_SLOW_TIMER_ENABLE(1U)
+
 #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
 
 #define S_UP_PO_SINGLE_OUTSTANDING    0
@@ -13177,6 +21236,11 @@
 #define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE)
 #define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE)
 
+#define S_CIM_PCIE_PKT_ERR_CODE    8
+#define M_CIM_PCIE_PKT_ERR_CODE    0xffU
+#define V_CIM_PCIE_PKT_ERR_CODE(x) ((x) << S_CIM_PCIE_PKT_ERR_CODE)
+#define G_CIM_PCIE_PKT_ERR_CODE(x) (((x) >> S_CIM_PCIE_PKT_ERR_CODE) & M_CIM_PCIE_PKT_ERR_CODE)
+
 #define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
 #define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
 
@@ -13212,6 +21276,10 @@
 #define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL)
 #define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL    V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U)
 
+#define S_PCIE_OBQ_IF_DISABLE    5
+#define V_PCIE_OBQ_IF_DISABLE(x) ((x) << S_PCIE_OBQ_IF_DISABLE)
+#define F_PCIE_OBQ_IF_DISABLE    V_PCIE_OBQ_IF_DISABLE(1U)
+
 #define A_CIM_CGEN_GLOBAL 0x7c50
 
 #define S_CGEN_GLOBAL    0
@@ -13385,6 +21453,18 @@
 #define V_ETHUPEN(x) ((x) << S_ETHUPEN)
 #define F_ETHUPEN    V_ETHUPEN(1U)
 
+#define S_CXOFFOVERRIDE    3
+#define V_CXOFFOVERRIDE(x) ((x) << S_CXOFFOVERRIDE)
+#define F_CXOFFOVERRIDE    V_CXOFFOVERRIDE(1U)
+
+#define S_EGREDROPEN    1
+#define V_EGREDROPEN(x) ((x) << S_EGREDROPEN)
+#define F_EGREDROPEN    V_EGREDROPEN(1U)
+
+#define S_CFASTDEMUXEN    0
+#define V_CFASTDEMUXEN(x) ((x) << S_CFASTDEMUXEN)
+#define F_CFASTDEMUXEN    V_CFASTDEMUXEN(1U)
+
 #define A_TP_OUT_CONFIG 0x7d04
 
 #define S_PORTQFCEN    28
@@ -13480,6 +21560,30 @@
 #define V_EVNTAGEN(x) ((x) << S_EVNTAGEN)
 #define F_EVNTAGEN    V_EVNTAGEN(1U)
 
+#define S_CCPLACKMODE    13
+#define V_CCPLACKMODE(x) ((x) << S_CCPLACKMODE)
+#define F_CCPLACKMODE    V_CCPLACKMODE(1U)
+
+#define S_RMWHINTENABLE    12
+#define V_RMWHINTENABLE(x) ((x) << S_RMWHINTENABLE)
+#define F_RMWHINTENABLE    V_RMWHINTENABLE(1U)
+
+#define S_EV6FLWEN    8
+#define V_EV6FLWEN(x) ((x) << S_EV6FLWEN)
+#define F_EV6FLWEN    V_EV6FLWEN(1U)
+
+#define S_EVLANPRIO    6
+#define V_EVLANPRIO(x) ((x) << S_EVLANPRIO)
+#define F_EVLANPRIO    V_EVLANPRIO(1U)
+
+#define S_CRXPKTENC    3
+#define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
+#define F_CRXPKTENC    V_CRXPKTENC(1U)
+
+#define S_CRXPKTXT    1
+#define V_CRXPKTXT(x) ((x) << S_CRXPKTXT)
+#define F_CRXPKTXT    V_CRXPKTXT(1U)
+
 #define A_TP_GLOBAL_CONFIG 0x7d08
 
 #define S_SYNCOOKIEPARAMS    26
@@ -13566,6 +21670,10 @@
 #define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
 #define F_ISSFROMCPLENABLE    V_ISSFROMCPLENABLE(1U)
 
+#define S_ACTIVEFILTERCOUNTS    22
+#define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS)
+#define F_ACTIVEFILTERCOUNTS    V_ACTIVEFILTERCOUNTS(1U)
+
 #define A_TP_DB_CONFIG 0x7d0c
 
 #define S_DBMAXOPCNT    24
@@ -13850,6 +21958,18 @@
 #define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT)
 #define F_ENABLEFILTERNAT    V_ENABLEFILTERNAT(1U)
 
+#define S_ENABLEFINCHECK    31
+#define V_ENABLEFINCHECK(x) ((x) << S_ENABLEFINCHECK)
+#define F_ENABLEFINCHECK    V_ENABLEFINCHECK(1U)
+
+#define S_ENABLEMIBVFPLD    21
+#define V_ENABLEMIBVFPLD(x) ((x) << S_ENABLEMIBVFPLD)
+#define F_ENABLEMIBVFPLD    V_ENABLEMIBVFPLD(1U)
+
+#define S_DISABLESEPPSHFLAG    4
+#define V_DISABLESEPPSHFLAG(x) ((x) << S_DISABLESEPPSHFLAG)
+#define F_DISABLESEPPSHFLAG    V_DISABLESEPPSHFLAG(1U)
+
 #define A_TP_PC_CONFIG2 0x7d4c
 
 #define S_ENABLEMTUVFMODE    31
@@ -14147,6 +22267,31 @@
 #define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE)
 #define F_SETTIMEENABLE    V_SETTIMEENABLE(1U)
 
+#define S_ECNCNGFIFO    19
+#define V_ECNCNGFIFO(x) ((x) << S_ECNCNGFIFO)
+#define F_ECNCNGFIFO    V_ECNCNGFIFO(1U)
+
+#define S_ECNSYNACK    18
+#define V_ECNSYNACK(x) ((x) << S_ECNSYNACK)
+#define F_ECNSYNACK    V_ECNSYNACK(1U)
+
+#define S_ECNTHRESH    16
+#define M_ECNTHRESH    0x3U
+#define V_ECNTHRESH(x) ((x) << S_ECNTHRESH)
+#define G_ECNTHRESH(x) (((x) >> S_ECNTHRESH) & M_ECNTHRESH)
+
+#define S_ECNMODE    15
+#define V_ECNMODE(x) ((x) << S_ECNMODE)
+#define F_ECNMODE    V_ECNMODE(1U)
+
+#define S_ECNMODECWR    14
+#define V_ECNMODECWR(x) ((x) << S_ECNMODECWR)
+#define F_ECNMODECWR    V_ECNMODECWR(1U)
+
+#define S_FORCESHOVE    10
+#define V_FORCESHOVE(x) ((x) << S_FORCESHOVE)
+#define F_FORCESHOVE    V_FORCESHOVE(1U)
+
 #define A_TP_PARA_REG1 0x7d64
 
 #define S_INITRWND    16
@@ -14426,6 +22571,14 @@
 #define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK)
 #define F_ENABLEFRAGCHECK    V_ENABLEFRAGCHECK(1U)
 
+#define S_ENABLEFCOECHECK    6
+#define V_ENABLEFCOECHECK(x) ((x) << S_ENABLEFCOECHECK)
+#define F_ENABLEFCOECHECK    V_ENABLEFCOECHECK(1U)
+
+#define S_ENABLERDMAFIX    1
+#define V_ENABLERDMAFIX(x) ((x) << S_ENABLERDMAFIX)
+#define F_ENABLERDMAFIX    V_ENABLERDMAFIX(1U)
+
 #define A_TP_PARA_REG6 0x7d78
 
 #define S_TXPDUSIZEADJ    24
@@ -14522,6 +22675,14 @@
 #define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK)
 #define F_DISABLEPDUACK    V_DISABLEPDUACK(1U)
 
+#define S_TXTCAMKEY    22
+#define V_TXTCAMKEY(x) ((x) << S_TXTCAMKEY)
+#define F_TXTCAMKEY    V_TXTCAMKEY(1U)
+
+#define S_ENABLECBYP    21
+#define V_ENABLECBYP(x) ((x) << S_ENABLECBYP)
+#define F_ENABLECBYP    V_ENABLECBYP(1U)
+
 #define A_TP_PARA_REG7 0x7d7c
 
 #define S_PMMAXXFERLEN1    16
@@ -14571,6 +22732,20 @@
 #define V_ENGINELATENCYBASE(x) ((x) << S_ENGINELATENCYBASE)
 #define G_ENGINELATENCYBASE(x) (((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE)
 
+#define A_TP_PARA_REG8 0x7d84
+
+#define S_ECNACKECT    2
+#define V_ECNACKECT(x) ((x) << S_ECNACKECT)
+#define F_ECNACKECT    V_ECNACKECT(1U)
+
+#define S_ECNFINECT    1
+#define V_ECNFINECT(x) ((x) << S_ECNFINECT)
+#define F_ECNFINECT    V_ECNFINECT(1U)
+
+#define S_ECNSYNECT    0
+#define V_ECNSYNECT(x) ((x) << S_ECNSYNECT)
+#define F_ECNSYNECT    V_ECNSYNECT(1U)
+
 #define A_TP_ERR_CONFIG 0x7d8c
 
 #define S_TNLERRORPING    30
@@ -14685,6 +22860,22 @@
 #define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA)
 #define F_DROPERRORFPMA    V_DROPERRORFPMA(1U)
 
+#define S_TNLERROROPAQUE    27
+#define V_TNLERROROPAQUE(x) ((x) << S_TNLERROROPAQUE)
+#define F_TNLERROROPAQUE    V_TNLERROROPAQUE(1U)
+
+#define S_TNLERRORIP6OPT    26
+#define V_TNLERRORIP6OPT(x) ((x) << S_TNLERRORIP6OPT)
+#define F_TNLERRORIP6OPT    V_TNLERRORIP6OPT(1U)
+
+#define S_DROPERROROPAQUE    11
+#define V_DROPERROROPAQUE(x) ((x) << S_DROPERROROPAQUE)
+#define F_DROPERROROPAQUE    V_DROPERROROPAQUE(1U)
+
+#define S_DROPERRORIP6OPT    10
+#define V_DROPERRORIP6OPT(x) ((x) << S_DROPERRORIP6OPT)
+#define F_DROPERRORIP6OPT    V_DROPERRORIP6OPT(1U)
+
 #define A_TP_TIMER_RESOLUTION 0x7d90
 
 #define S_TIMERRESOLUTION    16
@@ -14821,6 +23012,11 @@
 #define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
 #define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)
 
+#define S_T6_SYNSHIFTMAX    24
+#define M_T6_SYNSHIFTMAX    0xfU
+#define V_T6_SYNSHIFTMAX(x) ((x) << S_T6_SYNSHIFTMAX)
+#define G_T6_SYNSHIFTMAX(x) (((x) >> S_T6_SYNSHIFTMAX) & M_T6_SYNSHIFTMAX)
+
 #define A_TP_TM_CONFIG 0x7dc4
 
 #define S_CMTIMERMAXNUM    0
@@ -14926,6 +23122,78 @@
 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
 
+#define S_ULPTYPE7LENGTH    31
+#define V_ULPTYPE7LENGTH(x) ((x) << S_ULPTYPE7LENGTH)
+#define F_ULPTYPE7LENGTH    V_ULPTYPE7LENGTH(1U)
+
+#define S_ULPTYPE7OFFSET    28
+#define M_ULPTYPE7OFFSET    0x7U
+#define V_ULPTYPE7OFFSET(x) ((x) << S_ULPTYPE7OFFSET)
+#define G_ULPTYPE7OFFSET(x) (((x) >> S_ULPTYPE7OFFSET) & M_ULPTYPE7OFFSET)
+
+#define S_ULPTYPE6LENGTH    27
+#define V_ULPTYPE6LENGTH(x) ((x) << S_ULPTYPE6LENGTH)
+#define F_ULPTYPE6LENGTH    V_ULPTYPE6LENGTH(1U)
+
+#define S_ULPTYPE6OFFSET    24
+#define M_ULPTYPE6OFFSET    0x7U
+#define V_ULPTYPE6OFFSET(x) ((x) << S_ULPTYPE6OFFSET)
+#define G_ULPTYPE6OFFSET(x) (((x) >> S_ULPTYPE6OFFSET) & M_ULPTYPE6OFFSET)
+
+#define S_ULPTYPE5LENGTH    23
+#define V_ULPTYPE5LENGTH(x) ((x) << S_ULPTYPE5LENGTH)
+#define F_ULPTYPE5LENGTH    V_ULPTYPE5LENGTH(1U)
+
+#define S_ULPTYPE5OFFSET    20
+#define M_ULPTYPE5OFFSET    0x7U
+#define V_ULPTYPE5OFFSET(x) ((x) << S_ULPTYPE5OFFSET)
+#define G_ULPTYPE5OFFSET(x) (((x) >> S_ULPTYPE5OFFSET) & M_ULPTYPE5OFFSET)
+
+#define S_ULPTYPE4LENGTH    19
+#define V_ULPTYPE4LENGTH(x) ((x) << S_ULPTYPE4LENGTH)
+#define F_ULPTYPE4LENGTH    V_ULPTYPE4LENGTH(1U)
+
+#define S_ULPTYPE4OFFSET    16
+#define M_ULPTYPE4OFFSET    0x7U
+#define V_ULPTYPE4OFFSET(x) ((x) << S_ULPTYPE4OFFSET)
+#define G_ULPTYPE4OFFSET(x) (((x) >> S_ULPTYPE4OFFSET) & M_ULPTYPE4OFFSET)
+
+#define S_ULPTYPE3LENGTH    15
+#define V_ULPTYPE3LENGTH(x) ((x) << S_ULPTYPE3LENGTH)
+#define F_ULPTYPE3LENGTH    V_ULPTYPE3LENGTH(1U)
+
+#define S_ULPTYPE3OFFSET    12
+#define M_ULPTYPE3OFFSET    0x7U
+#define V_ULPTYPE3OFFSET(x) ((x) << S_ULPTYPE3OFFSET)
+#define G_ULPTYPE3OFFSET(x) (((x) >> S_ULPTYPE3OFFSET) & M_ULPTYPE3OFFSET)
+
+#define S_ULPTYPE2LENGTH    11
+#define V_ULPTYPE2LENGTH(x) ((x) << S_ULPTYPE2LENGTH)
+#define F_ULPTYPE2LENGTH    V_ULPTYPE2LENGTH(1U)
+
+#define S_ULPTYPE2OFFSET    8
+#define M_ULPTYPE2OFFSET    0x7U
+#define V_ULPTYPE2OFFSET(x) ((x) << S_ULPTYPE2OFFSET)
+#define G_ULPTYPE2OFFSET(x) (((x) >> S_ULPTYPE2OFFSET) & M_ULPTYPE2OFFSET)
+
+#define S_ULPTYPE1LENGTH    7
+#define V_ULPTYPE1LENGTH(x) ((x) << S_ULPTYPE1LENGTH)
+#define F_ULPTYPE1LENGTH    V_ULPTYPE1LENGTH(1U)
+
+#define S_ULPTYPE1OFFSET    4
+#define M_ULPTYPE1OFFSET    0x7U
+#define V_ULPTYPE1OFFSET(x) ((x) << S_ULPTYPE1OFFSET)
+#define G_ULPTYPE1OFFSET(x) (((x) >> S_ULPTYPE1OFFSET) & M_ULPTYPE1OFFSET)
+
+#define S_ULPTYPE0LENGTH    3
+#define V_ULPTYPE0LENGTH(x) ((x) << S_ULPTYPE0LENGTH)
+#define F_ULPTYPE0LENGTH    V_ULPTYPE0LENGTH(1U)
+
+#define S_ULPTYPE0OFFSET    0
+#define M_ULPTYPE0OFFSET    0x7U
+#define V_ULPTYPE0OFFSET(x) ((x) << S_ULPTYPE0OFFSET)
+#define G_ULPTYPE0OFFSET(x) (((x) >> S_ULPTYPE0OFFSET) & M_ULPTYPE0OFFSET)
+
 #define A_TP_RSS_LKP_TABLE 0x7dec
 
 #define S_LKPTBLROWVLD    31
@@ -14947,6 +23215,11 @@
 #define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
 #define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)
 
+#define S_T6_LKPTBLROWIDX    20
+#define M_T6_LKPTBLROWIDX    0x7ffU
+#define V_T6_LKPTBLROWIDX(x) ((x) << S_T6_LKPTBLROWIDX)
+#define G_T6_LKPTBLROWIDX(x) (((x) >> S_T6_LKPTBLROWIDX) & M_T6_LKPTBLROWIDX)
+
 #define A_TP_RSS_CONFIG 0x7df0
 
 #define S_TNL4TUPENIPV6    31
@@ -15073,6 +23346,10 @@
 #define V_HASHXOR(x) ((x) << S_HASHXOR)
 #define F_HASHXOR    V_HASHXOR(1U)
 
+#define S_TNLFCOESID    22
+#define V_TNLFCOESID(x) ((x) << S_TNLFCOESID)
+#define F_TNLFCOESID    V_TNLFCOESID(1U)
+
 #define A_TP_RSS_CONFIG_TNL 0x7df4
 
 #define S_MASKSIZE    28
@@ -15089,6 +23366,14 @@
 #define V_USEWIRECH(x) ((x) << S_USEWIRECH)
 #define F_USEWIRECH    V_USEWIRECH(1U)
 
+#define S_HASHALL    2
+#define V_HASHALL(x) ((x) << S_HASHALL)
+#define F_HASHALL    V_HASHALL(1U)
+
+#define S_HASHETH    1
+#define V_HASHETH(x) ((x) << S_HASHETH)
+#define F_HASHETH    V_HASHETH(1U)
+
 #define A_TP_RSS_CONFIG_OFD 0x7df8
 
 #define S_RRCPLMAPEN    20
@@ -15168,6 +23453,20 @@
 #define V_VFFWEN(x) ((x) << S_VFFWEN)
 #define F_VFFWEN    V_VFFWEN(1U)
 
+#define S_KEYWRADDRX    30
+#define M_KEYWRADDRX    0x3U
+#define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX)
+#define G_KEYWRADDRX(x) (((x) >> S_KEYWRADDRX) & M_KEYWRADDRX)
+
+#define S_KEYEXTEND    26
+#define V_KEYEXTEND(x) ((x) << S_KEYEXTEND)
+#define F_KEYEXTEND    V_KEYEXTEND(1U)
+
+#define S_T6_VFWRADDR    8
+#define M_T6_VFWRADDR    0xffU
+#define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR)
+#define G_T6_VFWRADDR(x) (((x) >> S_T6_VFWRADDR) & M_T6_VFWRADDR)
+
 #define A_TP_RSS_CONFIG_CNG 0x7e04
 
 #define S_CHNCOUNT3    31
@@ -15551,6 +23850,10 @@
 #define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR)
 #define F_CTPOUTPLDFIFOPERR    V_CTPOUTPLDFIFOPERR(1U)
 
+#define S_SRQTABLEPERR    1
+#define V_SRQTABLEPERR(x) ((x) << S_SRQTABLEPERR)
+#define F_SRQTABLEPERR    V_SRQTABLEPERR(1U)
+
 #define A_TP_INT_CAUSE 0x7e74
 #define A_TP_PER_ENABLE 0x7e78
 #define A_TP_FLM_FREE_PS_CNT 0x7e80
@@ -16256,6 +24559,14 @@
 #define V_TXMAPCHANNEL0(x) ((x) << S_TXMAPCHANNEL0)
 #define G_TXMAPCHANNEL0(x) (((x) >> S_TXMAPCHANNEL0) & M_TXMAPCHANNEL0)
 
+#define S_TXLPKCHANNEL1    17
+#define V_TXLPKCHANNEL1(x) ((x) << S_TXLPKCHANNEL1)
+#define F_TXLPKCHANNEL1    V_TXLPKCHANNEL1(1U)
+
+#define S_TXLPKCHANNEL0    16
+#define V_TXLPKCHANNEL0(x) ((x) << S_TXLPKCHANNEL0)
+#define F_TXLPKCHANNEL0    V_TXLPKCHANNEL0(1U)
+
 #define A_TP_TX_SCHED_HDR 0x23
 
 #define S_TXMAPHDRCHANNEL7    28
@@ -16613,13 +24924,56 @@
 #define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
 #define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)
 
+#define S_PRIENABLE    30
+#define V_PRIENABLE(x) ((x) << S_PRIENABLE)
+#define F_PRIENABLE    V_PRIENABLE(1U)
+
+#define S_T6_CHNENABLE    29
+#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
+#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
+
 #define A_TP_RSS_PF1_CONFIG 0x31
+
+#define S_T6_CHNENABLE    29
+#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
+#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
+
 #define A_TP_RSS_PF2_CONFIG 0x32
+
+#define S_T6_CHNENABLE    29
+#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
+#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
+
 #define A_TP_RSS_PF3_CONFIG 0x33
+
+#define S_T6_CHNENABLE    29
+#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
+#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
+
 #define A_TP_RSS_PF4_CONFIG 0x34
+
+#define S_T6_CHNENABLE    29
+#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
+#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
+
 #define A_TP_RSS_PF5_CONFIG 0x35
+
+#define S_T6_CHNENABLE    29
+#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
+#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
+
 #define A_TP_RSS_PF6_CONFIG 0x36
+
+#define S_T6_CHNENABLE    29
+#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
+#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
+
 #define A_TP_RSS_PF7_CONFIG 0x37
+
+#define S_T6_CHNENABLE    29
+#define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
+#define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
+
 #define A_TP_RSS_PF_MAP 0x38
 
 #define S_LKPIDXSIZE    24
@@ -16809,6 +25163,13 @@
 #define V_ETHTYPE0(x) ((x) << S_ETHTYPE0)
 #define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0)
 
+#define A_TP_VXLAN_HEADER 0x53
+
+#define S_VXLANPORT    0
+#define M_VXLANPORT    0xffffU
+#define V_VXLANPORT(x) ((x) << S_VXLANPORT)
+#define G_VXLANPORT(x) (((x) >> S_VXLANPORT) & M_VXLANPORT)
+
 #define A_TP_CORE_POWER 0x54
 
 #define S_SLEEPRDYVNT    12
@@ -16881,6 +25242,114 @@
 #define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN)
 #define F_IMMEDIATEEN    V_IMMEDIATEEN(1U)
 
+#define S_SHAREDRQEN    31
+#define V_SHAREDRQEN(x) ((x) << S_SHAREDRQEN)
+#define F_SHAREDRQEN    V_SHAREDRQEN(1U)
+
+#define S_SHAREDXRC    30
+#define V_SHAREDXRC(x) ((x) << S_SHAREDXRC)
+#define F_SHAREDXRC    V_SHAREDXRC(1U)
+
+#define A_TP_FRAG_CONFIG 0x56
+
+#define S_TLSMODE    16
+#define M_TLSMODE    0x3U
+#define V_TLSMODE(x) ((x) << S_TLSMODE)
+#define G_TLSMODE(x) (((x) >> S_TLSMODE) & M_TLSMODE)
+
+#define S_USERMODE    14
+#define M_USERMODE    0x3U
+#define V_USERMODE(x) ((x) << S_USERMODE)
+#define G_USERMODE(x) (((x) >> S_USERMODE) & M_USERMODE)
+
+#define S_FCOEMODE    12
+#define M_FCOEMODE    0x3U
+#define V_FCOEMODE(x) ((x) << S_FCOEMODE)
+#define G_FCOEMODE(x) (((x) >> S_FCOEMODE) & M_FCOEMODE)
+
+#define S_IANDPMODE    10
+#define M_IANDPMODE    0x3U
+#define V_IANDPMODE(x) ((x) << S_IANDPMODE)
+#define G_IANDPMODE(x) (((x) >> S_IANDPMODE) & M_IANDPMODE)
+
+#define S_RDDPMODE    8
+#define M_RDDPMODE    0x3U
+#define V_RDDPMODE(x) ((x) << S_RDDPMODE)
+#define G_RDDPMODE(x) (((x) >> S_RDDPMODE) & M_RDDPMODE)
+
+#define S_IWARPMODE    6
+#define M_IWARPMODE    0x3U
+#define V_IWARPMODE(x) ((x) << S_IWARPMODE)
+#define G_IWARPMODE(x) (((x) >> S_IWARPMODE) & M_IWARPMODE)
+
+#define S_ISCSIMODE    4
+#define M_ISCSIMODE    0x3U
+#define V_ISCSIMODE(x) ((x) << S_ISCSIMODE)
+#define G_ISCSIMODE(x) (((x) >> S_ISCSIMODE) & M_ISCSIMODE)
+
+#define S_DDPMODE    2
+#define M_DDPMODE    0x3U
+#define V_DDPMODE(x) ((x) << S_DDPMODE)
+#define G_DDPMODE(x) (((x) >> S_DDPMODE) & M_DDPMODE)
+
+#define S_PASSMODE    0
+#define M_PASSMODE    0x3U
+#define V_PASSMODE(x) ((x) << S_PASSMODE)
+#define G_PASSMODE(x) (((x) >> S_PASSMODE) & M_PASSMODE)
+
+#define A_TP_CMM_CONFIG 0x57
+
+#define S_WRCNTIDLE    16
+#define M_WRCNTIDLE    0xffffU
+#define V_WRCNTIDLE(x) ((x) << S_WRCNTIDLE)
+#define G_WRCNTIDLE(x) (((x) >> S_WRCNTIDLE) & M_WRCNTIDLE)
+
+#define S_RDTHRESHOLD    8
+#define M_RDTHRESHOLD    0x3fU
+#define V_RDTHRESHOLD(x) ((x) << S_RDTHRESHOLD)
+#define G_RDTHRESHOLD(x) (((x) >> S_RDTHRESHOLD) & M_RDTHRESHOLD)
+
+#define S_WRTHRLEVEL2    7
+#define V_WRTHRLEVEL2(x) ((x) << S_WRTHRLEVEL2)
+#define F_WRTHRLEVEL2    V_WRTHRLEVEL2(1U)
+
+#define S_WRTHRLEVEL1    6
+#define V_WRTHRLEVEL1(x) ((x) << S_WRTHRLEVEL1)
+#define F_WRTHRLEVEL1    V_WRTHRLEVEL1(1U)
+
+#define S_WRTHRTHRESHEN    5
+#define V_WRTHRTHRESHEN(x) ((x) << S_WRTHRTHRESHEN)
+#define F_WRTHRTHRESHEN    V_WRTHRTHRESHEN(1U)
+
+#define S_WRTHRTHRESH    0
+#define M_WRTHRTHRESH    0x1fU
+#define V_WRTHRTHRESH(x) ((x) << S_WRTHRTHRESH)
+#define G_WRTHRTHRESH(x) (((x) >> S_WRTHRTHRESH) & M_WRTHRTHRESH)
+
+#define A_TP_VXLAN_CONFIG 0x58
+
+#define S_VXLANFLAGS    16
+#define M_VXLANFLAGS    0xffffU
+#define V_VXLANFLAGS(x) ((x) << S_VXLANFLAGS)
+#define G_VXLANFLAGS(x) (((x) >> S_VXLANFLAGS) & M_VXLANFLAGS)
+
+#define S_VXLANTYPE    0
+#define M_VXLANTYPE    0xffffU
+#define V_VXLANTYPE(x) ((x) << S_VXLANTYPE)
+#define G_VXLANTYPE(x) (((x) >> S_VXLANTYPE) & M_VXLANTYPE)
+
+#define A_TP_NVGRE_CONFIG 0x59
+
+#define S_GREFLAGS    16
+#define M_GREFLAGS    0xffffU
+#define V_GREFLAGS(x) ((x) << S_GREFLAGS)
+#define G_GREFLAGS(x) (((x) >> S_GREFLAGS) & M_GREFLAGS)
+
+#define S_GRETYPE    0
+#define M_GRETYPE    0xffffU
+#define V_GRETYPE(x) ((x) << S_GRETYPE)
+#define G_GRETYPE(x) (((x) >> S_GRETYPE) & M_GRETYPE)
+
 #define A_TP_DBG_CLEAR 0x60
 #define A_TP_DBG_CORE_HDR0 0x61
 
@@ -17333,6 +25802,22 @@
 #define V_DELDRDY(x) ((x) << S_DELDRDY)
 #define F_DELDRDY    V_DELDRDY(1U)
 
+#define S_T5_ETXBUSY    1
+#define V_T5_ETXBUSY(x) ((x) << S_T5_ETXBUSY)
+#define F_T5_ETXBUSY    V_T5_ETXBUSY(1U)
+
+#define S_T5_EPCMDBUSY    0
+#define V_T5_EPCMDBUSY(x) ((x) << S_T5_EPCMDBUSY)
+#define F_T5_EPCMDBUSY    V_T5_EPCMDBUSY(1U)
+
+#define S_T6_ETXBUSY    1
+#define V_T6_ETXBUSY(x) ((x) << S_T6_ETXBUSY)
+#define F_T6_ETXBUSY    V_T6_ETXBUSY(1U)
+
+#define S_T6_EPCMDBUSY    0
+#define V_T6_EPCMDBUSY(x) ((x) << S_T6_EPCMDBUSY)
+#define F_T6_EPCMDBUSY    V_T6_EPCMDBUSY(1U)
+
 #define A_TP_DBG_ENG_RES1 0x67
 
 #define S_RXCPLSRDY    31
@@ -17422,6 +25907,10 @@
 #define V_RCFDATACMRDY(x) ((x) << S_RCFDATACMRDY)
 #define F_RCFDATACMRDY    V_RCFDATACMRDY(1U)
 
+#define S_RXISSSRDY    28
+#define V_RXISSSRDY(x) ((x) << S_RXISSSRDY)
+#define F_RXISSSRDY    V_RXISSSRDY(1U)
+
 #define A_TP_DBG_ENG_RES2 0x68
 
 #define S_CPLCMDRAW    24
@@ -17582,7 +26071,49 @@
 #define V_RXMODXOFF(x) ((x) << S_RXMODXOFF)
 #define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF)
 
+#define S_T5_RXFIFOCNG    20
+#define M_T5_RXFIFOCNG    0xfU
+#define V_T5_RXFIFOCNG(x) ((x) << S_T5_RXFIFOCNG)
+#define G_T5_RXFIFOCNG(x) (((x) >> S_T5_RXFIFOCNG) & M_T5_RXFIFOCNG)
+
+#define S_T5_RXPCMDCNG    14
+#define M_T5_RXPCMDCNG    0x3U
+#define V_T5_RXPCMDCNG(x) ((x) << S_T5_RXPCMDCNG)
+#define G_T5_RXPCMDCNG(x) (((x) >> S_T5_RXPCMDCNG) & M_T5_RXPCMDCNG)
+
+#define S_T6_RXFIFOCNG    20
+#define M_T6_RXFIFOCNG    0xfU
+#define V_T6_RXFIFOCNG(x) ((x) << S_T6_RXFIFOCNG)
+#define G_T6_RXFIFOCNG(x) (((x) >> S_T6_RXFIFOCNG) & M_T6_RXFIFOCNG)
+
+#define S_T6_RXPCMDCNG    14
+#define M_T6_RXPCMDCNG    0x3U
+#define V_T6_RXPCMDCNG(x) ((x) << S_T6_RXPCMDCNG)
+#define G_T6_RXPCMDCNG(x) (((x) >> S_T6_RXPCMDCNG) & M_T6_RXPCMDCNG)
+
 #define A_TP_DBG_ERROR_CNT 0x6c
+#define A_TP_DBG_CORE_CPL 0x6d
+
+#define S_CPLCMDOUT3    24
+#define M_CPLCMDOUT3    0xffU
+#define V_CPLCMDOUT3(x) ((x) << S_CPLCMDOUT3)
+#define G_CPLCMDOUT3(x) (((x) >> S_CPLCMDOUT3) & M_CPLCMDOUT3)
+
+#define S_CPLCMDOUT2    16
+#define M_CPLCMDOUT2    0xffU
+#define V_CPLCMDOUT2(x) ((x) << S_CPLCMDOUT2)
+#define G_CPLCMDOUT2(x) (((x) >> S_CPLCMDOUT2) & M_CPLCMDOUT2)
+
+#define S_CPLCMDOUT1    8
+#define M_CPLCMDOUT1    0xffU
+#define V_CPLCMDOUT1(x) ((x) << S_CPLCMDOUT1)
+#define G_CPLCMDOUT1(x) (((x) >> S_CPLCMDOUT1) & M_CPLCMDOUT1)
+
+#define S_CPLCMDOUT0    0
+#define M_CPLCMDOUT0    0xffU
+#define V_CPLCMDOUT0(x) ((x) << S_CPLCMDOUT0)
+#define G_CPLCMDOUT0(x) (((x) >> S_CPLCMDOUT0) & M_CPLCMDOUT0)
+
 #define A_TP_MIB_DEBUG 0x6f
 
 #define S_SRC3    31
@@ -17621,6 +26152,12 @@
 #define V_LINENUM0(x) ((x) << S_LINENUM0)
 #define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0)
 
+#define A_TP_DBG_CACHE_WR_ALL 0x70
+#define A_TP_DBG_CACHE_WR_HIT 0x71
+#define A_TP_DBG_CACHE_RD_ALL 0x72
+#define A_TP_DBG_CACHE_RD_HIT 0x73
+#define A_TP_DBG_CACHE_MC_REQ 0x74
+#define A_TP_DBG_CACHE_MC_RSP 0x75
 #define A_TP_T5_TX_DROP_CNT_CH0 0x120
 #define A_TP_T5_TX_DROP_CNT_CH1 0x121
 #define A_TP_TX_DROP_CNT_CH2 0x122
@@ -18090,7 +26627,36 @@
 #define V_TXFULL(x) ((x) << S_TXFULL)
 #define F_TXFULL    V_TXFULL(1U)
 
+#define S_FIFOGRERXVALID    15
+#define V_FIFOGRERXVALID(x) ((x) << S_FIFOGRERXVALID)
+#define F_FIFOGRERXVALID    V_FIFOGRERXVALID(1U)
+
+#define S_FIFOGRERXREADY    14
+#define V_FIFOGRERXREADY(x) ((x) << S_FIFOGRERXREADY)
+#define F_FIFOGRERXREADY    V_FIFOGRERXREADY(1U)
+
+#define S_FIFOGRERXSOCP    13
+#define V_FIFOGRERXSOCP(x) ((x) << S_FIFOGRERXSOCP)
+#define F_FIFOGRERXSOCP    V_FIFOGRERXSOCP(1U)
+
+#define S_T6_ESTATIC4    12
+#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
+#define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
+
+#define S_TXFULL_ESIDE0    0
+#define V_TXFULL_ESIDE0(x) ((x) << S_TXFULL_ESIDE0)
+#define F_TXFULL_ESIDE0    V_TXFULL_ESIDE0(1U)
+
 #define A_TP_DBG_ESIDE_DISP1 0x137
+
+#define S_T6_ESTATIC4    12
+#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
+#define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
+
+#define S_TXFULL_ESIDE1    0
+#define V_TXFULL_ESIDE1(x) ((x) << S_TXFULL_ESIDE1)
+#define F_TXFULL_ESIDE1    V_TXFULL_ESIDE1(1U)
+
 #define A_TP_MAC_MATCH_MAP0 0x138
 
 #define S_MAPVALUEWR    16
@@ -18119,7 +26685,25 @@
 #define G_MAPVALUERD(x) (((x) >> S_MAPVALUERD) & M_MAPVALUERD)
 
 #define A_TP_DBG_ESIDE_DISP2 0x13a
+
+#define S_T6_ESTATIC4    12
+#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
+#define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
+
+#define S_TXFULL_ESIDE2    0
+#define V_TXFULL_ESIDE2(x) ((x) << S_TXFULL_ESIDE2)
+#define F_TXFULL_ESIDE2    V_TXFULL_ESIDE2(1U)
+
 #define A_TP_DBG_ESIDE_DISP3 0x13b
+
+#define S_T6_ESTATIC4    12
+#define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
+#define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
+
+#define S_TXFULL_ESIDE3    0
+#define V_TXFULL_ESIDE3(x) ((x) << S_TXFULL_ESIDE3)
+#define F_TXFULL_ESIDE3    V_TXFULL_ESIDE3(1U)
+
 #define A_TP_DBG_ESIDE_HDR0 0x13c
 
 #define S_TCPSOPCNT    28
@@ -18267,6 +26851,10 @@
 #define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
 #define F_FRAG_LEN_MOD8_COMPAT    V_FRAG_LEN_MOD8_COMPAT(1U)
 
+#define S_USE_ENC_IDX    13
+#define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX)
+#define F_USE_ENC_IDX    V_USE_ENC_IDX(1U)
+
 #define A_TP_TX_DROP_CFG_CH2 0x142
 #define A_TP_TX_DROP_CFG_CH3 0x143
 #define A_TP_EGRESS_CONFIG 0x145
@@ -18387,6 +26975,14 @@
 #define V_TCPOPTTXFULL(x) ((x) << S_TCPOPTTXFULL)
 #define F_TCPOPTTXFULL    V_TCPOPTTXFULL(1U)
 
+#define S_PKTATTRSRDY    3
+#define V_PKTATTRSRDY(x) ((x) << S_PKTATTRSRDY)
+#define F_PKTATTRSRDY    V_PKTATTRSRDY(1U)
+
+#define S_PKTATTRDRDY    2
+#define V_PKTATTRDRDY(x) ((x) << S_PKTATTRDRDY)
+#define F_PKTATTRDRDY    V_PKTATTRDRDY(1U)
+
 #define A_TP_DBG_ESIDE_DEMUX 0x149
 
 #define S_EALLDONE    28
@@ -18654,6 +27250,11 @@
 #define V_ETXFULL(x) ((x) << S_ETXFULL)
 #define G_ETXFULL(x) (((x) >> S_ETXFULL) & M_ETXFULL)
 
+#define S_TXERRORCNT    8
+#define M_TXERRORCNT    0xffffffU
+#define V_TXERRORCNT(x) ((x) << S_TXERRORCNT)
+#define G_TXERRORCNT(x) (((x) >> S_TXERRORCNT) & M_TXERRORCNT)
+
 #define A_TP_ESIDE_SVID_MASK 0x151
 #define A_TP_ESIDE_DVID_MASK 0x152
 #define A_TP_ESIDE_ALIGN_MASK 0x153
@@ -18833,6 +27434,29 @@
 #define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0)
 #define G_OPT_PARSER_COOKIE_CHANNEL0(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0)
 
+#define A_TP_DBG_ESIDE_DEMUX_WAIT0 0x158
+#define A_TP_DBG_ESIDE_DEMUX_WAIT1 0x159
+#define A_TP_DBG_ESIDE_DEMUX_CNT0 0x15a
+#define A_TP_DBG_ESIDE_DEMUX_CNT1 0x15b
+#define A_TP_ESIDE_CONFIG 0x160
+
+#define S_VNI_EN    26
+#define V_VNI_EN(x) ((x) << S_VNI_EN)
+#define F_VNI_EN    V_VNI_EN(1U)
+
+#define S_ENC_RX_EN    25
+#define V_ENC_RX_EN(x) ((x) << S_ENC_RX_EN)
+#define F_ENC_RX_EN    V_ENC_RX_EN(1U)
+
+#define S_TNL_LKP_INNER_SEL    24
+#define V_TNL_LKP_INNER_SEL(x) ((x) << S_TNL_LKP_INNER_SEL)
+#define F_TNL_LKP_INNER_SEL    V_TNL_LKP_INNER_SEL(1U)
+
+#define S_ROCEV2UDPPORT    0
+#define M_ROCEV2UDPPORT    0xffffU
+#define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT)
+#define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT)
+
 #define A_TP_DBG_CSIDE_RX0 0x230
 
 #define S_CRXSOPCNT    28
@@ -19245,14 +27869,30 @@
 #define V_CMD_SEL(x) ((x) << S_CMD_SEL)
 #define F_CMD_SEL    V_CMD_SEL(1U)
 
+#define S_T5_TXFULL    31
+#define V_T5_TXFULL(x) ((x) << S_T5_TXFULL)
+#define F_T5_TXFULL    V_T5_TXFULL(1U)
+
 #define S_CPL5RXFULL    26
 #define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL)
 #define F_CPL5RXFULL    V_CPL5RXFULL(1U)
 
+#define S_T5_PLD_RXZEROP_SRDY    25
+#define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY)
+#define F_T5_PLD_RXZEROP_SRDY    V_T5_PLD_RXZEROP_SRDY(1U)
+
 #define S_PLD2XRXVALID    23
 #define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID)
 #define F_PLD2XRXVALID    V_PLD2XRXVALID(1U)
 
+#define S_T5_DDP_SRDY    22
+#define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY)
+#define F_T5_DDP_SRDY    V_T5_DDP_SRDY(1U)
+
+#define S_T5_DDP_DRDY    21
+#define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY)
+#define F_T5_DDP_DRDY    V_T5_DDP_DRDY(1U)
+
 #define S_DDPSTATE    16
 #define M_DDPSTATE    0x1fU
 #define V_DDPSTATE(x) ((x) << S_DDPSTATE)
@@ -19289,7 +27929,56 @@
 #define V_TXFULL2X(x) ((x) << S_TXFULL2X)
 #define F_TXFULL2X    V_TXFULL2X(1U)
 
+#define S_T6_TXFULL    31
+#define V_T6_TXFULL(x) ((x) << S_T6_TXFULL)
+#define F_T6_TXFULL    V_T6_TXFULL(1U)
+
+#define S_T6_PLD_RXZEROP_SRDY    25
+#define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY)
+#define F_T6_PLD_RXZEROP_SRDY    V_T6_PLD_RXZEROP_SRDY(1U)
+
+#define S_T6_DDP_SRDY    22
+#define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY)
+#define F_T6_DDP_SRDY    V_T6_DDP_SRDY(1U)
+
+#define S_T6_DDP_DRDY    21
+#define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY)
+#define F_T6_DDP_DRDY    V_T6_DDP_DRDY(1U)
+
 #define A_TP_DBG_CSIDE_DISP1 0x23b
+
+#define S_T5_TXFULL    31
+#define V_T5_TXFULL(x) ((x) << S_T5_TXFULL)
+#define F_T5_TXFULL    V_T5_TXFULL(1U)
+
+#define S_T5_PLD_RXZEROP_SRDY    25
+#define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY)
+#define F_T5_PLD_RXZEROP_SRDY    V_T5_PLD_RXZEROP_SRDY(1U)
+
+#define S_T5_DDP_SRDY    22
+#define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY)
+#define F_T5_DDP_SRDY    V_T5_DDP_SRDY(1U)
+
+#define S_T5_DDP_DRDY    21
+#define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY)
+#define F_T5_DDP_DRDY    V_T5_DDP_DRDY(1U)
+
+#define S_T6_TXFULL    31
+#define V_T6_TXFULL(x) ((x) << S_T6_TXFULL)
+#define F_T6_TXFULL    V_T6_TXFULL(1U)
+
+#define S_T6_PLD_RXZEROP_SRDY    25
+#define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY)
+#define F_T6_PLD_RXZEROP_SRDY    V_T6_PLD_RXZEROP_SRDY(1U)
+
+#define S_T6_DDP_SRDY    22
+#define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY)
+#define F_T6_DDP_SRDY    V_T6_DDP_SRDY(1U)
+
+#define S_T6_DDP_DRDY    21
+#define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY)
+#define F_T6_DDP_DRDY    V_T6_DDP_DRDY(1U)
+
 #define A_TP_DBG_CSIDE_DDP0 0x23c
 
 #define S_DDPMSGLATEST7    28
@@ -19496,6 +28185,10 @@
 #define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN)
 #define F_ATOMICCMDEN    V_ATOMICCMDEN(1U)
 
+#define S_ISCSICMDMODE    28
+#define V_ISCSICMDMODE(x) ((x) << S_ISCSICMDMODE)
+#define F_ISCSICMDMODE    V_ISCSICMDMODE(1U)
+
 #define A_TP_CSPI_POWER 0x243
 
 #define S_GATECHNTX3    11
@@ -19585,6 +28278,11 @@
 #define V_CRXFULL3(x) ((x) << S_CRXFULL3)
 #define F_CRXFULL3    V_CRXFULL3(1U)
 
+#define S_T5_CPRSSTATE3    24
+#define M_T5_CPRSSTATE3    0xfU
+#define V_T5_CPRSSTATE3(x) ((x) << S_T5_CPRSSTATE3)
+#define G_T5_CPRSSTATE3(x) (((x) >> S_T5_CPRSSTATE3) & M_T5_CPRSSTATE3)
+
 #define S_C4TUPBUSY2    23
 #define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2)
 #define F_C4TUPBUSY2    V_C4TUPBUSY2(1U)
@@ -19601,6 +28299,11 @@
 #define V_CRXFULL2(x) ((x) << S_CRXFULL2)
 #define F_CRXFULL2    V_CRXFULL2(1U)
 
+#define S_T5_CPRSSTATE2    16
+#define M_T5_CPRSSTATE2    0xfU
+#define V_T5_CPRSSTATE2(x) ((x) << S_T5_CPRSSTATE2)
+#define G_T5_CPRSSTATE2(x) (((x) >> S_T5_CPRSSTATE2) & M_T5_CPRSSTATE2)
+
 #define S_C4TUPBUSY1    15
 #define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1)
 #define F_C4TUPBUSY1    V_C4TUPBUSY1(1U)
@@ -19617,6 +28320,11 @@
 #define V_CRXFULL1(x) ((x) << S_CRXFULL1)
 #define F_CRXFULL1    V_CRXFULL1(1U)
 
+#define S_T5_CPRSSTATE1    8
+#define M_T5_CPRSSTATE1    0xfU
+#define V_T5_CPRSSTATE1(x) ((x) << S_T5_CPRSSTATE1)
+#define G_T5_CPRSSTATE1(x) (((x) >> S_T5_CPRSSTATE1) & M_T5_CPRSSTATE1)
+
 #define S_C4TUPBUSY0    7
 #define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0)
 #define F_C4TUPBUSY0    V_C4TUPBUSY0(1U)
@@ -19633,6 +28341,31 @@
 #define V_CRXFULL0(x) ((x) << S_CRXFULL0)
 #define F_CRXFULL0    V_CRXFULL0(1U)
 
+#define S_T5_CPRSSTATE0    0
+#define M_T5_CPRSSTATE0    0xfU
+#define V_T5_CPRSSTATE0(x) ((x) << S_T5_CPRSSTATE0)
+#define G_T5_CPRSSTATE0(x) (((x) >> S_T5_CPRSSTATE0) & M_T5_CPRSSTATE0)
+
+#define S_T6_CPRSSTATE3    24
+#define M_T6_CPRSSTATE3    0xfU
+#define V_T6_CPRSSTATE3(x) ((x) << S_T6_CPRSSTATE3)
+#define G_T6_CPRSSTATE3(x) (((x) >> S_T6_CPRSSTATE3) & M_T6_CPRSSTATE3)
+
+#define S_T6_CPRSSTATE2    16
+#define M_T6_CPRSSTATE2    0xfU
+#define V_T6_CPRSSTATE2(x) ((x) << S_T6_CPRSSTATE2)
+#define G_T6_CPRSSTATE2(x) (((x) >> S_T6_CPRSSTATE2) & M_T6_CPRSSTATE2)
+
+#define S_T6_CPRSSTATE1    8
+#define M_T6_CPRSSTATE1    0xfU
+#define V_T6_CPRSSTATE1(x) ((x) << S_T6_CPRSSTATE1)
+#define G_T6_CPRSSTATE1(x) (((x) >> S_T6_CPRSSTATE1) & M_T6_CPRSSTATE1)
+
+#define S_T6_CPRSSTATE0    0
+#define M_T6_CPRSSTATE0    0xfU
+#define V_T6_CPRSSTATE0(x) ((x) << S_T6_CPRSSTATE0)
+#define G_T6_CPRSSTATE0(x) (((x) >> S_T6_CPRSSTATE0) & M_T6_CPRSSTATE0)
+
 #define A_TP_DBG_CSIDE_DEMUX 0x247
 
 #define S_CALLDONE    28
@@ -19820,6 +28553,50 @@
 #define V_ERRVALID0(x) ((x) << S_ERRVALID0)
 #define F_ERRVALID0    V_ERRVALID0(1U)
 
+#define A_TP_DBG_CSIDE_TRACE_CNT 0x24a
+
+#define S_TRCSOPCNT    24
+#define M_TRCSOPCNT    0xffU
+#define V_TRCSOPCNT(x) ((x) << S_TRCSOPCNT)
+#define G_TRCSOPCNT(x) (((x) >> S_TRCSOPCNT) & M_TRCSOPCNT)
+
+#define S_TRCEOPCNT    16
+#define M_TRCEOPCNT    0xffU
+#define V_TRCEOPCNT(x) ((x) << S_TRCEOPCNT)
+#define G_TRCEOPCNT(x) (((x) >> S_TRCEOPCNT) & M_TRCEOPCNT)
+
+#define S_TRCFLTHIT    12
+#define M_TRCFLTHIT    0xfU
+#define V_TRCFLTHIT(x) ((x) << S_TRCFLTHIT)
+#define G_TRCFLTHIT(x) (((x) >> S_TRCFLTHIT) & M_TRCFLTHIT)
+
+#define S_TRCRNTPKT    8
+#define M_TRCRNTPKT    0xfU
+#define V_TRCRNTPKT(x) ((x) << S_TRCRNTPKT)
+#define G_TRCRNTPKT(x) (((x) >> S_TRCRNTPKT) & M_TRCRNTPKT)
+
+#define S_TRCPKTLEN    0
+#define M_TRCPKTLEN    0xffU
+#define V_TRCPKTLEN(x) ((x) << S_TRCPKTLEN)
+#define G_TRCPKTLEN(x) (((x) >> S_TRCPKTLEN) & M_TRCPKTLEN)
+
+#define A_TP_DBG_CSIDE_TRACE_RSS 0x24b
+#define A_TP_VLN_CONFIG 0x24c
+
+#define S_ETHTYPEQINQ    16
+#define M_ETHTYPEQINQ    0xffffU
+#define V_ETHTYPEQINQ(x) ((x) << S_ETHTYPEQINQ)
+#define G_ETHTYPEQINQ(x) (((x) >> S_ETHTYPEQINQ) & M_ETHTYPEQINQ)
+
+#define S_ETHTYPEVLAN    0
+#define M_ETHTYPEVLAN    0xffffU
+#define V_ETHTYPEVLAN(x) ((x) << S_ETHTYPEVLAN)
+#define G_ETHTYPEVLAN(x) (((x) >> S_ETHTYPEVLAN) & M_ETHTYPEVLAN)
+
+#define A_TP_DBG_CSIDE_ARBIT_WAIT0 0x24d
+#define A_TP_DBG_CSIDE_ARBIT_WAIT1 0x24e
+#define A_TP_DBG_CSIDE_ARBIT_CNT0 0x24f
+#define A_TP_DBG_CSIDE_ARBIT_CNT1 0x250
 #define A_TP_FIFO_CONFIG 0x8c0
 
 #define S_CH1_OUTPUT    27
@@ -19957,6 +28734,10 @@
 #define A_TP_MIB_ENG_LINE_1 0x6d
 #define A_TP_MIB_ENG_LINE_2 0x6e
 #define A_TP_MIB_ENG_LINE_3 0x6f
+#define A_TP_MIB_TNL_ERR_0 0x70
+#define A_TP_MIB_TNL_ERR_1 0x71
+#define A_TP_MIB_TNL_ERR_2 0x72
+#define A_TP_MIB_TNL_ERR_3 0x73
 
 /* registers for module ULP_TX */
 #define ULP_TX_BASE_ADDR 0x8dc0
@@ -19999,6 +28780,46 @@
 #define V_LOSDR(x) ((x) << S_LOSDR)
 #define F_LOSDR    V_LOSDR(1U)
 
+#define S_ULIMIT_EXCLUSIVE_FIX    16
+#define V_ULIMIT_EXCLUSIVE_FIX(x) ((x) << S_ULIMIT_EXCLUSIVE_FIX)
+#define F_ULIMIT_EXCLUSIVE_FIX    V_ULIMIT_EXCLUSIVE_FIX(1U)
+
+#define S_ISO_A_FLAG_EN    15
+#define V_ISO_A_FLAG_EN(x) ((x) << S_ISO_A_FLAG_EN)
+#define F_ISO_A_FLAG_EN    V_ISO_A_FLAG_EN(1U)
+
+#define S_IWARP_SEQ_FLIT_DIS    14
+#define V_IWARP_SEQ_FLIT_DIS(x) ((x) << S_IWARP_SEQ_FLIT_DIS)
+#define F_IWARP_SEQ_FLIT_DIS    V_IWARP_SEQ_FLIT_DIS(1U)
+
+#define S_MR_SIZE_FIX_EN    13
+#define V_MR_SIZE_FIX_EN(x) ((x) << S_MR_SIZE_FIX_EN)
+#define F_MR_SIZE_FIX_EN    V_MR_SIZE_FIX_EN(1U)
+
+#define S_T10_ISO_FIX_EN    12
+#define V_T10_ISO_FIX_EN(x) ((x) << S_T10_ISO_FIX_EN)
+#define F_T10_ISO_FIX_EN    V_T10_ISO_FIX_EN(1U)
+
+#define S_CPL_FLAGS_UPDATE_EN    11
+#define V_CPL_FLAGS_UPDATE_EN(x) ((x) << S_CPL_FLAGS_UPDATE_EN)
+#define F_CPL_FLAGS_UPDATE_EN    V_CPL_FLAGS_UPDATE_EN(1U)
+
+#define S_IWARP_SEQ_UPDATE_EN    10
+#define V_IWARP_SEQ_UPDATE_EN(x) ((x) << S_IWARP_SEQ_UPDATE_EN)
+#define F_IWARP_SEQ_UPDATE_EN    V_IWARP_SEQ_UPDATE_EN(1U)
+
+#define S_SEQ_UPDATE_EN    9
+#define V_SEQ_UPDATE_EN(x) ((x) << S_SEQ_UPDATE_EN)
+#define F_SEQ_UPDATE_EN    V_SEQ_UPDATE_EN(1U)
+
+#define S_ERR_ITT_EN    8
+#define V_ERR_ITT_EN(x) ((x) << S_ERR_ITT_EN)
+#define F_ERR_ITT_EN    V_ERR_ITT_EN(1U)
+
+#define S_ATOMIC_FIX_DIS    7
+#define V_ATOMIC_FIX_DIS(x) ((x) << S_ATOMIC_FIX_DIS)
+#define F_ATOMIC_FIX_DIS    V_ATOMIC_FIX_DIS(1U)
+
 #define A_ULP_TX_PERR_INJECT 0x8dc4
 #define A_ULP_TX_INT_ENABLE 0x8dc8
 
@@ -20137,6 +28958,28 @@
 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
 #define A_ULP_TX_PBL_ULIMIT 0x8de0
 #define A_ULP_TX_CPL_ERR_OFFSET 0x8de4
+#define A_ULP_TX_TLS_CTL 0x8de4
+
+#define S_TLSPERREN    4
+#define V_TLSPERREN(x) ((x) << S_TLSPERREN)
+#define F_TLSPERREN    V_TLSPERREN(1U)
+
+#define S_TLSPATHCTL    3
+#define V_TLSPATHCTL(x) ((x) << S_TLSPATHCTL)
+#define F_TLSPATHCTL    V_TLSPATHCTL(1U)
+
+#define S_TLSDISABLEIFUSE    2
+#define V_TLSDISABLEIFUSE(x) ((x) << S_TLSDISABLEIFUSE)
+#define F_TLSDISABLEIFUSE    V_TLSDISABLEIFUSE(1U)
+
+#define S_TLSDISABLECFUSE    1
+#define V_TLSDISABLECFUSE(x) ((x) << S_TLSDISABLECFUSE)
+#define F_TLSDISABLECFUSE    V_TLSDISABLECFUSE(1U)
+
+#define S_TLSDISABLE    0
+#define V_TLSDISABLE(x) ((x) << S_TLSDISABLE)
+#define F_TLSDISABLE    V_TLSDISABLE(1U)
+
 #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
 #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
 #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
@@ -20292,6 +29135,17 @@
 
 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
 #define A_ULP_TX_PERR_INJECT_2 0x8e34
+
+#define S_T5_MEMSEL    1
+#define M_T5_MEMSEL    0x7U
+#define V_T5_MEMSEL(x) ((x) << S_T5_MEMSEL)
+#define G_T5_MEMSEL(x) (((x) >> S_T5_MEMSEL) & M_T5_MEMSEL)
+
+#define S_MEMSEL_ULPTX    1
+#define M_MEMSEL_ULPTX    0x1fU
+#define V_MEMSEL_ULPTX(x) ((x) << S_MEMSEL_ULPTX)
+#define G_MEMSEL_ULPTX(x) (((x) >> S_MEMSEL_ULPTX) & M_MEMSEL_ULPTX)
+
 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
 #define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38
 
@@ -20400,6 +29254,102 @@
 #define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
 #define F_T10_PI_SRAM_PERR_SET0    V_T10_PI_SRAM_PERR_SET0(1U)
 
+#define S_EDMA_IN_FIFO_PERR_SET3    31
+#define V_EDMA_IN_FIFO_PERR_SET3(x) ((x) << S_EDMA_IN_FIFO_PERR_SET3)
+#define F_EDMA_IN_FIFO_PERR_SET3    V_EDMA_IN_FIFO_PERR_SET3(1U)
+
+#define S_EDMA_IN_FIFO_PERR_SET2    30
+#define V_EDMA_IN_FIFO_PERR_SET2(x) ((x) << S_EDMA_IN_FIFO_PERR_SET2)
+#define F_EDMA_IN_FIFO_PERR_SET2    V_EDMA_IN_FIFO_PERR_SET2(1U)
+
+#define S_EDMA_IN_FIFO_PERR_SET1    29
+#define V_EDMA_IN_FIFO_PERR_SET1(x) ((x) << S_EDMA_IN_FIFO_PERR_SET1)
+#define F_EDMA_IN_FIFO_PERR_SET1    V_EDMA_IN_FIFO_PERR_SET1(1U)
+
+#define S_EDMA_IN_FIFO_PERR_SET0    28
+#define V_EDMA_IN_FIFO_PERR_SET0(x) ((x) << S_EDMA_IN_FIFO_PERR_SET0)
+#define F_EDMA_IN_FIFO_PERR_SET0    V_EDMA_IN_FIFO_PERR_SET0(1U)
+
+#define S_ALIGN_CTL_FIFO_PERR_SET3    27
+#define V_ALIGN_CTL_FIFO_PERR_SET3(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET3)
+#define F_ALIGN_CTL_FIFO_PERR_SET3    V_ALIGN_CTL_FIFO_PERR_SET3(1U)
+
+#define S_ALIGN_CTL_FIFO_PERR_SET2    26
+#define V_ALIGN_CTL_FIFO_PERR_SET2(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET2)
+#define F_ALIGN_CTL_FIFO_PERR_SET2    V_ALIGN_CTL_FIFO_PERR_SET2(1U)
+
+#define S_ALIGN_CTL_FIFO_PERR_SET1    25
+#define V_ALIGN_CTL_FIFO_PERR_SET1(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET1)
+#define F_ALIGN_CTL_FIFO_PERR_SET1    V_ALIGN_CTL_FIFO_PERR_SET1(1U)
+
+#define S_ALIGN_CTL_FIFO_PERR_SET0    24
+#define V_ALIGN_CTL_FIFO_PERR_SET0(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET0)
+#define F_ALIGN_CTL_FIFO_PERR_SET0    V_ALIGN_CTL_FIFO_PERR_SET0(1U)
+
+#define S_SGE_FIFO_PERR_SET3    23
+#define V_SGE_FIFO_PERR_SET3(x) ((x) << S_SGE_FIFO_PERR_SET3)
+#define F_SGE_FIFO_PERR_SET3    V_SGE_FIFO_PERR_SET3(1U)
+
+#define S_SGE_FIFO_PERR_SET2    22
+#define V_SGE_FIFO_PERR_SET2(x) ((x) << S_SGE_FIFO_PERR_SET2)
+#define F_SGE_FIFO_PERR_SET2    V_SGE_FIFO_PERR_SET2(1U)
+
+#define S_SGE_FIFO_PERR_SET1    21
+#define V_SGE_FIFO_PERR_SET1(x) ((x) << S_SGE_FIFO_PERR_SET1)
+#define F_SGE_FIFO_PERR_SET1    V_SGE_FIFO_PERR_SET1(1U)
+
+#define S_SGE_FIFO_PERR_SET0    20
+#define V_SGE_FIFO_PERR_SET0(x) ((x) << S_SGE_FIFO_PERR_SET0)
+#define F_SGE_FIFO_PERR_SET0    V_SGE_FIFO_PERR_SET0(1U)
+
+#define S_STAG_FIFO_PERR_SET3    19
+#define V_STAG_FIFO_PERR_SET3(x) ((x) << S_STAG_FIFO_PERR_SET3)
+#define F_STAG_FIFO_PERR_SET3    V_STAG_FIFO_PERR_SET3(1U)
+
+#define S_STAG_FIFO_PERR_SET2    18
+#define V_STAG_FIFO_PERR_SET2(x) ((x) << S_STAG_FIFO_PERR_SET2)
+#define F_STAG_FIFO_PERR_SET2    V_STAG_FIFO_PERR_SET2(1U)
+
+#define S_STAG_FIFO_PERR_SET1    17
+#define V_STAG_FIFO_PERR_SET1(x) ((x) << S_STAG_FIFO_PERR_SET1)
+#define F_STAG_FIFO_PERR_SET1    V_STAG_FIFO_PERR_SET1(1U)
+
+#define S_STAG_FIFO_PERR_SET0    16
+#define V_STAG_FIFO_PERR_SET0(x) ((x) << S_STAG_FIFO_PERR_SET0)
+#define F_STAG_FIFO_PERR_SET0    V_STAG_FIFO_PERR_SET0(1U)
+
+#define S_MAP_FIFO_PERR_SET3    15
+#define V_MAP_FIFO_PERR_SET3(x) ((x) << S_MAP_FIFO_PERR_SET3)
+#define F_MAP_FIFO_PERR_SET3    V_MAP_FIFO_PERR_SET3(1U)
+
+#define S_MAP_FIFO_PERR_SET2    14
+#define V_MAP_FIFO_PERR_SET2(x) ((x) << S_MAP_FIFO_PERR_SET2)
+#define F_MAP_FIFO_PERR_SET2    V_MAP_FIFO_PERR_SET2(1U)
+
+#define S_MAP_FIFO_PERR_SET1    13
+#define V_MAP_FIFO_PERR_SET1(x) ((x) << S_MAP_FIFO_PERR_SET1)
+#define F_MAP_FIFO_PERR_SET1    V_MAP_FIFO_PERR_SET1(1U)
+
+#define S_MAP_FIFO_PERR_SET0    12
+#define V_MAP_FIFO_PERR_SET0(x) ((x) << S_MAP_FIFO_PERR_SET0)
+#define F_MAP_FIFO_PERR_SET0    V_MAP_FIFO_PERR_SET0(1U)
+
+#define S_DMA_FIFO_PERR_SET3    11
+#define V_DMA_FIFO_PERR_SET3(x) ((x) << S_DMA_FIFO_PERR_SET3)
+#define F_DMA_FIFO_PERR_SET3    V_DMA_FIFO_PERR_SET3(1U)
+
+#define S_DMA_FIFO_PERR_SET2    10
+#define V_DMA_FIFO_PERR_SET2(x) ((x) << S_DMA_FIFO_PERR_SET2)
+#define F_DMA_FIFO_PERR_SET2    V_DMA_FIFO_PERR_SET2(1U)
+
+#define S_DMA_FIFO_PERR_SET1    9
+#define V_DMA_FIFO_PERR_SET1(x) ((x) << S_DMA_FIFO_PERR_SET1)
+#define F_DMA_FIFO_PERR_SET1    V_DMA_FIFO_PERR_SET1(1U)
+
+#define S_DMA_FIFO_PERR_SET0    8
+#define V_DMA_FIFO_PERR_SET0(x) ((x) << S_DMA_FIFO_PERR_SET0)
+#define F_DMA_FIFO_PERR_SET0    V_DMA_FIFO_PERR_SET0(1U)
+
 #define A_ULP_TX_INT_CAUSE_2 0x8e80
 #define A_ULP_TX_PERR_ENABLE_2 0x8e84
 #define A_ULP_TX_SE_CNT_ERR 0x8ea0
@@ -20525,6 +29475,27 @@
 #define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0)
 
 #define A_ULP_TX_T5_DROP_CNT 0x8eb8
+
+#define S_DROP_INVLD_MC_CH3    28
+#define M_DROP_INVLD_MC_CH3    0xfU
+#define V_DROP_INVLD_MC_CH3(x) ((x) << S_DROP_INVLD_MC_CH3)
+#define G_DROP_INVLD_MC_CH3(x) (((x) >> S_DROP_INVLD_MC_CH3) & M_DROP_INVLD_MC_CH3)
+
+#define S_DROP_INVLD_MC_CH2    24
+#define M_DROP_INVLD_MC_CH2    0xfU
+#define V_DROP_INVLD_MC_CH2(x) ((x) << S_DROP_INVLD_MC_CH2)
+#define G_DROP_INVLD_MC_CH2(x) (((x) >> S_DROP_INVLD_MC_CH2) & M_DROP_INVLD_MC_CH2)
+
+#define S_DROP_INVLD_MC_CH1    20
+#define M_DROP_INVLD_MC_CH1    0xfU
+#define V_DROP_INVLD_MC_CH1(x) ((x) << S_DROP_INVLD_MC_CH1)
+#define G_DROP_INVLD_MC_CH1(x) (((x) >> S_DROP_INVLD_MC_CH1) & M_DROP_INVLD_MC_CH1)
+
+#define S_DROP_INVLD_MC_CH0    16
+#define M_DROP_INVLD_MC_CH0    0xfU
+#define V_DROP_INVLD_MC_CH0(x) ((x) << S_DROP_INVLD_MC_CH0)
+#define G_DROP_INVLD_MC_CH0(x) (((x) >> S_DROP_INVLD_MC_CH0) & M_DROP_INVLD_MC_CH0)
+
 #define A_ULP_TX_CSU_REVISION 0x8ebc
 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
@@ -20581,6 +29552,100 @@
 #define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
 #define A_ULP_TX_ASIC_DEBUG_3 0x8f80
 #define A_ULP_TX_ASIC_DEBUG_4 0x8f84
+#define A_ULP_TX_CPL_TX_DATA_FLAGS_MASK 0x8f88
+
+#define S_BYPASS_FIRST    26
+#define V_BYPASS_FIRST(x) ((x) << S_BYPASS_FIRST)
+#define F_BYPASS_FIRST    V_BYPASS_FIRST(1U)
+
+#define S_BYPASS_MIDDLE    25
+#define V_BYPASS_MIDDLE(x) ((x) << S_BYPASS_MIDDLE)
+#define F_BYPASS_MIDDLE    V_BYPASS_MIDDLE(1U)
+
+#define S_BYPASS_LAST    24
+#define V_BYPASS_LAST(x) ((x) << S_BYPASS_LAST)
+#define F_BYPASS_LAST    V_BYPASS_LAST(1U)
+
+#define S_PUSH_FIRST    22
+#define V_PUSH_FIRST(x) ((x) << S_PUSH_FIRST)
+#define F_PUSH_FIRST    V_PUSH_FIRST(1U)
+
+#define S_PUSH_MIDDLE    21
+#define V_PUSH_MIDDLE(x) ((x) << S_PUSH_MIDDLE)
+#define F_PUSH_MIDDLE    V_PUSH_MIDDLE(1U)
+
+#define S_PUSH_LAST    20
+#define V_PUSH_LAST(x) ((x) << S_PUSH_LAST)
+#define F_PUSH_LAST    V_PUSH_LAST(1U)
+
+#define S_SAVE_FIRST    18
+#define V_SAVE_FIRST(x) ((x) << S_SAVE_FIRST)
+#define F_SAVE_FIRST    V_SAVE_FIRST(1U)
+
+#define S_SAVE_MIDDLE    17
+#define V_SAVE_MIDDLE(x) ((x) << S_SAVE_MIDDLE)
+#define F_SAVE_MIDDLE    V_SAVE_MIDDLE(1U)
+
+#define S_SAVE_LAST    16
+#define V_SAVE_LAST(x) ((x) << S_SAVE_LAST)
+#define F_SAVE_LAST    V_SAVE_LAST(1U)
+
+#define S_FLUSH_FIRST    14
+#define V_FLUSH_FIRST(x) ((x) << S_FLUSH_FIRST)
+#define F_FLUSH_FIRST    V_FLUSH_FIRST(1U)
+
+#define S_FLUSH_MIDDLE    13
+#define V_FLUSH_MIDDLE(x) ((x) << S_FLUSH_MIDDLE)
+#define F_FLUSH_MIDDLE    V_FLUSH_MIDDLE(1U)
+
+#define S_FLUSH_LAST    12
+#define V_FLUSH_LAST(x) ((x) << S_FLUSH_LAST)
+#define F_FLUSH_LAST    V_FLUSH_LAST(1U)
+
+#define S_URGENT_FIRST    10
+#define V_URGENT_FIRST(x) ((x) << S_URGENT_FIRST)
+#define F_URGENT_FIRST    V_URGENT_FIRST(1U)
+
+#define S_URGENT_MIDDLE    9
+#define V_URGENT_MIDDLE(x) ((x) << S_URGENT_MIDDLE)
+#define F_URGENT_MIDDLE    V_URGENT_MIDDLE(1U)
+
+#define S_URGENT_LAST    8
+#define V_URGENT_LAST(x) ((x) << S_URGENT_LAST)
+#define F_URGENT_LAST    V_URGENT_LAST(1U)
+
+#define S_MORE_FIRST    6
+#define V_MORE_FIRST(x) ((x) << S_MORE_FIRST)
+#define F_MORE_FIRST    V_MORE_FIRST(1U)
+
+#define S_MORE_MIDDLE    5
+#define V_MORE_MIDDLE(x) ((x) << S_MORE_MIDDLE)
+#define F_MORE_MIDDLE    V_MORE_MIDDLE(1U)
+
+#define S_MORE_LAST    4
+#define V_MORE_LAST(x) ((x) << S_MORE_LAST)
+#define F_MORE_LAST    V_MORE_LAST(1U)
+
+#define S_SHOVE_FIRST    2
+#define V_SHOVE_FIRST(x) ((x) << S_SHOVE_FIRST)
+#define F_SHOVE_FIRST    V_SHOVE_FIRST(1U)
+
+#define S_SHOVE_MIDDLE    1
+#define V_SHOVE_MIDDLE(x) ((x) << S_SHOVE_MIDDLE)
+#define F_SHOVE_MIDDLE    V_SHOVE_MIDDLE(1U)
+
+#define S_SHOVE_LAST    0
+#define V_SHOVE_LAST(x) ((x) << S_SHOVE_LAST)
+#define F_SHOVE_LAST    V_SHOVE_LAST(1U)
+
+#define A_ULP_TX_TLS_IND_CMD 0x8fb8
+
+#define S_TLS_TX_REG_OFF_ADDR    0
+#define M_TLS_TX_REG_OFF_ADDR    0x3ffU
+#define V_TLS_TX_REG_OFF_ADDR(x) ((x) << S_TLS_TX_REG_OFF_ADDR)
+#define G_TLS_TX_REG_OFF_ADDR(x) (((x) >> S_TLS_TX_REG_OFF_ADDR) & M_TLS_TX_REG_OFF_ADDR)
+
+#define A_ULP_TX_TLS_IND_DATA 0x8fbc
 
 /* registers for module PM_RX */
 #define PM_RX_BASE_ADDR 0x8fc0
@@ -21077,6 +30142,16 @@
 #define V_DUPLICATE(x) ((x) << S_DUPLICATE)
 #define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE)
 
+#define S_RX_PCMD_SRDY_STAT4    8
+#define M_RX_PCMD_SRDY_STAT4    0x3U
+#define V_RX_PCMD_SRDY_STAT4(x) ((x) << S_RX_PCMD_SRDY_STAT4)
+#define G_RX_PCMD_SRDY_STAT4(x) (((x) >> S_RX_PCMD_SRDY_STAT4) & M_RX_PCMD_SRDY_STAT4)
+
+#define S_RX_PCMD_DRDY_STAT4    6
+#define M_RX_PCMD_DRDY_STAT4    0x3U
+#define V_RX_PCMD_DRDY_STAT4(x) ((x) << S_RX_PCMD_DRDY_STAT4)
+#define G_RX_PCMD_DRDY_STAT4(x) (((x) >> S_RX_PCMD_DRDY_STAT4) & M_RX_PCMD_DRDY_STAT4)
+
 #define A_PM_RX_DBG_STAT5 0x10026
 
 #define S_RX_ATLST_1_PCMD_CH1    29
@@ -21087,6 +30162,16 @@
 #define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0)
 #define F_RX_ATLST_1_PCMD_CH0    V_RX_ATLST_1_PCMD_CH0(1U)
 
+#define S_T5_RX_PCMD_DRDY    26
+#define M_T5_RX_PCMD_DRDY    0x3U
+#define V_T5_RX_PCMD_DRDY(x) ((x) << S_T5_RX_PCMD_DRDY)
+#define G_T5_RX_PCMD_DRDY(x) (((x) >> S_T5_RX_PCMD_DRDY) & M_T5_RX_PCMD_DRDY)
+
+#define S_T5_RX_PCMD_SRDY    24
+#define M_T5_RX_PCMD_SRDY    0x3U
+#define V_T5_RX_PCMD_SRDY(x) ((x) << S_T5_RX_PCMD_SRDY)
+#define G_T5_RX_PCMD_SRDY(x) (((x) >> S_T5_RX_PCMD_SRDY) & M_T5_RX_PCMD_SRDY)
+
 #define S_RX_ISPI_TXVALID    20
 #define M_RX_ISPI_TXVALID    0xfU
 #define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID)
@@ -21127,6 +30212,16 @@
 #define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL)
 #define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL)
 
+#define S_T6_RX_PCMD_DRDY    26
+#define M_T6_RX_PCMD_DRDY    0x3U
+#define V_T6_RX_PCMD_DRDY(x) ((x) << S_T6_RX_PCMD_DRDY)
+#define G_T6_RX_PCMD_DRDY(x) (((x) >> S_T6_RX_PCMD_DRDY) & M_T6_RX_PCMD_DRDY)
+
+#define S_T6_RX_PCMD_SRDY    24
+#define M_T6_RX_PCMD_SRDY    0x3U
+#define V_T6_RX_PCMD_SRDY(x) ((x) << S_T6_RX_PCMD_SRDY)
+#define G_T6_RX_PCMD_SRDY(x) (((x) >> S_T6_RX_PCMD_SRDY) & M_T6_RX_PCMD_SRDY)
+
 #define A_PM_RX_DBG_STAT6 0x10027
 
 #define S_RX_M_INTRNL_FIFO_CNT    4
@@ -21150,6 +30245,23 @@
 #define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY)
 #define F_RX_M_REQDATARDY    V_RX_M_REQDATARDY(1U)
 
+#define S_T6_RX_M_INTRNL_FIFO_CNT    7
+#define M_T6_RX_M_INTRNL_FIFO_CNT    0x3U
+#define V_T6_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_T6_RX_M_INTRNL_FIFO_CNT)
+#define G_T6_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_T6_RX_M_INTRNL_FIFO_CNT) & M_T6_RX_M_INTRNL_FIFO_CNT)
+
+#define S_RX_M_RSPVLD    6
+#define V_RX_M_RSPVLD(x) ((x) << S_RX_M_RSPVLD)
+#define F_RX_M_RSPVLD    V_RX_M_RSPVLD(1U)
+
+#define S_RX_M_RSPRDY    5
+#define V_RX_M_RSPRDY(x) ((x) << S_RX_M_RSPRDY)
+#define F_RX_M_RSPRDY    V_RX_M_RSPRDY(1U)
+
+#define S_RX_M_REQADDRVLD    4
+#define V_RX_M_REQADDRVLD(x) ((x) << S_RX_M_REQADDRVLD)
+#define F_RX_M_REQADDRVLD    V_RX_M_REQADDRVLD(1U)
+
 #define A_PM_RX_DBG_STAT7 0x10028
 
 #define S_RX_PCMD1_FREE_CNT    7
@@ -21531,6 +30643,14 @@
 #define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2)
 #define F_OSPI_OVERFLOW2    V_OSPI_OVERFLOW2(1U)
 
+#define S_T5_OSPI_OVERFLOW1    5
+#define V_T5_OSPI_OVERFLOW1(x) ((x) << S_T5_OSPI_OVERFLOW1)
+#define F_T5_OSPI_OVERFLOW1    V_T5_OSPI_OVERFLOW1(1U)
+
+#define S_T5_OSPI_OVERFLOW0    4
+#define V_T5_OSPI_OVERFLOW0(x) ((x) << S_T5_OSPI_OVERFLOW0)
+#define F_T5_OSPI_OVERFLOW0    V_T5_OSPI_OVERFLOW0(1U)
+
 #define S_M_INTFPERREN    3
 #define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN)
 #define F_M_INTFPERREN    V_M_INTFPERREN(1U)
@@ -21547,6 +30667,22 @@
 #define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN)
 #define F_SDC_ERR_EN    V_SDC_ERR_EN(1U)
 
+#define S_OSPI_OVERFLOW3_T5    7
+#define V_OSPI_OVERFLOW3_T5(x) ((x) << S_OSPI_OVERFLOW3_T5)
+#define F_OSPI_OVERFLOW3_T5    V_OSPI_OVERFLOW3_T5(1U)
+
+#define S_OSPI_OVERFLOW2_T5    6
+#define V_OSPI_OVERFLOW2_T5(x) ((x) << S_OSPI_OVERFLOW2_T5)
+#define F_OSPI_OVERFLOW2_T5    V_OSPI_OVERFLOW2_T5(1U)
+
+#define S_OSPI_OVERFLOW1_T5    5
+#define V_OSPI_OVERFLOW1_T5(x) ((x) << S_OSPI_OVERFLOW1_T5)
+#define F_OSPI_OVERFLOW1_T5    V_OSPI_OVERFLOW1_T5(1U)
+
+#define S_OSPI_OVERFLOW0_T5    4
+#define V_OSPI_OVERFLOW0_T5(x) ((x) << S_OSPI_OVERFLOW0_T5)
+#define F_OSPI_OVERFLOW0_T5    V_OSPI_OVERFLOW0_T5(1U)
+
 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023
 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024
 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025
@@ -21570,34 +30706,38 @@
 #define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b
 #define A_PM_TX_DBG_STAT0 0x1002c
 
-#define S_RD_I_BUSY    28
+#define S_RD_I_BUSY    29
 #define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY)
 #define F_RD_I_BUSY    V_RD_I_BUSY(1U)
 
-#define S_WR_O_ONLY    27
-#define V_WR_O_ONLY(x) ((x) << S_WR_O_ONLY)
-#define F_WR_O_ONLY    V_WR_O_ONLY(1U)
+#define S_WR_O_BUSY    28
+#define V_WR_O_BUSY(x) ((x) << S_WR_O_BUSY)
+#define F_WR_O_BUSY    V_WR_O_BUSY(1U)
 
-#define S_M_TO_BUSY    26
-#define V_M_TO_BUSY(x) ((x) << S_M_TO_BUSY)
-#define F_M_TO_BUSY    V_M_TO_BUSY(1U)
+#define S_M_TO_O_BUSY    27
+#define V_M_TO_O_BUSY(x) ((x) << S_M_TO_O_BUSY)
+#define F_M_TO_O_BUSY    V_M_TO_O_BUSY(1U)
 
-#define S_I_TO_M_BUSY    25
+#define S_I_TO_M_BUSY    26
 #define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY)
 #define F_I_TO_M_BUSY    V_I_TO_M_BUSY(1U)
 
-#define S_PCMD_FB_ONLY    24
+#define S_PCMD_FB_ONLY    25
 #define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY)
 #define F_PCMD_FB_ONLY    V_PCMD_FB_ONLY(1U)
 
-#define S_PCMD_MEM    23
+#define S_PCMD_MEM    24
 #define V_PCMD_MEM(x) ((x) << S_PCMD_MEM)
 #define F_PCMD_MEM    V_PCMD_MEM(1U)
 
-#define S_PCMD_BYPASS    22
+#define S_PCMD_BYPASS    23
 #define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS)
 #define F_PCMD_BYPASS    V_PCMD_BYPASS(1U)
 
+#define S_PCMD_EOP2    22
+#define V_PCMD_EOP2(x) ((x) << S_PCMD_EOP2)
+#define F_PCMD_EOP2    V_PCMD_EOP2(1U)
+
 #define S_PCMD_EOP    21
 #define V_PCMD_EOP(x) ((x) << S_PCMD_EOP)
 #define F_PCMD_EOP    V_PCMD_EOP(1U)
@@ -21616,6 +30756,34 @@
 #define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN)
 #define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN)
 
+#define S_T6_RD_I_BUSY    28
+#define V_T6_RD_I_BUSY(x) ((x) << S_T6_RD_I_BUSY)
+#define F_T6_RD_I_BUSY    V_T6_RD_I_BUSY(1U)
+
+#define S_T6_WR_O_BUSY    27
+#define V_T6_WR_O_BUSY(x) ((x) << S_T6_WR_O_BUSY)
+#define F_T6_WR_O_BUSY    V_T6_WR_O_BUSY(1U)
+
+#define S_T6_M_TO_O_BUSY    26
+#define V_T6_M_TO_O_BUSY(x) ((x) << S_T6_M_TO_O_BUSY)
+#define F_T6_M_TO_O_BUSY    V_T6_M_TO_O_BUSY(1U)
+
+#define S_T6_I_TO_M_BUSY    25
+#define V_T6_I_TO_M_BUSY(x) ((x) << S_T6_I_TO_M_BUSY)
+#define F_T6_I_TO_M_BUSY    V_T6_I_TO_M_BUSY(1U)
+
+#define S_T6_PCMD_FB_ONLY    24
+#define V_T6_PCMD_FB_ONLY(x) ((x) << S_T6_PCMD_FB_ONLY)
+#define F_T6_PCMD_FB_ONLY    V_T6_PCMD_FB_ONLY(1U)
+
+#define S_T6_PCMD_MEM    23
+#define V_T6_PCMD_MEM(x) ((x) << S_T6_PCMD_MEM)
+#define F_T6_PCMD_MEM    V_T6_PCMD_MEM(1U)
+
+#define S_T6_PCMD_BYPASS    22
+#define V_T6_PCMD_BYPASS(x) ((x) << S_T6_PCMD_BYPASS)
+#define F_T6_PCMD_BYPASS    V_T6_PCMD_BYPASS(1U)
+
 #define A_PM_TX_DBG_STAT1 0x1002d
 
 #define S_PCMD_MEM0    31
@@ -21950,6 +31118,33 @@
 #define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY)
 #define F_M_REQDATARDY    V_M_REQDATARDY(1U)
 
+#define S_T6_MC_RSP_FIFO_CNT    27
+#define M_T6_MC_RSP_FIFO_CNT    0x3U
+#define V_T6_MC_RSP_FIFO_CNT(x) ((x) << S_T6_MC_RSP_FIFO_CNT)
+#define G_T6_MC_RSP_FIFO_CNT(x) (((x) >> S_T6_MC_RSP_FIFO_CNT) & M_T6_MC_RSP_FIFO_CNT)
+
+#define S_T6_PCMD_FREE_CNT0    17
+#define M_T6_PCMD_FREE_CNT0    0x3ffU
+#define V_T6_PCMD_FREE_CNT0(x) ((x) << S_T6_PCMD_FREE_CNT0)
+#define G_T6_PCMD_FREE_CNT0(x) (((x) >> S_T6_PCMD_FREE_CNT0) & M_T6_PCMD_FREE_CNT0)
+
+#define S_T6_PCMD_FREE_CNT1    7
+#define M_T6_PCMD_FREE_CNT1    0x3ffU
+#define V_T6_PCMD_FREE_CNT1(x) ((x) << S_T6_PCMD_FREE_CNT1)
+#define G_T6_PCMD_FREE_CNT1(x) (((x) >> S_T6_PCMD_FREE_CNT1) & M_T6_PCMD_FREE_CNT1)
+
+#define S_M_RSPVLD    6
+#define V_M_RSPVLD(x) ((x) << S_M_RSPVLD)
+#define F_M_RSPVLD    V_M_RSPVLD(1U)
+
+#define S_M_RSPRDY    5
+#define V_M_RSPRDY(x) ((x) << S_M_RSPRDY)
+#define F_M_RSPRDY    V_M_RSPRDY(1U)
+
+#define S_M_REQADDRVLD    4
+#define V_M_REQADDRVLD(x) ((x) << S_M_REQADDRVLD)
+#define F_M_REQADDRVLD    V_M_REQADDRVLD(1U)
+
 #define A_PM_TX_DBG_STAT9 0x10035
 
 #define S_PCMD_FREE_CNT2    10
@@ -22092,6 +31287,16 @@
 #define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0)
 #define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0)
 
+#define S_T6_BUNDLE_LEN_SRDY    24
+#define M_T6_BUNDLE_LEN_SRDY    0x3U
+#define V_T6_BUNDLE_LEN_SRDY(x) ((x) << S_T6_BUNDLE_LEN_SRDY)
+#define G_T6_BUNDLE_LEN_SRDY(x) (((x) >> S_T6_BUNDLE_LEN_SRDY) & M_T6_BUNDLE_LEN_SRDY)
+
+#define S_T6_BUNDLE_LEN1    12
+#define M_T6_BUNDLE_LEN1    0xfffU
+#define V_T6_BUNDLE_LEN1(x) ((x) << S_T6_BUNDLE_LEN1)
+#define G_T6_BUNDLE_LEN1(x) (((x) >> S_T6_BUNDLE_LEN1) & M_T6_BUNDLE_LEN1)
+
 #define A_PM_TX_DBG_STAT16 0x1003c
 
 #define S_BUNDLE_LEN3    16
@@ -22428,6 +31633,22 @@
 #define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP)
 #define F_PTP_FWD_UP    V_PTP_FWD_UP(1U)
 
+#define S_HASH_PRIO_SEL_LPBK    25
+#define V_HASH_PRIO_SEL_LPBK(x) ((x) << S_HASH_PRIO_SEL_LPBK)
+#define F_HASH_PRIO_SEL_LPBK    V_HASH_PRIO_SEL_LPBK(1U)
+
+#define S_HASH_PRIO_SEL_MAC    24
+#define V_HASH_PRIO_SEL_MAC(x) ((x) << S_HASH_PRIO_SEL_MAC)
+#define F_HASH_PRIO_SEL_MAC    V_HASH_PRIO_SEL_MAC(1U)
+
+#define S_HASH_EN_LPBK    23
+#define V_HASH_EN_LPBK(x) ((x) << S_HASH_EN_LPBK)
+#define F_HASH_EN_LPBK    V_HASH_EN_LPBK(1U)
+
+#define S_HASH_EN_MAC    22
+#define V_HASH_EN_MAC(x) ((x) << S_HASH_EN_MAC)
+#define F_HASH_EN_MAC    V_HASH_EN_MAC(1U)
+
 #define A_MPS_PORT_RX_MTU 0x104
 #define A_MPS_PORT_RX_PF_MAP 0x108
 #define A_MPS_PORT_RX_VF_MAP0 0x10c
@@ -22497,9 +31718,179 @@
 #define V_FIXED_VF(x) ((x) << S_FIXED_VF)
 #define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF)
 
+#define S_T6_FIXED_PFVF_MAC    14
+#define V_T6_FIXED_PFVF_MAC(x) ((x) << S_T6_FIXED_PFVF_MAC)
+#define F_T6_FIXED_PFVF_MAC    V_T6_FIXED_PFVF_MAC(1U)
+
+#define S_T6_FIXED_PFVF_LPBK    13
+#define V_T6_FIXED_PFVF_LPBK(x) ((x) << S_T6_FIXED_PFVF_LPBK)
+#define F_T6_FIXED_PFVF_LPBK    V_T6_FIXED_PFVF_LPBK(1U)
+
+#define S_T6_FIXED_PFVF_LPBK_OV    12
+#define V_T6_FIXED_PFVF_LPBK_OV(x) ((x) << S_T6_FIXED_PFVF_LPBK_OV)
+#define F_T6_FIXED_PFVF_LPBK_OV    V_T6_FIXED_PFVF_LPBK_OV(1U)
+
+#define S_T6_FIXED_PF    9
+#define M_T6_FIXED_PF    0x7U
+#define V_T6_FIXED_PF(x) ((x) << S_T6_FIXED_PF)
+#define G_T6_FIXED_PF(x) (((x) >> S_T6_FIXED_PF) & M_T6_FIXED_PF)
+
+#define S_T6_FIXED_VF_VLD    8
+#define V_T6_FIXED_VF_VLD(x) ((x) << S_T6_FIXED_VF_VLD)
+#define F_T6_FIXED_VF_VLD    V_T6_FIXED_VF_VLD(1U)
+
+#define S_T6_FIXED_VF    0
+#define M_T6_FIXED_VF    0xffU
+#define V_T6_FIXED_VF(x) ((x) << S_T6_FIXED_VF)
+#define G_T6_FIXED_VF(x) (((x) >> S_T6_FIXED_VF) & M_T6_FIXED_VF)
+
 #define A_MPS_PORT_RX_SPARE 0x13c
 #define A_MPS_PORT_RX_PTP_RSS_HASH 0x140
 #define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144
+#define A_MPS_PORT_RX_TS_VLD 0x148
+
+#define S_TS_VLD    0
+#define M_TS_VLD    0x3U
+#define V_TS_VLD(x) ((x) << S_TS_VLD)
+#define G_TS_VLD(x) (((x) >> S_TS_VLD) & M_TS_VLD)
+
+#define A_MPS_PORT_RX_TNL_LKP_INNER_SEL 0x14c
+
+#define S_LKP_SEL    0
+#define V_LKP_SEL(x) ((x) << S_LKP_SEL)
+#define F_LKP_SEL    V_LKP_SEL(1U)
+
+#define A_MPS_PORT_RX_VF_MAP4 0x150
+#define A_MPS_PORT_RX_VF_MAP5 0x154
+#define A_MPS_PORT_RX_VF_MAP6 0x158
+#define A_MPS_PORT_RX_VF_MAP7 0x15c
+#define A_MPS_PORT_RX_PRS_DEBUG_FLAG_MAC 0x160
+
+#define S_OUTER_IPV4_N_INNER_IPV4    31
+#define V_OUTER_IPV4_N_INNER_IPV4(x) ((x) << S_OUTER_IPV4_N_INNER_IPV4)
+#define F_OUTER_IPV4_N_INNER_IPV4    V_OUTER_IPV4_N_INNER_IPV4(1U)
+
+#define S_OUTER_IPV4_N_INNER_IPV6    30
+#define V_OUTER_IPV4_N_INNER_IPV6(x) ((x) << S_OUTER_IPV4_N_INNER_IPV6)
+#define F_OUTER_IPV4_N_INNER_IPV6    V_OUTER_IPV4_N_INNER_IPV6(1U)
+
+#define S_OUTER_IPV6_N_INNER_IPV4    29
+#define V_OUTER_IPV6_N_INNER_IPV4(x) ((x) << S_OUTER_IPV6_N_INNER_IPV4)
+#define F_OUTER_IPV6_N_INNER_IPV4    V_OUTER_IPV6_N_INNER_IPV4(1U)
+
+#define S_OUTER_IPV6_N_INNER_IPV6    28
+#define V_OUTER_IPV6_N_INNER_IPV6(x) ((x) << S_OUTER_IPV6_N_INNER_IPV6)
+#define F_OUTER_IPV6_N_INNER_IPV6    V_OUTER_IPV6_N_INNER_IPV6(1U)
+
+#define S_OUTER_IPV4_N_VLAN_NVGRE    27
+#define V_OUTER_IPV4_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_VLAN_NVGRE)
+#define F_OUTER_IPV4_N_VLAN_NVGRE    V_OUTER_IPV4_N_VLAN_NVGRE(1U)
+
+#define S_OUTER_IPV6_N_VLAN_NVGRE    26
+#define V_OUTER_IPV6_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_VLAN_NVGRE)
+#define F_OUTER_IPV6_N_VLAN_NVGRE    V_OUTER_IPV6_N_VLAN_NVGRE(1U)
+
+#define S_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE    25
+#define V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE)
+#define F_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE    V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(1U)
+
+#define S_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE    24
+#define V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE)
+#define F_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE    V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(1U)
+
+#define S_OUTER_IPV4_N_VLAN_GRE    23
+#define V_OUTER_IPV4_N_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_VLAN_GRE)
+#define F_OUTER_IPV4_N_VLAN_GRE    V_OUTER_IPV4_N_VLAN_GRE(1U)
+
+#define S_OUTER_IPV6_N_VLAN_GRE    22
+#define V_OUTER_IPV6_N_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_VLAN_GRE)
+#define F_OUTER_IPV6_N_VLAN_GRE    V_OUTER_IPV6_N_VLAN_GRE(1U)
+
+#define S_OUTER_IPV4_N_DOUBLE_VLAN_GRE    21
+#define V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GRE)
+#define F_OUTER_IPV4_N_DOUBLE_VLAN_GRE    V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(1U)
+
+#define S_OUTER_IPV6_N_DOUBLE_VLAN_GRE    20
+#define V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GRE)
+#define F_OUTER_IPV6_N_DOUBLE_VLAN_GRE    V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(1U)
+
+#define S_OUTER_IPV4_N_VLAN_VXLAN    19
+#define V_OUTER_IPV4_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_VLAN_VXLAN)
+#define F_OUTER_IPV4_N_VLAN_VXLAN    V_OUTER_IPV4_N_VLAN_VXLAN(1U)
+
+#define S_OUTER_IPV6_N_VLAN_VXLAN    18
+#define V_OUTER_IPV6_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_VLAN_VXLAN)
+#define F_OUTER_IPV6_N_VLAN_VXLAN    V_OUTER_IPV6_N_VLAN_VXLAN(1U)
+
+#define S_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN    17
+#define V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN)
+#define F_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN    V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(1U)
+
+#define S_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN    16
+#define V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN)
+#define F_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN    V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(1U)
+
+#define S_OUTER_IPV4_N_VLAN_GENEVE    15
+#define V_OUTER_IPV4_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_VLAN_GENEVE)
+#define F_OUTER_IPV4_N_VLAN_GENEVE    V_OUTER_IPV4_N_VLAN_GENEVE(1U)
+
+#define S_OUTER_IPV6_N_VLAN_GENEVE    14
+#define V_OUTER_IPV6_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_VLAN_GENEVE)
+#define F_OUTER_IPV6_N_VLAN_GENEVE    V_OUTER_IPV6_N_VLAN_GENEVE(1U)
+
+#define S_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE    13
+#define V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE)
+#define F_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE    V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(1U)
+
+#define S_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE    12
+#define V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE)
+#define F_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE    V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(1U)
+
+#define S_ERR_TNL_HDR_LEN    11
+#define V_ERR_TNL_HDR_LEN(x) ((x) << S_ERR_TNL_HDR_LEN)
+#define F_ERR_TNL_HDR_LEN    V_ERR_TNL_HDR_LEN(1U)
+
+#define S_NON_RUNT_FRAME    10
+#define V_NON_RUNT_FRAME(x) ((x) << S_NON_RUNT_FRAME)
+#define F_NON_RUNT_FRAME    V_NON_RUNT_FRAME(1U)
+
+#define S_INNER_VLAN_VLD    9
+#define V_INNER_VLAN_VLD(x) ((x) << S_INNER_VLAN_VLD)
+#define F_INNER_VLAN_VLD    V_INNER_VLAN_VLD(1U)
+
+#define S_ERR_IP_PAYLOAD_LEN    8
+#define V_ERR_IP_PAYLOAD_LEN(x) ((x) << S_ERR_IP_PAYLOAD_LEN)
+#define F_ERR_IP_PAYLOAD_LEN    V_ERR_IP_PAYLOAD_LEN(1U)
+
+#define S_ERR_UDP_PAYLOAD_LEN    7
+#define V_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_ERR_UDP_PAYLOAD_LEN)
+#define F_ERR_UDP_PAYLOAD_LEN    V_ERR_UDP_PAYLOAD_LEN(1U)
+
+#define A_MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK 0x164
+
+#define S_T6_INNER_VLAN_VLD    10
+#define V_T6_INNER_VLAN_VLD(x) ((x) << S_T6_INNER_VLAN_VLD)
+#define F_T6_INNER_VLAN_VLD    V_T6_INNER_VLAN_VLD(1U)
+
+#define S_T6_ERR_IP_PAYLOAD_LEN    9
+#define V_T6_ERR_IP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_IP_PAYLOAD_LEN)
+#define F_T6_ERR_IP_PAYLOAD_LEN    V_T6_ERR_IP_PAYLOAD_LEN(1U)
+
+#define S_T6_ERR_UDP_PAYLOAD_LEN    8
+#define V_T6_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_UDP_PAYLOAD_LEN)
+#define F_T6_ERR_UDP_PAYLOAD_LEN    V_T6_ERR_UDP_PAYLOAD_LEN(1U)
+
+#define A_MPS_PORT_RX_REPL_VECT_SEL 0x168
+
+#define S_DIS_REPL_VECT_SEL    4
+#define V_DIS_REPL_VECT_SEL(x) ((x) << S_DIS_REPL_VECT_SEL)
+#define F_DIS_REPL_VECT_SEL    V_DIS_REPL_VECT_SEL(1U)
+
+#define S_REPL_VECT_SEL    0
+#define M_REPL_VECT_SEL    0xfU
+#define V_REPL_VECT_SEL(x) ((x) << S_REPL_VECT_SEL)
+#define G_REPL_VECT_SEL(x) (((x) >> S_REPL_VECT_SEL) & M_REPL_VECT_SEL)
+
 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
 
 #define S_CREDIT    0
@@ -22532,6 +31923,16 @@
 #define V_MAXPKTCNT(x) ((x) << S_MAXPKTCNT)
 #define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT)
 
+#define S_OUT_TH    22
+#define M_OUT_TH    0xffU
+#define V_OUT_TH(x) ((x) << S_OUT_TH)
+#define G_OUT_TH(x) (((x) >> S_OUT_TH) & M_OUT_TH)
+
+#define S_IN_TH    14
+#define M_IN_TH    0xffU
+#define V_IN_TH(x) ((x) << S_IN_TH)
+#define G_IN_TH(x) (((x) >> S_IN_TH) & M_IN_TH)
+
 #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
 
 #define S_FPGAPAUSEEN    0
@@ -22588,6 +31989,50 @@
 #define V_VF(x) ((x) << S_VF)
 #define G_VF(x) (((x) >> S_VF) & M_VF)
 
+#define S_DISENCAPOUTERRPLCT    23
+#define V_DISENCAPOUTERRPLCT(x) ((x) << S_DISENCAPOUTERRPLCT)
+#define F_DISENCAPOUTERRPLCT    V_DISENCAPOUTERRPLCT(1U)
+
+#define S_DISENCAP    22
+#define V_DISENCAP(x) ((x) << S_DISENCAP)
+#define F_DISENCAP    V_DISENCAP(1U)
+
+#define S_T6_VALID    21
+#define V_T6_VALID(x) ((x) << S_T6_VALID)
+#define F_T6_VALID    V_T6_VALID(1U)
+
+#define S_T6_HASHPORTMAP    17
+#define M_T6_HASHPORTMAP    0xfU
+#define V_T6_HASHPORTMAP(x) ((x) << S_T6_HASHPORTMAP)
+#define G_T6_HASHPORTMAP(x) (((x) >> S_T6_HASHPORTMAP) & M_T6_HASHPORTMAP)
+
+#define S_T6_MULTILISTEN    16
+#define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
+#define F_T6_MULTILISTEN    V_T6_MULTILISTEN(1U)
+
+#define S_T6_PRIORITY    13
+#define M_T6_PRIORITY    0x7U
+#define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
+#define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
+
+#define S_T6_REPLICATE    12
+#define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
+#define F_T6_REPLICATE    V_T6_REPLICATE(1U)
+
+#define S_T6_PF    9
+#define M_T6_PF    0x7U
+#define V_T6_PF(x) ((x) << S_T6_PF)
+#define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
+
+#define S_T6_VF_VALID    8
+#define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
+#define F_T6_VF_VALID    V_T6_VF_VALID(1U)
+
+#define S_T6_VF    0
+#define M_T6_VF    0xffU
+#define V_T6_VF(x) ((x) << S_T6_VF)
+#define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
+
 #define A_MPS_PF_CTL 0x2c0
 
 #define S_TXEN    1
@@ -22634,6 +32079,33 @@
 #define V_PROMISCEN(x) ((x) << S_PROMISCEN)
 #define F_PROMISCEN    V_PROMISCEN(1U)
 
+#define S_T6_MULTILISTEN    16
+#define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
+#define F_T6_MULTILISTEN    V_T6_MULTILISTEN(1U)
+
+#define S_T6_PRIORITY    13
+#define M_T6_PRIORITY    0x7U
+#define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
+#define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
+
+#define S_T6_REPLICATE    12
+#define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
+#define F_T6_REPLICATE    V_T6_REPLICATE(1U)
+
+#define S_T6_PF    9
+#define M_T6_PF    0x7U
+#define V_T6_PF(x) ((x) << S_T6_PF)
+#define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
+
+#define S_T6_VF_VALID    8
+#define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
+#define F_T6_VF_VALID    V_T6_VF_VALID(1U)
+
+#define S_T6_VF    0
+#define M_T6_VF    0xffU
+#define V_T6_VF(x) ((x) << S_T6_VF)
+#define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
+
 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
@@ -22647,6 +32119,10 @@
 #define V_BMC_VLD(x) ((x) << S_BMC_VLD)
 #define F_BMC_VLD    V_BMC_VLD(1U)
 
+#define S_MATCHALL    18
+#define V_MATCHALL(x) ((x) << S_MATCHALL)
+#define F_MATCHALL    V_MATCHALL(1U)
+
 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
 #define A_MPS_PORT_CLS_BMC_VLAN 0x314
 
@@ -22710,7 +32186,24 @@
 #define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL)
 
 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
+#define A_MPS_PORT_CLS_NCSI_ETH_TYPE 0x31c
+
+#define S_ETHTYPE2    0
+#define M_ETHTYPE2    0xffffU
+#define V_ETHTYPE2(x) ((x) << S_ETHTYPE2)
+#define G_ETHTYPE2(x) (((x) >> S_ETHTYPE2) & M_ETHTYPE2)
+
 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
+#define A_MPS_PORT_CLS_NCSI_ETH_TYPE_EN 0x320
+
+#define S_EN1    1
+#define V_EN1(x) ((x) << S_EN1)
+#define F_EN1    V_EN1(1U)
+
+#define S_EN2    0
+#define V_EN2(x) ((x) << S_EN2)
+#define F_EN2    V_EN2(1U)
+
 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
@@ -22886,6 +32379,19 @@
 #define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
 #define F_LPBKCRDTCTRL    V_LPBKCRDTCTRL(1U)
 
+#define S_TX_PORT_STATS_MODE    8
+#define V_TX_PORT_STATS_MODE(x) ((x) << S_TX_PORT_STATS_MODE)
+#define F_TX_PORT_STATS_MODE    V_TX_PORT_STATS_MODE(1U)
+
+#define S_T5MODE    7
+#define V_T5MODE(x) ((x) << S_T5MODE)
+#define F_T5MODE    V_T5MODE(1U)
+
+#define S_SPEEDMODE    5
+#define M_SPEEDMODE    0x3U
+#define V_SPEEDMODE(x) ((x) << S_SPEEDMODE)
+#define G_SPEEDMODE(x) (((x) >> S_SPEEDMODE) & M_SPEEDMODE)
+
 #define A_MPS_INT_ENABLE 0x9004
 
 #define S_STATINTENB    5
@@ -23111,6 +32617,33 @@
 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4
 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8
 #define A_MPS_BUILD_REVISION 0x90fc
+#define A_MPS_VF_TX_CTL_159_128 0x9100
+#define A_MPS_VF_TX_CTL_191_160 0x9104
+#define A_MPS_VF_TX_CTL_223_192 0x9108
+#define A_MPS_VF_TX_CTL_255_224 0x910c
+#define A_MPS_VF_RX_CTL_159_128 0x9110
+#define A_MPS_VF_RX_CTL_191_160 0x9114
+#define A_MPS_VF_RX_CTL_223_192 0x9118
+#define A_MPS_VF_RX_CTL_255_224 0x911c
+#define A_MPS_FPGA_BIST_CFG_P0 0x9120
+
+#define S_ADDRMASK    16
+#define M_ADDRMASK    0xffffU
+#define V_ADDRMASK(x) ((x) << S_ADDRMASK)
+#define G_ADDRMASK(x) (((x) >> S_ADDRMASK) & M_ADDRMASK)
+
+#define S_T6_BASEADDR    0
+#define M_T6_BASEADDR    0xffffU
+#define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR)
+#define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
+
+#define A_MPS_FPGA_BIST_CFG_P1 0x9124
+
+#define S_T6_BASEADDR    0
+#define M_T6_BASEADDR    0xffffU
+#define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR)
+#define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
+
 #define A_MPS_TX_PRTY_SEL 0x9400
 
 #define S_CH4_PRTY    20
@@ -23186,6 +32719,7 @@
 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
 
 #define A_MPS_TX_INT_CAUSE 0x9408
+#define A_MPS_TX_NCSI2MPS_CNT 0x940c
 #define A_MPS_TX_PERR_ENABLE 0x9410
 #define A_MPS_TX_PERR_INJECT 0x9414
 
@@ -23340,6 +32874,50 @@
 #define V_DATACH0(x) ((x) << S_DATACH0)
 #define G_DATACH0(x) (((x) >> S_DATACH0) & M_DATACH0)
 
+#define S_T5_SIZECH1    26
+#define M_T5_SIZECH1    0xfU
+#define V_T5_SIZECH1(x) ((x) << S_T5_SIZECH1)
+#define G_T5_SIZECH1(x) (((x) >> S_T5_SIZECH1) & M_T5_SIZECH1)
+
+#define S_T5_ERRCH1    25
+#define V_T5_ERRCH1(x) ((x) << S_T5_ERRCH1)
+#define F_T5_ERRCH1    V_T5_ERRCH1(1U)
+
+#define S_T5_FULLCH1    24
+#define V_T5_FULLCH1(x) ((x) << S_T5_FULLCH1)
+#define F_T5_FULLCH1    V_T5_FULLCH1(1U)
+
+#define S_T5_VALIDCH1    23
+#define V_T5_VALIDCH1(x) ((x) << S_T5_VALIDCH1)
+#define F_T5_VALIDCH1    V_T5_VALIDCH1(1U)
+
+#define S_T5_DATACH1    16
+#define M_T5_DATACH1    0x7fU
+#define V_T5_DATACH1(x) ((x) << S_T5_DATACH1)
+#define G_T5_DATACH1(x) (((x) >> S_T5_DATACH1) & M_T5_DATACH1)
+
+#define S_T5_SIZECH0    10
+#define M_T5_SIZECH0    0xfU
+#define V_T5_SIZECH0(x) ((x) << S_T5_SIZECH0)
+#define G_T5_SIZECH0(x) (((x) >> S_T5_SIZECH0) & M_T5_SIZECH0)
+
+#define S_T5_ERRCH0    9
+#define V_T5_ERRCH0(x) ((x) << S_T5_ERRCH0)
+#define F_T5_ERRCH0    V_T5_ERRCH0(1U)
+
+#define S_T5_FULLCH0    8
+#define V_T5_FULLCH0(x) ((x) << S_T5_FULLCH0)
+#define F_T5_FULLCH0    V_T5_FULLCH0(1U)
+
+#define S_T5_VALIDCH0    7
+#define V_T5_VALIDCH0(x) ((x) << S_T5_VALIDCH0)
+#define F_T5_VALIDCH0    V_T5_VALIDCH0(1U)
+
+#define S_T5_DATACH0    0
+#define M_T5_DATACH0    0x7fU
+#define V_T5_DATACH0(x) ((x) << S_T5_DATACH0)
+#define G_T5_DATACH0(x) (((x) >> S_T5_DATACH0) & M_T5_DATACH0)
+
 #define A_MPS_TX_DEBUG_REG_TP2TX_32 0x9448
 
 #define S_SOPCH3    31
@@ -23402,6 +32980,50 @@
 #define V_DATACH2(x) ((x) << S_DATACH2)
 #define G_DATACH2(x) (((x) >> S_DATACH2) & M_DATACH2)
 
+#define S_T5_SIZECH3    26
+#define M_T5_SIZECH3    0xfU
+#define V_T5_SIZECH3(x) ((x) << S_T5_SIZECH3)
+#define G_T5_SIZECH3(x) (((x) >> S_T5_SIZECH3) & M_T5_SIZECH3)
+
+#define S_T5_ERRCH3    25
+#define V_T5_ERRCH3(x) ((x) << S_T5_ERRCH3)
+#define F_T5_ERRCH3    V_T5_ERRCH3(1U)
+
+#define S_T5_FULLCH3    24
+#define V_T5_FULLCH3(x) ((x) << S_T5_FULLCH3)
+#define F_T5_FULLCH3    V_T5_FULLCH3(1U)
+
+#define S_T5_VALIDCH3    23
+#define V_T5_VALIDCH3(x) ((x) << S_T5_VALIDCH3)
+#define F_T5_VALIDCH3    V_T5_VALIDCH3(1U)
+
+#define S_T5_DATACH3    16
+#define M_T5_DATACH3    0x7fU
+#define V_T5_DATACH3(x) ((x) << S_T5_DATACH3)
+#define G_T5_DATACH3(x) (((x) >> S_T5_DATACH3) & M_T5_DATACH3)
+
+#define S_T5_SIZECH2    10
+#define M_T5_SIZECH2    0xfU
+#define V_T5_SIZECH2(x) ((x) << S_T5_SIZECH2)
+#define G_T5_SIZECH2(x) (((x) >> S_T5_SIZECH2) & M_T5_SIZECH2)
+
+#define S_T5_ERRCH2    9
+#define V_T5_ERRCH2(x) ((x) << S_T5_ERRCH2)
+#define F_T5_ERRCH2    V_T5_ERRCH2(1U)
+
+#define S_T5_FULLCH2    8
+#define V_T5_FULLCH2(x) ((x) << S_T5_FULLCH2)
+#define F_T5_FULLCH2    V_T5_FULLCH2(1U)
+
+#define S_T5_VALIDCH2    7
+#define V_T5_VALIDCH2(x) ((x) << S_T5_VALIDCH2)
+#define F_T5_VALIDCH2    V_T5_VALIDCH2(1U)
+
+#define S_T5_DATACH2    0
+#define M_T5_DATACH2    0x7fU
+#define V_T5_DATACH2(x) ((x) << S_T5_DATACH2)
+#define G_T5_DATACH2(x) (((x) >> S_T5_DATACH2) & M_T5_DATACH2)
+
 #define A_MPS_TX_DEBUG_REG_TX2MAC_10 0x944c
 
 #define S_SOPPT1    31
@@ -23464,6 +33086,50 @@
 #define V_DATAPT0(x) ((x) << S_DATAPT0)
 #define G_DATAPT0(x) (((x) >> S_DATAPT0) & M_DATAPT0)
 
+#define S_T5_SIZEPT1    26
+#define M_T5_SIZEPT1    0xfU
+#define V_T5_SIZEPT1(x) ((x) << S_T5_SIZEPT1)
+#define G_T5_SIZEPT1(x) (((x) >> S_T5_SIZEPT1) & M_T5_SIZEPT1)
+
+#define S_T5_ERRPT1    25
+#define V_T5_ERRPT1(x) ((x) << S_T5_ERRPT1)
+#define F_T5_ERRPT1    V_T5_ERRPT1(1U)
+
+#define S_T5_FULLPT1    24
+#define V_T5_FULLPT1(x) ((x) << S_T5_FULLPT1)
+#define F_T5_FULLPT1    V_T5_FULLPT1(1U)
+
+#define S_T5_VALIDPT1    23
+#define V_T5_VALIDPT1(x) ((x) << S_T5_VALIDPT1)
+#define F_T5_VALIDPT1    V_T5_VALIDPT1(1U)
+
+#define S_T5_DATAPT1    16
+#define M_T5_DATAPT1    0x7fU
+#define V_T5_DATAPT1(x) ((x) << S_T5_DATAPT1)
+#define G_T5_DATAPT1(x) (((x) >> S_T5_DATAPT1) & M_T5_DATAPT1)
+
+#define S_T5_SIZEPT0    10
+#define M_T5_SIZEPT0    0xfU
+#define V_T5_SIZEPT0(x) ((x) << S_T5_SIZEPT0)
+#define G_T5_SIZEPT0(x) (((x) >> S_T5_SIZEPT0) & M_T5_SIZEPT0)
+
+#define S_T5_ERRPT0    9
+#define V_T5_ERRPT0(x) ((x) << S_T5_ERRPT0)
+#define F_T5_ERRPT0    V_T5_ERRPT0(1U)
+
+#define S_T5_FULLPT0    8
+#define V_T5_FULLPT0(x) ((x) << S_T5_FULLPT0)
+#define F_T5_FULLPT0    V_T5_FULLPT0(1U)
+
+#define S_T5_VALIDPT0    7
+#define V_T5_VALIDPT0(x) ((x) << S_T5_VALIDPT0)
+#define F_T5_VALIDPT0    V_T5_VALIDPT0(1U)
+
+#define S_T5_DATAPT0    0
+#define M_T5_DATAPT0    0x7fU
+#define V_T5_DATAPT0(x) ((x) << S_T5_DATAPT0)
+#define G_T5_DATAPT0(x) (((x) >> S_T5_DATAPT0) & M_T5_DATAPT0)
+
 #define A_MPS_TX_DEBUG_REG_TX2MAC_32 0x9450
 
 #define S_SOPPT3    31
@@ -23526,6 +33192,50 @@
 #define V_DATAPT2(x) ((x) << S_DATAPT2)
 #define G_DATAPT2(x) (((x) >> S_DATAPT2) & M_DATAPT2)
 
+#define S_T5_SIZEPT3    26
+#define M_T5_SIZEPT3    0xfU
+#define V_T5_SIZEPT3(x) ((x) << S_T5_SIZEPT3)
+#define G_T5_SIZEPT3(x) (((x) >> S_T5_SIZEPT3) & M_T5_SIZEPT3)
+
+#define S_T5_ERRPT3    25
+#define V_T5_ERRPT3(x) ((x) << S_T5_ERRPT3)
+#define F_T5_ERRPT3    V_T5_ERRPT3(1U)
+
+#define S_T5_FULLPT3    24
+#define V_T5_FULLPT3(x) ((x) << S_T5_FULLPT3)
+#define F_T5_FULLPT3    V_T5_FULLPT3(1U)
+
+#define S_T5_VALIDPT3    23
+#define V_T5_VALIDPT3(x) ((x) << S_T5_VALIDPT3)
+#define F_T5_VALIDPT3    V_T5_VALIDPT3(1U)
+
+#define S_T5_DATAPT3    16
+#define M_T5_DATAPT3    0x7fU
+#define V_T5_DATAPT3(x) ((x) << S_T5_DATAPT3)
+#define G_T5_DATAPT3(x) (((x) >> S_T5_DATAPT3) & M_T5_DATAPT3)
+
+#define S_T5_SIZEPT2    10
+#define M_T5_SIZEPT2    0xfU
+#define V_T5_SIZEPT2(x) ((x) << S_T5_SIZEPT2)
+#define G_T5_SIZEPT2(x) (((x) >> S_T5_SIZEPT2) & M_T5_SIZEPT2)
+
+#define S_T5_ERRPT2    9
+#define V_T5_ERRPT2(x) ((x) << S_T5_ERRPT2)
+#define F_T5_ERRPT2    V_T5_ERRPT2(1U)
+
+#define S_T5_FULLPT2    8
+#define V_T5_FULLPT2(x) ((x) << S_T5_FULLPT2)
+#define F_T5_FULLPT2    V_T5_FULLPT2(1U)
+
+#define S_T5_VALIDPT2    7
+#define V_T5_VALIDPT2(x) ((x) << S_T5_VALIDPT2)
+#define F_T5_VALIDPT2    V_T5_VALIDPT2(1U)
+
+#define S_T5_DATAPT2    0
+#define M_T5_DATAPT2    0x7fU
+#define V_T5_DATAPT2(x) ((x) << S_T5_DATAPT2)
+#define G_T5_DATAPT2(x) (((x) >> S_T5_DATAPT2) & M_T5_DATAPT2)
+
 #define A_MPS_TX_SGE_CH_PAUSE_IGNR 0x9454
 
 #define S_SGEPAUSEIGNR    0
@@ -24031,6 +33741,14 @@
 #define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec
 #define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0
 #define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4
+#define A_MPS_STAT_STOP_UPD_RX_VF_128_159 0x96f8
+#define A_MPS_STAT_STOP_UPD_RX_VF_160_191 0x96fc
+#define A_MPS_STAT_STOP_UPD_RX_VF_192_223 0x9700
+#define A_MPS_STAT_STOP_UPD_RX_VF_224_255 0x9704
+#define A_MPS_STAT_STOP_UPD_TX_VF_128_159 0x9710
+#define A_MPS_STAT_STOP_UPD_TX_VF_160_191 0x9714
+#define A_MPS_STAT_STOP_UPD_TX_VF_192_223 0x9718
+#define A_MPS_STAT_STOP_UPD_TX_VF_224_255 0x971c
 #define A_MPS_TRC_CFG 0x9800
 
 #define S_TRCFIFOEMPTY    4
@@ -24253,9 +33971,164 @@
 #define V_VFFILTDATA(x) ((x) << S_VFFILTDATA)
 #define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA)
 
+#define S_T6_TRCMPS2TP_MACONLY    22
+#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
+#define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
+
+#define S_T6_TRCALLMPS2TP    21
+#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
+#define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
+
+#define S_T6_TRCALLTP2MPS    20
+#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
+#define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
+
+#define S_T6_TRCALLVF    19
+#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
+#define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
+
+#define S_T6_TRC_OFLD_EN    18
+#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
+#define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
+
+#define S_T6_VFFILTEN    17
+#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
+#define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
+
+#define S_T6_VFFILTMASK    9
+#define M_T6_VFFILTMASK    0xffU
+#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
+#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
+
+#define S_T6_VFFILTVALID    8
+#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
+#define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
+
+#define S_T6_VFFILTDATA    0
+#define M_T6_VFFILTDATA    0xffU
+#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
+#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
+
 #define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
+
+#define S_T6_TRCMPS2TP_MACONLY    22
+#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
+#define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
+
+#define S_T6_TRCALLMPS2TP    21
+#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
+#define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
+
+#define S_T6_TRCALLTP2MPS    20
+#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
+#define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
+
+#define S_T6_TRCALLVF    19
+#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
+#define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
+
+#define S_T6_TRC_OFLD_EN    18
+#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
+#define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
+
+#define S_T6_VFFILTEN    17
+#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
+#define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
+
+#define S_T6_VFFILTMASK    9
+#define M_T6_VFFILTMASK    0xffU
+#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
+#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
+
+#define S_T6_VFFILTVALID    8
+#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
+#define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
+
+#define S_T6_VFFILTDATA    0
+#define M_T6_VFFILTDATA    0xffU
+#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
+#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
+
 #define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
+
+#define S_T6_TRCMPS2TP_MACONLY    22
+#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
+#define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
+
+#define S_T6_TRCALLMPS2TP    21
+#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
+#define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
+
+#define S_T6_TRCALLTP2MPS    20
+#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
+#define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
+
+#define S_T6_TRCALLVF    19
+#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
+#define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
+
+#define S_T6_TRC_OFLD_EN    18
+#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
+#define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
+
+#define S_T6_VFFILTEN    17
+#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
+#define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
+
+#define S_T6_VFFILTMASK    9
+#define M_T6_VFFILTMASK    0xffU
+#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
+#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
+
+#define S_T6_VFFILTVALID    8
+#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
+#define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
+
+#define S_T6_VFFILTDATA    0
+#define M_T6_VFFILTDATA    0xffU
+#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
+#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
+
 #define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
+
+#define S_T6_TRCMPS2TP_MACONLY    22
+#define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
+#define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
+
+#define S_T6_TRCALLMPS2TP    21
+#define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
+#define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
+
+#define S_T6_TRCALLTP2MPS    20
+#define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
+#define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
+
+#define S_T6_TRCALLVF    19
+#define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
+#define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
+
+#define S_T6_TRC_OFLD_EN    18
+#define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
+#define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
+
+#define S_T6_VFFILTEN    17
+#define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
+#define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
+
+#define S_T6_VFFILTMASK    9
+#define M_T6_VFFILTMASK    0xffU
+#define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
+#define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
+
+#define S_T6_VFFILTVALID    8
+#define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
+#define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
+
+#define S_T6_VFFILTDATA    0
+#define M_T6_VFFILTDATA    0xffU
+#define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
+#define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
+
 #define A_MPS_TRC_CGEN 0xa020
 
 #define S_MPSTRCCGEN    0
@@ -24285,6 +34158,18 @@
 #define V_VLANCLSEN(x) ((x) << S_VLANCLSEN)
 #define F_VLANCLSEN    V_VLANCLSEN(1U)
 
+#define S_VLANCLSEN_IN    7
+#define V_VLANCLSEN_IN(x) ((x) << S_VLANCLSEN_IN)
+#define F_VLANCLSEN_IN    V_VLANCLSEN_IN(1U)
+
+#define S_DISTCAMPARCHK    6
+#define V_DISTCAMPARCHK(x) ((x) << S_DISTCAMPARCHK)
+#define F_DISTCAMPARCHK    V_DISTCAMPARCHK(1U)
+
+#define S_VLANLKPEN    5
+#define V_VLANLKPEN(x) ((x) << S_VLANLKPEN)
+#define F_VLANLKPEN    V_VLANLKPEN(1U)
+
 #define A_MPS_CLS_ARB_WEIGHT 0xd004
 
 #define S_PLWEIGHT    16
@@ -24302,6 +34187,8 @@
 #define V_LPBKWEIGHT(x) ((x) << S_LPBKWEIGHT)
 #define G_LPBKWEIGHT(x) (((x) >> S_LPBKWEIGHT) & M_LPBKWEIGHT)
 
+#define A_MPS_CLS_NCSI_ETH_TYPE 0xd008
+#define A_MPS_CLS_NCSI_ETH_TYPE_EN 0xd00c
 #define A_MPS_CLS_BMC_MAC_ADDR_L 0xd010
 #define A_MPS_CLS_BMC_MAC_ADDR_H 0xd014
 #define A_MPS_CLS_BMC_VLAN 0xd018
@@ -24370,6 +34257,30 @@
 #define V_CLS_MATCH(x) ((x) << S_CLS_MATCH)
 #define G_CLS_MATCH(x) (((x) >> S_CLS_MATCH) & M_CLS_MATCH)
 
+#define S_CLS_SPARE    28
+#define M_CLS_SPARE    0xfU
+#define V_CLS_SPARE(x) ((x) << S_CLS_SPARE)
+#define G_CLS_SPARE(x) (((x) >> S_CLS_SPARE) & M_CLS_SPARE)
+
+#define S_T6_CLS_PRIORITY    25
+#define M_T6_CLS_PRIORITY    0x7U
+#define V_T6_CLS_PRIORITY(x) ((x) << S_T6_CLS_PRIORITY)
+#define G_T6_CLS_PRIORITY(x) (((x) >> S_T6_CLS_PRIORITY) & M_T6_CLS_PRIORITY)
+
+#define S_T6_CLS_REPLICATE    24
+#define V_T6_CLS_REPLICATE(x) ((x) << S_T6_CLS_REPLICATE)
+#define F_T6_CLS_REPLICATE    V_T6_CLS_REPLICATE(1U)
+
+#define S_T6_CLS_INDEX    15
+#define M_T6_CLS_INDEX    0x1ffU
+#define V_T6_CLS_INDEX(x) ((x) << S_T6_CLS_INDEX)
+#define G_T6_CLS_INDEX(x) (((x) >> S_T6_CLS_INDEX) & M_T6_CLS_INDEX)
+
+#define S_T6_CLS_VF    7
+#define M_T6_CLS_VF    0xffU
+#define V_T6_CLS_VF(x) ((x) << S_T6_CLS_VF)
+#define G_T6_CLS_VF(x) (((x) >> S_T6_CLS_VF) & M_T6_CLS_VF)
+
 #define A_MPS_CLS_PL_TEST_CTL 0xd038
 
 #define S_PLTESTCTL    0
@@ -24382,6 +34293,108 @@
 #define V_PRTBMCCTL(x) ((x) << S_PRTBMCCTL)
 #define F_PRTBMCCTL    V_PRTBMCCTL(1U)
 
+#define A_MPS_CLS_MATCH_CNT_TCAM 0xd100
+#define A_MPS_CLS_MATCH_CNT_HASH 0xd104
+#define A_MPS_CLS_MATCH_CNT_BCAST 0xd108
+#define A_MPS_CLS_MATCH_CNT_BMC 0xd10c
+#define A_MPS_CLS_MATCH_CNT_PROM 0xd110
+#define A_MPS_CLS_MATCH_CNT_HPROM 0xd114
+#define A_MPS_CLS_MISS_CNT 0xd118
+#define A_MPS_CLS_REQUEST_TRACE_MAC_DA_L 0xd200
+#define A_MPS_CLS_REQUEST_TRACE_MAC_DA_H 0xd204
+
+#define S_CLSTRCMACDAHI    0
+#define M_CLSTRCMACDAHI    0xffffU
+#define V_CLSTRCMACDAHI(x) ((x) << S_CLSTRCMACDAHI)
+#define G_CLSTRCMACDAHI(x) (((x) >> S_CLSTRCMACDAHI) & M_CLSTRCMACDAHI)
+
+#define A_MPS_CLS_REQUEST_TRACE_MAC_SA_L 0xd208
+#define A_MPS_CLS_REQUEST_TRACE_MAC_SA_H 0xd20c
+
+#define S_CLSTRCMACSAHI    0
+#define M_CLSTRCMACSAHI    0xffffU
+#define V_CLSTRCMACSAHI(x) ((x) << S_CLSTRCMACSAHI)
+#define G_CLSTRCMACSAHI(x) (((x) >> S_CLSTRCMACSAHI) & M_CLSTRCMACSAHI)
+
+#define A_MPS_CLS_REQUEST_TRACE_PORT_VLAN 0xd210
+
+#define S_CLSTRCVLANVLD    31
+#define V_CLSTRCVLANVLD(x) ((x) << S_CLSTRCVLANVLD)
+#define F_CLSTRCVLANVLD    V_CLSTRCVLANVLD(1U)
+
+#define S_CLSTRCVLANID    16
+#define M_CLSTRCVLANID    0xfffU
+#define V_CLSTRCVLANID(x) ((x) << S_CLSTRCVLANID)
+#define G_CLSTRCVLANID(x) (((x) >> S_CLSTRCVLANID) & M_CLSTRCVLANID)
+
+#define S_CLSTRCREQPORT    0
+#define M_CLSTRCREQPORT    0xfU
+#define V_CLSTRCREQPORT(x) ((x) << S_CLSTRCREQPORT)
+#define G_CLSTRCREQPORT(x) (((x) >> S_CLSTRCREQPORT) & M_CLSTRCREQPORT)
+
+#define A_MPS_CLS_REQUEST_TRACE_ENCAP 0xd214
+
+#define S_CLSTRCLKPTYPE    31
+#define V_CLSTRCLKPTYPE(x) ((x) << S_CLSTRCLKPTYPE)
+#define F_CLSTRCLKPTYPE    V_CLSTRCLKPTYPE(1U)
+
+#define S_CLSTRCDIPHIT    30
+#define V_CLSTRCDIPHIT(x) ((x) << S_CLSTRCDIPHIT)
+#define F_CLSTRCDIPHIT    V_CLSTRCDIPHIT(1U)
+
+#define S_CLSTRCVNI    0
+#define M_CLSTRCVNI    0xffffffU
+#define V_CLSTRCVNI(x) ((x) << S_CLSTRCVNI)
+#define G_CLSTRCVNI(x) (((x) >> S_CLSTRCVNI) & M_CLSTRCVNI)
+
+#define A_MPS_CLS_RESULT_TRACE 0xd300
+
+#define S_CLSTRCPORTNUM    31
+#define V_CLSTRCPORTNUM(x) ((x) << S_CLSTRCPORTNUM)
+#define F_CLSTRCPORTNUM    V_CLSTRCPORTNUM(1U)
+
+#define S_CLSTRCPRIORITY    28
+#define M_CLSTRCPRIORITY    0x7U
+#define V_CLSTRCPRIORITY(x) ((x) << S_CLSTRCPRIORITY)
+#define G_CLSTRCPRIORITY(x) (((x) >> S_CLSTRCPRIORITY) & M_CLSTRCPRIORITY)
+
+#define S_CLSTRCMULTILISTEN    27
+#define V_CLSTRCMULTILISTEN(x) ((x) << S_CLSTRCMULTILISTEN)
+#define F_CLSTRCMULTILISTEN    V_CLSTRCMULTILISTEN(1U)
+
+#define S_CLSTRCREPLICATE    26
+#define V_CLSTRCREPLICATE(x) ((x) << S_CLSTRCREPLICATE)
+#define F_CLSTRCREPLICATE    V_CLSTRCREPLICATE(1U)
+
+#define S_CLSTRCPORTMAP    24
+#define M_CLSTRCPORTMAP    0x3U
+#define V_CLSTRCPORTMAP(x) ((x) << S_CLSTRCPORTMAP)
+#define G_CLSTRCPORTMAP(x) (((x) >> S_CLSTRCPORTMAP) & M_CLSTRCPORTMAP)
+
+#define S_CLSTRCMATCH    21
+#define M_CLSTRCMATCH    0x7U
+#define V_CLSTRCMATCH(x) ((x) << S_CLSTRCMATCH)
+#define G_CLSTRCMATCH(x) (((x) >> S_CLSTRCMATCH) & M_CLSTRCMATCH)
+
+#define S_CLSTRCINDEX    12
+#define M_CLSTRCINDEX    0x1ffU
+#define V_CLSTRCINDEX(x) ((x) << S_CLSTRCINDEX)
+#define G_CLSTRCINDEX(x) (((x) >> S_CLSTRCINDEX) & M_CLSTRCINDEX)
+
+#define S_CLSTRCVF_VLD    11
+#define V_CLSTRCVF_VLD(x) ((x) << S_CLSTRCVF_VLD)
+#define F_CLSTRCVF_VLD    V_CLSTRCVF_VLD(1U)
+
+#define S_CLSTRCPF    3
+#define M_CLSTRCPF    0xffU
+#define V_CLSTRCPF(x) ((x) << S_CLSTRCPF)
+#define G_CLSTRCPF(x) (((x) >> S_CLSTRCPF) & M_CLSTRCPF)
+
+#define S_CLSTRCVF    0
+#define M_CLSTRCVF    0x7U
+#define V_CLSTRCVF(x) ((x) << S_CLSTRCVF)
+#define G_CLSTRCVF(x) (((x) >> S_CLSTRCVF) & M_CLSTRCVF)
+
 #define A_MPS_CLS_VLAN_TABLE 0xdfc0
 
 #define S_VLAN_MASK    16
@@ -24441,6 +34454,73 @@
 #define F_SRAM_VLD    V_SRAM_VLD(1U)
 
 #define A_MPS_T5_CLS_SRAM_L 0xe000
+
+#define S_T6_DISENCAPOUTERRPLCT    31
+#define V_T6_DISENCAPOUTERRPLCT(x) ((x) << S_T6_DISENCAPOUTERRPLCT)
+#define F_T6_DISENCAPOUTERRPLCT    V_T6_DISENCAPOUTERRPLCT(1U)
+
+#define S_T6_DISENCAP    30
+#define V_T6_DISENCAP(x) ((x) << S_T6_DISENCAP)
+#define F_T6_DISENCAP    V_T6_DISENCAP(1U)
+
+#define S_T6_MULTILISTEN3    29
+#define V_T6_MULTILISTEN3(x) ((x) << S_T6_MULTILISTEN3)
+#define F_T6_MULTILISTEN3    V_T6_MULTILISTEN3(1U)
+
+#define S_T6_MULTILISTEN2    28
+#define V_T6_MULTILISTEN2(x) ((x) << S_T6_MULTILISTEN2)
+#define F_T6_MULTILISTEN2    V_T6_MULTILISTEN2(1U)
+
+#define S_T6_MULTILISTEN1    27
+#define V_T6_MULTILISTEN1(x) ((x) << S_T6_MULTILISTEN1)
+#define F_T6_MULTILISTEN1    V_T6_MULTILISTEN1(1U)
+
+#define S_T6_MULTILISTEN0    26
+#define V_T6_MULTILISTEN0(x) ((x) << S_T6_MULTILISTEN0)
+#define F_T6_MULTILISTEN0    V_T6_MULTILISTEN0(1U)
+
+#define S_T6_SRAM_PRIO3    23
+#define M_T6_SRAM_PRIO3    0x7U
+#define V_T6_SRAM_PRIO3(x) ((x) << S_T6_SRAM_PRIO3)
+#define G_T6_SRAM_PRIO3(x) (((x) >> S_T6_SRAM_PRIO3) & M_T6_SRAM_PRIO3)
+
+#define S_T6_SRAM_PRIO2    20
+#define M_T6_SRAM_PRIO2    0x7U
+#define V_T6_SRAM_PRIO2(x) ((x) << S_T6_SRAM_PRIO2)
+#define G_T6_SRAM_PRIO2(x) (((x) >> S_T6_SRAM_PRIO2) & M_T6_SRAM_PRIO2)
+
+#define S_T6_SRAM_PRIO1    17
+#define M_T6_SRAM_PRIO1    0x7U
+#define V_T6_SRAM_PRIO1(x) ((x) << S_T6_SRAM_PRIO1)
+#define G_T6_SRAM_PRIO1(x) (((x) >> S_T6_SRAM_PRIO1) & M_T6_SRAM_PRIO1)
+
+#define S_T6_SRAM_PRIO0    14
+#define M_T6_SRAM_PRIO0    0x7U
+#define V_T6_SRAM_PRIO0(x) ((x) << S_T6_SRAM_PRIO0)
+#define G_T6_SRAM_PRIO0(x) (((x) >> S_T6_SRAM_PRIO0) & M_T6_SRAM_PRIO0)
+
+#define S_T6_SRAM_VLD    13
+#define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD)
+#define F_T6_SRAM_VLD    V_T6_SRAM_VLD(1U)
+
+#define S_T6_REPLICATE    12
+#define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
+#define F_T6_REPLICATE    V_T6_REPLICATE(1U)
+
+#define S_T6_PF    9
+#define M_T6_PF    0x7U
+#define V_T6_PF(x) ((x) << S_T6_PF)
+#define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
+
+#define S_T6_VF_VALID    8
+#define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
+#define F_T6_VF_VALID    V_T6_VF_VALID(1U)
+
+#define S_T6_VF    0
+#define M_T6_VF    0xffU
+#define V_T6_VF(x) ((x) << S_T6_VF)
+#define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
+
 #define A_MPS_CLS_SRAM_H 0xe004
 
 #define S_MACPARITY1    9
@@ -24462,7 +34542,13 @@
 #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
 
 #define A_MPS_T5_CLS_SRAM_H 0xe004
+
+#define S_MACPARITY2    10
+#define V_MACPARITY2(x) ((x) << S_MACPARITY2)
+#define F_MACPARITY2    V_MACPARITY2(1U)
+
 #define A_MPS_CLS_TCAM_Y_L 0xf000
+#define A_MPS_CLS_TCAM_DATA0 0xf000
 #define A_MPS_CLS_TCAM_Y_H 0xf004
 
 #define S_TCAMYH    0
@@ -24470,7 +34556,65 @@
 #define V_TCAMYH(x) ((x) << S_TCAMYH)
 #define G_TCAMYH(x) (((x) >> S_TCAMYH) & M_TCAMYH)
 
+#define A_MPS_CLS_TCAM_DATA1 0xf004
+
+#define S_VIDL    16
+#define M_VIDL    0xffffU
+#define V_VIDL(x) ((x) << S_VIDL)
+#define G_VIDL(x) (((x) >> S_VIDL) & M_VIDL)
+
+#define S_DMACH    0
+#define M_DMACH    0xffffU
+#define V_DMACH(x) ((x) << S_DMACH)
+#define G_DMACH(x) (((x) >> S_DMACH) & M_DMACH)
+
 #define A_MPS_CLS_TCAM_X_L 0xf008
+#define A_MPS_CLS_TCAM_DATA2_CTL 0xf008
+
+#define S_CTLCMDTYPE    31
+#define V_CTLCMDTYPE(x) ((x) << S_CTLCMDTYPE)
+#define F_CTLCMDTYPE    V_CTLCMDTYPE(1U)
+
+#define S_CTLREQID    30
+#define V_CTLREQID(x) ((x) << S_CTLREQID)
+#define F_CTLREQID    V_CTLREQID(1U)
+
+#define S_CTLTCAMSEL    25
+#define V_CTLTCAMSEL(x) ((x) << S_CTLTCAMSEL)
+#define F_CTLTCAMSEL    V_CTLTCAMSEL(1U)
+
+#define S_CTLTCAMINDEX    17
+#define M_CTLTCAMINDEX    0xffU
+#define V_CTLTCAMINDEX(x) ((x) << S_CTLTCAMINDEX)
+#define G_CTLTCAMINDEX(x) (((x) >> S_CTLTCAMINDEX) & M_CTLTCAMINDEX)
+
+#define S_CTLXYBITSEL    16
+#define V_CTLXYBITSEL(x) ((x) << S_CTLXYBITSEL)
+#define F_CTLXYBITSEL    V_CTLXYBITSEL(1U)
+
+#define S_DATAPORTNUM    12
+#define M_DATAPORTNUM    0xfU
+#define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM)
+#define G_DATAPORTNUM(x) (((x) >> S_DATAPORTNUM) & M_DATAPORTNUM)
+
+#define S_DATALKPTYPE    10
+#define M_DATALKPTYPE    0x3U
+#define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE)
+#define G_DATALKPTYPE(x) (((x) >> S_DATALKPTYPE) & M_DATALKPTYPE)
+
+#define S_DATADIPHIT    8
+#define V_DATADIPHIT(x) ((x) << S_DATADIPHIT)
+#define F_DATADIPHIT    V_DATADIPHIT(1U)
+
+#define S_DATAVIDH2    7
+#define V_DATAVIDH2(x) ((x) << S_DATAVIDH2)
+#define F_DATAVIDH2    V_DATAVIDH2(1U)
+
+#define S_DATAVIDH1    0
+#define M_DATAVIDH1    0x7fU
+#define V_DATAVIDH1(x) ((x) << S_DATAVIDH1)
+#define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1)
+
 #define A_MPS_CLS_TCAM_X_H 0xf00c
 
 #define S_TCAMXH    0
@@ -24478,6 +34622,12 @@
 #define V_TCAMXH(x) ((x) << S_TCAMXH)
 #define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH)
 
+#define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010
+#define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014
+#define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018
+#define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020
+#define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024
+#define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028
 #define A_MPS_RX_CTL 0x11000
 
 #define S_FILT_VLAN_SEL    17
@@ -24536,7 +34686,15 @@
 #define V_CNT(x) ((x) << S_CNT)
 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
 
+#define A_MPS_RX_FIFO_0_CTL 0x11008
+
+#define S_DEST_SELECT    0
+#define M_DEST_SELECT    0xfU
+#define V_DEST_SELECT(x) ((x) << S_DEST_SELECT)
+#define G_DEST_SELECT(x) (((x) >> S_DEST_SELECT) & M_DEST_SELECT)
+
 #define A_MPS_RX_PKT_FL 0x1100c
+#define A_MPS_RX_FIFO_1_CTL 0x1100c
 #define A_MPS_RX_PG_RSV0 0x11010
 
 #define S_CLR_INTR    31
@@ -24567,7 +34725,9 @@
 #define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
 #define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)
 
+#define A_MPS_RX_FIFO_2_CTL 0x11010
 #define A_MPS_RX_PG_RSV1 0x11014
+#define A_MPS_RX_FIFO_3_CTL 0x11014
 #define A_MPS_RX_PG_RSV2 0x11018
 #define A_MPS_RX_PG_RSV3 0x1101c
 #define A_MPS_RX_PG_RSV4 0x11020
@@ -24642,6 +34802,11 @@
 #define V_T5_TH(x) ((x) << S_T5_TH)
 #define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH)
 
+#define S_T6_TH    0
+#define M_T6_TH    0x7ffU
+#define V_T6_TH(x) ((x) << S_T6_TH)
+#define G_T6_TH(x) (((x) >> S_T6_TH) & M_T6_TH)
+
 #define A_MPS_RX_PG_HYST_BG1 0x1104c
 #define A_MPS_RX_PG_HYST_BG2 0x11050
 #define A_MPS_RX_PG_HYST_BG3 0x11054
@@ -24788,8 +34953,22 @@
 #define V_CDM0(x) ((x) << S_CDM0)
 #define F_CDM0    V_CDM0(1U)
 
+#define S_T6_INT_ERR_INT    24
+#define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
+#define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
+
 #define A_MPS_RX_PERR_INT_ENABLE 0x11078
+
+#define S_T6_INT_ERR_INT    24
+#define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
+#define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
+
 #define A_MPS_RX_PERR_ENABLE 0x1107c
+
+#define S_T6_INT_ERR_INT    24
+#define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
+#define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
+
 #define A_MPS_RX_PERR_INJECT 0x11080
 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
 
@@ -24874,6 +35053,12 @@
 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
+#define A_MPS_RX_REPL_CTL 0x11098
+
+#define S_INDEX_SEL    0
+#define V_INDEX_SEL(x) ((x) << S_INDEX_SEL)
+#define F_INDEX_SEL    V_INDEX_SEL(1U)
+
 #define A_MPS_RX_PPP_ATRB 0x1109c
 
 #define S_ETYPE    16
@@ -24909,7 +35094,9 @@
 #define A_MPS_RX_PT_ARB1 0x110ac
 #define A_MPS_RX_PT_ARB2 0x110b0
 #define A_MPS_RX_PT_ARB3 0x110b4
+#define A_T6_MPS_PF_OUT_EN 0x110b4
 #define A_MPS_RX_PT_ARB4 0x110b8
+#define A_T6_MPS_BMC_MTU 0x110b8
 #define A_MPS_PF_OUT_EN 0x110bc
 
 #define S_OUTEN    0
@@ -24917,6 +35104,7 @@
 #define V_OUTEN(x) ((x) << S_OUTEN)
 #define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN)
 
+#define A_T6_MPS_BMC_PKT_CNT 0x110bc
 #define A_MPS_BMC_MTU 0x110c0
 
 #define S_MTU    0
@@ -24924,8 +35112,22 @@
 #define V_MTU(x) ((x) << S_MTU)
 #define G_MTU(x) (((x) >> S_MTU) & M_MTU)
 
+#define A_T6_MPS_BMC_BYTE_CNT 0x110c0
 #define A_MPS_BMC_PKT_CNT 0x110c4
+#define A_T6_MPS_PFVF_ATRB_CTL 0x110c4
+
+#define S_T6_PFVF    0
+#define M_T6_PFVF    0x1ffU
+#define V_T6_PFVF(x) ((x) << S_T6_PFVF)
+#define G_T6_PFVF(x) (((x) >> S_T6_PFVF) & M_T6_PFVF)
+
 #define A_MPS_BMC_BYTE_CNT 0x110c8
+#define A_T6_MPS_PFVF_ATRB 0x110c8
+
+#define S_FULL_FRAME_MODE    14
+#define V_FULL_FRAME_MODE(x) ((x) << S_FULL_FRAME_MODE)
+#define F_FULL_FRAME_MODE    V_FULL_FRAME_MODE(1U)
+
 #define A_MPS_PFVF_ATRB_CTL 0x110cc
 
 #define S_RD_WRN    31
@@ -24937,6 +35139,7 @@
 #define V_PFVF(x) ((x) << S_PFVF)
 #define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF)
 
+#define A_T6_MPS_PFVF_ATRB_FLTR0 0x110cc
 #define A_MPS_PFVF_ATRB 0x110d0
 
 #define S_ATTR_PF    28
@@ -24956,6 +35159,7 @@
 #define V_ATTR_MODE(x) ((x) << S_ATTR_MODE)
 #define F_ATTR_MODE    V_ATTR_MODE(1U)
 
+#define A_T6_MPS_PFVF_ATRB_FLTR1 0x110d0
 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4
 
 #define S_VLAN_EN    16
@@ -24967,21 +35171,37 @@
 #define V_VLAN_ID(x) ((x) << S_VLAN_ID)
 #define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID)
 
+#define A_T6_MPS_PFVF_ATRB_FLTR2 0x110d4
 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8
+#define A_T6_MPS_PFVF_ATRB_FLTR3 0x110d8
 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc
+#define A_T6_MPS_PFVF_ATRB_FLTR4 0x110dc
 #define A_MPS_PFVF_ATRB_FLTR3 0x110e0
+#define A_T6_MPS_PFVF_ATRB_FLTR5 0x110e0
 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4
+#define A_T6_MPS_PFVF_ATRB_FLTR6 0x110e4
 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8
+#define A_T6_MPS_PFVF_ATRB_FLTR7 0x110e8
 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec
+#define A_T6_MPS_PFVF_ATRB_FLTR8 0x110ec
 #define A_MPS_PFVF_ATRB_FLTR7 0x110f0
+#define A_T6_MPS_PFVF_ATRB_FLTR9 0x110f0
 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4
+#define A_T6_MPS_PFVF_ATRB_FLTR10 0x110f4
 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8
+#define A_T6_MPS_PFVF_ATRB_FLTR11 0x110f8
 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc
+#define A_T6_MPS_PFVF_ATRB_FLTR12 0x110fc
 #define A_MPS_PFVF_ATRB_FLTR11 0x11100
+#define A_T6_MPS_PFVF_ATRB_FLTR13 0x11100
 #define A_MPS_PFVF_ATRB_FLTR12 0x11104
+#define A_T6_MPS_PFVF_ATRB_FLTR14 0x11104
 #define A_MPS_PFVF_ATRB_FLTR13 0x11108
+#define A_T6_MPS_PFVF_ATRB_FLTR15 0x11108
 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c
+#define A_T6_MPS_RPLC_MAP_CTL 0x1110c
 #define A_MPS_PFVF_ATRB_FLTR15 0x11110
+#define A_T6_MPS_PF_RPLCT_MAP 0x11110
 #define A_MPS_RPLC_MAP_CTL 0x11114
 
 #define S_RPLC_MAP_ADDR    0
@@ -24989,6 +35209,7 @@
 #define V_RPLC_MAP_ADDR(x) ((x) << S_RPLC_MAP_ADDR)
 #define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR)
 
+#define A_T6_MPS_VF_RPLCT_MAP0 0x11114
 #define A_MPS_PF_RPLCT_MAP 0x11118
 
 #define S_PF_EN    0
@@ -24996,8 +35217,11 @@
 #define V_PF_EN(x) ((x) << S_PF_EN)
 #define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN)
 
+#define A_T6_MPS_VF_RPLCT_MAP1 0x11118
 #define A_MPS_VF_RPLCT_MAP0 0x1111c
+#define A_T6_MPS_VF_RPLCT_MAP2 0x1111c
 #define A_MPS_VF_RPLCT_MAP1 0x11120
+#define A_T6_MPS_VF_RPLCT_MAP3 0x11120
 #define A_MPS_VF_RPLCT_MAP2 0x11124
 #define A_MPS_VF_RPLCT_MAP3 0x11128
 #define A_MPS_MEM_DBG_CTL 0x1112c
@@ -25333,6 +35557,309 @@
 #define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN)
 #define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN)
 
+#define A_MPS_RX_MAC_BG_PG_CNT0 0x11208
+
+#define S_MAC_USED    16
+#define M_MAC_USED    0x7ffU
+#define V_MAC_USED(x) ((x) << S_MAC_USED)
+#define G_MAC_USED(x) (((x) >> S_MAC_USED) & M_MAC_USED)
+
+#define S_MAC_ALLOC    0
+#define M_MAC_ALLOC    0x7ffU
+#define V_MAC_ALLOC(x) ((x) << S_MAC_ALLOC)
+#define G_MAC_ALLOC(x) (((x) >> S_MAC_ALLOC) & M_MAC_ALLOC)
+
+#define A_MPS_RX_MAC_BG_PG_CNT1 0x1120c
+#define A_MPS_RX_MAC_BG_PG_CNT2 0x11210
+#define A_MPS_RX_MAC_BG_PG_CNT3 0x11214
+#define A_MPS_RX_LPBK_BG_PG_CNT0 0x11218
+
+#define S_LPBK_USED    16
+#define M_LPBK_USED    0x7ffU
+#define V_LPBK_USED(x) ((x) << S_LPBK_USED)
+#define G_LPBK_USED(x) (((x) >> S_LPBK_USED) & M_LPBK_USED)
+
+#define S_LPBK_ALLOC    0
+#define M_LPBK_ALLOC    0x7ffU
+#define V_LPBK_ALLOC(x) ((x) << S_LPBK_ALLOC)
+#define G_LPBK_ALLOC(x) (((x) >> S_LPBK_ALLOC) & M_LPBK_ALLOC)
+
+#define A_MPS_RX_LPBK_BG_PG_CNT1 0x1121c
+#define A_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11220
+
+#define S_CONG_EN    31
+#define V_CONG_EN(x) ((x) << S_CONG_EN)
+#define F_CONG_EN    V_CONG_EN(1U)
+
+#define S_CONG_TH    0
+#define M_CONG_TH    0xfffffU
+#define V_CONG_TH(x) ((x) << S_CONG_TH)
+#define G_CONG_TH(x) (((x) >> S_CONG_TH) & M_CONG_TH)
+
+#define A_MPS_RX_CONGESTION_THRESHOLD_BG1 0x11224
+#define A_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11228
+#define A_MPS_RX_CONGESTION_THRESHOLD_BG3 0x1122c
+#define A_MPS_RX_GRE_PROT_TYPE 0x11230
+
+#define S_NVGRE_EN    9
+#define V_NVGRE_EN(x) ((x) << S_NVGRE_EN)
+#define F_NVGRE_EN    V_NVGRE_EN(1U)
+
+#define S_GRE_EN    8
+#define V_GRE_EN(x) ((x) << S_GRE_EN)
+#define F_GRE_EN    V_GRE_EN(1U)
+
+#define S_GRE    0
+#define M_GRE    0xffU
+#define V_GRE(x) ((x) << S_GRE)
+#define G_GRE(x) (((x) >> S_GRE) & M_GRE)
+
+#define A_MPS_RX_VXLAN_TYPE 0x11234
+
+#define S_VXLAN_EN    16
+#define V_VXLAN_EN(x) ((x) << S_VXLAN_EN)
+#define F_VXLAN_EN    V_VXLAN_EN(1U)
+
+#define S_VXLAN    0
+#define M_VXLAN    0xffffU
+#define V_VXLAN(x) ((x) << S_VXLAN)
+#define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN)
+
+#define A_MPS_RX_GENEVE_TYPE 0x11238
+
+#define S_GENEVE_EN    16
+#define V_GENEVE_EN(x) ((x) << S_GENEVE_EN)
+#define F_GENEVE_EN    V_GENEVE_EN(1U)
+
+#define S_GENEVE    0
+#define M_GENEVE    0xffffU
+#define V_GENEVE(x) ((x) << S_GENEVE)
+#define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE)
+
+#define A_MPS_RX_INNER_HDR_IVLAN 0x1123c
+
+#define S_T6_IVLAN_EN    16
+#define V_T6_IVLAN_EN(x) ((x) << S_T6_IVLAN_EN)
+#define F_T6_IVLAN_EN    V_T6_IVLAN_EN(1U)
+
+#define A_MPS_RX_ENCAP_NVGRE 0x11240
+
+#define S_ETYPE_EN    16
+#define V_ETYPE_EN(x) ((x) << S_ETYPE_EN)
+#define F_ETYPE_EN    V_ETYPE_EN(1U)
+
+#define S_T6_ETYPE    0
+#define M_T6_ETYPE    0xffffU
+#define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
+#define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
+
+#define A_MPS_RX_ENCAP_GENEVE 0x11244
+
+#define S_T6_ETYPE    0
+#define M_T6_ETYPE    0xffffU
+#define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
+#define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
+
+#define A_MPS_RX_TCP 0x11248
+
+#define S_PROT_TYPE_EN    8
+#define V_PROT_TYPE_EN(x) ((x) << S_PROT_TYPE_EN)
+#define F_PROT_TYPE_EN    V_PROT_TYPE_EN(1U)
+
+#define S_PROT_TYPE    0
+#define M_PROT_TYPE    0xffU
+#define V_PROT_TYPE(x) ((x) << S_PROT_TYPE)
+#define G_PROT_TYPE(x) (((x) >> S_PROT_TYPE) & M_PROT_TYPE)
+
+#define A_MPS_RX_UDP 0x1124c
+#define A_MPS_RX_PAUSE 0x11250
+#define A_MPS_RX_LENGTH 0x11254
+
+#define S_SAP_VALUE    16
+#define M_SAP_VALUE    0xffffU
+#define V_SAP_VALUE(x) ((x) << S_SAP_VALUE)
+#define G_SAP_VALUE(x) (((x) >> S_SAP_VALUE) & M_SAP_VALUE)
+
+#define S_LENGTH_ETYPE    0
+#define M_LENGTH_ETYPE    0xffffU
+#define V_LENGTH_ETYPE(x) ((x) << S_LENGTH_ETYPE)
+#define G_LENGTH_ETYPE(x) (((x) >> S_LENGTH_ETYPE) & M_LENGTH_ETYPE)
+
+#define A_MPS_RX_CTL_ORG 0x11258
+
+#define S_CTL_VALUE    24
+#define M_CTL_VALUE    0xffU
+#define V_CTL_VALUE(x) ((x) << S_CTL_VALUE)
+#define G_CTL_VALUE(x) (((x) >> S_CTL_VALUE) & M_CTL_VALUE)
+
+#define S_ORG_VALUE    0
+#define M_ORG_VALUE    0xffffffU
+#define V_ORG_VALUE(x) ((x) << S_ORG_VALUE)
+#define G_ORG_VALUE(x) (((x) >> S_ORG_VALUE) & M_ORG_VALUE)
+
+#define A_MPS_RX_IPV4 0x1125c
+
+#define S_ETYPE_IPV4    0
+#define M_ETYPE_IPV4    0xffffU
+#define V_ETYPE_IPV4(x) ((x) << S_ETYPE_IPV4)
+#define G_ETYPE_IPV4(x) (((x) >> S_ETYPE_IPV4) & M_ETYPE_IPV4)
+
+#define A_MPS_RX_IPV6 0x11260
+
+#define S_ETYPE_IPV6    0
+#define M_ETYPE_IPV6    0xffffU
+#define V_ETYPE_IPV6(x) ((x) << S_ETYPE_IPV6)
+#define G_ETYPE_IPV6(x) (((x) >> S_ETYPE_IPV6) & M_ETYPE_IPV6)
+
+#define A_MPS_RX_TTL 0x11264
+
+#define S_TTL_IPV4    10
+#define M_TTL_IPV4    0xffU
+#define V_TTL_IPV4(x) ((x) << S_TTL_IPV4)
+#define G_TTL_IPV4(x) (((x) >> S_TTL_IPV4) & M_TTL_IPV4)
+
+#define S_TTL_IPV6    2
+#define M_TTL_IPV6    0xffU
+#define V_TTL_IPV6(x) ((x) << S_TTL_IPV6)
+#define G_TTL_IPV6(x) (((x) >> S_TTL_IPV6) & M_TTL_IPV6)
+
+#define S_TTL_CHK_EN_IPV4    1
+#define V_TTL_CHK_EN_IPV4(x) ((x) << S_TTL_CHK_EN_IPV4)
+#define F_TTL_CHK_EN_IPV4    V_TTL_CHK_EN_IPV4(1U)
+
+#define S_TTL_CHK_EN_IPV6    0
+#define V_TTL_CHK_EN_IPV6(x) ((x) << S_TTL_CHK_EN_IPV6)
+#define F_TTL_CHK_EN_IPV6    V_TTL_CHK_EN_IPV6(1U)
+
+#define A_MPS_RX_DEFAULT_VNI 0x11268
+
+#define S_VNI    0
+#define M_VNI    0xffffffU
+#define V_VNI(x) ((x) << S_VNI)
+#define G_VNI(x) (((x) >> S_VNI) & M_VNI)
+
+#define A_MPS_RX_PRS_CTL 0x1126c
+
+#define S_CTL_CHK_EN    28
+#define V_CTL_CHK_EN(x) ((x) << S_CTL_CHK_EN)
+#define F_CTL_CHK_EN    V_CTL_CHK_EN(1U)
+
+#define S_ORG_CHK_EN    27
+#define V_ORG_CHK_EN(x) ((x) << S_ORG_CHK_EN)
+#define F_ORG_CHK_EN    V_ORG_CHK_EN(1U)
+
+#define S_SAP_CHK_EN    26
+#define V_SAP_CHK_EN(x) ((x) << S_SAP_CHK_EN)
+#define F_SAP_CHK_EN    V_SAP_CHK_EN(1U)
+
+#define S_VXLAN_FLAG_CHK_EN    25
+#define V_VXLAN_FLAG_CHK_EN(x) ((x) << S_VXLAN_FLAG_CHK_EN)
+#define F_VXLAN_FLAG_CHK_EN    V_VXLAN_FLAG_CHK_EN(1U)
+
+#define S_VXLAN_FLAG_MASK    17
+#define M_VXLAN_FLAG_MASK    0xffU
+#define V_VXLAN_FLAG_MASK(x) ((x) << S_VXLAN_FLAG_MASK)
+#define G_VXLAN_FLAG_MASK(x) (((x) >> S_VXLAN_FLAG_MASK) & M_VXLAN_FLAG_MASK)
+
+#define S_VXLAN_FLAG    9
+#define M_VXLAN_FLAG    0xffU
+#define V_VXLAN_FLAG(x) ((x) << S_VXLAN_FLAG)
+#define G_VXLAN_FLAG(x) (((x) >> S_VXLAN_FLAG) & M_VXLAN_FLAG)
+
+#define S_GRE_VER_CHK_EN    8
+#define V_GRE_VER_CHK_EN(x) ((x) << S_GRE_VER_CHK_EN)
+#define F_GRE_VER_CHK_EN    V_GRE_VER_CHK_EN(1U)
+
+#define S_GRE_VER    5
+#define M_GRE_VER    0x7U
+#define V_GRE_VER(x) ((x) << S_GRE_VER)
+#define G_GRE_VER(x) (((x) >> S_GRE_VER) & M_GRE_VER)
+
+#define S_GENEVE_VER_CHK_EN    4
+#define V_GENEVE_VER_CHK_EN(x) ((x) << S_GENEVE_VER_CHK_EN)
+#define F_GENEVE_VER_CHK_EN    V_GENEVE_VER_CHK_EN(1U)
+
+#define S_GENEVE_VER    2
+#define M_GENEVE_VER    0x3U
+#define V_GENEVE_VER(x) ((x) << S_GENEVE_VER)
+#define G_GENEVE_VER(x) (((x) >> S_GENEVE_VER) & M_GENEVE_VER)
+
+#define S_DIP_EN    1
+#define V_DIP_EN(x) ((x) << S_DIP_EN)
+#define F_DIP_EN    V_DIP_EN(1U)
+
+#define A_MPS_RX_PRS_CTL_2 0x11270
+
+#define S_EN_UDP_CSUM_CHK    4
+#define V_EN_UDP_CSUM_CHK(x) ((x) << S_EN_UDP_CSUM_CHK)
+#define F_EN_UDP_CSUM_CHK    V_EN_UDP_CSUM_CHK(1U)
+
+#define S_EN_UDP_LEN_CHK    3
+#define V_EN_UDP_LEN_CHK(x) ((x) << S_EN_UDP_LEN_CHK)
+#define F_EN_UDP_LEN_CHK    V_EN_UDP_LEN_CHK(1U)
+
+#define S_EN_IP_CSUM_CHK    2
+#define V_EN_IP_CSUM_CHK(x) ((x) << S_EN_IP_CSUM_CHK)
+#define F_EN_IP_CSUM_CHK    V_EN_IP_CSUM_CHK(1U)
+
+#define S_EN_IP_PAYLOAD_LEN_CHK    1
+#define V_EN_IP_PAYLOAD_LEN_CHK(x) ((x) << S_EN_IP_PAYLOAD_LEN_CHK)
+#define F_EN_IP_PAYLOAD_LEN_CHK    V_EN_IP_PAYLOAD_LEN_CHK(1U)
+
+#define S_T6_IPV6_UDP_CSUM_COMPAT    0
+#define V_T6_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_T6_IPV6_UDP_CSUM_COMPAT)
+#define F_T6_IPV6_UDP_CSUM_COMPAT    V_T6_IPV6_UDP_CSUM_COMPAT(1U)
+
+#define A_MPS_RX_MPS2NCSI_CNT 0x11274
+#define A_MPS_RX_MAX_TNL_HDR_LEN 0x11278
+
+#define S_T6_LEN    0
+#define M_T6_LEN    0x1ffU
+#define V_T6_LEN(x) ((x) << S_T6_LEN)
+#define G_T6_LEN(x) (((x) >> S_T6_LEN) & M_T6_LEN)
+
+#define A_MPS_RX_PAUSE_DA_H 0x1127c
+#define A_MPS_RX_PAUSE_DA_L 0x11280
+#define A_MPS_RX_CNT_NVGRE_PKT_MAC0 0x11284
+#define A_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11288
+#define A_MPS_RX_CNT_GENEVE_PKT_MAC0 0x1128c
+#define A_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11290
+#define A_MPS_RX_CNT_NVGRE_PKT_MAC1 0x11294
+#define A_MPS_RX_CNT_VXLAN_PKT_MAC1 0x11298
+#define A_MPS_RX_CNT_GENEVE_PKT_MAC1 0x1129c
+#define A_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a0
+#define A_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112a4
+#define A_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112a8
+#define A_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112ac
+#define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b0
+#define A_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112b4
+#define A_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112b8
+#define A_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112bc
+#define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c0
+#define A_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112c4
+#define A_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112c8
+#define A_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112cc
+#define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d0
+#define A_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112d4
+#define A_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112d8
+#define A_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112dc
+#define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e0
+#define A_MPS_VF_RPLCT_MAP4 0x11300
+#define A_MPS_VF_RPLCT_MAP5 0x11304
+#define A_MPS_VF_RPLCT_MAP6 0x11308
+#define A_MPS_VF_RPLCT_MAP7 0x1130c
+#define A_MPS_CLS_DIPIPV4_ID_TABLE 0x12000
+#define A_MPS_CLS_DIPIPV4_MASK_TABLE 0x12004
+#define A_MPS_CLS_DIPIPV6ID_0_TABLE 0x12020
+#define A_MPS_CLS_DIPIPV6ID_1_TABLE 0x12024
+#define A_MPS_CLS_DIPIPV6ID_2_TABLE 0x12028
+#define A_MPS_CLS_DIPIPV6ID_3_TABLE 0x1202c
+#define A_MPS_CLS_DIPIPV6MASK_0_TABLE 0x12030
+#define A_MPS_CLS_DIPIPV6MASK_1_TABLE 0x12034
+#define A_MPS_CLS_DIPIPV6MASK_2_TABLE 0x12038
+#define A_MPS_CLS_DIPIPV6MASK_3_TABLE 0x1203c
+#define A_MPS_RX_HASH_LKP_TABLE 0x12060
+
 /* registers for module CPL_SWITCH */
 #define CPL_SWITCH_BASE_ADDR 0x19040
 
@@ -26203,6 +36730,10 @@
 #define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN)
 #define F_PCIE_PART_CGEN    V_PCIE_PART_CGEN(1U)
 
+#define S_PL_DIS_PRTY_CHK    20
+#define V_PL_DIS_PRTY_CHK(x) ((x) << S_PL_DIS_PRTY_CHK)
+#define F_PL_DIS_PRTY_CHK    V_PL_DIS_PRTY_CHK(1U)
+
 #define A_PMU_SLEEPMODE_WAKEUP 0x19124
 
 #define S_HWWAKEUPEN    5
@@ -26691,6 +37222,14 @@
 #define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1)
 #define F_PERR_RSVD1    V_PERR_RSVD1(1U)
 
+#define S_PERR_ENABLE_CTX_1    24
+#define V_PERR_ENABLE_CTX_1(x) ((x) << S_PERR_ENABLE_CTX_1)
+#define F_PERR_ENABLE_CTX_1    V_PERR_ENABLE_CTX_1(1U)
+
+#define S_PERR_ENABLE_CTX_0    23
+#define V_PERR_ENABLE_CTX_0(x) ((x) << S_PERR_ENABLE_CTX_0)
+#define F_PERR_ENABLE_CTX_0    V_PERR_ENABLE_CTX_0(1U)
+
 #define A_ULP_RX_PERR_INJECT 0x191a0
 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4
 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8
@@ -26937,6 +37476,78 @@
 #define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN)
 #define F_SDC_CRC_PROT_EN    V_SDC_CRC_PROT_EN(1U)
 
+#define S_ISCSI_DCRC_ERROR_CMP_EN    25
+#define V_ISCSI_DCRC_ERROR_CMP_EN(x) ((x) << S_ISCSI_DCRC_ERROR_CMP_EN)
+#define F_ISCSI_DCRC_ERROR_CMP_EN    V_ISCSI_DCRC_ERROR_CMP_EN(1U)
+
+#define S_ISCSITAGPI    24
+#define V_ISCSITAGPI(x) ((x) << S_ISCSITAGPI)
+#define F_ISCSITAGPI    V_ISCSITAGPI(1U)
+
+#define S_DDP_VERSION_1    22
+#define M_DDP_VERSION_1    0x3U
+#define V_DDP_VERSION_1(x) ((x) << S_DDP_VERSION_1)
+#define G_DDP_VERSION_1(x) (((x) >> S_DDP_VERSION_1) & M_DDP_VERSION_1)
+
+#define S_DDP_VERSION_0    20
+#define M_DDP_VERSION_0    0x3U
+#define V_DDP_VERSION_0(x) ((x) << S_DDP_VERSION_0)
+#define G_DDP_VERSION_0(x) (((x) >> S_DDP_VERSION_0) & M_DDP_VERSION_0)
+
+#define S_RDMA_VERSION_1    18
+#define M_RDMA_VERSION_1    0x3U
+#define V_RDMA_VERSION_1(x) ((x) << S_RDMA_VERSION_1)
+#define G_RDMA_VERSION_1(x) (((x) >> S_RDMA_VERSION_1) & M_RDMA_VERSION_1)
+
+#define S_RDMA_VERSION_0    16
+#define M_RDMA_VERSION_0    0x3U
+#define V_RDMA_VERSION_0(x) ((x) << S_RDMA_VERSION_0)
+#define G_RDMA_VERSION_0(x) (((x) >> S_RDMA_VERSION_0) & M_RDMA_VERSION_0)
+
+#define S_PBL_BOUND_CHECK_W_PGLEN    15
+#define V_PBL_BOUND_CHECK_W_PGLEN(x) ((x) << S_PBL_BOUND_CHECK_W_PGLEN)
+#define F_PBL_BOUND_CHECK_W_PGLEN    V_PBL_BOUND_CHECK_W_PGLEN(1U)
+
+#define S_ZBYTE_FIX_DISABLE    14
+#define V_ZBYTE_FIX_DISABLE(x) ((x) << S_ZBYTE_FIX_DISABLE)
+#define F_ZBYTE_FIX_DISABLE    V_ZBYTE_FIX_DISABLE(1U)
+
+#define S_T10_OFFSET_UPDATE_EN    13
+#define V_T10_OFFSET_UPDATE_EN(x) ((x) << S_T10_OFFSET_UPDATE_EN)
+#define F_T10_OFFSET_UPDATE_EN    V_T10_OFFSET_UPDATE_EN(1U)
+
+#define S_ULP_INSERT_PI    12
+#define V_ULP_INSERT_PI(x) ((x) << S_ULP_INSERT_PI)
+#define F_ULP_INSERT_PI    V_ULP_INSERT_PI(1U)
+
+#define S_PDU_DPI    11
+#define V_PDU_DPI(x) ((x) << S_PDU_DPI)
+#define F_PDU_DPI    V_PDU_DPI(1U)
+
+#define S_ISCSI_EFF_OFFSET_EN    10
+#define V_ISCSI_EFF_OFFSET_EN(x) ((x) << S_ISCSI_EFF_OFFSET_EN)
+#define F_ISCSI_EFF_OFFSET_EN    V_ISCSI_EFF_OFFSET_EN(1U)
+
+#define S_ISCSI_ALL_CMP_MODE    9
+#define V_ISCSI_ALL_CMP_MODE(x) ((x) << S_ISCSI_ALL_CMP_MODE)
+#define F_ISCSI_ALL_CMP_MODE    V_ISCSI_ALL_CMP_MODE(1U)
+
+#define S_ISCSI_ENABLE_HDR_CMD    8
+#define V_ISCSI_ENABLE_HDR_CMD(x) ((x) << S_ISCSI_ENABLE_HDR_CMD)
+#define F_ISCSI_ENABLE_HDR_CMD    V_ISCSI_ENABLE_HDR_CMD(1U)
+
+#define S_ISCSI_FORCE_CMP_MODE    7
+#define V_ISCSI_FORCE_CMP_MODE(x) ((x) << S_ISCSI_FORCE_CMP_MODE)
+#define F_ISCSI_FORCE_CMP_MODE    V_ISCSI_FORCE_CMP_MODE(1U)
+
+#define S_ISCSI_ENABLE_CMP_MODE    6
+#define V_ISCSI_ENABLE_CMP_MODE(x) ((x) << S_ISCSI_ENABLE_CMP_MODE)
+#define F_ISCSI_ENABLE_CMP_MODE    V_ISCSI_ENABLE_CMP_MODE(1U)
+
+#define S_PIO_RDMA_SEND_RQE    5
+#define V_PIO_RDMA_SEND_RQE(x) ((x) << S_PIO_RDMA_SEND_RQE)
+#define F_PIO_RDMA_SEND_RQE    V_PIO_RDMA_SEND_RQE(1U)
+
 #define A_ULP_RX_CH0_CGEN 0x19260
 
 #define S_BYPASS_CGEN    7
@@ -27114,6 +37725,44 @@
 #define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE)
 #define F_SEND_MSN_CHECK_ENABLE    V_SEND_MSN_CHECK_ENABLE(1U)
 
+#define A_ULP_RX_TLS_PP_LLIMIT 0x192a4
+
+#define S_TLSPPLLIMIT    6
+#define M_TLSPPLLIMIT    0x3ffffffU
+#define V_TLSPPLLIMIT(x) ((x) << S_TLSPPLLIMIT)
+#define G_TLSPPLLIMIT(x) (((x) >> S_TLSPPLLIMIT) & M_TLSPPLLIMIT)
+
+#define A_ULP_RX_TLS_PP_ULIMIT 0x192a8
+
+#define S_TLSPPULIMIT    6
+#define M_TLSPPULIMIT    0x3ffffffU
+#define V_TLSPPULIMIT(x) ((x) << S_TLSPPULIMIT)
+#define G_TLSPPULIMIT(x) (((x) >> S_TLSPPULIMIT) & M_TLSPPULIMIT)
+
+#define A_ULP_RX_TLS_KEY_LLIMIT 0x192ac
+
+#define S_TLSKEYLLIMIT    8
+#define M_TLSKEYLLIMIT    0xffffffU
+#define V_TLSKEYLLIMIT(x) ((x) << S_TLSKEYLLIMIT)
+#define G_TLSKEYLLIMIT(x) (((x) >> S_TLSKEYLLIMIT) & M_TLSKEYLLIMIT)
+
+#define A_ULP_RX_TLS_KEY_ULIMIT 0x192b0
+
+#define S_TLSKEYULIMIT    8
+#define M_TLSKEYULIMIT    0xffffffU
+#define V_TLSKEYULIMIT(x) ((x) << S_TLSKEYULIMIT)
+#define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT)
+
+#define A_ULP_RX_TLS_CTL 0x192bc
+#define A_ULP_RX_TLS_IND_CMD 0x19348
+
+#define S_TLS_RX_REG_OFF_ADDR    0
+#define M_TLS_RX_REG_OFF_ADDR    0x3ffU
+#define V_TLS_RX_REG_OFF_ADDR(x) ((x) << S_TLS_RX_REG_OFF_ADDR)
+#define G_TLS_RX_REG_OFF_ADDR(x) (((x) >> S_TLS_RX_REG_OFF_ADDR) & M_TLS_RX_REG_OFF_ADDR)
+
+#define A_ULP_RX_TLS_IND_DATA 0x1934c
+
 /* registers for module SF */
 #define SF_BASE_ADDR 0x193f8
 
@@ -27162,6 +37811,20 @@
 #define V_VFID(x) ((x) << S_VFID)
 #define G_VFID(x) (((x) >> S_VFID) & M_VFID)
 
+#define S_T6_SOURCEPF    9
+#define M_T6_SOURCEPF    0x7U
+#define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
+#define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
+
+#define S_T6_ISVF    8
+#define V_T6_ISVF(x) ((x) << S_T6_ISVF)
+#define F_T6_ISVF    V_T6_ISVF(1U)
+
+#define S_T6_VFID    0
+#define M_T6_VFID    0xffU
+#define V_T6_VFID(x) ((x) << S_T6_VFID)
+#define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
+
 #define A_PL_VF_REV 0x4
 
 #define S_CHIPID    4
@@ -27196,6 +37859,21 @@
 #define F_SWINT    V_SWINT(1U)
 
 #define A_PL_WHOAMI 0x19400
+
+#define S_T6_SOURCEPF    9
+#define M_T6_SOURCEPF    0x7U
+#define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
+#define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
+
+#define S_T6_ISVF    8
+#define V_T6_ISVF(x) ((x) << S_T6_ISVF)
+#define F_T6_ISVF    V_T6_ISVF(1U)
+
+#define S_T6_VFID    0
+#define M_T6_VFID    0xffU
+#define V_T6_VFID(x) ((x) << S_T6_VFID)
+#define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
+
 #define A_PL_PERR_CAUSE 0x19404
 
 #define S_UART    28
@@ -27513,16 +38191,71 @@
 #define V_LN0_AECMD(x) ((x) << S_LN0_AECMD)
 #define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD)
 
+#define S_T5_STATECFGINITF    16
+#define M_T5_STATECFGINITF    0x7fU
+#define V_T5_STATECFGINITF(x) ((x) << S_T5_STATECFGINITF)
+#define G_T5_STATECFGINITF(x) (((x) >> S_T5_STATECFGINITF) & M_T5_STATECFGINITF)
+
+#define S_T5_STATECFGINIT    12
+#define M_T5_STATECFGINIT    0xfU
+#define V_T5_STATECFGINIT(x) ((x) << S_T5_STATECFGINIT)
+#define G_T5_STATECFGINIT(x) (((x) >> S_T5_STATECFGINIT) & M_T5_STATECFGINIT)
+
 #define S_PCIE_SPEED    8
 #define M_PCIE_SPEED    0x3U
 #define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED)
 #define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED)
 
+#define S_T5_PERSTTIMEOUT    7
+#define V_T5_PERSTTIMEOUT(x) ((x) << S_T5_PERSTTIMEOUT)
+#define F_T5_PERSTTIMEOUT    V_T5_PERSTTIMEOUT(1U)
+
+#define S_T5_LTSSMENABLE    6
+#define V_T5_LTSSMENABLE(x) ((x) << S_T5_LTSSMENABLE)
+#define F_T5_LTSSMENABLE    V_T5_LTSSMENABLE(1U)
+
 #define S_LTSSM    0
 #define M_LTSSM    0x3fU
 #define V_LTSSM(x) ((x) << S_LTSSM)
 #define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM)
 
+#define S_T6_LN0_AESTAT    27
+#define M_T6_LN0_AESTAT    0x7U
+#define V_T6_LN0_AESTAT(x) ((x) << S_T6_LN0_AESTAT)
+#define G_T6_LN0_AESTAT(x) (((x) >> S_T6_LN0_AESTAT) & M_T6_LN0_AESTAT)
+
+#define S_T6_LN0_AECMD    24
+#define M_T6_LN0_AECMD    0x7U
+#define V_T6_LN0_AECMD(x) ((x) << S_T6_LN0_AECMD)
+#define G_T6_LN0_AECMD(x) (((x) >> S_T6_LN0_AECMD) & M_T6_LN0_AECMD)
+
+#define S_T6_STATECFGINITF    16
+#define M_T6_STATECFGINITF    0xffU
+#define V_T6_STATECFGINITF(x) ((x) << S_T6_STATECFGINITF)
+#define G_T6_STATECFGINITF(x) (((x) >> S_T6_STATECFGINITF) & M_T6_STATECFGINITF)
+
+#define S_T6_STATECFGINIT    12
+#define M_T6_STATECFGINIT    0xfU
+#define V_T6_STATECFGINIT(x) ((x) << S_T6_STATECFGINIT)
+#define G_T6_STATECFGINIT(x) (((x) >> S_T6_STATECFGINIT) & M_T6_STATECFGINIT)
+
+#define S_PHY_STATUS    10
+#define V_PHY_STATUS(x) ((x) << S_PHY_STATUS)
+#define F_PHY_STATUS    V_PHY_STATUS(1U)
+
+#define S_SPEED_PL    8
+#define M_SPEED_PL    0x3U
+#define V_SPEED_PL(x) ((x) << S_SPEED_PL)
+#define G_SPEED_PL(x) (((x) >> S_SPEED_PL) & M_SPEED_PL)
+
+#define S_PERSTTIMEOUT_PL    7
+#define V_PERSTTIMEOUT_PL(x) ((x) << S_PERSTTIMEOUT_PL)
+#define F_PERSTTIMEOUT_PL    V_PERSTTIMEOUT_PL(1U)
+
+#define S_T6_LTSSMENABLE    6
+#define V_T6_LTSSMENABLE(x) ((x) << S_T6_LTSSMENABLE)
+#define F_T6_LTSSMENABLE    V_T6_LTSSMENABLE(1U)
+
 #define A_PL_PCIE_CTL_STAT 0x19444
 
 #define S_PCIE_STATUS    16
@@ -27704,6 +38437,11 @@
 #define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
 #define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)
 
+#define S_T6_PL_TOVFID    0
+#define M_T6_PL_TOVFID    0x1ffU
+#define V_T6_PL_TOVFID(x) ((x) << S_T6_PL_TOVFID)
+#define G_T6_PL_TOVFID(x) (((x) >> S_T6_PL_TOVFID) & M_T6_PL_TOVFID)
+
 #define A_PL_VFID_MAP 0x19800
 
 #define S_VFID_VLD    7
@@ -27714,6 +38452,7 @@
 #define LE_BASE_ADDR 0x19c00
 
 #define A_LE_BUF_CONFIG 0x19c00
+#define A_LE_DB_ID 0x19c00
 #define A_LE_DB_CONFIG 0x19c04
 
 #define S_TCAMCMDOVLAPEN    21
@@ -27821,6 +38560,51 @@
 #define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
 #define F_SINGLETHREAD    V_SINGLETHREAD(1U)
 
+#define S_CHK_FUL_TUP_ZERO    27
+#define V_CHK_FUL_TUP_ZERO(x) ((x) << S_CHK_FUL_TUP_ZERO)
+#define F_CHK_FUL_TUP_ZERO    V_CHK_FUL_TUP_ZERO(1U)
+
+#define S_PRI_HASH    26
+#define V_PRI_HASH(x) ((x) << S_PRI_HASH)
+#define F_PRI_HASH    V_PRI_HASH(1U)
+
+#define S_EXTN_HASH_IPV4    25
+#define V_EXTN_HASH_IPV4(x) ((x) << S_EXTN_HASH_IPV4)
+#define F_EXTN_HASH_IPV4    V_EXTN_HASH_IPV4(1U)
+
+#define S_ASLIPCOMPEN_IPV4    18
+#define V_ASLIPCOMPEN_IPV4(x) ((x) << S_ASLIPCOMPEN_IPV4)
+#define F_ASLIPCOMPEN_IPV4    V_ASLIPCOMPEN_IPV4(1U)
+
+#define S_IGNR_TUP_ZERO    9
+#define V_IGNR_TUP_ZERO(x) ((x) << S_IGNR_TUP_ZERO)
+#define F_IGNR_TUP_ZERO    V_IGNR_TUP_ZERO(1U)
+
+#define S_IGNR_LIP_ZERO    8
+#define V_IGNR_LIP_ZERO(x) ((x) << S_IGNR_LIP_ZERO)
+#define F_IGNR_LIP_ZERO    V_IGNR_LIP_ZERO(1U)
+
+#define S_CLCAM_INIT_BUSY    7
+#define V_CLCAM_INIT_BUSY(x) ((x) << S_CLCAM_INIT_BUSY)
+#define F_CLCAM_INIT_BUSY    V_CLCAM_INIT_BUSY(1U)
+
+#define S_CLCAM_INIT    6
+#define V_CLCAM_INIT(x) ((x) << S_CLCAM_INIT)
+#define F_CLCAM_INIT    V_CLCAM_INIT(1U)
+
+#define S_MTCAM_INIT_BUSY    5
+#define V_MTCAM_INIT_BUSY(x) ((x) << S_MTCAM_INIT_BUSY)
+#define F_MTCAM_INIT_BUSY    V_MTCAM_INIT_BUSY(1U)
+
+#define S_MTCAM_INIT    4
+#define V_MTCAM_INIT(x) ((x) << S_MTCAM_INIT)
+#define F_MTCAM_INIT    V_MTCAM_INIT(1U)
+
+#define S_REGION_EN    0
+#define M_REGION_EN    0xfU
+#define V_REGION_EN(x) ((x) << S_REGION_EN)
+#define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN)
+
 #define A_LE_MISC 0x19c08
 
 #define S_CMPUNVAIL    0
@@ -27860,6 +38644,43 @@
 #define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF)
 #define F_HASHCLKOFF    V_HASHCLKOFF(1U)
 
+#define A_LE_DB_EXEC_CTRL 0x19c08
+
+#define S_TPDB_IF_PAUSE_ACK    10
+#define V_TPDB_IF_PAUSE_ACK(x) ((x) << S_TPDB_IF_PAUSE_ACK)
+#define F_TPDB_IF_PAUSE_ACK    V_TPDB_IF_PAUSE_ACK(1U)
+
+#define S_TPDB_IF_PAUSE_REQ    9
+#define V_TPDB_IF_PAUSE_REQ(x) ((x) << S_TPDB_IF_PAUSE_REQ)
+#define F_TPDB_IF_PAUSE_REQ    V_TPDB_IF_PAUSE_REQ(1U)
+
+#define S_ERRSTOP_EN    8
+#define V_ERRSTOP_EN(x) ((x) << S_ERRSTOP_EN)
+#define F_ERRSTOP_EN    V_ERRSTOP_EN(1U)
+
+#define S_CMDLIMIT    0
+#define M_CMDLIMIT    0xffU
+#define V_CMDLIMIT(x) ((x) << S_CMDLIMIT)
+#define G_CMDLIMIT(x) (((x) >> S_CMDLIMIT) & M_CMDLIMIT)
+
+#define A_LE_DB_PS_CTRL 0x19c0c
+
+#define S_CLTCAMDEEPSLEEP_STAT    10
+#define V_CLTCAMDEEPSLEEP_STAT(x) ((x) << S_CLTCAMDEEPSLEEP_STAT)
+#define F_CLTCAMDEEPSLEEP_STAT    V_CLTCAMDEEPSLEEP_STAT(1U)
+
+#define S_TCAMDEEPSLEEP_STAT    9
+#define V_TCAMDEEPSLEEP_STAT(x) ((x) << S_TCAMDEEPSLEEP_STAT)
+#define F_TCAMDEEPSLEEP_STAT    V_TCAMDEEPSLEEP_STAT(1U)
+
+#define S_CLTCAMDEEPSLEEP    7
+#define V_CLTCAMDEEPSLEEP(x) ((x) << S_CLTCAMDEEPSLEEP)
+#define F_CLTCAMDEEPSLEEP    V_CLTCAMDEEPSLEEP(1U)
+
+#define S_TCAMDEEPSLEEP    6
+#define V_TCAMDEEPSLEEP(x) ((x) << S_TCAMDEEPSLEEP)
+#define F_TCAMDEEPSLEEP    V_TCAMDEEPSLEEP(1U)
+
 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
 
 #define S_RTINDX    7
@@ -27867,6 +38688,13 @@
 #define V_RTINDX(x) ((x) << S_RTINDX)
 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
 
+#define A_LE_DB_ACTIVE_TABLE_START_INDEX 0x19c10
+
+#define S_ATINDX    0
+#define M_ATINDX    0xfffffU
+#define V_ATINDX(x) ((x) << S_ATINDX)
+#define G_ATINDX(x) (((x) >> S_ATINDX) & M_ATINDX)
+
 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
 
 #define S_FTINDX    7
@@ -27874,6 +38702,13 @@
 #define V_FTINDX(x) ((x) << S_FTINDX)
 #define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)
 
+#define A_LE_DB_NORM_FILT_TABLE_START_INDEX 0x19c14
+
+#define S_NFTINDX    0
+#define M_NFTINDX    0xfffffU
+#define V_NFTINDX(x) ((x) << S_NFTINDX)
+#define G_NFTINDX(x) (((x) >> S_NFTINDX) & M_NFTINDX)
+
 #define A_LE_DB_SERVER_INDEX 0x19c18
 
 #define S_SRINDX    7
@@ -27881,6 +38716,13 @@
 #define V_SRINDX(x) ((x) << S_SRINDX)
 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
 
+#define A_LE_DB_SRVR_START_INDEX 0x19c18
+
+#define S_T6_SRINDX    0
+#define M_T6_SRINDX    0xfffffU
+#define V_T6_SRINDX(x) ((x) << S_T6_SRINDX)
+#define G_T6_SRINDX(x) (((x) >> S_T6_SRINDX) & M_T6_SRINDX)
+
 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
 
 #define S_CLIPTINDX    7
@@ -27888,6 +38730,13 @@
 #define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
 #define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)
 
+#define A_LE_DB_HPRI_FILT_TABLE_START_INDEX 0x19c1c
+
+#define S_HFTINDX    0
+#define M_HFTINDX    0xfffffU
+#define V_HFTINDX(x) ((x) << S_HFTINDX)
+#define G_HFTINDX(x) (((x) >> S_HFTINDX) & M_HFTINDX)
+
 #define A_LE_DB_ACT_CNT_IPV4 0x19c20
 
 #define S_ACTCNTIPV4    0
@@ -27914,9 +38763,40 @@
 #define V_HASHSIZE(x) ((x) << S_HASHSIZE)
 #define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)
 
+#define S_NUMHASHBKT    20
+#define M_NUMHASHBKT    0x1fU
+#define V_NUMHASHBKT(x) ((x) << S_NUMHASHBKT)
+#define G_NUMHASHBKT(x) (((x) >> S_NUMHASHBKT) & M_NUMHASHBKT)
+
+#define S_HASHTBLSIZE    3
+#define M_HASHTBLSIZE    0x1ffffU
+#define V_HASHTBLSIZE(x) ((x) << S_HASHTBLSIZE)
+#define G_HASHTBLSIZE(x) (((x) >> S_HASHTBLSIZE) & M_HASHTBLSIZE)
+
 #define A_LE_DB_HASH_TABLE_BASE 0x19c2c
+#define A_LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES 0x19c2c
+
+#define S_MIN_ATCAM_ENTS    0
+#define M_MIN_ATCAM_ENTS    0xfffffU
+#define V_MIN_ATCAM_ENTS(x) ((x) << S_MIN_ATCAM_ENTS)
+#define G_MIN_ATCAM_ENTS(x) (((x) >> S_MIN_ATCAM_ENTS) & M_MIN_ATCAM_ENTS)
+
 #define A_LE_DB_HASH_TID_BASE 0x19c30
+#define A_LE_DB_HASH_TBL_BASE_ADDR 0x19c30
+
+#define S_HASHTBLADDR    4
+#define M_HASHTBLADDR    0xfffffffU
+#define V_HASHTBLADDR(x) ((x) << S_HASHTBLADDR)
+#define G_HASHTBLADDR(x) (((x) >> S_HASHTBLADDR) & M_HASHTBLADDR)
+
 #define A_LE_DB_SIZE 0x19c34
+#define A_LE_TCAM_SIZE 0x19c34
+
+#define S_TCAM_SIZE    0
+#define M_TCAM_SIZE    0x3U
+#define V_TCAM_SIZE(x) ((x) << S_TCAM_SIZE)
+#define G_TCAM_SIZE(x) (((x) >> S_TCAM_SIZE) & M_TCAM_SIZE)
+
 #define A_LE_DB_INT_ENABLE 0x19c38
 
 #define S_MSGSEL    27
@@ -28012,7 +38892,160 @@
 #define V_VFPARERR(x) ((x) << S_VFPARERR)
 #define F_VFPARERR    V_VFPARERR(1U)
 
+#define S_CLIPSUBERR    29
+#define V_CLIPSUBERR(x) ((x) << S_CLIPSUBERR)
+#define F_CLIPSUBERR    V_CLIPSUBERR(1U)
+
+#define S_CLCAMFIFOERR    28
+#define V_CLCAMFIFOERR(x) ((x) << S_CLCAMFIFOERR)
+#define F_CLCAMFIFOERR    V_CLCAMFIFOERR(1U)
+
+#define S_HASHTBLMEMCRCERR    27
+#define V_HASHTBLMEMCRCERR(x) ((x) << S_HASHTBLMEMCRCERR)
+#define F_HASHTBLMEMCRCERR    V_HASHTBLMEMCRCERR(1U)
+
+#define S_CTCAMINVLDENT    26
+#define V_CTCAMINVLDENT(x) ((x) << S_CTCAMINVLDENT)
+#define F_CTCAMINVLDENT    V_CTCAMINVLDENT(1U)
+
+#define S_TCAMINVLDENT    25
+#define V_TCAMINVLDENT(x) ((x) << S_TCAMINVLDENT)
+#define F_TCAMINVLDENT    V_TCAMINVLDENT(1U)
+
+#define S_TOTCNTERR    24
+#define V_TOTCNTERR(x) ((x) << S_TOTCNTERR)
+#define F_TOTCNTERR    V_TOTCNTERR(1U)
+
+#define S_CMDPRSRINTERR    23
+#define V_CMDPRSRINTERR(x) ((x) << S_CMDPRSRINTERR)
+#define F_CMDPRSRINTERR    V_CMDPRSRINTERR(1U)
+
+#define S_CMDTIDERR    22
+#define V_CMDTIDERR(x) ((x) << S_CMDTIDERR)
+#define F_CMDTIDERR    V_CMDTIDERR(1U)
+
+#define S_T6_ACTRGNFULL    21
+#define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
+#define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)
+
+#define S_T6_ACTCNTIPV6TZERO    20
+#define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
+#define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)
+
+#define S_T6_ACTCNTIPV4TZERO    19
+#define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
+#define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)
+
+#define S_T6_ACTCNTIPV6ZERO    18
+#define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
+#define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)
+
+#define S_T6_ACTCNTIPV4ZERO    17
+#define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
+#define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)
+
+#define S_MAIFWRINTPERR    16
+#define V_MAIFWRINTPERR(x) ((x) << S_MAIFWRINTPERR)
+#define F_MAIFWRINTPERR    V_MAIFWRINTPERR(1U)
+
+#define S_HASHTBLMEMACCERR    15
+#define V_HASHTBLMEMACCERR(x) ((x) << S_HASHTBLMEMACCERR)
+#define F_HASHTBLMEMACCERR    V_HASHTBLMEMACCERR(1U)
+
+#define S_TCAMCRCERR    14
+#define V_TCAMCRCERR(x) ((x) << S_TCAMCRCERR)
+#define F_TCAMCRCERR    V_TCAMCRCERR(1U)
+
+#define S_TCAMINTPERR    13
+#define V_TCAMINTPERR(x) ((x) << S_TCAMINTPERR)
+#define F_TCAMINTPERR    V_TCAMINTPERR(1U)
+
+#define S_VFSRAMPERR    12
+#define V_VFSRAMPERR(x) ((x) << S_VFSRAMPERR)
+#define F_VFSRAMPERR    V_VFSRAMPERR(1U)
+
+#define S_SRVSRAMPERR    11
+#define V_SRVSRAMPERR(x) ((x) << S_SRVSRAMPERR)
+#define F_SRVSRAMPERR    V_SRVSRAMPERR(1U)
+
+#define S_SSRAMINTPERR    10
+#define V_SSRAMINTPERR(x) ((x) << S_SSRAMINTPERR)
+#define F_SSRAMINTPERR    V_SSRAMINTPERR(1U)
+
+#define S_CLCAMINTPERR    9
+#define V_CLCAMINTPERR(x) ((x) << S_CLCAMINTPERR)
+#define F_CLCAMINTPERR    V_CLCAMINTPERR(1U)
+
+#define S_CLCAMCRCPARERR    8
+#define V_CLCAMCRCPARERR(x) ((x) << S_CLCAMCRCPARERR)
+#define F_CLCAMCRCPARERR    V_CLCAMCRCPARERR(1U)
+
+#define S_HASHTBLACCFAIL    7
+#define V_HASHTBLACCFAIL(x) ((x) << S_HASHTBLACCFAIL)
+#define F_HASHTBLACCFAIL    V_HASHTBLACCFAIL(1U)
+
+#define S_TCAMACCFAIL    6
+#define V_TCAMACCFAIL(x) ((x) << S_TCAMACCFAIL)
+#define F_TCAMACCFAIL    V_TCAMACCFAIL(1U)
+
+#define S_SRVSRAMACCFAIL    5
+#define V_SRVSRAMACCFAIL(x) ((x) << S_SRVSRAMACCFAIL)
+#define F_SRVSRAMACCFAIL    V_SRVSRAMACCFAIL(1U)
+
+#define S_CLIPTCAMACCFAIL    4
+#define V_CLIPTCAMACCFAIL(x) ((x) << S_CLIPTCAMACCFAIL)
+#define F_CLIPTCAMACCFAIL    V_CLIPTCAMACCFAIL(1U)
+
+#define S_T6_UNKNOWNCMD    3
+#define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
+#define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)
+
+#define S_T6_LIP0    2
+#define V_T6_LIP0(x) ((x) << S_T6_LIP0)
+#define F_T6_LIP0    V_T6_LIP0(1U)
+
+#define S_T6_LIPMISS    1
+#define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
+#define F_T6_LIPMISS    V_T6_LIPMISS(1U)
+
+#define S_PIPELINEERR    0
+#define V_PIPELINEERR(x) ((x) << S_PIPELINEERR)
+#define F_PIPELINEERR    V_PIPELINEERR(1U)
+
 #define A_LE_DB_INT_CAUSE 0x19c3c
+
+#define S_T6_ACTRGNFULL    21
+#define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
+#define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)
+
+#define S_T6_ACTCNTIPV6TZERO    20
+#define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
+#define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)
+
+#define S_T6_ACTCNTIPV4TZERO    19
+#define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
+#define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)
+
+#define S_T6_ACTCNTIPV6ZERO    18
+#define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
+#define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)
+
+#define S_T6_ACTCNTIPV4ZERO    17
+#define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
+#define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)
+
+#define S_T6_UNKNOWNCMD    3
+#define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
+#define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)
+
+#define S_T6_LIP0    2
+#define V_T6_LIP0(x) ((x) << S_T6_LIP0)
+#define F_T6_LIP0    V_T6_LIP0(1U)
+
+#define S_T6_LIPMISS    1
+#define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
+#define F_T6_LIPMISS    V_T6_LIPMISS(1U)
+
 #define A_LE_DB_INT_TID 0x19c40
 
 #define S_INTTID    0
@@ -28020,6 +39053,18 @@
 #define V_INTTID(x) ((x) << S_INTTID)
 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
 
+#define A_LE_DB_DBG_MATCH_CMD_IDX_MASK 0x19c40
+
+#define S_CMD_CMP_MASK    20
+#define M_CMD_CMP_MASK    0x1fU
+#define V_CMD_CMP_MASK(x) ((x) << S_CMD_CMP_MASK)
+#define G_CMD_CMP_MASK(x) (((x) >> S_CMD_CMP_MASK) & M_CMD_CMP_MASK)
+
+#define S_TID_CMP_MASK    0
+#define M_TID_CMP_MASK    0xfffffU
+#define V_TID_CMP_MASK(x) ((x) << S_TID_CMP_MASK)
+#define G_TID_CMP_MASK(x) (((x) >> S_TID_CMP_MASK) & M_TID_CMP_MASK)
+
 #define A_LE_DB_INT_PTID 0x19c44
 
 #define S_INTPTID    0
@@ -28027,6 +39072,18 @@
 #define V_INTPTID(x) ((x) << S_INTPTID)
 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
 
+#define A_LE_DB_DBG_MATCH_CMD_IDX_DATA 0x19c44
+
+#define S_CMD_CMP    20
+#define M_CMD_CMP    0x1fU
+#define V_CMD_CMP(x) ((x) << S_CMD_CMP)
+#define G_CMD_CMP(x) (((x) >> S_CMD_CMP) & M_CMD_CMP)
+
+#define S_TID_CMP    0
+#define M_TID_CMP    0xfffffU
+#define V_TID_CMP(x) ((x) << S_TID_CMP)
+#define G_TID_CMP(x) (((x) >> S_TID_CMP) & M_TID_CMP)
+
 #define A_LE_DB_INT_INDEX 0x19c48
 
 #define S_INTINDEX    0
@@ -28034,6 +39091,23 @@
 #define V_INTINDEX(x) ((x) << S_INTINDEX)
 #define G_INTINDEX(x) (((x) >> S_INTINDEX) & M_INTINDEX)
 
+#define A_LE_DB_ERR_CMD_TID 0x19c48
+
+#define S_ERR_CID    22
+#define M_ERR_CID    0xffU
+#define V_ERR_CID(x) ((x) << S_ERR_CID)
+#define G_ERR_CID(x) (((x) >> S_ERR_CID) & M_ERR_CID)
+
+#define S_ERR_PROT    20
+#define M_ERR_PROT    0x3U
+#define V_ERR_PROT(x) ((x) << S_ERR_PROT)
+#define G_ERR_PROT(x) (((x) >> S_ERR_PROT) & M_ERR_PROT)
+
+#define S_ERR_TID    0
+#define M_ERR_TID    0xfffffU
+#define V_ERR_TID(x) ((x) << S_ERR_TID)
+#define G_ERR_TID(x) (((x) >> S_ERR_TID) & M_ERR_TID)
+
 #define A_LE_DB_INT_CMD 0x19c4c
 
 #define S_INTCMD    0
@@ -28043,6 +39117,132 @@
 
 #define A_LE_DB_MASK_IPV4 0x19c50
 #define A_LE_T5_DB_MASK_IPV4 0x19c50
+#define A_LE_DB_DBG_MATCH_DATA_MASK 0x19c50
+#define A_LE_DB_MAX_NUM_HASH_ENTRIES 0x19c70
+
+#define S_MAX_HASH_ENTS    0
+#define M_MAX_HASH_ENTS    0xfffffU
+#define V_MAX_HASH_ENTS(x) ((x) << S_MAX_HASH_ENTS)
+#define G_MAX_HASH_ENTS(x) (((x) >> S_MAX_HASH_ENTS) & M_MAX_HASH_ENTS)
+
+#define A_LE_DB_RSP_CODE_0 0x19c74
+
+#define S_SUCCESS    25
+#define M_SUCCESS    0x1fU
+#define V_SUCCESS(x) ((x) << S_SUCCESS)
+#define G_SUCCESS(x) (((x) >> S_SUCCESS) & M_SUCCESS)
+
+#define S_TCAM_ACTV_SUCC    20
+#define M_TCAM_ACTV_SUCC    0x1fU
+#define V_TCAM_ACTV_SUCC(x) ((x) << S_TCAM_ACTV_SUCC)
+#define G_TCAM_ACTV_SUCC(x) (((x) >> S_TCAM_ACTV_SUCC) & M_TCAM_ACTV_SUCC)
+
+#define S_HASH_ACTV_SUCC    15
+#define M_HASH_ACTV_SUCC    0x1fU
+#define V_HASH_ACTV_SUCC(x) ((x) << S_HASH_ACTV_SUCC)
+#define G_HASH_ACTV_SUCC(x) (((x) >> S_HASH_ACTV_SUCC) & M_HASH_ACTV_SUCC)
+
+#define S_TCAM_SRVR_HIT    10
+#define M_TCAM_SRVR_HIT    0x1fU
+#define V_TCAM_SRVR_HIT(x) ((x) << S_TCAM_SRVR_HIT)
+#define G_TCAM_SRVR_HIT(x) (((x) >> S_TCAM_SRVR_HIT) & M_TCAM_SRVR_HIT)
+
+#define S_SRAM_SRVR_HIT    5
+#define M_SRAM_SRVR_HIT    0x1fU
+#define V_SRAM_SRVR_HIT(x) ((x) << S_SRAM_SRVR_HIT)
+#define G_SRAM_SRVR_HIT(x) (((x) >> S_SRAM_SRVR_HIT) & M_SRAM_SRVR_HIT)
+
+#define S_TCAM_ACTV_HIT    0
+#define M_TCAM_ACTV_HIT    0x1fU
+#define V_TCAM_ACTV_HIT(x) ((x) << S_TCAM_ACTV_HIT)
+#define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT)
+
+#define A_LE_DB_RSP_CODE_1 0x19c78
+
+#define S_HASH_ACTV_HIT    25
+#define M_HASH_ACTV_HIT    0x1fU
+#define V_HASH_ACTV_HIT(x) ((x) << S_HASH_ACTV_HIT)
+#define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT)
+
+#define S_T6_MISS    20
+#define M_T6_MISS    0x1fU
+#define V_T6_MISS(x) ((x) << S_T6_MISS)
+#define G_T6_MISS(x) (((x) >> S_T6_MISS) & M_T6_MISS)
+
+#define S_NORM_FILT_HIT    15
+#define M_NORM_FILT_HIT    0x1fU
+#define V_NORM_FILT_HIT(x) ((x) << S_NORM_FILT_HIT)
+#define G_NORM_FILT_HIT(x) (((x) >> S_NORM_FILT_HIT) & M_NORM_FILT_HIT)
+
+#define S_HPRI_FILT_HIT    10
+#define M_HPRI_FILT_HIT    0x1fU
+#define V_HPRI_FILT_HIT(x) ((x) << S_HPRI_FILT_HIT)
+#define G_HPRI_FILT_HIT(x) (((x) >> S_HPRI_FILT_HIT) & M_HPRI_FILT_HIT)
+
+#define S_ACTV_OPEN_ERR    5
+#define M_ACTV_OPEN_ERR    0x1fU
+#define V_ACTV_OPEN_ERR(x) ((x) << S_ACTV_OPEN_ERR)
+#define G_ACTV_OPEN_ERR(x) (((x) >> S_ACTV_OPEN_ERR) & M_ACTV_OPEN_ERR)
+
+#define S_ACTV_FULL_ERR    0
+#define M_ACTV_FULL_ERR    0x1fU
+#define V_ACTV_FULL_ERR(x) ((x) << S_ACTV_FULL_ERR)
+#define G_ACTV_FULL_ERR(x) (((x) >> S_ACTV_FULL_ERR) & M_ACTV_FULL_ERR)
+
+#define A_LE_DB_RSP_CODE_2 0x19c7c
+
+#define S_SRCH_RGN_HIT    25
+#define M_SRCH_RGN_HIT    0x1fU
+#define V_SRCH_RGN_HIT(x) ((x) << S_SRCH_RGN_HIT)
+#define G_SRCH_RGN_HIT(x) (((x) >> S_SRCH_RGN_HIT) & M_SRCH_RGN_HIT)
+
+#define S_CLIP_FAIL    20
+#define M_CLIP_FAIL    0x1fU
+#define V_CLIP_FAIL(x) ((x) << S_CLIP_FAIL)
+#define G_CLIP_FAIL(x) (((x) >> S_CLIP_FAIL) & M_CLIP_FAIL)
+
+#define S_LIP_ZERO_ERR    15
+#define M_LIP_ZERO_ERR    0x1fU
+#define V_LIP_ZERO_ERR(x) ((x) << S_LIP_ZERO_ERR)
+#define G_LIP_ZERO_ERR(x) (((x) >> S_LIP_ZERO_ERR) & M_LIP_ZERO_ERR)
+
+#define S_UNKNOWN_CMD    10
+#define M_UNKNOWN_CMD    0x1fU
+#define V_UNKNOWN_CMD(x) ((x) << S_UNKNOWN_CMD)
+#define G_UNKNOWN_CMD(x) (((x) >> S_UNKNOWN_CMD) & M_UNKNOWN_CMD)
+
+#define S_CMD_TID_ERR    5
+#define M_CMD_TID_ERR    0x1fU
+#define V_CMD_TID_ERR(x) ((x) << S_CMD_TID_ERR)
+#define G_CMD_TID_ERR(x) (((x) >> S_CMD_TID_ERR) & M_CMD_TID_ERR)
+
+#define S_INTERNAL_ERR    0
+#define M_INTERNAL_ERR    0x1fU
+#define V_INTERNAL_ERR(x) ((x) << S_INTERNAL_ERR)
+#define G_INTERNAL_ERR(x) (((x) >> S_INTERNAL_ERR) & M_INTERNAL_ERR)
+
+#define A_LE_DB_RSP_CODE_3 0x19c80
+
+#define S_SRAM_SRVR_HIT_ACTF    25
+#define M_SRAM_SRVR_HIT_ACTF    0x1fU
+#define V_SRAM_SRVR_HIT_ACTF(x) ((x) << S_SRAM_SRVR_HIT_ACTF)
+#define G_SRAM_SRVR_HIT_ACTF(x) (((x) >> S_SRAM_SRVR_HIT_ACTF) & M_SRAM_SRVR_HIT_ACTF)
+
+#define S_TCAM_SRVR_HIT_ACTF    20
+#define M_TCAM_SRVR_HIT_ACTF    0x1fU
+#define V_TCAM_SRVR_HIT_ACTF(x) ((x) << S_TCAM_SRVR_HIT_ACTF)
+#define G_TCAM_SRVR_HIT_ACTF(x) (((x) >> S_TCAM_SRVR_HIT_ACTF) & M_TCAM_SRVR_HIT_ACTF)
+
+#define S_INVLDRD    15
+#define M_INVLDRD    0x1fU
+#define V_INVLDRD(x) ((x) << S_INVLDRD)
+#define G_INVLDRD(x) (((x) >> S_INVLDRD) & M_INVLDRD)
+
+#define S_TUPLZERO    10
+#define M_TUPLZERO    0x1fU
+#define V_TUPLZERO(x) ((x) << S_TUPLZERO)
+#define G_TUPLZERO(x) (((x) >> S_TUPLZERO) & M_TUPLZERO)
+
 #define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
 #define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
 #define A_LE_ACT_CNT_THRSH 0x19c9c
@@ -28053,8 +39253,19 @@
 #define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)
 
 #define A_LE_DB_MASK_IPV6 0x19ca0
+#define A_LE_DB_DBG_MATCH_DATA 0x19ca0
 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
 
+#define S_T4_RSPCNT    16
+#define M_T4_RSPCNT    0xffffU
+#define V_T4_RSPCNT(x) ((x) << S_T4_RSPCNT)
+#define G_T4_RSPCNT(x) (((x) >> S_T4_RSPCNT) & M_T4_RSPCNT)
+
+#define S_T4_REQCNT    0
+#define M_T4_REQCNT    0xffffU
+#define V_T4_REQCNT(x) ((x) << S_T4_REQCNT)
+#define G_T4_REQCNT(x) (((x) >> S_T4_REQCNT) & M_T4_REQCNT)
+
 #define S_RSPCNTLE    16
 #define M_RSPCNTLE    0xffffU
 #define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
@@ -28122,6 +39333,14 @@
 #define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
 #define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)
 
+#define S_DBGICMDMSKREAD    21
+#define V_DBGICMDMSKREAD(x) ((x) << S_DBGICMDMSKREAD)
+#define F_DBGICMDMSKREAD    V_DBGICMDMSKREAD(1U)
+
+#define S_DBGICMDWRITE    17
+#define V_DBGICMDWRITE(x) ((x) << S_DBGICMDWRITE)
+#define F_DBGICMDWRITE    V_DBGICMDWRITE(1U)
+
 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
 
 #define S_DBGICMD    20
@@ -28134,6 +39353,13 @@
 #define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
 #define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)
 
+#define A_LE_DB_DBGI_REQ_CMD 0x19cf4
+
+#define S_DBGITID    0
+#define M_DBGITID    0xfffffU
+#define V_DBGITID(x) ((x) << S_DBGITID)
+#define G_DBGITID(x) (((x) >> S_DBGITID) & M_DBGITID)
+
 #define A_LE_PERR_ENABLE 0x19cf8
 
 #define S_REQQUEUE    1
@@ -28160,6 +39386,23 @@
 #define V_TCAMLE(x) ((x) << S_TCAMLE)
 #define F_TCAMLE    V_TCAMLE(1U)
 
+#define S_BKCHKPERIOD    22
+#define M_BKCHKPERIOD    0x3ffU
+#define V_BKCHKPERIOD(x) ((x) << S_BKCHKPERIOD)
+#define G_BKCHKPERIOD(x) (((x) >> S_BKCHKPERIOD) & M_BKCHKPERIOD)
+
+#define S_TCAMBKCHKEN    21
+#define V_TCAMBKCHKEN(x) ((x) << S_TCAMBKCHKEN)
+#define F_TCAMBKCHKEN    V_TCAMBKCHKEN(1U)
+
+#define S_T6_CLCAMFIFOERR    2
+#define V_T6_CLCAMFIFOERR(x) ((x) << S_T6_CLCAMFIFOERR)
+#define F_T6_CLCAMFIFOERR    V_T6_CLCAMFIFOERR(1U)
+
+#define S_T6_HASHTBLMEMCRCERR    1
+#define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR)
+#define F_T6_HASHTBLMEMCRCERR    V_T6_HASHTBLMEMCRCERR(1U)
+
 #define A_LE_SPARE 0x19cfc
 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
@@ -28191,6 +39434,16 @@
 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
 #define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
 
+#define S_DBGIRSPTID    12
+#define M_DBGIRSPTID    0xfffffU
+#define V_DBGIRSPTID(x) ((x) << S_DBGIRSPTID)
+#define G_DBGIRSPTID(x) (((x) >> S_DBGIRSPTID) & M_DBGIRSPTID)
+
+#define S_DBGIRSPLEARN    2
+#define V_DBGIRSPLEARN(x) ((x) << S_DBGIRSPLEARN)
+#define F_DBGIRSPLEARN    V_DBGIRSPLEARN(1U)
+
+#define A_LE_DBG_SEL 0x19d98
 #define A_LE_DB_DBGI_RSP_DATA 0x19da0
 #define A_LE_DB_DBGI_RSP_LAST_CMD 0x19de4
 
@@ -28230,6 +39483,13 @@
 #define V_SVRBASE_ADDR(x) ((x) << S_SVRBASE_ADDR)
 #define G_SVRBASE_ADDR(x) (((x) >> S_SVRBASE_ADDR) & M_SVRBASE_ADDR)
 
+#define A_LE_DB_TCAM_TID_BASE 0x19df0
+
+#define S_TCAM_TID_BASE    0
+#define M_TCAM_TID_BASE    0xfffffU
+#define V_TCAM_TID_BASE(x) ((x) << S_TCAM_TID_BASE)
+#define G_TCAM_TID_BASE(x) (((x) >> S_TCAM_TID_BASE) & M_TCAM_TID_BASE)
+
 #define A_LE_DB_FTID_FLTRBASE 0x19df4
 
 #define S_FLTRBASE_ADDR    2
@@ -28237,6 +39497,13 @@
 #define V_FLTRBASE_ADDR(x) ((x) << S_FLTRBASE_ADDR)
 #define G_FLTRBASE_ADDR(x) (((x) >> S_FLTRBASE_ADDR) & M_FLTRBASE_ADDR)
 
+#define A_LE_DB_CLCAM_TID_BASE 0x19df4
+
+#define S_CLCAM_TID_BASE    0
+#define M_CLCAM_TID_BASE    0xfffffU
+#define V_CLCAM_TID_BASE(x) ((x) << S_CLCAM_TID_BASE)
+#define G_CLCAM_TID_BASE(x) (((x) >> S_CLCAM_TID_BASE) & M_CLCAM_TID_BASE)
+
 #define A_LE_DB_TID_HASHBASE 0x19df8
 
 #define S_HASHBASE_ADDR    2
@@ -28244,6 +39511,13 @@
 #define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
 #define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)
 
+#define A_T6_LE_DB_HASH_TID_BASE 0x19df8
+
+#define S_HASH_TID_BASE    0
+#define M_HASH_TID_BASE    0xfffffU
+#define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE)
+#define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE)
+
 #define A_LE_PERR_INJECT 0x19dfc
 
 #define S_LEMEMSEL    1
@@ -28251,6 +39525,13 @@
 #define V_LEMEMSEL(x) ((x) << S_LEMEMSEL)
 #define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL)
 
+#define A_LE_DB_SSRAM_TID_BASE 0x19dfc
+
+#define S_SSRAM_TID_BASE    0
+#define M_SSRAM_TID_BASE    0xfffffU
+#define V_SSRAM_TID_BASE(x) ((x) << S_SSRAM_TID_BASE)
+#define G_SSRAM_TID_BASE(x) (((x) >> S_SSRAM_TID_BASE) & M_SSRAM_TID_BASE)
+
 #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
 #define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00
 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
@@ -28258,13 +39539,18 @@
 #define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0
 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
 #define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
+#define A_T6_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
 #define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
+#define A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 0x19ee4
 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
+#define A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 0x19ef0
 #define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8
+#define A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 0x19f04
 #define A_LE_DEBUG_LA_CONFIG 0x19f20
 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24
 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
+#define A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 0x19f28
 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
 #define A_LE_DEBUG_LA_SELECTOR 0x19f34
@@ -28283,6 +39569,20 @@
 #define V_SRVRINIT(x) ((x) << S_SRVRINIT)
 #define F_SRVRINIT    V_SRVRINIT(1U)
 
+#define A_LE_DB_SRVR_SRAM_CONFIG 0x19f34
+
+#define S_PRI_HFILT    4
+#define V_PRI_HFILT(x) ((x) << S_PRI_HFILT)
+#define F_PRI_HFILT    V_PRI_HFILT(1U)
+
+#define S_PRI_SRVR    3
+#define V_PRI_SRVR(x) ((x) << S_PRI_SRVR)
+#define F_PRI_SRVR    V_PRI_SRVR(1U)
+
+#define S_PRI_FILT    2
+#define V_PRI_FILT(x) ((x) << S_PRI_FILT)
+#define F_PRI_FILT    V_PRI_FILT(1U)
+
 #define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
 #define A_LE_SRVR_VF_SRCH_TABLE 0x19f38
 
@@ -28305,7 +39605,38 @@
 #define V_SRCHLADDR(x) ((x) << S_SRCHLADDR)
 #define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR)
 
+#define A_LE_DB_SRVR_VF_SRCH_TABLE_CTRL 0x19f38
+
+#define S_VFLUTBUSY    10
+#define V_VFLUTBUSY(x) ((x) << S_VFLUTBUSY)
+#define F_VFLUTBUSY    V_VFLUTBUSY(1U)
+
+#define S_VFLUTSTART    9
+#define V_VFLUTSTART(x) ((x) << S_VFLUTSTART)
+#define F_VFLUTSTART    V_VFLUTSTART(1U)
+
+#define S_T6_RDWR    8
+#define V_T6_RDWR(x) ((x) << S_T6_RDWR)
+#define F_T6_RDWR    V_T6_RDWR(1U)
+
+#define S_T6_VFINDEX    0
+#define M_T6_VFINDEX    0xffU
+#define V_T6_VFINDEX(x) ((x) << S_T6_VFINDEX)
+#define G_T6_VFINDEX(x) (((x) >> S_T6_VFINDEX) & M_T6_VFINDEX)
+
 #define A_LE_MA_DEBUG_LA_DATA 0x19f3c
+#define A_LE_DB_SRVR_VF_SRCH_TABLE_DATA 0x19f3c
+
+#define S_T6_SRCHHADDR    12
+#define M_T6_SRCHHADDR    0xfffU
+#define V_T6_SRCHHADDR(x) ((x) << S_T6_SRCHHADDR)
+#define G_T6_SRCHHADDR(x) (((x) >> S_T6_SRCHHADDR) & M_T6_SRCHHADDR)
+
+#define S_T6_SRCHLADDR    0
+#define M_T6_SRCHLADDR    0xfffU
+#define V_T6_SRCHLADDR(x) ((x) << S_T6_SRCHLADDR)
+#define G_T6_SRCHLADDR(x) (((x) >> S_T6_SRCHLADDR) & M_T6_SRCHLADDR)
+
 #define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
 #define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40
 #define A_LE_HASH_DEBUG_LA_DATA 0x19f44
@@ -29465,6 +40796,11 @@
 #define V_RXSOP(x) ((x) << S_RXSOP)
 #define G_RXSOP(x) (((x) >> S_RXSOP) & M_RXSOP)
 
+#define S_T4_RXEOP    0
+#define M_T4_RXEOP    0xffU
+#define V_T4_RXEOP(x) ((x) << S_T4_RXEOP)
+#define G_T4_RXEOP(x) (((x) >> S_T4_RXEOP) & M_T4_RXEOP)
+
 #define A_XGMAC_PORT_LINK_STATUS 0x1034
 
 #define S_REMFLT    3
@@ -32830,6 +44166,10 @@
 #define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
 #define F_QUEBAREADDR    V_QUEBAREADDR(1U)
 
+#define S_QUE1KEN    6
+#define V_QUE1KEN(x) ((x) << S_QUE1KEN)
+#define F_QUE1KEN    V_QUE1KEN(1U)
+
 #define A_UP_IBQ_0_REALADDR 0xd4
 
 #define S_QUERDADDRWRAP    31
@@ -32969,6 +44309,11 @@
 #define V_T5_UPRID(x) ((x) << S_T5_UPRID)
 #define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID)
 
+#define S_T6_UPRID    0
+#define M_T6_UPRID    0x1ffU
+#define V_T6_UPRID(x) ((x) << S_T6_UPRID)
+#define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID)
+
 #define A_UP_UP_SELF_CONTROL 0x14c
 
 #define S_UPSELFRESET    0
@@ -33034,6 +44379,18 @@
 #define V_TSCHCHNLCCNT(x) ((x) << S_TSCHCHNLCCNT)
 #define G_TSCHCHNLCCNT(x) (((x) >> S_TSCHCHNLCCNT) & M_TSCHCHNLCCNT)
 
+#define S_TSCHCHNLCHDIS    31
+#define V_TSCHCHNLCHDIS(x) ((x) << S_TSCHCHNLCHDIS)
+#define F_TSCHCHNLCHDIS    V_TSCHCHNLCHDIS(1U)
+
+#define S_TSCHCHNLWDIS    30
+#define V_TSCHCHNLWDIS(x) ((x) << S_TSCHCHNLWDIS)
+#define F_TSCHCHNLWDIS    V_TSCHCHNLWDIS(1U)
+
+#define S_TSCHCHNLCLDIS    29
+#define V_TSCHCHNLCLDIS(x) ((x) << S_TSCHCHNLCLDIS)
+#define F_TSCHCHNLCLDIS    V_TSCHCHNLCLDIS(1U)
+
 #define A_UP_UPLADBGPCCHKDATA_0 0x240
 #define A_UP_UPLADBGPCCHKMASK_0 0x244
 #define A_UP_UPLADBGPCCHKDATA_1 0x250
@@ -33165,6 +44522,14 @@
 #define V_PREFEN(x) ((x) << S_PREFEN)
 #define F_PREFEN    V_PREFEN(1U)
 
+#define S_DISSLOWTIMEOUT    14
+#define V_DISSLOWTIMEOUT(x) ((x) << S_DISSLOWTIMEOUT)
+#define F_DISSLOWTIMEOUT    V_DISSLOWTIMEOUT(1U)
+
+#define S_INTLRSPEN    9
+#define V_INTLRSPEN(x) ((x) << S_INTLRSPEN)
+#define F_INTLRSPEN    V_INTLRSPEN(1U)
+
 #define A_CIM_CTL_PREFADDR 0x4
 #define A_CIM_CTL_ALLOCADDR 0x8
 #define A_CIM_CTL_INVLDTADDR 0xc
@@ -33262,6 +44627,10 @@
 #define V_TSCHNRESET(x) ((x) << S_TSCHNRESET)
 #define F_TSCHNRESET    V_TSCHNRESET(1U)
 
+#define S_T6_MIN_MAX_EN    29
+#define V_T6_MIN_MAX_EN(x) ((x) << S_T6_MIN_MAX_EN)
+#define F_T6_MIN_MAX_EN    V_T6_MIN_MAX_EN(1U)
+
 #define A_CIM_CTL_TSCH_CHNLN_TICK 0x904
 
 #define S_TSCHNLTICK    0
@@ -33269,6 +44638,72 @@
 #define V_TSCHNLTICK(x) ((x) << S_TSCHNLTICK)
 #define G_TSCHNLTICK(x) (((x) >> S_TSCHNLTICK) & M_TSCHNLTICK)
 
+#define A_CIM_CTL_TSCH_CHNLN_CLASS_RATECTL 0x904
+
+#define S_TSC15RATECTL    15
+#define V_TSC15RATECTL(x) ((x) << S_TSC15RATECTL)
+#define F_TSC15RATECTL    V_TSC15RATECTL(1U)
+
+#define S_TSC14RATECTL    14
+#define V_TSC14RATECTL(x) ((x) << S_TSC14RATECTL)
+#define F_TSC14RATECTL    V_TSC14RATECTL(1U)
+
+#define S_TSC13RATECTL    13
+#define V_TSC13RATECTL(x) ((x) << S_TSC13RATECTL)
+#define F_TSC13RATECTL    V_TSC13RATECTL(1U)
+
+#define S_TSC12RATECTL    12
+#define V_TSC12RATECTL(x) ((x) << S_TSC12RATECTL)
+#define F_TSC12RATECTL    V_TSC12RATECTL(1U)
+
+#define S_TSC11RATECTL    11
+#define V_TSC11RATECTL(x) ((x) << S_TSC11RATECTL)
+#define F_TSC11RATECTL    V_TSC11RATECTL(1U)
+
+#define S_TSC10RATECTL    10
+#define V_TSC10RATECTL(x) ((x) << S_TSC10RATECTL)
+#define F_TSC10RATECTL    V_TSC10RATECTL(1U)
+
+#define S_TSC9RATECTL    9
+#define V_TSC9RATECTL(x) ((x) << S_TSC9RATECTL)
+#define F_TSC9RATECTL    V_TSC9RATECTL(1U)
+
+#define S_TSC8RATECTL    8
+#define V_TSC8RATECTL(x) ((x) << S_TSC8RATECTL)
+#define F_TSC8RATECTL    V_TSC8RATECTL(1U)
+
+#define S_TSC7RATECTL    7
+#define V_TSC7RATECTL(x) ((x) << S_TSC7RATECTL)
+#define F_TSC7RATECTL    V_TSC7RATECTL(1U)
+
+#define S_TSC6RATECTL    6
+#define V_TSC6RATECTL(x) ((x) << S_TSC6RATECTL)
+#define F_TSC6RATECTL    V_TSC6RATECTL(1U)
+
+#define S_TSC5RATECTL    5
+#define V_TSC5RATECTL(x) ((x) << S_TSC5RATECTL)
+#define F_TSC5RATECTL    V_TSC5RATECTL(1U)
+
+#define S_TSC4RATECTL    4
+#define V_TSC4RATECTL(x) ((x) << S_TSC4RATECTL)
+#define F_TSC4RATECTL    V_TSC4RATECTL(1U)
+
+#define S_TSC3RATECTL    3
+#define V_TSC3RATECTL(x) ((x) << S_TSC3RATECTL)
+#define F_TSC3RATECTL    V_TSC3RATECTL(1U)
+
+#define S_TSC2RATECTL    2
+#define V_TSC2RATECTL(x) ((x) << S_TSC2RATECTL)
+#define F_TSC2RATECTL    V_TSC2RATECTL(1U)
+
+#define S_TSC1RATECTL    1
+#define V_TSC1RATECTL(x) ((x) << S_TSC1RATECTL)
+#define F_TSC1RATECTL    V_TSC1RATECTL(1U)
+
+#define S_TSC0RATECTL    0
+#define V_TSC0RATECTL(x) ((x) << S_TSC0RATECTL)
+#define F_TSC0RATECTL    V_TSC0RATECTL(1U)
+
 #define A_CIM_CTL_TSCH_CHNLN_CLASS_ENABLE_A 0x908
 
 #define S_TSC15WRREN    31
@@ -33416,6 +44851,15 @@
 #define V_TSCHNLRATEL(x) ((x) << S_TSCHNLRATEL)
 #define G_TSCHNLRATEL(x) (((x) >> S_TSCHNLRATEL) & M_TSCHNLRATEL)
 
+#define S_TSCHNLRATEPROT    30
+#define V_TSCHNLRATEPROT(x) ((x) << S_TSCHNLRATEPROT)
+#define F_TSCHNLRATEPROT    V_TSCHNLRATEPROT(1U)
+
+#define S_T6_TSCHNLRATEL    0
+#define M_T6_TSCHNLRATEL    0x3fffffffU
+#define V_T6_TSCHNLRATEL(x) ((x) << S_T6_TSCHNLRATEL)
+#define G_T6_TSCHNLRATEL(x) (((x) >> S_T6_TSCHNLRATEL) & M_T6_TSCHNLRATEL)
+
 #define A_CIM_CTL_TSCH_CHNLN_RATE_PROPERTIES 0x914
 
 #define S_TSCHNLRMAX    16
@@ -33428,6 +44872,16 @@
 #define V_TSCHNLRINCR(x) ((x) << S_TSCHNLRINCR)
 #define G_TSCHNLRINCR(x) (((x) >> S_TSCHNLRINCR) & M_TSCHNLRINCR)
 
+#define S_TSCHNLRTSEL    14
+#define M_TSCHNLRTSEL    0x3U
+#define V_TSCHNLRTSEL(x) ((x) << S_TSCHNLRTSEL)
+#define G_TSCHNLRTSEL(x) (((x) >> S_TSCHNLRTSEL) & M_TSCHNLRTSEL)
+
+#define S_T6_TSCHNLRINCR    0
+#define M_T6_TSCHNLRINCR    0x3fffU
+#define V_T6_TSCHNLRINCR(x) ((x) << S_T6_TSCHNLRINCR)
+#define G_T6_TSCHNLRINCR(x) (((x) >> S_T6_TSCHNLRINCR) & M_T6_TSCHNLRINCR)
+
 #define A_CIM_CTL_TSCH_CHNLN_WRR 0x918
 #define A_CIM_CTL_TSCH_CHNLN_WEIGHT 0x91c
 
@@ -33447,6 +44901,10 @@
 #define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL)
 #define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL)
 
+#define S_TSCCLRATEPROT    30
+#define V_TSCCLRATEPROT(x) ((x) << S_TSCCLRATEPROT)
+#define F_TSCCLRATEPROT    V_TSCCLRATEPROT(1U)
+
 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
 
 #define S_TSCCLRMAX    16
@@ -33459,6 +44917,16 @@
 #define V_TSCCLRINCR(x) ((x) << S_TSCCLRINCR)
 #define G_TSCCLRINCR(x) (((x) >> S_TSCCLRINCR) & M_TSCCLRINCR)
 
+#define S_TSCCLRTSEL    14
+#define M_TSCCLRTSEL    0x3U
+#define V_TSCCLRTSEL(x) ((x) << S_TSCCLRTSEL)
+#define G_TSCCLRTSEL(x) (((x) >> S_TSCCLRTSEL) & M_TSCCLRTSEL)
+
+#define S_T6_TSCCLRINCR    0
+#define M_T6_TSCCLRINCR    0x3fffU
+#define V_T6_TSCCLRINCR(x) ((x) << S_T6_TSCCLRINCR)
+#define G_T6_TSCCLRINCR(x) (((x) >> S_T6_TSCCLRINCR) & M_T6_TSCCLRINCR)
+
 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WRR 0x928
 
 #define S_TSCCLWRRNEG    31
@@ -33470,6 +44938,10 @@
 #define V_TSCCLWRR(x) ((x) << S_TSCCLWRR)
 #define G_TSCCLWRR(x) (((x) >> S_TSCCLWRR) & M_TSCCLWRR)
 
+#define S_TSCCLWRRPROT    30
+#define V_TSCCLWRRPROT(x) ((x) << S_TSCCLWRRPROT)
+#define F_TSCCLWRRPROT    V_TSCCLWRRPROT(1U)
+
 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WEIGHT 0x92c
 
 #define S_TSCCLWEIGHT    0
@@ -33477,14 +44949,33 @@
 #define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT)
 #define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT)
 
+#define S_PAUSEVECSEL    28
+#define M_PAUSEVECSEL    0x3U
+#define V_PAUSEVECSEL(x) ((x) << S_PAUSEVECSEL)
+#define G_PAUSEVECSEL(x) (((x) >> S_PAUSEVECSEL) & M_PAUSEVECSEL)
+
+#define S_MPSPAUSEMASK    20
+#define M_MPSPAUSEMASK    0xffU
+#define V_MPSPAUSEMASK(x) ((x) << S_MPSPAUSEMASK)
+#define G_MPSPAUSEMASK(x) (((x) >> S_MPSPAUSEMASK) & M_MPSPAUSEMASK)
+
+#define A_CIM_CTL_TSCH_TICK0 0xd80
 #define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84
+#define A_CIM_CTL_TSCH_TICK1 0xd84
 #define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88
+#define A_CIM_CTL_TSCH_TICK2 0xd88
 #define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c
+#define A_CIM_CTL_TSCH_TICK3 0xd8c
 #define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
+#define A_T6_CIM_CTL_MAILBOX_PF0_CTL 0xd90
 #define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
+#define A_T6_CIM_CTL_MAILBOX_PF1_CTL 0xd94
 #define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
+#define A_T6_CIM_CTL_MAILBOX_PF2_CTL 0xd98
 #define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
+#define A_T6_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
 #define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
+#define A_T6_CIM_CTL_MAILBOX_PF4_CTL 0xda0
 #define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
 
 #define S_PF7_OWNER_PL    15
@@ -33551,6 +45042,7 @@
 #define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP)
 #define F_PF0_OWNER_UP    V_PF0_OWNER_UP(1U)
 
+#define A_T6_CIM_CTL_MAILBOX_PF5_CTL 0xda4
 #define A_CIM_CTL_PIO_MST_CONFIG 0xda8
 
 #define S_T5_CTLRID    0
@@ -33558,6 +45050,42 @@
 #define V_T5_CTLRID(x) ((x) << S_T5_CTLRID)
 #define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID)
 
+#define A_T6_CIM_CTL_MAILBOX_PF6_CTL 0xda8
+#define A_T6_CIM_CTL_MAILBOX_PF7_CTL 0xdac
+#define A_T6_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
+#define A_T6_CIM_CTL_PIO_MST_CONFIG 0xdb4
+
+#define S_T6_UPRID    0
+#define M_T6_UPRID    0x1ffU
+#define V_T6_UPRID(x) ((x) << S_T6_UPRID)
+#define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID)
+
+#define A_CIM_CTL_ULP_OBQ0_PAUSE_MASK 0xe00
+#define A_CIM_CTL_ULP_OBQ1_PAUSE_MASK 0xe04
+#define A_CIM_CTL_ULP_OBQ2_PAUSE_MASK 0xe08
+#define A_CIM_CTL_ULP_OBQ3_PAUSE_MASK 0xe0c
+#define A_CIM_CTL_ULP_OBQ_CONFIG 0xe10
+
+#define S_CH1_PRIO_EN    1
+#define V_CH1_PRIO_EN(x) ((x) << S_CH1_PRIO_EN)
+#define F_CH1_PRIO_EN    V_CH1_PRIO_EN(1U)
+
+#define S_CH0_PRIO_EN    0
+#define V_CH0_PRIO_EN(x) ((x) << S_CH0_PRIO_EN)
+#define F_CH0_PRIO_EN    V_CH0_PRIO_EN(1U)
+
+#define A_CIM_CTL_PIF_TIMEOUT 0xe40
+
+#define S_SLOW_TIMEOUT    16
+#define M_SLOW_TIMEOUT    0xffffU
+#define V_SLOW_TIMEOUT(x) ((x) << S_SLOW_TIMEOUT)
+#define G_SLOW_TIMEOUT(x) (((x) >> S_SLOW_TIMEOUT) & M_SLOW_TIMEOUT)
+
+#define S_MA_TIMEOUT    0
+#define M_MA_TIMEOUT    0xffffU
+#define V_MA_TIMEOUT(x) ((x) << S_MA_TIMEOUT)
+#define G_MA_TIMEOUT(x) (((x) >> S_MA_TIMEOUT) & M_MA_TIMEOUT)
+
 /* registers for module MAC */
 #define MAC_BASE_ADDR 0x0
 
@@ -33581,6 +45109,52 @@
 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
 
+#define S_ENA_ERR_RSP    28
+#define V_ENA_ERR_RSP(x) ((x) << S_ENA_ERR_RSP)
+#define F_ENA_ERR_RSP    V_ENA_ERR_RSP(1U)
+
+#define S_DEBUG_CLR    25
+#define V_DEBUG_CLR(x) ((x) << S_DEBUG_CLR)
+#define F_DEBUG_CLR    V_DEBUG_CLR(1U)
+
+#define S_PLL_SEL    23
+#define V_PLL_SEL(x) ((x) << S_PLL_SEL)
+#define F_PLL_SEL    V_PLL_SEL(1U)
+
+#define S_PORT_MAP    20
+#define M_PORT_MAP    0x7U
+#define V_PORT_MAP(x) ((x) << S_PORT_MAP)
+#define G_PORT_MAP(x) (((x) >> S_PORT_MAP) & M_PORT_MAP)
+
+#define S_AEC_PAT_DATA    15
+#define V_AEC_PAT_DATA(x) ((x) << S_AEC_PAT_DATA)
+#define F_AEC_PAT_DATA    V_AEC_PAT_DATA(1U)
+
+#define S_MACCLK_SEL    13
+#define V_MACCLK_SEL(x) ((x) << S_MACCLK_SEL)
+#define F_MACCLK_SEL    V_MACCLK_SEL(1U)
+
+#define S_XGMII_SEL    12
+#define V_XGMII_SEL(x) ((x) << S_XGMII_SEL)
+#define F_XGMII_SEL    V_XGMII_SEL(1U)
+
+#define S_DEBUG_PORT_SEL    10
+#define M_DEBUG_PORT_SEL    0x3U
+#define V_DEBUG_PORT_SEL(x) ((x) << S_DEBUG_PORT_SEL)
+#define G_DEBUG_PORT_SEL(x) (((x) >> S_DEBUG_PORT_SEL) & M_DEBUG_PORT_SEL)
+
+#define S_ENABLE_25G    7
+#define V_ENABLE_25G(x) ((x) << S_ENABLE_25G)
+#define F_ENABLE_25G    V_ENABLE_25G(1U)
+
+#define S_ENABLE_50G    6
+#define V_ENABLE_50G(x) ((x) << S_ENABLE_50G)
+#define F_ENABLE_50G    V_ENABLE_50G(1U)
+
+#define S_DEBUG_TX_RX_SEL    1
+#define V_DEBUG_TX_RX_SEL(x) ((x) << S_DEBUG_TX_RX_SEL)
+#define F_DEBUG_TX_RX_SEL    V_DEBUG_TX_RX_SEL(1U)
+
 #define A_MAC_PORT_RESET_CTRL 0x804
 
 #define S_TWGDSK_HSSC16B    31
@@ -33683,11 +45257,67 @@
 #define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
 #define F_MTIPSD0RXRST    V_MTIPSD0RXRST(1U)
 
+#define S_MAC100G40G_RESET    27
+#define V_MAC100G40G_RESET(x) ((x) << S_MAC100G40G_RESET)
+#define F_MAC100G40G_RESET    V_MAC100G40G_RESET(1U)
+
+#define S_MAC10G1G_RESET    26
+#define V_MAC10G1G_RESET(x) ((x) << S_MAC10G1G_RESET)
+#define F_MAC10G1G_RESET    V_MAC10G1G_RESET(1U)
+
+#define S_PCS1G_RESET    24
+#define V_PCS1G_RESET(x) ((x) << S_PCS1G_RESET)
+#define F_PCS1G_RESET    V_PCS1G_RESET(1U)
+
+#define S_PCS10G_RESET    15
+#define V_PCS10G_RESET(x) ((x) << S_PCS10G_RESET)
+#define F_PCS10G_RESET    V_PCS10G_RESET(1U)
+
+#define S_PCS40G_RESET    14
+#define V_PCS40G_RESET(x) ((x) << S_PCS40G_RESET)
+#define F_PCS40G_RESET    V_PCS40G_RESET(1U)
+
+#define S_PCS100G_RESET    13
+#define V_PCS100G_RESET(x) ((x) << S_PCS100G_RESET)
+#define F_PCS100G_RESET    V_PCS100G_RESET(1U)
+
 #define A_MAC_PORT_LED_CFG 0x808
+
+#define S_LED1_CFG1    14
+#define M_LED1_CFG1    0x3U
+#define V_LED1_CFG1(x) ((x) << S_LED1_CFG1)
+#define G_LED1_CFG1(x) (((x) >> S_LED1_CFG1) & M_LED1_CFG1)
+
+#define S_LED0_CFG1    12
+#define M_LED0_CFG1    0x3U
+#define V_LED0_CFG1(x) ((x) << S_LED0_CFG1)
+#define G_LED0_CFG1(x) (((x) >> S_LED0_CFG1) & M_LED0_CFG1)
+
+#define S_LED1_TLO    11
+#define V_LED1_TLO(x) ((x) << S_LED1_TLO)
+#define F_LED1_TLO    V_LED1_TLO(1U)
+
+#define S_LED1_THI    10
+#define V_LED1_THI(x) ((x) << S_LED1_THI)
+#define F_LED1_THI    V_LED1_THI(1U)
+
+#define S_LED0_TLO    9
+#define V_LED0_TLO(x) ((x) << S_LED0_TLO)
+#define F_LED0_TLO    V_LED0_TLO(1U)
+
+#define S_LED0_THI    8
+#define V_LED0_THI(x) ((x) << S_LED0_THI)
+#define F_LED0_THI    V_LED0_THI(1U)
+
 #define A_MAC_PORT_LED_COUNTHI 0x80c
 #define A_MAC_PORT_LED_COUNTLO 0x810
 #define A_MAC_PORT_CFG3 0x814
 
+#define S_T5_FPGA_PTP_PORT    26
+#define M_T5_FPGA_PTP_PORT    0x3U
+#define V_T5_FPGA_PTP_PORT(x) ((x) << S_T5_FPGA_PTP_PORT)
+#define G_T5_FPGA_PTP_PORT(x) (((x) >> S_T5_FPGA_PTP_PORT) & M_T5_FPGA_PTP_PORT)
+
 #define S_FCSDISCTRL    25
 #define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL)
 #define F_FCSDISCTRL    V_FCSDISCTRL(1U)
@@ -33737,6 +45367,24 @@
 #define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL)
 #define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL)
 
+#define S_REF_CLK_SEL    30
+#define M_REF_CLK_SEL    0x3U
+#define V_REF_CLK_SEL(x) ((x) << S_REF_CLK_SEL)
+#define G_REF_CLK_SEL(x) (((x) >> S_REF_CLK_SEL) & M_REF_CLK_SEL)
+
+#define S_SGMII_SD_SIG_DET    29
+#define V_SGMII_SD_SIG_DET(x) ((x) << S_SGMII_SD_SIG_DET)
+#define F_SGMII_SD_SIG_DET    V_SGMII_SD_SIG_DET(1U)
+
+#define S_SGMII_SGPCS_ENA    28
+#define V_SGMII_SGPCS_ENA(x) ((x) << S_SGMII_SGPCS_ENA)
+#define F_SGMII_SGPCS_ENA    V_SGMII_SGPCS_ENA(1U)
+
+#define S_MAC_FPGA_PTP_PORT    26
+#define M_MAC_FPGA_PTP_PORT    0x3U
+#define V_MAC_FPGA_PTP_PORT(x) ((x) << S_MAC_FPGA_PTP_PORT)
+#define G_MAC_FPGA_PTP_PORT(x) (((x) >> S_MAC_FPGA_PTP_PORT) & M_MAC_FPGA_PTP_PORT)
+
 #define A_MAC_PORT_CFG2 0x818
 
 #define S_T5_AEC_PMA_TX_READY    4
@@ -33749,6 +45397,10 @@
 #define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY)
 #define G_T5_AEC_PMA_RX_READY(x) (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY)
 
+#define S_AN_DATA_CTL    19
+#define V_AN_DATA_CTL(x) ((x) << S_AN_DATA_CTL)
+#define F_AN_DATA_CTL    V_AN_DATA_CTL(1U)
+
 #define A_MAC_PORT_PKT_COUNT 0x81c
 #define A_MAC_PORT_CFG4 0x820
 
@@ -33794,6 +45446,266 @@
 
 #define A_MAC_PORT_MAGIC_MACID_LO 0x824
 #define A_MAC_PORT_MAGIC_MACID_HI 0x828
+#define A_MAC_PORT_MTIP_RESET_CTRL 0x82c
+
+#define S_AN_RESET_SD_TX_CLK    31
+#define V_AN_RESET_SD_TX_CLK(x) ((x) << S_AN_RESET_SD_TX_CLK)
+#define F_AN_RESET_SD_TX_CLK    V_AN_RESET_SD_TX_CLK(1U)
+
+#define S_AN_RESET_SD_RX_CLK    30
+#define V_AN_RESET_SD_RX_CLK(x) ((x) << S_AN_RESET_SD_RX_CLK)
+#define F_AN_RESET_SD_RX_CLK    V_AN_RESET_SD_RX_CLK(1U)
+
+#define S_SGMII_RESET_TX_CLK    29
+#define V_SGMII_RESET_TX_CLK(x) ((x) << S_SGMII_RESET_TX_CLK)
+#define F_SGMII_RESET_TX_CLK    V_SGMII_RESET_TX_CLK(1U)
+
+#define S_SGMII_RESET_RX_CLK    28
+#define V_SGMII_RESET_RX_CLK(x) ((x) << S_SGMII_RESET_RX_CLK)
+#define F_SGMII_RESET_RX_CLK    V_SGMII_RESET_RX_CLK(1U)
+
+#define S_SGMII_RESET_REF_CLK    27
+#define V_SGMII_RESET_REF_CLK(x) ((x) << S_SGMII_RESET_REF_CLK)
+#define F_SGMII_RESET_REF_CLK    V_SGMII_RESET_REF_CLK(1U)
+
+#define S_PCS10G_RESET_XFI_RXCLK    26
+#define V_PCS10G_RESET_XFI_RXCLK(x) ((x) << S_PCS10G_RESET_XFI_RXCLK)
+#define F_PCS10G_RESET_XFI_RXCLK    V_PCS10G_RESET_XFI_RXCLK(1U)
+
+#define S_PCS10G_RESET_XFI_TXCLK    25
+#define V_PCS10G_RESET_XFI_TXCLK(x) ((x) << S_PCS10G_RESET_XFI_TXCLK)
+#define F_PCS10G_RESET_XFI_TXCLK    V_PCS10G_RESET_XFI_TXCLK(1U)
+
+#define S_PCS10G_RESET_SD_TX_CLK    24
+#define V_PCS10G_RESET_SD_TX_CLK(x) ((x) << S_PCS10G_RESET_SD_TX_CLK)
+#define F_PCS10G_RESET_SD_TX_CLK    V_PCS10G_RESET_SD_TX_CLK(1U)
+
+#define S_PCS10G_RESET_SD_RX_CLK    23
+#define V_PCS10G_RESET_SD_RX_CLK(x) ((x) << S_PCS10G_RESET_SD_RX_CLK)
+#define F_PCS10G_RESET_SD_RX_CLK    V_PCS10G_RESET_SD_RX_CLK(1U)
+
+#define S_PCS40G_RESET_RXCLK    22
+#define V_PCS40G_RESET_RXCLK(x) ((x) << S_PCS40G_RESET_RXCLK)
+#define F_PCS40G_RESET_RXCLK    V_PCS40G_RESET_RXCLK(1U)
+
+#define S_PCS40G_RESET_SD_TX_CLK    21
+#define V_PCS40G_RESET_SD_TX_CLK(x) ((x) << S_PCS40G_RESET_SD_TX_CLK)
+#define F_PCS40G_RESET_SD_TX_CLK    V_PCS40G_RESET_SD_TX_CLK(1U)
+
+#define S_PCS40G_RESET_SD0_RX_CLK    20
+#define V_PCS40G_RESET_SD0_RX_CLK(x) ((x) << S_PCS40G_RESET_SD0_RX_CLK)
+#define F_PCS40G_RESET_SD0_RX_CLK    V_PCS40G_RESET_SD0_RX_CLK(1U)
+
+#define S_PCS40G_RESET_SD1_RX_CLK    19
+#define V_PCS40G_RESET_SD1_RX_CLK(x) ((x) << S_PCS40G_RESET_SD1_RX_CLK)
+#define F_PCS40G_RESET_SD1_RX_CLK    V_PCS40G_RESET_SD1_RX_CLK(1U)
+
+#define S_PCS40G_RESET_SD2_RX_CLK    18
+#define V_PCS40G_RESET_SD2_RX_CLK(x) ((x) << S_PCS40G_RESET_SD2_RX_CLK)
+#define F_PCS40G_RESET_SD2_RX_CLK    V_PCS40G_RESET_SD2_RX_CLK(1U)
+
+#define S_PCS40G_RESET_SD3_RX_CLK    17
+#define V_PCS40G_RESET_SD3_RX_CLK(x) ((x) << S_PCS40G_RESET_SD3_RX_CLK)
+#define F_PCS40G_RESET_SD3_RX_CLK    V_PCS40G_RESET_SD3_RX_CLK(1U)
+
+#define S_PCS100G_RESET_CGMII_RXCLK    16
+#define V_PCS100G_RESET_CGMII_RXCLK(x) ((x) << S_PCS100G_RESET_CGMII_RXCLK)
+#define F_PCS100G_RESET_CGMII_RXCLK    V_PCS100G_RESET_CGMII_RXCLK(1U)
+
+#define S_PCS100G_RESET_CGMII_TXCLK    15
+#define V_PCS100G_RESET_CGMII_TXCLK(x) ((x) << S_PCS100G_RESET_CGMII_TXCLK)
+#define F_PCS100G_RESET_CGMII_TXCLK    V_PCS100G_RESET_CGMII_TXCLK(1U)
+
+#define S_PCS100G_RESET_TX_CLK    14
+#define V_PCS100G_RESET_TX_CLK(x) ((x) << S_PCS100G_RESET_TX_CLK)
+#define F_PCS100G_RESET_TX_CLK    V_PCS100G_RESET_TX_CLK(1U)
+
+#define S_PCS100G_RESET_SD0_RX_CLK    13
+#define V_PCS100G_RESET_SD0_RX_CLK(x) ((x) << S_PCS100G_RESET_SD0_RX_CLK)
+#define F_PCS100G_RESET_SD0_RX_CLK    V_PCS100G_RESET_SD0_RX_CLK(1U)
+
+#define S_PCS100G_RESET_SD1_RX_CLK    12
+#define V_PCS100G_RESET_SD1_RX_CLK(x) ((x) << S_PCS100G_RESET_SD1_RX_CLK)
+#define F_PCS100G_RESET_SD1_RX_CLK    V_PCS100G_RESET_SD1_RX_CLK(1U)
+
+#define S_PCS100G_RESET_SD2_RX_CLK    11
+#define V_PCS100G_RESET_SD2_RX_CLK(x) ((x) << S_PCS100G_RESET_SD2_RX_CLK)
+#define F_PCS100G_RESET_SD2_RX_CLK    V_PCS100G_RESET_SD2_RX_CLK(1U)
+
+#define S_PCS100G_RESET_SD3_RX_CLK    10
+#define V_PCS100G_RESET_SD3_RX_CLK(x) ((x) << S_PCS100G_RESET_SD3_RX_CLK)
+#define F_PCS100G_RESET_SD3_RX_CLK    V_PCS100G_RESET_SD3_RX_CLK(1U)
+
+#define S_MAC40G100G_RESET_TXCLK    9
+#define V_MAC40G100G_RESET_TXCLK(x) ((x) << S_MAC40G100G_RESET_TXCLK)
+#define F_MAC40G100G_RESET_TXCLK    V_MAC40G100G_RESET_TXCLK(1U)
+
+#define S_MAC40G100G_RESET_RXCLK    8
+#define V_MAC40G100G_RESET_RXCLK(x) ((x) << S_MAC40G100G_RESET_RXCLK)
+#define F_MAC40G100G_RESET_RXCLK    V_MAC40G100G_RESET_RXCLK(1U)
+
+#define S_MAC40G100G_RESET_FF_TX_CLK    7
+#define V_MAC40G100G_RESET_FF_TX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_TX_CLK)
+#define F_MAC40G100G_RESET_FF_TX_CLK    V_MAC40G100G_RESET_FF_TX_CLK(1U)
+
+#define S_MAC40G100G_RESET_FF_RX_CLK    6
+#define V_MAC40G100G_RESET_FF_RX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_RX_CLK)
+#define F_MAC40G100G_RESET_FF_RX_CLK    V_MAC40G100G_RESET_FF_RX_CLK(1U)
+
+#define S_MAC40G100G_RESET_TS_CLK    5
+#define V_MAC40G100G_RESET_TS_CLK(x) ((x) << S_MAC40G100G_RESET_TS_CLK)
+#define F_MAC40G100G_RESET_TS_CLK    V_MAC40G100G_RESET_TS_CLK(1U)
+
+#define S_MAC1G10G_RESET_RXCLK    4
+#define V_MAC1G10G_RESET_RXCLK(x) ((x) << S_MAC1G10G_RESET_RXCLK)
+#define F_MAC1G10G_RESET_RXCLK    V_MAC1G10G_RESET_RXCLK(1U)
+
+#define S_MAC1G10G_RESET_TXCLK    3
+#define V_MAC1G10G_RESET_TXCLK(x) ((x) << S_MAC1G10G_RESET_TXCLK)
+#define F_MAC1G10G_RESET_TXCLK    V_MAC1G10G_RESET_TXCLK(1U)
+
+#define S_MAC1G10G_RESET_FF_RX_CLK    2
+#define V_MAC1G10G_RESET_FF_RX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_RX_CLK)
+#define F_MAC1G10G_RESET_FF_RX_CLK    V_MAC1G10G_RESET_FF_RX_CLK(1U)
+
+#define S_MAC1G10G_RESET_FF_TX_CLK    1
+#define V_MAC1G10G_RESET_FF_TX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_TX_CLK)
+#define F_MAC1G10G_RESET_FF_TX_CLK    V_MAC1G10G_RESET_FF_TX_CLK(1U)
+
+#define S_XGMII_CLK_RESET    0
+#define V_XGMII_CLK_RESET(x) ((x) << S_XGMII_CLK_RESET)
+#define F_XGMII_CLK_RESET    V_XGMII_CLK_RESET(1U)
+
+#define A_MAC_PORT_MTIP_GATE_CTRL 0x830
+
+#define S_AN_GATE_SD_TX_CLK    31
+#define V_AN_GATE_SD_TX_CLK(x) ((x) << S_AN_GATE_SD_TX_CLK)
+#define F_AN_GATE_SD_TX_CLK    V_AN_GATE_SD_TX_CLK(1U)
+
+#define S_AN_GATE_SD_RX_CLK    30
+#define V_AN_GATE_SD_RX_CLK(x) ((x) << S_AN_GATE_SD_RX_CLK)
+#define F_AN_GATE_SD_RX_CLK    V_AN_GATE_SD_RX_CLK(1U)
+
+#define S_SGMII_GATE_TX_CLK    29
+#define V_SGMII_GATE_TX_CLK(x) ((x) << S_SGMII_GATE_TX_CLK)
+#define F_SGMII_GATE_TX_CLK    V_SGMII_GATE_TX_CLK(1U)
+
+#define S_SGMII_GATE_RX_CLK    28
+#define V_SGMII_GATE_RX_CLK(x) ((x) << S_SGMII_GATE_RX_CLK)
+#define F_SGMII_GATE_RX_CLK    V_SGMII_GATE_RX_CLK(1U)
+
+#define S_SGMII_GATE_REF_CLK    27
+#define V_SGMII_GATE_REF_CLK(x) ((x) << S_SGMII_GATE_REF_CLK)
+#define F_SGMII_GATE_REF_CLK    V_SGMII_GATE_REF_CLK(1U)
+
+#define S_PCS10G_GATE_XFI_RXCLK    26
+#define V_PCS10G_GATE_XFI_RXCLK(x) ((x) << S_PCS10G_GATE_XFI_RXCLK)
+#define F_PCS10G_GATE_XFI_RXCLK    V_PCS10G_GATE_XFI_RXCLK(1U)
+
+#define S_PCS10G_GATE_XFI_TXCLK    25
+#define V_PCS10G_GATE_XFI_TXCLK(x) ((x) << S_PCS10G_GATE_XFI_TXCLK)
+#define F_PCS10G_GATE_XFI_TXCLK    V_PCS10G_GATE_XFI_TXCLK(1U)
+
+#define S_PCS10G_GATE_SD_TX_CLK    24
+#define V_PCS10G_GATE_SD_TX_CLK(x) ((x) << S_PCS10G_GATE_SD_TX_CLK)
+#define F_PCS10G_GATE_SD_TX_CLK    V_PCS10G_GATE_SD_TX_CLK(1U)
+
+#define S_PCS10G_GATE_SD_RX_CLK    23
+#define V_PCS10G_GATE_SD_RX_CLK(x) ((x) << S_PCS10G_GATE_SD_RX_CLK)
+#define F_PCS10G_GATE_SD_RX_CLK    V_PCS10G_GATE_SD_RX_CLK(1U)
+
+#define S_PCS40G_GATE_RXCLK    22
+#define V_PCS40G_GATE_RXCLK(x) ((x) << S_PCS40G_GATE_RXCLK)
+#define F_PCS40G_GATE_RXCLK    V_PCS40G_GATE_RXCLK(1U)
+
+#define S_PCS40G_GATE_SD_TX_CLK    21
+#define V_PCS40G_GATE_SD_TX_CLK(x) ((x) << S_PCS40G_GATE_SD_TX_CLK)
+#define F_PCS40G_GATE_SD_TX_CLK    V_PCS40G_GATE_SD_TX_CLK(1U)
+
+#define S_PCS40G_GATE_SD_RX_CLK    20
+#define V_PCS40G_GATE_SD_RX_CLK(x) ((x) << S_PCS40G_GATE_SD_RX_CLK)
+#define F_PCS40G_GATE_SD_RX_CLK    V_PCS40G_GATE_SD_RX_CLK(1U)
+
+#define S_PCS100G_GATE_CGMII_RXCLK    19
+#define V_PCS100G_GATE_CGMII_RXCLK(x) ((x) << S_PCS100G_GATE_CGMII_RXCLK)
+#define F_PCS100G_GATE_CGMII_RXCLK    V_PCS100G_GATE_CGMII_RXCLK(1U)
+
+#define S_PCS100G_GATE_CGMII_TXCLK    18
+#define V_PCS100G_GATE_CGMII_TXCLK(x) ((x) << S_PCS100G_GATE_CGMII_TXCLK)
+#define F_PCS100G_GATE_CGMII_TXCLK    V_PCS100G_GATE_CGMII_TXCLK(1U)
+
+#define S_PCS100G_GATE_TX_CLK    17
+#define V_PCS100G_GATE_TX_CLK(x) ((x) << S_PCS100G_GATE_TX_CLK)
+#define F_PCS100G_GATE_TX_CLK    V_PCS100G_GATE_TX_CLK(1U)
+
+#define S_PCS100G_GATE_SD_RX_CLK    16
+#define V_PCS100G_GATE_SD_RX_CLK(x) ((x) << S_PCS100G_GATE_SD_RX_CLK)
+#define F_PCS100G_GATE_SD_RX_CLK    V_PCS100G_GATE_SD_RX_CLK(1U)
+
+#define S_MAC40G100G_GATE_TXCLK    15
+#define V_MAC40G100G_GATE_TXCLK(x) ((x) << S_MAC40G100G_GATE_TXCLK)
+#define F_MAC40G100G_GATE_TXCLK    V_MAC40G100G_GATE_TXCLK(1U)
+
+#define S_MAC40G100G_GATE_RXCLK    14
+#define V_MAC40G100G_GATE_RXCLK(x) ((x) << S_MAC40G100G_GATE_RXCLK)
+#define F_MAC40G100G_GATE_RXCLK    V_MAC40G100G_GATE_RXCLK(1U)
+
+#define S_MAC40G100G_GATE_FF_TX_CLK    13
+#define V_MAC40G100G_GATE_FF_TX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_TX_CLK)
+#define F_MAC40G100G_GATE_FF_TX_CLK    V_MAC40G100G_GATE_FF_TX_CLK(1U)
+
+#define S_MAC40G100G_GATE_FF_RX_CLK    12
+#define V_MAC40G100G_GATE_FF_RX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_RX_CLK)
+#define F_MAC40G100G_GATE_FF_RX_CLK    V_MAC40G100G_GATE_FF_RX_CLK(1U)
+
+#define S_MAC40G100G_TS_CLK    11
+#define V_MAC40G100G_TS_CLK(x) ((x) << S_MAC40G100G_TS_CLK)
+#define F_MAC40G100G_TS_CLK    V_MAC40G100G_TS_CLK(1U)
+
+#define S_MAC1G10G_GATE_RXCLK    10
+#define V_MAC1G10G_GATE_RXCLK(x) ((x) << S_MAC1G10G_GATE_RXCLK)
+#define F_MAC1G10G_GATE_RXCLK    V_MAC1G10G_GATE_RXCLK(1U)
+
+#define S_MAC1G10G_GATE_TXCLK    9
+#define V_MAC1G10G_GATE_TXCLK(x) ((x) << S_MAC1G10G_GATE_TXCLK)
+#define F_MAC1G10G_GATE_TXCLK    V_MAC1G10G_GATE_TXCLK(1U)
+
+#define S_MAC1G10G_GATE_FF_RX_CLK    8
+#define V_MAC1G10G_GATE_FF_RX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_RX_CLK)
+#define F_MAC1G10G_GATE_FF_RX_CLK    V_MAC1G10G_GATE_FF_RX_CLK(1U)
+
+#define S_MAC1G10G_GATE_FF_TX_CLK    7
+#define V_MAC1G10G_GATE_FF_TX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_TX_CLK)
+#define F_MAC1G10G_GATE_FF_TX_CLK    V_MAC1G10G_GATE_FF_TX_CLK(1U)
+
+#define S_AEC_RX    6
+#define V_AEC_RX(x) ((x) << S_AEC_RX)
+#define F_AEC_RX    V_AEC_RX(1U)
+
+#define S_AEC_TX    5
+#define V_AEC_TX(x) ((x) << S_AEC_TX)
+#define F_AEC_TX    V_AEC_TX(1U)
+
+#define S_PCS100G_CLK_ENABLE    4
+#define V_PCS100G_CLK_ENABLE(x) ((x) << S_PCS100G_CLK_ENABLE)
+#define F_PCS100G_CLK_ENABLE    V_PCS100G_CLK_ENABLE(1U)
+
+#define S_PCS40G_CLK_ENABLE    3
+#define V_PCS40G_CLK_ENABLE(x) ((x) << S_PCS40G_CLK_ENABLE)
+#define F_PCS40G_CLK_ENABLE    V_PCS40G_CLK_ENABLE(1U)
+
+#define S_PCS10G_CLK_ENABLE    2
+#define V_PCS10G_CLK_ENABLE(x) ((x) << S_PCS10G_CLK_ENABLE)
+#define F_PCS10G_CLK_ENABLE    V_PCS10G_CLK_ENABLE(1U)
+
+#define S_PCS1G_CLK_ENABLE    1
+#define V_PCS1G_CLK_ENABLE(x) ((x) << S_PCS1G_CLK_ENABLE)
+#define F_PCS1G_CLK_ENABLE    V_PCS1G_CLK_ENABLE(1U)
+
+#define S_AN_CLK_ENABLE    0
+#define V_AN_CLK_ENABLE(x) ((x) << S_AN_CLK_ENABLE)
+#define F_AN_CLK_ENABLE    V_AN_CLK_ENABLE(1U)
+
 #define A_MAC_PORT_LINK_STATUS 0x834
 
 #define S_AN_DONE    6
@@ -33808,6 +45720,606 @@
 #define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK)
 #define F_BLOCK_LOCK    V_BLOCK_LOCK(1U)
 
+#define S_HI_BER_ST    7
+#define V_HI_BER_ST(x) ((x) << S_HI_BER_ST)
+#define F_HI_BER_ST    V_HI_BER_ST(1U)
+
+#define S_AN_DONE_ST    6
+#define V_AN_DONE_ST(x) ((x) << S_AN_DONE_ST)
+#define F_AN_DONE_ST    V_AN_DONE_ST(1U)
+
+#define A_MAC_PORT_AEC_ADD_CTL_STAT_0 0x838
+
+#define S_AEC_SYS_LANE_TYPE_3    11
+#define V_AEC_SYS_LANE_TYPE_3(x) ((x) << S_AEC_SYS_LANE_TYPE_3)
+#define F_AEC_SYS_LANE_TYPE_3    V_AEC_SYS_LANE_TYPE_3(1U)
+
+#define S_AEC_SYS_LANE_TYPE_2    10
+#define V_AEC_SYS_LANE_TYPE_2(x) ((x) << S_AEC_SYS_LANE_TYPE_2)
+#define F_AEC_SYS_LANE_TYPE_2    V_AEC_SYS_LANE_TYPE_2(1U)
+
+#define S_AEC_SYS_LANE_TYPE_1    9
+#define V_AEC_SYS_LANE_TYPE_1(x) ((x) << S_AEC_SYS_LANE_TYPE_1)
+#define F_AEC_SYS_LANE_TYPE_1    V_AEC_SYS_LANE_TYPE_1(1U)
+
+#define S_AEC_SYS_LANE_TYPE_0    8
+#define V_AEC_SYS_LANE_TYPE_0(x) ((x) << S_AEC_SYS_LANE_TYPE_0)
+#define F_AEC_SYS_LANE_TYPE_0    V_AEC_SYS_LANE_TYPE_0(1U)
+
+#define S_AEC_SYS_LANE_SELECT_3    6
+#define M_AEC_SYS_LANE_SELECT_3    0x3U
+#define V_AEC_SYS_LANE_SELECT_3(x) ((x) << S_AEC_SYS_LANE_SELECT_3)
+#define G_AEC_SYS_LANE_SELECT_3(x) (((x) >> S_AEC_SYS_LANE_SELECT_3) & M_AEC_SYS_LANE_SELECT_3)
+
+#define S_AEC_SYS_LANE_SELECT_2    4
+#define M_AEC_SYS_LANE_SELECT_2    0x3U
+#define V_AEC_SYS_LANE_SELECT_2(x) ((x) << S_AEC_SYS_LANE_SELECT_2)
+#define G_AEC_SYS_LANE_SELECT_2(x) (((x) >> S_AEC_SYS_LANE_SELECT_2) & M_AEC_SYS_LANE_SELECT_2)
+
+#define S_AEC_SYS_LANE_SELECT_1    2
+#define M_AEC_SYS_LANE_SELECT_1    0x3U
+#define V_AEC_SYS_LANE_SELECT_1(x) ((x) << S_AEC_SYS_LANE_SELECT_1)
+#define G_AEC_SYS_LANE_SELECT_1(x) (((x) >> S_AEC_SYS_LANE_SELECT_1) & M_AEC_SYS_LANE_SELECT_1)
+
+#define S_AEC_SYS_LANE_SELECT_O    0
+#define M_AEC_SYS_LANE_SELECT_O    0x3U
+#define V_AEC_SYS_LANE_SELECT_O(x) ((x) << S_AEC_SYS_LANE_SELECT_O)
+#define G_AEC_SYS_LANE_SELECT_O(x) (((x) >> S_AEC_SYS_LANE_SELECT_O) & M_AEC_SYS_LANE_SELECT_O)
+
+#define A_MAC_PORT_AEC_ADD_CTL_STAT_1 0x83c
+
+#define S_AEC_RX_UNKNOWN_LANE_3    11
+#define V_AEC_RX_UNKNOWN_LANE_3(x) ((x) << S_AEC_RX_UNKNOWN_LANE_3)
+#define F_AEC_RX_UNKNOWN_LANE_3    V_AEC_RX_UNKNOWN_LANE_3(1U)
+
+#define S_AEC_RX_UNKNOWN_LANE_2    10
+#define V_AEC_RX_UNKNOWN_LANE_2(x) ((x) << S_AEC_RX_UNKNOWN_LANE_2)
+#define F_AEC_RX_UNKNOWN_LANE_2    V_AEC_RX_UNKNOWN_LANE_2(1U)
+
+#define S_AEC_RX_UNKNOWN_LANE_1    9
+#define V_AEC_RX_UNKNOWN_LANE_1(x) ((x) << S_AEC_RX_UNKNOWN_LANE_1)
+#define F_AEC_RX_UNKNOWN_LANE_1    V_AEC_RX_UNKNOWN_LANE_1(1U)
+
+#define S_AEC_RX_UNKNOWN_LANE_0    8
+#define V_AEC_RX_UNKNOWN_LANE_0(x) ((x) << S_AEC_RX_UNKNOWN_LANE_0)
+#define F_AEC_RX_UNKNOWN_LANE_0    V_AEC_RX_UNKNOWN_LANE_0(1U)
+
+#define S_AEC_RX_LANE_ID_3    6
+#define M_AEC_RX_LANE_ID_3    0x3U
+#define V_AEC_RX_LANE_ID_3(x) ((x) << S_AEC_RX_LANE_ID_3)
+#define G_AEC_RX_LANE_ID_3(x) (((x) >> S_AEC_RX_LANE_ID_3) & M_AEC_RX_LANE_ID_3)
+
+#define S_AEC_RX_LANE_ID_2    4
+#define M_AEC_RX_LANE_ID_2    0x3U
+#define V_AEC_RX_LANE_ID_2(x) ((x) << S_AEC_RX_LANE_ID_2)
+#define G_AEC_RX_LANE_ID_2(x) (((x) >> S_AEC_RX_LANE_ID_2) & M_AEC_RX_LANE_ID_2)
+
+#define S_AEC_RX_LANE_ID_1    2
+#define M_AEC_RX_LANE_ID_1    0x3U
+#define V_AEC_RX_LANE_ID_1(x) ((x) << S_AEC_RX_LANE_ID_1)
+#define G_AEC_RX_LANE_ID_1(x) (((x) >> S_AEC_RX_LANE_ID_1) & M_AEC_RX_LANE_ID_1)
+
+#define S_AEC_RX_LANE_ID_O    0
+#define M_AEC_RX_LANE_ID_O    0x3U
+#define V_AEC_RX_LANE_ID_O(x) ((x) << S_AEC_RX_LANE_ID_O)
+#define G_AEC_RX_LANE_ID_O(x) (((x) >> S_AEC_RX_LANE_ID_O) & M_AEC_RX_LANE_ID_O)
+
+#define A_MAC_PORT_AEC_XGMII_TIMER_LO_40G 0x840
+
+#define S_XGMII_CLK_IN_1MS_LO_40G    0
+#define M_XGMII_CLK_IN_1MS_LO_40G    0xffffU
+#define V_XGMII_CLK_IN_1MS_LO_40G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_40G)
+#define G_XGMII_CLK_IN_1MS_LO_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_40G) & M_XGMII_CLK_IN_1MS_LO_40G)
+
+#define A_MAC_PORT_AEC_XGMII_TIMER_HI_40G 0x844
+
+#define S_XGMII_CLK_IN_1MS_HI_40G    0
+#define M_XGMII_CLK_IN_1MS_HI_40G    0xfU
+#define V_XGMII_CLK_IN_1MS_HI_40G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_40G)
+#define G_XGMII_CLK_IN_1MS_HI_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_40G) & M_XGMII_CLK_IN_1MS_HI_40G)
+
+#define A_MAC_PORT_AEC_XGMII_TIMER_LO_100G 0x848
+
+#define S_XGMII_CLK_IN_1MS_LO_100G    0
+#define M_XGMII_CLK_IN_1MS_LO_100G    0xffffU
+#define V_XGMII_CLK_IN_1MS_LO_100G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_100G)
+#define G_XGMII_CLK_IN_1MS_LO_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_100G) & M_XGMII_CLK_IN_1MS_LO_100G)
+
+#define A_MAC_PORT_AEC_XGMII_TIMER_HI_100G 0x84c
+
+#define S_XGMII_CLK_IN_1MS_HI_100G    0
+#define M_XGMII_CLK_IN_1MS_HI_100G    0xfU
+#define V_XGMII_CLK_IN_1MS_HI_100G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_100G)
+#define G_XGMII_CLK_IN_1MS_HI_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_100G) & M_XGMII_CLK_IN_1MS_HI_100G)
+
+#define A_MAC_PORT_AEC_DEBUG_LO_0 0x850
+
+#define S_CTL_FSM_CUR_STATE    28
+#define M_CTL_FSM_CUR_STATE    0x7U
+#define V_CTL_FSM_CUR_STATE(x) ((x) << S_CTL_FSM_CUR_STATE)
+#define G_CTL_FSM_CUR_STATE(x) (((x) >> S_CTL_FSM_CUR_STATE) & M_CTL_FSM_CUR_STATE)
+
+#define S_CIN_FSM_CUR_STATE    26
+#define M_CIN_FSM_CUR_STATE    0x3U
+#define V_CIN_FSM_CUR_STATE(x) ((x) << S_CIN_FSM_CUR_STATE)
+#define G_CIN_FSM_CUR_STATE(x) (((x) >> S_CIN_FSM_CUR_STATE) & M_CIN_FSM_CUR_STATE)
+
+#define S_CRI_FSM_CUR_STATE    23
+#define M_CRI_FSM_CUR_STATE    0x7U
+#define V_CRI_FSM_CUR_STATE(x) ((x) << S_CRI_FSM_CUR_STATE)
+#define G_CRI_FSM_CUR_STATE(x) (((x) >> S_CRI_FSM_CUR_STATE) & M_CRI_FSM_CUR_STATE)
+
+#define S_CU_C3_ACK_VALUE    21
+#define M_CU_C3_ACK_VALUE    0x3U
+#define V_CU_C3_ACK_VALUE(x) ((x) << S_CU_C3_ACK_VALUE)
+#define G_CU_C3_ACK_VALUE(x) (((x) >> S_CU_C3_ACK_VALUE) & M_CU_C3_ACK_VALUE)
+
+#define S_CU_C2_ACK_VALUE    19
+#define M_CU_C2_ACK_VALUE    0x3U
+#define V_CU_C2_ACK_VALUE(x) ((x) << S_CU_C2_ACK_VALUE)
+#define G_CU_C2_ACK_VALUE(x) (((x) >> S_CU_C2_ACK_VALUE) & M_CU_C2_ACK_VALUE)
+
+#define S_CU_C1_ACK_VALUE    17
+#define M_CU_C1_ACK_VALUE    0x3U
+#define V_CU_C1_ACK_VALUE(x) ((x) << S_CU_C1_ACK_VALUE)
+#define G_CU_C1_ACK_VALUE(x) (((x) >> S_CU_C1_ACK_VALUE) & M_CU_C1_ACK_VALUE)
+
+#define S_CU_C0_ACK_VALUE    15
+#define M_CU_C0_ACK_VALUE    0x3U
+#define V_CU_C0_ACK_VALUE(x) ((x) << S_CU_C0_ACK_VALUE)
+#define G_CU_C0_ACK_VALUE(x) (((x) >> S_CU_C0_ACK_VALUE) & M_CU_C0_ACK_VALUE)
+
+#define S_CX_INIT    13
+#define V_CX_INIT(x) ((x) << S_CX_INIT)
+#define F_CX_INIT    V_CX_INIT(1U)
+
+#define S_CX_PRESET    12
+#define V_CX_PRESET(x) ((x) << S_CX_PRESET)
+#define F_CX_PRESET    V_CX_PRESET(1U)
+
+#define S_CUF_C3_UPDATE    9
+#define M_CUF_C3_UPDATE    0x3U
+#define V_CUF_C3_UPDATE(x) ((x) << S_CUF_C3_UPDATE)
+#define G_CUF_C3_UPDATE(x) (((x) >> S_CUF_C3_UPDATE) & M_CUF_C3_UPDATE)
+
+#define S_CUF_C2_UPDATE    7
+#define M_CUF_C2_UPDATE    0x3U
+#define V_CUF_C2_UPDATE(x) ((x) << S_CUF_C2_UPDATE)
+#define G_CUF_C2_UPDATE(x) (((x) >> S_CUF_C2_UPDATE) & M_CUF_C2_UPDATE)
+
+#define S_CUF_C1_UPDATE    5
+#define M_CUF_C1_UPDATE    0x3U
+#define V_CUF_C1_UPDATE(x) ((x) << S_CUF_C1_UPDATE)
+#define G_CUF_C1_UPDATE(x) (((x) >> S_CUF_C1_UPDATE) & M_CUF_C1_UPDATE)
+
+#define S_CUF_C0_UPDATE    3
+#define M_CUF_C0_UPDATE    0x3U
+#define V_CUF_C0_UPDATE(x) ((x) << S_CUF_C0_UPDATE)
+#define G_CUF_C0_UPDATE(x) (((x) >> S_CUF_C0_UPDATE) & M_CUF_C0_UPDATE)
+
+#define S_REG_FPH_ATTR_TXUPDAT_VALID    2
+#define V_REG_FPH_ATTR_TXUPDAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXUPDAT_VALID)
+#define F_REG_FPH_ATTR_TXUPDAT_VALID    V_REG_FPH_ATTR_TXUPDAT_VALID(1U)
+
+#define S_REG_FPH_ATTR_TXSTAT_VALID    1
+#define V_REG_FPH_ATTR_TXSTAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXSTAT_VALID)
+#define F_REG_FPH_ATTR_TXSTAT_VALID    V_REG_FPH_ATTR_TXSTAT_VALID(1U)
+
+#define S_REG_MAN_DEC_REQ    0
+#define V_REG_MAN_DEC_REQ(x) ((x) << S_REG_MAN_DEC_REQ)
+#define F_REG_MAN_DEC_REQ    V_REG_MAN_DEC_REQ(1U)
+
+#define A_MAC_PORT_AEC_DEBUG_HI_0 0x854
+
+#define S_FC_LSNA_    12
+#define V_FC_LSNA_(x) ((x) << S_FC_LSNA_)
+#define F_FC_LSNA_    V_FC_LSNA_(1U)
+
+#define S_CUF_C0_FSM_DEBUG    9
+#define M_CUF_C0_FSM_DEBUG    0x7U
+#define V_CUF_C0_FSM_DEBUG(x) ((x) << S_CUF_C0_FSM_DEBUG)
+#define G_CUF_C0_FSM_DEBUG(x) (((x) >> S_CUF_C0_FSM_DEBUG) & M_CUF_C0_FSM_DEBUG)
+
+#define S_CUF_C1_FSM_DEBUG    6
+#define M_CUF_C1_FSM_DEBUG    0x7U
+#define V_CUF_C1_FSM_DEBUG(x) ((x) << S_CUF_C1_FSM_DEBUG)
+#define G_CUF_C1_FSM_DEBUG(x) (((x) >> S_CUF_C1_FSM_DEBUG) & M_CUF_C1_FSM_DEBUG)
+
+#define S_CUF_C2_FSM_DEBUG    3
+#define M_CUF_C2_FSM_DEBUG    0x7U
+#define V_CUF_C2_FSM_DEBUG(x) ((x) << S_CUF_C2_FSM_DEBUG)
+#define G_CUF_C2_FSM_DEBUG(x) (((x) >> S_CUF_C2_FSM_DEBUG) & M_CUF_C2_FSM_DEBUG)
+
+#define S_LCK_FSM_CUR_STATE    0
+#define M_LCK_FSM_CUR_STATE    0x7U
+#define V_LCK_FSM_CUR_STATE(x) ((x) << S_LCK_FSM_CUR_STATE)
+#define G_LCK_FSM_CUR_STATE(x) (((x) >> S_LCK_FSM_CUR_STATE) & M_LCK_FSM_CUR_STATE)
+
+#define A_MAC_PORT_AEC_DEBUG_LO_1 0x858
+#define A_MAC_PORT_AEC_DEBUG_HI_1 0x85c
+#define A_MAC_PORT_AEC_DEBUG_LO_2 0x860
+#define A_MAC_PORT_AEC_DEBUG_HI_2 0x864
+#define A_MAC_PORT_AEC_DEBUG_LO_3 0x868
+#define A_MAC_PORT_AEC_DEBUG_HI_3 0x86c
+#define A_MAC_PORT_MAC_DEBUG_RO 0x870
+
+#define S_MAC40G100G_TX_UNDERFLOW    13
+#define V_MAC40G100G_TX_UNDERFLOW(x) ((x) << S_MAC40G100G_TX_UNDERFLOW)
+#define F_MAC40G100G_TX_UNDERFLOW    V_MAC40G100G_TX_UNDERFLOW(1U)
+
+#define S_MAC1G10G_MAGIC_IND    12
+#define V_MAC1G10G_MAGIC_IND(x) ((x) << S_MAC1G10G_MAGIC_IND)
+#define F_MAC1G10G_MAGIC_IND    V_MAC1G10G_MAGIC_IND(1U)
+
+#define S_MAC1G10G_FF_RX_EMPTY    11
+#define V_MAC1G10G_FF_RX_EMPTY(x) ((x) << S_MAC1G10G_FF_RX_EMPTY)
+#define F_MAC1G10G_FF_RX_EMPTY    V_MAC1G10G_FF_RX_EMPTY(1U)
+
+#define S_MAC1G10G_FF_TX_OVR_ERR    10
+#define V_MAC1G10G_FF_TX_OVR_ERR(x) ((x) << S_MAC1G10G_FF_TX_OVR_ERR)
+#define F_MAC1G10G_FF_TX_OVR_ERR    V_MAC1G10G_FF_TX_OVR_ERR(1U)
+
+#define S_MAC1G10G_IF_MODE_ENA    8
+#define M_MAC1G10G_IF_MODE_ENA    0x3U
+#define V_MAC1G10G_IF_MODE_ENA(x) ((x) << S_MAC1G10G_IF_MODE_ENA)
+#define G_MAC1G10G_IF_MODE_ENA(x) (((x) >> S_MAC1G10G_IF_MODE_ENA) & M_MAC1G10G_IF_MODE_ENA)
+
+#define S_MAC1G10G_MII_ENA_10    7
+#define V_MAC1G10G_MII_ENA_10(x) ((x) << S_MAC1G10G_MII_ENA_10)
+#define F_MAC1G10G_MII_ENA_10    V_MAC1G10G_MII_ENA_10(1U)
+
+#define S_MAC1G10G_PAUSE_ON    6
+#define V_MAC1G10G_PAUSE_ON(x) ((x) << S_MAC1G10G_PAUSE_ON)
+#define F_MAC1G10G_PAUSE_ON    V_MAC1G10G_PAUSE_ON(1U)
+
+#define S_MAC1G10G_PFC_MODE    5
+#define V_MAC1G10G_PFC_MODE(x) ((x) << S_MAC1G10G_PFC_MODE)
+#define F_MAC1G10G_PFC_MODE    V_MAC1G10G_PFC_MODE(1U)
+
+#define S_MAC1G10G_RX_SFD_O    4
+#define V_MAC1G10G_RX_SFD_O(x) ((x) << S_MAC1G10G_RX_SFD_O)
+#define F_MAC1G10G_RX_SFD_O    V_MAC1G10G_RX_SFD_O(1U)
+
+#define S_MAC1G10G_TX_EMPTY    3
+#define V_MAC1G10G_TX_EMPTY(x) ((x) << S_MAC1G10G_TX_EMPTY)
+#define F_MAC1G10G_TX_EMPTY    V_MAC1G10G_TX_EMPTY(1U)
+
+#define S_MAC1G10G_TX_SFD_O    2
+#define V_MAC1G10G_TX_SFD_O(x) ((x) << S_MAC1G10G_TX_SFD_O)
+#define F_MAC1G10G_TX_SFD_O    V_MAC1G10G_TX_SFD_O(1U)
+
+#define S_MAC1G10G_TX_TS_FRM_OUT    1
+#define V_MAC1G10G_TX_TS_FRM_OUT(x) ((x) << S_MAC1G10G_TX_TS_FRM_OUT)
+#define F_MAC1G10G_TX_TS_FRM_OUT    V_MAC1G10G_TX_TS_FRM_OUT(1U)
+
+#define S_MAC1G10G_TX_UNDERFLOW    0
+#define V_MAC1G10G_TX_UNDERFLOW(x) ((x) << S_MAC1G10G_TX_UNDERFLOW)
+#define F_MAC1G10G_TX_UNDERFLOW    V_MAC1G10G_TX_UNDERFLOW(1U)
+
+#define A_MAC_PORT_MAC_CTRL_RW 0x874
+
+#define S_MAC40G100G_FF_TX_PFC_XOFF    17
+#define M_MAC40G100G_FF_TX_PFC_XOFF    0xffU
+#define V_MAC40G100G_FF_TX_PFC_XOFF(x) ((x) << S_MAC40G100G_FF_TX_PFC_XOFF)
+#define G_MAC40G100G_FF_TX_PFC_XOFF(x) (((x) >> S_MAC40G100G_FF_TX_PFC_XOFF) & M_MAC40G100G_FF_TX_PFC_XOFF)
+
+#define S_MAC40G100G_TX_LOC_FAULT    16
+#define V_MAC40G100G_TX_LOC_FAULT(x) ((x) << S_MAC40G100G_TX_LOC_FAULT)
+#define F_MAC40G100G_TX_LOC_FAULT    V_MAC40G100G_TX_LOC_FAULT(1U)
+
+#define S_MAC40G100G_TX_REM_FAULT    15
+#define V_MAC40G100G_TX_REM_FAULT(x) ((x) << S_MAC40G100G_TX_REM_FAULT)
+#define F_MAC40G100G_TX_REM_FAULT    V_MAC40G100G_TX_REM_FAULT(1U)
+
+#define S_MAC40G_LOOP_BCK    14
+#define V_MAC40G_LOOP_BCK(x) ((x) << S_MAC40G_LOOP_BCK)
+#define F_MAC40G_LOOP_BCK    V_MAC40G_LOOP_BCK(1U)
+
+#define S_MAC1G10G_MAGIC_ENA    13
+#define V_MAC1G10G_MAGIC_ENA(x) ((x) << S_MAC1G10G_MAGIC_ENA)
+#define F_MAC1G10G_MAGIC_ENA    V_MAC1G10G_MAGIC_ENA(1U)
+
+#define S_MAC1G10G_IF_MODE_SET    11
+#define M_MAC1G10G_IF_MODE_SET    0x3U
+#define V_MAC1G10G_IF_MODE_SET(x) ((x) << S_MAC1G10G_IF_MODE_SET)
+#define G_MAC1G10G_IF_MODE_SET(x) (((x) >> S_MAC1G10G_IF_MODE_SET) & M_MAC1G10G_IF_MODE_SET)
+
+#define S_MAC1G10G_TX_LOC_FAULT    10
+#define V_MAC1G10G_TX_LOC_FAULT(x) ((x) << S_MAC1G10G_TX_LOC_FAULT)
+#define F_MAC1G10G_TX_LOC_FAULT    V_MAC1G10G_TX_LOC_FAULT(1U)
+
+#define S_MAC1G10G_TX_REM_FAULT    9
+#define V_MAC1G10G_TX_REM_FAULT(x) ((x) << S_MAC1G10G_TX_REM_FAULT)
+#define F_MAC1G10G_TX_REM_FAULT    V_MAC1G10G_TX_REM_FAULT(1U)
+
+#define S_MAC1G10G_XOFF_GEN    1
+#define M_MAC1G10G_XOFF_GEN    0xffU
+#define V_MAC1G10G_XOFF_GEN(x) ((x) << S_MAC1G10G_XOFF_GEN)
+#define G_MAC1G10G_XOFF_GEN(x) (((x) >> S_MAC1G10G_XOFF_GEN) & M_MAC1G10G_XOFF_GEN)
+
+#define S_MAC1G_LOOP_BCK    0
+#define V_MAC1G_LOOP_BCK(x) ((x) << S_MAC1G_LOOP_BCK)
+#define F_MAC1G_LOOP_BCK    V_MAC1G_LOOP_BCK(1U)
+
+#define A_MAC_PORT_PCS_DEBUG0_RO 0x878
+
+#define S_FPGA_LOCK    26
+#define M_FPGA_LOCK    0xfU
+#define V_FPGA_LOCK(x) ((x) << S_FPGA_LOCK)
+#define G_FPGA_LOCK(x) (((x) >> S_FPGA_LOCK) & M_FPGA_LOCK)
+
+#define S_T6_AN_DONE    25
+#define V_T6_AN_DONE(x) ((x) << S_T6_AN_DONE)
+#define F_T6_AN_DONE    V_T6_AN_DONE(1U)
+
+#define S_AN_INT    24
+#define V_AN_INT(x) ((x) << S_AN_INT)
+#define F_AN_INT    V_AN_INT(1U)
+
+#define S_AN_PCS_RX_CLK_ENA    23
+#define V_AN_PCS_RX_CLK_ENA(x) ((x) << S_AN_PCS_RX_CLK_ENA)
+#define F_AN_PCS_RX_CLK_ENA    V_AN_PCS_RX_CLK_ENA(1U)
+
+#define S_AN_PCS_TX_CLK_ENA    22
+#define V_AN_PCS_TX_CLK_ENA(x) ((x) << S_AN_PCS_TX_CLK_ENA)
+#define F_AN_PCS_TX_CLK_ENA    V_AN_PCS_TX_CLK_ENA(1U)
+
+#define S_AN_SELECT    17
+#define M_AN_SELECT    0x1fU
+#define V_AN_SELECT(x) ((x) << S_AN_SELECT)
+#define G_AN_SELECT(x) (((x) >> S_AN_SELECT) & M_AN_SELECT)
+
+#define S_AN_PROG    16
+#define V_AN_PROG(x) ((x) << S_AN_PROG)
+#define F_AN_PROG    V_AN_PROG(1U)
+
+#define S_PCS40G_BLOCK_LOCK    12
+#define M_PCS40G_BLOCK_LOCK    0xfU
+#define V_PCS40G_BLOCK_LOCK(x) ((x) << S_PCS40G_BLOCK_LOCK)
+#define G_PCS40G_BLOCK_LOCK(x) (((x) >> S_PCS40G_BLOCK_LOCK) & M_PCS40G_BLOCK_LOCK)
+
+#define S_PCS40G_BER_TIMER_DONE    11
+#define V_PCS40G_BER_TIMER_DONE(x) ((x) << S_PCS40G_BER_TIMER_DONE)
+#define F_PCS40G_BER_TIMER_DONE    V_PCS40G_BER_TIMER_DONE(1U)
+
+#define S_PCS10G_FEC_LOCKED    10
+#define V_PCS10G_FEC_LOCKED(x) ((x) << S_PCS10G_FEC_LOCKED)
+#define F_PCS10G_FEC_LOCKED    V_PCS10G_FEC_LOCKED(1U)
+
+#define S_PCS10G_BLOCK_LOCK    9
+#define V_PCS10G_BLOCK_LOCK(x) ((x) << S_PCS10G_BLOCK_LOCK)
+#define F_PCS10G_BLOCK_LOCK    V_PCS10G_BLOCK_LOCK(1U)
+
+#define S_SGMII_GMII_COL    8
+#define V_SGMII_GMII_COL(x) ((x) << S_SGMII_GMII_COL)
+#define F_SGMII_GMII_COL    V_SGMII_GMII_COL(1U)
+
+#define S_SGMII_GMII_CRS    7
+#define V_SGMII_GMII_CRS(x) ((x) << S_SGMII_GMII_CRS)
+#define F_SGMII_GMII_CRS    V_SGMII_GMII_CRS(1U)
+
+#define S_SGMII_SD_LOOPBACK    6
+#define V_SGMII_SD_LOOPBACK(x) ((x) << S_SGMII_SD_LOOPBACK)
+#define F_SGMII_SD_LOOPBACK    V_SGMII_SD_LOOPBACK(1U)
+
+#define S_SGMII_SG_AN_DONE    5
+#define V_SGMII_SG_AN_DONE(x) ((x) << S_SGMII_SG_AN_DONE)
+#define F_SGMII_SG_AN_DONE    V_SGMII_SG_AN_DONE(1U)
+
+#define S_SGMII_SG_HD    4
+#define V_SGMII_SG_HD(x) ((x) << S_SGMII_SG_HD)
+#define F_SGMII_SG_HD    V_SGMII_SG_HD(1U)
+
+#define S_SGMII_SG_PAGE_RX    3
+#define V_SGMII_SG_PAGE_RX(x) ((x) << S_SGMII_SG_PAGE_RX)
+#define F_SGMII_SG_PAGE_RX    V_SGMII_SG_PAGE_RX(1U)
+
+#define S_SGMII_SG_RX_SYNC    2
+#define V_SGMII_SG_RX_SYNC(x) ((x) << S_SGMII_SG_RX_SYNC)
+#define F_SGMII_SG_RX_SYNC    V_SGMII_SG_RX_SYNC(1U)
+
+#define S_SGMII_SG_SPEED    0
+#define M_SGMII_SG_SPEED    0x3U
+#define V_SGMII_SG_SPEED(x) ((x) << S_SGMII_SG_SPEED)
+#define G_SGMII_SG_SPEED(x) (((x) >> S_SGMII_SG_SPEED) & M_SGMII_SG_SPEED)
+
+#define A_MAC_PORT_PCS_CTRL_RW 0x87c
+
+#define S_TX_LI_FAULT    31
+#define V_TX_LI_FAULT(x) ((x) << S_TX_LI_FAULT)
+#define F_TX_LI_FAULT    V_TX_LI_FAULT(1U)
+
+#define S_T6_PAD    30
+#define V_T6_PAD(x) ((x) << S_T6_PAD)
+#define F_T6_PAD    V_T6_PAD(1U)
+
+#define S_BLK_STB_VAL    22
+#define M_BLK_STB_VAL    0xffU
+#define V_BLK_STB_VAL(x) ((x) << S_BLK_STB_VAL)
+#define G_BLK_STB_VAL(x) (((x) >> S_BLK_STB_VAL) & M_BLK_STB_VAL)
+
+#define S_DEBUG_SEL    18
+#define M_DEBUG_SEL    0xfU
+#define V_DEBUG_SEL(x) ((x) << S_DEBUG_SEL)
+#define G_DEBUG_SEL(x) (((x) >> S_DEBUG_SEL) & M_DEBUG_SEL)
+
+#define S_SGMII_LOOP    15
+#define M_SGMII_LOOP    0x7U
+#define V_SGMII_LOOP(x) ((x) << S_SGMII_LOOP)
+#define G_SGMII_LOOP(x) (((x) >> S_SGMII_LOOP) & M_SGMII_LOOP)
+
+#define S_AN_DIS_TIMER    14
+#define V_AN_DIS_TIMER(x) ((x) << S_AN_DIS_TIMER)
+#define F_AN_DIS_TIMER    V_AN_DIS_TIMER(1U)
+
+#define S_PCS100G_BER_TIMER_SHORT    13
+#define V_PCS100G_BER_TIMER_SHORT(x) ((x) << S_PCS100G_BER_TIMER_SHORT)
+#define F_PCS100G_BER_TIMER_SHORT    V_PCS100G_BER_TIMER_SHORT(1U)
+
+#define S_PCS100G_TX_LANE_THRESH    9
+#define M_PCS100G_TX_LANE_THRESH    0xfU
+#define V_PCS100G_TX_LANE_THRESH(x) ((x) << S_PCS100G_TX_LANE_THRESH)
+#define G_PCS100G_TX_LANE_THRESH(x) (((x) >> S_PCS100G_TX_LANE_THRESH) & M_PCS100G_TX_LANE_THRESH)
+
+#define S_PCS100G_VL_INTVL    8
+#define V_PCS100G_VL_INTVL(x) ((x) << S_PCS100G_VL_INTVL)
+#define F_PCS100G_VL_INTVL    V_PCS100G_VL_INTVL(1U)
+
+#define S_SGMII_TX_LANE_CKMULT    4
+#define M_SGMII_TX_LANE_CKMULT    0x7U
+#define V_SGMII_TX_LANE_CKMULT(x) ((x) << S_SGMII_TX_LANE_CKMULT)
+#define G_SGMII_TX_LANE_CKMULT(x) (((x) >> S_SGMII_TX_LANE_CKMULT) & M_SGMII_TX_LANE_CKMULT)
+
+#define S_SGMII_TX_LANE_THRESH    0
+#define M_SGMII_TX_LANE_THRESH    0xfU
+#define V_SGMII_TX_LANE_THRESH(x) ((x) << S_SGMII_TX_LANE_THRESH)
+#define G_SGMII_TX_LANE_THRESH(x) (((x) >> S_SGMII_TX_LANE_THRESH) & M_SGMII_TX_LANE_THRESH)
+
+#define A_MAC_PORT_PCS_DEBUG1_RO 0x880
+
+#define S_PCS100G_ALIGN_LOCK    21
+#define V_PCS100G_ALIGN_LOCK(x) ((x) << S_PCS100G_ALIGN_LOCK)
+#define F_PCS100G_ALIGN_LOCK    V_PCS100G_ALIGN_LOCK(1U)
+
+#define S_PCS100G_BER_TIMER_DONE    20
+#define V_PCS100G_BER_TIMER_DONE(x) ((x) << S_PCS100G_BER_TIMER_DONE)
+#define F_PCS100G_BER_TIMER_DONE    V_PCS100G_BER_TIMER_DONE(1U)
+
+#define S_PCS100G_BLOCK_LOCK    0
+#define M_PCS100G_BLOCK_LOCK    0xfffffU
+#define V_PCS100G_BLOCK_LOCK(x) ((x) << S_PCS100G_BLOCK_LOCK)
+#define G_PCS100G_BLOCK_LOCK(x) (((x) >> S_PCS100G_BLOCK_LOCK) & M_PCS100G_BLOCK_LOCK)
+
+#define A_MAC_PORT_PERR_INT_EN_100G 0x884
+
+#define S_PERR_RX_FEC100G_DLY    29
+#define V_PERR_RX_FEC100G_DLY(x) ((x) << S_PERR_RX_FEC100G_DLY)
+#define F_PERR_RX_FEC100G_DLY    V_PERR_RX_FEC100G_DLY(1U)
+
+#define S_PERR_RX_FEC100G    28
+#define V_PERR_RX_FEC100G(x) ((x) << S_PERR_RX_FEC100G)
+#define F_PERR_RX_FEC100G    V_PERR_RX_FEC100G(1U)
+
+#define S_PERR_RX3_FEC100G_DK    27
+#define V_PERR_RX3_FEC100G_DK(x) ((x) << S_PERR_RX3_FEC100G_DK)
+#define F_PERR_RX3_FEC100G_DK    V_PERR_RX3_FEC100G_DK(1U)
+
+#define S_PERR_RX2_FEC100G_DK    26
+#define V_PERR_RX2_FEC100G_DK(x) ((x) << S_PERR_RX2_FEC100G_DK)
+#define F_PERR_RX2_FEC100G_DK    V_PERR_RX2_FEC100G_DK(1U)
+
+#define S_PERR_RX1_FEC100G_DK    25
+#define V_PERR_RX1_FEC100G_DK(x) ((x) << S_PERR_RX1_FEC100G_DK)
+#define F_PERR_RX1_FEC100G_DK    V_PERR_RX1_FEC100G_DK(1U)
+
+#define S_PERR_RX0_FEC100G_DK    24
+#define V_PERR_RX0_FEC100G_DK(x) ((x) << S_PERR_RX0_FEC100G_DK)
+#define F_PERR_RX0_FEC100G_DK    V_PERR_RX0_FEC100G_DK(1U)
+
+#define S_PERR_TX3_PCS100G    23
+#define V_PERR_TX3_PCS100G(x) ((x) << S_PERR_TX3_PCS100G)
+#define F_PERR_TX3_PCS100G    V_PERR_TX3_PCS100G(1U)
+
+#define S_PERR_TX2_PCS100G    22
+#define V_PERR_TX2_PCS100G(x) ((x) << S_PERR_TX2_PCS100G)
+#define F_PERR_TX2_PCS100G    V_PERR_TX2_PCS100G(1U)
+
+#define S_PERR_TX1_PCS100G    21
+#define V_PERR_TX1_PCS100G(x) ((x) << S_PERR_TX1_PCS100G)
+#define F_PERR_TX1_PCS100G    V_PERR_TX1_PCS100G(1U)
+
+#define S_PERR_TX0_PCS100G    20
+#define V_PERR_TX0_PCS100G(x) ((x) << S_PERR_TX0_PCS100G)
+#define F_PERR_TX0_PCS100G    V_PERR_TX0_PCS100G(1U)
+
+#define S_PERR_RX19_PCS100G    19
+#define V_PERR_RX19_PCS100G(x) ((x) << S_PERR_RX19_PCS100G)
+#define F_PERR_RX19_PCS100G    V_PERR_RX19_PCS100G(1U)
+
+#define S_PERR_RX18_PCS100G    18
+#define V_PERR_RX18_PCS100G(x) ((x) << S_PERR_RX18_PCS100G)
+#define F_PERR_RX18_PCS100G    V_PERR_RX18_PCS100G(1U)
+
+#define S_PERR_RX17_PCS100G    17
+#define V_PERR_RX17_PCS100G(x) ((x) << S_PERR_RX17_PCS100G)
+#define F_PERR_RX17_PCS100G    V_PERR_RX17_PCS100G(1U)
+
+#define S_PERR_RX16_PCS100G    16
+#define V_PERR_RX16_PCS100G(x) ((x) << S_PERR_RX16_PCS100G)
+#define F_PERR_RX16_PCS100G    V_PERR_RX16_PCS100G(1U)
+
+#define S_PERR_RX15_PCS100G    15
+#define V_PERR_RX15_PCS100G(x) ((x) << S_PERR_RX15_PCS100G)
+#define F_PERR_RX15_PCS100G    V_PERR_RX15_PCS100G(1U)
+
+#define S_PERR_RX14_PCS100G    14
+#define V_PERR_RX14_PCS100G(x) ((x) << S_PERR_RX14_PCS100G)
+#define F_PERR_RX14_PCS100G    V_PERR_RX14_PCS100G(1U)
+
+#define S_PERR_RX13_PCS100G    13
+#define V_PERR_RX13_PCS100G(x) ((x) << S_PERR_RX13_PCS100G)
+#define F_PERR_RX13_PCS100G    V_PERR_RX13_PCS100G(1U)
+
+#define S_PERR_RX12_PCS100G    12
+#define V_PERR_RX12_PCS100G(x) ((x) << S_PERR_RX12_PCS100G)
+#define F_PERR_RX12_PCS100G    V_PERR_RX12_PCS100G(1U)
+
+#define S_PERR_RX11_PCS100G    11
+#define V_PERR_RX11_PCS100G(x) ((x) << S_PERR_RX11_PCS100G)
+#define F_PERR_RX11_PCS100G    V_PERR_RX11_PCS100G(1U)
+
+#define S_PERR_RX10_PCS100G    10
+#define V_PERR_RX10_PCS100G(x) ((x) << S_PERR_RX10_PCS100G)
+#define F_PERR_RX10_PCS100G    V_PERR_RX10_PCS100G(1U)
+
+#define S_PERR_RX9_PCS100G    9
+#define V_PERR_RX9_PCS100G(x) ((x) << S_PERR_RX9_PCS100G)
+#define F_PERR_RX9_PCS100G    V_PERR_RX9_PCS100G(1U)
+
+#define S_PERR_RX8_PCS100G    8
+#define V_PERR_RX8_PCS100G(x) ((x) << S_PERR_RX8_PCS100G)
+#define F_PERR_RX8_PCS100G    V_PERR_RX8_PCS100G(1U)
+
+#define S_PERR_RX7_PCS100G    7
+#define V_PERR_RX7_PCS100G(x) ((x) << S_PERR_RX7_PCS100G)
+#define F_PERR_RX7_PCS100G    V_PERR_RX7_PCS100G(1U)
+
+#define S_PERR_RX6_PCS100G    6
+#define V_PERR_RX6_PCS100G(x) ((x) << S_PERR_RX6_PCS100G)
+#define F_PERR_RX6_PCS100G    V_PERR_RX6_PCS100G(1U)
+
+#define S_PERR_RX5_PCS100G    5
+#define V_PERR_RX5_PCS100G(x) ((x) << S_PERR_RX5_PCS100G)
+#define F_PERR_RX5_PCS100G    V_PERR_RX5_PCS100G(1U)
+
+#define S_PERR_RX4_PCS100G    4
+#define V_PERR_RX4_PCS100G(x) ((x) << S_PERR_RX4_PCS100G)
+#define F_PERR_RX4_PCS100G    V_PERR_RX4_PCS100G(1U)
+
+#define S_PERR_RX3_PCS100G    3
+#define V_PERR_RX3_PCS100G(x) ((x) << S_PERR_RX3_PCS100G)
+#define F_PERR_RX3_PCS100G    V_PERR_RX3_PCS100G(1U)
+
+#define S_PERR_RX2_PCS100G    2
+#define V_PERR_RX2_PCS100G(x) ((x) << S_PERR_RX2_PCS100G)
+#define F_PERR_RX2_PCS100G    V_PERR_RX2_PCS100G(1U)
+
+#define S_PERR_RX1_PCS100G    1
+#define V_PERR_RX1_PCS100G(x) ((x) << S_PERR_RX1_PCS100G)
+#define F_PERR_RX1_PCS100G    V_PERR_RX1_PCS100G(1U)
+
+#define S_PERR_RX0_PCS100G    0
+#define V_PERR_RX0_PCS100G(x) ((x) << S_PERR_RX0_PCS100G)
+#define F_PERR_RX0_PCS100G    V_PERR_RX0_PCS100G(1U)
+
+#define A_MAC_PORT_PERR_INT_CAUSE_100G 0x888
+#define A_MAC_PORT_PERR_ENABLE_100G 0x88c
+#define A_MAC_PORT_MAC_STAT_DEBUG 0x890
+#define A_MAC_PORT_MAC_25G_50G_AM0 0x894
+#define A_MAC_PORT_MAC_25G_50G_AM1 0x898
+#define A_MAC_PORT_MAC_25G_50G_AM2 0x89c
+#define A_MAC_PORT_MAC_25G_50G_AM3 0x8a0
+#define A_MAC_PORT_MAC_AN_STATE_STATUS 0x8a4
 #define A_MAC_PORT_EPIO_DATA0 0x8c0
 #define A_MAC_PORT_EPIO_DATA1 0x8c4
 #define A_MAC_PORT_EPIO_DATA2 0x8c8
@@ -33824,6 +46336,18 @@
 #define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
 #define F_AN_PAGE_RCVD    V_AN_PAGE_RCVD(1U)
 
+#define S_PPS    30
+#define V_PPS(x) ((x) << S_PPS)
+#define F_PPS    V_PPS(1U)
+
+#define S_SINGLE_ALARM    28
+#define V_SINGLE_ALARM(x) ((x) << S_SINGLE_ALARM)
+#define F_SINGLE_ALARM    V_SINGLE_ALARM(1U)
+
+#define S_PERIODIC_ALARM    27
+#define V_PERIODIC_ALARM(x) ((x) << S_PERIODIC_ALARM)
+#define F_PERIODIC_ALARM    V_PERIODIC_ALARM(1U)
+
 #define A_MAC_PORT_INT_CAUSE 0x8dc
 #define A_MAC_PORT_PERR_INT_EN 0x8e0
 
@@ -33927,9 +46451,169 @@
 #define V_PERR0_TX(x) ((x) << S_PERR0_TX)
 #define F_PERR0_TX    V_PERR0_TX(1U)
 
+#define S_T6_PERR_PKT_RAM    31
+#define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
+#define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
+
+#define S_T6_PERR_MASK_RAM    30
+#define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
+#define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
+
+#define S_T6_PERR_CRC_RAM    29
+#define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
+#define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
+
+#define S_RX_MAC40G    28
+#define V_RX_MAC40G(x) ((x) << S_RX_MAC40G)
+#define F_RX_MAC40G    V_RX_MAC40G(1U)
+
+#define S_TX_MAC40G    27
+#define V_TX_MAC40G(x) ((x) << S_TX_MAC40G)
+#define F_TX_MAC40G    V_TX_MAC40G(1U)
+
+#define S_RX_ST_MAC40G    26
+#define V_RX_ST_MAC40G(x) ((x) << S_RX_ST_MAC40G)
+#define F_RX_ST_MAC40G    V_RX_ST_MAC40G(1U)
+
+#define S_TX_ST_MAC40G    25
+#define V_TX_ST_MAC40G(x) ((x) << S_TX_ST_MAC40G)
+#define F_TX_ST_MAC40G    V_TX_ST_MAC40G(1U)
+
+#define S_TX_MAC1G10G    24
+#define V_TX_MAC1G10G(x) ((x) << S_TX_MAC1G10G)
+#define F_TX_MAC1G10G    V_TX_MAC1G10G(1U)
+
+#define S_RX_MAC1G10G    23
+#define V_RX_MAC1G10G(x) ((x) << S_RX_MAC1G10G)
+#define F_RX_MAC1G10G    V_RX_MAC1G10G(1U)
+
+#define S_RX_STATUS_MAC1G10G    22
+#define V_RX_STATUS_MAC1G10G(x) ((x) << S_RX_STATUS_MAC1G10G)
+#define F_RX_STATUS_MAC1G10G    V_RX_STATUS_MAC1G10G(1U)
+
+#define S_RX_ST_MAC1G10G    21
+#define V_RX_ST_MAC1G10G(x) ((x) << S_RX_ST_MAC1G10G)
+#define F_RX_ST_MAC1G10G    V_RX_ST_MAC1G10G(1U)
+
+#define S_TX_ST_MAC1G10G    20
+#define V_TX_ST_MAC1G10G(x) ((x) << S_TX_ST_MAC1G10G)
+#define F_TX_ST_MAC1G10G    V_TX_ST_MAC1G10G(1U)
+
+#define S_PERR_TX0_PCS40G    19
+#define V_PERR_TX0_PCS40G(x) ((x) << S_PERR_TX0_PCS40G)
+#define F_PERR_TX0_PCS40G    V_PERR_TX0_PCS40G(1U)
+
+#define S_PERR_TX1_PCS40G    18
+#define V_PERR_TX1_PCS40G(x) ((x) << S_PERR_TX1_PCS40G)
+#define F_PERR_TX1_PCS40G    V_PERR_TX1_PCS40G(1U)
+
+#define S_PERR_TX2_PCS40G    17
+#define V_PERR_TX2_PCS40G(x) ((x) << S_PERR_TX2_PCS40G)
+#define F_PERR_TX2_PCS40G    V_PERR_TX2_PCS40G(1U)
+
+#define S_PERR_TX3_PCS40G    16
+#define V_PERR_TX3_PCS40G(x) ((x) << S_PERR_TX3_PCS40G)
+#define F_PERR_TX3_PCS40G    V_PERR_TX3_PCS40G(1U)
+
+#define S_PERR_TX0_FEC40G    15
+#define V_PERR_TX0_FEC40G(x) ((x) << S_PERR_TX0_FEC40G)
+#define F_PERR_TX0_FEC40G    V_PERR_TX0_FEC40G(1U)
+
+#define S_PERR_TX1_FEC40G    14
+#define V_PERR_TX1_FEC40G(x) ((x) << S_PERR_TX1_FEC40G)
+#define F_PERR_TX1_FEC40G    V_PERR_TX1_FEC40G(1U)
+
+#define S_PERR_TX2_FEC40G    13
+#define V_PERR_TX2_FEC40G(x) ((x) << S_PERR_TX2_FEC40G)
+#define F_PERR_TX2_FEC40G    V_PERR_TX2_FEC40G(1U)
+
+#define S_PERR_TX3_FEC40G    12
+#define V_PERR_TX3_FEC40G(x) ((x) << S_PERR_TX3_FEC40G)
+#define F_PERR_TX3_FEC40G    V_PERR_TX3_FEC40G(1U)
+
+#define S_PERR_RX0_PCS40G    11
+#define V_PERR_RX0_PCS40G(x) ((x) << S_PERR_RX0_PCS40G)
+#define F_PERR_RX0_PCS40G    V_PERR_RX0_PCS40G(1U)
+
+#define S_PERR_RX1_PCS40G    10
+#define V_PERR_RX1_PCS40G(x) ((x) << S_PERR_RX1_PCS40G)
+#define F_PERR_RX1_PCS40G    V_PERR_RX1_PCS40G(1U)
+
+#define S_PERR_RX2_PCS40G    9
+#define V_PERR_RX2_PCS40G(x) ((x) << S_PERR_RX2_PCS40G)
+#define F_PERR_RX2_PCS40G    V_PERR_RX2_PCS40G(1U)
+
+#define S_PERR_RX3_PCS40G    8
+#define V_PERR_RX3_PCS40G(x) ((x) << S_PERR_RX3_PCS40G)
+#define F_PERR_RX3_PCS40G    V_PERR_RX3_PCS40G(1U)
+
+#define S_PERR_RX0_FEC40G    7
+#define V_PERR_RX0_FEC40G(x) ((x) << S_PERR_RX0_FEC40G)
+#define F_PERR_RX0_FEC40G    V_PERR_RX0_FEC40G(1U)
+
+#define S_PERR_RX1_FEC40G    6
+#define V_PERR_RX1_FEC40G(x) ((x) << S_PERR_RX1_FEC40G)
+#define F_PERR_RX1_FEC40G    V_PERR_RX1_FEC40G(1U)
+
+#define S_PERR_RX2_FEC40G    5
+#define V_PERR_RX2_FEC40G(x) ((x) << S_PERR_RX2_FEC40G)
+#define F_PERR_RX2_FEC40G    V_PERR_RX2_FEC40G(1U)
+
+#define S_PERR_RX3_FEC40G    4
+#define V_PERR_RX3_FEC40G(x) ((x) << S_PERR_RX3_FEC40G)
+#define F_PERR_RX3_FEC40G    V_PERR_RX3_FEC40G(1U)
+
+#define S_PERR_RX_PCS10G_LPBK    3
+#define V_PERR_RX_PCS10G_LPBK(x) ((x) << S_PERR_RX_PCS10G_LPBK)
+#define F_PERR_RX_PCS10G_LPBK    V_PERR_RX_PCS10G_LPBK(1U)
+
+#define S_PERR_RX_PCS10G    2
+#define V_PERR_RX_PCS10G(x) ((x) << S_PERR_RX_PCS10G)
+#define F_PERR_RX_PCS10G    V_PERR_RX_PCS10G(1U)
+
+#define S_PERR_RX_PCS1G    1
+#define V_PERR_RX_PCS1G(x) ((x) << S_PERR_RX_PCS1G)
+#define F_PERR_RX_PCS1G    V_PERR_RX_PCS1G(1U)
+
+#define S_PERR_TX_PCS1G    0
+#define V_PERR_TX_PCS1G(x) ((x) << S_PERR_TX_PCS1G)
+#define F_PERR_TX_PCS1G    V_PERR_TX_PCS1G(1U)
+
 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
+
+#define S_T6_PERR_PKT_RAM    31
+#define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
+#define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
+
+#define S_T6_PERR_MASK_RAM    30
+#define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
+#define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
+
+#define S_T6_PERR_CRC_RAM    29
+#define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
+#define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
+
 #define A_MAC_PORT_PERR_ENABLE 0x8e8
+
+#define S_T6_PERR_PKT_RAM    31
+#define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
+#define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
+
+#define S_T6_PERR_MASK_RAM    30
+#define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
+#define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
+
+#define S_T6_PERR_CRC_RAM    29
+#define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
+#define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
+
 #define A_MAC_PORT_PERR_INJECT 0x8ec
+
+#define S_MEMSEL_PERR    1
+#define M_MEMSEL_PERR    0x3fU
+#define V_MEMSEL_PERR(x) ((x) << S_MEMSEL_PERR)
+#define G_MEMSEL_PERR(x) (((x) >> S_MEMSEL_PERR) & M_MEMSEL_PERR)
+
 #define A_MAC_PORT_HSS_CFG0 0x8f0
 
 #define S_HSSREFCLKVALIDA    20
@@ -34160,6 +46844,16 @@
 #define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA)
 #define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA)
 
+#define S_T6_HSSCALSSTN    22
+#define M_T6_HSSCALSSTN    0x3fU
+#define V_T6_HSSCALSSTN(x) ((x) << S_T6_HSSCALSSTN)
+#define G_T6_HSSCALSSTN(x) (((x) >> S_T6_HSSCALSSTN) & M_T6_HSSCALSSTN)
+
+#define S_T6_HSSCALSSTP    16
+#define M_T6_HSSCALSSTP    0x3fU
+#define V_T6_HSSCALSSTP(x) ((x) << S_T6_HSSCALSSTP)
+#define G_T6_HSSCALSSTP(x) (((x) >> S_T6_HSSCALSSTP) & M_T6_HSSCALSSTP)
+
 #define A_MAC_PORT_HSS_CFG4 0x900
 
 #define S_HSSDIVSELA    9
@@ -34172,6 +46866,24 @@
 #define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB)
 #define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB)
 
+#define S_HSSREFDIVA    24
+#define M_HSSREFDIVA    0xfU
+#define V_HSSREFDIVA(x) ((x) << S_HSSREFDIVA)
+#define G_HSSREFDIVA(x) (((x) >> S_HSSREFDIVA) & M_HSSREFDIVA)
+
+#define S_HSSREFDIVB    20
+#define M_HSSREFDIVB    0xfU
+#define V_HSSREFDIVB(x) ((x) << S_HSSREFDIVB)
+#define G_HSSREFDIVB(x) (((x) >> S_HSSREFDIVB) & M_HSSREFDIVB)
+
+#define S_HSSPLLDIV2B    19
+#define V_HSSPLLDIV2B(x) ((x) << S_HSSPLLDIV2B)
+#define F_HSSPLLDIV2B    V_HSSPLLDIV2B(1U)
+
+#define S_HSSPLLDIV2A    18
+#define V_HSSPLLDIV2A(x) ((x) << S_HSSPLLDIV2A)
+#define F_HSSPLLDIV2A    V_HSSPLLDIV2A(1U)
+
 #define A_MAC_PORT_HSS_STATUS 0x904
 
 #define S_HSSPLLLOCKB    3
@@ -34190,6 +46902,22 @@
 #define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA)
 #define F_HSSPRTREADYA    V_HSSPRTREADYA(1U)
 
+#define S_RXDERROFLOW    19
+#define V_RXDERROFLOW(x) ((x) << S_RXDERROFLOW)
+#define F_RXDERROFLOW    V_RXDERROFLOW(1U)
+
+#define S_RXCERROFLOW    18
+#define V_RXCERROFLOW(x) ((x) << S_RXCERROFLOW)
+#define F_RXCERROFLOW    V_RXCERROFLOW(1U)
+
+#define S_RXBERROFLOW    17
+#define V_RXBERROFLOW(x) ((x) << S_RXBERROFLOW)
+#define F_RXBERROFLOW    V_RXBERROFLOW(1U)
+
+#define S_RXAERROFLOW    16
+#define V_RXAERROFLOW(x) ((x) << S_RXAERROFLOW)
+#define F_RXAERROFLOW    V_RXAERROFLOW(1U)
+
 #define A_MAC_PORT_HSS_EEE_STATUS 0x908
 
 #define S_RXAQUIET_STATUS    15
@@ -34578,6 +47306,27 @@
 #define V_Q(x) ((x) << S_Q)
 #define G_Q(x) (((x) >> S_Q) & M_Q)
 
+#define S_ALARM_EN    21
+#define V_ALARM_EN(x) ((x) << S_ALARM_EN)
+#define F_ALARM_EN    V_ALARM_EN(1U)
+
+#define S_ALARM_START    20
+#define V_ALARM_START(x) ((x) << S_ALARM_START)
+#define F_ALARM_START    V_ALARM_START(1U)
+
+#define S_PPS_EN    19
+#define V_PPS_EN(x) ((x) << S_PPS_EN)
+#define F_PPS_EN    V_PPS_EN(1U)
+
+#define A_MAC_PORT_PTP_PPS 0x9b0
+#define A_MAC_PORT_PTP_SINGLE_ALARM 0x9b4
+#define A_MAC_PORT_PTP_PERIODIC_ALARM 0x9b8
+#define A_MAC_PORT_PTP_STATUS 0x9bc
+
+#define S_ALARM_DONE    0
+#define V_ALARM_DONE(x) ((x) << S_ALARM_DONE)
+#define F_ALARM_DONE    V_ALARM_DONE(1U)
+
 #define A_MAC_PORT_MTIP_REVISION 0xa00
 
 #define S_CUSTREV    16
@@ -34937,6 +47686,18 @@
 #define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0)
 #define F_SPEEDSEL0    V_SPEEDSEL0(1U)
 
+#define A_MAC_PORT_MTIP_1G10G_REVISION 0xd00
+
+#define S_VER_1G10G    8
+#define M_VER_1G10G    0xffU
+#define V_VER_1G10G(x) ((x) << S_VER_1G10G)
+#define G_VER_1G10G(x) (((x) >> S_VER_1G10G) & M_VER_1G10G)
+
+#define S_REV_1G10G    0
+#define M_REV_1G10G    0xffU
+#define V_REV_1G10G(x) ((x) << S_REV_1G10G)
+#define G_REV_1G10G(x) (((x) >> S_REV_1G10G) & M_REV_1G10G)
+
 #define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04
 
 #define S_100BASET4    15
@@ -34983,8 +47744,52 @@
 #define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY)
 #define F_EXTDCAPABILITY    V_EXTDCAPABILITY(1U)
 
+#define A_MAC_PORT_MTIP_1G10G_SCRATCH 0xd04
 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08
+#define A_MAC_PORT_MTIP_1G10G_COMMAND_CONFIG 0xd08
+
+#define S_SHORT_DISCARD    25
+#define V_SHORT_DISCARD(x) ((x) << S_SHORT_DISCARD)
+#define F_SHORT_DISCARD    V_SHORT_DISCARD(1U)
+
+#define S_REG_LOWP_RXEMPTY    24
+#define V_REG_LOWP_RXEMPTY(x) ((x) << S_REG_LOWP_RXEMPTY)
+#define F_REG_LOWP_RXEMPTY    V_REG_LOWP_RXEMPTY(1U)
+
+#define S_TX_LOWP_ENA    23
+#define V_TX_LOWP_ENA(x) ((x) << S_TX_LOWP_ENA)
+#define F_TX_LOWP_ENA    V_TX_LOWP_ENA(1U)
+
+#define S_TX_FLUSH_EN    22
+#define V_TX_FLUSH_EN(x) ((x) << S_TX_FLUSH_EN)
+#define F_TX_FLUSH_EN    V_TX_FLUSH_EN(1U)
+
+#define S_SFD_ANY    21
+#define V_SFD_ANY(x) ((x) << S_SFD_ANY)
+#define F_SFD_ANY    V_SFD_ANY(1U)
+
+#define S_COL_CNT_EXT    18
+#define V_COL_CNT_EXT(x) ((x) << S_COL_CNT_EXT)
+#define F_COL_CNT_EXT    V_COL_CNT_EXT(1U)
+
+#define S_FORCE_SEND_IDLE    16
+#define V_FORCE_SEND_IDLE(x) ((x) << S_FORCE_SEND_IDLE)
+#define F_FORCE_SEND_IDLE    V_FORCE_SEND_IDLE(1U)
+
+#define S_CNTL_FRM_ENA    13
+#define V_CNTL_FRM_ENA(x) ((x) << S_CNTL_FRM_ENA)
+#define F_CNTL_FRM_ENA    V_CNTL_FRM_ENA(1U)
+
+#define S_RX_ENAMAC    1
+#define V_RX_ENAMAC(x) ((x) << S_RX_ENAMAC)
+#define F_RX_ENAMAC    V_RX_ENAMAC(1U)
+
+#define S_TX_ENAMAC    0
+#define V_TX_ENAMAC(x) ((x) << S_TX_ENAMAC)
+#define F_TX_ENAMAC    V_TX_ENAMAC(1U)
+
 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c
+#define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_0 0xd0c
 #define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10
 
 #define S_RF2    13
@@ -35011,6 +47816,7 @@
 #define V_FD(x) ((x) << S_FD)
 #define F_FD    V_FD(1U)
 
+#define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_1 0xd10
 #define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14
 
 #define S_CULINKSTATUS    15
@@ -35026,6 +47832,18 @@
 #define V_CUSPEED(x) ((x) << S_CUSPEED)
 #define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED)
 
+#define A_MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU 0xd14
+
+#define S_SET_LEN    16
+#define M_SET_LEN    0xffffU
+#define V_SET_LEN(x) ((x) << S_SET_LEN)
+#define G_SET_LEN(x) (((x) >> S_SET_LEN) & M_SET_LEN)
+
+#define S_FRM_LEN_SET    0
+#define M_FRM_LEN_SET    0xffffU
+#define V_FRM_LEN_SET(x) ((x) << S_FRM_LEN_SET)
+#define G_FRM_LEN_SET(x) (((x) >> S_FRM_LEN_SET) & M_FRM_LEN_SET)
+
 #define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18
 
 #define S_PGRCVD    1
@@ -35037,8 +47855,117 @@
 #define F_REALTIMEPGRCVD    V_REALTIMEPGRCVD(1U)
 
 #define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c
+#define A_MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS 0xd1c
+
+#define S_RX1G10G_EMPTY    16
+#define M_RX1G10G_EMPTY    0xffffU
+#define V_RX1G10G_EMPTY(x) ((x) << S_RX1G10G_EMPTY)
+#define G_RX1G10G_EMPTY(x) (((x) >> S_RX1G10G_EMPTY) & M_RX1G10G_EMPTY)
+
+#define S_RX1G10G_AVAIL    0
+#define M_RX1G10G_AVAIL    0xffffU
+#define V_RX1G10G_AVAIL(x) ((x) << S_RX1G10G_AVAIL)
+#define G_RX1G10G_AVAIL(x) (((x) >> S_RX1G10G_AVAIL) & M_RX1G10G_AVAIL)
+
 #define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20
+#define A_MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS 0xd20
+
+#define S_TX1G10G_EMPTY    16
+#define M_TX1G10G_EMPTY    0xffffU
+#define V_TX1G10G_EMPTY(x) ((x) << S_TX1G10G_EMPTY)
+#define G_TX1G10G_EMPTY(x) (((x) >> S_TX1G10G_EMPTY) & M_TX1G10G_EMPTY)
+
+#define S_TX1G10G_AVAIL    0
+#define M_TX1G10G_AVAIL    0xffffU
+#define V_TX1G10G_AVAIL(x) ((x) << S_TX1G10G_AVAIL)
+#define G_TX1G10G_AVAIL(x) (((x) >> S_TX1G10G_AVAIL) & M_TX1G10G_AVAIL)
+
+#define A_MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E 0xd24
+
+#define S_ALMOSTFULL    16
+#define M_ALMOSTFULL    0xffffU
+#define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
+#define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
+
+#define S_ALMOSTEMPTY    0
+#define M_ALMOSTEMPTY    0xffffU
+#define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
+#define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
+
+#define A_MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E 0xd28
+#define A_MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD 0xd2c
+#define A_MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS 0xd30
+
+#define S_CLK_DIVISOR    7
+#define M_CLK_DIVISOR    0x1ffU
+#define V_CLK_DIVISOR(x) ((x) << S_CLK_DIVISOR)
+#define G_CLK_DIVISOR(x) (((x) >> S_CLK_DIVISOR) & M_CLK_DIVISOR)
+
+#define S_ENA_CLAUSE    6
+#define V_ENA_CLAUSE(x) ((x) << S_ENA_CLAUSE)
+#define F_ENA_CLAUSE    V_ENA_CLAUSE(1U)
+
+#define S_PREAMBLE_DISABLE    5
+#define V_PREAMBLE_DISABLE(x) ((x) << S_PREAMBLE_DISABLE)
+#define F_PREAMBLE_DISABLE    V_PREAMBLE_DISABLE(1U)
+
+#define S_HOLD_TIME_SETTING    2
+#define M_HOLD_TIME_SETTING    0x7U
+#define V_HOLD_TIME_SETTING(x) ((x) << S_HOLD_TIME_SETTING)
+#define G_HOLD_TIME_SETTING(x) (((x) >> S_HOLD_TIME_SETTING) & M_HOLD_TIME_SETTING)
+
+#define S_MDIO_READ_ERROR    1
+#define V_MDIO_READ_ERROR(x) ((x) << S_MDIO_READ_ERROR)
+#define F_MDIO_READ_ERROR    V_MDIO_READ_ERROR(1U)
+
+#define A_MAC_PORT_MTIP_1G10G_MDIO_COMMAND 0xd34
+
+#define S_READ_MODE    15
+#define V_READ_MODE(x) ((x) << S_READ_MODE)
+#define F_READ_MODE    V_READ_MODE(1U)
+
+#define S_POST_INCR_READ    14
+#define V_POST_INCR_READ(x) ((x) << S_POST_INCR_READ)
+#define F_POST_INCR_READ    V_POST_INCR_READ(1U)
+
+#define S_PORT_PHY_ADDR    5
+#define M_PORT_PHY_ADDR    0x1fU
+#define V_PORT_PHY_ADDR(x) ((x) << S_PORT_PHY_ADDR)
+#define G_PORT_PHY_ADDR(x) (((x) >> S_PORT_PHY_ADDR) & M_PORT_PHY_ADDR)
+
+#define S_DEVICE_REG_ADDR    0
+#define M_DEVICE_REG_ADDR    0x1fU
+#define V_DEVICE_REG_ADDR(x) ((x) << S_DEVICE_REG_ADDR)
+#define G_DEVICE_REG_ADDR(x) (((x) >> S_DEVICE_REG_ADDR) & M_DEVICE_REG_ADDR)
+
+#define A_MAC_PORT_MTIP_1G10G_MDIO_DATA 0xd38
+
+#define S_MDIO_DATA    0
+#define M_MDIO_DATA    0xffffU
+#define V_MDIO_DATA(x) ((x) << S_MDIO_DATA)
+#define G_MDIO_DATA(x) (((x) >> S_MDIO_DATA) & M_MDIO_DATA)
+
 #define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c
+#define A_MAC_PORT_MTIP_1G10G_MDIO_REGADDR 0xd3c
+#define A_MAC_PORT_MTIP_1G10G_STATUS 0xd40
+
+#define S_RX_LINT_FAULT    7
+#define V_RX_LINT_FAULT(x) ((x) << S_RX_LINT_FAULT)
+#define F_RX_LINT_FAULT    V_RX_LINT_FAULT(1U)
+
+#define S_RX_EMPTY    6
+#define V_RX_EMPTY(x) ((x) << S_RX_EMPTY)
+#define F_RX_EMPTY    V_RX_EMPTY(1U)
+
+#define S_TX_EMPTY    5
+#define V_TX_EMPTY(x) ((x) << S_TX_EMPTY)
+#define F_TX_EMPTY    V_TX_EMPTY(1U)
+
+#define S_RX_LOWP    4
+#define V_RX_LOWP(x) ((x) << S_RX_LOWP)
+#define F_RX_LOWP    V_RX_LOWP(1U)
+
+#define A_MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH 0xd44
 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48
 
 #define S_COUNT_LO    0
@@ -35046,6 +47973,7 @@
 #define V_COUNT_LO(x) ((x) << S_COUNT_LO)
 #define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO)
 
+#define A_MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER 0xd48
 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c
 
 #define S_COUNT_HI    0
@@ -35053,6 +47981,7 @@
 #define V_COUNT_HI(x) ((x) << S_COUNT_HI)
 #define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI)
 
+#define A_MAC_PORT_MTIP_1G10G_INIT_CREDIT 0xd4c
 #define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50
 
 #define S_SGMII_PCS_ENABLE    5
@@ -35076,6 +48005,272 @@
 #define V_SGMII_ENA(x) ((x) << S_SGMII_ENA)
 #define F_SGMII_ENA    V_SGMII_ENA(1U)
 
+#define A_MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA 0xd54
+
+#define S_CL1_PAUSE_QUANTA    16
+#define M_CL1_PAUSE_QUANTA    0xffffU
+#define V_CL1_PAUSE_QUANTA(x) ((x) << S_CL1_PAUSE_QUANTA)
+#define G_CL1_PAUSE_QUANTA(x) (((x) >> S_CL1_PAUSE_QUANTA) & M_CL1_PAUSE_QUANTA)
+
+#define S_CL0_PAUSE_QUANTA    0
+#define M_CL0_PAUSE_QUANTA    0xffffU
+#define V_CL0_PAUSE_QUANTA(x) ((x) << S_CL0_PAUSE_QUANTA)
+#define G_CL0_PAUSE_QUANTA(x) (((x) >> S_CL0_PAUSE_QUANTA) & M_CL0_PAUSE_QUANTA)
+
+#define A_MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA 0xd58
+
+#define S_CL3_PAUSE_QUANTA    16
+#define M_CL3_PAUSE_QUANTA    0xffffU
+#define V_CL3_PAUSE_QUANTA(x) ((x) << S_CL3_PAUSE_QUANTA)
+#define G_CL3_PAUSE_QUANTA(x) (((x) >> S_CL3_PAUSE_QUANTA) & M_CL3_PAUSE_QUANTA)
+
+#define S_CL2_PAUSE_QUANTA    0
+#define M_CL2_PAUSE_QUANTA    0xffffU
+#define V_CL2_PAUSE_QUANTA(x) ((x) << S_CL2_PAUSE_QUANTA)
+#define G_CL2_PAUSE_QUANTA(x) (((x) >> S_CL2_PAUSE_QUANTA) & M_CL2_PAUSE_QUANTA)
+
+#define A_MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA 0xd5c
+
+#define S_CL5_PAUSE_QUANTA    16
+#define M_CL5_PAUSE_QUANTA    0xffffU
+#define V_CL5_PAUSE_QUANTA(x) ((x) << S_CL5_PAUSE_QUANTA)
+#define G_CL5_PAUSE_QUANTA(x) (((x) >> S_CL5_PAUSE_QUANTA) & M_CL5_PAUSE_QUANTA)
+
+#define S_CL4_PAUSE_QUANTA    0
+#define M_CL4_PAUSE_QUANTA    0xffffU
+#define V_CL4_PAUSE_QUANTA(x) ((x) << S_CL4_PAUSE_QUANTA)
+#define G_CL4_PAUSE_QUANTA(x) (((x) >> S_CL4_PAUSE_QUANTA) & M_CL4_PAUSE_QUANTA)
+
+#define A_MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA 0xd60
+
+#define S_CL7_PAUSE_QUANTA    16
+#define M_CL7_PAUSE_QUANTA    0xffffU
+#define V_CL7_PAUSE_QUANTA(x) ((x) << S_CL7_PAUSE_QUANTA)
+#define G_CL7_PAUSE_QUANTA(x) (((x) >> S_CL7_PAUSE_QUANTA) & M_CL7_PAUSE_QUANTA)
+
+#define S_CL6_PAUSE_QUANTA    0
+#define M_CL6_PAUSE_QUANTA    0xffffU
+#define V_CL6_PAUSE_QUANTA(x) ((x) << S_CL6_PAUSE_QUANTA)
+#define G_CL6_PAUSE_QUANTA(x) (((x) >> S_CL6_PAUSE_QUANTA) & M_CL6_PAUSE_QUANTA)
+
+#define A_MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH 0xd64
+
+#define S_CL1_QUANTA_THRESH    16
+#define M_CL1_QUANTA_THRESH    0xffffU
+#define V_CL1_QUANTA_THRESH(x) ((x) << S_CL1_QUANTA_THRESH)
+#define G_CL1_QUANTA_THRESH(x) (((x) >> S_CL1_QUANTA_THRESH) & M_CL1_QUANTA_THRESH)
+
+#define S_CL0_QUANTA_THRESH    0
+#define M_CL0_QUANTA_THRESH    0xffffU
+#define V_CL0_QUANTA_THRESH(x) ((x) << S_CL0_QUANTA_THRESH)
+#define G_CL0_QUANTA_THRESH(x) (((x) >> S_CL0_QUANTA_THRESH) & M_CL0_QUANTA_THRESH)
+
+#define A_MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH 0xd68
+
+#define S_CL3_QUANTA_THRESH    16
+#define M_CL3_QUANTA_THRESH    0xffffU
+#define V_CL3_QUANTA_THRESH(x) ((x) << S_CL3_QUANTA_THRESH)
+#define G_CL3_QUANTA_THRESH(x) (((x) >> S_CL3_QUANTA_THRESH) & M_CL3_QUANTA_THRESH)
+
+#define S_CL2_QUANTA_THRESH    0
+#define M_CL2_QUANTA_THRESH    0xffffU
+#define V_CL2_QUANTA_THRESH(x) ((x) << S_CL2_QUANTA_THRESH)
+#define G_CL2_QUANTA_THRESH(x) (((x) >> S_CL2_QUANTA_THRESH) & M_CL2_QUANTA_THRESH)
+
+#define A_MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH 0xd6c
+
+#define S_CL5_QUANTA_THRESH    16
+#define M_CL5_QUANTA_THRESH    0xffffU
+#define V_CL5_QUANTA_THRESH(x) ((x) << S_CL5_QUANTA_THRESH)
+#define G_CL5_QUANTA_THRESH(x) (((x) >> S_CL5_QUANTA_THRESH) & M_CL5_QUANTA_THRESH)
+
+#define S_CL4_QUANTA_THRESH    0
+#define M_CL4_QUANTA_THRESH    0xffffU
+#define V_CL4_QUANTA_THRESH(x) ((x) << S_CL4_QUANTA_THRESH)
+#define G_CL4_QUANTA_THRESH(x) (((x) >> S_CL4_QUANTA_THRESH) & M_CL4_QUANTA_THRESH)
+
+#define A_MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH 0xd70
+
+#define S_CL7_QUANTA_THRESH    16
+#define M_CL7_QUANTA_THRESH    0xffffU
+#define V_CL7_QUANTA_THRESH(x) ((x) << S_CL7_QUANTA_THRESH)
+#define G_CL7_QUANTA_THRESH(x) (((x) >> S_CL7_QUANTA_THRESH) & M_CL7_QUANTA_THRESH)
+
+#define S_CL6_QUANTA_THRESH    0
+#define M_CL6_QUANTA_THRESH    0xffffU
+#define V_CL6_QUANTA_THRESH(x) ((x) << S_CL6_QUANTA_THRESH)
+#define G_CL6_QUANTA_THRESH(x) (((x) >> S_CL6_QUANTA_THRESH) & M_CL6_QUANTA_THRESH)
+
+#define A_MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS 0xd74
+
+#define S_STATUS_BIT    0
+#define M_STATUS_BIT    0xffU
+#define V_STATUS_BIT(x) ((x) << S_STATUS_BIT)
+#define G_STATUS_BIT(x) (((x) >> S_STATUS_BIT) & M_STATUS_BIT)
+
+#define A_MAC_PORT_MTIP_1G10G_TS_TIMESTAMP 0xd7c
+#define A_MAC_PORT_MTIP_1G10G_STATN_CONFIG 0xde0
+
+#define S_CLEAR    2
+#define V_CLEAR(x) ((x) << S_CLEAR)
+#define F_CLEAR    V_CLEAR(1U)
+
+#define S_CLEAR_ON_READ    1
+#define V_CLEAR_ON_READ(x) ((x) << S_CLEAR_ON_READ)
+#define F_CLEAR_ON_READ    V_CLEAR_ON_READ(1U)
+
+#define S_SATURATE    0
+#define V_SATURATE(x) ((x) << S_SATURATE)
+#define F_SATURATE    V_SATURATE(1U)
+
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS 0xe00
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI 0xe04
+#define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOK 0xe08
+#define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI 0xe0c
+#define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS 0xe10
+#define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI 0xe14
+#define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES 0xe18
+#define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI 0xe1c
+#define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOK 0xe20
+#define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI 0xe24
+#define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS 0xe28
+#define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI 0xe2c
+#define A_MAC_PORT_MTIP_1G10G_RX_VLANOK 0xe30
+#define A_MAC_PORT_MTIP_1G10G_RX_VLANOKHI 0xe34
+#define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORS 0xe38
+#define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI 0xe3c
+#define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS 0xe40
+#define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI 0xe44
+#define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS 0xe48
+#define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI 0xe4c
+#define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS 0xe50
+#define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI 0xe54
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS 0xe58
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI 0xe5c
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS 0xe60
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI 0xe64
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS 0xe68
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI 0xe6c
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS 0xe70
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI 0xe74
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS 0xe78
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI 0xe7c
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS 0xe80
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI 0xe84
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS 0xe88
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI 0xe8c
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS 0xe90
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI 0xe94
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS 0xe98
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xe9c
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX 0xea0
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI 0xea4
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS 0xea8
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI 0xeac
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS 0xeb0
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI 0xeb4
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS 0xeb8
+#define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI 0xebc
+#define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED 0xec0
+#define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI 0xec4
+#define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG 0xec8
+#define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI 0xecc
+#define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS 0xed0
+#define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI 0xed4
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS 0xf00
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI 0xf04
+#define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOK 0xf08
+#define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI 0xf0c
+#define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS 0xf10
+#define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI 0xf14
+#define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES 0xf18
+#define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI 0xf1c
+#define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOK 0xf20
+#define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI 0xf24
+#define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORS 0xf28
+#define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI 0xf2c
+#define A_MAC_PORT_MTIP_1G10G_TX_VLANOK 0xf30
+#define A_MAC_PORT_MTIP_1G10G_TX_VLANOKHI 0xf34
+#define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS 0xf38
+#define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI 0xf3c
+#define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS 0xf40
+#define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI 0xf44
+#define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS 0xf48
+#define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI 0xf4c
+#define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS 0xf50
+#define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI 0xf54
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS 0xf58
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI 0xf5c
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS 0xf60
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI 0xf64
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS 0xf68
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI 0xf6c
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS 0xf70
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI 0xf74
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS 0xf78
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI 0xf7c
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS 0xf80
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI 0xf84
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS 0xf88
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI 0xf8c
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS 0xf90
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI 0xf94
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS 0xf98
+#define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xf9c
+#define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU 0xfa0
+#define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI 0xfa4
+#define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES 0xfc0
+#define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI 0xfc4
+#define A_MAC_PORT_MTIP_1G10G_IF_MODE 0x1000
+
+#define S_MII_ENA_10    4
+#define V_MII_ENA_10(x) ((x) << S_MII_ENA_10)
+#define F_MII_ENA_10    V_MII_ENA_10(1U)
+
+#define S_IF_MODE    0
+#define M_IF_MODE    0x3U
+#define V_IF_MODE(x) ((x) << S_IF_MODE)
+#define G_IF_MODE(x) (((x) >> S_IF_MODE) & M_IF_MODE)
+
+#define A_MAC_PORT_MTIP_1G10G_IF_STATUS 0x1004
+
+#define S_IF_STATUS_MODE    0
+#define M_IF_STATUS_MODE    0x3U
+#define V_IF_STATUS_MODE(x) ((x) << S_IF_STATUS_MODE)
+#define G_IF_STATUS_MODE(x) (((x) >> S_IF_STATUS_MODE) & M_IF_STATUS_MODE)
+
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0 0x1080
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI 0x1084
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1 0x1088
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI 0x108c
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2 0x1090
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI 0x1094
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3 0x1098
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI 0x109c
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4 0x10a0
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI 0x10a4
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5 0x10a8
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI 0x10ac
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6 0x10b0
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI 0x10b4
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7 0x10b8
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI 0x10bc
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0 0x10c0
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI 0x10c4
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1 0x10c8
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI 0x10cc
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2 0x10d0
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI 0x10d4
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3 0x10d8
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI 0x10dc
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4 0x10e0
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI 0x10e4
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5 0x10e8
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI 0x10ec
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6 0x10f0
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI 0x10f4
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7 0x10f8
+#define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI 0x10fc
 #define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200
 
 #define S_ACTIVE    0
@@ -35083,6 +48278,28 @@
 #define V_ACTIVE(x) ((x) << S_ACTIVE)
 #define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE)
 
+#define A_T6_MAC_PORT_MTIP_SGMII_CONTROL 0x1200
+
+#define S_SPEED_SEL    13
+#define V_SPEED_SEL(x) ((x) << S_SPEED_SEL)
+#define F_SPEED_SEL    V_SPEED_SEL(1U)
+
+#define S_PWR_DWN    11
+#define V_PWR_DWN(x) ((x) << S_PWR_DWN)
+#define F_PWR_DWN    V_PWR_DWN(1U)
+
+#define S_DUPLEX_MODE    8
+#define V_DUPLEX_MODE(x) ((x) << S_DUPLEX_MODE)
+#define F_DUPLEX_MODE    V_DUPLEX_MODE(1U)
+
+#define S_COLLISION_TEST    7
+#define V_COLLISION_TEST(x) ((x) << S_COLLISION_TEST)
+#define F_COLLISION_TEST    V_COLLISION_TEST(1U)
+
+#define S_T6_SPEED_SEL1    6
+#define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1)
+#define F_T6_SPEED_SEL1    V_T6_SPEED_SEL1(1U)
+
 #define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204
 
 #define S_MODE_CTL    0
@@ -35090,6 +48307,12 @@
 #define V_MODE_CTL(x) ((x) << S_MODE_CTL)
 #define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL)
 
+#define A_T6_MAC_PORT_MTIP_SGMII_STATUS 0x1204
+
+#define S_T6_REM_FAULT    4
+#define V_T6_REM_FAULT(x) ((x) << S_T6_REM_FAULT)
+#define F_T6_REM_FAULT    V_T6_REM_FAULT(1U)
+
 #define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208
 
 #define S_TXCLK_CTL    0
@@ -35097,7 +48320,28 @@
 #define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL)
 #define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL)
 
+#define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0x1208
 #define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c
+#define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0x120c
+#define A_T6_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0x1210
+#define A_T6_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0x1214
+#define A_T6_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0x1218
+
+#define S_NEXT_PAGE_ABLE    2
+#define V_NEXT_PAGE_ABLE(x) ((x) << S_NEXT_PAGE_ABLE)
+#define F_NEXT_PAGE_ABLE    V_NEXT_PAGE_ABLE(1U)
+
+#define S_PAGE_RECEIVE    1
+#define V_PAGE_RECEIVE(x) ((x) << S_PAGE_RECEIVE)
+#define F_PAGE_RECEIVE    V_PAGE_RECEIVE(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_NP_TX 0x121c
+
+#define S_NP_TX    0
+#define M_NP_TX    0xffffU
+#define V_NP_TX(x) ((x) << S_NP_TX)
+#define G_NP_TX(x) (((x) >> S_NP_TX) & M_NP_TX)
+
 #define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220
 
 #define S_COL_CNT    0
@@ -35105,12 +48349,541 @@
 #define V_COL_CNT(x) ((x) << S_COL_CNT)
 #define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT)
 
+#define A_MAC_PORT_MTIP_SGMII_LP_NP_RX 0x1220
+
+#define S_LP_NP_RX    0
+#define M_LP_NP_RX    0xffffU
+#define V_LP_NP_RX(x) ((x) << S_LP_NP_RX)
+#define G_LP_NP_RX(x) (((x) >> S_LP_NP_RX) & M_LP_NP_RX)
+
+#define A_T6_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0x123c
+
+#define S_EXTENDED_STATUS    0
+#define M_EXTENDED_STATUS    0xffffU
+#define V_EXTENDED_STATUS(x) ((x) << S_EXTENDED_STATUS)
+#define G_EXTENDED_STATUS(x) (((x) >> S_EXTENDED_STATUS) & M_EXTENDED_STATUS)
+
 #define A_MAC_PORT_MTIP_VL_INTVL 0x1240
 
 #define S_VL_INTVL    1
 #define V_VL_INTVL(x) ((x) << S_VL_INTVL)
 #define F_VL_INTVL    V_VL_INTVL(1U)
 
+#define A_MAC_PORT_MTIP_SGMII_SCRATCH 0x1240
+
+#define S_SCRATCH    0
+#define M_SCRATCH    0xffffU
+#define V_SCRATCH(x) ((x) << S_SCRATCH)
+#define G_SCRATCH(x) (((x) >> S_SCRATCH) & M_SCRATCH)
+
+#define A_MAC_PORT_MTIP_SGMII_REV 0x1244
+
+#define S_SGMII_VER    8
+#define M_SGMII_VER    0xffU
+#define V_SGMII_VER(x) ((x) << S_SGMII_VER)
+#define G_SGMII_VER(x) (((x) >> S_SGMII_VER) & M_SGMII_VER)
+
+#define S_SGMII_REV    0
+#define M_SGMII_REV    0xffU
+#define V_SGMII_REV(x) ((x) << S_SGMII_REV)
+#define G_SGMII_REV(x) (((x) >> S_SGMII_REV) & M_SGMII_REV)
+
+#define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0x1248
+
+#define S_LINK_TIMER_LO    0
+#define M_LINK_TIMER_LO    0xffffU
+#define V_LINK_TIMER_LO(x) ((x) << S_LINK_TIMER_LO)
+#define G_LINK_TIMER_LO(x) (((x) >> S_LINK_TIMER_LO) & M_LINK_TIMER_LO)
+
+#define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0x124c
+
+#define S_LINK_TIMER_HI    0
+#define M_LINK_TIMER_HI    0xffffU
+#define V_LINK_TIMER_HI(x) ((x) << S_LINK_TIMER_HI)
+#define G_LINK_TIMER_HI(x) (((x) >> S_LINK_TIMER_HI) & M_LINK_TIMER_HI)
+
+#define A_T6_MAC_PORT_MTIP_SGMII_IF_MODE 0x1250
+
+#define S_SGMII_DUPLEX    4
+#define V_SGMII_DUPLEX(x) ((x) << S_SGMII_DUPLEX)
+#define F_SGMII_DUPLEX    V_SGMII_DUPLEX(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_DECODE_ERROR 0x1254
+
+#define S_T6_DECODE_ERROR    0
+#define M_T6_DECODE_ERROR    0xffffU
+#define V_T6_DECODE_ERROR(x) ((x) << S_T6_DECODE_ERROR)
+#define G_T6_DECODE_ERROR(x) (((x) >> S_T6_DECODE_ERROR) & M_T6_DECODE_ERROR)
+
+#define A_MAC_PORT_MTIP_KR_PCS_CONTROL_1 0x1300
+
+#define S_LOW_POWER    11
+#define V_LOW_POWER(x) ((x) << S_LOW_POWER)
+#define F_LOW_POWER    V_LOW_POWER(1U)
+
+#define S_T6_SPEED_SEL1    6
+#define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1)
+#define F_T6_SPEED_SEL1    V_T6_SPEED_SEL1(1U)
+
+#define S_SPEED_SEL2    2
+#define M_SPEED_SEL2    0xfU
+#define V_SPEED_SEL2(x) ((x) << S_SPEED_SEL2)
+#define G_SPEED_SEL2(x) (((x) >> S_SPEED_SEL2) & M_SPEED_SEL2)
+
+#define A_MAC_PORT_MTIP_KR_PCS_STATUS_1 0x1304
+
+#define S_TX_LPI    11
+#define V_TX_LPI(x) ((x) << S_TX_LPI)
+#define F_TX_LPI    V_TX_LPI(1U)
+
+#define S_RX_LPI    10
+#define V_RX_LPI(x) ((x) << S_RX_LPI)
+#define F_RX_LPI    V_RX_LPI(1U)
+
+#define S_TX_LPI_ACTIVE    9
+#define V_TX_LPI_ACTIVE(x) ((x) << S_TX_LPI_ACTIVE)
+#define F_TX_LPI_ACTIVE    V_TX_LPI_ACTIVE(1U)
+
+#define S_RX_LPI_ACTIVE    8
+#define V_RX_LPI_ACTIVE(x) ((x) << S_RX_LPI_ACTIVE)
+#define F_RX_LPI_ACTIVE    V_RX_LPI_ACTIVE(1U)
+
+#define S_FAULT    7
+#define V_FAULT(x) ((x) << S_FAULT)
+#define F_FAULT    V_FAULT(1U)
+
+#define S_PCS_RX_LINK_STAT    2
+#define V_PCS_RX_LINK_STAT(x) ((x) << S_PCS_RX_LINK_STAT)
+#define F_PCS_RX_LINK_STAT    V_PCS_RX_LINK_STAT(1U)
+
+#define S_LOW_POWER_ABILITY    1
+#define V_LOW_POWER_ABILITY(x) ((x) << S_LOW_POWER_ABILITY)
+#define F_LOW_POWER_ABILITY    V_LOW_POWER_ABILITY(1U)
+
+#define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1 0x1308
+#define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2 0x130c
+#define A_MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY 0x1310
+
+#define S_10G_CAPABLE    0
+#define V_10G_CAPABLE(x) ((x) << S_10G_CAPABLE)
+#define F_10G_CAPABLE    V_10G_CAPABLE(1U)
+
+#define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO 0x1314
+
+#define S_AUTO_NEGOTIATION_PRESENT    7
+#define V_AUTO_NEGOTIATION_PRESENT(x) ((x) << S_AUTO_NEGOTIATION_PRESENT)
+#define F_AUTO_NEGOTIATION_PRESENT    V_AUTO_NEGOTIATION_PRESENT(1U)
+
+#define S_DTE_XS_PRESENT    5
+#define V_DTE_XS_PRESENT(x) ((x) << S_DTE_XS_PRESENT)
+#define F_DTE_XS_PRESENT    V_DTE_XS_PRESENT(1U)
+
+#define S_PHY_XS_PRESENT    4
+#define V_PHY_XS_PRESENT(x) ((x) << S_PHY_XS_PRESENT)
+#define F_PHY_XS_PRESENT    V_PHY_XS_PRESENT(1U)
+
+#define S_PCS_PRESENT    3
+#define V_PCS_PRESENT(x) ((x) << S_PCS_PRESENT)
+#define F_PCS_PRESENT    V_PCS_PRESENT(1U)
+
+#define S_WIS_PRESENT    2
+#define V_WIS_PRESENT(x) ((x) << S_WIS_PRESENT)
+#define F_WIS_PRESENT    V_WIS_PRESENT(1U)
+
+#define S_PMD_PMA_PRESENT    1
+#define V_PMD_PMA_PRESENT(x) ((x) << S_PMD_PMA_PRESENT)
+#define F_PMD_PMA_PRESENT    V_PMD_PMA_PRESENT(1U)
+
+#define S_CLAUSE_22_REG_PRESENT    0
+#define V_CLAUSE_22_REG_PRESENT(x) ((x) << S_CLAUSE_22_REG_PRESENT)
+#define F_CLAUSE_22_REG_PRESENT    V_CLAUSE_22_REG_PRESENT(1U)
+
+#define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI 0x1318
+#define A_MAC_PORT_MTIP_KR_PCS_CONTROL_2 0x131c
+
+#define S_PCS_TYPE_SELECTION    0
+#define M_PCS_TYPE_SELECTION    0x3U
+#define V_PCS_TYPE_SELECTION(x) ((x) << S_PCS_TYPE_SELECTION)
+#define G_PCS_TYPE_SELECTION(x) (((x) >> S_PCS_TYPE_SELECTION) & M_PCS_TYPE_SELECTION)
+
+#define A_MAC_PORT_MTIP_KR_PCS_STATUS_2 0x1320
+
+#define S_DEVICE_PRESENT    14
+#define M_DEVICE_PRESENT    0x3U
+#define V_DEVICE_PRESENT(x) ((x) << S_DEVICE_PRESENT)
+#define G_DEVICE_PRESENT(x) (((x) >> S_DEVICE_PRESENT) & M_DEVICE_PRESENT)
+
+#define S_TRANSMIT_FAULT    11
+#define V_TRANSMIT_FAULT(x) ((x) << S_TRANSMIT_FAULT)
+#define F_TRANSMIT_FAULT    V_TRANSMIT_FAULT(1U)
+
+#define S_RECEIVE_FAULT    10
+#define V_RECEIVE_FAULT(x) ((x) << S_RECEIVE_FAULT)
+#define F_RECEIVE_FAULT    V_RECEIVE_FAULT(1U)
+
+#define S_10GBASE_W_CAPABLE    2
+#define V_10GBASE_W_CAPABLE(x) ((x) << S_10GBASE_W_CAPABLE)
+#define F_10GBASE_W_CAPABLE    V_10GBASE_W_CAPABLE(1U)
+
+#define S_10GBASE_X_CAPABLE    1
+#define V_10GBASE_X_CAPABLE(x) ((x) << S_10GBASE_X_CAPABLE)
+#define F_10GBASE_X_CAPABLE    V_10GBASE_X_CAPABLE(1U)
+
+#define S_10GBASE_R_CAPABLE    0
+#define V_10GBASE_R_CAPABLE(x) ((x) << S_10GBASE_R_CAPABLE)
+#define F_10GBASE_R_CAPABLE    V_10GBASE_R_CAPABLE(1U)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO 0x1338
+
+#define S_PCS_PACKAGE_IDENTIFIER_LO    0
+#define M_PCS_PACKAGE_IDENTIFIER_LO    0xffffU
+#define V_PCS_PACKAGE_IDENTIFIER_LO(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_LO)
+#define G_PCS_PACKAGE_IDENTIFIER_LO(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_LO) & M_PCS_PACKAGE_IDENTIFIER_LO)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI 0x133c
+
+#define S_PCS_PACKAGE_IDENTIFIER_HI    0
+#define M_PCS_PACKAGE_IDENTIFIER_HI    0xffffU
+#define V_PCS_PACKAGE_IDENTIFIER_HI(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_HI)
+#define G_PCS_PACKAGE_IDENTIFIER_HI(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_HI) & M_PCS_PACKAGE_IDENTIFIER_HI)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1 0x1380
+
+#define S_10GBASE_R_RX_LINK_STATUS    12
+#define V_10GBASE_R_RX_LINK_STATUS(x) ((x) << S_10GBASE_R_RX_LINK_STATUS)
+#define F_10GBASE_R_RX_LINK_STATUS    V_10GBASE_R_RX_LINK_STATUS(1U)
+
+#define S_PRBS9_PTTRN_TSTNG_ABILITY    3
+#define V_PRBS9_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS9_PTTRN_TSTNG_ABILITY)
+#define F_PRBS9_PTTRN_TSTNG_ABILITY    V_PRBS9_PTTRN_TSTNG_ABILITY(1U)
+
+#define S_PRBS31_PTTRN_TSTNG_ABILITY    2
+#define V_PRBS31_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS31_PTTRN_TSTNG_ABILITY)
+#define F_PRBS31_PTTRN_TSTNG_ABILITY    V_PRBS31_PTTRN_TSTNG_ABILITY(1U)
+
+#define S_10GBASE_R_PCS_HIGH_BER    1
+#define V_10GBASE_R_PCS_HIGH_BER(x) ((x) << S_10GBASE_R_PCS_HIGH_BER)
+#define F_10GBASE_R_PCS_HIGH_BER    V_10GBASE_R_PCS_HIGH_BER(1U)
+
+#define S_10GBASE_R_PCS_BLOCK_LOCK    0
+#define V_10GBASE_R_PCS_BLOCK_LOCK(x) ((x) << S_10GBASE_R_PCS_BLOCK_LOCK)
+#define F_10GBASE_R_PCS_BLOCK_LOCK    V_10GBASE_R_PCS_BLOCK_LOCK(1U)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2 0x1384
+
+#define S_LATCHED_BLOCK_LOCK    15
+#define V_LATCHED_BLOCK_LOCK(x) ((x) << S_LATCHED_BLOCK_LOCK)
+#define F_LATCHED_BLOCK_LOCK    V_LATCHED_BLOCK_LOCK(1U)
+
+#define S_LATCHED_HIGH_BER    14
+#define V_LATCHED_HIGH_BER(x) ((x) << S_LATCHED_HIGH_BER)
+#define F_LATCHED_HIGH_BER    V_LATCHED_HIGH_BER(1U)
+
+#define S_BERBER_COUNTER    8
+#define M_BERBER_COUNTER    0x3fU
+#define V_BERBER_COUNTER(x) ((x) << S_BERBER_COUNTER)
+#define G_BERBER_COUNTER(x) (((x) >> S_BERBER_COUNTER) & M_BERBER_COUNTER)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0 0x1388
+
+#define S_TEST_PATTERN_SEED_A0    0
+#define M_TEST_PATTERN_SEED_A0    0xffffU
+#define V_TEST_PATTERN_SEED_A0(x) ((x) << S_TEST_PATTERN_SEED_A0)
+#define G_TEST_PATTERN_SEED_A0(x) (((x) >> S_TEST_PATTERN_SEED_A0) & M_TEST_PATTERN_SEED_A0)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1 0x138c
+
+#define S_TEST_PATTERN_SEED_A1    0
+#define M_TEST_PATTERN_SEED_A1    0xffffU
+#define V_TEST_PATTERN_SEED_A1(x) ((x) << S_TEST_PATTERN_SEED_A1)
+#define G_TEST_PATTERN_SEED_A1(x) (((x) >> S_TEST_PATTERN_SEED_A1) & M_TEST_PATTERN_SEED_A1)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2 0x1390
+
+#define S_TEST_PATTERN_SEED_A2    0
+#define M_TEST_PATTERN_SEED_A2    0xffffU
+#define V_TEST_PATTERN_SEED_A2(x) ((x) << S_TEST_PATTERN_SEED_A2)
+#define G_TEST_PATTERN_SEED_A2(x) (((x) >> S_TEST_PATTERN_SEED_A2) & M_TEST_PATTERN_SEED_A2)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3 0x1394
+
+#define S_TEST_PATTERN_SEED_A3    0
+#define M_TEST_PATTERN_SEED_A3    0x3ffU
+#define V_TEST_PATTERN_SEED_A3(x) ((x) << S_TEST_PATTERN_SEED_A3)
+#define G_TEST_PATTERN_SEED_A3(x) (((x) >> S_TEST_PATTERN_SEED_A3) & M_TEST_PATTERN_SEED_A3)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0 0x1398
+
+#define S_TEST_PATTERN_SEED_B0    0
+#define M_TEST_PATTERN_SEED_B0    0xffffU
+#define V_TEST_PATTERN_SEED_B0(x) ((x) << S_TEST_PATTERN_SEED_B0)
+#define G_TEST_PATTERN_SEED_B0(x) (((x) >> S_TEST_PATTERN_SEED_B0) & M_TEST_PATTERN_SEED_B0)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1 0x139c
+
+#define S_TEST_PATTERN_SEED_B1    0
+#define M_TEST_PATTERN_SEED_B1    0xffffU
+#define V_TEST_PATTERN_SEED_B1(x) ((x) << S_TEST_PATTERN_SEED_B1)
+#define G_TEST_PATTERN_SEED_B1(x) (((x) >> S_TEST_PATTERN_SEED_B1) & M_TEST_PATTERN_SEED_B1)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2 0x13a0
+
+#define S_TEST_PATTERN_SEED_B2    0
+#define M_TEST_PATTERN_SEED_B2    0xffffU
+#define V_TEST_PATTERN_SEED_B2(x) ((x) << S_TEST_PATTERN_SEED_B2)
+#define G_TEST_PATTERN_SEED_B2(x) (((x) >> S_TEST_PATTERN_SEED_B2) & M_TEST_PATTERN_SEED_B2)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3 0x13a4
+
+#define S_TEST_PATTERN_SEED_B3    0
+#define M_TEST_PATTERN_SEED_B3    0x3ffU
+#define V_TEST_PATTERN_SEED_B3(x) ((x) << S_TEST_PATTERN_SEED_B3)
+#define G_TEST_PATTERN_SEED_B3(x) (((x) >> S_TEST_PATTERN_SEED_B3) & M_TEST_PATTERN_SEED_B3)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL 0x13a8
+
+#define S_PRBS9_TX_TST_PTTRN_EN    6
+#define V_PRBS9_TX_TST_PTTRN_EN(x) ((x) << S_PRBS9_TX_TST_PTTRN_EN)
+#define F_PRBS9_TX_TST_PTTRN_EN    V_PRBS9_TX_TST_PTTRN_EN(1U)
+
+#define S_PRBS31_RX_TST_PTTRN_EN    5
+#define V_PRBS31_RX_TST_PTTRN_EN(x) ((x) << S_PRBS31_RX_TST_PTTRN_EN)
+#define F_PRBS31_RX_TST_PTTRN_EN    V_PRBS31_RX_TST_PTTRN_EN(1U)
+
+#define S_PRBS31_TX_TST_PTTRN_EN    4
+#define V_PRBS31_TX_TST_PTTRN_EN(x) ((x) << S_PRBS31_TX_TST_PTTRN_EN)
+#define F_PRBS31_TX_TST_PTTRN_EN    V_PRBS31_TX_TST_PTTRN_EN(1U)
+
+#define S_TX_TEST_PATTERN_EN    3
+#define V_TX_TEST_PATTERN_EN(x) ((x) << S_TX_TEST_PATTERN_EN)
+#define F_TX_TEST_PATTERN_EN    V_TX_TEST_PATTERN_EN(1U)
+
+#define S_RX_TEST_PATTERN_EN    2
+#define V_RX_TEST_PATTERN_EN(x) ((x) << S_RX_TEST_PATTERN_EN)
+#define F_RX_TEST_PATTERN_EN    V_RX_TEST_PATTERN_EN(1U)
+
+#define S_TEST_PATTERN_SELECT    1
+#define V_TEST_PATTERN_SELECT(x) ((x) << S_TEST_PATTERN_SELECT)
+#define F_TEST_PATTERN_SELECT    V_TEST_PATTERN_SELECT(1U)
+
+#define S_DATA_PATTERN_SELECT    0
+#define V_DATA_PATTERN_SELECT(x) ((x) << S_DATA_PATTERN_SELECT)
+#define F_DATA_PATTERN_SELECT    V_DATA_PATTERN_SELECT(1U)
+
+#define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER 0x13ac
+
+#define S_TEST_PATTERN_ERR_CNTR    0
+#define M_TEST_PATTERN_ERR_CNTR    0xffffU
+#define V_TEST_PATTERN_ERR_CNTR(x) ((x) << S_TEST_PATTERN_ERR_CNTR)
+#define G_TEST_PATTERN_ERR_CNTR(x) (((x) >> S_TEST_PATTERN_ERR_CNTR) & M_TEST_PATTERN_ERR_CNTR)
+
+#define A_MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS 0x13b4
+
+#define S_TRANSMIT_FIFO_FAULT    1
+#define V_TRANSMIT_FIFO_FAULT(x) ((x) << S_TRANSMIT_FIFO_FAULT)
+#define F_TRANSMIT_FIFO_FAULT    V_TRANSMIT_FIFO_FAULT(1U)
+
+#define S_RECEIVE_FIFO_FAULT    0
+#define V_RECEIVE_FIFO_FAULT(x) ((x) << S_RECEIVE_FIFO_FAULT)
+#define F_RECEIVE_FIFO_FAULT    V_RECEIVE_FIFO_FAULT(1U)
+
+#define A_MAC_PORT_MTIP_KR4_CONTROL_1 0x1400
+
+#define S_SPEED_SELECTION    13
+#define V_SPEED_SELECTION(x) ((x) << S_SPEED_SELECTION)
+#define F_SPEED_SELECTION    V_SPEED_SELECTION(1U)
+
+#define S_SPEED_SELECTION1    6
+#define V_SPEED_SELECTION1(x) ((x) << S_SPEED_SELECTION1)
+#define F_SPEED_SELECTION1    V_SPEED_SELECTION1(1U)
+
+#define S_SPEED_SELECTION2    2
+#define M_SPEED_SELECTION2    0xfU
+#define V_SPEED_SELECTION2(x) ((x) << S_SPEED_SELECTION2)
+#define G_SPEED_SELECTION2(x) (((x) >> S_SPEED_SELECTION2) & M_SPEED_SELECTION2)
+
+#define A_MAC_PORT_MTIP_KR4_STATUS_1 0x1404
+
+#define S_RECEIVE_LINK_STAT    2
+#define V_RECEIVE_LINK_STAT(x) ((x) << S_RECEIVE_LINK_STAT)
+#define F_RECEIVE_LINK_STAT    V_RECEIVE_LINK_STAT(1U)
+
+#define A_MAC_PORT_MTIP_KR4_DEVICE_ID0 0x1408
+#define A_MAC_PORT_MTIP_KR4_DEVICE_ID1 0x140c
+
+#define S_T6_DEVICE_ID1    16
+#define M_T6_DEVICE_ID1    0xffffU
+#define V_T6_DEVICE_ID1(x) ((x) << S_T6_DEVICE_ID1)
+#define G_T6_DEVICE_ID1(x) (((x) >> S_T6_DEVICE_ID1) & M_T6_DEVICE_ID1)
+
+#define A_MAC_PORT_MTIP_KR4_SPEED_ABILITY 0x1410
+
+#define S_100G_CAPABLE    3
+#define V_100G_CAPABLE(x) ((x) << S_100G_CAPABLE)
+#define F_100G_CAPABLE    V_100G_CAPABLE(1U)
+
+#define S_40G_CAPABLE    2
+#define V_40G_CAPABLE(x) ((x) << S_40G_CAPABLE)
+#define F_40G_CAPABLE    V_40G_CAPABLE(1U)
+
+#define S_10PASS_TS_2BASE_TL_CAPABLE    1
+#define V_10PASS_TS_2BASE_TL_CAPABLE(x) ((x) << S_10PASS_TS_2BASE_TL_CAPABLE)
+#define F_10PASS_TS_2BASE_TL_CAPABLE    V_10PASS_TS_2BASE_TL_CAPABLE(1U)
+
+#define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1 0x1414
+
+#define S_CLAUSE_22_REG    0
+#define V_CLAUSE_22_REG(x) ((x) << S_CLAUSE_22_REG)
+#define F_CLAUSE_22_REG    V_CLAUSE_22_REG(1U)
+
+#define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2 0x1418
+
+#define S_VENDOR_SPECIFIC_DEVICE    15
+#define V_VENDOR_SPECIFIC_DEVICE(x) ((x) << S_VENDOR_SPECIFIC_DEVICE)
+#define F_VENDOR_SPECIFIC_DEVICE    V_VENDOR_SPECIFIC_DEVICE(1U)
+
+#define S_VENDOR_SPECIFIC_DEVICE1    14
+#define V_VENDOR_SPECIFIC_DEVICE1(x) ((x) << S_VENDOR_SPECIFIC_DEVICE1)
+#define F_VENDOR_SPECIFIC_DEVICE1    V_VENDOR_SPECIFIC_DEVICE1(1U)
+
+#define S_CLAUSE_22_EXT    13
+#define V_CLAUSE_22_EXT(x) ((x) << S_CLAUSE_22_EXT)
+#define F_CLAUSE_22_EXT    V_CLAUSE_22_EXT(1U)
+
+#define A_MAC_PORT_MTIP_KR4_CONTROL_2 0x141c
+
+#define S_PCS_TYPE_SEL    0
+#define M_PCS_TYPE_SEL    0x7U
+#define V_PCS_TYPE_SEL(x) ((x) << S_PCS_TYPE_SEL)
+#define G_PCS_TYPE_SEL(x) (((x) >> S_PCS_TYPE_SEL) & M_PCS_TYPE_SEL)
+
+#define A_MAC_PORT_MTIP_KR4_STATUS_2 0x1420
+
+#define S_100GBASE_R_CAPABLE    5
+#define V_100GBASE_R_CAPABLE(x) ((x) << S_100GBASE_R_CAPABLE)
+#define F_100GBASE_R_CAPABLE    V_100GBASE_R_CAPABLE(1U)
+
+#define S_40GBASE_R_CAPABLE    4
+#define V_40GBASE_R_CAPABLE(x) ((x) << S_40GBASE_R_CAPABLE)
+#define F_40GBASE_R_CAPABLE    V_40GBASE_R_CAPABLE(1U)
+
+#define S_10GBASE_T_CAPABLE    3
+#define V_10GBASE_T_CAPABLE(x) ((x) << S_10GBASE_T_CAPABLE)
+#define F_10GBASE_T_CAPABLE    V_10GBASE_T_CAPABLE(1U)
+
+#define A_MAC_PORT_MTIP_KR4_PKG_ID0 0x1438
+#define A_MAC_PORT_MTIP_KR4_PKG_ID1 0x143c
+#define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_1 0x1480
+
+#define S_T6_RX_LINK_STATUS    12
+#define V_T6_RX_LINK_STATUS(x) ((x) << S_T6_RX_LINK_STATUS)
+#define F_T6_RX_LINK_STATUS    V_T6_RX_LINK_STATUS(1U)
+
+#define S_HIGH_BER    1
+#define V_HIGH_BER(x) ((x) << S_HIGH_BER)
+#define F_HIGH_BER    V_HIGH_BER(1U)
+
+#define S_KR4_BLOCK_LOCK    0
+#define V_KR4_BLOCK_LOCK(x) ((x) << S_KR4_BLOCK_LOCK)
+#define F_KR4_BLOCK_LOCK    V_KR4_BLOCK_LOCK(1U)
+
+#define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_2 0x1484
+
+#define S_LATCHED_BL_LK    15
+#define V_LATCHED_BL_LK(x) ((x) << S_LATCHED_BL_LK)
+#define F_LATCHED_BL_LK    V_LATCHED_BL_LK(1U)
+
+#define S_LATCHED_HG_BR    14
+#define V_LATCHED_HG_BR(x) ((x) << S_LATCHED_HG_BR)
+#define F_LATCHED_HG_BR    V_LATCHED_HG_BR(1U)
+
+#define S_BER_CNT    8
+#define M_BER_CNT    0x3fU
+#define V_BER_CNT(x) ((x) << S_BER_CNT)
+#define G_BER_CNT(x) (((x) >> S_BER_CNT) & M_BER_CNT)
+
+#define S_ERR_BL_CNT    0
+#define M_ERR_BL_CNT    0xffU
+#define V_ERR_BL_CNT(x) ((x) << S_ERR_BL_CNT)
+#define G_ERR_BL_CNT(x) (((x) >> S_ERR_BL_CNT) & M_ERR_BL_CNT)
+
+#define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL 0x14a8
+
+#define S_TX_TP_EN    3
+#define V_TX_TP_EN(x) ((x) << S_TX_TP_EN)
+#define F_TX_TP_EN    V_TX_TP_EN(1U)
+
+#define S_RX_TP_EN    2
+#define V_RX_TP_EN(x) ((x) << S_RX_TP_EN)
+#define F_RX_TP_EN    V_RX_TP_EN(1U)
+
+#define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT 0x14ac
+
+#define S_TP_ERR_CNTR    0
+#define M_TP_ERR_CNTR    0xffffU
+#define V_TP_ERR_CNTR(x) ((x) << S_TP_ERR_CNTR)
+#define G_TP_ERR_CNTR(x) (((x) >> S_TP_ERR_CNTR) & M_TP_ERR_CNTR)
+
+#define A_MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT 0x14b0
+
+#define S_BER_HI_ORDER_CNT    0
+#define M_BER_HI_ORDER_CNT    0xffffU
+#define V_BER_HI_ORDER_CNT(x) ((x) << S_BER_HI_ORDER_CNT)
+#define G_BER_HI_ORDER_CNT(x) (((x) >> S_BER_HI_ORDER_CNT) & M_BER_HI_ORDER_CNT)
+
+#define A_MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT 0x14b4
+
+#define S_HI_ORDER_CNT_EN    15
+#define V_HI_ORDER_CNT_EN(x) ((x) << S_HI_ORDER_CNT_EN)
+#define F_HI_ORDER_CNT_EN    V_HI_ORDER_CNT_EN(1U)
+
+#define S_ERR_BLK_CNTR    0
+#define M_ERR_BLK_CNTR    0x3fffU
+#define V_ERR_BLK_CNTR(x) ((x) << S_ERR_BLK_CNTR)
+#define G_ERR_BLK_CNTR(x) (((x) >> S_ERR_BLK_CNTR) & M_ERR_BLK_CNTR)
+
+#define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1 0x14c8
+
+#define S_LANE_ALIGN_STATUS    12
+#define V_LANE_ALIGN_STATUS(x) ((x) << S_LANE_ALIGN_STATUS)
+#define F_LANE_ALIGN_STATUS    V_LANE_ALIGN_STATUS(1U)
+
+#define S_LANE_3_BLK_LCK    3
+#define V_LANE_3_BLK_LCK(x) ((x) << S_LANE_3_BLK_LCK)
+#define F_LANE_3_BLK_LCK    V_LANE_3_BLK_LCK(1U)
+
+#define S_LANE_2_BLK_LC32_6431K    2
+#define V_LANE_2_BLK_LC32_6431K(x) ((x) << S_LANE_2_BLK_LC32_6431K)
+#define F_LANE_2_BLK_LC32_6431K    V_LANE_2_BLK_LC32_6431K(1U)
+
+#define S_LANE_1_BLK_LCK    1
+#define V_LANE_1_BLK_LCK(x) ((x) << S_LANE_1_BLK_LCK)
+#define F_LANE_1_BLK_LCK    V_LANE_1_BLK_LCK(1U)
+
+#define S_LANE_0_BLK_LCK    0
+#define V_LANE_0_BLK_LCK(x) ((x) << S_LANE_0_BLK_LCK)
+#define F_LANE_0_BLK_LCK    V_LANE_0_BLK_LCK(1U)
+
+#define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2 0x14cc
+#define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3 0x14d0
+
+#define S_LANE_3_ALIGN_MRKR_LCK    3
+#define V_LANE_3_ALIGN_MRKR_LCK(x) ((x) << S_LANE_3_ALIGN_MRKR_LCK)
+#define F_LANE_3_ALIGN_MRKR_LCK    V_LANE_3_ALIGN_MRKR_LCK(1U)
+
+#define S_LANE_2_ALIGN_MRKR_LCK    2
+#define V_LANE_2_ALIGN_MRKR_LCK(x) ((x) << S_LANE_2_ALIGN_MRKR_LCK)
+#define F_LANE_2_ALIGN_MRKR_LCK    V_LANE_2_ALIGN_MRKR_LCK(1U)
+
+#define S_LANE_1_ALIGN_MRKR_LCK    1
+#define V_LANE_1_ALIGN_MRKR_LCK(x) ((x) << S_LANE_1_ALIGN_MRKR_LCK)
+#define F_LANE_1_ALIGN_MRKR_LCK    V_LANE_1_ALIGN_MRKR_LCK(1U)
+
+#define S_LANE_0_ALIGN_MRKR_LCK    0
+#define V_LANE_0_ALIGN_MRKR_LCK(x) ((x) << S_LANE_0_ALIGN_MRKR_LCK)
+#define F_LANE_0_ALIGN_MRKR_LCK    V_LANE_0_ALIGN_MRKR_LCK(1U)
+
+#define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4 0x14d4
 #define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600
 
 #define S_CLK_DIV    7
@@ -35177,6 +48950,34 @@
 #define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR)
 #define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR)
 
+#define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0 0x1720
+
+#define S_BIP_ERR_CNT_LANE_0    0
+#define M_BIP_ERR_CNT_LANE_0    0xffffU
+#define V_BIP_ERR_CNT_LANE_0(x) ((x) << S_BIP_ERR_CNT_LANE_0)
+#define G_BIP_ERR_CNT_LANE_0(x) (((x) >> S_BIP_ERR_CNT_LANE_0) & M_BIP_ERR_CNT_LANE_0)
+
+#define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1 0x1724
+
+#define S_BIP_ERR_CNT_LANE_1    0
+#define M_BIP_ERR_CNT_LANE_1    0xffffU
+#define V_BIP_ERR_CNT_LANE_1(x) ((x) << S_BIP_ERR_CNT_LANE_1)
+#define G_BIP_ERR_CNT_LANE_1(x) (((x) >> S_BIP_ERR_CNT_LANE_1) & M_BIP_ERR_CNT_LANE_1)
+
+#define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2 0x1728
+
+#define S_BIP_ERR_CNT_LANE_2    0
+#define M_BIP_ERR_CNT_LANE_2    0xffffU
+#define V_BIP_ERR_CNT_LANE_2(x) ((x) << S_BIP_ERR_CNT_LANE_2)
+#define G_BIP_ERR_CNT_LANE_2(x) (((x) >> S_BIP_ERR_CNT_LANE_2) & M_BIP_ERR_CNT_LANE_2)
+
+#define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3 0x172c
+
+#define S_BIP_ERR_CNT_LANE_3    0
+#define M_BIP_ERR_CNT_LANE_3    0xffffU
+#define V_BIP_ERR_CNT_LANE_3(x) ((x) << S_BIP_ERR_CNT_LANE_3)
+#define G_BIP_ERR_CNT_LANE_3(x) (((x) >> S_BIP_ERR_CNT_LANE_3) & M_BIP_ERR_CNT_LANE_3)
+
 #define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
 
 #define S_VLANTAG    0
@@ -35191,6 +48992,329 @@
 #define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14
 #define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18
 #define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c
+#define A_MAC_PORT_MTIP_KR4_LANE_0_MAPPING 0x1a40
+
+#define S_KR4_LANE_0_MAPPING    0
+#define M_KR4_LANE_0_MAPPING    0x3U
+#define V_KR4_LANE_0_MAPPING(x) ((x) << S_KR4_LANE_0_MAPPING)
+#define G_KR4_LANE_0_MAPPING(x) (((x) >> S_KR4_LANE_0_MAPPING) & M_KR4_LANE_0_MAPPING)
+
+#define A_MAC_PORT_MTIP_KR4_LANE_1_MAPPING 0x1a44
+
+#define S_KR4_LANE_1_MAPPING    0
+#define M_KR4_LANE_1_MAPPING    0x3U
+#define V_KR4_LANE_1_MAPPING(x) ((x) << S_KR4_LANE_1_MAPPING)
+#define G_KR4_LANE_1_MAPPING(x) (((x) >> S_KR4_LANE_1_MAPPING) & M_KR4_LANE_1_MAPPING)
+
+#define A_MAC_PORT_MTIP_KR4_LANE_2_MAPPING 0x1a48
+
+#define S_KR4_LANE_2_MAPPING    0
+#define M_KR4_LANE_2_MAPPING    0x3U
+#define V_KR4_LANE_2_MAPPING(x) ((x) << S_KR4_LANE_2_MAPPING)
+#define G_KR4_LANE_2_MAPPING(x) (((x) >> S_KR4_LANE_2_MAPPING) & M_KR4_LANE_2_MAPPING)
+
+#define A_MAC_PORT_MTIP_KR4_LANE_3_MAPPING 0x1a4c
+
+#define S_KR4_LANE_3_MAPPING    0
+#define M_KR4_LANE_3_MAPPING    0x3U
+#define V_KR4_LANE_3_MAPPING(x) ((x) << S_KR4_LANE_3_MAPPING)
+#define G_KR4_LANE_3_MAPPING(x) (((x) >> S_KR4_LANE_3_MAPPING) & M_KR4_LANE_3_MAPPING)
+
+#define A_MAC_PORT_MTIP_KR4_SCRATCH 0x1af0
+#define A_MAC_PORT_MTIP_KR4_CORE_REVISION 0x1af4
+#define A_MAC_PORT_MTIP_KR4_VL_INTVL 0x1af8
+
+#define S_SHRT_MRKR_CNFG    0
+#define V_SHRT_MRKR_CNFG(x) ((x) << S_SHRT_MRKR_CNFG)
+#define F_SHRT_MRKR_CNFG    V_SHRT_MRKR_CNFG(1U)
+
+#define A_MAC_PORT_MTIP_KR4_TX_LANE_THRESH 0x1afc
+#define A_MAC_PORT_MTIP_CR4_CONTROL_1 0x1b00
+#define A_MAC_PORT_MTIP_CR4_STATUS_1 0x1b04
+
+#define S_CR4_RX_LINK_STATUS    2
+#define V_CR4_RX_LINK_STATUS(x) ((x) << S_CR4_RX_LINK_STATUS)
+#define F_CR4_RX_LINK_STATUS    V_CR4_RX_LINK_STATUS(1U)
+
+#define A_MAC_PORT_MTIP_CR4_DEVICE_ID0 0x1b08
+
+#define S_CR4_DEVICE_ID0    0
+#define M_CR4_DEVICE_ID0    0xffffU
+#define V_CR4_DEVICE_ID0(x) ((x) << S_CR4_DEVICE_ID0)
+#define G_CR4_DEVICE_ID0(x) (((x) >> S_CR4_DEVICE_ID0) & M_CR4_DEVICE_ID0)
+
+#define A_MAC_PORT_MTIP_CR4_DEVICE_ID1 0x1b0c
+
+#define S_CR4_DEVICE_ID1    0
+#define M_CR4_DEVICE_ID1    0xffffU
+#define V_CR4_DEVICE_ID1(x) ((x) << S_CR4_DEVICE_ID1)
+#define G_CR4_DEVICE_ID1(x) (((x) >> S_CR4_DEVICE_ID1) & M_CR4_DEVICE_ID1)
+
+#define A_MAC_PORT_MTIP_CR4_SPEED_ABILITY 0x1b10
+
+#define S_CR4_100G_CAPABLE    8
+#define V_CR4_100G_CAPABLE(x) ((x) << S_CR4_100G_CAPABLE)
+#define F_CR4_100G_CAPABLE    V_CR4_100G_CAPABLE(1U)
+
+#define S_CR4_40G_CAPABLE    7
+#define V_CR4_40G_CAPABLE(x) ((x) << S_CR4_40G_CAPABLE)
+#define F_CR4_40G_CAPABLE    V_CR4_40G_CAPABLE(1U)
+
+#define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1 0x1b14
+
+#define S_CLAUSE22REG_PRESENT    0
+#define V_CLAUSE22REG_PRESENT(x) ((x) << S_CLAUSE22REG_PRESENT)
+#define F_CLAUSE22REG_PRESENT    V_CLAUSE22REG_PRESENT(1U)
+
+#define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2 0x1b18
+
+#define S_VSD_2_PRESENT    15
+#define V_VSD_2_PRESENT(x) ((x) << S_VSD_2_PRESENT)
+#define F_VSD_2_PRESENT    V_VSD_2_PRESENT(1U)
+
+#define S_VSD_1_PRESENT    14
+#define V_VSD_1_PRESENT(x) ((x) << S_VSD_1_PRESENT)
+#define F_VSD_1_PRESENT    V_VSD_1_PRESENT(1U)
+
+#define S_CLAUSE22_EXT_PRESENT    13
+#define V_CLAUSE22_EXT_PRESENT(x) ((x) << S_CLAUSE22_EXT_PRESENT)
+#define F_CLAUSE22_EXT_PRESENT    V_CLAUSE22_EXT_PRESENT(1U)
+
+#define A_MAC_PORT_MTIP_CR4_CONTROL_2 0x1b1c
+
+#define S_CR4_PCS_TYPE_SELECTION    0
+#define M_CR4_PCS_TYPE_SELECTION    0x7U
+#define V_CR4_PCS_TYPE_SELECTION(x) ((x) << S_CR4_PCS_TYPE_SELECTION)
+#define G_CR4_PCS_TYPE_SELECTION(x) (((x) >> S_CR4_PCS_TYPE_SELECTION) & M_CR4_PCS_TYPE_SELECTION)
+
+#define A_MAC_PORT_MTIP_CR4_STATUS_2 0x1b20
+#define A_MAC_PORT_MTIP_CR4_PKG_ID0 0x1b38
+#define A_MAC_PORT_MTIP_CR4_PKG_ID1 0x1b3c
+#define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_1 0x1b80
+
+#define S_RX_LINK_STAT    12
+#define V_RX_LINK_STAT(x) ((x) << S_RX_LINK_STAT)
+#define F_RX_LINK_STAT    V_RX_LINK_STAT(1U)
+
+#define S_BR_BLOCK_LOCK    0
+#define V_BR_BLOCK_LOCK(x) ((x) << S_BR_BLOCK_LOCK)
+#define F_BR_BLOCK_LOCK    V_BR_BLOCK_LOCK(1U)
+
+#define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_2 0x1b84
+
+#define S_BER_COUNTER    8
+#define M_BER_COUNTER    0x3fU
+#define V_BER_COUNTER(x) ((x) << S_BER_COUNTER)
+#define G_BER_COUNTER(x) (((x) >> S_BER_COUNTER) & M_BER_COUNTER)
+
+#define S_ERRORED_BLOCKS_CNTR    0
+#define M_ERRORED_BLOCKS_CNTR    0xffU
+#define V_ERRORED_BLOCKS_CNTR(x) ((x) << S_ERRORED_BLOCKS_CNTR)
+#define G_ERRORED_BLOCKS_CNTR(x) (((x) >> S_ERRORED_BLOCKS_CNTR) & M_ERRORED_BLOCKS_CNTR)
+
+#define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL 0x1ba8
+
+#define S_SCRAMBLED_ID_TP_EN    7
+#define V_SCRAMBLED_ID_TP_EN(x) ((x) << S_SCRAMBLED_ID_TP_EN)
+#define F_SCRAMBLED_ID_TP_EN    V_SCRAMBLED_ID_TP_EN(1U)
+
+#define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT 0x1bac
+
+#define S_BASE_R_TEST_ERR_CNT    0
+#define M_BASE_R_TEST_ERR_CNT    0xffffU
+#define V_BASE_R_TEST_ERR_CNT(x) ((x) << S_BASE_R_TEST_ERR_CNT)
+#define G_BASE_R_TEST_ERR_CNT(x) (((x) >> S_BASE_R_TEST_ERR_CNT) & M_BASE_R_TEST_ERR_CNT)
+
+#define A_MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT 0x1bb0
+
+#define S_BER_HIGH_ORDER_CNT    0
+#define M_BER_HIGH_ORDER_CNT    0xffffU
+#define V_BER_HIGH_ORDER_CNT(x) ((x) << S_BER_HIGH_ORDER_CNT)
+#define G_BER_HIGH_ORDER_CNT(x) (((x) >> S_BER_HIGH_ORDER_CNT) & M_BER_HIGH_ORDER_CNT)
+
+#define A_MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT 0x1bb4
+
+#define S_HI_ORDER_CNT_PRESENT    15
+#define V_HI_ORDER_CNT_PRESENT(x) ((x) << S_HI_ORDER_CNT_PRESENT)
+#define F_HI_ORDER_CNT_PRESENT    V_HI_ORDER_CNT_PRESENT(1U)
+
+#define S_ERR_BLKS_CNTR    0
+#define M_ERR_BLKS_CNTR    0x3fffU
+#define V_ERR_BLKS_CNTR(x) ((x) << S_ERR_BLKS_CNTR)
+#define G_ERR_BLKS_CNTR(x) (((x) >> S_ERR_BLKS_CNTR) & M_ERR_BLKS_CNTR)
+
+#define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1 0x1bc8
+
+#define S_LANE_ALIGN_STAT    12
+#define V_LANE_ALIGN_STAT(x) ((x) << S_LANE_ALIGN_STAT)
+#define F_LANE_ALIGN_STAT    V_LANE_ALIGN_STAT(1U)
+
+#define S_LANE_7_BLCK_LCK    7
+#define V_LANE_7_BLCK_LCK(x) ((x) << S_LANE_7_BLCK_LCK)
+#define F_LANE_7_BLCK_LCK    V_LANE_7_BLCK_LCK(1U)
+
+#define S_LANE_6_BLCK_LCK    6
+#define V_LANE_6_BLCK_LCK(x) ((x) << S_LANE_6_BLCK_LCK)
+#define F_LANE_6_BLCK_LCK    V_LANE_6_BLCK_LCK(1U)
+
+#define S_LANE_5_BLCK_LCK    5
+#define V_LANE_5_BLCK_LCK(x) ((x) << S_LANE_5_BLCK_LCK)
+#define F_LANE_5_BLCK_LCK    V_LANE_5_BLCK_LCK(1U)
+
+#define S_LANE_4_BLCK_LCK    4
+#define V_LANE_4_BLCK_LCK(x) ((x) << S_LANE_4_BLCK_LCK)
+#define F_LANE_4_BLCK_LCK    V_LANE_4_BLCK_LCK(1U)
+
+#define S_LANE_3_BLCK_LCK    3
+#define V_LANE_3_BLCK_LCK(x) ((x) << S_LANE_3_BLCK_LCK)
+#define F_LANE_3_BLCK_LCK    V_LANE_3_BLCK_LCK(1U)
+
+#define S_LANE_2_BLCK_LCK    2
+#define V_LANE_2_BLCK_LCK(x) ((x) << S_LANE_2_BLCK_LCK)
+#define F_LANE_2_BLCK_LCK    V_LANE_2_BLCK_LCK(1U)
+
+#define S_LANE_1_BLCK_LCK    1
+#define V_LANE_1_BLCK_LCK(x) ((x) << S_LANE_1_BLCK_LCK)
+#define F_LANE_1_BLCK_LCK    V_LANE_1_BLCK_LCK(1U)
+
+#define S_LANE_0_BLCK_LCK    0
+#define V_LANE_0_BLCK_LCK(x) ((x) << S_LANE_0_BLCK_LCK)
+#define F_LANE_0_BLCK_LCK    V_LANE_0_BLCK_LCK(1U)
+
+#define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2 0x1bcc
+
+#define S_LANE_19_BLCK_LCK    11
+#define V_LANE_19_BLCK_LCK(x) ((x) << S_LANE_19_BLCK_LCK)
+#define F_LANE_19_BLCK_LCK    V_LANE_19_BLCK_LCK(1U)
+
+#define S_LANE_18_BLCK_LCK    10
+#define V_LANE_18_BLCK_LCK(x) ((x) << S_LANE_18_BLCK_LCK)
+#define F_LANE_18_BLCK_LCK    V_LANE_18_BLCK_LCK(1U)
+
+#define S_LANE_17_BLCK_LCK    9
+#define V_LANE_17_BLCK_LCK(x) ((x) << S_LANE_17_BLCK_LCK)
+#define F_LANE_17_BLCK_LCK    V_LANE_17_BLCK_LCK(1U)
+
+#define S_LANE_16_BLCK_LCK    8
+#define V_LANE_16_BLCK_LCK(x) ((x) << S_LANE_16_BLCK_LCK)
+#define F_LANE_16_BLCK_LCK    V_LANE_16_BLCK_LCK(1U)
+
+#define S_LANE_15_BLCK_LCK    7
+#define V_LANE_15_BLCK_LCK(x) ((x) << S_LANE_15_BLCK_LCK)
+#define F_LANE_15_BLCK_LCK    V_LANE_15_BLCK_LCK(1U)
+
+#define S_LANE_14_BLCK_LCK    6
+#define V_LANE_14_BLCK_LCK(x) ((x) << S_LANE_14_BLCK_LCK)
+#define F_LANE_14_BLCK_LCK    V_LANE_14_BLCK_LCK(1U)
+
+#define S_LANE_13_BLCK_LCK    5
+#define V_LANE_13_BLCK_LCK(x) ((x) << S_LANE_13_BLCK_LCK)
+#define F_LANE_13_BLCK_LCK    V_LANE_13_BLCK_LCK(1U)
+
+#define S_LANE_12_BLCK_LCK    4
+#define V_LANE_12_BLCK_LCK(x) ((x) << S_LANE_12_BLCK_LCK)
+#define F_LANE_12_BLCK_LCK    V_LANE_12_BLCK_LCK(1U)
+
+#define S_LANE_11_BLCK_LCK    3
+#define V_LANE_11_BLCK_LCK(x) ((x) << S_LANE_11_BLCK_LCK)
+#define F_LANE_11_BLCK_LCK    V_LANE_11_BLCK_LCK(1U)
+
+#define S_LANE_10_BLCK_LCK    2
+#define V_LANE_10_BLCK_LCK(x) ((x) << S_LANE_10_BLCK_LCK)
+#define F_LANE_10_BLCK_LCK    V_LANE_10_BLCK_LCK(1U)
+
+#define S_LANE_9_BLCK_LCK    1
+#define V_LANE_9_BLCK_LCK(x) ((x) << S_LANE_9_BLCK_LCK)
+#define F_LANE_9_BLCK_LCK    V_LANE_9_BLCK_LCK(1U)
+
+#define S_LANE_8_BLCK_LCK    0
+#define V_LANE_8_BLCK_LCK(x) ((x) << S_LANE_8_BLCK_LCK)
+#define F_LANE_8_BLCK_LCK    V_LANE_8_BLCK_LCK(1U)
+
+#define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3 0x1bd0
+
+#define S_LANE7_ALGN_MRKR_LCK    7
+#define V_LANE7_ALGN_MRKR_LCK(x) ((x) << S_LANE7_ALGN_MRKR_LCK)
+#define F_LANE7_ALGN_MRKR_LCK    V_LANE7_ALGN_MRKR_LCK(1U)
+
+#define S_LANE6_ALGN_MRKR_LCK    6
+#define V_LANE6_ALGN_MRKR_LCK(x) ((x) << S_LANE6_ALGN_MRKR_LCK)
+#define F_LANE6_ALGN_MRKR_LCK    V_LANE6_ALGN_MRKR_LCK(1U)
+
+#define S_LANE5_ALGN_MRKR_LCK    5
+#define V_LANE5_ALGN_MRKR_LCK(x) ((x) << S_LANE5_ALGN_MRKR_LCK)
+#define F_LANE5_ALGN_MRKR_LCK    V_LANE5_ALGN_MRKR_LCK(1U)
+
+#define S_LANE4_ALGN_MRKR_LCK    4
+#define V_LANE4_ALGN_MRKR_LCK(x) ((x) << S_LANE4_ALGN_MRKR_LCK)
+#define F_LANE4_ALGN_MRKR_LCK    V_LANE4_ALGN_MRKR_LCK(1U)
+
+#define S_LANE3_ALGN_MRKR_LCK    3
+#define V_LANE3_ALGN_MRKR_LCK(x) ((x) << S_LANE3_ALGN_MRKR_LCK)
+#define F_LANE3_ALGN_MRKR_LCK    V_LANE3_ALGN_MRKR_LCK(1U)
+
+#define S_LANE2_ALGN_MRKR_LCK    2
+#define V_LANE2_ALGN_MRKR_LCK(x) ((x) << S_LANE2_ALGN_MRKR_LCK)
+#define F_LANE2_ALGN_MRKR_LCK    V_LANE2_ALGN_MRKR_LCK(1U)
+
+#define S_LANE1_ALGN_MRKR_LCK    1
+#define V_LANE1_ALGN_MRKR_LCK(x) ((x) << S_LANE1_ALGN_MRKR_LCK)
+#define F_LANE1_ALGN_MRKR_LCK    V_LANE1_ALGN_MRKR_LCK(1U)
+
+#define S_LANE0_ALGN_MRKR_LCK    0
+#define V_LANE0_ALGN_MRKR_LCK(x) ((x) << S_LANE0_ALGN_MRKR_LCK)
+#define F_LANE0_ALGN_MRKR_LCK    V_LANE0_ALGN_MRKR_LCK(1U)
+
+#define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4 0x1bd4
+
+#define S_LANE19_ALGN_MRKR_LCK    11
+#define V_LANE19_ALGN_MRKR_LCK(x) ((x) << S_LANE19_ALGN_MRKR_LCK)
+#define F_LANE19_ALGN_MRKR_LCK    V_LANE19_ALGN_MRKR_LCK(1U)
+
+#define S_LANE18_ALGN_MRKR_LCK    10
+#define V_LANE18_ALGN_MRKR_LCK(x) ((x) << S_LANE18_ALGN_MRKR_LCK)
+#define F_LANE18_ALGN_MRKR_LCK    V_LANE18_ALGN_MRKR_LCK(1U)
+
+#define S_LANE17_ALGN_MRKR_LCK    9
+#define V_LANE17_ALGN_MRKR_LCK(x) ((x) << S_LANE17_ALGN_MRKR_LCK)
+#define F_LANE17_ALGN_MRKR_LCK    V_LANE17_ALGN_MRKR_LCK(1U)
+
+#define S_LANE16_ALGN_MRKR_LCK    8
+#define V_LANE16_ALGN_MRKR_LCK(x) ((x) << S_LANE16_ALGN_MRKR_LCK)
+#define F_LANE16_ALGN_MRKR_LCK    V_LANE16_ALGN_MRKR_LCK(1U)
+
+#define S_LANE15_ALGN_MRKR_LCK    7
+#define V_LANE15_ALGN_MRKR_LCK(x) ((x) << S_LANE15_ALGN_MRKR_LCK)
+#define F_LANE15_ALGN_MRKR_LCK    V_LANE15_ALGN_MRKR_LCK(1U)
+
+#define S_LANE14_ALGN_MRKR_LCK    6
+#define V_LANE14_ALGN_MRKR_LCK(x) ((x) << S_LANE14_ALGN_MRKR_LCK)
+#define F_LANE14_ALGN_MRKR_LCK    V_LANE14_ALGN_MRKR_LCK(1U)
+
+#define S_LANE13_ALGN_MRKR_LCK    5
+#define V_LANE13_ALGN_MRKR_LCK(x) ((x) << S_LANE13_ALGN_MRKR_LCK)
+#define F_LANE13_ALGN_MRKR_LCK    V_LANE13_ALGN_MRKR_LCK(1U)
+
+#define S_LANE12_ALGN_MRKR_LCK    4
+#define V_LANE12_ALGN_MRKR_LCK(x) ((x) << S_LANE12_ALGN_MRKR_LCK)
+#define F_LANE12_ALGN_MRKR_LCK    V_LANE12_ALGN_MRKR_LCK(1U)
+
+#define S_LANE11_ALGN_MRKR_LCK    3
+#define V_LANE11_ALGN_MRKR_LCK(x) ((x) << S_LANE11_ALGN_MRKR_LCK)
+#define F_LANE11_ALGN_MRKR_LCK    V_LANE11_ALGN_MRKR_LCK(1U)
+
+#define S_LANE10_ALGN_MRKR_LCK    2
+#define V_LANE10_ALGN_MRKR_LCK(x) ((x) << S_LANE10_ALGN_MRKR_LCK)
+#define F_LANE10_ALGN_MRKR_LCK    V_LANE10_ALGN_MRKR_LCK(1U)
+
+#define S_LANE9_ALGN_MRKR_LCK    1
+#define V_LANE9_ALGN_MRKR_LCK(x) ((x) << S_LANE9_ALGN_MRKR_LCK)
+#define F_LANE9_ALGN_MRKR_LCK    V_LANE9_ALGN_MRKR_LCK(1U)
+
+#define S_LANE8_ALGN_MRKR_LCK    0
+#define V_LANE8_ALGN_MRKR_LCK(x) ((x) << S_LANE8_ALGN_MRKR_LCK)
+#define F_LANE8_ALGN_MRKR_LCK    V_LANE8_ALGN_MRKR_LCK(1U)
+
 #define A_MAC_PORT_MTIP_PCS_CTL 0x1e00
 
 #define S_PCS_LPBK    14
@@ -35349,6 +49473,48 @@
 #define V_10GBASE_R(x) ((x) << S_10GBASE_R)
 #define F_10GBASE_R    V_10GBASE_R(1U)
 
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0 0x1e20
+
+#define S_BIP_ERR_CNTLANE_0    0
+#define M_BIP_ERR_CNTLANE_0    0xffffU
+#define V_BIP_ERR_CNTLANE_0(x) ((x) << S_BIP_ERR_CNTLANE_0)
+#define G_BIP_ERR_CNTLANE_0(x) (((x) >> S_BIP_ERR_CNTLANE_0) & M_BIP_ERR_CNTLANE_0)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1 0x1e24
+
+#define S_BIP_ERR_CNTLANE_1    0
+#define M_BIP_ERR_CNTLANE_1    0xffffU
+#define V_BIP_ERR_CNTLANE_1(x) ((x) << S_BIP_ERR_CNTLANE_1)
+#define G_BIP_ERR_CNTLANE_1(x) (((x) >> S_BIP_ERR_CNTLANE_1) & M_BIP_ERR_CNTLANE_1)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2 0x1e28
+
+#define S_BIP_ERR_CNTLANE_2    0
+#define M_BIP_ERR_CNTLANE_2    0xffffU
+#define V_BIP_ERR_CNTLANE_2(x) ((x) << S_BIP_ERR_CNTLANE_2)
+#define G_BIP_ERR_CNTLANE_2(x) (((x) >> S_BIP_ERR_CNTLANE_2) & M_BIP_ERR_CNTLANE_2)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3 0x1e2c
+
+#define S_BIP_ERR_CNTLANE_3    0
+#define M_BIP_ERR_CNTLANE_3    0xffffU
+#define V_BIP_ERR_CNTLANE_3(x) ((x) << S_BIP_ERR_CNTLANE_3)
+#define G_BIP_ERR_CNTLANE_3(x) (((x) >> S_BIP_ERR_CNTLANE_3) & M_BIP_ERR_CNTLANE_3)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4 0x1e30
+
+#define S_BIP_ERR_CNTLANE_4    0
+#define M_BIP_ERR_CNTLANE_4    0xffffU
+#define V_BIP_ERR_CNTLANE_4(x) ((x) << S_BIP_ERR_CNTLANE_4)
+#define G_BIP_ERR_CNTLANE_4(x) (((x) >> S_BIP_ERR_CNTLANE_4) & M_BIP_ERR_CNTLANE_4)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5 0x1e34
+
+#define S_BIP_ERR_CNTLANE_5    0
+#define M_BIP_ERR_CNTLANE_5    0xffffU
+#define V_BIP_ERR_CNTLANE_5(x) ((x) << S_BIP_ERR_CNTLANE_5)
+#define G_BIP_ERR_CNTLANE_5(x) (((x) >> S_BIP_ERR_CNTLANE_5) & M_BIP_ERR_CNTLANE_5)
+
 #define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38
 
 #define S_PKG_ID0    0
@@ -35356,6 +49522,13 @@
 #define V_PKG_ID0(x) ((x) << S_PKG_ID0)
 #define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0)
 
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6 0x1e38
+
+#define S_BIP_ERR_CNTLANE_6    0
+#define M_BIP_ERR_CNTLANE_6    0xffffU
+#define V_BIP_ERR_CNTLANE_6(x) ((x) << S_BIP_ERR_CNTLANE_6)
+#define G_BIP_ERR_CNTLANE_6(x) (((x) >> S_BIP_ERR_CNTLANE_6) & M_BIP_ERR_CNTLANE_6)
+
 #define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c
 
 #define S_PKG_ID1    0
@@ -35363,6 +49536,97 @@
 #define V_PKG_ID1(x) ((x) << S_PKG_ID1)
 #define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1)
 
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7 0x1e3c
+
+#define S_BIP_ERR_CNTLANE_7    0
+#define M_BIP_ERR_CNTLANE_7    0xffffU
+#define V_BIP_ERR_CNTLANE_7(x) ((x) << S_BIP_ERR_CNTLANE_7)
+#define G_BIP_ERR_CNTLANE_7(x) (((x) >> S_BIP_ERR_CNTLANE_7) & M_BIP_ERR_CNTLANE_7)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8 0x1e40
+
+#define S_BIP_ERR_CNTLANE_8    0
+#define M_BIP_ERR_CNTLANE_8    0xffffU
+#define V_BIP_ERR_CNTLANE_8(x) ((x) << S_BIP_ERR_CNTLANE_8)
+#define G_BIP_ERR_CNTLANE_8(x) (((x) >> S_BIP_ERR_CNTLANE_8) & M_BIP_ERR_CNTLANE_8)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9 0x1e44
+
+#define S_BIP_ERR_CNTLANE_9    0
+#define M_BIP_ERR_CNTLANE_9    0xffffU
+#define V_BIP_ERR_CNTLANE_9(x) ((x) << S_BIP_ERR_CNTLANE_9)
+#define G_BIP_ERR_CNTLANE_9(x) (((x) >> S_BIP_ERR_CNTLANE_9) & M_BIP_ERR_CNTLANE_9)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10 0x1e48
+
+#define S_BIP_ERR_CNTLANE_10    0
+#define M_BIP_ERR_CNTLANE_10    0xffffU
+#define V_BIP_ERR_CNTLANE_10(x) ((x) << S_BIP_ERR_CNTLANE_10)
+#define G_BIP_ERR_CNTLANE_10(x) (((x) >> S_BIP_ERR_CNTLANE_10) & M_BIP_ERR_CNTLANE_10)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11 0x1e4c
+
+#define S_BIP_ERR_CNTLANE_11    0
+#define M_BIP_ERR_CNTLANE_11    0xffffU
+#define V_BIP_ERR_CNTLANE_11(x) ((x) << S_BIP_ERR_CNTLANE_11)
+#define G_BIP_ERR_CNTLANE_11(x) (((x) >> S_BIP_ERR_CNTLANE_11) & M_BIP_ERR_CNTLANE_11)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12 0x1e50
+
+#define S_BIP_ERR_CNTLANE_12    0
+#define M_BIP_ERR_CNTLANE_12    0xffffU
+#define V_BIP_ERR_CNTLANE_12(x) ((x) << S_BIP_ERR_CNTLANE_12)
+#define G_BIP_ERR_CNTLANE_12(x) (((x) >> S_BIP_ERR_CNTLANE_12) & M_BIP_ERR_CNTLANE_12)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13 0x1e54
+
+#define S_BIP_ERR_CNTLANE_13    0
+#define M_BIP_ERR_CNTLANE_13    0xffffU
+#define V_BIP_ERR_CNTLANE_13(x) ((x) << S_BIP_ERR_CNTLANE_13)
+#define G_BIP_ERR_CNTLANE_13(x) (((x) >> S_BIP_ERR_CNTLANE_13) & M_BIP_ERR_CNTLANE_13)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14 0x1e58
+
+#define S_BIP_ERR_CNTLANE_14    0
+#define M_BIP_ERR_CNTLANE_14    0xffffU
+#define V_BIP_ERR_CNTLANE_14(x) ((x) << S_BIP_ERR_CNTLANE_14)
+#define G_BIP_ERR_CNTLANE_14(x) (((x) >> S_BIP_ERR_CNTLANE_14) & M_BIP_ERR_CNTLANE_14)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15 0x1e5c
+
+#define S_BIP_ERR_CNTLANE_15    0
+#define M_BIP_ERR_CNTLANE_15    0xffffU
+#define V_BIP_ERR_CNTLANE_15(x) ((x) << S_BIP_ERR_CNTLANE_15)
+#define G_BIP_ERR_CNTLANE_15(x) (((x) >> S_BIP_ERR_CNTLANE_15) & M_BIP_ERR_CNTLANE_15)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16 0x1e60
+
+#define S_BIP_ERR_CNTLANE_16    0
+#define M_BIP_ERR_CNTLANE_16    0xffffU
+#define V_BIP_ERR_CNTLANE_16(x) ((x) << S_BIP_ERR_CNTLANE_16)
+#define G_BIP_ERR_CNTLANE_16(x) (((x) >> S_BIP_ERR_CNTLANE_16) & M_BIP_ERR_CNTLANE_16)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17 0x1e64
+
+#define S_BIP_ERR_CNTLANE_17    0
+#define M_BIP_ERR_CNTLANE_17    0xffffU
+#define V_BIP_ERR_CNTLANE_17(x) ((x) << S_BIP_ERR_CNTLANE_17)
+#define G_BIP_ERR_CNTLANE_17(x) (((x) >> S_BIP_ERR_CNTLANE_17) & M_BIP_ERR_CNTLANE_17)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18 0x1e68
+
+#define S_BIP_ERR_CNTLANE_18    0
+#define M_BIP_ERR_CNTLANE_18    0xffffU
+#define V_BIP_ERR_CNTLANE_18(x) ((x) << S_BIP_ERR_CNTLANE_18)
+#define G_BIP_ERR_CNTLANE_18(x) (((x) >> S_BIP_ERR_CNTLANE_18) & M_BIP_ERR_CNTLANE_18)
+
+#define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19 0x1e6c
+
+#define S_BIP_ERR_CNTLANE_19    0
+#define M_BIP_ERR_CNTLANE_19    0xffffU
+#define V_BIP_ERR_CNTLANE_19(x) ((x) << S_BIP_ERR_CNTLANE_19)
+#define G_BIP_ERR_CNTLANE_19(x) (((x) >> S_BIP_ERR_CNTLANE_19) & M_BIP_ERR_CNTLANE_19)
+
 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80
 
 #define S_RXLINKSTATUS    12
@@ -35745,6 +50009,154 @@
 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc
 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000
 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004
+#define A_MAC_PORT_MTIP_CR4_LANE_0_MAPPING 0x2140
+
+#define S_LANE_0_MAPPING    0
+#define M_LANE_0_MAPPING    0x3fU
+#define V_LANE_0_MAPPING(x) ((x) << S_LANE_0_MAPPING)
+#define G_LANE_0_MAPPING(x) (((x) >> S_LANE_0_MAPPING) & M_LANE_0_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_1_MAPPING 0x2144
+
+#define S_LANE_1_MAPPING    0
+#define M_LANE_1_MAPPING    0x3fU
+#define V_LANE_1_MAPPING(x) ((x) << S_LANE_1_MAPPING)
+#define G_LANE_1_MAPPING(x) (((x) >> S_LANE_1_MAPPING) & M_LANE_1_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_2_MAPPING 0x2148
+
+#define S_LANE_2_MAPPING    0
+#define M_LANE_2_MAPPING    0x3fU
+#define V_LANE_2_MAPPING(x) ((x) << S_LANE_2_MAPPING)
+#define G_LANE_2_MAPPING(x) (((x) >> S_LANE_2_MAPPING) & M_LANE_2_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_3_MAPPING 0x214c
+
+#define S_LANE_3_MAPPING    0
+#define M_LANE_3_MAPPING    0x3fU
+#define V_LANE_3_MAPPING(x) ((x) << S_LANE_3_MAPPING)
+#define G_LANE_3_MAPPING(x) (((x) >> S_LANE_3_MAPPING) & M_LANE_3_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_4_MAPPING 0x2150
+
+#define S_LANE_4_MAPPING    0
+#define M_LANE_4_MAPPING    0x3fU
+#define V_LANE_4_MAPPING(x) ((x) << S_LANE_4_MAPPING)
+#define G_LANE_4_MAPPING(x) (((x) >> S_LANE_4_MAPPING) & M_LANE_4_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_5_MAPPING 0x2154
+
+#define S_LANE_5_MAPPING    0
+#define M_LANE_5_MAPPING    0x3fU
+#define V_LANE_5_MAPPING(x) ((x) << S_LANE_5_MAPPING)
+#define G_LANE_5_MAPPING(x) (((x) >> S_LANE_5_MAPPING) & M_LANE_5_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_6_MAPPING 0x2158
+
+#define S_LANE_6_MAPPING    0
+#define M_LANE_6_MAPPING    0x3fU
+#define V_LANE_6_MAPPING(x) ((x) << S_LANE_6_MAPPING)
+#define G_LANE_6_MAPPING(x) (((x) >> S_LANE_6_MAPPING) & M_LANE_6_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_7_MAPPING 0x215c
+
+#define S_LANE_7_MAPPING    0
+#define M_LANE_7_MAPPING    0x3fU
+#define V_LANE_7_MAPPING(x) ((x) << S_LANE_7_MAPPING)
+#define G_LANE_7_MAPPING(x) (((x) >> S_LANE_7_MAPPING) & M_LANE_7_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_8_MAPPING 0x2160
+
+#define S_LANE_8_MAPPING    0
+#define M_LANE_8_MAPPING    0x3fU
+#define V_LANE_8_MAPPING(x) ((x) << S_LANE_8_MAPPING)
+#define G_LANE_8_MAPPING(x) (((x) >> S_LANE_8_MAPPING) & M_LANE_8_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_9_MAPPING 0x2164
+
+#define S_LANE_9_MAPPING    0
+#define M_LANE_9_MAPPING    0x3fU
+#define V_LANE_9_MAPPING(x) ((x) << S_LANE_9_MAPPING)
+#define G_LANE_9_MAPPING(x) (((x) >> S_LANE_9_MAPPING) & M_LANE_9_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_10_MAPPING 0x2168
+
+#define S_LANE_10_MAPPING    0
+#define M_LANE_10_MAPPING    0x3fU
+#define V_LANE_10_MAPPING(x) ((x) << S_LANE_10_MAPPING)
+#define G_LANE_10_MAPPING(x) (((x) >> S_LANE_10_MAPPING) & M_LANE_10_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_11_MAPPING 0x216c
+
+#define S_LANE_11_MAPPING    0
+#define M_LANE_11_MAPPING    0x3fU
+#define V_LANE_11_MAPPING(x) ((x) << S_LANE_11_MAPPING)
+#define G_LANE_11_MAPPING(x) (((x) >> S_LANE_11_MAPPING) & M_LANE_11_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_12_MAPPING 0x2170
+
+#define S_LANE_12_MAPPING    0
+#define M_LANE_12_MAPPING    0x3fU
+#define V_LANE_12_MAPPING(x) ((x) << S_LANE_12_MAPPING)
+#define G_LANE_12_MAPPING(x) (((x) >> S_LANE_12_MAPPING) & M_LANE_12_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_13_MAPPING 0x2174
+
+#define S_LANE_13_MAPPING    0
+#define M_LANE_13_MAPPING    0x3fU
+#define V_LANE_13_MAPPING(x) ((x) << S_LANE_13_MAPPING)
+#define G_LANE_13_MAPPING(x) (((x) >> S_LANE_13_MAPPING) & M_LANE_13_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_14_MAPPING 0x2178
+
+#define S_LANE_14_MAPPING    0
+#define M_LANE_14_MAPPING    0x3fU
+#define V_LANE_14_MAPPING(x) ((x) << S_LANE_14_MAPPING)
+#define G_LANE_14_MAPPING(x) (((x) >> S_LANE_14_MAPPING) & M_LANE_14_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_15_MAPPING 0x217c
+
+#define S_LANE_15_MAPPING    0
+#define M_LANE_15_MAPPING    0x3fU
+#define V_LANE_15_MAPPING(x) ((x) << S_LANE_15_MAPPING)
+#define G_LANE_15_MAPPING(x) (((x) >> S_LANE_15_MAPPING) & M_LANE_15_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_16_MAPPING 0x2180
+
+#define S_LANE_16_MAPPING    0
+#define M_LANE_16_MAPPING    0x3fU
+#define V_LANE_16_MAPPING(x) ((x) << S_LANE_16_MAPPING)
+#define G_LANE_16_MAPPING(x) (((x) >> S_LANE_16_MAPPING) & M_LANE_16_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_17_MAPPING 0x2184
+
+#define S_LANE_17_MAPPING    0
+#define M_LANE_17_MAPPING    0x3fU
+#define V_LANE_17_MAPPING(x) ((x) << S_LANE_17_MAPPING)
+#define G_LANE_17_MAPPING(x) (((x) >> S_LANE_17_MAPPING) & M_LANE_17_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_18_MAPPING 0x2188
+
+#define S_LANE_18_MAPPING    0
+#define M_LANE_18_MAPPING    0x3fU
+#define V_LANE_18_MAPPING(x) ((x) << S_LANE_18_MAPPING)
+#define G_LANE_18_MAPPING(x) (((x) >> S_LANE_18_MAPPING) & M_LANE_18_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_LANE_19_MAPPING 0x218c
+
+#define S_LANE_19_MAPPING    0
+#define M_LANE_19_MAPPING    0x3fU
+#define V_LANE_19_MAPPING(x) ((x) << S_LANE_19_MAPPING)
+#define G_LANE_19_MAPPING(x) (((x) >> S_LANE_19_MAPPING) & M_LANE_19_MAPPING)
+
+#define A_MAC_PORT_MTIP_CR4_SCRATCH 0x21f0
+#define A_MAC_PORT_MTIP_CR4_CORE_REVISION 0x21f4
+
+#define S_CORE_REVISION    0
+#define M_CORE_REVISION    0xffffU
+#define V_CORE_REVISION(x) ((x) << S_CORE_REVISION)
+#define G_CORE_REVISION(x) (((x) >> S_CORE_REVISION) & M_CORE_REVISION)
+
 #define A_MAC_PORT_BEAN_CTL 0x2200
 
 #define S_AN_RESET    15
@@ -35763,6 +50175,16 @@
 #define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN)
 #define F_RESTART_BEAN    V_RESTART_BEAN(1U)
 
+#define A_MAC_PORT_MTIP_RS_FEC_CONTROL 0x2200
+
+#define S_RS_FEC_BYPASS_ERROR_INDICATION    1
+#define V_RS_FEC_BYPASS_ERROR_INDICATION(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION)
+#define F_RS_FEC_BYPASS_ERROR_INDICATION    V_RS_FEC_BYPASS_ERROR_INDICATION(1U)
+
+#define S_RS_FEC_BYPASS_CORRECTION    0
+#define V_RS_FEC_BYPASS_CORRECTION(x) ((x) << S_RS_FEC_BYPASS_CORRECTION)
+#define F_RS_FEC_BYPASS_CORRECTION    V_RS_FEC_BYPASS_CORRECTION(1U)
+
 #define A_MAC_PORT_BEAN_STATUS 0x2204
 
 #define S_PDF    9
@@ -35793,6 +50215,28 @@
 #define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY)
 #define F_LP_BEAN_ABILITY    V_LP_BEAN_ABILITY(1U)
 
+#define A_MAC_PORT_MTIP_RS_FEC_STATUS 0x2204
+
+#define S_RS_FEC_PCS_ALIGN_STATUS    15
+#define V_RS_FEC_PCS_ALIGN_STATUS(x) ((x) << S_RS_FEC_PCS_ALIGN_STATUS)
+#define F_RS_FEC_PCS_ALIGN_STATUS    V_RS_FEC_PCS_ALIGN_STATUS(1U)
+
+#define S_FEC_ALIGN_STATUS    14
+#define V_FEC_ALIGN_STATUS(x) ((x) << S_FEC_ALIGN_STATUS)
+#define F_FEC_ALIGN_STATUS    V_FEC_ALIGN_STATUS(1U)
+
+#define S_RS_FEC_HIGH_SER    2
+#define V_RS_FEC_HIGH_SER(x) ((x) << S_RS_FEC_HIGH_SER)
+#define F_RS_FEC_HIGH_SER    V_RS_FEC_HIGH_SER(1U)
+
+#define S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY    1
+#define V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY)
+#define F_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY    V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(1U)
+
+#define S_RS_FEC_BYPASS_CORRECTION_ABILITY    0
+#define V_RS_FEC_BYPASS_CORRECTION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_CORRECTION_ABILITY)
+#define F_RS_FEC_BYPASS_CORRECTION_ABILITY    V_RS_FEC_BYPASS_CORRECTION_ABILITY(1U)
+
 #define A_MAC_PORT_BEAN_ABILITY_0 0x2208
 
 #define S_NXP    15
@@ -35818,6 +50262,13 @@
 #define V_SELECTOR(x) ((x) << S_SELECTOR)
 #define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR)
 
+#define A_MAC_PORT_MTIP_RS_FEC_CCW_LO 0x2208
+
+#define S_RS_RS_FEC_CCW_LO    0
+#define M_RS_RS_FEC_CCW_LO    0xffffU
+#define V_RS_RS_FEC_CCW_LO(x) ((x) << S_RS_RS_FEC_CCW_LO)
+#define G_RS_RS_FEC_CCW_LO(x) (((x) >> S_RS_RS_FEC_CCW_LO) & M_RS_RS_FEC_CCW_LO)
+
 #define A_MAC_PORT_BEAN_ABILITY_1 0x220c
 
 #define S_TECH_ABILITY_1    5
@@ -35830,6 +50281,13 @@
 #define V_TX_NONCE(x) ((x) << S_TX_NONCE)
 #define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE)
 
+#define A_MAC_PORT_MTIP_RS_FEC_CCW_HI 0x220c
+
+#define S_RS_RS_FEC_CCW_HI    0
+#define M_RS_RS_FEC_CCW_HI    0xffffU
+#define V_RS_RS_FEC_CCW_HI(x) ((x) << S_RS_RS_FEC_CCW_HI)
+#define G_RS_RS_FEC_CCW_HI(x) (((x) >> S_RS_RS_FEC_CCW_HI) & M_RS_RS_FEC_CCW_HI)
+
 #define A_MAC_PORT_BEAN_ABILITY_2 0x2210
 
 #define S_T5_FEC_ABILITY    14
@@ -35842,8 +50300,29 @@
 #define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2)
 #define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2)
 
+#define A_MAC_PORT_MTIP_RS_FEC_NCCW_LO 0x2210
+
+#define S_RS_RS_FEC_NCCW_LO    0
+#define M_RS_RS_FEC_NCCW_LO    0xffffU
+#define V_RS_RS_FEC_NCCW_LO(x) ((x) << S_RS_RS_FEC_NCCW_LO)
+#define G_RS_RS_FEC_NCCW_LO(x) (((x) >> S_RS_RS_FEC_NCCW_LO) & M_RS_RS_FEC_NCCW_LO)
+
 #define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214
+#define A_MAC_PORT_MTIP_RS_FEC_NCCW_HI 0x2214
+
+#define S_RS_RS_FEC_NCCW_HI    0
+#define M_RS_RS_FEC_NCCW_HI    0xffffU
+#define V_RS_RS_FEC_NCCW_HI(x) ((x) << S_RS_RS_FEC_NCCW_HI)
+#define G_RS_RS_FEC_NCCW_HI(x) (((x) >> S_RS_RS_FEC_NCCW_HI) & M_RS_RS_FEC_NCCW_HI)
+
 #define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218
+#define A_MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI 0x2218
+
+#define S_PMA_MAPPING    0
+#define M_PMA_MAPPING    0xffU
+#define V_PMA_MAPPING(x) ((x) << S_PMA_MAPPING)
+#define G_PMA_MAPPING(x) (((x) >> S_PMA_MAPPING) & M_PMA_MAPPING)
+
 #define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c
 #define A_MAC_PORT_BEAN_MS_COUNT 0x2220
 
@@ -35882,10 +50361,40 @@
 #define V_UNFORMATED(x) ((x) << S_UNFORMATED)
 #define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED)
 
+#define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO 0x2228
+
+#define S_RS_FEC_SYMBLERR0_LO    0
+#define V_RS_FEC_SYMBLERR0_LO(x) ((x) << S_RS_FEC_SYMBLERR0_LO)
+#define F_RS_FEC_SYMBLERR0_LO    V_RS_FEC_SYMBLERR0_LO(1U)
+
 #define A_MAC_PORT_BEAN_XNP_2 0x222c
+#define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI 0x222c
+
+#define S_RS_FEC_SYMBLERR0_HI    0
+#define V_RS_FEC_SYMBLERR0_HI(x) ((x) << S_RS_FEC_SYMBLERR0_HI)
+#define F_RS_FEC_SYMBLERR0_HI    V_RS_FEC_SYMBLERR0_HI(1U)
+
 #define A_MAC_PORT_LP_BEAN_XNP_0 0x2230
+#define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO 0x2230
+
+#define S_RS_FEC_SYMBLERR1_LO    0
+#define V_RS_FEC_SYMBLERR1_LO(x) ((x) << S_RS_FEC_SYMBLERR1_LO)
+#define F_RS_FEC_SYMBLERR1_LO    V_RS_FEC_SYMBLERR1_LO(1U)
+
 #define A_MAC_PORT_LP_BEAN_XNP_1 0x2234
+#define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI 0x2234
+
+#define S_RS_FEC_SYMBLERR1_HI    0
+#define V_RS_FEC_SYMBLERR1_HI(x) ((x) << S_RS_FEC_SYMBLERR1_HI)
+#define F_RS_FEC_SYMBLERR1_HI    V_RS_FEC_SYMBLERR1_HI(1U)
+
 #define A_MAC_PORT_LP_BEAN_XNP_2 0x2238
+#define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO 0x2238
+
+#define S_RS_FEC_SYMBLERR2_LO    0
+#define V_RS_FEC_SYMBLERR2_LO(x) ((x) << S_RS_FEC_SYMBLERR2_LO)
+#define F_RS_FEC_SYMBLERR2_LO    V_RS_FEC_SYMBLERR2_LO(1U)
+
 #define A_MAC_PORT_BEAN_ETH_STATUS 0x223c
 
 #define S_100GCR10    8
@@ -35916,8 +50425,26 @@
 #define V_1GKX(x) ((x) << S_1GKX)
 #define F_1GKX    V_1GKX(1U)
 
+#define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI 0x223c
+
+#define S_RS_FEC_SYMBLERR2_HI    0
+#define V_RS_FEC_SYMBLERR2_HI(x) ((x) << S_RS_FEC_SYMBLERR2_HI)
+#define F_RS_FEC_SYMBLERR2_HI    V_RS_FEC_SYMBLERR2_HI(1U)
+
 #define A_MAC_PORT_BEAN_CTL_LANE1 0x2240
+#define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO 0x2240
+
+#define S_RS_FEC_SYMBLERR3_LO    0
+#define V_RS_FEC_SYMBLERR3_LO(x) ((x) << S_RS_FEC_SYMBLERR3_LO)
+#define F_RS_FEC_SYMBLERR3_LO    V_RS_FEC_SYMBLERR3_LO(1U)
+
 #define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244
+#define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI 0x2244
+
+#define S_RS_FEC_SYMBLERR3_HI    0
+#define V_RS_FEC_SYMBLERR3_HI(x) ((x) << S_RS_FEC_SYMBLERR3_HI)
+#define F_RS_FEC_SYMBLERR3_HI    V_RS_FEC_SYMBLERR3_HI(1U)
+
 #define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248
 #define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c
 #define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250
@@ -35964,6 +50491,92 @@
 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4
 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8
 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc
+#define A_MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL 0x2400
+
+#define S_RS_FEC_ENABLED_STATUS    15
+#define V_RS_FEC_ENABLED_STATUS(x) ((x) << S_RS_FEC_ENABLED_STATUS)
+#define F_RS_FEC_ENABLED_STATUS    V_RS_FEC_ENABLED_STATUS(1U)
+
+#define S_RS_FEC_ENABLE    2
+#define V_RS_FEC_ENABLE(x) ((x) << S_RS_FEC_ENABLE)
+#define F_RS_FEC_ENABLE    V_RS_FEC_ENABLE(1U)
+
+#define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1 0x2404
+
+#define S_DESKEW_EMPTY    12
+#define M_DESKEW_EMPTY    0xfU
+#define V_DESKEW_EMPTY(x) ((x) << S_DESKEW_EMPTY)
+#define G_DESKEW_EMPTY(x) (((x) >> S_DESKEW_EMPTY) & M_DESKEW_EMPTY)
+
+#define S_FEC_ALIGN_STATUS_LH    10
+#define V_FEC_ALIGN_STATUS_LH(x) ((x) << S_FEC_ALIGN_STATUS_LH)
+#define F_FEC_ALIGN_STATUS_LH    V_FEC_ALIGN_STATUS_LH(1U)
+
+#define S_TX_DP_OVERFLOW    9
+#define V_TX_DP_OVERFLOW(x) ((x) << S_TX_DP_OVERFLOW)
+#define F_TX_DP_OVERFLOW    V_TX_DP_OVERFLOW(1U)
+
+#define S_RX_DP_OVERFLOW    8
+#define V_RX_DP_OVERFLOW(x) ((x) << S_RX_DP_OVERFLOW)
+#define F_RX_DP_OVERFLOW    V_RX_DP_OVERFLOW(1U)
+
+#define S_TX_DATAPATH_RESTART    7
+#define V_TX_DATAPATH_RESTART(x) ((x) << S_TX_DATAPATH_RESTART)
+#define F_TX_DATAPATH_RESTART    V_TX_DATAPATH_RESTART(1U)
+
+#define S_RX_DATAPATH_RESTART    6
+#define V_RX_DATAPATH_RESTART(x) ((x) << S_RX_DATAPATH_RESTART)
+#define F_RX_DATAPATH_RESTART    V_RX_DATAPATH_RESTART(1U)
+
+#define S_MARKER_CHECK_RESTART    5
+#define V_MARKER_CHECK_RESTART(x) ((x) << S_MARKER_CHECK_RESTART)
+#define F_MARKER_CHECK_RESTART    V_MARKER_CHECK_RESTART(1U)
+
+#define S_FEC_ALIGN_STATUS_LL    4
+#define V_FEC_ALIGN_STATUS_LL(x) ((x) << S_FEC_ALIGN_STATUS_LL)
+#define F_FEC_ALIGN_STATUS_LL    V_FEC_ALIGN_STATUS_LL(1U)
+
+#define S_AMPS_LOCK    0
+#define M_AMPS_LOCK    0xfU
+#define V_AMPS_LOCK(x) ((x) << S_AMPS_LOCK)
+#define G_AMPS_LOCK(x) (((x) >> S_AMPS_LOCK) & M_AMPS_LOCK)
+
+#define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2 0x2408
+#define A_MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION 0x240c
+
+#define S_RS_FEC_VENDOR_REVISION    0
+#define M_RS_FEC_VENDOR_REVISION    0xffffU
+#define V_RS_FEC_VENDOR_REVISION(x) ((x) << S_RS_FEC_VENDOR_REVISION)
+#define G_RS_FEC_VENDOR_REVISION(x) (((x) >> S_RS_FEC_VENDOR_REVISION) & M_RS_FEC_VENDOR_REVISION)
+
+#define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY 0x2410
+
+#define S_RS_FEC_VENDOR_TX_TEST_KEY    0
+#define M_RS_FEC_VENDOR_TX_TEST_KEY    0xffffU
+#define V_RS_FEC_VENDOR_TX_TEST_KEY(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_KEY)
+#define G_RS_FEC_VENDOR_TX_TEST_KEY(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_KEY) & M_RS_FEC_VENDOR_TX_TEST_KEY)
+
+#define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS 0x2414
+
+#define S_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0
+#define M_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0xffffU
+#define V_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
+#define G_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_SYMBOLS) & M_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
+
+#define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN 0x2418
+
+#define S_RS_FEC_VENDOR_TX_TEST_PATTERN    0
+#define M_RS_FEC_VENDOR_TX_TEST_PATTERN    0xffffU
+#define V_RS_FEC_VENDOR_TX_TEST_PATTERN(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_PATTERN)
+#define G_RS_FEC_VENDOR_TX_TEST_PATTERN(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_PATTERN) & M_RS_FEC_VENDOR_TX_TEST_PATTERN)
+
+#define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER 0x241c
+
+#define S_RS_FEC_VENDOR_TX_TEST_TRIGGER    0
+#define M_RS_FEC_VENDOR_TX_TEST_TRIGGER    0xffffU
+#define V_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_TRIGGER)
+#define G_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_TRIGGER) & M_RS_FEC_VENDOR_TX_TEST_TRIGGER)
+
 #define A_MAC_PORT_FEC_KR_CONTROL 0x2600
 
 #define S_ENABLE_TR    1
@@ -36050,6 +50663,16 @@
 #define V_ABILITY(x) ((x) << S_ABILITY)
 #define F_ABILITY    V_ABILITY(1U)
 
+#define A_MAC_PORT_MTIP_FEC_ABILITY 0x2618
+
+#define S_BASE_R_FEC_ERROR_INDICATION_ABILITY    1
+#define V_BASE_R_FEC_ERROR_INDICATION_ABILITY(x) ((x) << S_BASE_R_FEC_ERROR_INDICATION_ABILITY)
+#define F_BASE_R_FEC_ERROR_INDICATION_ABILITY    V_BASE_R_FEC_ERROR_INDICATION_ABILITY(1U)
+
+#define S_BASE_R_FEC_ABILITY    0
+#define V_BASE_R_FEC_ABILITY(x) ((x) << S_BASE_R_FEC_ABILITY)
+#define F_BASE_R_FEC_ABILITY    V_BASE_R_FEC_ABILITY(1U)
+
 #define A_MAC_PORT_FEC_CONTROL 0x261c
 
 #define S_FEC_EN_ERR_IND    1
@@ -36070,6 +50693,11 @@
 #define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED)
 #define F_FEC_LOCKED    V_FEC_LOCKED(1U)
 
+#define S_FEC_LOCKED0    1
+#define M_FEC_LOCKED0    0xfU
+#define V_FEC_LOCKED0(x) ((x) << S_FEC_LOCKED0)
+#define G_FEC_LOCKED0(x) (((x) >> S_FEC_LOCKED0) & M_FEC_LOCKED0)
+
 #define A_MAC_PORT_FEC_CERR_CNT_0 0x2624
 
 #define S_FEC_CERR_CNT_0    0
@@ -36077,6 +50705,7 @@
 #define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0)
 #define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0)
 
+#define A_MAC_PORT_MTIP_FEC0_CERR_CNT_0 0x2624
 #define A_MAC_PORT_FEC_CERR_CNT_1 0x2628
 
 #define S_FEC_CERR_CNT_1    0
@@ -36084,6 +50713,7 @@
 #define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1)
 #define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1)
 
+#define A_MAC_PORT_MTIP_FEC0_CERR_CNT_1 0x2628
 #define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c
 
 #define S_FEC_NCERR_CNT_0    0
@@ -36091,6 +50721,13 @@
 #define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0)
 #define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0)
 
+#define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_0 0x262c
+
+#define S_FEC0_NCERR_CNT_0    0
+#define M_FEC0_NCERR_CNT_0    0xffffU
+#define V_FEC0_NCERR_CNT_0(x) ((x) << S_FEC0_NCERR_CNT_0)
+#define G_FEC0_NCERR_CNT_0(x) (((x) >> S_FEC0_NCERR_CNT_0) & M_FEC0_NCERR_CNT_0)
+
 #define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630
 
 #define S_FEC_NCERR_CNT_1    0
@@ -36098,6 +50735,28 @@
 #define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1)
 #define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1)
 
+#define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_1 0x2630
+
+#define S_FEC0_NCERR_CNT_1    0
+#define M_FEC0_NCERR_CNT_1    0xffffU
+#define V_FEC0_NCERR_CNT_1(x) ((x) << S_FEC0_NCERR_CNT_1)
+#define G_FEC0_NCERR_CNT_1(x) (((x) >> S_FEC0_NCERR_CNT_1) & M_FEC0_NCERR_CNT_1)
+
+#define A_MAC_PORT_MTIP_FEC_STATUS1 0x2664
+#define A_MAC_PORT_MTIP_FEC1_CERR_CNT_0 0x2668
+#define A_MAC_PORT_MTIP_FEC1_CERR_CNT_1 0x266c
+#define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_0 0x2670
+#define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_1 0x2674
+#define A_MAC_PORT_MTIP_FEC_STATUS2 0x26a8
+#define A_MAC_PORT_MTIP_FEC2_CERR_CNT_0 0x26ac
+#define A_MAC_PORT_MTIP_FEC2_CERR_CNT_1 0x26b0
+#define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_0 0x26b4
+#define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_1 0x26b8
+#define A_MAC_PORT_MTIP_FEC_STATUS3 0x26ec
+#define A_MAC_PORT_MTIP_FEC3_CERR_CNT_0 0x26f0
+#define A_MAC_PORT_MTIP_FEC3_CERR_CNT_1 0x26f4
+#define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_0 0x26f8
+#define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_1 0x26fc
 #define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00
 
 #define S_T5_RXREQ_C2    4
@@ -36115,6 +50774,11 @@
 #define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0)
 #define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0)
 
+#define S_T5_RXREQ_C3    6
+#define M_T5_RXREQ_C3    0x3U
+#define V_T5_RXREQ_C3(x) ((x) << S_T5_RXREQ_C3)
+#define G_T5_RXREQ_C3(x) (((x) >> S_T5_RXREQ_C3) & M_T5_RXREQ_C3)
+
 #define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04
 
 #define S_T5_AE0_RXSTAT_RDY    15
@@ -36136,6 +50800,23 @@
 #define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0)
 #define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0)
 
+#define S_T5_AE0_RXSTAT_LSNA    14
+#define V_T5_AE0_RXSTAT_LSNA(x) ((x) << S_T5_AE0_RXSTAT_LSNA)
+#define F_T5_AE0_RXSTAT_LSNA    V_T5_AE0_RXSTAT_LSNA(1U)
+
+#define S_T5_AE0_RXSTAT_FEC    13
+#define V_T5_AE0_RXSTAT_FEC(x) ((x) << S_T5_AE0_RXSTAT_FEC)
+#define F_T5_AE0_RXSTAT_FEC    V_T5_AE0_RXSTAT_FEC(1U)
+
+#define S_T5_AE0_RXSTAT_TF    12
+#define V_T5_AE0_RXSTAT_TF(x) ((x) << S_T5_AE0_RXSTAT_TF)
+#define F_T5_AE0_RXSTAT_TF    V_T5_AE0_RXSTAT_TF(1U)
+
+#define S_T5_AE0_RXSTAT_C3    6
+#define M_T5_AE0_RXSTAT_C3    0x3U
+#define V_T5_AE0_RXSTAT_C3(x) ((x) << S_T5_AE0_RXSTAT_C3)
+#define G_T5_AE0_RXSTAT_C3(x) (((x) >> S_T5_AE0_RXSTAT_C3) & M_T5_AE0_RXSTAT_C3)
+
 #define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08
 
 #define S_T5_TXREQ_C2    4
@@ -36153,6 +50834,15 @@
 #define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0)
 #define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0)
 
+#define S_TXREQ_FEC    11
+#define V_TXREQ_FEC(x) ((x) << S_TXREQ_FEC)
+#define F_TXREQ_FEC    V_TXREQ_FEC(1U)
+
+#define S_T5_TXREQ_C3    6
+#define M_T5_TXREQ_C3    0x3U
+#define V_T5_TXREQ_C3(x) ((x) << S_T5_TXREQ_C3)
+#define G_T5_TXREQ_C3(x) (((x) >> S_T5_TXREQ_C3) & M_T5_TXREQ_C3)
+
 #define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c
 
 #define S_T5_TXSTAT_C2    4
@@ -36170,6 +50860,11 @@
 #define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0)
 #define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0)
 
+#define S_T5_TXSTAT_C3    6
+#define M_T5_TXSTAT_C3    0x3U
+#define V_T5_TXSTAT_C3(x) ((x) << S_T5_TXSTAT_C3)
+#define G_T5_TXSTAT_C3(x) (((x) >> S_T5_TXSTAT_C3) & M_T5_TXSTAT_C3)
+
 #define A_MAC_PORT_AE_REG_MODE 0x2a10
 
 #define S_AET_RSVD    7
@@ -36180,6 +50875,31 @@
 #define V_AET_ENABLE(x) ((x) << S_AET_ENABLE)
 #define F_AET_ENABLE    V_AET_ENABLE(1U)
 
+#define S_SET_WAIT_TIMER    13
+#define M_SET_WAIT_TIMER    0x3U
+#define V_SET_WAIT_TIMER(x) ((x) << S_SET_WAIT_TIMER)
+#define G_SET_WAIT_TIMER(x) (((x) >> S_SET_WAIT_TIMER) & M_SET_WAIT_TIMER)
+
+#define S_C2_C3_STATE_SEL    12
+#define V_C2_C3_STATE_SEL(x) ((x) << S_C2_C3_STATE_SEL)
+#define F_C2_C3_STATE_SEL    V_C2_C3_STATE_SEL(1U)
+
+#define S_FFE4_EN    11
+#define V_FFE4_EN(x) ((x) << S_FFE4_EN)
+#define F_FFE4_EN    V_FFE4_EN(1U)
+
+#define S_FEC_REQUEST    10
+#define V_FEC_REQUEST(x) ((x) << S_FEC_REQUEST)
+#define F_FEC_REQUEST    V_FEC_REQUEST(1U)
+
+#define S_FEC_SUPPORTED    9
+#define V_FEC_SUPPORTED(x) ((x) << S_FEC_SUPPORTED)
+#define F_FEC_SUPPORTED    V_FEC_SUPPORTED(1U)
+
+#define S_TX_FIXED    8
+#define V_TX_FIXED(x) ((x) << S_TX_FIXED)
+#define F_TX_FIXED    V_TX_FIXED(1U)
+
 #define A_MAC_PORT_AE_PRBS_CTL 0x2a14
 #define A_MAC_PORT_AE_FSM_CTL 0x2a18
 
@@ -36210,6 +50930,23 @@
 #define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0)
 #define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0)
 
+#define S_T5_AE1_RXSTAT_LSNA    14
+#define V_T5_AE1_RXSTAT_LSNA(x) ((x) << S_T5_AE1_RXSTAT_LSNA)
+#define F_T5_AE1_RXSTAT_LSNA    V_T5_AE1_RXSTAT_LSNA(1U)
+
+#define S_T5_AE1_RXSTAT_FEC    13
+#define V_T5_AE1_RXSTAT_FEC(x) ((x) << S_T5_AE1_RXSTAT_FEC)
+#define F_T5_AE1_RXSTAT_FEC    V_T5_AE1_RXSTAT_FEC(1U)
+
+#define S_T5_AE1_RXSTAT_TF    12
+#define V_T5_AE1_RXSTAT_TF(x) ((x) << S_T5_AE1_RXSTAT_TF)
+#define F_T5_AE1_RXSTAT_TF    V_T5_AE1_RXSTAT_TF(1U)
+
+#define S_T5_AE1_RXSTAT_C3    6
+#define M_T5_AE1_RXSTAT_C3    0x3U
+#define V_T5_AE1_RXSTAT_C3(x) ((x) << S_T5_AE1_RXSTAT_C3)
+#define G_T5_AE1_RXSTAT_C3(x) (((x) >> S_T5_AE1_RXSTAT_C3) & M_T5_AE1_RXSTAT_C3)
+
 #define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28
 #define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c
 #define A_MAC_PORT_AE_REG_MODE_1 0x2a30
@@ -36238,6 +50975,23 @@
 #define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0)
 #define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0)
 
+#define S_T5_AE2_RXSTAT_LSNA    14
+#define V_T5_AE2_RXSTAT_LSNA(x) ((x) << S_T5_AE2_RXSTAT_LSNA)
+#define F_T5_AE2_RXSTAT_LSNA    V_T5_AE2_RXSTAT_LSNA(1U)
+
+#define S_T5_AE2_RXSTAT_FEC    13
+#define V_T5_AE2_RXSTAT_FEC(x) ((x) << S_T5_AE2_RXSTAT_FEC)
+#define F_T5_AE2_RXSTAT_FEC    V_T5_AE2_RXSTAT_FEC(1U)
+
+#define S_T5_AE2_RXSTAT_TF    12
+#define V_T5_AE2_RXSTAT_TF(x) ((x) << S_T5_AE2_RXSTAT_TF)
+#define F_T5_AE2_RXSTAT_TF    V_T5_AE2_RXSTAT_TF(1U)
+
+#define S_T5_AE2_RXSTAT_C3    6
+#define M_T5_AE2_RXSTAT_C3    0x3U
+#define V_T5_AE2_RXSTAT_C3(x) ((x) << S_T5_AE2_RXSTAT_C3)
+#define G_T5_AE2_RXSTAT_C3(x) (((x) >> S_T5_AE2_RXSTAT_C3) & M_T5_AE2_RXSTAT_C3)
+
 #define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48
 #define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c
 #define A_MAC_PORT_AE_REG_MODE_2 0x2a50
@@ -36266,6 +51020,23 @@
 #define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0)
 #define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0)
 
+#define S_T5_AE3_RXSTAT_LSNA    14
+#define V_T5_AE3_RXSTAT_LSNA(x) ((x) << S_T5_AE3_RXSTAT_LSNA)
+#define F_T5_AE3_RXSTAT_LSNA    V_T5_AE3_RXSTAT_LSNA(1U)
+
+#define S_T5_AE3_RXSTAT_FEC    13
+#define V_T5_AE3_RXSTAT_FEC(x) ((x) << S_T5_AE3_RXSTAT_FEC)
+#define F_T5_AE3_RXSTAT_FEC    V_T5_AE3_RXSTAT_FEC(1U)
+
+#define S_T5_AE3_RXSTAT_TF    12
+#define V_T5_AE3_RXSTAT_TF(x) ((x) << S_T5_AE3_RXSTAT_TF)
+#define F_T5_AE3_RXSTAT_TF    V_T5_AE3_RXSTAT_TF(1U)
+
+#define S_T5_AE3_RXSTAT_C3    6
+#define M_T5_AE3_RXSTAT_C3    0x3U
+#define V_T5_AE3_RXSTAT_C3(x) ((x) << S_T5_AE3_RXSTAT_C3)
+#define G_T5_AE3_RXSTAT_C3(x) (((x) >> S_T5_AE3_RXSTAT_C3) & M_T5_AE3_RXSTAT_C3)
+
 #define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68
 #define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c
 #define A_MAC_PORT_AE_REG_MODE_3 0x2a70
@@ -36329,6 +51100,20 @@
 #define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL)
 #define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL)
 
+#define S_T6_INIT_METH    12
+#define M_T6_INIT_METH    0xfU
+#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
+#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
+
+#define S_INIT_CNT    8
+#define M_INIT_CNT    0xfU
+#define V_INIT_CNT(x) ((x) << S_INIT_CNT)
+#define G_INIT_CNT(x) (((x) >> S_INIT_CNT) & M_INIT_CNT)
+
+#define S_EN_AI_N0    5
+#define V_EN_AI_N0(x) ((x) << S_EN_AI_N0)
+#define F_EN_AI_N0    V_EN_AI_N0(1U)
+
 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04
 
 #define S_GAIN_TH    6
@@ -36349,6 +51134,23 @@
 #define V_AMIN_TH(x) ((x) << S_AMIN_TH)
 #define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH)
 
+#define S_FEC_CNV    15
+#define V_FEC_CNV(x) ((x) << S_FEC_CNV)
+#define F_FEC_CNV    V_FEC_CNV(1U)
+
+#define S_EN_RETRY    14
+#define V_EN_RETRY(x) ((x) << S_EN_RETRY)
+#define F_EN_RETRY    V_EN_RETRY(1U)
+
+#define S_DPC_METH    12
+#define M_DPC_METH    0x3U
+#define V_DPC_METH(x) ((x) << S_DPC_METH)
+#define G_DPC_METH(x) (((x) >> S_DPC_METH) & M_DPC_METH)
+
+#define S_EN_P2    11
+#define V_EN_P2(x) ((x) << S_EN_P2)
+#define F_EN_P2    V_EN_P2(1U)
+
 #define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08
 
 #define S_ACC_LIM    8
@@ -36392,6 +51194,11 @@
 #define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0)
 #define F_BOOT_DEC_C0    V_BOOT_DEC_C0(1U)
 
+#define S_BOOT_LUT5    8
+#define M_BOOT_LUT5    0xfU
+#define V_BOOT_LUT5(x) ((x) << S_BOOT_LUT5)
+#define G_BOOT_LUT5(x) (((x) >> S_BOOT_LUT5) & M_BOOT_LUT5)
+
 #define A_MAC_PORT_AET_STATUS_0 0x2b10
 
 #define S_AET_STAT    9
@@ -36409,21 +51216,146 @@
 #define V_CTRL_STATE(x) ((x) << S_CTRL_STATE)
 #define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE)
 
+#define S_CTRL_STAT    8
+#define M_CTRL_STAT    0x1fU
+#define V_CTRL_STAT(x) ((x) << S_CTRL_STAT)
+#define G_CTRL_STAT(x) (((x) >> S_CTRL_STAT) & M_CTRL_STAT)
+
+#define S_T6_NEU_STATE    4
+#define M_T6_NEU_STATE    0xfU
+#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
+#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
+
+#define S_T6_CTRL_STATE    0
+#define M_T6_CTRL_STATE    0xfU
+#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
+#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
+
+#define A_MAC_PORT_AET_STATUS_20 0x2b14
+
+#define S_FRAME_LOCK_CNT    0
+#define M_FRAME_LOCK_CNT    0x7U
+#define V_FRAME_LOCK_CNT(x) ((x) << S_FRAME_LOCK_CNT)
+#define G_FRAME_LOCK_CNT(x) (((x) >> S_FRAME_LOCK_CNT) & M_FRAME_LOCK_CNT)
+
+#define A_MAC_PORT_AET_LIMITS0 0x2b18
+
+#define S_DPC_TIME_LIM    0
+#define M_DPC_TIME_LIM    0x3U
+#define V_DPC_TIME_LIM(x) ((x) << S_DPC_TIME_LIM)
+#define G_DPC_TIME_LIM(x) (((x) >> S_DPC_TIME_LIM) & M_DPC_TIME_LIM)
+
 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
+
+#define S_T6_INIT_METH    12
+#define M_T6_INIT_METH    0xfU
+#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
+#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
+
 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
 #define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
 #define A_MAC_PORT_AET_STATUS_1 0x2b30
+
+#define S_T6_NEU_STATE    4
+#define M_T6_NEU_STATE    0xfU
+#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
+#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
+
+#define S_T6_CTRL_STATE    0
+#define M_T6_CTRL_STATE    0xfU
+#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
+#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
+
+#define A_MAC_PORT_AET_STATUS_21 0x2b34
+#define A_MAC_PORT_AET_LIMITS1 0x2b38
 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
+
+#define S_T6_INIT_METH    12
+#define M_T6_INIT_METH    0xfU
+#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
+#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
+
 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
 #define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
 #define A_MAC_PORT_AET_STATUS_2 0x2b50
+
+#define S_T6_NEU_STATE    4
+#define M_T6_NEU_STATE    0xfU
+#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
+#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
+
+#define S_T6_CTRL_STATE    0
+#define M_T6_CTRL_STATE    0xfU
+#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
+#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
+
+#define A_MAC_PORT_AET_STATUS_22 0x2b54
+#define A_MAC_PORT_AET_LIMITS2 0x2b58
 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
+
+#define S_T6_INIT_METH    12
+#define M_T6_INIT_METH    0xfU
+#define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
+#define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
+
 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
 #define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
 #define A_MAC_PORT_AET_STATUS_3 0x2b70
+
+#define S_T6_NEU_STATE    4
+#define M_T6_NEU_STATE    0xfU
+#define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
+#define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
+
+#define S_T6_CTRL_STATE    0
+#define M_T6_CTRL_STATE    0xfU
+#define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
+#define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
+
+#define A_MAC_PORT_AET_STATUS_23 0x2b74
+#define A_MAC_PORT_AET_LIMITS3 0x2b78
+#define A_T6_MAC_PORT_BEAN_CTL 0x2c00
+#define A_T6_MAC_PORT_BEAN_STATUS 0x2c04
+#define A_T6_MAC_PORT_BEAN_ABILITY_0 0x2c08
+
+#define S_BEAN_REM_FAULT    13
+#define V_BEAN_REM_FAULT(x) ((x) << S_BEAN_REM_FAULT)
+#define F_BEAN_REM_FAULT    V_BEAN_REM_FAULT(1U)
+
+#define A_T6_MAC_PORT_BEAN_ABILITY_1 0x2c0c
+#define A_T6_MAC_PORT_BEAN_ABILITY_2 0x2c10
+#define A_T6_MAC_PORT_BEAN_REM_ABILITY_0 0x2c14
+
+#define S_BEAN_ABL_REM_FAULT    13
+#define V_BEAN_ABL_REM_FAULT(x) ((x) << S_BEAN_ABL_REM_FAULT)
+#define F_BEAN_ABL_REM_FAULT    V_BEAN_ABL_REM_FAULT(1U)
+
+#define A_T6_MAC_PORT_BEAN_REM_ABILITY_1 0x2c18
+#define A_T6_MAC_PORT_BEAN_REM_ABILITY_2 0x2c1c
+#define A_T6_MAC_PORT_BEAN_MS_COUNT 0x2c20
+#define A_T6_MAC_PORT_BEAN_XNP_0 0x2c24
+#define A_T6_MAC_PORT_BEAN_XNP_1 0x2c28
+#define A_T6_MAC_PORT_BEAN_XNP_2 0x2c2c
+#define A_T6_MAC_PORT_LP_BEAN_XNP_0 0x2c30
+#define A_T6_MAC_PORT_LP_BEAN_XNP_1 0x2c34
+#define A_T6_MAC_PORT_LP_BEAN_XNP_2 0x2c38
+#define A_T6_MAC_PORT_BEAN_ETH_STATUS 0x2c3c
+
+#define S_100GCR4    11
+#define V_100GCR4(x) ((x) << S_100GCR4)
+#define F_100GCR4    V_100GCR4(1U)
+
+#define S_100GKR4    10
+#define V_100GKR4(x) ((x) << S_100GKR4)
+#define F_100GKR4    V_100GKR4(1U)
+
+#define S_100GKP4    9
+#define V_100GKP4(x) ((x) << S_100GKP4)
+#define F_100GKP4    V_100GKP4(1U)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000
 
 #define S_T5_TX_LINKEN    15
@@ -36481,6 +51413,19 @@
 #define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL)
 #define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL)
 
+#define S_T6_T5_TX_RXLOOP    5
+#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
+#define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
+
+#define S_T5_TX_ENFFE4    4
+#define V_T5_TX_ENFFE4(x) ((x) << S_T5_TX_ENFFE4)
+#define F_T5_TX_ENFFE4    V_T5_TX_ENFFE4(1U)
+
+#define S_T6_T5_TX_BWSEL    2
+#define M_T6_T5_TX_BWSEL    0x3U
+#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
+#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004
 
 #define S_SPSEL    11
@@ -36496,6 +51441,22 @@
 #define V_TPGMD(x) ((x) << S_TPGMD)
 #define F_TPGMD    V_TPGMD(1U)
 
+#define S_TC_FRCERR    10
+#define V_TC_FRCERR(x) ((x) << S_TC_FRCERR)
+#define F_TC_FRCERR    V_TC_FRCERR(1U)
+
+#define S_T6_ERROR    9
+#define V_T6_ERROR(x) ((x) << S_T6_ERROR)
+#define F_T6_ERROR    V_T6_ERROR(1U)
+
+#define S_SYNC    8
+#define V_SYNC(x) ((x) << S_SYNC)
+#define F_SYNC    V_SYNC(1U)
+
+#define S_P7CHK    5
+#define V_P7CHK(x) ((x) << S_P7CHK)
+#define F_P7CHK    V_P7CHK(1U)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008
 
 #define S_ZCALOVRD    8
@@ -36514,6 +51475,10 @@
 #define V_AESRC(x) ((x) << S_AESRC)
 #define F_AESRC    V_AESRC(1U)
 
+#define S_SASMODE    7
+#define V_SASMODE(x) ((x) << S_SASMODE)
+#define F_SASMODE    V_SASMODE(1U)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c
 
 #define S_T5DRVHIZ    5
@@ -36583,6 +51548,16 @@
 #define V_CALSSTP(x) ((x) << S_CALSSTP)
 #define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP)
 
+#define S_T6_CALSSTN    8
+#define M_T6_CALSSTN    0x3fU
+#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
+#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
+
+#define S_T6_CALSSTP    0
+#define M_T6_CALSSTP    0x3fU
+#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
+#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c
 
 #define S_DRTOL    0
@@ -36590,6 +51565,11 @@
 #define V_DRTOL(x) ((x) << S_DRTOL)
 #define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL)
 
+#define S_T6_DRTOL    2
+#define M_T6_DRTOL    0x7U
+#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
+#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020
 
 #define S_T5NXTT0    0
@@ -36597,6 +51577,11 @@
 #define V_T5NXTT0(x) ((x) << S_T5NXTT0)
 #define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0)
 
+#define S_T6_NXTT0    0
+#define M_T6_NXTT0    0x3fU
+#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
+#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024
 
 #define S_T5NXTT1    0
@@ -36611,6 +51596,18 @@
 #define V_T5NXTT2(x) ((x) << S_T5NXTT2)
 #define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2)
 
+#define S_T6_NXTT2    0
+#define M_T6_NXTT2    0x3fU
+#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
+#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT 0x302c
+
+#define S_NXTT3    0
+#define M_NXTT3    0x3fU
+#define V_NXTT3(x) ((x) << S_NXTT3)
+#define G_NXTT3(x) (((x) >> S_NXTT3) & M_NXTT3)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030
 
 #define S_T5TXPWR    0
@@ -36625,6 +51622,11 @@
 #define V_NXTPOL(x) ((x) << S_NXTPOL)
 #define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL)
 
+#define S_T6_NXTPOL    0
+#define M_T6_NXTPOL    0xfU
+#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
+#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038
 
 #define S_CPREST    13
@@ -36635,8 +51637,61 @@
 #define V_CINIT(x) ((x) << S_CINIT)
 #define F_CINIT    V_CINIT(1U)
 
+#define S_SASCMD    10
+#define M_SASCMD    0x3U
+#define V_SASCMD(x) ((x) << S_SASCMD)
+#define G_SASCMD(x) (((x) >> S_SASCMD) & M_SASCMD)
+
+#define S_T6_C0UPDT    6
+#define M_T6_C0UPDT    0x3U
+#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
+#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
+
+#define S_C3UPDT    4
+#define M_C3UPDT    0x3U
+#define V_C3UPDT(x) ((x) << S_C3UPDT)
+#define G_C3UPDT(x) (((x) >> S_C3UPDT) & M_C3UPDT)
+
+#define S_T6_C2UPDT    2
+#define M_T6_C2UPDT    0x3U
+#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
+#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
+
+#define S_T6_C1UPDT    0
+#define M_T6_C1UPDT    0x3U
+#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
+#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c
+
+#define S_T6_C0STAT    6
+#define M_T6_C0STAT    0x3U
+#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
+#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
+
+#define S_C3STAT    4
+#define M_C3STAT    0x3U
+#define V_C3STAT(x) ((x) << S_C3STAT)
+#define G_C3STAT(x) (((x) >> S_C3STAT) & M_C3STAT)
+
+#define S_T6_C2STAT    2
+#define M_T6_C2STAT    0x3U
+#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
+#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
+
+#define S_T6_C1STAT    0
+#define M_T6_C1STAT    0x3U
+#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
+#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3040
+
+#define S_AETAP0    0
+#define M_AETAP0    0x7fU
+#define V_AETAP0(x) ((x) << S_AETAP0)
+#define G_AETAP0(x) (((x) >> S_AETAP0) & M_AETAP0)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044
 
 #define S_T5NIDAC1    0
@@ -36644,6 +51699,13 @@
 #define V_T5NIDAC1(x) ((x) << S_T5NIDAC1)
 #define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3044
+
+#define S_AETAP1    0
+#define M_AETAP1    0x7fU
+#define V_AETAP1(x) ((x) << S_AETAP1)
+#define G_AETAP1(x) (((x) >> S_AETAP1) & M_AETAP1)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048
 
 #define S_T5NIDAC2    0
@@ -36651,7 +51713,81 @@
 #define V_T5NIDAC2(x) ((x) << S_T5NIDAC2)
 #define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3048
+
+#define S_AETAP2    0
+#define M_AETAP2    0x7fU
+#define V_AETAP2(x) ((x) << S_AETAP2)
+#define G_AETAP2(x) (((x) >> S_AETAP2) & M_AETAP2)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x304c
+
+#define S_AETAP3    0
+#define M_AETAP3    0x7fU
+#define V_AETAP3(x) ((x) << S_AETAP3)
+#define G_AETAP3(x) (((x) >> S_AETAP3) & M_AETAP3)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER 0x3050
+
+#define S_ATUNEN    8
+#define M_ATUNEN    0xffU
+#define V_ATUNEN(x) ((x) << S_ATUNEN)
+#define G_ATUNEN(x) (((x) >> S_ATUNEN) & M_ATUNEN)
+
+#define S_ATUNEP    0
+#define M_ATUNEP    0xffU
+#define V_ATUNEP(x) ((x) << S_ATUNEP)
+#define G_ATUNEP(x) (((x) >> S_ATUNEP) & M_ATUNEP)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3058
+
+#define S_DCCCOMPINV    8
+#define V_DCCCOMPINV(x) ((x) << S_DCCCOMPINV)
+#define F_DCCCOMPINV    V_DCCCOMPINV(1U)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED 0x3060
+
+#define S_AS4X7    14
+#define M_AS4X7    0x3U
+#define V_AS4X7(x) ((x) << S_AS4X7)
+#define G_AS4X7(x) (((x) >> S_AS4X7) & M_AS4X7)
+
+#define S_AS4X6    12
+#define M_AS4X6    0x3U
+#define V_AS4X6(x) ((x) << S_AS4X6)
+#define G_AS4X6(x) (((x) >> S_AS4X6) & M_AS4X6)
+
+#define S_AS4X5    10
+#define M_AS4X5    0x3U
+#define V_AS4X5(x) ((x) << S_AS4X5)
+#define G_AS4X5(x) (((x) >> S_AS4X5) & M_AS4X5)
+
+#define S_AS4X4    8
+#define M_AS4X4    0x3U
+#define V_AS4X4(x) ((x) << S_AS4X4)
+#define G_AS4X4(x) (((x) >> S_AS4X4) & M_AS4X4)
+
+#define S_AS4X3    6
+#define M_AS4X3    0x3U
+#define V_AS4X3(x) ((x) << S_AS4X3)
+#define G_AS4X3(x) (((x) >> S_AS4X3) & M_AS4X3)
+
+#define S_AS4X2    4
+#define M_AS4X2    0x3U
+#define V_AS4X2(x) ((x) << S_AS4X2)
+#define G_AS4X2(x) (((x) >> S_AS4X2) & M_AS4X2)
+
+#define S_AS4X1    2
+#define M_AS4X1    0x3U
+#define V_AS4X1(x) ((x) << S_AS4X1)
+#define G_AS4X1(x) (((x) >> S_AS4X1) & M_AS4X1)
+
+#define S_AS4X0    0
+#define M_AS4X0    0x3U
+#define V_AS4X0(x) ((x) << S_AS4X0)
+#define G_AS4X0(x) (((x) >> S_AS4X0) & M_AS4X0)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064
 
 #define S_T5AIDAC1    0
@@ -36659,7 +51795,78 @@
 #define V_T5AIDAC1(x) ((x) << S_T5AIDAC1)
 #define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED 0x3064
+
+#define S_AS2X3    6
+#define M_AS2X3    0x3U
+#define V_AS2X3(x) ((x) << S_AS2X3)
+#define G_AS2X3(x) (((x) >> S_AS2X3) & M_AS2X3)
+
+#define S_AS2X2    4
+#define M_AS2X2    0x3U
+#define V_AS2X2(x) ((x) << S_AS2X2)
+#define G_AS2X2(x) (((x) >> S_AS2X2) & M_AS2X2)
+
+#define S_AS2X1    2
+#define M_AS2X1    0x3U
+#define V_AS2X1(x) ((x) << S_AS2X1)
+#define G_AS2X1(x) (((x) >> S_AS2X1) & M_AS2X1)
+
+#define S_AS2X0    0
+#define M_AS2X0    0x3U
+#define V_AS2X0(x) ((x) << S_AS2X0)
+#define G_AS2X0(x) (((x) >> S_AS2X0) & M_AS2X0)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED 0x3068
+
+#define S_AS1X7    14
+#define M_AS1X7    0x3U
+#define V_AS1X7(x) ((x) << S_AS1X7)
+#define G_AS1X7(x) (((x) >> S_AS1X7) & M_AS1X7)
+
+#define S_AS1X6    12
+#define M_AS1X6    0x3U
+#define V_AS1X6(x) ((x) << S_AS1X6)
+#define G_AS1X6(x) (((x) >> S_AS1X6) & M_AS1X6)
+
+#define S_AS1X5    10
+#define M_AS1X5    0x3U
+#define V_AS1X5(x) ((x) << S_AS1X5)
+#define G_AS1X5(x) (((x) >> S_AS1X5) & M_AS1X5)
+
+#define S_AS1X4    8
+#define M_AS1X4    0x3U
+#define V_AS1X4(x) ((x) << S_AS1X4)
+#define G_AS1X4(x) (((x) >> S_AS1X4) & M_AS1X4)
+
+#define S_AS1X3    6
+#define M_AS1X3    0x3U
+#define V_AS1X3(x) ((x) << S_AS1X3)
+#define G_AS1X3(x) (((x) >> S_AS1X3) & M_AS1X3)
+
+#define S_AS1X2    4
+#define M_AS1X2    0x3U
+#define V_AS1X2(x) ((x) << S_AS1X2)
+#define G_AS1X2(x) (((x) >> S_AS1X2) & M_AS1X2)
+
+#define S_AS1X1    2
+#define M_AS1X1    0x3U
+#define V_AS1X1(x) ((x) << S_AS1X1)
+#define G_AS1X1(x) (((x) >> S_AS1X1) & M_AS1X1)
+
+#define S_AS1X0    0
+#define M_AS1X0    0x3U
+#define V_AS1X0(x) ((x) << S_AS1X0)
+#define G_AS1X0(x) (((x) >> S_AS1X0) & M_AS1X0)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x306c
+
+#define S_AT4X    0
+#define M_AT4X    0xffU
+#define V_AT4X(x) ((x) << S_AT4X)
+#define G_AT4X(x) (((x) >> S_AT4X) & M_AT4X)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070
 
 #define S_MAINSC    6
@@ -36672,6 +51879,13 @@
 #define V_POSTSC(x) ((x) << S_POSTSC)
 #define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3070
+
+#define S_AT2X    8
+#define M_AT2X    0xfU
+#define V_AT2X(x) ((x) << S_AT2X)
+#define G_AT2X(x) (((x) >> S_AT2X) & M_AT2X)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074
 
 #define S_PRESC    0
@@ -36679,6 +51893,13 @@
 #define V_PRESC(x) ((x) << S_PRESC)
 #define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3074
+
+#define S_ATSIGN    0
+#define M_ATSIGN    0xfU
+#define V_ATSIGN(x) ((x) << S_ATSIGN)
+#define G_ATSIGN(x) (((x) >> S_ATSIGN) & M_ATSIGN)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c
 
@@ -36691,6 +51912,11 @@
 #define V_T5XWR(x) ((x) << S_T5XWR)
 #define F_T5XWR    V_T5XWR(1U)
 
+#define S_T6_XADDR    1
+#define M_T6_XADDR    0x1fU
+#define V_T6_XADDR(x) ((x) << S_T6_XADDR)
+#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080
 
 #define S_XDAT10    0
@@ -36712,6 +51938,13 @@
 #define V_XDAT4(x) ((x) << S_XDAT4)
 #define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3088
+
+#define S_XDAT54    0
+#define M_XDAT54    0xffffU
+#define V_XDAT54(x) ((x) << S_XDAT54)
+#define G_XDAT54(x) (((x) >> S_XDAT54) & M_XDAT54)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c
 
 #define S_DCCTIMEDOUT    15
@@ -36745,6 +51978,13 @@
 #define V_DCCAEN(x) ((x) << S_DCCAEN)
 #define F_DCCAEN    V_DCCAEN(1U)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x308c
+
+#define S_XDAT76    0
+#define M_XDAT76    0xffffU
+#define V_XDAT76(x) ((x) << S_XDAT76)
+#define G_XDAT76(x) (((x) >> S_XDAT76) & M_XDAT76)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090
 
 #define S_DCCOUT    12
@@ -36808,6 +52048,203 @@
 #define V_LPIPRCD(x) ((x) << S_LPIPRCD)
 #define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD)
 
+#define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x30a0
+
+#define S_T6_DCCTIMEEN    13
+#define M_T6_DCCTIMEEN    0x3U
+#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
+#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
+
+#define S_T6_DCCLOCK    11
+#define M_T6_DCCLOCK    0x3U
+#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
+#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
+
+#define S_T6_DCCOFFSET    8
+#define M_T6_DCCOFFSET    0x7U
+#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
+#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
+
+#define S_TX_LINKA_DCCSTEP_CTL    6
+#define M_TX_LINKA_DCCSTEP_CTL    0x3U
+#define V_TX_LINKA_DCCSTEP_CTL(x) ((x) << S_TX_LINKA_DCCSTEP_CTL)
+#define G_TX_LINKA_DCCSTEP_CTL(x) (((x) >> S_TX_LINKA_DCCSTEP_CTL) & M_TX_LINKA_DCCSTEP_CTL)
+
+#define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x30a4
+#define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x30a8
+#define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x30ac
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE 0x30c0
+
+#define S_OSIGN    0
+#define M_OSIGN    0xfU
+#define V_OSIGN(x) ((x) << S_OSIGN)
+#define G_OSIGN(x) (((x) >> S_OSIGN) & M_OSIGN)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE 0x30c8
+
+#define S_OS4X7    14
+#define M_OS4X7    0x3U
+#define V_OS4X7(x) ((x) << S_OS4X7)
+#define G_OS4X7(x) (((x) >> S_OS4X7) & M_OS4X7)
+
+#define S_OS4X6    12
+#define M_OS4X6    0x3U
+#define V_OS4X6(x) ((x) << S_OS4X6)
+#define G_OS4X6(x) (((x) >> S_OS4X6) & M_OS4X6)
+
+#define S_OS4X5    10
+#define M_OS4X5    0x3U
+#define V_OS4X5(x) ((x) << S_OS4X5)
+#define G_OS4X5(x) (((x) >> S_OS4X5) & M_OS4X5)
+
+#define S_OS4X4    8
+#define M_OS4X4    0x3U
+#define V_OS4X4(x) ((x) << S_OS4X4)
+#define G_OS4X4(x) (((x) >> S_OS4X4) & M_OS4X4)
+
+#define S_OS4X3    6
+#define M_OS4X3    0x3U
+#define V_OS4X3(x) ((x) << S_OS4X3)
+#define G_OS4X3(x) (((x) >> S_OS4X3) & M_OS4X3)
+
+#define S_OS4X2    4
+#define M_OS4X2    0x3U
+#define V_OS4X2(x) ((x) << S_OS4X2)
+#define G_OS4X2(x) (((x) >> S_OS4X2) & M_OS4X2)
+
+#define S_OS4X1    2
+#define M_OS4X1    0x3U
+#define V_OS4X1(x) ((x) << S_OS4X1)
+#define G_OS4X1(x) (((x) >> S_OS4X1) & M_OS4X1)
+
+#define S_OS4X0    0
+#define M_OS4X0    0x3U
+#define V_OS4X0(x) ((x) << S_OS4X0)
+#define G_OS4X0(x) (((x) >> S_OS4X0) & M_OS4X0)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE 0x30cc
+
+#define S_OS2X3    6
+#define M_OS2X3    0x3U
+#define V_OS2X3(x) ((x) << S_OS2X3)
+#define G_OS2X3(x) (((x) >> S_OS2X3) & M_OS2X3)
+
+#define S_OS2X2    4
+#define M_OS2X2    0x3U
+#define V_OS2X2(x) ((x) << S_OS2X2)
+#define G_OS2X2(x) (((x) >> S_OS2X2) & M_OS2X2)
+
+#define S_OS2X1    2
+#define M_OS2X1    0x3U
+#define V_OS2X1(x) ((x) << S_OS2X1)
+#define G_OS2X1(x) (((x) >> S_OS2X1) & M_OS2X1)
+
+#define S_OS2X0    0
+#define M_OS2X0    0x3U
+#define V_OS2X0(x) ((x) << S_OS2X0)
+#define G_OS2X0(x) (((x) >> S_OS2X0) & M_OS2X0)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE 0x30d0
+
+#define S_OS1X7    14
+#define M_OS1X7    0x3U
+#define V_OS1X7(x) ((x) << S_OS1X7)
+#define G_OS1X7(x) (((x) >> S_OS1X7) & M_OS1X7)
+
+#define S_OS1X6    12
+#define M_OS1X6    0x3U
+#define V_OS1X6(x) ((x) << S_OS1X6)
+#define G_OS1X6(x) (((x) >> S_OS1X6) & M_OS1X6)
+
+#define S_OS1X5    10
+#define M_OS1X5    0x3U
+#define V_OS1X5(x) ((x) << S_OS1X5)
+#define G_OS1X5(x) (((x) >> S_OS1X5) & M_OS1X5)
+
+#define S_OS1X4    8
+#define M_OS1X4    0x3U
+#define V_OS1X4(x) ((x) << S_OS1X4)
+#define G_OS1X4(x) (((x) >> S_OS1X4) & M_OS1X4)
+
+#define S_OS1X3    6
+#define M_OS1X3    0x3U
+#define V_OS1X3(x) ((x) << S_OS1X3)
+#define G_OS1X3(x) (((x) >> S_OS1X3) & M_OS1X3)
+
+#define S_OS1X2    4
+#define M_OS1X2    0x3U
+#define V_OS1X2(x) ((x) << S_OS1X2)
+#define G_OS1X2(x) (((x) >> S_OS1X2) & M_OS1X2)
+
+#define S_OS1X1    2
+#define M_OS1X1    0x3U
+#define V_OS1X1(x) ((x) << S_OS1X1)
+#define G_OS1X1(x) (((x) >> S_OS1X1) & M_OS1X1)
+
+#define S_OS1X0    0
+#define M_OS1X0    0x3U
+#define V_OS1X0(x) ((x) << S_OS1X0)
+#define G_OS1X0(x) (((x) >> S_OS1X0) & M_OS1X0)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x30d8
+
+#define S_OT4X    0
+#define M_OT4X    0xffU
+#define V_OT4X(x) ((x) << S_OT4X)
+#define G_OT4X(x) (((x) >> S_OT4X) & M_OT4X)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x30dc
+
+#define S_OT2X    0
+#define M_OT2X    0xfU
+#define V_OT2X(x) ((x) << S_OT2X)
+#define G_OT2X(x) (((x) >> S_OT2X) & M_OT2X)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x30e0
+
+#define S_OT1X    0
+#define M_OT1X    0xffU
+#define V_OT1X(x) ((x) << S_OT1X)
+#define G_OT1X(x) (((x) >> S_OT1X) & M_OT1X)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5 0x30ec
+
+#define S_ERRORP    15
+#define V_ERRORP(x) ((x) << S_ERRORP)
+#define F_ERRORP    V_ERRORP(1U)
+
+#define S_ERRORN    14
+#define V_ERRORN(x) ((x) << S_ERRORN)
+#define F_ERRORN    V_ERRORN(1U)
+
+#define S_TESTENA    13
+#define V_TESTENA(x) ((x) << S_TESTENA)
+#define F_TESTENA    V_TESTENA(1U)
+
+#define S_TUNEBIT    10
+#define M_TUNEBIT    0x7U
+#define V_TUNEBIT(x) ((x) << S_TUNEBIT)
+#define G_TUNEBIT(x) (((x) >> S_TUNEBIT) & M_TUNEBIT)
+
+#define S_DATAPOS    8
+#define M_DATAPOS    0x3U
+#define V_DATAPOS(x) ((x) << S_DATAPOS)
+#define G_DATAPOS(x) (((x) >> S_DATAPOS) & M_DATAPOS)
+
+#define S_SEGSEL    3
+#define M_SEGSEL    0x1fU
+#define V_SEGSEL(x) ((x) << S_SEGSEL)
+#define G_SEGSEL(x) (((x) >> S_SEGSEL) & M_SEGSEL)
+
+#define S_TAPSEL    1
+#define M_TAPSEL    0x3U
+#define V_TAPSEL(x) ((x) << S_TAPSEL)
+#define G_TAPSEL(x) (((x) >> S_TAPSEL) & M_TAPSEL)
+
+#define S_DATASIGN    0
+#define V_DATASIGN(x) ((x) << S_DATASIGN)
+#define F_DATASIGN    V_DATASIGN(1U)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0
 
 #define S_SDOVRDEN    8
@@ -36819,6 +52256,11 @@
 #define V_SDOVRD(x) ((x) << S_SDOVRD)
 #define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD)
 
+#define S_T6_SDOVRD    0
+#define M_T6_SDOVRD    0xffffU
+#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
+#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4
 
 #define S_SLEWCODE    1
@@ -36830,6 +52272,11 @@
 #define V_ASEGEN(x) ((x) << S_ASEGEN)
 #define F_ASEGEN    V_ASEGEN(1U)
 
+#define S_WCNT    0
+#define M_WCNT    0x3ffU
+#define V_WCNT(x) ((x) << S_WCNT)
+#define G_WCNT(x) (((x) >> S_WCNT) & M_WCNT)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8
 
 #define S_AECMDVAL    14
@@ -36891,43 +52338,202 @@
 #define V_OBS(x) ((x) << S_OBS)
 #define F_OBS    V_OBS(1U)
 
+#define S_T6_SDOVRDEN    15
+#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
+#define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
+
+#define S_BSOUTN    7
+#define V_BSOUTN(x) ((x) << S_BSOUTN)
+#define F_BSOUTN    V_BSOUTN(1U)
+
+#define S_BSOUTP    6
+#define V_BSOUTP(x) ((x) << S_BSOUTP)
+#define F_BSOUTP    V_BSOUTP(1U)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
+
+#define S_T6_T5_TX_RXLOOP    5
+#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
+#define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
+
+#define S_T6_T5_TX_BWSEL    2
+#define M_T6_T5_TX_BWSEL    0x3U
+#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
+#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
+
+#define S_T6_ERROR    9
+#define V_T6_ERROR(x) ((x) << S_T6_ERROR)
+#define F_T6_ERROR    V_T6_ERROR(1U)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
+
+#define S_T6_CALSSTN    8
+#define M_T6_CALSSTN    0x3fU
+#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
+#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
+
+#define S_T6_CALSSTP    0
+#define M_T6_CALSSTP    0x3fU
+#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
+#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
+
+#define S_T6_DRTOL    2
+#define M_T6_DRTOL    0x7U
+#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
+#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
+
+#define S_T6_NXTT0    0
+#define M_T6_NXTT0    0x3fU
+#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
+#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
+
+#define S_T6_NXTT2    0
+#define M_T6_NXTT2    0x3fU
+#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
+#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
+
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT 0x312c
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
+
+#define S_T6_NXTPOL    0
+#define M_T6_NXTPOL    0xfU
+#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
+#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
+
+#define S_T6_C0UPDT    6
+#define M_T6_C0UPDT    0x3U
+#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
+#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
+
+#define S_T6_C2UPDT    2
+#define M_T6_C2UPDT    0x3U
+#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
+#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
+
+#define S_T6_C1UPDT    0
+#define M_T6_C1UPDT    0x3U
+#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
+#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
+
+#define S_T6_C0STAT    6
+#define M_T6_C0STAT    0x3U
+#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
+#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
+
+#define S_T6_C2STAT    2
+#define M_T6_C2STAT    0x3U
+#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
+#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
+
+#define S_T6_C1STAT    0
+#define M_T6_C1STAT    0x3U
+#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
+#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3140
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3144
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3148
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x314c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER 0x3150
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3158
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED 0x3160
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED 0x3164
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED 0x3168
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x316c
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3170
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3174
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
+
+#define S_T6_XADDR    1
+#define M_T6_XADDR    0x1fU
+#define V_T6_XADDR(x) ((x) << S_T6_XADDR)
+#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3188
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x318c
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
+#define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x31a0
+
+#define S_T6_DCCTIMEEN    13
+#define M_T6_DCCTIMEEN    0x3U
+#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
+#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
+
+#define S_T6_DCCLOCK    11
+#define M_T6_DCCLOCK    0x3U
+#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
+#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
+
+#define S_T6_DCCOFFSET    8
+#define M_T6_DCCOFFSET    0x7U
+#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
+#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
+
+#define S_TX_LINKB_DCCSTEP_CTL    6
+#define M_TX_LINKB_DCCSTEP_CTL    0x3U
+#define V_TX_LINKB_DCCSTEP_CTL(x) ((x) << S_TX_LINKB_DCCSTEP_CTL)
+#define G_TX_LINKB_DCCSTEP_CTL(x) (((x) >> S_TX_LINKB_DCCSTEP_CTL) & M_TX_LINKB_DCCSTEP_CTL)
+
+#define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x31a4
+#define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x31a8
+#define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x31ac
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE 0x31c0
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE 0x31c8
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE 0x31cc
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE 0x31d0
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x31d8
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x31dc
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x31e0
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5 0x31ec
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
+
+#define S_T6_SDOVRD    0
+#define M_T6_SDOVRD    0xffffU
+#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
+#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
+
+#define S_T6_SDOVRDEN    15
+#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
+#define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
 
 #define S_T5_RX_LINKEN    15
@@ -36979,6 +52585,10 @@
 #define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL)
 #define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL)
 
+#define S_T5_RX_MODE8023AZ    8
+#define V_T5_RX_MODE8023AZ(x) ((x) << S_T5_RX_MODE8023AZ)
+#define F_T5_RX_MODE8023AZ    V_T5_RX_MODE8023AZ(1U)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204
 
 #define S_FERRST    10
@@ -37010,6 +52620,20 @@
 #define V_PATSEL(x) ((x) << S_PATSEL)
 #define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL)
 
+#define S_APLYDCD    15
+#define V_APLYDCD(x) ((x) << S_APLYDCD)
+#define F_APLYDCD    V_APLYDCD(1U)
+
+#define S_PPOL    13
+#define M_PPOL    0x3U
+#define V_PPOL(x) ((x) << S_PPOL)
+#define G_PPOL(x) (((x) >> S_PPOL) & M_PPOL)
+
+#define S_PCLKSEL    11
+#define M_PCLKSEL    0x3U
+#define V_PCLKSEL(x) ((x) << S_PCLKSEL)
+#define G_PCLKSEL(x) (((x) >> S_PCLKSEL) & M_PCLKSEL)
+
 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208
 
 #define S_RSTUCK    3
@@ -37029,6 +52653,30 @@
 #define F_SSCEN    V_SSCEN(1U)
 
 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c
+
+#define S_H1ANOFST    12
+#define M_H1ANOFST    0xfU
+#define V_H1ANOFST(x) ((x) << S_H1ANOFST)
+#define G_H1ANOFST(x) (((x) >> S_H1ANOFST) & M_H1ANOFST)
+
+#define S_T6_TMSCAL    8
+#define M_T6_TMSCAL    0x3U
+#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
+#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
+
+#define S_T6_APADJ    7
+#define V_T6_APADJ(x) ((x) << S_T6_APADJ)
+#define F_T6_APADJ    V_T6_APADJ(1U)
+
+#define S_T6_RSEL    6
+#define V_T6_RSEL(x) ((x) << S_T6_RSEL)
+#define F_T6_RSEL    V_T6_RSEL(1U)
+
+#define S_T6_PHOFFS    0
+#define M_T6_PHOFFS    0x3fU
+#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
+#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
+
 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210
 
 #define S_ROT00    0
@@ -37036,6 +52684,16 @@
 #define V_ROT00(x) ((x) << S_ROT00)
 #define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00)
 
+#define S_ROTA    8
+#define M_ROTA    0x3fU
+#define V_ROTA(x) ((x) << S_ROTA)
+#define G_ROTA(x) (((x) >> S_ROTA) & M_ROTA)
+
+#define S_ROTD    0
+#define M_ROTD    0x3fU
+#define V_ROTD(x) ((x) << S_ROTD)
+#define G_ROTD(x) (((x) >> S_ROTD) & M_ROTD)
+
 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214
 
 #define S_FREQFW    8
@@ -37047,7 +52705,23 @@
 #define V_FWSNAP(x) ((x) << S_FWSNAP)
 #define F_FWSNAP    V_FWSNAP(1U)
 
+#define S_ROTE    0
+#define M_ROTE    0x3fU
+#define V_ROTE(x) ((x) << S_ROTE)
+#define G_ROTE(x) (((x) >> S_ROTE) & M_ROTE)
+
 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218
+
+#define S_RAOFFF    8
+#define M_RAOFFF    0xfU
+#define V_RAOFFF(x) ((x) << S_RAOFFF)
+#define G_RAOFFF(x) (((x) >> S_RAOFFF) & M_RAOFFF)
+
+#define S_RAOFF    0
+#define M_RAOFF    0x1fU
+#define V_RAOFF(x) ((x) << S_RAOFF)
+#define G_RAOFF(x) (((x) >> S_RAOFF) & M_RAOFF)
+
 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c
 
 #define S_RBOOFF    10
@@ -37061,6 +52735,12 @@
 #define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF)
 
 #define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220
+
+#define S_T6_SPIFMT    8
+#define M_T6_SPIFMT    0xfU
+#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
+#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
+
 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224
 
 #define S_T5BYTE1    8
@@ -37098,7 +52778,30 @@
 #define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP)
 #define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP)
 
+#define S_REQWOV    15
+#define V_REQWOV(x) ((x) << S_REQWOV)
+#define F_REQWOV    V_REQWOV(1U)
+
+#define S_RASEL    11
+#define M_RASEL    0x7U
+#define V_RASEL(x) ((x) << S_RASEL)
+#define G_RASEL(x) (((x) >> S_RASEL) & M_RASEL)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c
+
+#define S_T6_WRAPSEL    15
+#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
+#define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
+
+#define S_ACTL    14
+#define V_ACTL(x) ((x) << S_ACTL)
+#define F_ACTL    V_ACTL(1U)
+
+#define S_T6_PEAK    9
+#define M_T6_PEAK    0x1fU
+#define V_T6_PEAK(x) ((x) << S_T6_PEAK)
+#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230
 
 #define S_T5SHORTV    10
@@ -37110,6 +52813,37 @@
 #define V_T5VGAIN(x) ((x) << S_T5VGAIN)
 #define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN)
 
+#define S_FVOFFSKP    15
+#define V_FVOFFSKP(x) ((x) << S_FVOFFSKP)
+#define F_FVOFFSKP    V_FVOFFSKP(1U)
+
+#define S_FGAINCHK    14
+#define V_FGAINCHK(x) ((x) << S_FGAINCHK)
+#define F_FGAINCHK    V_FGAINCHK(1U)
+
+#define S_FH1ACAL    13
+#define V_FH1ACAL(x) ((x) << S_FH1ACAL)
+#define F_FH1ACAL    V_FH1ACAL(1U)
+
+#define S_FH1AFLTR    11
+#define M_FH1AFLTR    0x3U
+#define V_FH1AFLTR(x) ((x) << S_FH1AFLTR)
+#define G_FH1AFLTR(x) (((x) >> S_FH1AFLTR) & M_FH1AFLTR)
+
+#define S_WGAIN    8
+#define M_WGAIN    0x3U
+#define V_WGAIN(x) ((x) << S_WGAIN)
+#define G_WGAIN(x) (((x) >> S_WGAIN) & M_WGAIN)
+
+#define S_GAIN_STAT    7
+#define V_GAIN_STAT(x) ((x) << S_GAIN_STAT)
+#define F_GAIN_STAT    V_GAIN_STAT(1U)
+
+#define S_T6_T5VGAIN    0
+#define M_T6_T5VGAIN    0x7fU
+#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
+#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234
 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238
 
@@ -37128,6 +52862,34 @@
 #define V_DUTYI(x) ((x) << S_DUTYI)
 #define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI)
 
+#define A_MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3238
+
+#define S_PMCFG    6
+#define M_PMCFG    0x3U
+#define V_PMCFG(x) ((x) << S_PMCFG)
+#define G_PMCFG(x) (((x) >> S_PMCFG) & M_PMCFG)
+
+#define S_PMOFFTIME    0
+#define M_PMOFFTIME    0x3fU
+#define V_PMOFFTIME(x) ((x) << S_PMOFFTIME)
+#define G_PMOFFTIME(x) (((x) >> S_PMOFFTIME) & M_PMOFFTIME)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1 0x323c
+
+#define S_SELI    9
+#define V_SELI(x) ((x) << S_SELI)
+#define F_SELI    V_SELI(1U)
+
+#define S_SERVREF    5
+#define M_SERVREF    0x7U
+#define V_SERVREF(x) ((x) << S_SERVREF)
+#define G_SERVREF(x) (((x) >> S_SERVREF) & M_SERVREF)
+
+#define S_IQAMP    0
+#define M_IQAMP    0x1fU
+#define V_IQAMP(x) ((x) << S_IQAMP)
+#define G_IQAMP(x) (((x) >> S_IQAMP) & M_IQAMP)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240
 
 #define S_DTHR    8
@@ -37140,8 +52902,41 @@
 #define V_SNUL(x) ((x) << S_SNUL)
 #define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL)
 
+#define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2 0x3240
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3244
+
+#define S_SAVEADAC    8
+#define V_SAVEADAC(x) ((x) << S_SAVEADAC)
+#define F_SAVEADAC    V_SAVEADAC(1U)
+
+#define S_LOAD2    7
+#define V_LOAD2(x) ((x) << S_LOAD2)
+#define F_LOAD2    V_LOAD2(1U)
+
+#define S_LOAD1    6
+#define V_LOAD1(x) ((x) << S_LOAD1)
+#define F_LOAD1    V_LOAD1(1U)
+
+#define S_WRTACC2    5
+#define V_WRTACC2(x) ((x) << S_WRTACC2)
+#define F_WRTACC2    V_WRTACC2(1U)
+
+#define S_WRTACC1    4
+#define V_WRTACC1(x) ((x) << S_WRTACC1)
+#define F_WRTACC1    V_WRTACC1(1U)
+
+#define S_SELAPAN    3
+#define V_SELAPAN(x) ((x) << S_SELAPAN)
+#define F_SELAPAN    V_SELAPAN(1U)
+
+#define S_DASEL    0
+#define M_DASEL    0x7U
+#define V_DASEL(x) ((x) << S_DASEL)
+#define G_DASEL(x) (((x) >> S_DASEL) & M_DASEL)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248
 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN 0x324c
 #define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250
 
 #define S_ADSN_READWRITE    8
@@ -37152,6 +52947,61 @@
 #define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY)
 #define F_ADSN_READONLY    V_ADSN_READONLY(1U)
 
+#define S_ADAC2    8
+#define M_ADAC2    0xffU
+#define V_ADAC2(x) ((x) << S_ADAC2)
+#define G_ADAC2(x) (((x) >> S_ADAC2) & M_ADAC2)
+
+#define S_ADAC1    0
+#define M_ADAC1    0xffU
+#define V_ADAC1(x) ((x) << S_ADAC1)
+#define G_ADAC1(x) (((x) >> S_ADAC1) & M_ADAC1)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL 0x3254
+
+#define S_FACCPLDYN    13
+#define V_FACCPLDYN(x) ((x) << S_FACCPLDYN)
+#define F_FACCPLDYN    V_FACCPLDYN(1U)
+
+#define S_ACCPLGAIN    10
+#define M_ACCPLGAIN    0x7U
+#define V_ACCPLGAIN(x) ((x) << S_ACCPLGAIN)
+#define G_ACCPLGAIN(x) (((x) >> S_ACCPLGAIN) & M_ACCPLGAIN)
+
+#define S_ACCPLREF    8
+#define M_ACCPLREF    0x3U
+#define V_ACCPLREF(x) ((x) << S_ACCPLREF)
+#define G_ACCPLREF(x) (((x) >> S_ACCPLREF) & M_ACCPLREF)
+
+#define S_ACCPLSTEP    6
+#define M_ACCPLSTEP    0x3U
+#define V_ACCPLSTEP(x) ((x) << S_ACCPLSTEP)
+#define G_ACCPLSTEP(x) (((x) >> S_ACCPLSTEP) & M_ACCPLSTEP)
+
+#define S_ACCPLASTEP    1
+#define M_ACCPLASTEP    0x1fU
+#define V_ACCPLASTEP(x) ((x) << S_ACCPLASTEP)
+#define G_ACCPLASTEP(x) (((x) >> S_ACCPLASTEP) & M_ACCPLASTEP)
+
+#define S_FACCPL    0
+#define V_FACCPL(x) ((x) << S_FACCPL)
+#define F_FACCPL    V_FACCPL(1U)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE 0x3258
+
+#define S_ACCPLMEANS    15
+#define V_ACCPLMEANS(x) ((x) << S_ACCPLMEANS)
+#define F_ACCPLMEANS    V_ACCPLMEANS(1U)
+
+#define S_CDROVREN    8
+#define V_CDROVREN(x) ((x) << S_CDROVREN)
+#define F_CDROVREN    V_CDROVREN(1U)
+
+#define S_ACCPLBIAS    0
+#define M_ACCPLBIAS    0xffU
+#define V_ACCPLBIAS(x) ((x) << S_ACCPLBIAS)
+#define G_ACCPLBIAS(x) (((x) >> S_ACCPLBIAS) & M_ACCPLBIAS)
+
 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c
 
 #define S_H1O2    8
@@ -37164,6 +53014,13 @@
 #define V_H1E2(x) ((x) << S_H1E2)
 #define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2)
 
+#define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET 0x325c
+
+#define S_H123CH    0
+#define M_H123CH    0x3fU
+#define V_H123CH(x) ((x) << S_H123CH)
+#define G_H123CH(x) (((x) >> S_H123CH) & M_H123CH)
+
 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260
 
 #define S_H1O3    8
@@ -37176,6 +53033,18 @@
 #define V_H1E3(x) ((x) << S_H1E3)
 #define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3)
 
+#define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3260
+
+#define S_H1OX    8
+#define M_H1OX    0x3fU
+#define V_H1OX(x) ((x) << S_H1OX)
+#define G_H1OX(x) (((x) >> S_H1OX) & M_H1OX)
+
+#define S_H1EX    0
+#define M_H1EX    0x3fU
+#define V_H1EX(x) ((x) << S_H1EX)
+#define G_H1EX(x) (((x) >> S_H1EX) & M_H1EX)
+
 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264
 
 #define S_H1O4    8
@@ -37188,13 +53057,107 @@
 #define V_H1E4(x) ((x) << S_H1E4)
 #define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4)
 
+#define A_MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR 0x3264
+
+#define S_PILOCK    10
+#define V_PILOCK(x) ((x) << S_PILOCK)
+#define F_PILOCK    V_PILOCK(1U)
+
+#define S_UNPKPKA    2
+#define M_UNPKPKA    0x3fU
+#define V_UNPKPKA(x) ((x) << S_UNPKPKA)
+#define G_UNPKPKA(x) (((x) >> S_UNPKPKA) & M_UNPKPKA)
+
+#define S_UNPKVGA    0
+#define M_UNPKVGA    0x3U
+#define V_UNPKVGA(x) ((x) << S_UNPKVGA)
+#define G_UNPKVGA(x) (((x) >> S_UNPKVGA) & M_UNPKVGA)
+
+#define A_MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH 0x3268
+
+#define S_OVRAC    15
+#define V_OVRAC(x) ((x) << S_OVRAC)
+#define F_OVRAC    V_OVRAC(1U)
+
+#define S_OVRPK    14
+#define V_OVRPK(x) ((x) << S_OVRPK)
+#define F_OVRPK    V_OVRPK(1U)
+
+#define S_OVRTAILS    12
+#define M_OVRTAILS    0x3U
+#define V_OVRTAILS(x) ((x) << S_OVRTAILS)
+#define G_OVRTAILS(x) (((x) >> S_OVRTAILS) & M_OVRTAILS)
+
+#define S_OVRTAILV    9
+#define M_OVRTAILV    0x7U
+#define V_OVRTAILV(x) ((x) << S_OVRTAILV)
+#define G_OVRTAILV(x) (((x) >> S_OVRTAILV) & M_OVRTAILV)
+
+#define S_OVRCAP    8
+#define V_OVRCAP(x) ((x) << S_OVRCAP)
+#define F_OVRCAP    V_OVRCAP(1U)
+
+#define S_OVRDCDPRE    7
+#define V_OVRDCDPRE(x) ((x) << S_OVRDCDPRE)
+#define F_OVRDCDPRE    V_OVRDCDPRE(1U)
+
+#define S_OVRDCDPST    6
+#define V_OVRDCDPST(x) ((x) << S_OVRDCDPST)
+#define F_OVRDCDPST    V_OVRDCDPST(1U)
+
+#define S_DCVSCTMODE    2
+#define V_DCVSCTMODE(x) ((x) << S_DCVSCTMODE)
+#define F_DCVSCTMODE    V_DCVSCTMODE(1U)
+
+#define S_CDRANLGSW    0
+#define M_CDRANLGSW    0x3U
+#define V_CDRANLGSW(x) ((x) << S_CDRANLGSW)
+#define G_CDRANLGSW(x) (((x) >> S_CDRANLGSW) & M_CDRANLGSW)
+
+#define A_MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x326c
+
+#define S_PFLAG    5
+#define M_PFLAG    0x3U
+#define V_PFLAG(x) ((x) << S_PFLAG)
+#define G_PFLAG(x) (((x) >> S_PFLAG) & M_PFLAG)
+
 #define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270
 
 #define S_DPCMD    14
 #define V_DPCMD(x) ((x) << S_DPCMD)
 #define F_DPCMD    V_DPCMD(1U)
 
+#define S_DACCLIP    15
+#define V_DACCLIP(x) ((x) << S_DACCLIP)
+#define F_DACCLIP    V_DACCLIP(1U)
+
+#define S_DPCFRZ    14
+#define V_DPCFRZ(x) ((x) << S_DPCFRZ)
+#define F_DPCFRZ    V_DPCFRZ(1U)
+
+#define S_DPCLKNQ    11
+#define V_DPCLKNQ(x) ((x) << S_DPCLKNQ)
+#define F_DPCLKNQ    V_DPCLKNQ(1U)
+
+#define S_DPCWDFE    10
+#define V_DPCWDFE(x) ((x) << S_DPCWDFE)
+#define F_DPCWDFE    V_DPCWDFE(1U)
+
+#define S_DPCWPK    9
+#define V_DPCWPK(x) ((x) << S_DPCWPK)
+#define F_DPCWPK    V_DPCWPK(1U)
+
 #define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274
+
+#define S_VIEWSCAN    4
+#define V_VIEWSCAN(x) ((x) << S_VIEWSCAN)
+#define F_VIEWSCAN    V_VIEWSCAN(1U)
+
+#define S_T6_ODEC    0
+#define M_T6_ODEC    0xfU
+#define V_T6_ODEC(x) ((x) << S_T6_ODEC)
+#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278
 
 #define S_T5BER6VAL    15
@@ -37253,6 +53216,18 @@
 #define V_T5OCCMP(x) ((x) << S_T5OCCMP)
 #define F_T5OCCMP    V_T5OCCMP(1U)
 
+#define S_RX_LINKA_ACCCMP_RIS    11
+#define V_RX_LINKA_ACCCMP_RIS(x) ((x) << S_RX_LINKA_ACCCMP_RIS)
+#define F_RX_LINKA_ACCCMP_RIS    V_RX_LINKA_ACCCMP_RIS(1U)
+
+#define S_DCCCMP    10
+#define V_DCCCMP(x) ((x) << S_DCCCMP)
+#define F_DCCCMP    V_DCCCMP(1U)
+
+#define S_T5IQCMP    1
+#define V_T5IQCMP(x) ((x) << S_T5IQCMP)
+#define F_T5IQCMP    V_T5IQCMP(1U)
+
 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c
 
 #define S_FLOFF    1
@@ -37301,6 +53276,42 @@
 #define V_FDQCC(x) ((x) << S_FDQCC)
 #define F_FDQCC    V_FDQCC(1U)
 
+#define S_FDCCAL    14
+#define V_FDCCAL(x) ((x) << S_FDCCAL)
+#define F_FDCCAL    V_FDCCAL(1U)
+
+#define S_FROTCAL    13
+#define V_FROTCAL(x) ((x) << S_FROTCAL)
+#define F_FROTCAL    V_FROTCAL(1U)
+
+#define S_FIQAMP    12
+#define V_FIQAMP(x) ((x) << S_FIQAMP)
+#define F_FIQAMP    V_FIQAMP(1U)
+
+#define S_FRPTCALF    11
+#define V_FRPTCALF(x) ((x) << S_FRPTCALF)
+#define F_FRPTCALF    V_FRPTCALF(1U)
+
+#define S_FINTCALGS    10
+#define V_FINTCALGS(x) ((x) << S_FINTCALGS)
+#define F_FINTCALGS    V_FINTCALGS(1U)
+
+#define S_FDCC    9
+#define V_FDCC(x) ((x) << S_FDCC)
+#define F_FDCC    V_FDCC(1U)
+
+#define S_FDCD    7
+#define V_FDCD(x) ((x) << S_FDCD)
+#define F_FDCD    V_FDCD(1U)
+
+#define S_FINTRCALDYN    1
+#define V_FINTRCALDYN(x) ((x) << S_FINTRCALDYN)
+#define F_FINTRCALDYN    V_FINTRCALDYN(1U)
+
+#define S_FQCC    0
+#define V_FQCC(x) ((x) << S_FQCC)
+#define F_FQCC    V_FQCC(1U)
+
 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284
 
 #define S_LOFE2S_READWRITE    16
@@ -37330,6 +53341,31 @@
 #define V_LOFE1(x) ((x) << S_LOFE1)
 #define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1)
 
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL 0x3284
+
+#define S_QCCIND    13
+#define V_QCCIND(x) ((x) << S_QCCIND)
+#define F_QCCIND    V_QCCIND(1U)
+
+#define S_DCDIND    10
+#define M_DCDIND    0x7U
+#define V_DCDIND(x) ((x) << S_DCDIND)
+#define G_DCDIND(x) (((x) >> S_DCDIND) & M_DCDIND)
+
+#define S_DCCIND    8
+#define M_DCCIND    0x3U
+#define V_DCCIND(x) ((x) << S_DCCIND)
+#define G_DCCIND(x) (((x) >> S_DCCIND) & M_DCCIND)
+
+#define S_CFSEL    5
+#define V_CFSEL(x) ((x) << S_CFSEL)
+#define F_CFSEL    V_CFSEL(1U)
+
+#define S_LOFCH    0
+#define M_LOFCH    0x1fU
+#define V_LOFCH(x) ((x) << S_LOFCH)
+#define G_LOFCH(x) (((x) >> S_LOFCH) & M_LOFCH)
+
 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288
 
 #define S_LOFO2S_READWRITE    15
@@ -37358,6 +53394,18 @@
 #define V_LOFO1(x) ((x) << S_LOFO1)
 #define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1)
 
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE 0x3288
+
+#define S_LOFU    8
+#define M_LOFU    0x7fU
+#define V_LOFU(x) ((x) << S_LOFU)
+#define G_LOFU(x) (((x) >> S_LOFU) & M_LOFU)
+
+#define S_LOFL    0
+#define M_LOFL    0x7fU
+#define V_LOFL(x) ((x) << S_LOFL)
+#define G_LOFL(x) (((x) >> S_LOFL) & M_LOFL)
+
 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c
 
 #define S_LOFE4S_READWRITE    15
@@ -37386,6 +53434,42 @@
 #define V_LOFE3(x) ((x) << S_LOFE3)
 #define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3)
 
+#define A_MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST 0x328c
+
+#define S_HBISTMAN    12
+#define V_HBISTMAN(x) ((x) << S_HBISTMAN)
+#define F_HBISTMAN    V_HBISTMAN(1U)
+
+#define S_HBISTRES    11
+#define V_HBISTRES(x) ((x) << S_HBISTRES)
+#define F_HBISTRES    V_HBISTRES(1U)
+
+#define S_HBISTSP    8
+#define M_HBISTSP    0x7U
+#define V_HBISTSP(x) ((x) << S_HBISTSP)
+#define G_HBISTSP(x) (((x) >> S_HBISTSP) & M_HBISTSP)
+
+#define S_HBISTEN    7
+#define V_HBISTEN(x) ((x) << S_HBISTEN)
+#define F_HBISTEN    V_HBISTEN(1U)
+
+#define S_HBISTRST    6
+#define V_HBISTRST(x) ((x) << S_HBISTRST)
+#define F_HBISTRST    V_HBISTRST(1U)
+
+#define S_HCOMP    5
+#define V_HCOMP(x) ((x) << S_HCOMP)
+#define F_HCOMP    V_HCOMP(1U)
+
+#define S_HPASS    4
+#define V_HPASS(x) ((x) << S_HPASS)
+#define F_HPASS    V_HPASS(1U)
+
+#define S_HSEL    0
+#define M_HSEL    0xfU
+#define V_HSEL(x) ((x) << S_HSEL)
+#define G_HSEL(x) (((x) >> S_HSEL) & M_HSEL)
+
 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290
 
 #define S_LOFO4S_READWRITE    15
@@ -37414,6 +53498,30 @@
 #define V_LOFO3(x) ((x) << S_LOFO3)
 #define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3)
 
+#define A_MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST 0x3290
+
+#define S_RX_LINKA_ACCCMP_BIST    13
+#define V_RX_LINKA_ACCCMP_BIST(x) ((x) << S_RX_LINKA_ACCCMP_BIST)
+#define F_RX_LINKA_ACCCMP_BIST    V_RX_LINKA_ACCCMP_BIST(1U)
+
+#define S_ACCEN    12
+#define V_ACCEN(x) ((x) << S_ACCEN)
+#define F_ACCEN    V_ACCEN(1U)
+
+#define S_ACCRST    11
+#define V_ACCRST(x) ((x) << S_ACCRST)
+#define F_ACCRST    V_ACCRST(1U)
+
+#define S_ACCIND    8
+#define M_ACCIND    0x7U
+#define V_ACCIND(x) ((x) << S_ACCIND)
+#define G_ACCIND(x) (((x) >> S_ACCIND) & M_ACCIND)
+
+#define S_ACCRD    0
+#define M_ACCRD    0xffU
+#define V_ACCRD(x) ((x) << S_ACCRD)
+#define G_ACCRD(x) (((x) >> S_ACCRD) & M_ACCRD)
+
 #define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294
 
 #define S_T5E1SN_READWRITE    15
@@ -37457,6 +53565,42 @@
 #define V_T5LFSEL(x) ((x) << S_T5LFSEL)
 #define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL)
 
+#define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER 0x3298
+
+#define S_LFREG    15
+#define V_LFREG(x) ((x) << S_LFREG)
+#define F_LFREG    V_LFREG(1U)
+
+#define S_LFRC    14
+#define V_LFRC(x) ((x) << S_LFRC)
+#define F_LFRC    V_LFRC(1U)
+
+#define S_LGIDLE    13
+#define V_LGIDLE(x) ((x) << S_LGIDLE)
+#define F_LGIDLE    V_LGIDLE(1U)
+
+#define S_LFTGT    8
+#define M_LFTGT    0x1fU
+#define V_LFTGT(x) ((x) << S_LFTGT)
+#define G_LFTGT(x) (((x) >> S_LFTGT) & M_LFTGT)
+
+#define S_LGTGT    7
+#define V_LGTGT(x) ((x) << S_LGTGT)
+#define F_LGTGT    V_LGTGT(1U)
+
+#define S_LRDY    6
+#define V_LRDY(x) ((x) << S_LRDY)
+#define F_LRDY    V_LRDY(1U)
+
+#define S_LIDLE    5
+#define V_LIDLE(x) ((x) << S_LIDLE)
+#define F_LIDLE    V_LIDLE(1U)
+
+#define S_LCURR    0
+#define M_LCURR    0x1fU
+#define V_LCURR(x) ((x) << S_LCURR)
+#define G_LCURR(x) (((x) >> S_LCURR) & M_LCURR)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c
 
 #define S_OFFSN_READWRITE    14
@@ -37476,6 +53620,11 @@
 #define V_SDACDC(x) ((x) << S_SDACDC)
 #define F_SDACDC    V_SDACDC(1U)
 
+#define S_OFFSN    13
+#define M_OFFSN    0x3U
+#define V_OFFSN(x) ((x) << S_OFFSN)
+#define G_OFFSN(x) (((x) >> S_OFFSN) & M_OFFSN)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0
 
 #define S_T5_RX_SETHDIS    7
@@ -37507,6 +53656,43 @@
 #define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM)
 #define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM)
 
+#define S_RX_OVRSUMPD    15
+#define V_RX_OVRSUMPD(x) ((x) << S_RX_OVRSUMPD)
+#define F_RX_OVRSUMPD    V_RX_OVRSUMPD(1U)
+
+#define S_RX_OVRKBPD    14
+#define V_RX_OVRKBPD(x) ((x) << S_RX_OVRKBPD)
+#define F_RX_OVRKBPD    V_RX_OVRKBPD(1U)
+
+#define S_RX_OVRDIVPD    13
+#define V_RX_OVRDIVPD(x) ((x) << S_RX_OVRDIVPD)
+#define F_RX_OVRDIVPD    V_RX_OVRDIVPD(1U)
+
+#define S_RX_OFFVGADIS    12
+#define V_RX_OFFVGADIS(x) ((x) << S_RX_OFFVGADIS)
+#define F_RX_OFFVGADIS    V_RX_OFFVGADIS(1U)
+
+#define S_RX_OFFACDIS    11
+#define V_RX_OFFACDIS(x) ((x) << S_RX_OFFACDIS)
+#define F_RX_OFFACDIS    V_RX_OFFACDIS(1U)
+
+#define S_RX_VTERM    10
+#define V_RX_VTERM(x) ((x) << S_RX_VTERM)
+#define F_RX_VTERM    V_RX_VTERM(1U)
+
+#define S_RX_DISSPY2D    8
+#define V_RX_DISSPY2D(x) ((x) << S_RX_DISSPY2D)
+#define F_RX_DISSPY2D    V_RX_DISSPY2D(1U)
+
+#define S_RX_OBSOVEN    7
+#define V_RX_OBSOVEN(x) ((x) << S_RX_OBSOVEN)
+#define F_RX_OBSOVEN    V_RX_OBSOVEN(1U)
+
+#define S_RX_LINKANLGSW    0
+#define M_RX_LINKANLGSW    0x7fU
+#define V_RX_LINKANLGSW(x) ((x) << S_RX_LINKANLGSW)
+#define G_RX_LINKANLGSW(x) (((x) >> S_RX_LINKANLGSW) & M_RX_LINKANLGSW)
+
 #define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4
 
 #define S_ISTRIMS    14
@@ -37532,6 +53718,21 @@
 #define V_INTDAC(x) ((x) << S_INTDAC)
 #define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC)
 
+#define S_INTDACEGS    13
+#define M_INTDACEGS    0x7U
+#define V_INTDACEGS(x) ((x) << S_INTDACEGS)
+#define G_INTDACEGS(x) (((x) >> S_INTDACEGS) & M_INTDACEGS)
+
+#define S_INTDACE    8
+#define M_INTDACE    0x1fU
+#define V_INTDACE(x) ((x) << S_INTDACE)
+#define G_INTDACE(x) (((x) >> S_INTDACE) & M_INTDACE)
+
+#define S_INTDACGS    6
+#define M_INTDACGS    0x3U
+#define V_INTDACGS(x) ((x) << S_INTDACGS)
+#define G_INTDACGS(x) (((x) >> S_INTDACGS) & M_INTDACGS)
+
 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8
 
 #define S_MINWDTH    5
@@ -37568,6 +53769,29 @@
 #define V_T5EMEN(x) ((x) << S_T5EMEN)
 #define F_T5EMEN    V_T5EMEN(1U)
 
+#define S_SMQM    13
+#define M_SMQM    0x7U
+#define V_SMQM(x) ((x) << S_SMQM)
+#define G_SMQM(x) (((x) >> S_SMQM) & M_SMQM)
+
+#define S_SMQ    5
+#define M_SMQ    0xffU
+#define V_SMQ(x) ((x) << S_SMQ)
+#define G_SMQ(x) (((x) >> S_SMQ) & M_SMQ)
+
+#define S_T6_EMMD    3
+#define M_T6_EMMD    0x3U
+#define V_T6_EMMD(x) ((x) << S_T6_EMMD)
+#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
+
+#define S_T6_EMBRDY    2
+#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
+#define F_T6_EMBRDY    V_T6_EMBRDY(1U)
+
+#define S_T6_EMBUMP    1
+#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
+#define F_T6_EMBUMP    V_T6_EMBUMP(1U)
+
 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0
 
 #define S_EMF8    15
@@ -37591,6 +53815,14 @@
 #define V_EMCEN(x) ((x) << S_EMCEN)
 #define F_EMCEN    V_EMCEN(1U)
 
+#define S_EMSF    13
+#define V_EMSF(x) ((x) << S_EMSF)
+#define F_EMSF    V_EMSF(1U)
+
+#define S_EMDATA59    12
+#define V_EMDATA59(x) ((x) << S_EMDATA59)
+#define F_EMDATA59    V_EMDATA59(1U)
+
 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4
 
 #define S_SM2RDY    15
@@ -37613,6 +53845,72 @@
 #define V_SM0LEN(x) ((x) << S_SM0LEN)
 #define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN)
 
+#define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3 0x32bc
+
+#define S_FTIMEOUT    15
+#define V_FTIMEOUT(x) ((x) << S_FTIMEOUT)
+#define F_FTIMEOUT    V_FTIMEOUT(1U)
+
+#define S_FROTCAL4    14
+#define V_FROTCAL4(x) ((x) << S_FROTCAL4)
+#define F_FROTCAL4    V_FROTCAL4(1U)
+
+#define S_FDCD2    13
+#define V_FDCD2(x) ((x) << S_FDCD2)
+#define F_FDCD2    V_FDCD2(1U)
+
+#define S_FPRBSPOLTOG    12
+#define V_FPRBSPOLTOG(x) ((x) << S_FPRBSPOLTOG)
+#define F_FPRBSPOLTOG    V_FPRBSPOLTOG(1U)
+
+#define S_FPRBSOFF2    11
+#define V_FPRBSOFF2(x) ((x) << S_FPRBSOFF2)
+#define F_FPRBSOFF2    V_FPRBSOFF2(1U)
+
+#define S_FDDCAL2    10
+#define V_FDDCAL2(x) ((x) << S_FDDCAL2)
+#define F_FDDCAL2    V_FDDCAL2(1U)
+
+#define S_FDDCFLTR    9
+#define V_FDDCFLTR(x) ((x) << S_FDDCFLTR)
+#define F_FDDCFLTR    V_FDDCFLTR(1U)
+
+#define S_FDAC6    8
+#define V_FDAC6(x) ((x) << S_FDAC6)
+#define F_FDAC6    V_FDAC6(1U)
+
+#define S_FDDC5    7
+#define V_FDDC5(x) ((x) << S_FDDC5)
+#define F_FDDC5    V_FDDC5(1U)
+
+#define S_FDDC3456    6
+#define V_FDDC3456(x) ((x) << S_FDDC3456)
+#define F_FDDC3456    V_FDDC3456(1U)
+
+#define S_FSPY2DATA    5
+#define V_FSPY2DATA(x) ((x) << S_FSPY2DATA)
+#define F_FSPY2DATA    V_FSPY2DATA(1U)
+
+#define S_FPHSLOCK    4
+#define V_FPHSLOCK(x) ((x) << S_FPHSLOCK)
+#define F_FPHSLOCK    V_FPHSLOCK(1U)
+
+#define S_FCLKALGN    3
+#define V_FCLKALGN(x) ((x) << S_FCLKALGN)
+#define F_FCLKALGN    V_FCLKALGN(1U)
+
+#define S_FCLKALDYN    2
+#define V_FCLKALDYN(x) ((x) << S_FCLKALDYN)
+#define F_FCLKALDYN    V_FCLKALDYN(1U)
+
+#define S_FDFE    1
+#define V_FDFE(x) ((x) << S_FDFE)
+#define F_FDFE    V_FDFE(1U)
+
+#define S_FPRBSOFF    0
+#define V_FPRBSOFF(x) ((x) << S_FPRBSOFF)
+#define F_FPRBSOFF    V_FPRBSOFF(1U)
+
 #define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0
 
 #define S_H_EN    1
@@ -37620,7 +53918,21 @@
 #define V_H_EN(x) ((x) << S_H_EN)
 #define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN)
 
+#define A_MAC_PORT_RX_LINKA_DFE_TAP_CONTROL 0x32c0
+
+#define S_RX_LINKA_INDEX_DFE_TC    0
+#define M_RX_LINKA_INDEX_DFE_TC    0xfU
+#define V_RX_LINKA_INDEX_DFE_TC(x) ((x) << S_RX_LINKA_INDEX_DFE_TC)
+#define G_RX_LINKA_INDEX_DFE_TC(x) (((x) >> S_RX_LINKA_INDEX_DFE_TC) & M_RX_LINKA_INDEX_DFE_TC)
+
 #define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4
+#define A_MAC_PORT_RX_LINKA_DFE_TAP 0x32c4
+
+#define S_RX_LINKA_INDEX_DFE_TAP    0
+#define M_RX_LINKA_INDEX_DFE_TAP    0xfU
+#define V_RX_LINKA_INDEX_DFE_TAP(x) ((x) << S_RX_LINKA_INDEX_DFE_TAP)
+#define G_RX_LINKA_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKA_INDEX_DFE_TAP) & M_RX_LINKA_INDEX_DFE_TAP)
+
 #define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8
 
 #define S_H2OSN_READWRITE    14
@@ -37847,6 +54159,154 @@
 #define V_H12MAG(x) ((x) << S_H12MAG)
 #define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG)
 
+#define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2 0x32e4
+
+#define S_STNDBYSTAT    15
+#define V_STNDBYSTAT(x) ((x) << S_STNDBYSTAT)
+#define F_STNDBYSTAT    V_STNDBYSTAT(1U)
+
+#define S_CALSDONE    14
+#define V_CALSDONE(x) ((x) << S_CALSDONE)
+#define F_CALSDONE    V_CALSDONE(1U)
+
+#define S_ACISRCCMP    5
+#define V_ACISRCCMP(x) ((x) << S_ACISRCCMP)
+#define F_ACISRCCMP    V_ACISRCCMP(1U)
+
+#define S_PRBSOFFCMP    4
+#define V_PRBSOFFCMP(x) ((x) << S_PRBSOFFCMP)
+#define F_PRBSOFFCMP    V_PRBSOFFCMP(1U)
+
+#define S_CLKALGNCMP    3
+#define V_CLKALGNCMP(x) ((x) << S_CLKALGNCMP)
+#define F_CLKALGNCMP    V_CLKALGNCMP(1U)
+
+#define S_ROTFCMP    2
+#define V_ROTFCMP(x) ((x) << S_ROTFCMP)
+#define F_ROTFCMP    V_ROTFCMP(1U)
+
+#define S_DCDCMP    1
+#define V_DCDCMP(x) ((x) << S_DCDCMP)
+#define F_DCDCMP    V_DCDCMP(1U)
+
+#define S_QCCCMP    0
+#define V_QCCCMP(x) ((x) << S_QCCCMP)
+#define F_QCCCMP    V_QCCCMP(1U)
+
+#define A_MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x32e8
+
+#define S_FCSADJ    6
+#define V_FCSADJ(x) ((x) << S_FCSADJ)
+#define F_FCSADJ    V_FCSADJ(1U)
+
+#define S_CSIND    3
+#define M_CSIND    0x3U
+#define V_CSIND(x) ((x) << S_CSIND)
+#define G_CSIND(x) (((x) >> S_CSIND) & M_CSIND)
+
+#define S_CSVAL    0
+#define M_CSVAL    0x7U
+#define V_CSVAL(x) ((x) << S_CSVAL)
+#define G_CSVAL(x) (((x) >> S_CSVAL) & M_CSVAL)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL 0x32ec
+
+#define S_DCDTMDOUT    15
+#define V_DCDTMDOUT(x) ((x) << S_DCDTMDOUT)
+#define F_DCDTMDOUT    V_DCDTMDOUT(1U)
+
+#define S_DCDTOEN    14
+#define V_DCDTOEN(x) ((x) << S_DCDTOEN)
+#define F_DCDTOEN    V_DCDTOEN(1U)
+
+#define S_DCDLOCK    13
+#define V_DCDLOCK(x) ((x) << S_DCDLOCK)
+#define F_DCDLOCK    V_DCDLOCK(1U)
+
+#define S_DCDSTEP    11
+#define M_DCDSTEP    0x3U
+#define V_DCDSTEP(x) ((x) << S_DCDSTEP)
+#define G_DCDSTEP(x) (((x) >> S_DCDSTEP) & M_DCDSTEP)
+
+#define S_DCDALTWPDIS    10
+#define V_DCDALTWPDIS(x) ((x) << S_DCDALTWPDIS)
+#define F_DCDALTWPDIS    V_DCDALTWPDIS(1U)
+
+#define S_DCDOVRDEN    9
+#define V_DCDOVRDEN(x) ((x) << S_DCDOVRDEN)
+#define F_DCDOVRDEN    V_DCDOVRDEN(1U)
+
+#define S_DCCAOVRDEN    8
+#define V_DCCAOVRDEN(x) ((x) << S_DCCAOVRDEN)
+#define F_DCCAOVRDEN    V_DCCAOVRDEN(1U)
+
+#define S_DCDSIGN    6
+#define M_DCDSIGN    0x3U
+#define V_DCDSIGN(x) ((x) << S_DCDSIGN)
+#define G_DCDSIGN(x) (((x) >> S_DCDSIGN) & M_DCDSIGN)
+
+#define S_DCDAMP    0
+#define M_DCDAMP    0x3fU
+#define V_DCDAMP(x) ((x) << S_DCDAMP)
+#define G_DCDAMP(x) (((x) >> S_DCDAMP) & M_DCDAMP)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL 0x32f0
+
+#define S_PRBSMODE    14
+#define M_PRBSMODE    0x3U
+#define V_PRBSMODE(x) ((x) << S_PRBSMODE)
+#define G_PRBSMODE(x) (((x) >> S_PRBSMODE) & M_PRBSMODE)
+
+#define S_RX_LINKA_DCCSTEP_RXCTL    10
+#define M_RX_LINKA_DCCSTEP_RXCTL    0x3U
+#define V_RX_LINKA_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKA_DCCSTEP_RXCTL)
+#define G_RX_LINKA_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKA_DCCSTEP_RXCTL) & M_RX_LINKA_DCCSTEP_RXCTL)
+
+#define S_DCCOVRDEN    9
+#define V_DCCOVRDEN(x) ((x) << S_DCCOVRDEN)
+#define F_DCCOVRDEN    V_DCCOVRDEN(1U)
+
+#define S_RX_LINKA_DCCLOCK_RXCTL    8
+#define V_RX_LINKA_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKA_DCCLOCK_RXCTL)
+#define F_RX_LINKA_DCCLOCK_RXCTL    V_RX_LINKA_DCCLOCK_RXCTL(1U)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL 0x32f4
+
+#define S_DCCQCCMODE    15
+#define V_DCCQCCMODE(x) ((x) << S_DCCQCCMODE)
+#define F_DCCQCCMODE    V_DCCQCCMODE(1U)
+
+#define S_DCCQCCDYN    14
+#define V_DCCQCCDYN(x) ((x) << S_DCCQCCDYN)
+#define F_DCCQCCDYN    V_DCCQCCDYN(1U)
+
+#define S_DCCQCCHOLD    13
+#define V_DCCQCCHOLD(x) ((x) << S_DCCQCCHOLD)
+#define F_DCCQCCHOLD    V_DCCQCCHOLD(1U)
+
+#define S_QCCSTEP    10
+#define M_QCCSTEP    0x3U
+#define V_QCCSTEP(x) ((x) << S_QCCSTEP)
+#define G_QCCSTEP(x) (((x) >> S_QCCSTEP) & M_QCCSTEP)
+
+#define S_QCCOVRDEN    9
+#define V_QCCOVRDEN(x) ((x) << S_QCCOVRDEN)
+#define F_QCCOVRDEN    V_QCCOVRDEN(1U)
+
+#define S_QCCLOCK    8
+#define V_QCCLOCK(x) ((x) << S_QCCLOCK)
+#define F_QCCLOCK    V_QCCLOCK(1U)
+
+#define S_QCCSIGN    6
+#define M_QCCSIGN    0x3U
+#define V_QCCSIGN(x) ((x) << S_QCCSIGN)
+#define G_QCCSIGN(x) (((x) >> S_QCCSIGN) & M_QCCSIGN)
+
+#define S_QCDAMP    0
+#define M_QCDAMP    0x3fU
+#define V_QCDAMP(x) ((x) << S_QCDAMP)
+#define G_QCDAMP(x) (((x) >> S_QCDAMP) & M_QCDAMP)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8
 
 #define S_DFEDACLSSD    6
@@ -37877,6 +54337,12 @@
 #define V_ACJZNT(x) ((x) << S_ACJZNT)
 #define F_ACJZNT    V_ACJZNT(1U)
 
+#define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x32f8
+
+#define S_TSTCMP    15
+#define V_TSTCMP(x) ((x) << S_TSTCMP)
+#define F_TSTCMP    V_TSTCMP(1U)
+
 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc
 
 #define S_PHSLOCK    10
@@ -37923,49 +54389,168 @@
 #define V_MTHOLD(x) ((x) << S_MTHOLD)
 #define F_MTHOLD    V_MTHOLD(1U)
 
+#define S_CALMODEEDGE    14
+#define V_CALMODEEDGE(x) ((x) << S_CALMODEEDGE)
+#define F_CALMODEEDGE    V_CALMODEEDGE(1U)
+
+#define S_TESTCAP    13
+#define V_TESTCAP(x) ((x) << S_TESTCAP)
+#define F_TESTCAP    V_TESTCAP(1U)
+
+#define S_SNAPEN    12
+#define V_SNAPEN(x) ((x) << S_SNAPEN)
+#define F_SNAPEN    V_SNAPEN(1U)
+
+#define S_ASYNCDIR    11
+#define V_ASYNCDIR(x) ((x) << S_ASYNCDIR)
+#define F_ASYNCDIR    V_ASYNCDIR(1U)
+
 #define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300
 #define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
+
+#define S_T6_TMSCAL    8
+#define M_T6_TMSCAL    0x3U
+#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
+#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
+
+#define S_T6_APADJ    7
+#define V_T6_APADJ(x) ((x) << S_T6_APADJ)
+#define F_T6_APADJ    V_T6_APADJ(1U)
+
+#define S_T6_RSEL    6
+#define V_T6_RSEL(x) ((x) << S_T6_RSEL)
+#define F_T6_RSEL    V_T6_RSEL(1U)
+
+#define S_T6_PHOFFS    0
+#define M_T6_PHOFFS    0x3fU
+#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
+#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
+
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
 #define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
+
+#define S_T6_SPIFMT    8
+#define M_T6_SPIFMT    0xfU
+#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
+#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
+
 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
+
+#define S_T6_WRAPSEL    15
+#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
+#define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
+
+#define S_T6_PEAK    9
+#define M_T6_PEAK    0x1fU
+#define V_T6_PEAK(x) ((x) << S_T6_PEAK)
+#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
+
 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
+
+#define S_T6_T5VGAIN    0
+#define M_T6_T5VGAIN    0x7fU
+#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
+#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
+
 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
+#define A_MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3338
+#define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1 0x333c
 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340
+#define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2 0x3340
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3344
 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348
 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN 0x334c
 #define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350
+#define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL 0x3354
+#define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE 0x3358
 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c
+#define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET 0x335c
 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360
+#define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3360
 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364
+#define A_MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR 0x3364
+#define A_MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH 0x3368
+#define A_MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x336c
 #define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
 #define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
+
+#define S_T6_ODEC    0
+#define M_T6_ODEC    0xfU
+#define V_T6_ODEC(x) ((x) << S_T6_ODEC)
+#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
+
 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
+
+#define S_RX_LINKB_ACCCMP_RIS    11
+#define V_RX_LINKB_ACCCMP_RIS(x) ((x) << S_RX_LINKB_ACCCMP_RIS)
+#define F_RX_LINKB_ACCCMP_RIS    V_RX_LINKB_ACCCMP_RIS(1U)
+
 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c
 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380
 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL 0x3384
 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE 0x3388
 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c
+#define A_MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST 0x338c
 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390
+#define A_MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST 0x3390
+
+#define S_RX_LINKB_ACCCMP_BIST    13
+#define V_RX_LINKB_ACCCMP_BIST(x) ((x) << S_RX_LINKB_ACCCMP_BIST)
+#define F_RX_LINKB_ACCCMP_BIST    V_RX_LINKB_ACCCMP_BIST(1U)
+
 #define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394
 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398
+#define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER 0x3398
 #define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c
 #define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0
 #define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
+
+#define S_T6_EMMD    3
+#define M_T6_EMMD    0x3U
+#define V_T6_EMMD(x) ((x) << S_T6_EMMD)
+#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
+
+#define S_T6_EMBRDY    2
+#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
+#define F_T6_EMBRDY    V_T6_EMBRDY(1U)
+
+#define S_T6_EMBUMP    1
+#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
+#define F_T6_EMBUMP    V_T6_EMBUMP(1U)
+
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
+#define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3 0x33bc
 #define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0
+#define A_MAC_PORT_RX_LINKB_DFE_TAP_CONTROL 0x33c0
+
+#define S_RX_LINKB_INDEX_DFE_TC    0
+#define M_RX_LINKB_INDEX_DFE_TC    0xfU
+#define V_RX_LINKB_INDEX_DFE_TC(x) ((x) << S_RX_LINKB_INDEX_DFE_TC)
+#define G_RX_LINKB_INDEX_DFE_TC(x) (((x) >> S_RX_LINKB_INDEX_DFE_TC) & M_RX_LINKB_INDEX_DFE_TC)
+
 #define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4
+#define A_MAC_PORT_RX_LINKB_DFE_TAP 0x33c4
+
+#define S_RX_LINKB_INDEX_DFE_TAP    0
+#define M_RX_LINKB_INDEX_DFE_TAP    0xfU
+#define V_RX_LINKB_INDEX_DFE_TAP(x) ((x) << S_RX_LINKB_INDEX_DFE_TAP)
+#define G_RX_LINKB_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKB_INDEX_DFE_TAP) & M_RX_LINKB_INDEX_DFE_TAP)
+
 #define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8
 #define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc
 #define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0
@@ -37974,125 +54559,538 @@
 #define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc
 #define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0
 #define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4
+#define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2 0x33e4
+#define A_MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x33e8
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL 0x33ec
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL 0x33f0
+
+#define S_RX_LINKB_DCCSTEP_RXCTL    10
+#define M_RX_LINKB_DCCSTEP_RXCTL    0x3U
+#define V_RX_LINKB_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKB_DCCSTEP_RXCTL)
+#define G_RX_LINKB_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKB_DCCSTEP_RXCTL) & M_RX_LINKB_DCCSTEP_RXCTL)
+
+#define S_RX_LINKB_DCCLOCK_RXCTL    8
+#define V_RX_LINKB_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKB_DCCLOCK_RXCTL)
+#define F_RX_LINKB_DCCLOCK_RXCTL    V_RX_LINKB_DCCLOCK_RXCTL(1U)
+
+#define A_MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL 0x33f4
 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8
+#define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x33f8
 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
+
+#define S_T6_T5_TX_RXLOOP    5
+#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
+#define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
+
+#define S_T6_T5_TX_BWSEL    2
+#define M_T6_T5_TX_BWSEL    0x3U
+#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
+#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
+
+#define S_T6_ERROR    9
+#define V_T6_ERROR(x) ((x) << S_T6_ERROR)
+#define F_T6_ERROR    V_T6_ERROR(1U)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
+
+#define S_T6_CALSSTN    8
+#define M_T6_CALSSTN    0x3fU
+#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
+#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
+
+#define S_T6_CALSSTP    0
+#define M_T6_CALSSTP    0x3fU
+#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
+#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
+
+#define S_T6_DRTOL    2
+#define M_T6_DRTOL    0x7U
+#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
+#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
+
+#define S_T6_NXTT0    0
+#define M_T6_NXTT0    0x3fU
+#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
+#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
+
+#define S_T6_NXTT2    0
+#define M_T6_NXTT2    0x3fU
+#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
+#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
+
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT 0x342c
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
+
+#define S_T6_NXTPOL    0
+#define M_T6_NXTPOL    0xfU
+#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
+#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
+
+#define S_T6_C0UPDT    6
+#define M_T6_C0UPDT    0x3U
+#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
+#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
+
+#define S_T6_C2UPDT    2
+#define M_T6_C2UPDT    0x3U
+#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
+#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
+
+#define S_T6_C1UPDT    0
+#define M_T6_C1UPDT    0x3U
+#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
+#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
+
+#define S_T6_C0STAT    6
+#define M_T6_C0STAT    0x3U
+#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
+#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
+
+#define S_T6_C2STAT    2
+#define M_T6_C2STAT    0x3U
+#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
+#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
+
+#define S_T6_C1STAT    0
+#define M_T6_C1STAT    0x3U
+#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
+#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3440
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3444
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3448
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x344c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER 0x3450
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3458
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED 0x3460
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED 0x3464
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED 0x3468
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x346c
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3470
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3474
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
+
+#define S_T6_XADDR    1
+#define M_T6_XADDR    0x1fU
+#define V_T6_XADDR(x) ((x) << S_T6_XADDR)
+#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3488
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x348c
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
+#define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x34a0
+
+#define S_T6_DCCTIMEEN    13
+#define M_T6_DCCTIMEEN    0x3U
+#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
+#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
+
+#define S_T6_DCCLOCK    11
+#define M_T6_DCCLOCK    0x3U
+#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
+#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
+
+#define S_T6_DCCOFFSET    8
+#define M_T6_DCCOFFSET    0x7U
+#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
+#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
+
+#define S_TX_LINKC_DCCSTEP_CTL    6
+#define M_TX_LINKC_DCCSTEP_CTL    0x3U
+#define V_TX_LINKC_DCCSTEP_CTL(x) ((x) << S_TX_LINKC_DCCSTEP_CTL)
+#define G_TX_LINKC_DCCSTEP_CTL(x) (((x) >> S_TX_LINKC_DCCSTEP_CTL) & M_TX_LINKC_DCCSTEP_CTL)
+
+#define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x34a4
+#define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x34a8
+#define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x34ac
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE 0x34c0
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE 0x34c8
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE 0x34cc
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE 0x34d0
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x34d8
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x34dc
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x34e0
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5 0x34ec
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
+
+#define S_T6_SDOVRD    0
+#define M_T6_SDOVRD    0xffffU
+#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
+#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
+
+#define S_T6_SDOVRDEN    15
+#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
+#define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
+
+#define S_T6_T5_TX_RXLOOP    5
+#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
+#define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
+
+#define S_T6_T5_TX_BWSEL    2
+#define M_T6_T5_TX_BWSEL    0x3U
+#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
+#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
+
+#define S_T6_ERROR    9
+#define V_T6_ERROR(x) ((x) << S_T6_ERROR)
+#define F_T6_ERROR    V_T6_ERROR(1U)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
+
+#define S_T6_CALSSTN    8
+#define M_T6_CALSSTN    0x3fU
+#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
+#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
+
+#define S_T6_CALSSTP    0
+#define M_T6_CALSSTP    0x3fU
+#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
+#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
+
+#define S_T6_DRTOL    2
+#define M_T6_DRTOL    0x7U
+#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
+#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
+
+#define S_T6_NXTT0    0
+#define M_T6_NXTT0    0x3fU
+#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
+#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
+
+#define S_T6_NXTT2    0
+#define M_T6_NXTT2    0x3fU
+#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
+#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
+
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT 0x352c
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
+
+#define S_T6_NXTPOL    0
+#define M_T6_NXTPOL    0xfU
+#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
+#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
+
+#define S_T6_C0UPDT    6
+#define M_T6_C0UPDT    0x3U
+#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
+#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
+
+#define S_T6_C2UPDT    2
+#define M_T6_C2UPDT    0x3U
+#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
+#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
+
+#define S_T6_C1UPDT    0
+#define M_T6_C1UPDT    0x3U
+#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
+#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
+
+#define S_T6_C0STAT    6
+#define M_T6_C0STAT    0x3U
+#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
+#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
+
+#define S_T6_C2STAT    2
+#define M_T6_C2STAT    0x3U
+#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
+#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
+
+#define S_T6_C1STAT    0
+#define M_T6_C1STAT    0x3U
+#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
+#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3540
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3544
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3548
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x354c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER 0x3550
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3558
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED 0x3560
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED 0x3564
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED 0x3568
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x356c
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3570
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3574
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
+
+#define S_T6_XADDR    1
+#define M_T6_XADDR    0x1fU
+#define V_T6_XADDR(x) ((x) << S_T6_XADDR)
+#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3588
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x358c
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
+#define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x35a0
+
+#define S_T6_DCCTIMEEN    13
+#define M_T6_DCCTIMEEN    0x3U
+#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
+#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
+
+#define S_T6_DCCLOCK    11
+#define M_T6_DCCLOCK    0x3U
+#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
+#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
+
+#define S_T6_DCCOFFSET    8
+#define M_T6_DCCOFFSET    0x7U
+#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
+#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
+
+#define S_TX_LINKD_DCCSTEP_CTL    6
+#define M_TX_LINKD_DCCSTEP_CTL    0x3U
+#define V_TX_LINKD_DCCSTEP_CTL(x) ((x) << S_TX_LINKD_DCCSTEP_CTL)
+#define G_TX_LINKD_DCCSTEP_CTL(x) (((x) >> S_TX_LINKD_DCCSTEP_CTL) & M_TX_LINKD_DCCSTEP_CTL)
+
+#define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x35a4
+#define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x35a8
+#define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x35ac
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE 0x35c0
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE 0x35c8
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE 0x35cc
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE 0x35d0
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x35d8
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x35dc
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x35e0
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5 0x35ec
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
+
+#define S_T6_SDOVRD    0
+#define M_T6_SDOVRD    0xffffU
+#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
+#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
+
+#define S_T6_SDOVRDEN    15
+#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
+#define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
+
 #define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
 #define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
+
+#define S_T6_TMSCAL    8
+#define M_T6_TMSCAL    0x3U
+#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
+#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
+
+#define S_T6_APADJ    7
+#define V_T6_APADJ(x) ((x) << S_T6_APADJ)
+#define F_T6_APADJ    V_T6_APADJ(1U)
+
+#define S_T6_RSEL    6
+#define V_T6_RSEL(x) ((x) << S_T6_RSEL)
+#define F_T6_RSEL    V_T6_RSEL(1U)
+
+#define S_T6_PHOFFS    0
+#define M_T6_PHOFFS    0x3fU
+#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
+#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
+
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
 #define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
+
+#define S_T6_SPIFMT    8
+#define M_T6_SPIFMT    0xfU
+#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
+#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
+
 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
+
+#define S_T6_WRAPSEL    15
+#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
+#define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
+
+#define S_T6_PEAK    9
+#define M_T6_PEAK    0x1fU
+#define V_T6_PEAK(x) ((x) << S_T6_PEAK)
+#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
+
 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
+
+#define S_T6_T5VGAIN    0
+#define M_T6_T5VGAIN    0x7fU
+#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
+#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
+
 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
+#define A_MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3638
+#define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1 0x363c
 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640
+#define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2 0x3640
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3644
 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648
 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN 0x364c
 #define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650
+#define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL 0x3654
+#define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE 0x3658
 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c
+#define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET 0x365c
 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660
+#define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3660
 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664
+#define A_MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR 0x3664
+#define A_MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH 0x3668
+#define A_MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x366c
 #define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
 #define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
+
+#define S_T6_ODEC    0
+#define M_T6_ODEC    0xfU
+#define V_T6_ODEC(x) ((x) << S_T6_ODEC)
+#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
+
 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
+
+#define S_RX_LINKC_ACCCMP_RIS    11
+#define V_RX_LINKC_ACCCMP_RIS(x) ((x) << S_RX_LINKC_ACCCMP_RIS)
+#define F_RX_LINKC_ACCCMP_RIS    V_RX_LINKC_ACCCMP_RIS(1U)
+
 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c
 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680
 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL 0x3684
 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE 0x3688
 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c
+#define A_MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST 0x368c
 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690
+#define A_MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST 0x3690
+
+#define S_RX_LINKC_ACCCMP_BIST    13
+#define V_RX_LINKC_ACCCMP_BIST(x) ((x) << S_RX_LINKC_ACCCMP_BIST)
+#define F_RX_LINKC_ACCCMP_BIST    V_RX_LINKC_ACCCMP_BIST(1U)
+
 #define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694
 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698
+#define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER 0x3698
 #define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c
 #define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0
 #define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
+
+#define S_T6_EMMD    3
+#define M_T6_EMMD    0x3U
+#define V_T6_EMMD(x) ((x) << S_T6_EMMD)
+#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
+
+#define S_T6_EMBRDY    2
+#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
+#define F_T6_EMBRDY    V_T6_EMBRDY(1U)
+
+#define S_T6_EMBUMP    1
+#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
+#define F_T6_EMBUMP    V_T6_EMBUMP(1U)
+
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
+#define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3 0x36bc
 #define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0
+#define A_MAC_PORT_RX_LINKC_DFE_TAP_CONTROL 0x36c0
+
+#define S_RX_LINKC_INDEX_DFE_TC    0
+#define M_RX_LINKC_INDEX_DFE_TC    0xfU
+#define V_RX_LINKC_INDEX_DFE_TC(x) ((x) << S_RX_LINKC_INDEX_DFE_TC)
+#define G_RX_LINKC_INDEX_DFE_TC(x) (((x) >> S_RX_LINKC_INDEX_DFE_TC) & M_RX_LINKC_INDEX_DFE_TC)
+
 #define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4
+#define A_MAC_PORT_RX_LINKC_DFE_TAP 0x36c4
+
+#define S_RX_LINKC_INDEX_DFE_TAP    0
+#define M_RX_LINKC_INDEX_DFE_TAP    0xfU
+#define V_RX_LINKC_INDEX_DFE_TAP(x) ((x) << S_RX_LINKC_INDEX_DFE_TAP)
+#define G_RX_LINKC_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKC_INDEX_DFE_TAP) & M_RX_LINKC_INDEX_DFE_TAP)
+
 #define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8
 #define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc
 #define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0
@@ -38101,51 +55099,170 @@
 #define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc
 #define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0
 #define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4
+#define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2 0x36e4
+#define A_MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x36e8
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL 0x36ec
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL 0x36f0
+
+#define S_RX_LINKC_DCCSTEP_RXCTL    10
+#define M_RX_LINKC_DCCSTEP_RXCTL    0x3U
+#define V_RX_LINKC_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKC_DCCSTEP_RXCTL)
+#define G_RX_LINKC_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKC_DCCSTEP_RXCTL) & M_RX_LINKC_DCCSTEP_RXCTL)
+
+#define S_RX_LINKC_DCCLOCK_RXCTL    8
+#define V_RX_LINKC_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKC_DCCLOCK_RXCTL)
+#define F_RX_LINKC_DCCLOCK_RXCTL    V_RX_LINKC_DCCLOCK_RXCTL(1U)
+
+#define A_MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL 0x36f4
 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8
+#define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x36f8
 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc
 #define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700
 #define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
+
+#define S_T6_TMSCAL    8
+#define M_T6_TMSCAL    0x3U
+#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
+#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
+
+#define S_T6_APADJ    7
+#define V_T6_APADJ(x) ((x) << S_T6_APADJ)
+#define F_T6_APADJ    V_T6_APADJ(1U)
+
+#define S_T6_RSEL    6
+#define V_T6_RSEL(x) ((x) << S_T6_RSEL)
+#define F_T6_RSEL    V_T6_RSEL(1U)
+
+#define S_T6_PHOFFS    0
+#define M_T6_PHOFFS    0x3fU
+#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
+#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
+
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
 #define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
+
+#define S_T6_SPIFMT    8
+#define M_T6_SPIFMT    0xfU
+#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
+#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
+
 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
+
+#define S_T6_WRAPSEL    15
+#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
+#define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
+
+#define S_T6_PEAK    9
+#define M_T6_PEAK    0x1fU
+#define V_T6_PEAK(x) ((x) << S_T6_PEAK)
+#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
+
 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
+
+#define S_T6_T5VGAIN    0
+#define M_T6_T5VGAIN    0x7fU
+#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
+#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
+
 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
+#define A_MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3738
+#define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1 0x373c
 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740
+#define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2 0x3740
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3744
 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748
 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN 0x374c
 #define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750
+#define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL 0x3754
+#define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE 0x3758
 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c
+#define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET 0x375c
 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760
+#define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3760
 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764
+#define A_MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR 0x3764
+#define A_MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH 0x3768
+#define A_MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x376c
 #define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
 #define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
+
+#define S_T6_ODEC    0
+#define M_T6_ODEC    0xfU
+#define V_T6_ODEC(x) ((x) << S_T6_ODEC)
+#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
+
 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
+
+#define S_RX_LINKD_ACCCMP_RIS    11
+#define V_RX_LINKD_ACCCMP_RIS(x) ((x) << S_RX_LINKD_ACCCMP_RIS)
+#define F_RX_LINKD_ACCCMP_RIS    V_RX_LINKD_ACCCMP_RIS(1U)
+
 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c
 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780
 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL 0x3784
 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE 0x3788
 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c
+#define A_MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST 0x378c
 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790
+#define A_MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST 0x3790
+
+#define S_RX_LINKD_ACCCMP_BIST    13
+#define V_RX_LINKD_ACCCMP_BIST(x) ((x) << S_RX_LINKD_ACCCMP_BIST)
+#define F_RX_LINKD_ACCCMP_BIST    V_RX_LINKD_ACCCMP_BIST(1U)
+
 #define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794
 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798
+#define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER 0x3798
 #define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c
 #define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0
 #define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
+
+#define S_T6_EMMD    3
+#define M_T6_EMMD    0x3U
+#define V_T6_EMMD(x) ((x) << S_T6_EMMD)
+#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
+
+#define S_T6_EMBRDY    2
+#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
+#define F_T6_EMBRDY    V_T6_EMBRDY(1U)
+
+#define S_T6_EMBUMP    1
+#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
+#define F_T6_EMBUMP    V_T6_EMBUMP(1U)
+
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
+#define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3 0x37bc
 #define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0
+#define A_MAC_PORT_RX_LINKD_DFE_TAP_CONTROL 0x37c0
+
+#define S_RX_LINKD_INDEX_DFE_TC    0
+#define M_RX_LINKD_INDEX_DFE_TC    0xfU
+#define V_RX_LINKD_INDEX_DFE_TC(x) ((x) << S_RX_LINKD_INDEX_DFE_TC)
+#define G_RX_LINKD_INDEX_DFE_TC(x) (((x) >> S_RX_LINKD_INDEX_DFE_TC) & M_RX_LINKD_INDEX_DFE_TC)
+
 #define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4
+#define A_MAC_PORT_RX_LINKD_DFE_TAP 0x37c4
+
+#define S_RX_LINKD_INDEX_DFE_TAP    0
+#define M_RX_LINKD_INDEX_DFE_TAP    0xfU
+#define V_RX_LINKD_INDEX_DFE_TAP(x) ((x) << S_RX_LINKD_INDEX_DFE_TAP)
+#define G_RX_LINKD_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKD_INDEX_DFE_TAP) & M_RX_LINKD_INDEX_DFE_TAP)
+
 #define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8
 #define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc
 #define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0
@@ -38154,7 +55271,23 @@
 #define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc
 #define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0
 #define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4
+#define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2 0x37e4
+#define A_MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x37e8
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL 0x37ec
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL 0x37f0
+
+#define S_RX_LINKD_DCCSTEP_RXCTL    10
+#define M_RX_LINKD_DCCSTEP_RXCTL    0x3U
+#define V_RX_LINKD_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKD_DCCSTEP_RXCTL)
+#define G_RX_LINKD_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKD_DCCSTEP_RXCTL) & M_RX_LINKD_DCCSTEP_RXCTL)
+
+#define S_RX_LINKD_DCCLOCK_RXCTL    8
+#define V_RX_LINKD_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKD_DCCLOCK_RXCTL)
+#define F_RX_LINKD_DCCLOCK_RXCTL    V_RX_LINKD_DCCLOCK_RXCTL(1U)
+
+#define A_MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL 0x37f4
 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8
+#define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x37f8
 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc
 #define A_MAC_PORT_ANALOG_TEST_MUX 0x3814
 #define A_MAC_PORT_BANDGAP_CONTROL 0x382c
@@ -38164,6 +55297,52 @@
 #define V_T5BGCTL(x) ((x) << S_T5BGCTL)
 #define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL)
 
+#define A_MAC_PORT_PLLREFSEL_CONTROL 0x3854
+
+#define S_REFSEL    0
+#define M_REFSEL    0x7U
+#define V_REFSEL(x) ((x) << S_REFSEL)
+#define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL)
+
+#define A_MAC_PORT_REFISINK_CONTROL 0x3858
+
+#define S_REFISINK    0
+#define M_REFISINK    0x3fU
+#define V_REFISINK(x) ((x) << S_REFISINK)
+#define G_REFISINK(x) (((x) >> S_REFISINK) & M_REFISINK)
+
+#define A_MAC_PORT_REFISRC_CONTROL 0x385c
+
+#define S_REFISRC    0
+#define M_REFISRC    0x3fU
+#define V_REFISRC(x) ((x) << S_REFISRC)
+#define G_REFISRC(x) (((x) >> S_REFISRC) & M_REFISRC)
+
+#define A_MAC_PORT_REFVREG_CONTROL 0x3860
+
+#define S_REFVREG    0
+#define M_REFVREG    0x3fU
+#define V_REFVREG(x) ((x) << S_REFVREG)
+#define G_REFVREG(x) (((x) >> S_REFVREG) & M_REFVREG)
+
+#define A_MAC_PORT_VBGENDOC_CONTROL 0x3864
+
+#define S_BGCLKSEL    2
+#define V_BGCLKSEL(x) ((x) << S_BGCLKSEL)
+#define F_BGCLKSEL    V_BGCLKSEL(1U)
+
+#define S_VBGENDOC    0
+#define M_VBGENDOC    0x3U
+#define V_VBGENDOC(x) ((x) << S_VBGENDOC)
+#define G_VBGENDOC(x) (((x) >> S_VBGENDOC) & M_VBGENDOC)
+
+#define A_MAC_PORT_VREFTUNE_CONTROL 0x3868
+
+#define S_VREFTUNE    0
+#define M_VREFTUNE    0xfU
+#define V_VREFTUNE(x) ((x) << S_VREFTUNE)
+#define G_VREFTUNE(x) (((x) >> S_VREFTUNE) & M_VREFTUNE)
+
 #define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880
 
 #define S_RCCTL1    5
@@ -38190,6 +55369,24 @@
 #define V_RCRST(x) ((x) << S_RCRST)
 #define F_RCRST    V_RCRST(1U)
 
+#define A_MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL 0x3880
+
+#define S_FRCCAL_COMP    6
+#define V_FRCCAL_COMP(x) ((x) << S_FRCCAL_COMP)
+#define F_FRCCAL_COMP    V_FRCCAL_COMP(1U)
+
+#define S_IC_FRCERR    5
+#define V_IC_FRCERR(x) ((x) << S_IC_FRCERR)
+#define F_IC_FRCERR    V_IC_FRCERR(1U)
+
+#define S_CAL_BISTENAB    4
+#define V_CAL_BISTENAB(x) ((x) << S_CAL_BISTENAB)
+#define F_CAL_BISTENAB    V_CAL_BISTENAB(1U)
+
+#define S_RCAL_RESET    0
+#define V_RCAL_RESET(x) ((x) << S_RCAL_RESET)
+#define F_RCAL_RESET    V_RCAL_RESET(1U)
+
 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884
 
 #define S_RCERR    1
@@ -38200,6 +55397,24 @@
 #define V_RCCOMP(x) ((x) << S_RCCOMP)
 #define F_RCCOMP    V_RCCOMP(1U)
 
+#define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1 0x3884
+
+#define S_RCALBENAB    3
+#define V_RCALBENAB(x) ((x) << S_RCALBENAB)
+#define F_RCALBENAB    V_RCALBENAB(1U)
+
+#define S_RCALBUSY    2
+#define V_RCALBUSY(x) ((x) << S_RCALBUSY)
+#define F_RCALBUSY    V_RCALBUSY(1U)
+
+#define S_RCALERR    1
+#define V_RCALERR(x) ((x) << S_RCALERR)
+#define F_RCALERR    V_RCALERR(1U)
+
+#define S_RCALCOMP    0
+#define V_RCALCOMP(x) ((x) << S_RCALCOMP)
+#define F_RCALCOMP    V_RCALCOMP(1U)
+
 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888
 
 #define S_RESREG2    0
@@ -38207,6 +55422,13 @@
 #define V_RESREG2(x) ((x) << S_RESREG2)
 #define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2)
 
+#define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2 0x3888
+
+#define S_T6_RESREG2    0
+#define M_T6_RESREG2    0x3fU
+#define V_T6_RESREG2(x) ((x) << S_T6_RESREG2)
+#define G_T6_RESREG2(x) (((x) >> S_T6_RESREG2) & M_T6_RESREG2)
+
 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c
 
 #define S_RESREG3    0
@@ -38214,6 +55436,69 @@
 #define V_RESREG3(x) ((x) << S_RESREG3)
 #define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3)
 
+#define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3 0x388c
+
+#define S_T6_RESREG3    0
+#define M_T6_RESREG3    0x3fU
+#define V_T6_RESREG3(x) ((x) << S_T6_RESREG3)
+#define G_T6_RESREG3(x) (((x) >> S_T6_RESREG3) & M_T6_RESREG3)
+
+#define A_MAC_PORT_INEQUALITY_CONTROL_AND_RESULT 0x38c0
+
+#define S_ISGT    7
+#define V_ISGT(x) ((x) << S_ISGT)
+#define F_ISGT    V_ISGT(1U)
+
+#define S_ISLT    6
+#define V_ISLT(x) ((x) << S_ISLT)
+#define F_ISLT    V_ISLT(1U)
+
+#define S_ISEQ    5
+#define V_ISEQ(x) ((x) << S_ISEQ)
+#define F_ISEQ    V_ISEQ(1U)
+
+#define S_ISVAL    3
+#define M_ISVAL    0x3U
+#define V_ISVAL(x) ((x) << S_ISVAL)
+#define G_ISVAL(x) (((x) >> S_ISVAL) & M_ISVAL)
+
+#define S_GTORLT    1
+#define M_GTORLT    0x3U
+#define V_GTORLT(x) ((x) << S_GTORLT)
+#define G_GTORLT(x) (((x) >> S_GTORLT) & M_GTORLT)
+
+#define S_INEQ    0
+#define V_INEQ(x) ((x) << S_INEQ)
+#define F_INEQ    V_INEQ(1U)
+
+#define A_MAC_PORT_INEQUALITY_LOW_LIMIT 0x38c4
+
+#define S_LLIM    0
+#define M_LLIM    0xffffU
+#define V_LLIM(x) ((x) << S_LLIM)
+#define G_LLIM(x) (((x) >> S_LLIM) & M_LLIM)
+
+#define A_MAC_PORT_INEQUALITY_LOW_LIMIT_MASK 0x38c8
+
+#define S_LMSK    0
+#define M_LMSK    0xffffU
+#define V_LMSK(x) ((x) << S_LMSK)
+#define G_LMSK(x) (((x) >> S_LMSK) & M_LMSK)
+
+#define A_MAC_PORT_INEQUALITY_HIGH_LIMIT 0x38cc
+
+#define S_HLIM    0
+#define M_HLIM    0xffffU
+#define V_HLIM(x) ((x) << S_HLIM)
+#define G_HLIM(x) (((x) >> S_HLIM) & M_HLIM)
+
+#define A_MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK 0x38d0
+
+#define S_HMSK    0
+#define M_HMSK    0xffffU
+#define V_HMSK(x) ((x) << S_HMSK)
+#define G_HMSK(x) (((x) >> S_HMSK) & M_HMSK)
+
 #define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8
 
 #define S_LBIST    7
@@ -38279,85 +55564,335 @@
 #define F_MACROTEST    V_MACROTEST(1U)
 
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
+
+#define S_T6_T5_TX_RXLOOP    5
+#define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
+#define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
+
+#define S_T6_T5_TX_BWSEL    2
+#define M_T6_T5_TX_BWSEL    0x3U
+#define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
+#define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
+
+#define S_T6_ERROR    9
+#define V_T6_ERROR(x) ((x) << S_T6_ERROR)
+#define F_T6_ERROR    V_T6_ERROR(1U)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918
+
+#define S_T6_CALSSTN    8
+#define M_T6_CALSSTN    0x3fU
+#define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
+#define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
+
+#define S_T6_CALSSTP    0
+#define M_T6_CALSSTP    0x3fU
+#define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
+#define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c
+
+#define S_T6_DRTOL    2
+#define M_T6_DRTOL    0x7U
+#define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
+#define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920
+
+#define S_T6_NXTT0    0
+#define M_T6_NXTT0    0x3fU
+#define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
+#define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928
+
+#define S_T6_NXTT2    0
+#define M_T6_NXTT2    0x3fU
+#define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
+#define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
+
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT 0x392c
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934
+
+#define S_T6_NXTPOL    0
+#define M_T6_NXTPOL    0xfU
+#define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
+#define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938
+
+#define S_T6_C0UPDT    6
+#define M_T6_C0UPDT    0x3U
+#define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
+#define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
+
+#define S_T6_C2UPDT    2
+#define M_T6_C2UPDT    0x3U
+#define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
+#define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
+
+#define S_T6_C1UPDT    0
+#define M_T6_C1UPDT    0x3U
+#define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
+#define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c
+
+#define S_T6_C0STAT    6
+#define M_T6_C0STAT    0x3U
+#define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
+#define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
+
+#define S_T6_C2STAT    2
+#define M_T6_C2STAT    0x3U
+#define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
+#define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
+
+#define S_T6_C1STAT    0
+#define M_T6_C1STAT    0x3U
+#define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
+#define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3940
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3944
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3948
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x394c
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER 0x3950
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3958
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED 0x3960
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED 0x3964
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED 0x3968
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x396c
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3970
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3974
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c
+
+#define S_T6_XADDR    1
+#define M_T6_XADDR    0x1fU
+#define V_T6_XADDR(x) ((x) << S_T6_XADDR)
+#define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3988
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x398c
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c
+#define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x39a0
+
+#define S_T6_DCCTIMEEN    13
+#define M_T6_DCCTIMEEN    0x3U
+#define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
+#define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
+
+#define S_T6_DCCLOCK    11
+#define M_T6_DCCLOCK    0x3U
+#define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
+#define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
+
+#define S_T6_DCCOFFSET    8
+#define M_T6_DCCOFFSET    0x7U
+#define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
+#define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
+
+#define S_TX_LINK_BCST_DCCSTEP_CTL    6
+#define M_TX_LINK_BCST_DCCSTEP_CTL    0x3U
+#define V_TX_LINK_BCST_DCCSTEP_CTL(x) ((x) << S_TX_LINK_BCST_DCCSTEP_CTL)
+#define G_TX_LINK_BCST_DCCSTEP_CTL(x) (((x) >> S_TX_LINK_BCST_DCCSTEP_CTL) & M_TX_LINK_BCST_DCCSTEP_CTL)
+
+#define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x39a4
+#define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x39a8
+#define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x39ac
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE 0x39c0
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE 0x39c8
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE 0x39cc
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE 0x39d0
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x39d8
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x39dc
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x39e0
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5 0x39ec
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0
+
+#define S_T6_SDOVRD    0
+#define M_T6_SDOVRD    0xffffU
+#define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
+#define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc
+
+#define S_T6_SDOVRDEN    15
+#define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
+#define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
+
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c
+
+#define S_T6_TMSCAL    8
+#define M_T6_TMSCAL    0x3U
+#define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
+#define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
+
+#define S_T6_APADJ    7
+#define V_T6_APADJ(x) ((x) << S_T6_APADJ)
+#define F_T6_APADJ    V_T6_APADJ(1U)
+
+#define S_T6_RSEL    6
+#define V_T6_RSEL(x) ((x) << S_T6_RSEL)
+#define F_T6_RSEL    V_T6_RSEL(1U)
+
+#define S_T6_PHOFFS    0
+#define M_T6_PHOFFS    0x3fU
+#define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
+#define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
+
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18
 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c
 #define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20
+
+#define S_T6_SPIFMT    8
+#define M_T6_SPIFMT    0xfU
+#define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
+#define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
+
 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24
 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c
+
+#define S_T6_WRAPSEL    15
+#define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
+#define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
+
+#define S_T6_PEAK    9
+#define M_T6_PEAK    0x1fU
+#define V_T6_PEAK(x) ((x) << S_T6_PEAK)
+#define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
+
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30
+
+#define S_T6_T5VGAIN    0
+#define M_T6_T5VGAIN    0x7fU
+#define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
+#define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
+
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3a38
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1 0x3a3c
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2 0x3a40
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3a44
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN 0x3a4c
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL 0x3a54
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE 0x3a58
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET 0x3a5c
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3a60
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64
+#define A_MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR 0x3a64
+#define A_MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH 0x3a68
+#define A_MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x3a6c
 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70
 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74
+
+#define S_T6_ODEC    0
+#define M_T6_ODEC    0xfU
+#define V_T6_ODEC(x) ((x) << S_T6_ODEC)
+#define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
+
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78
+
+#define S_RX_LINK_BCST_ACCCMP_RIS    11
+#define V_RX_LINK_BCST_ACCCMP_RIS(x) ((x) << S_RX_LINK_BCST_ACCCMP_RIS)
+#define F_RX_LINK_BCST_ACCCMP_RIS    V_RX_LINK_BCST_ACCCMP_RIS(1U)
+
 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c
 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80
 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84
+#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL 0x3a84
 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88
+#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE 0x3a88
 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c
+#define A_MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST 0x3a8c
 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90
+#define A_MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST 0x3a90
+
+#define S_RX_LINK_BCST_ACCCMP_BIST    13
+#define V_RX_LINK_BCST_ACCCMP_BIST(x) ((x) << S_RX_LINK_BCST_ACCCMP_BIST)
+#define F_RX_LINK_BCST_ACCCMP_BIST    V_RX_LINK_BCST_ACCCMP_BIST(1U)
+
 #define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER 0x3a98
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0
 #define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac
+
+#define S_T6_EMMD    3
+#define M_T6_EMMD    0x3U
+#define V_T6_EMMD(x) ((x) << S_T6_EMMD)
+#define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
+
+#define S_T6_EMBRDY    2
+#define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
+#define F_T6_EMBRDY    V_T6_EMBRDY(1U)
+
+#define S_T6_EMBUMP    1
+#define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
+#define F_T6_EMBUMP    V_T6_EMBUMP(1U)
+
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4
 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8
+#define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3 0x3abc
 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0
+#define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL 0x3ac0
+
+#define S_RX_LINK_BCST_INDEX_DFE_TC    0
+#define M_RX_LINK_BCST_INDEX_DFE_TC    0xfU
+#define V_RX_LINK_BCST_INDEX_DFE_TC(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TC)
+#define G_RX_LINK_BCST_INDEX_DFE_TC(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TC) & M_RX_LINK_BCST_INDEX_DFE_TC)
+
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4
+#define A_MAC_PORT_RX_LINK_BCST_DFE_TAP 0x3ac4
+
+#define S_RX_LINK_BCST_INDEX_DFE_TAP    0
+#define M_RX_LINK_BCST_INDEX_DFE_TAP    0xfU
+#define V_RX_LINK_BCST_INDEX_DFE_TAP(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TAP)
+#define G_RX_LINK_BCST_INDEX_DFE_TAP(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TAP) & M_RX_LINK_BCST_INDEX_DFE_TAP)
+
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0
@@ -38366,13 +55901,39 @@
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0
 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2 0x3ae4
+#define A_MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x3ae8
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL 0x3aec
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL 0x3af0
+
+#define S_RX_LINK_BCST_DCCSTEP_RXCTL    10
+#define M_RX_LINK_BCST_DCCSTEP_RXCTL    0x3U
+#define V_RX_LINK_BCST_DCCSTEP_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCSTEP_RXCTL)
+#define G_RX_LINK_BCST_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINK_BCST_DCCSTEP_RXCTL) & M_RX_LINK_BCST_DCCSTEP_RXCTL)
+
+#define S_RX_LINK_BCST_DCCLOCK_RXCTL    8
+#define V_RX_LINK_BCST_DCCLOCK_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCLOCK_RXCTL)
+#define F_RX_LINK_BCST_DCCLOCK_RXCTL    V_RX_LINK_BCST_DCCLOCK_RXCTL(1U)
+
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL 0x3af4
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x3af8
 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc
 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00
 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04
 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08
 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c
 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10
+#define A_MAC_PORT_PLLA_POWER_CONTROL 0x3b24
+
+#define S_SPWRENA    1
+#define V_SPWRENA(x) ((x) << S_SPWRENA)
+#define F_SPWRENA    V_SPWRENA(1U)
+
+#define S_NPWRENA    0
+#define V_NPWRENA(x) ((x) << S_NPWRENA)
+#define F_NPWRENA    V_NPWRENA(1U)
+
 #define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28
 
 #define S_T5CPISEL    0
@@ -38380,6 +55941,7 @@
 #define V_T5CPISEL(x) ((x) << S_T5CPISEL)
 #define G_T5CPISEL(x) (((x) >> S_T5CPISEL) & M_T5CPISEL)
 
+#define A_MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL 0x3b38
 #define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c
 
 #define S_SPEDIV    3
@@ -38441,6 +56003,15 @@
 #define V_VBST(x) ((x) << S_VBST)
 #define G_VBST(x) (((x) >> S_VBST) & M_VBST)
 
+#define S_PLLDIVA    4
+#define V_PLLDIVA(x) ((x) << S_PLLDIVA)
+#define F_PLLDIVA    V_PLLDIVA(1U)
+
+#define S_REFDIV    0
+#define M_REFDIV    0xfU
+#define V_REFDIV(x) ((x) << S_REFDIV)
+#define G_REFDIV(x) (((x) >> S_REFDIV) & M_REFDIV)
+
 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4
 
 #define S_RESYNC    6
@@ -38490,7 +56061,9 @@
 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08
 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c
 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10
+#define A_MAC_PORT_PLLB_POWER_CONTROL 0x3c24
 #define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28
+#define A_MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL 0x3c38
 #define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c
 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40
 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44
@@ -38508,6 +56081,7 @@
 #define V_STEP(x) ((x) << S_STEP)
 #define G_STEP(x) (((x) >> S_STEP) & M_STEP)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
 
 #define S_C0INIT    0
@@ -38515,6 +56089,16 @@
 #define V_C0INIT(x) ((x) << S_C0INIT)
 #define G_C0INIT(x) (((x) >> S_C0INIT) & M_C0INIT)
 
+#define S_C0PRESET    8
+#define M_C0PRESET    0x7fU
+#define V_C0PRESET(x) ((x) << S_C0PRESET)
+#define G_C0PRESET(x) (((x) >> S_C0PRESET) & M_C0PRESET)
+
+#define S_C0INIT1    0
+#define M_C0INIT1    0x7fU
+#define V_C0INIT1(x) ((x) << S_C0INIT1)
+#define G_C0INIT1(x) (((x) >> S_C0INIT1) & M_C0INIT1)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
 
 #define S_C0MAX    8
@@ -38527,6 +56111,18 @@
 #define V_C0MIN(x) ((x) << S_C0MIN)
 #define G_C0MIN(x) (((x) >> S_C0MIN) & M_C0MIN)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
+
+#define S_T6_C0MAX    8
+#define M_T6_C0MAX    0x7fU
+#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
+#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
+
+#define S_T6_C0MIN    0
+#define M_T6_C0MIN    0x7fU
+#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
+#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
 
 #define S_C1INIT    0
@@ -38534,6 +56130,18 @@
 #define V_C1INIT(x) ((x) << S_C1INIT)
 #define G_C1INIT(x) (((x) >> S_C1INIT) & M_C1INIT)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
+
+#define S_C1PRESET    8
+#define M_C1PRESET    0x7fU
+#define V_C1PRESET(x) ((x) << S_C1PRESET)
+#define G_C1PRESET(x) (((x) >> S_C1PRESET) & M_C1PRESET)
+
+#define S_C1INIT1    0
+#define M_C1INIT1    0x7fU
+#define V_C1INIT1(x) ((x) << S_C1INIT1)
+#define G_C1INIT1(x) (((x) >> S_C1INIT1) & M_C1INIT1)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
 
 #define S_C1MAX    8
@@ -38546,6 +56154,7 @@
 #define V_C1MIN(x) ((x) << S_C1MIN)
 #define G_C1MIN(x) (((x) >> S_C1MIN) & M_C1MIN)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
 
 #define S_C2INIT    0
@@ -38553,6 +56162,18 @@
 #define V_C2INIT(x) ((x) << S_C2INIT)
 #define G_C2INIT(x) (((x) >> S_C2INIT) & M_C2INIT)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
+
+#define S_C2PRESET    8
+#define M_C2PRESET    0x7fU
+#define V_C2PRESET(x) ((x) << S_C2PRESET)
+#define G_C2PRESET(x) (((x) >> S_C2PRESET) & M_C2PRESET)
+
+#define S_C2INIT1    0
+#define M_C2INIT1    0x7fU
+#define V_C2INIT1(x) ((x) << S_C2INIT1)
+#define G_C2INIT1(x) (((x) >> S_C2INIT1) & M_C2INIT1)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
 
 #define S_C2MAX    8
@@ -38565,6 +56186,18 @@
 #define V_C2MIN(x) ((x) << S_C2MIN)
 #define G_C2MIN(x) (((x) >> S_C2MIN) & M_C2MIN)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
+
+#define S_T6_C2MAX    8
+#define M_T6_C2MAX    0x7fU
+#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
+#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
+
+#define S_T6_C2MIN    0
+#define M_T6_C2MIN    0x7fU
+#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
+#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
+
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
 
 #define S_VMMAX    0
@@ -38572,6 +56205,7 @@
 #define V_VMMAX(x) ((x) << S_VMMAX)
 #define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
 
 #define S_V2MIN    0
@@ -38579,42 +56213,507 @@
 #define V_V2MIN(x) ((x) << S_V2MIN)
 #define G_V2MIN(x) (((x) >> S_V2MIN) & M_V2MIN)
 
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
+
+#define S_C3PRESET    8
+#define M_C3PRESET    0x7fU
+#define V_C3PRESET(x) ((x) << S_C3PRESET)
+#define G_C3PRESET(x) (((x) >> S_C3PRESET) & M_C3PRESET)
+
+#define S_C3INIT1    0
+#define M_C3INIT1    0x7fU
+#define V_C3INIT1(x) ((x) << S_C3INIT1)
+#define G_C3INIT1(x) (((x) >> S_C3INIT1) & M_C3INIT1)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
+
+#define S_C3MAX    8
+#define M_C3MAX    0x7fU
+#define V_C3MAX(x) ((x) << S_C3MAX)
+#define G_C3MAX(x) (((x) >> S_C3MAX) & M_C3MAX)
+
+#define S_C3MIN    0
+#define M_C3MIN    0x7fU
+#define V_C3MIN(x) ((x) << S_C3MIN)
+#define G_C3MIN(x) (((x) >> S_C3MIN) & M_C3MIN)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
+
+#define S_C0INIT2    0
+#define M_C0INIT2    0x7fU
+#define V_C0INIT2(x) ((x) << S_C0INIT2)
+#define G_C0INIT2(x) (((x) >> S_C0INIT2) & M_C0INIT2)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
+
+#define S_C1INIT2    0
+#define M_C1INIT2    0x7fU
+#define V_C1INIT2(x) ((x) << S_C1INIT2)
+#define G_C1INIT2(x) (((x) >> S_C1INIT2) & M_C1INIT2)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
+
+#define S_C2INIT2    0
+#define M_C2INIT2    0x7fU
+#define V_C2INIT2(x) ((x) << S_C2INIT2)
+#define G_C2INIT2(x) (((x) >> S_C2INIT2) & M_C2INIT2)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
+
+#define S_C3INIT2    0
+#define M_C3INIT2    0x7fU
+#define V_C3INIT2(x) ((x) << S_C3INIT2)
+#define G_C3INIT2(x) (((x) >> S_C3INIT2) & M_C3INIT2)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
+
+#define S_T6_C0MAX    8
+#define M_T6_C0MAX    0x7fU
+#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
+#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
+
+#define S_T6_C0MIN    0
+#define M_T6_C0MIN    0x7fU
+#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
+#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
+
+#define S_T6_C2MAX    8
+#define M_T6_C2MAX    0x7fU
+#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
+#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
+
+#define S_T6_C2MIN    0
+#define M_T6_C2MIN    0x7fU
+#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
+#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
+
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
+
+#define S_T6_C0MAX    8
+#define M_T6_C0MAX    0x7fU
+#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
+#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
+
+#define S_T6_C0MIN    0
+#define M_T6_C0MIN    0x7fU
+#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
+#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
+
+#define S_T6_C2MAX    8
+#define M_T6_C2MAX    0x7fU
+#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
+#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
+
+#define S_T6_C2MIN    0
+#define M_T6_C2MIN    0x7fU
+#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
+#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
+
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
+
+#define S_T6_C0MAX    8
+#define M_T6_C0MAX    0x7fU
+#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
+#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
+
+#define S_T6_C0MIN    0
+#define M_T6_C0MIN    0x7fU
+#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
+#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
+
+#define S_T6_C2MAX    8
+#define M_T6_C2MAX    0x7fU
+#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
+#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
+
+#define S_T6_C2MIN    0
+#define M_T6_C2MIN    0x7fU
+#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
+#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
+
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
+
+#define S_T6_C0MAX    8
+#define M_T6_C0MAX    0x7fU
+#define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
+#define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
+
+#define S_T6_C0MIN    0
+#define M_T6_C0MIN    0x7fU
+#define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
+#define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
+
+#define S_T6_C2MAX    8
+#define M_T6_C2MAX    0x7fU
+#define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
+#define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
+
+#define S_T6_C2MIN    0
+#define M_T6_C2MIN    0x7fU
+#define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
+#define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
+
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
+#define A_T6_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x2a00
+
+#define S_RX_LINKA_INDEX_DFE_EN    1
+#define M_RX_LINKA_INDEX_DFE_EN    0x7fffU
+#define V_RX_LINKA_INDEX_DFE_EN(x) ((x) << S_RX_LINKA_INDEX_DFE_EN)
+#define G_RX_LINKA_INDEX_DFE_EN(x) (((x) >> S_RX_LINKA_INDEX_DFE_EN) & M_RX_LINKA_INDEX_DFE_EN)
+
+#define A_T6_MAC_PORT_RX_LINKA_DFE_H1 0x2a04
+
+#define S_T6_H1OSN    13
+#define M_T6_H1OSN    0x7U
+#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
+#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
+
+#define S_T6_H1OMAG    8
+#define M_T6_H1OMAG    0x1fU
+#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
+#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
+
+#define A_T6_MAC_PORT_RX_LINKA_DFE_H2 0x2a08
+#define A_T6_MAC_PORT_RX_LINKA_DFE_H3 0x2a0c
+#define A_T6_MAC_PORT_RX_LINKA_DFE_H4 0x2a10
+
+#define S_H4SN    4
+#define M_H4SN    0x3U
+#define V_H4SN(x) ((x) << S_H4SN)
+#define G_H4SN(x) (((x) >> S_H4SN) & M_H4SN)
+
+#define S_H4MAG    0
+#define M_H4MAG    0xfU
+#define V_H4MAG(x) ((x) << S_H4MAG)
+#define G_H4MAG(x) (((x) >> S_H4MAG) & M_H4MAG)
+
+#define A_T6_MAC_PORT_RX_LINKA_DFE_H5 0x2a14
+
+#define S_H5GS    6
+#define M_H5GS    0x3U
+#define V_H5GS(x) ((x) << S_H5GS)
+#define G_H5GS(x) (((x) >> S_H5GS) & M_H5GS)
+
+#define S_H5SN    4
+#define M_H5SN    0x3U
+#define V_H5SN(x) ((x) << S_H5SN)
+#define G_H5SN(x) (((x) >> S_H5SN) & M_H5SN)
+
+#define S_H5MAG    0
+#define M_H5MAG    0xfU
+#define V_H5MAG(x) ((x) << S_H5MAG)
+#define G_H5MAG(x) (((x) >> S_H5MAG) & M_H5MAG)
+
+#define A_T6_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x2a18
+
+#define S_H7SN    12
+#define M_H7SN    0x3U
+#define V_H7SN(x) ((x) << S_H7SN)
+#define G_H7SN(x) (((x) >> S_H7SN) & M_H7SN)
+
+#define S_H6SN    4
+#define M_H6SN    0x3U
+#define V_H6SN(x) ((x) << S_H6SN)
+#define G_H6SN(x) (((x) >> S_H6SN) & M_H6SN)
+
+#define A_T6_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x2a1c
+
+#define S_H9SN    12
+#define M_H9SN    0x3U
+#define V_H9SN(x) ((x) << S_H9SN)
+#define G_H9SN(x) (((x) >> S_H9SN) & M_H9SN)
+
+#define S_H8SN    4
+#define M_H8SN    0x3U
+#define V_H8SN(x) ((x) << S_H8SN)
+#define G_H8SN(x) (((x) >> S_H8SN) & M_H8SN)
+
+#define A_T6_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x2a20
+
+#define S_H11SN    12
+#define M_H11SN    0x3U
+#define V_H11SN(x) ((x) << S_H11SN)
+#define G_H11SN(x) (((x) >> S_H11SN) & M_H11SN)
+
+#define S_H10SN    4
+#define M_H10SN    0x3U
+#define V_H10SN(x) ((x) << S_H10SN)
+#define G_H10SN(x) (((x) >> S_H10SN) & M_H10SN)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H12_13 0x2a24
+
+#define S_H13GS    13
+#define M_H13GS    0x7U
+#define V_H13GS(x) ((x) << S_H13GS)
+#define G_H13GS(x) (((x) >> S_H13GS) & M_H13GS)
+
+#define S_H13SN    10
+#define M_H13SN    0x7U
+#define V_H13SN(x) ((x) << S_H13SN)
+#define G_H13SN(x) (((x) >> S_H13SN) & M_H13SN)
+
+#define S_H13MAG    8
+#define M_H13MAG    0x3U
+#define V_H13MAG(x) ((x) << S_H13MAG)
+#define G_H13MAG(x) (((x) >> S_H13MAG) & M_H13MAG)
+
+#define S_H12SN    4
+#define M_H12SN    0x3U
+#define V_H12SN(x) ((x) << S_H12SN)
+#define G_H12SN(x) (((x) >> S_H12SN) & M_H12SN)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H14_15 0x2a28
+
+#define S_H15GS    13
+#define M_H15GS    0x7U
+#define V_H15GS(x) ((x) << S_H15GS)
+#define G_H15GS(x) (((x) >> S_H15GS) & M_H15GS)
+
+#define S_H15SN    10
+#define M_H15SN    0x7U
+#define V_H15SN(x) ((x) << S_H15SN)
+#define G_H15SN(x) (((x) >> S_H15SN) & M_H15SN)
+
+#define S_H15MAG    8
+#define M_H15MAG    0x3U
+#define V_H15MAG(x) ((x) << S_H15MAG)
+#define G_H15MAG(x) (((x) >> S_H15MAG) & M_H15MAG)
+
+#define S_H14GS    6
+#define M_H14GS    0x3U
+#define V_H14GS(x) ((x) << S_H14GS)
+#define G_H14GS(x) (((x) >> S_H14GS) & M_H14GS)
+
+#define S_H14SN    4
+#define M_H14SN    0x3U
+#define V_H14SN(x) ((x) << S_H14SN)
+#define G_H14SN(x) (((x) >> S_H14SN) & M_H14SN)
+
+#define S_H14MAG    0
+#define M_H14MAG    0xfU
+#define V_H14MAG(x) ((x) << S_H14MAG)
+#define G_H14MAG(x) (((x) >> S_H14MAG) & M_H14MAG)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2a2c
+
+#define S_H1ODELTA    8
+#define M_H1ODELTA    0x1fU
+#define V_H1ODELTA(x) ((x) << S_H1ODELTA)
+#define G_H1ODELTA(x) (((x) >> S_H1ODELTA) & M_H1ODELTA)
+
+#define S_H1EDELTA    0
+#define M_H1EDELTA    0x3fU
+#define V_H1EDELTA(x) ((x) << S_H1EDELTA)
+#define G_H1EDELTA(x) (((x) >> S_H1EDELTA) & M_H1EDELTA)
+
+#define A_T6_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x2b00
+
+#define S_RX_LINKB_INDEX_DFE_EN    1
+#define M_RX_LINKB_INDEX_DFE_EN    0x7fffU
+#define V_RX_LINKB_INDEX_DFE_EN(x) ((x) << S_RX_LINKB_INDEX_DFE_EN)
+#define G_RX_LINKB_INDEX_DFE_EN(x) (((x) >> S_RX_LINKB_INDEX_DFE_EN) & M_RX_LINKB_INDEX_DFE_EN)
+
+#define A_T6_MAC_PORT_RX_LINKB_DFE_H1 0x2b04
+
+#define S_T6_H1OSN    13
+#define M_T6_H1OSN    0x7U
+#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
+#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
+
+#define S_T6_H1OMAG    8
+#define M_T6_H1OMAG    0x1fU
+#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
+#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
+
+#define A_T6_MAC_PORT_RX_LINKB_DFE_H2 0x2b08
+#define A_T6_MAC_PORT_RX_LINKB_DFE_H3 0x2b0c
+#define A_T6_MAC_PORT_RX_LINKB_DFE_H4 0x2b10
+#define A_T6_MAC_PORT_RX_LINKB_DFE_H5 0x2b14
+#define A_T6_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x2b18
+#define A_T6_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x2b1c
+#define A_T6_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x2b20
+#define A_MAC_PORT_RX_LINKB_DFE_H12_13 0x2b24
+#define A_MAC_PORT_RX_LINKB_DFE_H14_15 0x2b28
+#define A_MAC_PORT_RX_LINKB_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2b2c
+#define A_T6_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x2e00
+
+#define S_RX_LINKC_INDEX_DFE_EN    1
+#define M_RX_LINKC_INDEX_DFE_EN    0x7fffU
+#define V_RX_LINKC_INDEX_DFE_EN(x) ((x) << S_RX_LINKC_INDEX_DFE_EN)
+#define G_RX_LINKC_INDEX_DFE_EN(x) (((x) >> S_RX_LINKC_INDEX_DFE_EN) & M_RX_LINKC_INDEX_DFE_EN)
+
+#define A_T6_MAC_PORT_RX_LINKC_DFE_H1 0x2e04
+
+#define S_T6_H1OSN    13
+#define M_T6_H1OSN    0x7U
+#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
+#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
+
+#define S_T6_H1OMAG    8
+#define M_T6_H1OMAG    0x1fU
+#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
+#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
+
+#define A_T6_MAC_PORT_RX_LINKC_DFE_H2 0x2e08
+#define A_T6_MAC_PORT_RX_LINKC_DFE_H3 0x2e0c
+#define A_T6_MAC_PORT_RX_LINKC_DFE_H4 0x2e10
+#define A_T6_MAC_PORT_RX_LINKC_DFE_H5 0x2e14
+#define A_T6_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x2e18
+#define A_T6_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x2e1c
+#define A_T6_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x2e20
+#define A_MAC_PORT_RX_LINKC_DFE_H12_13 0x2e24
+#define A_MAC_PORT_RX_LINKC_DFE_H14_15 0x2e28
+#define A_MAC_PORT_RX_LINKC_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2e2c
+#define A_T6_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x2f00
+
+#define S_RX_LINKD_INDEX_DFE_EN    1
+#define M_RX_LINKD_INDEX_DFE_EN    0x7fffU
+#define V_RX_LINKD_INDEX_DFE_EN(x) ((x) << S_RX_LINKD_INDEX_DFE_EN)
+#define G_RX_LINKD_INDEX_DFE_EN(x) (((x) >> S_RX_LINKD_INDEX_DFE_EN) & M_RX_LINKD_INDEX_DFE_EN)
+
+#define A_T6_MAC_PORT_RX_LINKD_DFE_H1 0x2f04
+
+#define S_T6_H1OSN    13
+#define M_T6_H1OSN    0x7U
+#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
+#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
+
+#define S_T6_H1OMAG    8
+#define M_T6_H1OMAG    0x1fU
+#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
+#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
+
+#define A_T6_MAC_PORT_RX_LINKD_DFE_H2 0x2f08
+#define A_T6_MAC_PORT_RX_LINKD_DFE_H3 0x2f0c
+#define A_T6_MAC_PORT_RX_LINKD_DFE_H4 0x2f10
+#define A_T6_MAC_PORT_RX_LINKD_DFE_H5 0x2f14
+#define A_T6_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x2f18
+#define A_T6_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x2f1c
+#define A_T6_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x2f20
+#define A_MAC_PORT_RX_LINKD_DFE_H12_13 0x2f24
+#define A_MAC_PORT_RX_LINKD_DFE_H14_15 0x2f28
+#define A_MAC_PORT_RX_LINKD_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2f2c
+#define A_T6_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3200
+
+#define S_RX_LINK_BCST_INDEX_DFE_EN    1
+#define M_RX_LINK_BCST_INDEX_DFE_EN    0x7fffU
+#define V_RX_LINK_BCST_INDEX_DFE_EN(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_EN)
+#define G_RX_LINK_BCST_INDEX_DFE_EN(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_EN) & M_RX_LINK_BCST_INDEX_DFE_EN)
+
+#define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3204
+
+#define S_T6_H1OSN    13
+#define M_T6_H1OSN    0x7U
+#define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
+#define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
+
+#define S_T6_H1OMAG    8
+#define M_T6_H1OMAG    0x1fU
+#define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
+#define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
+
+#define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3208
+#define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H3 0x320c
+#define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3210
+#define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3214
+#define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3218
+#define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x321c
+#define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3220
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H12_13 0x3224
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H14_15 0x3228
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x322c
 
 /* registers for module MC_0 */
 #define MC_0_BASE_ADDR 0x40000
@@ -38655,6 +56754,28 @@
 #define V_CMD_OPCODE0(x) ((x) << S_CMD_OPCODE0)
 #define G_CMD_OPCODE0(x) (((x) >> S_CMD_OPCODE0) & M_CMD_OPCODE0)
 
+#define A_MC_LMC_MCSTAT 0x40040
+
+#define S_INIT_COMPLETE    31
+#define V_INIT_COMPLETE(x) ((x) << S_INIT_COMPLETE)
+#define F_INIT_COMPLETE    V_INIT_COMPLETE(1U)
+
+#define S_SELF_REF_MODE    30
+#define V_SELF_REF_MODE(x) ((x) << S_SELF_REF_MODE)
+#define F_SELF_REF_MODE    V_SELF_REF_MODE(1U)
+
+#define S_IDLE    29
+#define V_IDLE(x) ((x) << S_IDLE)
+#define F_IDLE    V_IDLE(1U)
+
+#define S_T6_DFI_INIT_COMPLETE    28
+#define V_T6_DFI_INIT_COMPLETE(x) ((x) << S_T6_DFI_INIT_COMPLETE)
+#define F_T6_DFI_INIT_COMPLETE    V_T6_DFI_INIT_COMPLETE(1U)
+
+#define S_PREFILL_COMPLETE    27
+#define V_PREFILL_COMPLETE(x) ((x) << S_PREFILL_COMPLETE)
+#define F_PREFILL_COMPLETE    V_PREFILL_COMPLETE(1U)
+
 #define A_MC_UPCTL_POWCTL 0x40044
 #define A_MC_UPCTL_POWSTAT 0x40048
 #define A_MC_UPCTL_CMDTSTAT 0x4004c
@@ -38765,7 +56886,163 @@
 #define V_CKE_OR_EN(x) ((x) << S_CKE_OR_EN)
 #define F_CKE_OR_EN    V_CKE_OR_EN(1U)
 
+#define A_MC_LMC_MCOPT1 0x40080
+
+#define S_MC_PROTOCOL    31
+#define V_MC_PROTOCOL(x) ((x) << S_MC_PROTOCOL)
+#define F_MC_PROTOCOL    V_MC_PROTOCOL(1U)
+
+#define S_DM_ENABLE    30
+#define V_DM_ENABLE(x) ((x) << S_DM_ENABLE)
+#define F_DM_ENABLE    V_DM_ENABLE(1U)
+
+#define S_T6_ECC_EN    29
+#define V_T6_ECC_EN(x) ((x) << S_T6_ECC_EN)
+#define F_T6_ECC_EN    V_T6_ECC_EN(1U)
+
+#define S_ECC_COR    28
+#define V_ECC_COR(x) ((x) << S_ECC_COR)
+#define F_ECC_COR    V_ECC_COR(1U)
+
+#define S_RDIMM    27
+#define V_RDIMM(x) ((x) << S_RDIMM)
+#define F_RDIMM    V_RDIMM(1U)
+
+#define S_PMUM    25
+#define M_PMUM    0x3U
+#define V_PMUM(x) ((x) << S_PMUM)
+#define G_PMUM(x) (((x) >> S_PMUM) & M_PMUM)
+
+#define S_WIDTH0    24
+#define V_WIDTH0(x) ((x) << S_WIDTH0)
+#define F_WIDTH0    V_WIDTH0(1U)
+
+#define S_PORT_ID_CHK_EN    23
+#define V_PORT_ID_CHK_EN(x) ((x) << S_PORT_ID_CHK_EN)
+#define F_PORT_ID_CHK_EN    V_PORT_ID_CHK_EN(1U)
+
+#define S_UIOS    22
+#define V_UIOS(x) ((x) << S_UIOS)
+#define F_UIOS    V_UIOS(1U)
+
+#define S_QUADCS_RDIMM    21
+#define V_QUADCS_RDIMM(x) ((x) << S_QUADCS_RDIMM)
+#define F_QUADCS_RDIMM    V_QUADCS_RDIMM(1U)
+
+#define S_ZQCL_EN    20
+#define V_ZQCL_EN(x) ((x) << S_ZQCL_EN)
+#define F_ZQCL_EN    V_ZQCL_EN(1U)
+
+#define S_WIDTH1    19
+#define V_WIDTH1(x) ((x) << S_WIDTH1)
+#define F_WIDTH1    V_WIDTH1(1U)
+
+#define S_WD_DLY    18
+#define V_WD_DLY(x) ((x) << S_WD_DLY)
+#define F_WD_DLY    V_WD_DLY(1U)
+
+#define S_QDEPTH    16
+#define M_QDEPTH    0x3U
+#define V_QDEPTH(x) ((x) << S_QDEPTH)
+#define G_QDEPTH(x) (((x) >> S_QDEPTH) & M_QDEPTH)
+
+#define S_RWOO    15
+#define V_RWOO(x) ((x) << S_RWOO)
+#define F_RWOO    V_RWOO(1U)
+
+#define S_WOOO    14
+#define V_WOOO(x) ((x) << S_WOOO)
+#define F_WOOO    V_WOOO(1U)
+
+#define S_DCOO    13
+#define V_DCOO(x) ((x) << S_DCOO)
+#define F_DCOO    V_DCOO(1U)
+
+#define S_DEF_REF    12
+#define V_DEF_REF(x) ((x) << S_DEF_REF)
+#define F_DEF_REF    V_DEF_REF(1U)
+
+#define S_DEV_TYPE    11
+#define V_DEV_TYPE(x) ((x) << S_DEV_TYPE)
+#define F_DEV_TYPE    V_DEV_TYPE(1U)
+
+#define S_CA_PTY_DLY    10
+#define V_CA_PTY_DLY(x) ((x) << S_CA_PTY_DLY)
+#define F_CA_PTY_DLY    V_CA_PTY_DLY(1U)
+
+#define S_ECC_MUX    8
+#define M_ECC_MUX    0x3U
+#define V_ECC_MUX(x) ((x) << S_ECC_MUX)
+#define G_ECC_MUX(x) (((x) >> S_ECC_MUX) & M_ECC_MUX)
+
+#define S_CE_THRESHOLD    0
+#define M_CE_THRESHOLD    0xffU
+#define V_CE_THRESHOLD(x) ((x) << S_CE_THRESHOLD)
+#define G_CE_THRESHOLD(x) (((x) >> S_CE_THRESHOLD) & M_CE_THRESHOLD)
+
 #define A_MC_UPCTL_PPCFG 0x40084
+#define A_MC_LMC_MCOPT2 0x40084
+
+#define S_SELF_REF_EN    31
+#define V_SELF_REF_EN(x) ((x) << S_SELF_REF_EN)
+#define F_SELF_REF_EN    V_SELF_REF_EN(1U)
+
+#define S_XSR_PREVENT    30
+#define V_XSR_PREVENT(x) ((x) << S_XSR_PREVENT)
+#define F_XSR_PREVENT    V_XSR_PREVENT(1U)
+
+#define S_INIT_START    29
+#define V_INIT_START(x) ((x) << S_INIT_START)
+#define F_INIT_START    V_INIT_START(1U)
+
+#define S_MC_ENABLE    28
+#define V_MC_ENABLE(x) ((x) << S_MC_ENABLE)
+#define F_MC_ENABLE    V_MC_ENABLE(1U)
+
+#define S_CLK_DISABLE    24
+#define M_CLK_DISABLE    0xfU
+#define V_CLK_DISABLE(x) ((x) << S_CLK_DISABLE)
+#define G_CLK_DISABLE(x) (((x) >> S_CLK_DISABLE) & M_CLK_DISABLE)
+
+#define S_RESET_RANK    20
+#define M_RESET_RANK    0xfU
+#define V_RESET_RANK(x) ((x) << S_RESET_RANK)
+#define G_RESET_RANK(x) (((x) >> S_RESET_RANK) & M_RESET_RANK)
+
+#define S_MCIF_COMP_PTY_EN    19
+#define V_MCIF_COMP_PTY_EN(x) ((x) << S_MCIF_COMP_PTY_EN)
+#define F_MCIF_COMP_PTY_EN    V_MCIF_COMP_PTY_EN(1U)
+
+#define S_CKE_OE    17
+#define V_CKE_OE(x) ((x) << S_CKE_OE)
+#define F_CKE_OE    V_CKE_OE(1U)
+
+#define S_RESET_OE    16
+#define V_RESET_OE(x) ((x) << S_RESET_OE)
+#define F_RESET_OE    V_RESET_OE(1U)
+
+#define S_DFI_PHYUD_CNTL    14
+#define V_DFI_PHYUD_CNTL(x) ((x) << S_DFI_PHYUD_CNTL)
+#define F_DFI_PHYUD_CNTL    V_DFI_PHYUD_CNTL(1U)
+
+#define S_DFI_PHYUD_ACK    13
+#define V_DFI_PHYUD_ACK(x) ((x) << S_DFI_PHYUD_ACK)
+#define F_DFI_PHYUD_ACK    V_DFI_PHYUD_ACK(1U)
+
+#define S_T6_DFI_INIT_START    12
+#define V_T6_DFI_INIT_START(x) ((x) << S_T6_DFI_INIT_START)
+#define F_T6_DFI_INIT_START    V_T6_DFI_INIT_START(1U)
+
+#define S_PM_ENABLE    8
+#define M_PM_ENABLE    0xfU
+#define V_PM_ENABLE(x) ((x) << S_PM_ENABLE)
+#define G_PM_ENABLE(x) (((x) >> S_PM_ENABLE) & M_PM_ENABLE)
+
+#define S_RD_DEFREF_CNT    4
+#define M_RD_DEFREF_CNT    0xfU
+#define V_RD_DEFREF_CNT(x) ((x) << S_RD_DEFREF_CNT)
+#define G_RD_DEFREF_CNT(x) (((x) >> S_RD_DEFREF_CNT) & M_RD_DEFREF_CNT)
+
 #define A_MC_UPCTL_MSTAT 0x40088
 
 #define S_SELF_REFRESH    2
@@ -38852,6 +57129,26 @@
 #define V_T_RTP0(x) ((x) << S_T_RTP0)
 #define G_T_RTP0(x) (((x) >> S_T_RTP0) & M_T_RTP0)
 
+#define A_MC_LMC_CFGR0 0x40100
+
+#define S_ROW_WIDTH    12
+#define M_ROW_WIDTH    0x7U
+#define V_ROW_WIDTH(x) ((x) << S_ROW_WIDTH)
+#define G_ROW_WIDTH(x) (((x) >> S_ROW_WIDTH) & M_ROW_WIDTH)
+
+#define S_ADDR_MODE    8
+#define M_ADDR_MODE    0xfU
+#define V_ADDR_MODE(x) ((x) << S_ADDR_MODE)
+#define G_ADDR_MODE(x) (((x) >> S_ADDR_MODE) & M_ADDR_MODE)
+
+#define S_MIRROR    4
+#define V_MIRROR(x) ((x) << S_MIRROR)
+#define F_MIRROR    V_MIRROR(1U)
+
+#define S_RANK_ENABLE    0
+#define V_RANK_ENABLE(x) ((x) << S_RANK_ENABLE)
+#define F_RANK_ENABLE    V_RANK_ENABLE(1U)
+
 #define A_MC_UPCTL_TWR 0x40104
 
 #define S_U_T_WR    0
@@ -38916,6 +57213,26 @@
 #define V_T_CKESR(x) ((x) << S_T_CKESR)
 #define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR)
 
+#define A_MC_LMC_INITSEQ0 0x40140
+
+#define S_INIT_ENABLE    31
+#define V_INIT_ENABLE(x) ((x) << S_INIT_ENABLE)
+#define F_INIT_ENABLE    V_INIT_ENABLE(1U)
+
+#define S_WAIT    16
+#define M_WAIT    0xfffU
+#define V_WAIT(x) ((x) << S_WAIT)
+#define G_WAIT(x) (((x) >> S_WAIT) & M_WAIT)
+
+#define S_EN_MULTI_RANK_SEL    4
+#define V_EN_MULTI_RANK_SEL(x) ((x) << S_EN_MULTI_RANK_SEL)
+#define F_EN_MULTI_RANK_SEL    V_EN_MULTI_RANK_SEL(1U)
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
 #define A_MC_UPCTL_TDPD 0x40144
 
 #define S_T_DPD    0
@@ -38923,7 +57240,90 @@
 #define V_T_DPD(x) ((x) << S_T_DPD)
 #define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD)
 
+#define A_MC_LMC_CMD0 0x40144
+
+#define S_CMD    29
+#define M_CMD    0x7U
+#define V_CMD(x) ((x) << S_CMD)
+#define G_CMD(x) (((x) >> S_CMD) & M_CMD)
+
+#define S_CMD_ACTN    28
+#define V_CMD_ACTN(x) ((x) << S_CMD_ACTN)
+#define F_CMD_ACTN    V_CMD_ACTN(1U)
+
+#define S_BG1    23
+#define V_BG1(x) ((x) << S_BG1)
+#define F_BG1    V_BG1(1U)
+
+#define S_BANK    20
+#define M_BANK    0x7U
+#define V_BANK(x) ((x) << S_BANK)
+#define G_BANK(x) (((x) >> S_BANK) & M_BANK)
+
+#define A_MC_LMC_INITSEQ1 0x40148
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD1 0x4014c
+#define A_MC_LMC_INITSEQ2 0x40150
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD2 0x40154
+#define A_MC_LMC_INITSEQ3 0x40158
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD3 0x4015c
+#define A_MC_LMC_INITSEQ4 0x40160
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD4 0x40164
+#define A_MC_LMC_INITSEQ5 0x40168
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD5 0x4016c
+#define A_MC_LMC_INITSEQ6 0x40170
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD6 0x40174
+#define A_MC_LMC_INITSEQ7 0x40178
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD7 0x4017c
 #define A_MC_UPCTL_ECCCFG 0x40180
+#define A_MC_LMC_INITSEQ8 0x40180
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
 #define A_MC_UPCTL_ECCTST 0x40184
 
 #define S_ECC_TEST_MASK0    0
@@ -38931,8 +57331,65 @@
 #define V_ECC_TEST_MASK0(x) ((x) << S_ECC_TEST_MASK0)
 #define G_ECC_TEST_MASK0(x) (((x) >> S_ECC_TEST_MASK0) & M_ECC_TEST_MASK0)
 
+#define A_MC_LMC_CMD8 0x40184
 #define A_MC_UPCTL_ECCCLR 0x40188
+#define A_MC_LMC_INITSEQ9 0x40188
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
 #define A_MC_UPCTL_ECCLOG 0x4018c
+#define A_MC_LMC_CMD9 0x4018c
+#define A_MC_LMC_INITSEQ10 0x40190
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD10 0x40194
+#define A_MC_LMC_INITSEQ11 0x40198
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD11 0x4019c
+#define A_MC_LMC_INITSEQ12 0x401a0
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD12 0x401a4
+#define A_MC_LMC_INITSEQ13 0x401a8
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD13 0x401ac
+#define A_MC_LMC_INITSEQ14 0x401b0
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD14 0x401b4
+#define A_MC_LMC_INITSEQ15 0x401b8
+
+#define S_T6_RANK    0
+#define M_T6_RANK    0xfU
+#define V_T6_RANK(x) ((x) << S_T6_RANK)
+#define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
+
+#define A_MC_LMC_CMD15 0x401bc
 #define A_MC_UPCTL_DTUWACTL 0x40200
 
 #define S_DTU_WR_ROW0    13
@@ -38940,6 +57397,18 @@
 #define V_DTU_WR_ROW0(x) ((x) << S_DTU_WR_ROW0)
 #define G_DTU_WR_ROW0(x) (((x) >> S_DTU_WR_ROW0) & M_DTU_WR_ROW0)
 
+#define A_MC_LMC_SDTR0 0x40200
+
+#define S_REFI    16
+#define M_REFI    0xffffU
+#define V_REFI(x) ((x) << S_REFI)
+#define G_REFI(x) (((x) >> S_REFI) & M_REFI)
+
+#define S_T_RFC_XPR    0
+#define M_T_RFC_XPR    0xfffU
+#define V_T_RFC_XPR(x) ((x) << S_T_RFC_XPR)
+#define G_T_RFC_XPR(x) (((x) >> S_T_RFC_XPR) & M_T_RFC_XPR)
+
 #define A_MC_UPCTL_DTURACTL 0x40204
 
 #define S_DTU_RD_ROW0    13
@@ -38947,15 +57416,177 @@
 #define V_DTU_RD_ROW0(x) ((x) << S_DTU_RD_ROW0)
 #define G_DTU_RD_ROW0(x) (((x) >> S_DTU_RD_ROW0) & M_DTU_RD_ROW0)
 
+#define A_MC_LMC_SDTR1 0x40204
+
+#define S_T_LEADOFF    31
+#define V_T_LEADOFF(x) ((x) << S_T_LEADOFF)
+#define F_T_LEADOFF    V_T_LEADOFF(1U)
+
+#define S_ODT_DELAY    30
+#define V_ODT_DELAY(x) ((x) << S_ODT_DELAY)
+#define F_ODT_DELAY    V_ODT_DELAY(1U)
+
+#define S_ODT_WIDTH    29
+#define V_ODT_WIDTH(x) ((x) << S_ODT_WIDTH)
+#define F_ODT_WIDTH    V_ODT_WIDTH(1U)
+
+#define S_T_WTRO    24
+#define M_T_WTRO    0xfU
+#define V_T_WTRO(x) ((x) << S_T_WTRO)
+#define G_T_WTRO(x) (((x) >> S_T_WTRO) & M_T_WTRO)
+
+#define S_T_RTWO    16
+#define M_T_RTWO    0xfU
+#define V_T_RTWO(x) ((x) << S_T_RTWO)
+#define G_T_RTWO(x) (((x) >> S_T_RTWO) & M_T_RTWO)
+
+#define S_T_RTW_ADJ    12
+#define M_T_RTW_ADJ    0xfU
+#define V_T_RTW_ADJ(x) ((x) << S_T_RTW_ADJ)
+#define G_T_RTW_ADJ(x) (((x) >> S_T_RTW_ADJ) & M_T_RTW_ADJ)
+
+#define S_T_WTWO    8
+#define M_T_WTWO    0xfU
+#define V_T_WTWO(x) ((x) << S_T_WTWO)
+#define G_T_WTWO(x) (((x) >> S_T_WTWO) & M_T_WTWO)
+
+#define S_T_RTRO    0
+#define M_T_RTRO    0xfU
+#define V_T_RTRO(x) ((x) << S_T_RTRO)
+#define G_T_RTRO(x) (((x) >> S_T_RTRO) & M_T_RTRO)
+
 #define A_MC_UPCTL_DTUCFG 0x40208
+#define A_MC_LMC_SDTR2 0x40208
+
+#define S_T6_T_CWL    28
+#define M_T6_T_CWL    0xfU
+#define V_T6_T_CWL(x) ((x) << S_T6_T_CWL)
+#define G_T6_T_CWL(x) (((x) >> S_T6_T_CWL) & M_T6_T_CWL)
+
+#define S_T_RCD0    24
+#define M_T_RCD0    0xfU
+#define V_T_RCD0(x) ((x) << S_T_RCD0)
+#define G_T_RCD0(x) (((x) >> S_T_RCD0) & M_T_RCD0)
+
+#define S_T_PL    20
+#define M_T_PL    0xfU
+#define V_T_PL(x) ((x) << S_T_PL)
+#define G_T_PL(x) (((x) >> S_T_PL) & M_T_PL)
+
+#define S_T_RP0    16
+#define M_T_RP0    0xfU
+#define V_T_RP0(x) ((x) << S_T_RP0)
+#define G_T_RP0(x) (((x) >> S_T_RP0) & M_T_RP0)
+
+#define S_T_RP1    15
+#define V_T_RP1(x) ((x) << S_T_RP1)
+#define F_T_RP1    V_T_RP1(1U)
+
+#define S_T_RCD1    14
+#define V_T_RCD1(x) ((x) << S_T_RCD1)
+#define F_T_RCD1    V_T_RCD1(1U)
+
+#define S_T6_T_RC    8
+#define M_T6_T_RC    0x3fU
+#define V_T6_T_RC(x) ((x) << S_T6_T_RC)
+#define G_T6_T_RC(x) (((x) >> S_T6_T_RC) & M_T6_T_RC)
+
 #define A_MC_UPCTL_DTUECTL 0x4020c
+#define A_MC_LMC_SDTR3 0x4020c
+
+#define S_T_WTR_S    28
+#define M_T_WTR_S    0xfU
+#define V_T_WTR_S(x) ((x) << S_T_WTR_S)
+#define G_T_WTR_S(x) (((x) >> S_T_WTR_S) & M_T_WTR_S)
+
+#define S_T6_T_WTR    24
+#define M_T6_T_WTR    0xfU
+#define V_T6_T_WTR(x) ((x) << S_T6_T_WTR)
+#define G_T6_T_WTR(x) (((x) >> S_T6_T_WTR) & M_T6_T_WTR)
+
+#define S_FAW_ADJ    20
+#define M_FAW_ADJ    0x3U
+#define V_FAW_ADJ(x) ((x) << S_FAW_ADJ)
+#define G_FAW_ADJ(x) (((x) >> S_FAW_ADJ) & M_FAW_ADJ)
+
+#define S_T6_T_RTP    16
+#define M_T6_T_RTP    0xfU
+#define V_T6_T_RTP(x) ((x) << S_T6_T_RTP)
+#define G_T6_T_RTP(x) (((x) >> S_T6_T_RTP) & M_T6_T_RTP)
+
+#define S_T_RRD_L    12
+#define M_T_RRD_L    0xfU
+#define V_T_RRD_L(x) ((x) << S_T_RRD_L)
+#define G_T_RRD_L(x) (((x) >> S_T_RRD_L) & M_T_RRD_L)
+
+#define S_T6_T_RRD    8
+#define M_T6_T_RRD    0xfU
+#define V_T6_T_RRD(x) ((x) << S_T6_T_RRD)
+#define G_T6_T_RRD(x) (((x) >> S_T6_T_RRD) & M_T6_T_RRD)
+
+#define S_T_XSDLL    0
+#define M_T_XSDLL    0xffU
+#define V_T_XSDLL(x) ((x) << S_T_XSDLL)
+#define G_T_XSDLL(x) (((x) >> S_T_XSDLL) & M_T_XSDLL)
+
 #define A_MC_UPCTL_DTUWD0 0x40210
+#define A_MC_LMC_SDTR4 0x40210
+
+#define S_T_RDDATA_EN    24
+#define M_T_RDDATA_EN    0x7fU
+#define V_T_RDDATA_EN(x) ((x) << S_T_RDDATA_EN)
+#define G_T_RDDATA_EN(x) (((x) >> S_T_RDDATA_EN) & M_T_RDDATA_EN)
+
+#define S_T_SYS_RDLAT    16
+#define M_T_SYS_RDLAT    0x3fU
+#define V_T_SYS_RDLAT(x) ((x) << S_T_SYS_RDLAT)
+#define G_T_SYS_RDLAT(x) (((x) >> S_T_SYS_RDLAT) & M_T_SYS_RDLAT)
+
+#define S_T_CCD_L    12
+#define M_T_CCD_L    0xfU
+#define V_T_CCD_L(x) ((x) << S_T_CCD_L)
+#define G_T_CCD_L(x) (((x) >> S_T_CCD_L) & M_T_CCD_L)
+
+#define S_T_CCD    8
+#define M_T_CCD    0x7U
+#define V_T_CCD(x) ((x) << S_T_CCD)
+#define G_T_CCD(x) (((x) >> S_T_CCD) & M_T_CCD)
+
+#define S_T_CPDED    5
+#define M_T_CPDED    0x7U
+#define V_T_CPDED(x) ((x) << S_T_CPDED)
+#define G_T_CPDED(x) (((x) >> S_T_CPDED) & M_T_CPDED)
+
+#define S_T6_T_MOD    0
+#define M_T6_T_MOD    0x1fU
+#define V_T6_T_MOD(x) ((x) << S_T6_T_MOD)
+#define G_T6_T_MOD(x) (((x) >> S_T6_T_MOD) & M_T6_T_MOD)
+
 #define A_MC_UPCTL_DTUWD1 0x40214
+#define A_MC_LMC_SDTR5 0x40214
+
+#define S_T_PHY_WRDATA    24
+#define M_T_PHY_WRDATA    0x7U
+#define V_T_PHY_WRDATA(x) ((x) << S_T_PHY_WRDATA)
+#define G_T_PHY_WRDATA(x) (((x) >> S_T_PHY_WRDATA) & M_T_PHY_WRDATA)
+
+#define S_T_PHY_WRLAT    16
+#define M_T_PHY_WRLAT    0x1fU
+#define V_T_PHY_WRLAT(x) ((x) << S_T_PHY_WRLAT)
+#define G_T_PHY_WRLAT(x) (((x) >> S_T_PHY_WRLAT) & M_T_PHY_WRLAT)
+
 #define A_MC_UPCTL_DTUWD2 0x40218
 #define A_MC_UPCTL_DTUWD3 0x4021c
 #define A_MC_UPCTL_DTUWDM 0x40220
 #define A_MC_UPCTL_DTURD0 0x40224
 #define A_MC_UPCTL_DTURD1 0x40228
+#define A_MC_LMC_DBG0 0x40228
+
+#define S_T_SYS_RDLAT_DBG    16
+#define M_T_SYS_RDLAT_DBG    0x1fU
+#define V_T_SYS_RDLAT_DBG(x) ((x) << S_T_SYS_RDLAT_DBG)
+#define G_T_SYS_RDLAT_DBG(x) (((x) >> S_T_SYS_RDLAT_DBG) & M_T_SYS_RDLAT_DBG)
+
 #define A_MC_UPCTL_DTURD2 0x4022c
 #define A_MC_UPCTL_DTURD3 0x40230
 #define A_MC_UPCTL_DTULFSRWD 0x40234
@@ -38974,12 +57605,105 @@
 #define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY)
 #define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY)
 
+#define A_MC_LMC_SMR0 0x40240
+
+#define S_SMR0_RFU0    13
+#define M_SMR0_RFU0    0x7U
+#define V_SMR0_RFU0(x) ((x) << S_SMR0_RFU0)
+#define G_SMR0_RFU0(x) (((x) >> S_SMR0_RFU0) & M_SMR0_RFU0)
+
+#define S_PPD    12
+#define V_PPD(x) ((x) << S_PPD)
+#define F_PPD    V_PPD(1U)
+
+#define S_WR_RTP    9
+#define M_WR_RTP    0x7U
+#define V_WR_RTP(x) ((x) << S_WR_RTP)
+#define G_WR_RTP(x) (((x) >> S_WR_RTP) & M_WR_RTP)
+
+#define S_SMR0_DLL    8
+#define V_SMR0_DLL(x) ((x) << S_SMR0_DLL)
+#define F_SMR0_DLL    V_SMR0_DLL(1U)
+
+#define S_TM    7
+#define V_TM(x) ((x) << S_TM)
+#define F_TM    V_TM(1U)
+
+#define S_CL31    4
+#define M_CL31    0x7U
+#define V_CL31(x) ((x) << S_CL31)
+#define G_CL31(x) (((x) >> S_CL31) & M_CL31)
+
+#define S_RBT    3
+#define V_RBT(x) ((x) << S_RBT)
+#define F_RBT    V_RBT(1U)
+
+#define S_CL0    2
+#define V_CL0(x) ((x) << S_CL0)
+#define F_CL0    V_CL0(1U)
+
+#define S_BL    0
+#define M_BL    0x3U
+#define V_BL(x) ((x) << S_BL)
+#define G_BL(x) (((x) >> S_BL) & M_BL)
+
 #define A_MC_UPCTL_DFIODTCFG 0x40244
 
 #define S_RANK3_ODT_WRITE_NSEL    26
 #define V_RANK3_ODT_WRITE_NSEL(x) ((x) << S_RANK3_ODT_WRITE_NSEL)
 #define F_RANK3_ODT_WRITE_NSEL    V_RANK3_ODT_WRITE_NSEL(1U)
 
+#define A_MC_LMC_SMR1 0x40244
+
+#define S_QOFF    12
+#define V_QOFF(x) ((x) << S_QOFF)
+#define F_QOFF    V_QOFF(1U)
+
+#define S_TDQS    11
+#define V_TDQS(x) ((x) << S_TDQS)
+#define F_TDQS    V_TDQS(1U)
+
+#define S_SMR1_RFU0    10
+#define V_SMR1_RFU0(x) ((x) << S_SMR1_RFU0)
+#define F_SMR1_RFU0    V_SMR1_RFU0(1U)
+
+#define S_RTT_NOM0    9
+#define V_RTT_NOM0(x) ((x) << S_RTT_NOM0)
+#define F_RTT_NOM0    V_RTT_NOM0(1U)
+
+#define S_SMR1_RFU1    8
+#define V_SMR1_RFU1(x) ((x) << S_SMR1_RFU1)
+#define F_SMR1_RFU1    V_SMR1_RFU1(1U)
+
+#define S_WR_LEVEL    7
+#define V_WR_LEVEL(x) ((x) << S_WR_LEVEL)
+#define F_WR_LEVEL    V_WR_LEVEL(1U)
+
+#define S_RTT_NOM1    6
+#define V_RTT_NOM1(x) ((x) << S_RTT_NOM1)
+#define F_RTT_NOM1    V_RTT_NOM1(1U)
+
+#define S_DIC0    5
+#define V_DIC0(x) ((x) << S_DIC0)
+#define F_DIC0    V_DIC0(1U)
+
+#define S_AL    3
+#define M_AL    0x3U
+#define V_AL(x) ((x) << S_AL)
+#define G_AL(x) (((x) >> S_AL) & M_AL)
+
+#define S_RTT_NOM2    2
+#define V_RTT_NOM2(x) ((x) << S_RTT_NOM2)
+#define F_RTT_NOM2    V_RTT_NOM2(1U)
+
+#define S_DIC1    1
+#define V_DIC1(x) ((x) << S_DIC1)
+#define F_DIC1    V_DIC1(1U)
+
+#define S_SMR1_DLL    0
+#define V_SMR1_DLL(x) ((x) << S_SMR1_DLL)
+#define F_SMR1_DLL    V_SMR1_DLL(1U)
+
 #define A_MC_UPCTL_DFIODTCFG1 0x40248
 
 #define S_ODT_LEN_B8_R    24
@@ -39002,6 +57726,43 @@
 #define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W)
 #define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W)
 
+#define A_MC_LMC_SMR2 0x40248
+
+#define S_WR_CRC    12
+#define V_WR_CRC(x) ((x) << S_WR_CRC)
+#define F_WR_CRC    V_WR_CRC(1U)
+
+#define S_RD_CRC    11
+#define V_RD_CRC(x) ((x) << S_RD_CRC)
+#define F_RD_CRC    V_RD_CRC(1U)
+
+#define S_RTT_WR    9
+#define M_RTT_WR    0x3U
+#define V_RTT_WR(x) ((x) << S_RTT_WR)
+#define G_RTT_WR(x) (((x) >> S_RTT_WR) & M_RTT_WR)
+
+#define S_SMR2_RFU0    8
+#define V_SMR2_RFU0(x) ((x) << S_SMR2_RFU0)
+#define F_SMR2_RFU0    V_SMR2_RFU0(1U)
+
+#define S_SRT_ASR1    7
+#define V_SRT_ASR1(x) ((x) << S_SRT_ASR1)
+#define F_SRT_ASR1    V_SRT_ASR1(1U)
+
+#define S_ASR0    6
+#define V_ASR0(x) ((x) << S_ASR0)
+#define F_ASR0    V_ASR0(1U)
+
+#define S_CWL    3
+#define M_CWL    0x7U
+#define V_CWL(x) ((x) << S_CWL)
+#define G_CWL(x) (((x) >> S_CWL) & M_CWL)
+
+#define S_PASR    0
+#define M_PASR    0x7U
+#define V_PASR(x) ((x) << S_PASR)
+#define G_PASR(x) (((x) >> S_PASR) & M_PASR)
+
 #define A_MC_UPCTL_DFIODTRANKMAP 0x4024c
 
 #define S_ODT_RANK_MAP3    12
@@ -39024,6 +57785,44 @@
 #define V_ODT_RANK_MAP0(x) ((x) << S_ODT_RANK_MAP0)
 #define G_ODT_RANK_MAP0(x) (((x) >> S_ODT_RANK_MAP0) & M_ODT_RANK_MAP0)
 
+#define A_MC_LMC_SMR3 0x4024c
+
+#define S_MPR_RD_FMT    11
+#define M_MPR_RD_FMT    0x3U
+#define V_MPR_RD_FMT(x) ((x) << S_MPR_RD_FMT)
+#define G_MPR_RD_FMT(x) (((x) >> S_MPR_RD_FMT) & M_MPR_RD_FMT)
+
+#define S_SMR3_RFU0    9
+#define M_SMR3_RFU0    0x3U
+#define V_SMR3_RFU0(x) ((x) << S_SMR3_RFU0)
+#define G_SMR3_RFU0(x) (((x) >> S_SMR3_RFU0) & M_SMR3_RFU0)
+
+#define S_FGR_MODE    6
+#define M_FGR_MODE    0x7U
+#define V_FGR_MODE(x) ((x) << S_FGR_MODE)
+#define G_FGR_MODE(x) (((x) >> S_FGR_MODE) & M_FGR_MODE)
+
+#define S_MRS_RDO    5
+#define V_MRS_RDO(x) ((x) << S_MRS_RDO)
+#define F_MRS_RDO    V_MRS_RDO(1U)
+
+#define S_DRAM_ADR    4
+#define V_DRAM_ADR(x) ((x) << S_DRAM_ADR)
+#define F_DRAM_ADR    V_DRAM_ADR(1U)
+
+#define S_GD_MODE    3
+#define V_GD_MODE(x) ((x) << S_GD_MODE)
+#define F_GD_MODE    V_GD_MODE(1U)
+
+#define S_MPR    2
+#define V_MPR(x) ((x) << S_MPR)
+#define F_MPR    V_MPR(1U)
+
+#define S_MPR_SEL    0
+#define M_MPR_SEL    0x3U
+#define V_MPR_SEL(x) ((x) << S_MPR_SEL)
+#define G_MPR_SEL(x) (((x) >> S_MPR_SEL) & M_MPR_SEL)
+
 #define A_MC_UPCTL_DFITPHYWRDATA 0x40250
 
 #define S_TPHY_WRDATA    0
@@ -39031,6 +57830,53 @@
 #define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA)
 #define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA)
 
+#define A_MC_LMC_SMR4 0x40250
+
+#define S_WR_PRE    12
+#define V_WR_PRE(x) ((x) << S_WR_PRE)
+#define F_WR_PRE    V_WR_PRE(1U)
+
+#define S_RD_PRE    11
+#define V_RD_PRE(x) ((x) << S_RD_PRE)
+#define F_RD_PRE    V_RD_PRE(1U)
+
+#define S_RPT_MODE    10
+#define V_RPT_MODE(x) ((x) << S_RPT_MODE)
+#define F_RPT_MODE    V_RPT_MODE(1U)
+
+#define S_FESR_MODE    9
+#define V_FESR_MODE(x) ((x) << S_FESR_MODE)
+#define F_FESR_MODE    V_FESR_MODE(1U)
+
+#define S_CS_LAT_MODE    6
+#define M_CS_LAT_MODE    0x7U
+#define V_CS_LAT_MODE(x) ((x) << S_CS_LAT_MODE)
+#define G_CS_LAT_MODE(x) (((x) >> S_CS_LAT_MODE) & M_CS_LAT_MODE)
+
+#define S_ALERT_STAT    5
+#define V_ALERT_STAT(x) ((x) << S_ALERT_STAT)
+#define F_ALERT_STAT    V_ALERT_STAT(1U)
+
+#define S_IVM_MODE    4
+#define V_IVM_MODE(x) ((x) << S_IVM_MODE)
+#define F_IVM_MODE    V_IVM_MODE(1U)
+
+#define S_TCR_MODE    3
+#define V_TCR_MODE(x) ((x) << S_TCR_MODE)
+#define F_TCR_MODE    V_TCR_MODE(1U)
+
+#define S_TCR_RANGE    2
+#define V_TCR_RANGE(x) ((x) << S_TCR_RANGE)
+#define F_TCR_RANGE    V_TCR_RANGE(1U)
+
+#define S_MPD_MODE    1
+#define V_MPD_MODE(x) ((x) << S_MPD_MODE)
+#define F_MPD_MODE    V_MPD_MODE(1U)
+
+#define S_SMR4_RFU    0
+#define V_SMR4_RFU(x) ((x) << S_SMR4_RFU)
+#define F_SMR4_RFU    V_SMR4_RFU(1U)
+
 #define A_MC_UPCTL_DFITPHYWRLAT 0x40254
 
 #define S_TPHY_WRLAT    0
@@ -39038,6 +57884,63 @@
 #define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT)
 #define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT)
 
+#define A_MC_LMC_SMR5 0x40254
+
+#define S_RD_DBI    11
+#define V_RD_DBI(x) ((x) << S_RD_DBI)
+#define F_RD_DBI    V_RD_DBI(1U)
+
+#define S_WR_DBI    10
+#define V_WR_DBI(x) ((x) << S_WR_DBI)
+#define F_WR_DBI    V_WR_DBI(1U)
+
+#define S_DM_MODE    9
+#define V_DM_MODE(x) ((x) << S_DM_MODE)
+#define F_DM_MODE    V_DM_MODE(1U)
+
+#define S_RTT_PARK    6
+#define M_RTT_PARK    0x7U
+#define V_RTT_PARK(x) ((x) << S_RTT_PARK)
+#define G_RTT_PARK(x) (((x) >> S_RTT_PARK) & M_RTT_PARK)
+
+#define S_SMR5_RFU    5
+#define V_SMR5_RFU(x) ((x) << S_SMR5_RFU)
+#define F_SMR5_RFU    V_SMR5_RFU(1U)
+
+#define S_PAR_ERR_STAT    4
+#define V_PAR_ERR_STAT(x) ((x) << S_PAR_ERR_STAT)
+#define F_PAR_ERR_STAT    V_PAR_ERR_STAT(1U)
+
+#define S_CRC_CLEAR    3
+#define V_CRC_CLEAR(x) ((x) << S_CRC_CLEAR)
+#define F_CRC_CLEAR    V_CRC_CLEAR(1U)
+
+#define S_PAR_LAT_MODE    0
+#define M_PAR_LAT_MODE    0x7U
+#define V_PAR_LAT_MODE(x) ((x) << S_PAR_LAT_MODE)
+#define G_PAR_LAT_MODE(x) (((x) >> S_PAR_LAT_MODE) & M_PAR_LAT_MODE)
+
+#define A_MC_LMC_SMR6 0x40258
+
+#define S_TCCD_L    10
+#define M_TCCD_L    0x7U
+#define V_TCCD_L(x) ((x) << S_TCCD_L)
+#define G_TCCD_L(x) (((x) >> S_TCCD_L) & M_TCCD_L)
+
+#define S_SRM6_RFU    7
+#define M_SRM6_RFU    0x7U
+#define V_SRM6_RFU(x) ((x) << S_SRM6_RFU)
+#define G_SRM6_RFU(x) (((x) >> S_SRM6_RFU) & M_SRM6_RFU)
+
+#define S_VREF_DQ_RANGE    6
+#define V_VREF_DQ_RANGE(x) ((x) << S_VREF_DQ_RANGE)
+#define F_VREF_DQ_RANGE    V_VREF_DQ_RANGE(1U)
+
+#define S_VREF_DQ_VALUE    0
+#define M_VREF_DQ_VALUE    0x3fU
+#define V_VREF_DQ_VALUE(x) ((x) << S_VREF_DQ_VALUE)
+#define G_VREF_DQ_VALUE(x) (((x) >> S_VREF_DQ_VALUE) & M_VREF_DQ_VALUE)
+
 #define A_MC_UPCTL_DFITRDDATAEN 0x40260
 
 #define S_TRDDATA_EN    0
@@ -39087,6 +57990,16 @@
 #define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN)
 #define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN)
 
+#define A_MC_LMC_ODTR0 0x40280
+
+#define S_RK0W    25
+#define V_RK0W(x) ((x) << S_RK0W)
+#define F_RK0W    V_RK0W(1U)
+
+#define S_RK0R    24
+#define V_RK0R(x) ((x) << S_RK0R)
+#define F_RK0R    V_RK0R(1U)
+
 #define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284
 
 #define S_TCTRLUPD_MAX    0
@@ -39284,6 +58197,17 @@
 
 #define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300
 #define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304
+#define A_MC_LMC_CALSTAT 0x40304
+
+#define S_PHYUPD_ERR    28
+#define M_PHYUPD_ERR    0xfU
+#define V_PHYUPD_ERR(x) ((x) << S_PHYUPD_ERR)
+#define G_PHYUPD_ERR(x) (((x) >> S_PHYUPD_ERR) & M_PHYUPD_ERR)
+
+#define S_PHYUPD_BUSY    27
+#define V_PHYUPD_BUSY(x) ((x) << S_PHYUPD_BUSY)
+#define F_PHYUPD_BUSY    V_PHYUPD_BUSY(1U)
+
 #define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308
 
 #define S_DFI_WRLVL_RESP2    0
@@ -39319,7 +58243,9 @@
 #define G_DFI_RDLVL_DELAY2(x) (((x) >> S_DFI_RDLVL_DELAY2) & M_DFI_RDLVL_DELAY2)
 
 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330
+#define A_MC_LMC_T_PHYUPD0 0x40330
 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334
+#define A_MC_LMC_T_PHYUPD1 0x40334
 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338
 
 #define S_DFI_RDLVL_GATE_DELAY2    0
@@ -39327,6 +58253,7 @@
 #define V_DFI_RDLVL_GATE_DELAY2(x) ((x) << S_DFI_RDLVL_GATE_DELAY2)
 #define G_DFI_RDLVL_GATE_DELAY2(x) (((x) >> S_DFI_RDLVL_GATE_DELAY2) & M_DFI_RDLVL_GATE_DELAY2)
 
+#define A_MC_LMC_T_PHYUPD2 0x40338
 #define A_MC_UPCTL_DFITRCMD 0x4033c
 
 #define S_DFITRCMD_START    31
@@ -39343,6 +58270,7 @@
 #define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE)
 #define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE)
 
+#define A_MC_LMC_T_PHYUPD3 0x4033c
 #define A_MC_UPCTL_IPVR 0x403f8
 #define A_MC_UPCTL_IPTR 0x403fc
 #define A_MC_P_DDRPHY_RST_CTRL 0x41300
@@ -39368,7 +58296,47 @@
 #define V_CTL_RST_N(x) ((x) << S_CTL_RST_N)
 #define F_CTL_RST_N    V_CTL_RST_N(1U)
 
+#define S_PHY_CAL_REQ    21
+#define V_PHY_CAL_REQ(x) ((x) << S_PHY_CAL_REQ)
+#define F_PHY_CAL_REQ    V_PHY_CAL_REQ(1U)
+
+#define S_T6_PHY_DRAM_WL    17
+#define M_T6_PHY_DRAM_WL    0xfU
+#define V_T6_PHY_DRAM_WL(x) ((x) << S_T6_PHY_DRAM_WL)
+#define G_T6_PHY_DRAM_WL(x) (((x) >> S_T6_PHY_DRAM_WL) & M_T6_PHY_DRAM_WL)
+
 #define A_MC_P_PERFORMANCE_CTRL 0x41304
+
+#define S_BUF_USE_TH    12
+#define M_BUF_USE_TH    0x7U
+#define V_BUF_USE_TH(x) ((x) << S_BUF_USE_TH)
+#define G_BUF_USE_TH(x) (((x) >> S_BUF_USE_TH) & M_BUF_USE_TH)
+
+#define S_MC_IDLE_TH    8
+#define M_MC_IDLE_TH    0xfU
+#define V_MC_IDLE_TH(x) ((x) << S_MC_IDLE_TH)
+#define G_MC_IDLE_TH(x) (((x) >> S_MC_IDLE_TH) & M_MC_IDLE_TH)
+
+#define S_RMW_DEFER_EN    7
+#define V_RMW_DEFER_EN(x) ((x) << S_RMW_DEFER_EN)
+#define F_RMW_DEFER_EN    V_RMW_DEFER_EN(1U)
+
+#define S_DDR3_BRBC_MODE    6
+#define V_DDR3_BRBC_MODE(x) ((x) << S_DDR3_BRBC_MODE)
+#define F_DDR3_BRBC_MODE    V_DDR3_BRBC_MODE(1U)
+
+#define S_RMW_DWRITE_EN    5
+#define V_RMW_DWRITE_EN(x) ((x) << S_RMW_DWRITE_EN)
+#define F_RMW_DWRITE_EN    V_RMW_DWRITE_EN(1U)
+
+#define S_RMW_MERGE_EN    4
+#define V_RMW_MERGE_EN(x) ((x) << S_RMW_MERGE_EN)
+#define F_RMW_MERGE_EN    V_RMW_MERGE_EN(1U)
+
+#define S_SYNC_PAB_EN    3
+#define V_SYNC_PAB_EN(x) ((x) << S_SYNC_PAB_EN)
+#define F_SYNC_PAB_EN    V_SYNC_PAB_EN(1U)
+
 #define A_MC_P_ECC_CTRL 0x41308
 #define A_MC_P_PAR_ENABLE 0x4130c
 #define A_MC_P_PAR_CAUSE 0x41310
@@ -39404,6 +58372,18 @@
 #define V_STATIC_LAT(x) ((x) << S_STATIC_LAT)
 #define F_STATIC_LAT    V_STATIC_LAT(1U)
 
+#define S_STATIC_PP64    26
+#define V_STATIC_PP64(x) ((x) << S_STATIC_PP64)
+#define F_STATIC_PP64    V_STATIC_PP64(1U)
+
+#define S_STATIC_PPEN    25
+#define V_STATIC_PPEN(x) ((x) << S_STATIC_PPEN)
+#define F_STATIC_PPEN    V_STATIC_PPEN(1U)
+
+#define S_STATIC_OOOEN    24
+#define V_STATIC_OOOEN(x) ((x) << S_STATIC_OOOEN)
+#define F_STATIC_OOOEN    V_STATIC_OOOEN(1U)
+
 #define A_MC_P_CORE_PCTL_STAT 0x41328
 #define A_MC_P_DEBUG_CNT 0x4132c
 #define A_MC_CE_ERR_DATA_RDATA 0x41330
@@ -39425,6 +58405,38 @@
 #define A_MC_P_FPGA_BONUS 0x413bc
 #define A_MC_P_DEBUG_CFG 0x413c0
 #define A_MC_P_DEBUG_RPT 0x413c4
+#define A_MC_P_PHY_ADR_CK_EN 0x413c8
+
+#define S_ADR_CK_EN    0
+#define V_ADR_CK_EN(x) ((x) << S_ADR_CK_EN)
+#define F_ADR_CK_EN    V_ADR_CK_EN(1U)
+
+#define A_MC_CE_ERR_ECC_DATA0 0x413d0
+#define A_MC_CE_ERR_ECC_DATA1 0x413d4
+#define A_MC_UE_ERR_ECC_DATA0 0x413d8
+#define A_MC_UE_ERR_ECC_DATA1 0x413dc
+#define A_MC_P_RMW_PRIO 0x413f0
+
+#define S_WR_HI_TH    24
+#define M_WR_HI_TH    0xffU
+#define V_WR_HI_TH(x) ((x) << S_WR_HI_TH)
+#define G_WR_HI_TH(x) (((x) >> S_WR_HI_TH) & M_WR_HI_TH)
+
+#define S_WR_MID_TH    16
+#define M_WR_MID_TH    0xffU
+#define V_WR_MID_TH(x) ((x) << S_WR_MID_TH)
+#define G_WR_MID_TH(x) (((x) >> S_WR_MID_TH) & M_WR_MID_TH)
+
+#define S_RD_HI_TH    8
+#define M_RD_HI_TH    0xffU
+#define V_RD_HI_TH(x) ((x) << S_RD_HI_TH)
+#define G_RD_HI_TH(x) (((x) >> S_RD_HI_TH) & M_RD_HI_TH)
+
+#define S_RD_MID_TH    0
+#define M_RD_MID_TH    0xffU
+#define V_RD_MID_TH(x) ((x) << S_RD_MID_TH)
+#define G_RD_MID_TH(x) (((x) >> S_RD_MID_TH) & M_RD_MID_TH)
+
 #define A_MC_P_BIST_CMD 0x41400
 
 #define S_BURST_LEN    16
@@ -39436,7 +58448,9 @@
 #define A_MC_P_BIST_CMD_LEN 0x41408
 #define A_MC_P_BIST_DATA_PATTERN 0x4140c
 #define A_MC_P_BIST_USER_WDATA0 0x41414
+#define A_MC_P_BIST_USER_WMASK0 0x41414
 #define A_MC_P_BIST_USER_WDATA1 0x41418
+#define A_MC_P_BIST_USER_WMASK1 0x41418
 #define A_MC_P_BIST_USER_WDATA2 0x4141c
 
 #define S_USER_DATA_MASK    8
@@ -39444,6 +58458,21 @@
 #define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK)
 #define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK)
 
+#define A_MC_P_BIST_USER_WMASK2 0x4141c
+
+#define S_MASK_128_1    9
+#define V_MASK_128_1(x) ((x) << S_MASK_128_1)
+#define F_MASK_128_1    V_MASK_128_1(1U)
+
+#define S_MASK_128_0    8
+#define V_MASK_128_0(x) ((x) << S_MASK_128_0)
+#define F_MASK_128_0    V_MASK_128_0(1U)
+
+#define S_USER_MASK_ECC    0
+#define M_USER_MASK_ECC    0xffU
+#define V_USER_MASK_ECC(x) ((x) << S_USER_MASK_ECC)
+#define G_USER_MASK_ECC(x) (((x) >> S_USER_MASK_ECC) & M_USER_MASK_ECC)
+
 #define A_MC_P_BIST_NUM_ERR 0x41480
 #define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484
 #define A_MC_P_BIST_STATUS_RDATA 0x41488
@@ -39490,6 +58519,14 @@
 #define V_MRS_CMD_DATA_N3(x) ((x) << S_MRS_CMD_DATA_N3)
 #define F_MRS_CMD_DATA_N3    V_MRS_CMD_DATA_N3(1U)
 
+#define S_DP18_WRAPSEL    5
+#define V_DP18_WRAPSEL(x) ((x) << S_DP18_WRAPSEL)
+#define F_DP18_WRAPSEL    V_DP18_WRAPSEL(1U)
+
+#define S_HW_VALUE    4
+#define V_HW_VALUE(x) ((x) << S_HW_VALUE)
+#define F_HW_VALUE    V_HW_VALUE(1U)
+
 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008
 
 #define S_DATA_BIT_DIR_0_15    0
@@ -39743,6 +58780,16 @@
 #define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL)
 #define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL)
 
+#define S_DP18_HS_PROBE_A_SEL    11
+#define M_DP18_HS_PROBE_A_SEL    0x1fU
+#define V_DP18_HS_PROBE_A_SEL(x) ((x) << S_DP18_HS_PROBE_A_SEL)
+#define G_DP18_HS_PROBE_A_SEL(x) (((x) >> S_DP18_HS_PROBE_A_SEL) & M_DP18_HS_PROBE_A_SEL)
+
+#define S_DP18_HS_PROBE_B_SEL    6
+#define M_DP18_HS_PROBE_B_SEL    0x1fU
+#define V_DP18_HS_PROBE_B_SEL(x) ((x) << S_DP18_HS_PROBE_B_SEL)
+#define G_DP18_HS_PROBE_B_SEL(x) (((x) >> S_DP18_HS_PROBE_B_SEL) & M_DP18_HS_PROBE_B_SEL)
+
 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030
 
 #define S_OFFSET_BITS1_7    8
@@ -39806,6 +58853,10 @@
 #define V_PER_RDCLK_UPDATE_DIS(x) ((x) << S_PER_RDCLK_UPDATE_DIS)
 #define F_PER_RDCLK_UPDATE_DIS    V_PER_RDCLK_UPDATE_DIS(1U)
 
+#define S_DQS_ALIGN_BY_QUAD    4
+#define V_DQS_ALIGN_BY_QUAD(x) ((x) << S_DQS_ALIGN_BY_QUAD)
+#define F_DQS_ALIGN_BY_QUAD    V_DQS_ALIGN_BY_QUAD(1U)
+
 #define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c
 
 #define S_DQS_GATE_DELAY_N0    12
@@ -39960,6 +59011,38 @@
 #define V_MIN_EYE_MASK(x) ((x) << S_MIN_EYE_MASK)
 #define F_MIN_EYE_MASK    V_MIN_EYE_MASK(1U)
 
+#define A_MC_DDRPHY_DP18_WRCLK_CNTL 0x44058
+
+#define S_PRBS_WAIT    14
+#define M_PRBS_WAIT    0x3U
+#define V_PRBS_WAIT(x) ((x) << S_PRBS_WAIT)
+#define G_PRBS_WAIT(x) (((x) >> S_PRBS_WAIT) & M_PRBS_WAIT)
+
+#define S_PRBS_SYNC_EARLY    13
+#define V_PRBS_SYNC_EARLY(x) ((x) << S_PRBS_SYNC_EARLY)
+#define F_PRBS_SYNC_EARLY    V_PRBS_SYNC_EARLY(1U)
+
+#define S_RD_DELAY_EARLY    12
+#define V_RD_DELAY_EARLY(x) ((x) << S_RD_DELAY_EARLY)
+#define F_RD_DELAY_EARLY    V_RD_DELAY_EARLY(1U)
+
+#define S_SS_QUAD_CAL    10
+#define V_SS_QUAD_CAL(x) ((x) << S_SS_QUAD_CAL)
+#define F_SS_QUAD_CAL    V_SS_QUAD_CAL(1U)
+
+#define S_SS_QUAD    8
+#define M_SS_QUAD    0x3U
+#define V_SS_QUAD(x) ((x) << S_SS_QUAD)
+#define G_SS_QUAD(x) (((x) >> S_SS_QUAD) & M_SS_QUAD)
+
+#define S_SS_RD_DELAY    7
+#define V_SS_RD_DELAY(x) ((x) << S_SS_RD_DELAY)
+#define F_SS_RD_DELAY    V_SS_RD_DELAY(1U)
+
+#define S_FORCE_HI_Z    6
+#define V_FORCE_HI_Z(x) ((x) << S_FORCE_HI_Z)
+#define F_FORCE_HI_Z    V_FORCE_HI_Z(1U)
+
 #define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c
 
 #define S_CLK_LEVEL    14
@@ -39995,6 +59078,10 @@
 #define V_ZERO_DETECTED(x) ((x) << S_ZERO_DETECTED)
 #define F_ZERO_DETECTED    V_ZERO_DETECTED(1U)
 
+#define S_WR_LVL_DONE    12
+#define V_WR_LVL_DONE(x) ((x) << S_WR_LVL_DONE)
+#define F_WR_LVL_DONE    V_WR_LVL_DONE(1U)
+
 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060
 
 #define S_BIT_CENTERED    11
@@ -40026,6 +59113,10 @@
 #define V_DDONE(x) ((x) << S_DDONE)
 #define F_DDONE    V_DDONE(1U)
 
+#define S_WR_CNTR_DONE    5
+#define V_WR_CNTR_DONE(x) ((x) << S_WR_CNTR_DONE)
+#define F_WR_CNTR_DONE    V_WR_CNTR_DONE(1U)
+
 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064
 
 #define S_FW_LEFT_SIDE    5
@@ -40132,6 +59223,18 @@
 #define V_OFFSET_ERR_MASK(x) ((x) << S_OFFSET_ERR_MASK)
 #define F_OFFSET_ERR_MASK    V_OFFSET_ERR_MASK(1U)
 
+#define S_DQS_REC_LOW_POWER    11
+#define V_DQS_REC_LOW_POWER(x) ((x) << S_DQS_REC_LOW_POWER)
+#define F_DQS_REC_LOW_POWER    V_DQS_REC_LOW_POWER(1U)
+
+#define S_DQ_REC_LOW_POWER    10
+#define V_DQ_REC_LOW_POWER(x) ((x) << S_DQ_REC_LOW_POWER)
+#define F_DQ_REC_LOW_POWER    V_DQ_REC_LOW_POWER(1U)
+
+#define S_ADVANCE_PR_VALUE    0
+#define V_ADVANCE_PR_VALUE(x) ((x) << S_ADVANCE_PR_VALUE)
+#define F_ADVANCE_PR_VALUE    V_ADVANCE_PR_VALUE(1U)
+
 #define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074
 
 #define S_CHECKER_RESET    14
@@ -40148,7 +59251,38 @@
 #define V_ERROR(x) ((x) << S_ERROR)
 #define G_ERROR(x) (((x) >> S_ERROR) & M_ERROR)
 
+#define S_CHECKER_ENABLE    15
+#define V_CHECKER_ENABLE(x) ((x) << S_CHECKER_ENABLE)
+#define F_CHECKER_ENABLE    V_CHECKER_ENABLE(1U)
+
+#define S_DP18_DFT_ERROR    0
+#define M_DP18_DFT_ERROR    0x3fU
+#define V_DP18_DFT_ERROR(x) ((x) << S_DP18_DFT_ERROR)
+#define G_DP18_DFT_ERROR(x) (((x) >> S_DP18_DFT_ERROR) & M_DP18_DFT_ERROR)
+
 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078
+
+#define S_SYSCLK_RDCLK_OFFSET    8
+#define M_SYSCLK_RDCLK_OFFSET    0x7fU
+#define V_SYSCLK_RDCLK_OFFSET(x) ((x) << S_SYSCLK_RDCLK_OFFSET)
+#define G_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_SYSCLK_RDCLK_OFFSET) & M_SYSCLK_RDCLK_OFFSET)
+
+#define S_SYSCLK_DQSCLK_OFFSET    0
+#define M_SYSCLK_DQSCLK_OFFSET    0x7fU
+#define V_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_SYSCLK_DQSCLK_OFFSET)
+#define G_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_SYSCLK_DQSCLK_OFFSET) & M_SYSCLK_DQSCLK_OFFSET)
+
+#define S_T6_SYSCLK_DQSCLK_OFFSET    8
+#define M_T6_SYSCLK_DQSCLK_OFFSET    0x7fU
+#define V_T6_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_T6_SYSCLK_DQSCLK_OFFSET)
+#define G_T6_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_DQSCLK_OFFSET) & M_T6_SYSCLK_DQSCLK_OFFSET)
+
+#define S_T6_SYSCLK_RDCLK_OFFSET    0
+#define M_T6_SYSCLK_RDCLK_OFFSET    0x7fU
+#define V_T6_SYSCLK_RDCLK_OFFSET(x) ((x) << S_T6_SYSCLK_RDCLK_OFFSET)
+#define G_T6_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_RDCLK_OFFSET) & M_T6_SYSCLK_RDCLK_OFFSET)
+
+#define A_MC_DDRPHY_DP18_WRCLK_AUX_CNTL 0x4407c
 #define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0
 
 #define S_DQSCLK_ROT_CLK_N0_N2    8
@@ -40289,7 +59423,64 @@
 #define G_MEMINTD23_POS(x) (((x) >> S_MEMINTD23_POS) & M_MEMINTD23_POS)
 
 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4
+
+#define S_DQS_ALIGN_SM    11
+#define M_DQS_ALIGN_SM    0x1fU
+#define V_DQS_ALIGN_SM(x) ((x) << S_DQS_ALIGN_SM)
+#define G_DQS_ALIGN_SM(x) (((x) >> S_DQS_ALIGN_SM) & M_DQS_ALIGN_SM)
+
+#define S_DQS_ALIGN_CNTR    7
+#define M_DQS_ALIGN_CNTR    0xfU
+#define V_DQS_ALIGN_CNTR(x) ((x) << S_DQS_ALIGN_CNTR)
+#define G_DQS_ALIGN_CNTR(x) (((x) >> S_DQS_ALIGN_CNTR) & M_DQS_ALIGN_CNTR)
+
+#define S_ITERATION_CNTR    6
+#define V_ITERATION_CNTR(x) ((x) << S_ITERATION_CNTR)
+#define F_ITERATION_CNTR    V_ITERATION_CNTR(1U)
+
+#define S_DQS_ALIGN_ITER_CNTR    0
+#define M_DQS_ALIGN_ITER_CNTR    0x3fU
+#define V_DQS_ALIGN_ITER_CNTR(x) ((x) << S_DQS_ALIGN_ITER_CNTR)
+#define G_DQS_ALIGN_ITER_CNTR(x) (((x) >> S_DQS_ALIGN_ITER_CNTR) & M_DQS_ALIGN_ITER_CNTR)
+
 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8
+
+#define S_CALIBRATE_BIT    13
+#define M_CALIBRATE_BIT    0x7U
+#define V_CALIBRATE_BIT(x) ((x) << S_CALIBRATE_BIT)
+#define G_CALIBRATE_BIT(x) (((x) >> S_CALIBRATE_BIT) & M_CALIBRATE_BIT)
+
+#define S_DQS_ALIGN_QUAD    11
+#define M_DQS_ALIGN_QUAD    0x3U
+#define V_DQS_ALIGN_QUAD(x) ((x) << S_DQS_ALIGN_QUAD)
+#define G_DQS_ALIGN_QUAD(x) (((x) >> S_DQS_ALIGN_QUAD) & M_DQS_ALIGN_QUAD)
+
+#define S_DQS_QUAD_CONFIG    8
+#define M_DQS_QUAD_CONFIG    0x7U
+#define V_DQS_QUAD_CONFIG(x) ((x) << S_DQS_QUAD_CONFIG)
+#define G_DQS_QUAD_CONFIG(x) (((x) >> S_DQS_QUAD_CONFIG) & M_DQS_QUAD_CONFIG)
+
+#define S_OPERATE_MODE    4
+#define M_OPERATE_MODE    0xfU
+#define V_OPERATE_MODE(x) ((x) << S_OPERATE_MODE)
+#define G_OPERATE_MODE(x) (((x) >> S_OPERATE_MODE) & M_OPERATE_MODE)
+
+#define S_EN_DQS_OFFSET    3
+#define V_EN_DQS_OFFSET(x) ((x) << S_EN_DQS_OFFSET)
+#define F_EN_DQS_OFFSET    V_EN_DQS_OFFSET(1U)
+
+#define S_DQS_ALIGN_JITTER    2
+#define V_DQS_ALIGN_JITTER(x) ((x) << S_DQS_ALIGN_JITTER)
+#define F_DQS_ALIGN_JITTER    V_DQS_ALIGN_JITTER(1U)
+
+#define S_DIS_CLK_GATE    1
+#define V_DIS_CLK_GATE(x) ((x) << S_DIS_CLK_GATE)
+#define F_DIS_CLK_GATE    V_DIS_CLK_GATE(1U)
+
+#define S_MAX_DQS_ITER    0
+#define V_MAX_DQS_ITER(x) ((x) << S_MAX_DQS_ITER)
+#define F_MAX_DQS_ITER    V_MAX_DQS_ITER(1U)
+
 #define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc
 
 #define S_DQS_OFFSET    8
@@ -40363,6 +59554,80 @@
 #define G_INITIAL_DQS_ROT_N1_N3(x) (((x) >> S_INITIAL_DQS_ROT_N1_N3) & M_INITIAL_DQS_ROT_N1_N3)
 
 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174
+#define A_MC_DDRPHY_DP18_WRCLK_STATUS 0x44178
+
+#define S_WRCLK_CALIB_DONE    15
+#define V_WRCLK_CALIB_DONE(x) ((x) << S_WRCLK_CALIB_DONE)
+#define F_WRCLK_CALIB_DONE    V_WRCLK_CALIB_DONE(1U)
+
+#define S_VALUE_UPDATED    14
+#define V_VALUE_UPDATED(x) ((x) << S_VALUE_UPDATED)
+#define F_VALUE_UPDATED    V_VALUE_UPDATED(1U)
+
+#define S_FAIL_PASS_V    13
+#define V_FAIL_PASS_V(x) ((x) << S_FAIL_PASS_V)
+#define F_FAIL_PASS_V    V_FAIL_PASS_V(1U)
+
+#define S_PASS_FAIL_V    12
+#define V_PASS_FAIL_V(x) ((x) << S_PASS_FAIL_V)
+#define F_PASS_FAIL_V    V_PASS_FAIL_V(1U)
+
+#define S_FP_PF_EDGE_NF    11
+#define V_FP_PF_EDGE_NF(x) ((x) << S_FP_PF_EDGE_NF)
+#define F_FP_PF_EDGE_NF    V_FP_PF_EDGE_NF(1U)
+
+#define S_NON_SYMETRIC    10
+#define V_NON_SYMETRIC(x) ((x) << S_NON_SYMETRIC)
+#define F_NON_SYMETRIC    V_NON_SYMETRIC(1U)
+
+#define S_FULL_RANGE    8
+#define V_FULL_RANGE(x) ((x) << S_FULL_RANGE)
+#define F_FULL_RANGE    V_FULL_RANGE(1U)
+
+#define S_QUAD3_EDGES    7
+#define V_QUAD3_EDGES(x) ((x) << S_QUAD3_EDGES)
+#define F_QUAD3_EDGES    V_QUAD3_EDGES(1U)
+
+#define S_QUAD2_EDGES    6
+#define V_QUAD2_EDGES(x) ((x) << S_QUAD2_EDGES)
+#define F_QUAD2_EDGES    V_QUAD2_EDGES(1U)
+
+#define S_QUAD1_EDGES    5
+#define V_QUAD1_EDGES(x) ((x) << S_QUAD1_EDGES)
+#define F_QUAD1_EDGES    V_QUAD1_EDGES(1U)
+
+#define S_QUAD0_EDGES    4
+#define V_QUAD0_EDGES(x) ((x) << S_QUAD0_EDGES)
+#define F_QUAD0_EDGES    V_QUAD0_EDGES(1U)
+
+#define S_QUAD3_CAVEAT    3
+#define V_QUAD3_CAVEAT(x) ((x) << S_QUAD3_CAVEAT)
+#define F_QUAD3_CAVEAT    V_QUAD3_CAVEAT(1U)
+
+#define S_QUAD2_CAVEAT    2
+#define V_QUAD2_CAVEAT(x) ((x) << S_QUAD2_CAVEAT)
+#define F_QUAD2_CAVEAT    V_QUAD2_CAVEAT(1U)
+
+#define S_QUAD1_CAVEAT    1
+#define V_QUAD1_CAVEAT(x) ((x) << S_QUAD1_CAVEAT)
+#define F_QUAD1_CAVEAT    V_QUAD1_CAVEAT(1U)
+
+#define S_QUAD0_CAVEAT    0
+#define V_QUAD0_CAVEAT(x) ((x) << S_QUAD0_CAVEAT)
+#define F_QUAD0_CAVEAT    V_QUAD0_CAVEAT(1U)
+
+#define A_MC_DDRPHY_DP18_WRCLK_EDGE 0x4417c
+
+#define S_FAIL_PASS_VALUE    8
+#define M_FAIL_PASS_VALUE    0x7fU
+#define V_FAIL_PASS_VALUE(x) ((x) << S_FAIL_PASS_VALUE)
+#define G_FAIL_PASS_VALUE(x) (((x) >> S_FAIL_PASS_VALUE) & M_FAIL_PASS_VALUE)
+
+#define S_PASS_FAIL_VALUE    0
+#define M_PASS_FAIL_VALUE    0xffU
+#define V_PASS_FAIL_VALUE(x) ((x) << S_PASS_FAIL_VALUE)
+#define G_PASS_FAIL_VALUE(x) (((x) >> S_PASS_FAIL_VALUE) & M_PASS_FAIL_VALUE)
+
 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180
 
 #define S_RD_EYE_SIZE_BITS2_7    8
@@ -40387,7 +59652,45 @@
 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8
 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac
 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4
+
+#define S_DESIRED_EDGE_CNTR_TARGET_HIGH    8
+#define M_DESIRED_EDGE_CNTR_TARGET_HIGH    0xffU
+#define V_DESIRED_EDGE_CNTR_TARGET_HIGH(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_HIGH)
+#define G_DESIRED_EDGE_CNTR_TARGET_HIGH(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_HIGH) & M_DESIRED_EDGE_CNTR_TARGET_HIGH)
+
+#define S_DESIRED_EDGE_CNTR_TARGET_LOW    0
+#define M_DESIRED_EDGE_CNTR_TARGET_LOW    0xffU
+#define V_DESIRED_EDGE_CNTR_TARGET_LOW(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_LOW)
+#define G_DESIRED_EDGE_CNTR_TARGET_LOW(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_LOW) & M_DESIRED_EDGE_CNTR_TARGET_LOW)
+
 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8
+
+#define S_APPROACH_ALIGNMENT    15
+#define V_APPROACH_ALIGNMENT(x) ((x) << S_APPROACH_ALIGNMENT)
+#define F_APPROACH_ALIGNMENT    V_APPROACH_ALIGNMENT(1U)
+
+#define A_MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL 0x441bc
+
+#define S_QUAD0_PWR_CTL    12
+#define M_QUAD0_PWR_CTL    0xfU
+#define V_QUAD0_PWR_CTL(x) ((x) << S_QUAD0_PWR_CTL)
+#define G_QUAD0_PWR_CTL(x) (((x) >> S_QUAD0_PWR_CTL) & M_QUAD0_PWR_CTL)
+
+#define S_QUAD1_PWR_CTL    8
+#define M_QUAD1_PWR_CTL    0xfU
+#define V_QUAD1_PWR_CTL(x) ((x) << S_QUAD1_PWR_CTL)
+#define G_QUAD1_PWR_CTL(x) (((x) >> S_QUAD1_PWR_CTL) & M_QUAD1_PWR_CTL)
+
+#define S_QUAD2_PWR_CTL    4
+#define M_QUAD2_PWR_CTL    0xfU
+#define V_QUAD2_PWR_CTL(x) ((x) << S_QUAD2_PWR_CTL)
+#define G_QUAD2_PWR_CTL(x) (((x) >> S_QUAD2_PWR_CTL) & M_QUAD2_PWR_CTL)
+
+#define S_QUAD3_PWR_CTL    0
+#define M_QUAD3_PWR_CTL    0xfU
+#define V_QUAD3_PWR_CTL(x) ((x) << S_QUAD3_PWR_CTL)
+#define G_QUAD3_PWR_CTL(x) (((x) >> S_QUAD3_PWR_CTL) & M_QUAD3_PWR_CTL)
+
 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0
 
 #define S_REFERENCE_BITS1_7    8
@@ -40519,6 +59822,28 @@
 #define G_DQ_WR_OFFSET_N3(x) (((x) >> S_DQ_WR_OFFSET_N3) & M_DQ_WR_OFFSET_N3)
 
 #define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc
+
+#define S_EYEDAC_PD    13
+#define V_EYEDAC_PD(x) ((x) << S_EYEDAC_PD)
+#define F_EYEDAC_PD    V_EYEDAC_PD(1U)
+
+#define S_ANALOG_OUTPUT_STAB    9
+#define V_ANALOG_OUTPUT_STAB(x) ((x) << S_ANALOG_OUTPUT_STAB)
+#define F_ANALOG_OUTPUT_STAB    V_ANALOG_OUTPUT_STAB(1U)
+
+#define S_DP18_RX_PD    2
+#define M_DP18_RX_PD    0x3U
+#define V_DP18_RX_PD(x) ((x) << S_DP18_RX_PD)
+#define G_DP18_RX_PD(x) (((x) >> S_DP18_RX_PD) & M_DP18_RX_PD)
+
+#define S_DELAY_LINE_CTL_OVERRIDE    4
+#define V_DELAY_LINE_CTL_OVERRIDE(x) ((x) << S_DELAY_LINE_CTL_OVERRIDE)
+#define F_DELAY_LINE_CTL_OVERRIDE    V_DELAY_LINE_CTL_OVERRIDE(1U)
+
+#define S_VCC_REG_PD    0
+#define V_VCC_REG_PD(x) ((x) << S_VCC_REG_PD)
+#define F_VCC_REG_PD    V_VCC_REG_PD(1U)
+
 #define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000
 
 #define S_BIT_ENABLE_0_11    4
@@ -40853,6 +60178,40 @@
 #define V_ADR_LANE_12_15_PD(x) ((x) << S_ADR_LANE_12_15_PD)
 #define G_ADR_LANE_12_15_PD(x) (((x) >> S_ADR_LANE_12_15_PD) & M_ADR_LANE_12_15_PD)
 
+#define A_T6_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45800
+#define A_T6_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45804
+#define A_T6_MC_ADR_DDRPHY_ADR_DELAY0 0x45810
+#define A_T6_MC_ADR_DDRPHY_ADR_DELAY1 0x45814
+#define A_T6_MC_ADR_DDRPHY_ADR_DELAY2 0x45818
+#define A_T6_MC_ADR_DDRPHY_ADR_DELAY3 0x4581c
+#define A_T6_MC_ADR_DDRPHY_ADR_DELAY4 0x45820
+#define A_T6_MC_ADR_DDRPHY_ADR_DELAY5 0x45824
+#define A_T6_MC_ADR_DDRPHY_ADR_DELAY6 0x45828
+#define A_T6_MC_ADR_DDRPHY_ADR_DELAY7 0x4582c
+#define A_T6_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45830
+
+#define S_ADR_TEST_MODE    5
+#define M_ADR_TEST_MODE    0x3U
+#define V_ADR_TEST_MODE(x) ((x) << S_ADR_TEST_MODE)
+#define G_ADR_TEST_MODE(x) (((x) >> S_ADR_TEST_MODE) & M_ADR_TEST_MODE)
+
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45840
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45844
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45848
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4584c
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45850
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45854
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45858
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4585c
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45860
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45868
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45880
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45884
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x458a0
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x458a4
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x458a8
+#define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x458ac
+#define A_T6_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x458b0
 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0
 
 #define S_PLL_TUNE_0_2    13
@@ -40880,6 +60239,7 @@
 #define V_PLL_PLLXTR_0_1(x) ((x) << S_PLL_PLLXTR_0_1)
 #define G_PLL_PLLXTR_0_1(x) (((x) >> S_PLL_PLLXTR_0_1) & M_PLL_PLLXTR_0_1)
 
+#define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0 0x460c0
 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4
 
 #define S_PLL_TUNETDIV_0_2    13
@@ -40919,6 +60279,7 @@
 #define V_ANALOG_WRAPON(x) ((x) << S_ANALOG_WRAPON)
 #define F_ANALOG_WRAPON    V_ANALOG_WRAPON(1U)
 
+#define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1 0x460c4
 #define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8
 
 #define S_SYSCLK_ENABLE    15
@@ -40959,6 +60320,7 @@
 #define V_CE0DLTVCC(x) ((x) << S_CE0DLTVCC)
 #define G_CE0DLTVCC(x) (((x) >> S_CE0DLTVCC) & M_CE0DLTVCC)
 
+#define A_MC_DDRPHY_AD32S_SYSCLK_CNTL_PR 0x460c8
 #define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
 
 #define S_TSYS_WRCLK    8
@@ -40966,6 +60328,7 @@
 #define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK)
 #define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK)
 
+#define A_MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
 #define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0
 
 #define S_SLEW_LATE_SAMPLE    15
@@ -40995,6 +60358,7 @@
 #define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL)
 #define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL)
 
+#define A_MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO 0x460d0
 #define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4
 
 #define S_FLUSH    15
@@ -41035,6 +60399,22 @@
 #define V_ATEST1CTL3(x) ((x) << S_ATEST1CTL3)
 #define F_ATEST1CTL3    V_ATEST1CTL3(1U)
 
+#define A_MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL 0x460d4
+
+#define S_FORCE_EN    14
+#define V_FORCE_EN(x) ((x) << S_FORCE_EN)
+#define F_FORCE_EN    V_FORCE_EN(1U)
+
+#define S_AD32S_HS_PROBE_A_SEL    8
+#define M_AD32S_HS_PROBE_A_SEL    0xfU
+#define V_AD32S_HS_PROBE_A_SEL(x) ((x) << S_AD32S_HS_PROBE_A_SEL)
+#define G_AD32S_HS_PROBE_A_SEL(x) (((x) >> S_AD32S_HS_PROBE_A_SEL) & M_AD32S_HS_PROBE_A_SEL)
+
+#define S_AD32S_HS_PROBE_B_SEL    4
+#define M_AD32S_HS_PROBE_B_SEL    0xfU
+#define V_AD32S_HS_PROBE_B_SEL(x) ((x) << S_AD32S_HS_PROBE_B_SEL)
+#define G_AD32S_HS_PROBE_B_SEL(x) (((x) >> S_AD32S_HS_PROBE_B_SEL) & M_AD32S_HS_PROBE_B_SEL)
+
 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8
 
 #define S_GIANT_MUX_TEST_RESULTS    0
@@ -41042,7 +60422,15 @@
 #define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS)
 #define G_GIANT_MUX_TEST_RESULTS(x) (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS)
 
+#define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0 0x460d8
+
+#define S_OUTPUT_DRIVER_FORCE_VALUE    0
+#define M_OUTPUT_DRIVER_FORCE_VALUE    0xffffU
+#define V_OUTPUT_DRIVER_FORCE_VALUE(x) ((x) << S_OUTPUT_DRIVER_FORCE_VALUE)
+#define G_OUTPUT_DRIVER_FORCE_VALUE(x) (((x) >> S_OUTPUT_DRIVER_FORCE_VALUE) & M_OUTPUT_DRIVER_FORCE_VALUE)
+
 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc
+#define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1 0x460dc
 #define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0
 
 #define S_MASTER_PD_CNTL    15
@@ -41078,6 +60466,7 @@
 #define V_DVCC_REG_PD(x) ((x) << S_DVCC_REG_PD)
 #define F_DVCC_REG_PD    V_DVCC_REG_PD(1U)
 
+#define A_MC_DDRPHY_AD32S_POWERDOWN_1 0x460e0
 #define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4
 
 #define S_SLEW_CAL_ENABLE    15
@@ -41102,6 +60491,7 @@
 #define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET)
 #define G_SLEW_TARGET_PR_OFFSET(x) (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET)
 
+#define A_MC_DDRPHY_AD32S_SLEW_CAL_CNTL 0x460e4
 #define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000
 
 #define S_DP18_PLL_LOCK    1
@@ -41254,18 +60644,18 @@
 #define V_PER_ENA_SYSCLK_ALIGN(x) ((x) << S_PER_ENA_SYSCLK_ALIGN)
 #define F_PER_ENA_SYSCLK_ALIGN    V_PER_ENA_SYSCLK_ALIGN(1U)
 
-#define S_ENA_PER_RDCLK_ALIGN    9
+#define S_ENA_PER_READ_CTR    9
+#define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR)
+#define F_ENA_PER_READ_CTR    V_ENA_PER_READ_CTR(1U)
+
+#define S_ENA_PER_RDCLK_ALIGN    8
 #define V_ENA_PER_RDCLK_ALIGN(x) ((x) << S_ENA_PER_RDCLK_ALIGN)
 #define F_ENA_PER_RDCLK_ALIGN    V_ENA_PER_RDCLK_ALIGN(1U)
 
-#define S_ENA_PER_DQS_ALIGN    8
+#define S_ENA_PER_DQS_ALIGN    7
 #define V_ENA_PER_DQS_ALIGN(x) ((x) << S_ENA_PER_DQS_ALIGN)
 #define F_ENA_PER_DQS_ALIGN    V_ENA_PER_DQS_ALIGN(1U)
 
-#define S_ENA_PER_READ_CTR    7
-#define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR)
-#define F_ENA_PER_READ_CTR    V_ENA_PER_READ_CTR(1U)
-
 #define S_PER_NEXT_RANK_PAIR    5
 #define M_PER_NEXT_RANK_PAIR    0x3U
 #define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR)
@@ -41283,6 +60673,14 @@
 #define V_START_PER_CAL(x) ((x) << S_START_PER_CAL)
 #define F_START_PER_CAL    V_START_PER_CAL(1U)
 
+#define S_ABORT_ON_ERR_EN    1
+#define V_ABORT_ON_ERR_EN(x) ((x) << S_ABORT_ON_ERR_EN)
+#define F_ABORT_ON_ERR_EN    V_ABORT_ON_ERR_EN(1U)
+
+#define S_ENA_PER_RD_CTR    9
+#define V_ENA_PER_RD_CTR(x) ((x) << S_ENA_PER_RD_CTR)
+#define F_ENA_PER_RD_CTR    V_ENA_PER_RD_CTR(1U)
+
 #define A_MC_DDRPHY_PC_CONFIG0 0x47030
 
 #define S_PROTOCOL_DDR    12
@@ -41323,6 +60721,19 @@
 #define V_DDR4_VLEVEL_BANK_GROUP(x) ((x) << S_DDR4_VLEVEL_BANK_GROUP)
 #define F_DDR4_VLEVEL_BANK_GROUP    V_DDR4_VLEVEL_BANK_GROUP(1U)
 
+#define S_DDRPHY_PROTOCOL    12
+#define M_DDRPHY_PROTOCOL    0xfU
+#define V_DDRPHY_PROTOCOL(x) ((x) << S_DDRPHY_PROTOCOL)
+#define G_DDRPHY_PROTOCOL(x) (((x) >> S_DDRPHY_PROTOCOL) & M_DDRPHY_PROTOCOL)
+
+#define S_SPAM_EN    10
+#define V_SPAM_EN(x) ((x) << S_SPAM_EN)
+#define F_SPAM_EN    V_SPAM_EN(1U)
+
+#define S_DDR4_IPW_LOOP_DIS    2
+#define V_DDR4_IPW_LOOP_DIS(x) ((x) << S_DDR4_IPW_LOOP_DIS)
+#define F_DDR4_IPW_LOOP_DIS    V_DDR4_IPW_LOOP_DIS(1U)
+
 #define A_MC_DDRPHY_PC_CONFIG1 0x47034
 
 #define S_WRITE_LATENCY_OFFSET    12
@@ -41347,6 +60758,19 @@
 #define V_DISABLE_MEMCTL_CAL(x) ((x) << S_DISABLE_MEMCTL_CAL)
 #define F_DISABLE_MEMCTL_CAL    V_DISABLE_MEMCTL_CAL(1U)
 
+#define S_MEMCTL_CIS_IGNORE    6
+#define V_MEMCTL_CIS_IGNORE(x) ((x) << S_MEMCTL_CIS_IGNORE)
+#define F_MEMCTL_CIS_IGNORE    V_MEMCTL_CIS_IGNORE(1U)
+
+#define S_MEMORY_TYPE    2
+#define M_MEMORY_TYPE    0x7U
+#define V_MEMORY_TYPE(x) ((x) << S_MEMORY_TYPE)
+#define G_MEMORY_TYPE(x) (((x) >> S_MEMORY_TYPE) & M_MEMORY_TYPE)
+
+#define S_DDR4_PDA_MODE    1
+#define V_DDR4_PDA_MODE(x) ((x) << S_DDR4_PDA_MODE)
+#define F_DDR4_PDA_MODE    V_DDR4_PDA_MODE(1U)
+
 #define A_MC_DDRPHY_PC_RESETS 0x47038
 
 #define S_PLL_RESET    15
@@ -41412,6 +60836,30 @@
 #define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING)
 #define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING)
 
+#define S_ADDR_MIRROR_A3_A4    5
+#define V_ADDR_MIRROR_A3_A4(x) ((x) << S_ADDR_MIRROR_A3_A4)
+#define F_ADDR_MIRROR_A3_A4    V_ADDR_MIRROR_A3_A4(1U)
+
+#define S_ADDR_MIRROR_A5_A6    4
+#define V_ADDR_MIRROR_A5_A6(x) ((x) << S_ADDR_MIRROR_A5_A6)
+#define F_ADDR_MIRROR_A5_A6    V_ADDR_MIRROR_A5_A6(1U)
+
+#define S_ADDR_MIRROR_A7_A8    3
+#define V_ADDR_MIRROR_A7_A8(x) ((x) << S_ADDR_MIRROR_A7_A8)
+#define F_ADDR_MIRROR_A7_A8    V_ADDR_MIRROR_A7_A8(1U)
+
+#define S_ADDR_MIRROR_A11_A13    2
+#define V_ADDR_MIRROR_A11_A13(x) ((x) << S_ADDR_MIRROR_A11_A13)
+#define F_ADDR_MIRROR_A11_A13    V_ADDR_MIRROR_A11_A13(1U)
+
+#define S_ADDR_MIRROR_BA0_BA1    1
+#define V_ADDR_MIRROR_BA0_BA1(x) ((x) << S_ADDR_MIRROR_BA0_BA1)
+#define F_ADDR_MIRROR_BA0_BA1    V_ADDR_MIRROR_BA0_BA1(1U)
+
+#define S_ADDR_MIRROR_BG0_BG1    0
+#define V_ADDR_MIRROR_BG0_BG1(x) ((x) << S_ADDR_MIRROR_BG0_BG1)
+#define F_ADDR_MIRROR_BG0_BG1    V_ADDR_MIRROR_BG0_BG1(1U)
+
 #define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048
 
 #define S_RC_ERROR    15
@@ -41504,6 +60952,19 @@
 #define V_VREFDQ1D(x) ((x) << S_VREFDQ1D)
 #define G_VREFDQ1D(x) (((x) >> S_VREFDQ1D) & M_VREFDQ1D)
 
+#define S_EN_ANALOG_PD    3
+#define V_EN_ANALOG_PD(x) ((x) << S_EN_ANALOG_PD)
+#define F_EN_ANALOG_PD    V_EN_ANALOG_PD(1U)
+
+#define S_ANALOG_PD_DLY    2
+#define V_ANALOG_PD_DLY(x) ((x) << S_ANALOG_PD_DLY)
+#define F_ANALOG_PD_DLY    V_ANALOG_PD_DLY(1U)
+
+#define S_ANALOG_PD_DIV    0
+#define M_ANALOG_PD_DIV    0x3U
+#define V_ANALOG_PD_DIV(x) ((x) << S_ANALOG_PD_DIV)
+#define G_ANALOG_PD_DIV(x) (((x) >> S_ANALOG_PD_DIV) & M_ANALOG_PD_DIV)
+
 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058
 
 #define S_ENA_WR_LEVEL    15
@@ -41638,6 +61099,10 @@
 #define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE)
 #define G_INIT_CAL_COMPLETE(x) (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE)
 
+#define S_PER_CAL_ABORT    6
+#define V_PER_CAL_ABORT(x) ((x) << S_PER_CAL_ABORT)
+#define F_PER_CAL_ABORT    V_PER_CAL_ABORT(1U)
+
 #define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068
 
 #define S_ERROR_WR_LEVEL_MASK    15
@@ -41746,6 +61211,34 @@
 #define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN)
 #define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN)
 
+#define S_PARITY_DLY    9
+#define V_PARITY_DLY(x) ((x) << S_PARITY_DLY)
+#define F_PARITY_DLY    V_PARITY_DLY(1U)
+
+#define S_FORCE_RESERVED    7
+#define V_FORCE_RESERVED(x) ((x) << S_FORCE_RESERVED)
+#define F_FORCE_RESERVED    V_FORCE_RESERVED(1U)
+
+#define S_HALT_ROTATION    6
+#define V_HALT_ROTATION(x) ((x) << S_HALT_ROTATION)
+#define F_HALT_ROTATION    V_HALT_ROTATION(1U)
+
+#define S_FORCE_MPR    5
+#define V_FORCE_MPR(x) ((x) << S_FORCE_MPR)
+#define F_FORCE_MPR    V_FORCE_MPR(1U)
+
+#define S_IPW_SIDEAB_SEL    2
+#define V_IPW_SIDEAB_SEL(x) ((x) << S_IPW_SIDEAB_SEL)
+#define F_IPW_SIDEAB_SEL    V_IPW_SIDEAB_SEL(1U)
+
+#define S_PARITY_A17_MASK    1
+#define V_PARITY_A17_MASK(x) ((x) << S_PARITY_A17_MASK)
+#define F_PARITY_A17_MASK    V_PARITY_A17_MASK(1U)
+
+#define S_X16_DEVICE    0
+#define V_X16_DEVICE(x) ((x) << S_X16_DEVICE)
+#define F_X16_DEVICE    V_X16_DEVICE(1U)
+
 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c
 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210
 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214
@@ -41890,6 +61383,11 @@
 #define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES)
 #define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES)
 
+#define S_MRS_CMD_SPACE    0
+#define M_MRS_CMD_SPACE    0xfU
+#define V_MRS_CMD_SPACE(x) ((x) << S_MRS_CMD_SPACE)
+#define G_MRS_CMD_SPACE(x) (((x) >> S_MRS_CMD_SPACE) & M_MRS_CMD_SPACE)
+
 #define A_MC_DDRPHY_RC_CONFIG0 0x47400
 
 #define S_GLOBAL_PHY_OFFSET    12
@@ -41929,6 +61427,10 @@
 #define V_STAGGERED_PATTERN(x) ((x) << S_STAGGERED_PATTERN)
 #define F_STAGGERED_PATTERN    V_STAGGERED_PATTERN(1U)
 
+#define S_ERS_MODE    10
+#define V_ERS_MODE(x) ((x) << S_ERS_MODE)
+#define F_ERS_MODE    V_ERS_MODE(1U)
+
 #define A_MC_DDRPHY_RC_CONFIG1 0x47404
 
 #define S_OUTER_LOOP_CNT    2
@@ -41952,6 +61454,10 @@
 #define V_ALLOW_RD_FIFO_AUTO_R_ESET(x) ((x) << S_ALLOW_RD_FIFO_AUTO_R_ESET)
 #define F_ALLOW_RD_FIFO_AUTO_R_ESET    V_ALLOW_RD_FIFO_AUTO_R_ESET(1U)
 
+#define S_DIS_LOW_PWR_PER_CAL    3
+#define V_DIS_LOW_PWR_PER_CAL(x) ((x) << S_DIS_LOW_PWR_PER_CAL)
+#define F_DIS_LOW_PWR_PER_CAL    V_DIS_LOW_PWR_PER_CAL(1U)
+
 #define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414
 
 #define S_RD_CNTL_ERROR    15
@@ -42036,6 +61542,15 @@
 #define V_FW_RD_WR(x) ((x) << S_FW_RD_WR)
 #define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR)
 
+#define S_EN_RESET_WR_DELAY_WL    0
+#define V_EN_RESET_WR_DELAY_WL(x) ((x) << S_EN_RESET_WR_DELAY_WL)
+#define F_EN_RESET_WR_DELAY_WL    V_EN_RESET_WR_DELAY_WL(1U)
+
+#define S_TWR_MPR    2
+#define M_TWR_MPR    0xfU
+#define V_TWR_MPR(x) ((x) << S_TWR_MPR)
+#define G_TWR_MPR(x) (((x) >> S_TWR_MPR) & M_TWR_MPR)
+
 #define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c
 
 #define S_WR_CNTL_ERROR    15
@@ -42220,6 +61735,69 @@
 #define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL)
 #define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL)
 
+#define A_MC_DDRPHY_APB_MTCTL_REG0 0x47820
+
+#define S_MT_DATA_MUX4_1MODE    15
+#define V_MT_DATA_MUX4_1MODE(x) ((x) << S_MT_DATA_MUX4_1MODE)
+#define F_MT_DATA_MUX4_1MODE    V_MT_DATA_MUX4_1MODE(1U)
+
+#define S_MT_PLL_RESET    14
+#define V_MT_PLL_RESET(x) ((x) << S_MT_PLL_RESET)
+#define F_MT_PLL_RESET    V_MT_PLL_RESET(1U)
+
+#define S_MT_SYSCLK_RESET    13
+#define V_MT_SYSCLK_RESET(x) ((x) << S_MT_SYSCLK_RESET)
+#define F_MT_SYSCLK_RESET    V_MT_SYSCLK_RESET(1U)
+
+#define S_MT_GLOBAL_PHY_OFFSET    9
+#define M_MT_GLOBAL_PHY_OFFSET    0xfU
+#define V_MT_GLOBAL_PHY_OFFSET(x) ((x) << S_MT_GLOBAL_PHY_OFFSET)
+#define G_MT_GLOBAL_PHY_OFFSET(x) (((x) >> S_MT_GLOBAL_PHY_OFFSET) & M_MT_GLOBAL_PHY_OFFSET)
+
+#define S_MT_DQ_SEL_QUAD    7
+#define M_MT_DQ_SEL_QUAD    0x3U
+#define V_MT_DQ_SEL_QUAD(x) ((x) << S_MT_DQ_SEL_QUAD)
+#define G_MT_DQ_SEL_QUAD(x) (((x) >> S_MT_DQ_SEL_QUAD) & M_MT_DQ_SEL_QUAD)
+
+#define S_MT_PERFORM_RDCLK_ALIGN    6
+#define V_MT_PERFORM_RDCLK_ALIGN(x) ((x) << S_MT_PERFORM_RDCLK_ALIGN)
+#define F_MT_PERFORM_RDCLK_ALIGN    V_MT_PERFORM_RDCLK_ALIGN(1U)
+
+#define S_MT_ALIGN_ON_EVEN_CYCLES    5
+#define V_MT_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_MT_ALIGN_ON_EVEN_CYCLES)
+#define F_MT_ALIGN_ON_EVEN_CYCLES    V_MT_ALIGN_ON_EVEN_CYCLES(1U)
+
+#define S_MT_WRCLK_CAL_START    4
+#define V_MT_WRCLK_CAL_START(x) ((x) << S_MT_WRCLK_CAL_START)
+#define F_MT_WRCLK_CAL_START    V_MT_WRCLK_CAL_START(1U)
+
+#define A_MC_DDRPHY_APB_MTCTL_REG1 0x47824
+
+#define S_MT_WPRD_ENABLE    15
+#define V_MT_WPRD_ENABLE(x) ((x) << S_MT_WPRD_ENABLE)
+#define F_MT_WPRD_ENABLE    V_MT_WPRD_ENABLE(1U)
+
+#define S_MT_PVTP    10
+#define M_MT_PVTP    0x1fU
+#define V_MT_PVTP(x) ((x) << S_MT_PVTP)
+#define G_MT_PVTP(x) (((x) >> S_MT_PVTP) & M_MT_PVTP)
+
+#define S_MT_PVTN    5
+#define M_MT_PVTN    0x1fU
+#define V_MT_PVTN(x) ((x) << S_MT_PVTN)
+#define G_MT_PVTN(x) (((x) >> S_MT_PVTN) & M_MT_PVTN)
+
+#define A_MC_DDRPHY_APB_MTSTAT_REG0 0x47828
+#define A_MC_DDRPHY_APB_MTSTAT_REG1 0x4782c
+
+#define S_MT_ADR32_PLL_LOCK_SUM    1
+#define V_MT_ADR32_PLL_LOCK_SUM(x) ((x) << S_MT_ADR32_PLL_LOCK_SUM)
+#define F_MT_ADR32_PLL_LOCK_SUM    V_MT_ADR32_PLL_LOCK_SUM(1U)
+
+#define S_MT_DP18_PLL_LOCK_SUM    0
+#define V_MT_DP18_PLL_LOCK_SUM(x) ((x) << S_MT_DP18_PLL_LOCK_SUM)
+#define F_MT_DP18_PLL_LOCK_SUM    V_MT_DP18_PLL_LOCK_SUM(1U)
+
 /* registers for module MC_1 */
 #define MC_1_BASE_ADDR 0x48000
 
@@ -42258,6 +61836,19 @@
 
 #define A_EDC_H_INT_ENABLE 0x50074
 #define A_EDC_H_INT_CAUSE 0x50078
+
+#define S_ECC_UE_INT0_CAUSE    5
+#define V_ECC_UE_INT0_CAUSE(x) ((x) << S_ECC_UE_INT0_CAUSE)
+#define F_ECC_UE_INT0_CAUSE    V_ECC_UE_INT0_CAUSE(1U)
+
+#define S_ECC_CE_INT0_CAUSE    4
+#define V_ECC_CE_INT0_CAUSE(x) ((x) << S_ECC_CE_INT0_CAUSE)
+#define F_ECC_CE_INT0_CAUSE    V_ECC_CE_INT0_CAUSE(1U)
+
+#define S_PERR_INT0_CAUSE    3
+#define V_PERR_INT0_CAUSE(x) ((x) << S_PERR_INT0_CAUSE)
+#define F_PERR_INT0_CAUSE    V_PERR_INT0_CAUSE(1U)
+
 #define A_EDC_H_ECC_STATUS 0x5007c
 #define A_EDC_H_ECC_ERR_SEL 0x50080
 
@@ -42347,3 +61938,936 @@
 #define A_HMA_PAR_ENABLE 0x51300
 #define A_HMA_INT_ENABLE 0x51304
 #define A_HMA_INT_CAUSE 0x51308
+
+/* registers for module EDC_T60 */
+#define EDC_T60_BASE_ADDR 0x50000
+
+#define S_QDR_CLKPHASE    24
+#define M_QDR_CLKPHASE    0x7U
+#define V_QDR_CLKPHASE(x) ((x) << S_QDR_CLKPHASE)
+#define G_QDR_CLKPHASE(x) (((x) >> S_QDR_CLKPHASE) & M_QDR_CLKPHASE)
+
+#define S_MAXOPSPERTRC    21
+#define M_MAXOPSPERTRC    0x7U
+#define V_MAXOPSPERTRC(x) ((x) << S_MAXOPSPERTRC)
+#define G_MAXOPSPERTRC(x) (((x) >> S_MAXOPSPERTRC) & M_MAXOPSPERTRC)
+
+#define S_NUMPIPESTAGES    19
+#define M_NUMPIPESTAGES    0x3U
+#define V_NUMPIPESTAGES(x) ((x) << S_NUMPIPESTAGES)
+#define G_NUMPIPESTAGES(x) (((x) >> S_NUMPIPESTAGES) & M_NUMPIPESTAGES)
+
+#define A_EDC_H_DBG_MA_CMD_INTF 0x50300
+
+#define S_MCMDADDR    12
+#define M_MCMDADDR    0xfffffU
+#define V_MCMDADDR(x) ((x) << S_MCMDADDR)
+#define G_MCMDADDR(x) (((x) >> S_MCMDADDR) & M_MCMDADDR)
+
+#define S_MCMDLEN    5
+#define M_MCMDLEN    0x7fU
+#define V_MCMDLEN(x) ((x) << S_MCMDLEN)
+#define G_MCMDLEN(x) (((x) >> S_MCMDLEN) & M_MCMDLEN)
+
+#define S_MCMDNRE    4
+#define V_MCMDNRE(x) ((x) << S_MCMDNRE)
+#define F_MCMDNRE    V_MCMDNRE(1U)
+
+#define S_MCMDNRB    3
+#define V_MCMDNRB(x) ((x) << S_MCMDNRB)
+#define F_MCMDNRB    V_MCMDNRB(1U)
+
+#define S_MCMDWR    2
+#define V_MCMDWR(x) ((x) << S_MCMDWR)
+#define F_MCMDWR    V_MCMDWR(1U)
+
+#define S_MCMDRDY    1
+#define V_MCMDRDY(x) ((x) << S_MCMDRDY)
+#define F_MCMDRDY    V_MCMDRDY(1U)
+
+#define S_MCMDVLD    0
+#define V_MCMDVLD(x) ((x) << S_MCMDVLD)
+#define F_MCMDVLD    V_MCMDVLD(1U)
+
+#define A_EDC_H_DBG_MA_WDATA_INTF 0x50304
+
+#define S_MWDATAVLD    31
+#define V_MWDATAVLD(x) ((x) << S_MWDATAVLD)
+#define F_MWDATAVLD    V_MWDATAVLD(1U)
+
+#define S_MWDATARDY    30
+#define V_MWDATARDY(x) ((x) << S_MWDATARDY)
+#define F_MWDATARDY    V_MWDATARDY(1U)
+
+#define S_MWDATA    0
+#define M_MWDATA    0x3fffffffU
+#define V_MWDATA(x) ((x) << S_MWDATA)
+#define G_MWDATA(x) (((x) >> S_MWDATA) & M_MWDATA)
+
+#define A_EDC_H_DBG_MA_RDATA_INTF 0x50308
+
+#define S_MRSPVLD    31
+#define V_MRSPVLD(x) ((x) << S_MRSPVLD)
+#define F_MRSPVLD    V_MRSPVLD(1U)
+
+#define S_MRSPRDY    30
+#define V_MRSPRDY(x) ((x) << S_MRSPRDY)
+#define F_MRSPRDY    V_MRSPRDY(1U)
+
+#define S_MRSPDATA    0
+#define M_MRSPDATA    0x3fffffffU
+#define V_MRSPDATA(x) ((x) << S_MRSPDATA)
+#define G_MRSPDATA(x) (((x) >> S_MRSPDATA) & M_MRSPDATA)
+
+#define A_EDC_H_DBG_BIST_CMD_INTF 0x5030c
+
+#define S_BCMDADDR    9
+#define M_BCMDADDR    0x7fffffU
+#define V_BCMDADDR(x) ((x) << S_BCMDADDR)
+#define G_BCMDADDR(x) (((x) >> S_BCMDADDR) & M_BCMDADDR)
+
+#define S_BCMDLEN    3
+#define M_BCMDLEN    0x3fU
+#define V_BCMDLEN(x) ((x) << S_BCMDLEN)
+#define G_BCMDLEN(x) (((x) >> S_BCMDLEN) & M_BCMDLEN)
+
+#define S_BCMDWR    2
+#define V_BCMDWR(x) ((x) << S_BCMDWR)
+#define F_BCMDWR    V_BCMDWR(1U)
+
+#define S_BCMDRDY    1
+#define V_BCMDRDY(x) ((x) << S_BCMDRDY)
+#define F_BCMDRDY    V_BCMDRDY(1U)
+
+#define S_BCMDVLD    0
+#define V_BCMDVLD(x) ((x) << S_BCMDVLD)
+#define F_BCMDVLD    V_BCMDVLD(1U)
+
+#define A_EDC_H_DBG_BIST_WDATA_INTF 0x50310
+
+#define S_BWDATAVLD    31
+#define V_BWDATAVLD(x) ((x) << S_BWDATAVLD)
+#define F_BWDATAVLD    V_BWDATAVLD(1U)
+
+#define S_BWDATARDY    30
+#define V_BWDATARDY(x) ((x) << S_BWDATARDY)
+#define F_BWDATARDY    V_BWDATARDY(1U)
+
+#define S_BWDATA    0
+#define M_BWDATA    0x3fffffffU
+#define V_BWDATA(x) ((x) << S_BWDATA)
+#define G_BWDATA(x) (((x) >> S_BWDATA) & M_BWDATA)
+
+#define A_EDC_H_DBG_BIST_RDATA_INTF 0x50314
+
+#define S_BRSPVLD    31
+#define V_BRSPVLD(x) ((x) << S_BRSPVLD)
+#define F_BRSPVLD    V_BRSPVLD(1U)
+
+#define S_BRSPRDY    30
+#define V_BRSPRDY(x) ((x) << S_BRSPRDY)
+#define F_BRSPRDY    V_BRSPRDY(1U)
+
+#define S_BRSPDATA    0
+#define M_BRSPDATA    0x3fffffffU
+#define V_BRSPDATA(x) ((x) << S_BRSPDATA)
+#define G_BRSPDATA(x) (((x) >> S_BRSPDATA) & M_BRSPDATA)
+
+#define A_EDC_H_DBG_EDRAM_CMD_INTF 0x50318
+
+#define S_EDRAMADDR    16
+#define M_EDRAMADDR    0xffffU
+#define V_EDRAMADDR(x) ((x) << S_EDRAMADDR)
+#define G_EDRAMADDR(x) (((x) >> S_EDRAMADDR) & M_EDRAMADDR)
+
+#define S_EDRAMDWSN    8
+#define M_EDRAMDWSN    0xffU
+#define V_EDRAMDWSN(x) ((x) << S_EDRAMDWSN)
+#define G_EDRAMDWSN(x) (((x) >> S_EDRAMDWSN) & M_EDRAMDWSN)
+
+#define S_EDRAMCRA    5
+#define M_EDRAMCRA    0x7U
+#define V_EDRAMCRA(x) ((x) << S_EDRAMCRA)
+#define G_EDRAMCRA(x) (((x) >> S_EDRAMCRA) & M_EDRAMCRA)
+
+#define S_EDRAMREFENLO    4
+#define V_EDRAMREFENLO(x) ((x) << S_EDRAMREFENLO)
+#define F_EDRAMREFENLO    V_EDRAMREFENLO(1U)
+
+#define S_EDRAM1WRENLO    3
+#define V_EDRAM1WRENLO(x) ((x) << S_EDRAM1WRENLO)
+#define F_EDRAM1WRENLO    V_EDRAM1WRENLO(1U)
+
+#define S_EDRAM1RDENLO    2
+#define V_EDRAM1RDENLO(x) ((x) << S_EDRAM1RDENLO)
+#define F_EDRAM1RDENLO    V_EDRAM1RDENLO(1U)
+
+#define S_EDRAM0WRENLO    1
+#define V_EDRAM0WRENLO(x) ((x) << S_EDRAM0WRENLO)
+#define F_EDRAM0WRENLO    V_EDRAM0WRENLO(1U)
+
+#define S_EDRAM0RDENLO    0
+#define V_EDRAM0RDENLO(x) ((x) << S_EDRAM0RDENLO)
+#define F_EDRAM0RDENLO    V_EDRAM0RDENLO(1U)
+
+#define A_EDC_H_DBG_EDRAM_WDATA_INTF 0x5031c
+
+#define S_EDRAMWDATA    9
+#define M_EDRAMWDATA    0x7fffffU
+#define V_EDRAMWDATA(x) ((x) << S_EDRAMWDATA)
+#define G_EDRAMWDATA(x) (((x) >> S_EDRAMWDATA) & M_EDRAMWDATA)
+
+#define S_EDRAMWBYTEEN    0
+#define M_EDRAMWBYTEEN    0x1ffU
+#define V_EDRAMWBYTEEN(x) ((x) << S_EDRAMWBYTEEN)
+#define G_EDRAMWBYTEEN(x) (((x) >> S_EDRAMWBYTEEN) & M_EDRAMWBYTEEN)
+
+#define A_EDC_H_DBG_EDRAM0_RDATA_INTF 0x50320
+#define A_EDC_H_DBG_EDRAM1_RDATA_INTF 0x50324
+#define A_EDC_H_DBG_MA_WR_REQ_CNT 0x50328
+#define A_EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT 0x5032c
+#define A_EDC_H_DBG_MA_WR_DAT_CYC_CNT 0x50330
+#define A_EDC_H_DBG_MA_RD_REQ_CNT 0x50334
+#define A_EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT 0x50338
+#define A_EDC_H_DBG_MA_RD_DAT_CYC_CNT 0x5033c
+#define A_EDC_H_DBG_BIST_WR_REQ_CNT 0x50340
+#define A_EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT 0x50344
+#define A_EDC_H_DBG_BIST_WR_DAT_CYC_CNT 0x50348
+#define A_EDC_H_DBG_BIST_RD_REQ_CNT 0x5034c
+#define A_EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT 0x50350
+#define A_EDC_H_DBG_BIST_RD_DAT_CYC_CNT 0x50354
+#define A_EDC_H_DBG_EDRAM0_WR_REQ_CNT 0x50358
+#define A_EDC_H_DBG_EDRAM0_RD_REQ_CNT 0x5035c
+#define A_EDC_H_DBG_EDRAM0_RMW_CNT 0x50360
+#define A_EDC_H_DBG_EDRAM1_WR_REQ_CNT 0x50364
+#define A_EDC_H_DBG_EDRAM1_RD_REQ_CNT 0x50368
+#define A_EDC_H_DBG_EDRAM1_RMW_CNT 0x5036c
+#define A_EDC_H_DBG_EDRAM_REF_BURST_CNT 0x50370
+#define A_EDC_H_DBG_FIFO_STATUS 0x50374
+
+#define S_RDTAG_NOTFULL    17
+#define V_RDTAG_NOTFULL(x) ((x) << S_RDTAG_NOTFULL)
+#define F_RDTAG_NOTFULL    V_RDTAG_NOTFULL(1U)
+
+#define S_RDTAG_NOTEMPTY    16
+#define V_RDTAG_NOTEMPTY(x) ((x) << S_RDTAG_NOTEMPTY)
+#define F_RDTAG_NOTEMPTY    V_RDTAG_NOTEMPTY(1U)
+
+#define S_INP_CMDQ_NOTFULL_ARB    15
+#define V_INP_CMDQ_NOTFULL_ARB(x) ((x) << S_INP_CMDQ_NOTFULL_ARB)
+#define F_INP_CMDQ_NOTFULL_ARB    V_INP_CMDQ_NOTFULL_ARB(1U)
+
+#define S_INP_CMDQ_NOTEMPTY    14
+#define V_INP_CMDQ_NOTEMPTY(x) ((x) << S_INP_CMDQ_NOTEMPTY)
+#define F_INP_CMDQ_NOTEMPTY    V_INP_CMDQ_NOTEMPTY(1U)
+
+#define S_INP_WRDQ_WRRDY    13
+#define V_INP_WRDQ_WRRDY(x) ((x) << S_INP_WRDQ_WRRDY)
+#define F_INP_WRDQ_WRRDY    V_INP_WRDQ_WRRDY(1U)
+
+#define S_INP_WRDQ_NOTEMPTY    12
+#define V_INP_WRDQ_NOTEMPTY(x) ((x) << S_INP_WRDQ_NOTEMPTY)
+#define F_INP_WRDQ_NOTEMPTY    V_INP_WRDQ_NOTEMPTY(1U)
+
+#define S_INP_BEQ_WRRDY_OPEN    11
+#define V_INP_BEQ_WRRDY_OPEN(x) ((x) << S_INP_BEQ_WRRDY_OPEN)
+#define F_INP_BEQ_WRRDY_OPEN    V_INP_BEQ_WRRDY_OPEN(1U)
+
+#define S_INP_BEQ_NOTEMPTY    10
+#define V_INP_BEQ_NOTEMPTY(x) ((x) << S_INP_BEQ_NOTEMPTY)
+#define F_INP_BEQ_NOTEMPTY    V_INP_BEQ_NOTEMPTY(1U)
+
+#define S_RDDQ_NOTFULL_OPEN    9
+#define V_RDDQ_NOTFULL_OPEN(x) ((x) << S_RDDQ_NOTFULL_OPEN)
+#define F_RDDQ_NOTFULL_OPEN    V_RDDQ_NOTFULL_OPEN(1U)
+
+#define S_RDDQ_RDCNT    4
+#define M_RDDQ_RDCNT    0x1fU
+#define V_RDDQ_RDCNT(x) ((x) << S_RDDQ_RDCNT)
+#define G_RDDQ_RDCNT(x) (((x) >> S_RDDQ_RDCNT) & M_RDDQ_RDCNT)
+
+#define S_RDSIDEQ_NOTFULL    3
+#define V_RDSIDEQ_NOTFULL(x) ((x) << S_RDSIDEQ_NOTFULL)
+#define F_RDSIDEQ_NOTFULL    V_RDSIDEQ_NOTFULL(1U)
+
+#define S_RDSIDEQ_NOTEMPTY    2
+#define V_RDSIDEQ_NOTEMPTY(x) ((x) << S_RDSIDEQ_NOTEMPTY)
+#define F_RDSIDEQ_NOTEMPTY    V_RDSIDEQ_NOTEMPTY(1U)
+
+#define S_STG_CMDQ_NOTEMPTY    1
+#define V_STG_CMDQ_NOTEMPTY(x) ((x) << S_STG_CMDQ_NOTEMPTY)
+#define F_STG_CMDQ_NOTEMPTY    V_STG_CMDQ_NOTEMPTY(1U)
+
+#define S_STG_WRDQ_NOTEMPTY    0
+#define V_STG_WRDQ_NOTEMPTY(x) ((x) << S_STG_WRDQ_NOTEMPTY)
+#define F_STG_WRDQ_NOTEMPTY    V_STG_WRDQ_NOTEMPTY(1U)
+
+#define A_EDC_H_DBG_FSM_STATE 0x50378
+
+#define S_CMDSPLITFSM    3
+#define V_CMDSPLITFSM(x) ((x) << S_CMDSPLITFSM)
+#define F_CMDSPLITFSM    V_CMDSPLITFSM(1U)
+
+#define S_CMDFSM    0
+#define M_CMDFSM    0x7U
+#define V_CMDFSM(x) ((x) << S_CMDFSM)
+#define G_CMDFSM(x) (((x) >> S_CMDFSM) & M_CMDFSM)
+
+#define A_EDC_H_DBG_STALL_CYCLES 0x5037c
+
+#define S_STALL_RMW    19
+#define V_STALL_RMW(x) ((x) << S_STALL_RMW)
+#define F_STALL_RMW    V_STALL_RMW(1U)
+
+#define S_STALL_EDC_CMD    18
+#define V_STALL_EDC_CMD(x) ((x) << S_STALL_EDC_CMD)
+#define F_STALL_EDC_CMD    V_STALL_EDC_CMD(1U)
+
+#define S_DEAD_CYCLE0    17
+#define V_DEAD_CYCLE0(x) ((x) << S_DEAD_CYCLE0)
+#define F_DEAD_CYCLE0    V_DEAD_CYCLE0(1U)
+
+#define S_DEAD_CYCLE1    16
+#define V_DEAD_CYCLE1(x) ((x) << S_DEAD_CYCLE1)
+#define F_DEAD_CYCLE1    V_DEAD_CYCLE1(1U)
+
+#define S_DEAD_CYCLE0_BBI    15
+#define V_DEAD_CYCLE0_BBI(x) ((x) << S_DEAD_CYCLE0_BBI)
+#define F_DEAD_CYCLE0_BBI    V_DEAD_CYCLE0_BBI(1U)
+
+#define S_DEAD_CYCLE1_BBI    14
+#define V_DEAD_CYCLE1_BBI(x) ((x) << S_DEAD_CYCLE1_BBI)
+#define F_DEAD_CYCLE1_BBI    V_DEAD_CYCLE1_BBI(1U)
+
+#define S_DEAD_CYCLE0_MAX_OP    13
+#define V_DEAD_CYCLE0_MAX_OP(x) ((x) << S_DEAD_CYCLE0_MAX_OP)
+#define F_DEAD_CYCLE0_MAX_OP    V_DEAD_CYCLE0_MAX_OP(1U)
+
+#define S_DEAD_CYCLE1_MAX_OP    12
+#define V_DEAD_CYCLE1_MAX_OP(x) ((x) << S_DEAD_CYCLE1_MAX_OP)
+#define F_DEAD_CYCLE1_MAX_OP    V_DEAD_CYCLE1_MAX_OP(1U)
+
+#define S_DEAD_CYCLE0_PRE_REF    11
+#define V_DEAD_CYCLE0_PRE_REF(x) ((x) << S_DEAD_CYCLE0_PRE_REF)
+#define F_DEAD_CYCLE0_PRE_REF    V_DEAD_CYCLE0_PRE_REF(1U)
+
+#define S_DEAD_CYCLE1_PRE_REF    10
+#define V_DEAD_CYCLE1_PRE_REF(x) ((x) << S_DEAD_CYCLE1_PRE_REF)
+#define F_DEAD_CYCLE1_PRE_REF    V_DEAD_CYCLE1_PRE_REF(1U)
+
+#define S_DEAD_CYCLE0_POST_REF    9
+#define V_DEAD_CYCLE0_POST_REF(x) ((x) << S_DEAD_CYCLE0_POST_REF)
+#define F_DEAD_CYCLE0_POST_REF    V_DEAD_CYCLE0_POST_REF(1U)
+
+#define S_DEAD_CYCLE1_POST_REF    8
+#define V_DEAD_CYCLE1_POST_REF(x) ((x) << S_DEAD_CYCLE1_POST_REF)
+#define F_DEAD_CYCLE1_POST_REF    V_DEAD_CYCLE1_POST_REF(1U)
+
+#define S_DEAD_CYCLE0_RMW    7
+#define V_DEAD_CYCLE0_RMW(x) ((x) << S_DEAD_CYCLE0_RMW)
+#define F_DEAD_CYCLE0_RMW    V_DEAD_CYCLE0_RMW(1U)
+
+#define S_DEAD_CYCLE1_RMW    6
+#define V_DEAD_CYCLE1_RMW(x) ((x) << S_DEAD_CYCLE1_RMW)
+#define F_DEAD_CYCLE1_RMW    V_DEAD_CYCLE1_RMW(1U)
+
+#define S_DEAD_CYCLE0_BBI_RMW    5
+#define V_DEAD_CYCLE0_BBI_RMW(x) ((x) << S_DEAD_CYCLE0_BBI_RMW)
+#define F_DEAD_CYCLE0_BBI_RMW    V_DEAD_CYCLE0_BBI_RMW(1U)
+
+#define S_DEAD_CYCLE1_BBI_RMW    4
+#define V_DEAD_CYCLE1_BBI_RMW(x) ((x) << S_DEAD_CYCLE1_BBI_RMW)
+#define F_DEAD_CYCLE1_BBI_RMW    V_DEAD_CYCLE1_BBI_RMW(1U)
+
+#define S_DEAD_CYCLE0_PRE_REF_RMW    3
+#define V_DEAD_CYCLE0_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE0_PRE_REF_RMW)
+#define F_DEAD_CYCLE0_PRE_REF_RMW    V_DEAD_CYCLE0_PRE_REF_RMW(1U)
+
+#define S_DEAD_CYCLE1_PRE_REF_RMW    2
+#define V_DEAD_CYCLE1_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE1_PRE_REF_RMW)
+#define F_DEAD_CYCLE1_PRE_REF_RMW    V_DEAD_CYCLE1_PRE_REF_RMW(1U)
+
+#define S_DEAD_CYCLE0_POST_REF_RMW    1
+#define V_DEAD_CYCLE0_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE0_POST_REF_RMW)
+#define F_DEAD_CYCLE0_POST_REF_RMW    V_DEAD_CYCLE0_POST_REF_RMW(1U)
+
+#define S_DEAD_CYCLE1_POST_REF_RMW    0
+#define V_DEAD_CYCLE1_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE1_POST_REF_RMW)
+#define F_DEAD_CYCLE1_POST_REF_RMW    V_DEAD_CYCLE1_POST_REF_RMW(1U)
+
+#define A_EDC_H_DBG_CMD_QUEUE 0x50380
+
+#define S_ECMDNRE    31
+#define V_ECMDNRE(x) ((x) << S_ECMDNRE)
+#define F_ECMDNRE    V_ECMDNRE(1U)
+
+#define S_ECMDNRB    30
+#define V_ECMDNRB(x) ((x) << S_ECMDNRB)
+#define F_ECMDNRB    V_ECMDNRB(1U)
+
+#define S_ECMDWR    29
+#define V_ECMDWR(x) ((x) << S_ECMDWR)
+#define F_ECMDWR    V_ECMDWR(1U)
+
+#define S_ECMDLEN    22
+#define M_ECMDLEN    0x7fU
+#define V_ECMDLEN(x) ((x) << S_ECMDLEN)
+#define G_ECMDLEN(x) (((x) >> S_ECMDLEN) & M_ECMDLEN)
+
+#define S_ECMDADDR    0
+#define M_ECMDADDR    0x3fffffU
+#define V_ECMDADDR(x) ((x) << S_ECMDADDR)
+#define G_ECMDADDR(x) (((x) >> S_ECMDADDR) & M_ECMDADDR)
+
+#define A_EDC_H_DBG_REFRESH 0x50384
+
+#define S_REFDONE    12
+#define V_REFDONE(x) ((x) << S_REFDONE)
+#define F_REFDONE    V_REFDONE(1U)
+
+#define S_REFCNTEXPR    11
+#define V_REFCNTEXPR(x) ((x) << S_REFCNTEXPR)
+#define F_REFCNTEXPR    V_REFCNTEXPR(1U)
+
+#define S_REFPTR    8
+#define M_REFPTR    0x7U
+#define V_REFPTR(x) ((x) << S_REFPTR)
+#define G_REFPTR(x) (((x) >> S_REFPTR) & M_REFPTR)
+
+#define S_REFCNT    0
+#define M_REFCNT    0xffU
+#define V_REFCNT(x) ((x) << S_REFCNT)
+#define G_REFCNT(x) (((x) >> S_REFCNT) & M_REFCNT)
+
+/* registers for module EDC_T61 */
+#define EDC_T61_BASE_ADDR 0x50800
+
+/* registers for module HMA_T6 */
+#define HMA_T6_BASE_ADDR 0x51000
+
+#define S_TPH    12
+#define M_TPH    0x3U
+#define V_TPH(x) ((x) << S_TPH)
+#define G_TPH(x) (((x) >> S_TPH) & M_TPH)
+
+#define S_TPH_V    11
+#define V_TPH_V(x) ((x) << S_TPH_V)
+#define F_TPH_V    V_TPH_V(1U)
+
+#define S_DCA    0
+#define M_DCA    0x7ffU
+#define V_DCA(x) ((x) << S_DCA)
+#define G_DCA(x) (((x) >> S_DCA) & M_DCA)
+
+#define A_HMA_CFG 0x51020
+
+#define S_OP_MODE    31
+#define V_OP_MODE(x) ((x) << S_OP_MODE)
+#define F_OP_MODE    V_OP_MODE(1U)
+
+#define A_HMA_TLB_ACCESS 0x51028
+
+#define S_INV_ALL    29
+#define V_INV_ALL(x) ((x) << S_INV_ALL)
+#define F_INV_ALL    V_INV_ALL(1U)
+
+#define S_LOCK_ENTRY    28
+#define V_LOCK_ENTRY(x) ((x) << S_LOCK_ENTRY)
+#define F_LOCK_ENTRY    V_LOCK_ENTRY(1U)
+
+#define S_E_SEL    0
+#define M_E_SEL    0x1fU
+#define V_E_SEL(x) ((x) << S_E_SEL)
+#define G_E_SEL(x) (((x) >> S_E_SEL) & M_E_SEL)
+
+#define A_HMA_TLB_BITS 0x5102c
+
+#define S_VA    12
+#define M_VA    0xfffffU
+#define V_VA(x) ((x) << S_VA)
+#define G_VA(x) (((x) >> S_VA) & M_VA)
+
+#define S_VALID_E    4
+#define V_VALID_E(x) ((x) << S_VALID_E)
+#define F_VALID_E    V_VALID_E(1U)
+
+#define S_LOCK_HMA    3
+#define V_LOCK_HMA(x) ((x) << S_LOCK_HMA)
+#define F_LOCK_HMA    V_LOCK_HMA(1U)
+
+#define S_T6_USED    2
+#define V_T6_USED(x) ((x) << S_T6_USED)
+#define F_T6_USED    V_T6_USED(1U)
+
+#define S_REGION    0
+#define M_REGION    0x3U
+#define V_REGION(x) ((x) << S_REGION)
+#define G_REGION(x) (((x) >> S_REGION) & M_REGION)
+
+#define A_HMA_TLB_DESC_0_H 0x51030
+#define A_HMA_TLB_DESC_0_L 0x51034
+#define A_HMA_TLB_DESC_1_H 0x51038
+#define A_HMA_TLB_DESC_1_L 0x5103c
+#define A_HMA_TLB_DESC_2_H 0x51040
+#define A_HMA_TLB_DESC_2_L 0x51044
+#define A_HMA_TLB_DESC_3_H 0x51048
+#define A_HMA_TLB_DESC_3_L 0x5104c
+#define A_HMA_TLB_DESC_4_H 0x51050
+#define A_HMA_TLB_DESC_4_L 0x51054
+#define A_HMA_TLB_DESC_5_H 0x51058
+#define A_HMA_TLB_DESC_5_L 0x5105c
+#define A_HMA_TLB_DESC_6_H 0x51060
+#define A_HMA_TLB_DESC_6_L 0x51064
+#define A_HMA_TLB_DESC_7_H 0x51068
+#define A_HMA_TLB_DESC_7_L 0x5106c
+#define A_HMA_REG0_MIN 0x51070
+
+#define S_ADDR0_MIN    12
+#define M_ADDR0_MIN    0xfffffU
+#define V_ADDR0_MIN(x) ((x) << S_ADDR0_MIN)
+#define G_ADDR0_MIN(x) (((x) >> S_ADDR0_MIN) & M_ADDR0_MIN)
+
+#define A_HMA_REG0_MAX 0x51074
+
+#define S_ADDR0_MAX    12
+#define M_ADDR0_MAX    0xfffffU
+#define V_ADDR0_MAX(x) ((x) << S_ADDR0_MAX)
+#define G_ADDR0_MAX(x) (((x) >> S_ADDR0_MAX) & M_ADDR0_MAX)
+
+#define A_HMA_REG0_MASK 0x51078
+
+#define S_PAGE_SIZE0    12
+#define M_PAGE_SIZE0    0xfffffU
+#define V_PAGE_SIZE0(x) ((x) << S_PAGE_SIZE0)
+#define G_PAGE_SIZE0(x) (((x) >> S_PAGE_SIZE0) & M_PAGE_SIZE0)
+
+#define A_HMA_REG0_BASE 0x5107c
+#define A_HMA_REG1_MIN 0x51080
+
+#define S_ADDR1_MIN    12
+#define M_ADDR1_MIN    0xfffffU
+#define V_ADDR1_MIN(x) ((x) << S_ADDR1_MIN)
+#define G_ADDR1_MIN(x) (((x) >> S_ADDR1_MIN) & M_ADDR1_MIN)
+
+#define A_HMA_REG1_MAX 0x51084
+
+#define S_ADDR1_MAX    12
+#define M_ADDR1_MAX    0xfffffU
+#define V_ADDR1_MAX(x) ((x) << S_ADDR1_MAX)
+#define G_ADDR1_MAX(x) (((x) >> S_ADDR1_MAX) & M_ADDR1_MAX)
+
+#define A_HMA_REG1_MASK 0x51088
+
+#define S_PAGE_SIZE1    12
+#define M_PAGE_SIZE1    0xfffffU
+#define V_PAGE_SIZE1(x) ((x) << S_PAGE_SIZE1)
+#define G_PAGE_SIZE1(x) (((x) >> S_PAGE_SIZE1) & M_PAGE_SIZE1)
+
+#define A_HMA_REG1_BASE 0x5108c
+#define A_HMA_REG2_MIN 0x51090
+
+#define S_ADDR2_MIN    12
+#define M_ADDR2_MIN    0xfffffU
+#define V_ADDR2_MIN(x) ((x) << S_ADDR2_MIN)
+#define G_ADDR2_MIN(x) (((x) >> S_ADDR2_MIN) & M_ADDR2_MIN)
+
+#define A_HMA_REG2_MAX 0x51094
+
+#define S_ADDR2_MAX    12
+#define M_ADDR2_MAX    0xfffffU
+#define V_ADDR2_MAX(x) ((x) << S_ADDR2_MAX)
+#define G_ADDR2_MAX(x) (((x) >> S_ADDR2_MAX) & M_ADDR2_MAX)
+
+#define A_HMA_REG2_MASK 0x51098
+
+#define S_PAGE_SIZE2    12
+#define M_PAGE_SIZE2    0xfffffU
+#define V_PAGE_SIZE2(x) ((x) << S_PAGE_SIZE2)
+#define G_PAGE_SIZE2(x) (((x) >> S_PAGE_SIZE2) & M_PAGE_SIZE2)
+
+#define A_HMA_REG2_BASE 0x5109c
+#define A_HMA_REG3_MIN 0x510a0
+
+#define S_ADDR3_MIN    12
+#define M_ADDR3_MIN    0xfffffU
+#define V_ADDR3_MIN(x) ((x) << S_ADDR3_MIN)
+#define G_ADDR3_MIN(x) (((x) >> S_ADDR3_MIN) & M_ADDR3_MIN)
+
+#define A_HMA_REG3_MAX 0x510a4
+
+#define S_ADDR3_MAX    12
+#define M_ADDR3_MAX    0xfffffU
+#define V_ADDR3_MAX(x) ((x) << S_ADDR3_MAX)
+#define G_ADDR3_MAX(x) (((x) >> S_ADDR3_MAX) & M_ADDR3_MAX)
+
+#define A_HMA_REG3_MASK 0x510a8
+
+#define S_PAGE_SIZE3    12
+#define M_PAGE_SIZE3    0xfffffU
+#define V_PAGE_SIZE3(x) ((x) << S_PAGE_SIZE3)
+#define G_PAGE_SIZE3(x) (((x) >> S_PAGE_SIZE3) & M_PAGE_SIZE3)
+
+#define A_HMA_REG3_BASE 0x510ac
+#define A_HMA_SW_SYNC 0x510b0
+
+#define S_ENTER_SYNC    31
+#define V_ENTER_SYNC(x) ((x) << S_ENTER_SYNC)
+#define F_ENTER_SYNC    V_ENTER_SYNC(1U)
+
+#define S_EXIT_SYNC    30
+#define V_EXIT_SYNC(x) ((x) << S_EXIT_SYNC)
+#define F_EXIT_SYNC    V_EXIT_SYNC(1U)
+
+#define S_IDTF_INT_ENABLE    5
+#define V_IDTF_INT_ENABLE(x) ((x) << S_IDTF_INT_ENABLE)
+#define F_IDTF_INT_ENABLE    V_IDTF_INT_ENABLE(1U)
+
+#define S_OTF_INT_ENABLE    4
+#define V_OTF_INT_ENABLE(x) ((x) << S_OTF_INT_ENABLE)
+#define F_OTF_INT_ENABLE    V_OTF_INT_ENABLE(1U)
+
+#define S_RTF_INT_ENABLE    3
+#define V_RTF_INT_ENABLE(x) ((x) << S_RTF_INT_ENABLE)
+#define F_RTF_INT_ENABLE    V_RTF_INT_ENABLE(1U)
+
+#define S_PCIEMST_INT_ENABLE    2
+#define V_PCIEMST_INT_ENABLE(x) ((x) << S_PCIEMST_INT_ENABLE)
+#define F_PCIEMST_INT_ENABLE    V_PCIEMST_INT_ENABLE(1U)
+
+#define S_MAMST_INT_ENABLE    1
+#define V_MAMST_INT_ENABLE(x) ((x) << S_MAMST_INT_ENABLE)
+#define F_MAMST_INT_ENABLE    V_MAMST_INT_ENABLE(1U)
+
+#define S_IDTF_INT_CAUSE    5
+#define V_IDTF_INT_CAUSE(x) ((x) << S_IDTF_INT_CAUSE)
+#define F_IDTF_INT_CAUSE    V_IDTF_INT_CAUSE(1U)
+
+#define S_OTF_INT_CAUSE    4
+#define V_OTF_INT_CAUSE(x) ((x) << S_OTF_INT_CAUSE)
+#define F_OTF_INT_CAUSE    V_OTF_INT_CAUSE(1U)
+
+#define S_RTF_INT_CAUSE    3
+#define V_RTF_INT_CAUSE(x) ((x) << S_RTF_INT_CAUSE)
+#define F_RTF_INT_CAUSE    V_RTF_INT_CAUSE(1U)
+
+#define S_PCIEMST_INT_CAUSE    2
+#define V_PCIEMST_INT_CAUSE(x) ((x) << S_PCIEMST_INT_CAUSE)
+#define F_PCIEMST_INT_CAUSE    V_PCIEMST_INT_CAUSE(1U)
+
+#define S_MAMST_INT_CAUSE    1
+#define V_MAMST_INT_CAUSE(x) ((x) << S_MAMST_INT_CAUSE)
+#define F_MAMST_INT_CAUSE    V_MAMST_INT_CAUSE(1U)
+
+#define A_HMA_MA_MST_ERR 0x5130c
+#define A_HMA_RTF_ERR 0x51310
+#define A_HMA_OTF_ERR 0x51314
+#define A_HMA_IDTF_ERR 0x51318
+#define A_HMA_EXIT_TF 0x5131c
+
+#define S_RTF    30
+#define V_RTF(x) ((x) << S_RTF)
+#define F_RTF    V_RTF(1U)
+
+#define S_OTF    29
+#define V_OTF(x) ((x) << S_OTF)
+#define F_OTF    V_OTF(1U)
+
+#define S_IDTF    28
+#define V_IDTF(x) ((x) << S_IDTF)
+#define F_IDTF    V_IDTF(1U)
+
+#define A_HMA_LOCAL_DEBUG_CFG 0x51320
+#define A_HMA_LOCAL_DEBUG_RPT 0x51324
+#define A_HMA_DEBUG_FSM_0 0xa000
+
+#define S_EDC_FSM    18
+#define M_EDC_FSM    0x1fU
+#define V_EDC_FSM(x) ((x) << S_EDC_FSM)
+#define G_EDC_FSM(x) (((x) >> S_EDC_FSM) & M_EDC_FSM)
+
+#define S_RAS_FSM_SLV    15
+#define M_RAS_FSM_SLV    0x7U
+#define V_RAS_FSM_SLV(x) ((x) << S_RAS_FSM_SLV)
+#define G_RAS_FSM_SLV(x) (((x) >> S_RAS_FSM_SLV) & M_RAS_FSM_SLV)
+
+#define S_FC_FSM    10
+#define M_FC_FSM    0x1fU
+#define V_FC_FSM(x) ((x) << S_FC_FSM)
+#define G_FC_FSM(x) (((x) >> S_FC_FSM) & M_FC_FSM)
+
+#define S_COOKIE_ARB_FSM    8
+#define M_COOKIE_ARB_FSM    0x3U
+#define V_COOKIE_ARB_FSM(x) ((x) << S_COOKIE_ARB_FSM)
+#define G_COOKIE_ARB_FSM(x) (((x) >> S_COOKIE_ARB_FSM) & M_COOKIE_ARB_FSM)
+
+#define S_PCIE_CHUNK_FSM    6
+#define M_PCIE_CHUNK_FSM    0x3U
+#define V_PCIE_CHUNK_FSM(x) ((x) << S_PCIE_CHUNK_FSM)
+#define G_PCIE_CHUNK_FSM(x) (((x) >> S_PCIE_CHUNK_FSM) & M_PCIE_CHUNK_FSM)
+
+#define S_WTRANSFER_FSM    4
+#define M_WTRANSFER_FSM    0x3U
+#define V_WTRANSFER_FSM(x) ((x) << S_WTRANSFER_FSM)
+#define G_WTRANSFER_FSM(x) (((x) >> S_WTRANSFER_FSM) & M_WTRANSFER_FSM)
+
+#define S_WD_FSM    2
+#define M_WD_FSM    0x3U
+#define V_WD_FSM(x) ((x) << S_WD_FSM)
+#define G_WD_FSM(x) (((x) >> S_WD_FSM) & M_WD_FSM)
+
+#define S_RD_FSM    0
+#define M_RD_FSM    0x3U
+#define V_RD_FSM(x) ((x) << S_RD_FSM)
+#define G_RD_FSM(x) (((x) >> S_RD_FSM) & M_RD_FSM)
+
+#define A_HMA_DEBUG_FSM_1 0xa001
+
+#define S_SYNC_FSM    11
+#define M_SYNC_FSM    0x3ffU
+#define V_SYNC_FSM(x) ((x) << S_SYNC_FSM)
+#define G_SYNC_FSM(x) (((x) >> S_SYNC_FSM) & M_SYNC_FSM)
+
+#define S_OCHK_FSM    9
+#define M_OCHK_FSM    0x3U
+#define V_OCHK_FSM(x) ((x) << S_OCHK_FSM)
+#define G_OCHK_FSM(x) (((x) >> S_OCHK_FSM) & M_OCHK_FSM)
+
+#define S_TLB_FSM    5
+#define M_TLB_FSM    0xfU
+#define V_TLB_FSM(x) ((x) << S_TLB_FSM)
+#define G_TLB_FSM(x) (((x) >> S_TLB_FSM) & M_TLB_FSM)
+
+#define S_PIO_FSM    0
+#define M_PIO_FSM    0x1fU
+#define V_PIO_FSM(x) ((x) << S_PIO_FSM)
+#define G_PIO_FSM(x) (((x) >> S_PIO_FSM) & M_PIO_FSM)
+
+#define A_HMA_DEBUG_PCIE_INTF 0xa002
+
+#define S_T6_H_REQVLD    28
+#define V_T6_H_REQVLD(x) ((x) << S_T6_H_REQVLD)
+#define F_T6_H_REQVLD    V_T6_H_REQVLD(1U)
+
+#define S_H_REQFULL    27
+#define V_H_REQFULL(x) ((x) << S_H_REQFULL)
+#define F_H_REQFULL    V_H_REQFULL(1U)
+
+#define S_H_REQSOP    26
+#define V_H_REQSOP(x) ((x) << S_H_REQSOP)
+#define F_H_REQSOP    V_H_REQSOP(1U)
+
+#define S_H_REQEOP    25
+#define V_H_REQEOP(x) ((x) << S_H_REQEOP)
+#define F_H_REQEOP    V_H_REQEOP(1U)
+
+#define S_T6_H_RSPVLD    24
+#define V_T6_H_RSPVLD(x) ((x) << S_T6_H_RSPVLD)
+#define F_T6_H_RSPVLD    V_T6_H_RSPVLD(1U)
+
+#define S_H_RSPFULL    23
+#define V_H_RSPFULL(x) ((x) << S_H_RSPFULL)
+#define F_H_RSPFULL    V_H_RSPFULL(1U)
+
+#define S_H_RSPSOP    22
+#define V_H_RSPSOP(x) ((x) << S_H_RSPSOP)
+#define F_H_RSPSOP    V_H_RSPSOP(1U)
+
+#define S_H_RSPEOP    21
+#define V_H_RSPEOP(x) ((x) << S_H_RSPEOP)
+#define F_H_RSPEOP    V_H_RSPEOP(1U)
+
+#define S_H_RSPERR    20
+#define V_H_RSPERR(x) ((x) << S_H_RSPERR)
+#define F_H_RSPERR    V_H_RSPERR(1U)
+
+#define S_PCIE_CMD_AVAIL    19
+#define V_PCIE_CMD_AVAIL(x) ((x) << S_PCIE_CMD_AVAIL)
+#define F_PCIE_CMD_AVAIL    V_PCIE_CMD_AVAIL(1U)
+
+#define S_PCIE_CMD_RDY    18
+#define V_PCIE_CMD_RDY(x) ((x) << S_PCIE_CMD_RDY)
+#define F_PCIE_CMD_RDY    V_PCIE_CMD_RDY(1U)
+
+#define S_PCIE_WNR    17
+#define V_PCIE_WNR(x) ((x) << S_PCIE_WNR)
+#define F_PCIE_WNR    V_PCIE_WNR(1U)
+
+#define S_PCIE_LEN    9
+#define M_PCIE_LEN    0xffU
+#define V_PCIE_LEN(x) ((x) << S_PCIE_LEN)
+#define G_PCIE_LEN(x) (((x) >> S_PCIE_LEN) & M_PCIE_LEN)
+
+#define S_PCIE_TRWDAT_RDY    8
+#define V_PCIE_TRWDAT_RDY(x) ((x) << S_PCIE_TRWDAT_RDY)
+#define F_PCIE_TRWDAT_RDY    V_PCIE_TRWDAT_RDY(1U)
+
+#define S_PCIE_TRWDAT_AVAIL    7
+#define V_PCIE_TRWDAT_AVAIL(x) ((x) << S_PCIE_TRWDAT_AVAIL)
+#define F_PCIE_TRWDAT_AVAIL    V_PCIE_TRWDAT_AVAIL(1U)
+
+#define S_PCIE_TRWSOP    6
+#define V_PCIE_TRWSOP(x) ((x) << S_PCIE_TRWSOP)
+#define F_PCIE_TRWSOP    V_PCIE_TRWSOP(1U)
+
+#define S_PCIE_TRWEOP    5
+#define V_PCIE_TRWEOP(x) ((x) << S_PCIE_TRWEOP)
+#define F_PCIE_TRWEOP    V_PCIE_TRWEOP(1U)
+
+#define S_PCIE_TRRDAT_RDY    4
+#define V_PCIE_TRRDAT_RDY(x) ((x) << S_PCIE_TRRDAT_RDY)
+#define F_PCIE_TRRDAT_RDY    V_PCIE_TRRDAT_RDY(1U)
+
+#define S_PCIE_TRRDAT_AVAIL    3
+#define V_PCIE_TRRDAT_AVAIL(x) ((x) << S_PCIE_TRRDAT_AVAIL)
+#define F_PCIE_TRRDAT_AVAIL    V_PCIE_TRRDAT_AVAIL(1U)
+
+#define S_PCIE_TRRSOP    2
+#define V_PCIE_TRRSOP(x) ((x) << S_PCIE_TRRSOP)
+#define F_PCIE_TRRSOP    V_PCIE_TRRSOP(1U)
+
+#define S_PCIE_TRREOP    1
+#define V_PCIE_TRREOP(x) ((x) << S_PCIE_TRREOP)
+#define F_PCIE_TRREOP    V_PCIE_TRREOP(1U)
+
+#define S_PCIE_TRRERR    0
+#define V_PCIE_TRRERR(x) ((x) << S_PCIE_TRRERR)
+#define F_PCIE_TRRERR    V_PCIE_TRRERR(1U)
+
+#define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_LO 0xa003
+#define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_HI 0xa004
+#define A_HMA_DEBUG_PCIE_REQ_DATA_EXTERNAL 0xa005
+
+#define S_REQDATA2    24
+#define M_REQDATA2    0xffU
+#define V_REQDATA2(x) ((x) << S_REQDATA2)
+#define G_REQDATA2(x) (((x) >> S_REQDATA2) & M_REQDATA2)
+
+#define S_REQDATA1    21
+#define M_REQDATA1    0x7U
+#define V_REQDATA1(x) ((x) << S_REQDATA1)
+#define G_REQDATA1(x) (((x) >> S_REQDATA1) & M_REQDATA1)
+
+#define S_REQDATA0    0
+#define M_REQDATA0    0x1fffffU
+#define V_REQDATA0(x) ((x) << S_REQDATA0)
+#define G_REQDATA0(x) (((x) >> S_REQDATA0) & M_REQDATA0)
+
+#define A_HMA_DEBUG_PCIE_RSP_DATA_EXTERNAL 0xa006
+
+#define S_RSPDATA3    24
+#define M_RSPDATA3    0xffU
+#define V_RSPDATA3(x) ((x) << S_RSPDATA3)
+#define G_RSPDATA3(x) (((x) >> S_RSPDATA3) & M_RSPDATA3)
+
+#define S_RSPDATA2    16
+#define M_RSPDATA2    0xffU
+#define V_RSPDATA2(x) ((x) << S_RSPDATA2)
+#define G_RSPDATA2(x) (((x) >> S_RSPDATA2) & M_RSPDATA2)
+
+#define S_RSPDATA1    8
+#define M_RSPDATA1    0xffU
+#define V_RSPDATA1(x) ((x) << S_RSPDATA1)
+#define G_RSPDATA1(x) (((x) >> S_RSPDATA1) & M_RSPDATA1)
+
+#define S_RSPDATA0    0
+#define M_RSPDATA0    0xffU
+#define V_RSPDATA0(x) ((x) << S_RSPDATA0)
+#define G_RSPDATA0(x) (((x) >> S_RSPDATA0) & M_RSPDATA0)
+
+#define A_HMA_DEBUG_MA_SLV_CTL 0xa007
+
+#define S_MA_CMD_AVAIL    19
+#define V_MA_CMD_AVAIL(x) ((x) << S_MA_CMD_AVAIL)
+#define F_MA_CMD_AVAIL    V_MA_CMD_AVAIL(1U)
+
+#define S_MA_CLNT    15
+#define M_MA_CLNT    0xfU
+#define V_MA_CLNT(x) ((x) << S_MA_CLNT)
+#define G_MA_CLNT(x) (((x) >> S_MA_CLNT) & M_MA_CLNT)
+
+#define S_MA_WNR    14
+#define V_MA_WNR(x) ((x) << S_MA_WNR)
+#define F_MA_WNR    V_MA_WNR(1U)
+
+#define S_MA_LEN    6
+#define M_MA_LEN    0xffU
+#define V_MA_LEN(x) ((x) << S_MA_LEN)
+#define G_MA_LEN(x) (((x) >> S_MA_LEN) & M_MA_LEN)
+
+#define S_MA_MST_RD    5
+#define V_MA_MST_RD(x) ((x) << S_MA_MST_RD)
+#define F_MA_MST_RD    V_MA_MST_RD(1U)
+
+#define S_MA_MST_VLD    4
+#define V_MA_MST_VLD(x) ((x) << S_MA_MST_VLD)
+#define F_MA_MST_VLD    V_MA_MST_VLD(1U)
+
+#define S_MA_MST_ERR    3
+#define V_MA_MST_ERR(x) ((x) << S_MA_MST_ERR)
+#define F_MA_MST_ERR    V_MA_MST_ERR(1U)
+
+#define S_MAS_TLB_REQ    2
+#define V_MAS_TLB_REQ(x) ((x) << S_MAS_TLB_REQ)
+#define F_MAS_TLB_REQ    V_MAS_TLB_REQ(1U)
+
+#define S_MAS_TLB_ACK    1
+#define V_MAS_TLB_ACK(x) ((x) << S_MAS_TLB_ACK)
+#define F_MAS_TLB_ACK    V_MAS_TLB_ACK(1U)
+
+#define S_MAS_TLB_ERR    0
+#define V_MAS_TLB_ERR(x) ((x) << S_MAS_TLB_ERR)
+#define F_MAS_TLB_ERR    V_MAS_TLB_ERR(1U)
+
+#define A_HMA_DEBUG_MA_SLV_ADDR_INTERNAL 0xa008
+#define A_HMA_DEBUG_TLB_HIT_ENTRY 0xa009
+#define A_HMA_DEBUG_TLB_HIT_CNT 0xa00a
+#define A_HMA_DEBUG_TLB_MISS_CNT 0xa00b
+#define A_HMA_DEBUG_PAGE_TBL_LKP_CTL 0xa00c
+
+#define S_LKP_REQ_VLD    4
+#define V_LKP_REQ_VLD(x) ((x) << S_LKP_REQ_VLD)
+#define F_LKP_REQ_VLD    V_LKP_REQ_VLD(1U)
+
+#define S_LKP_DESC_SEL    1
+#define M_LKP_DESC_SEL    0x7U
+#define V_LKP_DESC_SEL(x) ((x) << S_LKP_DESC_SEL)
+#define G_LKP_DESC_SEL(x) (((x) >> S_LKP_DESC_SEL) & M_LKP_DESC_SEL)
+
+#define S_LKP_RSP_VLD    0
+#define V_LKP_RSP_VLD(x) ((x) << S_LKP_RSP_VLD)
+#define F_LKP_RSP_VLD    V_LKP_RSP_VLD(1U)
+
+#define A_HMA_DEBUG_PAGE_TBL_LKP_REQ_ADDR 0xa00d
+#define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_0 0xa00e
+#define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_1 0xa00f
+#define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_2 0xa010
+#define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_3 0xa011
+#define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_4 0xa012
+#define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_5 0xa013
+#define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_6 0xa014
+#define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_7 0xa015
+#define A_HMA_DEBUG_PHYS_DESC_INTERNAL_LO 0xa016
+#define A_HMA_DEBUG_PCIE_RD_REQ_CNT_LO 0xa017
+#define A_HMA_DEBUG_PCIE_RD_REQ_CNT_HI 0xa018
+#define A_HMA_DEBUG_PCIE_WR_REQ_CNT_LO 0xa019
+#define A_HMA_DEBUG_PCIE_WR_REQ_CNT_HI 0xa01a
+#define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_LO 0xa01b
+#define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_HI 0xa01c
+#define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_LO 0xa01d
+#define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_HI 0xa01e
+#define A_HMA_DEBUG_PCIE_SOP_EOP_CNT 0xa01f
+
+#define S_WR_EOP_CNT    16
+#define M_WR_EOP_CNT    0xffU
+#define V_WR_EOP_CNT(x) ((x) << S_WR_EOP_CNT)
+#define G_WR_EOP_CNT(x) (((x) >> S_WR_EOP_CNT) & M_WR_EOP_CNT)
+
+#define S_RD_SOP_CNT    8
+#define M_RD_SOP_CNT    0xffU
+#define V_RD_SOP_CNT(x) ((x) << S_RD_SOP_CNT)
+#define G_RD_SOP_CNT(x) (((x) >> S_RD_SOP_CNT) & M_RD_SOP_CNT)
+
+#define S_RD_EOP_CNT    0
+#define M_RD_EOP_CNT    0xffU
+#define V_RD_EOP_CNT(x) ((x) << S_RD_EOP_CNT)
+#define G_RD_EOP_CNT(x) (((x) >> S_RD_EOP_CNT) & M_RD_EOP_CNT)
diff --git a/contrib/ofed/libcxgb4/src/verbs.c b/contrib/ofed/libcxgb4/src/verbs.c
index 4d2a69d27427..6b99c75f1e37 100644
--- a/contrib/ofed/libcxgb4/src/verbs.c
+++ b/contrib/ofed/libcxgb4/src/verbs.c
@@ -212,10 +212,10 @@ struct ibv_cq *c4iw_create_cq(struct ibv_context *context, int cqe,
 	if (chp->cq.ugts == MAP_FAILED)
 		goto err3;
 
-	if (dev_is_t5(chp->rhp))
-		chp->cq.ugts += 5;
-	else
+	if (dev_is_t4(chp->rhp))
 		chp->cq.ugts += 1;
+	else
+		chp->cq.ugts += 5;
 	chp->cq.sw_queue = calloc(chp->cq.size, sizeof *chp->cq.queue);
 	if (!chp->cq.sw_queue)
 		goto err4;