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authorKyle Crenshaw <B1nc0d3x@gmail.com>2026-05-14 21:07:42 +0000
committerMitchell Horne <mhorne@FreeBSD.org>2026-05-27 18:21:19 +0000
commitccda002ca10f9fb88e65d4bc27f0676e6f97d16d (patch)
tree1043161b80745d40ab4fa2b65b7854408d24e53e /gnu/tests/Makefile.depend
parentd1488cd762bee79240a715bf04f3d30e9a121b26 (diff)
rk_gpio: implement PIC masking methods and mask unhandled IRQs
The Rockchip GPIO controller implements PIC operations for the INTRNG framework but is missing four masking methods that INTRNG calls during the filter/ithread handoff: pic_disable_intr, pic_enable_intr, pic_pre_ithread, pic_post_ithread. Without them, level-sensitive interrupt sources connected to a Rockchip GPIO pin re-fire continuously while their ithread runs. On a RockPro64 with a FUSB302B Type-C controller (i2c) attached to gpio1 INT_N, the system enters a ~210 kHz interrupt storm the moment the fusb302 driver attaches and INT_N goes low. Two complementary changes: 1. Add the four pic_disable_intr/pic_enable_intr/pic_pre_ithread/ pic_post_ithread method bodies. Each toggles the pin's RK_GPIO_INTMASK bit so the source is masked during the in-flight ithread window and unmasked on return, honouring the generic INTRNG mask/unmask sequence. 2. When the GPIO IRQ filter dispatches a pin and finds no consumer registered, mask the pin at the controller (INTMASK=1, INTEN=0) before continuing. Level-triggered sources keep asserting until acked, so a single stuck pin used to flood the console with thousands of "Interrupt pin=N unhandled" lines per second. The mask survives until something re-attaches and re-enables the IRQ via the standard pic_enable_intr path. Affects all level-triggered IRQs on Rockchip GPIO banks; edge- triggered IRQs were already self-acking and unaffected. Signed-off-by: Kyle Crenshaw <B1nc0d3x@gmail.com> Reviewed by: mhorne MFC after: 2 weeks Pull Request: https://github.com/freebsd/freebsd-src/pull/2197
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