e1000: Report 82576 memory ECC errorsHEADmain

82576 exposes clear-on-read corrected error counters for RX, TX,
switch, IPsec, descriptor-handler, PCIe retry, PCIe write, and
MSI-X memories.  The packet and descriptor memories also count
uncorrectable errors.

Sample each status register exactly once from the regular hardware
statistics update and immediately before handling a memory-error
interrupt.  Group the counters by packet buffer, descriptor handler,
and PCIe region.  Skip the absent IPsec block on 82576NS.

PRBESTS and PMSIXESTS are shared by both LAN ports.  Attribute an
indication to whichever attached port samples the clear-on-read
register first so it is not counted twice.

Hardware validation used an 82576EB revision 1.  All nine implemented
status registers reported their ECC-enable bit set.  The sysctl
counters remained clear across interface lifecycle, two-stream
line-rate traffic, and NFER and FER cause injections.  Each reset
preserved the ECC enables while the driver restored PEINDM reactions.

ICR cause injection does not corrupt SRAM, and the only documented
data injector is specific to the IPsec packet buffer.  Exact counter
increments for the other memories were therefore validated against
the register definitions rather than an injected ECC error.

MFC after:	2 weeks
Sponsored by:	BBOX.io

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