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| author | Dimitry Andric <dim@FreeBSD.org> | 2015-01-15 22:30:16 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-01-15 22:30:16 +0000 |
| commit | 9f61947910e6ab40de38e6b4034751ef1513200f (patch) | |
| tree | 3231b7529d89052b2edb92bb5ddc6a9e960e5161 /lib/Target/Mips/MipsInstrInfo.td | |
| parent | 5ca98fd98791947eba83a1ed3f2c8191ef7afa6c (diff) | |
| download | src-9f61947910e6ab40de38e6b4034751ef1513200f.tar.gz src-9f61947910e6ab40de38e6b4034751ef1513200f.zip | |
Vendor import of llvm RELEASE_351/final tag r225668 (effectively, 3.5.1 release):vendor/llvm/llvm-release_351-r225668
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=277220
svn path=/vendor/llvm/llvm-release_351-r225668/; revision=277221; tag=vendor/llvm/llvm-release_351-r225668
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 8e9472c2d9d8..26ecfbf6f4e6 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1414,13 +1414,15 @@ def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>; def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>; def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>; -class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> : +class CacheOp<string instr_asm, Operand MemOpnd> : InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), - !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther>; + !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther> { + let DecoderMethod = "DecodeCacheOp"; +} -def CACHE : CacheOp<"cache", mem, GPR32Opnd>, CACHEOP_FM<0b101111>, +def CACHE : CacheOp<"cache", mem>, CACHEOP_FM<0b101111>, INSN_MIPS3_32_NOT_32R6_64R6; -def PREF : CacheOp<"pref", mem, GPR32Opnd>, CACHEOP_FM<0b110011>, +def PREF : CacheOp<"pref", mem>, CACHEOP_FM<0b110011>, INSN_MIPS3_32_NOT_32R6_64R6; //===----------------------------------------------------------------------===// |