e1000: Report PCH packet buffer ECC statisticsHEADmain

PCH packet buffer ECC status contains read-clear byte counters for
corrected and uncorrected errors.  Sample them with the regular
hardware statistics update and account for the snapshot captured by
the fatal error interrupt path.

Expose the counters and the number of reset worthy interrupt
indications under dev.em.N.memory_errors.  Keeping the reset counter
separate also preserves evidence when another status reader wins the
read-clear race.

Hardware validation used an I219-LM.  Three documented ICS.ECCER
injections advanced fatal_resets from zero to three, exactly once per
reset.  corrected_packet_buffer and uncorrected_packet_buffer remained
zero, as expected because ICS does not inject a memory error or alter
PBECCSTS.

MFC after:	2 weeks
Sponsored by:	BBOX.io

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