pmc(3): remove Pentium-related man pages and references

Support for Pentium events was removed completely in e92a1350b50e.

Don't bump .Dd where we are just removing xrefs.

Reviewed by:	emaste
MFC after:	1 week
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D31423

(cherry picked from commit d78896e46f1d7744155919476c012400321d0dab)

29 files changed, 1 insertions, 2830 deletions

diff --git a/lib/libpmc/Makefile b/lib/libpmc/Makefile
index 285b6c539ece..2ef0d288064c 100644
--- a/lib/libpmc/Makefile
+++ b/lib/libpmc/Makefile
@@ -83,9 +83,6 @@ MAN+=	pmc.k7.3
 MAN+=	pmc.k8.3
 MAN+=	pmc.mips24k.3
 MAN+=	pmc.octeon.3
-MAN+=	pmc.p4.3
-MAN+=	pmc.p5.3
-MAN+=	pmc.p6.3
 MAN+=	pmc.sandybridge.3
 MAN+=	pmc.sandybridgeuc.3
 MAN+=	pmc.sandybridgexeon.3
diff --git a/lib/libpmc/pmc.3 b/lib/libpmc/pmc.3
index c70862668980..4bf2907db129 100644
--- a/lib/libpmc/pmc.3
+++ b/lib/libpmc/pmc.3
@@ -23,7 +23,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd December 12, 2020
+.Dd August 10, 2021
 .Dt PMC 3
 .Os
 .Sh NAME
@@ -161,26 +161,6 @@ and
 CPUs, and other CPUs conforming to version 2 of the
 .Tn Intel
 performance measurement architecture.
-.It Li PMC_CPU_INTEL_P5
-.Tn Intel
-.Tn "Pentium"
-CPUs.
-.It Li PMC_CPU_INTEL_P6
-.Tn Intel
-.Tn "Pentium Pro"
-CPUs.
-.It Li PMC_CPU_INTEL_PII
-.Tn "Intel Pentium II"
-CPUs.
-.It Li PMC_CPU_INTEL_PIII
-.Tn "Intel Pentium III"
-CPUs.
-.It Li PMC_CPU_INTEL_PIV
-.Tn "Intel Pentium 4"
-CPUs.
-.It Li PMC_CPU_INTEL_PM
-.Tn "Intel Pentium M"
-CPUs.
 .El
 .Ss Supported PMCs
 PMC supported by this library are named by the
@@ -205,25 +185,6 @@ CPUs.
 Programmable hardware counters present in
 .Tn "AMD Athlon64"
 CPUs.
-.It Li PMC_CLASS_P4
-Programmable hardware counters present in
-.Tn "Intel Pentium 4"
-CPUs.
-.It Li PMC_CLASS_P5
-Programmable hardware counters present in
-.Tn Intel
-.Tn Pentium
-CPUs.
-.It Li PMC_CLASS_P6
-Programmable hardware counters present in
-.Tn Intel
-.Tn "Pentium Pro" ,
-.Tn "Pentium II" ,
-.Tn "Pentium III" ,
-.Tn "Celeron" ,
-and
-.Tn "Pentium M"
-CPUs.
 .It Li PMC_CLASS_TSC
 The timestamp counter on i386 and amd64 architecture CPUs.
 .It Li PMC_CLASS_SOFT
@@ -473,9 +434,6 @@ following manual pages:
 .It Li PMC_CLASS_IAP    Ta Xr pmc.atom 3 , Xr pmc.core 3 , Xr pmc.core2 3
 .It Li PMC_CLASS_K7     Ta Xr pmc.k7 3
 .It Li PMC_CLASS_K8     Ta Xr pmc.k8 3
-.It Li PMC_CLASS_P4     Ta Xr pmc.p4 3
-.It Li PMC_CLASS_P5     Ta Xr pmc.p5 3
-.It Li PMC_CLASS_P6     Ta Xr pmc.p6 3
 .It Li PMC_CLASS_TSC    Ta Xr pmc.tsc 3
 .El
 .Ss Event Name Aliases
@@ -535,9 +493,6 @@ API is
 .Xr pmc.k8 3 ,
 .Xr pmc.mips24k 3 ,
 .Xr pmc.octeon 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.sandybridge 3 ,
 .Xr pmc.sandybridgeuc 3 ,
 .Xr pmc.sandybridgexeon 3 ,
diff --git a/lib/libpmc/pmc.atom.3 b/lib/libpmc/pmc.atom.3
index edf81ba54a5e..a79d14c9d4c1 100644
--- a/lib/libpmc/pmc.atom.3
+++ b/lib/libpmc/pmc.atom.3
@@ -1174,9 +1174,6 @@ and the underlying hardware events used on these CPUs.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc_cpuinfo 3 ,
diff --git a/lib/libpmc/pmc.atomsilvermont.3 b/lib/libpmc/pmc.atomsilvermont.3
index 7ed9de461e33..dd1f66a429c7 100644
--- a/lib/libpmc/pmc.atomsilvermont.3
+++ b/lib/libpmc/pmc.atomsilvermont.3
@@ -512,9 +512,6 @@ The number of times the MSROM starts a flow of UOPS.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc_cpuinfo 3 ,
diff --git a/lib/libpmc/pmc.core.3 b/lib/libpmc/pmc.core.3
index 551e615dc320..8d922cf3c1af 100644
--- a/lib/libpmc/pmc.core.3
+++ b/lib/libpmc/pmc.core.3
@@ -789,9 +789,6 @@ may not count some transitions.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmclog 3 ,
diff --git a/lib/libpmc/pmc.core2.3 b/lib/libpmc/pmc.core2.3
index cd038fb411d9..7c7049136c2b 100644
--- a/lib/libpmc/pmc.core2.3
+++ b/lib/libpmc/pmc.core2.3
@@ -1104,9 +1104,6 @@ and the underlying hardware events used.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc_cpuinfo 3 ,
diff --git a/lib/libpmc/pmc.corei7.3 b/lib/libpmc/pmc.corei7.3
index e9e2a6e61784..0c405d8e6e7f 100644
--- a/lib/libpmc/pmc.corei7.3
+++ b/lib/libpmc/pmc.corei7.3
@@ -1583,9 +1583,6 @@ Counts number of segment register loads.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc.ucf 3 ,
diff --git a/lib/libpmc/pmc.corei7uc.3 b/lib/libpmc/pmc.corei7uc.3
index 1f49222ceda6..a102a7b6c1b3 100644
--- a/lib/libpmc/pmc.corei7uc.3
+++ b/lib/libpmc/pmc.corei7uc.3
@@ -886,9 +886,6 @@ into a power down mode.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc.ucf 3 ,
diff --git a/lib/libpmc/pmc.haswell.3 b/lib/libpmc/pmc.haswell.3
index c69d4b694ca2..c858c702fdf1 100644
--- a/lib/libpmc/pmc.haswell.3
+++ b/lib/libpmc/pmc.haswell.3
@@ -921,9 +921,6 @@ Dirty L2 cache lines evicted by demand.
 .Xr pmc.ivybridgexeon 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.sandybridge 3 ,
 .Xr pmc.sandybridgeuc 3 ,
 .Xr pmc.sandybridgexeon 3 ,
diff --git a/lib/libpmc/pmc.haswelluc.3 b/lib/libpmc/pmc.haswelluc.3
index e7b57c59d0e5..a067a75201ce 100644
--- a/lib/libpmc/pmc.haswelluc.3
+++ b/lib/libpmc/pmc.haswelluc.3
@@ -205,9 +205,6 @@ Number of requests allocated in Coherency Tracker.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.sandybridge 3 ,
 .Xr pmc.sandybridgeuc 3 ,
 .Xr pmc.sandybridgexeon 3 ,
diff --git a/lib/libpmc/pmc.haswellxeon.3 b/lib/libpmc/pmc.haswellxeon.3
index 5f9a5b20eb5c..7610775adcb3 100644
--- a/lib/libpmc/pmc.haswellxeon.3
+++ b/lib/libpmc/pmc.haswellxeon.3
@@ -935,9 +935,6 @@ Dirty L2 cache lines evicted by demand.
 .Xr pmc.ivybridgexeon 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.sandybridge 3 ,
 .Xr pmc.sandybridgeuc 3 ,
 .Xr pmc.sandybridgexeon 3 ,
diff --git a/lib/libpmc/pmc.iaf.3 b/lib/libpmc/pmc.iaf.3
index f80560999f46..fcfa98042aaf 100644
--- a/lib/libpmc/pmc.iaf.3
+++ b/lib/libpmc/pmc.iaf.3
@@ -128,9 +128,6 @@ CPU, use the event specifier
 .Xr pmc.core2 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc_cpuinfo 3 ,
diff --git a/lib/libpmc/pmc.ivybridge.3 b/lib/libpmc/pmc.ivybridge.3
index d86199b4d407..938d2947a844 100644
--- a/lib/libpmc/pmc.ivybridge.3
+++ b/lib/libpmc/pmc.ivybridge.3
@@ -833,9 +833,6 @@ Dirty L2 cache lines evicted by the MLC prefetcher.
 .Xr pmc.ivybridgexeon 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.sandybridge 3 ,
 .Xr pmc.sandybridgeuc 3 ,
 .Xr pmc.sandybridgexeon 3 ,
diff --git a/lib/libpmc/pmc.ivybridgexeon.3 b/lib/libpmc/pmc.ivybridgexeon.3
index 1bbe16039bd2..9bcf4dbd56da 100644
--- a/lib/libpmc/pmc.ivybridgexeon.3
+++ b/lib/libpmc/pmc.ivybridgexeon.3
@@ -866,9 +866,6 @@ Dirty L2 cache lines filling the L2.
 .Xr pmc.ivybridge 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.sandybridge 3 ,
 .Xr pmc.sandybridgeuc 3 ,
 .Xr pmc.sandybridgexeon 3 ,
diff --git a/lib/libpmc/pmc.k7.3 b/lib/libpmc/pmc.k7.3
index a8be8143f9ea..42933f1958fb 100644
--- a/lib/libpmc/pmc.k7.3
+++ b/lib/libpmc/pmc.k7.3
@@ -246,9 +246,6 @@ and the underlying hardware events used.
 .Xr pmc.core2 3 ,
 .Xr pmc.iaf 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmclog 3 ,
diff --git a/lib/libpmc/pmc.k8.3 b/lib/libpmc/pmc.k8.3
index 45c70baa438c..cbfe617f31b1 100644
--- a/lib/libpmc/pmc.k8.3
+++ b/lib/libpmc/pmc.k8.3
@@ -779,9 +779,6 @@ and the underlying hardware events used.
 .Xr pmc.core2 3 ,
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmclog 3 ,
diff --git a/lib/libpmc/pmc.mips24k.3 b/lib/libpmc/pmc.mips24k.3
index d886d0e8c906..52761d5db751 100644
--- a/lib/libpmc/pmc.mips24k.3
+++ b/lib/libpmc/pmc.mips24k.3
@@ -389,9 +389,6 @@ and the underlying hardware events used.
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
 .Xr pmc.octeon 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc_cpuinfo 3 ,
diff --git a/lib/libpmc/pmc.octeon.3 b/lib/libpmc/pmc.octeon.3
index 019b448522e9..43d204f164e6 100644
--- a/lib/libpmc/pmc.octeon.3
+++ b/lib/libpmc/pmc.octeon.3
@@ -229,9 +229,6 @@ and the underlying hardware events used.
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
 .Xr pmc.mips24k 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc_cpuinfo 3 ,
diff --git a/lib/libpmc/pmc.p4.3 b/lib/libpmc/pmc.p4.3
deleted file mode 100644
index e113b72001e1..000000000000
--- a/lib/libpmc/pmc.p4.3
+++ /dev/null
@@ -1,1223 +0,0 @@
-.\" Copyright (c) 2003-2008 Joseph Koshy.  All rights reserved.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\"    notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\"    notice, this list of conditions and the following disclaimer in the
-.\"    documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.\" $FreeBSD$
-.\"
-.Dd October 4, 2008
-.Dt PMC.P4 3
-.Os
-.Sh NAME
-.Nm pmc.p4
-.Nd measurement events for
-.Tn "Intel Pentium 4"
-and other
-.Tn Netburst
-architecture CPUs
-.Sh LIBRARY
-.Lb libpmc
-.Sh SYNOPSIS
-.In pmc.h
-.Sh DESCRIPTION
-Intel P4 PMCs are present in Intel
-.Tn "Pentium 4"
-and
-.Tn Xeon
-processors that use the
-.Tn Netburst
-CPU architecture.
-.Pp
-These PMCs are documented in
-.Rs
-.%B "IA-32 Intel(R) Architecture Software Developer's Manual"
-.%T "Volume 3: System Programming Guide"
-.%N "Order Number 245472-012"
-.%D 2003
-.%Q "Intel Corporation"
-.Re
-Further information about using these PMCs may be found in
-.Rs
-.%B "IA-32 Intel(R) Architecture Optimization Guide"
-.%D 2003
-.%N "Order Number 248966-009"
-.%Q "Intel Corporation"
-.Re
-Some of these events are affected by processor errata described in
-.Rs
-.%B "Intel(R) Pentium(R) 4 Processor Specification Update"
-.%N "Document Number: 249199-059"
-.%D "April 2005"
-.%Q "Intel Corporation"
-.Re
-.Ss PMC Features
-Intel Pentium 4 PMCs are 40 bits wide.
-Each CPU contains 18 PMCs, divided into 4 groups with 4, 4, 4 and 6
-PMCs respectively.
-On processors with hyperthreading support, PMC resources are shared
-between logical processors.
-These PMCs support the following capabilities:
-.Bl -column "PMC_CAP_INTERRUPT" "Support"
-.It Em Capability Ta Em Support
-.It PMC_CAP_CASCADE Ta Yes
-.It PMC_CAP_EDGE Ta Yes
-.It PMC_CAP_INTERRUPT Ta Yes
-.It PMC_CAP_INVERT Ta Yes
-.It PMC_CAP_READ Ta Yes
-.It PMC_CAP_PRECISE Ta Unimplemented
-.It PMC_CAP_SYSTEM Ta Yes
-.It PMC_CAP_TAGGING Ta Yes
-.It PMC_CAP_THRESHOLD Ta Yes
-.It PMC_CAP_USER Ta Yes
-.It PMC_CAP_WRITE Ta Yes
-.El
-.Ss Event Qualifiers
-Event specifiers for Intel P4 PMCs can have the following common
-qualifiers:
-.Bl -tag -width indent
-.It Li active= Ns Ar choice
-(On P4 HTT CPUs) Filter event counting based on which logical
-processors are active.
-The allowed values of
-.Ar choice
-are:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count when either logical processor is active.
-.It Li both
-Count when both logical processors are active.
-.It Li none
-Count only when neither logical processor is active.
-.It Li single
-Count only when one logical processor is active.
-.El
-.Pp
-The default is
-.Dq Li both .
-.It Li cascade
-Configure the PMC to cascade onto its partner.
-See
-.Sx "Cascading P4 PMCs"
-below for more information.
-.It Li edge
-Configure the counter to count false to true transitions of the threshold
-comparison output.
-This qualifier only takes effect if a threshold qualifier has also been
-specified.
-.It Li complement
-Configure the counter to increment only when the event count seen is
-less than the threshold qualifier value specified.
-.It Li mask= Ns Ar qualifier
-Many event specifiers for Intel P4 PMCs need to be additionally
-qualified using a mask qualifier.
-The allowed syntax for these qualifiers is event specific and is
-described along with the events.
-.It Li os
-Configure the PMC to count when the CPL of the processor is 0.
-.It Li precise
-Select precise event based sampling.
-Precise sampling is supported by the hardware for a limited set of
-events.
-.It Li tag= Ns Ar value
-Configure the PMC to tag the internal uop selected by the other
-fields in this event specifier with value
-.Ar value .
-This feature is used when cascading PMCs.
-.It Li threshold= Ns Ar value
-Configure the PMC to increment only when the event counts seen are
-greater than the specified threshold value
-.Ar value .
-.It Li usr
-Configure the PMC to count when the CPL of the processor is 1, 2 or 3.
-.El
-.Pp
-If neither of the
-.Dq Li os
-or
-.Dq Li usr
-qualifiers are specified, the default is to enable both.
-.Pp
-On Intel Pentium 4 processors with HTT, events are
-divided into two classes:
-.Pp
-.Bl -tag -width indent -compact
-.It "TS Events"
-are those where hardware can differentiate between events
-generated on one logical processor from those generated on the
-other.
-.It "TI Events"
-are those where hardware cannot differentiate between events
-generated by multiple logical processors in a package.
-.El
-.Pp
-Only TS events are allowed for use with process-mode PMCs on
-Pentium-4/HTT CPUs.
-.Pp
-The event specifiers supported by Intel P4 PMCs are:
-.Bl -tag -width indent
-.It Li p4-128bit-mmx-uop Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count integer SIMD SSE2 instructions that operate on 128 bit SIMD
-operands.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count all uops operating on 128 bit SIMD integer operands in memory or
-XMM register.
-.El
-.Pp
-If an instruction contains more than one 128 bit MMX uop, then each
-uop will be counted.
-.It Li p4-64bit-mmx-uop Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count MMX instructions that operate on 64 bit SIMD operands.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count all uops operating on 64 bit SIMD integer operands in memory or
-in MMX registers.
-.El
-.Pp
-If an instruction contains more than one 64 bit MMX uop, then each
-uop will be counted.
-.It Li p4-b2b-cycles
-.Pq "TI event"
-Count back-to-back bus cycles.
-Further documentation for this event is unavailable.
-.It Li p4-bnr
-.Pq "TI event"
-Count bus-not-ready conditions.
-Further documentation for this event is unavailable.
-.It Li p4-bpu-fetch-request Op Li ,mask= Ns Ar qualifier
-.Pq "TS event"
-Count instruction fetch requests qualified by additional
-flags specified in
-.Ar qualifier .
-At this point only one flag is supported:
-.Pp
-.Bl -tag -width indent -compact
-.It Li tcmiss
-Count trace cache lookup misses.
-.El
-.Pp
-The default qualifier is also
-.Dq Li mask=tcmiss .
-.It Li p4-branch-retired Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Counts retired branches.
-Qualifier
-.Ar flags
-is a list of the following
-.Ql +
-separated strings:
-.Pp
-.Bl -tag -width indent -compact
-.It Li mmnp
-Count branches not-taken and predicted.
-.It Li mmnm
-Count branches not-taken and mis-predicted.
-.It Li mmtp
-Count branches taken and predicted.
-.It Li mmtm
-Count branches taken and mis-predicted.
-.El
-.Pp
-The default qualifier counts all four kinds of branches.
-.It Li p4-bsq-active-entries Op Li ,mask= Ns Ar qualifier
-.Pq "TS event"
-Count the number of entries (clipped at 15) currently active in the
-BSQ.
-Qualifier
-.Ar qualifier
-is a
-.Ql +
-separated set of the following flags:
-.Pp
-.Bl -tag -width indent -compact
-.It Li req-type0 , Li req-type1
-Forms a 2-bit number used to select the request type encoding:
-.Pp
-.Bl -tag -width indent -compact
-.It Li 0
-reads excluding read invalidate
-.It Li 1
-read invalidates
-.It Li 2
-writes other than writebacks
-.It Li 3
-writebacks
-.El
-.Pp
-Bit
-.Dq Li req-type1
-is the MSB for this two bit number.
-.It Li req-len0 , Li req-len1
-Forms a two-bit number that specifies the request length encoding:
-.Pp
-.Bl -tag -width indent -compact
-.It Li 0
-0 chunks
-.It Li 1
-1 chunk
-.It Li 3
-8 chunks
-.El
-.Pp
-Bit
-.Dq Li req-len1
-is the MSB for this two bit number.
-.It Li req-io-type
-Count requests that are input or output requests.
-.It Li req-lock-type
-Count requests that lock the bus.
-.It Li req-lock-cache
-Count requests that lock the cache.
-.It Li req-split-type
-Count requests that is a bus 8-byte chunk that is split across an
-8-byte boundary.
-.It Li req-dem-type
-Count requests that are demand (not prefetches) if set.
-Count requests that are prefetches if not set.
-.It Li req-ord-type
-Count requests that are ordered.
-.It Li mem-type0 , Li mem-type1 , Li mem-type2
-Forms a 3-bit number that specifies a memory type encoding:
-.Pp
-.Bl -tag -width indent -compact
-.It Li 0
-UC
-.It Li 1
-USWC
-.It Li 4
-WT
-.It Li 5
-WP
-.It Li 6
-WB
-.El
-.Pp
-Bit
-.Dq Li mem-type2
-is the MSB of this 3-bit number.
-.El
-.Pp
-The default qualifier has all the above bits set.
-.Pp
-Edge triggering using the
-.Dq Li edge
-qualifier should not be used with this event when counting cycles.
-.It Li p4-bsq-allocation Op Li ,mask= Ns Ar qualifier
-.Pq "TS event"
-Count allocations in the bus sequence unit according to the flags
-specified in
-.Ar qualifier ,
-which is a
-.Ql +
-separated set of the following flags:
-.Pp
-.Bl -tag -width indent -compact
-.It Li req-type0 , Li req-type1
-Forms a 2-bit number used to select the request type encoding:
-.Pp
-.Bl -tag -width indent -compact
-.It Li 0
-reads excluding read invalidate
-.It Li 1
-read invalidates
-.It Li 2
-writes other than writebacks
-.It Li 3
-writebacks
-.El
-.Pp
-Bit
-.Dq Li req-type1
-is the MSB for this two bit number.
-.It Li req-len0 , Li req-len1
-Forms a two-bit number that specifies the request length encoding:
-.Pp
-.Bl -tag -width indent -compact
-.It Li 0
-0 chunks
-.It Li 1
-1 chunk
-.It Li 3
-8 chunks
-.El
-.Pp
-Bit
-.Dq Li req-len1
-is the MSB for this two bit number.
-.It Li req-io-type
-Count requests that are input or output requests.
-.It Li req-lock-type
-Count requests that lock the bus.
-.It Li req-lock-cache
-Count requests that lock the cache.
-.It Li req-split-type
-Count requests that is a bus 8-byte chunk that is split across an
-8-byte boundary.
-.It Li req-dem-type
-Count requests that are demand (not prefetches) if set.
-Count requests that are prefetches if not set.
-.It Li req-ord-type
-Count requests that are ordered.
-.It Li mem-type0 , Li mem-type1 , Li mem-type2
-Forms a 3-bit number that specifies a memory type encoding:
-.Pp
-.Bl -tag -width indent -compact
-.It Li 0
-UC
-.It Li 1
-USWC
-.It Li 4
-WT
-.It Li 5
-WP
-.It Li 6
-WB
-.El
-.Pp
-Bit
-.Dq Li mem-type2
-is the MSB of this 3-bit number.
-.El
-.Pp
-The default qualifier has all the above bits set.
-.Pp
-This event is usually used along with the
-.Dq Li edge
-qualifier to avoid multiple counting.
-.It Li p4-bsq-cache-reference Op Li ,mask= Ns Ar qualifier
-.Pq "TS event"
-Count cache references as seen by the bus unit (2nd or 3rd level
-cache references).
-Qualifier
-.Ar qualifier
-is a
-.Ql +
-separated list of the following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li rd-2ndl-hits
-Count 2nd level cache hits in the shared state.
-.It Li rd-2ndl-hite
-Count 2nd level cache hits in the exclusive state.
-.It Li rd-2ndl-hitm
-Count 2nd level cache hits in the modified state.
-.It Li rd-3rdl-hits
-Count 3rd level cache hits in the shared state.
-.It Li rd-3rdl-hite
-Count 3rd level cache hits in the exclusive state.
-.It Li rd-3rdl-hitm
-Count 3rd level cache hits in the modified state.
-.It Li rd-2ndl-miss
-Count 2nd level cache misses.
-.It Li rd-3rdl-miss
-Count 3rd level cache misses.
-.It Li wr-2ndl-miss
-Count write-back lookups from the data access cache that miss the 2nd
-level cache.
-.El
-.Pp
-The default is to count all the above events.
-.It Li p4-execution-event Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count the retirement of tagged uops selected through the execution
-tagging mechanism.
-Qualifier
-.Ar flags
-can contain the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li nbogus0 , Li nbogus1 , Li nbogus2 , Li nbogus3
-The marked uops are not bogus.
-.It Li bogus0 , Li bogus1 , Li bogus2 , Li bogus3
-The marked uops are bogus.
-.El
-.Pp
-This event requires additional (upstream) events to be allocated to
-perform the desired uop tagging.
-The default is to set all the above flags.
-This event can be used for precise event based sampling.
-.It Li p4-front-end-event Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count the retirement of tagged uops selected through the front-end
-tagging mechanism.
-Qualifier
-.Ar flags
-can contain the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li nbogus
-The marked uops are not bogus.
-.It Li bogus
-The marked uops are bogus.
-.El
-.Pp
-This event requires additional (upstream) events to be allocated to
-perform the desired uop tagging.
-The default is to select both kinds of events.
-This event can be used for precise event based sampling.
-.It Li p4-fsb-data-activity Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count each DBSY or DRDY event selected by qualifier
-.Ar flags .
-Qualifier
-.Ar flags
-is a
-.Ql +
-separated set of the following flags:
-.Pp
-.Bl -tag -width indent -compact
-.It Li drdy-drv
-Count when this processor is driving data onto the bus.
-.It Li drdy-own
-Count when this processor is reading data from the bus.
-.It Li drdy-other
-Count when data is on the bus but not being sampled by this processor.
-.It Li dbsy-drv
-Count when this processor reserves the bus for use in the next cycle
-in order to drive data.
-.It Li dbsy-own
-Count when some agent reserves the bus for use in the next bus cycle
-to drive data that this processor will sample.
-.It Li dbsy-other
-Count when some agent reserves the bus for use in the next bus cycle
-to drive data that this processor will not sample.
-.El
-.Pp
-Flags
-.Dq Li drdy-own
-and
-.Dq Li drdy-other
-are mutually exclusive.
-Flags
-.Dq Li dbsy-own
-and
-.Dq Li dbsy-other
-are mutually exclusive.
-The default value for
-.Ar qualifier
-is
-.Dq Li drdy-drv+drdy-own+dbsy-drv+dbsy-own .
-.It Li p4-global-power-events Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count cycles during which the processor is not stopped.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li running
-Count cycles when the processor is active.
-.El
-.It Li p4-instr-retired Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count instructions retired during a clock cycle.
-Qualifier
-.Ar flags
-comprises of the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li nbogusntag
-Count non-bogus instructions that are not tagged.
-.It Li nbogustag
-Count non-bogus instructions that are tagged.
-.It Li bogusntag
-Count bogus instructions that are not tagged.
-.It Li bogustag
-Count bogus instructions that are tagged.
-.El
-.Pp
-The default qualifier counts all the above kinds of instructions.
-.It Li p4-ioq-active-entries Xo
-.Op Li ,mask= Ns Ar qualifier
-.Op Li ,busreqtype= Ns Ar req-type
-.Xc
-.Pq "TS event"
-Count the number of entries (clipped at 15) in the IOQ that are
-active.
-The event masks are specified by qualifier
-.Ar qualifier
-and
-.Ar req-type .
-.Pp
-Qualifier
-.Ar qualifier
-is a
-.Ql +
-separated set of the following flags:
-.Pp
-.Bl -tag -width indent -compact
-.It Li all-read
-Count read entries.
-.It Li all-write
-Count write entries.
-.It Li mem-uc
-Count entries accessing un-cacheable memory.
-.It Li mem-wc
-Count entries accessing write-combining memory.
-.It Li mem-wt
-Count entries accessing write-through memory.
-.It Li mem-wp
-Count entries accessing write-protected memory
-.It Li mem-wb
-Count entries accessing write-back memory.
-.It Li own
-Count store requests driven by the processor (i.e., not by other
-processors or by DMA).
-.It Li other
-Count store requests driven by other processors or by DMA.
-.It Li prefetch
-Include hardware and software prefetch requests in the count.
-.El
-.Pp
-The default value for
-.Ar qualifier
-is to enable all the above flags.
-.Pp
-The
-.Ar req-type
-qualifier is a 5-bit number can be additionally used to select a
-specific bus request type.
-The default is 0.
-.Pp
-The
-.Dq Li edge
-qualifier should not be used when counting cycles with this event.
-The exact behavior of this event depends on the processor revision.
-.It Li p4-ioq-allocation Xo
-.Op Li ,mask= Ns Ar qualifier
-.Op Li ,busreqtype= Ns Ar req-type
-.Xc
-.Pq "TS event"
-Count various types of transactions on the bus matching the flags set
-in
-.Ar qualifier
-and
-.Ar req-type .
-.Pp
-Qualifier
-.Ar qualifier
-is a
-.Ql +
-separated set of the following flags:
-.Pp
-.Bl -tag -width indent -compact
-.It Li all-read
-Count read entries.
-.It Li all-write
-Count write entries.
-.It Li mem-uc
-Count entries accessing un-cacheable memory.
-.It Li mem-wc
-Count entries accessing write-combining memory.
-.It Li mem-wt
-Count entries accessing write-through memory.
-.It Li mem-wp
-Count entries accessing write-protected memory
-.It Li mem-wb
-Count entries accessing write-back memory.
-.It Li own
-Count store requests driven by the processor (i.e., not by other
-processors or by DMA).
-.It Li other
-Count store requests driven by other processors or by DMA.
-.It Li prefetch
-Include hardware and software prefetch requests in the count.
-.El
-.Pp
-The default value for
-.Ar qualifier
-is to enable all the above flags.
-.Pp
-The
-.Ar req-type
-qualifier is a 5-bit number can be additionally used to select a
-specific bus request type.
-The default is 0.
-.Pp
-The
-.Dq Li edge
-qualifier is normally used with this event to prevent multiple
-counting.
-The exact behavior of this event depends on the processor revision.
-.It Li p4-itlb-reference Op mask= Ns Ar qualifier
-.Pq "TS event"
-Count translations using the instruction translation look-aside
-buffer.
-The
-.Ar qualifier
-argument is a list of the following strings separated by
-.Ql +
-characters.
-.Pp
-.Bl -tag -width indent -compact
-.It Li hit
-Count ITLB hits.
-.It Li miss
-Count ITLB misses.
-.It Li hit-uc
-Count un-cacheable ITLB hits.
-.El
-.Pp
-If no
-.Ar qualifier
-is specified the default is to count all the three kinds of ITLB
-translations.
-.It Li p4-load-port-replay Op Li ,mask= Ns Ar qualifier
-.Pq "TS event"
-Count replayed events at the load port.
-Qualifier
-.Ar qualifier
-can take on one value:
-.Pp
-.Bl -tag -width indent -compact
-.It Li split-ld
-Count split loads.
-.El
-.Pp
-The default value for
-.Ar qualifier
-is
-.Dq Li split-ld .
-.It Li p4-mispred-branch-retired Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count mispredicted IA-32 branch instructions.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li nbogus
-Count non-bogus retired branch instructions.
-.El
-.It Li p4-machine-clear Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count the number of pipeline clears seen by the processor.
-Qualifier
-.Ar flags
-is a list of the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li clear
-Count for a portion of the many cycles when the machine is being
-cleared for any reason.
-.It Li moclear
-Count machine clears due to memory ordering issues.
-.It Li smclear
-Count machine clears due to self-modifying code.
-.El
-.Pp
-Use qualifier
-.Dq Li edge
-to get a count of occurrences of machine clears.
-The default qualifier is
-.Dq Li clear .
-.It Li p4-memory-cancel Op Li ,mask= Ns Ar event-list
-.Pq "TS event"
-Count the canceling of various kinds of requests in the data cache
-address control unit of the CPU.
-The qualifier
-.Ar event-list
-is a list of the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li st-rb-full
-Requests cancelled because no store request buffer was available.
-.It Li 64k-conf
-Requests that conflict due to 64K aliasing.
-.El
-.Pp
-If
-.Ar event-list
-is not specified, then the default is to count both kinds of events.
-.It Li p4-memory-complete Op Li ,mask= Ns Ar event-list
-.Pq "TS event"
-Count the completion of load split, store split, un-cacheable split and
-un-cacheable load operations selected by qualifier
-.Ar event-list .
-The qualifier
-.Ar event-list
-is a
-.Ql +
-separated list of the following flags:
-.Pp
-.Bl -tag -width indent -compact
-.It Li lsc
-Count load splits completed, excluding loads from un-cacheable or
-write-combining areas.
-.It Li ssc
-Count any split stores completed.
-.El
-.Pp
-The default is to count both kinds of operations.
-.It Li p4-mob-load-replay Op Li ,mask= Ns Ar qualifier
-.Pq "TS event"
-Count load replays triggered by the memory order buffer.
-Qualifier
-.Ar qualifier
-can be a
-.Ql +
-separated list of the following flags:
-.Pp
-.Bl -tag -width indent -compact
-.It Li no-sta
-Count replays because of unknown store addresses.
-.It Li no-std
-Count replays because of unknown store data.
-.It Li partial-data
-Count replays because of partially overlapped data accesses between
-load and store operations.
-.It Li unalgn-addr
-Count replays because of mismatches in the lower 4 bits of load and
-store operations.
-.El
-.Pp
-The default qualifier is
-.Ar no-sta+no-std+partial-data+unalgn-addr .
-.It Li p4-packed-dp-uop Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count packed double-precision uops.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count all uops operating on packed double-precision operands.
-.El
-.It Li p4-packed-sp-uop Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count packed single-precision uops.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count all uops operating on packed single-precision operands.
-.El
-.It Li p4-page-walk-type Op Li ,mask= Ns Ar qualifier
-.Pq "TI event"
-Count page walks performed by the page miss handler.
-Qualifier
-.Ar qualifier
-can be a
-.Ql +
-separated list of the following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li dtmiss
-Count page walks for data TLB misses.
-.It Li itmiss
-Count page walks for instruction TLB misses.
-.El
-.Pp
-The default value for
-.Ar qualifier
-is
-.Dq Li dtmiss+itmiss .
-.It Li p4-replay-event Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count the retirement of tagged uops selected through the replay
-tagging mechanism.
-Qualifier
-.Ar flags
-contains a
-.Ql +
-separated set of the following strings:
-.Pp
-.Bl -tag -width indent -compact
-.It Li nbogus
-The marked uops are not bogus.
-.It Li bogus
-The marked uops are bogus.
-.El
-.Pp
-This event requires additional (upstream) events to be allocated to
-perform the desired uop tagging.
-The default qualifier counts both kinds of uops.
-This event can be used for precise event based sampling.
-.It Li p4-resource-stall Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count the occurrence or latency of stalls in the allocator.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li sbfull
-A stall due to the lack of store buffers.
-.El
-.It Li p4-response
-.Pq "TI event"
-Count different types of responses.
-Further documentation on this event is not available.
-.It Li p4-retired-branch-type Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count branches retired.
-Qualifier
-.Ar flags
-contains a
-.Ql +
-separated list of strings:
-.Pp
-.Bl -tag -width indent -compact
-.It Li conditional
-Count conditional jumps.
-.It Li call
-Count direct and indirect call branches.
-.It Li return
-Count return branches.
-.It Li indirect
-Count returns, indirect calls or indirect jumps.
-.El
-.Pp
-The default qualifier counts all the above branch types.
-.It Li p4-retired-mispred-branch-type Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count mispredicted branches retired.
-Qualifier
-.Ar flags
-contains a
-.Ql +
-separated list of strings:
-.Pp
-.Bl -tag -width indent -compact
-.It Li conditional
-Count conditional jumps.
-.It Li call
-Count indirect call branches.
-.It Li return
-Count return branches.
-.It Li indirect
-Count returns, indirect calls or indirect jumps.
-.El
-.Pp
-The default qualifier counts all the above branch types.
-.It Li p4-scalar-dp-uop Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count the number of scalar double-precision uops.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count the number of scalar double-precision uops.
-.El
-.It Li p4-scalar-sp-uop Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count the number of scalar single-precision uops.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count all uops operating on scalar single-precision operands.
-.El
-.It Li p4-snoop
-.Pq "TI event"
-Count snoop traffic.
-Further documentation on this event is not available.
-.It Li p4-sse-input-assist Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count the number of times an assist is required to handle problems
-with the operands for SSE and SSE2 operations.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count assists for all SSE and SSE2 uops.
-.El
-.It Li p4-store-port-replay Op Li ,mask= Ns Ar qualifier
-.Pq "TS event"
-Count events replayed at the store port.
-Qualifier
-.Ar qualifier
-can take on one value:
-.Pp
-.Bl -tag -width indent -compact
-.It Li split-st
-Count split stores.
-.El
-.Pp
-The default value for
-.Ar qualifier
-is
-.Dq Li split-st .
-.It Li p4-tc-deliver-mode Op Li ,mask= Ns Ar qualifier
-.Pq "TI event"
-Count the duration in cycles of operating modes of the trace cache and
-decode engine.
-The desired operating mode is selected by
-.Ar qualifier ,
-which is a list of the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li DD
-Both logical processors are in deliver mode.
-.It Li DB
-Logical processor 0 is in deliver mode while logical processor 1 is in
-build mode.
-.It Li DI
-Logical processor 0 is in deliver mode while logical processor 1 is
-halted, or in machine clear, or transitioning to a long microcode
-flow.
-.It Li BD
-Logical processor 0 is in build mode while logical processor 1 is in
-deliver mode.
-.It Li BB
-Both logical processors are in build mode.
-.It Li BI
-Logical processor 0 is in build mode while logical processor 1 is
-halted, or in machine clear or transitioning to a long microcode
-flow.
-.It Li ID
-Logical processor 0 is halted, or in machine clear or transitioning to
-a long microcode flow while logical processor 1 is in deliver mode.
-.It Li IB
-Logical processor 0 is halted, or in machine clear or transitioning to
-a long microcode flow while logical processor 1 is in build mode.
-.El
-.Pp
-If there is only one logical processor in the processor package then
-the qualifier for logical processor 1 is ignored.
-If no qualifier is specified, the default qualifier is
-.Dq Li DD+DB+DI+BD+BB+BI+ID+IB .
-.It Li p4-tc-ms-xfer Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count the number of times uop delivery changed from the trace cache to
-MS ROM.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li cisc
-Count TC to MS transfers.
-.El
-.It Li p4-uop-queue-writes Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count the number of valid uops written to the uop queue.
-Qualifier
-.Ar flags
-is a list of the following strings, separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li from-tc-build
-Count uops being written from the trace cache in build mode.
-.It Li from-tc-deliver
-Count uops being written from the trace cache in deliver mode.
-.It Li from-rom
-Count uops being written from microcode ROM.
-.El
-.Pp
-The default qualifier counts all the above kinds of uops.
-.It Li p4-uop-type Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-This event is used in conjunction with the front-end at-retirement
-mechanism to tag load and store uops.
-Qualifier
-.Ar flags
-comprises the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li tagloads
-Mark uops that are load operations.
-.It Li tagstores
-Mark uops that are store operations.
-.El
-.Pp
-The default qualifier counts both kinds of uops.
-.It Li p4-uops-retired Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count uops retired during a clock cycle.
-Qualifier
-.Ar flags
-comprises the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li nbogus
-Count marked uops that are not bogus.
-.It Li bogus
-Count marked uops that are bogus.
-.El
-.Pp
-The default qualifier counts both kinds of uops.
-.It Li p4-wc-buffer Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count write-combining buffer operations.
-Qualifier
-.Ar flags
-contains the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li wcb-evicts
-WC buffer evictions due to any cause.
-.It Li wcb-full-evict
-WC buffer evictions due to no WC buffer being available.
-.El
-.Pp
-The default qualifier counts both kinds of evictions.
-.It Li p4-x87-assist Op Li ,mask= Ns Ar flags
-.Pq "TS event"
-Count the retirement of x87 instructions that required special
-handling.
-Qualifier
-.Ar flags
-contains the following strings separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li fpsu
-Count instructions that saw an FP stack underflow.
-.It Li fpso
-Count instructions that saw an FP stack overflow.
-.It Li poao
-Count instructions that saw an x87 output overflow.
-.It Li poau
-Count instructions that saw an x87 output underflow.
-.It Li prea
-Count instructions that needed an x87 input assist.
-.El
-.Pp
-The default qualifier counts all the above types of instruction
-retirements.
-.It Li p4-x87-fp-uop Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count x87 floating-point uops.
-Qualifier
-.Ar flags
-can take the following value (which is also the default):
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count all x87 floating-point uops.
-.El
-.Pp
-If an instruction contains more than one x87 floating-point uops, then
-all x87 floating-point uops will be counted.
-This event does not count x87 floating-point data movement operations.
-.It Li p4-x87-simd-moves-uop Op Li ,mask= Ns Ar flags
-.Pq "TI event"
-Count each x87 FPU, MMX, SSE, or SSE2 uops that load data or store
-data or perform register-to-register moves.
-This event does not count integer move uops.
-Qualifier
-.Ar flags
-may contain the following keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li allp0
-Count all x87 and SIMD store and move uops.
-.It Li allp2
-Count all x87 and SIMD load uops.
-.El
-.Pp
-The default is to count all uops.
-.Pq Errata
-This event may be affected by processor errata N43.
-.El
-.Ss "Cascading P4 PMCs"
-PMC cascading support is currently poorly implemented.
-While individual event counters may be allocated with a
-.Dq Li cascade
-qualifier, the current API does not offer the ability
-to name and allocate all the resources needed for a
-cascaded event counter pair in a single operation.
-.Ss "Precise Event Based Sampling"
-Support for precise event based sampling is currently
-unimplemented.
-.Ss Event Name Aliases
-The following table shows the mapping between the PMC-independent
-aliases supported by
-.Lb libpmc
-and the underlying hardware events used.
-.Bl -column "branch-mispredicts" "Description"
-.It Em Alias Ta Em Event
-.It Li branches Ta Li p4-branch-retired,mask=mmtp+mmtm
-.It Li branch-mispredicts Ta Li p4-mispred-branch-retired
-.It Li dc-misses Ta (unsupported)
-.It Li ic-misses Ta (unsupported)
-.It Li instructions Ta Li p4-instr-retired,mask=nbogusntag+nbogustag
-.It Li interrupts Ta Li (unsupported)
-.It Li unhalted-cycles Ta Li p4-global-power-events
-.El
-.Sh SEE ALSO
-.Xr pmc 3 ,
-.Xr pmc.atom 3 ,
-.Xr pmc.core 3 ,
-.Xr pmc.core2 3 ,
-.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
-.Xr pmc.k8 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
-.Xr pmc.soft 3 ,
-.Xr pmc.tsc 3 ,
-.Xr pmclog 3 ,
-.Xr hwpmc 4
-.Sh HISTORY
-The
-.Nm pmc
-library first appeared in
-.Fx 6.0 .
-.Sh AUTHORS
-The
-.Lb libpmc
-library was written by
-.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
diff --git a/lib/libpmc/pmc.p5.3 b/lib/libpmc/pmc.p5.3
deleted file mode 100644
index 91d7677057ba..000000000000
--- a/lib/libpmc/pmc.p5.3
+++ /dev/null
@@ -1,460 +0,0 @@
-.\" Copyright (c) 2003-2008 Joseph Koshy.  All rights reserved.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\"    notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\"    notice, this list of conditions and the following disclaimer in the
-.\"    documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.\" $FreeBSD$
-.\"
-.Dd October 4, 2008
-.Dt PMC 3
-.Os
-.Sh NAME
-.Nm pmc
-.Nd library for accessing hardware performance monitoring counters
-.Sh LIBRARY
-.Lb libpmc
-.Sh SYNOPSIS
-.In pmc.h
-.Sh DESCRIPTION
-Intel Pentium PMCs are present in Intel
-.Tn Pentium
-and
-.Tn "Pentium MMX"
-processors.
-These PMCs are documented in the
-.Rs
-.%B "Intel 64 and IA-32 Intel(R) Architectures Software Developer's Manual"
-.%T "Volume 3B: System Programming Guide, Part 2"
-.%N "Order Number 253669-024US"
-.%D "August 2007"
-.%Q "Intel Corporation"
-.Re
-.Ss PMC Features
-These CPUs contain two PMCs, each 40 bits wide.
-These PMCs support the following capabilities:
-.Bl -column "PMC_CAP_INTERRUPT" "Support"
-.It Em Capability Ta Em Support
-.It PMC_CAP_CASCADE Ta \&No
-.It PMC_CAP_EDGE Ta \&No
-.It PMC_CAP_INTERRUPT Ta \&No
-.It PMC_CAP_INVERT Ta \&No
-.It PMC_CAP_READ Ta Yes
-.It PMC_CAP_PRECISE Ta \&No
-.It PMC_CAP_SYSTEM Ta Yes
-.It PMC_CAP_TAGGING Ta \&No
-.It PMC_CAP_THRESHOLD Ta \&No
-.It PMC_CAP_USER Ta Yes
-.It PMC_CAP_WRITE Ta Yes
-.El
-.Ss Event Qualifiers
-Event specifiers for Intel Pentium PMCs can have the following common
-qualifiers:
-.Bl -tag -width indent
-.It Li duration
-Count duration (in clocks) of events.
-The default is to count events.
-.It Li os
-Measure events at privilege levels 0, 1 and 2.
-.It Li overflow
-Assert the external processor pin associated with a counter on counter
-overflow.
-.It Li usr
-Measure events at privilege level 3.
-.El
-.Pp
-If neither of the
-.Dq Li os
-or
-.Dq Li usr
-qualifiers are specified, the default is to enable both.
-.Pp
-Some events may only be used on specific counters and some events
-are defined only on processors supporting the MMX instruction set.
-Note that these PMCs do not have the ability to interrupt the CPU.
-.Ss Intel Pentium Event Specifiers
-The event specifiers supported by Intel Pentium PMCs are:
-.Bl -tag -width indent
-.It Li p5-any-segment-register-loaded
-.Pq Event 0FH
-The number of writes to any segment register, including the LDTR,
-GDTR, TR and IDTR.
-Far control transfers and task switches that involve privilege
-level changes will count this event twice.
-.It Li p5-bank-conflicts
-.Pq Event 0AH
-The number of actual bank conflicts.
-.It Li p5-branches
-.Pq Event 12H
-The number of taken and not taken branches including branches, jumps, calls,
-software interrupts and interrupt returns.
-.It Li p5-breakpoint-match-on-dr0-register
-.Pq Event 23H
-The number of matches on the DR0 breakpoint register.
-.It Li p5-breakpoint-match-on-dr1-register
-.Pq Event 24H
-The number of matches on the DR1 breakpoint register.
-.It Li p5-breakpoint-match-on-dr2-register
-.Pq Event 25H
-The number of matches on the DR2 breakpoint register.
-.It Li p5-breakpoint-match-on-dr3-register
-.Pq Event 26H
-The number of matches on the DR3 breakpoint register.
-.It Li p5-btb-false-entries
-.Pq Event 3AH , Tn Pentium MMX
-The number of false entries in the BTB.
-This event is only allocated on counter 0.
-.It Li p5-btb-hits
-.Pq Event 13H
-The number of branches executed that hit in the branch table buffer.
-.It Li p5-btb-miss-prediction-on-not-taken-branch
-.Pq Event 3AH , Tn Pentium MMX
-The number of times the BTB predicted a not-taken branch as taken.
-This event is only allocated on counter 1.
-.It Li p5-bus-cycle-duration
-.Pq Event 18H
-The number of cycles while a bus cycle was in progress.
-.It Li p5-bus-ownership-latency
-.Pq Event 2AH , Tn Pentium MMX
-The time from bus ownership being requested to ownership being granted.
-This event is only allocated on counter 0.
-.It Li p5-bus-ownership-transfers
-.Pq Event 2AH , Tn Pentium MMX
-The number of bus ownership transfers.
-This event is only allocated on counter 1.
-.It Li p5-bus-utilization-due-to-processor-activity
-.Pq Event 2EH , Tn Pentium MMX
-The number of clocks the bus is busy due to the processor's own
-activity.
-This event is only allocated on counter 0.
-.It Li p5-cache-line-sharing
-.Pq Event 2CH , Tn Pentium MMX
-The number of shared data lines in L1 cache.
-This event is only allocated on counter 1.
-.It Li p5-cache-m-state-line-sharing
-.Pq Event 2CH , Tn Pentium MMX
-The number of hits to an M- state line due to a memory access by
-another processor.
-This event is only allocated on counter 0.
-.It Li p5-code-cache-miss
-.Pq Event 0EH
-The number of instruction reads that miss the internal code cache.
-Both cacheable and un-cacheable misses are counted.
-.It Li p5-code-read
-.Pq Event 0CH
-The number of instruction reads to both cacheable and un-cacheable regions.
-.It Li p5-code-tlb-miss
-.Pq Event 0DH
-The number of instruction reads that miss the instruction TLB.
-Both cacheable and un-cacheable unreads are counted.
-.It Li p5-d1-starvation-and-fifo-is-empty
-.Pq Event 33H , Tn Pentium MMX
-The number of times the D1 stage cannot issue any instructions because
-the FIFO was empty.
-This event is only allocated on counter 0.
-.It Li p5-d1-starvation-and-only-one-instruction-in-fifo
-.Pq Event 33H , Tn Pentium MMX
-The number of times the D1 stage could issue only one instruction
-because the FIFO had one instruction ready.
-This event is only allocated on counter 1.
-.It Li p5-data-cache-lines-written-back
-.Pq Event 06H
-The number of data cache lines that are written back, including
-those caused by internal and external snoops.
-.It Li p5-data-cache-tlb-miss-stall-duration
-.Pq Event 30H , Tn Pentium MMX
-The number of clocks the pipeline is stalled due to a data cache
-TLB miss.
-This event is only allocated on counter 1.
-.It Li p5-data-read
-.Pq Event 00H
-The number of memory data reads, counting internal data cache hits and
-misses.
-I/O and data memory accesses due to TLB miss processing are
-not included.
-Split cycle reads are counted individually.
-.It Li p5-data-read-miss
-.Pq Event 03H
-The number of memory read accesses that miss the data cache, counting
-both cacheable and un-cacheable accesses.
-Data accesses that are part of TLB miss processing are not included.
-I/O accesses are not included.
-.It Li p5-data-read-miss-or-write-miss
-.Pq Event 29H
-The number of data reads and writes that miss the internal data cache,
-counting un-cacheable accesses.
-Data accesses due to TLB miss processing are not counted.
-.It Li p5-data-read-or-write
-.Pq Event 28H
-The number of data reads and writes including internal data cache hits
-and misses.
-Data reads due to TLB miss processing are not counted.
-.It Li p5-data-tlb-miss
-.Pq Event 02H
-The number of misses to the data cache translation look aside buffer.
-.It Li p5-data-write
-.Pq Event 01H
-The number of memory data writes, counting internal data cache hits
-and misses.
-I/O is not included and split cycle writes are counted individually.
-.It Li p5-data-write-miss
-.Pq Event 04H
-The number of memory write accesses that miss the data cache, counting
-both cacheable and un-cacheable accesses.
-I/O accesses are not counted.
-.It Li p5-emms-instructions-executed
-.Pq Event 2DH , Tn Pentium MMX
-The number of EMMS instructions executed.
-This event is only allocated on counter 0.
-.It Li p5-external-data-cache-snoop-hits
-.Pq Event 08H
-The number of external snoops to the data cache that hit a valid line,
-or the data line fill buffer, or one of the write back buffers.
-.It Li p5-external-snoops
-.Pq Event 07H
-The number of external snoop requests accepted, including snoops that
-hit in the code cache, the data cache and that hit in neither.
-.It Li p5-floating-point-stalls-duration
-.Pq Event 32H , Tn Pentium MMX
-The number of cycles the pipeline is stalled due to a floating point
-freeze.
-This event is only allocated on counter 0.
-.It Li p5-flops
-.Pq Event 22H
-The number of floating point adds, subtracts, multiples, divides and
-square roots.
-Transcendental instructions trigger this event multiple times.
-Instructions generating divide-by-zero, negative square root, special
-operand and stack exceptions are not counted.
-Integer multiply instructions that use the x87 FPU are counted.
-.It Li p5-full-write-buffer-stall-duration-while-executing-mmx-instructions
-.Pq Event 3BH , Tn Pentium MMX
-The number of clocks the pipeline has stalled due to full write
-buffers when executing MMX instructions.
-This event is only allocated on counter 0.
-.It Li p5-hardware-interrupts
-.Pq Event 27H
-The number of taken INTR and NMI interrupts.
-.It Li p5-instructions-executed
-.Pq Event 16H
-The number of instructions executed.
-Repeat prefixed instructions are counted only once.
-The HLT instruction is counted only once, irrespective of the number
-of cycles spent in the halted state.
-All hardware and software exceptions are counted as instructions, and
-fault handler invocations are also counted as instructions.
-.It Li p5-instructions-executed-v-pipe
-.Pq Event 17H
-The number of instructions that executed in the V pipe.
-.It Li p5-io-read-or-write-cycle
-.Pq Event 1DH
-The number of bus cycles directed to I/O space.
-.It Li p5-locked-bus-cycle
-.Pq Event 1CH
-The number of locked bus cycles that occur on account of the lock
-prefixes, LOCK instructions, page table updates and descriptor table
-updates.
-.It Li p5-memory-accesses-in-both-pipes
-.Pq Event 09H
-The number of data memory reads or writes that are paired in both pipes.
-.It Li p5-misaligned-data-memory-or-io-references
-.Pq Event 0BH
-The number of memory or I/O reads or writes that are not aligned on
-natural boundaries.
-2- and 4-byte accesses are counted as misaligned if they cross a 4
-byte boundary.
-.It Li p5-misaligned-data-memory-reference-on-mmx-instructions
-.Pq Event 36H , Tn Pentium MMX
-The number of misaligned data memory references when executing MMX
-instructions.
-This event is only allocated on counter 0.
-.It Li p5-mispredicted-or-unpredicted-returns
-.Pq Event 37H , Tn Pentium MMX
-The number of returns predicted incorrectly or not at all, only
-counting RET instructions.
-This event is only allocated on counter 0.
-.It Li p5-mmx-instruction-data-read-misses
-.Pq Event 31H , Tn Pentium MMX
-The number of MMX instruction data read misses.
-This event is only allocated on counter 1.
-.It Li p5-mmx-instruction-data-reads
-.Pq Event 31H , Tn Pentium MMX
-The number of MMX instruction data reads.
-This event is only allocated on counter 0.
-.It Li p5-mmx-instruction-data-write-misses
-.Pq Event 34H , Tn Pentium MMX
-The number of data write misses caused by MMX instructions.
-This event is only allocated on counter 1.
-.It Li p5-mmx-instruction-data-writes
-.Pq Event 34H , Tn Pentium MMX
-The number of data writes caused by MMX instructions.
-This event is only allocated on counter 0.
-.It Li p5-mmx-instructions-executed-u-pipe
-.Pq Event 2BH , Tn Pentium MMX
-The number of MMX instructions executed in the U pipe.
-This event is only allocated on counter 0.
-.It Li p5-mmx-instructions-executed-v-pipe
-.Pq Event 2BH , Tn Pentium MMX
-The number of MMX instructions executed in the V pipe.
-This event is only allocated on counter 1.
-.It Li p5-mmx-multiply-unit-interlock
-.Pq Event 38H , Tn Pentium MMX
-The number of clocks the pipeline is stalled because the destination
-of a prior MMX multiply is not ready.
-This event is only allocated on counter 0.
-.It Li p5-movd-movq-store-stall-due-to-previous-mmx-operation
-.Pq Event 38H , Tn Pentium MMX
-The number of clocks a MOVD/MOVQ instruction stalled in the D2 stage
-of the pipeline due to a previous MMX instruction.
-This event is only allocated on counter 1.
-.It Li p5-noncacheable-memory-reads
-.Pq Event 1EH
-The number of bus cycles for non-cacheable instruction or data reads,
-including cycles caused by TLB misses.
-.It Li p5-number-of-cycles-not-in-halt-state
-.Pq Event 30H , Tn Pentium MMX
-The number of cycles the processor is not idle due to the HLT
-instruction.
-This event is only allocated on counter 0.
-.It Li p5-pipeline-agi-stalls
-.Pq Event 1FH
-The number of address generation interlock stalls.
-An AGI that occurs in both the U and V pipelines in the same clock
-signals the event twice.
-.It Li p5-pipeline-flushes
-.Pq Event 15H
-The number of pipeline flushes that occur.
-Pipeline flushes are caused by branch mispredicts, exceptions,
-interrupts, some segment register loads, and BTB misses.
-Prefetch queue flushes due to serializing instructions are not
-counted.
-.It Li p5-pipeline-flushes-due-to-wrong-branch-predictions
-.Pq Event 35H , Tn Pentium MMX
-The number of pipeline flushes due to wrong branch predictions
-resolved in either the E- or WB- stage of the pipeline.
-This event is only allocated on counter 0.
-.It Li p5-pipeline-flushes-due-to-wrong-branch-predictions-resolved-in-wb-stage
-.Pq Event 35H , Tn Pentium MMX
-The number of pipeline flushes due to wrong branch predictions
-resolved in the stage of the pipeline.
-This event is only allocated on counter 1.
-.It Li p5-pipeline-stall-for-mmx-instruction-data-memory-reads
-.Pq Event 36H , Tn Pentium MMX
-The number of clocks during pipeline stalls caused by waiting MMX data
-memory reads.
-This event is only allocated on counter 1.
-.It Li p5-predicted-returns
-.Pq Event 37H , Tn Pentium MMX
-The number of predicted returns, whether correct or incorrect.
-This counter only counts RET instructions.
-This event is only allocated on counter 1.
-.It Li p5-returns
-.Pq Event 39H , Tn Pentium MMX
-The number of RET instructions executed.
-This event is only allocated on counter 0.
-.It Li p5-saturating-mmx-instructions-executed
-.Pq Event 2FH , Tn Pentium MMX
-The number of saturating MMX instructions executed.
-This event is only allocated on counter 0.
-.It Li p5-saturations-performed
-.Pq Event 2FH , Tn Pentium MMX
-The number of saturating MMX instructions executed when at least one
-of its results were actually saturated.
-This event is only allocated on counter 1.
-.It Li p5-stall-on-mmx-instruction-write-to-e-o-m-state-line
-.Pq Event 3BH , Tn Pentium MMX
-The number of clocks during stalls on MMX instructions writing to
-E- or M- state cache lines.
-This event is only allocated on counter 1.
-.It Li p5-stall-on-write-to-an-e-or-m-state-line
-.Pq Event 1BH
-The number of stalls on a write to an exclusive or modified data cache
-line.
-.It Li p5-taken-branch-or-btb-hit
-.Pq Event 14H
-The number of events that may cause a hit in the BTB, namely either
-taken branches or BTB hits.
-.It Li p5-taken-branches
-.Pq Event 32H , Tn Pentium MMX
-The number of taken branches.
-This event is only allocated on counter 1.
-.It Li p5-transitions-between-mmx-and-fp-instructions
-.Pq Event 2DH , Tn Pentium MMX
-The number of transitions between MMX and floating-point instructions
-and vice-versa.
-This event is only allocated on counter 1.
-.It Li p5-waiting-for-data-memory-read-stall-duration
-.Pq Event 1AH
-The number of clocks the pipeline was stalled waiting for data
-memory reads.
-Data TLB misses processing is included in this count.
-.It Li p5-write-buffer-full-stall-duration
-.Pq Event 19H
-The number of clocks while the pipeline was stalled due to write
-buffers being full.
-.It Li p5-write-hit-to-m-or-e-state-lines
-.Pq Event 05H
-The number of writes that hit exclusive or modified lines in the data
-cache.
-.It Li p5-writes-to-noncacheable-memory
-.Pq Event 2EH , Tn Pentium MMX
-The number of writes to non-cacheable memory, including write cycles
-caused by TLB misses and I/O writes.
-This event is only allocated on counter 1.
-.El
-.Ss Event Name Aliases
-The following table shows the mapping between the PMC-independent
-aliases supported by
-.Lb libpmc
-and the underlying hardware events used.
-.Bl -column "branch-mispredicts" "Description"
-.It Em Alias Ta Em Event
-.It Li branches Ta Li p5-taken-branches
-.It Li branch-mispredicts Ta Li (unsupported)
-.It Li dc-misses Ta Li p5-data-read-miss-or-write-miss
-.It Li ic-misses Ta Li p5-code-cache-miss
-.It Li instructions Ta Li p5-instructions-executed
-.It Li interrupts Ta Li p5-hardware-interrupts
-.It Li unhalted-cycles Ta Li p5-number-of-cycles-not-in-halt-state
-.El
-.Sh SEE ALSO
-.Xr pmc 3 ,
-.Xr pmc.atom 3 ,
-.Xr pmc.core 3 ,
-.Xr pmc.core2 3 ,
-.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
-.Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p6 3 ,
-.Xr pmc.soft 3 ,
-.Xr pmc.tsc 3 ,
-.Xr pmclog 3 ,
-.Xr hwpmc 4
-.Sh HISTORY
-The
-.Nm pmc
-library first appeared in
-.Fx 6.0 .
-.Sh AUTHORS
-The
-.Lb libpmc
-library was written by
-.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
diff --git a/lib/libpmc/pmc.p6.3 b/lib/libpmc/pmc.p6.3
deleted file mode 100644
index 6a8270a86793..000000000000
--- a/lib/libpmc/pmc.p6.3
+++ /dev/null
@@ -1,1026 +0,0 @@
-.\" Copyright (c) 2003-2008 Joseph Koshy.  All rights reserved.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\"    notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\"    notice, this list of conditions and the following disclaimer in the
-.\"    documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.\" $FreeBSD$
-.\"
-.Dd October 4, 2008
-.Dt PMC.P6 3
-.Os
-.Sh NAME
-.Nm pmc.p6
-.Nd measurement events for
-.Tn Intel
-Pentium Pro, P-II, P-III family CPUs
-.Sh LIBRARY
-.Lb libpmc
-.Sh SYNOPSIS
-.In pmc.h
-.Sh DESCRIPTION
-Intel P6 PMCs are present in Intel
-.Tn "Pentium Pro" ,
-.Tn "Pentium II" ,
-.Tn Celeron ,
-.Tn "Pentium III"
-and
-.Tn "Pentium M"
-processors.
-.Pp
-They are documented in
-.Rs
-.%B "IA-32 Intel(R) Architecture Software Developer's Manual"
-.%T "Volume 3: System Programming Guide"
-.%N "Order Number 245472-012"
-.%D 2003
-.%Q "Intel Corporation"
-.Re
-.Pp
-Some of these events are affected by processor errata described in
-.Rs
-.%B "Intel(R) Pentium(R) III Processor Specification Update"
-.%N "Document Number: 244453-054"
-.%D "April 2005"
-.%Q "Intel Corporation"
-.Re
-.Ss PMC Features
-These CPUs have two counters, each 40 bits wide.
-Some events may only be used on specific counters and some events are
-defined only on specific processor models.
-These PMCs support the following capabilities:
-.Bl -column "PMC_CAP_INTERRUPT" "Support"
-.It Em Capability Ta Em Support
-.It PMC_CAP_CASCADE Ta \&No
-.It PMC_CAP_EDGE Ta Yes
-.It PMC_CAP_INTERRUPT Ta Yes
-.It PMC_CAP_INVERT Ta Yes
-.It PMC_CAP_READ Ta Yes
-.It PMC_CAP_PRECISE Ta \&No
-.It PMC_CAP_SYSTEM Ta Yes
-.It PMC_CAP_TAGGING Ta \&No
-.It PMC_CAP_THRESHOLD Ta Yes
-.It PMC_CAP_USER Ta Yes
-.It PMC_CAP_WRITE Ta Yes
-.El
-.Ss Event Qualifiers
-Event specifiers for Intel P6 PMCs can have the following common
-qualifiers:
-.Bl -tag -width indent
-.It Li cmask= Ns Ar value
-Configure the PMC to increment only if the number of configured
-events measured in a cycle is greater than or equal to
-.Ar value .
-.It Li edge
-Configure the PMC to count the number of de-asserted to asserted
-transitions of the conditions expressed by the other qualifiers.
-If specified, the counter will increment only once whenever a
-condition becomes true, irrespective of the number of clocks during
-which the condition remains true.
-.It Li inv
-Invert the sense of comparison when the
-.Dq Li cmask
-qualifier is present, making the counter increment when the number of
-events per cycle is less than the value specified by the
-.Dq Li cmask
-qualifier.
-.It Li os
-Configure the PMC to count events happening at processor privilege
-level 0.
-.It Li umask= Ns Ar value
-This qualifier is used to further qualify the event selected (see
-below).
-.It Li usr
-Configure the PMC to count events occurring at privilege levels 1, 2
-or 3.
-.El
-.Pp
-If neither of the
-.Dq Li os
-or
-.Dq Li usr
-qualifiers are specified, the default is to enable both.
-.Pp
-The event specifiers supported by Intel P6 PMCs are:
-.Bl -tag -width indent
-.It Li p6-baclears
-.Pq Event E6H
-Count the number of times a static branch prediction was made by the
-branch decoder because the BTB did not have a prediction.
-.It Li p6-br-bac-missp-exec
-.Pq Event 8AH , Tn "Pentium M"
-Count the number of branch instructions executed that where
-mispredicted at the Front End (BAC).
-.It Li p6-br-bogus
-.Pq Event E4H
-Count the number of bogus branches.
-.It Li p6-br-call-exec
-.Pq Event 92H , Tn "Pentium M"
-Count the number of call instructions executed.
-.It Li p6-br-call-missp-exec
-.Pq Event 93H , Tn "Pentium M"
-Count the number of call instructions executed that were mispredicted.
-.It Li p6-br-cnd-exec
-.Pq Event 8BH , Tn "Pentium M"
-Count the number of conditional branch instructions executed.
-.It Li p6-br-cnd-missp-exec
-.Pq Event 8CH , Tn "Pentium M"
-Count the number of conditional branch instructions executed that were
-mispredicted.
-.It Li p6-br-ind-call-exec
-.Pq Event 94H , Tn "Pentium M"
-Count the number of indirect call instructions executed.
-.It Li p6-br-ind-exec
-.Pq Event 8DH , Tn "Pentium M"
-Count the number of indirect branch instructions executed.
-.It Li p6-br-ind-missp-exec
-.Pq Event 8EH , Tn "Pentium M"
-Count the number of indirect branch instructions executed that were
-mispredicted.
-.It Li p6-br-inst-decoded
-.Pq Event E0H
-Count the number of branch instructions decoded.
-.It Li p6-br-inst-exec
-.Pq Event 88H , Tn "Pentium M"
-Count the number of branch instructions executed but necessarily retired.
-.It Li p6-br-inst-retired
-.Pq Event C4H
-Count the number of branch instructions retired.
-.It Li p6-br-miss-pred-retired
-.Pq Event C5H
-Count the number of mispredicted branch instructions retired.
-.It Li p6-br-miss-pred-taken-ret
-.Pq Event C9H
-Count the number of taken mispredicted branches retired.
-.It Li p6-br-missp-exec
-.Pq Event 89H , Tn "Pentium M"
-Count the number of branch instructions executed that were
-mispredicted at execution.
-.It Li p6-br-ret-bac-missp-exec
-.Pq Event 91H , Tn "Pentium M"
-Count the number of return instructions executed that were
-mispredicted at the Front End (BAC).
-.It Li p6-br-ret-exec
-.Pq Event 8FH , Tn "Pentium M"
-Count the number of return instructions executed.
-.It Li p6-br-ret-missp-exec
-.Pq Event 90H , Tn "Pentium M"
-Count the number of return instructions executed that were
-mispredicted at execution.
-.It Li p6-br-taken-retired
-.Pq Event C9H
-Count the number of taken branches retired.
-.It Li p6-btb-misses
-.Pq Event E2H
-Count the number of branches for which the BTB did not produce a
-prediction.
-.It Li p6-bus-bnr-drv
-.Pq Event 61H
-Count the number of bus clock cycles during which this processor is
-driving the BNR# pin.
-.It Li p6-bus-data-rcv
-.Pq Event 64H
-Count the number of bus clock cycles during which this processor is
-receiving data.
-.It Li p6-bus-drdy-clocks Op Li ,umask= Ns Ar qualifier
-.Pq Event 62H
-Count the number of clocks during which DRDY# is asserted.
-An additional qualifier may be specified, and comprises one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-hit-drv
-.Pq Event 7AH
-Count the number of bus clock cycles during which this processor is
-driving the HIT# pin.
-.It Li p6-bus-hitm-drv
-.Pq Event 7BH
-Count the number of bus clock cycles during which this processor is
-driving the HITM# pin.
-.It Li p6-bus-lock-clocks Op Li ,umask= Ns Ar qualifier
-.Pq Event 63H
-Count the number of clocks during with LOCK# is asserted on the
-external system bus.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-req-outstanding
-.Pq Event 60H
-Count the number of bus requests outstanding in any given cycle.
-.It Li p6-bus-snoop-stall
-.Pq Event 7EH
-Count the number of clock cycles during which the bus is snoop stalled.
-.It Li p6-bus-tran-any Op Li ,umask= Ns Ar qualifier
-.Pq Event 70H
-Count the number of completed bus transactions of any kind.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-tran-brd Op Li ,umask= Ns Ar qualifier
-.Pq Event 65H
-Count the number of burst read transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-tran-burst Op Li ,umask= Ns Ar qualifier
-.Pq Event 6EH
-Count the number of completed burst transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-tran-def Op Li ,umask= Ns Ar qualifier
-.Pq Event 6DH
-Count the number of completed deferred transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-tran-ifetch Op Li ,umask= Ns Ar qualifier
-.Pq Event 68H
-Count the number of completed instruction fetch transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-tran-inval Op Li ,umask= Ns Ar qualifier
-.Pq Event 69H
-Count the number of completed invalidate transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-tran-mem Op Li ,umask= Ns Ar qualifier
-.Pq Event 6FH
-Count the number of completed memory transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-tran-pwr Op Li ,umask= Ns Ar qualifier
-.Pq Event 6AH
-Count the number of completed partial write transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-tran-rfo Op Li ,umask= Ns Ar qualifier
-.Pq Event 66H
-Count the number of completed read-for-ownership transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-trans-io Op Li ,umask= Ns Ar qualifier
-.Pq Event 6CH
-Count the number of completed I/O transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-trans-p Op Li ,umask= Ns Ar qualifier
-.Pq Event 6BH
-Count the number of completed partial transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-bus-trans-wb Op Li ,umask= Ns Ar qualifier
-.Pq Event 67H
-Count the number of completed write-back transactions.
-An additional qualifier may be specified and comprises one of the following
-keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li any
-Count transactions generated by any agent on the bus.
-.It Li self
-Count transactions generated by this processor.
-.El
-.Pp
-The default is to count operations generated by this processor.
-.It Li p6-cpu-clk-unhalted
-.Pq Event 79H
-Count the number of cycles during with the processor was not halted.
-.Pp
-.Pq Tn "Pentium M"
-Count the number of cycles during with the processor was not halted
-and not in a thermal trip.
-.It Li p6-cycles-div-busy
-.Pq Event 14H
-Count the number of cycles during which the divider is busy and cannot
-accept new divides.
-This event is only allocated on counter 0.
-.It Li p6-cycles-int-pending-and-masked
-.Pq Event C7H
-Count the number of processor cycles for which interrupts were
-disabled and interrupts were pending.
-.It Li p6-cycles-int-masked
-.Pq Event C6H
-Count the number of processor cycles for which interrupts were
-disabled.
-.It Li p6-data-mem-refs
-.Pq Event 43H
-Count all loads and all stores using any memory type, including
-internal retries.
-Each part of a split store is counted separately.
-.It Li p6-dcu-lines-in
-.Pq Event 45H
-Count the total lines allocated in the data cache unit.
-.It Li p6-dcu-m-lines-in
-.Pq Event 46H
-Count the number of M state lines allocated in the data cache unit.
-.It Li p6-dcu-m-lines-out
-.Pq Event 47H
-Count the number of M state lines evicted from the data cache unit.
-.It Li p6-dcu-miss-outstanding
-.Pq Event 48H
-Count the weighted number of cycles while a data cache unit miss is
-outstanding, incremented by the number of outstanding cache misses at
-any time.
-.It Li p6-div
-.Pq Event 13H
-Count the number of integer and floating-point divides including
-speculative divides.
-This event is only allocated on counter 1.
-.It Li p6-emon-esp-uops
-.Pq Event D7H , Tn "Pentium M"
-Count the total number of micro-ops.
-.It Li p6-emon-est-trans Op Li ,umask= Ns Ar qualifier
-.Pq Event 58H , Tn "Pentium M"
-Count the number of
-.Tn "Enhanced Intel SpeedStep"
-transitions.
-An additional qualifier may be specified, and can be one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count all transitions.
-.It Li freq
-Count only frequency transitions.
-.El
-.Pp
-The default is to count all transitions.
-.It Li p6-emon-fused-uops-ret Op Li ,umask= Ns Ar qualifier
-.Pq Event DAH , Tn "Pentium M"
-Count the number of retired fused micro-ops.
-An additional qualifier may be specified, and may be one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li all
-Count all fused micro-ops.
-.It Li loadop
-Count only load and op micro-ops.
-.It Li stdsta
-Count only STD/STA micro-ops.
-.El
-.Pp
-The default is to count all fused micro-ops.
-.It Li p6-emon-kni-comp-inst-ret
-.Pq Event D9H , Tn "Pentium III"
-Count the number of SSE computational instructions retired.
-An additional qualifier may be specified, and comprises one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li packed-and-scalar
-Count packed and scalar operations.
-.It Li scalar
-Count scalar operations only.
-.El
-.Pp
-The default is to count packed and scalar operations.
-.It Li p6-emon-kni-inst-retired Op Li ,umask= Ns Ar qualifier
-.Pq Event D8H , Tn "Pentium III"
-Count the number of SSE instructions retired.
-An additional qualifier may be specified, and comprises one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li packed-and-scalar
-Count packed and scalar operations.
-.It Li scalar
-Count scalar operations only.
-.El
-.Pp
-The default is to count packed and scalar operations.
-.It Li p6-emon-kni-pref-dispatched Op Li ,umask= Ns Ar qualifier
-.Pq Event 07H , Tn "Pentium III"
-Count the number of SSE prefetch or weakly ordered instructions
-dispatched (including speculative prefetches).
-An additional qualifier may be specified, and comprises one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li nta
-Count non-temporal prefetches.
-.It Li t1
-Count prefetches to L1.
-.It Li t2
-Count prefetches to L2.
-.It Li wos
-Count weakly ordered stores.
-.El
-.Pp
-The default is to count non-temporal prefetches.
-.It Li p6-emon-kni-pref-miss Op Li ,umask= Ns Ar qualifier
-.Pq Event 4BH , Tn "Pentium III"
-Count the number of prefetch or weakly ordered instructions that miss
-all caches.
-An additional qualifier may be specified, and comprises one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li nta
-Count non-temporal prefetches.
-.It Li t1
-Count prefetches to L1.
-.It Li t2
-Count prefetches to L2.
-.It Li wos
-Count weakly ordered stores.
-.El
-.Pp
-The default is to count non-temporal prefetches.
-.It Li p6-emon-pref-rqsts-dn
-.Pq Event F8H , Tn "Pentium M"
-Count the number of downward prefetches issued.
-.It Li p6-emon-pref-rqsts-up
-.Pq Event F0H , Tn "Pentium M"
-Count the number of upward prefetches issued.
-.It Li p6-emon-simd-instr-retired
-.Pq Event CEH , Tn "Pentium M"
-Count the number of retired
-.Tn MMX
-instructions.
-.It Li p6-emon-sse-sse2-comp-inst-retired Op Li ,umask= Ns Ar qualifier
-.Pq Event D9H , Tn "Pentium M"
-Count the number of computational SSE instructions retired.
-An additional qualifier may be specified and can be one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li sse-packed-single
-Count SSE packed-single instructions.
-.It Li sse-scalar-single
-Count SSE scalar-single instructions.
-.It Li sse2-packed-double
-Count SSE2 packed-double instructions.
-.It Li sse2-scalar-double
-Count SSE2 scalar-double instructions.
-.El
-.Pp
-The default is to count SSE packed-single instructions.
-.It Li p6-emon-sse-sse2-inst-retired Op Li ,umask= Ns Ar qualifier
-.Pq Event D8H , Tn "Pentium M"
-Count the number of SSE instructions retired.
-An additional qualifier can be specified, and can be one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li sse-packed-single
-Count SSE packed-single instructions.
-.It Li sse-packed-single-scalar-single
-Count SSE packed-single and scalar-single instructions.
-.It Li sse2-packed-double
-Count SSE2 packed-double instructions.
-.It Li sse2-scalar-double
-Count SSE2 scalar-double instructions.
-.El
-.Pp
-The default is to count SSE packed-single instructions.
-.It Li p6-emon-synch-uops
-.Pq Event D3H , Tn "Pentium M"
-Count the number of sync micro-ops.
-.It Li p6-emon-thermal-trip
-.Pq Event 59H , Tn "Pentium M"
-Count the duration or occurrences of thermal trips.
-Use the
-.Dq Li edge
-qualifier to count occurrences of thermal trips.
-.It Li p6-emon-unfusion
-.Pq Event DBH , Tn "Pentium M"
-Count the number of unfusion events in the reorder buffer.
-.It Li p6-flops
-.Pq Event C1H
-Count the number of computational floating point operations retired.
-This event is only allocated on counter 0.
-.It Li p6-fp-assist
-.Pq Event 11H
-Count the number of floating point exceptions handled by microcode.
-This event is only allocated on counter 1.
-.It Li p6-fp-comps-ops-exe
-.Pq Event 10H
-Count the number of computation floating point operations executed.
-This event is only allocated on counter 0.
-.It Li p6-fp-mmx-trans Op Li ,umask= Ns Ar qualifier
-.Pq Event CCH , Tn "Pentium II" , Tn "Pentium III"
-Count the number of transitions between MMX and floating-point
-instructions.
-An additional qualifier may be specified, and comprises one of the
-following keywords:
-.Pp
-.Bl -tag -width indent -compact
-.It Li mmxtofp
-Count transitions from MMX instructions to floating-point instructions.
-.It Li fptommx
-Count transitions from floating-point instructions to MMX instructions.
-.El
-.Pp
-The default is to count MMX to floating-point transitions.
-.It Li p6-hw-int-rx
-.Pq Event C8H
-Count the number of hardware interrupts received.
-.It Li p6-ifu-ifetch
-.Pq Event 80H
-Count the number of instruction fetches, both cacheable and non-cacheable.
-.It Li p6-ifu-ifetch-miss
-.Pq Event 81H
-Count the number of instruction fetch misses (i.e., those that produce
-memory accesses).
-.It Li p6-ifu-mem-stall
-.Pq Event 86H
-Count the number of cycles instruction fetch is stalled for any reason.
-.It Li p6-ild-stall
-.Pq Event 87H
-Count the number of cycles the instruction length decoder is stalled.
-.It Li p6-inst-decoded
-.Pq Event D0H
-Count the number of instructions decoded.
-.It Li p6-inst-retired
-.Pq Event C0H
-Count the number of instructions retired.
-.It Li p6-itlb-miss
-.Pq Event 85H
-Count the number of instruction TLB misses.
-.It Li p6-l2-ads
-.Pq Event 21H
-Count the number of L2 address strobes.
-.It Li p6-l2-dbus-busy
-.Pq Event 22H
-Count the number of cycles during which the L2 cache data bus was busy.
-.It Li p6-l2-dbus-busy-rd
-.Pq Event 23H
-Count the number of cycles during which the L2 cache data bus was busy
-transferring read data from L2 to the processor.
-.It Li p6-l2-ifetch Op Li ,umask= Ns Ar qualifier
-.Pq Event 28H
-Count the number of L2 instruction fetches.
-An additional qualifier may be specified and comprises a list of the following
-keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li e
-Count operations affecting E (exclusive) state lines.
-.It Li i
-Count operations affecting I (invalid) state lines.
-.It Li m
-Count operations affecting M (modified) state lines.
-.It Li s
-Count operations affecting S (shared) state lines.
-.El
-.Pp
-The default is to count operations affecting all (MESI) state lines.
-.It Li p6-l2-ld Op Li ,umask= Ns Ar qualifier
-.Pq Event 29H
-Count the number of L2 data loads.
-An additional qualifier may be specified and comprises a list of the following
-keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li both
-.Pq Tn "Pentium M"
-Count both hardware-prefetched lines and non-hardware-prefetched lines.
-.It Li e
-Count operations affecting E (exclusive) state lines.
-.It Li hw
-.Pq Tn "Pentium M"
-Count hardware-prefetched lines only.
-.It Li i
-Count operations affecting I (invalid) state lines.
-.It Li m
-Count operations affecting M (modified) state lines.
-.It Li nonhw
-.Pq Tn "Pentium M"
-Exclude hardware-prefetched lines.
-.It Li s
-Count operations affecting S (shared) state lines.
-.El
-.Pp
-The default on processors other than
-.Tn "Pentium M"
-processors is to count operations affecting all (MESI) state lines.
-The default on
-.Tn "Pentium M"
-processors is to count both hardware-prefetched and
-non-hardware-prefetch operations on all (MESI) state lines.
-.Pq Errata
-This event is affected by processor errata E53.
-.It Li p6-l2-lines-in Op Li ,umask= Ns Ar qualifier
-.Pq Event 24H
-Count the number of L2 lines allocated.
-An additional qualifier may be specified and comprises a list of the following
-keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li both
-.Pq Tn "Pentium M"
-Count both hardware-prefetched lines and non-hardware-prefetched lines.
-.It Li e
-Count operations affecting E (exclusive) state lines.
-.It Li hw
-.Pq Tn "Pentium M"
-Count hardware-prefetched lines only.
-.It Li i
-Count operations affecting I (invalid) state lines.
-.It Li m
-Count operations affecting M (modified) state lines.
-.It Li nonhw
-.Pq Tn "Pentium M"
-Exclude hardware-prefetched lines.
-.It Li s
-Count operations affecting S (shared) state lines.
-.El
-.Pp
-The default on processors other than
-.Tn "Pentium M"
-processors is to count operations affecting all (MESI) state lines.
-The default on
-.Tn "Pentium M"
-processors is to count both hardware-prefetched and
-non-hardware-prefetch operations on all (MESI) state lines.
-.Pq Errata
-This event is affected by processor errata E45.
-.It Li p6-l2-lines-out Op Li ,umask= Ns Ar qualifier
-.Pq Event 26H
-Count the number of L2 lines evicted.
-An additional qualifier may be specified and comprises a list of the following
-keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li both
-.Pq Tn "Pentium M"
-Count both hardware-prefetched lines and non-hardware-prefetched lines.
-.It Li e
-Count operations affecting E (exclusive) state lines.
-.It Li hw
-.Pq Tn "Pentium M"
-Count hardware-prefetched lines only.
-.It Li i
-Count operations affecting I (invalid) state lines.
-.It Li m
-Count operations affecting M (modified) state lines.
-.It Li nonhw
-.Pq Tn "Pentium M" only
-Exclude hardware-prefetched lines.
-.It Li s
-Count operations affecting S (shared) state lines.
-.El
-.Pp
-The default on processors other than
-.Tn "Pentium M"
-processors is to count operations affecting all (MESI) state lines.
-The default on
-.Tn "Pentium M"
-processors is to count both hardware-prefetched and
-non-hardware-prefetch operations on all (MESI) state lines.
-.Pq Errata
-This event is affected by processor errata E45.
-.It Li p6-l2-m-lines-inm
-.Pq Event 25H
-Count the number of modified lines allocated in L2 cache.
-.It Li p6-l2-m-lines-outm Op Li ,umask= Ns Ar qualifier
-.Pq Event 27H
-Count the number of L2 M-state lines evicted.
-.Pp
-.Pq Tn "Pentium M"
-On these processors an additional qualifier may be specified and
-comprises a list of the following keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li both
-Count both hardware-prefetched lines and non-hardware-prefetched lines.
-.It Li hw
-Count hardware-prefetched lines only.
-.It Li nonhw
-Exclude hardware-prefetched lines.
-.El
-.Pp
-The default is to count both hardware-prefetched and
-non-hardware-prefetch operations.
-.Pq Errata
-This event is affected by processor errata E53.
-.It Li p6-l2-rqsts Op Li ,umask= Ns Ar qualifier
-.Pq Event 2EH
-Count the total number of L2 requests.
-An additional qualifier may be specified and comprises a list of the following
-keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li e
-Count operations affecting E (exclusive) state lines.
-.It Li i
-Count operations affecting I (invalid) state lines.
-.It Li m
-Count operations affecting M (modified) state lines.
-.It Li s
-Count operations affecting S (shared) state lines.
-.El
-.Pp
-The default is to count operations affecting all (MESI) state lines.
-.It Li p6-l2-st
-.Pq Event 2AH
-Count the number of L2 data stores.
-An additional qualifier may be specified and comprises a list of the following
-keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li e
-Count operations affecting E (exclusive) state lines.
-.It Li i
-Count operations affecting I (invalid) state lines.
-.It Li m
-Count operations affecting M (modified) state lines.
-.It Li s
-Count operations affecting S (shared) state lines.
-.El
-.Pp
-The default is to count operations affecting all (MESI) state lines.
-.It Li p6-ld-blocks
-.Pq Event 03H
-Count the number of load operations delayed due to store buffer blocks.
-.It Li p6-misalign-mem-ref
-.Pq Event 05H
-Count the number of misaligned data memory references (crossing a 64
-bit boundary).
-.It Li p6-mmx-assist
-.Pq Event CDH , Tn "Pentium II" , Tn "Pentium III"
-Count the number of MMX assists executed.
-.It Li p6-mmx-instr-exec
-.Pq Event B0H
-.Pq Tn Celeron , Tn "Pentium II"
-Count the number of MMX instructions executed, except MOVQ and MOVD
-stores from register to memory.
-.It Li p6-mmx-instr-ret
-.Pq Event CEH , Tn "Pentium II"
-Count the number of MMX instructions retired.
-.It Li p6-mmx-instr-type-exec Op Li ,umask= Ns Ar qualifier
-.Pq Event B3H , Tn "Pentium II" , Tn "Pentium III"
-Count the number of MMX instructions executed.
-An additional qualifier may be specified and comprises a list of
-the following keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li pack
-Count MMX pack operation instructions.
-.It Li packed-arithmetic
-Count MMX packed arithmetic instructions.
-.It Li packed-logical
-Count MMX packed logical instructions.
-.It Li packed-multiply
-Count MMX packed multiply instructions.
-.It Li packed-shift
-Count MMX packed shift instructions.
-.It Li unpack
-Count MMX unpack operation instructions.
-.El
-.Pp
-The default is to count all operations.
-.It Li p6-mmx-sat-instr-exec
-.Pq Event B1H , Tn "Pentium II" , Tn "Pentium III"
-Count the number of MMX saturating instructions executed.
-.It Li p6-mmx-uops-exec
-.Pq Event B2H , Tn "Pentium II" , Tn "Pentium III"
-Count the number of MMX micro-ops executed.
-.It Li p6-mul
-.Pq Event 12H
-Count the number of integer and floating-point multiplies, including
-speculative multiplies.
-This event is only allocated on counter 1.
-.It Li p6-partial-rat-stalls
-.Pq Event D2H
-Count the number of cycles or events for partial stalls.
-.It Li p6-resource-stalls
-.Pq Event A2H
-Count the number of cycles there was a resource related stall of any kind.
-.It Li p6-ret-seg-renames
-.Pq Event D6H , Tn "Pentium II" , Tn "Pentium III"
-Count the number of segment register rename events retired.
-.It Li p6-sb-drains
-.Pq Event 04H
-Count the number of cycles the store buffer is draining.
-.It Li p6-seg-reg-renames Op Li ,umask= Ns Ar qualifier
-.Pq Event D5H , Tn "Pentium II" , Tn "Pentium III"
-Count the number of segment register renames.
-An additional qualifier may be specified, and comprises a list of the
-following keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li ds
-Count renames for segment register DS.
-.It Li es
-Count renames for segment register ES.
-.It Li fs
-Count renames for segment register FS.
-.It Li gs
-Count renames for segment register GS.
-.El
-.Pp
-The default is to count operations affecting all segment registers.
-.It Li p6-seg-rename-stalls
-.Pq Event D4H , Tn "Pentium II" , Tn "Pentium III"
-Count the number of segment register renaming stalls.
-An additional qualifier may be specified, and comprises a list of the
-following keywords separated by
-.Ql +
-characters:
-.Pp
-.Bl -tag -width indent -compact
-.It Li ds
-Count stalls for segment register DS.
-.It Li es
-Count stalls for segment register ES.
-.It Li fs
-Count stalls for segment register FS.
-.It Li gs
-Count stalls for segment register GS.
-.El
-.Pp
-The default is to count operations affecting all the segment registers.
-.It Li p6-segment-reg-loads
-.Pq Event 06H
-Count the number of segment register loads.
-.It Li p6-uops-retired
-.Pq Event C2H
-Count the number of micro-ops retired.
-.El
-.Ss Event Name Aliases
-The following table shows the mapping between the PMC-independent
-aliases supported by
-.Lb libpmc
-and the underlying hardware events used.
-.Bl -column "branch-mispredicts" "Description"
-.It Em Alias Ta Em Event
-.It Li branches Ta Li p6-br-inst-retired
-.It Li branch-mispredicts Ta Li p6-br-miss-pred-retired
-.It Li dc-misses Ta Li p6-dcu-lines-in
-.It Li ic-misses Ta Li p6-ifu-fetch-miss
-.It Li instructions Ta Li p6-inst-retired
-.It Li interrupts Ta Li p6-hw-int-rx
-.It Li unhalted-cycles Ta Li p6-cpu-clk-unhalted
-.El
-.Sh SEE ALSO
-.Xr pmc 3 ,
-.Xr pmc.atom 3 ,
-.Xr pmc.core 3 ,
-.Xr pmc.core2 3 ,
-.Xr pmc.iaf 3 ,
-.Xr pmc.k7 3 ,
-.Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.soft 3 ,
-.Xr pmc.tsc 3 ,
-.Xr pmclog 3 ,
-.Xr hwpmc 4
-.Sh HISTORY
-The
-.Nm pmc
-library first appeared in
-.Fx 6.0 .
-.Sh AUTHORS
-The
-.Lb libpmc
-library was written by
-.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
diff --git a/lib/libpmc/pmc.sandybridge.3 b/lib/libpmc/pmc.sandybridge.3
index 72503e516f27..97d5d21a6e80 100644
--- a/lib/libpmc/pmc.sandybridge.3
+++ b/lib/libpmc/pmc.sandybridge.3
@@ -913,9 +913,6 @@ Split locks in SQ.
 .Xr pmc.ivybridgexeon 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.sandybridgeuc 3 ,
 .Xr pmc.sandybridgexeon 3 ,
 .Xr pmc.soft 3 ,
diff --git a/lib/libpmc/pmc.sandybridgeuc.3 b/lib/libpmc/pmc.sandybridgeuc.3
index f78ff10de4fe..7628c4b0e0e0 100644
--- a/lib/libpmc/pmc.sandybridgeuc.3
+++ b/lib/libpmc/pmc.sandybridgeuc.3
@@ -204,9 +204,6 @@ Counts the number of core-outgoing entries in the coherent tracker queue.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.sandybridge 3 ,
 .Xr pmc.sandybridgexeon 3 ,
 .Xr pmc.soft 3 ,
diff --git a/lib/libpmc/pmc.sandybridgexeon.3 b/lib/libpmc/pmc.sandybridgexeon.3
index 4abd1fa8aa19..fd9c7e35fc6a 100644
--- a/lib/libpmc/pmc.sandybridgexeon.3
+++ b/lib/libpmc/pmc.sandybridgexeon.3
@@ -990,9 +990,6 @@ Split locks in SQ.
 .Xr pmc.ivybridgexeon 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.sandybridge 3 ,
 .Xr pmc.sandybridgeuc 3 ,
 .Xr pmc.soft 3 ,
diff --git a/lib/libpmc/pmc.soft.3 b/lib/libpmc/pmc.soft.3
index ec532066bead..a3cd4f01e607 100644
--- a/lib/libpmc/pmc.soft.3
+++ b/lib/libpmc/pmc.soft.3
@@ -81,9 +81,6 @@ Write page fault.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc.ucf 3 ,
 .Xr pmc.westmereuc 3 ,
diff --git a/lib/libpmc/pmc.tsc.3 b/lib/libpmc/pmc.tsc.3
index 2392eb8db7a8..21b014618bd9 100644
--- a/lib/libpmc/pmc.tsc.3
+++ b/lib/libpmc/pmc.tsc.3
@@ -65,9 +65,6 @@ maps to the TSC.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmclog 3 ,
 .Xr hwpmc 4
diff --git a/lib/libpmc/pmc.ucf.3 b/lib/libpmc/pmc.ucf.3
index bdbb20029997..8bf2aa5d09b7 100644
--- a/lib/libpmc/pmc.ucf.3
+++ b/lib/libpmc/pmc.ucf.3
@@ -91,9 +91,6 @@ offset C0H under device number 0 and Function 0.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc.westmere 3 ,
diff --git a/lib/libpmc/pmc.westmere.3 b/lib/libpmc/pmc.westmere.3
index 4f861690584e..09c9d0b42125 100644
--- a/lib/libpmc/pmc.westmere.3
+++ b/lib/libpmc/pmc.westmere.3
@@ -1376,9 +1376,6 @@ Counts number of SID integer 64 bit shift or move operations.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc.ucf 3 ,
diff --git a/lib/libpmc/pmc.westmereuc.3 b/lib/libpmc/pmc.westmereuc.3
index 5e7154efad3f..166522e032ef 100644
--- a/lib/libpmc/pmc.westmereuc.3
+++ b/lib/libpmc/pmc.westmereuc.3
@@ -1080,9 +1080,6 @@ disabled.
 .Xr pmc.iaf 3 ,
 .Xr pmc.k7 3 ,
 .Xr pmc.k8 3 ,
-.Xr pmc.p4 3 ,
-.Xr pmc.p5 3 ,
-.Xr pmc.p6 3 ,
 .Xr pmc.soft 3 ,
 .Xr pmc.tsc 3 ,
 .Xr pmc.ucf 3 ,