Whitespace cleanup:

 o Wrap sentences on to new lines
 o Cleanup trailing whitespace

Found with:	textproc/igor
MFC after:	1 week
X-MFC-With:	r232157

2 files changed, 21 insertions, 16 deletions

diff --git a/lib/libc/sys/pdfork.2 b/lib/libc/sys/pdfork.2
index 4bd7d72a89b3..0808fbc91076 100644
--- a/lib/libc/sys/pdfork.2
+++ b/lib/libc/sys/pdfork.2
@@ -101,7 +101,8 @@ queries status of a process descriptor; currently only the
 .Fa st_ctime
 and
 .Fa st_mtime
-fields are defined. If the owner read, write, and execute bits are set then the
+fields are defined.
+If the owner read, write, and execute bits are set then the
 process represented by the process descriptor is still alive.
 .Pp
 .Xr poll 2
diff --git a/lib/libpmc/pmc.mips.3 b/lib/libpmc/pmc.mips.3
index 2f9be214fe1f..134dd6361a32 100644
--- a/lib/libpmc/pmc.mips.3
+++ b/lib/libpmc/pmc.mips.3
@@ -54,16 +54,16 @@ MIPS programmable PMCs support the following events:
 .Bl -tag -width indent
 .It Li CYCLE
 .Pq Event 0, Counter 0/1
-Total number of cycles. 
+Total number of cycles.
 The performance counters are clocked by the
-top-level gated clock. 
+top-level gated clock.
 If the core is built with that clock gater
 present, none of the counters will increment while the clock is
 stopped - due to a WAIT instruction.
 .It Li INSTR_EXECUTED
 .Pq Event 1, Counter 0/1
 Total number of instructions completed.
-.It Li BRANCH_COMPLETED 
+.It Li BRANCH_COMPLETED
 .Pq Event 2, Counter 0
 Total number of branch instructions completed.
 .It Li BRANCH_MISPRED
@@ -85,9 +85,9 @@ If RPS use is disabled, JR $31 will not be predicted.
 .Pq Event 5, Counter 0
 Counts ITLB accesses that are due to fetches showing up in the
 instruction fetch stage of the pipeline and which do not use a fixed
-mapping or are not in unmapped space. 
+mapping or are not in unmapped space.
 If an address is fetched twice from the pipe (as in the case of a
-cache miss), that instruction willcount as 2 ITLB accesses. 
+cache miss), that instruction willcount as 2 ITLB accesses.
 Since each fetch gets us 2 instructions,there is one access marked per double
 word.
 .It Li ITLB_MISS
@@ -102,7 +102,8 @@ They are also ignored if there is some form of address error.
 Counts DTLB access including those in unmapped address spaces.
 .It Li DTLB_MISS
 .Pq Event 6, Counter 1
-Counts DTLB misses. Back to back misses that result in only one DTLB
+Counts DTLB misses.
+Back to back misses that result in only one DTLB
 entry getting refilled are counted as a single miss.
 .It Li JTLB_IACCESS
 .Pq Event 7, Counter 0
@@ -119,7 +120,8 @@ Data JTLB accesses.
 Counts data JTLB accesses that result in no match or a match on an invalid translation.
 .It Li IC_FETCH
 .Pq Event 9, Counter 0
-Counts every time the instruction cache is accessed. All replays,
+Counts every time the instruction cache is accessed.
+All replays,
 wasted fetches etc. are counted.
 For example, following a branch, even though the prediction is taken,
 the fall through access is counted.
@@ -179,7 +181,8 @@ when both stalls are active will only be counted once.
 replay traps (other than uTLB)
 .It Li STORE_COND_COMPLETED
 .Pq Event 19, Counter 0
-Conditional stores completed.  Counts all events, including failed stores.
+Conditional stores completed.
+Counts all events, including failed stores.
 .It Li STORE_COND_FAILED
 .Pq Event 19, Counter 1
 Conditional store instruction that did not update memory.
@@ -189,7 +192,7 @@ different and the observed operating mode could change between them,
 causing some inaccuracy in the measured ratio.
 .It Li ICACHE_REQUESTS
 .Pq Event 20, Counter 0
-Note that this only counts PREFs that are actually attempted. 
+Note that this only counts PREFs that are actually attempted.
 PREFs to uncached addresses or ones with translation errors are not counted
 .It Li ICACHE_HIT
 .Pq Event 20, Counter 1
@@ -214,7 +217,7 @@ Any type of exception taken.
 Counts cycles where the LSU is in fixup and cannot accept a new
 instruction from the ALU.
 Fixups are replays within the LSU that occur when an instruction needs
-to re-access the cache or the DTLB. 
+to re-access the cache or the DTLB.
 .It Li IFU_CYCLES_STALLED
 .Pq Event 25, Counter 0
 Counts the number of cycles where the fetch unit is not providing a
@@ -256,7 +259,7 @@ Cycles where the main pipeline is stalled because of an index conflict
 in the Fill Store Buffer.
 .It Li DMISS_CYCLES
 .Pq Event 39, Counter 0
-Data miss is outstanding, but not necessarily stalling the pipeline. 
+Data miss is outstanding, but not necessarily stalling the pipeline.
 The difference between this and D$ miss stall cycles can show the gain
 from non-blocking cache misses.
 .It Li L2_MISS_CYCLES
@@ -282,7 +285,8 @@ Counts all cycles where integer pipeline waits on CorExtend return data.
 Count all pipeline bubbles that are a result of multicycle ISPRAM
 access.
 Pipeline bubbles are defined as all cycles that IFU doesn't present an
-instruction to ALU. The four cycles after a redirect are not counted.
+instruction to ALU.
+The four cycles after a redirect are not counted.
 .It Li DSPRAM_STALL_CYCLES
 .Pq Event 43, Counter 1
 Counts stall cycles created by an instruction waiting for access to DSPRAM.
@@ -372,10 +376,10 @@ aliases supported by
 .Lb libpmc
 and the underlying hardware events used.
 .Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p"
-.It Em Alias Ta Em Event Ta 
+.It Em Alias Ta Em Event Ta
 .It Li instructions Ta Li INSTR_EXECUTED Ta
-.It Li branches Ta Li BRANCH_COMPLETED Ta 
-.It Li branch-mispredicts Ta Li BRANCH_MISPRED Ta 
+.It Li branches Ta Li BRANCH_COMPLETED Ta
+.It Li branch-mispredicts Ta Li BRANCH_MISPRED Ta
 .El
 .Sh SEE ALSO
 .Xr pmc 3 ,