pci_dw: Honor the max-link-speed propertyHEADmain

The root port reports in LNKCAP the highest link speed the core was
synthesized for, which can be more than the PHY behind it supports.  On
the RK3568 pcie2x1 the root port advertises 8GT/s while the PHY only
does 5GT/s.  The link stays at 2.5GT/s after the directed speed change.

Read max-link-speed from the device tree and write it to the Max Link
Speed field of LNKCAP and to the Target Link Speed field of LNKCTL2
before requesting the speed change.  Nothing changes when the property
is absent.

Tested on a Quartz64 Model A with a Samsung 970 EVO Plus NVMe drive: the
link now trains at 5GT/s and the sequential throughput goes from 200MB/s
to 400MB/s.

Differential Revision:	https://reviews.freebsd.org/D61014

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