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| author | Justin Hibbits <jhibbits@FreeBSD.org> | 2026-07-26 04:01:51 +0000 |
|---|---|---|
| committer | Justin Hibbits <jhibbits@FreeBSD.org> | 2026-08-21 02:26:10 +0000 |
| commit | 86a88972dc311b5d4fd112564bfe19c6d7549b5f (patch) | |
| tree | 28c27fcf06dc2694e534df3bb80d1e217d3740b7 /packages/Python/lldbsuite/test/lang/cpp/gmodules-templates/(developers-only) | |
| parent | 86715a30e2708eacedaafed629d196d945c12b1e (diff) | |
* Add interrupt coalescing for DQRR and MR, with thresholds and period
as tunable sysctls under the `hw.qman` tree.
* Do lazy/sloppy buffer management to avoid constantly checking
thresholds via QMan portal round-trips.
* Add cache stashing to prewarm caches, reducing latency.
* Fix the definition of Context_A in the init_fq MC command/result
structures, they're 64-bit fields, not 32-bit.
* Reorder the dpaa_eth_frame_info as a bit of cleanup.
* Take advantage of the fact that UMA small allocations are returned in
the DMAP, and avoid pmap_kextract().
These changes together improve throughput by ~1.5%
(925Mbps->935-940Mbps) consistently, and reduce CPU usage by a bit,
increasing idle CPU from 30%->35% minimum.
Diffstat (limited to 'packages/Python/lldbsuite/test/lang/cpp/gmodules-templates/(developers-only)')
0 files changed, 0 insertions, 0 deletions
