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author | Landon J. Fuller <landonf@FreeBSD.org> | 2017-11-22 20:27:46 +0000 |
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committer | Landon J. Fuller <landonf@FreeBSD.org> | 2017-11-22 20:27:46 +0000 |
commit | 4e96bf3a37e326dcb741f289d8adfac8884cca78 (patch) | |
tree | cfbdc4fef8416b6d33d8cbdee639c4a3a1befb0f /sbin/sconfig | |
parent | 512bd18da5a0eab33f48b56327fb7812bb05e886 (diff) | |
download | src-4e96bf3a37e326dcb741f289d8adfac8884cca78.tar.gz src-4e96bf3a37e326dcb741f289d8adfac8884cca78.zip |
bhnd(4): extend the PMU APIs to support bwn(4)
The bwn(4) driver requires a number of extensions to the bhnd(4) PMU
interface to support external configuration of PLLs, LDOs, and other
parameters that require chipset or PHY-specific workarounds.
These changes add support for:
- Writing raw voltage register values to PHY-specific LDO regulator
registers (required by LP-PHY).
- Enabling/disabling PHY-specific LDOs (required by LP-PHY)
- Writing to arbitrary PMU chipctrl registers (required for common PHY PLL
reset support).
- Requesting chipset/PLL-specific spurious signal avoidance modes.
- Querying clock frequency and latency.
Additionally, rather than updating legacy PWRCTL support to conform to the
new PMU interface:
- PWRCTL API is now provided by a bhnd_pwrctl_if.m interface.
- Since PWRCTL is only found in older SSB-based chipsets, translation from
bhnd(4) bus APIs to corresponding PWRCTL operations is now handled
entirely within the siba(4) driver.
- The PWRCTL-specific host bridge clock gating APIs in bhnd_bus_if.m have
been lifted out into a standalone bhnd_pwrctl_hostb_if.m interface.
Approved by: adrian (mentor, implicit)
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D12664
Notes
Notes:
svn path=/head/; revision=326102
Diffstat (limited to 'sbin/sconfig')
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