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authorAlexander Motin <mav@FreeBSD.org>2011-12-20 15:19:33 +0000
committerAlexander Motin <mav@FreeBSD.org>2011-12-20 15:19:33 +0000
commit8f72e930c1154d58f0ab355ba03455cc01761965 (patch)
tree7f36033911afbddcfa6de8f56f023aaa60ca8ede /share/man/man4/apic.4
parentf9a01458572f322a617ba89d4213bd99779bf34e (diff)
downloadsrc-8f72e930c1154d58f0ab355ba03455cc01761965.tar.gz
src-8f72e930c1154d58f0ab355ba03455cc01761965.zip
s/LAPIC/local APIC/ to closer follow Intel documents.
Submitted by: jhb
Notes
Notes: svn path=/head/; revision=228739
Diffstat (limited to 'share/man/man4/apic.4')
-rw-r--r--share/man/man4/apic.48
1 files changed, 4 insertions, 4 deletions
diff --git a/share/man/man4/apic.4 b/share/man/man4/apic.4
index bcd9c3fa3ffe..224e4f6cdf4a 100644
--- a/share/man/man4/apic.4
+++ b/share/man/man4/apic.4
@@ -51,20 +51,20 @@ Set this to 1 to disable APIC support, falling back to the legacy PIC.
.Sh DESCRIPTION
There are two components in the Intel APIC system, the local APIC (LAPIC)
and the I/O APIC.
-There is one LAPIC in each CPU in the system.
+There is one local APIC in each CPU in the system.
There is typically one I/O APIC for each peripheral bus in the system.
.Pp
-LAPICs manage all external interrupts for specific processor in an SMP system.
+Local APICs manage all external interrupts for a specific processor.
In addition, they are able to accept and generate inter-processor interrupts
(IPIs).
.Pp
I/O APICs contain a redirection table, which is used to route the interrupts
they receive from peripheral buses to one or more local APICs.
.Pp
-Each LAPIC includes one 32-bit programable timer.
+Each local APIC includes one 32-bit programable timer.
This driver uses them to supply kernel with one event timer named "LAPIC".
Event timer provided by the driver supports both one-shot an periodic modes.
-Because of LAPIC nature it is per-CPU.
+Because of local APIC nature it is per-CPU.
The timer frequency is not reported by the platform and so automatically
measured by the driver on the first use.
Depending on CPU model this timer may stop in C3 and deeper CPU sleep states.