cgem: add 64-bit support

Add 64-bit address support to Cadence CGEM Ethernet driver for use in
other SoCs such as the Zynq UltraScale+ and SiFive HighFive Unleashed.

Reviewed by:	philip, 0mp (manpages)
Differential Revision: https://reviews.freebsd.org/D24304

3 files changed, 17 insertions, 8 deletions

diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile
index c72caf0199c9..b8e63315cb95 100644
--- a/share/man/man4/Makefile
+++ b/share/man/man4/Makefile
@@ -106,6 +106,7 @@ MAN=	aac.4 \
 	cdceem.4 \
 	cfi.4 \
 	cfumass.4 \
+	${_cgem.4} \
 	ch.4 \
 	chromebook_platform.4 \
 	${_chvgpio.4} \
@@ -903,6 +904,12 @@ _virtio_scsi.4=	virtio_scsi.4
 _vtnet.4=	vtnet.4
 .endif
 
+.if ${MACHINE_CPUARCH} == "arm" || ${MACHINE_CPUARCH} == "aarch64" || \
+	 ${MACHINE_CPUARCH} == "riscv"
+_cgem.4=	cgem.4
+MLINKS+=cgem.4 if_cgem.4
+.endif
+
 .if empty(MAN_ARCH)
 __arches=	${MACHINE} ${MACHINE_ARCH} ${MACHINE_CPUARCH}
 .elif ${MAN_ARCH} == "all"
diff --git a/share/man/man4/man4.arm/cgem.4 b/share/man/man4/cgem.4
index 6de1d7961788..f9f525dc4554 100644
--- a/share/man/man4/man4.arm/cgem.4
+++ b/share/man/man4/cgem.4
@@ -24,7 +24,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd August 26, 2014
+.Dd January 10, 2021
 .Dt CGEM 4
 .Os
 .Sh NAME
@@ -44,7 +44,8 @@ The
 .Nm
 driver provides support for the Cadence GEM (Gigabit Ethernet MAC).
 The Cadence GEM is used in some SoC (System on a Chip) devices such as
-the Xilinx Zynq-7000 and the Atmel SAMA5D3.
+the Xilinx Zynq-7000, the Xilinx Zynq UltraScale+, and the SiFive
+HiFive Unleashed.
 .Pp
 The
 .Nm
@@ -284,7 +285,7 @@ There are
 variables that count
 packets discarded by the hardware (see below).
 .Pp
-The GEM used in the Zynq-7000 has a bug such that  the receiver can
+The GEM used in the Zynq-7000 has a bug such that the receiver can
 potentially freeze up under a high load.
 The issue is described in sec. 16.7
 "Known Issues" of the Zynq-7000 SoC Technical Reference Manual (Xilinx
@@ -292,7 +293,10 @@ UG585 v1.7).
 The
 .Nm
 driver implements the work-around suggested in the manual.
-If the bug does not exist in other versions of this device, the
-work-around can be disabled by setting the dev.cgem.%d.rxhangwar
+It is believed that the bug does not exist in the Zynq UltraScale+ and
+SiFive SoCs so the work-around is disabled in those instances and enabled
+in all others.
+The work-around can be disabled by setting the
+.Va dev.cgem.%d.rxhangwar
 .Xr sysctl 8
 variable to 0.
diff --git a/share/man/man4/man4.arm/Makefile b/share/man/man4/man4.arm/Makefile
index 21d53f43a7c8..0b3eec427934 100644
--- a/share/man/man4/man4.arm/Makefile
+++ b/share/man/man4/man4.arm/Makefile
@@ -8,7 +8,6 @@ MAN=	\
 	aw_spi.4 \
 	aw_syscon.4 \
 	bcm283x_pwm.4 \
-	cgem.4 \
 	devcfg.4 \
 	imx6_ahci.4 \
 	imx6_snvs.4 \
@@ -16,8 +15,7 @@ MAN=	\
 	mge.4 \
 	ti_adc.4
 
-MLINKS= cgem.4 if_cgem.4
-MLINKS+= imx_wdog.4 imxwdt.4
+MLINKS= imx_wdog.4 imxwdt.4
 MLINKS+= mge.4 if_mge.4
 
 MANSUBDIR=/arm