arm64: avoid full icache flushes on PIPT icachesHEADmain

On many arm64 processors, the kernel plays a part in maintaining
instruction cache (icache) coherence as the contents of the underlying
physical pages change.  Previously, the only mechanism for maintaining
icache coherence implemented by the machine-dependent layer was a full
icache flush.  However, on machines with physically indexed and
physically tagged (PIPT) icaches, where aliasing cannot occur, we can
instead selectively invalidate just the affected cache lines.

Reviewed by:	andrew
Tested by:	markj
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D60271

0 files changed, 0 insertions, 0 deletions