e1000: Report corrected I350 ECC errorsHEADmain

I350 does not interrupt for corrected internal ECC errors.  Instead,
the PCIe, DMA, packet buffer, loopback, and management memories expose
sticky status bits in their region-specific status registers.

Sample those bits with the regular hardware statistics update, preserve
the RX and TX packet buffer ECC enable state while clearing RW1C
indications, and expose counters grouped by memory region.  Each counter
records observed indication bits rather than exact error counts because
repeated corrections between samples collapse into one sticky bit.

On an I350 (8086:1521 revision 1), the ECC enables remained set.  All
corrected-error status registers remained clear across boot, interface
down/up, three FER recovery resets, and bidirectional line-rate traffic.
The device has no documented corrected error injector.  Therefore, the
per-region paths were validated against the register definitions rather
than an injected SRAM error.

MFC after:	2 weeks
Sponsored by:	BBOX.io

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