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| author | John Baldwin <jhb@FreeBSD.org> | 2009-03-24 18:10:22 +0000 |
|---|---|---|
| committer | John Baldwin <jhb@FreeBSD.org> | 2009-03-24 18:10:22 +0000 |
| commit | 6cad8eb41df7ba8e6191d5f689bf1783dfd94411 (patch) | |
| tree | 83e2b89a622fb80bb1a4d9d15a9e53de4354c2c0 /sys/amd64/pci | |
| parent | 903823870202876be9d07b63d894b9ae84077c10 (diff) | |
| download | src-6cad8eb41df7ba8e6191d5f689bf1783dfd94411.tar.gz src-6cad8eb41df7ba8e6191d5f689bf1783dfd94411.zip | |
Fall back to using configuration type 1 accesses for PCI config requests if
the requested PCI bus falls outside of the bus range given in the ACPI
MCFG table. Several BIOSes seem to not include all of the PCI busses in
systems in their MCFG tables. It maybe that the BIOS is simply buggy and
does support all the busses, but it is more conservative to just fall back
to the old method unless it is certain that memory accesses will work.
Notes
Notes:
svn path=/head/; revision=190386
Diffstat (limited to 'sys/amd64/pci')
| -rw-r--r-- | sys/amd64/pci/pci_cfgreg.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c index 8f757a74d7d0..61a2db55f1d8 100644 --- a/sys/amd64/pci/pci_cfgreg.c +++ b/sys/amd64/pci/pci_cfgreg.c @@ -119,6 +119,7 @@ pci_docfgregread(int bus, int slot, int func, int reg, int bytes) { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) return (pciereg_cfgread(bus, slot, func, reg, bytes)); else @@ -158,6 +159,7 @@ pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) { if (cfgmech == CFGMECH_PCIE && + (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) pciereg_cfgwrite(bus, slot, func, reg, data, bytes); else |