Commit MD parts of a loosely functional AMD64 port. This is based on

a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to
attempt to get a stable base to start from.  There is a lot missing still.
Worth noting:
- The kernel runs at 1GB in order to cheat with the pmap code.  pmap uses
  a variation of the PAE code in order to avoid having to worry about 4
  levels of page tables yet.
- It boots in 64 bit "long mode" with a tiny trampoline embedded in the
  i386 loader.  This simplifies locore.s greatly.
- There are still quite a few fragments of i386-specific code that have
  not been translated yet, and some that I cheated and wrote dumb C
  versions of (bcopy etc).
- It has both int 0x80 for syscalls (but using registers for argument
  passing, as is native on the amd64 ABI), and the 'syscall' instruction
  for syscalls.  int 0x80 preserves all registers, 'syscall' does not.
- I have tried to minimize looking at the NetBSD code, except in a couple
  of places (eg: to find which register they use to replace the trashed
  %rcx register in the syscall instruction).  As a result, there is not a
  lot of similarity.  I did look at NetBSD a few times while debugging to
  get some ideas about what I might have done wrong in my first attempt.

2 files changed, 18 insertions, 558 deletions

diff --git a/sys/amd64/pci/pci_bus.c b/sys/amd64/pci/pci_bus.c
index 9e288686e883..4465e7ad952f 100644
--- a/sys/amd64/pci/pci_bus.c
+++ b/sys/amd64/pci/pci_bus.c
@@ -44,14 +44,10 @@
 #include <machine/pci_cfgreg.h>
 #include <machine/segments.h>
 #include <machine/cputypes.h>
-#include <machine/pc/bios.h>
 #include <machine/md_var.h>
 
 #include "pcib_if.h"
 
-static int	pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
-    int pin);
-
 static int
 nexus_pcib_maxslots(device_t dev)
 {
@@ -81,7 +77,9 @@ nexus_pcib_write_config(device_t dev, int bus, int slot, int func,
 static int
 nexus_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
 {
-	return (pcibios_pcib_route_interrupt(pcib, dev, pin));
+
+	/* No routing possible */
+	return (PCI_INVALID_IRQ);
 }
 
 static const char *
@@ -605,67 +603,3 @@ static driver_t pcibus_pnp_driver = {
 static devclass_t pcibus_pnp_devclass;
 
 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
-
-
-/*
- * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
- * that appear in the PCIBIOS Interrupt Routing Table to use the routing
- * table for interrupt routing when possible.
- */
-static int	pcibios_pcib_probe(device_t bus);
-
-static device_method_t pcibios_pcib_pci_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		pcibios_pcib_probe),
-	DEVMETHOD(device_attach,	pcib_attach),
-	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	DEVMETHOD(device_suspend,	bus_generic_suspend),
-	DEVMETHOD(device_resume,	bus_generic_resume),
-
-	/* Bus interface */
-	DEVMETHOD(bus_print_child,	bus_generic_print_child),
-	DEVMETHOD(bus_read_ivar,	pcib_read_ivar),
-	DEVMETHOD(bus_write_ivar,	pcib_write_ivar),
-	DEVMETHOD(bus_alloc_resource,	pcib_alloc_resource),
-	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
-	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
-	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
-	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
-
-	/* pcib interface */
-	DEVMETHOD(pcib_maxslots,	pcib_maxslots),
-	DEVMETHOD(pcib_read_config,	pcib_read_config),
-	DEVMETHOD(pcib_write_config,	pcib_write_config),
-	DEVMETHOD(pcib_route_interrupt,	pcibios_pcib_route_interrupt),
-
-	{0, 0}
-};
-
-static driver_t pcibios_pcib_driver = {
-	"pcib",
-	pcibios_pcib_pci_methods,
-	sizeof(struct pcib_softc),
-};
-
-DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
-
-static int
-pcibios_pcib_probe(device_t dev)
-{
-
-	if ((pci_get_class(dev) != PCIC_BRIDGE) ||
-	    (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
-		return (ENXIO);
-	if (pci_probe_route_table(pcib_get_bus(dev)) == 0)
-		return (ENXIO);
-	device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
-	return (-2000);
-}
-
-static int
-pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
-{
-	return(pci_cfgintr(pci_get_bus(dev), pci_get_slot(dev), pin,
-		   pci_get_irq(dev)));
-}
diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c
index 4a174bd1fd73..2352c3004107 100644
--- a/sys/amd64/pci/pci_cfgreg.c
+++ b/sys/amd64/pci/pci_cfgreg.c
@@ -44,76 +44,18 @@
 #include <dev/pci/pcireg.h>
 #include <isa/isavar.h>
 #include <machine/pci_cfgreg.h>
-#include <machine/segments.h>
-#include <machine/pc/bios.h>
-
-#ifdef APIC_IO
-#include <machine/smp.h>
-#endif /* APIC_IO */
 
 #include "pcib_if.h"
 
-#define PRVERB(a) do {							\
-	if (bootverbose)						\
-		printf a ;						\
-} while(0)
-
 static int cfgmech;
 static int devmax;
 
-static int	pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq);
-static int	pci_cfgintr_unique(struct PIR_entry *pe, int pin);
-static int	pci_cfgintr_linked(struct PIR_entry *pe, int pin);
-static int	pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin);
-static int	pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
-
-static void	pci_print_irqmask(u_int16_t irqs);
-static void	pci_print_route_table(struct PIR_table *prt, int size);
 static int	pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
 static void	pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
 static int	pcireg_cfgopen(void);
 
-static struct PIR_table *pci_route_table;
-static int pci_route_count;
-
 static struct mtx pcicfg_mtx;
 
-/*
- * Some BIOS writers seem to want to ignore the spec and put
- * 0 in the intline rather than 255 to indicate none.  Some use
- * numbers in the range 128-254 to indicate something strange and
- * apparently undocumented anywhere.  Assume these are completely bogus
- * and map them to 255, which means "none".
- */
-static __inline__ int 
-pci_i386_map_intline(int line)
-{
-	if (line == 0 || line >= 128)
-		return (PCI_INVALID_IRQ);
-	return (line);
-}
-
-static u_int16_t
-pcibios_get_version(void)
-{
-	struct bios_regs args;
-
-	if (PCIbios.ventry == 0) {
-		PRVERB(("pcibios: No call entry point\n"));
-		return (0);
-	}
-	args.eax = PCIBIOS_BIOS_PRESENT;
-	if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
-		PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
-		return (0);
-	}
-	if (args.edx != 0x20494350) {
-		PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
-		return (0);
-	}
-	return (args.ebx & 0xffff);
-}
-
 /* 
  * Initialise access to PCI configuration space 
  */
@@ -121,59 +63,14 @@ int
 pci_cfgregopen(void)
 {
 	static int		opened = 0;
-	u_long			sigaddr;
-	static struct PIR_table	*pt;
-	u_int16_t		v;
-	u_int8_t		ck, *cv;
-	int			i;
 
 	if (opened)
-		return(1);
-
+		return (1);
 	if (pcireg_cfgopen() == 0)
-		return(0);
-
-	v = pcibios_get_version();
-	if (v > 0)
-		printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
-		    v & 0xff);
-
-	/*
-	 * Look for the interrupt routing table.
-	 *
-	 * We use PCI BIOS's PIR table if it's available $PIR is the
-	 * standard way to do this.  Sadly, some machines are not
-	 * standards conforming and have _PIR instead.  We shrug and cope
-	 * by looking for both.
-	 */
-	if (pcibios_get_version() >= 0x0210 && pt == NULL) {
-		sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0);
-		if (sigaddr == 0)
-			sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0);
-		if (sigaddr != 0) {
-			pt = (struct PIR_table *)(uintptr_t)
-			    BIOS_PADDRTOVADDR(sigaddr);
-			for (cv = (u_int8_t *)pt, ck = 0, i = 0;
-			     i < (pt->pt_header.ph_length); i++) {
-				ck += cv[i];
-			}
-			if (ck == 0 && pt->pt_header.ph_length >
-			    sizeof(struct PIR_header)) {
-				pci_route_table = pt;
-				pci_route_count = (pt->pt_header.ph_length -
-				    sizeof(struct PIR_header)) / 
-				    sizeof(struct PIR_entry);
-				printf("Using $PIR table, %d entries at %p\n",
-				    pci_route_count, pci_route_table);
-				if (bootverbose)
-					pci_print_route_table(pci_route_table,
-					    pci_route_count);
-			}
-		}
-	}
+		return (0);
 	mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
 	opened = 1;
-	return(1);
+	return (1);
 }
 
 /* 
@@ -183,60 +80,22 @@ u_int32_t
 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
 {
 	uint32_t line;
-#ifdef APIC_IO
-	uint32_t pin;
-
-	/*
-	 * If we are using the APIC, the contents of the intline
-	 * register will probably be wrong (since they are set up for
-	 * use with the PIC.  Rather than rewrite these registers
-	 * (maybe that would be smarter) we trap attempts to read them
-	 * and translate to our private vector numbers.
-	 */
-	if ((reg == PCIR_INTLINE) && (bytes == 1)) {
-
-		pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1);
-		line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
 
-		if (pin != 0) {
-			int airq;
-
-			airq = pci_apic_irq(bus, slot, pin);
-			if (airq >= 0) {
-				/* PCI specific entry found in MP table */
-				if (airq != line)
-					undirect_pci_irq(line);
-				return(airq);
-			} else {
-				/* 
-				 * PCI interrupts might be redirected
-				 * to the ISA bus according to some MP
-				 * tables. Use the same methods as
-				 * used by the ISA devices devices to
-				 * find the proper IOAPIC int pin.
-				 */
-				airq = isa_apic_irq(line);
-				if ((airq >= 0) && (airq != line)) {
-					/* XXX: undirect_pci_irq() ? */
-					undirect_isa_irq(line);
-					return(airq);
-				}
-			}
-		}
-		return(line);
-	}
-#else
 	/*
 	 * Some BIOS writers seem to want to ignore the spec and put
-	 * 0 in the intline rather than 255 to indicate none.  The rest of
-	 * the code uses 255 as an invalid IRQ.
+	 * 0 in the intline rather than 255 to indicate none.  Some use
+	 * numbers in the range 128-254 to indicate something strange and
+	 * apparently undocumented anywhere.  Assume these are completely bogus
+	 * and map them to 255, which the rest of the PCI code recognizes as
+	 * as an invalid IRQ.
 	 */
 	if (reg == PCIR_INTLINE && bytes == 1) {
 		line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
-		return pci_i386_map_intline(line);
+		if (line == 0 || line >= 128)
+			line = PCI_INVALID_IRQ;
+		return (line);
 	}
-#endif /* APIC_IO */
-	return(pcireg_cfgread(bus, slot, func, reg, bytes));
+	return (pcireg_cfgread(bus, slot, func, reg, bytes));
 }
 
 /* 
@@ -255,342 +114,10 @@ pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
 int
 pci_cfgintr(int bus, int device, int pin, int oldirq)
 {
-	struct PIR_entry	*pe;
-	int			i, irq;
-	struct bios_regs	args;
-	u_int16_t		v;
- 	int already = 0;
- 	int errok = 0;
-    
-	v = pcibios_get_version();
-	if (v < 0x0210) {
-		PRVERB((
-		"pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n",
-		    (v & 0xff00) >> 8, v & 0xff));
-		return (PCI_INVALID_IRQ);
-	}
-	if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) ||
-	    (pin < 1) || (pin > 4))
-		return(PCI_INVALID_IRQ);
-
-	/*
-	 * Scan the entry table for a contender
-	 */
-	for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count; 
-	     i++, pe++) {
-		if ((bus != pe->pe_bus) || (device != pe->pe_device))
-			continue;
-		/*
-		 * A link of 0 means that this intpin is not connected to
-		 * any other device's interrupt pins and is not connected to
-		 * any of the Interrupt Router's interrupt pins, so we can't
-		 * route it.
-		 */
-		if (pe->pe_intpin[pin - 1].link == 0)
-			continue;
-
-		if (pci_cfgintr_valid(pe, pin, oldirq)) {
-			printf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus,
-			    device, 'A' + pin - 1, oldirq);
-			return (oldirq);
-		}
-
-		/*
-		 * We try to find a linked interrupt, then we look to see
-		 * if the interrupt is uniquely routed, then we look for
-		 * a virgin interrupt.  The virgin interrupt should return
-		 * an interrupt we can route, but if that fails, maybe we
-		 * should try harder to route a different interrupt.
-		 * However, experience has shown that that's rarely the
-		 * failure mode we see.
-		 */
-		irq = pci_cfgintr_linked(pe, pin);
-		if (irq != PCI_INVALID_IRQ)
-			already = 1;
-		if (irq == PCI_INVALID_IRQ) {
-			irq = pci_cfgintr_unique(pe, pin);
-			if (irq != PCI_INVALID_IRQ)
-				errok = 1;
-		}
-		if (irq == PCI_INVALID_IRQ)
-			irq = pci_cfgintr_virgin(pe, pin);
-		if (irq == PCI_INVALID_IRQ)
-			break;
-
-		/*
-		 * Ask the BIOS to route the interrupt.  If we picked an
-		 * interrupt that failed, we should really try other
-		 * choices that the BIOS offers us.
-		 *
-		 * For uniquely routed interrupts, we need to try
-		 * to route them on some machines.  Yet other machines
-		 * fail to route, so we have to pretend that in that
-		 * case it worked.  Isn't pc hardware fun?
-		 *
-		 * NOTE: if we want to whack hardware to do this, then
-		 * I think the right way to do that would be to have
-		 * bridge drivers that do this.  I'm not sure that the
-		 * $PIR table would be valid for those interrupt
-		 * routers.
-		 */
-		args.eax = PCIBIOS_ROUTE_INTERRUPT;
-		args.ebx = (bus << 8) | (device << 3);
-		/* pin value is 0xa - 0xd */
-		args.ecx = (irq << 8) | (0xa + pin - 1);
-		if (!already &&
-		    bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)) &&
-		    !errok) {
-			PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n"));
-			return(PCI_INVALID_IRQ);
-		}
-		printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus, 
-		    device, 'A' + pin - 1, irq);
-		return(irq);
-	}
-
-	PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus, 
-	    device, 'A' + pin - 1));
-	return(PCI_INVALID_IRQ);
-}
-
-/*
- * Check to see if an existing IRQ setting is valid.
- */
-static int
-pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq)
-{
-	uint32_t irqmask;
 
-	if (!PCI_INTERRUPT_VALID(irq))
-		return (0);
-	irqmask = pe->pe_intpin[pin - 1].irqs;
-	if (irqmask & (1 << irq)) {
-		PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq));
-		return (1);
-	}
-	return (0);
-}
-
-/*
- * Look to see if the routing table claims this pin is uniquely routed.
- */
-static int
-pci_cfgintr_unique(struct PIR_entry *pe, int pin)
-{
-	int		irq;
-	uint32_t	irqmask;
-    
-	irqmask = pe->pe_intpin[pin - 1].irqs;
-	if (irqmask != 0 && powerof2(irqmask)) {
-		irq = ffs(irqmask) - 1;
-		PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq));
-		return(irq);
-	}
-	return(PCI_INVALID_IRQ);
-}
-
-/*
- * Look for another device which shares the same link byte and
- * already has a unique IRQ, or which has had one routed already.
- */
-static int
-pci_cfgintr_linked(struct PIR_entry *pe, int pin)
-{
-	struct PIR_entry	*oe;
-	struct PIR_intpin	*pi;
-	int			i, j, irq;
-
-	/*
-	 * Scan table slots.
-	 */
-	for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count;
-	     i++, oe++) {
-		/* scan interrupt pins */
-		for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) {
-
-			/* don't look at the entry we're trying to match */
-			if ((pe == oe) && (i == (pin - 1)))
-				continue;
-			/* compare link bytes */
-			if (pi->link != pe->pe_intpin[pin - 1].link)
-				continue;
-			/* link destination mapped to a unique interrupt? */
-			if (pi->irqs != 0 && powerof2(pi->irqs)) {
-				irq = ffs(pi->irqs) - 1;
-				PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n",
-				    pi->link, irq));
-				return(irq);
-			} 
-
-			/* 
-			 * look for the real PCI device that matches this 
-			 * table entry 
-			 */
-			irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device,
-			    j, pin);
-			if (irq != PCI_INVALID_IRQ)
-				return(irq);
-		}
-	}
-	return(PCI_INVALID_IRQ);
-}
-
-/*
- * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and
- * see if it has already been assigned an interrupt.
- */
-static int
-pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin)
-{
-	devclass_t		pci_devclass;
-	device_t		*pci_devices;
-	int			pci_count;
-	device_t		*pci_children;
-	int			pci_childcount;
-	device_t		*busp, *childp;
-	int			i, j, irq;
-
-	/*
-	 * Find all the PCI busses.
-	 */
-	pci_count = 0;
-	if ((pci_devclass = devclass_find("pci")) != NULL)
-		devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
-
-	/*
-	 * Scan all the PCI busses/devices looking for this one.
-	 */
-	irq = PCI_INVALID_IRQ;
-	for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ);
-	     i++, busp++) {
-		pci_childcount = 0;
-		device_get_children(*busp, &pci_children, &pci_childcount);
-		
-		for (j = 0, childp = pci_children; j < pci_childcount; j++, 
-		    childp++) {
-			if ((pci_get_bus(*childp) == bus) &&
-			    (pci_get_slot(*childp) == device) &&
-			    (pci_get_intpin(*childp) == matchpin)) {
-				irq = pci_i386_map_intline(pci_get_irq(*childp));
-				if (irq != PCI_INVALID_IRQ)
-					PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n",
-					    pe->pe_intpin[pin - 1].link, irq,
-					    pci_get_bus(*childp),
-					    pci_get_slot(*childp), 
-					    pci_get_function(*childp)));
-				break;
-			}
-		}
-		if (pci_children != NULL)
-			free(pci_children, M_TEMP);
-	}
-	if (pci_devices != NULL)
-		free(pci_devices, M_TEMP);
-	return(irq);
-}
-
-/*
- * Pick a suitable IRQ from those listed as routable to this device.
- */
-static int
-pci_cfgintr_virgin(struct PIR_entry *pe, int pin)
-{
-	int		irq, ibit;
-    
-	/*
-	 * first scan the set of PCI-only interrupts and see if any of these 
-	 * are routable
-	 */ 
-	for (irq = 0; irq < 16; irq++) {
-		ibit = (1 << irq);
-
-		/* can we use this interrupt? */
-		if ((pci_route_table->pt_header.ph_pci_irqs & ibit) &&
-		    (pe->pe_intpin[pin - 1].irqs & ibit)) {
-			PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq));
-			return(irq);
-		}
-	}
-    
-	/* life is tough, so just pick an interrupt */
-	for (irq = 0; irq < 16; irq++) {
-		ibit = (1 << irq);
-		if (pe->pe_intpin[pin - 1].irqs & ibit) {
-			PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq));
-			return(irq);
-		}
-	}
-	return(PCI_INVALID_IRQ);
-}
-
-static void
-pci_print_irqmask(u_int16_t irqs)
-{
-	int i, first;
-
-	if (irqs == 0) {
-		printf("none");
-		return;
-	}
-	first = 1;
-	for (i = 0; i < 16; i++, irqs >>= 1)
-		if (irqs & 1) {
-			if (!first)
-				printf(" ");
-			else
-				first = 0;
-			printf("%d", i);
-		}
-}
-
-/*
- * Dump the contents of a PCI BIOS Interrupt Routing Table to the console.
- */
-static void
-pci_print_route_table(struct PIR_table *prt, int size)
-{
-	struct PIR_entry *entry;
-	struct PIR_intpin *intpin;
-	int i, pin;
-
-	printf("PCI-Only Interrupts: ");
-	pci_print_irqmask(prt->pt_header.ph_pci_irqs);
-	printf("\nLocation  Bus Device Pin  Link  IRQs\n");
-	entry = &prt->pt_entry[0];
-	for (i = 0; i < size; i++, entry++) {
-		intpin = &entry->pe_intpin[0];
-		for (pin = 0; pin < 4; pin++, intpin++)
-			if (intpin->link != 0) {
-				if (entry->pe_slot == 0)
-					printf("embedded ");
-				else
-					printf("slot %-3d ", entry->pe_slot);
-				printf(" %3d  %3d    %c   0x%02x  ",
-				    entry->pe_bus, entry->pe_device,
-				    'A' + pin, intpin->link);
-				pci_print_irqmask(intpin->irqs);
-				printf("\n");
-			}
-	}
-}
-
-/*
- * See if any interrupts for a given PCI bus are routed in the PIR.  Don't
- * even bother looking if the BIOS doesn't support routing anyways.
- */
-int
-pci_probe_route_table(int bus)
-{
-	int i;
-	u_int16_t v;
-
-	v = pcibios_get_version();
-	if (v < 0x0210)
-		return (0);
-	for (i = 0; i < pci_route_count; i++)
-		if (pci_route_table->pt_entry[i].pe_bus == bus)
-			return (1);
-	return (0);
+	printf("pci_cfgintr: can't route an interrupt to %d:%d INT%c without ACPI\n", bus, 
+	    device, 'A' + pin - 1);
+	return (PCI_INVALID_IRQ);
 }
 
 /* 
@@ -819,4 +346,3 @@ pcireg_cfgopen(void)
 	devmax = 0;
 	return (cfgmech);
 }
-