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| author | John Baldwin <jhb@FreeBSD.org> | 2015-01-05 20:44:44 +0000 |
|---|---|---|
| committer | John Baldwin <jhb@FreeBSD.org> | 2015-01-05 20:44:44 +0000 |
| commit | 92597e064b0d9c92229690e9cc9832e0559f4970 (patch) | |
| tree | ec71cc12df2ca8f19bd299ffa3546e15f67fbb62 /sys/amd64 | |
| parent | a9c218da80c3c79d35b52faeede65603b958385f (diff) | |
| download | src-92597e064b0d9c92229690e9cc9832e0559f4970.tar.gz src-92597e064b0d9c92229690e9cc9832e0559f4970.zip | |
On some Intel CPUs with a P-state but not C-state invariant TSC the TSC
may also halt in C2 and not just C3 (it seems that in some cases the BIOS
advertises its C3 state as a C2 state in _CST). Just play it safe and
disable both C2 and C3 states if a user forces the use of the TSC as the
timecounter on such CPUs.
PR: 192316
Differential Revision: https://reviews.freebsd.org/D1441
No objection from: jkim
MFC after: 1 week
Notes
Notes:
svn path=/head/; revision=276724
Diffstat (limited to 'sys/amd64')
| -rw-r--r-- | sys/amd64/amd64/machdep.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sys/amd64/amd64/machdep.c b/sys/amd64/amd64/machdep.c index 95d67c039f39..bcfdac143b4e 100644 --- a/sys/amd64/amd64/machdep.c +++ b/sys/amd64/amd64/machdep.c @@ -839,7 +839,7 @@ cpu_idle(int busy) } /* Apply AMD APIC timer C1E workaround. */ - if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { + if (cpu_ident_amdc1e && cpu_disable_c3_sleep) { msr = rdmsr(MSR_AMDK8_IPM); if (msr & AMDK8_CMPHALT) wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); |