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| author | Rafal Jaworowski <raj@FreeBSD.org> | 2008-10-13 18:16:54 +0000 |
|---|---|---|
| committer | Rafal Jaworowski <raj@FreeBSD.org> | 2008-10-13 18:16:54 +0000 |
| commit | ba6faad63c6859c777915629f8036fc236f03f64 (patch) | |
| tree | 8760a63d9c68590231c64efd968790b4094cb95d /sys/arm/include/armreg.h | |
| parent | 206267e7bbf6076a60e21786c94cb190e1d0c917 (diff) | |
| download | src-ba6faad63c6859c777915629f8036fc236f03f64.tar.gz src-ba6faad63c6859c777915629f8036fc236f03f64.zip | |
Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.
They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and
MV78100 (Discovery) system-on-chip families.
Obtained from: Marvell, Semihalf
Notes
Notes:
svn path=/head/; revision=183835
Diffstat (limited to 'sys/arm/include/armreg.h')
| -rw-r--r-- | sys/arm/include/armreg.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index eabcea82b9f3..6ba8cf437008 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -148,6 +148,9 @@ #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 #define CPU_ID_TI925T 0x54029250 +#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ +#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ +#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ #define CPU_ID_FA526 0x66015260 #define CPU_ID_SA1110 0x6901b110 #define CPU_ID_IXP1200 0x6901c120 @@ -253,6 +256,18 @@ /* Xscale Core 3 only */ #define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ +/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ +#define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ +#define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ +#define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ +#define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ +#define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ +#define FC_L2CACHE_EN 0x00400000 /* L2 enable */ +#define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ +#define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ +#define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ +#define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ + /* Cache type register definitions */ #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ |