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| author | Olivier Houchard <cognet@FreeBSD.org> | 2013-10-17 21:06:19 +0000 |
|---|---|---|
| committer | Olivier Houchard <cognet@FreeBSD.org> | 2013-10-17 21:06:19 +0000 |
| commit | f81c09049ad960c62dc7f3e96196400d8e7ad124 (patch) | |
| tree | 0eb36b67b911df6f5b8ca4e260c5c78e0b12e80c /sys/arm/include/pmap.h | |
| parent | 523ea374b63acf0a6149a0d8e24ce421ba8f6147 (diff) | |
| download | src-f81c09049ad960c62dc7f3e96196400d8e7ad124.tar.gz src-f81c09049ad960c62dc7f3e96196400d8e7ad124.zip | |
- Switch to use WBWA mappings for page tables on armv6, this is needed for SMP.
- Fix PTE_SYNC() for PIPT L2 caches, using the virtual address wasn't so useful.
- Use PTE_SYNC() for >= armv6
Notes
Notes:
svn path=/head/; revision=256707
Diffstat (limited to 'sys/arm/include/pmap.h')
| -rw-r--r-- | sys/arm/include/pmap.h | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h index 207abd0a0c1f..e5dbf52cf62d 100644 --- a/sys/arm/include/pmap.h +++ b/sys/arm/include/pmap.h @@ -63,7 +63,7 @@ #endif #define PTE_CACHE 6 #define PTE_DEVICE 2 -#define PTE_PAGETABLE 4 +#define PTE_PAGETABLE 6 #else #define PTE_NOCACHE 1 #define PTE_CACHE 2 @@ -489,7 +489,7 @@ extern int pmap_needs_pte_sync; #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC -#elif defined(CPU_XSCALE_81342) +#elif defined(CPU_XSCALE_81342) || defined(ARM_ARCH_7) || defined(ARM_ARCH_7A) #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC #elif (ARM_MMU_SA1 == 0) @@ -559,11 +559,18 @@ extern int pmap_needs_pte_sync; #define PMAP_INCLUDE_PTE_SYNC #endif +#ifdef ARM_L2_PIPT +#define _sync_l2(pte, size) cpu_l2cache_wb_range(vtophys(pte), size) +#else +#define _sync_l2(pte, size) cpu_l2_cache_wb_range(pte, size) +#endif + #define PTE_SYNC(pte) \ do { \ if (PMAP_NEEDS_PTE_SYNC) { \ cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ - cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ + cpu_drain_writebuf(); \ + _sync_l2((vm_offset_t)(pte), sizeof(pt_entry_t));\ } else \ cpu_drain_writebuf(); \ } while (/*CONSTCOND*/0) @@ -573,7 +580,8 @@ do { \ if (PMAP_NEEDS_PTE_SYNC) { \ cpu_dcache_wb_range((vm_offset_t)(pte), \ (cnt) << 2); /* * sizeof(pt_entry_t) */ \ - cpu_l2cache_wb_range((vm_offset_t)(pte), \ + cpu_drain_writebuf(); \ + _sync_l2((vm_offset_t)(pte), \ (cnt) << 2); /* * sizeof(pt_entry_t) */ \ } else \ cpu_drain_writebuf(); \ |