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| author | Andrew Turner <andrew@FreeBSD.org> | 2023-06-02 14:59:46 +0000 |
|---|---|---|
| committer | Andrew Turner <andrew@FreeBSD.org> | 2023-06-02 15:24:15 +0000 |
| commit | 4baf5db06ccfdb616abb6a68be99f297f7377bf4 (patch) | |
| tree | 96e3f1386fb851bcdc39c0be19b1e25063fb86ee /sys/arm64/include/armreg.h | |
| parent | 8cca8e248fb7f5fb475544a08d8cdb24d26bf4b3 (diff) | |
| download | src-4baf5db06ccfdb616abb6a68be99f297f7377bf4.tar.gz src-4baf5db06ccfdb616abb6a68be99f297f7377bf4.zip | |
Add more arm64 ID registers
These will be used by bhyve to emulate these registers.
Sponsored by: Arm Ltd
Diffstat (limited to 'sys/arm64/include/armreg.h')
| -rw-r--r-- | sys/arm64/include/armreg.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index cd5e7b8e1db8..c175c8d7a85c 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -451,6 +451,22 @@ /* ICC_SRE_EL1 */ #define ICC_SRE_EL1_SRE (1U << 0) +/* ID_AA64AFR0_EL1 */ +#define ID_AA64AFR0_EL1 MRS_REG(ID_AA64AFR0_EL1) +#define ID_AA64AFR0_EL1_op0 3 +#define ID_AA64AFR0_EL1_op1 0 +#define ID_AA64AFR0_EL1_CRn 0 +#define ID_AA64AFR0_EL1_CRm 5 +#define ID_AA64AFR0_EL1_op2 4 + +/* ID_AA64AFR1_EL1 */ +#define ID_AA64AFR1_EL1 MRS_REG(ID_AA64AFR1_EL1) +#define ID_AA64AFR1_EL1_op0 3 +#define ID_AA64AFR1_EL1_op1 0 +#define ID_AA64AFR1_EL1_CRn 0 +#define ID_AA64AFR1_EL1_CRm 5 +#define ID_AA64AFR1_EL1_op2 5 + /* ID_AA64DFR0_EL1 */ #define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1) #define ID_AA64DFR0_EL1_op0 0x3 |