Add the ARMv8.3 ID register fields. These were found in the A-Profile

exploration tools documentation:
https://developer.arm.com/products/architecture/a-profile/exploration-tools

Sponsored by:	DARPA, AFRL

1 files changed, 69 insertions, 3 deletions

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index c8d381e019bd..a7a15fc87850 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -205,7 +205,7 @@
 #define	 ID_AA64DFR0_PMS_VER_V1		(0x1ul << ID_AA64DFR0_PMS_VER_SHIFT)
 
 /* ID_AA64ISAR0_EL1 */
-#define	ID_AA64ISAR0_MASK		0xf0fffff0
+#define	ID_AA64ISAR0_MASK		0x0000fffff0fffff0ul
 #define	ID_AA64ISAR0_AES_SHIFT		4
 #define	ID_AA64ISAR0_AES_MASK		(0xf << ID_AA64ISAR0_AES_SHIFT)
 #define	ID_AA64ISAR0_AES(x)		((x) & ID_AA64ISAR0_AES_MASK)
@@ -222,6 +222,7 @@
 #define	ID_AA64ISAR0_SHA2(x)		((x) & ID_AA64ISAR0_SHA2_MASK)
 #define	 ID_AA64ISAR0_SHA2_NONE		(0x0 << ID_AA64ISAR0_SHA2_SHIFT)
 #define	 ID_AA64ISAR0_SHA2_BASE		(0x1 << ID_AA64ISAR0_SHA2_SHIFT)
+#define	 ID_AA64ISAR0_SHA2_512		(0x2 << ID_AA64ISAR0_SHA2_SHIFT)
 #define	ID_AA64ISAR0_CRC32_SHIFT	16
 #define	ID_AA64ISAR0_CRC32_MASK		(0xf << ID_AA64ISAR0_CRC32_SHIFT)
 #define	ID_AA64ISAR0_CRC32(x)		((x) & ID_AA64ISAR0_CRC32_MASK)
@@ -237,14 +238,69 @@
 #define	ID_AA64ISAR0_RDM(x)		((x) & ID_AA64ISAR0_RDM_MASK)
 #define	 ID_AA64ISAR0_RDM_NONE		(0x0 << ID_AA64ISAR0_RDM_SHIFT)
 #define	 ID_AA64ISAR0_RDM_IMPL		(0x1 << ID_AA64ISAR0_RDM_SHIFT)
+#define	ID_AA64ISAR0_SHA3_SHIFT		32
+#define	ID_AA64ISAR0_SHA3_MASK		(0xful << ID_AA64ISAR0_SHA3_SHIFT)
+#define	ID_AA64ISAR0_SHA3(x)		((x) & ID_AA64ISAR0_SHA3_MASK)
+#define	 ID_AA64ISAR0_SHA3_NONE		(0x0ul << ID_AA64ISAR0_SHA3_SHIFT)
+#define	 ID_AA64ISAR0_SHA3_IMPL		(0x1ul << ID_AA64ISAR0_SHA3_SHIFT)
+#define	ID_AA64ISAR0_SM3_SHIFT		36
+#define	ID_AA64ISAR0_SM3_MASK		(0xful << ID_AA64ISAR0_SM3_SHIFT)
+#define	ID_AA64ISAR0_SM3(x)		((x) & ID_AA64ISAR0_SM3_MASK)
+#define	 ID_AA64ISAR0_SM3_NONE		(0x0ul << ID_AA64ISAR0_SM3_SHIFT)
+#define	 ID_AA64ISAR0_SM3_IMPL		(0x1ul << ID_AA64ISAR0_SM3_SHIFT)
+#define	ID_AA64ISAR0_SM4_SHIFT		40
+#define	ID_AA64ISAR0_SM4_MASK		(0xful << ID_AA64ISAR0_SM4_SHIFT)
+#define	ID_AA64ISAR0_SM4(x)		((x) & ID_AA64ISAR0_SM4_MASK)
+#define	 ID_AA64ISAR0_SM4_NONE		(0x0ul << ID_AA64ISAR0_SM4_SHIFT)
+#define	 ID_AA64ISAR0_SM4_IMPL		(0x1ul << ID_AA64ISAR0_SM4_SHIFT)
+#define	ID_AA64ISAR0_DP_SHIFT		48
+#define	ID_AA64ISAR0_DP_MASK		(0xful << ID_AA64ISAR0_DP_SHIFT)
+#define	ID_AA64ISAR0_DP(x)		((x) & ID_AA64ISAR0_DP_MASK)
+#define	 ID_AA64ISAR0_DP_NONE		(0x0ul << ID_AA64ISAR0_DP_SHIFT)
+#define	 ID_AA64ISAR0_DP_IMPL		(0x1ul << ID_AA64ISAR0_DP_SHIFT)
 
 /* ID_AA64ISAR1_EL1 */
-#define	ID_AA64ISAR1_MASK		0x0000000f
+#define	ID_AA64ISAR1_MASK		0xffffffff
 #define	ID_AA64ISAR1_DPB_SHIFT		0
 #define	ID_AA64ISAR1_DPB_MASK		(0xf << ID_AA64ISAR1_DPB_SHIFT)
 #define	ID_AA64ISAR1_DPB(x)		((x) & ID_AA64ISAR1_DPB_MASK)
 #define	 ID_AA64ISAR1_DPB_NONE		(0x0 << ID_AA64ISAR1_DPB_SHIFT)
 #define	 ID_AA64ISAR1_DPB_IMPL		(0x1 << ID_AA64ISAR1_DPB_SHIFT)
+#define	ID_AA64ISAR1_APA_SHIFT		4
+#define	ID_AA64ISAR1_APA_MASK		(0xf << ID_AA64ISAR1_APA_SHIFT)
+#define	ID_AA64ISAR1_APA(x)		((x) & ID_AA64ISAR1_APA_MASK)
+#define	 ID_AA64ISAR1_APA_NONE		(0x0 << ID_AA64ISAR1_APA_SHIFT)
+#define	 ID_AA64ISAR1_APA_IMPL		(0x1 << ID_AA64ISAR1_APA_SHIFT)
+#define	ID_AA64ISAR1_API_SHIFT		8
+#define	ID_AA64ISAR1_API_MASK		(0xf << ID_AA64ISAR1_API_SHIFT)
+#define	ID_AA64ISAR1_API(x)		((x) & ID_AA64ISAR1_API_MASK)
+#define	 ID_AA64ISAR1_API_NONE		(0x0 << ID_AA64ISAR1_API_SHIFT)
+#define	 ID_AA64ISAR1_API_IMPL		(0x1 << ID_AA64ISAR1_API_SHIFT)
+#define	ID_AA64ISAR1_JSCVT_SHIFT	12
+#define	ID_AA64ISAR1_JSCVT_MASK		(0xf << ID_AA64ISAR1_JSCVT_SHIFT)
+#define	ID_AA64ISAR1_JSCVT(x)		((x) & ID_AA64ISAR1_JSCVT_MASK)
+#define	 ID_AA64ISAR1_JSCVT_NONE	(0x0 << ID_AA64ISAR1_JSCVT_SHIFT)
+#define	 ID_AA64ISAR1_JSCVT_IMPL	(0x1 << ID_AA64ISAR1_JSCVT_SHIFT)
+#define	ID_AA64ISAR1_FCMA_SHIFT		16
+#define	ID_AA64ISAR1_FCMA_MASK		(0xf << ID_AA64ISAR1_FCMA_SHIFT)
+#define	ID_AA64ISAR1_FCMA(x)		((x) & ID_AA64ISAR1_FCMA_MASK)
+#define	 ID_AA64ISAR1_FCMA_NONE		(0x0 << ID_AA64ISAR1_FCMA_SHIFT)
+#define	 ID_AA64ISAR1_FCMA_IMPL		(0x1 << ID_AA64ISAR1_FCMA_SHIFT)
+#define	ID_AA64ISAR1_LRCPC_SHIFT	20
+#define	ID_AA64ISAR1_LRCPC_MASK		(0xf << ID_AA64ISAR1_LRCPC_SHIFT)
+#define	ID_AA64ISAR1_LRCPC(x)		((x) & ID_AA64ISAR1_LRCPC_MASK)
+#define	 ID_AA64ISAR1_LRCPC_NONE	(0x0 << ID_AA64ISAR1_LRCPC_SHIFT)
+#define	 ID_AA64ISAR1_LRCPC_IMPL	(0x1 << ID_AA64ISAR1_LRCPC_SHIFT)
+#define	ID_AA64ISAR1_GPA_SHIFT		24
+#define	ID_AA64ISAR1_GPA_MASK		(0xf << ID_AA64ISAR1_GPA_SHIFT)
+#define	ID_AA64ISAR1_GPA(x)		((x) & ID_AA64ISAR1_GPA_MASK)
+#define	 ID_AA64ISAR1_GPA_NONE		(0x0 << ID_AA64ISAR1_GPA_SHIFT)
+#define	 ID_AA64ISAR1_GPA_IMPL		(0x1 << ID_AA64ISAR1_GPA_SHIFT)
+#define	ID_AA64ISAR1_GPI_SHIFT		28
+#define	ID_AA64ISAR1_GPI_MASK		(0xf << ID_AA64ISAR1_GPI_SHIFT)
+#define	ID_AA64ISAR1_GPI(x)		((x) & ID_AA64ISAR1_GPI_MASK)
+#define	 ID_AA64ISAR1_GPI_NONE		(0x0 << ID_AA64ISAR1_GPI_SHIFT)
+#define	 ID_AA64ISAR1_GPI_IMPL		(0x1 << ID_AA64ISAR1_GPI_SHIFT)
 
 /* ID_AA64MMFR0_EL1 */
 #define	ID_AA64MMFR0_MASK		0xffffffff
@@ -342,7 +398,7 @@
 
 /* ID_AA64MMFR2_EL1 */
 #define	ID_AA64MMFR2_EL1		S3_0_C0_C7_2
-#define	ID_AA64MMFR2_MASK		0x000fffff
+#define	ID_AA64MMFR2_MASK		0x0fffffff
 #define	ID_AA64MMFR2_CNP_SHIFT		0
 #define	ID_AA64MMFR2_CNP_MASK		(0xf << ID_AA64MMFR2_CNP_SHIFT)
 #define	ID_AA64MMFR2_CNP(x)		((x) & ID_AA64MMFR2_CNP_MASK)
@@ -368,6 +424,16 @@
 #define	ID_AA64MMFR2_VA_RANGE(x)	((x) & ID_AA64MMFR2_VA_RANGE_MASK)
 #define	 ID_AA64MMFR2_VA_RANGE_48	(0x0 << ID_AA64MMFR2_VA_RANGE_SHIFT)
 #define	 ID_AA64MMFR2_VA_RANGE_52	(0x1 << ID_AA64MMFR2_VA_RANGE_SHIFT)
+#define	ID_AA64MMFR2_CCIDX_SHIFT	20
+#define	ID_AA64MMFR2_CCIDX_MASK		(0xf << ID_AA64MMFR2_CCIDX_SHIFT)
+#define	ID_AA64MMFR2_CCIDX(x)		((x) & ID_AA64MMFR2_CCIDX_MASK)
+#define	 ID_AA64MMFR2_CCIDX_32		(0x0 << ID_AA64MMFR2_CCIDX_SHIFT)
+#define	 ID_AA64MMFR2_CCIDX_64		(0x1 << ID_AA64MMFR2_CCIDX_SHIFT)
+#define	ID_AA64MMFR2_NV_SHIFT		24
+#define	ID_AA64MMFR2_NV_MASK		(0xf << ID_AA64MMFR2_NV_SHIFT)
+#define	ID_AA64MMFR2_NV(x)		((x) & ID_AA64MMFR2_NV_MASK)
+#define	 ID_AA64MMFR2_NV_NONE		(0x0 << ID_AA64MMFR2_NV_SHIFT)
+#define	 ID_AA64MMFR2_NV_IMPL		(0x1 << ID_AA64MMFR2_NV_SHIFT)
 
 /* ID_AA64PFR0_EL1 */
 #define	ID_AA64PFR0_MASK		0x0000000ffffffffful