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| author | Dimitry Andric <dim@FreeBSD.org> | 2016-11-19 16:05:55 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2016-11-19 16:05:55 +0000 |
| commit | 67bc8c8b9e69bc53221a9bd914e418d81d6cdc7d (patch) | |
| tree | 7d222a83de8d7e5d1465e33f3c24660799770c92 /sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi | |
| parent | 2828dafcf3e7b225b70cbb380eb8c7dae452493e (diff) | |
| parent | 57b28934e964b15f1fcd91734c6dbef762222079 (diff) | |
| download | src-67bc8c8b9e69bc53221a9bd914e418d81d6cdc7d.tar.gz src-67bc8c8b9e69bc53221a9bd914e418d81d6cdc7d.zip | |
Merge ^/head r308491 through r308841.
Notes
Notes:
svn path=/projects/clang390-import/; revision=308842
Diffstat (limited to 'sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi')
| -rw-r--r-- | sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi | 22 |
1 files changed, 4 insertions, 18 deletions
diff --git a/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi b/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi index 2567be51da61..c83d6a2c1d99 100644 --- a/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi +++ b/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi @@ -28,25 +28,11 @@ / { clocks { - pll3: clk@01c20010 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clock-output-names = "pll3-1x", "pll3-2x"; - }; - - pll7: clk@01c20030 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clock-output-names = "pll7-1x", "pll7-2x"; - }; - hdmi_clk: clk@01c20150 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-hdmi-clk"; reg = <0x01c20150 0x4>; - clocks = <&pll3 0>, <&pll7 0>, <&pll3 1>, <&pll7 1>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; clock-output-names = "hdmi"; }; @@ -55,7 +41,7 @@ #reset-cells = <0>; compatible = "allwinner,sun4i-a10-lcd-ch0-clk"; reg = <0x01c20118 0x4>; - clocks = <&pll3 0>, <&pll7 0>, <&pll3 1>, <&pll6 2>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll6 2>; clock-output-names = "lcd0_ch0"; }; @@ -63,7 +49,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-lcd-ch1-clk"; reg = <0x01c2012c 0x4>; - clocks = <&pll3 0>, <&pll7 0>, <&pll3 1>, <&pll7 1>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; clock-output-names = "lcd0_ch1_sclk1", "lcd0_ch1_sclk2"; }; @@ -73,7 +59,7 @@ #reset-cells = <0>; compatible = "allwinner,sun4i-a10-de-be-clk"; reg = <0x01c20104 0x4>; - clocks = <&pll3 0>, <&pll7 0>, <&pll5 1>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; clock-output-names = "de_be0"; }; }; |