bhnd(4): include a subset of the ChipCommon capability flags in bhnd_chipid;

this provides early access to device capability flags required by bhnd(4)
bus and bhndb(4) bridge drivers.

1 files changed, 0 insertions, 168 deletions

diff --git a/sys/dev/bhnd/bhnd_subr.c b/sys/dev/bhnd/bhnd_subr.c
index 639153478f73..d8f3b486037c 100644
--- a/sys/dev/bhnd/bhnd_subr.c
+++ b/sys/dev/bhnd/bhnd_subr.c
@@ -1057,174 +1057,6 @@ bhnd_release_resources(device_t dev, const struct resource_spec *rs,
 }
 
 /**
- * Parse the CHIPC_ID_* fields from the ChipCommon CHIPC_ID
- * register, returning its bhnd_chipid representation.
- * 
- * @param idreg The CHIPC_ID register value.
- * @param enum_addr The enumeration address to include in the result.
- *
- * @warning
- * On early siba(4) devices, the ChipCommon core does not provide
- * a valid CHIPC_ID_NUMCORE field. On these ChipCommon revisions
- * (see CHIPC_NCORES_MIN_HWREV()), this function will parse and return
- * an invalid `ncores` value.
- */
-struct bhnd_chipid
-bhnd_parse_chipid(uint32_t idreg, bhnd_addr_t enum_addr)
-{
-	struct bhnd_chipid result;
-
-	/* Fetch the basic chip info */
-	result.chip_id = CHIPC_GET_BITS(idreg, CHIPC_ID_CHIP);
-	result.chip_pkg = CHIPC_GET_BITS(idreg, CHIPC_ID_PKG);
-	result.chip_rev = CHIPC_GET_BITS(idreg, CHIPC_ID_REV);
-	result.chip_type = CHIPC_GET_BITS(idreg, CHIPC_ID_BUS);
-	result.ncores = CHIPC_GET_BITS(idreg, CHIPC_ID_NUMCORE);
-
-	result.enum_addr = enum_addr;
-
-	return (result);
-}
-
-
-/**
- * Determine the correct core count for a chip identification value that
- * may contain an invalid core count.
- * 
- * On some early siba(4) devices (see CHIPC_NCORES_MIN_HWREV()), the ChipCommon
- * core does not provide a valid CHIPC_ID_NUMCORE field.
- * 
- * @param cid The chip identification to be queried.
- * @param chipc_hwrev The hardware revision of the ChipCommon core from which
- * @p cid was parsed.
- * @param[out] ncores On success, will be set to the correct core count.
- * 
- * @retval 0 If the core count is already correct, or was mapped to a
- * a correct value.
- * @retval EINVAL If the core count is incorrect, but the chip was not
- * recognized.
- */
-int
-bhnd_chipid_fixed_ncores(const struct bhnd_chipid *cid, uint16_t chipc_hwrev,
-    uint8_t *ncores)
-{
-	/* bcma(4), and most siba(4) devices */
-	if (CHIPC_NCORES_MIN_HWREV(chipc_hwrev)) {
-		*ncores = cid->ncores;
-		return (0);
-	}
-
-	/* broken siba(4) chipsets */
-	switch (cid->chip_id) {
-	case BHND_CHIPID_BCM4306:
-		*ncores = 6;
-		break;
-	case BHND_CHIPID_BCM4704:
-		*ncores = 9;
-		break;
-	case BHND_CHIPID_BCM5365:
-		/*
-		* BCM5365 does support ID_NUMCORE in at least
-		* some of its revisions, but for unknown
-		* reasons, Broadcom's drivers always exclude
-		* the ChipCommon revision (0x5) used by BCM5365
-		* from the set of revisions supporting
-		* ID_NUMCORE, and instead supply a fixed value.
-		* 
-		* Presumably, at least some of these devices
-		* shipped with a broken ID_NUMCORE value.
-		*/
-		*ncores = 7;
-		break;
-	default:
-		return (EINVAL);
-	}
-
-	return (0);
-}
-
-/**
- * Allocate the resource defined by @p rs via @p dev, use it
- * to read the ChipCommon ID register relative to @p chipc_offset,
- * then release the resource.
- * 
- * @param dev The device owning @p rs.
- * @param rs A resource spec that encompasses the ChipCommon register block.
- * @param chipc_offset The offset of the ChipCommon registers within @p rs.
- * @param[out] result The chip identification data.
- * 
- * @retval 0 success
- * @retval non-zero if the ChipCommon identification data could not be read.
- */
-int
-bhnd_read_chipid(device_t dev, struct resource_spec *rs,
-    bus_size_t chipc_offset, struct bhnd_chipid *result)
-{
-	struct resource			*res;
-	bhnd_addr_t			 enum_addr;
-	uint32_t			 reg;
-	uint8_t				 chip_type;
-	int				 error, rid, rtype;
-
-	rid = rs->rid;
-	rtype = rs->type;
-	error = 0;
-
-	/* Allocate the ChipCommon window resource and fetch the chipid data */
-	res = bus_alloc_resource_any(dev, rtype, &rid, RF_ACTIVE);
-	if (res == NULL) {
-		device_printf(dev,
-		    "failed to allocate bhnd chipc resource\n");
-		return (ENXIO);
-	}
-
-	/* Fetch the basic chip info */
-	reg = bus_read_4(res, chipc_offset + CHIPC_ID);
-	chip_type = CHIPC_GET_BITS(reg, CHIPC_ID_BUS);
-
-	/* Fetch the EROMPTR */
-	if (BHND_CHIPTYPE_HAS_EROM(chip_type)) {
-		enum_addr = bus_read_4(res, chipc_offset + CHIPC_EROMPTR);
-	} else if (chip_type == BHND_CHIPTYPE_SIBA) {
-		/* siba(4) uses the ChipCommon base address as the enumeration
-		 * address */
-		enum_addr = BHND_DEFAULT_CHIPC_ADDR;
-	} else {
-		device_printf(dev, "unknown chip type %hhu\n", chip_type);
-		error = ENODEV;
-		goto cleanup;
-	}
-
-	*result = bhnd_parse_chipid(reg, enum_addr);
-
-	/* Fix the core count on early siba(4) devices */
-	if (chip_type == BHND_CHIPTYPE_SIBA) {
-		uint32_t	idh;
-		uint16_t	chipc_hwrev;
-
-		/* 
-		 * We need the ChipCommon revision to determine whether
-		 * the ncore field is valid.
-		 * 
-		 * We can safely assume the siba IDHIGH register is mapped
-		 * within the chipc register block.
-		 */
-		idh = bus_read_4(res, SB0_REG_ABS(SIBA_CFG0_IDHIGH));
-		chipc_hwrev = SIBA_IDH_CORE_REV(idh);
-
-		error = bhnd_chipid_fixed_ncores(result, chipc_hwrev,
-		    &result->ncores);
-		if (error)
-			goto cleanup;
-	}
-
-cleanup:
-	/* Clean up */
-	bus_release_resource(dev, rtype, rid, res);
-	return (error);
-}
-
-/**
  * Allocate and return a new per-core PMU clock control/status (clkctl)
  * instance for @p dev.
  *