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authorAndrew Turner <andrew@FreeBSD.org>2026-09-18 11:29:19 +0000
committerAndrew Turner <andrew@FreeBSD.org>2026-09-18 11:29:19 +0000
commit50e01b6351b1a4955814cce021852c65a5b5bb9f (patch)
tree6d873f94f2732679f162a7217907387d5f5c8ced /sys/dev/dwc
parent0689a5ea451bdef62f7e81ffb3e5f580c5c99b2b (diff)
arm64/smmu: Only MSI poll when cache-coherentHEADmain
Only use the MSI polling method when we support MSIs and the SMMU is cache-coherent. The SMMU writes to a memory location. If it is not cache-coherent then the CPU may read the existing value in its cache and miss the signal the sync operation has completed. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D59489
Diffstat (limited to 'sys/dev/dwc')
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