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author | Emmanuel Vadot <manu@FreeBSD.org> | 2019-08-10 18:50:37 +0000 |
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committer | Emmanuel Vadot <manu@FreeBSD.org> | 2019-08-10 18:50:37 +0000 |
commit | 8c8b86922a8eb034e9d38a19d7c8b6462ba698fd (patch) | |
tree | 71f29be16968ce01eca1ea3a92e4516a35a5e798 /sys/dev/extres | |
parent | d52a918e3fefc8583dd0383c95fff2f1b4ea352a (diff) | |
download | src-8c8b86922a8eb034e9d38a19d7c8b6462ba698fd.tar.gz src-8c8b86922a8eb034e9d38a19d7c8b6462ba698fd.zip |
allwinner: Add a new clock aw_clk_m
We used the aw_clk_nm clock for clock with only one divider factor
and used a fake multiplier factor. This cannot work properly as we
end up writing the "fake" factor to the register (and so always set
the LSB to 1).
Create a new clock for those.
The reason for not using the clk_div clock is because those clocks are
a bit special. Since they are (almost) all related to video we also need
to set the parent clock (the main PLL) to a frequency that they can support.
As the main PLL have some minimal frequency that they can support we need to
be able to set the main PLL to a multiple of the desired frequency.
Let say you want to have a 71Mhz pixel clock (typical for a 1280x800 display)
and the main PLL cannot go under 192Mhz, you need to set it to 3 times the
desired frequency and set the divider to 3 on the hdmi clock.
So this also introduce the CLK_SET_ROUND_MULTIPLE flag that allow for this kind
of scenario.
Notes
Notes:
svn path=/head/; revision=350844
Diffstat (limited to 'sys/dev/extres')
-rw-r--r-- | sys/dev/extres/clk/clk.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sys/dev/extres/clk/clk.h b/sys/dev/extres/clk/clk.h index 4be9d3f12396..696967a69d9d 100644 --- a/sys/dev/extres/clk/clk.h +++ b/sys/dev/extres/clk/clk.h @@ -48,6 +48,7 @@ #define CLK_SET_ROUND_EXACT 0 #define CLK_SET_ROUND_UP 0x00000001 #define CLK_SET_ROUND_DOWN 0x00000002 +#define CLK_SET_ROUND_MULTIPLE 0x00000004 #define CLK_SET_ROUND_ANY (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN) #define CLK_SET_USER_MASK 0x0000FFFF |