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| author | Hidetoshi Shimokawa <simokawa@FreeBSD.org> | 2002-12-26 03:17:59 +0000 |
|---|---|---|
| committer | Hidetoshi Shimokawa <simokawa@FreeBSD.org> | 2002-12-26 03:17:59 +0000 |
| commit | ac9f66922bc9e79d754d2349f535d4d00accbcba (patch) | |
| tree | 24c2f3ab3349ce71dcd3c7c66ef961f07d7e2855 /sys/dev/firewire/fwohcireg.h | |
| parent | fcfa5b69b12c6137a15b43540501845b4bf47f33 (diff) | |
| download | src-ac9f66922bc9e79d754d2349f535d4d00accbcba.tar.gz src-ac9f66922bc9e79d754d2349f535d4d00accbcba.zip | |
firewire.c
- Fix permission of device node.
fwochi.c, fwohcireg.h
- Detect phy access failure correct way.
- Set root hold-off bit before initiating bus reset.
This should fix the problem with VIA6306.
fwohcivar.h
- Fix over-allocation of array. (fwohcivar.h)
sbp.c
- Return CAM_DEV_NOT_THERE rather than CAM_TID_INVALID to prevent retry.
Notes
Notes:
svn path=/head/; revision=108276
Diffstat (limited to 'sys/dev/firewire/fwohcireg.h')
| -rw-r--r-- | sys/dev/firewire/fwohcireg.h | 23 |
1 files changed, 2 insertions, 21 deletions
diff --git a/sys/dev/firewire/fwohcireg.h b/sys/dev/firewire/fwohcireg.h index cbc556d50c01..cb399b6beb78 100644 --- a/sys/dev/firewire/fwohcireg.h +++ b/sys/dev/firewire/fwohcireg.h @@ -300,27 +300,6 @@ struct fwohcidb_tr{ /* * OHCI info structure. */ -#if 0 -struct fwohci_softc { - struct fw_softc fc; - volatile struct ohci_registers *base; - int init; -#define SIDPHASE 1 - u_int32_t flags; - struct fwohcidb_tr *db_tr[OHCI_MAX_DMA_CH]; - struct fwohcidb_tr *db_first[OHCI_MAX_DMA_CH]; - struct fwohcidb_tr *db_last[OHCI_MAX_DMA_CH]; - struct { - int tail; - struct fwohcidb_tr *db_tr; - struct fwohcidb *db; - }dbdvtx[MAX_DVFRAME], dbdvrx[MAX_DVFRAME]; - int ndb[OHCI_MAX_DMA_CH]; - u_int32_t isohdr[OHCI_MAX_DMA_CH]; - int queued[OHCI_MAX_DMA_CH]; - int dma_ch[OHCI_MAX_DMA_CH]; -}; -#endif struct fwohci_txpkthdr{ union{ u_int32_t ld[4]; @@ -378,6 +357,8 @@ struct fwohci_trailer{ #define OHCI_INT_PHY_SID (0x1 << 16) #define OHCI_INT_PHY_BUS_R (0x1 << 17) +#define OHCI_INT_REG_FAIL (0x1 << 18) + #define OHCI_INT_PHY_INT (0x1 << 19) #define OHCI_INT_CYC_START (0x1 << 20) #define OHCI_INT_CYC_64SECOND (0x1 << 21) |