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authorMaxime Henrion <mux@FreeBSD.org>2005-09-27 09:01:11 +0000
committerMaxime Henrion <mux@FreeBSD.org>2005-09-27 09:01:11 +0000
commit05bd8c224e8acd185365751be72b5c4751abfcd0 (patch)
tree3d649e4216ae9d3b4bc8c9a8a8ebd04167ebf058 /sys/dev/fxp/if_fxpvar.h
parent762fcdcf7df7c0350db8f58a049e0538a8cd4dc5 (diff)
downloadsrc-05bd8c224e8acd185365751be72b5c4751abfcd0.tar.gz
src-05bd8c224e8acd185365751be72b5c4751abfcd0.zip
Convert fxp(4) to use the new bus_alloc_resources() API, it simplifies
the resource allocation code significantly.
Notes
Notes: svn path=/head/; revision=150610
Diffstat (limited to 'sys/dev/fxp/if_fxpvar.h')
-rw-r--r--sys/dev/fxp/if_fxpvar.h26
1 files changed, 8 insertions, 18 deletions
diff --git a/sys/dev/fxp/if_fxpvar.h b/sys/dev/fxp/if_fxpvar.h
index f8da9874b94a..b00f9eba58c8 100644
--- a/sys/dev/fxp/if_fxpvar.h
+++ b/sys/dev/fxp/if_fxpvar.h
@@ -142,14 +142,10 @@ struct fxp_desc_list {
*/
struct fxp_softc {
struct ifnet *ifp; /* per-interface network data */
- struct resource *mem; /* resource descriptor for registers */
- int rtp; /* register resource type */
- int rgd; /* register descriptor in use */
- struct resource *irq; /* resource descriptor for interrupt */
+ struct resource *fxp_res[2]; /* I/O and IRQ resources */
+ struct resource_spec *fxp_spec; /* the resource spec we used */
void *ih; /* interrupt handler cookie */
struct mtx sc_mtx;
- bus_space_tag_t sc_st; /* bus space tag */
- bus_space_handle_t sc_sh; /* bus space handle */
bus_dma_tag_t fxp_mtag; /* bus DMA tag for mbufs */
bus_dma_tag_t fxp_stag; /* bus DMA tag for stats */
bus_dmamap_t fxp_smap; /* bus DMA map for stats */
@@ -198,15 +194,9 @@ struct fxp_softc {
#define FXP_FLAG_SAVE_BAD 0x0800 /* save bad pkts: bad size, CRC, etc */
/* Macros to ease CSR access. */
-#define CSR_READ_1(sc, reg) \
- bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
-#define CSR_READ_2(sc, reg) \
- bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
-#define CSR_READ_4(sc, reg) \
- bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
-#define CSR_WRITE_1(sc, reg, val) \
- bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
-#define CSR_WRITE_2(sc, reg, val) \
- bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
-#define CSR_WRITE_4(sc, reg, val) \
- bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
+#define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg)
+#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)
+#define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)
+#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)
+#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val)
+#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->fxp_res[0], reg, val)