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| author | Andrew Turner <andrew@FreeBSD.org> | 2019-10-30 12:47:00 +0000 |
|---|---|---|
| committer | Andrew Turner <andrew@FreeBSD.org> | 2019-10-30 12:47:00 +0000 |
| commit | fc232b89add74a4e6a2d66734c1a0739754b2162 (patch) | |
| tree | 1292a43e2db9770b00b188150ceb0049a299cc7a /sys/dev/hwpmc/hwpmc_arm64.c | |
| parent | cb5343c27885c17ff794497aa8d16294986a8add (diff) | |
| download | src-fc232b89add74a4e6a2d66734c1a0739754b2162.tar.gz src-fc232b89add74a4e6a2d66734c1a0739754b2162.zip | |
Use a lowercase name for arm64 special registers so they don't conflict
with macros of the same name.
Sponsored by: DARPA, AFRL
Notes
Notes:
svn path=/head/; revision=354177
Diffstat (limited to 'sys/dev/hwpmc/hwpmc_arm64.c')
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_arm64.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c index af028d3fce94..2618a889e86f 100644 --- a/sys/dev/hwpmc/hwpmc_arm64.c +++ b/sys/dev/hwpmc/hwpmc_arm64.c @@ -63,7 +63,7 @@ arm64_interrupt_enable(uint32_t pmc) uint32_t reg; reg = (1 << pmc); - WRITE_SPECIALREG(PMINTENSET_EL1, reg); + WRITE_SPECIALREG(pmintenset_el1, reg); isb(); } @@ -77,7 +77,7 @@ arm64_interrupt_disable(uint32_t pmc) uint32_t reg; reg = (1 << pmc); - WRITE_SPECIALREG(PMINTENCLR_EL1, reg); + WRITE_SPECIALREG(pmintenclr_el1, reg); isb(); } @@ -91,7 +91,7 @@ arm64_counter_enable(unsigned int pmc) uint32_t reg; reg = (1 << pmc); - WRITE_SPECIALREG(PMCNTENSET_EL0, reg); + WRITE_SPECIALREG(pmcntenset_el0, reg); isb(); } @@ -105,7 +105,7 @@ arm64_counter_disable(unsigned int pmc) uint32_t reg; reg = (1 << pmc); - WRITE_SPECIALREG(PMCNTENCLR_EL0, reg); + WRITE_SPECIALREG(pmcntenclr_el0, reg); isb(); } @@ -118,7 +118,7 @@ arm64_pmcr_read(void) { uint32_t reg; - reg = READ_SPECIALREG(PMCR_EL0); + reg = READ_SPECIALREG(pmcr_el0); return (reg); } @@ -127,7 +127,7 @@ static void arm64_pmcr_write(uint32_t reg) { - WRITE_SPECIALREG(PMCR_EL0, reg); + WRITE_SPECIALREG(pmcr_el0, reg); isb(); } @@ -141,11 +141,11 @@ arm64_pmcn_read(unsigned int pmc) KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); - WRITE_SPECIALREG(PMSELR_EL0, pmc); + WRITE_SPECIALREG(pmselr_el0, pmc); isb(); - return (READ_SPECIALREG(PMXEVCNTR_EL0)); + return (READ_SPECIALREG(pmxevcntr_el0)); } static void @@ -154,8 +154,8 @@ arm64_pmcn_write(unsigned int pmc, uint32_t reg) KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); - WRITE_SPECIALREG(PMSELR_EL0, pmc); - WRITE_SPECIALREG(PMXEVCNTR_EL0, reg); + WRITE_SPECIALREG(pmselr_el0, pmc); + WRITE_SPECIALREG(pmxevcntr_el0, reg); isb(); } @@ -273,8 +273,8 @@ arm64_start_pmc(int cpu, int ri) /* * Configure the event selection. */ - WRITE_SPECIALREG(PMSELR_EL0, ri); - WRITE_SPECIALREG(PMXEVTYPER_EL0, config); + WRITE_SPECIALREG(pmselr_el0, ri); + WRITE_SPECIALREG(pmxevtyper_el0, config); isb(); @@ -347,10 +347,10 @@ arm64_intr(struct trapframe *tf) /* Check if counter is overflowed */ reg = (1 << ri); - if ((READ_SPECIALREG(PMOVSCLR_EL0) & reg) == 0) + if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) continue; /* Clear Overflow Flag */ - WRITE_SPECIALREG(PMOVSCLR_EL0, reg); + WRITE_SPECIALREG(pmovsclr_el0, reg); isb(); |