Allow the i2c node requirements to be slightly relaxed.

These realtek switch PHYs speak a variant of i2c with some slightly
modified handling.

From the submitter, slightly modified now that some further digging
has been done:

  The I2C framework makes a assumption that the read/not-write bit of the first
  byte (the address) indicates whether reads or writes are to follow.

  The RTL8366 family uses the bus: after sending the address+read/not-write byte,
  two register address bytes are sent, then the 16-bit register value is sent
  or received.  While the register write access can be performed as a 4-byte
  write, the read access requires the read bit to be set, but the first two bytes
  for the register address then need to be transmitted.

This patch maintains the i2c protocol behaviour but allows it to be relaxed
(for these kinds of switch PHYs, and whatever else Realtek may do with this
almost-but-not-quite i2c bus) - by setting the "strict" hint to 0.
The "strict" hint defaults to 1.

Submitted by:	Stefan Bethke <stb@lassitu.de>

1 files changed, 2 insertions, 0 deletions

diff --git a/sys/dev/iicbus/iicbus.h b/sys/dev/iicbus/iicbus.h
index 0698d5c17b4a..92c250ea8013 100644
--- a/sys/dev/iicbus/iicbus.h
+++ b/sys/dev/iicbus/iicbus.h
@@ -41,6 +41,8 @@ struct iicbus_softc
 	device_t owner;		/* iicbus owner device structure */
 	u_char started;		/* address of the 'started' slave
 				 * 0 if no start condition succeeded */
+	u_char strict;		/* deny operations that violate the
+				 * I2C protocol */
 	struct mtx lock;
 };