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| author | Paulo Fragoso <paulo@nlink.com.br> | 2026-03-12 15:21:33 +0000 |
|---|---|---|
| committer | Mitchell Horne <mhorne@FreeBSD.org> | 2026-03-12 15:29:04 +0000 |
| commit | ce9aff829e02c9a21c04eae77a45f2193d1ed5a1 (patch) | |
| tree | 41950fc2e6de680feebbd21688bdce649746340c /sys/dev/qat/qat_hw | |
| parent | 25cc459286a02b646751541ccde5a33319471c73 (diff) | |
The previous code subtracted AMD_PMC_PERFCTR_0 (0xC0010004) from all
perfctr MSR addresses to compute a relative offset. This is incorrect
for counters using AMD_PMC_CORE_BASE (0xC0010200), AMD_PMC_L3_BASE
(0xC0010230), and AMD_PMC_DF_BASE (0xC0010240), producing wrong offsets.
Fix by promoting amd_core_npmcs, amd_l3_npmcs, and amd_df_npmcs to
static module-level variables and computing the correct flat RDPMC
index per AMD BKDG 24594 page 440:
ECX 0-5: Core counters 0-5
ECX 6-9: DF counters 0-3
ECX 10-15: L3 Cache counters 0-5
ECX 16-27: DF counters 4-15
ECX > 27: Reserved, returns EINVAL
Reviewed by: Ali Mashtizadeh <ali@mashtizadeh.com>, mhorne
Sponsored by: NLINK (https://nlink.com.br), Recife, Brazil
Fixes: 37bba2ad92d8 ("hwpmc_amd: Add support for additional counters")
Differential Revision: https://reviews.freebsd.org/D55607
Diffstat (limited to 'sys/dev/qat/qat_hw')
0 files changed, 0 insertions, 0 deletions