MFC

5 files changed, 1745 insertions, 4 deletions

diff --git a/sys/dev/usb/net/if_axe.c b/sys/dev/usb/net/if_axe.c
index fbe63de90c39..00d1c0b4b069 100644
--- a/sys/dev/usb/net/if_axe.c
+++ b/sys/dev/usb/net/if_axe.c
@@ -514,7 +514,7 @@ static void
 axe_ax88178_init(struct axe_softc *sc)
 {
 	struct usb_ether *ue;
-	int gpio0, phymode;
+	int gpio0, ledmode, phymode;
 	uint16_t eeprom, val;
 
 	ue = &sc->sc_ue;
@@ -528,9 +528,11 @@ axe_ax88178_init(struct axe_softc *sc)
 	if (eeprom == 0xffff) {
 		phymode = AXE_PHY_MODE_MARVELL;
 		gpio0 = 1;
+		ledmode = 0;
 	} else {
 		phymode = eeprom & 0x7f;
 		gpio0 = (eeprom & 0x80) ? 0 : 1;
+		ledmode = eeprom >> 8;
 	}
 
 	if (bootverbose)
@@ -548,9 +550,22 @@ axe_ax88178_init(struct axe_softc *sc)
 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
 			    hz / 32);
-		} else
+		} else {
 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
-			    AXE_GPIO1_EN, hz / 32);
+			    AXE_GPIO1_EN, hz / 3);
+			if (ledmode == 1) {
+				AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
+				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
+				    hz / 3);
+			} else {
+				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
+				    AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
+				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
+				    AXE_GPIO2_EN, hz / 4);
+				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
+				    AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
+			}
+		}
 		break;
 	case AXE_PHY_MODE_CICADA:
 	case AXE_PHY_MODE_CICADA_V2:
diff --git a/sys/dev/usb/serial/umcs7840.c b/sys/dev/usb/serial/umcs7840.c
new file mode 100644
index 000000000000..34b68a15a769
--- /dev/null
+++ b/sys/dev/usb/serial/umcs7840.c
@@ -0,0 +1,1075 @@
+/*-
+ * Copyright (c) 2010 Lev Serebryakov <lev@FreeBSD.org>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * This driver supports several multiport USB-to-RS232 serial adapters driven
+ * by MosChip mos7820 and mos7840, bridge chips.
+ * The adapters are sold under many different brand names.
+ *
+ * Datasheets are available at MosChip www site at
+ * http://www.moschip.com.  The datasheets don't contain full
+ * programming information for the chip.
+ *
+ * It is nornal to have only two enabled ports in devices, based on
+ * quad-port mos7840.
+ *
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/stdint.h>
+#include <sys/stddef.h>
+#include <sys/param.h>
+#include <sys/queue.h>
+#include <sys/types.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/linker_set.h>
+#include <sys/module.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+#include <sys/sysctl.h>
+#include <sys/sx.h>
+#include <sys/unistd.h>
+#include <sys/callout.h>
+#include <sys/malloc.h>
+#include <sys/priv.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdi_util.h>
+#include <dev/usb/usb_cdc.h>
+#include "usbdevs.h"
+
+#define	USB_DEBUG_VAR umcs7840_debug
+#include <dev/usb/usb_debug.h>
+#include <dev/usb/usb_process.h>
+
+#include <dev/usb/serial/usb_serial.h>
+
+#include <dev/usb/serial/umcs7840.h>
+
+#define	UMCS7840_MODVER	1
+
+#ifdef USB_DEBUG
+static int umcs7840_debug = 0;
+
+SYSCTL_NODE(_hw_usb, OID_AUTO, umcs7840, CTLFLAG_RW, 0, "USB umcs7840 quadport serial adapter");
+SYSCTL_INT(_hw_usb_umcs7840, OID_AUTO, debug, CTLFLAG_RW, &umcs7840_debug, 0, "Debug level");
+#endif					/* USB_DEBUG */
+
+
+/*
+ * Two-port devices (both with 7820 chip and 7840 chip configured as two-port)
+ * have ports 0 and 2, with ports 1 and 3 omitted.
+ * So,PHYSICAL port numbers (indexes) on two-port device will be 0 and 2.
+ * This driver trys to use physical numbers as much as possible.
+ */
+
+/*
+ * Indexed by PHYSICAL port number.
+ * Pack non-regular registers to array to easier if-less access.
+ */
+struct umcs7840_port_registers {
+	uint8_t	reg_sp;			/* SP register. */
+	uint8_t	reg_control;		/* CONTROL register. */
+	uint8_t	reg_dcr;		/* DCR0 register. DCR1 & DCR2 can be
+					 * calculated */
+};
+
+static const struct umcs7840_port_registers umcs7840_port_registers[UMCS7840_MAX_PORTS] = {
+	{.reg_sp = MCS7840_DEV_REG_SP1,.reg_control = MCS7840_DEV_REG_CONTROL1,.reg_dcr = MCS7840_DEV_REG_DCR0_1},
+	{.reg_sp = MCS7840_DEV_REG_SP2,.reg_control = MCS7840_DEV_REG_CONTROL2,.reg_dcr = MCS7840_DEV_REG_DCR0_2},
+	{.reg_sp = MCS7840_DEV_REG_SP3,.reg_control = MCS7840_DEV_REG_CONTROL3,.reg_dcr = MCS7840_DEV_REG_DCR0_3},
+	{.reg_sp = MCS7840_DEV_REG_SP4,.reg_control = MCS7840_DEV_REG_CONTROL4,.reg_dcr = MCS7840_DEV_REG_DCR0_4},
+};
+
+enum {
+	UMCS7840_BULK_RD_EP,
+	UMCS7840_BULK_WR_EP,
+	UMCS7840_N_TRANSFERS
+};
+
+struct umcs7840_softc_oneport {
+	struct usb_xfer *sc_xfer[UMCS7840_N_TRANSFERS];	/* Control structures
+							 * for two transfers */
+
+	uint8_t	sc_lcr;			/* local line control register */
+	uint8_t	sc_mcr;			/* local modem control register */
+	uint8_t	sc_lsr;			/* local line status register */
+	uint8_t	sc_msr;			/* local modem status register */
+};
+
+struct umcs7840_softc {
+	struct ucom_super_softc sc_super_ucom;
+	struct ucom_softc sc_ucom[UMCS7840_MAX_PORTS];	/* Need to be continuous
+							 * array, so indexed by
+							 * LOGICAL port
+							 * (subunit) number */
+
+	struct usb_xfer *sc_intr_xfer;	/* Interrupt endpoint */
+
+	device_t sc_dev;		/* Device for error prints */
+	struct usb_device *sc_udev;	/* USB Device for all operations */
+	struct mtx sc_mtx;		/* ucom requires this */
+
+	uint8_t	sc_driver_done;		/* Flag when enumeration is finished */
+
+	uint8_t	sc_numports;		/* Number of ports (subunits) */
+	struct umcs7840_softc_oneport sc_ports[UMCS7840_MAX_PORTS];	/* Indexed by PHYSICAL
+									 * port number. */
+};
+
+/* prototypes */
+static usb_error_t umcs7840_get_reg_sync(struct umcs7840_softc *, uint8_t, uint8_t *);
+static usb_error_t umcs7840_set_reg_sync(struct umcs7840_softc *, uint8_t, uint8_t);
+static usb_error_t umcs7840_get_UART_reg_sync(struct umcs7840_softc *, uint8_t, uint8_t, uint8_t *);
+static usb_error_t umcs7840_set_UART_reg_sync(struct umcs7840_softc *, uint8_t, uint8_t, uint8_t);
+
+static usb_error_t umcs7840_set_baudrate(struct umcs7840_softc *, uint8_t, uint32_t);
+static usb_error_t umcs7840_calc_baudrate(uint32_t rate, uint16_t *, uint8_t *);
+
+static void umcs7840_cfg_get_status(struct ucom_softc *, uint8_t *, uint8_t *);
+static void umcs7840_cfg_set_dtr(struct ucom_softc *, uint8_t);
+static void umcs7840_cfg_set_rts(struct ucom_softc *, uint8_t);
+static void umcs7840_cfg_set_break(struct ucom_softc *, uint8_t);
+static void umcs7840_cfg_param(struct ucom_softc *, struct termios *);
+static void umcs7840_cfg_open(struct ucom_softc *);
+static void umcs7840_cfg_close(struct ucom_softc *);
+
+static int umcs7840_pre_param(struct ucom_softc *, struct termios *);
+
+static void umcs7840_start_read(struct ucom_softc *);
+static void umcs7840_stop_read(struct ucom_softc *);
+
+static void umcs7840_start_write(struct ucom_softc *);
+static void umcs7840_stop_write(struct ucom_softc *);
+
+static void umcs7840_poll(struct ucom_softc *ucom);
+
+static device_probe_t umcs7840_probe;
+static device_attach_t umcs7840_attach;
+static device_detach_t umcs7840_detach;
+
+static usb_callback_t umcs7840_intr_callback;
+static usb_callback_t umcs7840_read_callback1;
+static usb_callback_t umcs7840_read_callback2;
+static usb_callback_t umcs7840_read_callback3;
+static usb_callback_t umcs7840_read_callback4;
+static usb_callback_t umcs7840_write_callback1;
+static usb_callback_t umcs7840_write_callback2;
+static usb_callback_t umcs7840_write_callback3;
+static usb_callback_t umcs7840_write_callback4;
+
+static void umcs7840_read_callbackN(struct usb_xfer *, usb_error_t, uint8_t);
+static void umcs7840_write_callbackN(struct usb_xfer *, usb_error_t, uint8_t);
+
+/* Indexed by LOGICAL port number (subunit), so two-port device uses 0 & 1 */
+static usb_callback_t *umcs7840_rw_callbacks[UMCS7840_MAX_PORTS][UMCS7840_N_TRANSFERS] = {
+	{&umcs7840_read_callback1, &umcs7840_write_callback1},
+	{&umcs7840_read_callback2, &umcs7840_write_callback2},
+	{&umcs7840_read_callback3, &umcs7840_write_callback3},
+	{&umcs7840_read_callback4, &umcs7840_write_callback4},
+};
+
+static const struct usb_config umcs7840_bulk_config_data[UMCS7840_N_TRANSFERS] = {
+	[UMCS7840_BULK_RD_EP] = {
+		.type = UE_BULK,
+		.endpoint = 0x01,
+		.direction = UE_DIR_IN,
+		.flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
+		.bufsize = 0,		/* use wMaxPacketSize */
+		.callback = &umcs7840_read_callback1,
+		.if_index = 0,
+	},
+
+	[UMCS7840_BULK_WR_EP] = {
+		.type = UE_BULK,
+		.endpoint = 0x02,
+		.direction = UE_DIR_OUT,
+		.flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
+		.bufsize = 0,		/* use wMaxPacketSize */
+		.callback = &umcs7840_write_callback1,
+		.if_index = 0,
+	},
+};
+
+static const struct usb_config umcs7840_intr_config_data[1] = {
+	[0] = {
+		.type = UE_INTERRUPT,
+		.endpoint = 0x09,
+		.direction = UE_DIR_IN,
+		.flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
+		.bufsize = 0,		/* use wMaxPacketSize */
+		.callback = &umcs7840_intr_callback,
+		.if_index = 0,
+	},
+};
+
+static struct ucom_callback umcs7840_callback = {
+	.ucom_cfg_get_status = &umcs7840_cfg_get_status,
+
+	.ucom_cfg_set_dtr = &umcs7840_cfg_set_dtr,
+	.ucom_cfg_set_rts = &umcs7840_cfg_set_rts,
+	.ucom_cfg_set_break = &umcs7840_cfg_set_break,
+
+	.ucom_cfg_param = &umcs7840_cfg_param,
+	.ucom_cfg_open = &umcs7840_cfg_open,
+	.ucom_cfg_close = &umcs7840_cfg_close,
+
+	.ucom_pre_param = &umcs7840_pre_param,
+
+	.ucom_start_read = &umcs7840_start_read,
+	.ucom_stop_read = &umcs7840_stop_read,
+
+	.ucom_start_write = &umcs7840_start_write,
+	.ucom_stop_write = &umcs7840_stop_write,
+
+	.ucom_poll = &umcs7840_poll,
+};
+
+static const struct usb_device_id umcs7840_devs[] = {
+	{USB_VPI(USB_VENDOR_MOSCHIP, USB_PRODUCT_MOSCHIP_MCS7820, 0)},
+	{USB_VPI(USB_VENDOR_MOSCHIP, USB_PRODUCT_MOSCHIP_MCS7840, 0)},
+};
+
+static device_method_t umcs7840_methods[] = {
+	DEVMETHOD(device_probe, umcs7840_probe),
+	DEVMETHOD(device_attach, umcs7840_attach),
+	DEVMETHOD(device_detach, umcs7840_detach),
+	{0, 0}
+};
+
+static devclass_t umcs7840_devclass;
+
+static driver_t umcs7840_driver = {
+	.name = "umcs7840",
+	.methods = umcs7840_methods,
+	.size = sizeof(struct umcs7840_softc),
+};
+
+DRIVER_MODULE(umcs7840, uhub, umcs7840_driver, umcs7840_devclass, 0, 0);
+MODULE_DEPEND(umcs7840, ucom, 1, 1, 1);
+MODULE_DEPEND(umcs7840, usb, 1, 1, 1);
+MODULE_VERSION(umcs7840, UMCS7840_MODVER);
+
+static int
+umcs7840_probe(device_t dev)
+{
+	struct usb_attach_arg *uaa = device_get_ivars(dev);
+
+	if (uaa->usb_mode != USB_MODE_HOST)
+		return (ENXIO);
+	if (uaa->info.bConfigIndex != MCS7840_CONFIG_INDEX)
+		return (ENXIO);
+	if (uaa->info.bIfaceIndex != MCS7840_IFACE_INDEX)
+		return (ENXIO);
+	return (usbd_lookup_id_by_uaa(umcs7840_devs, sizeof(umcs7840_devs), uaa));
+}
+
+static int
+umcs7840_attach(device_t dev)
+{
+	struct usb_config umcs7840_config_tmp[UMCS7840_N_TRANSFERS];
+	struct usb_attach_arg *uaa = device_get_ivars(dev);
+	struct umcs7840_softc *sc = device_get_softc(dev);
+
+	uint8_t iface_index = MCS7840_IFACE_INDEX;
+	int error;
+	int subunit;
+	int n;
+	uint8_t data;
+
+	for (n = 0; n < UMCS7840_N_TRANSFERS; ++n)
+		umcs7840_config_tmp[n] = umcs7840_bulk_config_data[n];
+
+	device_set_usb_desc(dev);
+	mtx_init(&sc->sc_mtx, "umcs7840", NULL, MTX_DEF);
+
+	sc->sc_dev = dev;
+	sc->sc_udev = uaa->device;
+
+	/*
+	 * Get number of ports
+	 * Documentation (full datasheet) says, that number of ports is
+	 * set as MCS7840_DEV_MODE_SELECT24S bit in MODE R/Only
+	 * register. But vendor driver uses these undocumented
+	 * register & bit.
+	 *
+	 * Experiments show, that MODE register can have `0'
+	 * (4 ports) bit on 2-port device, so use vendor driver's way.
+	 *
+	 * Also, see notes in header file for these constants.
+	 */
+	umcs7840_get_reg_sync(sc, MCS7840_DEV_REG_GPIO, &data);
+	if (data & MCS7840_DEV_GPIO_4PORTS) {
+		sc->sc_numports = 4;
+		/* Store physical port numbers in sc_portno */
+		sc->sc_ucom[0].sc_portno = 0;
+		sc->sc_ucom[1].sc_portno = 1;
+		sc->sc_ucom[2].sc_portno = 2;
+		sc->sc_ucom[3].sc_portno = 3;
+	} else {
+		sc->sc_numports = 2;
+		/* Store physical port numbers in sc_portno */
+		sc->sc_ucom[0].sc_portno = 0;
+		sc->sc_ucom[1].sc_portno = 2;	/* '1' is skipped */
+	}
+	device_printf(dev, "Chip mcs%04x, found %d active ports\n", uaa->info.idProduct, sc->sc_numports);
+	if (!umcs7840_get_reg_sync(sc, MCS7840_DEV_REG_MODE, &data)) {
+		device_printf(dev, "On-die confguration: RST: active %s, HRD: %s, PLL: %s, POR: %s, Ports: %s, EEPROM write %s, IrDA is %savailable\n",
+		    (data & MCS7840_DEV_MODE_RESET) ? "low" : "high",
+		    (data & MCS7840_DEV_MODE_SER_PRSNT) ? "yes" : "no",
+		    (data & MCS7840_DEV_MODE_PLLBYPASS) ? "bypassed" : "avail",
+		    (data & MCS7840_DEV_MODE_PORBYPASS) ? "bypassed" : "avail",
+		    (data & MCS7840_DEV_MODE_SELECT24S) ? "2" : "4",
+		    (data & MCS7840_DEV_MODE_EEPROMWR) ? "enabled" : "disabled",
+		    (data & MCS7840_DEV_MODE_IRDA) ? "" : "not ");
+	}
+	/* Setup all transfers */
+	for (subunit = 0; subunit < sc->sc_numports; ++subunit) {
+		for (n = 0; n < UMCS7840_N_TRANSFERS; ++n) {
+			/* Set endpoint address */
+			umcs7840_config_tmp[n].endpoint = umcs7840_bulk_config_data[n].endpoint + 2 * sc->sc_ucom[subunit].sc_portno;
+			umcs7840_config_tmp[n].callback = umcs7840_rw_callbacks[subunit][n];
+		}
+		error = usbd_transfer_setup(uaa->device,
+		    &iface_index, sc->sc_ports[sc->sc_ucom[subunit].sc_portno].sc_xfer, umcs7840_config_tmp,
+		    UMCS7840_N_TRANSFERS, sc, &sc->sc_mtx);
+		if (error) {
+			device_printf(dev, "allocating USB transfers failed for subunit %d of %d\n",
+			    subunit + 1, sc->sc_numports);
+			goto detach;
+		}
+	}
+	error = usbd_transfer_setup(uaa->device,
+	    &iface_index, &sc->sc_intr_xfer, umcs7840_intr_config_data,
+	    1, sc, &sc->sc_mtx);
+	if (error) {
+		device_printf(dev, "allocating USB transfers failed for interrupt\n");
+		goto detach;
+	}
+	/* clear stall at first run */
+	mtx_lock(&sc->sc_mtx);
+	for (subunit = 0; subunit < sc->sc_numports; ++subunit) {
+		usbd_xfer_set_stall(sc->sc_ports[sc->sc_ucom[subunit].sc_portno].sc_xfer[UMCS7840_BULK_RD_EP]);
+		usbd_xfer_set_stall(sc->sc_ports[sc->sc_ucom[subunit].sc_portno].sc_xfer[UMCS7840_BULK_WR_EP]);
+	}
+	mtx_unlock(&sc->sc_mtx);
+
+	error = ucom_attach(&sc->sc_super_ucom, sc->sc_ucom, sc->sc_numports, sc,
+	    &umcs7840_callback, &sc->sc_mtx);
+	if (error)
+		goto detach;
+
+	ucom_set_pnpinfo_usb(&sc->sc_super_ucom, dev);
+
+	return (0);
+
+detach:
+	umcs7840_detach(dev);
+	return (ENXIO);
+}
+
+static int
+umcs7840_detach(device_t dev)
+{
+	struct umcs7840_softc *sc = device_get_softc(dev);
+	int subunit;
+
+	ucom_detach(&sc->sc_super_ucom, sc->sc_ucom);
+
+	for (subunit = 0; subunit < sc->sc_numports; ++subunit)
+		usbd_transfer_unsetup(sc->sc_ports[sc->sc_ucom[subunit].sc_portno].sc_xfer, UMCS7840_N_TRANSFERS);
+	usbd_transfer_unsetup(&sc->sc_intr_xfer, 1);
+
+	mtx_destroy(&sc->sc_mtx);
+	return (0);
+}
+
+static void
+umcs7840_cfg_open(struct ucom_softc *ucom)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint16_t pn = ucom->sc_portno;
+	uint8_t data;
+
+	/* If it very first open, finish global configuration */
+	if (!sc->sc_driver_done) {
+		/*
+		 * USB enumeration is finished, pass internal memory to FIFOs
+		 * If it is done in the end of "attach", kernel panics.
+		 */
+		if (umcs7840_get_reg_sync(sc, MCS7840_DEV_REG_CONTROL1, &data))
+			return;
+		data |= MCS7840_DEV_CONTROL1_DRIVER_DONE;
+		if (umcs7840_set_reg_sync(sc, MCS7840_DEV_REG_CONTROL1, data))
+			return;
+		sc->sc_driver_done = 1;
+	}
+	/* Toggle reset bit on-off */
+	if (umcs7840_get_reg_sync(sc, umcs7840_port_registers[pn].reg_sp, &data))
+		return;
+	data |= MCS7840_DEV_SPx_UART_RESET;
+	if (umcs7840_set_reg_sync(sc, umcs7840_port_registers[pn].reg_sp, data))
+		return;
+	data &= ~MCS7840_DEV_SPx_UART_RESET;
+	if (umcs7840_set_reg_sync(sc, umcs7840_port_registers[pn].reg_sp, data))
+		return;
+
+	/* Set RS-232 mode */
+	if (umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_SCRATCHPAD, MCS7840_UART_SCRATCHPAD_RS232))
+		return;
+
+	/* Disable RX on time of initialization */
+	if (umcs7840_get_reg_sync(sc, umcs7840_port_registers[pn].reg_control, &data))
+		return;
+	data |= MCS7840_DEV_CONTROLx_RX_DISABLE;
+	if (umcs7840_set_reg_sync(sc, umcs7840_port_registers[pn].reg_control, data))
+		return;
+
+	/* Disable all interrupts */
+	if (umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_IER, 0))
+		return;
+
+	/* Reset FIFO -- documented */
+	if (umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_FCR, 0))
+		return;
+	if (umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_FCR,
+	    MCS7840_UART_FCR_ENABLE | MCS7840_UART_FCR_FLUSHRHR |
+	    MCS7840_UART_FCR_FLUSHTHR | MCS7840_UART_FCR_RTL_1_14))
+		return;
+
+	/* Set 8 bit, no parity, 1 stop bit -- documented */
+	sc->sc_ports[pn].sc_lcr = MCS7840_UART_LCR_DATALEN8 | MCS7840_UART_LCR_STOPB1;
+	if (umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_LCR, sc->sc_ports[pn].sc_lcr))
+		return;
+
+	/*
+	 * Enable DTR/RTS on modem control, enable modem interrupts --
+	 * documented
+	 */
+	sc->sc_ports[pn].sc_mcr = MCS7840_UART_MCR_DTR | MCS7840_UART_MCR_RTS | MCS7840_UART_MCR_IE;
+	if (umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_MCR, sc->sc_ports[pn].sc_mcr))
+		return;
+
+	/* Clearing Bulkin and Bulkout FIFO */
+	if (umcs7840_get_reg_sync(sc, umcs7840_port_registers[pn].reg_sp, &data))
+		return;
+	data |= MCS7840_DEV_SPx_RESET_OUT_FIFO | MCS7840_DEV_SPx_RESET_IN_FIFO;
+	if (umcs7840_set_reg_sync(sc, umcs7840_port_registers[pn].reg_sp, data))
+		return;
+	data &= ~(MCS7840_DEV_SPx_RESET_OUT_FIFO | MCS7840_DEV_SPx_RESET_IN_FIFO);
+	if (umcs7840_set_reg_sync(sc, umcs7840_port_registers[pn].reg_sp, data))
+		return;
+
+	/* Set speed 9600 */
+	if (umcs7840_set_baudrate(sc, pn, 9600))
+		return;
+
+
+	/* Finally enable all interrupts -- documented */
+	/*
+	 * Copied from vendor driver, I don't know why we should read LCR
+	 * here
+	 */
+	if (umcs7840_get_UART_reg_sync(sc, pn, MCS7840_UART_REG_LCR, &sc->sc_ports[pn].sc_lcr))
+		return;
+	if (umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_IER,
+	    MCS7840_UART_IER_RXSTAT | MCS7840_UART_IER_MODEM))
+		return;
+
+	/* Enable RX */
+	if (umcs7840_get_reg_sync(sc, umcs7840_port_registers[pn].reg_control, &data))
+		return;
+	data &= ~MCS7840_DEV_CONTROLx_RX_DISABLE;
+	if (umcs7840_set_reg_sync(sc, umcs7840_port_registers[pn].reg_control, data))
+		return;
+
+	/* Read LSR & MSR */
+	if (umcs7840_get_UART_reg_sync(sc, pn, MCS7840_UART_REG_LSR, &sc->sc_ports[pn].sc_lsr))
+		return;
+	if (umcs7840_get_UART_reg_sync(sc, pn, MCS7840_UART_REG_MSR, &sc->sc_ports[pn].sc_msr))
+		return;
+	DPRINTF("Port %d has been opened, LSR=%02x MSR=%02x\n", pn, sc->sc_ports[pn].sc_lsr, sc->sc_ports[pn].sc_msr);
+}
+
+static void
+umcs7840_cfg_close(struct ucom_softc *ucom)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint16_t pn = ucom->sc_portno;
+	uint8_t data;
+
+	umcs7840_stop_read(ucom);
+	umcs7840_stop_write(ucom);
+
+	umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_MCR, 0);
+	umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_IER, 0);
+
+	/* Disable RX */
+	if (umcs7840_get_reg_sync(sc, umcs7840_port_registers[pn].reg_control, &data))
+		return;
+	data |= MCS7840_DEV_CONTROLx_RX_DISABLE;
+	if (umcs7840_set_reg_sync(sc, umcs7840_port_registers[pn].reg_control, data))
+		return;
+	DPRINTF("Port %d has been closed\n", pn);
+}
+
+static void
+umcs7840_cfg_set_dtr(struct ucom_softc *ucom, uint8_t onoff)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint8_t pn = ucom->sc_portno;
+
+	if (onoff)
+		sc->sc_ports[pn].sc_mcr |= MCS7840_UART_MCR_DTR;
+	else
+		sc->sc_ports[pn].sc_mcr &= ~MCS7840_UART_MCR_DTR;
+
+	umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_MCR, sc->sc_ports[pn].sc_mcr);
+	DPRINTF("Port %d DTR set to: %s\n", pn, onoff ? "on" : "off");
+}
+
+static void
+umcs7840_cfg_set_rts(struct ucom_softc *ucom, uint8_t onoff)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint8_t pn = ucom->sc_portno;
+
+	if (onoff)
+		sc->sc_ports[pn].sc_mcr |= MCS7840_UART_MCR_RTS;
+	else
+		sc->sc_ports[pn].sc_mcr &= ~MCS7840_UART_MCR_RTS;
+
+	umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_MCR, sc->sc_ports[pn].sc_mcr);
+	DPRINTF("Port %d RTS set to: %s\n", pn, onoff ? "on" : "off");
+}
+
+static void
+umcs7840_cfg_set_break(struct ucom_softc *ucom, uint8_t onoff)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint8_t pn = ucom->sc_portno;
+
+	if (onoff)
+		sc->sc_ports[pn].sc_lcr |= MCS7840_UART_LCR_BREAK;
+	else
+		sc->sc_ports[pn].sc_lcr &= ~MCS7840_UART_LCR_BREAK;
+
+	umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_LCR, sc->sc_ports[pn].sc_lcr);
+	DPRINTF("Port %d BREAK set to: %s\n", pn, onoff ? "on" : "off");
+}
+
+
+static void
+umcs7840_cfg_param(struct ucom_softc *ucom, struct termios *t)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint8_t pn = ucom->sc_portno;
+	uint8_t lcr = sc->sc_ports[pn].sc_lcr;
+	uint8_t mcr = sc->sc_ports[pn].sc_mcr;
+
+	DPRINTF("Port %d config:\n", pn);
+	if (t->c_cflag & CSTOPB) {
+		DPRINTF("  2 stop bits\n");
+		lcr |= MCS7840_UART_LCR_STOPB2;
+	} else {
+		lcr |= MCS7840_UART_LCR_STOPB1;
+		DPRINTF("  1 stop bit\n");
+	}
+
+	lcr &= ~MCS7840_UART_LCR_PARITYMASK;
+	if (t->c_cflag & PARENB) {
+		lcr |= MCS7840_UART_LCR_PARITYON;
+		if (t->c_cflag & PARODD) {
+			lcr = MCS7840_UART_LCR_PARITYODD;
+			DPRINTF("  parity on - odd\n");
+		} else {
+			lcr = MCS7840_UART_LCR_PARITYEVEN;
+			DPRINTF("  parity on - even\n");
+		}
+	} else {
+		lcr &= ~MCS7840_UART_LCR_PARITYON;
+		DPRINTF("  parity off\n");
+	}
+
+	lcr &= ~MCS7840_UART_LCR_DATALENMASK;
+	switch (t->c_cflag & CSIZE) {
+	case CS5:
+		lcr |= MCS7840_UART_LCR_DATALEN5;
+		DPRINTF("  5 bit\n");
+		break;
+	case CS6:
+		lcr |= MCS7840_UART_LCR_DATALEN6;
+		DPRINTF("  6 bit\n");
+		break;
+	case CS7:
+		lcr |= MCS7840_UART_LCR_DATALEN7;
+		DPRINTF("  7 bit\n");
+		break;
+	case CS8:
+		lcr |= MCS7840_UART_LCR_DATALEN8;
+		DPRINTF("  8 bit\n");
+		break;
+	}
+
+	if (t->c_cflag & CRTSCTS) {
+		mcr |= MCS7840_UART_MCR_CTSRTS;
+		DPRINTF("  CTS/RTS\n");
+	} else
+		mcr &= ~MCS7840_UART_MCR_CTSRTS;
+
+	if (t->c_cflag & (CDTR_IFLOW | CDSR_OFLOW)) {
+		mcr |= MCS7840_UART_MCR_DTRDSR;
+		DPRINTF("  DTR/DSR\n");
+	} else
+		mcr &= ~MCS7840_UART_MCR_DTRDSR;
+
+	sc->sc_ports[pn].sc_lcr = lcr;
+	umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_LCR, sc->sc_ports[pn].sc_lcr);
+	DPRINTF("Port %d LCR=%02x\n", pn, sc->sc_ports[pn].sc_lcr);
+
+	sc->sc_ports[pn].sc_mcr = mcr;
+	umcs7840_set_UART_reg_sync(sc, pn, MCS7840_UART_REG_MCR, sc->sc_ports[pn].sc_mcr);
+	DPRINTF("Port %d MCR=%02x\n", pn, sc->sc_ports[pn].sc_mcr);
+
+	umcs7840_set_baudrate(sc, pn, t->c_ospeed);
+}
+
+
+static int
+umcs7840_pre_param(struct ucom_softc *ucom, struct termios *t)
+{
+	uint8_t clk;
+	uint16_t divisor;
+
+	if (umcs7840_calc_baudrate(t->c_ospeed, &divisor, &clk) || !divisor)
+		return (EINVAL);
+	return (0);
+}
+
+static void
+umcs7840_start_read(struct ucom_softc *ucom)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint8_t pn = ucom->sc_portno;
+
+	/* Start interrupt transfer */
+	usbd_transfer_start(sc->sc_intr_xfer);
+
+	/* Start read transfer */
+	usbd_transfer_start(sc->sc_ports[pn].sc_xfer[UMCS7840_BULK_RD_EP]);
+}
+
+static void
+umcs7840_stop_read(struct ucom_softc *ucom)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint8_t pn = ucom->sc_portno;
+
+	/* Stop read transfer */
+	usbd_transfer_stop(sc->sc_ports[pn].sc_xfer[UMCS7840_BULK_RD_EP]);
+}
+
+static void
+umcs7840_start_write(struct ucom_softc *ucom)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint8_t pn = ucom->sc_portno;
+
+	/* Start interrupt transfer */
+	usbd_transfer_start(sc->sc_intr_xfer);
+
+	/* Start write transfer */
+	usbd_transfer_start(sc->sc_ports[pn].sc_xfer[UMCS7840_BULK_WR_EP]);
+}
+
+static void
+umcs7840_stop_write(struct ucom_softc *ucom)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+	uint8_t pn = ucom->sc_portno;
+
+	/* Stop write transfer */
+	usbd_transfer_stop(sc->sc_ports[pn].sc_xfer[UMCS7840_BULK_WR_EP]);
+}
+
+static void
+umcs7840_cfg_get_status(struct ucom_softc *ucom, uint8_t *lsr, uint8_t *msr)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+
+	*lsr = sc->sc_ports[ucom->sc_portno].sc_lsr;
+	*msr = sc->sc_ports[ucom->sc_portno].sc_msr;
+	DPRINTF("Port %d status: LSR=%02x MSR=%02x\n", ucom->sc_portno, *lsr, *msr);
+}
+
+static void
+umcs7840_intr_callback(struct usb_xfer *xfer, usb_error_t error)
+{
+	struct umcs7840_softc *sc = usbd_xfer_softc(xfer);
+	struct usb_page_cache *pc;
+	uint8_t buf[13];
+	int actlen;
+	int subunit;
+
+	usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
+
+	switch (USB_GET_STATE(xfer)) {
+	case USB_ST_TRANSFERRED:
+		if (actlen == 5 || actlen == 13) {
+			pc = usbd_xfer_get_frame(xfer, 0);
+			usbd_copy_out(pc, 0, buf, actlen);
+			/* Check status of all ports */
+			for (subunit = 0; subunit < sc->sc_numports; ++subunit) {
+				uint8_t pn = sc->sc_ucom[subunit].sc_portno;
+
+				if (buf[pn] & MCS7840_UART_ISR_NOPENDING)
+					continue;
+				DPRINTF("Port %d has pending interrupt: %02x (FIFO: %02x)\n", pn, buf[pn] & MCS7840_UART_ISR_INTMASK, buf[pn] & (~MCS7840_UART_ISR_INTMASK));
+				switch (buf[pn] & MCS7840_UART_ISR_INTMASK) {
+				case MCS7840_UART_ISR_RXERR:
+				case MCS7840_UART_ISR_RXHASDATA:
+				case MCS7840_UART_ISR_RXTIMEOUT:
+					/* Read new LSR */
+					if (umcs7840_get_UART_reg_sync(sc, pn, MCS7840_UART_REG_LSR, &sc->sc_ports[pn].sc_lsr))
+						break;	/* Inner switch */
+					ucom_status_change(&sc->sc_ucom[subunit]);
+					/* Inner switch */
+					break;
+				case MCS7840_UART_ISR_TXEMPTY:
+					/* Do nothing */
+					break;	/* Inner switch */
+				case MCS7840_UART_ISR_MSCHANGE:
+					/* Read new MSR */
+					if (umcs7840_get_UART_reg_sync(sc, pn, MCS7840_UART_REG_MSR, &sc->sc_ports[pn].sc_msr))
+						break;	/* Inner switch */
+					DPRINTF("Port %d: new MSR %02x\n", pn, sc->sc_ports[pn].sc_msr);
+					ucom_status_change(&sc->sc_ucom[subunit]);
+					break;
+				}
+			}
+		} else
+			device_printf(sc->sc_dev, "Invalid interrupt data length %d", actlen);
+		/* FALLTHROUGH */
+	case USB_ST_SETUP:
+tr_setup:
+		usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
+		usbd_transfer_submit(xfer);
+		return;
+
+	default:			/* Error */
+		if (error != USB_ERR_CANCELLED) {
+			/* try to clear stall first */
+			usbd_xfer_set_stall(xfer);
+			goto tr_setup;
+		}
+		return;
+	}
+}
+
+static void
+umcs7840_read_callback1(struct usb_xfer *xfer, usb_error_t error)
+{
+	umcs7840_read_callbackN(xfer, error, 0);
+}
+
+static void
+umcs7840_read_callback2(struct usb_xfer *xfer, usb_error_t error)
+{
+	umcs7840_read_callbackN(xfer, error, 1);
+}
+static void
+umcs7840_read_callback3(struct usb_xfer *xfer, usb_error_t error)
+{
+	umcs7840_read_callbackN(xfer, error, 2);
+}
+
+static void
+umcs7840_read_callback4(struct usb_xfer *xfer, usb_error_t error)
+{
+	umcs7840_read_callbackN(xfer, error, 3);
+}
+
+static void
+umcs7840_read_callbackN(struct usb_xfer *xfer, usb_error_t error, uint8_t subunit)
+{
+	struct umcs7840_softc *sc = usbd_xfer_softc(xfer);
+	struct ucom_softc *ucom = &sc->sc_ucom[subunit];
+	struct usb_page_cache *pc;
+	int actlen;
+
+	usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
+
+	DPRINTF("Port %d read, state = %d, data length = %d\n", ucom->sc_portno, USB_GET_STATE(xfer), actlen);
+
+	switch (USB_GET_STATE(xfer)) {
+	case USB_ST_TRANSFERRED:
+		pc = usbd_xfer_get_frame(xfer, 0);
+		ucom_put_data(ucom, pc, 0, actlen);
+		/* FALLTHROUGH */
+	case USB_ST_SETUP:
+tr_setup:
+		usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
+		usbd_transfer_submit(xfer);
+		return;
+
+	default:			/* Error */
+		if (error != USB_ERR_CANCELLED) {
+			/* try to clear stall first */
+			usbd_xfer_set_stall(xfer);
+			goto tr_setup;
+		}
+		return;
+	}
+}
+
+static void
+umcs7840_write_callback1(struct usb_xfer *xfer, usb_error_t error)
+{
+	umcs7840_write_callbackN(xfer, error, 0);
+}
+
+static void
+umcs7840_write_callback2(struct usb_xfer *xfer, usb_error_t error)
+{
+	umcs7840_write_callbackN(xfer, error, 1);
+}
+
+static void
+umcs7840_write_callback3(struct usb_xfer *xfer, usb_error_t error)
+{
+	umcs7840_write_callbackN(xfer, error, 2);
+}
+
+static void
+umcs7840_write_callback4(struct usb_xfer *xfer, usb_error_t error)
+{
+	umcs7840_write_callbackN(xfer, error, 3);
+}
+
+static void
+umcs7840_write_callbackN(struct usb_xfer *xfer, usb_error_t error, uint8_t subunit)
+{
+	struct umcs7840_softc *sc = usbd_xfer_softc(xfer);
+	struct ucom_softc *ucom = &sc->sc_ucom[subunit];
+	struct usb_page_cache *pc;
+	uint32_t actlen;
+
+	DPRINTF("Port %d write, state = %d\n", ucom->sc_portno, USB_GET_STATE(xfer));
+
+	switch (USB_GET_STATE(xfer)) {
+	case USB_ST_SETUP:
+	case USB_ST_TRANSFERRED:
+tr_setup:
+		pc = usbd_xfer_get_frame(xfer, 0);
+		if (ucom_get_data(ucom, pc, 0, usbd_xfer_max_len(xfer), &actlen)) {
+			DPRINTF("Port %d write, has %d bytes\n", ucom->sc_portno, actlen);
+			usbd_xfer_set_frame_len(xfer, 0, actlen);
+			usbd_transfer_submit(xfer);
+		}
+		return;
+
+	default:			/* Error */
+		if (error != USB_ERR_CANCELLED) {
+			/* try to clear stall first */
+			usbd_xfer_set_stall(xfer);
+			goto tr_setup;
+		}
+		return;
+	}
+}
+
+static void
+umcs7840_poll(struct ucom_softc *ucom)
+{
+	struct umcs7840_softc *sc = ucom->sc_parent;
+
+	DPRINTF("Port %d poll\n", ucom->sc_portno);
+	usbd_transfer_poll(sc->sc_ports[ucom->sc_portno].sc_xfer, UMCS7840_N_TRANSFERS);
+	usbd_transfer_poll(&sc->sc_intr_xfer, 1);
+}
+
+static usb_error_t
+umcs7840_get_reg_sync(struct umcs7840_softc *sc, uint8_t reg, uint8_t *data)
+{
+	struct usb_device_request req;
+	usb_error_t err;
+	uint16_t len;
+
+	req.bmRequestType = UT_READ_VENDOR_DEVICE;
+	req.bRequest = MCS7840_RDREQ;
+	USETW(req.wValue, 0);
+	USETW(req.wIndex, reg);
+	USETW(req.wLength, UMCS7840_READ_LENGTH);
+
+	err = usbd_do_request_proc(sc->sc_udev, &sc->sc_super_ucom.sc_tq, &req, (void *)data, 0, &len, UMCS7840_CTRL_TIMEOUT);
+	if (err == USB_ERR_NORMAL_COMPLETION && len != 1) {
+		device_printf(sc->sc_dev, "Reading register %d failed: invalid length %d\n", reg, len);
+		return (USB_ERR_INVAL);
+	} else if (err)
+		device_printf(sc->sc_dev, "Reading register %d failed: %s\n", reg, usbd_errstr(err));
+	return (err);
+}
+
+static usb_error_t
+umcs7840_set_reg_sync(struct umcs7840_softc *sc, uint8_t reg, uint8_t data)
+{
+	struct usb_device_request req;
+	usb_error_t err;
+
+	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
+	req.bRequest = MCS7840_WRREQ;
+	USETW(req.wValue, data);
+	USETW(req.wIndex, reg);
+	USETW(req.wLength, 0);
+
+	err = usbd_do_request_proc(sc->sc_udev, &sc->sc_super_ucom.sc_tq, &req, NULL, 0, NULL, UMCS7840_CTRL_TIMEOUT);
+	if (err)
+		device_printf(sc->sc_dev, "Writing register %d failed: %s\n", reg, usbd_errstr(err));
+
+	return (err);
+}
+
+static usb_error_t
+umcs7840_get_UART_reg_sync(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t *data)
+{
+	struct usb_device_request req;
+	uint16_t wVal;
+	usb_error_t err;
+	uint16_t len;
+
+	/* portno is port number */
+	wVal = ((uint16_t)(portno + 1)) << 8;
+
+	req.bmRequestType = UT_READ_VENDOR_DEVICE;
+	req.bRequest = MCS7840_RDREQ;
+	USETW(req.wValue, wVal);
+	USETW(req.wIndex, reg);
+	USETW(req.wLength, UMCS7840_READ_LENGTH);
+
+	err = usbd_do_request_proc(sc->sc_udev, &sc->sc_super_ucom.sc_tq, &req, (void *)data, 0, &len, UMCS7840_CTRL_TIMEOUT);
+	if (err == USB_ERR_NORMAL_COMPLETION && len != 1) {
+		device_printf(sc->sc_dev, "Reading UART%d register %d failed: invalid length %d\n", portno, reg, len);
+		return (USB_ERR_INVAL);
+	} else if (err)
+		device_printf(sc->sc_dev, "Reading UART%d register %d failed: %s\n", portno, reg, usbd_errstr(err));
+	return (err);
+}
+
+static usb_error_t
+umcs7840_set_UART_reg_sync(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t data)
+{
+	struct usb_device_request req;
+	usb_error_t err;
+	uint16_t wVal;
+
+	/* portno is port number */
+	wVal = ((uint16_t)(portno + 1)) << 8 | data;
+
+	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
+	req.bRequest = MCS7840_WRREQ;
+	USETW(req.wValue, wVal);
+	USETW(req.wIndex, reg);
+	USETW(req.wLength, 0);
+
+	err = usbd_do_request_proc(sc->sc_udev, &sc->sc_super_ucom.sc_tq, &req, NULL, 0, NULL, UMCS7840_CTRL_TIMEOUT);
+	if (err)
+		device_printf(sc->sc_dev, "Writing UART%d register %d failed: %s\n", portno, reg, usbd_errstr(err));
+	return (err);
+}
+
+static usb_error_t
+umcs7840_set_baudrate(struct umcs7840_softc *sc, uint8_t portno, uint32_t rate)
+{
+	usb_error_t err;
+	uint16_t divisor;
+	uint8_t clk;
+	uint8_t data;
+
+	if (umcs7840_calc_baudrate(rate, &divisor, &clk)) {
+		DPRINTF("Port %d bad speed: %d\n", portno, rate);
+		return (-1);
+	}
+	if (divisor == 0 || (clk & MCS7840_DEV_SPx_CLOCK_MASK) != clk) {
+		DPRINTF("Port %d bad speed calculation: %d\n", portno, rate);
+		return (-1);
+	}
+	DPRINTF("Port %d set speed: %d (%02x / %d)\n", portno, rate, clk, divisor);
+
+	/* Set clock source for standard BAUD frequences */
+	err = umcs7840_get_reg_sync(sc, umcs7840_port_registers[portno].reg_sp, &data);
+	if (err)
+		return (err);
+	data &= MCS7840_DEV_SPx_CLOCK_MASK;
+	data |= clk;
+	err = umcs7840_set_reg_sync(sc, umcs7840_port_registers[portno].reg_sp, data);
+	if (err)
+		return (err);
+
+	/* Set divider */
+	sc->sc_ports[portno].sc_lcr |= MCS7840_UART_LCR_DIVISORS;
+	err = umcs7840_set_UART_reg_sync(sc, portno, MCS7840_UART_REG_LCR, sc->sc_ports[portno].sc_lcr);
+	if (err)
+		return (err);
+
+	err = umcs7840_set_UART_reg_sync(sc, portno, MCS7840_UART_REG_DLL, (uint8_t)(divisor & 0xff));
+	if (err)
+		return (err);
+	err = umcs7840_set_UART_reg_sync(sc, portno, MCS7840_UART_REG_DLM, (uint8_t)((divisor >> 8) & 0xff));
+	if (err)
+		return (err);
+
+	/* Turn off access to DLL/DLM registers of UART */
+	sc->sc_ports[portno].sc_lcr &= ~MCS7840_UART_LCR_DIVISORS;
+	err = umcs7840_set_UART_reg_sync(sc, portno, MCS7840_UART_REG_LCR, sc->sc_ports[portno].sc_lcr);
+	if (err)
+		return (err);
+	return (0);
+}
+
+/* Maximum speeds for standard frequences, when PLL is not used */
+static const uint32_t umcs7840_baudrate_divisors[] = {0, 115200, 230400, 403200, 460800, 806400, 921600, 1572864, 3145728,};
+static const uint8_t umcs7840_baudrate_divisors_len = sizeof(umcs7840_baudrate_divisors) / sizeof(umcs7840_baudrate_divisors[0]);
+
+static usb_error_t
+umcs7840_calc_baudrate(uint32_t rate, uint16_t *divisor, uint8_t *clk)
+{
+	uint8_t i = 0;
+
+	if (rate > umcs7840_baudrate_divisors[umcs7840_baudrate_divisors_len - 1])
+		return (-1);
+
+	for (i = 0; i < umcs7840_baudrate_divisors_len - 1 &&
+	    !(rate > umcs7840_baudrate_divisors[i] && rate <= umcs7840_baudrate_divisors[i + 1]); ++i);
+	*divisor = umcs7840_baudrate_divisors[i + 1] / rate;
+	/* 0x00 .. 0x70 */
+	*clk = i << MCS7840_DEV_SPx_CLOCK_SHIFT;
+	return (0);
+}
diff --git a/sys/dev/usb/serial/umcs7840.h b/sys/dev/usb/serial/umcs7840.h
new file mode 100644
index 000000000000..310b4af65f3a
--- /dev/null
+++ b/sys/dev/usb/serial/umcs7840.h
@@ -0,0 +1,644 @@
+/* $FreeBSD$ */
+/*-
+ * Copyright (c) 2010 Lev Serebryakov <lev@FreeBSD.org>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#ifndef _UMCS7840_H_
+#define	_UMCS7840_H_
+
+#define	UMCS7840_MAX_PORTS	4
+
+#define	UMCS7840_READ_LENGTH	1	/* bytes */
+#define	UMCS7840_CTRL_TIMEOUT	500	/* ms */
+
+/* Read/Wrtire registers vendor commands */
+#define	MCS7840_RDREQ		0x0d
+#define	MCS7840_WRREQ		0x0e
+
+/* Read/Wrtie EEPROM values */
+#define	MCS7840_EEPROM_RW_WVALUE	0x0900
+
+/*
+ *   All these registers are documented only in full datasheet,
+ * which can be requested from MosChip tech support.
+ */
+#define	MCS7840_DEV_REG_SP1		0x00	/* Options for for UART 1, R/W */
+#define	MCS7840_DEV_REG_CONTROL1	0x01	/* Control bits for UART 1,
+						 * R/W */
+#define	MCS7840_DEV_REG_PINPONGHIGH	0x02	/* High bits of ping-pong
+						 * register, R/W */
+#define	MCS7840_DEV_REG_PINPONGLOW	0x03	/* Low bits of ping-pong
+						 * register, R/W */
+/* DCRx_1 Registers goes here (see below, they are documented) */
+#define	MCS7840_DEV_REG_GPIO		0x07	/* GPIO_0 and GPIO_1 bits,
+						 * undocumented, see notes
+						 * below R/W */
+#define	MCS7840_DEV_REG_SP2		0x08	/* Options for for UART 2, R/W */
+#define	MCS7840_DEV_REG_CONTROL2	0x09	/* Control bits for UART 2,
+						 * R/W */
+#define	MCS7840_DEV_REG_SP3		0x0a	/* Options for for UART 3, R/W */
+#define	MCS7840_DEV_REG_CONTROL3	0x0b	/* Control bits for UART 3,
+						 * R/W */
+#define	MCS7840_DEV_REG_SP4		0x0c	/* Options for for UART 4, R/W */
+#define	MCS7840_DEV_REG_CONTROL4	0x0d	/* Control bits for UART 4,
+						 * R/W */
+#define	MCS7840_DEV_REG_PLL_DIV_M	0x0e	/* Pre-diviedr for PLL, R/W */
+#define	MCS7840_DEV_REG_UNKNOWN1	0x0f	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_PLL_DIV_N	0x10	/* Loop divider for PLL, R/W */
+#define	MCS7840_DEV_REG_CLOCK_MUX	0x12	/* PLL input clock & Interrupt
+						 * endpoint control, R/W */
+#define	MCS7840_DEV_REG_UNKNOWN2	0x11	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_CLOCK_SELECT12	0x13	/* Clock source for ports 1 &
+						 * 2, R/W */
+#define	MCS7840_DEV_REG_CLOCK_SELECT34	0x14	/* Clock source for ports 3 &
+						 * 4, R/W */
+#define	MCS7840_DEV_REG_UNKNOWN3	0x15	/* NOT MENTIONED AND NOT USED */
+/* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */
+#define	MCS7840_DEV_REG_UNKNOWN4	0x1f	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWN5	0x20	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWN6	0x21	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWN7	0x22	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWN8	0x23	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWN9	0x24	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWNA	0x25	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWNB	0x26	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWNC	0x27	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWND	0x28	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWNE	0x29	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_UNKNOWNF	0x2a	/* NOT MENTIONED AND NOT USED */
+#define	MCS7840_DEV_REG_MODE		0x2b	/* Hardware configuration,
+						 * R/Only */
+#define	MCS7840_DEV_REG_SP1_ICG		0x2c	/* Inter character gap
+						 * configuration for Port 1,
+						 * R/W */
+#define	MCS7840_DEV_REG_SP2_ICG		0x2d	/* Inter character gap
+						 * configuration for Port 2,
+						 * R/W */
+#define	MCS7840_DEV_REG_SP3_ICG		0x2e	/* Inter character gap
+						 * configuration for Port 3,
+						 * R/W */
+#define	MCS7840_DEV_REG_SP4_ICG		0x2f	/* Inter character gap
+						 * configuration for Port 4,
+						 * R/W */
+#define	MCS7840_DEV_REG_RX_SAMPLING12	0x30	/* RX sampling for ports 1 &
+						 * 2, R/W */
+#define	MCS7840_DEV_REG_RX_SAMPLING34	0x31	/* RX sampling for ports 3 &
+						 * 4, R/W */
+#define	MCS7840_DEV_REG_BI_FIFO_STAT1	0x32	/* Bulk-In FIFO Stat for Port
+						 * 1, contains number of
+						 * availiable bytes, R/Only */
+#define	MCS7840_DEV_REG_BO_FIFO_STAT1	0x33	/* Bulk-out FIFO Stat for Port
+						 * 1, contains number of
+						 * availiable bytes, R/Only */
+#define	MCS7840_DEV_REG_BI_FIFO_STAT2	0x34	/* Bulk-In FIFO Stat for Port
+						 * 2, contains number of
+						 * availiable bytes, R/Only */
+#define	MCS7840_DEV_REG_BO_FIFO_STAT2	0x35	/* Bulk-out FIFO Stat for Port
+						 * 2, contains number of
+						 * availiable bytes, R/Only */
+#define	MCS7840_DEV_REG_BI_FIFO_STAT3	0x36	/* Bulk-In FIFO Stat for Port
+						 * 3, contains number of
+						 * availiable bytes, R/Only */
+#define	MCS7840_DEV_REG_BO_FIFO_STAT3	0x37	/* Bulk-out FIFO Stat for Port
+						 * 3, contains number of
+						 * availiable bytes, R/Only */
+#define	MCS7840_DEV_REG_BI_FIFO_STAT4	0x38	/* Bulk-In FIFO Stat for Port
+						 * 4, contains number of
+						 * availiable bytes, R/Only */
+#define	MCS7840_DEV_REG_BO_FIFO_STAT4	0x39	/* Bulk-out FIFO Stat for Port
+						 * 4, contains number of
+						 * availiable bytes, R/Only */
+#define	MCS7840_DEV_REG_ZERO_PERIOD1	0x3a	/* Period between zero out
+						 * frames for Port 1, R/W */
+#define	MCS7840_DEV_REG_ZERO_PERIOD2	0x3b	/* Period between zero out
+						 * frames for Port 1, R/W */
+#define	MCS7840_DEV_REG_ZERO_PERIOD3	0x3c	/* Period between zero out
+						 * frames for Port 1, R/W */
+#define	MCS7840_DEV_REG_ZERO_PERIOD4	0x3d	/* Period between zero out
+						 * frames for Port 1, R/W */
+#define	MCS7840_DEV_REG_ZERO_ENABLE	0x3e	/* Enable/disable of zero out
+						 * frames, R/W */
+#define	MCS7840_DEV_REG_THR_VAL_LOW1	0x3f	/* Low 8 bits of threshhold
+						 * value for Bulk-Out for Port
+						 * 1, R/W */
+#define	MCS7840_DEV_REG_THR_VAL_HIGH1	0x40	/* High 1 bit of threshhold
+						 * value for Bulk-Out and
+						 * enable flag for Port 1, R/W */
+#define	MCS7840_DEV_REG_THR_VAL_LOW2	0x41	/* Low 8 bits of threshhold
+						 * value for Bulk-Out for Port
+						 * 2, R/W */
+#define	MCS7840_DEV_REG_THR_VAL_HIGH2	0x42	/* High 1 bit of threshhold
+						 * value for Bulk-Out and
+						 * enable flag for Port 2, R/W */
+#define	MCS7840_DEV_REG_THR_VAL_LOW3	0x43	/* Low 8 bits of threshhold
+						 * value for Bulk-Out for Port
+						 * 3, R/W */
+#define	MCS7840_DEV_REG_THR_VAL_HIGH3	0x44	/* High 1 bit of threshhold
+						 * value for Bulk-Out and
+						 * enable flag for Port 3, R/W */
+#define	MCS7840_DEV_REG_THR_VAL_LOW4	0x45	/* Low 8 bits of threshhold
+						 * value for Bulk-Out for Port
+						 * 4, R/W */
+#define	MCS7840_DEV_REG_THR_VAL_HIGH4	0x46	/* High 1 bit of threshhold
+						 * value for Bulk-Out and
+						 * enable flag for Port 4, R/W */
+
+/* Bits for SPx registers */
+#define	MCS7840_DEV_SPx_LOOP_PIPES	0x01	/* Loop Bulk-Out FIFO to the
+						 * Bulk-In FIFO, default = 0 */
+#define	MCS7840_DEV_SPx_SKIP_ERR_DATA	0x02	/* Drop data bytes from UART,
+						 * which were recevied with
+						 * errors, default = 0 */
+#define	MCS7840_DEV_SPx_RESET_OUT_FIFO	0x04	/* Reset Bulk-Out FIFO */
+#define	MCS7840_DEV_SPx_RESET_IN_FIFO	0x08	/* Reset Bulk-In FIFO */
+#define	MCS7840_DEV_SPx_CLOCK_MASK	0x70	/* Mask to extract Baud CLK
+						 * source */
+#define	MCS7840_DEV_SPx_CLOCK_X1	0x00	/* CLK =  1.8432Mhz, max speed
+						 * = 115200 bps, default */
+#define	MCS7840_DEV_SPx_CLOCK_X2	0x10	/* CLK =  3.6864Mhz, max speed
+						 * = 230400 bps */
+#define	MCS7840_DEV_SPx_CLOCK_X35	0x20	/* CLK =  6.4512Mhz, max speed
+						 * = 403200 bps */
+#define	MCS7840_DEV_SPx_CLOCK_X4	0x30	/* CLK =  7.3728Mhz, max speed
+						 * = 460800 bps */
+#define	MCS7840_DEV_SPx_CLOCK_X7	0x40	/* CLK = 12.9024Mhz, max speed
+						 * = 806400 bps */
+#define	MCS7840_DEV_SPx_CLOCK_X8	0x50	/* CLK = 14.7456Mhz, max speed
+						 * = 921600 bps */
+#define	MCS7840_DEV_SPx_CLOCK_24MHZ	0x60	/* CLK = 24.0000Mhz, max speed
+						 * = 1.5 Mbps */
+#define	MCS7840_DEV_SPx_CLOCK_48MHZ	0x70	/* CLK = 48.0000Mhz, max speed
+						 * = 3.0 Mbps */
+#define	MCS7840_DEV_SPx_CLOCK_SHIFT	4	/* Value 0..7 can be shifted
+						 * to get clock value */
+#define	MCS7840_DEV_SPx_UART_RESET	0x80	/* Reset UART */
+
+/* Bits for CONTROLx registers */
+#define	MCS7840_DEV_CONTROLx_HWFC		0x01	/* Enable hardware flow
+							 * control (when power
+							 * down? It is unclear
+							 * in documents),
+							 * default = 0 */
+#define	MCS7840_DEV_CONTROLx_UNUNSED1		0x02	/* Reserved */
+#define	MCS7840_DEV_CONTROLx_CTS_ENABLE		0x04	/* CTS changes are
+							 * translated to MSR,
+							 * default = 0 */
+#define	MCS7840_DEV_CONTROLx_UNUSED2		0x08	/* Reserved for ports
+							 * 2,3,4 */
+#define	MCS7840_DEV_CONTROL1_DRIVER_DONE	0x08	/* USB enumerating is
+							 * finished, USB
+							 * enumeration memory
+							 * can be used as FIFOs */
+#define	MCS7840_DEV_CONTROLx_RX_NEGATE		0x10	/* Negate RX input,
+							 * works for IrDA mode
+							 * only, default = 0 */
+#define	MCS7840_DEV_CONTROLx_RX_DISABLE		0x20	/* Disable RX logic,
+							 * works only for
+							 * RS-232/RS-485 mode,
+							 * default = 0 */
+#define	MCS7840_DEV_CONTROLx_FSM_CONTROL	0x40	/* Disable RX FSM when
+							 * TX is in progress,
+							 * works for IrDA mode
+							 * only, default = 0 */
+#define	MCS7840_DEV_CONTROLx_UNUSED3		0x80	/* Reserved */
+
+/*
+ * Bits for PINPONGx registers
+ * These registers control how often two input buffers
+ * for Bulk-In FIFOs are swapped. One of buffers is used
+ * for USB trnasfer, other for receiving data from UART.
+ * Exact meaning of 15 bit value in these registers is unknown
+ */
+#define	MCS7840_DEV_PINPONGHIGH_MULT	128	/* Only 7 bits in PINPONGLOW
+						 * register */
+#define	MCS7840_DEV_PINPONGLOW_BITS	7	/* Only 7 bits in PINPONGLOW
+						 * register */
+
+/*
+ *  THIS ONE IS UNDOCUMENTED IN FULL DATASHEET, but e-mail from tech support
+ * confirms, that it is register for GPIO_0 and GPIO_1 data input/output.
+ *  Chips has 2 GPIO, but first one (lower bit) MUST be used by device
+ * authors as "number of port" indicator, grounded (0) for two-port
+ * devices and pulled-up to 1 for 4-port devices.
+ */
+#define	MCS7840_DEV_GPIO_4PORTS		0x01	/* Device has 4 ports
+						 * configured */
+#define	MCS7840_DEV_GPIO_GPIO_0		0x01	/* The same as above */
+#define	MCS7840_DEV_GPIO_GPIO_1		0x02	/* GPIO_1 data */
+
+/*
+ * Constants for PLL dividers
+ * Ouptut frequency of PLL is:
+ *   Fout = (N/M) * Fin.
+ * Default PLL input frequency Fin is 12Mhz (on-chip).
+ */
+#define	MCS7840_DEV_PLL_DIV_M_BITS	6	/* Number of useful bits for M
+						 * divider */
+#define	MCS7840_DEV_PLL_DIV_M_MASK	0x3f	/* Mask for M divider */
+#define	MCS7840_DEV_PLL_DIV_M_MIN	1	/* Minimum value for M, 0 is
+						 * forbidden */
+#define	MCS7840_DEV_PLL_DIV_M_DEF	1	/* Default value for M */
+#define	MCS7840_DEV_PLL_DIV_M_MAX	63	/* Maximum value for M */
+#define	MCS7840_DEV_PLL_DIV_N_BITS	6	/* Number of useful bits for N
+						 * divider */
+#define	MCS7840_DEV_PLL_DIV_N_MASK	0x3f	/* Mask for N divider */
+#define	MCS7840_DEV_PLL_DIV_N_MIN	1	/* Minimum value for N, 0 is
+						 * forbidden */
+#define	MCS7840_DEV_PLL_DIV_N_DEF	8	/* Default value for N */
+#define	MCS7840_DEV_PLL_DIV_N_MAX	63	/* Maximum value for N */
+
+/* Bits for CLOCK_MUX register */
+#define	MCS7840_DEV_CLOCK_MUX_INPUTMASK	0x03	/* Mask to extract PLL clock
+						 * input */
+#define	MCS7840_DEV_CLOCK_MUX_IN12MHZ	0x00	/* 12Mhz PLL input, default */
+#define	MCS7840_DEV_CLOCK_MUX_INEXTRN	0x01	/* External (device-depended)
+						 * PLL input */
+#define	MCS7840_DEV_CLOCK_MUX_INRSV1	0x02	/* Reserved */
+#define	MCS7840_DEV_CLOCK_MUX_INRSV2	0x03	/* Reserved */
+#define	MCS7840_DEV_CLOCK_MUX_PLLHIGH	0x04	/* 0 = PLL Output is
+						 * 20MHz-100MHz (default), 1 =
+						 * 100MHz-300MHz range */
+#define	MCS7840_DEV_CLOCK_MUX_INTRFIFOS	0x08	/* Enable additional 8 bytes
+						 * fro Interrupt USB pipe with
+						 * USB FIFOs statuses, default
+						 * = 0 */
+#define	MCS7840_DEV_CLOCK_MUX_RESERVED1	0x10	/* Unused */
+#define	MCS7840_DEV_CLOCK_MUX_RESERVED2	0x20	/* Unused */
+#define	MCS7840_DEV_CLOCK_MUX_RESERVED3	0x40	/* Unused */
+#define	MCS7840_DEV_CLOCK_MUX_RESERVED4	0x80	/* Unused */
+
+/* Bits for CLOCK_SELECTxx registers	*/
+#define	MCS7840_DEV_CLOCK_SELECT1_MASK	0x07	/* Bits for port 1 in
+						 * CLOCK_SELECT12 */
+#define	MCS7840_DEV_CLOCK_SELECT1_SHIFT	0	/* Shift for port 1in
+						 * CLOCK_SELECT12 */
+#define	MCS7840_DEV_CLOCK_SELECT2_MASK	0x38	/* Bits for port 2 in
+						 * CLOCK_SELECT12 */
+#define	MCS7840_DEV_CLOCK_SELECT2_SHIFT	3	/* Shift for port 2 in
+						 * CLOCK_SELECT12 */
+#define	MCS7840_DEV_CLOCK_SELECT3_MASK	0x07	/* Bits for port 3 in
+						 * CLOCK_SELECT23 */
+#define	MCS7840_DEV_CLOCK_SELECT3_SHIFT	0	/* Shift for port 3 in
+						 * CLOCK_SELECT23 */
+#define	MCS7840_DEV_CLOCK_SELECT4_MASK	0x38	/* Bits for port 4 in
+						 * CLOCK_SELECT23 */
+#define	MCS7840_DEV_CLOCK_SELECT4_SHIFT	3	/* Shift for port 4 in
+						 * CLOCK_SELECT23 */
+#define	MCS7840_DEV_CLOCK_SELECT_STD	0x00	/* STANDARD baudrate derived
+						 * from 96Mhz, default for all
+						 * ports */
+#define	MCS7840_DEV_CLOCK_SELECT_30MHZ	0x01	/* 30Mhz */
+#define	MCS7840_DEV_CLOCK_SELECT_96MHZ	0x02	/* 96Mhz direct */
+#define	MCS7840_DEV_CLOCK_SELECT_120MHZ	0x03	/* 120Mhz */
+#define	MCS7840_DEV_CLOCK_SELECT_PLL	0x04	/* PLL output (see for M and N
+						 * dividers) */
+#define	MCS7840_DEV_CLOCK_SELECT_EXT	0x05	/* External clock input
+						 * (device-dependend) */
+#define	MCS7840_DEV_CLOCK_SELECT_RES1	0x06	/* Unused */
+#define	MCS7840_DEV_CLOCK_SELECT_RES2	0x07	/* Unused */
+
+/* Bits for MODE register */
+#define	MCS7840_DEV_MODE_RESERVED1	0x01	/* Unused */
+#define	MCS7840_DEV_MODE_RESET		0x02	/* 0: RESET = Active High
+						 * (default), 1: Reserved (?) */
+#define	MCS7840_DEV_MODE_SER_PRSNT	0x04	/* 0: Reserved, 1: Do not use
+						 * hardocded values (default)
+						 * (?) */
+#define	MCS7840_DEV_MODE_PLLBYPASS	0x08	/* 1: PLL output is bypassed,
+						 * default = 0 */
+#define	MCS7840_DEV_MODE_PORBYPASS	0x10	/* 1: Power-On Reset is
+						 * bypassed, default = 0 */
+#define	MCS7840_DEV_MODE_SELECT24S	0x20	/* 0: 4 Serial Ports / IrDA
+						 * active, 1: 2 Serial Ports /
+						 * IrDA active */
+#define	MCS7840_DEV_MODE_EEPROMWR	0x40	/* EEPROM write is enabled,
+						 * default */
+#define	MCS7840_DEV_MODE_IRDA		0x80	/* IrDA mode is activated
+						 * (could be turned on),
+						 * default */
+
+/* Bits for SPx ICG */
+#define	MCS7840_DEV_SPx_ICG_DEF		0x24	/* All 8 bits is used as
+						 * number of BAUD clocks of
+						 * pause */
+
+/*
+ * Bits for RX_SAMPLINGxx registers
+ * These registers control when bit value will be sampled within
+ * the baud period.
+ * 0 is very beginning of period, 15 is very end, 7 is the middle.
+ */
+#define	MCS7840_DEV_RX_SAMPLING1_MASK	0x0f	/* Bits for port 1 in
+						 * RX_SAMPLING12 */
+#define	MCS7840_DEV_RX_SAMPLING1_SHIFT	0	/* Shift for port 1in
+						 * RX_SAMPLING12 */
+#define	MCS7840_DEV_RX_SAMPLING2_MASK	0xf0	/* Bits for port 2 in
+						 * RX_SAMPLING12 */
+#define	MCS7840_DEV_RX_SAMPLING2_SHIFT	4	/* Shift for port 2 in
+						 * RX_SAMPLING12 */
+#define	MCS7840_DEV_RX_SAMPLING3_MASK	0x0f	/* Bits for port 3 in
+						 * RX_SAMPLING23 */
+#define	MCS7840_DEV_RX_SAMPLING3_SHIFT	0	/* Shift for port 3 in
+						 * RX_SAMPLING23 */
+#define	MCS7840_DEV_RX_SAMPLING4_MASK	0xf0	/* Bits for port 4 in
+						 * RX_SAMPLING23 */
+#define	MCS7840_DEV_RX_SAMPLING4_SHIFT	4	/* Shift for port 4 in
+						 * RX_SAMPLING23 */
+#define	MCS7840_DEV_RX_SAMPLINGx_MIN	0	/* Max for any RX Sampling */
+#define	MCS7840_DEV_RX_SAMPLINGx_DEF	7	/* Default for any RX
+						 * Sampling, center of period */
+#define	MCS7840_DEV_RX_SAMPLINGx_MAX	15	/* Min for any RX Sampling */
+
+/* Bits for ZERO_PERIODx */
+#define	MCS7840_DEV_ZERO_PERIODx_DEF	20	/* Number of Bulk-in requests
+						 * befor sending zero-sized
+						 * reply */
+
+/* Bits for ZERO_ENABLE */
+#define	MCS7840_DEV_ZERO_ENABLE_PORT1	0x01	/* Enable of sending
+						 * zero-sized replies for port
+						 * 1, default */
+#define	MCS7840_DEV_ZERO_ENABLE_PORT2	0x02	/* Enable of sending
+						 * zero-sized replies for port
+						 * 2, default */
+#define	MCS7840_DEV_ZERO_ENABLE_PORT3	0x04	/* Enable of sending
+						 * zero-sized replies for port
+						 * 3, default */
+#define	MCS7840_DEV_ZERO_ENABLE_PORT4	0x08	/* Enable of sending
+						 * zero-sized replies for port
+						 * 4, default */
+
+/* Bits for THR_VAL_HIGHx */
+#define	MCS7840_DEV_THR_VAL_HIGH_MASK	0x01	/* Only one bit is used */
+#define	MCS7840_DEV_THR_VAL_HIGH_MUL	256	/* This one bit is means "256" */
+#define	MCS7840_DEV_THR_VAL_HIGH_SHIFT	8	/* This one bit is means "256" */
+#define	MCS7840_DEV_THR_VAL_HIGH_ENABLE	0x80	/* Enable threshold */
+
+/* These are documented in "public" datasheet */
+#define	MCS7840_DEV_REG_DCR0_1	0x04	/* Device contol register 0 for Port
+					 * 1, R/W */
+#define	MCS7840_DEV_REG_DCR1_1	0x05	/* Device contol register 1 for Port
+					 * 1, R/W */
+#define	MCS7840_DEV_REG_DCR2_1	0x06	/* Device contol register 2 for Port
+					 * 1, R/W */
+#define	MCS7840_DEV_REG_DCR0_2	0x16	/* Device contol register 0 for Port
+					 * 2, R/W */
+#define	MCS7840_DEV_REG_DCR1_2	0x17	/* Device contol register 1 for Port
+					 * 2, R/W */
+#define	MCS7840_DEV_REG_DCR2_2	0x18	/* Device contol register 2 for Port
+					 * 2, R/W */
+#define	MCS7840_DEV_REG_DCR0_3	0x19	/* Device contol register 0 for Port
+					 * 3, R/W */
+#define	MCS7840_DEV_REG_DCR1_3	0x1a	/* Device contol register 1 for Port
+					 * 3, R/W */
+#define	MCS7840_DEV_REG_DCR2_3	0x1b	/* Device contol register 2 for Port
+					 * 3, R/W */
+#define	MCS7840_DEV_REG_DCR0_4	0x1c	/* Device contol register 0 for Port
+					 * 4, R/W */
+#define	MCS7840_DEV_REG_DCR1_4	0x1d	/* Device contol register 1 for Port
+					 * 4, R/W */
+#define	MCS7840_DEV_REG_DCR2_4	0x1e	/* Device contol register 2 for Port
+					 * 4, R/W */
+
+/* Bits of DCR0 registers, documented in datasheet */
+#define	MCS7840_DEV_DCR0_PWRSAVE		0x01	/* Shutdown transiver
+							 * when USB Suspend is
+							 * engaged, default = 1 */
+#define	MCS7840_DEV_DCR0_RESERVED1		0x02	/* Unused */
+#define	MCS7840_DEV_DCR0_GPIO_MODE_MASK		0x0c	/* GPIO Mode bits, WORKS
+							 * ONLY FOR PORT 1 */
+#define	MCS7840_DEV_DCR0_GPIO_MODE_IN		0x00	/* GPIO Mode - Input
+							 * (0b00), WORKS ONLY
+							 * FOR PORT 1 */
+#define	MCS7840_DEV_DCR0_GPIO_MODE_OUT		0x08	/* GPIO Mode - Input
+							 * (0b10), WORKS ONLY
+							 * FOR PORT 1 */
+#define	MCS7840_DEV_DCR0_RTS_ACTIVE_HIGH	0x10	/* RTS Active is HIGH,
+							 * default = 0 (low) */
+#define	MCS7840_DEV_DCR0_RTS_AUTO		0x20	/* RTS is controlled by
+							 * state of TX buffer,
+							 * default = 0
+							 * (controlled by MCR) */
+#define	MCS7840_DEV_DCR0_IRDA			0x40	/* IrDA mode */
+#define	MCS7840_DEV_DCR0_RESERVED2		0x80	/* Unused */
+
+/* Bits of DCR1 registers, documented in datasheet */
+#define	MCS7840_DEV_DCR1_GPIO_CURRENT_MASK	0x03	/* Mask to extract GPIO
+							 * current value, WORKS
+							 * ONLY FOR PORT 1 */
+#define	MCS7840_DEV_DCR1_GPIO_CURRENT_6MA	0x00	/* GPIO output current
+							 * 6mA, WORKS ONLY FOR
+							 * PORT 1 */
+#define	MCS7840_DEV_DCR1_GPIO_CURRENT_8MA	0x01	/* GPIO output current
+							 * 8mA, defauilt, WORKS
+							 * ONLY FOR PORT 1 */
+#define	MCS7840_DEV_DCR1_GPIO_CURRENT_10MA	0x02	/* GPIO output current
+							 * 10mA, WORKS ONLY FOR
+							 * PORT 1 */
+#define	MCS7840_DEV_DCR1_GPIO_CURRENT_12MA	0x03	/* GPIO output current
+							 * 12mA, WORKS ONLY FOR
+							 * PORT 1 */
+#define	MCS7840_DEV_DCR1_UART_CURRENT_MASK	0x0c	/* Mask to extract UART
+							 * signals current value */
+#define	MCS7840_DEV_DCR1_UART_CURRENT_6MA	0x00	/* UART output current
+							 * 6mA */
+#define	MCS7840_DEV_DCR1_UART_CURRENT_8MA	0x04	/* UART output current
+							 * 8mA, defauilt */
+#define	MCS7840_DEV_DCR1_UART_CURRENT_10MA	0x08	/* UART output current
+							 * 10mA */
+#define	MCS7840_DEV_DCR1_UART_CURRENT_12MA	0x0c	/* UART output current
+							 * 12mA */
+#define	MCS7840_DEV_DCR1_WAKEUP_DISABLE		0x10	/* Disable Remote USB
+							 * Wakeup */
+#define	MCS7840_DEV_DCR1_PLLPWRDOWN_DISABLE	0x20	/* Disable PLL power
+							 * down when not needed,
+							 * WORKS ONLY FOR PORT 1 */
+#define	MCS7840_DEV_DCR1_LONG_INTERRUPT		0x40	/* Enable 13 bytes of
+							 * interrupt data, with
+							 * FIFO statistics,
+							 * WORKS ONLY FOR PORT 1 */
+#define	MCS7840_DEV_DCR1_RESERVED1		0x80	/* Unused */
+
+/*
+ * Bits of DCR2 registers, documented in datasheet
+ * Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and
+ * DCR1_WAKEUP_DISABLE = 0 (wakeup enabled).
+ */
+#define	MCS7840_DEV_DCR2_WAKEUP_CTS	0x01	/* Wakeup on CTS change,
+						 * default = 0 */
+#define	MCS7840_DEV_DCR2_WAKEUP_DCD	0x02	/* Wakeup on DCD change,
+						 * default = 0 */
+#define	MCS7840_DEV_DCR2_WAKEUP_RI	0x04	/* Wakeup on RI change,
+						 * default = 1 */
+#define	MCS7840_DEV_DCR2_WAKEUP_DSR	0x08	/* Wakeup on DSR change,
+						 * default = 0 */
+#define	MCS7840_DEV_DCR2_WAKEUP_RXD	0x10	/* Wakeup on RX Data change,
+						 * default = 0 */
+#define	MCS7840_DEV_DCR2_WAKEUP_RESUME	0x20	/* Wakeup issues RESUME
+						 * signal, DISCONNECT
+						 * otherwise, default = 1 */
+#define	MCS7840_DEV_DCR2_RESERVED1	0x40	/* Unused */
+#define	MCS7840_DEV_DCR2_SHDN_POLARITY	0x80	/* 0: Pin 12 Active Low, 1:
+						 * Pin 12 Active High, default
+						 * = 0 */
+
+/* Interrupt endpoint bytes & bits */
+#define	MCS7840_IEP_FIFO_STATUS_INDEX	5
+/*
+ * Thesse can be calculated as "1 << portnumber" for Bulk-out and
+ * "1 << (portnumber+1)" for Bulk-in
+ */
+#define	MCS7840_IEP_BO_PORT1_HASDATA	0x01
+#define	MCS7840_IEP_BI_PORT1_HASDATA	0x02
+#define	MCS7840_IEP_BO_PORT2_HASDATA	0x04
+#define	MCS7840_IEP_BI_PORT2_HASDATA	0x08
+#define	MCS7840_IEP_BO_PORT3_HASDATA	0x10
+#define	MCS7840_IEP_BI_PORT3_HASDATA	0x20
+#define	MCS7840_IEP_BO_PORT4_HASDATA	0x40
+#define	MCS7840_IEP_BI_PORT4_HASDATA	0x80
+
+/* Documented UART registers (fully compatible with 16550 UART) */
+#define	MCS7840_UART_REG_THR		0x00	/* Transmitter Holding
+						 * Register W/Only */
+#define	MCS7840_UART_REG_RHR		0x00	/* Receiver Holding Register
+						 * R/Only */
+#define	MCS7840_UART_REG_IER		0x01	/* Interrupt enable register -
+						 * R/W */
+#define	MCS7840_UART_REG_FCR		0x02	/* FIFO Control register -
+						 * W/Only */
+#define	MCS7840_UART_REG_ISR		0x02	/* Interrupt Status Registter
+						 * R/Only */
+#define	MCS7840_UART_REG_LCR		0x03	/* Line control register R/W */
+#define	MCS7840_UART_REG_MCR		0x04	/* Modem control register R/W */
+#define	MCS7840_UART_REG_LSR		0x05	/* Line status register R/Only */
+#define	MCS7840_UART_REG_MSR		0x06	/* Modem status register
+						 * R/Only */
+#define	MCS7840_UART_REG_SCRATCHPAD	0x07	/* Scratch pad register */
+
+#define	MCS7840_UART_REG_DLL		0x00	/* Low bits of BAUD divider */
+#define	MCS7840_UART_REG_DLM		0x01	/* High bits of BAUD divider */
+
+/* IER bits */
+#define	MCS7840_UART_IER_RXREADY	0x01	/* RX Ready interrumpt mask */
+#define	MCS7840_UART_IER_TXREADY	0x02	/* TX Ready interrumpt mask */
+#define	MCS7840_UART_IER_RXSTAT		0x04	/* RX Status interrumpt mask */
+#define	MCS7840_UART_IER_MODEM		0x08	/* Modem status change
+						 * interrumpt mask */
+#define	MCS7840_UART_IER_SLEEP		0x10	/* SLEEP enable */
+
+/* FCR bits */
+#define	MCS7840_UART_FCR_ENABLE		0x01	/* Enable FIFO */
+#define	MCS7840_UART_FCR_FLUSHRHR	0x02	/* Flush RHR and FIFO */
+#define	MCS7840_UART_FCR_FLUSHTHR	0x04	/* Flush THR and FIFO */
+#define	MCS7840_UART_FCR_RTLMASK	0xa0	/* Mask to select RHR
+						 * Interrupt Trigger level */
+#define	MCS7840_UART_FCR_RTL_1_1	0x00	/* L1 = 1, L2 = 1 */
+#define	MCS7840_UART_FCR_RTL_1_4	0x40	/* L1 = 1, L2 = 4 */
+#define	MCS7840_UART_FCR_RTL_1_8	0x80	/* L1 = 1, L2 = 8 */
+#define	MCS7840_UART_FCR_RTL_1_14	0xa0	/* L1 = 1, L2 = 14 */
+
+/* ISR bits */
+#define	MCS7840_UART_ISR_NOPENDING	0x01	/* No interrupt pending */
+#define	MCS7840_UART_ISR_INTMASK	0x3f	/* Mask to select interrupt
+						 * source */
+#define	MCS7840_UART_ISR_RXERR		0x06	/* Recevir error */
+#define	MCS7840_UART_ISR_RXHASDATA	0x04	/* Recevier has data */
+#define	MCS7840_UART_ISR_RXTIMEOUT	0x0c	/* Recevier timeout */
+#define	MCS7840_UART_ISR_TXEMPTY	0x02	/* Transmitter empty */
+#define	MCS7840_UART_ISR_MSCHANGE	0x00	/* Modem status change */
+
+/* LCR bits */
+#define	MCS7840_UART_LCR_DATALENMASK	0x03	/* Mask for data length */
+#define	MCS7840_UART_LCR_DATALEN5	0x00	/* 5 data bits */
+#define	MCS7840_UART_LCR_DATALEN6	0x01	/* 6 data bits */
+#define	MCS7840_UART_LCR_DATALEN7	0x02	/* 7 data bits */
+#define	MCS7840_UART_LCR_DATALEN8	0x03	/* 8 data bits */
+
+#define	MCS7840_UART_LCR_STOPBMASK	0x04	/* Mask for stop bits */
+#define	MCS7840_UART_LCR_STOPB1		0x00	/* 1 stop bit in any case */
+#define	MCS7840_UART_LCR_STOPB2		0x04	/* 1.5-2 stop bits depends on
+						 * data length */
+
+#define	MCS7840_UART_LCR_PARITYMASK	0x38	/* Mask for all parity data */
+#define	MCS7840_UART_LCR_PARITYON	0x08	/* Parity ON/OFF - ON */
+#define	MCS7840_UART_LCR_PARITYODD	0x00	/* Parity Odd */
+#define	MCS7840_UART_LCR_PARITYEVEN	0x10	/* Parity Even */
+#define	MCS7840_UART_LCR_PARITYODD	0x00	/* Parity Odd */
+#define	MCS7840_UART_LCR_PARITYFORCE	0x20	/* Force parity odd/even */
+
+#define	MCS7840_UART_LCR_BREAK		0x40	/* Send BREAK */
+#define	MCS7840_UART_LCR_DIVISORS	0x80	/* Map DLL/DLM instead of
+						 * xHR/IER */
+
+/* LSR bits */
+#define	MCS7840_UART_LSR_RHRAVAIL	0x01	/* Data available for read */
+#define	MCS7840_UART_LSR_RHROVERRUN	0x02	/* Data FIFO/register overflow */
+#define	MCS7840_UART_LSR_PARITYERR	0x04	/* Parity error */
+#define	MCS7840_UART_LSR_FRAMEERR	0x10	/* Framing error */
+#define	MCS7840_UART_LSR_BREAKERR	0x20	/* BREAK sigmal received */
+#define	MCS7840_UART_LSR_THREMPTY	0x40	/* THR register is empty,
+						 * ready for transmit */
+#define	MCS7840_UART_LSR_HASERR		0x80	/* Has error in receiver FIFO */
+
+/* MCR bits */
+#define	MCS7840_UART_MCR_DTR		0x01	/* Force DTR to be active
+						 * (low) */
+#define	MCS7840_UART_MCR_RTS		0x02	/* Force RTS to be active
+						 * (low) */
+#define	MCS7840_UART_MCR_IE		0x04	/* Enable interrupts (from
+						 * code, not documented) */
+#define	MCS7840_UART_MCR_LOOPBACK	0x10	/* Enable local loopback test
+						 * mode */
+#define	MCS7840_UART_MCR_CTSRTS		0x20	/* Enable CTS/RTS flow control
+						 * in 550 (FIFO) mode */
+#define	MCS7840_UART_MCR_DTRDSR		0x40	/* Enable DTR/DSR flow control
+						 * in 550 (FIFO) mode */
+#define	MCS7840_UART_MCR_DCD		0x80	/* Enable DCD flow control in
+						 * 550 (FIFO) mode */
+
+/* MSR bits */
+#define	MCS7840_UART_MSR_DELTACTS	0x01	/* CTS was changed since last
+						 * read */
+#define	MCS7840_UART_MSR_DELTADSR	0x02	/* DSR was changed since last
+						 * read */
+#define	MCS7840_UART_MSR_DELTARI	0x04	/* RI was changed from low to
+						 * high since last read */
+#define	MCS7840_UART_MSR_DELTADCD	0x08	/* DCD was changed since last
+						 * read */
+#define	MCS7840_UART_MSR_NEGCTS		0x10	/* Negated CTS signal */
+#define	MCS7840_UART_MSR_NEGDSR		0x20	/* Negated DSR signal */
+#define	MCS7840_UART_MSR_NEGRI		0x40	/* Negated RI signal */
+#define	MCS7840_UART_MSR_NEGDCD		0x80	/* Negated DCD signal */
+
+/* SCRATCHPAD bits */
+#define	MCS7840_UART_SCRATCHPAD_RS232		0x00	/* RS-485 disabled */
+#define	MCS7840_UART_SCRATCHPAD_RS485_DTRRX	0x80	/* RS-485 mode, DTR High
+							 * = RX */
+#define	MCS7840_UART_SCRATCHPAD_RS485_DTRTX	0xc0	/* RS-485 mode, DTR High
+							 * = TX */
+
+#define	MCS7840_CONFIG_INDEX	0
+#define	MCS7840_IFACE_INDEX	0
+
+#endif
diff --git a/sys/dev/usb/usb_process.c b/sys/dev/usb/usb_process.c
index 0509ec274ce2..051ded993d96 100644
--- a/sys/dev/usb/usb_process.c
+++ b/sys/dev/usb/usb_process.c
@@ -360,7 +360,12 @@ usb_proc_is_gone(struct usb_process *up)
 	if (up->up_gone)
 		return (1);
 
-	mtx_assert(up->up_mtx, MA_OWNED);
+	/*
+	 * Allow calls when up_mtx is NULL, before the USB process
+	 * structure is initialised.
+	 */
+	if (up->up_mtx != NULL)
+		mtx_assert(up->up_mtx, MA_OWNED);
 	return (0);
 }
 
diff --git a/sys/dev/usb/usbdevs b/sys/dev/usb/usbdevs
index eb49eb250fc1..a970206b2e7a 100644
--- a/sys/dev/usb/usbdevs
+++ b/sys/dev/usb/usbdevs
@@ -2273,7 +2273,9 @@ product MOBILITY EASIDOCK	0x0304	EasiDock Ethernet
 /* MosChip products */
 product MOSCHIP MCS7703		0x7703	MCS7703 Serial Port Adapter
 product MOSCHIP MCS7730		0x7730  MCS7730 Ethernet
+product MOSCHIP MCS7820		0x7820	MCS7820 Serial Port Adapter
 product MOSCHIP MCS7830		0x7830	MCS7830 Ethernet
+product MOSCHIP MCS7840		0x7840	MCS7840 Serial Port Adapter
 
 /* Motorola products */
 product MOTOROLA MC141555	0x1555	MC141555 hub controller