diff options
| author | Paul Traina <pst@FreeBSD.org> | 1994-09-04 19:59:24 +0000 |
|---|---|---|
| committer | Paul Traina <pst@FreeBSD.org> | 1994-09-04 19:59:24 +0000 |
| commit | c78417231805fb62bcf9acd6977a3b7c6862a6b6 (patch) | |
| tree | 41915c593ebc31ab434cdeaf9ccb1f28710e35da /sys/i386/i386 | |
| parent | b54c304080a1751aec03bcabd8b112bf998711c5 (diff) | |
| download | src-c78417231805fb62bcf9acd6977a3b7c6862a6b6.tar.gz src-c78417231805fb62bcf9acd6977a3b7c6862a6b6.zip | |
Detect if we're running on a Cyrix 486DLC and enable automatic cache
negation whenever we access memory between 640k and 1M.
Original code from NetBSD 1.0-BETA. The exact origins are unclear but
Theo de Raadt, Charles, and Michael V. may have contributed to it.
Submitted by: pst
Notes
Notes:
svn path=/head/; revision=2495
Diffstat (limited to 'sys/i386/i386')
| -rw-r--r-- | sys/i386/i386/locore.s | 32 | ||||
| -rw-r--r-- | sys/i386/i386/machdep.c | 5 |
2 files changed, 34 insertions, 3 deletions
diff --git a/sys/i386/i386/locore.s b/sys/i386/i386/locore.s index 58b165ba2d60..b216f8f4e1aa 100644 --- a/sys/i386/i386/locore.s +++ b/sys/i386/i386/locore.s @@ -34,7 +34,7 @@ * SUCH DAMAGE. * * from: @(#)locore.s 7.3 (Berkeley) 5/13/91 - * $Id: locore.s,v 1.22 1994/09/02 01:29:20 davidg Exp $ + * $Id: locore.s,v 1.23 1994/09/04 00:33:00 davidg Exp $ */ /* @@ -213,6 +213,36 @@ NON_GPROF_ENTRY(btext) testl %eax,%eax jnz 1f movl $CPU_486,_cpu-KERNBASE + + /* check for Cyrix 486DLC -- based on check routine */ + /* documented in "Cx486SLC/e SMM Programmer's Guide" */ + xorw %dx,%dx + cmpw %dx,%dx # set flags to known state + pushfw + popw %cx # store flags in ecx + movw $0xffff,%ax + movw $0x0004,%bx + divw %bx + pushfw + popw %ax + andw $0x08d5,%ax # mask off important bits + andw $0x08d5,%cx + cmpw %ax,%cx + + jnz 2f # if flags changed, Intel chip + + movl $CPU_486DLC,_cpu-KERNBASE # set CPU value for Cyrix + movl $0x69727943,_cpu_vendor-KERNBASE # store vendor string + movw $0x0078,_cpu_vendor-KERNBASE+4 + + invd # Start with guaranteed clean cache + /* Disable caching of the ISA hole only. */ + movb $CCR0,%al # Configuration Register index (CCR0) + outb %al,$0x22 + inb $0x23,%al + orb $CCR0_NC1,%al + outb %al,$0x23 + invd jmp 2f 1: /* Use the `cpuid' instruction. */ diff --git a/sys/i386/i386/machdep.c b/sys/i386/i386/machdep.c index 18d1553d2c93..480f00edbea2 100644 --- a/sys/i386/i386/machdep.c +++ b/sys/i386/i386/machdep.c @@ -35,7 +35,7 @@ * SUCH DAMAGE. * * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 - * $Id: machdep.c,v 1.59 1994/08/31 15:55:29 davidg Exp $ + * $Id: machdep.c,v 1.60 1994/09/02 04:12:04 davidg Exp $ */ #include "npx.h" @@ -97,7 +97,7 @@ static void initcpu(void); static int test_page(int *, int); char machine[] = "i386"; -char cpu_model[sizeof("Pentium") + 1]; +char cpu_model[sizeof("Cy486DLC") + 1]; #ifndef PANIC_REBOOT_WAIT_TIME #define PANIC_REBOOT_WAIT_TIME 15 /* default to 15 seconds */ @@ -354,6 +354,7 @@ struct cpu_nameclass i386_cpus[] = { { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ { "i486DX", CPUCLASS_486 }, /* CPU_486 */ { "Pentium", CPUCLASS_586 }, /* CPU_586 */ + { "Cy486DLC", CPUCLASS_486 }, /* CPU_486DLC */ }; static void |