diff options
| author | Adrian Chadd <adrian@FreeBSD.org> | 2013-10-09 03:19:05 +0000 |
|---|---|---|
| committer | Adrian Chadd <adrian@FreeBSD.org> | 2013-10-09 03:19:05 +0000 |
| commit | 490cbcd9cba948ed2aa3eee28e307f9f5d26748f (patch) | |
| tree | 81f8ce2e2b25b52b03f57d41c8f73f558ce25945 /sys/mips/atheros | |
| parent | 50c55142271e40c6e58fecf7361ec776dd63b254 (diff) | |
| download | src-490cbcd9cba948ed2aa3eee28e307f9f5d26748f.tar.gz src-490cbcd9cba948ed2aa3eee28e307f9f5d26748f.zip | |
Add some missing AR934x register definitions.
These are needed for ethernet bootstrap.
Approved by: re@ (gjb)
Notes
Notes:
svn path=/head/; revision=256175
Diffstat (limited to 'sys/mips/atheros')
| -rw-r--r-- | sys/mips/atheros/ar71xxreg.h | 12 | ||||
| -rw-r--r-- | sys/mips/atheros/ar934xreg.h | 33 |
2 files changed, 45 insertions, 0 deletions
diff --git a/sys/mips/atheros/ar71xxreg.h b/sys/mips/atheros/ar71xxreg.h index 7d6d6b2f5a4c..5e3505be23ef 100644 --- a/sys/mips/atheros/ar71xxreg.h +++ b/sys/mips/atheros/ar71xxreg.h @@ -336,6 +336,7 @@ typedef enum { #define MAC_MII_CFG_SCAN_AUTO_INC (1 << 5) #define MAC_MII_CFG_PREAMBLE_SUP (1 << 4) #define MAC_MII_CFG_CLOCK_SELECT_MASK 0x7 +#define MAC_MII_CFG_CLOCK_SELECT_MASK_AR933X 0xf #define MAC_MII_CFG_CLOCK_DIV_4 0 #define MAC_MII_CFG_CLOCK_DIV_6 2 #define MAC_MII_CFG_CLOCK_DIV_8 3 @@ -343,6 +344,17 @@ typedef enum { #define MAC_MII_CFG_CLOCK_DIV_14 5 #define MAC_MII_CFG_CLOCK_DIV_20 6 #define MAC_MII_CFG_CLOCK_DIV_28 7 + +/* .. and the AR933x/AR934x extensions */ +#define MAC_MII_CFG_CLOCK_DIV_34 8 +#define MAC_MII_CFG_CLOCK_DIV_42 9 +#define MAC_MII_CFG_CLOCK_DIV_50 10 +#define MAC_MII_CFG_CLOCK_DIV_58 11 +#define MAC_MII_CFG_CLOCK_DIV_66 12 +#define MAC_MII_CFG_CLOCK_DIV_74 13 +#define MAC_MII_CFG_CLOCK_DIV_82 14 +#define MAC_MII_CFG_CLOCK_DIV_98 15 + #define AR71XX_MAC_MII_CMD 0x24 #define MAC_MII_CMD_SCAN_CYCLE (1 << 1) #define MAC_MII_CMD_READ 1 diff --git a/sys/mips/atheros/ar934xreg.h b/sys/mips/atheros/ar934xreg.h index 3b0381f8f7f1..2aa3f46ca843 100644 --- a/sys/mips/atheros/ar934xreg.h +++ b/sys/mips/atheros/ar934xreg.h @@ -29,6 +29,8 @@ #ifndef __AR934X_REG_H__ #define __AR934X_REG_H__ +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) #define AR934X_WMAC_SIZE 0x20000 #define AR934X_EHCI_BASE 0x1b000000 @@ -36,6 +38,23 @@ #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) #define AR934X_SRIF_SIZE 0x1000 +/* AR934x GMAC configuration */ +#define AR934X_GMAC_REG_ETH_CFG (AR934X_GMAC_BASE + 0x00) + +#define AR934X_ETH_CFG_RGMII_GMAC0 (1 << 0) +#define AR934X_ETH_CFG_MII_GMAC0 (1 << 1) +#define AR934X_ETH_CFG_GMII_GMAC0 (1 << 2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER (1 << 3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE (1 << 4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN (1 << 5) +#define AR934X_ETH_CFG_SW_ONLY_MODE (1 << 6) +#define AR934X_ETH_CFG_SW_PHY_SWAP (1 << 7) +#define AR934X_ETH_CFG_SW_APB_ACCESS (1 << 9) +#define AR934X_ETH_CFG_RMII_GMAC0 (1 << 10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED (1 << 11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER (1 << 12) +#define AR934X_ETH_CFG_SW_ACC_MSB_FIRST (1 << 13) + #define AR934X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c) #define AR934X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0) #define AR934X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4) @@ -45,6 +64,9 @@ #define AR934X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00) #define AR934X_PLL_DDR_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x04) #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08) +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x24) +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL (1 << 6) +#define AR934X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x2c) #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f @@ -81,7 +103,13 @@ #define AR934X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xb0) #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS (AR71XX_RST_BLOCK_BASE + 0xac) +#define AR934X_RESET_GE1_MDIO (1 << 23) +#define AR934X_RESET_GE0_MDIO (1 << 22) +#define AR934X_RESET_GE1_MAC (1 << 13) +#define AR934X_RESET_ETH_SWITCH_ANALOG (1 << 12) #define AR934X_RESET_USB_PHY_ANALOG (1 << 11) +#define AR934X_RESET_GE0_MAC (1 << 9) +#define AR934X_RESET_ETH_SWITCH (1 << 8) #define AR934X_RESET_USB_HOST (1 << 5) #define AR934X_RESET_USB_PHY (1 << 4) #define AR934X_RESET_USBSUS_OVERRIDE (1 << 3) @@ -153,4 +181,9 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 +/* XXX verify! */ +#define AR934X_PLL_VAL_1000 0x16000000 +#define AR934X_PLL_VAL_100 0x00000101 +#define AR934X_PLL_VAL_10 0x00001616 + #endif /* __AR934X_REG_H__ */ |