e1000: Serialize 82579 CSR writes with the Management EngineHEADmain

The 82579 PCIm2PCI arbiter can acknowledge a host MAC CSR write while
the Management Engine is accessing another CSR.  The host write can be
lost; subsequent target accesses may no longer be claimed by the MAC and
can hang the system.

For 82579 controllers with valid management firmware, wait for the ME
CSR access indication before every MAC CSR write.  Keep the wait bounded
and use DELAY because writes occur in interrupt and datapath contexts.
Verify every transmit and receive tail write.  If a tail does not hold
the requested value, disable its datapath direction and request a full
iflib reset.

Keep the ordinary register-write path as a direct MMIO write behind a
predicted per-device gate.  Contain the wait and tail recovery in the
82579 slow path rather than adding tail-specific accessors and state to
the rest of the e1000 family.

Documentation on the PCH NICs is scare so Intel's Linux e1000e fixes
publicly document the hardware failure and required serialization as
commits bdc125f73f3c and d601afcae2fe.  This implementation is a bit
cleaner.

Tested on a Thinkpad T430 (82579LM) with a test kernel to simulate ME
contention without incident as well as lost tail writes causing a
succesful recovery.

MFC after:	2 weeks
Sponsored by:	BBOX.io

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