aboutsummaryrefslogtreecommitdiff
path: root/sys/pci/if_rl.c
diff options
context:
space:
mode:
authorBill Paul <wpaul@FreeBSD.org>2002-04-07 20:55:50 +0000
committerBill Paul <wpaul@FreeBSD.org>2002-04-07 20:55:50 +0000
commita72c060fb00fdbefd3df75aa593c99d96c200544 (patch)
treed8d07d2e39818081fc33934d98636b41b3ef3379 /sys/pci/if_rl.c
parenta8b1e59eb28a533a62c0ff287f0d8d8cc18ebbfc (diff)
downloadsrc-a72c060fb00fdbefd3df75aa593c99d96c200544.tar.gz
src-a72c060fb00fdbefd3df75aa593c99d96c200544.zip
Teach the rlphy driver how to do parallel link detection. If the link partner
doesn't support NWAY, the RealTek PHY (both the integrated ones on 8139 chips and the RTL8201L 10/100 PHY) will not report the link speed via the ANLPAR or BMSR registers. For the 8201L, we need to look in magic vendor-specific PHY register 0x19. For the 8139 MAC+PHY combo, we have to be able to test the RL_MEDIASTAT register. The changes to rlphy.c are based largely on the patch from PR 30836, however I tried to eliminate some magic numbers by creating an entry for the 8201 PHY in miidevs. Also updated if_rl.c to allow the rlphy driver to read the RL_MEDIASTAT register via the rl_miibus_readreg() routine.
Notes
Notes: svn path=/head/; revision=94149
Diffstat (limited to 'sys/pci/if_rl.c')
-rw-r--r--sys/pci/if_rl.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/sys/pci/if_rl.c b/sys/pci/if_rl.c
index b91257192a35..a08e56103a22 100644
--- a/sys/pci/if_rl.c
+++ b/sys/pci/if_rl.c
@@ -609,6 +609,17 @@ static int rl_miibus_readreg(dev, phy, reg)
RL_UNLOCK(sc);
return(0);
break;
+ /*
+ * Allow the rlphy driver to read the media status
+ * register. If we have a link partner which does not
+ * support NWAY, this is the register which will tell
+ * us the results of parallel detection.
+ */
+ case RL_MEDIASTAT:
+ rval = CSR_READ_1(sc, RL_MEDIASTAT);
+ RL_UNLOCK(sc);
+ return(rval);
+ break;
default:
printf("rl%d: bad phy register\n", sc->rl_unit);
RL_UNLOCK(sc);