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author | Marcel Moolenaar <marcel@FreeBSD.org> | 2009-10-21 18:38:02 +0000 |
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committer | Marcel Moolenaar <marcel@FreeBSD.org> | 2009-10-21 18:38:02 +0000 |
commit | 1a4fcaebe30b3067a19baf8871a27942f4bb32cf (patch) | |
tree | 9665f89431ede73407ae0ad11ebcc8198166085e /sys/powerpc/powerpc/mmu_if.m | |
parent | a7b5ad271ca6f0dca42accb1e6b16a630f74451d (diff) | |
download | src-1a4fcaebe30b3067a19baf8871a27942f4bb32cf.tar.gz src-1a4fcaebe30b3067a19baf8871a27942f4bb32cf.zip |
o Introduce vm_sync_icache() for making the I-cache coherent with
the memory or D-cache, depending on the semantics of the platform.
vm_sync_icache() is basically a wrapper around pmap_sync_icache(),
that translates the vm_map_t argumument to pmap_t.
o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc
it replaces the pmap_page_executable() function, added to solve
the I-cache problem in uiomove_fromphys().
o In proc_rwmem() call vm_sync_icache() when writing to a page that
has execute permissions. This assures that when breakpoints are
written, the I-cache will be coherent and the process will actually
hit the breakpoint.
o This also fixes the Book-E PMAP implementation that was missing
necessary locking while trying to deal with the I-cache coherency
in pmap_enter() (read: mmu_booke_enter_locked).
The key property of this change is that the I-cache is made coherent
*after* writes have been done. Doing it in the PMAP layer when adding
or changing a mapping means that the I-cache is made coherent *before*
any writes happen. The difference is key when the I-cache prefetches.
Notes
Notes:
svn path=/head/; revision=198341
Diffstat (limited to 'sys/powerpc/powerpc/mmu_if.m')
-rw-r--r-- | sys/powerpc/powerpc/mmu_if.m | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/sys/powerpc/powerpc/mmu_if.m b/sys/powerpc/powerpc/mmu_if.m index 4a5a37c456c5..5b8ba14d6898 100644 --- a/sys/powerpc/powerpc/mmu_if.m +++ b/sys/powerpc/powerpc/mmu_if.m @@ -789,15 +789,21 @@ METHOD boolean_t dev_direct_mapped { /** - * @brief Evaluate if a physical page has an executable mapping + * @brief Enforce instruction cache coherency. Typically called after a + * region of memory has been modified and before execution of or within + * that region is attempted. Setting breakpoints in a process through + * ptrace(2) is one example of when the instruction cache needs to be + * made coherent. * - * @param _pg physical page - * - * @retval bool TRUE if a physical mapping exists for the given page. + * @param _pm the physical map of the virtual address + * @param _va the virtual address of the modified region + * @param _sz the size of the modified region */ -METHOD boolean_t page_executable { +METHOD void sync_icache { mmu_t _mmu; - vm_page_t _pg; + pmap_t _pm; + vm_offset_t _va; + vm_size_t _sz; }; |