Various fixes for TLB management on RISC-V.

- Remove the arm64-specific cpu_*cache* and cpu_tlb_flush* functions.
  Instead, add RISC-V specific inline functions in cpufunc.h for the
  fence.i and sfence.vma instructions.
- Catch up to changes in the arm64 pmap and remove all the cpu_dcache_*
  calls, pmap_is_current, pmap_l3_valid_cacheable, and PTE_NEXT bits from
  pmap.
- Remove references to the unimplemented riscv_setttb().
- Remove unused cpu_nullop.
- Add a link to the SBI doc to sbi.h.
- Add support for a 4th argument in SBI calls.  It's not documented but
  it seems implied for the asid argument to SBI_REMOVE_SFENCE_VMA_ASID.
- Pass the arguments from sbi_remote_sfence*() to the SEE.  BBL ignores
  them so this is just cosmetic.
- Flush icaches on other CPUs when they resume from kdb in case the
  debugger wrote any breakpoints while the CPUs were paused in the IPI_STOP
  handler.
- Add SMP vs UP versions of pmap_invalidate_* similar to amd64.  The
  UP versions just use simple fences.  The SMP versions use the
  sbi_remove_sfence*() functions to perform TLB shootdowns.  Since we
  don't have a valid pm_active field in the riscv pmap, just IPI all
  CPUs for all invalidations for now.
- Remove an extraneous TLB flush from the end of pmap_bootstrap().
- Don't do a TLB flush when writing new mappings in pmap_enter(), only if
  modifying an existing mapping.  Note that for COW faults a TLB flush is
  only performed after explicitly clearing the old mapping as is done in
  other pmaps.
- Sync the i-cache on all harts before updating the PTE for executable
  mappings in pmap_enter and pmap_enter_quick.  Previously the i-cache was
  only sync'd after updating the PTE in pmap_enter.
- Use sbi_remote_fence() instead of smp_rendezvous in pmap_sync_icache().

Reviewed by:	markj
Approved by:	re (gjb, kib)
Sponsored by:	DARPA
Differential Revision:	https://reviews.freebsd.org/D17414

1 files changed, 20 insertions, 12 deletions

diff --git a/sys/riscv/include/sbi.h b/sys/riscv/include/sbi.h
index b2505aa7f6c6..0ba23c35f97a 100644
--- a/sys/riscv/include/sbi.h
+++ b/sys/riscv/include/sbi.h
@@ -47,18 +47,25 @@
 #define	SBI_REMOTE_SFENCE_VMA_ASID	7
 #define	SBI_SHUTDOWN			8
 
+/*
+ * Documentation available at
+ * https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md
+ */
+
 static __inline uint64_t
-sbi_call(uint64_t arg7, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+sbi_call(uint64_t arg7, uint64_t arg0, uint64_t arg1, uint64_t arg2,
+    uint64_t arg3)
 {
-
 	register uintptr_t a0 __asm ("a0") = (uintptr_t)(arg0);
 	register uintptr_t a1 __asm ("a1") = (uintptr_t)(arg1);
 	register uintptr_t a2 __asm ("a2") = (uintptr_t)(arg2);
+	register uintptr_t a3 __asm ("a3") = (uintptr_t)(arg3);
 	register uintptr_t a7 __asm ("a7") = (uintptr_t)(arg7);
+
 	__asm __volatile(			\
 		"ecall"				\
 		:"+r"(a0)			\
-		:"r"(a1), "r"(a2), "r"(a7)	\
+		:"r"(a1), "r"(a2), "r" (a3), "r"(a7)	\
 		:"memory");
 
 	return (a0);
@@ -68,49 +75,49 @@ static __inline void
 sbi_console_putchar(int ch)
 {
 
-	sbi_call(SBI_CONSOLE_PUTCHAR, ch, 0, 0);
+	sbi_call(SBI_CONSOLE_PUTCHAR, ch, 0, 0, 0);
 }
 
 static __inline int
 sbi_console_getchar(void)
 {
 
-	return (sbi_call(SBI_CONSOLE_GETCHAR, 0, 0, 0));
+	return (sbi_call(SBI_CONSOLE_GETCHAR, 0, 0, 0, 0));
 }
 
 static __inline void
 sbi_set_timer(uint64_t val)
 {
 
-	sbi_call(SBI_SET_TIMER, val, 0, 0);
+	sbi_call(SBI_SET_TIMER, val, 0, 0, 0);
 }
 
 static __inline void
 sbi_shutdown(void)
 {
 
-	sbi_call(SBI_SHUTDOWN, 0, 0, 0);
+	sbi_call(SBI_SHUTDOWN, 0, 0, 0, 0);
 }
 
 static __inline void
 sbi_clear_ipi(void)
 {
 
-	sbi_call(SBI_CLEAR_IPI, 0, 0, 0);
+	sbi_call(SBI_CLEAR_IPI, 0, 0, 0, 0);
 }
 
 static __inline void
 sbi_send_ipi(const unsigned long *hart_mask)
 {
 
-	sbi_call(SBI_SEND_IPI, (uint64_t)hart_mask, 0, 0);
+	sbi_call(SBI_SEND_IPI, (uint64_t)hart_mask, 0, 0, 0);
 }
 
 static __inline void
 sbi_remote_fence_i(const unsigned long *hart_mask)
 {
 
-	sbi_call(SBI_REMOTE_FENCE_I, (uint64_t)hart_mask, 0, 0);
+	sbi_call(SBI_REMOTE_FENCE_I, (uint64_t)hart_mask, 0, 0, 0);
 }
 
 static __inline void
@@ -118,7 +125,7 @@ sbi_remote_sfence_vma(const unsigned long *hart_mask,
     unsigned long start, unsigned long size)
 {
 
-	sbi_call(SBI_REMOTE_SFENCE_VMA, (uint64_t)hart_mask, 0, 0);
+	sbi_call(SBI_REMOTE_SFENCE_VMA, (uint64_t)hart_mask, start, size, 0);
 }
 
 static __inline void
@@ -127,7 +134,8 @@ sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
     unsigned long asid)
 {
 
-	sbi_call(SBI_REMOTE_SFENCE_VMA_ASID, (uint64_t)hart_mask, 0, 0);
+	sbi_call(SBI_REMOTE_SFENCE_VMA_ASID, (uint64_t)hart_mask, start, size,
+	    asid);
 }
 
 #endif /* !_MACHINE_SBI_H_ */