- Move the routine for flushing all user mappings from the tlb from pmap to

  the cpu dependent files.  It will need to be done differently for USIII.
- Simplify the logic for detecting context rollovers.  Instead of dealing
  with it when the next context switch would cause the context numbers to
  rollover, deal with it when they actually do rollover.
- Move some things around in cpu_switch so that we only do 1 membar #Sync
  when switching address space, instead of 2.
- Detect kernel threads by comparing the new vm space to vmspace0, instead
  if checking if the tlb context is 0.
- Removed some debug code.

1 files changed, 3 insertions, 0 deletions

diff --git a/sys/sparc64/sparc64/cache.c b/sys/sparc64/sparc64/cache.c
index a3e1a1c953c1..dad13f129e32 100644
--- a/sys/sparc64/sparc64/cache.c
+++ b/sys/sparc64/sparc64/cache.c
@@ -81,6 +81,7 @@
 #include <dev/ofw/openfirm.h>
 
 #include <machine/cache.h>
+#include <machine/tlb.h>
 #include <machine/ver.h>
 
 struct cacheinfo cache;
@@ -126,8 +127,10 @@ cache_init(phandle_t node)
 	if (cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
 		dcache_page_inval = cheetah_dcache_page_inval;
 		icache_page_inval = cheetah_icache_page_inval;
+		tlb_flush_user = cheetah_tlb_flush_user;
 	} else {
 		dcache_page_inval = spitfire_dcache_page_inval;
 		icache_page_inval = spitfire_icache_page_inval;
+		tlb_flush_user = spitfire_tlb_flush_user;
 	}
 }